repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
96flashbacks/96flashbacks
| 2,524
|
lib/asm/llmuldiv_gcc.s
|
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64
.include "macros.inc"
.section .text, "ax"
/* -------------------------------------------------------------------------------------- */
/* need to asm these functions because lib32gcc-7-dev-mips-cross does not exist so we */
/* cannot naturally link a libgcc variant for this target given this architecture and */
/* compiler. Until we have a good workaround with a gcc target that doesn't involve */
/* assuming a 32-bit to 64-bit change, we have to encode these functions as raw assembly */
/* for it to compile. */
/* -------------------------------------------------------------------------------------- */
/* TODO: Is there a non-insane way to fix this hack that doesn't involve the user compiling */
/* a library themselves? */
glabel __umoddi3
sw $a0, ($sp)
sw $a1, 4($sp)
sw $a2, 8($sp)
sw $a3, 0xc($sp)
ld $t7, 8($sp)
ld $t6, ($sp)
ddivu $zero, $t6, $t7
bnez $t7, .L80324144
nop
break 7
.L80324144:
mfhi $v0
dsll32 $v1, $v0, 0
dsra32 $v1, $v1, 0
jr $ra
dsra32 $v0, $v0, 0
glabel __udivdi3
sw $a0, ($sp)
sw $a1, 4($sp)
sw $a2, 8($sp)
sw $a3, 0xc($sp)
ld $t7, 8($sp)
ld $t6, ($sp)
ddivu $zero, $t6, $t7
bnez $t7, .L80324180
nop
break 7
.L80324180:
mflo $v0
dsll32 $v1, $v0, 0
dsra32 $v1, $v1, 0
jr $ra
dsra32 $v0, $v0, 0
glabel __moddi3
sw $a0, ($sp)
sw $a1, 4($sp)
sw $a2, 8($sp)
sw $a3, 0xc($sp)
ld $t7, 8($sp)
ld $t6, ($sp)
ddivu $zero, $t6, $t7
bnez $t7, .L803241E8
nop
break 7
.L803241E8:
mfhi $v0
dsll32 $v1, $v0, 0
dsra32 $v1, $v1, 0
jr $ra
dsra32 $v0, $v0, 0
glabel __divdi3
sw $a0, ($sp)
sw $a1, 4($sp)
sw $a2, 8($sp)
sw $a3, 0xc($sp)
ld $t7, 8($sp)
ld $t6, ($sp)
ddiv $zero, $t6, $t7
nop
bnez $t7, .L80324228
nop
break 7
.L80324228:
daddiu $at, $zero, -1
bne $t7, $at, .L80324244
daddiu $at, $zero, 1
dsll32 $at, $at, 0x1f
bne $t6, $at, .L80324244
nop
break 6
.L80324244:
mflo $v0
dsll32 $v1, $v0, 0
dsra32 $v1, $v1, 0
jr $ra
dsra32 $v0, $v0, 0
|
96flashbacks/96flashbacks
| 1,153
|
lib/asm/osMapTLB.s
|
.set noreorder # don't insert nops after branches
.set gp=64
.include "macros.inc"
.section .text, "ax"
# This file is handwritten
#void osMapTLB(s32 index, OSPageMask pm, void *vaddr, u32 evenpaddr, u32 oddpaddr, s32 asid);
glabel osMapTLB
mfc0 $t0, $10
mtc0 $a0, $0
mtc0 $a1, $5
lw $t1, 0x14($sp) #asid
beq $t1, -1, .L803214D8
li $t4, 1
li $t2, 30
b .L803214DC
or $a2, $a2, $t1 #vaddr
.L803214D8:
li $t2, 31
.L803214DC:
mtc0 $a2, $10 #vaddr
beq $a3, -1, .L80321500 #even paddr
nop
srl $t3, $a3, 6 #evenpaddr
or $t3, $t3, $t2
mtc0 $t3, $2
b .L80321504
nop
.L80321500:
mtc0 $t4, $2
.L80321504:
lw $t3, 0x10($sp) #oddpaddr
beq $t3, -1, .L80321528
nop
srl $t3, $t3, 6
or $t3, $t3, $t2
mtc0 $t3, $3
b .L80321540
nop
.L80321528:
mtc0 $t4, $3
bne $a3, -1, .L80321540 #evenpaddr
nop
lui $t3, 0x8000
mtc0 $t3, $10
.L80321540:
nop
tlbwi
nop
nop
nop
nop
mtc0 $t0, $10
jr $ra
nop #file gets padded but
nop
nop
nop
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_led_and_delay/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_led_and_delay/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_led_and_delay/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_led_and_delay/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_led_and_delay/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_led_and_delay/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_led_and_delay/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_led_and_delay/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
96flashbacks/springroll
| 2,242
|
lib/asm/bzero.s
|
.set noreorder // don't insert nops after branches
#include "macros.inc"
// this file is probably handwritten
//TODO There seem to be patterns in these iQue diffs. Can we figure out what's causing them? Could this have been written in C? See also bcopy.s.
.section .text, "ax"
glabel bzero
#ifdef VERSION_CN
negu $v1, $a0
blt $a1, 0xc, .L80303790
nop
andi $v1, $v1, 3
beqz $v1, .L80303734
subu $a1, $a1, $v1
swl $zero, ($a0)
addu $a0, $a0, $v1
.L80303734:
and $a3, $a1, -32
beqz $a3, .L80303770
subu $a1, $a1, $a3
addu $a3, $a3, $a0
.L80303748:
sw $zero, ($a0)
sw $zero, 4($a0)
sw $zero, 8($a0)
sw $zero, 0xc($a0)
addiu $a0, $a0, 0x20
sw $zero, -0x10($a0)
sw $zero, -0xc($a0)
sw $zero, -8($a0)
bne $a0, $a3, .L80303748
sw $zero, -4($a0)
.L80303770:
and $a3, $a1, -4
beqz $a3, .L80303790
subu $a1, $a1, $a3
addu $a3, $a3, $a0
.L80303784:
addiu $a0, $a0, 4
bne $a0, $a3, .L80303784
sw $zero, -4($a0)
.L80303790:
blez $a1, .L803037A8
nop
addu $a1, $a1, $a0
.L8030379C:
addiu $a0, $a0, 1
bne $a0, $a1, .L8030379C
sb $zero, -1($a0)
.L803037A8:
jr $ra
nop
#else
blt $a1, 0xc, .L803236BC
negu $v1, $a0
andi $v1, $v1, 3
beqz $v1, .L80323660
subu $a1, $a1, $v1
swl $zero, ($a0)
addu $a0, $a0, $v1
.L80323660:
and $a3, $a1, -32
beqz $a3, .L8032369C
subu $a1, $a1, $a3
addu $a3, $a3, $a0
.L80323674:
addiu $a0, $a0, 0x20
sw $zero, -0x20($a0)
sw $zero, -0x1c($a0)
sw $zero, -0x18($a0)
sw $zero, -0x14($a0)
sw $zero, -0x10($a0)
sw $zero, -0xc($a0)
sw $zero, -8($a0)
bne $a0, $a3, .L80323674
sw $zero, -4($a0)
.L8032369C:
and $a3, $a1, -4
beqz $a3, .L803236BC
subu $a1, $a1, $a3
addu $a3, $a3, $a0
.L803236B0:
addiu $a0, $a0, 4
bne $a0, $a3, .L803236B0
sw $zero, -4($a0)
.L803236BC:
blez $a1, .L803236D4
nop
addu $a1, $a1, $a0
.L803236C8:
addiu $a0, $a0, 1
bne $a0, $a1, .L803236C8
sb $zero, -1($a0)
.L803236D4:
jr $ra
#endif
|
96flashbacks/springroll
| 25,700
|
lib/asm/__osExceptionPreamble.s
|
.set noat // allow manual use of $at
.set noreorder // don't insert nops after branches
#include "macros.inc"
#include <PR/R4300.h>
#include <PR/rcp.h>
#include <PR/ique.h>
#if defined(VERSION_EU) || defined(VERSION_SH)
#define VERSION_EU_SH
#endif
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
#define VERSION_EU_SH_CN
#endif
.section .text, "ax"
#ifdef AVOID_UB
.set __osThreadTail, __osThreadTail_fix
#endif
glabel __osExceptionPreamble
la $k0, __osException
jr $k0
nop
glabel __osException
la $k0, __osThreadSave
sd $at, 0x20($k0)
mfc0 $k1, $12
sw $k1, 0x118($k0)
li $at, -4
and $k1, $k1, $at
mtc0 $k1, $12
sd $t0, 0x58($k0)
sd $t1, 0x60($k0)
sd $t2, 0x68($k0)
sw $zero, 0x18($k0)
mfc0 $t0, $13
#ifndef VERSION_EU_SH_CN
andi $t1, $t0, 0x7c
li $t2, 0
bne $t1, $t2, .L80326750
nop
and $t1, $k1, $t0
andi $t2, $t1, 0x4000
beqz $t2, .L80326734
nop
li $t1, 1
lui $at, %hi(D_80334934)
b .L80326794
sw $t1, %lo(D_80334934)($at)
.L80326734:
andi $t2, $t1, 0x2000
beqz $t2, .L80326750
nop
li $t1, 1
lui $at, %hi(D_80334938)
b .L80326794
sw $t1, %lo(D_80334938)($at)
.L80326750:
lui $at, %hi(D_80334934)
sw $zero, %lo(D_80334934)($at)
lui $at, %hi(D_80334938)
#endif
move $t0, $k0
#ifndef VERSION_EU_SH_CN
sw $zero, %lo(D_80334938)($at)
#endif
lui $k0, %hi(__osThreadTail + 0x10)
lw $k0, %lo(__osThreadTail + 0x10)($k0)
ld $t1, 0x20($t0)
sd $t1, 0x20($k0)
ld $t1, 0x118($t0)
sd $t1, 0x118($k0)
ld $t1, 0x58($t0)
sd $t1, 0x58($k0)
ld $t1, 0x60($t0)
sd $t1, 0x60($k0)
ld $t1, 0x68($t0)
sd $t1, 0x68($k0)
#ifdef VERSION_EU_SH
lw $k1, 0x118($k0)
#else
.L80326794:
#endif
#ifndef VERSION_CN
mflo $t0
sd $t0, 0x108($k0)
mfhi $t0
#endif
#ifdef VERSION_EU_SH
andi $t1, $k1, 0xff00
#endif
sd $v0, 0x28($k0)
sd $v1, 0x30($k0)
sd $a0, 0x38($k0)
sd $a1, 0x40($k0)
sd $a2, 0x48($k0)
sd $a3, 0x50($k0)
sd $t3, 0x70($k0)
sd $t4, 0x78($k0)
sd $t5, 0x80($k0)
sd $t6, 0x88($k0)
sd $t7, 0x90($k0)
sd $s0, 0x98($k0)
sd $s1, 0xa0($k0)
sd $s2, 0xa8($k0)
sd $s3, 0xb0($k0)
sd $s4, 0xb8($k0)
sd $s5, 0xc0($k0)
sd $s6, 0xc8($k0)
sd $s7, 0xd0($k0)
sd $t8, 0xd8($k0)
sd $t9, 0xe0($k0)
sd $gp, 0xe8($k0)
sd $sp, 0xf0($k0)
sd $fp, 0xf8($k0)
sd $ra, 0x100($k0)
#ifdef VERSION_EU_SH_CN
#ifdef VERSION_CN
mflo $t0
sd $t0, 0x108($k0)
mfhi $t0
sd $t0, 0x110($k0)
lw $k1, 0x118($k0)
andi $t1, $k1, SR_IMASK
beqz $t1, savercp
nop
la $t0, __OSGlobalIntMask
lw $t0, ($t0)
lui $at, (0xFFFFFFFF >> 16)
ori $at, (0xFFFFFFFF & 0xFFFF)
xor $t2, $t0, $at
andi $t2, $t2, SR_IMASK
or $t4, $t1, $t2
lui $at, (~SR_IMASK >> 16) & 0xFFFF
ori $at, (~SR_IMASK & 0xFFFF)
and $t3, $k1, $at
or $t3, $t3, $t4
sw $t3, 0x118($k0)
andi $t0, $t0, SR_IMASK
and $t1, $t1, $t0
lui $at, (~SR_IMASK >> 16) & 0xFFFF
ori $at, (~SR_IMASK & 0xFFFF)
and $k1, $k1, $at
or $k1, $k1, $t1
#else
beqz $t1, savercp
sd $t0, 0x110($k0)
la $t0, __OSGlobalIntMask
lw $t0, ($t0)
li $at, -1
#ifdef VERSION_EU
xor $t0, $t0, $at
#else
xor $t2, $t0, $at
#endif
lui $at, (~SR_IMASK >> 16) & 0xFFFF
#ifdef VERSION_EU
andi $t0, $t0, SR_IMASK
#else
andi $t2, $t2, SR_IMASK
#endif
ori $at, (~SR_IMASK & 0xFFFF)
#ifdef VERSION_EU
or $t1, $t1, $t0
and $k1, $k1, $at
or $k1, $k1, $t1
sw $k1, 0x118($k0)
#else
or $t4, $t1, $t2
and $t3, $k1, $at
andi $t0, $t0, SR_IMASK
or $t3, $t3, $t4
and $t1, $t1, $t0
and $k1, $k1, $at
sw $t3, 0x118($k0)
or $k1, $k1, $t1
#endif
#endif
savercp:
lui $t1, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
lw $t1, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($t1)
beqz $t1, endrcp
nop
la $t0, __OSGlobalIntMask
lw $t0, ($t0)
#ifdef VERSION_CN
srl $t0, $t0, 0x10
li $at, 0xFFFFFFFF
#else
lw $t4, 0x128($k0)
li $at, 0xFFFFFFFF
srl $t0, $t0, 0x10
#endif
xor $t0, $t0, $at
andi $t0, $t0, 0x3f
#ifdef VERSION_CN
lw $t4, 0x128($k0)
#endif
and $t0, $t0, $t4
or $t1, $t1, $t0
endrcp:
sw $t1, 0x128($k0)
#else
sd $t0, 0x110($k0)
#endif
mfc0 $t0, C0_EPC
sw $t0, 0x11c($k0)
lw $t0, 0x18($k0)
beqz $t0, .L80326868
nop
cfc1 $t0, $31
nop
sw $t0, 0x12c($k0)
sdc1 $f0, 0x130($k0)
sdc1 $f2, 0x138($k0)
sdc1 $f4, 0x140($k0)
sdc1 $f6, 0x148($k0)
sdc1 $f8, 0x150($k0)
sdc1 $f10, 0x158($k0)
sdc1 $f12, 0x160($k0)
sdc1 $f14, 0x168($k0)
sdc1 $f16, 0x170($k0)
sdc1 $f18, 0x178($k0)
sdc1 $f20, 0x180($k0)
sdc1 $f22, 0x188($k0)
sdc1 $f24, 0x190($k0)
sdc1 $f26, 0x198($k0)
sdc1 $f28, 0x1a0($k0)
sdc1 $f30, 0x1a8($k0)
.L80326868:
mfc0 $t0, C0_CAUSE
sw $t0, 0x120($k0)
#ifndef VERSION_EU_SH_CN
lui $t1, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
lw $t1, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($t1)
sw $t1, 0x128($k0)
#endif
li $t1, 2
sh $t1, 0x10($k0)
#ifndef VERSION_EU_SH_CN
lui $t1, %hi(D_80334934)
lw $t1, %lo(D_80334934)($t1)
beqz $t1, .L803268B4
nop
lui $t2, %hi(D_C0000008)
sw $zero, %lo(D_C0000008)($t2)
lui $a0, %hi(D_C0000000)
addiu $t2, %lo(D_C0000008)
jal kdebugserver
lw $a0, %lo(D_C0000000)($a0)
b .L80326E08
nop
.L803268B4:
lui $t1, %hi(D_80334938)
lw $t1, %lo(D_80334938)($t1)
beqz $t1, .L80326900
nop
lui $t2, %hi(D_C000000C)
sw $zero, %lo(D_C000000C)($t2)
lui $t1, %hi(__osRdbSendMessage)
lw $t1, %lo(__osRdbSendMessage)($t1)
addiu $t2, %lo(D_C000000C)
beqz $t1, .L803268E8
nop
jal send_mesg
li $a0, 120
.L803268E8:
lui $t1, %hi(__osRdbWriteOK)
lw $t1, %lo(__osRdbWriteOK)($t1)
lui $at, %hi(__osRdbWriteOK)
addi $t1, $t1, 1
b .L80326E08
sw $t1, %lo(__osRdbWriteOK)($at)
.L80326900:
#endif
andi $t1, $t0, CAUSE_EXCMASK
li $t2, EXC_BREAK
beq $t1, $t2, handle_break
nop
li $t2, EXC_CPU
beq $t1, $t2, handle_CpU
nop
li $t2, EXC_INT
bne $t1, $t2, panic
nop
and $s0, $k1, $t0
next_interrupt:
andi $t1, $s0, SR_IMASK
srl $t2, $t1, 0xc
bnez $t2, .L80326944
nop
srl $t2, $t1, 8
addi $t2, $t2, 0x10
.L80326944:
// TODO: Get rid of noat
.set at
lbu $t2, __osIntOffTable($t2)
lw $t2, __osIntTable($t2)
.set noat
jr $t2
nop
#ifdef VERSION_EU_SH_CN
glabel IP6_Hdlr
li $at, ~CAUSE_IP6
b next_interrupt
and $s0, $s0, $at
glabel IP7_Hdlr
li $at, ~CAUSE_IP7
b next_interrupt
and $s0, $s0, $at
#endif
glabel counter
mfc0 $t1, C0_COMPARE
mtc0 $t1, C0_COMPARE
#ifdef VERSION_CN
li $a0, 24
jal send_mesg
nop
#else
jal send_mesg
li $a0, 24
#endif
lui $at, (~CAUSE_IP8 >> 16) & 0xFFFF
ori $at, (~CAUSE_IP8 & 0xFFFF)
b next_interrupt
and $s0, $s0, $at
glabel cart
#ifdef VERSION_EU_SH_CN
li $at, ~CAUSE_IP4
and $s0, $s0, $at
#endif
#ifdef VERSION_CN
la $t1, __osHwIntTable
addi $t1, $t1, 4 * 2
lw $t2, ($t1)
beqz $t2, .L80307480
nop
jalr $t2
lw $sp, 4($t1)
beqz $v0, .L80307480
nop
b redispatch
nop
.L80307480:
lui $s1, %hi(PHYS_TO_K1(MI_HW_INTR_REG))
lw $s1, %lo(PHYS_TO_K1(MI_HW_INTR_REG))($s1)
andi $t1, $s1, 0x40
beqz $t1, .L803074AC
nop
andi $s1, $s1, 0x3F80
li $t1, 0
lui $at, %hi(PHYS_TO_K1(PI_CARD_ADDR_REG))
sw $t1, %lo(PHYS_TO_K1(PI_CARD_ADDR_REG))($at)
jal send_mesg
li $a0, 184
.L803074AC:
andi $t1, $s1, 0x2000
beqz $t1, .L803074D0
nop
andi $s1, $s1, 0x1FC0
li $t1, 0x2000
lui $at, %hi(PHYS_TO_K1(MI_HW_INTR_REG))
sw $t1, %lo(PHYS_TO_K1(MI_HW_INTR_REG))($at)
jal send_mesg
li $a0, 240
.L803074D0:
andi $t1, $s1, 0x80
beqz $t1, .L803074F4
nop
andi $s1, $s1, 0x3F40
li $t1, 0x4000
lui $at, %hi(PHYS_TO_K1(MI_HW_INTR_MASK_REG))
sw $t1, %lo(PHYS_TO_K1(MI_HW_INTR_MASK_REG))($at)
jal send_mesg
li $a0, 192
.L803074F4:
andi $t1, $s1, 0x100
beqz $t1, .L80307518
nop
andi $s1, $s1, 0x3EC0
lui $t1, 1
lui $at, %hi(PHYS_TO_K1(MI_HW_INTR_MASK_REG))
sw $t1, %lo(PHYS_TO_K1(MI_HW_INTR_MASK_REG))($at)
jal send_mesg
li $a0, 200
.L80307518:
andi $t1, $s1, 0x200
beqz $t1, .L8030753C
nop
andi $s1, $s1, 0x3DC0
lui $t1, 4
lui $at, %hi(PHYS_TO_K1(MI_HW_INTR_MASK_REG))
sw $t1, %lo(PHYS_TO_K1(MI_HW_INTR_MASK_REG))($at)
jal send_mesg
li $a0, 208
.L8030753C:
andi $t1, $s1, 0x400
beqz $t1, .L80307560
nop
andi $s1, $s1, 0x3BC0
lui $t1, 0x10
lui $at, %hi(PHYS_TO_K1(MI_HW_INTR_MASK_REG))
sw $t1, %lo(PHYS_TO_K1(MI_HW_INTR_MASK_REG))($at)
jal send_mesg
li $a0, 216
.L80307560:
andi $t1, $s1, 0x800
beqz $t1, .L80307584
nop
andi $s1, $s1, 0x37C0
lui $t1, 0x40
lui $at, %hi(PHYS_TO_K1(MI_HW_INTR_MASK_REG))
sw $t1, %lo(PHYS_TO_K1(MI_HW_INTR_MASK_REG))($at)
jal send_mesg
li $a0, 224
.L80307584:
b next_interrupt
nop
#else
li $t2, 4
lui $at, %hi(__osHwIntTable)
addu $at, $at, $t2
lw $t2, %lo(__osHwIntTable)($at)
#ifdef VERSION_EU_SH
la $sp, leoDiskStack
li $a0, 16
beqz $t2, .L803269A4
addiu $sp, $sp, 0xff0
#else
beqz $t2, .L803269A4
nop
#endif
jalr $t2
nop
#ifdef VERSION_EU_SH
beqz $v0, .L803269A4
#ifdef VERSION_SH
li $a0, 0x10
#else
nop
#endif
b redispatch
nop
#endif
.L803269A4:
jal send_mesg
#ifdef VERSION_EU_SH
nop
b next_interrupt
nop
#else
li $a0, 16
li $at, -2049
b next_interrupt
and $s0, $s0, $at
#endif
#endif
glabel rcp
#ifdef VERSION_EU_SH
la $t0, __OSGlobalIntMask
lw $t0, ($t0)
#endif
lui $s1, %hi(PHYS_TO_K1(MI_INTR_REG))
lw $s1, %lo(PHYS_TO_K1(MI_INTR_REG))($s1)
#ifdef VERSION_CN
la $t0, __OSGlobalIntMask
lw $t0, ($t0)
#endif
#ifdef VERSION_EU_SH_CN
srl $t0, $t0, 0x10
and $s1, $s1, $t0
#else
andi $s1, $s1, 0x3f
#endif
andi $t1, $s1, MI_INTR_SP
beqz $t1, vi
nop
#ifdef VERSION_CN
andi $s1, $s1, 0x3e
#endif
lui $t4, %hi(PHYS_TO_K1(SP_STATUS_REG))
lw $t4, %lo(PHYS_TO_K1(SP_STATUS_REG))($t4)
#ifdef VERSION_CN
li $t1, SP_CLR_INTR | SP_CLR_SIG3
#else
li $t1, SP_CLR_INTR
#endif
lui $at, %hi(PHYS_TO_K1(SP_STATUS_REG))
#ifdef VERSION_CN
sw $t1, %lo(PHYS_TO_K1(SP_STATUS_REG))($at)
andi $t4, $t4, 0x300
beqz $t4, sp_other_break
nop
#else
andi $t4, $t4, 0x300
andi $s1, $s1, 0x3e
beqz $t4, sp_other_break
sw $t1, %lo(PHYS_TO_K1(SP_STATUS_REG))($at)
#endif
jal send_mesg
li $a0, 32
beqz $s1, no_more_rcp_ints
nop
b vi
nop
sp_other_break:
jal send_mesg
li $a0, 88
beqz $s1, no_more_rcp_ints
nop
vi:
andi $t1, $s1, 8
beqz $t1, ai
#ifdef VERSION_CN
nop
andi $s1, $s1, 0x37
lui $at, %hi(PHYS_TO_K1(VI_CURRENT_REG))
#else
lui $at, %hi(PHYS_TO_K1(VI_CURRENT_REG))
andi $s1, $s1, 0x37
#endif
sw $zero, %lo(PHYS_TO_K1(VI_CURRENT_REG))($at)
jal send_mesg
li $a0, 56
beqz $s1, no_more_rcp_ints
nop
ai:
andi $t1, $s1, 4
beqz $t1, si
nop
#ifdef VERSION_CN
andi $s1, $s1, 0x3b
#endif
li $t1, 1
lui $at, %hi(PHYS_TO_K1(AI_STATUS_REG))
#ifndef VERSION_CN
andi $s1, $s1, 0x3b
#endif
sw $t1, %lo(PHYS_TO_K1(AI_STATUS_REG))($at)
jal send_mesg
li $a0, 48
beqz $s1, no_more_rcp_ints
nop
si:
andi $t1, $s1, 2
beqz $t1, pi
#ifdef VERSION_CN
nop
#else
lui $at, %hi(PHYS_TO_K1(SI_STATUS_REG))
#endif
andi $s1, $s1, 0x3d
#ifdef VERSION_CN
lui $at, %hi(PHYS_TO_K1(SI_STATUS_REG))
#endif
sw $zero, %lo(PHYS_TO_K1(SI_STATUS_REG))($at)
jal send_mesg
li $a0, 40
beqz $s1, no_more_rcp_ints
nop
pi:
andi $t1, $s1, 0x10
beqz $t1, dp
nop
#ifdef VERSION_CN
andi $s1, $s1, 0x2f
li $t1, 2
lui $at, %hi(PHYS_TO_K1(PI_STATUS_REG))
sw $t1, %lo(PHYS_TO_K1(PI_STATUS_REG))($at)
la $t1, D_CN_80319658
lw $t2, ($t1)
beqz $t2, .L803076C0
nop
lw $sp, 4($t1)
jalr $t2
move $a0, $v0
bnez $v0, .L803076C8
nop
.L803076C0:
#else
li $t1, 2
lui $at, %hi(PHYS_TO_K1(PI_STATUS_REG))
andi $s1, $s1, 0x2f
sw $t1, %lo(PHYS_TO_K1(PI_STATUS_REG))($at)
#endif
jal send_mesg
li $a0, 64
.L803076C8:
beqz $s1, no_more_rcp_ints
nop
dp:
andi $t1, $s1, 0x20
beqz $t1, no_more_rcp_ints
nop
#ifdef VERSION_CN
andi $s1, $s1, 0x1f
#endif
li $t1, MI_CLR_DP_INTR
lui $at, %hi(PHYS_TO_K1(MI_MODE_REG))
#ifndef VERSION_CN
andi $s1, $s1, 0x1f
#endif
sw $t1, %lo(PHYS_TO_K1(MI_MODE_REG))($at)
jal send_mesg
li $a0, 72
no_more_rcp_ints:
li $at, -1025
b next_interrupt
and $s0, $s0, $at
glabel prenmi
lw $k1, 0x118($k0)
li $at, -4097
#ifdef VERSION_CN
and $k1, $k1, $at
sw $k1, 0x118($k0)
la $t1, __osShutdown
#else
lui $t1, %hi(__osShutdown)
and $k1, $k1, $at
sw $k1, 0x118($k0)
addiu $t1, %lo(__osShutdown)
#endif
lw $t2, ($t1)
beqz $t2, firstnmi
#ifdef VERSION_CN
nop
#endif
li $at, -4097
b redispatch
and $s0, $s0, $at
firstnmi:
li $t2, 1
sw $t2, ($t1)
jal send_mesg
li $a0, 112
#ifdef VERSION_CN
li $at, -4097
and $s0, $s0, $at
#endif
lui $t2, %hi(__osThreadTail + 0x8)
lw $t2, %lo(__osThreadTail + 0x8)($t2)
#ifndef VERSION_CN
li $at, -4097
and $s0, $s0, $at
#endif
lw $k1, 0x118($t2)
#ifdef VERSION_CN
li $at, -4097
#endif
and $k1, $k1, $at
b redispatch
sw $k1, 0x118($t2)
glabel sw2
li $at, -513
and $t0, $t0, $at
mtc0 $t0, $13
#ifdef VERSION_CN
li $a0, 8
jal send_mesg
nop
#else
jal send_mesg
li $a0, 8
#endif
li $at, -513
b next_interrupt
and $s0, $s0, $at
glabel sw1
li $at, -257
and $t0, $t0, $at
mtc0 $t0, $13
#ifdef VERSION_CN
li $a0, 0
jal send_mesg
nop
#else
jal send_mesg
li $a0, 0
#endif
li $at, -257
b next_interrupt
and $s0, $s0, $at
handle_break:
li $t1, 1
sh $t1, 0x12($k0)
jal send_mesg
li $a0, 80
b redispatch
nop
glabel redispatch
#ifdef VERSION_CN
lw $t1, 4($k0)
lui $t2, %hi(__osThreadTail + 0x8)
lw $t2, %lo(__osThreadTail + 0x8)($t2)
lw $t3, 4($t2)
slt $at, $t1, $t3
beqz $at, enqueue_running
nop
move $a1, $k0
la $a0, __osThreadTail + 0x8
jal __osEnqueueThread
nop
#else
lui $t2, %hi(__osThreadTail + 0x8)
lw $t2, %lo(__osThreadTail + 0x8)($t2)
lw $t1, 4($k0)
lw $t3, 4($t2)
slt $at, $t1, $t3
beqz $at, enqueue_running
nop
lui $a0, %hi(__osThreadTail + 0x8)
move $a1, $k0
jal __osEnqueueThread
addiu $a0, %lo(__osThreadTail + 0x8)
#endif
j __osDispatchThread
nop
enqueue_running:
la $t1, __osThreadTail + 0x8
lw $t2, ($t1)
sw $t2, ($k0)
j __osDispatchThread
sw $k0, ($t1)
glabel panic
lui $at, %hi(__osThreadTail + 0x14)
sw $k0, %lo(__osThreadTail + 0x14)($at)
li $t1, 1
sh $t1, 0x10($k0)
li $t1, 2
sh $t1, 0x12($k0)
mfc0 $t2, $8
sw $t2, 0x124($k0)
jal send_mesg
li $a0, 96
j __osDispatchThread
nop
glabel send_mesg
#ifdef VERSION_CN
move $s2, $ra
#endif
la $t2, __osEventStateTab
addu $t2, $t2, $a0
lw $t1, ($t2)
#ifndef VERSION_CN
move $s2, $ra
#endif
beqz $t1, .L80326CC4
nop
lw $t3, 8($t1)
lw $t4, 0x10($t1)
slt $at, $t3, $t4
beqz $at, .L80326CC4
nop
lw $t5, 0xc($t1)
addu $t5, $t5, $t3
#ifdef VERSION_CN
bnez $t4, .L80326C60
div $zero, $t5, $t4
#else
div $zero, $t5, $t4
bnez $t4, .L80326C60
nop
#endif
break 7
.L80326C60:
li $at, -1
bne $t4, $at, .L80326C78
lui $at, 0x8000
bne $t5, $at, .L80326C78
nop
break 6
.L80326C78:
#ifdef VERSION_CN
mfhi $t5
lw $t4, 0x14($t1)
li $at, 4
mult $t5, $at
mflo $t5
#else
lw $t4, 0x14($t1)
mfhi $t5
sll $t5, $t5, 2
#endif
addu $t4, $t4, $t5
lw $t5, 4($t2)
#ifdef VERSION_CN
sw $t5, ($t4)
addiu $t2, $t3, 1
#else
addiu $t2, $t3, 1
sw $t5, ($t4)
#endif
sw $t2, 8($t1)
lw $t2, ($t1)
lw $t3, ($t2)
beqz $t3, .L80326CC4
nop
jal __osPopThread
move $a0, $t1
move $t2, $v0
#ifdef VERSION_CN
move $a1, $t2
la $a0, __osThreadTail + 0x8
jal __osEnqueueThread
nop
#else
lui $a0, %hi(__osThreadTail + 0x8)
move $a1, $t2
jal __osEnqueueThread
addiu $a0, %lo(__osThreadTail + 0x8)
#endif
.L80326CC4:
jr $s2
nop
handle_CpU: // coprocessor error
lui $at, 0x3000
and $t1, $t0, $at
srl $t1, $t1, 0x1c
li $t2, 1
bne $t1, $t2, panic
nop
#ifdef VERSION_CN
li $t1, 1
sw $t1, 0x18($k0)
lw $k1, 0x118($k0)
lui $at, 0x2000
or $k1, $k1, $at
#else
lw $k1, 0x118($k0)
lui $at, 0x2000
li $t1, 1
or $k1, $k1, $at
sw $t1, 0x18($k0)
#endif
b enqueue_running
sw $k1, 0x118($k0)
glabel __osEnqueueAndYield
lui $a1, %hi(__osThreadTail + 0x10)
lw $a1, %lo(__osThreadTail + 0x10)($a1)
mfc0 $t0, $12
#ifndef VERSION_CN
lw $k1, 0x18($a1)
#endif
ori $t0, $t0, 2
sw $t0, 0x118($a1)
sd $s0, 0x98($a1)
sd $s1, 0xa0($a1)
sd $s2, 0xa8($a1)
sd $s3, 0xb0($a1)
sd $s4, 0xb8($a1)
sd $s5, 0xc0($a1)
sd $s6, 0xc8($a1)
sd $s7, 0xd0($a1)
sd $gp, 0xe8($a1)
sd $sp, 0xf0($a1)
sd $fp, 0xf8($a1)
sd $ra, 0x100($a1)
#ifdef VERSION_CN
sw $ra, 0x11c($a1)
lw $k1, 0x18($a1)
beqz $k1, .L80326D70
nop
cfc1 $k1, $31
sw $k1, 0x12c($a1)
#else
beqz $k1, .L80326D70
sw $ra, 0x11c($a1)
cfc1 $k1, $31
#endif
sdc1 $f20, 0x180($a1)
sdc1 $f22, 0x188($a1)
sdc1 $f24, 0x190($a1)
sdc1 $f26, 0x198($a1)
sdc1 $f28, 0x1a0($a1)
sdc1 $f30, 0x1a8($a1)
#ifndef VERSION_CN
sw $k1, 0x12c($a1)
#endif
.L80326D70:
#ifdef VERSION_EU_SH_CN
lw $k1, 0x118($a1)
andi $t1, $k1, 0xff00
beqz $t1, .L802F3FBC
nop
la $t0, __OSGlobalIntMask
lw $t0, ($t0)
li $at, 0xFFFFFFFF
xor $t0, $t0, $at
#ifdef VERSION_CN
andi $t0, $t0, SR_IMASK
or $t1, $t1, $t0
li $at, ~SR_IMASK
#else
lui $at, (~SR_IMASK >> 16) & 0xFFFF
andi $t0, $t0, SR_IMASK
ori $at, (~SR_IMASK & 0xFFFF)
or $t1, $t1, $t0
#endif
and $k1, $k1, $at
or $k1, $k1, $t1
sw $k1, 0x118($a1)
.L802F3FBC:
#endif
lui $k1, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
lw $k1, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($k1)
#ifdef VERSION_EU_SH_CN
beqz $k1, .L802F3FF4
nop
la $k0, __OSGlobalIntMask
lw $k0, ($k0)
#ifdef VERSION_CN
srl $k0, $k0, 0x10
li $at, 0xFFFFFFFF
xor $k0, $k0, $at
andi $k0, $k0, 0x3f
lw $t0, 0x128($a1)
#else
lw $t0, 0x128($a1)
li $at, 0xFFFFFFFF
srl $k0, $k0, 0x10
xor $k0, $k0, $at
andi $k0, $k0, 0x3f
#endif
and $k0, $k0, $t0
or $k1, $k1, $k0
.L802F3FF4:
#endif
beqz $a0, .L80326D88
sw $k1, 0x128($a1)
jal __osEnqueueThread
nop
.L80326D88:
j __osDispatchThread
nop
// enqueue and pop look like compiled functions? but there's no easy way to extract them
glabel __osEnqueueThread
#ifdef VERSION_CN
move $t9, $a0
#endif
lw $t8, ($a0)
lw $t7, 4($a1)
#ifndef VERSION_CN
move $t9, $a0
#endif
lw $t6, 4($t8)
slt $at, $t6, $t7
bnez $at, .L80326DC4
nop
.L80326DAC:
move $t9, $t8
lw $t8, ($t8)
lw $t6, 4($t8)
slt $at, $t6, $t7
beqz $at, .L80326DAC
nop
.L80326DC4:
lw $t8, ($t9)
sw $t8, ($a1)
sw $a1, ($t9)
jr $ra
sw $a0, 8($a1)
glabel __osPopThread
lw $v0, ($a0)
lw $t9, ($v0)
jr $ra
sw $t9, ($a0)
#ifdef VERSION_CN
func_unused:
jr $ra
nop
#endif
glabel __osDispatchThread
#ifdef VERSION_CN
la $a0, __osThreadTail + 0x8
jal __osPopThread
nop
#else
lui $a0, %hi(__osThreadTail + 0x8)
jal __osPopThread
addiu $a0, %lo(__osThreadTail + 0x8)
#endif
lui $at, %hi(__osThreadTail + 0x10)
sw $v0, %lo(__osThreadTail + 0x10)($at)
li $t0, 4
sh $t0, 0x10($v0)
move $k0, $v0
#ifdef VERSION_EU_SH_CN
#ifdef VERSION_CN
lw $k1, 0x118($k0)
la $t0, __OSGlobalIntMask
lw $t0, ($t0)
andi $t0, $t0, SR_IMASK
andi $t1, $k1, SR_IMASK
and $t1, $t1, $t0
li $at, ~SR_IMASK
#else
lui $t0, %hi(__OSGlobalIntMask)
lw $k1, 0x118($k0)
addiu $t0, %lo(__OSGlobalIntMask)
lw $t0, ($t0)
lui $at, (~SR_IMASK >> 16) & 0xFFFF
andi $t1, $k1, SR_IMASK
ori $at, (~SR_IMASK & 0xFFFF)
andi $t0, $t0, SR_IMASK
and $t1, $t1, $t0
#endif
and $k1, $k1, $at
or $k1, $k1, $t1
mtc0 $k1, $12
#endif
.L80326E08:
#ifndef VERSION_CN
ld $k1, 0x108($k0)
#endif
ld $at, 0x20($k0)
ld $v0, 0x28($k0)
#ifndef VERSION_CN
mtlo $k1
ld $k1, 0x110($k0)
#endif
ld $v1, 0x30($k0)
ld $a0, 0x38($k0)
ld $a1, 0x40($k0)
ld $a2, 0x48($k0)
ld $a3, 0x50($k0)
ld $t0, 0x58($k0)
ld $t1, 0x60($k0)
ld $t2, 0x68($k0)
ld $t3, 0x70($k0)
ld $t4, 0x78($k0)
ld $t5, 0x80($k0)
ld $t6, 0x88($k0)
ld $t7, 0x90($k0)
ld $s0, 0x98($k0)
ld $s1, 0xa0($k0)
ld $s2, 0xa8($k0)
ld $s3, 0xb0($k0)
ld $s4, 0xb8($k0)
ld $s5, 0xc0($k0)
ld $s6, 0xc8($k0)
ld $s7, 0xd0($k0)
ld $t8, 0xd8($k0)
ld $t9, 0xe0($k0)
ld $gp, 0xe8($k0)
#ifndef VERSION_CN
mthi $k1
#endif
ld $sp, 0xf0($k0)
ld $fp, 0xf8($k0)
ld $ra, 0x100($k0)
#ifdef VERSION_CN
ld $k1, 0x108($k0)
mtlo $k1
ld $k1, 0x110($k0)
mthi $k1
#endif
lw $k1, 0x11c($k0)
mtc0 $k1, $14
#ifndef VERSION_EU_SH_CN
lw $k1, 0x118($k0)
mtc0 $k1, $12
#endif
lw $k1, 0x18($k0)
beqz $k1, .L80326EF0
nop
lw $k1, 0x12c($k0)
ctc1 $k1, $31
ldc1 $f0, 0x130($k0)
ldc1 $f2, 0x138($k0)
ldc1 $f4, 0x140($k0)
ldc1 $f6, 0x148($k0)
ldc1 $f8, 0x150($k0)
ldc1 $f10, 0x158($k0)
ldc1 $f12, 0x160($k0)
ldc1 $f14, 0x168($k0)
ldc1 $f16, 0x170($k0)
ldc1 $f18, 0x178($k0)
ldc1 $f20, 0x180($k0)
ldc1 $f22, 0x188($k0)
ldc1 $f24, 0x190($k0)
ldc1 $f26, 0x198($k0)
ldc1 $f28, 0x1a0($k0)
ldc1 $f30, 0x1a8($k0)
.L80326EF0:
lw $k1, 0x128($k0)
#ifdef VERSION_EU_SH_CN
la $k0, __OSGlobalIntMask
lw $k0, ($k0)
srl $k0, $k0, 0x10
and $k1, $k1, $k0
#endif
sll $k1, $k1, 1
la $k0, __osRcpImTable
addu $k1, $k1, $k0
lhu $k1, ($k1)
#ifdef VERSION_CN
li $k0, PHYS_TO_K1(MI_INTR_MASK_REG)
#else
// TODO: is this an la?
lui $k0, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
addiu $k0, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))
#endif
sw $k1, ($k0)
nop
nop
nop
nop
eret
glabel __osCleanupThread
jal osDestroyThread
move $a0, $zero
.section .data
glabel __osHwIntTable
.word 0
.word 0
.word 0
.word 0
.word 0
#ifdef VERSION_CN
// CN: table is now 2 words per entry (handler, sp)
.word 0
.word 0
.word 0
.word 0
.word 0
// Is this part of __osHwIntTable?
glabel D_CN_80319658
.word 0
#endif
#ifndef VERSION_EU_SH_CN
glabel D_80334934
.word 0
glabel D_80334938
.word 0
.word 0
#endif
.section .rodata
glabel __osIntOffTable
.byte 0x00,0x14,0x18,0x18,0x1C,0x1C,0x1C,0x1C,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x04,0x08,0x08,0x0C,0x0C,0x0C,0x0C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10
glabel __osIntTable
.word redispatch
.word sw1
.word sw2
.word rcp
.word cart
.word prenmi
#ifdef VERSION_EU_SH_CN
.word IP6_Hdlr
.word IP7_Hdlr
#else
.word panic
.word panic
#endif
.word counter
.word 0
.word 0
.word 0
|
96flashbacks/springroll
| 8,318
|
lib/asm/bcopy.s
|
.set noat // allow manual use of $at
.set noreorder // don't insert nops after branches
#include "macros.inc"
.section .text, "ax"
//TODO There seem to be patterns in these iQue diffs. Can we figure out what's causing them? Could this have been written in C?
//also ifdef hell lol
glabel bcopy
beqz $a2, .L80323A4C
move $a3, $a1
#ifdef VERSION_CN
beq $a0, $a1, .L80323A4C
nop
slt $at, $a1, $a0
bnez $at, .L80323A14
nop
add $v0, $a0, $a2
slt $at, $a1, $v0
beqz $at, .L80323A14
nop
b .L80323B78
nop
.L80323A14:
slti $at, $a2, 0x10
#else
beq $a0, $a1, .L80323A4C
slt $at, $a1, $a0
bnezl $at, .L80323A14
slti $at, $a2, 0x10
add $v0, $a0, $a2
slt $at, $a1, $v0
beqzl $at, .L80323A14
slti $at, $a2, 0x10
b .L80323B78
slti $at, $a2, 0x10
slti $at, $a2, 0x10
.L80323A14:
#endif
bnez $at, .L80323A2C
nop
andi $v0, $a0, 3
andi $v1, $a1, 3
beq $v0, $v1, .L80323A54
nop
.L80323A2C:
beqz $a2, .L80323A4C
nop
addu $v1, $a0, $a2
.L80323A38:
lb $v0, ($a0)
addiu $a0, $a0, 1
#ifdef VERSION_CN
sb $v0, ($a1)
bne $a0, $v1, .L80323A38
addiu $a1, $a1, 1
#else
addiu $a1, $a1, 1
bne $a0, $v1, .L80323A38
sb $v0, -1($a1)
#endif
.L80323A4C:
jr $ra
move $v0, $a3
.L80323A54:
#ifdef VERSION_CN
beqz $v0, .L80323AB8
nop
li $at, 1
beq $v0, $at, .L80323A9C
nop
li $at, 2
beq $v0, $at, .L80323A88
nop
lb $v0, ($a0)
addiu $a0, $a0, 1
sb $v0, ($a1)
addiu $a1, $a1, 1
b .L80323AB8
addiu $a2, $a2, -1
.L80323A88:
lh $v0, ($a0)
#else
beqz $v0, .L80323AB8
li $at, 1
beq $v0, $at, .L80323A9C
li $at, 2
beql $v0, $at, .L80323A88
lh $v0, ($a0)
lb $v0, ($a0)
addiu $a0, $a0, 1
addiu $a1, $a1, 1
addiu $a2, $a2, -1
b .L80323AB8
sb $v0, -1($a1)
lh $v0, ($a0)
.L80323A88:
#endif
addiu $a0, $a0, 2
#ifdef VERSION_CN
sh $v0, ($a1)
addiu $a1, $a1, 2
b .L80323AB8
addiu $a2, $a2, -2
#else
addiu $a1, $a1, 2
addiu $a2, $a2, -2
b .L80323AB8
sh $v0, -2($a1)
#endif
.L80323A9C:
lb $v0, ($a0)
lh $v1, 1($a0)
addiu $a0, $a0, 3
#ifdef VERSION_CN
sb $v0, ($a1)
sh $v1, 1($a1)
#endif
addiu $a1, $a1, 3
addiu $a2, $a2, -3
#ifndef VERSION_CN
sb $v0, -3($a1)
sh $v1, -2($a1)
#endif
.L80323AB8:
slti $at, $a2, 0x20
#ifdef VERSION_CN
bnez $at, .L80323B14
nop
#else
bnezl $at, .L80323B18
slti $at, $a2, 0x10
#endif
lw $v0, ($a0)
lw $v1, 4($a0)
lw $t0, 8($a0)
lw $t1, 0xc($a0)
lw $t2, 0x10($a0)
lw $t3, 0x14($a0)
lw $t4, 0x18($a0)
lw $t5, 0x1c($a0)
addiu $a0, $a0, 0x20
#ifdef VERSION_CN
sw $v0, ($a1)
sw $v1, 4($a1)
sw $t0, 8($a1)
sw $t1, 0xc($a1)
sw $t2, 0x10($a1)
sw $t3, 0x14($a1)
sw $t4, 0x18($a1)
sw $t5, 0x1c($a1)
#endif
addiu $a1, $a1, 0x20
#ifndef VERSION_CN
addiu $a2, $a2, -0x20
sw $v0, -0x20($a1)
sw $v1, -0x1c($a1)
sw $t0, -0x18($a1)
sw $t1, -0x14($a1)
sw $t2, -0x10($a1)
sw $t3, -0xc($a1)
sw $t4, -8($a1)
#endif
b .L80323AB8
#ifdef VERSION_CN
addiu $a2, $a2, -0x20
#else
sw $t5, -4($a1)
#endif
.L80323B14:
slti $at, $a2, 0x10
.L80323B18:
#ifdef VERSION_CN
bnez $at, .L80323B50
nop
#else
bnezl $at, .L80323B54
slti $at, $a2, 4
#endif
lw $v0, ($a0)
lw $v1, 4($a0)
lw $t0, 8($a0)
lw $t1, 0xc($a0)
addiu $a0, $a0, 0x10
#ifdef VERSION_CN
sw $v0, ($a1)
sw $v1, 4($a1)
sw $t0, 8($a1)
sw $t1, 0xc($a1)
#endif
addiu $a1, $a1, 0x10
#ifndef VERSION_CN
addiu $a2, $a2, -0x10
sw $v0, -0x10($a1)
sw $v1, -0xc($a1)
sw $t0, -8($a1)
#endif
b .L80323B14
#ifdef VERSION_CN
addiu $a2, $a2, -0x10
#else
sw $t1, -4($a1)
#endif
.L80323B50:
slti $at, $a2, 4
.L80323B54:
bnez $at, .L80323A2C
nop
lw $v0, ($a0)
addiu $a0, $a0, 4
#ifdef VERSION_CN
sw $v0, ($a1)
#endif
addiu $a1, $a1, 4
#ifndef VERSION_CN
addiu $a2, $a2, -4
#endif
b .L80323B50
#ifdef VERSION_CN
addiu $a2, $a2, -4
#else
sw $v0, -4($a1)
slti $at, $a2, 0x10
#endif
.L80323B78:
add $a0, $a0, $a2
#ifdef VERSION_CN
add $a1, $a1, $a2
slti $at, $a2, 0x10
#endif
bnez $at, .L80323B94
#ifdef VERSION_CN
nop
#else
add $a1, $a1, $a2
#endif
andi $v0, $a0, 3
andi $v1, $a1, 3
beq $v0, $v1, .L80323BC4
nop
.L80323B94:
beqz $a2, .L80323A4C
nop
addiu $a0, $a0, -1
addiu $a1, $a1, -1
subu $v1, $a0, $a2
.L80323BA8:
lb $v0, ($a0)
addiu $a0, $a0, -1
#ifdef VERSION_CN
sb $v0, 0($a1)
#else
addiu $a1, $a1, -1
#endif
bne $a0, $v1, .L80323BA8
#ifdef VERSION_CN
addiu $a1, $a1, -1
#else
sb $v0, 1($a1)
#endif
jr $ra
move $v0, $a3
.L80323BC4:
beqz $v0, .L80323C28
#ifdef VERSION_CN
nop
#endif
li $at, 3
beq $v0, $at, .L80323C0C
#ifdef VERSION_CN
nop
#endif
li $at, 2
#ifdef VERSION_CN
beq $v0, $at, .L80323BF4
nop
#else
beql $v0, $at, .L80323BF8
lh $v0, -2($a0)
#endif
lb $v0, -1($a0)
addiu $a0, $a0, -1
#ifdef VERSION_CN
sb $v0, -1($a1)
#endif
addiu $a1, $a1, -1
#ifndef VERSION_CN
addiu $a2, $a2, -1
#endif
b .L80323C28
#ifdef VERSION_CN
addiu $a2, $a2, -1
#else
sb $v0, ($a1)
#endif
.L80323BF4:
lh $v0, -2($a0)
.L80323BF8:
addiu $a0, $a0, -2
#ifdef VERSION_CN
sh $v0, -2($a1)
#endif
addiu $a1, $a1, -2
#ifndef VERSION_CN
addiu $a2, $a2, -2
#endif
b .L80323C28
#ifdef VERSION_CN
addiu $a2, $a2, -2
#else
sh $v0, ($a1)
#endif
.L80323C0C:
lb $v0, -1($a0)
lh $v1, -3($a0)
addiu $a0, $a0, -3
#ifdef VERSION_CN
sb $v0, -1($a1)
sh $v1, -3($a1)
addiu $a1, $a1, -3
addiu $a2, $a2, -3
#else
addiu $a1, $a1, -3
addiu $a2, $a2, -3
sb $v0, 2($a1)
sh $v1, ($a1)
#endif
.L80323C28:
slti $at, $a2, 0x20
#ifdef VERSION_CN
bnez $at, .L80323C84
nop
#else
bnezl $at, .L80323C88
slti $at, $a2, 0x10
#endif
lw $v0, -4($a0)
lw $v1, -8($a0)
lw $t0, -0xc($a0)
lw $t1, -0x10($a0)
lw $t2, -0x14($a0)
lw $t3, -0x18($a0)
lw $t4, -0x1c($a0)
lw $t5, -0x20($a0)
addiu $a0, $a0, -0x20
#ifdef VERSION_CN
sw $v0, -4($a1)
sw $v1, -8($a1)
sw $t0, -0xc($a1)
sw $t1, -0x10($a1)
sw $t2, -0x14($a1)
sw $t3, -0x18($a1)
sw $t4, -0x1c($a1)
sw $t5, -0x20($a1)
addiu $a1, $a1, -0x20
#else
addiu $a1, $a1, -0x20
addiu $a2, $a2, -0x20
sw $v0, 0x1c($a1)
sw $v1, 0x18($a1)
sw $t0, 0x14($a1)
sw $t1, 0x10($a1)
sw $t2, 0xc($a1)
sw $t3, 8($a1)
sw $t4, 4($a1)
#endif
b .L80323C28
#ifdef VERSION_CN
addiu $a2, $a2, -0x20
#else
sw $t5, ($a1)
#endif
.L80323C84:
slti $at, $a2, 0x10
.L80323C88:
#ifdef VERSION_CN
bnez $at, .L80323CC0
nop
#else
bnezl $at, .L80323CC4
slti $at, $a2, 4
#endif
lw $v0, -4($a0)
lw $v1, -8($a0)
lw $t0, -0xc($a0)
lw $t1, -0x10($a0)
addiu $a0, $a0, -0x10
#ifdef VERSION_CN
sw $v0, -4($a1)
sw $v1, -8($a1)
sw $t0, -0xc($a1)
sw $t1, -0x10($a1)
addiu $a1, $a1, -0x10
#else
addiu $a1, $a1, -0x10
addiu $a2, $a2, -0x10
sw $v0, 0xc($a1)
sw $v1, 8($a1)
sw $t0, 4($a1)
#endif
b .L80323C84
#ifdef VERSION_CN
addiu $a2, $a2, -0x10
#else
sw $t1, ($a1)
#endif
.L80323CC0:
slti $at, $a2, 4
.L80323CC4:
bnez $at, .L80323B94
nop
lw $v0, -4($a0)
addiu $a0, $a0, -4
#ifdef VERSION_CN
sw $v0, -4($a1)
#endif
addiu $a1, $a1, -4
#ifndef VERSION_CN
addiu $a2, $a2, -4
#endif
b .L80323CC0
#ifdef VERSION_CN
addiu $a2, $a2, -4
#else
sw $v0, ($a1)
nop
nop
nop
#endif
|
96flashbacks/springroll
| 1,329
|
lib/asm/__osSetCompare.s
|
.set noat
.set noreorder // don't insert nops after branches
#include "macros.inc"
#include <PR/R4300.h>
.section .text, "ax"
#ifdef VERSION_CN
glabel __osSetCompare
addiu $sp, $sp, -0x38
sd $ra, 0x30($sp)
sd $fp, 0x28($sp)
move $fp, $sp
sw $a0, 0x3c($fp)
lw $v0, 0x3c($fp)
beqz $v0, .L8030A25C
nop
jal __osDisableInt
nop
sw $v0, 0x20($fp)
lw $v0, 0x3c($fp)
lui $v1, %hi(sLastHighestCount2) # $v1, 0x8032
lw $v1, %lo(sLastHighestCount2)($v1)
sltu $v0, $v0, $v1
lui $v1, %hi(sNumCountOverflows2) # $v1, 0x8032
lw $v1, %lo(sNumCountOverflows2)($v1)
addu $v0, $v0, $v1
sw $v0, 0x24($fp)
lwu $v0, 0x24($fp)
dsll32 $v1, $v0, 0
lwu $a0, 0x3c($fp)
or $v0, $v1, $a0
move $a0, $v0
dsll $v1, $a0, 1
daddu $v1, $v1, $v0
dsll $a0, $v1, 6
li $at, 125
ddivu $zero, $a0, $at
mflo $v0
dsll32 $v0, $v0, 0
dsra32 $v0, $v0, 0
sw $v0, 0x3c($fp)
jal __osRestoreInt
lw $a0, 0x20($fp)
.L8030A25C:
lw $a1, 0x3c($fp)
mtc0 $a1, C0_COMPARE
move $sp, $fp
ld $ra, 0x30($sp)
ld $fp, 0x28($sp)
jr $ra
addiu $sp, $sp, 0x38
#else
glabel __osSetCompare
mtc0 $a0, C0_COMPARE
jr $ra
nop
#endif
|
96flashbacks/springroll
| 1,240
|
lib/asm/osInvalDCache.s
|
.set noat // allow manual use of $at
.set noreorder // don't insert nops after branches
#include "macros.inc"
.section .text, "ax"
glabel osInvalDCache
blez $a1, .L80323500
nop
li $t3, 8192
sltu $at, $a1, $t3
beqz $at, .L80323508
nop
move $t0, $a0
addu $t1, $a0, $a1
sltu $at, $t0, $t1
beqz $at, .L80323500
nop
#ifdef VERSION_CN
addiu $t1, $t1, -0x10
andi $t2, $t0, 0xf
beqz $t2, .L803234D0
nop
#else
andi $t2, $t0, 0xf
beqz $t2, .L803234D0
addiu $t1, $t1, -0x10
#endif
subu $t0, $t0, $t2
cache 0x15, ($t0)
sltu $at, $t0, $t1
beqz $at, .L80323500
nop
addiu $t0, $t0, 0x10
.L803234D0:
andi $t2, $t1, 0xf
beqz $t2, .L803234F0
nop
subu $t1, $t1, $t2
cache 0x15, 0x10($t1)
sltu $at, $t1, $t0
bnez $at, .L80323500
nop
.L803234F0:
cache 0x11, ($t0)
sltu $at, $t0, $t1
bnez $at, .L803234F0
addiu $t0, $t0, 0x10
.L80323500:
jr $ra
nop
.L80323508:
li $t0, K0BASE
addu $t1, $t0, $t3
addiu $t1, $t1, -0x10
.L80323514:
cache 1, ($t0)
sltu $at, $t0, $t1
bnez $at, .L80323514
addiu $t0, $t0, 0x10
jr $ra
nop
|
96flashbacks/springroll
| 1,959
|
lib/asm/osGetCount.s
|
.set noreorder // don't insert nops after branches
#include "macros.inc"
.section .text, "ax"
#ifdef VERSION_CN
glabel osGetCount
addiu $sp, $sp, -0x38
sd $ra, 0x30($sp)
sd $fp, 0x28($sp)
jal __osDisableInt
move $fp, $sp
sw $v0, 0x24($fp)
mfc0 $a1, $9
sw $a1, 0x20($fp)
lw $v0, 0x20($fp)
lui $v1, %hi(sLastHighestCount) # $v1, 0x8032
lw $v1, %lo(sLastHighestCount)($v1)
sltu $v0, $v0, $v1
beqz $v0, .L80304FCC
nop
lui $v0, %hi(sNumCountOverflows) # $v0, 0x8032
lw $v0, %lo(sNumCountOverflows)($v0)
addiu $v1, $v0, 1
sw $v1, sNumCountOverflows
.L80304FCC:
lw $v0, 0x20($fp)
sw $v0, sLastHighestCount
lui $v0, %hi(sNumCountOverflows) // $v0, 0x8032
lwu $v0, %lo(sNumCountOverflows)($v0)
dsll32 $v1, $v0, 0
lwu $a0, 0x20($fp)
or $v0, $v1, $a0
move $a0, $v0
dsll $v1, $a0, 5
dsubu $v1, $v1, $v0
dsll $a0, $v1, 2
daddu $a0, $a0, $v0
.set noat // gas seems to add an extra mflo $zero after, if we don't manually use $at
li $at, 192
ddivu $zero, $a0, $at
.set at
mflo $v0
dsll32 $v0, $v0, 0
dsra32 $v0, $v0, 0
sw $v0, 0x20($fp)
lw $v0, 0x20($fp)
lui $v1, %hi(sLastHighestCount2) // $v1, 0x8032
lw $v1, %lo(sLastHighestCount2)($v1)
sltu $v0, $v0, $v1
beqz $v0, .L80305044
nop
lui $v0, %hi(sNumCountOverflows2) // $v0, 0x8032
lw $v0, %lo(sNumCountOverflows2)($v0)
addiu $v1, $v0, 1
sw $v1, sNumCountOverflows2
.L80305044:
lw $v0, 0x20($fp)
sw $v0, sLastHighestCount2
jal __osRestoreInt
lw $a0, 0x24($fp)
lw $v1, 0x20($fp)
j .L80305064
move $v0, $v1
.L80305064:
move $sp, $fp
ld $ra, 0x30($sp)
ld $fp, 0x28($sp)
jr $ra
addiu $sp, $sp, 0x38
#else
glabel osGetCount
mfc0 $v0, $9
jr $ra
nop
nop
#endif
|
96flashbacks/springroll
| 1,125
|
lib/asm/guScale.s
|
.set noat
.set noreorder // don't insert nops after branches
#include "macros.inc"
.section .text, "ax"
#ifdef VERSION_CN
.balign 32
glabel guScale
li $at, 0x47800000 // 65536.000000
mtc1 $at, $f4
mtc1 $a1, $f6
mul.s $f8, $f6, $f4
trunc.w.s $f10, $f8
mfc1 $t1, $f10
srl $t2, $t1, 0x10
sll $t0, $t2, 0x10
sw $t0, ($a0)
sll $t2, $t1, 0x10
sw $t2, 0x20($a0)
mtc1 $a2, $f6
mul.s $f8, $f6, $f4
trunc.w.s $f10, $f8
mfc1 $t1, $f10
srl $t0, $t1, 0x10
sw $t0, 8($a0)
andi $t2, $t1, 0xffff
sw $t2, 0x28($a0)
mtc1 $a3, $f6
mul.s $f8, $f6, $f4
trunc.w.s $f10, $f8
mfc1 $t1, $f10
srl $t2, $t1, 0x10
sll $t0, $t2, 0x10
sw $t0, 0x14($a0)
sll $t2, $t1, 0x10
sw $t2, 0x34($a0)
li $t0, 1
sw $t0, 0x1c($a0)
sw $zero, 4($a0)
sw $zero, 0xc($a0)
sw $zero, 0x10($a0)
sw $zero, 0x18($a0)
sw $zero, 0x24($a0)
sw $zero, 0x2c($a0)
sw $zero, 0x30($a0)
sw $zero, 0x38($a0)
jr $ra
sw $zero, 0x3c($a0)
#endif
|
96flashbacks/springroll
| 2,835
|
lib/asm/osSetIntMask.s
|
.set noat // allow manual use of $at
.set noreorder // don't insert nops after branches
#include "macros.inc"
#include <PR/R4300.h>
#include <PR/rcp.h>
#include <PR/os.h>
.section .text, "ax"
glabel osSetIntMask
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
mfc0 $t4, $12
andi $v0, $t4, OS_IM_CPU
lui $t0, %hi(__OSGlobalIntMask) // $t0, 0x8030
addiu $t0, %lo(__OSGlobalIntMask) // addiu $t0, $t0, 0x208c
lw $t3, ($t0)
li $at, 0xFFFFFFFF
xor $t0, $t3, $at
andi $t0, $t0, SR_IMASK
or $v0, $v0, $t0
#else
mfc0 $t1, $12
andi $v0, $t1, OS_IM_CPU
#endif
lui $t2, %hi(PHYS_TO_K1(MI_INTR_MASK_REG)) // $t2, 0xa430
lw $t2, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($t2)
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
beqz $t2, .L80200074
srl $t1, $t3, 0x10
li $at, 0xFFFFFFFF
xor $t1, $t1, $at
andi $t1, $t1, 0x3f
or $t2, $t2, $t1
.L80200074:
#endif
sll $t2, $t2, 0x10
or $v0, $v0, $t2
lui $at, 0x3f
and $t0, $a0, $at
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
and $t0, $t0, $t3
#endif
srl $t0, $t0, 0xf
lui $t2, %hi(__osRcpImTable)
addu $t2, $t2, $t0
lhu $t2, %lo(__osRcpImTable)($t2)
lui $at, %hi(PHYS_TO_K1(MI_INTR_MASK_REG)) // $at, 0xa430
sw $t2, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($at)
andi $t0, $a0, OS_IM_CPU
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
andi $t1, $t3, 0xff00
and $t0, $t0, $t1
#endif
lui $at, (0xFFFF00FF >> 16) // lui $at, 0xffff
ori $at, (0xFFFF00FF & 0xFFFF) // ori $at, $at, 0xff
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
and $t4, $t4, $at
or $t4, $t4, $t0
mtc0 $t4, $12
#else
and $t1, $t1, $at
or $t1, $t1, $t0
mtc0 $t1, $12
#endif
nop
nop
jr $ra
nop
.section .rodata
glabel __osRcpImTable
.half 0x0555
.half 0x0556
.half 0x0559
.half 0x055A
.half 0x0565
.half 0x0566
.half 0x0569
.half 0x056A
.half 0x0595
.half 0x0596
.half 0x0599
.half 0x059A
.half 0x05A5
.half 0x05A6
.half 0x05A9
.half 0x05AA
.half 0x0655
.half 0x0656
.half 0x0659
.half 0x065A
.half 0x0665
.half 0x0666
.half 0x0669
.half 0x066A
.half 0x0695
.half 0x0696
.half 0x0699
.half 0x069A
.half 0x06A5
.half 0x06A6
.half 0x06A9
.half 0x06AA
.half 0x0955
.half 0x0956
.half 0x0959
.half 0x095A
.half 0x0965
.half 0x0966
.half 0x0969
.half 0x096A
.half 0x0995
.half 0x0996
.half 0x0999
.half 0x099A
.half 0x09A5
.half 0x09A6
.half 0x09A9
.half 0x09AA
.half 0x0A55
.half 0x0A56
.half 0x0A59
.half 0x0A5A
.half 0x0A65
.half 0x0A66
.half 0x0A69
.half 0x0A6A
.half 0x0A95
.half 0x0A96
.half 0x0A99
.half 0x0A9A
.half 0x0AA5
.half 0x0AA6
.half 0x0AA9
.half 0x0AAA
|
96flashbacks/springroll
| 1,088
|
lib/asm/__osProbeTLB.s
|
.set noat // allow manual use of $at
.set noreorder // don't insert nops after branches
#include "macros.inc"
.section .text, "ax"
glabel __osProbeTLB
mfc0 $t0, $10
andi $t1, $t0, 0xff
li $at, 0xFFFFE000
and $t2, $a0, $at
or $t1, $t1, $t2
mtc0 $t1, $10
nop
nop
nop
tlbp
nop
nop
mfc0 $t3, $0
lui $at, 0x8000
and $t3, $t3, $at
bnez $t3, .L8032A0D8
nop
tlbr
nop
nop
nop
mfc0 $t3, $5
addi $t3, $t3, 0x2000
srl $t3, $t3, 1
and $t4, $t3, $a0
bnez $t4, .L8032A0A8
addi $t3, $t3, -1
mfc0 $v0, $2
b .L8032A0AC
nop
.L8032A0A8:
mfc0 $v0, $3
.L8032A0AC:
andi $t5, $v0, 2
beqz $t5, .L8032A0D8
nop
lui $at, (0x3FFFFFC0 >> 16) // lui $at, 0x3fff
ori $at, (0x3FFFFFC0 & 0xFFFF) // ori $at, $at, 0xffc0
and $v0, $v0, $at
sll $v0, $v0, 6
and $t5, $a0, $t3
add $v0, $v0, $t5
b .L8032A0DC
nop
.L8032A0D8:
li $v0, -1
.L8032A0DC:
mtc0 $t0, $10
jr $ra
nop
|
96flashbacks/springroll
| 1,420
|
lib/asm/guTranslate.s
|
.set noat
.set noreorder // don't insert nops after branches
#include "macros.inc"
.section .text, "ax"
#ifdef VERSION_CN
.balign 16
glabel guTranslate
li $at, 0x47800000 // 65536.000000
mtc1 $at, $f4
mtc1 $a1, $f6
mul.s $f8, $f6, $f4
trunc.w.s $f10, $f8
mfc1 $t1, $f10
mtc1 $a2, $f6
mul.s $f8, $f6, $f4
trunc.w.s $f10, $f8
mfc1 $t3, $f10
srl $t2, $t1, 0x10
sll $t0, $t2, 0x10
srl $t2, $t3, 0x10
or $t0, $t0, $t2
sw $t0, 0x18($a0)
sll $t0, $t1, 0x10
sll $t2, $t3, 0x10
srl $t2, $t2, 0x10
or $t0, $t0, $t2
sw $t0, 0x38($a0)
mtc1 $a3, $f6
mul.s $f8, $f6, $f4
trunc.w.s $f10, $f8
mfc1 $t1, $f10
srl $t2, $t1, 0x10
sll $t0, $t2, 0x10
addiu $t0, $t0, 1
sw $t0, 0x1c($a0)
sll $t2, $t1, 0x10
sw $t2, 0x3c($a0)
sw $zero, ($a0)
sw $zero, 4($a0)
sw $zero, 8($a0)
sw $zero, 0xc($a0)
sw $zero, 0x10($a0)
sw $zero, 0x14($a0)
sw $zero, 0x20($a0)
sw $zero, 0x24($a0)
sw $zero, 0x28($a0)
sw $zero, 0x2c($a0)
sw $zero, 0x30($a0)
sw $zero, 0x34($a0)
lui $t0, 1
ori $t0, $t0, 0
sw $t0, ($a0)
sw $t0, 0x14($a0)
lui $t0, (0x00000001 >> 16) # lui $t0, 0
ori $t0, (0x00000001 & 0xFFFF) # ori $t0, $t0, 1
jr $ra
sw $t0, 8($a0)
#endif
|
96flashbacks/springroll
| 2,544
|
lib/asm/llmuldiv_gcc.s
|
// assembler directives
.set noat // allow manual use of $at
.set noreorder // don't insert nops after branches
#include "macros.inc"
#ifndef VERSION_CN
.section .text, "ax"
/* -------------------------------------------------------------------------------------- */
/* need to asm these functions because lib32gcc-7-dev-mips-cross does not exist so we */
/* cannot naturally link a libgcc variant for this target given this architecture and */
/* compiler. Until we have a good workaround with a gcc target that doesn't involve */
/* assuming a 32-bit to 64-bit change, we have to encode these functions as raw assembly */
/* for it to compile. */
/* -------------------------------------------------------------------------------------- */
/* TODO: Is there a non-insane way to fix this hack that doesn't involve the user compiling */
/* a library themselves? */
glabel __umoddi3
sw $a0, ($sp)
sw $a1, 4($sp)
sw $a2, 8($sp)
sw $a3, 0xc($sp)
ld $t7, 8($sp)
ld $t6, ($sp)
ddivu $zero, $t6, $t7
bnez $t7, .L80324144
nop
break 7
.L80324144:
mfhi $v0
dsll32 $v1, $v0, 0
dsra32 $v1, $v1, 0
jr $ra
dsra32 $v0, $v0, 0
glabel __udivdi3
sw $a0, ($sp)
sw $a1, 4($sp)
sw $a2, 8($sp)
sw $a3, 0xc($sp)
ld $t7, 8($sp)
ld $t6, ($sp)
ddivu $zero, $t6, $t7
bnez $t7, .L80324180
nop
break 7
.L80324180:
mflo $v0
dsll32 $v1, $v0, 0
dsra32 $v1, $v1, 0
jr $ra
dsra32 $v0, $v0, 0
glabel __moddi3
sw $a0, ($sp)
sw $a1, 4($sp)
sw $a2, 8($sp)
sw $a3, 0xc($sp)
ld $t7, 8($sp)
ld $t6, ($sp)
ddivu $zero, $t6, $t7
bnez $t7, .L803241E8
nop
break 7
.L803241E8:
mfhi $v0
dsll32 $v1, $v0, 0
dsra32 $v1, $v1, 0
jr $ra
dsra32 $v0, $v0, 0
glabel __divdi3
sw $a0, ($sp)
sw $a1, 4($sp)
sw $a2, 8($sp)
sw $a3, 0xc($sp)
ld $t7, 8($sp)
ld $t6, ($sp)
ddiv $zero, $t6, $t7
nop
bnez $t7, .L80324228
nop
break 7
.L80324228:
daddiu $at, $zero, -1
bne $t7, $at, .L80324244
daddiu $at, $zero, 1
dsll32 $at, $at, 0x1f
bne $t6, $at, .L80324244
nop
break 6
.L80324244:
mflo $v0
dsll32 $v1, $v0, 0
dsra32 $v1, $v1, 0
jr $ra
dsra32 $v0, $v0, 0
#endif
|
96flashbacks/springroll
| 1,146
|
lib/asm/osMapTLB.s
|
.set noreorder // don't insert nops after branches
#include "macros.inc"
.section .text, "ax"
// This file is handwritten
// void osMapTLB(s32 index, OSPageMask pm, void *vaddr, u32 evenpaddr, u32 oddpaddr, s32 asid);
glabel osMapTLB
mfc0 $t0, $10
mtc0 $a0, $0
mtc0 $a1, $5
lw $t1, 0x14($sp) #asid
beq $t1, -1, .L803214D8
li $t4, 1
li $t2, 30
b .L803214DC
or $a2, $a2, $t1 #vaddr
.L803214D8:
li $t2, 31
.L803214DC:
mtc0 $a2, $10 #vaddr
beq $a3, -1, .L80321500 #even paddr
nop
srl $t3, $a3, 6 #evenpaddr
or $t3, $t3, $t2
mtc0 $t3, $2
b .L80321504
nop
.L80321500:
mtc0 $t4, $2
.L80321504:
lw $t3, 0x10($sp) #oddpaddr
beq $t3, -1, .L80321528
nop
srl $t3, $t3, 6
or $t3, $t3, $t2
mtc0 $t3, $3
b .L80321540
nop
.L80321528:
mtc0 $t4, $3
bne $a3, -1, .L80321540 #evenpaddr
nop
lui $t3, 0x8000
mtc0 $t3, $10
.L80321540:
nop
tlbwi
nop
nop
nop
nop
mtc0 $t0, $10
jr $ra
nop #file gets padded but
nop
nop
nop
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_ds18b20/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_ds18b20/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_ds18b20/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_ds18b20/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_ds18b20/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_ds18b20/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_ds18b20/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_ds18b20/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_spi_hard_dma_ssd1306/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_spi_hard_dma_ssd1306/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_spi_hard_dma_ssd1306/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_spi_hard_dma_ssd1306/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_spi_hard_dma_ssd1306/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_spi_hard_dma_ssd1306/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_spi_hard_dma_ssd1306/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_spi_hard_dma_ssd1306/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
96flashbacks/96flashbacks
| 152,035
|
sound/sequences/00_sound_player.s
|
.include "seq_macros.inc"
.section .rodata
.align 0
sequence_start:
seq_setmutebhv 0x60
seq_setmutescale 0
seq_setvol 127
seq_settempo 120
seq_initchannels 0x3ff
seq_startchannel 0, .channel0
seq_startchannel 1, .channel1
seq_startchannel 2, .channel2
seq_startchannel 3, .channel38
seq_startchannel 4, .channel4
seq_startchannel 5, .channel59
seq_startchannel 6, .channel6
seq_startchannel 7, .channel7
seq_startchannel 8, .channel38
seq_startchannel 9, .channel59
.seq_loop:
seq_delay 20000
seq_jump .seq_loop
.channel0:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel0_table
chan_jump .main_loop_023589
.channel2:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel2_table
chan_jump .main_loop_023589
.channel38:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel38_table
chan_jump .main_loop_023589
.channel59:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel59_table
chan_jump .main_loop_023589
# Main loop for standard, non-continuous sound effects
.main_loop_023589:
chan_delay1
chan_ioreadval 0
chan_bltz .main_loop_023589
.start_playing_023589:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_setval 0
chan_iowriteval 5
chan_ioreadval 4
chan_dyncall
# keep looping until layer 0 finishes or we are told to stop or to play something else
.poll_023589:
chan_delay1
chan_ioreadval 0
chan_bltz .skip_023589 # if we have a signal:
chan_beqz .force_stop_023589 # told to stop
chan_jump .start_playing_023589 # told to play something else
.skip_023589:
chan_testlayerfinished 0
chan_beqz .poll_023589 # if layer 0 hasn't finished, keep polling
chan_jump .main_loop_023589 # otherwise go back to the main loop
.force_stop_023589:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_jump .main_loop_023589
.channel1:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_setmutebhv 0x20
chan_stereoheadseteffects 1
chan_setdyntable .channel1_table
chan_jump .main_loop_146
.channel4:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_setmutebhv 0x20
chan_stereoheadseteffects 1
chan_setdyntable .channel4_table
chan_jump .main_loop_146
.channel6:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_setmutebhv 0x20
chan_stereoheadseteffects 1
chan_setdyntable .channel6_table
chan_jump .main_loop_146
# Main loop for moving, env and air sound effects, which play continuously
.main_loop_146:
chan_delay1
chan_ioreadval 0
chan_bltz .main_loop_146
.start_playing_146:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_setvolscale 127
chan_setval 0
chan_iowriteval 5
chan_ioreadval 4
chan_dyncall
# keep looping until we are told to stop or to play something else
.poll_146:
chan_delay1
chan_ioreadval 0
chan_bltz .poll_146
chan_beqz .force_stop_146
chan_jump .start_playing_146
.force_stop_146:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_jump .main_loop_146
.channel7:
chan_largenoteson
chan_setinstr 0
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel7_table
# Loop for menu sound effects
.main_loop_7:
chan_delay1
chan_ioreadval 0
chan_bltz .main_loop_7
.start_playing_7:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_setval 0
chan_iowriteval 5
chan_setreverb 0
chan_setpan 64
chan_setpanmix 127
chan_ioreadval 4
chan_dyncall
# keep looping until layer 0 finishes or we are told to stop or to play something else
.poll_7:
chan_delay1
chan_ioreadval 0
chan_bltz .skip_7 # if we have a signal:
chan_beqz .force_stop_7 # told to stop
chan_unreservenotes
chan_jump .start_playing_7 # told to play something else
.skip_7:
chan_testlayerfinished 0
chan_beqz .poll_7 # if layer 0 hasn't finished, keep polling
chan_unreservenotes
chan_jump .main_loop_7 # otherwise go back to the main loop
.force_stop_7:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_unreservenotes
chan_jump .main_loop_7
# Delay for a number of ticks (1-255) in an interruptible manner.
.delay:
chan_writeseq_nextinstr 0, 1
chan_loop 20
chan_delay1
chan_ioreadval 0
chan_iowriteval 1
chan_bgez .delay_interrupt
chan_loopend
chan_end
.delay_interrupt:
chan_setpanmix 127
chan_setvolscale 127
chan_setvibratoextent 0
chan_ioreadval 1 # IO slots 0-3 are reset to -1 when read; restore the value
chan_iowriteval 0
chan_break # break out of the loop
chan_break # force the caller to return immediately
chan_end
# Set reverb in way that takes area echo level and volume into account. This
# is done by writing to IO slot 5 and letting get_sound_reverb in external.c
# do the necessary math.
.set_reverb:
chan_writeseq_nextinstr 0, 1
chan_setreverb 10
chan_iowriteval 5
chan_end
.channel0_table:
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_grass
sound_ref .sound_action_jump_water
sound_ref .sound_action_jump_stone
sound_ref .sound_action_jump_spooky
sound_ref .sound_action_jump_snow
sound_ref .sound_action_jump_ice
sound_ref .sound_action_jump_sand
sound_ref .sound_action_landing_default
sound_ref .sound_action_landing_grass
sound_ref .sound_action_landing_water
sound_ref .sound_action_landing_stone
sound_ref .sound_action_landing_spooky
sound_ref .sound_action_landing_snow
sound_ref .sound_action_landing_ice
sound_ref .sound_action_landing_sand
sound_ref .sound_action_step_default
sound_ref .sound_action_step_grass
sound_ref .sound_action_step_water
sound_ref .sound_action_step_stone
sound_ref .sound_action_step_spooky
sound_ref .sound_action_step_snow
sound_ref .sound_action_step_ice
sound_ref .sound_action_step_sand
sound_ref .sound_action_body_hit_ground_default
sound_ref .sound_action_body_hit_ground_grass
sound_ref .sound_action_body_hit_ground_water
sound_ref .sound_action_body_hit_ground_stone
sound_ref .sound_action_body_hit_ground_spooky
sound_ref .sound_action_body_hit_ground_snow
sound_ref .sound_action_body_hit_ground_ice
sound_ref .sound_action_body_hit_ground_sand
sound_ref .sound_action_step_tiptoe_default
sound_ref .sound_action_step_tiptoe_grass
sound_ref .sound_action_step_tiptoe_water
sound_ref .sound_action_step_tiptoe_stone
sound_ref .sound_action_step_tiptoe_spooky
sound_ref .sound_action_step_tiptoe_snow
sound_ref .sound_action_step_tiptoe_ice
sound_ref .sound_action_step_tiptoe_sand
sound_ref .sound_action_metal_jump
sound_ref .sound_action_metal_landing
sound_ref .sound_action_metal_step
sound_ref .sound_action_metal_heavy_landing
sound_ref .sound_action_clap_hands_cold
sound_ref .sound_action_hanging_step
sound_ref .sound_action_quicksand_step
sound_ref .sound_action_metal_step_tiptoe
sound_ref .chan_4E5
sound_ref .chan_4F1
sound_ref .chan_4FD
sound_ref .sound_action_swim
sound_ref .chan_522
sound_ref .sound_action_throw
sound_ref .sound_action_key_swish
sound_ref .sound_action_spin
sound_ref .sound_action_spin
sound_ref .sound_action_spin
sound_ref .sound_action_climb_up_tree
sound_ref .sound_action_climb_down_tree
sound_ref .chan_582
sound_ref .chan_591
sound_ref .chan_5A3
sound_ref .sound_action_pat_back
sound_ref .sound_action_brush_hair
sound_ref .sound_action_climb_up_pole
sound_ref .sound_action_metal_bonk
sound_ref .sound_action_unstuck_from_ground
sound_ref .sound_action_hit
sound_ref .sound_action_bonk
sound_ref .sound_action_enter_bbh
sound_ref .sound_action_swim_fast
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_snow
sound_ref .sound_action_stuck_in_ground_sand
sound_ref .sound_action_stuck_in_ground_sand
sound_ref .sound_action_metal_jump_water
sound_ref .sound_action_metal_land_water
sound_ref .sound_action_metal_step_water
sound_ref .chan_731
sound_ref .chan_743
sound_ref .chan_756
sound_ref .sound_action_flying_fast
sound_ref .sound_action_teleport
sound_ref .chan_7A5
sound_ref .sound_action_bounce_off_object
sound_ref .chan_7ED
sound_ref .sound_action_read_sign
sound_ref .chan_810
.ifdef VERSION_JP
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
.else
sound_ref .chan_828
sound_ref .sound_action_intro_unk45e
sound_ref .sound_action_intro_unk45f
.endif
sound_ref .sound_action_heavy_landing_default
sound_ref .sound_action_heavy_landing_grass
sound_ref .sound_action_heavy_landing_water
sound_ref .sound_action_heavy_landing_stone
sound_ref .sound_action_heavy_landing_spooky
sound_ref .sound_action_heavy_landing_snow
sound_ref .sound_action_heavy_landing_ice
sound_ref .sound_action_heavy_landing_sand
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
.sound_action_jump_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_234
chan_end
.layer_234:
layer_note1 41, 0xc, 117
layer_note1 46, 0x18, 117
layer_end
.sound_action_jump_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_243
chan_end
.layer_243:
layer_note1 41, 0xc, 120
layer_note1 50, 0x18, 120
layer_end
.sound_action_jump_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_252
chan_end
.layer_252:
layer_note1 41, 0x6, 80
layer_note1 50, 0x18, 80
layer_end
.sound_action_jump_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_261
chan_end
.layer_261:
layer_note1 41, 0xc, 127
layer_note1 50, 0x18, 127
layer_end
.sound_action_jump_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_270
chan_end
.layer_270:
layer_note1 41, 0xc, 90
layer_note1 50, 0x18, 90
layer_end
.sound_action_jump_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_27F
chan_end
.layer_27F:
layer_note1 41, 0xc, 80
layer_note1 50, 0x18, 80
layer_end
.sound_action_jump_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_28E
chan_end
.layer_28E:
layer_note1 29, 0xc, 127
layer_note1 38, 0x18, 127
layer_end
.sound_action_jump_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_29D
chan_end
.layer_29D:
layer_note0 34, 0xc, 100, 127
layer_note0 43, 0x24, 100, 127
layer_end
.sound_action_landing_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_2AE
chan_end
.layer_2AE:
layer_note1 46, 0xc, 117
layer_note1 41, 0x18, 117
layer_end
.sound_action_landing_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_2BD
chan_end
.layer_2BD:
layer_note1 50, 0xc, 120
layer_note1 41, 0x18, 120
layer_end
.sound_action_landing_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_2CC
chan_end
.layer_2CC:
layer_note1 50, 0xc, 80
layer_note1 41, 0x18, 80
layer_end
.sound_action_landing_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_2DB
chan_end
.layer_2DB:
layer_note1 50, 0xc, 127
layer_note1 41, 0x18, 127
layer_end
.sound_action_landing_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_2EA
chan_end
.layer_2EA:
layer_note1 50, 0xc, 90
layer_note1 41, 0x18, 90
layer_end
.sound_action_landing_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_2F9
chan_end
.layer_2F9:
layer_note1 50, 0xc, 80
layer_note1 41, 0x18, 80
layer_end
.sound_action_landing_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_308
chan_end
.layer_308:
layer_note1 38, 0xc, 127
layer_note1 29, 0x18, 127
layer_end
.sound_action_landing_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_317
chan_end
.layer_317:
layer_note0 43, 0xc, 100, 127
layer_note0 34, 0x24, 100, 127
layer_end
.sound_action_step_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_328
chan_end
.layer_328:
layer_note1 39, 0x18, 100
layer_end
.sound_action_step_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_334
chan_end
.layer_334:
layer_note1 39, 0x18, 100
layer_end
.sound_action_step_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_340
chan_end
.layer_340:
layer_note1 43, 0x18, 63
layer_end
.sound_action_step_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_34C
chan_end
.layer_34C:
layer_note1 39, 0x18, 100
layer_end
.sound_action_step_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_358
chan_end
.layer_358:
layer_note1 39, 0x18, 100
layer_end
.sound_action_step_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_364
chan_end
.layer_364:
layer_note1 39, 0x18, 100
layer_end
.sound_action_step_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_370
chan_end
.layer_370:
layer_note1 39, 0x18, 100
layer_end
.sound_action_step_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_37C
chan_end
.layer_37C:
layer_note1 39, 0x18, 100
layer_end
.sound_action_body_hit_ground_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_388
chan_end
.layer_388:
layer_note1 17, 0xc, 117
layer_note1 19, 0x18, 117
layer_end
.sound_action_body_hit_ground_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_397
chan_end
.layer_397:
layer_note1 29, 0xc, 120
layer_note1 31, 0x18, 120
layer_end
.sound_action_body_hit_ground_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_3A6
chan_end
.layer_3A6:
layer_note1 34, 0xc, 80
layer_note1 39, 0x18, 80
layer_end
.sound_action_body_hit_ground_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_3B5
chan_end
.layer_3B5:
layer_note1 29, 0xc, 115
layer_note1 31, 0xc, 115
layer_end
.sound_action_body_hit_ground_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_3C4
chan_end
.layer_3C4:
layer_note1 29, 0xc, 90
layer_note1 31, 0x18, 90
layer_end
.sound_action_body_hit_ground_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_3D3
chan_end
.layer_3D3:
layer_note1 34, 0xc, 80
layer_note1 36, 0x18, 80
layer_end
.sound_action_body_hit_ground_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_3E2
chan_end
.layer_3E2:
layer_note1 29, 0xc, 127
layer_note1 31, 0x18, 127
layer_end
.sound_action_body_hit_ground_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_3F1
chan_end
.layer_3F1:
layer_note0 31, 0xc, 100, 127
layer_note0 32, 0x24, 100, 127
layer_end
.sound_action_step_tiptoe_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_402
chan_end
.layer_402:
layer_note1 37, 0x18, 63
layer_end
.sound_action_step_tiptoe_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_40E
chan_end
.layer_40E:
layer_note1 37, 0x18, 57
layer_end
.sound_action_step_tiptoe_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_41A
chan_end
.layer_41A:
layer_note1 39, 0x18, 39
layer_end
.sound_action_step_tiptoe_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_426
chan_end
.layer_426:
layer_note1 37, 0x18, 49
layer_end
.sound_action_step_tiptoe_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_432
chan_end
.layer_432:
layer_note1 37, 0x18, 39
layer_end
.sound_action_step_tiptoe_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_43E
chan_end
.layer_43E:
layer_note1 37, 0x18, 39
layer_end
.sound_action_step_tiptoe_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_44A
chan_end
.layer_44A:
layer_note1 37, 0x18, 70
layer_end
.sound_action_step_tiptoe_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_456
chan_end
.layer_456:
layer_note1 35, 0x18, 49
layer_end
.sound_action_metal_jump:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_462
chan_end
.layer_462:
layer_note1 29, 0xc, 100
layer_note1 38, 0x12, 100
layer_end
.sound_action_metal_landing:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_471
chan_end
.layer_471:
layer_note1 38, 0xc, 100
layer_note1 29, 0x18, 100
layer_end
.sound_action_metal_step:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_480
chan_end
.layer_480:
layer_portamento 0x85, 27, 255
layer_note1 31, 0x10, 100
layer_end
.sound_action_metal_heavy_landing:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_490
chan_end
.layer_490:
layer_note1 20, 0xc, 100
layer_note1 24, 0x18, 100
layer_end
.sound_action_clap_hands_cold:
chan_setbank 3
chan_setinstr 6
chan_setenvelope .envelope_3304
chan_setlayer 0, .layer_4A2
chan_end
.layer_4A2:
layer_note1 62, 0x6, 90
layer_note1 58, 0x7, 90
layer_end
.sound_action_hanging_step:
chan_setbank 0
chan_setinstr 2
chan_setlayer 0, .layer_4BD
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_end
.layer_4BD:
layer_note1 62, 0x4, 127
layer_note0 56, 0x3, 127, 80
layer_end
.sound_action_quicksand_step:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_4CD
chan_end
.layer_4CD:
layer_portamento 0x1, 29, 0x12
layer_note1 24, 0x12, 115
layer_end
.sound_action_metal_step_tiptoe:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_4DD
chan_end
.layer_4DD:
layer_portamento 0x85, 25, 255
layer_note1 29, 0x10, 70
layer_end
.chan_4E5:
chan_setbank 2
chan_setinstr 0
chan_setlayer 0, .layer_4ED
chan_end
.layer_4ED:
layer_note1 39, 0x7f, 100
layer_end
.chan_4F1:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_4F9
chan_end
.layer_4F9:
layer_note1 36, 0x64, 90
layer_end
.chan_4FD:
chan_setbank 2
chan_setlayer 0, .layer_503
chan_end
.layer_503:
layer_setinstr 2
layer_note1 36, 0xa, 80
layer_setinstr 0
layer_portamento 0x81, 36, 255
layer_note1 50, 0x32, 80
layer_end
.sound_action_swim:
chan_setbank 2
chan_setinstr 2
chan_setlayer 0, .layer_51A
chan_end
.layer_51A:
layer_portamento 0x81, 35, 255
layer_note1 30, 0x3c, 110
layer_end
.chan_522:
chan_setbank 2
chan_setinstr 2
chan_setlayer 0, .layer_52A
chan_end
.layer_52A:
layer_note1 39, 0x7f, 115
layer_end
.sound_action_throw:
chan_setbank 0
chan_setinstr 0
chan_setlayer 0, .layer_538
chan_end
.layer_536:
layer_transpose 1
.layer_538:
layer_portamento 0x81, 46, 255
layer_note1 31, 0xf, 100
layer_end
.sound_action_key_swish:
chan_setbank 0
chan_setinstr 0
chan_setlayer 0, .layer_548
chan_end
.layer_548:
layer_note1 39, 0x12, 100
layer_end
.sound_action_spin:
chan_setbank 0
chan_setinstr 0
chan_setlayer 0, .layer_556
chan_end
.layer_556:
layer_note1 39, 0x12, 100
layer_end
.sound_action_climb_up_tree:
chan_setbank 0
chan_setinstr 1
chan_setlayer 0, .layer_566
chan_end
.layer_566:
layer_note1 37, 0xa, 105
layer_portamento 0x81, 42, 255
layer_note1 37, 0x1e, 105
layer_end
.sound_action_climb_down_tree: # unused
chan_setbank 0
chan_setinstr 1
chan_setlayer 0, .layer_579
chan_end
.layer_579:
layer_portamento 0x81, 44, 255
layer_note1 40, 0xb4, 100
layer_end
.chan_582: # unused
chan_setbank 0
chan_setinstr 2
chan_setlayer 0, .layer_58A
chan_end
.layer_58A:
layer_note1 39, 0x4, 127
layer_note1 41, 0x12, 127
layer_end
.chan_591:
chan_setbank 1
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_59C
chan_end
.layer_59C:
layer_note1 38, 0x6, 127
layer_note1 41, 0x6, 127
layer_end
.chan_5A3:
chan_setbank 1
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_5AE
chan_end
.layer_5AE:
layer_note1 41, 0x6, 127
layer_note1 38, 0x6, 127
layer_end
.sound_action_pat_back:
chan_setbank 0
chan_setinstr 2
chan_setlayer 0, .layer_5BD
chan_end
.layer_5BD:
layer_note1 32, 0xa, 127
layer_end
.sound_action_brush_hair:
chan_setbank 0
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_5CC
chan_end
.layer_5CC:
layer_note1 39, 0x8, 90
layer_note1 41, 0x8, 90
layer_end
.sound_action_climb_up_pole:
chan_setbank 3
chan_setinstr 1
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_5DE
chan_end
.layer_5DE:
layer_portamento 0x85, 53, 255
layer_note1 55, 0xc, 127
layer_note1 53, 0x18, 127
layer_end
.sound_action_metal_bonk:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_5F1
chan_end
.layer_5F1:
layer_note1 39, 0x7, 100
layer_note1 20, 0x18, 115
layer_end
.sound_action_unstuck_from_ground:
chan_setbank 0
chan_setinstr 4
chan_setlayer 0, .layer_600
chan_end
.layer_600:
layer_note1 37, 0x48, 127
layer_end
.sound_action_hit:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_618
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_3314
chan_end
.layer_618:
layer_portamento 0x81, 27, 255
layer_note1 46, 0xb, 127
.layer_61F:
layer_somethingon
layer_portamento 0x85, 32, 255
layer_note1 44, 0x5, 100
layer_call .layer_fn_64A
layer_transpose 1
layer_call .layer_fn_64A
layer_transpose 3
layer_call .layer_fn_64A
layer_transpose 4
layer_call .layer_fn_64A
layer_transpose 6
layer_call .layer_fn_64A
layer_transpose 7
layer_call .layer_fn_64A
layer_transpose 9
layer_call .layer_fn_64A
layer_transpose 10
.layer_fn_64A:
layer_note1 20, 0x5, 115
layer_note1 32, 0x5, 115
layer_end
.sound_action_bonk:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_659
chan_end
.layer_659:
layer_portamento 0x82, 19, 255
layer_note1 34, 0x5, 110
layer_note1 39, 0x2, 110
layer_end
.sound_action_enter_bbh:
chan_setbank 3
chan_setinstr 3
chan_setval 50
chan_call .set_reverb
chan_setenvelope .envelope_3324
chan_setlayer 0, .layer_68F
chan_delay 1
chan_setlayer 1, .layer_6A1
chan_setbank 9
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_setdecayrelease 20
chan_delay 1
chan_setlayer 2, .layer_699
chan_setbank 4
chan_setinstr 14
chan_setdecayrelease 12
chan_setvibratoextent 10
chan_end
.layer_68F:
layer_transpose 36
layer_portamento 0x81, 62, 255
layer_note1 38, 0x7f, 127
layer_end
.layer_699:
layer_portamento 0x81, 39, 255
layer_note1 15, 0x7f, 127
layer_end
.layer_6A1:
layer_portamento 0x81, 62, 255
layer_note1 38, 0x7f, 100
layer_end
.sound_action_swim_fast:
chan_setbank 2
chan_setinstr 2
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_6C1
chan_setlayer 1, .layer_6B9
chan_end
.layer_6B9:
layer_portamento 0x81, 23, 255
layer_note1 59, 0x30, 120
layer_end
.layer_6C1:
layer_portamento 0x81, 35, 255
layer_note1 42, 0x3c, 110
layer_end
.sound_action_stuck_in_ground_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_6D1
chan_end
.layer_6D1:
layer_note1 17, 0x6, 127
layer_portamento 0x81, 31, 255
layer_note1 7, 0xc, 127
layer_end
.sound_action_stuck_in_ground_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_6E4
chan_end
.layer_6E4:
layer_note1 23, 0x6, 127
layer_note1 25, 0xc, 127
layer_end
.sound_action_stuck_in_ground_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_6F3
chan_end
.layer_6F3:
layer_note1 17, 0x6, 127
layer_note1 19, 0xc, 127
layer_end
.sound_action_metal_jump_water:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_705
chan_end
.layer_705:
layer_note1 20, 0xf, 90
layer_note1 29, 0x17, 90
layer_end
.sound_action_metal_land_water:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_717
chan_end
.layer_717:
layer_note1 29, 0xf, 90
layer_note1 20, 0x1f, 90
layer_end
.sound_action_metal_step_water:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_729
chan_end
.layer_729:
layer_portamento 0x85, 18, 255
layer_note1 22, 0x15, 90
layer_end
.chan_731:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_73C
chan_end
.layer_73C:
layer_note1 11, 0xf, 90
layer_note1 15, 0x1f, 90
layer_end
.chan_743:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_74E
chan_end
.layer_74E:
layer_portamento 0x85, 18, 255
layer_note1 22, 0x10, 90
layer_end
.chan_756:
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_761
chan_end
.layer_761:
layer_transpose 8
layer_jump .layer_61F
.sound_action_flying_fast:
chan_setbank 5
chan_setinstr 6
chan_setenvelope .envelope_33AC
chan_setlayer 0, .layer_774
chan_setlayer 1, .layer_776
chan_end
.layer_774:
layer_transpose 12
.layer_776:
layer_somethingon
layer_portamento 0x85, 27, 255
layer_note1 51, 0x14, 127
layer_note1 36, 0x5a, 127
layer_end
.sound_action_teleport:
chan_setbank 9
chan_setinstr 3
chan_setvibratoextent 60
chan_setvibratorate 60
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_79D
chan_setlayer 1, .layer_79B
chan_setval 36
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_79B:
layer_transpose 1
.layer_79D:
layer_portamento 0x81, 20, 100
layer_note1 27, 0x30, 127
layer_end
.chan_7A5:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_7B9
chan_setval 4
chan_call .delay
chan_setbank 9
chan_setinstr 3
chan_end
.layer_7B9:
layer_note1 43, 0x3, 115
layer_note1 48, 0x5, 115
layer_transpose 12
layer_note1 55, 0x6, 80
layer_end
.sound_action_bounce_off_object:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_7D9
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_3314
chan_end
.layer_7D9:
layer_portamento 0x81, 27, 255
layer_note1 41, 0xb, 127
layer_somethingon
layer_transpose 252
layer_portamento 0x85, 32, 255
layer_note1 44, 0x5, 100
layer_jump .layer_fn_64A
.chan_7ED:
chan_setbank 0
chan_setinstr 3
chan_setdecayrelease 30
chan_setlayer 0, .layer_7F7
chan_end
.layer_7F7:
layer_setinstr 0
layer_portamento 0x81, 32, 255
layer_note1 39, 0x24, 127
layer_end
.sound_action_read_sign:
chan_jump .sound_menu_read_sign
.heavy_landing_common:
chan_setbank 0
chan_setinstr 5
chan_setlayer 0, .layer_80C
chan_end
.layer_80C:
layer_note1 41, 0x3c, 127
layer_end
.chan_810:
chan_setbank 1
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_81B
chan_end
.layer_81B:
layer_note1 38, 0x8, 127
layer_note1 41, 0x9, 127
layer_note1 39, 0xa, 127
layer_note1 42, 0x8, 127
layer_end
.ifndef VERSION_JP
.chan_828: # unused
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_83C
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_3314
chan_end
.layer_83C:
layer_portamento 0x81, 27, 255
layer_note1 46, 0x7, 127
layer_portamento 0x85, 3, 255
layer_note1 39, 0xf, 100
layer_end
.sound_action_intro_unk45e:
chan_setbank 5
chan_setinstr 6
chan_setenvelope .envelope_33AC
chan_setlayer 0, .layer_859
chan_setlayer 1, .layer_85B
chan_end
.layer_859:
layer_transpose 12
.layer_85B:
layer_portamento 0x85, 26, 240
layer_note1 51, 0x53, 127
layer_end
.sound_action_intro_unk45f:
chan_setbank 5
chan_setinstr 6
chan_setenvelope .envelope_33AC
chan_setlayer 0, .layer_871
chan_setlayer 1, .layer_776
chan_end
.layer_871:
layer_transpose 8
layer_jump .layer_776
.endif
.sound_action_heavy_landing_default:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 0
chan_setlayer 1, .layer_388
chan_end
.sound_action_heavy_landing_grass:
chan_jump .sound_action_heavy_landing_stone
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 1
chan_setlayer 1, .layer_397
chan_end
.sound_action_heavy_landing_water:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 2
chan_setinstr 1
chan_setlayer 1, .layer_3A6
chan_end
.sound_action_heavy_landing_stone:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 3
chan_setlayer 1, .layer_3B5
chan_end
.sound_action_heavy_landing_spooky:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 4
chan_setlayer 1, .layer_3C4
chan_end
.sound_action_heavy_landing_snow:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 5
chan_setlayer 1, .layer_3D3
chan_end
.sound_action_heavy_landing_ice:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 6
chan_setlayer 1, .layer_3E2
chan_end
.sound_action_heavy_landing_sand:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 8
chan_setlayer 1, .layer_3F1
chan_end
.channel1_table:
sound_ref .sound_moving_slide_default
sound_ref .sound_moving_slide_grass
sound_ref .sound_moving_slide_water
sound_ref .sound_moving_slide_stone
sound_ref .sound_moving_slide_spooky
sound_ref .sound_moving_slide_snow
sound_ref .sound_moving_slide_ice
sound_ref .sound_moving_slide_sand
sound_ref .sound_moving_slide_default
sound_ref .sound_moving_slide_grass
sound_ref .sound_moving_slide_water
sound_ref .sound_moving_slide_stone
sound_ref .sound_moving_slide_spooky
sound_ref .sound_moving_slide_snow
sound_ref .sound_moving_slide_ice
sound_ref .sound_moving_slide_sand
sound_ref .sound_moving_lava_burn
sound_ref .sound_moving_slide_down_pole
sound_ref .sound_moving_slide_down_tree
sound_ref .sound_general_coin
sound_ref .sound_moving_quicksand_death
sound_ref .sound_general_coin
sound_ref .sound_moving_shocked
sound_ref .sound_moving_flying
sound_ref .sound_moving_almost_drowning
sound_ref .sound_moving_aim_cannon
sound_ref .chan_AC3
sound_ref .sound_moving_slide_stone
sound_ref .sound_moving_slide_spooky
sound_ref .sound_moving_slide_snow
sound_ref .sound_moving_slide_ice
sound_ref .sound_moving_slide_sand
sound_ref .sound_moving_riding_shell_default
sound_ref .sound_moving_riding_shell_grass
sound_ref .sound_moving_riding_shell_water
sound_ref .sound_moving_riding_shell_stone
sound_ref .sound_moving_riding_shell_spooky
sound_ref .sound_moving_riding_shell_snow
sound_ref .sound_moving_riding_shell_ice
sound_ref .sound_moving_riding_shell_sand
sound_ref .sound_moving_riding_shell_lava
sound_ref .sound_moving_riding_shell_grass
sound_ref .sound_moving_riding_shell_water
sound_ref .sound_moving_riding_shell_stone
sound_ref .sound_moving_riding_shell_spooky
sound_ref .sound_moving_riding_shell_snow
sound_ref .sound_moving_riding_shell_ice
sound_ref .sound_moving_riding_shell_sand
sound_ref .sound_moving_riding_shell_default
sound_ref .sound_moving_riding_shell_grass
sound_ref .sound_moving_riding_shell_water
sound_ref .sound_moving_riding_shell_stone
sound_ref .sound_moving_riding_shell_spooky
sound_ref .sound_moving_riding_shell_snow
sound_ref .sound_moving_riding_shell_ice
sound_ref .sound_moving_riding_shell_sand
.sound_moving_slide_default:
chan_setbank 3
chan_setinstr 0
chan_setlayer 0, .layer_96E
chan_end
.layer_96E:
layer_somethingon
.layer_96F:
layer_note1 39, 0x12c, 80
layer_jump .layer_96F
layer_end
.sound_moving_slide_grass:
chan_jump .sound_moving_slide_stone
chan_setinstr 1
chan_setlayer 0, .layer_988
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 1
chan_end
.layer_988:
layer_note1 41, 0x8, 105
layer_somethingon
.layer_98C:
layer_note1 39, 0x12c, 70
layer_jump .layer_98C
layer_end
.sound_moving_slide_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_9A8
chan_setlayer 1, .layer_9B3
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 2
chan_end
.layer_9A8:
layer_delay 1
layer_somethingon
.layer_9AB:
layer_note1 39, 0x12c, 88
layer_jump .layer_9AB
layer_end
.layer_9B3:
layer_portamento 0x81, 39, 255
layer_note1 48, 0x32, 80
layer_end
.sound_moving_slide_stone:
chan_setbank 3
chan_setinstr 3
chan_setlayer 0, .layer_9C3
chan_end
.layer_9C3:
layer_somethingon
.layer_9C4:
layer_note1 39, 0x12c, 68
layer_jump .layer_9C4
layer_end
.sound_moving_slide_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_9DD
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 4
chan_end
.layer_9DD:
layer_note1 42, 0xc, 75
layer_somethingon
.layer_9E1:
layer_note1 39, 0x12c, 76
layer_jump .layer_9E1
layer_end
.sound_moving_slide_snow:
chan_setbank 3
chan_setinstr 5
chan_setlayer 0, .layer_9F1
chan_end
.layer_9F1:
layer_somethingon
.layer_9F2:
layer_note1 39, 0x12c, 80
layer_jump .layer_9F2
layer_end
.sound_moving_slide_ice:
chan_setbank 3
chan_setinstr 6
chan_setlayer 0, .layer_A02
chan_end
.layer_A02:
layer_somethingon
.layer_A03:
layer_note1 39, 0x12c, 100
layer_jump .layer_A03
layer_end
.sound_moving_slide_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_A1C
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 8
chan_end
.layer_A1C:
layer_note1 42, 0xc, 100
layer_somethingon
.layer_A20:
layer_note1 39, 0x12c, 120
layer_jump .layer_A20
layer_end
.sound_moving_lava_burn:
chan_setbank 3
chan_setinstr 8
chan_setlayer 0, .layer_A30
chan_end
.layer_A30:
layer_somethingon
.layer_A31:
layer_note1 39, 0x12c, 120
layer_jump .layer_A31
layer_end
.sound_moving_slide_down_pole:
chan_setbank 3
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_A44
chan_end
.layer_A44:
layer_somethingon
.layer_A45:
layer_note1 43, 0x12c, 80
layer_jump .layer_A45
layer_end
.sound_moving_slide_down_tree:
chan_setbank 0
chan_setinstr 1
chan_setlayer 0, .layer_A55
chan_end
.layer_A55:
layer_portamento 0x81, 44, 255
.layer_A59:
layer_somethingon
layer_note1 40, 0xb4, 100
layer_jump .layer_A59
layer_end
.sound_moving_quicksand_death:
chan_setbank 3
chan_setinstr 7
chan_setlayer 0, .layer_A6A
chan_end
.layer_A6A:
layer_somethingon
layer_portamento 0x85, 37, 255
.layer_A6F:
layer_note1 34, 0xc8, 127
layer_jump .layer_A6F
layer_end
.sound_moving_shocked:
chan_setbank 3
chan_setinstr 9
chan_setlayer 0, .layer_A84
chan_setlayer 1, .layer_A82
chan_end
.layer_A82:
layer_transpose 24
.layer_A84:
layer_note1_long 43, 0x6, 127
layer_jump .layer_A84
layer_end
.sound_moving_flying:
chan_setbank 5
chan_setinstr 6
chan_setlayer 0, .layer_A9B
chan_setlayer 1, .layer_A97
chan_end
.layer_A97:
layer_setinstr 13
layer_transpose 244
.layer_A9B:
layer_somethingon
.layer_A9C:
layer_note1 43, 0x12c, 105
layer_jump .layer_A9C
.sound_moving_almost_drowning:
chan_setbank 9
chan_setinstr 3
chan_setval 40
chan_call .set_reverb
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_AB3
chan_end
.layer_AB3:
layer_transpose 12
.layer_AB5:
layer_note0 60, 0xc, 100, 127
layer_note0 60, 0x30, 100, 127
layer_jump .layer_AB5
.sound_moving_aim_cannon:
chan_jump .chan_29C2
.chan_AC3:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3368
chan_setlayer 0, .layer_AD8
chan_setlayer 1, .layer_AD6
chan_setlayer 2, .layer_AD4
chan_end
.layer_AD4:
layer_delay 0x4
.layer_AD6:
layer_delay 0x4
.layer_AD8:
layer_transpose 24
.layer_ADA:
layer_portamento 0x85, 32, 40
layer_note1 39, 0x9, 100
layer_note1 44, 0x6, 50
layer_note1 51, 0x3, 20
layer_jump .layer_ADA
.sound_moving_riding_shell_default:
chan_setbank 3
chan_setinstr 0
chan_setlayer 0, .layer_AF2
chan_end
.layer_AF2:
layer_transpose 4
layer_jump .layer_96E
.sound_moving_riding_shell_grass:
chan_jump .sound_moving_riding_shell_stone
chan_setinstr 1
chan_setlayer 0, .layer_B08
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 1
chan_end
.layer_B08:
layer_transpose 4
layer_jump .layer_988
.sound_moving_riding_shell_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_B21
chan_setlayer 1, .layer_B26
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 2
chan_end
.layer_B21:
layer_transpose 4
layer_jump .layer_9A8
.layer_B26:
layer_transpose 4
layer_jump .layer_9B3
.sound_moving_riding_shell_stone:
chan_setbank 3
chan_setinstr 3
chan_setlayer 0, .layer_B33
chan_end
.layer_B33:
layer_transpose 4
layer_jump .layer_9C3
.sound_moving_riding_shell_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_B49
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 4
chan_end
.layer_B49:
layer_transpose 4
layer_jump .layer_9DD
.sound_moving_riding_shell_snow:
chan_setbank 3
chan_setinstr 5
chan_setlayer 0, .layer_B56
chan_end
.layer_B56:
layer_transpose 4
layer_jump .layer_9F1
.sound_moving_riding_shell_ice:
chan_setbank 3
chan_setinstr 6
chan_setlayer 0, .layer_B63
chan_end
.layer_B63:
layer_transpose 4
layer_jump .layer_A02
.sound_moving_riding_shell_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_B79
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 8
chan_end
.layer_B79:
layer_transpose 4
layer_jump .layer_A1C
layer_note1 39, 0x12c, 120
.sound_moving_riding_shell_lava:
chan_setlayer 0, .layer_B9F
chan_setlayer 1, .layer_BA8
.chan_B84:
chan_setbank 3
chan_setinstr 2
chan_setval 1
chan_call .delay
chan_setdecayrelease 30
chan_setbank 2
chan_setinstr 1
chan_setenvelope .envelope_3334
chan_setval 1
chan_call .delay
chan_jump .chan_B84
chan_end
.layer_B9F:
layer_somethingon
.layer_BA0:
layer_note1 42, 0x12c, 88
layer_jump .layer_BA0
layer_end
.layer_BA8:
layer_delay 1
.layer_BAA:
layer_portamento 0x81, 41, 255
layer_note1 56, 0xa, 127
layer_jump .layer_BAA
.channel2_table:
sound_ref .sound_mario_jump_yah
sound_ref .sound_mario_jump_wah
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_hoohoo
sound_ref .sound_mario_yahoo
sound_ref .sound_mario_uh
sound_ref .sound_mario_hrmm
sound_ref .sound_mario_wah2
sound_ref .sound_mario_whoa
sound_ref .sound_mario_eeuh
sound_ref .sound_mario_attacked
sound_ref .sound_mario_ooof
sound_ref .sound_mario_here_we_go
sound_ref .sound_mario_yawning
sound_ref .sound_mario_snoring1
sound_ref .sound_mario_snoring2
sound_ref .sound_mario_waaaooow
sound_ref .sound_mario_haha
sound_ref .sound_mario_panting1
sound_ref .sound_mario_uh2
sound_ref .sound_mario_on_fire
sound_ref .sound_mario_dying
sound_ref .sound_mario_panting_cold
sound_ref .sound_mario_coughing3
sound_ref .sound_mario_panting1
sound_ref .sound_mario_panting2
sound_ref .sound_mario_panting3
sound_ref .sound_mario_coughing1
sound_ref .sound_mario_coughing2
sound_ref .sound_mario_coughing3
sound_ref .sound_mario_punch_yah
sound_ref .sound_mario_punch_hoo
sound_ref .sound_mario_mama_mia
sound_ref .sound_mario_okey_dokey
sound_ref .sound_mario_ground_pound_wah
sound_ref .sound_mario_drowning
sound_ref .sound_mario_punch_wah
sound_ref .sound_mario_uh
sound_ref .sound_mario_hrmm
sound_ref .sound_mario_wah2
.ifdef VERSION_JP
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
.else
sound_ref .sound_peach_dear_mario
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_yahoo
sound_ref .sound_mario_yahoo
sound_ref .sound_mario_yahoo
sound_ref .sound_mario_waha
sound_ref .sound_mario_yippee
sound_ref .sound_mario_doh
sound_ref .sound_mario_game_over
sound_ref .sound_mario_hello
sound_ref .sound_mario_press_start_to_play
sound_ref .sound_mario_twirl_bounce
sound_ref .sound_mario_snoring3
sound_ref .sound_mario_so_longa_bowser
sound_ref .sound_mario_ima_tired
sound_ref .sound_peach_mario
sound_ref .sound_peach_power_of_the_stars
sound_ref .sound_peach_thanks_to_you
sound_ref .sound_peach_thank_you_mario
sound_ref .sound_peach_something_special
sound_ref .sound_peach_bake_a_cake
sound_ref .sound_peach_for_mario
sound_ref .sound_peach_mario2
.endif
.sound_mario_jump_hoo:
chan_setbank 8
chan_setinstr 0
chan_setlayer 0, .layer_C3C
chan_end
.layer_C3C:
.ifdef VERSION_EU
layer_transpose 2
.endif
#layer_portamento 0, 41, 127
layer_note1 37, 0x18, 127
layer_end
.sound_mario_jump_wah:
chan_setbank 8
chan_setinstr 1
chan_setlayer 0, .layer_C4C
chan_end
.layer_C4C:
layer_transpose 254
.layer_C4E:
layer_note1 38, 0x18, 127
layer_end
.sound_mario_jump_yah:
chan_setbank 8
chan_setinstr 2
chan_setlayer 0, .layer_C5A
chan_end
.layer_C5A:
layer_transpose 254
.layer_C5C:
layer_note1 38, 0x10, 130
layer_end
.sound_mario_hoohoo:
chan_setbank 10
chan_setinstr 1
chan_setlayer 0, .layer_C6C
chan_end
.layer_C6C:
.ifdef VERSION_EU
layer_transpose 1
.endif
layer_portamento 0x82, 44, 200
layer_note1 39, 0x30, 127
layer_end
.sound_mario_yahoo:
chan_setbank 8
chan_setinstr 4
chan_setlayer 0, .layer_C7C
chan_end
.layer_C7C:
layer_transpose 256
layer_somethingon
layer_note1 39, 0x5a, 97
layer_end
.sound_mario_uh:
chan_setbank 8
chan_setinstr 5
chan_setlayer 0, .layer_C92
chan_end
.layer_C92:
layer_transpose 254
layer_portamento 0x81, 41, 255
layer_note1 38, 0x2b, 115
layer_end
.sound_mario_hrmm:
chan_setbank 8
chan_setinstr 6
chan_setlayer 0, .layer_CA4
chan_end
.layer_CA4:
layer_transpose 254
layer_note1 44, 0x1e, 110
layer_end
.sound_mario_wah2:
chan_setbank 8
chan_setinstr 7
chan_setlayer 0, .layer_CB2
chan_end
.layer_CB2:
layer_transpose 253
layer_note1 40, 0x1c, 127
layer_end
.sound_mario_whoa:
chan_setbank 8
chan_setinstr 8
chan_setlayer 0, .layer_CC0
chan_end
.layer_CC0:
layer_transpose 254
layer_note1 40, 0x30, 110
layer_end
.sound_mario_eeuh:
chan_setbank 8
chan_setinstr 9
chan_setlayer 0, .layer_CCE
chan_end
.layer_CCE:
layer_note1 43, 0x30, 145
layer_end
.sound_mario_attacked:
chan_setbank 8
chan_setinstr 10
chan_setlayer 0, .layer_CDC
chan_end
.layer_CDC:
layer_transpose 254
layer_note1 41, 0x30, 120
layer_end
.sound_mario_ooof:
chan_setbank 8
chan_setinstr 11
chan_setlayer 0, .layer_CEA
chan_end
.layer_CEA:
layer_transpose 254
layer_note1 38, 0x30, 127
layer_end
.sound_mario_here_we_go:
chan_setbank 8
chan_setinstr 12
chan_setlayer 0, .layer_CF8
chan_end
.layer_CF8:
layer_portamento 0x81, 38, 200
layer_note1 41, 0x85, 127
layer_end
.sound_mario_yawning:
chan_setbank 8
chan_setinstr 13
chan_setlayer 0, .layer_D09
chan_end
.layer_D09:
layer_note1 37, 0x7f, 127
layer_end
.sound_mario_snoring1:
chan_setbank 8
chan_setinstr 14
chan_setlayer 0, .layer_D17
chan_end
.layer_D17:
layer_note1 39, 0x60, 127
layer_end
.sound_mario_snoring2:
chan_setbank 8
chan_setinstr 15
chan_setlayer 0, .layer_D25
chan_end
.layer_D25:
layer_transpose 254
layer_note1 39, 0x5c, 52
layer_end
.sound_mario_waaaooow:
chan_setbank 10
chan_setinstr 0
chan_setlayer 0, .layer_D33
chan_end
.layer_D33:
layer_transpose 254
layer_note1 39, 0xaa, 127
layer_end
.sound_mario_haha:
chan_setbank 8
chan_setinstr 3
chan_setlayer 0, .layer_D42
chan_end
.layer_D42:
layer_transpose 255
layer_note1 39, 0x4d, 120
layer_end
.sound_mario_uh2:
chan_jump .sound_mario_eeuh
chan_setinstr 6
chan_setlayer 0, .layer_D50
chan_end
.layer_D50:
layer_transpose 254
layer_note1 43, 0x1e, 105
layer_end
.sound_mario_on_fire:
chan_setbank 10
chan_setinstr 5
chan_setlayer 0, .layer_D5E
chan_end
.layer_D5E:
layer_transpose 254
layer_note1 39, 0xc8, 127
layer_end
.sound_mario_dying:
chan_setbank 10
chan_setinstr 4
chan_setlayer 0, .layer_D6D
chan_end
.layer_D6D:
layer_transpose 254
layer_note1 39, 0x8c, 110
layer_end
.sound_mario_panting_cold:
chan_setbank 10
chan_setinstr 2
chan_setlayer 0, .layer_D7C
chan_end
.layer_D7C:
layer_transpose 254
layer_portamento 0x82, 35, 255
layer_note1 38, 0x30, 127
layer_end
.sound_mario_panting1:
chan_setbank 10
chan_setinstr 2
chan_setlayer 0, .layer_D8E
chan_end
.layer_D8E:
layer_transpose 254
layer_note1 39, 0x3c, 100
layer_end
.sound_mario_panting2:
chan_setbank 10
chan_setinstr 2
chan_setlayer 0, .layer_D9C
chan_end
.layer_D9C:
layer_transpose 254
layer_delay 0x4
layer_note1 38, 0x3c, 100
layer_end
.sound_mario_panting3:
chan_setbank 10
chan_setinstr 2
chan_setlayer 0, .layer_DAC
chan_end
.layer_DAC:
layer_transpose 254
layer_delay 0x8
layer_note1 40, 0x3c, 100
layer_end
.sound_mario_coughing1:
chan_setbank 10
chan_setinstr 7
chan_setlayer 0, .layer_DBC
chan_end
.layer_DBC:
layer_transpose 254
layer_note1 39, 0x10, 115
layer_end
.sound_mario_coughing2:
chan_setbank 10
chan_setinstr 7
chan_setlayer 0, .layer_DCA
chan_end
.layer_DCA:
layer_transpose 254
layer_portamento 0x81, 38, 255
layer_note1 41, 0x18, 115
layer_end
.sound_mario_coughing3:
chan_setbank 10
chan_setinstr 7
chan_setlayer 0, .layer_DDC
chan_end
.layer_DDC:
layer_transpose 254
layer_somethingon
layer_portamento 0x85, 38, 255
layer_note1 41, 0xc, 115
layer_note1 35, 0x12, 115
layer_end
.sound_mario_punch_yah:
chan_setbank 10
chan_setinstr 9
chan_setlayer 0, .layer_DFE
chan_setval 1
chan_call .delay
chan_setbank 0
chan_setinstr 0
chan_setlayer 1, .layer_538
chan_end
.layer_DFE:
layer_transpose 254
layer_jump .layer_C5C
.sound_mario_punch_hoo:
chan_setbank 10
chan_setinstr 10
chan_setlayer 0, .layer_E17
chan_setval 1
chan_call .delay
chan_setbank 0
chan_setinstr 0
chan_setlayer 1, .layer_556
chan_end
.layer_E17:
layer_transpose 254
layer_note1 0, 0, 0
layer_end
.sound_mario_mama_mia:
chan_setbank 10
chan_setinstr 11
chan_setlayer 0, .layer_E29
chan_end
.layer_E29:
layer_portamento 0x81, 38, 255
layer_note1 36, 0x8c, 115
layer_end
.sound_mario_okey_dokey:
chan_setbank 10
chan_setinstr 12
chan_setlayer 0, .layer_E3A
chan_end
.layer_E3A:
layer_note1 39, 0x60, 115
layer_end
.sound_mario_ground_pound_wah:
chan_jump .sound_mario_wah2
.sound_mario_drowning:
chan_setbank 10
chan_setinstr 13
chan_setlayer 0, .layer_E49
chan_end
.layer_E49:
layer_note1 38, 0x91, 127
layer_end
.sound_mario_punch_wah:
chan_setbank 8
chan_setinstr 1
chan_setlayer 0, .layer_E62
chan_setval 1
chan_call .delay
chan_setbank 0
chan_setinstr 0
chan_setlayer 1, .layer_536
chan_end
.layer_E62:
layer_transpose 255
layer_jump .layer_C4E
.ifndef VERSION_JP
.sound_peach_dear_mario:
chan_setbank 10
chan_setinstr 15
chan_setlayer 0, .layer_E6F
chan_end
.layer_E6F:
layer_note1 39, 0x2bc, 127
layer_end
.sound_mario_waha:
chan_setbank 8
chan_setinstr 24
chan_setlayer 0, .layer_E7C
chan_end
.layer_E7C:
layer_note1 39, 0x5a, 127
layer_end
.sound_mario_yippee:
chan_setbank 8
chan_setinstr 25
chan_setlayer 0, .layer_E88
chan_end
.layer_E88:
layer_note1 39, 0x5a, 97
layer_end
.sound_mario_doh:
chan_setbank 8
chan_setinstr 16
chan_setlayer 0, .layer_E94
chan_end
.layer_E94:
layer_note1 41, 0x46, 127
layer_end
.sound_mario_game_over:
chan_setbank 8
chan_setinstr 17
chan_setlayer 0, .layer_EA0
chan_end
.layer_EA0:
layer_note1 39, 0x55, 110
layer_end
.sound_mario_hello:
chan_setbank 8
chan_setinstr 18
chan_setlayer 0, .layer_EAC
chan_end
.layer_EAC:
layer_note1 39, 0x46, 127
layer_end
.sound_mario_press_start_to_play:
chan_setbank 8
chan_setinstr 19
chan_setlayer 0, .layer_EB8
chan_end
.layer_EB8:
layer_note1 39, 0x12c, 127
layer_end
.sound_mario_twirl_bounce:
chan_setbank 8
chan_setinstr 8
chan_setlayer 0, .layer_EC5
chan_end
.layer_EC5:
layer_note1 39, 0x30, 127
layer_end
.sound_mario_snoring3:
chan_setbank 8
chan_setlayer 0, .layer_ECF
chan_end
.layer_ECF:
layer_delay 0x4e
.layer_ED1:
layer_loop 50
layer_call .layer_fn_EE1
layer_loopend
layer_setinstr 21
layer_note1 39, 0x44c, 127
layer_jump .layer_ED1
layer_end
.layer_fn_EE1:
layer_setinstr 21
layer_note1 37, 0x53, 127
layer_setinstr 15
layer_note1 37, 0x4e, 64
layer_end
.sound_mario_so_longa_bowser:
chan_setbank 8
chan_setinstr 22
chan_setlayer 0, .layer_EF7
chan_setlayer 1, .layer_EF7
chan_end
.layer_EF7:
layer_portamento 0x82, 42, 200
layer_note1 39, 0xc8, 110
layer_end
.sound_mario_ima_tired:
chan_setbank 8
chan_setinstr 23
chan_setlayer 0, .layer_F08
chan_end
.layer_F08:
layer_note1 39, 0x96, 110
layer_end
.sound_peach_mario:
chan_setbank 10
chan_setinstr 16
chan_setlayer 0, .layer_F18
chan_setlayer 1, .layer_F18
chan_end
.layer_F18:
layer_note1 39, 0x46, 127
layer_end
.sound_peach_power_of_the_stars:
chan_setbank 10
chan_setinstr 17
chan_setlayer 0, .layer_F27
chan_setlayer 1, .layer_F27
chan_end
.layer_F27:
layer_note1 39, 0x15e, 127
layer_end
.sound_peach_thanks_to_you:
chan_setbank 10
chan_setinstr 18
chan_setlayer 0, .layer_F37
chan_setlayer 1, .layer_F37
chan_end
.layer_F37:
layer_note1 39, 0xb4, 127
layer_end
.sound_peach_thank_you_mario:
chan_setbank 10
chan_setinstr 19
chan_setlayer 0, .layer_F47
chan_setlayer 1, .layer_F47
chan_end
.layer_F47:
layer_note1 39, 0x64, 127
layer_end
.sound_peach_something_special:
chan_setbank 10
chan_setinstr 20
chan_setlayer 0, .layer_F56
chan_setlayer 1, .layer_F56
chan_end
.layer_F56:
layer_note1 39, 0xdc, 127
layer_end
.sound_peach_bake_a_cake:
chan_setbank 10
chan_setinstr 21
chan_setlayer 0, .layer_F66
chan_setlayer 1, .layer_F66
chan_end
.layer_F66:
layer_note1 39, 0x190, 127
layer_end
.sound_peach_for_mario:
chan_setbank 10
chan_setinstr 22
chan_setlayer 0, .layer_F76
chan_setlayer 1, .layer_F76
chan_end
.layer_F76:
layer_note1 39, 0x50, 127
layer_end
.sound_peach_mario2:
chan_setbank 10
chan_setinstr 23
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_F8A
chan_setlayer 1, .layer_F8A
chan_end
.layer_F8A:
layer_note1 39, 0x50, 127
layer_end
.endif
.ifdef VERSION_EU
.chan_unused_F9A_eu:
chan_setbank 8
chan_setinstr 0
chan_setlayer 0, .layer_FA2_eu
chan_end
.layer_FA2_eu:
layer_delay 0x5
layer_end
.endif
.channel38_table:
sound_ref .sound_general_activate_cap_switch
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_enter_hole
sound_ref .sound_general_flame_out
sound_ref .sound_general_open_wood_door
sound_ref .sound_general_close_wood_door
sound_ref .sound_general_open_iron_door
sound_ref .sound_general_close_iron_door
sound_ref .sound_general_bubbles
sound_ref .sound_general_moving_water
sound_ref .sound_general_swish_water
sound_ref .sound_general_quiet_bubble
sound_ref .sound_general_volcano_explosion
sound_ref .sound_general_quiet_bubble2
sound_ref .sound_general_castle_trap_open
sound_ref .sound_general_wall_explosion
sound_ref .sound_general_coin
sound_ref .sound_general_coin
sound_ref .sound_general_coin_water
sound_ref .sound_general_coin_water
sound_ref .sound_general_coin_water
sound_ref .sound_general_coin_water
sound_ref .sound_general_short_star
sound_ref .sound_general_big_clock
sound_ref .sound_general_loud_pound
sound_ref .sound_general_loud_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_open_chest
sound_ref .sound_general_open_chest
sound_ref .sound_general_clam_shell1
sound_ref .sound_general_clam_shell1
sound_ref .sound_general_box_landing
sound_ref .chan_12EB
sound_ref .sound_general_clam_shell2
sound_ref .sound_general_clam_shell3
sound_ref .sound_general_painting_eject
sound_ref .sound_general_painting_eject
sound_ref .sound_general_painting_eject
sound_ref .sound_general_painting_eject
sound_ref .sound_menu_star_sound
sound_ref .sound_general_platform
sound_ref .sound_general_bobomb_explosion
sound_ref .sound_general_bowser_bomb_explosion
sound_ref .sound_general_coin_spurt
sound_ref .sound_general_explosion6
sound_ref .chan_13D4
sound_ref .sound_general_coin
sound_ref .sound_general_boat_tilt1
sound_ref .sound_general_boat_tilt2
sound_ref .sound_general_coin_drop
sound_ref .chan_1429
sound_ref .sound_general_pendulum_swing
sound_ref .sound_general_chain_chomp1
sound_ref .sound_general_chain_chomp2
sound_ref .sound_general_door_turn_key
sound_ref .sound_general_moving_in_sand
sound_ref .chan_1519
sound_ref .sound_general_moving_platform_switch
sound_ref .sound_general_cage_open
sound_ref .sound_general_quiet_pound1
sound_ref .sound_general_break_box
sound_ref .sound_general_door_insert_key
sound_ref .sound_general_quiet_pound2
sound_ref .sound_general_big_pound
sound_ref .chan_15CD
sound_ref .chan_15DA
sound_ref .sound_general_cannon_up
sound_ref .sound_general_grindel_spindel_roll
sound_ref .sound_general_explosion7
sound_ref .sound_general_shake_coffin
sound_ref .sound_general_pyramid_top_spin
sound_ref .sound_general_pyramid_top_explosion
sound_ref .sound_general_race_gun_shot
sound_ref .sound_general_star_door_open
sound_ref .sound_general_star_door_close
sound_ref .sound_general_bird_chirp2
sound_ref .sound_obj_bird_chirp3
sound_ref .sound_obj_bird_chirp1
sound_ref .sound_air_castle_outdoors_ambient
sound_ref .sound_general_switch_tick_fast
sound_ref .sound_general_switch_tick_slow
sound_ref .sound_general_pound_rock
sound_ref .sound_general_star_appears
sound_ref .sound_general_collect_1up
sound_ref .sound_general_rotating_block_alert
sound_ref .sound_general_button_press
sound_ref .sound_general_elevator_move
sound_ref .sound_general_swish_air
sound_ref .sound_general_haunted_chair
sound_ref .sound_general_soft_landing
sound_ref .sound_general_haunted_chair_move
sound_ref .sound_general_bowser_explode
sound_ref .sound_general_bowser_key
sound_ref .sound_general_bowser_platform
sound_ref .sound_general_1up_appear
sound_ref .sound_general_heart_spin
sound_ref .sound_general_pound_wood_post
sound_ref .sound_general_water_level_trig
sound_ref .sound_general_switch_door_open
sound_ref .sound_general_red_coin
sound_ref .sound_general_birds_fly_away
sound_ref .sound_general_right_answer
sound_ref .sound_general_metal_pound
sound_ref .sound_general_boing1
sound_ref .sound_general_boing2
sound_ref .sound_general_yoshi_walk
sound_ref .sound_general_enemy_alert1
sound_ref .sound_general_yoshi_talk
sound_ref .sound_general_splattering
sound_ref .sound_general_boing3
sound_ref .sound_general_grand_star
sound_ref .sound_general_grand_star_jump
sound_ref .sound_general_boat_rock
.ifdef VERSION_JP
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_enter_hole
sound_ref .sound_general_open_wood_door
sound_ref .sound_general_close_wood_door
sound_ref .sound_general_open_iron_door
sound_ref .sound_general_close_iron_door
sound_ref .sound_general_bubbles
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_enter_hole
.else
sound_ref .sound_general_vanish_sfx
sound_ref .sound_menu_enter_hole
sound_ref .sound_general_red_coin
sound_ref .sound_general_birds_fly_away
sound_ref .sound_general_right_answer
sound_ref .sound_general_metal_pound
sound_ref .sound_general_boing1
sound_ref .sound_general_boing2
sound_ref .sound_general_yoshi_walk
sound_ref .sound_general_enemy_alert1
.endif
.sound_general_activate_cap_switch:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_109F
chan_delay 1
chan_setbank 4
chan_setinstr 9
chan_setlayer 1, .layer_1537
chan_end
.layer_109F:
layer_portamento 0x1, 27, 0x28
layer_note1 37, 0x7f, 120
layer_end
.sound_menu_enter_hole:
chan_setbank 4
chan_setinstr 0
chan_setlayer 0, .layer_10AF
chan_end
.layer_10AF:
layer_note1 39, 0x30, 85
layer_end
.sound_general_flame_out:
chan_setbank 3
chan_setinstr 8
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_10BE
chan_end
.layer_10BE:
layer_somethingon
layer_portamento 0x85, 34, 255
layer_note1 43, 0x8, 127
layer_note1 27, 0x7f, 127
layer_end
.sound_general_open_wood_door:
chan_setbank 4
chan_setinstr 1
chan_setlayer 0, .layer_10D2
chan_end
.layer_10D2:
layer_note1 39, 0x18, 100
layer_setinstr 2
layer_note1 39, 0x48, 60
layer_end
.sound_general_close_wood_door:
chan_setbank 4
chan_setinstr 1
chan_setlayer 0, .layer_10E3
chan_end
.layer_10E3:
layer_note1 37, 0x6, 100
layer_note1 34, 0x18, 100
layer_end
.sound_general_open_iron_door:
chan_setbank 4
chan_setinstr 4
chan_setlayer 0, .layer_10FE
chan_setlayer 1, .layer_1108
chan_setval 6
chan_call .delay
chan_setbank 4
chan_setinstr 3
chan_end
.layer_10FE:
layer_delay 0xf
layer_portamento 0x81, 39, 255
layer_note1 44, 0x38, 115
layer_end
.layer_1108:
layer_portamento 0x81, 44, 255
layer_note1 34, 0x2c, 85
layer_end
.sound_general_close_iron_door:
chan_setbank 4
chan_setinstr 4
chan_setlayer 0, .layer_1118
chan_end
.layer_1118:
layer_note1 39, 0x30, 115
layer_end
.sound_general_bubbles:
chan_setbank 4
chan_setinstr 6
chan_setlayer 0, .layer_1124
chan_end
.layer_1124:
layer_transpose 24
layer_note1 39, 0xa, 65
layer_note1 39, 0x9, 70
layer_note1 39, 0x8, 75
layer_end
.sound_general_moving_water:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_1138
chan_end
.layer_1138:
layer_note1 39, 0x91, 127
layer_end
.sound_obj_sushi_shark_water_sound:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_1145
chan_end
.layer_1145:
layer_portamento 0x81, 27, 255
layer_note1 32, 0x60, 127
layer_end
.sound_general_quiet_bubble:
chan_setbank 4
chan_setinstr 6
chan_setlayer 0, .layer_1155
chan_end
.layer_1155:
layer_note1 39, 0x14, 70
layer_end
.sound_general_volcano_explosion:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_1161
chan_end
.layer_1161:
layer_note1 32, 0x18, 127
layer_portamento 0x81, 41, 255
layer_note1 27, 0x96, 127
layer_end
.sound_general_quiet_bubble2:
chan_setbank 4
chan_setinstr 6
chan_setlayer 0, .layer_1175
chan_end
.layer_1175:
layer_portamento 0x81, 34, 255
layer_note1 37, 0x18, 80
layer_end
.sound_general_castle_trap_open:
chan_setbank 4
chan_setinstr 8
chan_setlayer 0, .layer_1185
chan_end
.layer_1185:
layer_note1 39, 0x40, 120
layer_end
.sound_general_wall_explosion:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_109F
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 9
chan_setlayer 1, .layer_119D
chan_end
.layer_119D:
layer_transpose 244
.layer_fn_119F:
layer_portamento 0x83, 27, 255
layer_note0 55, 0x4, 127, 64
layer_note0 51, 0x5, 127, 64
layer_note0 48, 0x4, 127, 64
layer_note0 44, 0x6, 127, 64
layer_note0 41, 0x9, 127, 64
layer_note0 39, 0x6, 127, 64
.layer_11BB:
layer_note0 37, 0x7, 127, 64
layer_note0 34, 0x5, 127, 64
layer_note0 31, 0x8, 127, 64
layer_note0 29, 0x9, 127, 64
layer_note0 24, 0x8, 127, 64
layer_end
.sound_general_coin:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setvibratoextent 3
chan_setvibratorate 60
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_11E4
chan_end
.layer_11E4:
layer_transpose 24
.layer_fn_11E6:
layer_note1 25, 0x2, 40
layer_note1 37, 0x7, 85
layer_note1 30, 0x5, 40
layer_note1 42, 0x37, 85
layer_end
.sound_general_coin_water:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setvibratoextent 12
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_1242
chan_setlayer 1, .layer_1254
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 6
chan_setval 1
chan_call .delay
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setval 9
chan_call .delay
chan_setbank 4
chan_setinstr 6
chan_setval 3
chan_call .delay
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setval 6
chan_call .delay
chan_setbank 4
chan_setinstr 6
chan_setval 49
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_1242:
layer_delay 1
layer_setinstr 6
layer_transpose 22
layer_note1 39, 0xa, 55
layer_note1 39, 0x9, 60
layer_note1 39, 0x8, 65
layer_delay 0x29
layer_end
.layer_1254:
layer_transpose 23
layer_call .layer_fn_11E6
layer_end
.sound_general_short_star:
chan_setbank 4
chan_setinstr 14
chan_setenvelope .envelope_33FC
chan_setlayer 0, .layer_1265
chan_end
.layer_1265:
layer_portamento 0x81, 34, 127
layer_note1 38, 0x30, 127
layer_delay 0x30
layer_end
.sound_general_big_clock:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1277
chan_end
.layer_1277:
layer_note1 37, 0xa, 100
layer_note1 26, 0x12, 120
layer_end
.sound_general_loud_pound:
chan_setbank 4
chan_setinstr 10
chan_setlayer 0, .layer_1286
chan_end
.layer_1286:
layer_note1 39, 0xf, 120
layer_end
.sound_general_short_pound:
chan_setbank 4
chan_setinstr 10
chan_setlayer 0, .layer_1292
chan_end
.layer_1292:
layer_note1 37, 0x12, 120
layer_end
.sound_general_open_chest:
chan_setbank 7
chan_setinstr 1
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_12AF
chan_setlayer 1, .layer_12AF
chan_setval 6
chan_call .delay
chan_setbank 4
chan_setinstr 4
chan_end
.layer_12AF:
layer_note1 43, 0x5, 127
layer_note1 62, 0x9, 127
layer_setinstr 2
layer_portamento 0x81, 27, 255
layer_note1 25, 0x5a, 108
layer_end
.sound_general_clam_shell1:
chan_setbank 4
chan_setinstr 11
chan_setlayer 0, .layer_12C7
chan_end
.layer_12C7:
layer_note1 24, 0xa, 110
.layer_12CA:
layer_setinstr 5
layer_portamento 0x82, 27, 255
layer_note1 32, 0x73, 127
layer_end
.sound_general_box_landing:
chan_setbank 4
chan_setinstr 1
chan_setenvelope .envelope_33CC
chan_setlayer 0, .layer_12DF
chan_end
.layer_12DF:
layer_somethingon
layer_note1 39, 0x4, 127
layer_portamento 0x82, 36, 255
layer_note1 27, 0x9, 115
layer_end
.chan_12EB:
chan_setbank 4
chan_setinstr 2
chan_setenvelope .envelope_3454
chan_setlayer 0, .layer_12F9
chan_setlayer 1, .layer_12FB
chan_end
.layer_12F9:
layer_transpose 3
.layer_12FB:
layer_portamento 0x2, 17, 0x28
layer_note1 5, 0x60, 127
layer_end
.sound_general_clam_shell2:
chan_setbank 4
chan_setinstr 11
chan_setlayer 0, .layer_130B
chan_end
.layer_130B:
layer_note1 19, 0x6, 110
layer_note1 31, 0x6, 110
layer_transpose 8
layer_jump .layer_12CA
.sound_general_clam_shell3:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_131E
chan_end
.layer_131E:
layer_setinstr 11
layer_note1 31, 0x6, 127
layer_note1 19, 0x6, 127
layer_setinstr 5
layer_portamento 0x82, 20, 255
layer_note1 32, 0x5a, 127
layer_end
.sound_general_painting_eject:
chan_setbank 4
chan_setinstr 13
chan_setlayer 0, .layer_1338
chan_end
.layer_1338:
layer_note1 39, 0x73, 95
layer_end
.sound_menu_star_sound:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1344
chan_end
.layer_1344:
layer_note1 39, 0x7f, 115
layer_end
.sound_general_platform:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_1350
chan_end
.layer_1350:
layer_note0 36, 0xd, 115, 20
layer_note0 34, 0xe, 115, 20
layer_note0 32, 0xd, 115, 20
layer_note0 31, 0xa, 115, 20
layer_note0 30, 0x7, 115, 20
layer_note0 29, 0x60, 115, 20
layer_end
.sound_general_bobomb_explosion:
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_33EC
chan_setlayer 0, .layer_137B
chan_setlayer 1, .layer_1377
chan_end
.layer_1377:
layer_note1 15, 0x7f, 127
layer_end
.layer_137B:
layer_note1 55, 0x6, 115
layer_note1 43, 0xc, 115
layer_note1 34, 0x7f, 127
layer_end
.sound_general_bowser_bomb_explosion:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_1395
chan_setlayer 1, .layer_13A0
chan_setlayer 2, .layer_1393
chan_end
.layer_1393:
layer_transpose 6
.layer_1395:
layer_note1 44, 0x7, 127
layer_note1 39, 0x8, 127
layer_note1 36, 0x96, 127
layer_end
.layer_13A0:
layer_note1 22, 0x96, 127
layer_end
.sound_general_coin_spurt:
chan_setbank 9
chan_setinstr 3
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_13B2
chan_end
.layer_13B2:
layer_portamento 0x81, 36, 255
layer_note1 48, 0x6, 80
layer_end
.sound_general_explosion6:
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_33EC
chan_setlayer 0, .layer_13C8
chan_setlayer 1, .layer_13D0
chan_end
.layer_13C8:
layer_portamento 0x81, 56, 255
layer_note1 20, 0x78, 80
layer_end
.layer_13D0:
layer_note1 15, 0x78, 127
layer_end
.chan_13D4:
chan_setbank 4
chan_setinstr 6
chan_setlayer 0, .layer_13DC
chan_end
.layer_13DC:
layer_portamento 0x81, 37, 255
layer_note1 39, 0x8, 127
layer_setinstr 5
layer_portamento 0x81, 20, 255
layer_note1 25, 0x60, 127
layer_end
.sound_general_boat_tilt1:
chan_setbank 4
chan_setinstr 2
chan_setlayer 0, .layer_13F5
chan_end
.layer_13F5:
layer_portamento 0x81, 12, 255
layer_note1 13, 0x6e, 127
layer_end
.sound_general_boat_tilt2:
chan_setbank 4
chan_setinstr 2
chan_setlayer 0, .layer_1405
chan_end
.layer_1405:
layer_portamento 0x81, 15, 255
layer_note1 11, 0x6e, 127
layer_end
.sound_general_coin_drop:
chan_setbank 9
chan_setinstr 3
chan_setval 40
chan_call .set_reverb
chan_setlayer 0, .layer_141A
chan_end
.layer_141A:
layer_transpose 24
layer_note1 39, 0x4, 90
layer_note1 51, 0xc, 90
layer_note1 39, 0x4, 50
layer_note1 51, 0xc, 50
layer_end
.chan_1429:
chan_setbank 9
chan_setinstr 3
chan_setval 40
chan_call .set_reverb
chan_setlayer 0, .layer_1436
chan_end
.layer_1436:
layer_transpose 12
layer_note1 39, 0x3, 90
layer_note1 51, 0x3, 90
layer_note1 27, 0xa, 115
layer_note1 39, 0x3, 50
layer_note1 51, 0x3, 50
layer_note1 27, 0xa, 75
layer_end
.sound_general_pendulum_swing:
chan_setbank 4
chan_setinstr 9
chan_setval 50
chan_call .set_reverb
chan_setlayer 0, .layer_1463
chan_setval 13
chan_call .delay
chan_setdecayrelease 30
chan_setbank 4
chan_setinstr 2
chan_end
.layer_1463:
layer_note1 33, 0xc, 100
layer_note1 25, 0x28, 120
layer_portamento 0x81, 22, 255
layer_note1 15, 0x48, 80
layer_end
.sound_general_chain_chomp1:
chan_setbank 1
chan_setinstr 1
chan_setval 15
chan_call .set_reverb
chan_setlayer 0, .layer_148A
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3368
chan_end
.layer_148A:
layer_note1 29, 0xc, 120
layer_transpose 12
layer_portamento 0x81, 51, 255
layer_note1 53, 0x6, 118
layer_portamento 0x81, 52, 255
layer_note1 54, 0x9, 118
layer_end
.sound_general_chain_chomp2:
chan_setbank 7
.ifdef VERSION_JP
chan_setinstr 8
.else
chan_setinstr 14
.endif
chan_setval 15
chan_call .set_reverb
chan_setlayer 0, .layer_14C6
chan_setlayer 1, .layer_14E3
.ifndef VERSION_JP
chan_setlayer 2, .layer_14E3
.endif
chan_setval 1
chan_call .delay
chan_setenvelope .envelope_3368
chan_setbank 1
chan_setinstr 7
chan_setval 13
chan_call .delay
chan_setbank 7
.ifdef VERSION_JP
chan_setinstr 8
.else
chan_setinstr 14
.endif
chan_end
.layer_14C6:
layer_delay 1
layer_transpose 12
layer_portamento 0x81, 54, 255
layer_note0 55, 0x6, 118, 127
layer_portamento 0x81, 55, 255
layer_note0 56, 0x5, 118, 127
layer_portamento 0x81, 57, 255
layer_note0 58, 0xc, 118, 127
layer_end
.layer_14E3:
layer_loop 1
.ifdef VERSION_JP
layer_portamento 0x81, 36, 255
layer_note1 21, 0x18, 127
.else
layer_note1 34, 0x19, 100
.endif
layer_loopend
layer_end
.sound_general_door_turn_key:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_14F2
chan_end
.layer_14F2:
layer_note0 31, 0x12, 80, 80
layer_portamento 0x82, 53, 255
layer_note1 44, 0x7, 88
layer_end
.sound_general_moving_in_sand:
chan_setbank 3
chan_setinstr 5
chan_setenvelope .envelope_32D4
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_150E
chan_end
.layer_150E:
layer_note1 41, 0x4, 100
layer_note0 34, 0x14, 100, 100
layer_note1 29, 0x6, 115
layer_end
.chan_1519:
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_152B
chan_setlayer 1, .layer_1529
chan_setbank 4
chan_setinstr 1
chan_end
.layer_1529:
layer_transpose 1
.layer_152B:
layer_note1 15, 0x2c, 127
layer_end
.sound_general_moving_platform_switch:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1539
chan_end
.layer_1537:
layer_transpose 253
.layer_1539:
layer_note1 39, 0x6, 120
layer_portamento 0x81, 15, 255
layer_note1 8, 0xc, 120
layer_portamento 0x81, 27, 255
layer_note1 3, 0x18, 120
layer_end
.sound_general_cage_open:
chan_setbank 4
chan_setinstr 3
chan_setval 30
chan_call .set_reverb
chan_setlayer 0, .layer_1558
chan_end
.layer_1558:
layer_portamento 0x81, 19, 40
layer_note1 22, 0xb4, 115
layer_end
.sound_general_quiet_pound1:
chan_setbank 5
chan_setinstr 5
chan_setenvelope .envelope_3344
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_1571
chan_end
.layer_1571:
layer_note1 14, 0x34, 110
layer_delay 0x14
layer_end
.sound_general_break_box:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_1582
chan_setlayer 1, .layer_1582
chan_end
.layer_1582:
layer_somethingon
layer_portamento 0x85, 39, 255
layer_note1 36, 0x14, 110
layer_note1 38, 0x10, 110
layer_note1 27, 0x64, 110
layer_end
.sound_general_door_insert_key:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1599
chan_end
.layer_1599:
layer_note0 36, 0xa, 80, 80
layer_note0 24, 0xa, 80, 80
layer_end
.sound_general_quiet_pound2:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_15AA
chan_end
.layer_15AA:
layer_somethingon
layer_portamento 0x85, 35, 255
layer_note1 34, 0x60, 127
layer_note1 32, 0x60, 127
layer_note1 32, 0x30, 127
layer_end
.sound_general_big_pound:
chan_setbank 6
chan_setinstr 1
chan_setval 55
chan_call .set_reverb
chan_setlayer 0, .layer_15C6
chan_end
.layer_15C6:
layer_note1 32, 0xc, 127
layer_note1 27, 0x30, 127
layer_end
.chan_15CD:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_15D5
chan_end
.layer_15D5:
layer_note1 31, 0xc0, 127
layer_end
.chan_15DA:
chan_setbank 7
chan_setinstr 1
chan_setlayer 0, .layer_15EB
chan_setval 1
chan_call .delay
chan_setbank 5
chan_setinstr 5
chan_end
.layer_15EB:
layer_note1 24, 0xc, 127
layer_note1 22, 0x48, 127
layer_end
.sound_general_cannon_up:
chan_setbank 6
chan_setinstr 10
chan_setlayer 0, .layer_15FA
chan_end
.layer_15FA:
layer_note1 44, 0xfa, 127
layer_end
.sound_general_grindel_spindel_roll:
chan_setbank 6
chan_setinstr 1
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_160C
chan_end
.layer_160C:
layer_note1 29, 0xc, 120
layer_note1 24, 0x24, 120
layer_end
.sound_general_explosion7:
chan_setbank 3
chan_setinstr 5
chan_setenvelope .envelope_3358
chan_setlayer 0, .layer_162D
chan_setlayer 1, .layer_1637
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_3358
chan_end
.layer_162D:
layer_delay 1
layer_note1 36, 0xc, 127
layer_note1 32, 0x96, 127
layer_end
.layer_1637:
layer_note1 24, 0x60, 127
layer_end
.sound_general_shake_coffin:
chan_setbank 6
chan_setinstr 15
chan_setenvelope .envelope_3304
chan_setlayer 0, .layer_1646
chan_end
.layer_1646:
layer_note1 31, 0xa, 127
layer_note1 43, 0x10, 127
layer_end
.sound_general_pyramid_top_spin:
chan_setbank 4
chan_setinstr 15
chan_setval 30
chan_call .set_reverb
chan_setlayer 0, .layer_1660
chan_setlayer 1, .layer_1669
chan_setlayer 2, .layer_1665
chan_end
.layer_1660:
layer_note1 20, 0x226, 0
layer_end
.layer_1665:
layer_delay 0x4
layer_transpose 244
.layer_1669:
layer_note1 27, 0x4f, 93
layer_note1 28, 0x41, 99
layer_note1 29, 0x36, 101
layer_note1 30, 0x31, 109
layer_note1 36, 0xe, 113
layer_note1 38, 0x3b, 123
layer_note1 32, 0x27, 105
layer_note1 35, 0x60, 92
layer_note1 32, 0xe, 100
layer_note1 36, 0xb, 105
layer_note1 39, 0x31, 116
layer_end
.sound_general_pyramid_top_explosion:
chan_setbank 4
chan_setinstr 15
chan_setval 30
chan_call .set_reverb
chan_setenvelope .envelope_338C
chan_setlayer 0, .layer_16A1
chan_setlayer 1, .layer_16AA
chan_setlayer 2, .layer_16A6
chan_end
.layer_16A1:
layer_note1 24, 0x12c, 127
layer_end
.layer_16A6:
layer_delay 0x4
layer_transpose 244
.layer_16AA:
layer_note1 46, 0xe, 116
layer_note1 44, 0xb, 121
layer_note1 48, 0x12, 101
layer_note1 41, 0xf, 109
layer_note1 43, 0xfa, 113
layer_end
.sound_general_race_gun_shot:
chan_setbank 5
chan_setinstr 0
chan_setval 127
chan_call .set_reverb
chan_setlayer 0, .layer_16CE
chan_setlayer 1, .layer_16CE
chan_setlayer 2, .layer_16D2
chan_end
.layer_16CE:
layer_note1 49, 0x3a, 127
layer_end
.layer_16D2:
layer_delay 0xa
layer_note1 48, 0x30, 85
layer_end
.sound_general_star_door_open:
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_16E3
chan_end
.layer_16E3:
layer_portamento 0x81, 51, 96
layer_note1 58, 0x40, 100
layer_end
.sound_general_star_door_close:
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_16F6
chan_end
.layer_16F6:
layer_portamento 0x82, 51, 96
layer_note1 58, 0x40, 100
layer_end
.sound_general_pound_rock:
chan_setbank 6
chan_setinstr 1
chan_setval 55
chan_call .set_reverb
chan_setlayer 0, .layer_170B
chan_end
.layer_170B:
layer_note1 27, 0x7, 127
layer_note1 15, 0x12, 127
layer_end
.sound_general_star_appears:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_171A
chan_end
.layer_171A:
layer_portamento 0x81, 43, 127
layer_note1 31, 0x7f, 115
layer_end
.sound_general_collect_1up:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setlayer 0, .layer_1734
chan_setdecayrelease 50
chan_setlayer 1, .layer_1732
chan_end
.layer_1732:
layer_delay 0x4
.layer_1734:
layer_transpose 24
layer_note1 31, 0xc, 100
layer_note1 34, 0xc, 100
layer_note1 43, 0xc, 100
layer_note1 39, 0xc, 100
layer_note1 41, 0xc, 100
layer_note1 46, 0x18, 100
layer_end
.sound_general_rotating_block_alert:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1751
chan_end
.layer_1751:
layer_call .layer_fn_1756
layer_transpose 252
.layer_fn_1756:
layer_note1 27, 0x5, 105
layer_portamento 0x81, 15, 255
layer_note1 8, 0xa, 100
layer_end
.sound_general_button_press:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1769
chan_end
.layer_1769:
layer_note1 8, 0x5, 127
layer_note1 18, 0x12, 127
layer_end
.sound_general_elevator_move:
chan_setbank 4
chan_setinstr 9
chan_setenvelope .envelope_33BC
chan_setlayer 0, .layer_177B
chan_end
.layer_177B:
layer_portamento 0x82, 5, 255
layer_note1 8, 0xa, 127
layer_end
.sound_general_swish_air:
chan_setbank 0
chan_setinstr 0
chan_setlayer 0, .layer_178B
chan_end
.layer_178B:
layer_note1 44, 0x6, 100
layer_portamento 0x81, 44, 255
layer_note1 32, 0x12, 100
layer_end
.sound_general_haunted_chair:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_17A1
chan_end
.layer_17A1:
layer_transpose 12
layer_portamento 0x85, 62, 255
layer_note1 38, 0x78, 93
layer_end
.sound_general_soft_landing:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_17B3
chan_end
.layer_17B3:
layer_note1 29, 0xc, 127
layer_end
.sound_general_haunted_chair_move:
chan_setbank 4
chan_setinstr 1
chan_setlayer 0, .layer_17C4
chan_setlayer 1, .layer_17C2
chan_end
.layer_17C2:
layer_delay 1
.layer_17C4:
layer_note1 34, 0x6, 127
layer_note1 33, 0x7, 127
layer_note1 33, 0x6, 127
layer_note1 34, 0x6, 127
layer_end
.sound_general_bowser_explode:
chan_setbank 6
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_17E8
chan_setval 1
chan_call .delay
chan_setenvelope .envelope_32D4
chan_setlayer 1, .layer_17F3
chan_setlayer 2, .layer_17EF
chan_end
.layer_17E8:
layer_setinstr 10
layer_transpose 24
layer_jump .layer_17F5
.layer_17EF:
layer_delay 0x2
layer_transpose 12
.layer_17F3:
layer_setinstr 0
.layer_17F5:
layer_portamento 0x83, 3, 255
layer_note1 15, 0x30, 100
layer_note1 17, 0x2c, 100
layer_note1 19, 0x28, 100
layer_note1 20, 0x24, 100
layer_note1 22, 0x20, 100
layer_note1 24, 0x1c, 100
layer_note1 26, 0x18, 100
layer_note1 27, 0x14, 100
layer_note1 29, 0x11, 100
layer_note1 31, 0xe, 100
layer_note1 32, 0xc, 100
.layer_181A:
layer_note1 34, 0xa, 100
layer_jump .layer_181A
layer_end
.sound_general_bowser_key:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_171A
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_33EC
chan_setlayer 1, .layer_137B
chan_setval 100
chan_call .delay
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1844
chan_end
.layer_1844:
layer_transpose 250
layer_portamento 0x81, 43, 127
layer_note1 31, 0xfa, 115
layer_end
.sound_general_bowser_platform:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_185C
chan_setlayer 1, .layer_185A
chan_end
.layer_185A:
layer_transpose 2
.layer_185C:
layer_note1 39, 0xc, 127
layer_jump .layer_1350
.sound_general_1up_appear:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_186A
chan_end
.layer_186A:
layer_portamento 0x83, 39, 128
layer_note1 42, 0x2d, 115
layer_note1 42, 0x2d, 115
layer_note1 42, 0x2d, 115
layer_note1 44, 0x7f, 115
layer_end
.sound_general_heart_spin:
chan_setbank 9
chan_setinstr 3
chan_setval 30
chan_call .set_reverb
chan_setlayer 0, .layer_1888
chan_end
.layer_1888:
layer_transpose 12
layer_portamento 0x83, 3, 255
layer_note1 27, 0xa, 85
layer_note1 32, 0xa, 85
layer_note1 39, 0xa, 85
layer_note1 44, 0xa, 85
layer_note1 51, 0xa, 85
layer_note1 56, 0xa, 85
layer_note1 51, 0xa, 45
layer_note1 56, 0xa, 35
layer_end
.sound_general_pound_wood_post:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_18B8
chan_delay 1
chan_setbank 4
chan_setinstr 9
chan_setlayer 1, .layer_1537
chan_end
.layer_18B8:
layer_portamento 0x1, 27, 0x28
layer_note1 32, 0x32, 120
layer_end
.sound_general_water_level_trig:
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_2DBF
chan_setval 9
chan_call .delay
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3454
chan_setlayer 0, .layer_2D26
chan_end
.sound_general_switch_door_open:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1539
chan_setval 12
chan_call .delay
chan_setbank 6
chan_setinstr 1
chan_setlayer 0, .layer_18EB
chan_end
.layer_18EB:
layer_portamento 0x82, 15, 255
layer_note1 31, 0x14, 127
layer_end
.sound_general_red_coin:
.ifdef VERSION_JP
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_1909
chan_setlayer 1, .layer_1902
chan_setlayer 2, .layer_1907
.else
.ifdef VERSION_EU
chan_setbank 9
chan_setinstr 3
.else
chan_setinstr 128
.endif
chan_setenvelope .envelope_3378
chan_setlayer 0, .layer_1907
chan_setlayer 1, .layer_1902
chan_setlayer 2, .layer_1909
.endif
chan_end
.layer_1902:
layer_transpose 7
layer_jump .layer_190B
.layer_1907:
layer_delay 0x6
.layer_1909:
layer_transpose 12
.layer_190B:
layer_note0 46, 0xc, 90, 20
layer_note0 45, 0xc, 90, 20
layer_note0 46, 0xc, 90, 20
layer_note0 58, 0x10, 100, 80
layer_note0 58, 0x10, 60, 80
layer_note0 58, 0x10, 40, 80
layer_note0 58, 0x10, 25, 80
layer_delay 0xa
layer_end
.sound_general_birds_fly_away:
chan_setbank 5
chan_setinstr 13
chan_setenvelope .envelope_33DC
chan_setval 20
chan_call .set_reverb
chan_setval 127
chan_iowriteval 7
chan_setlayer 0, .layer_195F
chan_setlayer 1, .layer_1986
chan_setlayer 2, .layer_1982
.chan_1942:
chan_setval 4
chan_call .delay
chan_ioreadval 7
chan_subtract 1
chan_beqz .chan_1957
chan_iowriteval 7
chan_writeseq_nextinstr 0, 1
chan_setvolscale 127
chan_jump .chan_1942
.chan_1957:
chan_setval 127
chan_call .delay
chan_jump .chan_1957
.layer_195F:
layer_setinstr 9
layer_note1 40, 0x6, 122
layer_note1 41, 0x4, 112
layer_note1 43, 0x5, 109
layer_note1 44, 0x6, 124
layer_note1 44, 0x4, 116
layer_note1 45, 0x7, 114
layer_delay 0x19
.layer_1975:
layer_note1 43, 0x7f, 122
layer_note1 43, 0xa, 127
layer_note1 43, 0x64, 114
layer_jump .layer_1975
layer_end
.layer_1982:
layer_transpose 4
layer_delay 0x2
.layer_1986:
layer_portamento 0x83, 39, 255
layer_loop 2
layer_note1 55, 0x6, 120
layer_note1 60, 0x9, 112
layer_delay 0x4
layer_loopend
layer_note1 56, 0x5, 125
layer_note1 62, 0xa, 109
layer_delay 0x5
layer_note1 56, 0x6, 123
layer_note1 62, 0x7, 119
layer_delay 0x8
.layer_19A5:
layer_loop 10
layer_note1 57, 0x5, 120
layer_note1 62, 0x8, 120
layer_delay 0x5
layer_loopend
layer_loop 10
layer_note1 59, 0x7, 115
layer_note1 60, 0x7, 113
layer_delay 0x2
layer_loopend
layer_loop 10
layer_note1 55, 0x8, 115
layer_note1 58, 0x6, 113
layer_delay 0x5
layer_loopend
layer_jump .layer_19A5
layer_end
.sound_general_right_answer:
chan_setbank 9
chan_setinstr 3
chan_setval 40
chan_call .set_reverb
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_19DA
chan_end
.layer_19DA:
layer_loop 2
layer_note1 62, 0x6, 110
layer_note1 62, 0x2, 45
layer_note1 58, 0x6, 110
layer_note1 58, 0x2, 45
layer_loopend
layer_end
.sound_general_metal_pound:
chan_setbank 7
chan_setinstr 1
chan_setlayer 0, .layer_1A00
chan_setlayer 1, .layer_19FE
chan_setval 1
chan_call .delay
chan_setbank 5
chan_setinstr 5
chan_end
.layer_19FE:
layer_transpose 250
.layer_1A00:
layer_note1 15, 0xc, 127
layer_note1 17, 0x3a, 127
layer_end
.sound_general_boing1:
chan_setbank 5
chan_setinstr 14
chan_setlayer 0, .layer_1A0F
chan_end
.layer_1A0F:
layer_portamento 0x82, 40, 127
layer_note1 38, 0x28, 100
layer_end
.sound_general_boing2:
chan_setbank 5
chan_setinstr 14
chan_setlayer 0, .layer_1A1F
chan_end
.layer_1A1F:
layer_portamento 0x82, 43, 127
layer_note1 39, 0x36, 100
layer_end
.sound_general_yoshi_walk:
chan_jump .sound_obj_koopa_the_quick_walk
.sound_general_enemy_alert1:
chan_jump .sound_obj_goomba_alert
.sound_general_yoshi_talk:
chan_setbank 0
chan_setinstr 3
chan_setlayer 0, .layer_1A35
chan_end
.layer_1A35:
layer_note1 39, 0x32, 127
layer_end
.sound_general_splattering:
chan_setbank 6
chan_setinstr 2
chan_setlayer 0, .layer_1A44
chan_setlayer 1, .layer_1A44
chan_end
.layer_1A44:
layer_transpose 7
layer_call .layer_fn_1A4B
layer_transpose 254
.layer_fn_1A4B:
layer_portamento 0x83, 31, 255
layer_note1 51, 0x6, 127
layer_note1 56, 0xc, 127
layer_end
.sound_general_boing3:
chan_setbank 9
chan_setinstr 6
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_1A66
chan_setlayer 1, .layer_1A66
chan_end
.layer_1A66:
layer_portamento 0x82, 39, 255
layer_note1 31, 0x60, 100
layer_end
.sound_general_grand_star:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1A79
chan_setlayer 1, .layer_1A7D
chan_end
.layer_1A79:
layer_transpose 3
layer_delay 0x5
.layer_1A7D:
layer_somethingon
layer_portamento 0x85, 31, 255
layer_note1 34, 0x12c, 127
layer_end
.sound_general_grand_star_jump:
chan_setbank 4
chan_setinstr 14
chan_setenvelope .envelope_3358
chan_setlayer 0, .layer_1AA0
chan_setval 1
chan_call .delay
chan_setenvelope .envelope_3358
chan_setlayer 1, .layer_1AAA
chan_setlayer 2, .layer_1AA8
chan_end
.layer_1AA0:
layer_portamento 0x81, 32, 64
layer_note1 38, 0x46, 127
layer_end
.layer_1AA8:
layer_delay 0x4
.layer_1AAA:
layer_delay 0x4
layer_portamento 0x81, 36, 40
layer_note1 41, 0xc, 127
layer_end
.ifdef VERSION_JP
.sound_general_boat_rock:
chan_setbank 9
chan_setinstr 0
chan_setenvelope .envelope_3438
chan_setvibratorate 25
chan_setvibratoextent 110
chan_setlayer 0, .layer_1943_jp
chan_setval 40
chan_call .delay
chan_end
.layer_1943_jp:
layer_portamento 0x1, 32, 0x7f
layer_note1 60, 0x28, 100
layer_end
.else
.sound_general_boat_rock:
chan_setbank 4
chan_setinstr 2
chan_setlayer 0, .layer_1AC1
chan_setlayer 1, .layer_1ABF
chan_end
.layer_1ABF:
layer_transpose 12
.layer_1AC1:
layer_portamento 0x81, 7, 255
layer_note1 15, 0x3c, 127
layer_portamento 0x81, 20, 200
layer_note1 7, 0x5a, 127
layer_end
.sound_general_vanish_sfx:
chan_setbank 9
chan_setinstr 3
chan_setvibratoextent 70
chan_setvibratorate 70
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_1AEB
chan_setlayer 1, .layer_1AE9
chan_setval 35
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_1AE9:
layer_transpose 1
.layer_1AEB:
layer_portamento 0x81, 19, 255
layer_note1 31, 0x32, 115
layer_end
.endif
.channel4_table:
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_elevator1
sound_ref .sound_env_droning1
sound_ref .sound_env_droning1
sound_ref .sound_env_wind1
sound_ref .sound_env_moving_sand_snow
sound_ref .chan_1BE5
sound_ref .sound_env_elevator2
sound_ref .sound_env_water
sound_ref .chan_1C46
sound_ref .sound_env_boat_rocking1
sound_ref .sound_env_elevator3
sound_ref .sound_env_elevator4
sound_ref .sound_env_movingsand
sound_ref .sound_env_merry_go_round_creaking
sound_ref .sound_env_wind2
sound_ref .sound_air_rough_slide
sound_ref .chan_1D42
sound_ref .sound_env_sliding
sound_ref .sound_env_star
sound_ref .chan_1D81
sound_ref .sound_env_water_drain
sound_ref .sound_env_metal_box_push
sound_ref .sound_env_sink_quicksand
sound_ref .sound_air_peach_twinkle
sound_ref .sound_env_elevator1
sound_ref .sound_env_droning1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_menu_enter_hole
sound_ref .sound_general_elevator_move
sound_ref .sound_env_elevator1
sound_ref .sound_env_droning1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
.sound_env_waterfall1:
chan_setbank 5
chan_setinstr 1
chan_setval 25
chan_call .set_reverb
.ifdef VERSION_JP
chan_setenvelope .envelope_32E4
.else
chan_setenvelope .envelope_32C4
.endif
chan_setlayer 0, .layer_1B53
chan_end
.layer_1B53:
layer_somethingon
.ifdef VERSION_JP
layer_delay 0x6
.else
layer_delay 0x4
.endif
.layer_1B56:
layer_note1 41, 0x12c, 95
layer_jump .layer_1B56
.sound_env_elevator1:
chan_setbank 5
chan_setinstr 2
chan_setlayer 0, .layer_1B65
chan_end
.layer_1B65:
layer_somethingon
.layer_1B66:
layer_note1 39, 0x12c, 90
layer_jump .layer_1B66
.sound_env_droning1:
chan_setbank 5
chan_setinstr 3
chan_setlayer 0, .layer_1B75
chan_end
.layer_1B75:
layer_somethingon
.layer_1B76:
layer_note1 44, 0x12c, 105
layer_jump .layer_1B76
.sound_env_wind1:
chan_setbank 5
chan_setinstr 6
chan_setdecayrelease 13
chan_setlayer 0, .layer_1B8A
chan_setlayer 1, .layer_1B8C
chan_end
.layer_1B8A:
layer_transpose 244
.layer_1B8C:
layer_somethingon
layer_portamento 0x85, 39, 255
.layer_1B91:
layer_note1 44, 0x18, 110
layer_note1 38, 0x3c, 110
layer_note1 47, 0xa, 110
layer_note1 49, 0x32, 110
layer_note1 40, 0x4b, 110
layer_note1 37, 0x14, 110
layer_note1 46, 0xc, 110
layer_note1 48, 0x1f, 110
layer_note1 55, 0x18, 110
layer_note1 46, 0x40, 110
layer_note1 36, 0xc, 110
layer_note1 39, 0xa, 110
layer_note1 36, 0xe, 110
layer_note1 39, 0xc, 110
layer_note1 32, 0x54, 110
layer_note1 39, 0xa, 110
layer_note1 36, 0x2b, 110
layer_note1 41, 0x60, 110
layer_note1 39, 0x22, 110
layer_jump .layer_1B91
.sound_env_moving_sand_snow:
chan_setbank 3
chan_setinstr 2
chan_setlayer 0, .layer_1BD5
chan_end
.layer_1BD5:
layer_somethingon
layer_portamento 0x85, 36, 255
.layer_1BDA:
layer_note1 34, 0x12c, 95
layer_note1 36, 0x12c, 95
layer_jump .layer_1BDA
.chan_1BE5:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_1BED
chan_end
.layer_1BED:
layer_somethingon
layer_note1 43, 0xc, 127
layer_portamento 0x81, 44, 255
layer_note1 43, 0x50, 127
.layer_1BF8:
layer_note1 43, 0x12c, 127
layer_jump .layer_1BF8
.sound_env_elevator2:
chan_setbank 5
chan_setinstr 2
chan_setlayer 0, .layer_1C07
chan_end
.layer_1C07:
layer_somethingon
.layer_1C08:
layer_note1 27, 0x12c, 100
layer_jump .layer_1C08
.sound_env_water:
chan_setbank 4
chan_setinstr 5
chan_setenvelope .envelope_32E4
chan_setdecayrelease 25
chan_setlayer 0, .layer_1C1C
chan_end
.layer_1C1C:
layer_transpose 6
layer_portamento 0x85, 39, 255
.layer_1C22:
layer_note1 39, 0x18, 127
layer_note1 31, 0x36, 127
layer_note1 43, 0xc, 127
layer_note1 36, 0x32, 127
layer_note1 27, 0x50, 127
layer_note1 36, 0x37, 127
layer_note1 34, 0x40, 127
layer_note1 32, 0x3d, 127
layer_note1 29, 0x4a, 127
layer_note1 32, 0x31, 127
layer_note1 38, 0x1f, 127
layer_jump .layer_1C22
.chan_1C46:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_1C4E
chan_end
.layer_1C4E:
layer_somethingon
layer_portamento 0x85, 39, 255
layer_note1 42, 0x3c, 127
.layer_1C56:
layer_note1 41, 0x3c, 127
layer_note1 42, 0x3c, 127
layer_jump .layer_1C56
.sound_env_boat_rocking1:
chan_setbank 4
chan_setinstr 2
chan_setdecayrelease 30
chan_setlayer 0, .layer_1C69
chan_end
.layer_1C69:
layer_portamento 0x81, 15, 255
.ifdef VERSION_JP
layer_note1 11, 0x1f4, 100
.else
layer_note1 11, 0x1f4, 127
.endif
layer_end
.sound_env_elevator3:
chan_setbank 5
chan_setinstr 5
chan_setenvelope .envelope_3368
chan_setval 45
chan_call .set_reverb
chan_setlayer 0, .layer_1C82
chan_end
.layer_1C82:
layer_call .layer_fn_1CA3
layer_delay 0xb
layer_call .layer_fn_1CA3
layer_delay 0x9
layer_call .layer_fn_1CA3
layer_delay 0x8
layer_call .layer_fn_1CA3
layer_delay 0x6
layer_call .layer_fn_1CA3
layer_delay 0x5
.layer_1C9B:
layer_call .layer_fn_1CA3
layer_delay 0x3
layer_jump .layer_1C9B
.layer_fn_1CA3:
layer_transpose 0
layer_setinstr 4
layer_note1 22, 0x6, 127
layer_transpose 36
layer_setinstr 5
layer_somethingon
layer_portamento 0x85, 51, 255
layer_note1 41, 0x5, 77
layer_delay 0x4
layer_disableportamento
layer_somethingoff
layer_end
.sound_env_elevator4:
chan_setbank 4
chan_setinstr 2
chan_setlayer 0, .layer_1CC3
chan_end
.layer_1CC3:
layer_portamento 0x81, 19, 10
layer_note1 8, 0x9, 127
layer_jump .layer_1CC3
.sound_env_movingsand:
chan_setbank 3
chan_setinstr 7
chan_setdecayrelease 5
chan_setlayer 0, .layer_1CE2
chan_setlayer 1, .layer_1CDA
chan_end
.layer_1CDA:
layer_somethingon
.layer_1CDB:
layer_note1 47, 0x1f4, 90
layer_jump .layer_1CDB
.layer_1CE2:
layer_somethingon
.layer_1CE3:
layer_note1 46, 0x1f4, 90
layer_jump .layer_1CE3
.sound_env_merry_go_round_creaking:
chan_setbank 4
chan_setinstr 2
chan_setdecayrelease 30
chan_setlayer 0, .layer_1CF9
chan_setlayer 1, .layer_1CF7
chan_end
.layer_1CF7:
layer_transpose 6
.layer_1CF9:
layer_portamento 0x85, 7, 255
layer_note1_long 13, 0x46, 120
layer_jump .layer_1CF9
.sound_env_wind2:
chan_setbank 5
chan_setinstr 6
chan_setdecayrelease 13
chan_setlayer 0, .layer_1D11
chan_setlayer 1, .layer_1D13
chan_end
.layer_1D11:
layer_transpose 250
.layer_1D13:
layer_somethingon
layer_portamento 0x85, 34, 255
.layer_1D18:
layer_note1 51, 0x18, 110
layer_note1 43, 0x63, 110
layer_note1 47, 0xa, 110
layer_note1 49, 0x32, 110
layer_note1 41, 0x4b, 110
layer_note1 46, 0xc, 110
layer_note1 48, 0x1f, 110
layer_note1 55, 0x7f, 110
layer_note1 46, 0x63, 110
layer_note1 43, 0xa, 110
layer_note1 39, 0xc, 110
layer_note1 41, 0x60, 110
layer_note1 39, 0x22, 110
layer_jump .layer_1D18
.chan_1D42:
chan_setbank 4
chan_setinstr 2
chan_setbank 6
chan_setenvelope .envelope_3314
chan_setdecayrelease 200
chan_setlayer 0, .layer_1D51
chan_end
.layer_1D51:
layer_transpose 3
.layer_1D53:
layer_note0 62, 0x2, 127, 127
layer_jump .layer_1D53
.sound_env_sliding:
chan_setbank 3
chan_setinstr 1
chan_setenvelope .envelope_32E4
chan_setdecayrelease 15
chan_setlayer 0, .layer_1D67
chan_end
.layer_1D67:
layer_somethingon
.layer_1D68:
layer_note1 44, 0x12c, 95
layer_jump .layer_1D68
.sound_env_star:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1D77
chan_end
.layer_1D77:
layer_portamento 0x81, 38, 127
layer_note1 39, 0x9, 127
layer_jump .layer_1D77
.chan_1D81:
chan_setval 50
chan_call .set_reverb
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_1DA5
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 15
chan_setlayer 1, .layer_1DAD
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 15
chan_setdecayrelease 10
chan_end
.layer_1DA5:
layer_note1 21, 0xc, 127
layer_note1 18, 0x226, 127
layer_end
.layer_1DAD:
layer_transpose 24
layer_portamento 0x82, 19, 255
layer_note1 20, 0x1f4, 127
layer_end
.sound_env_water_drain:
chan_setbank 3
chan_setinstr 2
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_1DD4
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 5
chan_setdecayrelease 20
chan_setlayer 1, .layer_1DE4
chan_setlayer 2, .layer_1DE2
chan_end
.layer_1DD4:
layer_transpose 244
layer_somethingon
layer_portamento 0x82, 39, 255
.layer_1DDB:
layer_note1 46, 0x2710, 80
layer_jump .layer_1DDB
.layer_1DE2:
layer_transpose 6
.layer_1DE4:
layer_portamento 0x83, 20, 255
layer_note1 15, 0x5a, 127
layer_note1 32, 0x2d, 127
layer_note1 29, 0x46, 127
layer_note1 24, 0x78, 127
layer_note1 32, 0x44, 127
layer_note1 24, 0x74, 127
layer_transpose 7
layer_jump .layer_1DE4
.sound_env_metal_box_push:
chan_setbank 6
chan_setinstr 1
chan_setlayer 0, .layer_1E0C
chan_setlayer 1, .layer_1E12
chan_setdecayrelease 127
chan_end
.layer_1E0C:
layer_note1 24, 0xc, 85
layer_jump .layer_1E0C
.layer_1E12:
layer_setinstr 15
.layer_1E14:
layer_note1 39, 0x10, 115
layer_jump .layer_1E14
.sound_env_sink_quicksand:
chan_setbank 3
chan_setinstr 6
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_1E28
chan_setlayer 1, .layer_1E28
chan_end
.layer_1E28:
layer_portamento 0x81, 38, 80
layer_somethingon
.layer_1E2D:
layer_note1 35, 0x12c, 100
layer_jump .layer_1E2D
layer_end
.sound_air_peach_twinkle:
chan_setbank 5
chan_setinstr 15
chan_setenvelope .envelope_32E4
chan_setdecayrelease 8
chan_setlayer 0, .layer_1E42
chan_end
.layer_1E42:
layer_somethingon
layer_portamento 0x82, 20, 255
.layer_1E47:
layer_note1 43, 0x1b58, 63
layer_jump .layer_1E47
.channel59_table:
sound_ref .sound_obj_sushi_shark_water_sound
sound_ref .sound_obj_mri_shoot
sound_ref .sound_obj_baby_penguin_walk
sound_ref .sound_obj_bowser_walk
sound_ref .sound_obj_bowser_roar
sound_ref .sound_obj_bowser_tail_pickup
sound_ref .sound_obj_bowser_defeated
sound_ref .sound_obj_bowser_spinning
sound_ref .sound_obj_bowser_inhaling
sound_ref .sound_obj_big_penguin_walk
sound_ref .sound_obj_boo_bounce_top
sound_ref .sound_obj_boo_laugh_short
sound_ref .sound_obj_thwomp
sound_ref .sound_obj_cannon1
sound_ref .sound_obj_cannon2
sound_ref .sound_obj_cannon3
sound_ref .sound_obj_piranha_plant_bite
sound_ref .sound_obj_piranha_plant_dying
sound_ref .sound_obj_jump_walk_water
sound_ref .chan_20B2
sound_ref .sound_obj_mri_death
sound_ref .sound_obj_pounding1
sound_ref .sound_obj_king_bobomb
sound_ref .sound_obj_bully_metal
sound_ref .sound_obj_bully_explode
sound_ref .sound_obj_bowser_puzzle_piece_move
sound_ref .sound_obj_pounding_cannon
sound_ref .sound_obj_bully_walk
sound_ref .sound_obj_bully_attacked
sound_ref .chan_2177
sound_ref .chan_218E
sound_ref .sound_obj_baby_penguin_dive
sound_ref .sound_obj_goomba_walk
sound_ref .sound_obj_ukiki_chatter_long
sound_ref .sound_obj_monty_mole_lakitu_attack
sound_ref .chan_21FF
sound_ref .sound_obj_dying_enemy1
sound_ref .sound_obj_cannon4
sound_ref .sound_obj_dying_enemy2
sound_ref .sound_obj_bobomb_walk
sound_ref .sound_obj_something_landing
sound_ref .sound_obj_diving_in_water
sound_ref .sound_obj_snow_sand1
sound_ref .sound_obj_snow_sand2
sound_ref .sound_obj_default_death
sound_ref .sound_obj_big_penguin_yell
sound_ref .sound_obj_water_bomb_bouncing
sound_ref .sound_obj_goomba_alert
sound_ref .sound_obj_stomped
sound_ref .chan_233D
sound_ref .sound_obj_diving_into_water
sound_ref .sound_obj_piranha_plant_shrink
sound_ref .sound_obj_koopa_the_quick_walk
sound_ref .sound_obj_koopa_walk
sound_ref .sound_obj_bully_walking
sound_ref .sound_obj_dorrie
sound_ref .sound_obj_bowser_laugh
sound_ref .sound_obj_ukiki_chatter_short
sound_ref .sound_obj_ukiki_chatter_idle
sound_ref .sound_obj_ukiki_step_default
sound_ref .sound_obj_ukiki_step_leaves
sound_ref .sound_obj_koopa_talk
sound_ref .sound_obj_koopa_damage
sound_ref .sound_obj_klepto1
sound_ref .sound_obj_klepto2
sound_ref .sound_obj_king_bobomb_talk
sound_ref .sound_obj_king_bobomb_damage
sound_ref .sound_obj_scuttlebug_walk
sound_ref .sound_obj_scuttlebug_alert
sound_ref .sound_obj_baby_penguin_yell
sound_ref .sound_obj_king_bobomb_jump
sound_ref .sound_obj_king_whomp_death
sound_ref .sound_obj_boo_laugh_long
sound_ref .sound_obj_swoop
sound_ref .sound_obj_eel
sound_ref .sound_obj_eyerok_show_eye
sound_ref .sound_obj_mr_blizzard_alert
sound_ref .sound_obj_snufit_shoot
sound_ref .sound_obj_skeeter_walk
sound_ref .sound_obj_walking_water
sound_ref .sound_general_bird_chirp2
sound_ref .sound_obj_bird_chirp3
sound_ref .sound_obj_bird_chirp1
sound_ref .sound_air_castle_outdoors_ambient
sound_ref .sound_obj_piranha_plant_appear
sound_ref .sound_obj_flame_blown
sound_ref .sound_obj_mad_piano_chomping
sound_ref .sound_obj_large_bully_attacked
sound_ref .sound_obj_bobomb_buddy_talk
sound_ref .chan_26A9
sound_ref .sound_obj_eyerok_sound_short
sound_ref .sound_obj_eyerok_sound_long
sound_ref .sound_obj_wiggler_high_pitch
sound_ref .sound_obj_heaveho_tossed
sound_ref .sound_obj_wiggler_death
sound_ref .sound_obj_bowser_intro_laugh
sound_ref .sound_obj_enemy_death_high
sound_ref .sound_obj_enemy_death_low
sound_ref .sound_obj_swoop_death
sound_ref .sound_obj_koopa_flyguy_pokey_death
sound_ref .sound_obj_snowman_bounce
sound_ref .sound_obj_snowman_explode
sound_ref .sound_obj_bowser_teleport
sound_ref .sound_obj_monty_mole_appear
sound_ref .sound_obj_pounding_loud
sound_ref .sound_obj_boss_dialog_grunt
sound_ref .sound_obj_mips_rabbit
sound_ref .sound_obj_mri_spinning
sound_ref .sound_obj_mips_rabbit_water
sound_ref .sound_obj_eyerok_explode
sound_ref .sound_obj_chuckya_death
sound_ref .sound_obj_wiggler_talk
sound_ref .sound_obj_wiggler_attacked
sound_ref .sound_obj_wiggler_low_pitch
sound_ref .sound_obj_snufit_skeeter_death
sound_ref .sound_obj_bubba_chomp
sound_ref .sound_obj_enemy_defeat_shrink
sound_ref .sound_obj_bowser_tail_pickup
sound_ref .sound_obj_bowser_defeated
sound_ref .sound_obj_bowser_spinning
sound_ref .sound_obj_klepto2
sound_ref .sound_obj_king_bobomb_talk
sound_ref .sound_obj_baby_penguin_walk
sound_ref .sound_obj_bowser_walk
sound_ref .sound_obj_bowser_roar
sound_ref .sound_obj_bowser_tail_pickup
sound_ref .sound_obj_bowser_defeated
sound_ref .sound_obj_bowser_spinning
.sound_general_swish_water:
chan_setbank 6
chan_setinstr 5
chan_setlayer 0, .layer_1F56
chan_end
.layer_1F56:
layer_note1 27, 0x8, 90
layer_portamento 0x81, 43, 255
layer_note1 27, 0x21, 90
layer_end
.sound_obj_mri_shoot:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_1F72
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 0
chan_end
.layer_1F72:
layer_note1 43, 0xf, 90
layer_portamento 0x82, 27, 255
layer_note1 36, 0xb, 90
layer_end
.sound_obj_baby_penguin_walk:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_1F85
chan_end
.layer_1F85:
layer_portamento 0x81, 43, 255
layer_note1 48, 0x30, 110
layer_end
.sound_obj_bowser_walk:
chan_setbank 6
chan_setinstr 1
chan_setval 60
chan_call .set_reverb
chan_setlayer 0, .layer_1F9D
chan_setlayer 1, .layer_1FA6
chan_end
.layer_1F9D:
layer_note1 36, 0x8, 120
layer_note1 35, 0x28, 120
layer_delay 0x30
layer_end
.layer_1FA6:
layer_delay 0x18
layer_note1 0, 0x1e, 95
layer_end
.sound_obj_bowser_roar:
chan_setbank 6
chan_setinstr 2
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_1FC0
chan_setlayer 1, .layer_1FBC
chan_end
.layer_1FBC:
layer_delay 0x3
layer_transpose 5
.layer_1FC0:
layer_note1 39, 0x7f, 127
layer_end
.sound_obj_bowser_tail_pickup:
chan_setbank 6
chan_setinstr 2
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_1FD8
chan_setlayer 1, .layer_1FD4
chan_end
.layer_1FD4:
layer_delay 0x3
layer_transpose 5
.layer_1FD8:
layer_portamento 0x81, 45, 255
layer_note1 33, 0x30, 127
layer_end
.sound_obj_bowser_defeated:
chan_setbank 6
chan_setinstr 4
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_1FED
chan_end
.layer_1FED:
layer_note1 32, 0x104, 127
layer_end
.sound_obj_bowser_spinning:
chan_setbank 6
chan_setinstr 5
chan_setlayer 0, .layer_1FFA
chan_end
.layer_1FFA:
layer_note1 32, 0x28, 127
layer_end
.sound_obj_bowser_inhaling:
chan_setbank 6
chan_setinstr 6
chan_setlayer 0, .layer_2006
chan_end
.layer_2006:
layer_note1 36, 0x5a, 127
layer_end
.sound_obj_big_penguin_walk:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_2012
chan_end
.layer_2012:
layer_portamento 0x81, 39, 255
layer_note1 36, 0x26, 100
layer_end
.sound_obj_boo_bounce_top:
chan_setbank 6
chan_setinstr 8
chan_setlayer 0, .layer_2022
chan_end
.layer_2022:
layer_note1 39, 0x18, 127
layer_end
.sound_obj_boo_laugh_short:
chan_setbank 6
chan_setinstr 9
chan_setlayer 0, .layer_202E
chan_end
.layer_202E:
layer_note1 50, 0xa, 127
layer_note1 55, 0xa, 127
layer_end
.sound_obj_thwomp:
chan_setbank 8
chan_setinstr 13
chan_setlayer 0, .layer_204E
chan_end
.layer_204E:
layer_note1 37, 0x7f, 127
layer_end
.layer_2055:
layer_note1 31, 0x2a, 127
layer_end
.sound_obj_cannon1:
chan_setbank 6
chan_setinstr 10
chan_setlayer 0, .layer_2061
chan_end
.layer_2061:
layer_note1 39, 0xd2, 127
layer_end
.sound_obj_cannon2:
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_206E
chan_end
.layer_206E:
layer_note1 39, 0xd2, 127
layer_end
.sound_obj_cannon3:
chan_setbank 6
chan_setinstr 12
chan_setlayer 0, .layer_207B
chan_end
.layer_207B:
layer_note1 39, 0x24, 127
layer_end
.sound_obj_piranha_plant_bite:
chan_jump .sound_mario_snoring1
chan_setinstr 11
chan_setlayer 0, .layer_2087
chan_end
.layer_2087:
layer_portamento 0x81, 33, 255
layer_note1 57, 0x4, 127
layer_transpose 252
layer_portamento 0x81, 57, 255
layer_note1 33, 0x6, 127
layer_delay 0x14
layer_end
.sound_obj_piranha_plant_dying:
chan_setbank 6
chan_setinstr 14
chan_setlayer 0, .layer_20A2
chan_end
.layer_20A2:
layer_note1 0, 0x00, 110
layer_end
.sound_obj_jump_walk_water:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_20AE
chan_end
.layer_20AE:
layer_note1 59, 0x24, 105
layer_end
.chan_20B2:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_20BA
chan_end
.layer_20BA:
layer_note1 39, 0x4c, 127
layer_end
.sound_obj_mri_death:
chan_setbank 7
chan_setinstr 0
chan_setlayer 0, .layer_20C6
chan_end
.layer_20C6:
layer_note1 39, 0x18, 105
layer_end
.sound_obj_pounding1:
chan_setbank 6
chan_setinstr 1
chan_setlayer 0, .layer_20D2
chan_end
.layer_20D2:
layer_portamento 0x81, 44, 255
.ifdef VERSION_JP
layer_note1 36, 0x18, 90
.else
layer_note1 36, 0x18, 115
.endif
layer_delay 0x32
layer_end
.sound_obj_king_bobomb:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_20F0
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 1
chan_setlayer 1, .layer_20F4
chan_end
.layer_20F0:
layer_note1 31, 0x26, 127
layer_end
.layer_20F4:
.ifdef VERSION_JP
layer_note1 38, 0x8, 120
layer_note1 33, 0x1e, 120
.else
layer_note1 38, 0x8, 127
layer_note1 33, 0x1e, 127
.endif
layer_end
.sound_obj_bully_metal:
chan_setbank 7
chan_setinstr 1
chan_setlayer 0, .layer_2103
chan_end
.layer_2103:
layer_note1 39, 0x24, 120
layer_end
.sound_obj_bully_explode:
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_33EC
chan_setlayer 0, .layer_211C
chan_setlayer 1, .layer_2126
chan_setlayer 2, .layer_2124
chan_setval 1
chan_setdecayrelease 10
chan_end
.layer_211C:
layer_portamento 0x81, 51, 255
layer_note1 20, 0x2e, 115
layer_end
.layer_2124:
layer_transpose 3
.layer_2126:
layer_setinstr 5
layer_delay 0xa
layer_note1 48, 0x23, 127
layer_end
.sound_obj_bowser_puzzle_piece_move:
chan_setbank 7
chan_setinstr 2
chan_setlayer 0, .layer_2136
chan_end
.layer_2136:
layer_note1 39, 0xc, 105
layer_end
.sound_obj_pounding_cannon:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_2142
chan_end
.layer_2142:
layer_note1 39, 0x68, 127
layer_end
.sound_obj_bully_walk:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_214E
chan_end
.layer_214E:
layer_portamento 0x82, 38, 127
layer_note1 51, 0x4, 80
layer_delay 0x1e
layer_end
.sound_obj_bully_attacked:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_2160
chan_end
.layer_2160:
layer_portamento 0x83, 33, 255
layer_note0 40, 0xf, 127, 127
layer_note1 26, 0x20, 127
layer_end
.layer_unused_216C:
layer_portamento 0x83, 27, 255
layer_note1 22, 0x9, 127
layer_note1 24, 0x1c, 127
layer_end
.chan_2177:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_217F
chan_end
.layer_217F:
layer_portamento 0x81, 27, 255
layer_note1 48, 0x9, 100
layer_portamento 0x81, 27, 255
layer_note1 48, 0x5, 100
layer_end
.chan_218E:
chan_setbank 6
chan_setinstr 5
chan_setlayer 0, .layer_2196
chan_end
.layer_2196:
layer_note1 36, 0x8, 90
layer_portamento 0x81, 43, 255
layer_note1 27, 0x14, 90
layer_end
.sound_obj_baby_penguin_dive:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_21A9
chan_end
.layer_21A9:
layer_portamento 0x81, 39, 255
layer_note1 44, 0xc, 110
layer_portamento 0x81, 46, 255
layer_note1 58, 0x30, 110
layer_end
.sound_obj_goomba_walk:
chan_setbank 6
chan_setinstr 12
chan_setlayer 0, .layer_21C9
chan_setval 1
chan_call .delay
chan_setbank 0
chan_setinstr 4
chan_end
.layer_21C9:
layer_portamento 0x82, 24, 255
layer_note1 12, 0x4, 100
layer_note1 51, 0x8, 80
layer_delay 0x1e
layer_end
.sound_obj_ukiki_chatter_long:
chan_setbank 7
chan_setinstr 7
chan_setdecayrelease 15
chan_setlayer 0, .layer_21E0
chan_end
.layer_21E0:
layer_note1 39, 0x30, 127
layer_end
.sound_obj_monty_mole_lakitu_attack:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_21F4
chan_end
.layer_21F4:
layer_portamento 0x85, 48, 255
layer_note1 60, 0x7, 115
layer_note1 39, 0x23, 115
layer_end
.chan_21FF:
chan_setbank 4
chan_setinstr 13
chan_setlayer 0, .layer_2207
chan_end
.layer_2207:
layer_portamento 0x81, 27, 255
layer_note1 3, 0x14, 115
layer_delay 0x1e
layer_end
.sound_obj_dying_enemy1:
chan_setbank 7
chan_setinstr 0
chan_setlayer 0, .layer_2219
chan_end
.layer_2219:
layer_note1 39, 0x9f, 255
layer_end
.sound_obj_cannon4:
chan_setbank 7
chan_setinstr 3
chan_setval 15
chan_call .set_reverb
chan_setlayer 0, .layer_2231
chan_end
.layer_2231:
layer_note1 48, 0x55, 127
layer_end
.sound_obj_dying_enemy2:
chan_setbank 7
chan_setinstr 8
chan_setlayer 0, .layer_223D
chan_end
.layer_223D:
layer_note1 44, 0xc, 100
layer_portamento 0x81, 44, 255
layer_note1 32, 0x18, 105
layer_end
.sound_obj_bobomb_walk:
chan_setbank 9
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_2253
chan_end
.layer_2253:
layer_portamento 0x83, 46, 255
layer_note1 27, 0x5, 127
layer_note1 32, 0x3, 127
layer_delay 0x22
layer_end
.sound_obj_something_landing:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_226B
chan_end
.layer_226B:
layer_somethingon
layer_portamento 0x85, 62, 255
layer_note1 50, 0x24, 93
layer_note1 26, 0x3c, 93
layer_end
.sound_obj_diving_in_water:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_2288
chan_setval 1
chan_call .delay
chan_setbank 2
chan_setinstr 0
chan_end
.layer_2288:
layer_note1 62, 0x4, 105
layer_portamento 0x81, 43, 200
layer_note1 36, 0x4e, 127
layer_end
.sound_obj_snow_sand1:
chan_setbank 3
chan_setinstr 5
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_229E
chan_end
.layer_229E:
layer_note1 41, 0x6, 100
layer_note1 24, 0x1c, 100
layer_end
.sound_obj_snow_sand2:
chan_setbank 3
chan_setinstr 5
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_22B0
chan_end
.layer_22B0:
layer_note1 36, 0x5, 100
layer_note1 44, 0x18, 100
layer_end
.sound_obj_default_death:
chan_setbank 0
chan_setinstr 4
chan_setenvelope .envelope_32D4
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_22C7
chan_end
.layer_22C7:
layer_somethingon
layer_portamento 0x81, 39, 255
layer_note1 62, 0x1b, 107
layer_delay 0x12
layer_end
.sound_obj_big_penguin_yell:
chan_setbank 7
chan_setinstr 10
chan_setlayer 0, .layer_22DA
chan_end
.layer_22DA:
layer_somethingon
layer_portamento 0x85, 41, 255
layer_note1 45, 0x28, 127
layer_note1 41, 0xf, 127
layer_end
.sound_obj_water_bomb_bouncing:
chan_setbank 7
chan_setinstr 11
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_22F3
chan_end
.layer_unused_22F1:
layer_transpose 244
.layer_22F3:
layer_somethingon
layer_portamento 0x85, 39, 255
layer_note1 32, 0xc, 127
layer_note1 39, 0x60, 127
layer_end
.sound_obj_goomba_alert:
chan_setbank 9
chan_setinstr 3
chan_setval 20
chan_call .set_reverb
chan_setenvelope .envelope_33EC
chan_setlayer 0, .layer_230F
chan_end
.layer_230F:
layer_transpose 232
layer_somethingon
layer_portamento 0x85, 25, 255
layer_note1 3, 0xf, 85
layer_transpose 0
layer_note1 51, 0x1c, 85
layer_delay 0x19
layer_end
.sound_obj_stomped:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_232C
chan_end
.layer_232C:
layer_transpose 253
layer_somethingon
layer_portamento 0x85, 24, 255
layer_note1 17, 0xa, 100
layer_note1 32, 0xa, 100
layer_note1 27, 0x6, 100
layer_end
.chan_233D:
chan_setbank 6
chan_setinstr 5
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_2348
chan_end
.layer_2348:
layer_call .layer_fn_2353
layer_delay 0x14
layer_end
.layer_fn_2353:
layer_portamento 0x85, 52, 255
layer_note1 48, 0x4, 115
layer_note1 52, 0x2, 115
layer_delay 0x2
layer_disableportamento
layer_end
.sound_obj_diving_into_water:
chan_setbank 2
chan_setlayer 0, .layer_236A
chan_setlayer 1, .layer_2374
chan_end
.layer_236A:
layer_setinstr 0
layer_portamento 0x82, 44, 255
layer_note1 43, 0x54, 100
layer_end
.layer_2374:
layer_setinstr 1
layer_portamento 0x82, 32, 255
layer_note1 31, 0x54, 100
layer_end
.sound_obj_piranha_plant_shrink:
chan_setbank 3
chan_setinstr 0
chan_setenvelope .envelope_3324
chan_setlayer 0, .layer_2389
chan_end
.layer_2389:
layer_portamento 0x81, 62, 255
layer_note1 38, 0x7f, 117
layer_end
.sound_obj_koopa_the_quick_walk:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_2399
chan_end
.layer_2399:
layer_note1 27, 0x6, 100
layer_note1 29, 0x3, 70
layer_delay 0x1e
layer_end
.sound_obj_koopa_walk:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_23AA
chan_end
.layer_23AA:
layer_note1 20, 0x4, 100
layer_delay 0x1e
layer_end
.sound_obj_bully_walking:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_23B8
chan_end
.layer_23B8:
layer_portamento 0x82, 29, 255
layer_note1 46, 0xc, 80
layer_end
.sound_obj_dorrie:
chan_setbank 6
chan_setinstr 4
chan_setenvelope .envelope_32F4
chan_setlayer 0, .layer_23CD
chan_end
.layer_unused_23CB:
layer_transpose 12
.layer_23CD:
layer_somethingon
layer_portamento 0x85, 36, 255
layer_note1 48, 0x8, 100
layer_note1 45, 0x4, 100
layer_note1 48, 0xa, 100
layer_note1 41, 0x48, 100
layer_end
.sound_obj_bowser_laugh:
chan_setbank 6
chan_setinstr 9
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_23EF
chan_setlayer 1, .layer_23EF
chan_end
.layer_23EF:
layer_portamento 0x81, 20, 255
layer_note1 26, 0x12c, 127
layer_end
.sound_obj_ukiki_chatter_short:
chan_setbank 7
chan_setinstr 7
chan_setlayer 0, .layer_2400
chan_end
.layer_2400:
layer_portamento 0x81, 32, 221
layer_note1 34, 0xa, 115
layer_end
.sound_obj_ukiki_chatter_idle:
chan_setbank 7
chan_setinstr 7
chan_setlayer 0, .layer_2410
chan_end
.layer_2410:
layer_portamento 0x81, 34, 221
layer_note1 38, 0xc, 127
layer_portamento 0x82, 34, 221
layer_note1 39, 0x12, 127
layer_end
.sound_obj_ukiki_step_default:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_2427
chan_end
.layer_2427:
layer_portamento 0x81, 58, 255
layer_note1 52, 0x6, 105
layer_end
.sound_obj_ukiki_step_leaves:
chan_setbank 0
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_243A
chan_end
.layer_243A:
layer_note1 43, 0x6, 90
layer_note1 44, 0x6, 90
layer_end
.sound_obj_koopa_talk:
chan_setbank 7
chan_setinstr 8
chan_setlayer 0, .layer_2449
chan_end
.layer_2449:
layer_transpose 248
layer_call .layer_fn_244E
.layer_fn_244E:
layer_portamento 0x85, 44, 255
layer_note1 51, 0x9, 100
layer_note1 39, 0xc, 100
layer_end
.sound_obj_koopa_damage:
chan_setbank 7
chan_setinstr 8
chan_setlayer 0, .layer_2461
chan_end
.layer_2461:
layer_transpose 10
layer_portamento 0x83, 32, 255
layer_note1 39, 0x6, 105
layer_note1 27, 0x12, 105
layer_end
.sound_obj_klepto1:
chan_setbank 7
chan_setinstr 9
chan_setlayer 0, .layer_2476
chan_end
.layer_2476:
layer_somethingon
layer_portamento 0x83, 39, 255
layer_note1 41, 0x6, 127
layer_note1 37, 0x24, 127
layer_end
.sound_obj_klepto2:
chan_setbank 7
chan_setinstr 9
chan_setlayer 0, .layer_248A
chan_end
.layer_248A:
layer_portamento 0x81, 48, 255
layer_note1 40, 0x24, 127
layer_end
.sound_obj_king_bobomb_talk:
chan_setbank 7
chan_setinstr 9
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_249F
chan_end
.layer_249F:
layer_transpose 251
layer_call .layer_fn_24AF
layer_delay 0xb
layer_transpose 248
layer_call .layer_fn_24AF
layer_delay 0xa
layer_transpose 246
.layer_fn_24AF:
layer_portamento 0x85, 29, 255
layer_note1 24, 0x2, 127
layer_note1 41, 0x10, 127
layer_end
.sound_obj_king_bobomb_damage:
chan_setbank 7
chan_setinstr 9
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_24C7
chan_end
.layer_24C7:
layer_note1 0, 0, 0
layer_end
.sound_obj_scuttlebug_walk:
chan_setbank 7
chan_setinstr 2
chan_setlayer 0, .layer_24DC
chan_end
.layer_24DC:
layer_note1 44, 0x4, 127
layer_delay 0x14
layer_end
.sound_obj_scuttlebug_alert:
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_24EA
chan_end
.layer_24EA:
layer_portamento 0x81, 24, 255
layer_note1 53, 0x12, 80
layer_end
.sound_obj_baby_penguin_yell:
chan_setbank 7
chan_setinstr 10
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_24FD
chan_end
.layer_24FD:
layer_note1 50, 0x8, 105
layer_portamento 0x82, 46, 255
layer_note1 50, 0x30, 105
layer_end
.sound_obj_king_bobomb_jump:
chan_setbank 6
chan_setinstr 1
chan_setlayer 0, .layer_2510
chan_end
.layer_2510:
layer_portamento 0x81, 27, 255
layer_note1 43, 0x1e, 127
layer_end
.sound_obj_king_whomp_death:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_252C
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 12
chan_setlayer 1, .layer_26D7
chan_end
.layer_252C:
layer_note1 34, 0xaf, 127
layer_end
.sound_obj_boo_laugh_long:
chan_setbank 6
chan_setinstr 9
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_253E
chan_end
.layer_253E:
layer_note1 55, 0x32, 127
layer_end
.sound_obj_swoop:
chan_setbank 7
chan_setinstr 7
chan_setlayer 0, .layer_254A
chan_end
.layer_254A:
layer_portamento 0x82, 51, 127
layer_note1 48, 0x6, 127
layer_end
.sound_obj_eel:
chan_setbank 6
chan_setinstr 2
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_2564
chan_setlayer 1, .layer_2562
chan_end
.layer_2562:
layer_delay 0x4
.layer_2564:
layer_somethingon
layer_portamento 0x85, 31, 255
layer_note1 34, 0x18, 127
layer_note1 17, 0x48, 127
layer_end
.sound_obj_eyerok_show_eye:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_257D
chan_setlayer 1, .layer_257B
chan_end
.layer_257B:
layer_transpose 4
.layer_257D:
layer_jump .layer_11BB
.sound_obj_mr_blizzard_alert:
chan_setbank 9
chan_setinstr 3
chan_setval 24
chan_call .set_reverb
chan_setenvelope .envelope_3428
chan_setvibratoextent 80
chan_setvibratorate 60
chan_setlayer 0, .layer_259B
chan_setval 30
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_259B:
layer_somethingon
layer_portamento 0x85, 15, 255
layer_note1 3, 0x7, 100
layer_note1 36, 0x18, 100
layer_end
.sound_obj_snufit_shoot:
chan_setbank 6
chan_setinstr 0
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_25B2
chan_end
.layer_25B2:
layer_somethingon
layer_portamento 0x81, 44, 255
layer_note1 51, 0x8, 118
layer_end
.sound_obj_skeeter_walk:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_25CC
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 2
chan_end
.layer_25CC:
layer_portamento 0x81, 3, 255
layer_note1 39, 0x5, 127
layer_portamento 0x81, 27, 255
layer_note1 49, 0x6, 127
layer_end
.sound_obj_walking_water:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_25EC
chan_setval 1
chan_call .delay
chan_setbank 2
chan_setinstr 1
chan_end
.layer_25EC:
layer_portamento 0x81, 3, 255
layer_note1 39, 0x5, 127
layer_portamento 0x83, 36, 255
layer_note1 48, 0x6, 92
layer_note1 55, 0x30, 92
layer_end
.sound_obj_piranha_plant_appear:
chan_setbank 3
chan_setinstr 0
chan_setenvelope .envelope_3324
chan_setlayer 0, .layer_2609
chan_end
.layer_2609:
layer_portamento 0x82, 62, 255
layer_note1 38, 0x60, 117
layer_end
.sound_obj_flame_blown:
chan_setbank 7
chan_setinstr 5
chan_setenvelope .envelope_32F4
chan_setlayer 0, .layer_261C
chan_end
.layer_261C:
layer_portamento 0x85, 41, 255
layer_note1 36, 0x18, 127
layer_end
.sound_obj_mad_piano_chomping:
chan_call .sound_obj_piranha_plant_bite
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 13
chan_setlayer 1, .layer_2655
chan_setlayer 2, .layer_2659
chan_setval 11
chan_call .delay
chan_call .sound_general_elevator_move
chan_setval 20
chan_call .delay
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_264B
chan_end
.layer_264B:
layer_note1 37, 0x8, 96
layer_note1 41, 0x6, 96
layer_note1 32, 0x18, 96
layer_end
.layer_2655:
layer_note1 46, 0x32, 127
layer_end
.layer_2659:
layer_note1 39, 0x32, 127
layer_end
.sound_obj_large_bully_attacked:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_2665
chan_end
.layer_2665:
layer_portamento 0x83, 27, 255
layer_note0 34, 0x12, 127, 127
layer_note1 20, 0x28, 127
layer_end
.sound_obj_bobomb_buddy_talk:
chan_setbank 8
chan_setinstr 12
chan_setvibratoextent 80
chan_setvibratorate 5
chan_setlayer 0, .layer_2684
chan_setval 88
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_2684:
layer_portamento 0x83, 44, 200
layer_note0 49, 0xc, 127, 127
layer_note0 40, 0x12, 127, 155
layer_note0 39, 0xb, 127, 127
layer_portamento 0x83, 41, 200
layer_note0 51, 0xa, 127, 127
layer_note0 48, 0x12, 127, 80
layer_note0 46, 0xa, 127, 127
layer_note0 48, 0xb, 127, 127
layer_end
.chan_26A9:
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_26B1
chan_end
.layer_26B1:
layer_portamento 0x85, 31, 255
layer_note1 8, 0x6, 100
layer_note1 32, 0xc, 100
layer_end
.sound_obj_eyerok_sound_short:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_26C7
chan_setlayer 1, .layer_26C7
chan_end
.layer_26C7:
layer_portamento 0x81, 32, 255
layer_note1 22, 0x24, 110
layer_end
.sound_obj_eyerok_sound_long:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_26D7
chan_end
.layer_26D7:
layer_portamento 0x81, 26, 255
layer_note1 19, 0x60, 127
layer_end
.sound_obj_wiggler_high_pitch:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_26E7
chan_end
.layer_26E7:
layer_transpose 3
layer_note0 31, 0x8, 127, 70
layer_note0 30, 0x9, 127, 70
layer_note0 29, 0x8, 127, 70
layer_note0 28, 0x9, 127, 70
layer_end
.sound_obj_heaveho_tossed:
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_2702
chan_end
.layer_2702:
layer_portamento 0x81, 12, 255
layer_note1 51, 0x24, 127
layer_end
.sound_obj_bowser_intro_laugh:
chan_setbank 6
chan_setinstr 9
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_271A
chan_setlayer 1, .layer_271A
chan_end
.layer_271A:
layer_delay 0xdc
.layer_271D:
layer_portamento 0x81, 20, 255
layer_note1 26, 0xc8, 110
layer_end
.sound_obj_enemy_death_high:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 8
chan_setlayer 1, .layer_223D
chan_end
.sound_obj_enemy_death_low:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 8
chan_setlayer 1, .layer_2746
chan_end
.layer_2746:
layer_note1 39, 0xe, 100
layer_portamento 0x81, 39, 255
layer_note1 27, 0x1c, 105
layer_end
.sound_obj_swoop_death:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 7
chan_setlayer 1, .layer_254A
chan_end
.sound_obj_koopa_flyguy_pokey_death:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 8
chan_setlayer 1, .layer_2461
chan_end
.sound_obj_wiggler_death:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 0
chan_setlayer 1, .layer_2219
chan_end
.sound_obj_snowman_bounce:
chan_call .sound_obj_water_bomb_bouncing
chan_setlayer 1, .layer_22F3
chan_end
.sound_obj_snowman_explode:
chan_call .sound_general_explosion7
chan_setval 12
chan_call .delay
chan_setbank 6
chan_setinstr 1
chan_setlayer 2, .layer_2798
chan_end
.layer_2798:
layer_note1 24, 0x46, 127
layer_end
.sound_obj_bowser_teleport:
chan_setbank 9
chan_setinstr 3
chan_setvibratoextent 80
chan_setvibratorate 60
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_27B7
chan_setlayer 1, .layer_27B5
chan_setval 56
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_27B5:
layer_transpose 1
.layer_27B7:
layer_note1 15, 0x48, 127
layer_end
.sound_obj_monty_mole_appear:
chan_setbank 4
chan_setinstr 15
chan_setval 40
chan_call .set_reverb
chan_setenvelope .envelope_33BC
chan_setlayer 0, .layer_27CB
chan_end
.layer_27CB:
layer_portamento 0x84, 3, 255
layer_note1 39, 0x7, 127
layer_note1 44, 0x8, 127
layer_note1 51, 0x7, 127
layer_note1 56, 0x8, 127
layer_end
.sound_obj_pounding_loud:
chan_setbank 6
chan_setinstr 1
chan_setval 55
chan_call .set_reverb
chan_setlayer 0, .layer_204E
chan_end
.sound_obj_boss_dialog_grunt:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_27F1
chan_end
.layer_27F1:
layer_note1 29, 0x7, 127
layer_note0 31, 0x18, 127, 127
layer_note1 27, 0x26, 127
layer_end
.sound_obj_mips_rabbit:
chan_setbank 6
chan_setinstr 0
chan_setlayer 0, .layer_2804
chan_end
.layer_2804:
layer_somethingon
layer_portamento 0x85, 32, 255
layer_note1 46, 0x9, 80
layer_note1 36, 0xa, 90
layer_end
.sound_obj_mri_spinning:
chan_setbank 6
chan_setinstr 11
chan_setenvelope .envelope_3304
chan_setlayer 0, .layer_281B
chan_end
.layer_281B:
layer_somethingon
layer_portamento 0x85, 19, 255
layer_note1 31, 0xe, 127
layer_note1 62, 0x8, 127
layer_end
.sound_obj_mips_rabbit_water:
chan_setbank 2
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_283E
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 0
chan_setlayer 1, .layer_2804
chan_end
.layer_283E:
layer_portamento 0x81, 47, 255
layer_note1 50, 0x18, 115
layer_end
.sound_obj_eyerok_explode:
chan_setbank 4
chan_setinstr 9
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_2854
chan_setlayer 1, .layer_2856
chan_end
.layer_2854:
layer_setinstr 15
.layer_2856:
layer_transpose 6
layer_call .layer_fn_119F
layer_transpose 247
layer_call .layer_fn_119F
layer_transpose 236
layer_jump .layer_fn_119F
.sound_obj_chuckya_death:
chan_call .sound_obj_king_whomp_death
chan_setlayer 1, .layer_288B
chan_setval 2
chan_call .delay
chan_setbank 8
chan_setinstr 10
chan_setlayer 2, .layer_2878
chan_end
.layer_2878:
layer_portamento 0x83, 43, 255
layer_note1 46, 0x9, 115
layer_somethingon
layer_portamento 0x85, 48, 255
layer_note1 50, 0x8, 127
layer_note1 44, 0x1e, 127
layer_end
.layer_288B:
layer_transpose 2
layer_jump .layer_252C
.sound_obj_wiggler_talk:
chan_setbank 7
chan_setinstr 10
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_289B
chan_end
.layer_289B:
layer_transpose 3
layer_portamento 0x81, 46, 255
layer_note1 55, 0xa, 105
layer_call .layer_fn_28BF
layer_delay 0xf
layer_portamento 0x81, 44, 255
layer_note0 53, 0xf, 105, 127
layer_portamento 0x81, 43, 255
layer_note1 51, 0xc, 105
layer_portamento 0x81, 46, 255
layer_note1 43, 0xe, 105
.layer_fn_28BF:
layer_portamento 0x81, 43, 255
layer_note1 51, 0xc, 105
layer_end
.sound_obj_wiggler_attacked:
chan_setbank 7
chan_setinstr 10
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_28D2
chan_end
.layer_28D2:
layer_transpose 6
layer_portamento 0x83, 53, 255
layer_note1 48, 0x8, 105
layer_note0 60, 0x9, 105, 100
layer_note1 39, 0xb, 105
layer_end
.sound_obj_wiggler_low_pitch:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_28EB
chan_end
.layer_28EB:
layer_transpose 254
layer_note0 31, 0xa, 127, 70
layer_note0 30, 0xb, 127, 70
layer_note0 29, 0xa, 127, 70
layer_note0 28, 0xc, 127, 70
layer_end
.sound_obj_snufit_skeeter_death:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 10
chan_setenvelope .envelope_3344
chan_setlayer 1, .layer_2911
chan_end
.layer_2911:
layer_transpose 12
layer_portamento 0x83, 53, 255
layer_note1 48, 0x8, 105
layer_note0 60, 0x9, 105, 100
layer_note1 39, 0x14, 105
layer_end
.sound_obj_bubba_chomp:
chan_call .sound_obj_piranha_plant_bite
chan_setval 10
chan_call .delay
chan_setbank 9
chan_setinstr 0
chan_setenvelope .envelope_340C
chan_setlayer 0, .layer_2935
chan_end
.layer_2935:
layer_transpose 6
layer_portamento 0x85, 12, 255
layer_note1 0, 0x12, 127
layer_note1 10, 0x14, 127
layer_end
#arsebloody
.sound_obj_enemy_defeat_shrink:
chan_setbank 7
chan_setinstr 0
chan_setlayer 0, .layer_2951
chan_end
.layer_294D:
layer_transpose 5
layer_delay 0x3
.layer_2951:
layer_note1 39, 0x9f, 105
layer_end
.channel6_table:
sound_ref .sound_air_bowser_spit_fire
sound_ref .chan_29C2
sound_ref .sound_air_lakitu_fly
sound_ref .sound_air_amp_buzz
sound_ref .sound_air_blow_fire
sound_ref .sound_air_rough_slide
sound_ref .sound_air_heaveho_move
sound_ref .chan_2A3D
sound_ref .sound_air_bobomb_lit_fuse
sound_ref .sound_air_howling_wind
sound_ref .sound_air_chuckya_move
sound_ref .sound_air_peach_twinkle
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_castle_outdoors_ambient
sound_ref .chan_29C2
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .chan_29C2
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
.sound_air_bowser_spit_fire:
chan_setbank 7
chan_setinstr 5
chan_setlayer 0, .layer_29B9
chan_end
.layer_29B9:
layer_somethingon
.layer_29BA:
layer_note1 39, 0x12c, 127
layer_jump .layer_29BA
layer_end
.chan_29C2:
chan_setbank 7
chan_setinstr 6
chan_setlayer 0, .layer_29CA
chan_end
.layer_29CA:
layer_somethingon
.layer_29CB:
layer_note1 39, 0x12c, 90
layer_jump .layer_29CB
layer_end
.sound_air_lakitu_fly:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_29DE
chan_end
.layer_29DE:
layer_transpose 12
layer_somethingon
layer_portamento 0x85, 27, 255
.layer_29E5:
layer_note1 51, 0x16, 50
layer_note1 27, 0x16, 50
layer_jump .layer_29E5
layer_end
.sound_air_amp_buzz:
chan_setbank 3
chan_setinstr 9
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_29FA
chan_end
.layer_29FA:
layer_somethingon
.layer_29FB:
layer_note1 46, 0xc8, 92
layer_jump .layer_29FB
layer_end
.sound_air_blow_fire:
chan_setbank 7
chan_setinstr 5
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_2A0E
chan_end
.layer_2A0E:
layer_somethingon
.layer_2A0F:
layer_note1 44, 0x12c, 127
layer_jump .layer_2A0F
layer_end
.sound_air_rough_slide:
chan_setbank 3
chan_setinstr 6
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_2A22
chan_end
.layer_2A22:
layer_somethingon
.layer_2A23:
layer_note1 35, 0x12c, 127
layer_jump .layer_2A23
layer_end
.sound_air_heaveho_move:
chan_setbank 5
chan_setinstr 5
chan_setlayer 0, .layer_2A33
chan_end
.layer_2A33:
layer_note1 56, 0x4, 62
layer_note1 32, 0x3, 62
layer_jump .layer_2A33
layer_end
.chan_2A3D:
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_2A45
chan_end
.layer_2A45:
layer_portamento 0x81, 24, 255
layer_note1 56, 0x10, 55
layer_jump .layer_2A45
layer_end
.sound_air_bobomb_lit_fuse:
chan_setbank 3
chan_setinstr 5
chan_setlayer 0, .layer_2A61
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 8
chan_end
.layer_2A61:
layer_note1 48, 0x6, 100
layer_somethingon
.layer_2A65:
layer_note1 44, 0x12c, 127
layer_jump .layer_2A65
layer_end
.chan_unused_2A6D:
chan_setbank 3
chan_setinstr 6
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_2A78
chan_end
.layer_2A78:
layer_somethingon
layer_note1 35, 0x12c, 100
layer_jump .layer_2A23
layer_end
.sound_air_howling_wind:
chan_setlayer 0, .layer_2AA7
chan_setlayer 1, .layer_2AB7
chan_setpanmix 0
.chan_2A89:
chan_setbank 5
chan_setinstr 6
chan_setdecayrelease 3
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 9
chan_setdecayrelease 3
chan_setval 199
chan_call .delay
chan_setval 100
chan_call .delay
chan_jump .chan_2A89
.layer_2AA7:
layer_somethingon
layer_portamento 0x85, 38, 255
.layer_2AAC:
layer_note1 41, 0x12c, 127
layer_note1 38, 0x12c, 127
layer_jump .layer_2AAC
.layer_2AB7:
layer_delay 1
layer_setpan 30
layer_note1 56, 0xc, 10
layer_delay 0x6c
layer_setpan 90
layer_note1 55, 0x1e, 35
layer_delay 0x3b
layer_setpan 55
layer_note1 56, 0x2e, 68
layer_delay 0x2d
layer_note1 58, 0x25, 34
layer_delay 0x2b
layer_setpan 91
layer_note1 53, 0x6, 55
layer_note1 55, 0x18, 70
layer_delay 0x2b
layer_setpan 21
layer_note1 56, 0x28, 52
layer_delay 0x1b
layer_note1 57, 0x18, 65
layer_delay 0x38
layer_setpan 75
layer_note1 53, 0x22, 67
layer_delay 0x4c
layer_setpan 105
layer_note1 53, 0x3, 54
layer_note1 55, 0x17, 61
layer_delay 0x43
layer_setpan 64
layer_note1 52, 0x28, 45
layer_delay 0x38
layer_jump .layer_2AB7
.sound_air_chuckya_move:
chan_setbank 5
chan_setinstr 5
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_2B0F
chan_end
.layer_2B0F:
layer_portamento 0x81, 56, 255
layer_note1 44, 0x3, 85
layer_note1 20, 0x2, 85
layer_jump .layer_2B0F
layer_end
.channel7_table:
sound_ref .sound_menu_change_select
sound_ref .sound_menu_reverse_pause
sound_ref .sound_menu_pause
sound_ref .sound_menu_pause
sound_ref .sound_menu_message_appear
sound_ref .sound_menu_message_disappear
sound_ref .sound_menu_camera_zoom_in
sound_ref .sound_menu_camera_zoom_out
sound_ref .sound_menu_pinch_mario_face
sound_ref .sound_menu_let_go_mario_face
sound_ref .sound_menu_hand_appear
sound_ref .sound_menu_hand_disappear
sound_ref .chan_2D18
sound_ref .sound_menu_power_meter
sound_ref .sound_menu_camera_buzz
sound_ref .sound_menu_camera_turn
sound_ref .chan_2DA8
sound_ref .sound_menu_click_file_select
sound_ref .sound_menu_read_sign
sound_ref .sound_menu_message_next_page
sound_ref .sound_menu_coin_its_a_me_mario
sound_ref .sound_menu_yoshi_gain_lives
sound_ref .sound_menu_enter_pipe
sound_ref .sound_menu_exit_pipe
sound_ref .sound_menu_bowser_laugh
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_click_change_view
sound_ref .sound_menu_camera_unused1
sound_ref .sound_menu_camera_unused2
sound_ref .sound_menu_mario_castle_warp
sound_ref .sound_menu_star_sound
sound_ref .sound_menu_thank_you_playing_my_game
sound_ref .sound_menu_read_a_sign
sound_ref .sound_menu_exit_a_sign
sound_ref .sound_menu_mario_castle_warp2
.ifdef VERSION_JP
sound_ref .sound_menu_message_next_page
sound_ref .sound_menu_coin_its_a_me_mario
sound_ref .sound_menu_yoshi_gain_lives
sound_ref .sound_menu_enter_pipe
sound_ref .sound_menu_exit_pipe
sound_ref .sound_menu_bowser_laugh
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_click_change_view
sound_ref .sound_menu_camera_unused1
sound_ref .sound_menu_camera_unused2
sound_ref .sound_menu_mario_castle_warp
sound_ref .sound_menu_star_sound
sound_ref .sound_menu_change_select
.else
sound_ref .sound_menu_star_sound_okey_dokey
sound_ref .sound_menu_star_sound_lets_a_go
sound_ref .sound_menu_yoshi_gain_lives
sound_ref .sound_menu_enter_pipe
sound_ref .sound_menu_exit_pipe
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_pinch_mario_face
sound_ref .sound_menu_let_go_mario_face
sound_ref .sound_menu_hand_appear
sound_ref .sound_menu_hand_disappear
sound_ref .chan_2D18
sound_ref .sound_menu_power_meter
sound_ref .sound_menu_camera_buzz
sound_ref .sound_menu_camera_turn
.endif
.sound_menu_change_select:
chan_setbank 9
chan_setinstr 1
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setpanmix 0
chan_setenvelope .envelope_340C
chan_setlayer 0, .layer_2BB0
chan_setlayer 1, .layer_2BBD
chan_end
.layer_2BB0:
layer_portamento 0x1, 35, 0xa
layer_note1 41, 0xa, 80
layer_setpan 0
layer_note1 41, 0xa, 80
layer_end
.layer_2BBD:
layer_setpan 127
layer_delay 0xc
layer_note1 41, 0xa, 80
layer_end
.sound_menu_reverse_pause:
chan_setbank 9
chan_setinstr 1
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setpanmix 0
chan_setlayer 0, .layer_2BD5
chan_setlayer 1, .layer_2BEC
chan_end
.layer_2BD5:
layer_setpan 34
.layer_2BD7:
layer_note0 45, 0xc, 80, 63
layer_note0 41, 0xc, 80, 63
layer_note0 48, 0xc, 80, 63
layer_note0 41, 0xc, 38, 63
layer_note0 48, 0xc, 38, 63
layer_end
.layer_2BEC:
layer_setpan 94
layer_delay 0x2
layer_jump .layer_2BD7
.sound_menu_pause:
chan_setbank 9
chan_setinstr 1
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setpanmix 0
chan_setlayer 0, .layer_2C03
chan_setlayer 1, .layer_2C10
chan_end
.layer_2C03:
layer_note1 43, 0x9, 95
layer_note1 39, 0x9, 90
layer_note1 43, 0x9, 95
layer_note1 39, 0x9, 90
layer_end
.layer_2C10:
layer_delay 0x8
layer_setpan 40
layer_note1 43, 0x9, 35
layer_setpan 88
layer_note1 39, 0x9, 35
layer_setpan 36
layer_note1 43, 0x9, 30
layer_setpan 92
layer_note1 39, 0x9, 30
layer_setpan 28
layer_note1 43, 0x9, 25
layer_setpan 100
layer_note1 39, 0x9, 25
layer_end
.sound_menu_message_appear:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 2
chan_setlayer 0, .layer_2C3A
chan_end
.layer_2C3A:
layer_portamento 0x1, 32, 0x7f
layer_note1 56, 0x1e, 102
layer_end
.sound_menu_message_disappear:
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 0
chan_setenvelope .envelope_3438
chan_setlayer 0, .layer_2C4E
chan_end
.layer_2C4E:
layer_portamento 0x1, 32, 0x7f
layer_note1 53, 0x1e, 78
layer_end
.sound_menu_camera_zoom_out:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_341C
chan_setlayer 0, .layer_2C64
chan_end
.layer_2C64:
layer_portamento 0x1, 32, 0x8
layer_note1 27, 0x8, 127
layer_portamento 0x81, 39, 255
layer_note1 20, 0x28, 127
layer_end
.sound_menu_camera_zoom_in:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_2C81
chan_end
.layer_2C81:
layer_portamento 0x1, 27, 0x8
layer_note1 32, 0x8, 93
layer_portamento 0x81, 20, 255
layer_note1 39, 0x28, 93
layer_end
.sound_menu_pinch_mario_face:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 1
chan_setenvelope .envelope_3444
chan_setvibratorate 1
chan_setvibratoextent 100
chan_setlayer 0, .layer_2CA0
chan_end
.layer_2CA0:
layer_somethingon
layer_portamento 0x85, 27, 255
layer_note1 15, 0x6, 127
layer_note1 34, 0xc, 127
layer_end
.sound_menu_let_go_mario_face:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 1
chan_setenvelope .envelope_3454
chan_setvibratorate 25
chan_setvibratoextent 80
chan_setlayer 0, .layer_2CDA
chan_setlayer 1, .layer_2CD6
chan_setval 5
chan_call .delay
chan_setvibratorate 35
chan_setvibratoextent 115
chan_setval 55
chan_call .delay
chan_setvibratoextent 80
chan_setval 67
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_2CD6:
layer_transpose 12
layer_delay 0x3
.layer_2CDA:
layer_portamento 0x85, 24, 255
layer_note1 28, 0x5, 110
layer_note1 28, 0x78, 110
layer_end
.sound_menu_hand_appear:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 3
chan_setlayer 0, .layer_2CF3
chan_setlayer 1, .layer_2CF1
chan_end
.layer_2CF1:
layer_delay 0x2
.layer_2CF3:
layer_portamento 0x85, 47, 255
layer_note1 35, 0x8, 90
layer_note1 47, 0x10, 90
layer_end
.sound_menu_hand_disappear:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 3
chan_setlayer 0, .layer_2D0C
chan_setlayer 1, .layer_2D0A
chan_end
.layer_2D0A:
layer_delay 0x2
.layer_2D0C:
layer_portamento 0x85, 35, 255
layer_note1 47, 0x8, 90
layer_note1 35, 0x10, 90
layer_disableportamento
layer_end
.chan_2D18:
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_3454
chan_setlayer 0, .layer_2D26
chan_end
.layer_2D26:
layer_note1 45, 0x6, 100
layer_note1 57, 0x6, 100
layer_note1 57, 0xc, 100
layer_setpan 10
layer_note1 57, 0x6, 57
layer_note1 57, 0xc, 57
layer_setpan 117
layer_note1 57, 0x6, 38
layer_note1 57, 0xc, 38
layer_end
.sound_menu_power_meter:
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_3454
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_2D53
chan_end
.layer_2D53:
layer_setpan 30
layer_note1 44, 0x5, 105
layer_setpan 50
layer_note1 47, 0x5, 105
layer_setpan 77
layer_note1 52, 0x5, 105
layer_setpan 97
layer_note1 56, 0xa, 105
layer_setpan 30
layer_note1 52, 0x5, 45
layer_setpan 97
layer_note1 56, 0xa, 45
layer_setpan 30
layer_note1 52, 0x5, 32
layer_setpan 97
layer_note1 56, 0xa, 32
layer_end
.sound_menu_camera_buzz:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 4
chan_setlayer 0, .layer_2D87
chan_end
.layer_2D87:
layer_note1 39, 0x18, 105
layer_end
.sound_menu_camera_turn:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_2D99
chan_end
.layer_2D99:
layer_portamento 0x81, 23, 255
layer_note1 35, 0x9, 96
layer_portamento 0x81, 36, 255
layer_note1 43, 0x44, 100
layer_end
.chan_2DA8:
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_2DB1
chan_end
.layer_2DB1:
layer_delay 1
layer_end
.sound_menu_click_file_select:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_2DBF
chan_end
.layer_2DBF:
layer_portamento 0x81, 32, 255
layer_note0 39, 0x5, 115, 255
layer_portamento 0x81, 44, 255
layer_note0 51, 0x3, 115, 255
layer_end
.sound_menu_read_sign:
chan_setmutebhv 0x0
chan_setbank 9
chan_setinstr 1
chan_setval 60
chan_call .set_reverb
chan_setlayer 0, .layer_2DDF
chan_end
.layer_2DDF:
layer_note1 46, 0x3, 90
layer_note1 46, 0x3, 30
layer_note1 58, 0x3, 90
layer_note1 58, 0x3, 30
layer_note1 46, 0x3, 90
layer_note1 46, 0x3, 30
layer_end
.sound_menu_message_next_page:
chan_setbank 9
chan_setinstr 0
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_2DFD
chan_end
.layer_2DFD:
layer_portamento 0x81, 15, 255
layer_note1 51, 0x5, 73
layer_end
.sound_menu_coin_its_a_me_mario:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setval 25
chan_setlayer 0, .layer_2E28
chan_setlayer 1, .layer_2E3D
chan_setval 70
chan_call .delay
chan_setbank 10
chan_setinstr 8
chan_end
.layer_2E28:
layer_call .layer_11E4
layer_delay 0x12
layer_transpose 0
layer_note1 39, 0xc8, 120
layer_end
.layer_2E3D:
layer_transpose 24
layer_delay 0x1e
layer_note1 25, 0x2, 18
layer_note1 37, 0x7, 36
layer_note1 30, 0x5, 18
layer_note1 42, 0x37, 36
layer_end
.sound_menu_yoshi_gain_lives:
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_3454
chan_setval 25
chan_call .set_reverb
chan_setpanmix 0
chan_stereoheadseteffects 1
chan_setlayer 0, .layer_2E65
chan_end
.layer_2E65:
layer_note1 46, 0x5, 105
layer_note1 53, 0x5, 105
layer_note1 58, 0x5, 105
layer_setpan 30
layer_note1 53, 0x5, 50
layer_setpan 98
layer_note1 58, 0x5, 50
layer_setpan 20
layer_note1 53, 0x5, 20
layer_setpan 108
layer_note1 58, 0x5, 20
layer_end
.sound_menu_enter_pipe:
chan_reservenotes 4
chan_setbank 9
chan_setinstr 2
chan_setpanmix 0
chan_stereoheadseteffects 1
chan_setval 30
chan_call .set_reverb
chan_setenvelope .envelope_33BC
chan_setdecayrelease 220
chan_setlayer 0, .layer_2EA3
chan_setlayer 1, .layer_2E9E
chan_end
.layer_2E9E:
layer_transpose 244
layer_jump .layer_2EA5
.layer_2EA3:
layer_transpose 232
.layer_2EA5:
layer_call .layer_fn_2EAB
layer_call .layer_fn_2EAB
.layer_fn_2EAB:
layer_portamento 0x85, 60, 192
layer_setpan 117
layer_note1 60, 0x3, 126
layer_setpan 105
layer_note1 58, 0x3, 126
layer_setpan 93
layer_note1 55, 0x3, 126
layer_setpan 81
layer_note1 51, 0x3, 126
layer_setpan 46
layer_note1 50, 0x3, 126
layer_setpan 34
layer_note1 46, 0x3, 126
layer_setpan 22
layer_note1 44, 0x3, 126
layer_setpan 10
layer_note1 41, 0x3, 126
layer_end
.sound_menu_exit_pipe:
chan_reservenotes 4
chan_setbank 9
chan_setinstr 2
chan_setval 30
chan_call .set_reverb
chan_setenvelope .envelope_3464
chan_setdecayrelease 220
chan_setlayer 0, .layer_2EF4
chan_setlayer 1, .layer_2EEF
chan_end
.layer_2EEF:
layer_transpose 24
layer_jump .layer_2EF6
.layer_2EF4:
layer_transpose 12
.layer_2EF6:
layer_portamento 0x85, 15, 128
layer_note1 15, 0x3, 126
layer_note1 19, 0x3, 126
layer_note1 22, 0x3, 126
layer_note1 27, 0x3, 126
layer_note1 22, 0x3, 126
layer_note1 27, 0x3, 126
layer_note1 31, 0x3, 126
layer_note1 34, 0x3, 126
layer_note1 39, 0x3, 126
layer_note1 34, 0x3, 126
layer_note1 23, 0x3, 126
layer_note1 27, 0x3, 126
layer_note1 30, 0x3, 126
layer_note1 35, 0x3, 126
layer_note1 30, 0x3, 126
layer_note1 35, 0x3, 126
layer_note1 39, 0x3, 126
layer_note1 42, 0x3, 126
layer_note1 47, 0x3, 126
layer_note1 42, 0x3, 126
layer_note1 25, 0x3, 126
layer_note1 29, 0x3, 126
layer_note1 32, 0x3, 126
layer_note1 37, 0x3, 126
layer_note1 32, 0x3, 126
layer_note1 37, 0x3, 126
layer_note1 41, 0x3, 126
layer_note1 44, 0x3, 126
layer_note1 49, 0x3, 126
layer_note1 44, 0x3, 126
layer_end
.sound_menu_bowser_laugh:
chan_setbank 6
chan_setinstr 9
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_271D
chan_setlayer 1, .layer_271D
chan_end
.sound_menu_click_change_view:
chan_setbank 9
chan_setinstr 5
chan_setlayer 0, .layer_2F6D
chan_end
.layer_2F6D:
layer_note1 39, 0x30, 127
layer_end
.sound_menu_camera_unused1:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_2F7C
chan_end
.layer_2F7C:
layer_transpose 244
layer_portamento 0x83, 3, 255
layer_note1 15, 0xa, 127
layer_somethingon
layer_transpose 0
layer_note1 46, 0x64, 127
layer_end
.sound_menu_camera_unused2:
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_2F97
chan_setenvelope .envelope_32D4
chan_end
.layer_2F97:
layer_portamento 0x81, 3, 255
layer_note1 15, 0xc, 127
layer_portamento 0x81, 39, 255
layer_note1 3, 0x64, 127
layer_end
.sound_menu_mario_castle_warp:
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_340C
chan_setreverb 30
chan_setlayer 0, .layer_3032
chan_setlayer 1, .layer_2FB9
chan_end
.layer_2FB9:
layer_transpose 232
layer_setpan 24
layer_call .layer_fn_300D
layer_transpose 244
layer_setpan 44
layer_call .layer_fn_300D
layer_transpose 0
.layer_2FC9:
layer_setpan 64
layer_call .layer_fn_300D
layer_transpose 12
layer_setpan 84
layer_call .layer_fn_300D
layer_transpose 24
layer_setpan 104
layer_call .layer_fn_300D
layer_setpan 24
layer_note1 56, 0x2, 100
layer_note1 56, 0x1, 50
layer_setpan 104
layer_note1 60, 0x14, 70
layer_note1 60, 0xa, 30
layer_setpan 24
layer_note1 56, 0x2, 50
layer_note1 56, 0x1, 20
layer_setpan 104
layer_note1 60, 0x14, 30
layer_note1 60, 0xa, 10
layer_setpan 24
layer_note1 56, 0x2, 30
layer_note1 56, 0x1, 10
layer_setpan 104
layer_note1 60, 0x14, 20
layer_note1 60, 0xa, 7
layer_end
.layer_fn_300D:
layer_note1 51, 0x2, 50
layer_note1 39, 0x1, 40
layer_note1 39, 0x2, 20
layer_note1 55, 0x2, 50
layer_note1 43, 0x1, 40
layer_note1 43, 0x2, 20
layer_note1 56, 0x2, 50
layer_note1 44, 0x1, 40
layer_note1 44, 0x2, 20
layer_note1 60, 0x2, 50
layer_note1 48, 0x1, 40
layer_note1 48, 0x2, 20
layer_end
.layer_3032:
layer_transpose 232
layer_call .layer_fn_3072
layer_transpose 244
layer_call .layer_fn_3072
layer_transpose 0
layer_call .layer_fn_3072
.layer_3041:
layer_transpose 12
layer_call .layer_fn_3072
layer_transpose 24
layer_call .layer_fn_3072
layer_setpan 64
layer_note1 44, 0x1, 100
layer_note1 56, 0x2, 50
layer_note1 48, 0xa, 70
layer_note1 60, 0x14, 30
layer_note1 44, 0x1, 50
layer_note1 56, 0x2, 20
layer_note1 48, 0xa, 30
layer_note1 60, 0x14, 10
layer_note1 44, 0x1, 30
layer_note1 56, 0x2, 10
layer_note1 48, 0xa, 20
layer_note1 60, 0x14, 7
layer_end
.layer_fn_3072:
layer_setpan 54
layer_note1 39, 0x3, 100
layer_note1 51, 0x1, 50
layer_note1 51, 0x1, 20
layer_setpan 74
layer_note1 43, 0x3, 100
layer_note1 55, 0x1, 50
layer_note1 55, 0x1, 20
layer_setpan 54
layer_note1 44, 0x3, 100
layer_note1 56, 0x1, 50
layer_note1 56, 0x1, 20
layer_setpan 74
layer_note1 48, 0x3, 100
layer_note1 60, 0x1, 50
layer_note1 60, 0x1, 20
layer_end
.sound_menu_thank_you_playing_my_game:
chan_setbank 10
chan_setinstr 14
chan_setlayer 0, .layer_30AA
chan_setlayer 1, .layer_30AF
chan_end
.layer_30AA:
layer_note1 39, 0x99999999999999, 127
layer_end
.layer_30AF:
layer_delay 0x9
layer_note1 39, 0xf1, 45
layer_end
.sound_menu_read_a_sign:
chan_setbank 9
chan_setinstr 1
chan_setlayer 0, .layer_30BE
chan_end
.layer_30BE:
layer_note1 46, 0x3, 90
layer_note1 46, 0x3, 30
layer_note1 58, 0x3, 90
layer_note1 58, 0x3, 30
layer_end
.sound_menu_exit_a_sign:
chan_setbank 9
chan_setinstr 1
chan_setlayer 0, .layer_30D3
chan_end
.layer_30D3:
layer_note1 58, 0x3, 90
layer_note1 58, 0x3, 30
layer_note1 46, 0x3, 90
layer_note1 46, 0x3, 30
layer_end
.sound_menu_mario_castle_warp2:
chan_reservenotes 6
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_340C
chan_setreverb 30
chan_setlayer 0, .layer_3041
chan_setlayer 1, .layer_2FC9
chan_end
.ifndef VERSION_JP
.sound_menu_star_sound_okey_dokey:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1344
chan_setval 1
chan_call .delay
chan_setbank 10
chan_setinstr 12
chan_setlayer 1, .layer_E3A
chan_end
.sound_menu_star_sound_lets_a_go:
chan_setbank 8
chan_setinstr 26
chan_setlayer 0, .layer_311D
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 14
chan_setlayer 1, .layer_1344
chan_end
.layer_311D:
layer_note1 39, 0xb4, 127
layer_end
.sound_menu_collect_red_coin:
chan_setinstr 128
chan_setnotepriority 14
chan_setpanmix 0
chan_setenvelope .envelope_3378
chan_ioreadval 4
chan_subtract 0x28
chan_readseq .major_scale
chan_writeseq 0, .transpose_by_coin_index, 1
chan_setlayer 0, .layer_3146
chan_setlayer 1, .layer_3168
chan_setlayer 2, .layer_3148
chan_end
.major_scale:
.byte 0
.byte 2
.byte 4
.byte 5
.byte 7
.byte 9
.byte 11
.byte 12
.layer_3146:
layer_delay 0x6
.layer_3148:
layer_call .transpose_by_coin_index
layer_note0 46, 0xc, 75, 20
layer_note0 45, 0xc, 75, 20
layer_note0 46, 0xc, 75, 20
layer_note0 58, 0x10, 80, 80
layer_note0 58, 0x10, 45, 80
layer_note0 58, 0x10, 20, 80
layer_note0 58, 0x10, 15, 80
layer_end
.layer_3168:
layer_call .transpose_by_coin_index
layer_note0 41, 0xc, 75, 20
layer_note0 40, 0xc, 75, 20
layer_note0 41, 0xc, 75, 20
layer_note0 53, 0x10, 80, 80
layer_note0 53, 0x10, 45, 80
layer_note0 53, 0x10, 20, 80
layer_note0 53, 0x10, 15, 80
layer_end
.transpose_by_coin_index:
layer_transpose 0
layer_end
.sound_menu_collect_secret:
chan_setbank 4
chan_setinstr 14
chan_setnotepriority 14
chan_setpanmix 0
chan_ioreadval 4
chan_subtract 0x30
chan_readseq .major_scale
chan_writeseq 0, .layer_31A0, 1
chan_setlayer 0, .layer_31A0
chan_end
.layer_31A0:
layer_transpose 0
layer_note1 32, 0x7f, 115
layer_end
.endif
.sound_general_bird_chirp2:
chan_setbank 5
chan_setinstr 9
chan_setval 40
chan_call .set_reverb
chan_setlayer 0, .layer_31B3
chan_end
.layer_31B3:
layer_delay 0x4b
layer_note0 39, 0xf5, 100, 127
layer_note0 39, 0xa, 85, 127
layer_note0 40, 0x123, 98, 127
layer_note0 39, 0x91, 75, 127
layer_note0 41, 0xbd, 84, 127
layer_note0 39, 0x4b, 73, 127
layer_note0 39, 0x96, 94, 127
layer_note0 36, 0x74, 78, 127
layer_jump .layer_31B3
layer_end
.sound_obj_bird_chirp3:
chan_setbank 5
chan_setinstr 10
chan_setval 60
chan_call .set_reverb
chan_setlayer 0, .layer_31EB
chan_end
.layer_31EB:
layer_delay 0x14
layer_note1 39, 0x71, 70
layer_note1 37, 0xd3, 62
layer_note1 39, 0x48, 84
layer_note1 40, 0x71, 49
layer_note1 39, 0xa8, 65
layer_note1 41, 0x86, 59
layer_note1 41, 0x31, 54
layer_note1 38, 0x6f, 51
layer_note1 39, 0xc7, 79
layer_note1 35, 0xe9, 74
layer_jump .layer_31EB
layer_end
.sound_obj_bird_chirp1:
chan_setbank 5
chan_setinstr 12
chan_setval 30
chan_call .set_reverb
chan_setlayer 0, .layer_3221
chan_end
.layer_3221:
layer_delay 0x32
layer_note1 41, 0x31, 66
layer_delay 0x9f
layer_note1 39, 0x31, 51
layer_delay 0xf9
layer_note1 38, 0x1d, 60
layer_note1 41, 0x4c, 77
layer_delay_long 0x64
layer_note1 42, 0x31, 59
layer_delay 0x159
layer_note1 36, 0x4f, 61
layer_delay 0xc6
layer_jump .layer_3221
layer_end
.sound_air_castle_outdoors_ambient:
chan_setbank 5
chan_setval 15
chan_call .set_reverb
chan_setlayer 0, .layer_3259
chan_setlayer 1, .layer_327F
chan_setlayer 2, .layer_3281
chan_end
.layer_3259:
layer_setinstr 8
layer_delay 0x18
layer_note1 41, 0x9, 26
layer_note1 37, 0xbc, 22
layer_note1 39, 0x71, 33
layer_note1 40, 0xd7, 33
layer_note1 39, 0x54, 39
layer_note1 39, 0x6f, 31
layer_note1 43, 0xa8, 26
layer_note1 40, 0xe1, 22
layer_note1 38, 0x74, 31
layer_jump .layer_3259
.layer_327F:
layer_transpose 12
.layer_3281:
layer_setinstr 13
layer_somethingon
layer_delay 0xf
.layer_3286:
layer_note1 39, 0x12c, 25
layer_jump .layer_3286
.sound_general_switch_tick_slow:
chan_setval 18
chan_jump .chan_3294
.sound_general_switch_tick_fast:
chan_setval 42
.chan_3294:
chan_writeseq 0, .layer_32BF, 1
chan_reservenotes 4
chan_setbank 4
chan_setinstr 2
chan_setenvelope .envelope_3314
chan_setdecayrelease 15
chan_setlayer 0, .layer_32B7
chan_setlayer 1, .layer_32B3
.chan_32A9:
chan_delay1
chan_ioreadval 0
chan_iowriteval 0
chan_subtract 255
chan_beqz .chan_32A9
chan_unreservenotes
chan_end
.layer_32B3:
layer_setinstr 9
layer_transpose 12
.layer_32B7:
layer_note0 50, 0x3, 127, 127
layer_note0 38, 0x3, 127, 127
.layer_32BF:
layer_delay 0x2a
layer_jump .layer_32B7
.align 2, 0
.envelope_32C4:
envelope_line 7 20000
envelope_line 6 32700
envelope_line 32700 32700
envelope_goto 2
.envelope_32D4:
envelope_line 9 15000
envelope_line 7 32700
envelope_line 32700 32700
envelope_goto 2
.envelope_32E4:
envelope_line 10 10000
envelope_line 100 32700
envelope_line 32700 32700
envelope_goto 2
.envelope_32F4:
envelope_line 35 32700
envelope_line 10 32700
envelope_line 300 0
envelope_goto 2
.envelope_3304:
envelope_line 15 20000
envelope_line 5 32700
envelope_line 32700 32700
envelope_goto 2
.envelope_3314:
envelope_line 8 32700
envelope_line 50 32700
envelope_line 300 0
envelope_goto 2
.envelope_3324:
envelope_line 100 25000
envelope_line 35 32700
envelope_line 300 5000
envelope_goto 2
.envelope_3334:
envelope_line 25 32700
envelope_line 4 22500
envelope_line 35 32700
envelope_goto 2
.envelope_3344:
envelope_line 1 32700
envelope_line 10 30000
envelope_line 50 30000
envelope_line 100 0
envelope_goto 3
.envelope_3358:
envelope_line 4 32700
envelope_line 100 15000
envelope_line 1000 0
envelope_goto 2
.envelope_3368:
envelope_line 10 32700
envelope_line 1 32700
envelope_line 10 0
envelope_goto 2
.ifndef VERSION_JP
.envelope_3378:
envelope_line 3 32700
envelope_line 10 30000
envelope_line 10 10000
envelope_line 100 0
envelope_goto 3
.endif
.envelope_338C:
envelope_line 1 32700
envelope_line 20 32700
envelope_line 600 6000
envelope_goto 2
.envelope_unused_339C:
envelope_line 1 32700
envelope_line 20 32700
envelope_line 100 18000
envelope_goto 2
.envelope_33AC:
envelope_line 1 32700
envelope_line 20 32700
envelope_line 300 6000
envelope_goto 2
.envelope_33BC:
envelope_line 7 18000
envelope_line 4 32760
envelope_line 30 0
envelope_goto 2
.envelope_33CC:
envelope_line 19 32700
envelope_line 5 32700
envelope_line 15 0
envelope_goto 2
.envelope_33DC:
envelope_line 25 32700
envelope_line 9 32700
envelope_line 9 0
envelope_goto 2
.envelope_33EC:
envelope_line 1 32700
envelope_line 100 32760
envelope_line 300 0
envelope_goto 2
.envelope_33FC:
envelope_line 22 32700
envelope_line 50 32760
envelope_line 70 0
envelope_goto 2
.envelope_340C:
envelope_line 5 32760
envelope_line 192 0
envelope_line 1000 1000
envelope_goto 2
.envelope_341C:
envelope_line 25 32760
envelope_line 60 10000
envelope_goto 2
.envelope_3428:
envelope_line 1 10000
envelope_line 1 10000
envelope_line 40 32760
envelope_goto 2
.envelope_3438:
envelope_line 23 32760
envelope_line 80 15000
envelope_goto 2
.envelope_3444:
envelope_line 22 32760
envelope_line 50 32760
envelope_line 100 25000
envelope_goto 2
.envelope_3454:
envelope_line 13 32760
envelope_line 50 32760
envelope_line 200 0
envelope_goto 2
.envelope_3464:
envelope_line 6 12000
envelope_line 4 32760
envelope_line 50 32760
envelope_line 200 0
envelope_goto 2
.envelope_unused_3478:
envelope_line 1 32700
envelope_line 1000 32700
envelope_line 10 16000
envelope_line 200 32760
envelope_goto 3
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
96flashbacks/96flashbacks
| 48,463
|
asm/non_matchings/seq_channel_layer_process_script_jp.s
|
.late_rodata
glabel jtbl_80337C90
.word L8031B2C0
.word L8031B27C
.word L8031B690
.word L8031B690
.word L8031B30C
.word L8031B220
.word L8031B690
.word L8031B690
.word L8031B1E4
glabel jtbl_80337CB4
.word L8031B350
.word L8031B3A8
.word L8031B444
.word L8031B3D4
.word L8031B3D4
.word L8031B494
.word L8031B5B8
.word L8031B688
.word L8031B3A8
.word L8031B350
glabel jtbl_80337CDC
.word L8031BBE8
.word L8031BBF4
.word L8031BBE8
.word L8031BBF4
.word L8031BBE8
glabel D_80337CF0
.double 32512.0
glabel D_80337CF8
.double 127.0
.text
glabel seq_channel_layer_process_script
/* 0D60A4 8031B0A4 27BDFFA0 */ addiu $sp, $sp, -0x60
/* 0D60A8 8031B0A8 240E0001 */ li $t6, 1
/* 0D60AC 8031B0AC AFBF001C */ sw $ra, 0x1c($sp)
/* 0D60B0 8031B0B0 AFB00018 */ sw $s0, 0x18($sp)
/* 0D60B4 8031B0B4 A3AE003F */ sb $t6, 0x3f($sp)
/* 0D60B8 8031B0B8 8C820000 */ lw $v0, ($a0)
/* 0D60BC 8031B0BC 00808025 */ move $s0, $a0
/* 0D60C0 8031B0C0 00027FC2 */ srl $t7, $v0, 0x1f
/* 0D60C4 8031B0C4 51E00376 */ beql $t7, $zero, .L8031BEA0
/* 0D60C8 8031B0C8 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D60CC 8031B0CC 8483003C */ lh $v1, 0x3c($a0)
/* 0D60D0 8031B0D0 00027080 */ sll $t6, $v0, 2
/* 0D60D4 8031B0D4 0002C8C0 */ sll $t9, $v0, 3
/* 0D60D8 8031B0D8 28610002 */ slti $at, $v1, 2
/* 0D60DC 8031B0DC 1420000E */ bnez $at, .L8031B118
/* 0D60E0 8031B0E0 2478FFFF */ addiu $t8, $v1, -1
/* 0D60E4 8031B0E4 05C0036D */ bltz $t6, .L8031BE9C
/* 0D60E8 8031B0E8 A498003C */ sh $t8, 0x3c($a0)
/* 0D60EC 8031B0EC 848F003E */ lh $t7, 0x3e($a0)
/* 0D60F0 8031B0F0 8498003C */ lh $t8, 0x3c($a0)
/* 0D60F4 8031B0F4 01F8082A */ slt $at, $t7, $t8
/* 0D60F8 8031B0F8 54200369 */ bnezl $at, .L8031BEA0
/* 0D60FC 8031B0FC 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D6100 8031B100 0C0C63B1 */ jal seq_channel_layer_note_decay
/* 0D6104 8031B104 00000000 */ nop
/* 0D6108 8031B108 920E0000 */ lbu $t6, ($s0)
/* 0D610C 8031B10C 35CF0020 */ ori $t7, $t6, 0x20
/* 0D6110 8031B110 10000362 */ b .L8031BE9C
/* 0D6114 8031B114 A20F0000 */ sb $t7, ($s0)
.L8031B118:
/* 0D6118 8031B118 07220004 */ bltzl $t9, .L8031B12C
/* 0D611C 8031B11C 92020004 */ lbu $v0, 4($s0)
/* 0D6120 8031B120 0C0C63B1 */ jal seq_channel_layer_note_decay
/* 0D6124 8031B124 02002025 */ move $a0, $s0
/* 0D6128 8031B128 92020004 */ lbu $v0, 4($s0)
.L8031B12C:
/* 0D612C 8031B12C 2401FF7F */ li $at, -129
/* 0D6130 8031B130 44800000 */ mtc1 $zero, $f0
/* 0D6134 8031B134 00417024 */ and $t6, $v0, $at
/* 0D6138 8031B138 24010001 */ li $at, 1
/* 0D613C 8031B13C 11C10004 */ beq $t6, $at, .L8031B150
/* 0D6140 8031B140 3C1F8022 */ lui $ra, %hi(gCtlEntries) # $ra, 0x8022
/* 0D6144 8031B144 24010002 */ li $at, 2
/* 0D6148 8031B148 55C10003 */ bnel $t6, $at, .L8031B158
/* 0D614C 8031B14C 8E0D0050 */ lw $t5, 0x50($s0)
.L8031B150:
/* 0D6150 8031B150 A2000004 */ sb $zero, 4($s0)
/* 0D6154 8031B154 8E0D0050 */ lw $t5, 0x50($s0)
.L8031B158:
/* 0D6158 8031B158 3C013F80 */ lui $at, 0x3f80
/* 0D615C 8031B15C 3C0B8022 */ lui $t3, %hi(gBankLoadedPool)
/* 0D6160 8031B160 44810800 */ mtc1 $at, $f1
/* 0D6164 8031B164 256B14F8 */ addiu $t3, $t3, %lo(gBankLoadedPool)
/* 0D6168 8031B168 27FF6D60 */ addiu $ra, %lo(gCtlEntries) # addiu $ra, $ra, 0x6d60
/* 0D616C 8031B16C 97AA003A */ lhu $t2, 0x3a($sp)
/* 0D6170 8031B170 240900FF */ li $t1, 255
/* 0D6174 8031B174 8DAC0040 */ lw $t4, 0x40($t5)
.L8031B178:
/* 0D6178 8031B178 8E020054 */ lw $v0, 0x54($s0)
.L8031B17C:
/* 0D617C 8031B17C 244F0001 */ addiu $t7, $v0, 1
/* 0D6180 8031B180 AE0F0054 */ sw $t7, 0x54($s0)
/* 0D6184 8031B184 90440000 */ lbu $a0, ($v0)
/* 0D6188 8031B188 288100C1 */ slti $at, $a0, 0xc1
/* 0D618C 8031B18C 14200159 */ bnez $at, .L8031B6F4
/* 0D6190 8031B190 00802825 */ move $a1, $a0
/* 0D6194 8031B194 288100CB */ slti $at, $a0, 0xcb
/* 0D6198 8031B198 1420000A */ bnez $at, .L8031B1C4
/* 0D619C 8031B19C 24B9FF3F */ addiu $t9, $a1, -0xc1
/* 0D61A0 8031B1A0 2498FF09 */ addiu $t8, $a0, -0xf7
/* 0D61A4 8031B1A4 2F010009 */ sltiu $at, $t8, 9
/* 0D61A8 8031B1A8 10200139 */ beqz $at, .L8031B690
/* 0D61AC 8031B1AC 0018C080 */ sll $t8, $t8, 2
/* 0D61B0 8031B1B0 3C018033 */ lui $at, %hi(jtbl_80337C90)
/* 0D61B4 8031B1B4 00380821 */ addu $at, $at, $t8
/* 0D61B8 8031B1B8 8C387C90 */ lw $t8, %lo(jtbl_80337C90)($at)
/* 0D61BC 8031B1BC 03000008 */ jr $t8
/* 0D61C0 8031B1C0 00000000 */ nop
.L8031B1C4:
/* 0D61C4 8031B1C4 2F21000A */ sltiu $at, $t9, 0xa
/* 0D61C8 8031B1C8 10200131 */ beqz $at, .L8031B690
/* 0D61CC 8031B1CC 0019C880 */ sll $t9, $t9, 2
/* 0D61D0 8031B1D0 3C018033 */ lui $at, %hi(jtbl_80337CB4)
/* 0D61D4 8031B1D4 00390821 */ addu $at, $at, $t9
/* 0D61D8 8031B1D8 8C397CB4 */ lw $t9, %lo(jtbl_80337CB4)($at)
/* 0D61DC 8031B1DC 03200008 */ jr $t9
/* 0D61E0 8031B1E0 00000000 */ nop
glabel L8031B1E4
/* 0D61E4 8031B1E4 26020054 */ addiu $v0, $s0, 0x54
/* 0D61E8 8031B1E8 90430018 */ lbu $v1, 0x18($v0)
/* 0D61EC 8031B1EC 14600005 */ bnez $v1, .L8031B204
/* 0D61F0 8031B1F0 246EFFFF */ addiu $t6, $v1, -1
/* 0D61F4 8031B1F4 0C0C6A84 */ jal seq_channel_layer_disable
/* 0D61F8 8031B1F8 02002025 */ move $a0, $s0
/* 0D61FC 8031B1FC 10000328 */ b .L8031BEA0
/* 0D6200 8031B200 8FBF001C */ lw $ra, 0x1c($sp)
.L8031B204:
/* 0D6204 8031B204 31CF00FF */ andi $t7, $t6, 0xff
/* 0D6208 8031B208 000FC080 */ sll $t8, $t7, 2
/* 0D620C 8031B20C 0058C821 */ addu $t9, $v0, $t8
/* 0D6210 8031B210 A04E0018 */ sb $t6, 0x18($v0)
/* 0D6214 8031B214 8F2E0004 */ lw $t6, 4($t9)
/* 0D6218 8031B218 1000FFD7 */ b .L8031B178
/* 0D621C 8031B21C AC4E0000 */ sw $t6, ($v0)
glabel L8031B220
/* 0D6220 8031B220 26020054 */ addiu $v0, $s0, 0x54
/* 0D6224 8031B224 8C430000 */ lw $v1, ($v0)
/* 0D6228 8031B228 90640000 */ lbu $a0, ($v1)
/* 0D622C 8031B22C 246E0001 */ addiu $t6, $v1, 1
/* 0D6230 8031B230 AC4E0000 */ sw $t6, ($v0)
/* 0D6234 8031B234 91CF0000 */ lbu $t7, ($t6)
/* 0D6238 8031B238 0004CA00 */ sll $t9, $a0, 8
/* 0D623C 8031B23C 01F92825 */ or $a1, $t7, $t9
/* 0D6240 8031B240 904F0018 */ lbu $t7, 0x18($v0)
/* 0D6244 8031B244 25D90001 */ addiu $t9, $t6, 1
/* 0D6248 8031B248 AC590000 */ sw $t9, ($v0)
/* 0D624C 8031B24C 25F80001 */ addiu $t8, $t7, 1
/* 0D6250 8031B250 330E00FF */ andi $t6, $t8, 0xff
/* 0D6254 8031B254 000E7880 */ sll $t7, $t6, 2
/* 0D6258 8031B258 A0580018 */ sb $t8, 0x18($v0)
/* 0D625C 8031B25C 004FC021 */ addu $t8, $v0, $t7
/* 0D6260 8031B260 AF190000 */ sw $t9, ($t8)
/* 0D6264 8031B264 8D8E0014 */ lw $t6, 0x14($t4)
/* 0D6268 8031B268 30AFFFFF */ andi $t7, $a1, 0xffff
/* 0D626C 8031B26C 30AAFFFF */ andi $t2, $a1, 0xffff
/* 0D6270 8031B270 01CFC821 */ addu $t9, $t6, $t7
/* 0D6274 8031B274 1000FFC0 */ b .L8031B178
/* 0D6278 8031B278 AC590000 */ sw $t9, ($v0)
glabel L8031B27C
/* 0D627C 8031B27C 26020054 */ addiu $v0, $s0, 0x54
/* 0D6280 8031B280 8C430000 */ lw $v1, ($v0)
/* 0D6284 8031B284 904E0018 */ lbu $t6, 0x18($v0)
/* 0D6288 8031B288 24780001 */ addiu $t8, $v1, 1
/* 0D628C 8031B28C AC580000 */ sw $t8, ($v0)
/* 0D6290 8031B290 90650000 */ lbu $a1, ($v1)
/* 0D6294 8031B294 004E7821 */ addu $t7, $v0, $t6
/* 0D6298 8031B298 A1E50014 */ sb $a1, 0x14($t7)
/* 0D629C 8031B29C 90590018 */ lbu $t9, 0x18($v0)
/* 0D62A0 8031B2A0 8C4E0000 */ lw $t6, ($v0)
/* 0D62A4 8031B2A4 27380001 */ addiu $t8, $t9, 1
/* 0D62A8 8031B2A8 330F00FF */ andi $t7, $t8, 0xff
/* 0D62AC 8031B2AC 000FC880 */ sll $t9, $t7, 2
/* 0D62B0 8031B2B0 A0580018 */ sb $t8, 0x18($v0)
/* 0D62B4 8031B2B4 0059C021 */ addu $t8, $v0, $t9
/* 0D62B8 8031B2B8 1000FFAF */ b .L8031B178
/* 0D62BC 8031B2BC AF0E0000 */ sw $t6, ($t8)
glabel L8031B2C0
/* 0D62C0 8031B2C0 26020054 */ addiu $v0, $s0, 0x54
/* 0D62C4 8031B2C4 904F0018 */ lbu $t7, 0x18($v0)
/* 0D62C8 8031B2C8 004F2021 */ addu $a0, $v0, $t7
/* 0D62CC 8031B2CC 90990013 */ lbu $t9, 0x13($a0)
/* 0D62D0 8031B2D0 272EFFFF */ addiu $t6, $t9, -1
/* 0D62D4 8031B2D4 A08E0013 */ sb $t6, 0x13($a0)
/* 0D62D8 8031B2D8 90430018 */ lbu $v1, 0x18($v0)
/* 0D62DC 8031B2DC 0043C021 */ addu $t8, $v0, $v1
/* 0D62E0 8031B2E0 930F0013 */ lbu $t7, 0x13($t8)
/* 0D62E4 8031B2E4 00602825 */ move $a1, $v1
/* 0D62E8 8031B2E8 0005C880 */ sll $t9, $a1, 2
/* 0D62EC 8031B2EC 11E00004 */ beqz $t7, .L8031B300
/* 0D62F0 8031B2F0 00597021 */ addu $t6, $v0, $t9
/* 0D62F4 8031B2F4 8DD80000 */ lw $t8, ($t6)
/* 0D62F8 8031B2F8 1000FF9F */ b .L8031B178
/* 0D62FC 8031B2FC AC580000 */ sw $t8, ($v0)
.L8031B300:
/* 0D6300 8031B300 246FFFFF */ addiu $t7, $v1, -1
/* 0D6304 8031B304 1000FF9C */ b .L8031B178
/* 0D6308 8031B308 A04F0018 */ sb $t7, 0x18($v0)
glabel L8031B30C
/* 0D630C 8031B30C 26020054 */ addiu $v0, $s0, 0x54
/* 0D6310 8031B310 8C430000 */ lw $v1, ($v0)
/* 0D6314 8031B314 90640000 */ lbu $a0, ($v1)
/* 0D6318 8031B318 246F0001 */ addiu $t7, $v1, 1
/* 0D631C 8031B31C AC4F0000 */ sw $t7, ($v0)
/* 0D6320 8031B320 91F90000 */ lbu $t9, ($t7)
/* 0D6324 8031B324 0004C200 */ sll $t8, $a0, 8
/* 0D6328 8031B328 25EF0001 */ addiu $t7, $t7, 1
/* 0D632C 8031B32C 03387025 */ or $t6, $t9, $t8
/* 0D6330 8031B330 AC4F0000 */ sw $t7, ($v0)
/* 0D6334 8031B334 8D990014 */ lw $t9, 0x14($t4)
/* 0D6338 8031B338 01C0C025 */ move $t8, $t6
/* 0D633C 8031B33C 330AFFFF */ andi $t2, $t8, 0xffff
/* 0D6340 8031B340 330EFFFF */ andi $t6, $t8, 0xffff
/* 0D6344 8031B344 032EC021 */ addu $t8, $t9, $t6
/* 0D6348 8031B348 1000FF8B */ b .L8031B178
/* 0D634C 8031B34C AC580000 */ sw $t8, ($v0)
glabel L8031B350
/* 0D6350 8031B350 26020054 */ addiu $v0, $s0, 0x54
/* 0D6354 8031B354 8C430000 */ lw $v1, ($v0)
/* 0D6358 8031B358 240100C1 */ li $at, 193
/* 0D635C 8031B35C 90640000 */ lbu $a0, ($v1)
/* 0D6360 8031B360 246F0001 */ addiu $t7, $v1, 1
/* 0D6364 8031B364 14A10008 */ bne $a1, $at, .L8031B388
/* 0D6368 8031B368 AC4F0000 */ sw $t7, ($v0)
/* 0D636C 8031B36C 00840019 */ multu $a0, $a0
/* 0D6370 8031B370 0000C812 */ mflo $t9
/* 0D6374 8031B374 44992000 */ mtc1 $t9, $f4
/* 0D6378 8031B378 00000000 */ nop
/* 0D637C 8031B37C 468021A0 */ cvt.s.w $f6, $f4
/* 0D6380 8031B380 1000FF7D */ b .L8031B178
/* 0D6384 8031B384 E6060024 */ swc1 $f6, 0x24($s0)
.L8031B388:
/* 0D6388 8031B388 44844000 */ mtc1 $a0, $f8
/* 0D638C 8031B38C 00000000 */ nop
/* 0D6390 8031B390 468042A0 */ cvt.s.w $f10, $f8
/* 0D6394 8031B394 46005421 */ cvt.d.s $f16, $f10
/* 0D6398 8031B398 46208482 */ mul.d $f18, $f16, $f0
/* 0D639C 8031B39C 46209120 */ cvt.s.d $f4, $f18
/* 0D63A0 8031B3A0 1000FF75 */ b .L8031B178
/* 0D63A4 8031B3A4 E6040028 */ swc1 $f4, 0x28($s0)
glabel L8031B3A8
/* 0D63A8 8031B3A8 26020054 */ addiu $v0, $s0, 0x54
/* 0D63AC 8031B3AC 8C430000 */ lw $v1, ($v0)
/* 0D63B0 8031B3B0 240100C9 */ li $at, 201
/* 0D63B4 8031B3B4 90640000 */ lbu $a0, ($v1)
/* 0D63B8 8031B3B8 246E0001 */ addiu $t6, $v1, 1
/* 0D63BC 8031B3BC 14A10003 */ bne $a1, $at, .L8031B3CC
/* 0D63C0 8031B3C0 AC4E0000 */ sw $t6, ($v0)
/* 0D63C4 8031B3C4 1000FF6C */ b .L8031B178
/* 0D63C8 8031B3C8 A2040002 */ sb $a0, 2($s0)
.L8031B3CC:
/* 0D63CC 8031B3CC 1000FF6A */ b .L8031B178
/* 0D63D0 8031B3D0 A604001E */ sh $a0, 0x1e($s0)
glabel L8031B3D4
/* 0D63D4 8031B3D4 240100C4 */ li $at, 196
/* 0D63D8 8031B3D8 14A10003 */ bne $a1, $at, .L8031B3E8
/* 0D63DC 8031B3DC 02002025 */ move $a0, $s0
/* 0D63E0 8031B3E0 10000002 */ b .L8031B3EC
/* 0D63E4 8031B3E4 24020001 */ li $v0, 1
.L8031B3E8:
/* 0D63E8 8031B3E8 00001025 */ move $v0, $zero
.L8031B3EC:
/* 0D63EC 8031B3EC 920E0000 */ lbu $t6, ($s0)
/* 0D63F0 8031B3F0 00027900 */ sll $t7, $v0, 4
/* 0D63F4 8031B3F4 31F90010 */ andi $t9, $t7, 0x10
/* 0D63F8 8031B3F8 31D8FFEF */ andi $t8, $t6, 0xffef
/* 0D63FC 8031B3FC 03387825 */ or $t7, $t9, $t8
/* 0D6400 8031B400 A20F0000 */ sb $t7, ($s0)
/* 0D6404 8031B404 AFAD0058 */ sw $t5, 0x58($sp)
/* 0D6408 8031B408 AFAC005C */ sw $t4, 0x5c($sp)
/* 0D640C 8031B40C 0C0C63B1 */ jal seq_channel_layer_note_decay
/* 0D6410 8031B410 A7AA003A */ sh $t2, 0x3a($sp)
/* 0D6414 8031B414 3C013F80 */ li $at, 0x3F800000 # 1.000000
/* 0D6418 8031B418 44810800 */ mtc1 $at, $f1
/* 0D641C 8031B41C 3C0B8022 */ lui $t3, %hi(gBankLoadedPool) # $t3, 0x8022
/* 0D6420 8031B420 3C1F8022 */ lui $ra, %hi(gCtlEntries)
/* 0D6424 8031B424 44800000 */ mtc1 $zero, $f0
/* 0D6428 8031B428 27FF6D60 */ addiu $ra, $ra, %lo(gCtlEntries)
/* 0D642C 8031B42C 256B14F8 */ addiu $t3, %lo(gBankLoadedPool) # addiu $t3, $t3, 0x14f8
/* 0D6430 8031B430 240900FF */ li $t1, 255
/* 0D6434 8031B434 97AA003A */ lhu $t2, 0x3a($sp)
/* 0D6438 8031B438 8FAC005C */ lw $t4, 0x5c($sp)
/* 0D643C 8031B43C 1000FF4E */ b .L8031B178
/* 0D6440 8031B440 8FAD0058 */ lw $t5, 0x58($sp)
glabel L8031B444
/* 0D6444 8031B444 26020054 */ addiu $v0, $s0, 0x54
/* 0D6448 8031B448 8C430000 */ lw $v1, ($v0)
/* 0D644C 8031B44C 90640000 */ lbu $a0, ($v1)
/* 0D6450 8031B450 246E0001 */ addiu $t6, $v1, 1
/* 0D6454 8031B454 AC4E0000 */ sw $t6, ($v0)
/* 0D6458 8031B458 30990080 */ andi $t9, $a0, 0x80
/* 0D645C 8031B45C 1320000A */ beqz $t9, .L8031B488
/* 0D6460 8031B460 00802825 */ move $a1, $a0
/* 0D6464 8031B464 01C01825 */ move $v1, $t6
/* 0D6468 8031B468 91CE0000 */ lbu $t6, ($t6)
/* 0D646C 8031B46C 00052200 */ sll $a0, $a1, 8
/* 0D6470 8031B470 308F7F00 */ andi $t7, $a0, 0x7f00
/* 0D6474 8031B474 01CF2025 */ or $a0, $t6, $t7
/* 0D6478 8031B478 3085FFFF */ andi $a1, $a0, 0xffff
/* 0D647C 8031B47C 24780001 */ addiu $t8, $v1, 1
/* 0D6480 8031B480 AC580000 */ sw $t8, ($v0)
/* 0D6484 8031B484 00A02025 */ move $a0, $a1
.L8031B488:
/* 0D6488 8031B488 308AFFFF */ andi $t2, $a0, 0xffff
/* 0D648C 8031B48C 1000FF3A */ b .L8031B178
/* 0D6490 8031B490 A6050038 */ sh $a1, 0x38($s0)
glabel L8031B494
/* 0D6494 8031B494 26020054 */ addiu $v0, $s0, 0x54
/* 0D6498 8031B498 8C430000 */ lw $v1, ($v0)
/* 0D649C 8031B49C 246F0001 */ addiu $t7, $v1, 1
/* 0D64A0 8031B4A0 AC4F0000 */ sw $t7, ($v0)
/* 0D64A4 8031B4A4 90650000 */ lbu $a1, ($v1)
/* 0D64A8 8031B4A8 28A1007F */ slti $at, $a1, 0x7f
/* 0D64AC 8031B4AC 5020FF33 */ beql $at, $zero, .L8031B17C
/* 0D64B0 8031B4B0 8E020054 */ lw $v0, 0x54($s0)
/* 0D64B4 8031B4B4 91B90005 */ lbu $t9, 5($t5)
/* 0D64B8 8031B4B8 8FEE0000 */ lw $t6, ($ra)
/* 0D64BC 8031B4BC 30A200FF */ andi $v0, $a1, 0xff
/* 0D64C0 8031B4C0 0019C080 */ sll $t8, $t9, 2
/* 0D64C4 8031B4C4 0319C023 */ subu $t8, $t8, $t9
/* 0D64C8 8031B4C8 0018C080 */ sll $t8, $t8, 2
/* 0D64CC 8031B4CC 01D83821 */ addu $a3, $t6, $t8
/* 0D64D0 8031B4D0 90E30001 */ lbu $v1, 1($a3)
/* 0D64D4 8031B4D4 00A3082A */ slt $at, $a1, $v1
/* 0D64D8 8031B4D8 54200008 */ bnezl $at, .L8031B4FC
/* 0D64DC 8031B4DC 8CE30004 */ lw $v1, 4($a3)
/* 0D64E0 8031B4E0 306200FF */ andi $v0, $v1, 0xff
/* 0D64E4 8031B4E4 5040FF25 */ beql $v0, $zero, .L8031B17C
/* 0D64E8 8031B4E8 8E020054 */ lw $v0, 0x54($s0)
/* 0D64EC 8031B4EC 2442FFFF */ addiu $v0, $v0, -1
/* 0D64F0 8031B4F0 304F00FF */ andi $t7, $v0, 0xff
/* 0D64F4 8031B4F4 01E01025 */ move $v0, $t7
/* 0D64F8 8031B4F8 8CE30004 */ lw $v1, 4($a3)
.L8031B4FC:
/* 0D64FC 8031B4FC 0002C880 */ sll $t9, $v0, 2
/* 0D6500 8031B500 26050048 */ addiu $a1, $s0, 0x48
/* 0D6504 8031B504 00797021 */ addu $t6, $v1, $t9
/* 0D6508 8031B508 8DC40000 */ lw $a0, ($t6)
/* 0D650C 8031B50C 5480000C */ bnezl $a0, .L8031B540
/* 0D6510 8031B510 8D630004 */ lw $v1, 4($t3)
/* 0D6514 8031B514 11220009 */ beq $t1, $v0, .L8031B53C
.L8031B518:
/* 0D6518 8031B518 0002C080 */ sll $t8, $v0, 2
/* 0D651C 8031B51C 00787821 */ addu $t7, $v1, $t8
/* 0D6520 8031B520 8DE40000 */ lw $a0, ($t7)
/* 0D6524 8031B524 54800006 */ bnezl $a0, .L8031B540
/* 0D6528 8031B528 8D630004 */ lw $v1, 4($t3)
/* 0D652C 8031B52C 2442FFFF */ addiu $v0, $v0, -1
/* 0D6530 8031B530 305900FF */ andi $t9, $v0, 0xff
/* 0D6534 8031B534 1539FFF8 */ bne $t1, $t9, .L8031B518
/* 0D6538 8031B538 03201025 */ move $v0, $t9
.L8031B53C:
/* 0D653C 8031B53C 8D630004 */ lw $v1, 4($t3)
.L8031B540:
/* 0D6540 8031B540 0083082B */ sltu $at, $a0, $v1
/* 0D6544 8031B544 54200007 */ bnezl $at, .L8031B564
/* 0D6548 8031B548 8D630198 */ lw $v1, 0x198($t3)
/* 0D654C 8031B54C 8D6E000C */ lw $t6, 0xc($t3)
/* 0D6550 8031B550 006EC021 */ addu $t8, $v1, $t6
/* 0D6554 8031B554 0304082B */ sltu $at, $t8, $a0
/* 0D6558 8031B558 5020000B */ beql $at, $zero, .L8031B588
/* 0D655C 8031B55C 8C8E0004 */ lw $t6, 4($a0)
/* 0D6560 8031B560 8D630198 */ lw $v1, 0x198($t3)
.L8031B564:
/* 0D6564 8031B564 0083082B */ sltu $at, $a0, $v1
/* 0D6568 8031B568 5420000E */ bnezl $at, .L8031B5A4
/* 0D656C 8031B56C 3C010002 */ lui $at, 2
/* 0D6570 8031B570 8D6F01A0 */ lw $t7, 0x1a0($t3)
/* 0D6574 8031B574 006FC821 */ addu $t9, $v1, $t7
/* 0D6578 8031B578 0324082B */ sltu $at, $t9, $a0
/* 0D657C 8031B57C 54200009 */ bnezl $at, .L8031B5A4
/* 0D6580 8031B580 3C010002 */ lui $at, 2
/* 0D6584 8031B584 8C8E0004 */ lw $t6, 4($a0)
.L8031B588:
/* 0D6588 8031B588 26020014 */ addiu $v0, $s0, 0x14
/* 0D658C 8031B58C AC4E0004 */ sw $t6, 4($v0)
/* 0D6590 8031B590 90980003 */ lbu $t8, 3($a0)
/* 0D6594 8031B594 A0580000 */ sb $t8, ($v0)
/* 0D6598 8031B598 1000FEF7 */ b .L8031B178
/* 0D659C 8031B59C ACA40000 */ sw $a0, ($a1)
/* 0D65A0 8031B5A0 3C010002 */ lui $at, 2
.L8031B5A4:
/* 0D65A4 8031B5A4 00417821 */ addu $t7, $v0, $at
/* 0D65A8 8031B5A8 3C018033 */ lui $at, %hi(gAudioErrorFlags) # $at, 0x8033
/* 0D65AC 8031B5AC AC2F1D40 */ sw $t7, %lo(gAudioErrorFlags)($at)
/* 0D65B0 8031B5B0 1000FEF1 */ b .L8031B178
/* 0D65B4 8031B5B4 ACA00000 */ sw $zero, ($a1)
glabel L8031B5B8
/* 0D65B8 8031B5B8 26020054 */ addiu $v0, $s0, 0x54
/* 0D65BC 8031B5BC 8C430000 */ lw $v1, ($v0)
/* 0D65C0 8031B5C0 24790001 */ addiu $t9, $v1, 1
/* 0D65C4 8031B5C4 AC590000 */ sw $t9, ($v0)
/* 0D65C8 8031B5C8 90650000 */ lbu $a1, ($v1)
/* 0D65CC 8031B5CC A2050004 */ sb $a1, 4($s0)
/* 0D65D0 8031B5D0 8C430000 */ lw $v1, ($v0)
/* 0D65D4 8031B5D4 246E0001 */ addiu $t6, $v1, 1
/* 0D65D8 8031B5D8 AC4E0000 */ sw $t6, ($v0)
/* 0D65DC 8031B5DC 85B8001A */ lh $t8, 0x1a($t5)
/* 0D65E0 8031B5E0 90670000 */ lbu $a3, ($v1)
/* 0D65E4 8031B5E4 8619001E */ lh $t9, 0x1e($s0)
/* 0D65E8 8031B5E8 03077821 */ addu $t7, $t8, $a3
/* 0D65EC 8031B5EC 85980010 */ lh $t8, 0x10($t4)
/* 0D65F0 8031B5F0 01F97021 */ addu $t6, $t7, $t9
/* 0D65F4 8031B5F4 01D84021 */ addu $t0, $t6, $t8
/* 0D65F8 8031B5F8 310F00FF */ andi $t7, $t0, 0xff
/* 0D65FC 8031B5FC 29E10080 */ slti $at, $t7, 0x80
/* 0D6600 8031B600 14200002 */ bnez $at, .L8031B60C
/* 0D6604 8031B604 01E04025 */ move $t0, $t7
/* 0D6608 8031B608 00004025 */ move $t0, $zero
.L8031B60C:
/* 0D660C 8031B60C 92190004 */ lbu $t9, 4($s0)
/* 0D6610 8031B610 A2080003 */ sb $t0, 3($s0)
/* 0D6614 8031B614 332E0080 */ andi $t6, $t9, 0x80
/* 0D6618 8031B618 51C00009 */ beql $t6, $zero, .L8031B640
/* 0D661C 8031B61C 8C430000 */ lw $v1, ($v0)
/* 0D6620 8031B620 8C580000 */ lw $t8, ($v0)
/* 0D6624 8031B624 930F0000 */ lbu $t7, ($t8)
/* 0D6628 8031B628 A60F001C */ sh $t7, 0x1c($s0)
/* 0D662C 8031B62C 8C590000 */ lw $t9, ($v0)
/* 0D6630 8031B630 272E0001 */ addiu $t6, $t9, 1
/* 0D6634 8031B634 1000FED0 */ b .L8031B178
/* 0D6638 8031B638 AC4E0000 */ sw $t6, ($v0)
/* 0D663C 8031B63C 8C430000 */ lw $v1, ($v0)
.L8031B640:
/* 0D6640 8031B640 90640000 */ lbu $a0, ($v1)
/* 0D6644 8031B644 24780001 */ addiu $t8, $v1, 1
/* 0D6648 8031B648 AC580000 */ sw $t8, ($v0)
/* 0D664C 8031B64C 308F0080 */ andi $t7, $a0, 0x80
/* 0D6650 8031B650 11E0000A */ beqz $t7, .L8031B67C
/* 0D6654 8031B654 00802825 */ move $a1, $a0
/* 0D6658 8031B658 03001825 */ move $v1, $t8
/* 0D665C 8031B65C 93180000 */ lbu $t8, ($t8)
/* 0D6660 8031B660 00052200 */ sll $a0, $a1, 8
/* 0D6664 8031B664 308E7F00 */ andi $t6, $a0, 0x7f00
/* 0D6668 8031B668 030E2025 */ or $a0, $t8, $t6
/* 0D666C 8031B66C 308FFFFF */ andi $t7, $a0, 0xffff
/* 0D6670 8031B670 24790001 */ addiu $t9, $v1, 1
/* 0D6674 8031B674 AC590000 */ sw $t9, ($v0)
/* 0D6678 8031B678 01E02025 */ move $a0, $t7
.L8031B67C:
/* 0D667C 8031B67C 308AFFFF */ andi $t2, $a0, 0xffff
/* 0D6680 8031B680 1000FEBD */ b .L8031B178
/* 0D6684 8031B684 A604001C */ sh $a0, 0x1c($s0)
glabel L8031B688
/* 0D6688 8031B688 1000FEBB */ b .L8031B178
/* 0D668C 8031B68C A2000004 */ sb $zero, 4($s0)
.L8031B690:
glabel L8031B690
/* 0D6690 8031B690 30A200F0 */ andi $v0, $a1, 0xf0
/* 0D6694 8031B694 240100D0 */ li $at, 208
/* 0D6698 8031B698 10410005 */ beq $v0, $at, .L8031B6B0
/* 0D669C 8031B69C 240100E0 */ li $at, 224
/* 0D66A0 8031B6A0 5041000F */ beql $v0, $at, .L8031B6E0
/* 0D66A4 8031B6A4 8D8E008C */ lw $t6, 0x8c($t4)
/* 0D66A8 8031B6A8 1000FEB4 */ b .L8031B17C
/* 0D66AC 8031B6AC 8E020054 */ lw $v0, 0x54($s0)
.L8031B6B0:
/* 0D66B0 8031B6B0 8D8E0088 */ lw $t6, 0x88($t4)
/* 0D66B4 8031B6B4 30B8000F */ andi $t8, $a1, 0xf
/* 0D66B8 8031B6B8 01D87821 */ addu $t7, $t6, $t8
/* 0D66BC 8031B6BC 91EA0000 */ lbu $t2, ($t7)
/* 0D66C0 8031B6C0 014A0019 */ multu $t2, $t2
/* 0D66C4 8031B6C4 0000C812 */ mflo $t9
/* 0D66C8 8031B6C8 44993000 */ mtc1 $t9, $f6
/* 0D66CC 8031B6CC 00000000 */ nop
/* 0D66D0 8031B6D0 46803220 */ cvt.s.w $f8, $f6
/* 0D66D4 8031B6D4 1000FEA8 */ b .L8031B178
/* 0D66D8 8031B6D8 E6080024 */ swc1 $f8, 0x24($s0)
/* 0D66DC 8031B6DC 8D8E008C */ lw $t6, 0x8c($t4)
.L8031B6E0:
/* 0D66E0 8031B6E0 30B8000F */ andi $t8, $a1, 0xf
/* 0D66E4 8031B6E4 01D87821 */ addu $t7, $t6, $t8
/* 0D66E8 8031B6E8 91F90000 */ lbu $t9, ($t7)
/* 0D66EC 8031B6EC 1000FEA2 */ b .L8031B178
/* 0D66F0 8031B6F0 A2190002 */ sb $t9, 2($s0)
.L8031B6F4:
/* 0D66F4 8031B6F4 240100C0 */ li $at, 192
/* 0D66F8 8031B6F8 14A10015 */ bne $a1, $at, .L8031B750
/* 0D66FC 8031B6FC 26020054 */ addiu $v0, $s0, 0x54
/* 0D6700 8031B700 8C430000 */ lw $v1, ($v0)
/* 0D6704 8031B704 90640000 */ lbu $a0, ($v1)
/* 0D6708 8031B708 246E0001 */ addiu $t6, $v1, 1
/* 0D670C 8031B70C AC4E0000 */ sw $t6, ($v0)
/* 0D6710 8031B710 30980080 */ andi $t8, $a0, 0x80
/* 0D6714 8031B714 13000009 */ beqz $t8, .L8031B73C
/* 0D6718 8031B718 00802825 */ move $a1, $a0
/* 0D671C 8031B71C 01C01825 */ move $v1, $t6
/* 0D6720 8031B720 91CE0000 */ lbu $t6, ($t6)
/* 0D6724 8031B724 00042200 */ sll $a0, $a0, 8
/* 0D6728 8031B728 30997F00 */ andi $t9, $a0, 0x7f00
/* 0D672C 8031B72C 246F0001 */ addiu $t7, $v1, 1
/* 0D6730 8031B730 01D92025 */ or $a0, $t6, $t9
/* 0D6734 8031B734 3085FFFF */ andi $a1, $a0, 0xffff
/* 0D6738 8031B738 AC4F0000 */ sw $t7, ($v0)
.L8031B73C:
/* 0D673C 8031B73C 920E0000 */ lbu $t6, ($s0)
/* 0D6740 8031B740 A605003C */ sh $a1, 0x3c($s0)
/* 0D6744 8031B744 35D80020 */ ori $t8, $t6, 0x20
/* 0D6748 8031B748 1000019C */ b .L8031BDBC
/* 0D674C 8031B74C A2180000 */ sb $t8, ($s0)
.L8031B750:
/* 0D6750 8031B750 920F0000 */ lbu $t7, ($s0)
/* 0D6754 8031B754 24010001 */ li $at, 1
/* 0D6758 8031B758 30A900C0 */ andi $t1, $a1, 0xc0
/* 0D675C 8031B75C 31F9FFDF */ andi $t9, $t7, 0xffdf
/* 0D6760 8031B760 A2190000 */ sb $t9, ($s0)
/* 0D6764 8031B764 8DAE0000 */ lw $t6, ($t5)
/* 0D6768 8031B768 000EC180 */ sll $t8, $t6, 6
/* 0D676C 8031B76C 00187FC2 */ srl $t7, $t8, 0x1f
/* 0D6770 8031B770 15E10057 */ bne $t7, $at, .L8031B8D0
/* 0D6774 8031B774 00000000 */ nop
/* 0D6778 8031B778 30A900C0 */ andi $t1, $a1, 0xc0
/* 0D677C 8031B77C 11200009 */ beqz $t1, .L8031B7A4
/* 0D6780 8031B780 26020054 */ addiu $v0, $s0, 0x54
/* 0D6784 8031B784 24010040 */ li $at, 64
/* 0D6788 8031B788 11210023 */ beq $t1, $at, .L8031B818
/* 0D678C 8031B78C 26020054 */ addiu $v0, $s0, 0x54
/* 0D6790 8031B790 24010080 */ li $at, 128
/* 0D6794 8031B794 11210039 */ beq $t1, $at, .L8031B87C
/* 0D6798 8031B798 26020054 */ addiu $v0, $s0, 0x54
/* 0D679C 8031B79C 10000043 */ b .L8031B8AC
/* 0D67A0 8031B7A0 01402025 */ move $a0, $t2
.L8031B7A4:
/* 0D67A4 8031B7A4 8C430000 */ lw $v1, ($v0)
/* 0D67A8 8031B7A8 90660000 */ lbu $a2, ($v1)
/* 0D67AC 8031B7AC 24790001 */ addiu $t9, $v1, 1
/* 0D67B0 8031B7B0 AC590000 */ sw $t9, ($v0)
/* 0D67B4 8031B7B4 30CE0080 */ andi $t6, $a2, 0x80
/* 0D67B8 8031B7B8 11C0000A */ beqz $t6, .L8031B7E4
/* 0D67BC 8031B7BC 00C03825 */ or $a3, $a2, $zero
/* 0D67C0 8031B7C0 03201825 */ move $v1, $t9
/* 0D67C4 8031B7C4 93390000 */ lbu $t9, ($t9)
/* 0D67C8 8031B7C8 00073200 */ sll $a2, $a3, 8
/* 0D67CC 8031B7CC 30CF7F00 */ andi $t7, $a2, 0x7f00
/* 0D67D0 8031B7D0 032F3025 */ or $a2, $t9, $t7
/* 0D67D4 8031B7D4 30C7FFFF */ andi $a3, $a2, 0xffff
/* 0D67D8 8031B7D8 24780001 */ addiu $t8, $v1, 1
/* 0D67DC 8031B7DC AC580000 */ sw $t8, ($v0)
/* 0D67E0 8031B7E0 00E03025 */ move $a2, $a3
.L8031B7E4:
/* 0D67E4 8031B7E4 8C430000 */ lw $v1, ($v0)
/* 0D67E8 8031B7E8 30CAFFFF */ andi $t2, $a2, 0xffff
/* 0D67EC 8031B7EC 01402025 */ move $a0, $t2
/* 0D67F0 8031B7F0 906B0000 */ lbu $t3, ($v1)
/* 0D67F4 8031B7F4 246F0001 */ addiu $t7, $v1, 1
/* 0D67F8 8031B7F8 AC4F0000 */ sw $t7, ($v0)
/* 0D67FC 8031B7FC 91EE0000 */ lbu $t6, ($t7)
/* 0D6800 8031B800 A20E0002 */ sb $t6, 2($s0)
/* 0D6804 8031B804 8C580000 */ lw $t8, ($v0)
/* 0D6808 8031B808 270F0001 */ addiu $t7, $t8, 1
/* 0D680C 8031B80C AC4F0000 */ sw $t7, ($v0)
/* 0D6810 8031B810 10000027 */ b .L8031B8B0
/* 0D6814 8031B814 A607003A */ sh $a3, 0x3a($s0)
.L8031B818:
/* 0D6818 8031B818 8C430000 */ lw $v1, ($v0)
/* 0D681C 8031B81C 90660000 */ lbu $a2, ($v1)
/* 0D6820 8031B820 24790001 */ addiu $t9, $v1, 1
/* 0D6824 8031B824 AC590000 */ sw $t9, ($v0)
/* 0D6828 8031B828 30CE0080 */ andi $t6, $a2, 0x80
/* 0D682C 8031B82C 11C0000A */ beqz $t6, .L8031B858
/* 0D6830 8031B830 00C03825 */ or $a3, $a2, $zero
/* 0D6834 8031B834 03201825 */ move $v1, $t9
/* 0D6838 8031B838 93390000 */ lbu $t9, ($t9)
/* 0D683C 8031B83C 00073200 */ sll $a2, $a3, 8
/* 0D6840 8031B840 30CF7F00 */ andi $t7, $a2, 0x7f00
/* 0D6844 8031B844 032F3025 */ or $a2, $t9, $t7
/* 0D6848 8031B848 30C7FFFF */ andi $a3, $a2, 0xffff
/* 0D684C 8031B84C 24780001 */ addiu $t8, $v1, 1
/* 0D6850 8031B850 AC580000 */ sw $t8, ($v0)
/* 0D6854 8031B854 00E03025 */ move $a2, $a3
.L8031B858:
/* 0D6858 8031B858 8C430000 */ lw $v1, ($v0)
/* 0D685C 8031B85C 30CAFFFF */ andi $t2, $a2, 0xffff
/* 0D6860 8031B860 01402025 */ move $a0, $t2
/* 0D6864 8031B864 906B0000 */ lbu $t3, ($v1)
/* 0D6868 8031B868 246F0001 */ addiu $t7, $v1, 1
/* 0D686C 8031B86C AC4F0000 */ sw $t7, ($v0)
/* 0D6870 8031B870 A2000002 */ sb $zero, 2($s0)
/* 0D6874 8031B874 1000000E */ b .L8031B8B0
/* 0D6878 8031B878 A607003A */ sh $a3, 0x3a($s0)
.L8031B87C:
/* 0D687C 8031B87C 8C430000 */ lw $v1, ($v0)
/* 0D6880 8031B880 960A003A */ lhu $t2, 0x3a($s0)
/* 0D6884 8031B884 906B0000 */ lbu $t3, ($v1)
/* 0D6888 8031B888 24790001 */ addiu $t9, $v1, 1
/* 0D688C 8031B88C AC590000 */ sw $t9, ($v0)
/* 0D6890 8031B890 93380000 */ lbu $t8, ($t9)
/* 0D6894 8031B894 01402025 */ move $a0, $t2
/* 0D6898 8031B898 A2180002 */ sb $t8, 2($s0)
/* 0D689C 8031B89C 8C4F0000 */ lw $t7, ($v0)
/* 0D68A0 8031B8A0 25F90001 */ addiu $t9, $t7, 1
/* 0D68A4 8031B8A4 10000002 */ b .L8031B8B0
/* 0D68A8 8031B8A8 AC590000 */ sw $t9, ($v0)
.L8031B8AC:
/* 0D68AC 8031B8AC 8FAB0030 */ lw $t3, 0x30($sp)
.L8031B8B0:
/* 0D68B0 8031B8B0 016B0019 */ multu $t3, $t3
/* 0D68B4 8031B8B4 00A91823 */ subu $v1, $a1, $t1
/* 0D68B8 8031B8B8 00007012 */ mflo $t6
/* 0D68BC 8031B8BC 448E5000 */ mtc1 $t6, $f10
/* 0D68C0 8031B8C0 00000000 */ nop
/* 0D68C4 8031B8C4 46805420 */ cvt.s.w $f16, $f10
/* 0D68C8 8031B8C8 10000024 */ b .L8031B95C
/* 0D68CC 8031B8CC E6100024 */ swc1 $f16, 0x24($s0)
.L8031B8D0:
/* 0D68D0 8031B8D0 11200008 */ beqz $t1, .L8031B8F4
/* 0D68D4 8031B8D4 26020054 */ addiu $v0, $s0, 0x54
/* 0D68D8 8031B8D8 24010040 */ li $at, 64
/* 0D68DC 8031B8DC 11210019 */ beq $t1, $at, .L8031B944
/* 0D68E0 8031B8E0 24010080 */ li $at, 128
/* 0D68E4 8031B8E4 5121001B */ beql $t1, $at, .L8031B954
/* 0D68E8 8031B8E8 960A003A */ lhu $t2, 0x3a($s0)
/* 0D68EC 8031B8EC 1000001A */ b .L8031B958
/* 0D68F0 8031B8F0 01402025 */ move $a0, $t2
.L8031B8F4:
/* 0D68F4 8031B8F4 8C430000 */ lw $v1, ($v0)
/* 0D68F8 8031B8F8 90660000 */ lbu $a2, ($v1)
/* 0D68FC 8031B8FC 24780001 */ addiu $t8, $v1, 1
/* 0D6900 8031B900 AC580000 */ sw $t8, ($v0)
/* 0D6904 8031B904 30CF0080 */ andi $t7, $a2, 0x80
/* 0D6908 8031B908 11E0000A */ beqz $t7, .L8031B934
/* 0D690C 8031B90C 00C03825 */ or $a3, $a2, $zero
/* 0D6910 8031B910 03001825 */ move $v1, $t8
/* 0D6914 8031B914 93180000 */ lbu $t8, ($t8)
/* 0D6918 8031B918 00073200 */ sll $a2, $a3, 8
/* 0D691C 8031B91C 30CE7F00 */ andi $t6, $a2, 0x7f00
/* 0D6920 8031B920 030E3025 */ or $a2, $t8, $t6
/* 0D6924 8031B924 30C7FFFF */ andi $a3, $a2, 0xffff
/* 0D6928 8031B928 24790001 */ addiu $t9, $v1, 1
/* 0D692C 8031B92C AC590000 */ sw $t9, ($v0)
/* 0D6930 8031B930 00E03025 */ move $a2, $a3
.L8031B934:
/* 0D6934 8031B934 30CAFFFF */ andi $t2, $a2, 0xffff
/* 0D6938 8031B938 A607003A */ sh $a3, 0x3a($s0)
/* 0D693C 8031B93C 10000006 */ b .L8031B958
/* 0D6940 8031B940 01402025 */ move $a0, $t2
.L8031B944:
/* 0D6944 8031B944 960A0038 */ lhu $t2, 0x38($s0)
/* 0D6948 8031B948 10000003 */ b .L8031B958
/* 0D694C 8031B94C 01402025 */ move $a0, $t2
/* 0D6950 8031B950 960A003A */ lhu $t2, 0x3a($s0)
.L8031B954:
/* 0D6954 8031B954 01402025 */ move $a0, $t2
.L8031B958:
/* 0D6958 8031B958 00A91823 */ subu $v1, $a1, $t1
.L8031B95C:
/* 0D695C 8031B95C 920E0002 */ lbu $t6, 2($s0)
/* 0D6960 8031B960 A604003C */ sh $a0, 0x3c($s0)
/* 0D6964 8031B964 01C40019 */ multu $t6, $a0
/* 0D6968 8031B968 0000C012 */ mflo $t8
/* 0D696C 8031B96C 07010003 */ bgez $t8, .L8031B97C
/* 0D6970 8031B970 00187A03 */ sra $t7, $t8, 8
/* 0D6974 8031B974 270100FF */ addiu $at, $t8, 0xff
/* 0D6978 8031B978 00017A03 */ sra $t7, $at, 8
.L8031B97C:
/* 0D697C 8031B97C A60F003E */ sh $t7, 0x3e($s0)
/* 0D6980 8031B980 8D990000 */ lw $t9, ($t4)
/* 0D6984 8031B984 0019C080 */ sll $t8, $t9, 2
/* 0D6988 8031B988 07030006 */ bgezl $t8, .L8031B9A4
/* 0D698C 8031B98C 8DA20000 */ lw $v0, ($t5)
/* 0D6990 8031B990 91AF0002 */ lbu $t7, 2($t5)
/* 0D6994 8031B994 31F90040 */ andi $t9, $t7, 0x40
/* 0D6998 8031B998 57200008 */ bnezl $t9, .L8031B9BC
/* 0D699C 8031B99C 92180000 */ lbu $t8, ($s0)
/* 0D69A0 8031B9A0 8DA20000 */ lw $v0, ($t5)
.L8031B9A4:
/* 0D69A4 8031B9A4 0002C0C0 */ sll $t8, $v0, 3
/* 0D69A8 8031B9A8 07000003 */ bltz $t8, .L8031B9B8
/* 0D69AC 8031B9AC 0002C900 */ sll $t9, $v0, 4
/* 0D69B0 8031B9B0 07220006 */ bltzl $t9, .L8031B9CC
/* 0D69B4 8031B9B4 85B90018 */ lh $t9, 0x18($t5)
.L8031B9B8:
/* 0D69B8 8031B9B8 92180000 */ lbu $t8, ($s0)
.L8031B9BC:
/* 0D69BC 8031B9BC 370F0020 */ ori $t7, $t8, 0x20
/* 0D69C0 8031B9C0 100000FE */ b .L8031BDBC
/* 0D69C4 8031B9C4 A20F0000 */ sb $t7, ($s0)
/* 0D69C8 8031B9C8 85B90018 */ lh $t9, 0x18($t5)
.L8031B9CC:
/* 0D69CC 8031B9CC 5720003B */ bnezl $t9, .L8031BABC
/* 0D69D0 8031B9D0 85980010 */ lh $t8, 0x10($t4)
/* 0D69D4 8031B9D4 85B8001A */ lh $t8, 0x1a($t5)
/* 0D69D8 8031B9D8 8619001E */ lh $t9, 0x1e($s0)
/* 0D69DC 8031B9DC 00787821 */ addu $t7, $v1, $t8
/* 0D69E0 8031B9E0 01F94021 */ addu $t0, $t7, $t9
/* 0D69E4 8031B9E4 91AF0005 */ lbu $t7, 5($t5)
/* 0D69E8 8031B9E8 8FF80000 */ lw $t8, ($ra)
/* 0D69EC 8031B9EC 310E00FF */ andi $t6, $t0, 0xff
/* 0D69F0 8031B9F0 000FC880 */ sll $t9, $t7, 2
/* 0D69F4 8031B9F4 032FC823 */ subu $t9, $t9, $t7
/* 0D69F8 8031B9F8 0019C880 */ sll $t9, $t9, 2
/* 0D69FC 8031B9FC 03193821 */ addu $a3, $t8, $t9
/* 0D6A00 8031BA00 90E20002 */ lbu $v0, 2($a3)
/* 0D6A04 8031BA04 01C04025 */ move $t0, $t6
/* 0D6A08 8031BA08 01C2082A */ slt $at, $t6, $v0
/* 0D6A0C 8031BA0C 5420000C */ bnezl $at, .L8031BA40
/* 0D6A10 8031BA10 8CEE0008 */ lw $t6, 8($a3)
/* 0D6A14 8031BA14 304800FF */ andi $t0, $v0, 0xff
/* 0D6A18 8031BA18 55000006 */ bnezl $t0, .L8031BA34
/* 0D6A1C 8031BA1C 2508FFFF */ addiu $t0, $t0, -1
/* 0D6A20 8031BA20 920F0000 */ lbu $t7, ($s0)
/* 0D6A24 8031BA24 35F80020 */ ori $t8, $t7, 0x20
/* 0D6A28 8031BA28 100000E2 */ b .L8031BDB4
/* 0D6A2C 8031BA2C A2180000 */ sb $t8, ($s0)
/* 0D6A30 8031BA30 2508FFFF */ addiu $t0, $t0, -1
.L8031BA34:
/* 0D6A34 8031BA34 311900FF */ andi $t9, $t0, 0xff
/* 0D6A38 8031BA38 03204025 */ move $t0, $t9
/* 0D6A3C 8031BA3C 8CEE0008 */ lw $t6, 8($a3)
.L8031BA40:
/* 0D6A40 8031BA40 00087880 */ sll $t7, $t0, 2
/* 0D6A44 8031BA44 01CFC021 */ addu $t8, $t6, $t7
/* 0D6A48 8031BA48 8F020000 */ lw $v0, ($t8)
/* 0D6A4C 8031BA4C 54400006 */ bnezl $v0, .L8031BA68
/* 0D6A50 8031BA50 8C58000C */ lw $t8, 0xc($v0)
/* 0D6A54 8031BA54 920E0000 */ lbu $t6, ($s0)
/* 0D6A58 8031BA58 35CF0020 */ ori $t7, $t6, 0x20
/* 0D6A5C 8031BA5C 100000D5 */ b .L8031BDB4
/* 0D6A60 8031BA60 A20F0000 */ sb $t7, ($s0)
/* 0D6A64 8031BA64 8C58000C */ lw $t8, 0xc($v0)
.L8031BA68:
/* 0D6A68 8031BA68 3C014F80 */ li $at, 0x4F800000 # 4294967296.000000
/* 0D6A6C 8031BA6C AE180018 */ sw $t8, 0x18($s0)
/* 0D6A70 8031BA70 90590000 */ lbu $t9, ($v0)
/* 0D6A74 8031BA74 A2190014 */ sb $t9, 0x14($s0)
/* 0D6A78 8031BA78 904E0001 */ lbu $t6, 1($v0)
/* 0D6A7C 8031BA7C 448E9000 */ mtc1 $t6, $f18
/* 0D6A80 8031BA80 05C10004 */ bgez $t6, .L8031BA94
/* 0D6A84 8031BA84 46809120 */ cvt.s.w $f4, $f18
/* 0D6A88 8031BA88 44813000 */ mtc1 $at, $f6
/* 0D6A8C 8031BA8C 00000000 */ nop
/* 0D6A90 8031BA90 46062100 */ add.s $f4, $f4, $f6
.L8031BA94:
/* 0D6A94 8031BA94 46002221 */ cvt.d.s $f8, $f4
/* 0D6A98 8031BA98 24430004 */ addiu $v1, $v0, 4
/* 0D6A9C 8031BA9C 46204282 */ mul.d $f10, $f8, $f0
/* 0D6AA0 8031BAA0 AE03004C */ sw $v1, 0x4c($s0)
/* 0D6AA4 8031BAA4 46205420 */ cvt.s.d $f16, $f10
/* 0D6AA8 8031BAA8 E6100028 */ swc1 $f16, 0x28($s0)
/* 0D6AAC 8031BAAC C4720004 */ lwc1 $f18, 4($v1)
/* 0D6AB0 8031BAB0 100000C0 */ b .L8031BDB4
/* 0D6AB4 8031BAB4 E6120020 */ swc1 $f18, 0x20($s0)
/* 0D6AB8 8031BAB8 85980010 */ lh $t8, 0x10($t4)
.L8031BABC:
/* 0D6ABC 8031BABC 85AE001A */ lh $t6, 0x1a($t5)
/* 0D6AC0 8031BAC0 0078C821 */ addu $t9, $v1, $t8
/* 0D6AC4 8031BAC4 8618001E */ lh $t8, 0x1e($s0)
/* 0D6AC8 8031BAC8 032E7821 */ addu $t7, $t9, $t6
/* 0D6ACC 8031BACC 01F84021 */ addu $t0, $t7, $t8
/* 0D6AD0 8031BAD0 310200FF */ andi $v0, $t0, 0xff
/* 0D6AD4 8031BAD4 28410080 */ slti $at, $v0, 0x80
/* 0D6AD8 8031BAD8 14200005 */ bnez $at, .L8031BAF0
/* 0D6ADC 8031BADC 00404025 */ move $t0, $v0
/* 0D6AE0 8031BAE0 920F0000 */ lbu $t7, ($s0)
/* 0D6AE4 8031BAE4 35F80020 */ ori $t8, $t7, 0x20
/* 0D6AE8 8031BAE8 100000B2 */ b .L8031BDB4
/* 0D6AEC 8031BAEC A2180000 */ sb $t8, ($s0)
.L8031BAF0:
/* 0D6AF0 8031BAF0 8E030048 */ lw $v1, 0x48($s0)
/* 0D6AF4 8031BAF4 54600003 */ bnezl $v1, .L8031BB04
/* 0D6AF8 8031BAF8 92190004 */ lbu $t9, 4($s0)
/* 0D6AFC 8031BAFC 8DA3003C */ lw $v1, 0x3c($t5)
/* 0D6B00 8031BB00 92190004 */ lbu $t9, 4($s0)
.L8031BB04:
/* 0D6B04 8031BB04 13200088 */ beqz $t9, .L8031BD28
/* 0D6B08 8031BB08 00000000 */ nop
/* 0D6B0C 8031BB0C 92040003 */ lbu $a0, 3($s0)
/* 0D6B10 8031BB10 0082082A */ slt $at, $a0, $v0
/* 0D6B14 8031BB14 10200003 */ beqz $at, .L8031BB24
/* 0D6B18 8031BB18 00802825 */ move $a1, $a0
/* 0D6B1C 8031BB1C 10000001 */ b .L8031BB24
/* 0D6B20 8031BB20 00402825 */ move $a1, $v0
.L8031BB24:
/* 0D6B24 8031BB24 10600017 */ beqz $v1, .L8031BB84
/* 0D6B28 8031BB28 3C013F80 */ li $at, 0x3F800000 # 1.000000
/* 0D6B2C 8031BB2C 906E0001 */ lbu $t6, 1($v1)
/* 0D6B30 8031BB30 30A200FF */ andi $v0, $a1, 0xff
/* 0D6B34 8031BB34 004E082A */ slt $at, $v0, $t6
/* 0D6B38 8031BB38 50200004 */ beql $at, $zero, .L8031BB4C
/* 0D6B3C 8031BB3C 906F0002 */ lbu $t7, 2($v1)
/* 0D6B40 8031BB40 10000009 */ b .L8031BB68
/* 0D6B44 8031BB44 24620008 */ addiu $v0, $v1, 8
/* 0D6B48 8031BB48 906F0002 */ lbu $t7, 2($v1)
.L8031BB4C:
/* 0D6B4C 8031BB4C 24640018 */ addiu $a0, $v1, 0x18
/* 0D6B50 8031BB50 01E2082A */ slt $at, $t7, $v0
/* 0D6B54 8031BB54 14200003 */ bnez $at, .L8031BB64
/* 0D6B58 8031BB58 00000000 */ nop
/* 0D6B5C 8031BB5C 10000001 */ b .L8031BB64
/* 0D6B60 8031BB60 24640010 */ addiu $a0, $v1, 0x10
.L8031BB64:
/* 0D6B64 8031BB64 00801025 */ move $v0, $a0
.L8031BB68:
/* 0D6B68 8031BB68 8E18004C */ lw $t8, 0x4c($s0)
/* 0D6B6C 8031BB6C 0058C826 */ xor $t9, $v0, $t8
/* 0D6B70 8031BB70 2F390001 */ sltiu $t9, $t9, 1
/* 0D6B74 8031BB74 A3B9003F */ sb $t9, 0x3f($sp)
/* 0D6B78 8031BB78 AE02004C */ sw $v0, 0x4c($s0)
/* 0D6B7C 8031BB7C 10000003 */ b .L8031BB8C
/* 0D6B80 8031BB80 C4400004 */ lwc1 $f0, 4($v0)
.L8031BB84:
/* 0D6B84 8031BB84 44810000 */ mtc1 $at, $f0
/* 0D6B88 8031BB88 AE00004C */ sw $zero, 0x4c($s0)
.L8031BB8C:
/* 0D6B8C 8031BB8C 3C038033 */ lui $v1, %hi(gNoteFrequencies)
/* 0D6B90 8031BB90 24632884 */ addiu $v1, %lo(gNoteFrequencies) # addiu $v1, $v1, 0x2884
/* 0D6B94 8031BB94 00087080 */ sll $t6, $t0, 2
/* 0D6B98 8031BB98 92180003 */ lbu $t8, 3($s0)
/* 0D6B9C 8031BB9C 006E7821 */ addu $t7, $v1, $t6
/* 0D6BA0 8031BBA0 C5E60000 */ lwc1 $f6, ($t7)
/* 0D6BA4 8031BBA4 920F0004 */ lbu $t7, 4($s0)
/* 0D6BA8 8031BBA8 0018C880 */ sll $t9, $t8, 2
/* 0D6BAC 8031BBAC 00797021 */ addu $t6, $v1, $t9
/* 0D6BB0 8031BBB0 C5C40000 */ lwc1 $f4, ($t6)
/* 0D6BB4 8031BBB4 46003082 */ mul.s $f2, $f6, $f0
/* 0D6BB8 8031BBB8 2401FF7F */ li $at, -129
/* 0D6BBC 8031BBBC 01E1C024 */ and $t8, $t7, $at
/* 0D6BC0 8031BBC0 2719FFFF */ addiu $t9, $t8, -1
/* 0D6BC4 8031BBC4 2F210005 */ sltiu $at, $t9, 5
/* 0D6BC8 8031BBC8 46002302 */ mul.s $f12, $f4, $f0
/* 0D6BCC 8031BBCC 1020000C */ beqz $at, .L8031BC00
/* 0D6BD0 8031BBD0 0019C880 */ sll $t9, $t9, 2
/* 0D6BD4 8031BBD4 3C018033 */ lui $at, %hi(jtbl_80337CDC)
/* 0D6BD8 8031BBD8 00390821 */ addu $at, $at, $t9
/* 0D6BDC 8031BBDC 8C397CDC */ lw $t9, %lo(jtbl_80337CDC)($at)
/* 0D6BE0 8031BBE0 03200008 */ jr $t9
/* 0D6BE4 8031BBE4 00000000 */ nop
glabel L8031BBE8
/* 0D6BE8 8031BBE8 E7A20024 */ swc1 $f2, 0x24($sp)
/* 0D6BEC 8031BBEC 10000005 */ b .L8031BC04
/* 0D6BF0 8031BBF0 46006006 */ mov.s $f0, $f12
glabel L8031BBF4
/* 0D6BF4 8031BBF4 46001006 */ mov.s $f0, $f2
/* 0D6BF8 8031BBF8 10000002 */ b .L8031BC04
/* 0D6BFC 8031BBFC E7AC0024 */ swc1 $f12, 0x24($sp)
.L8031BC00:
/* 0D6C00 8031BC00 C7A00028 */ lwc1 $f0, 0x28($sp)
.L8031BC04:
/* 0D6C04 8031BC04 C7A80024 */ lwc1 $f8, 0x24($sp)
/* 0D6C08 8031BC08 3C013FF0 */ li $at, 0x3FF00000 # 1.875000
/* 0D6C0C 8031BC0C 44819800 */ mtc1 $at, $f19
/* 0D6C10 8031BC10 46004283 */ div.s $f10, $f8, $f0
/* 0D6C14 8031BC14 44809000 */ mtc1 $zero, $f18
/* 0D6C18 8031BC18 26020004 */ addiu $v0, $s0, 4
/* 0D6C1C 8031BC1C 46005421 */ cvt.d.s $f16, $f10
/* 0D6C20 8031BC20 46328181 */ sub.d $f6, $f16, $f18
/* 0D6C24 8031BC24 46203120 */ cvt.s.d $f4, $f6
/* 0D6C28 8031BC28 E444000C */ swc1 $f4, 0xc($v0)
/* 0D6C2C 8031BC2C 920E0004 */ lbu $t6, 4($s0)
/* 0D6C30 8031BC30 31CF0080 */ andi $t7, $t6, 0x80
/* 0D6C34 8031BC34 11E00023 */ beqz $t7, .L8031BCC4
/* 0D6C38 8031BC38 3C0E8022 */ lui $t6, %hi(gTempoInternalToExternal)
/* 0D6C3C 8031BC3C 9598000A */ lhu $t8, 0xa($t4)
/* 0D6C40 8031BC40 3C018033 */ lui $at, %hi(D_80337CF0)
/* 0D6C44 8031BC44 D4287CF0 */ ldc1 $f8, %lo(D_80337CF0)($at)
/* 0D6C48 8031BC48 44985000 */ mtc1 $t8, $f10
/* 0D6C4C 8031BC4C 3C014F80 */ li $at, 0x4F800000 # 4294967296.000000
/* 0D6C50 8031BC50 07010004 */ bgez $t8, .L8031BC64
/* 0D6C54 8031BC54 46805420 */ cvt.s.w $f16, $f10
/* 0D6C58 8031BC58 44819000 */ mtc1 $at, $f18
/* 0D6C5C 8031BC5C 00000000 */ nop
/* 0D6C60 8031BC60 46128400 */ add.s $f16, $f16, $f18
.L8031BC64:
/* 0D6C64 8031BC64 8619003C */ lh $t9, 0x3c($s0)
/* 0D6C68 8031BC68 85CE6D7C */ lh $t6, %lo(gTempoInternalToExternal)($t6)
/* 0D6C6C 8031BC6C 460081A1 */ cvt.d.s $f6, $f16
/* 0D6C70 8031BC70 44995000 */ mtc1 $t9, $f10
/* 0D6C74 8031BC74 448E8000 */ mtc1 $t6, $f16
/* 0D6C78 8031BC78 46264102 */ mul.d $f4, $f8, $f6
/* 0D6C7C 8031BC7C 960F001C */ lhu $t7, 0x1c($s0)
/* 0D6C80 8031BC80 3C014F80 */ li $at, 0x4F800000 # 4294967296.000000
/* 0D6C84 8031BC84 468054A0 */ cvt.s.w $f18, $f10
/* 0D6C88 8031BC88 448F5000 */ mtc1 $t7, $f10
/* 0D6C8C 8031BC8C 46808220 */ cvt.s.w $f8, $f16
/* 0D6C90 8031BC90 46805420 */ cvt.s.w $f16, $f10
/* 0D6C94 8031BC94 46089182 */ mul.s $f6, $f18, $f8
/* 0D6C98 8031BC98 05E10004 */ bgez $t7, .L8031BCAC
/* 0D6C9C 8031BC9C 00000000 */ nop
/* 0D6CA0 8031BCA0 44819000 */ mtc1 $at, $f18
/* 0D6CA4 8031BCA4 00000000 */ nop
/* 0D6CA8 8031BCA8 46128400 */ add.s $f16, $f16, $f18
.L8031BCAC:
/* 0D6CAC 8031BCAC 46068202 */ mul.s $f8, $f16, $f6
/* 0D6CB0 8031BCB0 460042A1 */ cvt.d.s $f10, $f8
/* 0D6CB4 8031BCB4 462A2483 */ div.d $f18, $f4, $f10
/* 0D6CB8 8031BCB8 46209420 */ cvt.s.d $f16, $f18
/* 0D6CBC 8031BCBC 1000000F */ b .L8031BCFC
/* 0D6CC0 8031BCC0 E4500008 */ swc1 $f16, 8($v0)
.L8031BCC4:
/* 0D6CC4 8031BCC4 9618001C */ lhu $t8, 0x1c($s0)
/* 0D6CC8 8031BCC8 3C018033 */ lui $at, %hi(D_80337CF8)
/* 0D6CCC 8031BCCC D4267CF8 */ ldc1 $f6, %lo(D_80337CF8)($at)
/* 0D6CD0 8031BCD0 44984000 */ mtc1 $t8, $f8
/* 0D6CD4 8031BCD4 3C014F80 */ li $at, 0x4F800000 # 4294967296.000000
/* 0D6CD8 8031BCD8 07010004 */ bgez $t8, .L8031BCEC
/* 0D6CDC 8031BCDC 46804120 */ cvt.s.w $f4, $f8
/* 0D6CE0 8031BCE0 44815000 */ mtc1 $at, $f10
/* 0D6CE4 8031BCE4 00000000 */ nop
/* 0D6CE8 8031BCE8 460A2100 */ add.s $f4, $f4, $f10
.L8031BCEC:
/* 0D6CEC 8031BCEC 460024A1 */ cvt.d.s $f18, $f4
/* 0D6CF0 8031BCF0 46323403 */ div.d $f16, $f6, $f18
/* 0D6CF4 8031BCF4 46208220 */ cvt.s.d $f8, $f16
/* 0D6CF8 8031BCF8 E4480008 */ swc1 $f8, 8($v0)
.L8031BCFC:
/* 0D6CFC 8031BCFC 44805000 */ mtc1 $zero, $f10
/* 0D6D00 8031BD00 2401FF7F */ li $at, -129
/* 0D6D04 8031BD04 E44A0004 */ swc1 $f10, 4($v0)
/* 0D6D08 8031BD08 92190004 */ lbu $t9, 4($s0)
/* 0D6D0C 8031BD0C E6000020 */ swc1 $f0, 0x20($s0)
/* 0D6D10 8031BD10 03217024 */ and $t6, $t9, $at
/* 0D6D14 8031BD14 24010005 */ li $at, 5
/* 0D6D18 8031BD18 55C10027 */ bnel $t6, $at, .L8031BDB8
/* 0D6D1C 8031BD1C 860F003C */ lh $t7, 0x3c($s0)
/* 0D6D20 8031BD20 10000024 */ b .L8031BDB4
/* 0D6D24 8031BD24 A2080003 */ sb $t0, 3($s0)
.L8031BD28:
/* 0D6D28 8031BD28 1060001C */ beqz $v1, .L8031BD9C
/* 0D6D2C 8031BD2C 0008C880 */ sll $t9, $t0, 2
/* 0D6D30 8031BD30 906F0001 */ lbu $t7, 1($v1)
/* 0D6D34 8031BD34 004F082A */ slt $at, $v0, $t7
/* 0D6D38 8031BD38 10200003 */ beqz $at, .L8031BD48
/* 0D6D3C 8031BD3C 00087880 */ sll $t7, $t0, 2
/* 0D6D40 8031BD40 10000009 */ b .L8031BD68
/* 0D6D44 8031BD44 24620008 */ addiu $v0, $v1, 8
.L8031BD48:
/* 0D6D48 8031BD48 90780002 */ lbu $t8, 2($v1)
/* 0D6D4C 8031BD4C 24640018 */ addiu $a0, $v1, 0x18
/* 0D6D50 8031BD50 0302082A */ slt $at, $t8, $v0
/* 0D6D54 8031BD54 14200003 */ bnez $at, .L8031BD64
/* 0D6D58 8031BD58 00000000 */ nop
/* 0D6D5C 8031BD5C 10000001 */ b .L8031BD64
/* 0D6D60 8031BD60 24640010 */ addiu $a0, $v1, 0x10
.L8031BD64:
/* 0D6D64 8031BD64 00801025 */ move $v0, $a0
.L8031BD68:
/* 0D6D68 8031BD68 8E19004C */ lw $t9, 0x4c($s0)
/* 0D6D6C 8031BD6C 3C038033 */ lui $v1, %hi(gNoteFrequencies) # $v1, 0x8033
/* 0D6D70 8031BD70 24632884 */ addiu $v1, %lo(gNoteFrequencies) # addiu $v1, $v1, 0x2884
/* 0D6D74 8031BD74 00597026 */ xor $t6, $v0, $t9
/* 0D6D78 8031BD78 2DCE0001 */ sltiu $t6, $t6, 1
/* 0D6D7C 8031BD7C A3AE003F */ sb $t6, 0x3f($sp)
/* 0D6D80 8031BD80 AE02004C */ sw $v0, 0x4c($s0)
/* 0D6D84 8031BD84 006FC021 */ addu $t8, $v1, $t7
/* 0D6D88 8031BD88 C7060000 */ lwc1 $f6, ($t8)
/* 0D6D8C 8031BD8C C4440004 */ lwc1 $f4, 4($v0)
/* 0D6D90 8031BD90 46062482 */ mul.s $f18, $f4, $f6
/* 0D6D94 8031BD94 10000007 */ b .L8031BDB4
/* 0D6D98 8031BD98 E6120020 */ swc1 $f18, 0x20($s0)
.L8031BD9C:
/* 0D6D9C 8031BD9C 3C038033 */ lui $v1, %hi(gNoteFrequencies) # $v1, 0x8033
/* 0D6DA0 8031BDA0 24632884 */ addiu $v1, %lo(gNoteFrequencies) # addiu $v1, $v1, 0x2884
/* 0D6DA4 8031BDA4 AE00004C */ sw $zero, 0x4c($s0)
/* 0D6DA8 8031BDA8 00797021 */ addu $t6, $v1, $t9
/* 0D6DAC 8031BDAC C5D00000 */ lwc1 $f16, ($t6)
/* 0D6DB0 8031BDB0 E6100020 */ swc1 $f16, 0x20($s0)
.L8031BDB4:
/* 0D6DB4 8031BDB4 860F003C */ lh $t7, 0x3c($s0)
.L8031BDB8:
/* 0D6DB8 8031BDB8 A60F0040 */ sh $t7, 0x40($s0)
.L8031BDBC:
/* 0D6DBC 8031BDBC 8E020000 */ lw $v0, ($s0)
/* 0D6DC0 8031BDC0 24010001 */ li $at, 1
/* 0D6DC4 8031BDC4 0002C080 */ sll $t8, $v0, 2
/* 0D6DC8 8031BDC8 0018CFC2 */ srl $t9, $t8, 0x1f
/* 0D6DCC 8031BDCC 5721000C */ bnel $t9, $at, .L8031BE00
/* 0D6DD0 8031BDD0 000270C0 */ sll $t6, $v0, 3
/* 0D6DD4 8031BDD4 8E0E0044 */ lw $t6, 0x44($s0)
/* 0D6DD8 8031BDD8 0002C0C0 */ sll $t8, $v0, 3
/* 0D6DDC 8031BDDC 15C00003 */ bnez $t6, .L8031BDEC
/* 0D6DE0 8031BDE0 00000000 */ nop
/* 0D6DE4 8031BDE4 0703002E */ bgezl $t8, .L8031BEA0
/* 0D6DE8 8031BDE8 8FBF001C */ lw $ra, 0x1c($sp)
.L8031BDEC:
/* 0D6DEC 8031BDEC 0C0C63B1 */ jal seq_channel_layer_note_decay
/* 0D6DF0 8031BDF0 02002025 */ move $a0, $s0
/* 0D6DF4 8031BDF4 1000002A */ b .L8031BEA0
/* 0D6DF8 8031BDF8 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D6DFC 8031BDFC 000270C0 */ sll $t6, $v0, 3
.L8031BE00:
/* 0D6E00 8031BE00 05C00003 */ bltz $t6, .L8031BE10
/* 0D6E04 8031BE04 00004025 */ move $t0, $zero
/* 0D6E08 8031BE08 10000017 */ b .L8031BE68
/* 0D6E0C 8031BE0C 24080001 */ li $t0, 1
.L8031BE10:
/* 0D6E10 8031BE10 8E040044 */ lw $a0, 0x44($s0)
/* 0D6E14 8031BE14 10800005 */ beqz $a0, .L8031BE2C
/* 0D6E18 8031BE18 00000000 */ nop
/* 0D6E1C 8031BE1C 920F0001 */ lbu $t7, 1($s0)
/* 0D6E20 8031BE20 93B8003F */ lbu $t8, 0x3f($sp)
/* 0D6E24 8031BE24 15E00003 */ bnez $t7, .L8031BE34
/* 0D6E28 8031BE28 00000000 */ nop
.L8031BE2C:
/* 0D6E2C 8031BE2C 1000000E */ b .L8031BE68
/* 0D6E30 8031BE30 24080001 */ li $t0, 1
.L8031BE34:
/* 0D6E34 8031BE34 57000006 */ bnezl $t8, .L8031BE50
/* 0D6E38 8031BE38 8E19004C */ lw $t9, 0x4c($s0)
/* 0D6E3C 8031BE3C 0C0C63B1 */ jal seq_channel_layer_note_decay
/* 0D6E40 8031BE40 02002025 */ move $a0, $s0
/* 0D6E44 8031BE44 10000008 */ b .L8031BE68
/* 0D6E48 8031BE48 24080001 */ li $t0, 1
/* 0D6E4C 8031BE4C 8E19004C */ lw $t9, 0x4c($s0)
.L8031BE50:
/* 0D6E50 8031BE50 02002825 */ move $a1, $s0
/* 0D6E54 8031BE54 17200004 */ bnez $t9, .L8031BE68
/* 0D6E58 8031BE58 00000000 */ nop
/* 0D6E5C 8031BE5C 0C0C6459 */ jal init_synthetic_wave
/* 0D6E60 8031BE60 A3A8003D */ sb $t0, 0x3d($sp)
/* 0D6E64 8031BE64 93A8003D */ lbu $t0, 0x3d($sp)
.L8031BE68:
/* 0D6E68 8031BE68 51000005 */ beql $t0, $zero, .L8031BE80
/* 0D6E6C 8031BE6C 8E040044 */ lw $a0, 0x44($s0)
/* 0D6E70 8031BE70 0C0C6638 */ jal alloc_note
/* 0D6E74 8031BE74 02002025 */ move $a0, $s0
/* 0D6E78 8031BE78 AE020044 */ sw $v0, 0x44($s0)
/* 0D6E7C 8031BE7C 8E040044 */ lw $a0, 0x44($s0)
.L8031BE80:
/* 0D6E80 8031BE80 50800007 */ beql $a0, $zero, .L8031BEA0
/* 0D6E84 8031BE84 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D6E88 8031BE88 8C8E002C */ lw $t6, 0x2c($a0)
/* 0D6E8C 8031BE8C 560E0004 */ bnel $s0, $t6, .L8031BEA0
/* 0D6E90 8031BE90 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D6E94 8031BE94 0C0C691E */ jal note_vibrato_init
/* 0D6E98 8031BE98 00000000 */ nop
.L8031BE9C:
/* 0D6E9C 8031BE9C 8FBF001C */ lw $ra, 0x1c($sp)
.L8031BEA0:
/* 0D6EA0 8031BEA0 8FB00018 */ lw $s0, 0x18($sp)
/* 0D6EA4 8031BEA4 27BD0060 */ addiu $sp, $sp, 0x60
/* 0D6EA8 8031BEA8 03E00008 */ jr $ra
/* 0D6EAC 8031BEAC 00000000 */ nop
|
96flashbacks/96flashbacks
| 38,488
|
asm/non_matchings/sequence_channel_process_script_jp.s
|
.late_rodata
.late_rodata_alignment 8
glabel jtbl_80337D08 # US: 80338EC0
.word L8031C430
.word L8031C3DC
.word L8031C44C
.word L8031C45C
.word L8031C3F8
.word L8031C6C8
.word L8031C724
.word L8031C75C
.word L8031C75C
.word L8031C7A8
.word L8031C7B8
.word L8031C75C
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C7D8
.word L8031C7FC
.word L8031C80C
.word L8031C508
.word L8031C6B8
.word L8031C1CC
.word L8031C698
.word L8031C600
.word L8031C5E4
.word L8031C5D4
.word L8031C5B8
.word L8031C5A0
.word L8031C568
.word L8031C530
.word L8031C4C0
.word L8031C46C
.word L8031C488
.word L8031C650
.word L8031C61C
.word L8031C684
.word L8031C820
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C3CC
.word L8031C3A4
.word L8031C1CC
.word L8031C1CC
.word L8031C34C
.word L8031C33C
.word L8031C2F4
.word L8031C2BC
.word L8031C34C
.word L8031C34C
.word L8031C34C
.word L8031C280
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
glabel jtbl_80337E04 # US: 80338FBC
.word L8031C89C
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C9E4
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031CA14
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031CA30
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031CA58
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C8F8
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C9DC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C8CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C8DC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C914
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C960
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C1CC
.word L8031C97C
.text
glabel sequence_channel_process_script
/* 0D7104 8031C104 27BDFF98 */ addiu $sp, $sp, -0x68
/* 0D7108 8031C108 AFBF0034 */ sw $ra, 0x34($sp)
/* 0D710C 8031C10C AFB50030 */ sw $s5, 0x30($sp)
/* 0D7110 8031C110 AFB4002C */ sw $s4, 0x2c($sp)
/* 0D7114 8031C114 AFB30028 */ sw $s3, 0x28($sp)
/* 0D7118 8031C118 AFB20024 */ sw $s2, 0x24($sp)
/* 0D711C 8031C11C AFB10020 */ sw $s1, 0x20($sp)
/* 0D7120 8031C120 AFB0001C */ sw $s0, 0x1c($sp)
/* 0D7124 8031C124 F7B40010 */ sdc1 $f20, 0x10($sp)
/* 0D7128 8031C128 8C820000 */ lw $v0, ($a0)
/* 0D712C 8031C12C 00809025 */ move $s2, $a0
/* 0D7130 8031C130 000277C2 */ srl $t6, $v0, 0x1f
/* 0D7134 8031C134 11C0025D */ beqz $t6, .L8031CAAC
/* 0D7138 8031C138 0002C080 */ sll $t8, $v0, 2
/* 0D713C 8031C13C 0701000D */ bgez $t8, .L8031C174
/* 0D7140 8031C140 00008025 */ move $s0, $zero
/* 0D7144 8031C144 00808825 */ move $s1, $a0
/* 0D7148 8031C148 24120010 */ li $s2, 16
.L8031C14C:
/* 0D714C 8031C14C 8E240044 */ lw $a0, 0x44($s1)
/* 0D7150 8031C150 50800004 */ beql $a0, $zero, .L8031C164
/* 0D7154 8031C154 26100004 */ addiu $s0, $s0, 4
/* 0D7158 8031C158 0C0C6C29 */ jal seq_channel_layer_process_script
/* 0D715C 8031C15C 00000000 */ nop
/* 0D7160 8031C160 26100004 */ addiu $s0, $s0, 4
.L8031C164:
/* 0D7164 8031C164 1612FFF9 */ bne $s0, $s2, .L8031C14C
/* 0D7168 8031C168 26310004 */ addiu $s1, $s1, 4
/* 0D716C 8031C16C 10000250 */ b .L8031CAB0
/* 0D7170 8031C170 8FBF0034 */ lw $ra, 0x34($sp)
.L8031C174:
/* 0D7174 8031C174 8E540040 */ lw $s4, 0x40($s2)
/* 0D7178 8031C178 8E990000 */ lw $t9, ($s4)
/* 0D717C 8031C17C 00195080 */ sll $t2, $t9, 2
/* 0D7180 8031C180 05430006 */ bgezl $t2, .L8031C19C
/* 0D7184 8031C184 96430016 */ lhu $v1, 0x16($s2)
/* 0D7188 8031C188 924B0002 */ lbu $t3, 2($s2)
/* 0D718C 8031C18C 316C0080 */ andi $t4, $t3, 0x80
/* 0D7190 8031C190 55800247 */ bnezl $t4, .L8031CAB0
/* 0D7194 8031C194 8FBF0034 */ lw $ra, 0x34($sp)
/* 0D7198 8031C198 96430016 */ lhu $v1, 0x16($s2)
.L8031C19C:
/* 0D719C 8031C19C 2650005C */ addiu $s0, $s2, 0x5c
/* 0D71A0 8031C1A0 3C013F80 */ li $at, 0x3F800000 # 1.000000
/* 0D71A4 8031C1A4 10600004 */ beqz $v1, .L8031C1B8
/* 0D71A8 8031C1A8 00601025 */ move $v0, $v1
/* 0D71AC 8031C1AC 246DFFFF */ addiu $t5, $v1, -1
/* 0D71B0 8031C1B0 A64D0016 */ sh $t5, 0x16($s2)
/* 0D71B4 8031C1B4 31A2FFFF */ andi $v0, $t5, 0xffff
.L8031C1B8:
/* 0D71B8 8031C1B8 14400231 */ bnez $v0, .L8031CA80
/* 0D71BC 8031C1BC 2415FFFF */ li $s5, -1
/* 0D71C0 8031C1C0 4481A800 */ mtc1 $at, $f21
/* 0D71C4 8031C1C4 4480A000 */ mtc1 $zero, $f20
/* 0D71C8 8031C1C8 83B30053 */ lb $s3, 0x53($sp)
.L8031C1CC:
glabel L8031C1CC
/* 0D71CC 8031C1CC 0C0C6C07 */ jal m64_read_u8
/* 0D71D0 8031C1D0 02002025 */ move $a0, $s0
/* 0D71D4 8031C1D4 240100FF */ li $at, 255
/* 0D71D8 8031C1D8 305100FF */ andi $s1, $v0, 0xff
/* 0D71DC 8031C1DC 1441000E */ bne $v0, $at, .L8031C218
/* 0D71E0 8031C1E0 00401825 */ move $v1, $v0
/* 0D71E4 8031C1E4 92040018 */ lbu $a0, 0x18($s0)
/* 0D71E8 8031C1E8 14800005 */ bnez $a0, .L8031C200
/* 0D71EC 8031C1EC 248EFFFF */ addiu $t6, $a0, -1
/* 0D71F0 8031C1F0 0C0C6AB4 */ jal sequence_channel_disable
/* 0D71F4 8031C1F4 02402025 */ move $a0, $s2
/* 0D71F8 8031C1F8 10000222 */ b .L8031CA84
/* 0D71FC 8031C1FC 02408825 */ move $s1, $s2
.L8031C200:
/* 0D7200 8031C200 31CF00FF */ andi $t7, $t6, 0xff
/* 0D7204 8031C204 000FC080 */ sll $t8, $t7, 2
/* 0D7208 8031C208 0218C821 */ addu $t9, $s0, $t8
/* 0D720C 8031C20C A20E0018 */ sb $t6, 0x18($s0)
/* 0D7210 8031C210 8F290004 */ lw $t1, 4($t9)
/* 0D7214 8031C214 AE090000 */ sw $t1, ($s0)
.L8031C218:
/* 0D7218 8031C218 240100FE */ li $at, 254
/* 0D721C 8031C21C 10610218 */ beq $v1, $at, .L8031CA80
/* 0D7220 8031C220 240100FD */ li $at, 253
/* 0D7224 8031C224 14610005 */ bne $v1, $at, .L8031C23C
/* 0D7228 8031C228 307900F0 */ andi $t9, $v1, 0xf0
/* 0D722C 8031C22C 0C0C6C18 */ jal m64_read_compressed_u16
/* 0D7230 8031C230 02002025 */ move $a0, $s0
/* 0D7234 8031C234 10000212 */ b .L8031CA80
/* 0D7238 8031C238 A6420016 */ sh $v0, 0x16($s2)
.L8031C23C:
/* 0D723C 8031C23C 240100F3 */ li $at, 243
/* 0D7240 8031C240 14610005 */ bne $v1, $at, .L8031C258
/* 0D7244 8031C244 246DFF3F */ addiu $t5, $v1, -0xc1
/* 0D7248 8031C248 924B0000 */ lbu $t3, ($s2)
/* 0D724C 8031C24C 356C0020 */ ori $t4, $t3, 0x20
/* 0D7250 8031C250 1000020B */ b .L8031CA80
/* 0D7254 8031C254 A24C0000 */ sb $t4, ($s2)
.L8031C258:
/* 0D7258 8031C258 286100C1 */ slti $at, $v1, 0xc1
/* 0D725C 8031C25C 14200185 */ bnez $at, .L8031C874
/* 0D7260 8031C260 2DA1003F */ sltiu $at, $t5, 0x3f
/* 0D7264 8031C264 1020FFD9 */ beqz $at, .L8031C1CC
/* 0D7268 8031C268 000D6880 */ sll $t5, $t5, 2
/* 0D726C 8031C26C 3C018033 */ lui $at, %hi(jtbl_80337D08)
/* 0D7270 8031C270 002D0821 */ addu $at, $at, $t5
/* 0D7274 8031C274 8C2D7D08 */ lw $t5, %lo(jtbl_80337D08)($at)
/* 0D7278 8031C278 01A00008 */ jr $t5
/* 0D727C 8031C27C 00000000 */ nop
glabel L8031C280
/* 0D7280 8031C280 0C0C6C0C */ jal m64_read_s16
/* 0D7284 8031C284 02002025 */ move $a0, $s0
/* 0D7288 8031C288 920E0018 */ lbu $t6, 0x18($s0)
/* 0D728C 8031C28C 8E180000 */ lw $t8, ($s0)
/* 0D7290 8031C290 304CFFFF */ andi $t4, $v0, 0xffff
/* 0D7294 8031C294 25CF0001 */ addiu $t7, $t6, 1
/* 0D7298 8031C298 31F900FF */ andi $t9, $t7, 0xff
/* 0D729C 8031C29C 00194880 */ sll $t1, $t9, 2
/* 0D72A0 8031C2A0 02095021 */ addu $t2, $s0, $t1
/* 0D72A4 8031C2A4 A20F0018 */ sb $t7, 0x18($s0)
/* 0D72A8 8031C2A8 AD580000 */ sw $t8, ($t2)
/* 0D72AC 8031C2AC 8E8B0014 */ lw $t3, 0x14($s4)
/* 0D72B0 8031C2B0 016C6821 */ addu $t5, $t3, $t4
/* 0D72B4 8031C2B4 1000FFC5 */ b .L8031C1CC
/* 0D72B8 8031C2B8 AE0D0000 */ sw $t5, ($s0)
glabel L8031C2BC
/* 0D72BC 8031C2BC 0C0C6C07 */ jal m64_read_u8
/* 0D72C0 8031C2C0 02002025 */ move $a0, $s0
/* 0D72C4 8031C2C4 920E0018 */ lbu $t6, 0x18($s0)
/* 0D72C8 8031C2C8 020E7821 */ addu $t7, $s0, $t6
/* 0D72CC 8031C2CC A1E20014 */ sb $v0, 0x14($t7)
/* 0D72D0 8031C2D0 92190018 */ lbu $t9, 0x18($s0)
/* 0D72D4 8031C2D4 8E180000 */ lw $t8, ($s0)
/* 0D72D8 8031C2D8 27290001 */ addiu $t1, $t9, 1
/* 0D72DC 8031C2DC 312A00FF */ andi $t2, $t1, 0xff
/* 0D72E0 8031C2E0 000A5880 */ sll $t3, $t2, 2
/* 0D72E4 8031C2E4 020B6021 */ addu $t4, $s0, $t3
/* 0D72E8 8031C2E8 A2090018 */ sb $t1, 0x18($s0)
/* 0D72EC 8031C2EC 1000FFB7 */ b .L8031C1CC
/* 0D72F0 8031C2F0 AD980000 */ sw $t8, ($t4)
glabel L8031C2F4
/* 0D72F4 8031C2F4 920D0018 */ lbu $t5, 0x18($s0)
/* 0D72F8 8031C2F8 020D1021 */ addu $v0, $s0, $t5
/* 0D72FC 8031C2FC 904E0013 */ lbu $t6, 0x13($v0)
/* 0D7300 8031C300 25CFFFFF */ addiu $t7, $t6, -1
/* 0D7304 8031C304 A04F0013 */ sb $t7, 0x13($v0)
/* 0D7308 8031C308 92040018 */ lbu $a0, 0x18($s0)
/* 0D730C 8031C30C 0204C821 */ addu $t9, $s0, $a0
/* 0D7310 8031C310 93290013 */ lbu $t1, 0x13($t9)
/* 0D7314 8031C314 00801825 */ move $v1, $a0
/* 0D7318 8031C318 00035080 */ sll $t2, $v1, 2
/* 0D731C 8031C31C 11200005 */ beqz $t1, .L8031C334
/* 0D7320 8031C320 248CFFFF */ addiu $t4, $a0, -1
/* 0D7324 8031C324 020A5821 */ addu $t3, $s0, $t2
/* 0D7328 8031C328 8D780000 */ lw $t8, ($t3)
/* 0D732C 8031C32C 1000FFA7 */ b .L8031C1CC
/* 0D7330 8031C330 AE180000 */ sw $t8, ($s0)
.L8031C334:
/* 0D7334 8031C334 1000FFA5 */ b .L8031C1CC
/* 0D7338 8031C338 A20C0018 */ sb $t4, 0x18($s0)
glabel L8031C33C
/* 0D733C 8031C33C 920D0018 */ lbu $t5, 0x18($s0)
/* 0D7340 8031C340 25AEFFFF */ addiu $t6, $t5, -1
/* 0D7344 8031C344 1000FFA1 */ b .L8031C1CC
/* 0D7348 8031C348 A20E0018 */ sb $t6, 0x18($s0)
glabel L8031C34C
/* 0D734C 8031C34C 0C0C6C0C */ jal m64_read_s16
/* 0D7350 8031C350 02002025 */ move $a0, $s0
/* 0D7354 8031C354 240100FA */ li $at, 250
/* 0D7358 8031C358 16210003 */ bne $s1, $at, .L8031C368
/* 0D735C 8031C35C 02201825 */ move $v1, $s1
/* 0D7360 8031C360 1660FF9A */ bnez $s3, .L8031C1CC
/* 0D7364 8031C364 00000000 */ nop
.L8031C368:
/* 0D7368 8031C368 240100F9 */ li $at, 249
/* 0D736C 8031C36C 54610004 */ bnel $v1, $at, .L8031C380
/* 0D7370 8031C370 240100F5 */ li $at, 245
/* 0D7374 8031C374 0661FF95 */ bgez $s3, .L8031C1CC
/* 0D7378 8031C378 00000000 */ nop
/* 0D737C 8031C37C 240100F5 */ li $at, 245
.L8031C380:
/* 0D7380 8031C380 54610004 */ bnel $v1, $at, .L8031C394
/* 0D7384 8031C384 8E8F0014 */ lw $t7, 0x14($s4)
/* 0D7388 8031C388 0660FF90 */ bltz $s3, .L8031C1CC
/* 0D738C 8031C38C 00000000 */ nop
/* 0D7390 8031C390 8E8F0014 */ lw $t7, 0x14($s4)
.L8031C394:
/* 0D7394 8031C394 3059FFFF */ andi $t9, $v0, 0xffff
/* 0D7398 8031C398 01F94821 */ addu $t1, $t7, $t9
/* 0D739C 8031C39C 1000FF8B */ b .L8031C1CC
/* 0D73A0 8031C3A0 AE090000 */ sw $t1, ($s0)
glabel L8031C3A4
/* 0D73A4 8031C3A4 26510080 */ addiu $s1, $s2, 0x80
/* 0D73A8 8031C3A8 0C0C64BF */ jal note_pool_clear
/* 0D73AC 8031C3AC 02202025 */ move $a0, $s1
/* 0D73B0 8031C3B0 0C0C6C07 */ jal m64_read_u8
/* 0D73B4 8031C3B4 02002025 */ move $a0, $s0
/* 0D73B8 8031C3B8 02202025 */ move $a0, $s1
/* 0D73BC 8031C3BC 0C0C650A */ jal note_pool_fill
/* 0D73C0 8031C3C0 00402825 */ move $a1, $v0
/* 0D73C4 8031C3C4 1000FF81 */ b .L8031C1CC
/* 0D73C8 8031C3C8 00000000 */ nop
glabel L8031C3CC
/* 0D73CC 8031C3CC 0C0C64BF */ jal note_pool_clear
/* 0D73D0 8031C3D0 26440080 */ addiu $a0, $s2, 0x80
/* 0D73D4 8031C3D4 1000FF7D */ b .L8031C1CC
/* 0D73D8 8031C3D8 00000000 */ nop
glabel L8031C3DC
/* 0D73DC 8031C3DC 0C0C6C0C */ jal m64_read_s16
/* 0D73E0 8031C3E0 02002025 */ move $a0, $s0
/* 0D73E4 8031C3E4 8E8A0014 */ lw $t2, 0x14($s4)
/* 0D73E8 8031C3E8 304BFFFF */ andi $t3, $v0, 0xffff
/* 0D73EC 8031C3EC 014BC021 */ addu $t8, $t2, $t3
/* 0D73F0 8031C3F0 1000FF76 */ b .L8031C1CC
/* 0D73F4 8031C3F4 AE580030 */ sw $t8, 0x30($s2)
glabel L8031C3F8
/* 0D73F8 8031C3F8 1275FF74 */ beq $s3, $s5, .L8031C1CC
/* 0D73FC 8031C3FC 00000000 */ nop
/* 0D7400 8031C400 8E4C0030 */ lw $t4, 0x30($s2)
/* 0D7404 8031C404 00136840 */ sll $t5, $s3, 1
/* 0D7408 8031C408 8E8A0014 */ lw $t2, 0x14($s4)
/* 0D740C 8031C40C 018D1021 */ addu $v0, $t4, $t5
/* 0D7410 8031C410 904F0000 */ lbu $t7, ($v0)
/* 0D7414 8031C414 904E0001 */ lbu $t6, 1($v0)
/* 0D7418 8031C418 000FCA00 */ sll $t9, $t7, 8
/* 0D741C 8031C41C 01D93821 */ addu $a3, $t6, $t9
/* 0D7420 8031C420 30E9FFFF */ andi $t1, $a3, 0xffff
/* 0D7424 8031C424 01495821 */ addu $t3, $t2, $t1
/* 0D7428 8031C428 1000FF68 */ b .L8031C1CC
/* 0D742C 8031C42C AE4B0030 */ sw $t3, 0x30($s2)
glabel L8031C430
/* 0D7430 8031C430 0C0C6C07 */ jal m64_read_u8
/* 0D7434 8031C434 02002025 */ move $a0, $s0
/* 0D7438 8031C438 02402025 */ move $a0, $s2
/* 0D743C 8031C43C 0C0C700C */ jal set_instrument
/* 0D7440 8031C440 304500FF */ andi $a1, $v0, 0xff
/* 0D7444 8031C444 1000FF61 */ b .L8031C1CC
/* 0D7448 8031C448 00000000 */ nop
glabel L8031C44C
/* 0D744C 8031C44C 92580000 */ lbu $t8, ($s2)
/* 0D7450 8031C450 330CFFFD */ andi $t4, $t8, 0xfffd
/* 0D7454 8031C454 1000FF5D */ b .L8031C1CC
/* 0D7458 8031C458 A24C0000 */ sb $t4, ($s2)
glabel L8031C45C
/* 0D745C 8031C45C 924F0000 */ lbu $t7, ($s2)
/* 0D7460 8031C460 35EE0002 */ ori $t6, $t7, 2
/* 0D7464 8031C464 1000FF59 */ b .L8031C1CC
/* 0D7468 8031C468 A24E0000 */ sb $t6, ($s2)
glabel L8031C46C
/* 0D746C 8031C46C 0C0C6C07 */ jal m64_read_u8
/* 0D7470 8031C470 02002025 */ move $a0, $s0
/* 0D7474 8031C474 02402025 */ move $a0, $s2
/* 0D7478 8031C478 0C0C7031 */ jal sequence_channel_set_volume
/* 0D747C 8031C47C 304500FF */ andi $a1, $v0, 0xff
/* 0D7480 8031C480 1000FF52 */ b .L8031C1CC
/* 0D7484 8031C484 00000000 */ nop
glabel L8031C488
/* 0D7488 8031C488 0C0C6C07 */ jal m64_read_u8
/* 0D748C 8031C48C 02002025 */ move $a0, $s0
/* 0D7490 8031C490 44822000 */ mtc1 $v0, $f4
/* 0D7494 8031C494 3C014F80 */ li $at, 0x4F800000 # 4294967296.000000
/* 0D7498 8031C498 04410004 */ bgez $v0, .L8031C4AC
/* 0D749C 8031C49C 468021A0 */ cvt.s.w $f6, $f4
/* 0D74A0 8031C4A0 44814000 */ mtc1 $at, $f8
/* 0D74A4 8031C4A4 00000000 */ nop
/* 0D74A8 8031C4A8 46083180 */ add.s $f6, $f6, $f8
.L8031C4AC:
/* 0D74AC 8031C4AC 460032A1 */ cvt.d.s $f10, $f6
/* 0D74B0 8031C4B0 46345402 */ mul.d $f16, $f10, $f20
/* 0D74B4 8031C4B4 462084A0 */ cvt.s.d $f18, $f16
/* 0D74B8 8031C4B8 1000FF44 */ b .L8031C1CC
/* 0D74BC 8031C4BC E652001C */ swc1 $f18, 0x1c($s2)
glabel L8031C4C0
/* 0D74C0 8031C4C0 0C0C6C0C */ jal m64_read_s16
/* 0D74C4 8031C4C4 02002025 */ move $a0, $s0
/* 0D74C8 8031C4C8 3059FFFF */ andi $t9, $v0, 0xffff
/* 0D74CC 8031C4CC 44992000 */ mtc1 $t9, $f4
/* 0D74D0 8031C4D0 44808000 */ mtc1 $zero, $f16
/* 0D74D4 8031C4D4 07210005 */ bgez $t9, .L8031C4EC
/* 0D74D8 8031C4D8 46802220 */ cvt.s.w $f8, $f4
/* 0D74DC 8031C4DC 3C014F80 */ li $at, 0x4F800000 # 4294967296.000000
/* 0D74E0 8031C4E0 44813000 */ mtc1 $at, $f6
/* 0D74E4 8031C4E4 00000000 */ nop
/* 0D74E8 8031C4E8 46064200 */ add.s $f8, $f8, $f6
.L8031C4EC:
/* 0D74EC 8031C4EC 3C0140E0 */ li $at, 0x40E00000 # 7.000000
/* 0D74F0 8031C4F0 44818800 */ mtc1 $at, $f17
/* 0D74F4 8031C4F4 460042A1 */ cvt.d.s $f10, $f8
/* 0D74F8 8031C4F8 46305483 */ div.d $f18, $f10, $f16
/* 0D74FC 8031C4FC 46209120 */ cvt.s.d $f4, $f18
/* 0D7500 8031C500 1000FF32 */ b .L8031C1CC
/* 0D7504 8031C504 E644002C */ swc1 $f4, 0x2c($s2)
glabel L8031C508
/* 0D7508 8031C508 0C0C6C07 */ jal m64_read_u8
/* 0D750C 8031C50C 02002025 */ move $a0, $s0
/* 0D7510 8031C510 2449007F */ addiu $t1, $v0, 0x7f
/* 0D7514 8031C514 312A00FF */ andi $t2, $t1, 0xff
/* 0D7518 8031C518 000A5880 */ sll $t3, $t2, 2
/* 0D751C 8031C51C 3C018033 */ lui $at, %hi(gPitchBendFrequencyScale)
/* 0D7520 8031C520 002B0821 */ addu $at, $at, $t3
/* 0D7524 8031C524 C4262488 */ lwc1 $f6, %lo(gPitchBendFrequencyScale)($at)
/* 0D7528 8031C528 1000FF28 */ b .L8031C1CC
/* 0D752C 8031C52C E646002C */ swc1 $f6, 0x2c($s2)
glabel L8031C530
/* 0D7530 8031C530 0C0C6C07 */ jal m64_read_u8
/* 0D7534 8031C534 02002025 */ move $a0, $s0
/* 0D7538 8031C538 44824000 */ mtc1 $v0, $f8
/* 0D753C 8031C53C 3C014F80 */ li $at, 0x4F800000 # 4294967296.000000
/* 0D7540 8031C540 04410004 */ bgez $v0, .L8031C554
/* 0D7544 8031C544 468042A0 */ cvt.s.w $f10, $f8
/* 0D7548 8031C548 44818000 */ mtc1 $at, $f16
/* 0D754C 8031C54C 00000000 */ nop
/* 0D7550 8031C550 46105280 */ add.s $f10, $f10, $f16
.L8031C554:
/* 0D7554 8031C554 460054A1 */ cvt.d.s $f18, $f10
/* 0D7558 8031C558 46349102 */ mul.d $f4, $f18, $f20
/* 0D755C 8031C55C 462021A0 */ cvt.s.d $f6, $f4
/* 0D7560 8031C560 1000FF1A */ b .L8031C1CC
/* 0D7564 8031C564 E6460024 */ swc1 $f6, 0x24($s2)
glabel L8031C568
/* 0D7568 8031C568 0C0C6C07 */ jal m64_read_u8
/* 0D756C 8031C56C 02002025 */ move $a0, $s0
/* 0D7570 8031C570 44824000 */ mtc1 $v0, $f8
/* 0D7574 8031C574 3C014F80 */ li $at, 0x4F800000 # 4294967296.000000
/* 0D7578 8031C578 04410004 */ bgez $v0, .L8031C58C
/* 0D757C 8031C57C 46804420 */ cvt.s.w $f16, $f8
/* 0D7580 8031C580 44815000 */ mtc1 $at, $f10
/* 0D7584 8031C584 00000000 */ nop
/* 0D7588 8031C588 460A8400 */ add.s $f16, $f16, $f10
.L8031C58C:
/* 0D758C 8031C58C 460084A1 */ cvt.d.s $f18, $f16
/* 0D7590 8031C590 46349102 */ mul.d $f4, $f18, $f20
/* 0D7594 8031C594 462021A0 */ cvt.s.d $f6, $f4
/* 0D7598 8031C598 1000FF0C */ b .L8031C1CC
/* 0D759C 8031C59C E6460028 */ swc1 $f6, 0x28($s2)
glabel L8031C5A0
/* 0D75A0 8031C5A0 8E020000 */ lw $v0, ($s0)
/* 0D75A4 8031C5A4 80430000 */ lb $v1, ($v0)
/* 0D75A8 8031C5A8 24580001 */ addiu $t8, $v0, 1
/* 0D75AC 8031C5AC AE180000 */ sw $t8, ($s0)
/* 0D75B0 8031C5B0 1000FF06 */ b .L8031C1CC
/* 0D75B4 8031C5B4 A643001A */ sh $v1, 0x1a($s2)
glabel L8031C5B8
/* 0D75B8 8031C5B8 0C0C6C0C */ jal m64_read_s16
/* 0D75BC 8031C5BC 02002025 */ move $a0, $s0
/* 0D75C0 8031C5C0 8E8C0014 */ lw $t4, 0x14($s4)
/* 0D75C4 8031C5C4 304DFFFF */ andi $t5, $v0, 0xffff
/* 0D75C8 8031C5C8 018D7821 */ addu $t7, $t4, $t5
/* 0D75CC 8031C5CC 1000FEFF */ b .L8031C1CC
/* 0D75D0 8031C5D0 AE4F007C */ sw $t7, 0x7c($s2)
glabel L8031C5D4
/* 0D75D4 8031C5D4 0C0C6C07 */ jal m64_read_u8
/* 0D75D8 8031C5D8 02002025 */ move $a0, $s0
/* 0D75DC 8031C5DC 1000FEFB */ b .L8031C1CC
/* 0D75E0 8031C5E0 A2420078 */ sb $v0, 0x78($s2)
glabel L8031C5E4
/* 0D75E4 8031C5E4 0C0C6C07 */ jal m64_read_u8
/* 0D75E8 8031C5E8 02002025 */ move $a0, $s0
/* 0D75EC 8031C5EC 000270C0 */ sll $t6, $v0, 3
/* 0D75F0 8031C5F0 A64E000E */ sh $t6, 0xe($s2)
/* 0D75F4 8031C5F4 A640000A */ sh $zero, 0xa($s2)
/* 0D75F8 8031C5F8 1000FEF4 */ b .L8031C1CC
/* 0D75FC 8031C5FC A6400012 */ sh $zero, 0x12($s2)
glabel L8031C600
/* 0D7600 8031C600 0C0C6C07 */ jal m64_read_u8
/* 0D7604 8031C604 02002025 */ move $a0, $s0
/* 0D7608 8031C608 00021940 */ sll $v1, $v0, 5
/* 0D760C 8031C60C A643000C */ sh $v1, 0xc($s2)
/* 0D7610 8031C610 A6430008 */ sh $v1, 8($s2)
/* 0D7614 8031C614 1000FEED */ b .L8031C1CC
/* 0D7618 8031C618 A6400010 */ sh $zero, 0x10($s2)
glabel L8031C61C
/* 0D761C 8031C61C 0C0C6C07 */ jal m64_read_u8
/* 0D7620 8031C620 02002025 */ move $a0, $s0
/* 0D7624 8031C624 0002C8C0 */ sll $t9, $v0, 3
/* 0D7628 8031C628 A659000A */ sh $t9, 0xa($s2)
/* 0D762C 8031C62C 0C0C6C07 */ jal m64_read_u8
/* 0D7630 8031C630 02002025 */ move $a0, $s0
/* 0D7634 8031C634 000248C0 */ sll $t1, $v0, 3
/* 0D7638 8031C638 A649000E */ sh $t1, 0xe($s2)
/* 0D763C 8031C63C 0C0C6C07 */ jal m64_read_u8
/* 0D7640 8031C640 02002025 */ move $a0, $s0
/* 0D7644 8031C644 00025100 */ sll $t2, $v0, 4
/* 0D7648 8031C648 1000FEE0 */ b .L8031C1CC
/* 0D764C 8031C64C A64A0012 */ sh $t2, 0x12($s2)
glabel L8031C650
/* 0D7650 8031C650 0C0C6C07 */ jal m64_read_u8
/* 0D7654 8031C654 02002025 */ move $a0, $s0
/* 0D7658 8031C658 00025940 */ sll $t3, $v0, 5
/* 0D765C 8031C65C A64B0008 */ sh $t3, 8($s2)
/* 0D7660 8031C660 0C0C6C07 */ jal m64_read_u8
/* 0D7664 8031C664 02002025 */ move $a0, $s0
/* 0D7668 8031C668 0002C140 */ sll $t8, $v0, 5
/* 0D766C 8031C66C A658000C */ sh $t8, 0xc($s2)
/* 0D7670 8031C670 0C0C6C07 */ jal m64_read_u8
/* 0D7674 8031C674 02002025 */ move $a0, $s0
/* 0D7678 8031C678 00026100 */ sll $t4, $v0, 4
/* 0D767C 8031C67C 1000FED3 */ b .L8031C1CC
/* 0D7680 8031C680 A64C0010 */ sh $t4, 0x10($s2)
glabel L8031C684
/* 0D7684 8031C684 0C0C6C07 */ jal m64_read_u8
/* 0D7688 8031C688 02002025 */ move $a0, $s0
/* 0D768C 8031C68C 00026900 */ sll $t5, $v0, 4
/* 0D7690 8031C690 1000FECE */ b .L8031C1CC
/* 0D7694 8031C694 A64D0014 */ sh $t5, 0x14($s2)
glabel L8031C698
/* 0D7698 8031C698 0C0C6C07 */ jal m64_read_u8
/* 0D769C 8031C69C 02002025 */ move $a0, $s0
/* 0D76A0 8031C6A0 14400003 */ bnez $v0, .L8031C6B0
/* 0D76A4 8031C6A4 305100FF */ andi $s1, $v0, 0xff
/* 0D76A8 8031C6A8 3C118022 */ lui $s1, %hi(gAudioUpdatesPerFrame) # $s1, 0x8022
/* 0D76AC 8031C6AC 92316D7E */ lbu $s1, %lo(gAudioUpdatesPerFrame)($s1)
.L8031C6B0:
/* 0D76B0 8031C6B0 1000FEC6 */ b .L8031C1CC
/* 0D76B4 8031C6B4 A2510006 */ sb $s1, 6($s2)
glabel L8031C6B8
/* 0D76B8 8031C6B8 0C0C6C07 */ jal m64_read_u8
/* 0D76BC 8031C6BC 02002025 */ move $a0, $s0
/* 0D76C0 8031C6C0 1000FEC2 */ b .L8031C1CC
/* 0D76C4 8031C6C4 A2420003 */ sb $v0, 3($s2)
glabel L8031C6C8
/* 0D76C8 8031C6C8 0C0C6C07 */ jal m64_read_u8
/* 0D76CC 8031C6CC 02002025 */ move $a0, $s0
/* 0D76D0 8031C6D0 928F0005 */ lbu $t7, 5($s4)
/* 0D76D4 8031C6D4 3C038022 */ lui $v1, %hi(gAlBankSets) # $v1, 0x8022
/* 0D76D8 8031C6D8 8C636D58 */ lw $v1, %lo(gAlBankSets)($v1)
/* 0D76DC 8031C6DC 000F7040 */ sll $t6, $t7, 1
/* 0D76E0 8031C6E0 3C048022 */ lui $a0, %hi(gBankLoadedPool) # $a0, 0x8022
/* 0D76E4 8031C6E4 006EC821 */ addu $t9, $v1, $t6
/* 0D76E8 8031C6E8 97270000 */ lhu $a3, ($t9)
/* 0D76EC 8031C6EC 248414F8 */ addiu $a0, %lo(gBankLoadedPool) # addiu $a0, $a0, 0x14f8
/* 0D76F0 8031C6F0 24050002 */ li $a1, 2
/* 0D76F4 8031C6F4 00E34821 */ addu $t1, $a3, $v1
/* 0D76F8 8031C6F8 91280000 */ lbu $t0, ($t1)
/* 0D76FC 8031C6FC 00E85021 */ addu $t2, $a3, $t0
/* 0D7700 8031C700 01425823 */ subu $t3, $t2, $v0
/* 0D7704 8031C704 0163C021 */ addu $t8, $t3, $v1
/* 0D7708 8031C708 93110000 */ lbu $s1, ($t8)
/* 0D770C 8031C70C 0C0C5A03 */ jal get_bank_or_seq
/* 0D7710 8031C710 02203025 */ move $a2, $s1
/* 0D7714 8031C714 1040FEAD */ beqz $v0, .L8031C1CC
/* 0D7718 8031C718 00000000 */ nop
/* 0D771C 8031C71C 1000FEAB */ b .L8031C1CC
/* 0D7720 8031C720 A2510005 */ sb $s1, 5($s2)
glabel L8031C724
/* 0D7724 8031C724 326C00FF */ andi $t4, $s3, 0xff
/* 0D7728 8031C728 AFAC0038 */ sw $t4, 0x38($sp)
/* 0D772C 8031C72C 0C0C6C07 */ jal m64_read_u8
/* 0D7730 8031C730 02002025 */ move $a0, $s0
/* 0D7734 8031C734 305100FF */ andi $s1, $v0, 0xff
/* 0D7738 8031C738 0C0C6C0C */ jal m64_read_s16
/* 0D773C 8031C73C 02002025 */ move $a0, $s0
/* 0D7740 8031C740 8E8D0014 */ lw $t5, 0x14($s4)
/* 0D7744 8031C744 8FAE0038 */ lw $t6, 0x38($sp)
/* 0D7748 8031C748 304FFFFF */ andi $t7, $v0, 0xffff
/* 0D774C 8031C74C 01AF1821 */ addu $v1, $t5, $t7
/* 0D7750 8031C750 01D1C821 */ addu $t9, $t6, $s1
/* 0D7754 8031C754 1000FE9D */ b .L8031C1CC
/* 0D7758 8031C758 A0790000 */ sb $t9, ($v1)
glabel L8031C75C
/* 0D775C 8031C75C 0C0C6C07 */ jal m64_read_u8
/* 0D7760 8031C760 02002025 */ move $a0, $s0
/* 0D7764 8031C764 240100C8 */ li $at, 200
/* 0D7768 8031C768 16210005 */ bne $s1, $at, .L8031C780
/* 0D776C 8031C76C 02201825 */ move $v1, $s1
/* 0D7770 8031C770 02629823 */ subu $s3, $s3, $v0
/* 0D7774 8031C774 00135E00 */ sll $t3, $s3, 0x18
/* 0D7778 8031C778 1000FE94 */ b .L8031C1CC
/* 0D777C 8031C77C 000B9E03 */ sra $s3, $t3, 0x18
.L8031C780:
/* 0D7780 8031C780 240100CC */ li $at, 204
/* 0D7784 8031C784 14610005 */ bne $v1, $at, .L8031C79C
/* 0D7788 8031C788 02629824 */ and $s3, $s3, $v0
/* 0D778C 8031C78C 00029E00 */ sll $s3, $v0, 0x18
/* 0D7790 8031C790 00136603 */ sra $t4, $s3, 0x18
/* 0D7794 8031C794 1000FE8D */ b .L8031C1CC
/* 0D7798 8031C798 01809825 */ move $s3, $t4
.L8031C79C:
/* 0D779C 8031C79C 00137600 */ sll $t6, $s3, 0x18
/* 0D77A0 8031C7A0 1000FE8A */ b .L8031C1CC
/* 0D77A4 8031C7A4 000E9E03 */ sra $s3, $t6, 0x18
glabel L8031C7A8
/* 0D77A8 8031C7A8 0C0C6C07 */ jal m64_read_u8
/* 0D77AC 8031C7AC 02002025 */ move $a0, $s0
/* 0D77B0 8031C7B0 1000FE86 */ b .L8031C1CC
/* 0D77B4 8031C7B4 A2420002 */ sb $v0, 2($s2)
glabel L8031C7B8
/* 0D77B8 8031C7B8 0C0C6C0C */ jal m64_read_s16
/* 0D77BC 8031C7BC 02002025 */ move $a0, $s0
/* 0D77C0 8031C7C0 8E890014 */ lw $t1, 0x14($s4)
/* 0D77C4 8031C7C4 304AFFFF */ andi $t2, $v0, 0xffff
/* 0D77C8 8031C7C8 01535821 */ addu $t3, $t2, $s3
/* 0D77CC 8031C7CC 012BC021 */ addu $t8, $t1, $t3
/* 0D77D0 8031C7D0 1000FE7E */ b .L8031C1CC
/* 0D77D4 8031C7D4 83130000 */ lb $s3, ($t8)
glabel L8031C7D8
/* 0D77D8 8031C7D8 0C0C6C07 */ jal m64_read_u8
/* 0D77DC 8031C7DC 02002025 */ move $a0, $s0
/* 0D77E0 8031C7E0 924E0000 */ lbu $t6, ($s2)
/* 0D77E4 8031C7E4 00026880 */ sll $t5, $v0, 2
/* 0D77E8 8031C7E8 31AF0004 */ andi $t7, $t5, 4
/* 0D77EC 8031C7EC 31D9FFFB */ andi $t9, $t6, 0xfffb
/* 0D77F0 8031C7F0 01F95025 */ or $t2, $t7, $t9
/* 0D77F4 8031C7F4 1000FE75 */ b .L8031C1CC
/* 0D77F8 8031C7F8 A24A0000 */ sb $t2, ($s2)
glabel L8031C7FC
/* 0D77FC 8031C7FC 0C0C6C07 */ jal m64_read_u8
/* 0D7800 8031C800 02002025 */ move $a0, $s0
/* 0D7804 8031C804 1000FE71 */ b .L8031C1CC
/* 0D7808 8031C808 A2420001 */ sb $v0, 1($s2)
glabel L8031C80C
/* 0D780C 8031C80C 0C0C6C07 */ jal m64_read_u8
/* 0D7810 8031C810 02002025 */ move $a0, $s0
/* 0D7814 8031C814 00024A00 */ sll $t1, $v0, 8
/* 0D7818 8031C818 1000FE6C */ b .L8031C1CC
/* 0D781C 8031C81C A649007A */ sh $t1, 0x7a($s2)
glabel L8031C820
/* 0D7820 8031C820 1275FE6A */ beq $s3, $s5, .L8031C1CC
/* 0D7824 8031C824 0013C040 */ sll $t8, $s3, 1
/* 0D7828 8031C828 920C0018 */ lbu $t4, 0x18($s0)
/* 0D782C 8031C82C 8E4B0030 */ lw $t3, 0x30($s2)
/* 0D7830 8031C830 8E0E0000 */ lw $t6, ($s0)
/* 0D7834 8031C834 258D0001 */ addiu $t5, $t4, 1
/* 0D7838 8031C838 31AF00FF */ andi $t7, $t5, 0xff
/* 0D783C 8031C83C 000FC880 */ sll $t9, $t7, 2
/* 0D7840 8031C840 02195021 */ addu $t2, $s0, $t9
/* 0D7844 8031C844 A20D0018 */ sb $t5, 0x18($s0)
/* 0D7848 8031C848 01781021 */ addu $v0, $t3, $t8
/* 0D784C 8031C84C AD4E0000 */ sw $t6, ($t2)
/* 0D7850 8031C850 904B0000 */ lbu $t3, ($v0)
/* 0D7854 8031C854 90490001 */ lbu $t1, 1($v0)
/* 0D7858 8031C858 8E8D0014 */ lw $t5, 0x14($s4)
/* 0D785C 8031C85C 000BC200 */ sll $t8, $t3, 8
/* 0D7860 8031C860 01383821 */ addu $a3, $t1, $t8
/* 0D7864 8031C864 30ECFFFF */ andi $t4, $a3, 0xffff
/* 0D7868 8031C868 01AC7821 */ addu $t7, $t5, $t4
/* 0D786C 8031C86C 1000FE57 */ b .L8031C1CC
/* 0D7870 8031C870 AE0F0000 */ sw $t7, ($s0)
.L8031C874:
/* 0D7874 8031C874 3064000F */ andi $a0, $v1, 0xf
/* 0D7878 8031C878 2F2100B1 */ sltiu $at, $t9, 0xb1
/* 0D787C 8031C87C 1020FE53 */ beqz $at, .L8031C1CC
/* 0D7880 8031C880 308800FF */ andi $t0, $a0, 0xff
/* 0D7884 8031C884 0019C880 */ sll $t9, $t9, 2
/* 0D7888 8031C888 3C018033 */ lui $at, %hi(jtbl_80337E04)
/* 0D788C 8031C88C 00390821 */ addu $at, $at, $t9
/* 0D7890 8031C890 8C397E04 */ lw $t9, %lo(jtbl_80337E04)($at)
/* 0D7894 8031C894 03200008 */ jr $t9
/* 0D7898 8031C898 00000000 */ nop
glabel L8031C89C
/* 0D789C 8031C89C 308E00FF */ andi $t6, $a0, 0xff
/* 0D78A0 8031C8A0 000E5080 */ sll $t2, $t6, 2
/* 0D78A4 8031C8A4 024A5821 */ addu $t3, $s2, $t2
/* 0D78A8 8031C8A8 8D630044 */ lw $v1, 0x44($t3)
/* 0D78AC 8031C8AC 1060FE47 */ beqz $v1, .L8031C1CC
/* 0D78B0 8031C8B0 00000000 */ nop
/* 0D78B4 8031C8B4 8C730000 */ lw $s3, ($v1)
/* 0D78B8 8031C8B8 00134840 */ sll $t1, $s3, 1
/* 0D78BC 8031C8BC 0009C7C2 */ srl $t8, $t1, 0x1f
/* 0D78C0 8031C8C0 00186600 */ sll $t4, $t8, 0x18
/* 0D78C4 8031C8C4 1000FE41 */ b .L8031C1CC
/* 0D78C8 8031C8C8 000C9E03 */ sra $s3, $t4, 0x18
glabel L8031C8CC
/* 0D78CC 8031C8CC 308F00FF */ andi $t7, $a0, 0xff
/* 0D78D0 8031C8D0 024FC821 */ addu $t9, $s2, $t7
/* 0D78D4 8031C8D4 1000FE3D */ b .L8031C1CC
/* 0D78D8 8031C8D8 A3330054 */ sb $s3, 0x54($t9)
glabel L8031C8DC
/* 0D78DC 8031C8DC 308300FF */ andi $v1, $a0, 0xff
/* 0D78E0 8031C8E0 02432821 */ addu $a1, $s2, $v1
/* 0D78E4 8031C8E4 28610004 */ slti $at, $v1, 4
/* 0D78E8 8031C8E8 1020FE38 */ beqz $at, .L8031C1CC
/* 0D78EC 8031C8EC 80B30054 */ lb $s3, 0x54($a1)
/* 0D78F0 8031C8F0 1000FE36 */ b .L8031C1CC
/* 0D78F4 8031C8F4 A0B50054 */ sb $s5, 0x54($a1)
glabel L8031C8F8
/* 0D78F8 8031C8F8 308E00FF */ andi $t6, $a0, 0xff
/* 0D78FC 8031C8FC 024E5021 */ addu $t2, $s2, $t6
/* 0D7900 8031C900 814B0054 */ lb $t3, 0x54($t2)
/* 0D7904 8031C904 026B9823 */ subu $s3, $s3, $t3
/* 0D7908 8031C908 00134E00 */ sll $t1, $s3, 0x18
/* 0D790C 8031C90C 1000FE2F */ b .L8031C1CC
/* 0D7910 8031C910 00099E03 */ sra $s3, $t1, 0x18
glabel L8031C914
/* 0D7914 8031C914 0C0C6C0C */ jal m64_read_s16
/* 0D7918 8031C918 02002025 */ move $a0, $s0
/* 0D791C 8031C91C 02201825 */ move $v1, $s1
/* 0D7920 8031C920 3065000F */ andi $a1, $v1, 0xf
/* 0D7924 8031C924 00A01825 */ move $v1, $a1
/* 0D7928 8031C928 AFA50038 */ sw $a1, 0x38($sp)
/* 0D792C 8031C92C 02402025 */ move $a0, $s2
/* 0D7930 8031C930 0C0C6A48 */ jal seq_channel_set_layer
/* 0D7934 8031C934 A7A2005A */ sh $v0, 0x5a($sp)
/* 0D7938 8031C938 8FA30038 */ lw $v1, 0x38($sp)
/* 0D793C 8031C93C 1440FE23 */ bnez $v0, .L8031C1CC
/* 0D7940 8031C940 97A7005A */ lhu $a3, 0x5a($sp)
/* 0D7944 8031C944 8E8D0014 */ lw $t5, 0x14($s4)
/* 0D7948 8031C948 0003C880 */ sll $t9, $v1, 2
/* 0D794C 8031C94C 02597021 */ addu $t6, $s2, $t9
/* 0D7950 8031C950 8DCA0044 */ lw $t2, 0x44($t6)
/* 0D7954 8031C954 01A77821 */ addu $t7, $t5, $a3
/* 0D7958 8031C958 1000FE1C */ b .L8031C1CC
/* 0D795C 8031C95C AD4F0054 */ sw $t7, 0x54($t2)
glabel L8031C960
/* 0D7960 8031C960 02202825 */ move $a1, $s1
/* 0D7964 8031C964 30AB000F */ andi $t3, $a1, 0xf
/* 0D7968 8031C968 01602825 */ move $a1, $t3
/* 0D796C 8031C96C 0C0C6A93 */ jal seq_channel_layer_free
/* 0D7970 8031C970 02402025 */ move $a0, $s2
/* 0D7974 8031C974 1000FE15 */ b .L8031C1CC
/* 0D7978 8031C978 00000000 */ nop
glabel L8031C97C
/* 0D797C 8031C97C 1275FE13 */ beq $s3, $s5, .L8031C1CC
/* 0D7980 8031C980 02402025 */ move $a0, $s2
/* 0D7984 8031C984 02201825 */ move $v1, $s1
/* 0D7988 8031C988 3065000F */ andi $a1, $v1, 0xf
/* 0D798C 8031C98C 00A01825 */ move $v1, $a1
/* 0D7990 8031C990 0C0C6A48 */ jal seq_channel_set_layer
/* 0D7994 8031C994 AFA50038 */ sw $a1, 0x38($sp)
/* 0D7998 8031C998 1055FE0C */ beq $v0, $s5, .L8031C1CC
/* 0D799C 8031C99C 8FA30038 */ lw $v1, 0x38($sp)
/* 0D79A0 8031C9A0 8E580030 */ lw $t8, 0x30($s2)
/* 0D79A4 8031C9A4 00136040 */ sll $t4, $s3, 1
/* 0D79A8 8031C9A8 8E8A0014 */ lw $t2, 0x14($s4)
/* 0D79AC 8031C9AC 030C1021 */ addu $v0, $t8, $t4
/* 0D79B0 8031C9B0 90590000 */ lbu $t9, ($v0)
/* 0D79B4 8031C9B4 904D0001 */ lbu $t5, 1($v0)
/* 0D79B8 8031C9B8 00034880 */ sll $t1, $v1, 2
/* 0D79BC 8031C9BC 00197200 */ sll $t6, $t9, 8
/* 0D79C0 8031C9C0 0249C021 */ addu $t8, $s2, $t1
/* 0D79C4 8031C9C4 01AE3821 */ addu $a3, $t5, $t6
/* 0D79C8 8031C9C8 8F0C0044 */ lw $t4, 0x44($t8)
/* 0D79CC 8031C9CC 30EFFFFF */ andi $t7, $a3, 0xffff
/* 0D79D0 8031C9D0 014F5821 */ addu $t3, $t2, $t7
/* 0D79D4 8031C9D4 1000FDFD */ b .L8031C1CC
/* 0D79D8 8031C9D8 AD8B0054 */ sw $t3, 0x54($t4)
glabel L8031C9DC
/* 0D79DC 8031C9DC 1000FDFB */ b .L8031C1CC
/* 0D79E0 8031C9E0 A2440004 */ sb $a0, 4($s2)
glabel L8031C9E4
/* 0D79E4 8031C9E4 0C0C6C0C */ jal m64_read_s16
/* 0D79E8 8031C9E8 02002025 */ move $a0, $s0
/* 0D79EC 8031C9EC 8E8D0014 */ lw $t5, 0x14($s4)
/* 0D79F0 8031C9F0 02202825 */ move $a1, $s1
/* 0D79F4 8031C9F4 30B9000F */ andi $t9, $a1, 0xf
/* 0D79F8 8031C9F8 304EFFFF */ andi $t6, $v0, 0xffff
/* 0D79FC 8031C9FC 03202825 */ move $a1, $t9
/* 0D7A00 8031CA00 02802025 */ move $a0, $s4
/* 0D7A04 8031CA04 0C0C6B60 */ jal sequence_channel_enable
/* 0D7A08 8031CA08 01AE3021 */ addu $a2, $t5, $t6
/* 0D7A0C 8031CA0C 1000FDEF */ b .L8031C1CC
/* 0D7A10 8031CA10 00000000 */ nop
glabel L8031CA14
/* 0D7A14 8031CA14 322A000F */ andi $t2, $s1, 0xf
/* 0D7A18 8031CA18 000A4880 */ sll $t1, $t2, 2
/* 0D7A1C 8031CA1C 0289C021 */ addu $t8, $s4, $t1
/* 0D7A20 8031CA20 0C0C6AB4 */ jal sequence_channel_disable
/* 0D7A24 8031CA24 8F04002C */ lw $a0, 0x2c($t8)
/* 0D7A28 8031CA28 1000FDE8 */ b .L8031C1CC
/* 0D7A2C 8031CA2C 00000000 */ nop
glabel L8031CA30
/* 0D7A30 8031CA30 02002025 */ move $a0, $s0
/* 0D7A34 8031CA34 0C0C6C07 */ jal m64_read_u8
/* 0D7A38 8031CA38 A3A8005D */ sb $t0, 0x5d($sp)
/* 0D7A3C 8031CA3C 93A8005D */ lbu $t0, 0x5d($sp)
/* 0D7A40 8031CA40 00085880 */ sll $t3, $t0, 2
/* 0D7A44 8031CA44 028B6021 */ addu $t4, $s4, $t3
/* 0D7A48 8031CA48 8D99002C */ lw $t9, 0x2c($t4)
/* 0D7A4C 8031CA4C 03226821 */ addu $t5, $t9, $v0
/* 0D7A50 8031CA50 1000FDDE */ b .L8031C1CC
/* 0D7A54 8031CA54 A1B30054 */ sb $s3, 0x54($t5)
glabel L8031CA58
/* 0D7A58 8031CA58 02002025 */ move $a0, $s0
/* 0D7A5C 8031CA5C 0C0C6C07 */ jal m64_read_u8
/* 0D7A60 8031CA60 A3A8005D */ sb $t0, 0x5d($sp)
/* 0D7A64 8031CA64 93A8005D */ lbu $t0, 0x5d($sp)
/* 0D7A68 8031CA68 00087080 */ sll $t6, $t0, 2
/* 0D7A6C 8031CA6C 028E7821 */ addu $t7, $s4, $t6
/* 0D7A70 8031CA70 8DEA002C */ lw $t2, 0x2c($t7)
/* 0D7A74 8031CA74 01424821 */ addu $t1, $t2, $v0
/* 0D7A78 8031CA78 1000FDD4 */ b .L8031C1CC
/* 0D7A7C 8031CA7C 81330054 */ lb $s3, 0x54($t1)
.L8031CA80:
/* 0D7A80 8031CA80 02408825 */ move $s1, $s2
.L8031CA84:
/* 0D7A84 8031CA84 24120010 */ li $s2, 16
/* 0D7A88 8031CA88 00008025 */ move $s0, $zero
.L8031CA8C:
/* 0D7A8C 8031CA8C 8E240044 */ lw $a0, 0x44($s1)
/* 0D7A90 8031CA90 50800004 */ beql $a0, $zero, .L8031CAA4
/* 0D7A94 8031CA94 26100004 */ addiu $s0, $s0, 4
/* 0D7A98 8031CA98 0C0C6C29 */ jal seq_channel_layer_process_script
/* 0D7A9C 8031CA9C 00000000 */ nop
/* 0D7AA0 8031CAA0 26100004 */ addiu $s0, $s0, 4
.L8031CAA4:
/* 0D7AA4 8031CAA4 1612FFF9 */ bne $s0, $s2, .L8031CA8C
/* 0D7AA8 8031CAA8 26310004 */ addiu $s1, $s1, 4
.L8031CAAC:
/* 0D7AAC 8031CAAC 8FBF0034 */ lw $ra, 0x34($sp)
.L8031CAB0:
/* 0D7AB0 8031CAB0 D7B40010 */ ldc1 $f20, 0x10($sp)
/* 0D7AB4 8031CAB4 8FB0001C */ lw $s0, 0x1c($sp)
/* 0D7AB8 8031CAB8 8FB10020 */ lw $s1, 0x20($sp)
/* 0D7ABC 8031CABC 8FB20024 */ lw $s2, 0x24($sp)
/* 0D7AC0 8031CAC0 8FB30028 */ lw $s3, 0x28($sp)
/* 0D7AC4 8031CAC4 8FB4002C */ lw $s4, 0x2c($sp)
/* 0D7AC8 8031CAC8 8FB50030 */ lw $s5, 0x30($sp)
/* 0D7ACC 8031CACC 03E00008 */ jr $ra
/* 0D7AD0 8031CAD0 27BD0068 */ addiu $sp, $sp, 0x68
|
96flashbacks/96flashbacks
| 16,105
|
asm/non_matchings/process_level_music_dynamics.s
|
.late_rodata
glabel jtbl_80338418
.word L8031FBAC
.word L8031FBEC
.word L8031FC2C
.word L8031FC6C
.word L8031FCAC
.word L8031FCEC
.word L8031FD2C
.word L8031FD54
.text
glabel process_level_music_dynamics # US: 803208EC
/* 0DAA4C 8031FA4C 27BDFFA0 */ addiu $sp, $sp, -0x60
/* 0DAA50 8031FA50 AFBF0024 */ sw $ra, 0x24($sp)
/* 0DAA54 8031FA54 AFB20020 */ sw $s2, 0x20($sp)
/* 0DAA58 8031FA58 AFB1001C */ sw $s1, 0x1c($sp)
/* 0DAA5C 8031FA5C AFB00018 */ sw $s0, 0x18($sp)
/* 0DAA60 8031FA60 0C0C7E5B */ jal func_8031F96C
/* 0DAA64 8031FA64 00002025 */ move $a0, $zero
/* 0DAA68 8031FA68 0C0C7E5B */ jal func_8031F96C
/* 0DAA6C 8031FA6C 24040002 */ li $a0, 2
/* 0DAA70 8031FA70 0C0C83B6 */ jal func_80320ED8
/* 0DAA74 8031FA74 00000000 */ nop
/* 0DAA78 8031FA78 3C038033 */ lui $v1, %hi(sMusicDynamicDelay) # $v1, 0x8033
/* 0DAA7C 8031FA7C 246320A0 */ addiu $v1, %lo(sMusicDynamicDelay) # addiu $v1, $v1, 0x20a0
/* 0DAA80 8031FA80 90620000 */ lbu $v0, ($v1)
/* 0DAA84 8031FA84 10400003 */ beqz $v0, .L8031FA94
/* 0DAA88 8031FA88 244EFFFF */ addiu $t6, $v0, -1
/* 0DAA8C 8031FA8C 10000005 */ b .L8031FAA4
/* 0DAA90 8031FA90 A06E0000 */ sb $t6, ($v1)
.L8031FA94:
/* 0DAA94 8031FA94 3C0F8033 */ lui $t7, %hi(sPlayer0CurSeqId) # $t7, 0x8033
/* 0DAA98 8031FA98 91EF209C */ lbu $t7, %lo(sPlayer0CurSeqId)($t7)
/* 0DAA9C 8031FA9C 3C018033 */ lui $at, %hi(sBackgroundMusicForDynamics) # $at, 0x8033
/* 0DAAA0 8031FAA0 A02F1EB0 */ sb $t7, %lo(sBackgroundMusicForDynamics)($at)
.L8031FAA4:
/* 0DAAA4 8031FAA4 3C188033 */ lui $t8, %hi(gCurrLevelNum) # $t8, 0x8033
/* 0DAAA8 8031FAA8 8718CE98 */ lh $t8, %lo(gCurrLevelNum)($t8)
/* 0DAAAC 8031FAAC 3C098033 */ lui $t1, %hi(sLevelDynamics)
/* 0DAAB0 8031FAB0 3C0C8033 */ lui $t4, %hi(sBackgroundMusicForDynamics) # $t4, 0x8033
/* 0DAAB4 8031FAB4 0018C880 */ sll $t9, $t8, 2
/* 0DAAB8 8031FAB8 01394821 */ addu $t1, $t1, $t9
/* 0DAABC 8031FABC 8D291EB4 */ lw $t1, %lo(sLevelDynamics)($t1)
/* 0DAAC0 8031FAC0 918C1EB0 */ lbu $t4, %lo(sBackgroundMusicForDynamics)($t4)
/* 0DAAC4 8031FAC4 852D0000 */ lh $t5, ($t1)
/* 0DAAC8 8031FAC8 558D00FC */ bnel $t4, $t5, .L8031FEBC
/* 0DAACC 8031FACC 8FBF0024 */ lw $ra, 0x24($sp)
/* 0DAAD0 8031FAD0 852F0002 */ lh $t7, 2($t1)
/* 0DAAD4 8031FAD4 24110002 */ li $s1, 2
/* 0DAAD8 8031FAD8 3C0B8034 */ lui $t3, %hi(gCurrAreaIndex) # $t3, 0x8034
/* 0DAADC 8031FADC 31F0FF00 */ andi $s0, $t7, 0xff00
/* 0DAAE0 8031FAE0 3218FF00 */ andi $t8, $s0, 0xff00
/* 0DAAE4 8031FAE4 130000B9 */ beqz $t8, .L8031FDCC
/* 0DAAE8 8031FAE8 A3AF0057 */ sb $t7, 0x57($sp)
/* 0DAAEC 8031FAEC 3C0A8036 */ lui $t2, %hi(gMarioCurrentRoom) # $t2, 0x8036
/* 0DAAF0 8031FAF0 3C078034 */ lui $a3, %hi(gMarioStates) # $a3, 0x8034
/* 0DAAF4 8031FAF4 24E79E00 */ addiu $a3, %lo(gMarioStates) # addiu $a3, $a3, -0x6200
/* 0DAAF8 8031FAF8 254AFEE0 */ addiu $t2, %lo(gMarioCurrentRoom) # addiu $t2, $t2, -0x120
/* 0DAAFC 8031FAFC 256BA75A */ addiu $t3, %lo(gCurrAreaIndex) # addiu $t3, $t3, -0x58a6
/* 0DAB00 8031FB00 27A8003C */ addiu $t0, $sp, 0x3c
/* 0DAB04 8031FB04 27A60044 */ addiu $a2, $sp, 0x44
.L8031FB08:
/* 0DAB08 8031FB08 00001025 */ move $v0, $zero
/* 0DAB0C 8031FB0C 00002025 */ move $a0, $zero
/* 0DAB10 8031FB10 34058000 */ li $a1, 32768
.L8031FB14:
/* 0DAB14 8031FB14 00B0C824 */ and $t9, $a1, $s0
/* 0DAB18 8031FB18 1320000F */ beqz $t9, .L8031FB58
/* 0DAB1C 8031FB1C 00A01825 */ move $v1, $a1
/* 0DAB20 8031FB20 00116040 */ sll $t4, $s1, 1
/* 0DAB24 8031FB24 012C6821 */ addu $t5, $t1, $t4
/* 0DAB28 8031FB28 85AE0000 */ lh $t6, ($t5)
/* 0DAB2C 8031FB2C 00047840 */ sll $t7, $a0, 1
/* 0DAB30 8031FB30 01046021 */ addu $t4, $t0, $a0
/* 0DAB34 8031FB34 00CFC021 */ addu $t8, $a2, $t7
/* 0DAB38 8031FB38 26310001 */ addiu $s1, $s1, 1
/* 0DAB3C 8031FB3C 24840001 */ addiu $a0, $a0, 1
/* 0DAB40 8031FB40 323900FF */ andi $t9, $s1, 0xff
/* 0DAB44 8031FB44 308D00FF */ andi $t5, $a0, 0xff
/* 0DAB48 8031FB48 A70E0000 */ sh $t6, ($t8)
/* 0DAB4C 8031FB4C 03208825 */ move $s1, $t9
/* 0DAB50 8031FB50 A1820000 */ sb $v0, ($t4)
/* 0DAB54 8031FB54 01A02025 */ move $a0, $t5
.L8031FB58:
/* 0DAB58 8031FB58 24420001 */ addiu $v0, $v0, 1
/* 0DAB5C 8031FB5C 304F00FF */ andi $t7, $v0, 0xff
/* 0DAB60 8031FB60 00032843 */ sra $a1, $v1, 1
/* 0DAB64 8031FB64 30AEFFFF */ andi $t6, $a1, 0xffff
/* 0DAB68 8031FB68 29E10008 */ slti $at, $t7, 8
/* 0DAB6C 8031FB6C 01E01025 */ move $v0, $t7
/* 0DAB70 8031FB70 1420FFE8 */ bnez $at, .L8031FB14
/* 0DAB74 8031FB74 01C02825 */ move $a1, $t6
/* 0DAB78 8031FB78 00001025 */ move $v0, $zero
/* 0DAB7C 8031FB7C 18800083 */ blez $a0, .L8031FD8C
/* 0DAB80 8031FB80 00801825 */ move $v1, $a0
.L8031FB84:
/* 0DAB84 8031FB84 0102C021 */ addu $t8, $t0, $v0
/* 0DAB88 8031FB88 93190000 */ lbu $t9, ($t8)
/* 0DAB8C 8031FB8C 2F210008 */ sltiu $at, $t9, 8
/* 0DAB90 8031FB90 10200079 */ beqz $at, .L8031FD78
/* 0DAB94 8031FB94 0019C880 */ sll $t9, $t9, 2
/* 0DAB98 8031FB98 3C018034 */ lui $at, %hi(jtbl_80338418)
/* 0DAB9C 8031FB9C 00390821 */ addu $at, $at, $t9
/* 0DABA0 8031FBA0 8C398418 */ lw $t9, %lo(jtbl_80338418)($at)
/* 0DABA4 8031FBA4 03200008 */ jr $t9
/* 0DABA8 8031FBA8 00000000 */ nop
glabel L8031FBAC
/* 0DABAC 8031FBAC C4E4003C */ lwc1 $f4, 0x3c($a3)
/* 0DABB0 8031FBB0 0002C040 */ sll $t8, $v0, 1
/* 0DABB4 8031FBB4 00D8C821 */ addu $t9, $a2, $t8
/* 0DABB8 8031FBB8 4600218D */ trunc.w.s $f6, $f4
/* 0DABBC 8031FBBC 872C0000 */ lh $t4, ($t9)
/* 0DABC0 8031FBC0 440D3000 */ mfc1 $t5, $f6
/* 0DABC4 8031FBC4 00000000 */ nop
/* 0DABC8 8031FBC8 000D7C00 */ sll $t7, $t5, 0x10
/* 0DABCC 8031FBCC 000F7403 */ sra $t6, $t7, 0x10
/* 0DABD0 8031FBD0 01CC082A */ slt $at, $t6, $t4
/* 0DABD4 8031FBD4 50200069 */ beql $at, $zero, .L8031FD7C
/* 0DABD8 8031FBD8 24420001 */ addiu $v0, $v0, 1
/* 0DABDC 8031FBDC 24620001 */ addiu $v0, $v1, 1
/* 0DABE0 8031FBE0 304D00FF */ andi $t5, $v0, 0xff
/* 0DABE4 8031FBE4 10000064 */ b .L8031FD78
/* 0DABE8 8031FBE8 01A01025 */ move $v0, $t5
glabel L8031FBEC
/* 0DABEC 8031FBEC C4E80040 */ lwc1 $f8, 0x40($a3)
/* 0DABF0 8031FBF0 00026040 */ sll $t4, $v0, 1
/* 0DABF4 8031FBF4 00CC6821 */ addu $t5, $a2, $t4
/* 0DABF8 8031FBF8 4600428D */ trunc.w.s $f10, $f8
/* 0DABFC 8031FBFC 85AF0000 */ lh $t7, ($t5)
/* 0DAC00 8031FC00 44185000 */ mfc1 $t8, $f10
/* 0DAC04 8031FC04 00000000 */ nop
/* 0DAC08 8031FC08 0018CC00 */ sll $t9, $t8, 0x10
/* 0DAC0C 8031FC0C 00197403 */ sra $t6, $t9, 0x10
/* 0DAC10 8031FC10 01CF082A */ slt $at, $t6, $t7
/* 0DAC14 8031FC14 50200059 */ beql $at, $zero, .L8031FD7C
/* 0DAC18 8031FC18 24420001 */ addiu $v0, $v0, 1
/* 0DAC1C 8031FC1C 24620001 */ addiu $v0, $v1, 1
/* 0DAC20 8031FC20 305800FF */ andi $t8, $v0, 0xff
/* 0DAC24 8031FC24 10000054 */ b .L8031FD78
/* 0DAC28 8031FC28 03001025 */ move $v0, $t8
glabel L8031FC2C
/* 0DAC2C 8031FC2C C4F00044 */ lwc1 $f16, 0x44($a3)
/* 0DAC30 8031FC30 00027840 */ sll $t7, $v0, 1
/* 0DAC34 8031FC34 00CFC021 */ addu $t8, $a2, $t7
/* 0DAC38 8031FC38 4600848D */ trunc.w.s $f18, $f16
/* 0DAC3C 8031FC3C 87190000 */ lh $t9, ($t8)
/* 0DAC40 8031FC40 440C9000 */ mfc1 $t4, $f18
/* 0DAC44 8031FC44 00000000 */ nop
/* 0DAC48 8031FC48 000C6C00 */ sll $t5, $t4, 0x10
/* 0DAC4C 8031FC4C 000D7403 */ sra $t6, $t5, 0x10
/* 0DAC50 8031FC50 01D9082A */ slt $at, $t6, $t9
/* 0DAC54 8031FC54 50200049 */ beql $at, $zero, .L8031FD7C
/* 0DAC58 8031FC58 24420001 */ addiu $v0, $v0, 1
/* 0DAC5C 8031FC5C 24620001 */ addiu $v0, $v1, 1
/* 0DAC60 8031FC60 304C00FF */ andi $t4, $v0, 0xff
/* 0DAC64 8031FC64 10000044 */ b .L8031FD78
/* 0DAC68 8031FC68 01801025 */ move $v0, $t4
glabel L8031FC6C
/* 0DAC6C 8031FC6C C4E4003C */ lwc1 $f4, 0x3c($a3)
/* 0DAC70 8031FC70 0002C840 */ sll $t9, $v0, 1
/* 0DAC74 8031FC74 00D96021 */ addu $t4, $a2, $t9
/* 0DAC78 8031FC78 4600218D */ trunc.w.s $f6, $f4
/* 0DAC7C 8031FC7C 858D0000 */ lh $t5, ($t4)
/* 0DAC80 8031FC80 440F3000 */ mfc1 $t7, $f6
/* 0DAC84 8031FC84 00000000 */ nop
/* 0DAC88 8031FC88 000FC400 */ sll $t8, $t7, 0x10
/* 0DAC8C 8031FC8C 00187403 */ sra $t6, $t8, 0x10
/* 0DAC90 8031FC90 01CD082A */ slt $at, $t6, $t5
/* 0DAC94 8031FC94 54200039 */ bnezl $at, .L8031FD7C
/* 0DAC98 8031FC98 24420001 */ addiu $v0, $v0, 1
/* 0DAC9C 8031FC9C 24620001 */ addiu $v0, $v1, 1
/* 0DACA0 8031FCA0 304F00FF */ andi $t7, $v0, 0xff
/* 0DACA4 8031FCA4 10000034 */ b .L8031FD78
/* 0DACA8 8031FCA8 01E01025 */ move $v0, $t7
glabel L8031FCAC
/* 0DACAC 8031FCAC C4E80040 */ lwc1 $f8, 0x40($a3)
/* 0DACB0 8031FCB0 00026840 */ sll $t5, $v0, 1
/* 0DACB4 8031FCB4 00CD7821 */ addu $t7, $a2, $t5
/* 0DACB8 8031FCB8 4600428D */ trunc.w.s $f10, $f8
/* 0DACBC 8031FCBC 85F80000 */ lh $t8, ($t7)
/* 0DACC0 8031FCC0 44195000 */ mfc1 $t9, $f10
/* 0DACC4 8031FCC4 00000000 */ nop
/* 0DACC8 8031FCC8 00196400 */ sll $t4, $t9, 0x10
/* 0DACCC 8031FCCC 000C7403 */ sra $t6, $t4, 0x10
/* 0DACD0 8031FCD0 01D8082A */ slt $at, $t6, $t8
/* 0DACD4 8031FCD4 54200029 */ bnezl $at, .L8031FD7C
/* 0DACD8 8031FCD8 24420001 */ addiu $v0, $v0, 1
/* 0DACDC 8031FCDC 24620001 */ addiu $v0, $v1, 1
/* 0DACE0 8031FCE0 305900FF */ andi $t9, $v0, 0xff
/* 0DACE4 8031FCE4 10000024 */ b .L8031FD78
/* 0DACE8 8031FCE8 03201025 */ move $v0, $t9
glabel L8031FCEC
/* 0DACEC 8031FCEC C4F00044 */ lwc1 $f16, 0x44($a3)
/* 0DACF0 8031FCF0 0002C040 */ sll $t8, $v0, 1
/* 0DACF4 8031FCF4 00D8C821 */ addu $t9, $a2, $t8
/* 0DACF8 8031FCF8 4600848D */ trunc.w.s $f18, $f16
/* 0DACFC 8031FCFC 872C0000 */ lh $t4, ($t9)
/* 0DAD00 8031FD00 440D9000 */ mfc1 $t5, $f18
/* 0DAD04 8031FD04 00000000 */ nop
/* 0DAD08 8031FD08 000D7C00 */ sll $t7, $t5, 0x10
/* 0DAD0C 8031FD0C 000F7403 */ sra $t6, $t7, 0x10
/* 0DAD10 8031FD10 01CC082A */ slt $at, $t6, $t4
/* 0DAD14 8031FD14 54200019 */ bnezl $at, .L8031FD7C
/* 0DAD18 8031FD18 24420001 */ addiu $v0, $v0, 1
/* 0DAD1C 8031FD1C 24620001 */ addiu $v0, $v1, 1
/* 0DAD20 8031FD20 304D00FF */ andi $t5, $v0, 0xff
/* 0DAD24 8031FD24 10000014 */ b .L8031FD78
/* 0DAD28 8031FD28 01A01025 */ move $v0, $t5
glabel L8031FD2C
/* 0DAD2C 8031FD2C 0002C040 */ sll $t8, $v0, 1
/* 0DAD30 8031FD30 00D8C821 */ addu $t9, $a2, $t8
/* 0DAD34 8031FD34 872E0000 */ lh $t6, ($t9)
/* 0DAD38 8031FD38 856F0000 */ lh $t7, ($t3)
/* 0DAD3C 8031FD3C 51EE000F */ beql $t7, $t6, .L8031FD7C
/* 0DAD40 8031FD40 24420001 */ addiu $v0, $v0, 1
/* 0DAD44 8031FD44 24620001 */ addiu $v0, $v1, 1
/* 0DAD48 8031FD48 304C00FF */ andi $t4, $v0, 0xff
/* 0DAD4C 8031FD4C 1000000A */ b .L8031FD78
/* 0DAD50 8031FD50 01801025 */ move $v0, $t4
glabel L8031FD54
/* 0DAD54 8031FD54 0002C040 */ sll $t8, $v0, 1
/* 0DAD58 8031FD58 00D8C821 */ addu $t9, $a2, $t8
/* 0DAD5C 8031FD5C 872F0000 */ lh $t7, ($t9)
/* 0DAD60 8031FD60 854D0000 */ lh $t5, ($t2)
/* 0DAD64 8031FD64 51AF0005 */ beql $t5, $t7, .L8031FD7C
/* 0DAD68 8031FD68 24420001 */ addiu $v0, $v0, 1
/* 0DAD6C 8031FD6C 24620001 */ addiu $v0, $v1, 1
/* 0DAD70 8031FD70 304E00FF */ andi $t6, $v0, 0xff
/* 0DAD74 8031FD74 01C01025 */ move $v0, $t6
.L8031FD78:
/* 0DAD78 8031FD78 24420001 */ addiu $v0, $v0, 1
.L8031FD7C:
/* 0DAD7C 8031FD7C 304C00FF */ andi $t4, $v0, 0xff
/* 0DAD80 8031FD80 0183082A */ slt $at, $t4, $v1
/* 0DAD84 8031FD84 1420FF7F */ bnez $at, .L8031FB84
/* 0DAD88 8031FD88 01801025 */ move $v0, $t4
.L8031FD8C:
/* 0DAD8C 8031FD8C 14620003 */ bne $v1, $v0, .L8031FD9C
/* 0DAD90 8031FD90 0011C040 */ sll $t8, $s1, 1
/* 0DAD94 8031FD94 1000000A */ b .L8031FDC0
/* 0DAD98 8031FD98 00001825 */ move $v1, $zero
.L8031FD9C:
/* 0DAD9C 8031FD9C 0138C821 */ addu $t9, $t1, $t8
/* 0DADA0 8031FDA0 872F0000 */ lh $t7, ($t9)
/* 0DADA4 8031FDA4 26310001 */ addiu $s1, $s1, 1
/* 0DADA8 8031FDA8 322E00FF */ andi $t6, $s1, 0xff
/* 0DADAC 8031FDAC 01E01825 */ move $v1, $t7
/* 0DADB0 8031FDB0 306DFF00 */ andi $t5, $v1, 0xff00
/* 0DADB4 8031FDB4 01A01825 */ move $v1, $t5
/* 0DADB8 8031FDB8 01C08825 */ move $s1, $t6
/* 0DADBC 8031FDBC A3AF0057 */ sb $t7, 0x57($sp)
.L8031FDC0:
/* 0DADC0 8031FDC0 306CFF00 */ andi $t4, $v1, 0xff00
/* 0DADC4 8031FDC4 1580FF50 */ bnez $t4, .L8031FB08
/* 0DADC8 8031FDC8 00608025 */ move $s0, $v1
.L8031FDCC:
/* 0DADCC 8031FDCC 3C028033 */ lui $v0, %hi(sCurrentMusicDynamic) # $v0, 0x8033
/* 0DADD0 8031FDD0 90421EAC */ lbu $v0, %lo(sCurrentMusicDynamic)($v0)
/* 0DADD4 8031FDD4 93B80057 */ lbu $t8, 0x57($sp)
/* 0DADD8 8031FDD8 240100FF */ li $at, 255
/* 0DADDC 8031FDDC 00008825 */ move $s1, $zero
/* 0DADE0 8031FDE0 53020036 */ beql $t8, $v0, .L8031FEBC
/* 0DADE4 8031FDE4 8FBF0024 */ lw $ra, 0x24($sp)
/* 0DADE8 8031FDE8 1441000C */ bne $v0, $at, .L8031FE1C
/* 0DADEC 8031FDEC 24030001 */ li $v1, 1
/* 0DADF0 8031FDF0 00187880 */ sll $t7, $t8, 2
/* 0DADF4 8031FDF4 01F87823 */ subu $t7, $t7, $t8
/* 0DADF8 8031FDF8 3C0E8033 */ lui $t6, %hi(sMusicDynamics) # $t6, 0x8033
/* 0DADFC 8031FDFC 24190001 */ li $t9, 1
/* 0DAE00 8031FE00 25CE1F50 */ addiu $t6, %lo(sMusicDynamics) # addiu $t6, $t6, 0x1f50
/* 0DAE04 8031FE04 000F7880 */ sll $t7, $t7, 2
/* 0DAE08 8031FE08 240D0001 */ li $t5, 1
/* 0DAE0C 8031FE0C A7B9003A */ sh $t9, 0x3a($sp)
/* 0DAE10 8031FE10 A7AD0038 */ sh $t5, 0x38($sp)
/* 0DAE14 8031FE14 1000000C */ b .L8031FE48
/* 0DAE18 8031FE18 01EE9021 */ addu $s2, $t7, $t6
.L8031FE1C:
/* 0DAE1C 8031FE1C 93AC0057 */ lbu $t4, 0x57($sp)
/* 0DAE20 8031FE20 3C0D8033 */ lui $t5, %hi(sMusicDynamics) # $t5, 0x8033
/* 0DAE24 8031FE24 25AD1F50 */ addiu $t5, %lo(sMusicDynamics) # addiu $t5, $t5, 0x1f50
/* 0DAE28 8031FE28 000CC880 */ sll $t9, $t4, 2
/* 0DAE2C 8031FE2C 032CC823 */ subu $t9, $t9, $t4
/* 0DAE30 8031FE30 0019C880 */ sll $t9, $t9, 2
/* 0DAE34 8031FE34 032D9021 */ addu $s2, $t9, $t5
/* 0DAE38 8031FE38 86580004 */ lh $t8, 4($s2)
/* 0DAE3C 8031FE3C 864F000A */ lh $t7, 0xa($s2)
/* 0DAE40 8031FE40 A7B8003A */ sh $t8, 0x3a($sp)
/* 0DAE44 8031FE44 A7AF0038 */ sh $t7, 0x38($sp)
.L8031FE48:
/* 0DAE48 8031FE48 864E0000 */ lh $t6, ($s2)
/* 0DAE4C 8031FE4C 00608025 */ move $s0, $v1
/* 0DAE50 8031FE50 00002025 */ move $a0, $zero
/* 0DAE54 8031FE54 01C36024 */ and $t4, $t6, $v1
/* 0DAE58 8031FE58 11800004 */ beqz $t4, .L8031FE6C
/* 0DAE5C 8031FE5C 322500FF */ andi $a1, $s1, 0xff
/* 0DAE60 8031FE60 92460003 */ lbu $a2, 3($s2)
/* 0DAE64 8031FE64 0C0C7E22 */ jal fade_channel_volume_scale
/* 0DAE68 8031FE68 97A7003A */ lhu $a3, 0x3a($sp)
.L8031FE6C:
/* 0DAE6C 8031FE6C 86590006 */ lh $t9, 6($s2)
/* 0DAE70 8031FE70 00002025 */ move $a0, $zero
/* 0DAE74 8031FE74 322500FF */ andi $a1, $s1, 0xff
/* 0DAE78 8031FE78 03306824 */ and $t5, $t9, $s0
/* 0DAE7C 8031FE7C 11A00003 */ beqz $t5, .L8031FE8C
/* 0DAE80 8031FE80 97A70038 */ lhu $a3, 0x38($sp)
/* 0DAE84 8031FE84 0C0C7E22 */ jal fade_channel_volume_scale
/* 0DAE88 8031FE88 92460009 */ lbu $a2, 9($s2)
.L8031FE8C:
/* 0DAE8C 8031FE8C 26310001 */ addiu $s1, $s1, 1
/* 0DAE90 8031FE90 322F00FF */ andi $t7, $s1, 0xff
/* 0DAE94 8031FE94 00101840 */ sll $v1, $s0, 1
/* 0DAE98 8031FE98 29E10010 */ slti $at, $t7, 0x10
/* 0DAE9C 8031FE9C 3078FFFF */ andi $t8, $v1, 0xffff
/* 0DAEA0 8031FEA0 01E08825 */ move $s1, $t7
/* 0DAEA4 8031FEA4 1420FFE8 */ bnez $at, .L8031FE48
/* 0DAEA8 8031FEA8 03001825 */ move $v1, $t8
/* 0DAEAC 8031FEAC 93AE0057 */ lbu $t6, 0x57($sp)
/* 0DAEB0 8031FEB0 3C018033 */ lui $at, %hi(sCurrentMusicDynamic) # $at, 0x8033
/* 0DAEB4 8031FEB4 A02E1EAC */ sb $t6, %lo(sCurrentMusicDynamic)($at)
/* 0DAEB8 8031FEB8 8FBF0024 */ lw $ra, 0x24($sp)
.L8031FEBC:
/* 0DAEBC 8031FEBC 8FB00018 */ lw $s0, 0x18($sp)
/* 0DAEC0 8031FEC0 8FB1001C */ lw $s1, 0x1c($sp)
/* 0DAEC4 8031FEC4 8FB20020 */ lw $s2, 0x20($sp)
/* 0DAEC8 8031FEC8 03E00008 */ jr $ra
/* 0DAECC 8031FECC 27BD0060 */ addiu $sp, $sp, 0x60
|
96flashbacks/96flashbacks
| 46,792
|
asm/non_matchings/seq_channel_layer_process_script_us.s
|
.late_rodata
glabel jtbl_80337C90
.word L8031C2DC
.word L8031C298
.word L8031C6A0
.word L8031C6A0
.word L8031C328
.word L8031C23C
.word L8031C6A0
.word L8031C6A0
.word L8031C200
glabel jtbl_80337CB4
.word L8031C36C
.word L8031C3BC
.word L8031C454
.word L8031C3E8
.word L8031C3E8
.word L8031C4A4
.word L8031C5C8
.word L8031C698
.word L8031C3BC
.word L8031C36C
glabel jtbl_80337CDC
.word L8031CBE0
.word L8031CBEC
.word L8031CBE0
.word L8031CBEC
.word L8031CBE0
.text
glabel seq_channel_layer_process_script
/* 0D70C4 8031C0C4 27BDFFA0 */ addiu $sp, $sp, -0x60
/* 0D70C8 8031C0C8 240E0001 */ li $t6, 1
/* 0D70CC 8031C0CC AFBF001C */ sw $ra, 0x1c($sp)
/* 0D70D0 8031C0D0 AFB00018 */ sw $s0, 0x18($sp)
/* 0D70D4 8031C0D4 A3AE003F */ sb $t6, 0x3f($sp)
/* 0D70D8 8031C0D8 8C820000 */ lw $v0, ($a0)
/* 0D70DC 8031C0DC 00808025 */ move $s0, $a0
/* 0D70E0 8031C0E0 00027FC2 */ srl $t7, $v0, 0x1f
/* 0D70E4 8031C0E4 51E00357 */ beql $t7, $zero, .L8031CE44
/* 0D70E8 8031C0E8 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D70EC 8031C0EC 8483003C */ lh $v1, 0x3c($a0)
/* 0D70F0 8031C0F0 00027080 */ sll $t6, $v0, 2
/* 0D70F4 8031C0F4 0002C8C0 */ sll $t9, $v0, 3
/* 0D70F8 8031C0F8 28610002 */ slti $at, $v1, 2
/* 0D70FC 8031C0FC 1420000E */ bnez $at, .L8031C138
/* 0D7100 8031C100 2478FFFF */ addiu $t8, $v1, -1
/* 0D7104 8031C104 05C0034E */ bltz $t6, .L8031CE40
/* 0D7108 8031C108 A498003C */ sh $t8, 0x3c($a0)
/* 0D710C 8031C10C 848F003E */ lh $t7, 0x3e($a0)
/* 0D7110 8031C110 8498003C */ lh $t8, 0x3c($a0)
/* 0D7114 8031C114 01F8082A */ slt $at, $t7, $t8
/* 0D7118 8031C118 5420034A */ bnezl $at, .L8031CE44
/* 0D711C 8031C11C 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D7120 8031C120 0C0C67D9 */ jal seq_channel_layer_note_decay
/* 0D7124 8031C124 00000000 */ nop
/* 0D7128 8031C128 920E0000 */ lbu $t6, ($s0)
/* 0D712C 8031C12C 35CF0020 */ ori $t7, $t6, 0x20
/* 0D7130 8031C130 10000343 */ b .L8031CE40
/* 0D7134 8031C134 A20F0000 */ sb $t7, ($s0)
.L8031C138:
/* 0D7138 8031C138 07220004 */ bltzl $t9, .L8031C14C_2
/* 0D713C 8031C13C 92020004 */ lbu $v0, 4($s0)
/* 0D7140 8031C140 0C0C67D9 */ jal seq_channel_layer_note_decay
/* 0D7144 8031C144 02002025 */ move $a0, $s0
/* 0D7148 8031C148 92020004 */ lbu $v0, 4($s0)
.L8031C14C_2:
/* 0D714C 8031C14C 2401FF7F */ li $at, -129
/* 0D7150 8031C150 3C1F8022 */ lui $ra, %hi(gCtlEntries) # $ra, 0x8022
/* 0D7154 8031C154 00417024 */ and $t6, $v0, $at
/* 0D7158 8031C158 24010001 */ li $at, 1
/* 0D715C 8031C15C 11C10004 */ beq $t6, $at, .L8031C170
/* 0D7160 8031C160 27FF6B60 */ addiu $ra, %lo(gCtlEntries) # addiu $ra, $ra, 0x6b60
/* 0D7164 8031C164 24010002 */ li $at, 2
/* 0D7168 8031C168 55C10003 */ bnel $t6, $at, .L8031C178
/* 0D716C 8031C16C 8E0D0050 */ lw $t5, 0x50($s0)
.L8031C170:
/* 0D7170 8031C170 A2000004 */ sb $zero, 4($s0)
/* 0D7174 8031C174 8E0D0050 */ lw $t5, 0x50($s0)
.L8031C178:
/* 0D7178 8031C178 3C013C00 */ li $at, 0x3C000000 # 0.007812
/* 0D717C 8031C17C 3C0B8022 */ lui $t3, %hi(gBankLoadedPool) # $t3, 0x8022
/* 0D7180 8031C180 44810000 */ mtc1 $at, $f0
/* 0D7184 8031C184 256B10F8 */ addiu $t3, %lo(gBankLoadedPool) # addiu $t3, $t3, 0x10f8
/* 0D7188 8031C188 97AA003A */ lhu $t2, 0x3a($sp)
/* 0D718C 8031C18C 240900FF */ li $t1, 255
/* 0D7190 8031C190 8DAC0040 */ lw $t4, 0x40($t5)
.L8031C194:
/* 0D7194 8031C194 8E020054 */ lw $v0, 0x54($s0)
.L8031C198:
/* 0D7198 8031C198 244F0001 */ addiu $t7, $v0, 1
/* 0D719C 8031C19C AE0F0054 */ sw $t7, 0x54($s0)
/* 0D71A0 8031C1A0 90440000 */ lbu $a0, ($v0)
/* 0D71A4 8031C1A4 288100C1 */ slti $at, $a0, 0xc1
/* 0D71A8 8031C1A8 14200156 */ bnez $at, .L8031C704
/* 0D71AC 8031C1AC 00802825 */ move $a1, $a0
/* 0D71B0 8031C1B0 288100CB */ slti $at, $a0, 0xcb
/* 0D71B4 8031C1B4 1420000A */ bnez $at, .L8031C1E0
/* 0D71B8 8031C1B8 24B9FF3F */ addiu $t9, $a1, -0xc1
/* 0D71BC 8031C1BC 2498FF09 */ addiu $t8, $a0, -0xf7
/* 0D71C0 8031C1C0 2F010009 */ sltiu $at, $t8, 9
/* 0D71C4 8031C1C4 10200136 */ beqz $at, .L8031C6A0
/* 0D71C8 8031C1C8 0018C080 */ sll $t8, $t8, 2
/* 0D71CC 8031C1CC 3C018034 */ lui $at, %hi(jtbl_80337C90)
/* 0D71D0 8031C1D0 00380821 */ addu $at, $at, $t8
/* 0D71D4 8031C1D4 8C388E60 */ lw $t8, %lo(jtbl_80337C90)($at)
/* 0D71D8 8031C1D8 03000008 */ jr $t8
/* 0D71DC 8031C1DC 00000000 */ nop
.L8031C1E0:
/* 0D71E0 8031C1E0 2F21000A */ sltiu $at, $t9, 0xa
/* 0D71E4 8031C1E4 1020012E */ beqz $at, .L8031C6A0
/* 0D71E8 8031C1E8 0019C880 */ sll $t9, $t9, 2
/* 0D71EC 8031C1EC 3C018034 */ lui $at, %hi(jtbl_80337CB4)
/* 0D71F0 8031C1F0 00390821 */ addu $at, $at, $t9
/* 0D71F4 8031C1F4 8C398E84 */ lw $t9, %lo(jtbl_80337CB4)($at)
/* 0D71F8 8031C1F8 03200008 */ jr $t9
/* 0D71FC 8031C1FC 00000000 */ nop
glabel L8031C200
/* 0D7200 8031C200 26020054 */ addiu $v0, $s0, 0x54
/* 0D7204 8031C204 90430018 */ lbu $v1, 0x18($v0)
/* 0D7208 8031C208 14600005 */ bnez $v1, .L8031C220
/* 0D720C 8031C20C 246EFFFF */ addiu $t6, $v1, -1
/* 0D7210 8031C210 0C0C6E8C */ jal seq_channel_layer_disable
/* 0D7214 8031C214 02002025 */ move $a0, $s0
/* 0D7218 8031C218 1000030A */ b .L8031CE44
/* 0D721C 8031C21C 8FBF001C */ lw $ra, 0x1c($sp)
.L8031C220:
/* 0D7220 8031C220 31CF00FF */ andi $t7, $t6, 0xff
/* 0D7224 8031C224 000FC080 */ sll $t8, $t7, 2
/* 0D7228 8031C228 0058C821 */ addu $t9, $v0, $t8
/* 0D722C 8031C22C A04E0018 */ sb $t6, 0x18($v0)
/* 0D7230 8031C230 8F2E0004 */ lw $t6, 4($t9)
/* 0D7234 8031C234 1000FFD7 */ b .L8031C194
/* 0D7238 8031C238 AC4E0000 */ sw $t6, ($v0)
glabel L8031C23C
/* 0D723C 8031C23C 26020054 */ addiu $v0, $s0, 0x54
/* 0D7240 8031C240 8C430000 */ lw $v1, ($v0)
/* 0D7244 8031C244 90640000 */ lbu $a0, ($v1)
/* 0D7248 8031C248 246E0001 */ addiu $t6, $v1, 1
/* 0D724C 8031C24C AC4E0000 */ sw $t6, ($v0)
/* 0D7250 8031C250 91CF0000 */ lbu $t7, ($t6)
/* 0D7254 8031C254 0004CA00 */ sll $t9, $a0, 8
/* 0D7258 8031C258 01F92825 */ or $a1, $t7, $t9
/* 0D725C 8031C25C 904F0018 */ lbu $t7, 0x18($v0)
/* 0D7260 8031C260 25D90001 */ addiu $t9, $t6, 1
/* 0D7264 8031C264 AC590000 */ sw $t9, ($v0)
/* 0D7268 8031C268 25F80001 */ addiu $t8, $t7, 1
/* 0D726C 8031C26C 330E00FF */ andi $t6, $t8, 0xff
/* 0D7270 8031C270 000E7880 */ sll $t7, $t6, 2
/* 0D7274 8031C274 A0580018 */ sb $t8, 0x18($v0)
/* 0D7278 8031C278 004FC021 */ addu $t8, $v0, $t7
/* 0D727C 8031C27C AF190000 */ sw $t9, ($t8)
/* 0D7280 8031C280 8D8E0014 */ lw $t6, 0x14($t4)
/* 0D7284 8031C284 30AFFFFF */ andi $t7, $a1, 0xffff
/* 0D7288 8031C288 30AAFFFF */ andi $t2, $a1, 0xffff
/* 0D728C 8031C28C 01CFC821 */ addu $t9, $t6, $t7
/* 0D7290 8031C290 1000FFC0 */ b .L8031C194
/* 0D7294 8031C294 AC590000 */ sw $t9, ($v0)
glabel L8031C298
/* 0D7298 8031C298 26020054 */ addiu $v0, $s0, 0x54
/* 0D729C 8031C29C 8C430000 */ lw $v1, ($v0)
/* 0D72A0 8031C2A0 904E0018 */ lbu $t6, 0x18($v0)
/* 0D72A4 8031C2A4 24780001 */ addiu $t8, $v1, 1
/* 0D72A8 8031C2A8 AC580000 */ sw $t8, ($v0)
/* 0D72AC 8031C2AC 90650000 */ lbu $a1, ($v1)
/* 0D72B0 8031C2B0 004E7821 */ addu $t7, $v0, $t6
/* 0D72B4 8031C2B4 A1E50014 */ sb $a1, 0x14($t7)
/* 0D72B8 8031C2B8 90590018 */ lbu $t9, 0x18($v0)
/* 0D72BC 8031C2BC 8C4E0000 */ lw $t6, ($v0)
/* 0D72C0 8031C2C0 27380001 */ addiu $t8, $t9, 1
/* 0D72C4 8031C2C4 330F00FF */ andi $t7, $t8, 0xff
/* 0D72C8 8031C2C8 000FC880 */ sll $t9, $t7, 2
/* 0D72CC 8031C2CC A0580018 */ sb $t8, 0x18($v0)
/* 0D72D0 8031C2D0 0059C021 */ addu $t8, $v0, $t9
/* 0D72D4 8031C2D4 1000FFAF */ b .L8031C194
/* 0D72D8 8031C2D8 AF0E0000 */ sw $t6, ($t8)
glabel L8031C2DC
/* 0D72DC 8031C2DC 26020054 */ addiu $v0, $s0, 0x54
/* 0D72E0 8031C2E0 904F0018 */ lbu $t7, 0x18($v0)
/* 0D72E4 8031C2E4 004F2021 */ addu $a0, $v0, $t7
/* 0D72E8 8031C2E8 90990013 */ lbu $t9, 0x13($a0)
/* 0D72EC 8031C2EC 272EFFFF */ addiu $t6, $t9, -1
/* 0D72F0 8031C2F0 A08E0013 */ sb $t6, 0x13($a0)
/* 0D72F4 8031C2F4 90430018 */ lbu $v1, 0x18($v0)
/* 0D72F8 8031C2F8 0043C021 */ addu $t8, $v0, $v1
/* 0D72FC 8031C2FC 930F0013 */ lbu $t7, 0x13($t8)
/* 0D7300 8031C300 00602825 */ move $a1, $v1
/* 0D7304 8031C304 0005C880 */ sll $t9, $a1, 2
/* 0D7308 8031C308 11E00004 */ beqz $t7, .L8031C31C
/* 0D730C 8031C30C 00597021 */ addu $t6, $v0, $t9
/* 0D7310 8031C310 8DD80000 */ lw $t8, ($t6)
/* 0D7314 8031C314 1000FF9F */ b .L8031C194
/* 0D7318 8031C318 AC580000 */ sw $t8, ($v0)
.L8031C31C:
/* 0D731C 8031C31C 246FFFFF */ addiu $t7, $v1, -1
/* 0D7320 8031C320 1000FF9C */ b .L8031C194
/* 0D7324 8031C324 A04F0018 */ sb $t7, 0x18($v0)
glabel L8031C328
/* 0D7328 8031C328 26020054 */ addiu $v0, $s0, 0x54
/* 0D732C 8031C32C 8C430000 */ lw $v1, ($v0)
/* 0D7330 8031C330 90640000 */ lbu $a0, ($v1)
/* 0D7334 8031C334 246F0001 */ addiu $t7, $v1, 1
/* 0D7338 8031C338 AC4F0000 */ sw $t7, ($v0)
/* 0D733C 8031C33C 91F90000 */ lbu $t9, ($t7)
/* 0D7340 8031C340 0004C200 */ sll $t8, $a0, 8
/* 0D7344 8031C344 25EF0001 */ addiu $t7, $t7, 1
/* 0D7348 8031C348 03387025 */ or $t6, $t9, $t8
/* 0D734C 8031C34C AC4F0000 */ sw $t7, ($v0)
/* 0D7350 8031C350 8D990014 */ lw $t9, 0x14($t4)
/* 0D7354 8031C354 01C0C025 */ move $t8, $t6
/* 0D7358 8031C358 330AFFFF */ andi $t2, $t8, 0xffff
/* 0D735C 8031C35C 330EFFFF */ andi $t6, $t8, 0xffff
/* 0D7360 8031C360 032EC021 */ addu $t8, $t9, $t6
/* 0D7364 8031C364 1000FF8B */ b .L8031C194
/* 0D7368 8031C368 AC580000 */ sw $t8, ($v0)
glabel L8031C36C
/* 0D736C 8031C36C 26020054 */ addiu $v0, $s0, 0x54
/* 0D7370 8031C370 8C430000 */ lw $v1, ($v0)
/* 0D7374 8031C374 240100C1 */ li $at, 193
/* 0D7378 8031C378 90640000 */ lbu $a0, ($v1)
/* 0D737C 8031C37C 246F0001 */ addiu $t7, $v1, 1
/* 0D7380 8031C380 14A10008 */ bne $a1, $at, .L8031C3A4
/* 0D7384 8031C384 AC4F0000 */ sw $t7, ($v0)
/* 0D7388 8031C388 00840019 */ multu $a0, $a0
/* 0D738C 8031C38C 0000C812 */ mflo $t9
/* 0D7390 8031C390 44992000 */ mtc1 $t9, $f4
/* 0D7394 8031C394 00000000 */ nop
/* 0D7398 8031C398 468021A0 */ cvt.s.w $f6, $f4
/* 0D739C 8031C39C 1000FF7D */ b .L8031C194
/* 0D73A0 8031C3A0 E6060024 */ swc1 $f6, 0x24($s0)
.L8031C3A4:
/* 0D73A4 8031C3A4 44844000 */ mtc1 $a0, $f8
/* 0D73A8 8031C3A8 00000000 */ nop
/* 0D73AC 8031C3AC 468042A0 */ cvt.s.w $f10, $f8
/* 0D73B0 8031C3B0 46005402 */ mul.s $f16, $f10, $f0
/* 0D73B4 8031C3B4 1000FF77 */ b .L8031C194
/* 0D73B8 8031C3B8 E6100028 */ swc1 $f16, 0x28($s0)
glabel L8031C3BC
/* 0D73BC 8031C3BC 26020054 */ addiu $v0, $s0, 0x54
/* 0D73C0 8031C3C0 8C430000 */ lw $v1, ($v0)
/* 0D73C4 8031C3C4 240100C9 */ li $at, 201
/* 0D73C8 8031C3C8 90640000 */ lbu $a0, ($v1)
/* 0D73CC 8031C3CC 246E0001 */ addiu $t6, $v1, 1
/* 0D73D0 8031C3D0 14A10003 */ bne $a1, $at, .L8031C3E0
/* 0D73D4 8031C3D4 AC4E0000 */ sw $t6, ($v0)
/* 0D73D8 8031C3D8 1000FF6E */ b .L8031C194
/* 0D73DC 8031C3DC A2040002 */ sb $a0, 2($s0)
.L8031C3E0:
/* 0D73E0 8031C3E0 1000FF6C */ b .L8031C194
/* 0D73E4 8031C3E4 A604001E */ sh $a0, 0x1e($s0)
glabel L8031C3E8
/* 0D73E8 8031C3E8 240100C4 */ li $at, 196
/* 0D73EC 8031C3EC 14A10003 */ bne $a1, $at, .L8031C3FC
/* 0D73F0 8031C3F0 02002025 */ move $a0, $s0
/* 0D73F4 8031C3F4 10000002 */ b .L8031C400
/* 0D73F8 8031C3F8 24020001 */ li $v0, 1
.L8031C3FC:
/* 0D73FC 8031C3FC 00001025 */ move $v0, $zero
.L8031C400:
/* 0D7400 8031C400 920E0000 */ lbu $t6, ($s0)
/* 0D7404 8031C404 00027900 */ sll $t7, $v0, 4
/* 0D7408 8031C408 31F90010 */ andi $t9, $t7, 0x10
/* 0D740C 8031C40C 31D8FFEF */ andi $t8, $t6, 0xffef
/* 0D7410 8031C410 03387825 */ or $t7, $t9, $t8
/* 0D7414 8031C414 A20F0000 */ sb $t7, ($s0)
/* 0D7418 8031C418 AFAD0058 */ sw $t5, 0x58($sp)
/* 0D741C 8031C41C AFAC005C */ sw $t4, 0x5c($sp)
/* 0D7420 8031C420 0C0C67D9 */ jal seq_channel_layer_note_decay
/* 0D7424 8031C424 A7AA003A */ sh $t2, 0x3a($sp)
/* 0D7428 8031C428 3C013C00 */ li $at, 0x3C000000 # 0.007812
/* 0D742C 8031C42C 44810000 */ mtc1 $at, $f0
/* 0D7430 8031C430 3C0B8022 */ lui $t3, %hi(gBankLoadedPool) # $t3, 0x8022
/* 0D7434 8031C434 3C1F8022 */ lui $ra, %hi(gCtlEntries) # $ra, 0x8022
/* 0D7438 8031C438 27FF6B60 */ addiu $ra, %lo(gCtlEntries) # addiu $ra, $ra, 0x6b60
/* 0D743C 8031C43C 256B10F8 */ addiu $t3, %lo(gBankLoadedPool) # addiu $t3, $t3, 0x10f8
/* 0D7440 8031C440 240900FF */ li $t1, 255
/* 0D7444 8031C444 97AA003A */ lhu $t2, 0x3a($sp)
/* 0D7448 8031C448 8FAC005C */ lw $t4, 0x5c($sp)
/* 0D744C 8031C44C 1000FF51 */ b .L8031C194
/* 0D7450 8031C450 8FAD0058 */ lw $t5, 0x58($sp)
glabel L8031C454
/* 0D7454 8031C454 26020054 */ addiu $v0, $s0, 0x54
/* 0D7458 8031C458 8C430000 */ lw $v1, ($v0)
/* 0D745C 8031C45C 90640000 */ lbu $a0, ($v1)
/* 0D7460 8031C460 246E0001 */ addiu $t6, $v1, 1
/* 0D7464 8031C464 AC4E0000 */ sw $t6, ($v0)
/* 0D7468 8031C468 30990080 */ andi $t9, $a0, 0x80
/* 0D746C 8031C46C 1320000A */ beqz $t9, .L8031C498
/* 0D7470 8031C470 00802825 */ move $a1, $a0
/* 0D7474 8031C474 01C01825 */ move $v1, $t6
/* 0D7478 8031C478 91CE0000 */ lbu $t6, ($t6)
/* 0D747C 8031C47C 00052200 */ sll $a0, $a1, 8
/* 0D7480 8031C480 308F7F00 */ andi $t7, $a0, 0x7f00
/* 0D7484 8031C484 01CF2025 */ or $a0, $t6, $t7
/* 0D7488 8031C488 3085FFFF */ andi $a1, $a0, 0xffff
/* 0D748C 8031C48C 24780001 */ addiu $t8, $v1, 1
/* 0D7490 8031C490 AC580000 */ sw $t8, ($v0)
/* 0D7494 8031C494 00A02025 */ move $a0, $a1
.L8031C498:
/* 0D7498 8031C498 308AFFFF */ andi $t2, $a0, 0xffff
/* 0D749C 8031C49C 1000FF3D */ b .L8031C194
/* 0D74A0 8031C4A0 A6050038 */ sh $a1, 0x38($s0)
glabel L8031C4A4
/* 0D74A4 8031C4A4 26020054 */ addiu $v0, $s0, 0x54
/* 0D74A8 8031C4A8 8C430000 */ lw $v1, ($v0)
/* 0D74AC 8031C4AC 246F0001 */ addiu $t7, $v1, 1
/* 0D74B0 8031C4B0 AC4F0000 */ sw $t7, ($v0)
/* 0D74B4 8031C4B4 90650000 */ lbu $a1, ($v1)
/* 0D74B8 8031C4B8 28A1007F */ slti $at, $a1, 0x7f
/* 0D74BC 8031C4BC 5020FF36 */ beql $at, $zero, .L8031C198
/* 0D74C0 8031C4C0 8E020054 */ lw $v0, 0x54($s0)
/* 0D74C4 8031C4C4 91B90005 */ lbu $t9, 5($t5)
/* 0D74C8 8031C4C8 8FEE0000 */ lw $t6, ($ra)
/* 0D74CC 8031C4CC 30A200FF */ andi $v0, $a1, 0xff
/* 0D74D0 8031C4D0 0019C080 */ sll $t8, $t9, 2
/* 0D74D4 8031C4D4 0319C023 */ subu $t8, $t8, $t9
/* 0D74D8 8031C4D8 0018C080 */ sll $t8, $t8, 2
/* 0D74DC 8031C4DC 01D83821 */ addu $a3, $t6, $t8
/* 0D74E0 8031C4E0 90E30001 */ lbu $v1, 1($a3)
/* 0D74E4 8031C4E4 00A3082A */ slt $at, $a1, $v1
/* 0D74E8 8031C4E8 54200008 */ bnezl $at, .L8031C50C
/* 0D74EC 8031C4EC 8CE30004 */ lw $v1, 4($a3)
/* 0D74F0 8031C4F0 306200FF */ andi $v0, $v1, 0xff
/* 0D74F4 8031C4F4 5040FF28 */ beql $v0, $zero, .L8031C198
/* 0D74F8 8031C4F8 8E020054 */ lw $v0, 0x54($s0)
/* 0D74FC 8031C4FC 2442FFFF */ addiu $v0, $v0, -1
/* 0D7500 8031C500 304F00FF */ andi $t7, $v0, 0xff
/* 0D7504 8031C504 01E01025 */ move $v0, $t7
/* 0D7508 8031C508 8CE30004 */ lw $v1, 4($a3)
.L8031C50C:
/* 0D750C 8031C50C 0002C880 */ sll $t9, $v0, 2
/* 0D7510 8031C510 26050048 */ addiu $a1, $s0, 0x48
/* 0D7514 8031C514 00797021 */ addu $t6, $v1, $t9
/* 0D7518 8031C518 8DC40000 */ lw $a0, ($t6)
/* 0D751C 8031C51C 5480000C */ bnezl $a0, .L8031C550
/* 0D7520 8031C520 8D630004 */ lw $v1, 4($t3)
/* 0D7524 8031C524 11220009 */ beq $t1, $v0, .L8031C54C
.L8031C528:
/* 0D7528 8031C528 0002C080 */ sll $t8, $v0, 2
/* 0D752C 8031C52C 00787821 */ addu $t7, $v1, $t8
/* 0D7530 8031C530 8DE40000 */ lw $a0, ($t7)
/* 0D7534 8031C534 54800006 */ bnezl $a0, .L8031C550
/* 0D7538 8031C538 8D630004 */ lw $v1, 4($t3)
/* 0D753C 8031C53C 2442FFFF */ addiu $v0, $v0, -1
/* 0D7540 8031C540 305900FF */ andi $t9, $v0, 0xff
/* 0D7544 8031C544 1539FFF8 */ bne $t1, $t9, .L8031C528
/* 0D7548 8031C548 03201025 */ move $v0, $t9
.L8031C54C:
/* 0D754C 8031C54C 8D630004 */ lw $v1, 4($t3)
.L8031C550:
/* 0D7550 8031C550 0083082B */ sltu $at, $a0, $v1
/* 0D7554 8031C554 54200007 */ bnezl $at, .L8031C574
/* 0D7558 8031C558 8D630198 */ lw $v1, 0x198($t3)
/* 0D755C 8031C55C 8D6E000C */ lw $t6, 0xc($t3)
/* 0D7560 8031C560 006EC021 */ addu $t8, $v1, $t6
/* 0D7564 8031C564 0304082B */ sltu $at, $t8, $a0
/* 0D7568 8031C568 5020000B */ beql $at, $zero, .L8031C598
/* 0D756C 8031C56C 8C8E0004 */ lw $t6, 4($a0)
/* 0D7570 8031C570 8D630198 */ lw $v1, 0x198($t3)
.L8031C574:
/* 0D7574 8031C574 0083082B */ sltu $at, $a0, $v1
/* 0D7578 8031C578 5420000E */ bnezl $at, .L8031C5B4
/* 0D757C 8031C57C 3C010002 */ lui $at, 2
/* 0D7580 8031C580 8D6F01A0 */ lw $t7, 0x1a0($t3)
/* 0D7584 8031C584 006FC821 */ addu $t9, $v1, $t7
/* 0D7588 8031C588 0324082B */ sltu $at, $t9, $a0
/* 0D758C 8031C58C 54200009 */ bnezl $at, .L8031C5B4
/* 0D7590 8031C590 3C010002 */ lui $at, 2
/* 0D7594 8031C594 8C8E0004 */ lw $t6, 4($a0)
.L8031C598:
/* 0D7598 8031C598 26020014 */ addiu $v0, $s0, 0x14
/* 0D759C 8031C59C AC4E0004 */ sw $t6, 4($v0)
/* 0D75A0 8031C5A0 90980003 */ lbu $t8, 3($a0)
/* 0D75A4 8031C5A4 A0580000 */ sb $t8, ($v0)
/* 0D75A8 8031C5A8 1000FEFA */ b .L8031C194
/* 0D75AC 8031C5AC ACA40000 */ sw $a0, ($a1)
/* 0D75B0 8031C5B0 3C010002 */ lui $at, 2
.L8031C5B4:
/* 0D75B4 8031C5B4 00417821 */ addu $t7, $v0, $at
/* 0D75B8 8031C5B8 3C018033 */ lui $at, %hi(gAudioErrorFlags) # $at, 0x8033
/* 0D75BC 8031C5BC AC2F2E50 */ sw $t7, %lo(gAudioErrorFlags)($at)
/* 0D75C0 8031C5C0 1000FEF4 */ b .L8031C194
/* 0D75C4 8031C5C4 ACA00000 */ sw $zero, ($a1)
glabel L8031C5C8
/* 0D75C8 8031C5C8 26020054 */ addiu $v0, $s0, 0x54
/* 0D75CC 8031C5CC 8C430000 */ lw $v1, ($v0)
/* 0D75D0 8031C5D0 24790001 */ addiu $t9, $v1, 1
/* 0D75D4 8031C5D4 AC590000 */ sw $t9, ($v0)
/* 0D75D8 8031C5D8 90650000 */ lbu $a1, ($v1)
/* 0D75DC 8031C5DC A2050004 */ sb $a1, 4($s0)
/* 0D75E0 8031C5E0 8C430000 */ lw $v1, ($v0)
/* 0D75E4 8031C5E4 246E0001 */ addiu $t6, $v1, 1
/* 0D75E8 8031C5E8 AC4E0000 */ sw $t6, ($v0)
/* 0D75EC 8031C5EC 85B8001A */ lh $t8, 0x1a($t5)
/* 0D75F0 8031C5F0 90670000 */ lbu $a3, ($v1)
/* 0D75F4 8031C5F4 8619001E */ lh $t9, 0x1e($s0)
/* 0D75F8 8031C5F8 03077821 */ addu $t7, $t8, $a3
/* 0D75FC 8031C5FC 85980010 */ lh $t8, 0x10($t4)
/* 0D7600 8031C600 01F97021 */ addu $t6, $t7, $t9
/* 0D7604 8031C604 01D84021 */ addu $t0, $t6, $t8
/* 0D7608 8031C608 310F00FF */ andi $t7, $t0, 0xff
/* 0D760C 8031C60C 29E10080 */ slti $at, $t7, 0x80
/* 0D7610 8031C610 14200002 */ bnez $at, .L8031C61C
/* 0D7614 8031C614 01E04025 */ move $t0, $t7
/* 0D7618 8031C618 00004025 */ move $t0, $zero
.L8031C61C:
/* 0D761C 8031C61C 92190004 */ lbu $t9, 4($s0)
/* 0D7620 8031C620 A2080003 */ sb $t0, 3($s0)
/* 0D7624 8031C624 332E0080 */ andi $t6, $t9, 0x80
/* 0D7628 8031C628 51C00009 */ beql $t6, $zero, .L8031C650
/* 0D762C 8031C62C 8C430000 */ lw $v1, ($v0)
/* 0D7630 8031C630 8C580000 */ lw $t8, ($v0)
/* 0D7634 8031C634 930F0000 */ lbu $t7, ($t8)
/* 0D7638 8031C638 A60F001C */ sh $t7, 0x1c($s0)
/* 0D763C 8031C63C 8C590000 */ lw $t9, ($v0)
/* 0D7640 8031C640 272E0001 */ addiu $t6, $t9, 1
/* 0D7644 8031C644 1000FED3 */ b .L8031C194
/* 0D7648 8031C648 AC4E0000 */ sw $t6, ($v0)
/* 0D764C 8031C64C 8C430000 */ lw $v1, ($v0)
.L8031C650:
/* 0D7650 8031C650 90640000 */ lbu $a0, ($v1)
/* 0D7654 8031C654 24780001 */ addiu $t8, $v1, 1
/* 0D7658 8031C658 AC580000 */ sw $t8, ($v0)
/* 0D765C 8031C65C 308F0080 */ andi $t7, $a0, 0x80
/* 0D7660 8031C660 11E0000A */ beqz $t7, .L8031C68C
/* 0D7664 8031C664 00802825 */ move $a1, $a0
/* 0D7668 8031C668 03001825 */ move $v1, $t8
/* 0D766C 8031C66C 93180000 */ lbu $t8, ($t8)
/* 0D7670 8031C670 00052200 */ sll $a0, $a1, 8
/* 0D7674 8031C674 308E7F00 */ andi $t6, $a0, 0x7f00
/* 0D7678 8031C678 030E2025 */ or $a0, $t8, $t6
/* 0D767C 8031C67C 308FFFFF */ andi $t7, $a0, 0xffff
/* 0D7680 8031C680 24790001 */ addiu $t9, $v1, 1
/* 0D7684 8031C684 AC590000 */ sw $t9, ($v0)
/* 0D7688 8031C688 01E02025 */ move $a0, $t7
.L8031C68C:
/* 0D768C 8031C68C 308AFFFF */ andi $t2, $a0, 0xffff
/* 0D7690 8031C690 1000FEC0 */ b .L8031C194
/* 0D7694 8031C694 A604001C */ sh $a0, 0x1c($s0)
glabel L8031C698
/* 0D7698 8031C698 1000FEBE */ b .L8031C194
/* 0D769C 8031C69C A2000004 */ sb $zero, 4($s0)
glabel L8031C6A0
.L8031C6A0:
/* 0D76A0 8031C6A0 30A200F0 */ andi $v0, $a1, 0xf0
/* 0D76A4 8031C6A4 240100D0 */ li $at, 208
/* 0D76A8 8031C6A8 10410005 */ beq $v0, $at, .L8031C6C0
/* 0D76AC 8031C6AC 240100E0 */ li $at, 224
/* 0D76B0 8031C6B0 5041000F */ beql $v0, $at, .L8031C6F0
/* 0D76B4 8031C6B4 8D8E008C */ lw $t6, 0x8c($t4)
/* 0D76B8 8031C6B8 1000FEB7 */ b .L8031C198
/* 0D76BC 8031C6BC 8E020054 */ lw $v0, 0x54($s0)
.L8031C6C0:
/* 0D76C0 8031C6C0 8D8E0088 */ lw $t6, 0x88($t4)
/* 0D76C4 8031C6C4 30B8000F */ andi $t8, $a1, 0xf
/* 0D76C8 8031C6C8 01D87821 */ addu $t7, $t6, $t8
/* 0D76CC 8031C6CC 91EA0000 */ lbu $t2, ($t7)
/* 0D76D0 8031C6D0 014A0019 */ multu $t2, $t2
/* 0D76D4 8031C6D4 0000C812 */ mflo $t9
/* 0D76D8 8031C6D8 44999000 */ mtc1 $t9, $f18
/* 0D76DC 8031C6DC 00000000 */ nop
/* 0D76E0 8031C6E0 46809120 */ cvt.s.w $f4, $f18
/* 0D76E4 8031C6E4 1000FEAB */ b .L8031C194
/* 0D76E8 8031C6E8 E6040024 */ swc1 $f4, 0x24($s0)
/* 0D76EC 8031C6EC 8D8E008C */ lw $t6, 0x8c($t4)
.L8031C6F0:
/* 0D76F0 8031C6F0 30B8000F */ andi $t8, $a1, 0xf
/* 0D76F4 8031C6F4 01D87821 */ addu $t7, $t6, $t8
/* 0D76F8 8031C6F8 91F90000 */ lbu $t9, ($t7)
/* 0D76FC 8031C6FC 1000FEA5 */ b .L8031C194
/* 0D7700 8031C700 A2190002 */ sb $t9, 2($s0)
.L8031C704:
/* 0D7704 8031C704 240100C0 */ li $at, 192
/* 0D7708 8031C708 14A10015 */ bne $a1, $at, .L8031C760
/* 0D770C 8031C70C 26020054 */ addiu $v0, $s0, 0x54
/* 0D7710 8031C710 8C430000 */ lw $v1, ($v0)
/* 0D7714 8031C714 90640000 */ lbu $a0, ($v1)
/* 0D7718 8031C718 246E0001 */ addiu $t6, $v1, 1
/* 0D771C 8031C71C AC4E0000 */ sw $t6, ($v0)
/* 0D7720 8031C720 30980080 */ andi $t8, $a0, 0x80
/* 0D7724 8031C724 13000009 */ beqz $t8, .L8031C74C
/* 0D7728 8031C728 00802825 */ move $a1, $a0
/* 0D772C 8031C72C 01C01825 */ move $v1, $t6
/* 0D7730 8031C730 91CE0000 */ lbu $t6, ($t6)
/* 0D7734 8031C734 00042200 */ sll $a0, $a0, 8
/* 0D7738 8031C738 30997F00 */ andi $t9, $a0, 0x7f00
/* 0D773C 8031C73C 246F0001 */ addiu $t7, $v1, 1
/* 0D7740 8031C740 01D92025 */ or $a0, $t6, $t9
/* 0D7744 8031C744 3085FFFF */ andi $a1, $a0, 0xffff
/* 0D7748 8031C748 AC4F0000 */ sw $t7, ($v0)
.L8031C74C:
/* 0D774C 8031C74C 920E0000 */ lbu $t6, ($s0)
/* 0D7750 8031C750 A605003C */ sh $a1, 0x3c($s0)
/* 0D7754 8031C754 35D80020 */ ori $t8, $t6, 0x20
/* 0D7758 8031C758 10000181 */ b .L8031CD60
/* 0D775C 8031C75C A2180000 */ sb $t8, ($s0)
.L8031C760:
/* 0D7760 8031C760 920F0000 */ lbu $t7, ($s0)
/* 0D7764 8031C764 24010001 */ li $at, 1
/* 0D7768 8031C768 30A900C0 */ andi $t1, $a1, 0xc0
/* 0D776C 8031C76C 31F9FFDF */ andi $t9, $t7, 0xffdf
/* 0D7770 8031C770 A2190000 */ sb $t9, ($s0)
/* 0D7774 8031C774 8DAE0000 */ lw $t6, ($t5)
/* 0D7778 8031C778 000EC180 */ sll $t8, $t6, 6
/* 0D777C 8031C77C 00187FC2 */ srl $t7, $t8, 0x1f
/* 0D7780 8031C780 15E10057 */ bne $t7, $at, .L8031C8E0
/* 0D7784 8031C784 00000000 */ nop
/* 0D7788 8031C788 30A900C0 */ andi $t1, $a1, 0xc0
/* 0D778C 8031C78C 11200009 */ beqz $t1, .L8031C7B4
/* 0D7790 8031C790 26020054 */ addiu $v0, $s0, 0x54
/* 0D7794 8031C794 24010040 */ li $at, 64
/* 0D7798 8031C798 11210023 */ beq $t1, $at, .L8031C828
/* 0D779C 8031C79C 26020054 */ addiu $v0, $s0, 0x54
/* 0D77A0 8031C7A0 24010080 */ li $at, 128
/* 0D77A4 8031C7A4 11210039 */ beq $t1, $at, .L8031C88C
/* 0D77A8 8031C7A8 26020054 */ addiu $v0, $s0, 0x54
/* 0D77AC 8031C7AC 10000043 */ b .L8031C8BC
/* 0D77B0 8031C7B0 01402025 */ move $a0, $t2
.L8031C7B4:
/* 0D77B4 8031C7B4 8C430000 */ lw $v1, ($v0)
/* 0D77B8 8031C7B8 90660000 */ lbu $a2, ($v1)
/* 0D77BC 8031C7BC 24790001 */ addiu $t9, $v1, 1
/* 0D77C0 8031C7C0 AC590000 */ sw $t9, ($v0)
/* 0D77C4 8031C7C4 30CE0080 */ andi $t6, $a2, 0x80
/* 0D77C8 8031C7C8 11C0000A */ beqz $t6, .L8031C7F4
/* 0D77CC 8031C7CC 00C03825 */ move $a3, $a2
/* 0D77D0 8031C7D0 03201825 */ move $v1, $t9
/* 0D77D4 8031C7D4 93390000 */ lbu $t9, ($t9)
/* 0D77D8 8031C7D8 00073200 */ sll $a2, $a3, 8
/* 0D77DC 8031C7DC 30CF7F00 */ andi $t7, $a2, 0x7f00
/* 0D77E0 8031C7E0 032F3025 */ or $a2, $t9, $t7
/* 0D77E4 8031C7E4 30C7FFFF */ andi $a3, $a2, 0xffff
/* 0D77E8 8031C7E8 24780001 */ addiu $t8, $v1, 1
/* 0D77EC 8031C7EC AC580000 */ sw $t8, ($v0)
/* 0D77F0 8031C7F0 00E03025 */ move $a2, $a3
.L8031C7F4:
/* 0D77F4 8031C7F4 8C430000 */ lw $v1, ($v0)
/* 0D77F8 8031C7F8 30CAFFFF */ andi $t2, $a2, 0xffff
/* 0D77FC 8031C7FC 01402025 */ move $a0, $t2
/* 0D7800 8031C800 906B0000 */ lbu $t3, ($v1)
/* 0D7804 8031C804 246F0001 */ addiu $t7, $v1, 1
/* 0D7808 8031C808 AC4F0000 */ sw $t7, ($v0)
/* 0D780C 8031C80C 91EE0000 */ lbu $t6, ($t7)
/* 0D7810 8031C810 A20E0002 */ sb $t6, 2($s0)
/* 0D7814 8031C814 8C580000 */ lw $t8, ($v0)
/* 0D7818 8031C818 270F0001 */ addiu $t7, $t8, 1
/* 0D781C 8031C81C AC4F0000 */ sw $t7, ($v0)
/* 0D7820 8031C820 10000027 */ b .L8031C8C0
/* 0D7824 8031C824 A607003A */ sh $a3, 0x3a($s0)
.L8031C828:
/* 0D7828 8031C828 8C430000 */ lw $v1, ($v0)
/* 0D782C 8031C82C 90660000 */ lbu $a2, ($v1)
/* 0D7830 8031C830 24790001 */ addiu $t9, $v1, 1
/* 0D7834 8031C834 AC590000 */ sw $t9, ($v0)
/* 0D7838 8031C838 30CE0080 */ andi $t6, $a2, 0x80
/* 0D783C 8031C83C 11C0000A */ beqz $t6, .L8031C868
/* 0D7840 8031C840 00C03825 */ move $a3, $a2
/* 0D7844 8031C844 03201825 */ move $v1, $t9
/* 0D7848 8031C848 93390000 */ lbu $t9, ($t9)
/* 0D784C 8031C84C 00073200 */ sll $a2, $a3, 8
/* 0D7850 8031C850 30CF7F00 */ andi $t7, $a2, 0x7f00
/* 0D7854 8031C854 032F3025 */ or $a2, $t9, $t7
/* 0D7858 8031C858 30C7FFFF */ andi $a3, $a2, 0xffff
/* 0D785C 8031C85C 24780001 */ addiu $t8, $v1, 1
/* 0D7860 8031C860 AC580000 */ sw $t8, ($v0)
/* 0D7864 8031C864 00E03025 */ move $a2, $a3
.L8031C868:
/* 0D7868 8031C868 8C430000 */ lw $v1, ($v0)
/* 0D786C 8031C86C 30CAFFFF */ andi $t2, $a2, 0xffff
/* 0D7870 8031C870 01402025 */ move $a0, $t2
/* 0D7874 8031C874 906B0000 */ lbu $t3, ($v1)
/* 0D7878 8031C878 246F0001 */ addiu $t7, $v1, 1
/* 0D787C 8031C87C AC4F0000 */ sw $t7, ($v0)
/* 0D7880 8031C880 A2000002 */ sb $zero, 2($s0)
/* 0D7884 8031C884 1000000E */ b .L8031C8C0
/* 0D7888 8031C888 A607003A */ sh $a3, 0x3a($s0)
.L8031C88C:
/* 0D788C 8031C88C 8C430000 */ lw $v1, ($v0)
/* 0D7890 8031C890 960A003A */ lhu $t2, 0x3a($s0)
/* 0D7894 8031C894 906B0000 */ lbu $t3, ($v1)
/* 0D7898 8031C898 24790001 */ addiu $t9, $v1, 1
/* 0D789C 8031C89C AC590000 */ sw $t9, ($v0)
/* 0D78A0 8031C8A0 93380000 */ lbu $t8, ($t9)
/* 0D78A4 8031C8A4 01402025 */ move $a0, $t2
/* 0D78A8 8031C8A8 A2180002 */ sb $t8, 2($s0)
/* 0D78AC 8031C8AC 8C4F0000 */ lw $t7, ($v0)
/* 0D78B0 8031C8B0 25F90001 */ addiu $t9, $t7, 1
/* 0D78B4 8031C8B4 10000002 */ b .L8031C8C0
/* 0D78B8 8031C8B8 AC590000 */ sw $t9, ($v0)
.L8031C8BC:
/* 0D78BC 8031C8BC 8FAB0030 */ lw $t3, 0x30($sp)
.L8031C8C0:
/* 0D78C0 8031C8C0 016B0019 */ multu $t3, $t3
/* 0D78C4 8031C8C4 00A91823 */ subu $v1, $a1, $t1
/* 0D78C8 8031C8C8 00007012 */ mflo $t6
/* 0D78CC 8031C8CC 448E3000 */ mtc1 $t6, $f6
/* 0D78D0 8031C8D0 00000000 */ nop
/* 0D78D4 8031C8D4 46803220 */ cvt.s.w $f8, $f6
/* 0D78D8 8031C8D8 10000024 */ b .L8031C96C
/* 0D78DC 8031C8DC E6080024 */ swc1 $f8, 0x24($s0)
.L8031C8E0:
/* 0D78E0 8031C8E0 11200008 */ beqz $t1, .L8031C904
/* 0D78E4 8031C8E4 26020054 */ addiu $v0, $s0, 0x54
/* 0D78E8 8031C8E8 24010040 */ li $at, 64
/* 0D78EC 8031C8EC 11210019 */ beq $t1, $at, .L8031C954
/* 0D78F0 8031C8F0 24010080 */ li $at, 128
/* 0D78F4 8031C8F4 5121001B */ beql $t1, $at, .L8031C964
/* 0D78F8 8031C8F8 960A003A */ lhu $t2, 0x3a($s0)
/* 0D78FC 8031C8FC 1000001A */ b .L8031C968
/* 0D7900 8031C900 01402025 */ move $a0, $t2
.L8031C904:
/* 0D7904 8031C904 8C430000 */ lw $v1, ($v0)
/* 0D7908 8031C908 90660000 */ lbu $a2, ($v1)
/* 0D790C 8031C90C 24780001 */ addiu $t8, $v1, 1
/* 0D7910 8031C910 AC580000 */ sw $t8, ($v0)
/* 0D7914 8031C914 30CF0080 */ andi $t7, $a2, 0x80
/* 0D7918 8031C918 11E0000A */ beqz $t7, .L8031C944
/* 0D791C 8031C91C 00C03825 */ move $a3, $a2
/* 0D7920 8031C920 03001825 */ move $v1, $t8
/* 0D7924 8031C924 93180000 */ lbu $t8, ($t8)
/* 0D7928 8031C928 00073200 */ sll $a2, $a3, 8
/* 0D792C 8031C92C 30CE7F00 */ andi $t6, $a2, 0x7f00
/* 0D7930 8031C930 030E3025 */ or $a2, $t8, $t6
/* 0D7934 8031C934 30C7FFFF */ andi $a3, $a2, 0xffff
/* 0D7938 8031C938 24790001 */ addiu $t9, $v1, 1
/* 0D793C 8031C93C AC590000 */ sw $t9, ($v0)
/* 0D7940 8031C940 00E03025 */ move $a2, $a3
.L8031C944:
/* 0D7944 8031C944 30CAFFFF */ andi $t2, $a2, 0xffff
/* 0D7948 8031C948 A607003A */ sh $a3, 0x3a($s0)
/* 0D794C 8031C94C 10000006 */ b .L8031C968
/* 0D7950 8031C950 01402025 */ move $a0, $t2
.L8031C954:
/* 0D7954 8031C954 960A0038 */ lhu $t2, 0x38($s0)
/* 0D7958 8031C958 10000003 */ b .L8031C968
/* 0D795C 8031C95C 01402025 */ move $a0, $t2
/* 0D7960 8031C960 960A003A */ lhu $t2, 0x3a($s0)
.L8031C964:
/* 0D7964 8031C964 01402025 */ move $a0, $t2
.L8031C968:
/* 0D7968 8031C968 00A91823 */ subu $v1, $a1, $t1
.L8031C96C:
/* 0D796C 8031C96C 920E0002 */ lbu $t6, 2($s0)
/* 0D7970 8031C970 A604003C */ sh $a0, 0x3c($s0)
/* 0D7974 8031C974 01C40019 */ multu $t6, $a0
/* 0D7978 8031C978 0000C012 */ mflo $t8
/* 0D797C 8031C97C 07010003 */ bgez $t8, .L8031C98C
/* 0D7980 8031C980 00187A03 */ sra $t7, $t8, 8
/* 0D7984 8031C984 270100FF */ addiu $at, $t8, 0xff
/* 0D7988 8031C988 00017A03 */ sra $t7, $at, 8
.L8031C98C:
/* 0D798C 8031C98C A60F003E */ sh $t7, 0x3e($s0)
/* 0D7990 8031C990 8D990000 */ lw $t9, ($t4)
/* 0D7994 8031C994 0019C080 */ sll $t8, $t9, 2
/* 0D7998 8031C998 07030006 */ bgezl $t8, .L8031C9B4
/* 0D799C 8031C99C 8DA20000 */ lw $v0, ($t5)
/* 0D79A0 8031C9A0 91AF0002 */ lbu $t7, 2($t5)
/* 0D79A4 8031C9A4 31F90040 */ andi $t9, $t7, 0x40
/* 0D79A8 8031C9A8 57200008 */ bnezl $t9, .L8031C9CC
/* 0D79AC 8031C9AC 92180000 */ lbu $t8, ($s0)
/* 0D79B0 8031C9B0 8DA20000 */ lw $v0, ($t5)
.L8031C9B4:
/* 0D79B4 8031C9B4 0002C0C0 */ sll $t8, $v0, 3
/* 0D79B8 8031C9B8 07000003 */ bltz $t8, .L8031C9C8
/* 0D79BC 8031C9BC 0002C900 */ sll $t9, $v0, 4
/* 0D79C0 8031C9C0 07220006 */ bltzl $t9, .L8031C9DC
/* 0D79C4 8031C9C4 85B90018 */ lh $t9, 0x18($t5)
.L8031C9C8:
/* 0D79C8 8031C9C8 92180000 */ lbu $t8, ($s0)
.L8031C9CC:
/* 0D79CC 8031C9CC 370F0020 */ ori $t7, $t8, 0x20
/* 0D79D0 8031C9D0 100000E3 */ b .L8031CD60
/* 0D79D4 8031C9D4 A20F0000 */ sb $t7, ($s0)
/* 0D79D8 8031C9D8 85B90018 */ lh $t9, 0x18($t5)
.L8031C9DC:
/* 0D79DC 8031C9DC 57200035 */ bnezl $t9, .L8031CAB4
/* 0D79E0 8031C9E0 85980010 */ lh $t8, 0x10($t4)
/* 0D79E4 8031C9E4 85B8001A */ lh $t8, 0x1a($t5)
/* 0D79E8 8031C9E8 8619001E */ lh $t9, 0x1e($s0)
/* 0D79EC 8031C9EC 00787821 */ addu $t7, $v1, $t8
/* 0D79F0 8031C9F0 01F94021 */ addu $t0, $t7, $t9
/* 0D79F4 8031C9F4 91AF0005 */ lbu $t7, 5($t5)
/* 0D79F8 8031C9F8 8FF80000 */ lw $t8, ($ra)
/* 0D79FC 8031C9FC 310E00FF */ andi $t6, $t0, 0xff
/* 0D7A00 8031CA00 000FC880 */ sll $t9, $t7, 2
/* 0D7A04 8031CA04 032FC823 */ subu $t9, $t9, $t7
/* 0D7A08 8031CA08 0019C880 */ sll $t9, $t9, 2
/* 0D7A0C 8031CA0C 03193821 */ addu $a3, $t8, $t9
/* 0D7A10 8031CA10 90E20002 */ lbu $v0, 2($a3)
/* 0D7A14 8031CA14 01C04025 */ move $t0, $t6
/* 0D7A18 8031CA18 01C2082A */ slt $at, $t6, $v0
/* 0D7A1C 8031CA1C 5420000C */ bnezl $at, .L8031CA50
/* 0D7A20 8031CA20 8CEE0008 */ lw $t6, 8($a3)
/* 0D7A24 8031CA24 304800FF */ andi $t0, $v0, 0xff
/* 0D7A28 8031CA28 55000006 */ bnezl $t0, .L8031CA44
/* 0D7A2C 8031CA2C 2508FFFF */ addiu $t0, $t0, -1
/* 0D7A30 8031CA30 920F0000 */ lbu $t7, ($s0)
/* 0D7A34 8031CA34 35F80020 */ ori $t8, $t7, 0x20
/* 0D7A38 8031CA38 100000C7 */ b .L8031CD58
/* 0D7A3C 8031CA3C A2180000 */ sb $t8, ($s0)
/* 0D7A40 8031CA40 2508FFFF */ addiu $t0, $t0, -1
.L8031CA44:
/* 0D7A44 8031CA44 311900FF */ andi $t9, $t0, 0xff
/* 0D7A48 8031CA48 03204025 */ move $t0, $t9
/* 0D7A4C 8031CA4C 8CEE0008 */ lw $t6, 8($a3)
.L8031CA50:
/* 0D7A50 8031CA50 00087880 */ sll $t7, $t0, 2
/* 0D7A54 8031CA54 01CFC021 */ addu $t8, $t6, $t7
/* 0D7A58 8031CA58 8F020000 */ lw $v0, ($t8)
/* 0D7A5C 8031CA5C 54400006 */ bnezl $v0, .L8031CA78
/* 0D7A60 8031CA60 8C58000C */ lw $t8, 0xc($v0)
/* 0D7A64 8031CA64 920E0000 */ lbu $t6, ($s0)
/* 0D7A68 8031CA68 35CF0020 */ ori $t7, $t6, 0x20
/* 0D7A6C 8031CA6C 100000BA */ b .L8031CD58
/* 0D7A70 8031CA70 A20F0000 */ sb $t7, ($s0)
/* 0D7A74 8031CA74 8C58000C */ lw $t8, 0xc($v0)
.L8031CA78:
/* 0D7A78 8031CA78 24430004 */ addiu $v1, $v0, 4
/* 0D7A7C 8031CA7C AE180018 */ sw $t8, 0x18($s0)
/* 0D7A80 8031CA80 90590000 */ lbu $t9, ($v0)
/* 0D7A84 8031CA84 A2190014 */ sb $t9, 0x14($s0)
/* 0D7A88 8031CA88 904E0001 */ lbu $t6, 1($v0)
/* 0D7A8C 8031CA8C AE03004C */ sw $v1, 0x4c($s0)
/* 0D7A90 8031CA90 448E5000 */ mtc1 $t6, $f10
/* 0D7A94 8031CA94 00000000 */ nop
/* 0D7A98 8031CA98 46805420 */ cvt.s.w $f16, $f10
/* 0D7A9C 8031CA9C 46008482 */ mul.s $f18, $f16, $f0
/* 0D7AA0 8031CAA0 E6120028 */ swc1 $f18, 0x28($s0)
/* 0D7AA4 8031CAA4 C4640004 */ lwc1 $f4, 4($v1)
/* 0D7AA8 8031CAA8 100000AB */ b .L8031CD58
/* 0D7AAC 8031CAAC E6040020 */ swc1 $f4, 0x20($s0)
/* 0D7AB0 8031CAB0 85980010 */ lh $t8, 0x10($t4)
.L8031CAB4:
/* 0D7AB4 8031CAB4 85AE001A */ lh $t6, 0x1a($t5)
/* 0D7AB8 8031CAB8 0078C821 */ addu $t9, $v1, $t8
/* 0D7ABC 8031CABC 8618001E */ lh $t8, 0x1e($s0)
/* 0D7AC0 8031CAC0 032E7821 */ addu $t7, $t9, $t6
/* 0D7AC4 8031CAC4 01F84021 */ addu $t0, $t7, $t8
/* 0D7AC8 8031CAC8 310200FF */ andi $v0, $t0, 0xff
/* 0D7ACC 8031CACC 28410080 */ slti $at, $v0, 0x80
/* 0D7AD0 8031CAD0 14200005 */ bnez $at, .L8031CAE8
/* 0D7AD4 8031CAD4 00404025 */ move $t0, $v0
/* 0D7AD8 8031CAD8 920F0000 */ lbu $t7, ($s0)
/* 0D7ADC 8031CADC 35F80020 */ ori $t8, $t7, 0x20
/* 0D7AE0 8031CAE0 1000009D */ b .L8031CD58
/* 0D7AE4 8031CAE4 A2180000 */ sb $t8, ($s0)
.L8031CAE8:
/* 0D7AE8 8031CAE8 8E030048 */ lw $v1, 0x48($s0)
/* 0D7AEC 8031CAEC 54600003 */ bnezl $v1, .L8031CAFC
/* 0D7AF0 8031CAF0 92190004 */ lbu $t9, 4($s0)
/* 0D7AF4 8031CAF4 8DA3003C */ lw $v1, 0x3c($t5)
/* 0D7AF8 8031CAF8 92190004 */ lbu $t9, 4($s0)
.L8031CAFC:
/* 0D7AFC 8031CAFC 13200073 */ beqz $t9, .L8031CCCC
/* 0D7B00 8031CB00 00000000 */ nop
/* 0D7B04 8031CB04 92040003 */ lbu $a0, 3($s0)
/* 0D7B08 8031CB08 0082082A */ slt $at, $a0, $v0
/* 0D7B0C 8031CB0C 10200003 */ beqz $at, .L8031CB1C
/* 0D7B10 8031CB10 00802825 */ move $a1, $a0
/* 0D7B14 8031CB14 10000001 */ b .L8031CB1C
/* 0D7B18 8031CB18 00402825 */ move $a1, $v0
.L8031CB1C:
/* 0D7B1C 8031CB1C 10600017 */ beqz $v1, .L8031CB7C
/* 0D7B20 8031CB20 3C013F80 */ li $at, 0x3F800000 # 1.000000
/* 0D7B24 8031CB24 906E0001 */ lbu $t6, 1($v1)
/* 0D7B28 8031CB28 30A200FF */ andi $v0, $a1, 0xff
/* 0D7B2C 8031CB2C 004E082A */ slt $at, $v0, $t6
/* 0D7B30 8031CB30 50200004 */ beql $at, $zero, .L8031CB44
/* 0D7B34 8031CB34 906F0002 */ lbu $t7, 2($v1)
/* 0D7B38 8031CB38 10000009 */ b .L8031CB60
/* 0D7B3C 8031CB3C 24620008 */ addiu $v0, $v1, 8
/* 0D7B40 8031CB40 906F0002 */ lbu $t7, 2($v1)
.L8031CB44:
/* 0D7B44 8031CB44 24640018 */ addiu $a0, $v1, 0x18
/* 0D7B48 8031CB48 01E2082A */ slt $at, $t7, $v0
/* 0D7B4C 8031CB4C 14200003 */ bnez $at, .L8031CB5C
/* 0D7B50 8031CB50 00000000 */ nop
/* 0D7B54 8031CB54 10000001 */ b .L8031CB5C
/* 0D7B58 8031CB58 24640010 */ addiu $a0, $v1, 0x10
.L8031CB5C:
/* 0D7B5C 8031CB5C 00801025 */ move $v0, $a0
.L8031CB60:
/* 0D7B60 8031CB60 8E18004C */ lw $t8, 0x4c($s0)
/* 0D7B64 8031CB64 0058C826 */ xor $t9, $v0, $t8
/* 0D7B68 8031CB68 2F390001 */ sltiu $t9, $t9, 1
/* 0D7B6C 8031CB6C A3B9003F */ sb $t9, 0x3f($sp)
/* 0D7B70 8031CB70 AE02004C */ sw $v0, 0x4c($s0)
/* 0D7B74 8031CB74 10000003 */ b .L8031CB84
/* 0D7B78 8031CB78 C4400004 */ lwc1 $f0, 4($v0)
.L8031CB7C:
/* 0D7B7C 8031CB7C 44810000 */ mtc1 $at, $f0
/* 0D7B80 8031CB80 AE00004C */ sw $zero, 0x4c($s0)
.L8031CB84:
/* 0D7B84 8031CB84 3C038033 */ lui $v1, %hi(gNoteFrequencies) # $v1, 0x8033
/* 0D7B88 8031CB88 24633994 */ addiu $v1, %lo(gNoteFrequencies) # addiu $v1, $v1, 0x3994
/* 0D7B8C 8031CB8C 00087080 */ sll $t6, $t0, 2
/* 0D7B90 8031CB90 92180003 */ lbu $t8, 3($s0)
/* 0D7B94 8031CB94 006E7821 */ addu $t7, $v1, $t6
/* 0D7B98 8031CB98 C5E60000 */ lwc1 $f6, ($t7)
/* 0D7B9C 8031CB9C 920F0004 */ lbu $t7, 4($s0)
/* 0D7BA0 8031CBA0 0018C880 */ sll $t9, $t8, 2
/* 0D7BA4 8031CBA4 00797021 */ addu $t6, $v1, $t9
/* 0D7BA8 8031CBA8 C5C80000 */ lwc1 $f8, ($t6)
/* 0D7BAC 8031CBAC 46003082 */ mul.s $f2, $f6, $f0
/* 0D7BB0 8031CBB0 2401FF7F */ li $at, -129
/* 0D7BB4 8031CBB4 01E1C024 */ and $t8, $t7, $at
/* 0D7BB8 8031CBB8 2719FFFF */ addiu $t9, $t8, -1
/* 0D7BBC 8031CBBC 2F210005 */ sltiu $at, $t9, 5
/* 0D7BC0 8031CBC0 46004302 */ mul.s $f12, $f8, $f0
/* 0D7BC4 8031CBC4 1020000C */ beqz $at, .L8031CBF8
/* 0D7BC8 8031CBC8 0019C880 */ sll $t9, $t9, 2
/* 0D7BCC 8031CBCC 3C018034 */ lui $at, %hi(jtbl_80337CDC)
/* 0D7BD0 8031CBD0 00390821 */ addu $at, $at, $t9
/* 0D7BD4 8031CBD4 8C398EAC */ lw $t9, %lo(jtbl_80337CDC)($at)
/* 0D7BD8 8031CBD8 03200008 */ jr $t9
/* 0D7BDC 8031CBDC 00000000 */ nop
glabel L8031CBE0
/* 0D7BE0 8031CBE0 E7A20024 */ swc1 $f2, 0x24($sp)
/* 0D7BE4 8031CBE4 10000005 */ b .L8031CBFC
/* 0D7BE8 8031CBE8 46006006 */ mov.s $f0, $f12
glabel L8031CBEC
/* 0D7BEC 8031CBEC 46001006 */ mov.s $f0, $f2
/* 0D7BF0 8031CBF0 10000002 */ b .L8031CBFC
/* 0D7BF4 8031CBF4 E7AC0024 */ swc1 $f12, 0x24($sp)
.L8031CBF8:
/* 0D7BF8 8031CBF8 C7A00028 */ lwc1 $f0, 0x28($sp)
.L8031CBFC:
/* 0D7BFC 8031CBFC C7AA0024 */ lwc1 $f10, 0x24($sp)
/* 0D7C00 8031CC00 3C013F80 */ li $at, 0x3F800000 # 1.000000
/* 0D7C04 8031CC04 44819000 */ mtc1 $at, $f18
/* 0D7C08 8031CC08 46005403 */ div.s $f16, $f10, $f0
/* 0D7C0C 8031CC0C 26020004 */ addiu $v0, $s0, 4
/* 0D7C10 8031CC10 3C0146FE */ li $at, 0x46FE0000 # 32512.000000
/* 0D7C14 8031CC14 46128101 */ sub.s $f4, $f16, $f18
/* 0D7C18 8031CC18 E444000C */ swc1 $f4, 0xc($v0)
/* 0D7C1C 8031CC1C 920E0004 */ lbu $t6, 4($s0)
/* 0D7C20 8031CC20 31CF0080 */ andi $t7, $t6, 0x80
/* 0D7C24 8031CC24 51E00017 */ beql $t7, $zero, .L8031CC84
/* 0D7C28 8031CC28 9618001C */ lhu $t8, 0x1c($s0)
/* 0D7C2C 8031CC2C 9598000A */ lhu $t8, 0xa($t4)
/* 0D7C30 8031CC30 3C0E8022 */ lui $t6, %hi(gTempoInternalToExternal) # $t6, 0x8022
/* 0D7C34 8031CC34 85CE6B7C */ lh $t6, %lo(gTempoInternalToExternal)($t6)
/* 0D7C38 8031CC38 44984000 */ mtc1 $t8, $f8
/* 0D7C3C 8031CC3C 8619003C */ lh $t9, 0x3c($s0)
/* 0D7C40 8031CC40 44813000 */ mtc1 $at, $f6
/* 0D7C44 8031CC44 468042A0 */ cvt.s.w $f10, $f8
/* 0D7C48 8031CC48 448E4000 */ mtc1 $t6, $f8
/* 0D7C4C 8031CC4C 44999000 */ mtc1 $t9, $f18
/* 0D7C50 8031CC50 960F001C */ lhu $t7, 0x1c($s0)
/* 0D7C54 8031CC54 46809120 */ cvt.s.w $f4, $f18
/* 0D7C58 8031CC58 460A3402 */ mul.s $f16, $f6, $f10
/* 0D7C5C 8031CC5C 448F9000 */ mtc1 $t7, $f18
/* 0D7C60 8031CC60 468041A0 */ cvt.s.w $f6, $f8
/* 0D7C64 8031CC64 46809220 */ cvt.s.w $f8, $f18
/* 0D7C68 8031CC68 46062282 */ mul.s $f10, $f4, $f6
/* 0D7C6C 8031CC6C 00000000 */ nop
/* 0D7C70 8031CC70 460A4102 */ mul.s $f4, $f8, $f10
/* 0D7C74 8031CC74 46048183 */ div.s $f6, $f16, $f4
/* 0D7C78 8031CC78 10000009 */ b .L8031CCA0
/* 0D7C7C 8031CC7C E4460008 */ swc1 $f6, 8($v0)
/* 0D7C80 8031CC80 9618001C */ lhu $t8, 0x1c($s0)
.L8031CC84:
/* 0D7C84 8031CC84 3C0142FE */ li $at, 0x42FE0000 # 127.000000
/* 0D7C88 8031CC88 44819000 */ mtc1 $at, $f18
/* 0D7C8C 8031CC8C 44984000 */ mtc1 $t8, $f8
/* 0D7C90 8031CC90 00000000 */ nop
/* 0D7C94 8031CC94 468042A0 */ cvt.s.w $f10, $f8
/* 0D7C98 8031CC98 460A9403 */ div.s $f16, $f18, $f10
/* 0D7C9C 8031CC9C E4500008 */ swc1 $f16, 8($v0)
.L8031CCA0:
/* 0D7CA0 8031CCA0 44802000 */ mtc1 $zero, $f4
/* 0D7CA4 8031CCA4 2401FF7F */ li $at, -129
/* 0D7CA8 8031CCA8 E4440004 */ swc1 $f4, 4($v0)
/* 0D7CAC 8031CCAC 92190004 */ lbu $t9, 4($s0)
/* 0D7CB0 8031CCB0 E6000020 */ swc1 $f0, 0x20($s0)
/* 0D7CB4 8031CCB4 03217024 */ and $t6, $t9, $at
/* 0D7CB8 8031CCB8 24010005 */ li $at, 5
/* 0D7CBC 8031CCBC 55C10027 */ bnel $t6, $at, .L8031CD5C
/* 0D7CC0 8031CCC0 860F003C */ lh $t7, 0x3c($s0)
/* 0D7CC4 8031CCC4 10000024 */ b .L8031CD58
/* 0D7CC8 8031CCC8 A2080003 */ sb $t0, 3($s0)
.L8031CCCC:
/* 0D7CCC 8031CCCC 1060001C */ beqz $v1, .L8031CD40
/* 0D7CD0 8031CCD0 0008C880 */ sll $t9, $t0, 2
/* 0D7CD4 8031CCD4 906F0001 */ lbu $t7, 1($v1)
/* 0D7CD8 8031CCD8 004F082A */ slt $at, $v0, $t7
/* 0D7CDC 8031CCDC 10200003 */ beqz $at, .L8031CCEC
/* 0D7CE0 8031CCE0 00087880 */ sll $t7, $t0, 2
/* 0D7CE4 8031CCE4 10000009 */ b .L8031CD0C
/* 0D7CE8 8031CCE8 24620008 */ addiu $v0, $v1, 8
.L8031CCEC:
/* 0D7CEC 8031CCEC 90780002 */ lbu $t8, 2($v1)
/* 0D7CF0 8031CCF0 24640018 */ addiu $a0, $v1, 0x18
/* 0D7CF4 8031CCF4 0302082A */ slt $at, $t8, $v0
/* 0D7CF8 8031CCF8 14200003 */ bnez $at, .L8031CD08
/* 0D7CFC 8031CCFC 00000000 */ nop
/* 0D7D00 8031CD00 10000001 */ b .L8031CD08
/* 0D7D04 8031CD04 24640010 */ addiu $a0, $v1, 0x10
.L8031CD08:
/* 0D7D08 8031CD08 00801025 */ move $v0, $a0
.L8031CD0C:
/* 0D7D0C 8031CD0C 8E19004C */ lw $t9, 0x4c($s0)
/* 0D7D10 8031CD10 3C038033 */ lui $v1, %hi(gNoteFrequencies) # $v1, 0x8033
/* 0D7D14 8031CD14 24633994 */ addiu $v1, %lo(gNoteFrequencies) # addiu $v1, $v1, 0x3994
/* 0D7D18 8031CD18 00597026 */ xor $t6, $v0, $t9
/* 0D7D1C 8031CD1C 2DCE0001 */ sltiu $t6, $t6, 1
/* 0D7D20 8031CD20 A3AE003F */ sb $t6, 0x3f($sp)
/* 0D7D24 8031CD24 AE02004C */ sw $v0, 0x4c($s0)
/* 0D7D28 8031CD28 006FC021 */ addu $t8, $v1, $t7
/* 0D7D2C 8031CD2C C7080000 */ lwc1 $f8, ($t8)
/* 0D7D30 8031CD30 C4460004 */ lwc1 $f6, 4($v0)
/* 0D7D34 8031CD34 46083482 */ mul.s $f18, $f6, $f8
/* 0D7D38 8031CD38 10000007 */ b .L8031CD58
/* 0D7D3C 8031CD3C E6120020 */ swc1 $f18, 0x20($s0)
.L8031CD40:
/* 0D7D40 8031CD40 3C038033 */ lui $v1, %hi(gNoteFrequencies) # $v1, 0x8033
/* 0D7D44 8031CD44 24633994 */ addiu $v1, %lo(gNoteFrequencies) # addiu $v1, $v1, 0x3994
/* 0D7D48 8031CD48 AE00004C */ sw $zero, 0x4c($s0)
/* 0D7D4C 8031CD4C 00797021 */ addu $t6, $v1, $t9
/* 0D7D50 8031CD50 C5CA0000 */ lwc1 $f10, ($t6)
/* 0D7D54 8031CD54 E60A0020 */ swc1 $f10, 0x20($s0)
.L8031CD58:
/* 0D7D58 8031CD58 860F003C */ lh $t7, 0x3c($s0)
.L8031CD5C:
/* 0D7D5C 8031CD5C A60F0040 */ sh $t7, 0x40($s0)
.L8031CD60:
/* 0D7D60 8031CD60 8E020000 */ lw $v0, ($s0)
/* 0D7D64 8031CD64 24010001 */ li $at, 1
/* 0D7D68 8031CD68 0002C080 */ sll $t8, $v0, 2
/* 0D7D6C 8031CD6C 0018CFC2 */ srl $t9, $t8, 0x1f
/* 0D7D70 8031CD70 5721000C */ bnel $t9, $at, .L8031CDA4
/* 0D7D74 8031CD74 000270C0 */ sll $t6, $v0, 3
/* 0D7D78 8031CD78 8E0E0044 */ lw $t6, 0x44($s0)
/* 0D7D7C 8031CD7C 0002C0C0 */ sll $t8, $v0, 3
/* 0D7D80 8031CD80 15C00003 */ bnez $t6, .L8031CD90
/* 0D7D84 8031CD84 00000000 */ nop
/* 0D7D88 8031CD88 0703002E */ bgezl $t8, .L8031CE44
/* 0D7D8C 8031CD8C 8FBF001C */ lw $ra, 0x1c($sp)
.L8031CD90:
/* 0D7D90 8031CD90 0C0C67D9 */ jal seq_channel_layer_note_decay
/* 0D7D94 8031CD94 02002025 */ move $a0, $s0
/* 0D7D98 8031CD98 1000002A */ b .L8031CE44
/* 0D7D9C 8031CD9C 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D7DA0 8031CDA0 000270C0 */ sll $t6, $v0, 3
.L8031CDA4:
/* 0D7DA4 8031CDA4 05C00003 */ bltz $t6, .L8031CDB4
/* 0D7DA8 8031CDA8 00004025 */ move $t0, $zero
/* 0D7DAC 8031CDAC 10000017 */ b .L8031CE0C
/* 0D7DB0 8031CDB0 24080001 */ li $t0, 1
.L8031CDB4:
/* 0D7DB4 8031CDB4 8E040044 */ lw $a0, 0x44($s0)
/* 0D7DB8 8031CDB8 10800005 */ beqz $a0, .L8031CDD0
/* 0D7DBC 8031CDBC 00000000 */ nop
/* 0D7DC0 8031CDC0 920F0001 */ lbu $t7, 1($s0)
/* 0D7DC4 8031CDC4 93B8003F */ lbu $t8, 0x3f($sp)
/* 0D7DC8 8031CDC8 15E00003 */ bnez $t7, .L8031CDD8
/* 0D7DCC 8031CDCC 00000000 */ nop
.L8031CDD0:
/* 0D7DD0 8031CDD0 1000000E */ b .L8031CE0C
/* 0D7DD4 8031CDD4 24080001 */ li $t0, 1
.L8031CDD8:
/* 0D7DD8 8031CDD8 57000006 */ bnezl $t8, .L8031CDF4
/* 0D7DDC 8031CDDC 8E19004C */ lw $t9, 0x4c($s0)
/* 0D7DE0 8031CDE0 0C0C67D9 */ jal seq_channel_layer_note_decay
/* 0D7DE4 8031CDE4 02002025 */ move $a0, $s0
/* 0D7DE8 8031CDE8 10000008 */ b .L8031CE0C
/* 0D7DEC 8031CDEC 24080001 */ li $t0, 1
/* 0D7DF0 8031CDF0 8E19004C */ lw $t9, 0x4c($s0)
.L8031CDF4:
/* 0D7DF4 8031CDF4 02002825 */ move $a1, $s0
/* 0D7DF8 8031CDF8 17200004 */ bnez $t9, .L8031CE0C
/* 0D7DFC 8031CDFC 00000000 */ nop
/* 0D7E00 8031CE00 0C0C6874 */ jal init_synthetic_wave
/* 0D7E04 8031CE04 A3A8003D */ sb $t0, 0x3d($sp)
/* 0D7E08 8031CE08 93A8003D */ lbu $t0, 0x3d($sp)
.L8031CE0C:
/* 0D7E0C 8031CE0C 51000005 */ beql $t0, $zero, .L8031CE24
/* 0D7E10 8031CE10 8E040044 */ lw $a0, 0x44($s0)
/* 0D7E14 8031CE14 0C0C6A53 */ jal alloc_note
/* 0D7E18 8031CE18 02002025 */ move $a0, $s0
/* 0D7E1C 8031CE1C AE020044 */ sw $v0, 0x44($s0)
/* 0D7E20 8031CE20 8E040044 */ lw $a0, 0x44($s0)
.L8031CE24:
/* 0D7E24 8031CE24 50800007 */ beql $a0, $zero, .L8031CE44
/* 0D7E28 8031CE28 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D7E2C 8031CE2C 8C8E002C */ lw $t6, 0x2c($a0)
/* 0D7E30 8031CE30 560E0004 */ bnel $s0, $t6, .L8031CE44
/* 0D7E34 8031CE34 8FBF001C */ lw $ra, 0x1c($sp)
/* 0D7E38 8031CE38 0C0C6D28 */ jal note_vibrato_init
/* 0D7E3C 8031CE3C 00000000 */ nop
.L8031CE40:
/* 0D7E40 8031CE40 8FBF001C */ lw $ra, 0x1c($sp)
.L8031CE44:
/* 0D7E44 8031CE44 8FB00018 */ lw $s0, 0x18($sp)
/* 0D7E48 8031CE48 27BD0060 */ addiu $sp, $sp, 0x60
/* 0D7E4C 8031CE4C 03E00008 */ jr $ra
/* 0D7E50 8031CE50 00000000 */ nop
|
96flashbacks/96flashbacks
| 37,866
|
asm/non_matchings/sequence_channel_process_script_us.s
|
.late_rodata
.late_rodata_alignment 8
glabel jtbl_80337D08 # US: 80338EC0
.word L_U_8031D3A8
.word L_U_8031D354
.word L_U_8031D3C4
.word L_U_8031D3D4
.word L_U_8031D370
.word L_U_8031D5E4
.word L_U_8031D640
.word L_U_8031D678
.word L_U_8031D678
.word L_U_8031D6C4
.word L_U_8031D6D4
.word L_U_8031D678
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D6F4
.word L_U_8031D718
.word L_U_8031D728
.word L_U_8031D44C
.word L_U_8031D5D4
.word L_U_8031D144
.word L_U_8031D5B4
.word L_U_8031D51C
.word L_U_8031D500
.word L_U_8031D4F0
.word L_U_8031D4D4
.word L_U_8031D4BC
.word L_U_8031D498
.word L_U_8031D474
.word L_U_8031D424
.word L_U_8031D3E4
.word L_U_8031D400
.word L_U_8031D56C
.word L_U_8031D538
.word L_U_8031D5A0
.word L_U_8031D73C
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D344
.word L_U_8031D31C
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D2C4
.word L_U_8031D2B4
.word L_U_8031D26C
.word L_U_8031D234
.word L_U_8031D2C4
.word L_U_8031D2C4
.word L_U_8031D2C4
.word L_U_8031D1F8
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
glabel jtbl_80337E04 # US: 80338FBC
.word L_U_8031D7B8
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D900
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D930
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D94C
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D974
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D814
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D8F8
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D7E8
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D7F8
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D830
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D87C
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D144
.word L_U_8031D898
.text
glabel sequence_channel_process_script
/* 0D808C 8031D08C 27BDFFA0 */ addiu $sp, $sp, -0x60
/* 0D8090 8031D090 AFBF002C */ sw $ra, 0x2c($sp)
/* 0D8094 8031D094 AFB50028 */ sw $s5, 0x28($sp)
/* 0D8098 8031D098 AFB40024 */ sw $s4, 0x24($sp)
/* 0D809C 8031D09C AFB30020 */ sw $s3, 0x20($sp)
/* 0D80A0 8031D0A0 AFB2001C */ sw $s2, 0x1c($sp)
/* 0D80A4 8031D0A4 AFB10018 */ sw $s1, 0x18($sp)
/* 0D80A8 8031D0A8 AFB00014 */ sw $s0, 0x14($sp)
/* 0D80AC 8031D0AC 8C820000 */ lw $v0, ($a0)
/* 0D80B0 8031D0B0 00809025 */ move $s2, $a0
/* 0D80B4 8031D0B4 000277C2 */ srl $t6, $v0, 0x1f
/* 0D80B8 8031D0B8 11C00243 */ beqz $t6, .L8031D9C8
/* 0D80BC 8031D0BC 0002C080 */ sll $t8, $v0, 2
/* 0D80C0 8031D0C0 0701000D */ bgez $t8, .L8031D0F8
/* 0D80C4 8031D0C4 00008025 */ move $s0, $zero
/* 0D80C8 8031D0C8 00808825 */ move $s1, $a0
/* 0D80CC 8031D0CC 24120010 */ li $s2, 16
.L8031D0D0:
/* 0D80D0 8031D0D0 8E240044 */ lw $a0, 0x44($s1)
/* 0D80D4 8031D0D4 50800004 */ beql $a0, $zero, .L8031D0E8
/* 0D80D8 8031D0D8 26100004 */ addiu $s0, $s0, 4
/* 0D80DC 8031D0DC 0C0C7031 */ jal seq_channel_layer_process_script
/* 0D80E0 8031D0E0 00000000 */ nop
/* 0D80E4 8031D0E4 26100004 */ addiu $s0, $s0, 4
.L8031D0E8:
/* 0D80E8 8031D0E8 1612FFF9 */ bne $s0, $s2, .L8031D0D0
/* 0D80EC 8031D0EC 26310004 */ addiu $s1, $s1, 4
/* 0D80F0 8031D0F0 10000236 */ b .L8031D9CC
/* 0D80F4 8031D0F4 8FBF002C */ lw $ra, 0x2c($sp)
.L8031D0F8:
/* 0D80F8 8031D0F8 8E540040 */ lw $s4, 0x40($s2)
/* 0D80FC 8031D0FC 8E990000 */ lw $t9, ($s4)
/* 0D8100 8031D100 00195080 */ sll $t2, $t9, 2
/* 0D8104 8031D104 05430006 */ bgezl $t2, .L8031D120
/* 0D8108 8031D108 96430016 */ lhu $v1, 0x16($s2)
/* 0D810C 8031D10C 924B0002 */ lbu $t3, 2($s2)
/* 0D8110 8031D110 316C0080 */ andi $t4, $t3, 0x80
/* 0D8114 8031D114 5580022D */ bnezl $t4, .L8031D9CC
/* 0D8118 8031D118 8FBF002C */ lw $ra, 0x2c($sp)
/* 0D811C 8031D11C 96430016 */ lhu $v1, 0x16($s2)
.L8031D120:
/* 0D8120 8031D120 2650005C */ addiu $s0, $s2, 0x5c
/* 0D8124 8031D124 2415FFFF */ li $s5, -1
/* 0D8128 8031D128 10600004 */ beqz $v1, .L8031D13C
/* 0D812C 8031D12C 00601025 */ move $v0, $v1
/* 0D8130 8031D130 246DFFFF */ addiu $t5, $v1, -1
/* 0D8134 8031D134 A64D0016 */ sh $t5, 0x16($s2)
/* 0D8138 8031D138 31A2FFFF */ andi $v0, $t5, 0xffff
.L8031D13C:
/* 0D813C 8031D13C 14400217 */ bnez $v0, .L8031D99C
/* 0D8140 8031D140 83B3004B */ lb $s3, 0x4b($sp)
glabel L_U_8031D144
.L8031D144:
/* 0D8144 8031D144 0C0C700F */ jal m64_read_u8
/* 0D8148 8031D148 02002025 */ move $a0, $s0
/* 0D814C 8031D14C 240100FF */ li $at, 255
/* 0D8150 8031D150 305100FF */ andi $s1, $v0, 0xff
/* 0D8154 8031D154 1441000E */ bne $v0, $at, .L8031D190
/* 0D8158 8031D158 00401825 */ move $v1, $v0
/* 0D815C 8031D15C 92040018 */ lbu $a0, 0x18($s0)
/* 0D8160 8031D160 14800005 */ bnez $a0, .L8031D178
/* 0D8164 8031D164 248EFFFF */ addiu $t6, $a0, -1
/* 0D8168 8031D168 0C0C6EBC */ jal sequence_channel_disable
/* 0D816C 8031D16C 02402025 */ move $a0, $s2
/* 0D8170 8031D170 1000020B */ b .L8031D9A0
/* 0D8174 8031D174 02408825 */ move $s1, $s2
.L8031D178:
/* 0D8178 8031D178 31CF00FF */ andi $t7, $t6, 0xff
/* 0D817C 8031D17C 000FC080 */ sll $t8, $t7, 2
/* 0D8180 8031D180 0218C821 */ addu $t9, $s0, $t8
/* 0D8184 8031D184 A20E0018 */ sb $t6, 0x18($s0)
/* 0D8188 8031D188 8F290004 */ lw $t1, 4($t9)
/* 0D818C 8031D18C AE090000 */ sw $t1, ($s0)
.L8031D190:
/* 0D8190 8031D190 240100FE */ li $at, 254
/* 0D8194 8031D194 10610201 */ beq $v1, $at, .L8031D99C
/* 0D8198 8031D198 240100FD */ li $at, 253
/* 0D819C 8031D19C 14610005 */ bne $v1, $at, .L8031D1B4
/* 0D81A0 8031D1A0 307900F0 */ andi $t9, $v1, 0xf0
/* 0D81A4 8031D1A4 0C0C7020 */ jal m64_read_compressed_u16
/* 0D81A8 8031D1A8 02002025 */ move $a0, $s0
/* 0D81AC 8031D1AC 100001FB */ b .L8031D99C
/* 0D81B0 8031D1B0 A6420016 */ sh $v0, 0x16($s2)
.L8031D1B4:
/* 0D81B4 8031D1B4 240100F3 */ li $at, 243
/* 0D81B8 8031D1B8 14610005 */ bne $v1, $at, .L8031D1D0
/* 0D81BC 8031D1BC 246DFF3F */ addiu $t5, $v1, -0xc1
/* 0D81C0 8031D1C0 924B0000 */ lbu $t3, ($s2)
/* 0D81C4 8031D1C4 356C0020 */ ori $t4, $t3, 0x20
/* 0D81C8 8031D1C8 100001F4 */ b .L8031D99C
/* 0D81CC 8031D1CC A24C0000 */ sb $t4, ($s2)
.L8031D1D0:
/* 0D81D0 8031D1D0 286100C1 */ slti $at, $v1, 0xc1
/* 0D81D4 8031D1D4 1420016E */ bnez $at, .L8031D790
/* 0D81D8 8031D1D8 2DA1003F */ sltiu $at, $t5, 0x3f
/* 0D81DC 8031D1DC 1020FFD9 */ beqz $at, .L8031D144
/* 0D81E0 8031D1E0 000D6880 */ sll $t5, $t5, 2
/* 0D81E4 8031D1E4 3C018034 */ lui $at, %hi(jtbl_80337D08)
/* 0D81E8 8031D1E8 002D0821 */ addu $at, $at, $t5
/* 0D81EC 8031D1EC 8C2D8EC0 */ lw $t5, %lo(jtbl_80337D08)($at)
/* 0D81F0 8031D1F0 01A00008 */ jr $t5
/* 0D81F4 8031D1F4 00000000 */ nop
glabel L_U_8031D1F8
/* 0D81F8 8031D1F8 0C0C7014 */ jal m64_read_s16
/* 0D81FC 8031D1FC 02002025 */ move $a0, $s0
/* 0D8200 8031D200 920E0018 */ lbu $t6, 0x18($s0)
/* 0D8204 8031D204 8E180000 */ lw $t8, ($s0)
/* 0D8208 8031D208 304CFFFF */ andi $t4, $v0, 0xffff
/* 0D820C 8031D20C 25CF0001 */ addiu $t7, $t6, 1
/* 0D8210 8031D210 31F900FF */ andi $t9, $t7, 0xff
/* 0D8214 8031D214 00194880 */ sll $t1, $t9, 2
/* 0D8218 8031D218 02095021 */ addu $t2, $s0, $t1
/* 0D821C 8031D21C A20F0018 */ sb $t7, 0x18($s0)
/* 0D8220 8031D220 AD580000 */ sw $t8, ($t2)
/* 0D8224 8031D224 8E8B0014 */ lw $t3, 0x14($s4)
/* 0D8228 8031D228 016C6821 */ addu $t5, $t3, $t4
/* 0D822C 8031D22C 1000FFC5 */ b .L8031D144
/* 0D8230 8031D230 AE0D0000 */ sw $t5, ($s0)
glabel L_U_8031D234
/* 0D8234 8031D234 0C0C700F */ jal m64_read_u8
/* 0D8238 8031D238 02002025 */ move $a0, $s0
/* 0D823C 8031D23C 920E0018 */ lbu $t6, 0x18($s0)
/* 0D8240 8031D240 020E7821 */ addu $t7, $s0, $t6
/* 0D8244 8031D244 A1E20014 */ sb $v0, 0x14($t7)
/* 0D8248 8031D248 92190018 */ lbu $t9, 0x18($s0)
/* 0D824C 8031D24C 8E180000 */ lw $t8, ($s0)
/* 0D8250 8031D250 27290001 */ addiu $t1, $t9, 1
/* 0D8254 8031D254 312A00FF */ andi $t2, $t1, 0xff
/* 0D8258 8031D258 000A5880 */ sll $t3, $t2, 2
/* 0D825C 8031D25C 020B6021 */ addu $t4, $s0, $t3
/* 0D8260 8031D260 A2090018 */ sb $t1, 0x18($s0)
/* 0D8264 8031D264 1000FFB7 */ b .L8031D144
/* 0D8268 8031D268 AD980000 */ sw $t8, ($t4)
glabel L_U_8031D26C
/* 0D826C 8031D26C 920D0018 */ lbu $t5, 0x18($s0)
/* 0D8270 8031D270 020D1021 */ addu $v0, $s0, $t5
/* 0D8274 8031D274 904E0013 */ lbu $t6, 0x13($v0)
/* 0D8278 8031D278 25CFFFFF */ addiu $t7, $t6, -1
/* 0D827C 8031D27C A04F0013 */ sb $t7, 0x13($v0)
/* 0D8280 8031D280 92040018 */ lbu $a0, 0x18($s0)
/* 0D8284 8031D284 0204C821 */ addu $t9, $s0, $a0
/* 0D8288 8031D288 93290013 */ lbu $t1, 0x13($t9)
/* 0D828C 8031D28C 00801825 */ move $v1, $a0
/* 0D8290 8031D290 00035080 */ sll $t2, $v1, 2
/* 0D8294 8031D294 11200005 */ beqz $t1, .L8031D2AC
/* 0D8298 8031D298 248CFFFF */ addiu $t4, $a0, -1
/* 0D829C 8031D29C 020A5821 */ addu $t3, $s0, $t2
/* 0D82A0 8031D2A0 8D780000 */ lw $t8, ($t3)
/* 0D82A4 8031D2A4 1000FFA7 */ b .L8031D144
/* 0D82A8 8031D2A8 AE180000 */ sw $t8, ($s0)
.L8031D2AC:
/* 0D82AC 8031D2AC 1000FFA5 */ b .L8031D144
/* 0D82B0 8031D2B0 A20C0018 */ sb $t4, 0x18($s0)
glabel L_U_8031D2B4
/* 0D82B4 8031D2B4 920D0018 */ lbu $t5, 0x18($s0)
/* 0D82B8 8031D2B8 25AEFFFF */ addiu $t6, $t5, -1
/* 0D82BC 8031D2BC 1000FFA1 */ b .L8031D144
/* 0D82C0 8031D2C0 A20E0018 */ sb $t6, 0x18($s0)
glabel L_U_8031D2C4
/* 0D82C4 8031D2C4 0C0C7014 */ jal m64_read_s16
/* 0D82C8 8031D2C8 02002025 */ move $a0, $s0
/* 0D82CC 8031D2CC 240100FA */ li $at, 250
/* 0D82D0 8031D2D0 16210003 */ bne $s1, $at, .L8031D2E0
/* 0D82D4 8031D2D4 02201825 */ move $v1, $s1
/* 0D82D8 8031D2D8 1660FF9A */ bnez $s3, .L8031D144
/* 0D82DC 8031D2DC 00000000 */ nop
.L8031D2E0:
/* 0D82E0 8031D2E0 240100F9 */ li $at, 249
/* 0D82E4 8031D2E4 54610004 */ bnel $v1, $at, .L8031D2F8
/* 0D82E8 8031D2E8 240100F5 */ li $at, 245
/* 0D82EC 8031D2EC 0661FF95 */ bgez $s3, .L8031D144
/* 0D82F0 8031D2F0 00000000 */ nop
/* 0D82F4 8031D2F4 240100F5 */ li $at, 245
.L8031D2F8:
/* 0D82F8 8031D2F8 54610004 */ bnel $v1, $at, .L8031D30C
/* 0D82FC 8031D2FC 8E8F0014 */ lw $t7, 0x14($s4)
/* 0D8300 8031D300 0660FF90 */ bltz $s3, .L8031D144
/* 0D8304 8031D304 00000000 */ nop
/* 0D8308 8031D308 8E8F0014 */ lw $t7, 0x14($s4)
.L8031D30C:
/* 0D830C 8031D30C 3059FFFF */ andi $t9, $v0, 0xffff
/* 0D8310 8031D310 01F94821 */ addu $t1, $t7, $t9
/* 0D8314 8031D314 1000FF8B */ b .L8031D144
/* 0D8318 8031D318 AE090000 */ sw $t1, ($s0)
glabel L_U_8031D31C
/* 0D831C 8031D31C 26510080 */ addiu $s1, $s2, 0x80
/* 0D8320 8031D320 0C0C68DA */ jal note_pool_clear
/* 0D8324 8031D324 02202025 */ move $a0, $s1
/* 0D8328 8031D328 0C0C700F */ jal m64_read_u8
/* 0D832C 8031D32C 02002025 */ move $a0, $s0
/* 0D8330 8031D330 02202025 */ move $a0, $s1
/* 0D8334 8031D334 0C0C6925 */ jal note_pool_fill
/* 0D8338 8031D338 00402825 */ move $a1, $v0
/* 0D833C 8031D33C 1000FF81 */ b .L8031D144
/* 0D8340 8031D340 00000000 */ nop
glabel L_U_8031D344
/* 0D8344 8031D344 0C0C68DA */ jal note_pool_clear
/* 0D8348 8031D348 26440080 */ addiu $a0, $s2, 0x80
/* 0D834C 8031D34C 1000FF7D */ b .L8031D144
/* 0D8350 8031D350 00000000 */ nop
glabel L_U_8031D354
/* 0D8354 8031D354 0C0C7014 */ jal m64_read_s16
/* 0D8358 8031D358 02002025 */ move $a0, $s0
/* 0D835C 8031D35C 8E8A0014 */ lw $t2, 0x14($s4)
/* 0D8360 8031D360 304BFFFF */ andi $t3, $v0, 0xffff
/* 0D8364 8031D364 014BC021 */ addu $t8, $t2, $t3
/* 0D8368 8031D368 1000FF76 */ b .L8031D144
/* 0D836C 8031D36C AE580030 */ sw $t8, 0x30($s2)
glabel L_U_8031D370
/* 0D8370 8031D370 1275FF74 */ beq $s3, $s5, .L8031D144
/* 0D8374 8031D374 00000000 */ nop
/* 0D8378 8031D378 8E4C0030 */ lw $t4, 0x30($s2)
/* 0D837C 8031D37C 00136840 */ sll $t5, $s3, 1
/* 0D8380 8031D380 8E8A0014 */ lw $t2, 0x14($s4)
/* 0D8384 8031D384 018D1021 */ addu $v0, $t4, $t5
/* 0D8388 8031D388 904F0000 */ lbu $t7, ($v0)
/* 0D838C 8031D38C 904E0001 */ lbu $t6, 1($v0)
/* 0D8390 8031D390 000FCA00 */ sll $t9, $t7, 8
/* 0D8394 8031D394 01D93821 */ addu $a3, $t6, $t9
/* 0D8398 8031D398 30E9FFFF */ andi $t1, $a3, 0xffff
/* 0D839C 8031D39C 01495821 */ addu $t3, $t2, $t1
/* 0D83A0 8031D3A0 1000FF68 */ b .L8031D144
/* 0D83A4 8031D3A4 AE4B0030 */ sw $t3, 0x30($s2)
glabel L_U_8031D3A8
/* 0D83A8 8031D3A8 0C0C700F */ jal m64_read_u8
/* 0D83AC 8031D3AC 02002025 */ move $a0, $s0
/* 0D83B0 8031D3B0 02402025 */ move $a0, $s2
/* 0D83B4 8031D3B4 0C0C73F5 */ jal set_instrument
/* 0D83B8 8031D3B8 304500FF */ andi $a1, $v0, 0xff
/* 0D83BC 8031D3BC 1000FF61 */ b .L8031D144
/* 0D83C0 8031D3C0 00000000 */ nop
glabel L_U_8031D3C4
/* 0D83C4 8031D3C4 92580000 */ lbu $t8, ($s2)
/* 0D83C8 8031D3C8 330CFFFD */ andi $t4, $t8, 0xfffd
/* 0D83CC 8031D3CC 1000FF5D */ b .L8031D144
/* 0D83D0 8031D3D0 A24C0000 */ sb $t4, ($s2)
glabel L_U_8031D3D4
/* 0D83D4 8031D3D4 924F0000 */ lbu $t7, ($s2)
/* 0D83D8 8031D3D8 35EE0002 */ ori $t6, $t7, 2
/* 0D83DC 8031D3DC 1000FF59 */ b .L8031D144
/* 0D83E0 8031D3E0 A24E0000 */ sb $t6, ($s2)
glabel L_U_8031D3E4
/* 0D83E4 8031D3E4 0C0C700F */ jal m64_read_u8
/* 0D83E8 8031D3E8 02002025 */ move $a0, $s0
/* 0D83EC 8031D3EC 02402025 */ move $a0, $s2
/* 0D83F0 8031D3F0 0C0C741A */ jal sequence_channel_set_volume
/* 0D83F4 8031D3F4 304500FF */ andi $a1, $v0, 0xff
/* 0D83F8 8031D3F8 1000FF52 */ b .L8031D144
/* 0D83FC 8031D3FC 00000000 */ nop
glabel L_U_8031D400
/* 0D8400 8031D400 0C0C700F */ jal m64_read_u8
/* 0D8404 8031D404 02002025 */ move $a0, $s0
/* 0D8408 8031D408 44822000 */ mtc1 $v0, $f4
/* 0D840C 8031D40C 3C013C00 */ li $at, 0x3C000000 # 0.007812
/* 0D8410 8031D410 44814000 */ mtc1 $at, $f8
/* 0D8414 8031D414 468021A0 */ cvt.s.w $f6, $f4
/* 0D8418 8031D418 46083282 */ mul.s $f10, $f6, $f8
/* 0D841C 8031D41C 1000FF49 */ b .L8031D144
/* 0D8420 8031D420 E64A001C */ swc1 $f10, 0x1c($s2)
glabel L_U_8031D424
/* 0D8424 8031D424 0C0C7014 */ jal m64_read_s16
/* 0D8428 8031D428 02002025 */ move $a0, $s0
/* 0D842C 8031D42C 3059FFFF */ andi $t9, $v0, 0xffff
/* 0D8430 8031D430 44998000 */ mtc1 $t9, $f16
/* 0D8434 8031D434 3C014700 */ li $at, 0x47000000 # 32768.000000
/* 0D8438 8031D438 44812000 */ mtc1 $at, $f4
/* 0D843C 8031D43C 468084A0 */ cvt.s.w $f18, $f16
/* 0D8440 8031D440 46049183 */ div.s $f6, $f18, $f4
/* 0D8444 8031D444 1000FF3F */ b .L8031D144
/* 0D8448 8031D448 E646002C */ swc1 $f6, 0x2c($s2)
glabel L_U_8031D44C
/* 0D844C 8031D44C 0C0C700F */ jal m64_read_u8
/* 0D8450 8031D450 02002025 */ move $a0, $s0
/* 0D8454 8031D454 2449007F */ addiu $t1, $v0, 0x7f
/* 0D8458 8031D458 312A00FF */ andi $t2, $t1, 0xff
/* 0D845C 8031D45C 000A5880 */ sll $t3, $t2, 2
/* 0D8460 8031D460 3C018033 */ lui $at, %hi(gPitchBendFrequencyScale)
/* 0D8464 8031D464 002B0821 */ addu $at, $at, $t3
/* 0D8468 8031D468 C4283598 */ lwc1 $f8, %lo(gPitchBendFrequencyScale)($at)
/* 0D846C 8031D46C 1000FF35 */ b .L8031D144
/* 0D8470 8031D470 E648002C */ swc1 $f8, 0x2c($s2)
glabel L_U_8031D474
/* 0D8474 8031D474 0C0C700F */ jal m64_read_u8
/* 0D8478 8031D478 02002025 */ move $a0, $s0
/* 0D847C 8031D47C 44825000 */ mtc1 $v0, $f10
/* 0D8480 8031D480 3C013C00 */ li $at, 0x3C000000 # 0.007812
/* 0D8484 8031D484 44819000 */ mtc1 $at, $f18
/* 0D8488 8031D488 46805420 */ cvt.s.w $f16, $f10
/* 0D848C 8031D48C 46128102 */ mul.s $f4, $f16, $f18
/* 0D8490 8031D490 1000FF2C */ b .L8031D144
/* 0D8494 8031D494 E6440024 */ swc1 $f4, 0x24($s2)
glabel L_U_8031D498
/* 0D8498 8031D498 0C0C700F */ jal m64_read_u8
/* 0D849C 8031D49C 02002025 */ move $a0, $s0
/* 0D84A0 8031D4A0 44823000 */ mtc1 $v0, $f6
/* 0D84A4 8031D4A4 3C013C00 */ li $at, 0x3C000000 # 0.007812
/* 0D84A8 8031D4A8 44815000 */ mtc1 $at, $f10
/* 0D84AC 8031D4AC 46803220 */ cvt.s.w $f8, $f6
/* 0D84B0 8031D4B0 460A4402 */ mul.s $f16, $f8, $f10
/* 0D84B4 8031D4B4 1000FF23 */ b .L8031D144
/* 0D84B8 8031D4B8 E6500028 */ swc1 $f16, 0x28($s2)
glabel L_U_8031D4BC
/* 0D84BC 8031D4BC 8E020000 */ lw $v0, ($s0)
/* 0D84C0 8031D4C0 80430000 */ lb $v1, ($v0)
/* 0D84C4 8031D4C4 24580001 */ addiu $t8, $v0, 1
/* 0D84C8 8031D4C8 AE180000 */ sw $t8, ($s0)
/* 0D84CC 8031D4CC 1000FF1D */ b .L8031D144
/* 0D84D0 8031D4D0 A643001A */ sh $v1, 0x1a($s2)
glabel L_U_8031D4D4
/* 0D84D4 8031D4D4 0C0C7014 */ jal m64_read_s16
/* 0D84D8 8031D4D8 02002025 */ move $a0, $s0
/* 0D84DC 8031D4DC 8E8C0014 */ lw $t4, 0x14($s4)
/* 0D84E0 8031D4E0 304DFFFF */ andi $t5, $v0, 0xffff
/* 0D84E4 8031D4E4 018D7821 */ addu $t7, $t4, $t5
/* 0D84E8 8031D4E8 1000FF16 */ b .L8031D144
/* 0D84EC 8031D4EC AE4F007C */ sw $t7, 0x7c($s2)
glabel L_U_8031D4F0
/* 0D84F0 8031D4F0 0C0C700F */ jal m64_read_u8
/* 0D84F4 8031D4F4 02002025 */ move $a0, $s0
/* 0D84F8 8031D4F8 1000FF12 */ b .L8031D144
/* 0D84FC 8031D4FC A2420078 */ sb $v0, 0x78($s2)
glabel L_U_8031D500
/* 0D8500 8031D500 0C0C700F */ jal m64_read_u8
/* 0D8504 8031D504 02002025 */ move $a0, $s0
/* 0D8508 8031D508 000270C0 */ sll $t6, $v0, 3
/* 0D850C 8031D50C A64E000E */ sh $t6, 0xe($s2)
/* 0D8510 8031D510 A640000A */ sh $zero, 0xa($s2)
/* 0D8514 8031D514 1000FF0B */ b .L8031D144
/* 0D8518 8031D518 A6400012 */ sh $zero, 0x12($s2)
glabel L_U_8031D51C
/* 0D851C 8031D51C 0C0C700F */ jal m64_read_u8
/* 0D8520 8031D520 02002025 */ move $a0, $s0
/* 0D8524 8031D524 00021940 */ sll $v1, $v0, 5
/* 0D8528 8031D528 A643000C */ sh $v1, 0xc($s2)
/* 0D852C 8031D52C A6430008 */ sh $v1, 8($s2)
/* 0D8530 8031D530 1000FF04 */ b .L8031D144
/* 0D8534 8031D534 A6400010 */ sh $zero, 0x10($s2)
glabel L_U_8031D538
/* 0D8538 8031D538 0C0C700F */ jal m64_read_u8
/* 0D853C 8031D53C 02002025 */ move $a0, $s0
/* 0D8540 8031D540 0002C8C0 */ sll $t9, $v0, 3
/* 0D8544 8031D544 A659000A */ sh $t9, 0xa($s2)
/* 0D8548 8031D548 0C0C700F */ jal m64_read_u8
/* 0D854C 8031D54C 02002025 */ move $a0, $s0
/* 0D8550 8031D550 000248C0 */ sll $t1, $v0, 3
/* 0D8554 8031D554 A649000E */ sh $t1, 0xe($s2)
/* 0D8558 8031D558 0C0C700F */ jal m64_read_u8
/* 0D855C 8031D55C 02002025 */ move $a0, $s0
/* 0D8560 8031D560 00025100 */ sll $t2, $v0, 4
/* 0D8564 8031D564 1000FEF7 */ b .L8031D144
/* 0D8568 8031D568 A64A0012 */ sh $t2, 0x12($s2)
glabel L_U_8031D56C
/* 0D856C 8031D56C 0C0C700F */ jal m64_read_u8
/* 0D8570 8031D570 02002025 */ move $a0, $s0
/* 0D8574 8031D574 00025940 */ sll $t3, $v0, 5
/* 0D8578 8031D578 A64B0008 */ sh $t3, 8($s2)
/* 0D857C 8031D57C 0C0C700F */ jal m64_read_u8
/* 0D8580 8031D580 02002025 */ move $a0, $s0
/* 0D8584 8031D584 0002C140 */ sll $t8, $v0, 5
/* 0D8588 8031D588 A658000C */ sh $t8, 0xc($s2)
/* 0D858C 8031D58C 0C0C700F */ jal m64_read_u8
/* 0D8590 8031D590 02002025 */ move $a0, $s0
/* 0D8594 8031D594 00026100 */ sll $t4, $v0, 4
/* 0D8598 8031D598 1000FEEA */ b .L8031D144
/* 0D859C 8031D59C A64C0010 */ sh $t4, 0x10($s2)
glabel L_U_8031D5A0
/* 0D85A0 8031D5A0 0C0C700F */ jal m64_read_u8
/* 0D85A4 8031D5A4 02002025 */ move $a0, $s0
/* 0D85A8 8031D5A8 00026900 */ sll $t5, $v0, 4
/* 0D85AC 8031D5AC 1000FEE5 */ b .L8031D144
/* 0D85B0 8031D5B0 A64D0014 */ sh $t5, 0x14($s2)
glabel L_U_8031D5B4
/* 0D85B4 8031D5B4 0C0C700F */ jal m64_read_u8
/* 0D85B8 8031D5B8 02002025 */ move $a0, $s0
/* 0D85BC 8031D5BC 14400003 */ bnez $v0, .L8031D5CC
/* 0D85C0 8031D5C0 305100FF */ andi $s1, $v0, 0xff
/* 0D85C4 8031D5C4 3C118022 */ lui $s1, %hi(gAudioUpdatesPerFrame) # $s1, 0x8022
/* 0D85C8 8031D5C8 92316B7E */ lbu $s1, %lo(gAudioUpdatesPerFrame)($s1)
.L8031D5CC:
/* 0D85CC 8031D5CC 1000FEDD */ b .L8031D144
/* 0D85D0 8031D5D0 A2510006 */ sb $s1, 6($s2)
glabel L_U_8031D5D4
/* 0D85D4 8031D5D4 0C0C700F */ jal m64_read_u8
/* 0D85D8 8031D5D8 02002025 */ move $a0, $s0
/* 0D85DC 8031D5DC 1000FED9 */ b .L8031D144
/* 0D85E0 8031D5E0 A2420003 */ sb $v0, 3($s2)
glabel L_U_8031D5E4
/* 0D85E4 8031D5E4 0C0C700F */ jal m64_read_u8
/* 0D85E8 8031D5E8 02002025 */ move $a0, $s0
/* 0D85EC 8031D5EC 928F0005 */ lbu $t7, 5($s4)
/* 0D85F0 8031D5F0 3C038022 */ lui $v1, %hi(gAlBankSets) # $v1, 0x8022
/* 0D85F4 8031D5F4 8C636B58 */ lw $v1, %lo(gAlBankSets)($v1)
/* 0D85F8 8031D5F8 000F7040 */ sll $t6, $t7, 1
/* 0D85FC 8031D5FC 3C048022 */ lui $a0, %hi(gBankLoadedPool) # $a0, 0x8022
/* 0D8600 8031D600 006EC821 */ addu $t9, $v1, $t6
/* 0D8604 8031D604 97270000 */ lhu $a3, ($t9)
/* 0D8608 8031D608 248410F8 */ addiu $a0, %lo(gBankLoadedPool) # addiu $a0, $a0, 0x10f8
/* 0D860C 8031D60C 24050002 */ li $a1, 2
/* 0D8610 8031D610 00E34821 */ addu $t1, $a3, $v1
/* 0D8614 8031D614 91280000 */ lbu $t0, ($t1)
/* 0D8618 8031D618 00E85021 */ addu $t2, $a3, $t0
/* 0D861C 8031D61C 01425823 */ subu $t3, $t2, $v0
/* 0D8620 8031D620 0163C021 */ addu $t8, $t3, $v1
/* 0D8624 8031D624 93110000 */ lbu $s1, ($t8)
/* 0D8628 8031D628 0C0C5E0B */ jal get_bank_or_seq
/* 0D862C 8031D62C 02203025 */ move $a2, $s1
/* 0D8630 8031D630 1040FEC4 */ beqz $v0, .L8031D144
/* 0D8634 8031D634 00000000 */ nop
/* 0D8638 8031D638 1000FEC2 */ b .L8031D144
/* 0D863C 8031D63C A2510005 */ sb $s1, 5($s2)
glabel L_U_8031D640
/* 0D8640 8031D640 326C00FF */ andi $t4, $s3, 0xff
/* 0D8644 8031D644 AFAC0030 */ sw $t4, 0x30($sp)
/* 0D8648 8031D648 0C0C700F */ jal m64_read_u8
/* 0D864C 8031D64C 02002025 */ move $a0, $s0
/* 0D8650 8031D650 305100FF */ andi $s1, $v0, 0xff
/* 0D8654 8031D654 0C0C7014 */ jal m64_read_s16
/* 0D8658 8031D658 02002025 */ move $a0, $s0
/* 0D865C 8031D65C 8E8D0014 */ lw $t5, 0x14($s4)
/* 0D8660 8031D660 8FAE0030 */ lw $t6, 0x30($sp)
/* 0D8664 8031D664 304FFFFF */ andi $t7, $v0, 0xffff
/* 0D8668 8031D668 01AF1821 */ addu $v1, $t5, $t7
/* 0D866C 8031D66C 01D1C821 */ addu $t9, $t6, $s1
/* 0D8670 8031D670 1000FEB4 */ b .L8031D144
/* 0D8674 8031D674 A0790000 */ sb $t9, ($v1)
glabel L_U_8031D678
/* 0D8678 8031D678 0C0C700F */ jal m64_read_u8
/* 0D867C 8031D67C 02002025 */ move $a0, $s0
/* 0D8680 8031D680 240100C8 */ li $at, 200
/* 0D8684 8031D684 16210005 */ bne $s1, $at, .L8031D69C
/* 0D8688 8031D688 02201825 */ move $v1, $s1
/* 0D868C 8031D68C 02629823 */ subu $s3, $s3, $v0
/* 0D8690 8031D690 00135E00 */ sll $t3, $s3, 0x18
/* 0D8694 8031D694 1000FEAB */ b .L8031D144
/* 0D8698 8031D698 000B9E03 */ sra $s3, $t3, 0x18
.L8031D69C:
/* 0D869C 8031D69C 240100CC */ li $at, 204
/* 0D86A0 8031D6A0 14610005 */ bne $v1, $at, .L8031D6B8
/* 0D86A4 8031D6A4 02629824 */ and $s3, $s3, $v0
/* 0D86A8 8031D6A8 00029E00 */ sll $s3, $v0, 0x18
/* 0D86AC 8031D6AC 00136603 */ sra $t4, $s3, 0x18
/* 0D86B0 8031D6B0 1000FEA4 */ b .L8031D144
/* 0D86B4 8031D6B4 01809825 */ move $s3, $t4
.L8031D6B8:
/* 0D86B8 8031D6B8 00137600 */ sll $t6, $s3, 0x18
/* 0D86BC 8031D6BC 1000FEA1 */ b .L8031D144
/* 0D86C0 8031D6C0 000E9E03 */ sra $s3, $t6, 0x18
glabel L_U_8031D6C4
/* 0D86C4 8031D6C4 0C0C700F */ jal m64_read_u8
/* 0D86C8 8031D6C8 02002025 */ move $a0, $s0
/* 0D86CC 8031D6CC 1000FE9D */ b .L8031D144
/* 0D86D0 8031D6D0 A2420002 */ sb $v0, 2($s2)
glabel L_U_8031D6D4
/* 0D86D4 8031D6D4 0C0C7014 */ jal m64_read_s16
/* 0D86D8 8031D6D8 02002025 */ move $a0, $s0
/* 0D86DC 8031D6DC 8E890014 */ lw $t1, 0x14($s4)
/* 0D86E0 8031D6E0 304AFFFF */ andi $t2, $v0, 0xffff
/* 0D86E4 8031D6E4 01535821 */ addu $t3, $t2, $s3
/* 0D86E8 8031D6E8 012BC021 */ addu $t8, $t1, $t3
/* 0D86EC 8031D6EC 1000FE95 */ b .L8031D144
/* 0D86F0 8031D6F0 83130000 */ lb $s3, ($t8)
glabel L_U_8031D6F4
/* 0D86F4 8031D6F4 0C0C700F */ jal m64_read_u8
/* 0D86F8 8031D6F8 02002025 */ move $a0, $s0
/* 0D86FC 8031D6FC 924E0000 */ lbu $t6, ($s2)
/* 0D8700 8031D700 00026880 */ sll $t5, $v0, 2
/* 0D8704 8031D704 31AF0004 */ andi $t7, $t5, 4
/* 0D8708 8031D708 31D9FFFB */ andi $t9, $t6, 0xfffb
/* 0D870C 8031D70C 01F95025 */ or $t2, $t7, $t9
/* 0D8710 8031D710 1000FE8C */ b .L8031D144
/* 0D8714 8031D714 A24A0000 */ sb $t2, ($s2)
glabel L_U_8031D718
/* 0D8718 8031D718 0C0C700F */ jal m64_read_u8
/* 0D871C 8031D71C 02002025 */ move $a0, $s0
/* 0D8720 8031D720 1000FE88 */ b .L8031D144
/* 0D8724 8031D724 A2420001 */ sb $v0, 1($s2)
glabel L_U_8031D728
/* 0D8728 8031D728 0C0C700F */ jal m64_read_u8
/* 0D872C 8031D72C 02002025 */ move $a0, $s0
/* 0D8730 8031D730 00024A00 */ sll $t1, $v0, 8
/* 0D8734 8031D734 1000FE83 */ b .L8031D144
/* 0D8738 8031D738 A649007A */ sh $t1, 0x7a($s2)
glabel L_U_8031D73C
/* 0D873C 8031D73C 1275FE81 */ beq $s3, $s5, .L8031D144
/* 0D8740 8031D740 0013C040 */ sll $t8, $s3, 1
/* 0D8744 8031D744 920C0018 */ lbu $t4, 0x18($s0)
/* 0D8748 8031D748 8E4B0030 */ lw $t3, 0x30($s2)
/* 0D874C 8031D74C 8E0E0000 */ lw $t6, ($s0)
/* 0D8750 8031D750 258D0001 */ addiu $t5, $t4, 1
/* 0D8754 8031D754 31AF00FF */ andi $t7, $t5, 0xff
/* 0D8758 8031D758 000FC880 */ sll $t9, $t7, 2
/* 0D875C 8031D75C 02195021 */ addu $t2, $s0, $t9
/* 0D8760 8031D760 A20D0018 */ sb $t5, 0x18($s0)
/* 0D8764 8031D764 01781021 */ addu $v0, $t3, $t8
/* 0D8768 8031D768 AD4E0000 */ sw $t6, ($t2)
/* 0D876C 8031D76C 904B0000 */ lbu $t3, ($v0)
/* 0D8770 8031D770 90490001 */ lbu $t1, 1($v0)
/* 0D8774 8031D774 8E8D0014 */ lw $t5, 0x14($s4)
/* 0D8778 8031D778 000BC200 */ sll $t8, $t3, 8
/* 0D877C 8031D77C 01383821 */ addu $a3, $t1, $t8
/* 0D8780 8031D780 30ECFFFF */ andi $t4, $a3, 0xffff
/* 0D8784 8031D784 01AC7821 */ addu $t7, $t5, $t4
/* 0D8788 8031D788 1000FE6E */ b .L8031D144
/* 0D878C 8031D78C AE0F0000 */ sw $t7, ($s0)
.L8031D790:
/* 0D8790 8031D790 3064000F */ andi $a0, $v1, 0xf
/* 0D8794 8031D794 2F2100B1 */ sltiu $at, $t9, 0xb1
/* 0D8798 8031D798 1020FE6A */ beqz $at, .L8031D144
/* 0D879C 8031D79C 308800FF */ andi $t0, $a0, 0xff
/* 0D87A0 8031D7A0 0019C880 */ sll $t9, $t9, 2
/* 0D87A4 8031D7A4 3C018034 */ lui $at, %hi(jtbl_80337E04)
/* 0D87A8 8031D7A8 00390821 */ addu $at, $at, $t9
/* 0D87AC 8031D7AC 8C398FBC */ lw $t9, %lo(jtbl_80337E04)($at)
/* 0D87B0 8031D7B0 03200008 */ jr $t9
/* 0D87B4 8031D7B4 00000000 */ nop
glabel L_U_8031D7B8
/* 0D87B8 8031D7B8 308E00FF */ andi $t6, $a0, 0xff
/* 0D87BC 8031D7BC 000E5080 */ sll $t2, $t6, 2
/* 0D87C0 8031D7C0 024A5821 */ addu $t3, $s2, $t2
/* 0D87C4 8031D7C4 8D630044 */ lw $v1, 0x44($t3)
/* 0D87C8 8031D7C8 1060FE5E */ beqz $v1, .L8031D144
/* 0D87CC 8031D7CC 00000000 */ nop
/* 0D87D0 8031D7D0 8C730000 */ lw $s3, ($v1)
/* 0D87D4 8031D7D4 00134840 */ sll $t1, $s3, 1
/* 0D87D8 8031D7D8 0009C7C2 */ srl $t8, $t1, 0x1f
/* 0D87DC 8031D7DC 00186600 */ sll $t4, $t8, 0x18
/* 0D87E0 8031D7E0 1000FE58 */ b .L8031D144
/* 0D87E4 8031D7E4 000C9E03 */ sra $s3, $t4, 0x18
glabel L_U_8031D7E8
/* 0D87E8 8031D7E8 308F00FF */ andi $t7, $a0, 0xff
/* 0D87EC 8031D7EC 024FC821 */ addu $t9, $s2, $t7
/* 0D87F0 8031D7F0 1000FE54 */ b .L8031D144
/* 0D87F4 8031D7F4 A3330054 */ sb $s3, 0x54($t9)
glabel L_U_8031D7F8
/* 0D87F8 8031D7F8 308300FF */ andi $v1, $a0, 0xff
/* 0D87FC 8031D7FC 02432821 */ addu $a1, $s2, $v1
/* 0D8800 8031D800 28610004 */ slti $at, $v1, 4
/* 0D8804 8031D804 1020FE4F */ beqz $at, .L8031D144
/* 0D8808 8031D808 80B30054 */ lb $s3, 0x54($a1)
/* 0D880C 8031D80C 1000FE4D */ b .L8031D144
/* 0D8810 8031D810 A0B50054 */ sb $s5, 0x54($a1)
glabel L_U_8031D814
/* 0D8814 8031D814 308E00FF */ andi $t6, $a0, 0xff
/* 0D8818 8031D818 024E5021 */ addu $t2, $s2, $t6
/* 0D881C 8031D81C 814B0054 */ lb $t3, 0x54($t2)
/* 0D8820 8031D820 026B9823 */ subu $s3, $s3, $t3
/* 0D8824 8031D824 00134E00 */ sll $t1, $s3, 0x18
/* 0D8828 8031D828 1000FE46 */ b .L8031D144
/* 0D882C 8031D82C 00099E03 */ sra $s3, $t1, 0x18
glabel L_U_8031D830
/* 0D8830 8031D830 0C0C7014 */ jal m64_read_s16
/* 0D8834 8031D834 02002025 */ move $a0, $s0
/* 0D8838 8031D838 02201825 */ move $v1, $s1
/* 0D883C 8031D83C 3065000F */ andi $a1, $v1, 0xf
/* 0D8840 8031D840 00A01825 */ move $v1, $a1
/* 0D8844 8031D844 AFA50030 */ sw $a1, 0x30($sp)
/* 0D8848 8031D848 02402025 */ move $a0, $s2
/* 0D884C 8031D84C 0C0C6E50 */ jal seq_channel_set_layer
/* 0D8850 8031D850 A7A20052 */ sh $v0, 0x52($sp)
/* 0D8854 8031D854 8FA30030 */ lw $v1, 0x30($sp)
/* 0D8858 8031D858 1440FE3A */ bnez $v0, .L8031D144
/* 0D885C 8031D85C 97A70052 */ lhu $a3, 0x52($sp)
/* 0D8860 8031D860 8E8D0014 */ lw $t5, 0x14($s4)
/* 0D8864 8031D864 0003C880 */ sll $t9, $v1, 2
/* 0D8868 8031D868 02597021 */ addu $t6, $s2, $t9
/* 0D886C 8031D86C 8DCA0044 */ lw $t2, 0x44($t6)
/* 0D8870 8031D870 01A77821 */ addu $t7, $t5, $a3
/* 0D8874 8031D874 1000FE33 */ b .L8031D144
/* 0D8878 8031D878 AD4F0054 */ sw $t7, 0x54($t2)
glabel L_U_8031D87C
/* 0D887C 8031D87C 02202825 */ move $a1, $s1
/* 0D8880 8031D880 30AB000F */ andi $t3, $a1, 0xf
/* 0D8884 8031D884 01602825 */ move $a1, $t3
/* 0D8888 8031D888 0C0C6E9B */ jal seq_channel_layer_free
/* 0D888C 8031D88C 02402025 */ move $a0, $s2
/* 0D8890 8031D890 1000FE2C */ b .L8031D144
/* 0D8894 8031D894 00000000 */ nop
glabel L_U_8031D898
/* 0D8898 8031D898 1275FE2A */ beq $s3, $s5, .L8031D144
/* 0D889C 8031D89C 02402025 */ move $a0, $s2
/* 0D88A0 8031D8A0 02201825 */ move $v1, $s1
/* 0D88A4 8031D8A4 3065000F */ andi $a1, $v1, 0xf
/* 0D88A8 8031D8A8 00A01825 */ move $v1, $a1
/* 0D88AC 8031D8AC 0C0C6E50 */ jal seq_channel_set_layer
/* 0D88B0 8031D8B0 AFA50030 */ sw $a1, 0x30($sp)
/* 0D88B4 8031D8B4 1055FE23 */ beq $v0, $s5, .L8031D144
/* 0D88B8 8031D8B8 8FA30030 */ lw $v1, 0x30($sp)
/* 0D88BC 8031D8BC 8E580030 */ lw $t8, 0x30($s2)
/* 0D88C0 8031D8C0 00136040 */ sll $t4, $s3, 1
/* 0D88C4 8031D8C4 8E8A0014 */ lw $t2, 0x14($s4)
/* 0D88C8 8031D8C8 030C1021 */ addu $v0, $t8, $t4
/* 0D88CC 8031D8CC 90590000 */ lbu $t9, ($v0)
/* 0D88D0 8031D8D0 904D0001 */ lbu $t5, 1($v0)
/* 0D88D4 8031D8D4 00034880 */ sll $t1, $v1, 2
/* 0D88D8 8031D8D8 00197200 */ sll $t6, $t9, 8
/* 0D88DC 8031D8DC 0249C021 */ addu $t8, $s2, $t1
/* 0D88E0 8031D8E0 01AE3821 */ addu $a3, $t5, $t6
/* 0D88E4 8031D8E4 8F0C0044 */ lw $t4, 0x44($t8)
/* 0D88E8 8031D8E8 30EFFFFF */ andi $t7, $a3, 0xffff
/* 0D88EC 8031D8EC 014F5821 */ addu $t3, $t2, $t7
/* 0D88F0 8031D8F0 1000FE14 */ b .L8031D144
/* 0D88F4 8031D8F4 AD8B0054 */ sw $t3, 0x54($t4)
glabel L_U_8031D8F8
/* 0D88F8 8031D8F8 1000FE12 */ b .L8031D144
/* 0D88FC 8031D8FC A2440004 */ sb $a0, 4($s2)
glabel L_U_8031D900
/* 0D8900 8031D900 0C0C7014 */ jal m64_read_s16
/* 0D8904 8031D904 02002025 */ move $a0, $s0
/* 0D8908 8031D908 8E8D0014 */ lw $t5, 0x14($s4)
/* 0D890C 8031D90C 02202825 */ move $a1, $s1
/* 0D8910 8031D910 30B9000F */ andi $t9, $a1, 0xf
/* 0D8914 8031D914 304EFFFF */ andi $t6, $v0, 0xffff
/* 0D8918 8031D918 03202825 */ move $a1, $t9
/* 0D891C 8031D91C 02802025 */ move $a0, $s4
/* 0D8920 8031D920 0C0C6F68 */ jal sequence_channel_enable
/* 0D8924 8031D924 01AE3021 */ addu $a2, $t5, $t6
/* 0D8928 8031D928 1000FE06 */ b .L8031D144
/* 0D892C 8031D92C 00000000 */ nop
glabel L_U_8031D930
/* 0D8930 8031D930 322A000F */ andi $t2, $s1, 0xf
/* 0D8934 8031D934 000A4880 */ sll $t1, $t2, 2
/* 0D8938 8031D938 0289C021 */ addu $t8, $s4, $t1
/* 0D893C 8031D93C 0C0C6EBC */ jal sequence_channel_disable
/* 0D8940 8031D940 8F04002C */ lw $a0, 0x2c($t8)
/* 0D8944 8031D944 1000FDFF */ b .L8031D144
/* 0D8948 8031D948 00000000 */ nop
glabel L_U_8031D94C
/* 0D894C 8031D94C 02002025 */ move $a0, $s0
/* 0D8950 8031D950 0C0C700F */ jal m64_read_u8
/* 0D8954 8031D954 A3A80055 */ sb $t0, 0x55($sp)
/* 0D8958 8031D958 93A80055 */ lbu $t0, 0x55($sp)
/* 0D895C 8031D95C 00085880 */ sll $t3, $t0, 2
/* 0D8960 8031D960 028B6021 */ addu $t4, $s4, $t3
/* 0D8964 8031D964 8D99002C */ lw $t9, 0x2c($t4)
/* 0D8968 8031D968 03226821 */ addu $t5, $t9, $v0
/* 0D896C 8031D96C 1000FDF5 */ b .L8031D144
/* 0D8970 8031D970 A1B30054 */ sb $s3, 0x54($t5)
glabel L_U_8031D974
/* 0D8974 8031D974 02002025 */ move $a0, $s0
/* 0D8978 8031D978 0C0C700F */ jal m64_read_u8
/* 0D897C 8031D97C A3A80055 */ sb $t0, 0x55($sp)
/* 0D8980 8031D980 93A80055 */ lbu $t0, 0x55($sp)
/* 0D8984 8031D984 00087080 */ sll $t6, $t0, 2
/* 0D8988 8031D988 028E7821 */ addu $t7, $s4, $t6
/* 0D898C 8031D98C 8DEA002C */ lw $t2, 0x2c($t7)
/* 0D8990 8031D990 01424821 */ addu $t1, $t2, $v0
/* 0D8994 8031D994 1000FDEB */ b .L8031D144
/* 0D8998 8031D998 81330054 */ lb $s3, 0x54($t1)
.L8031D99C:
/* 0D899C 8031D99C 02408825 */ move $s1, $s2
.L8031D9A0:
/* 0D89A0 8031D9A0 24120010 */ li $s2, 16
/* 0D89A4 8031D9A4 00008025 */ move $s0, $zero
.L8031D9A8:
/* 0D89A8 8031D9A8 8E240044 */ lw $a0, 0x44($s1)
/* 0D89AC 8031D9AC 50800004 */ beql $a0, $zero, .L8031D9C0
/* 0D89B0 8031D9B0 26100004 */ addiu $s0, $s0, 4
/* 0D89B4 8031D9B4 0C0C7031 */ jal seq_channel_layer_process_script
/* 0D89B8 8031D9B8 00000000 */ nop
/* 0D89BC 8031D9BC 26100004 */ addiu $s0, $s0, 4
.L8031D9C0:
/* 0D89C0 8031D9C0 1612FFF9 */ bne $s0, $s2, .L8031D9A8
/* 0D89C4 8031D9C4 26310004 */ addiu $s1, $s1, 4
.L8031D9C8:
/* 0D89C8 8031D9C8 8FBF002C */ lw $ra, 0x2c($sp)
.L8031D9CC:
/* 0D89CC 8031D9CC 8FB00014 */ lw $s0, 0x14($sp)
/* 0D89D0 8031D9D0 8FB10018 */ lw $s1, 0x18($sp)
/* 0D89D4 8031D9D4 8FB2001C */ lw $s2, 0x1c($sp)
/* 0D89D8 8031D9D8 8FB30020 */ lw $s3, 0x20($sp)
/* 0D89DC 8031D9DC 8FB40024 */ lw $s4, 0x24($sp)
/* 0D89E0 8031D9E0 8FB50028 */ lw $s5, 0x28($sp)
/* 0D89E4 8031D9E4 03E00008 */ jr $ra
/* 0D89E8 8031D9E8 27BD0060 */ addiu $sp, $sp, 0x60
|
96flashbacks/96flashbacks
| 42,312
|
asm/non_matchings/eu/audio/sequence_channel_process_script.s
|
.data
.asciiz "Audio:Track :Call Macro Level Over Error!\n"
.balign 4
.asciiz "Audio:Track :Loops Macro Level Over Error!\n"
.balign 4
.asciiz "SUB:ERR:BANK %d NOT CACHED.\n"
.balign 4
.asciiz "SUB:ERR:BANK %d NOT CACHED.\n"
.balign 4
.asciiz "Audio:Track: CTBLCALL Macro Level Over Error!\n"
.balign 4
.asciiz "Err :Sub %x ,address %x:Undefined SubTrack Function %x"
.balign 4
.late_rodata
.late_rodata_alignment 4
glabel jtbl_EU_80306714
.word L802E8650
.word L802E85A0, L802E866C
.word L802E867C, L802E85BC
.word L802E8888, L802E88E4
.word L802E891C, L802E891C
.word L802E8968, L802E8978
.word L802E891C, L802E8368
.word L802E8368, L802E8368
.word L802E8998, L802E89BC
.word L802E89CC, L802E8714
.word L802E8878, L802E8368
.word L802E8368, L802E87E0
.word L802E87C4, L802E87B4
.word L802E8798, L802E8780
.word L802E8764, L802E8748
.word L802E86E0, L802E868C
.word L802E86B0, L802E8830
.word L802E87FC, L802E8864
.word L802E89EC, L802E89DC
.word L802E8A48, L802E8A58
.word L802E8AC0, L802E8B60
.word L802E83EC, L802E85F8
.word L802E8B38, L802E8368
.word L802E8368, L802E8368
.word L802E8590, L802E8568
.word L802E8520, L802E8520
.word L802E8520, L802E84C8
.word L802E84B8, L802E8470
.word L802E8438, L802E84C8
.word L802E84C8, L802E84C8
.word L802E83FC, L802E83DC
.word L802E8D98, L802E83A4
glabel jtbl_EU_80306810
.word L802E8B9C, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8CFC, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8D2C, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8D48, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8D70, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8C04, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8C20, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8BD4, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8BE4, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8C2C, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8C78, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8368, L802E8368
.word L802E8C94
.text
glabel sequence_channel_process_script
/* 0A7AB8 802E82B8 27BDFFA0 */ addiu $sp, $sp, -0x60
/* 0A7ABC 802E82BC AFBF002C */ sw $ra, 0x2c($sp)
/* 0A7AC0 802E82C0 AFB40028 */ sw $s4, 0x28($sp)
/* 0A7AC4 802E82C4 AFB30024 */ sw $s3, 0x24($sp)
/* 0A7AC8 802E82C8 AFB20020 */ sw $s2, 0x20($sp)
/* 0A7ACC 802E82CC AFB1001C */ sw $s1, 0x1c($sp)
/* 0A7AD0 802E82D0 AFB00018 */ sw $s0, 0x18($sp)
/* 0A7AD4 802E82D4 8C820000 */ lw $v0, ($a0)
/* 0A7AD8 802E82D8 00809025 */ move $s2, $a0
/* 0A7ADC 802E82DC 000277C2 */ srl $t6, $v0, 0x1f
/* 0A7AE0 802E82E0 11C002B8 */ beqz $t6, .L80200BC4
/* 0A7AE4 802E82E4 0002C080 */ sll $t8, $v0, 2
/* 0A7AE8 802E82E8 0701000D */ bgez $t8, .L80200120
/* 0A7AEC 802E82EC 00008025 */ move $s0, $zero
/* 0A7AF0 802E82F0 00808825 */ move $s1, $a0
/* 0A7AF4 802E82F4 24120010 */ li $s2, 16
.L802000F8:
/* 0A7AF8 802E82F8 8E240048 */ lw $a0, 0x48($s1)
/* 0A7AFC 802E82FC 50800004 */ beql $a0, $zero, .L80200110
/* 0A7B00 802E8300 26100004 */ addiu $s0, $s0, 4
/* 0A7B04 802E8304 0C0B9DC2 */ jal seq_channel_layer_process_script
/* 0A7B08 802E8308 00000000 */ nop
/* 0A7B0C 802E830C 26100004 */ addiu $s0, $s0, 4
.L80200110:
/* 0A7B10 802E8310 1612FFF9 */ bne $s0, $s2, .L802000F8
/* 0A7B14 802E8314 26310004 */ addiu $s1, $s1, 4
/* 0A7B18 802E8318 100002AB */ b .L80200BC8
/* 0A7B1C 802E831C 8FBF002C */ lw $ra, 0x2c($sp)
.L80200120:
/* 0A7B20 802E8320 8E540044 */ lw $s4, 0x44($s2)
/* 0A7B24 802E8324 8E990000 */ lw $t9, ($s4)
/* 0A7B28 802E8328 00195080 */ sll $t2, $t9, 2
/* 0A7B2C 802E832C 05430006 */ bgezl $t2, .L80200148
/* 0A7B30 802E8330 9643001A */ lhu $v1, 0x1a($s2)
/* 0A7B34 802E8334 924B0003 */ lbu $t3, 3($s2)
/* 0A7B38 802E8338 316C0080 */ andi $t4, $t3, 0x80
/* 0A7B3C 802E833C 558002A2 */ bnezl $t4, .L80200BC8
/* 0A7B40 802E8340 8FBF002C */ lw $ra, 0x2c($sp)
/* 0A7B44 802E8344 9643001A */ lhu $v1, 0x1a($s2)
.L80200148:
/* 0A7B48 802E8348 26510060 */ addiu $s1, $s2, 0x60
/* 0A7B4C 802E834C 10600004 */ beqz $v1, .L80200160
/* 0A7B50 802E8350 00601025 */ move $v0, $v1
/* 0A7B54 802E8354 246DFFFF */ addiu $t5, $v1, -1
/* 0A7B58 802E8358 A64D001A */ sh $t5, 0x1a($s2)
/* 0A7B5C 802E835C 31A2FFFF */ andi $v0, $t5, 0xffff
.L80200160:
/* 0A7B60 802E8360 1440028D */ bnez $v0, .L802E8D98
/* 0A7B64 802E8364 83B3004B */ lb $s3, 0x4b($sp)
glabel L802E8368
.L802E8368:
/* 0A7B68 802E8368 0C0B9DA0 */ jal m64_read_u8
/* 0A7B6C 802E836C 02202025 */ move $a0, $s1
/* 0A7B70 802E8370 284100C1 */ slti $at, $v0, 0xc1
/* 0A7B74 802E8374 305000FF */ andi $s0, $v0, 0xff
/* 0A7B78 802E8378 142001FD */ bnez $at, .L80200970
/* 0A7B7C 802E837C 00401825 */ move $v1, $v0
/* 0A7B80 802E8380 244EFF3F */ addiu $t6, $v0, -0xc1
/* 0A7B84 802E8384 2DC1003F */ sltiu $at, $t6, 0x3f
/* 0A7B88 802E8388 1020FFF7 */ beqz $at, .L802E8368
/* 0A7B8C 802E838C 000E7080 */ sll $t6, $t6, 2
/* 0A7B90 802E8390 3C018030 */ lui $at, %hi(jtbl_EU_80306714)
/* 0A7B94 802E8394 002E0821 */ addu $at, $at, $t6
/* 0A7B98 802E8398 8C2E6714 */ lw $t6, %lo(jtbl_EU_80306714)($at)
/* 0A7B9C 802E839C 01C00008 */ jr $t6
/* 0A7BA0 802E83A0 00000000 */ nop
glabel L802E83A4
/* 0A7BA4 802E83A4 92240018 */ lbu $a0, 0x18($s1)
/* 0A7BA8 802E83A8 14800005 */ bnez $a0, .L802001C0
/* 0A7BAC 802E83AC 2482FFFF */ addiu $v0, $a0, -1
/* 0A7BB0 802E83B0 0C0B9C41 */ jal sequence_channel_disable
/* 0A7BB4 802E83B4 02402025 */ move $a0, $s2
/* 0A7BB8 802E83B8 10000278 */ b .L80200B9C
/* 0A7BBC 802E83BC 02408825 */ move $s1, $s2
.L802001C0:
/* 0A7BC0 802E83C0 304F00FF */ andi $t7, $v0, 0xff
/* 0A7BC4 802E83C4 000FC080 */ sll $t8, $t7, 2
/* 0A7BC8 802E83C8 0238C821 */ addu $t9, $s1, $t8
/* 0A7BCC 802E83CC A22F0018 */ sb $t7, 0x18($s1)
/* 0A7BD0 802E83D0 8F290004 */ lw $t1, 4($t9)
/* 0A7BD4 802E83D4 1000FFE4 */ b .L802E8368
/* 0A7BD8 802E83D8 AE290000 */ sw $t1, ($s1)
glabel L802E83DC
/* 0A7BDC 802E83DC 0C0B9DB1 */ jal m64_read_compressed_u16
/* 0A7BE0 802E83E0 02202025 */ move $a0, $s1
/* 0A7BE4 802E83E4 1000026C */ b .L802E8D98
/* 0A7BE8 802E83E8 A642001A */ sh $v0, 0x1a($s2)
glabel L802E83EC
/* 0A7BEC 802E83EC 924B0000 */ lbu $t3, ($s2)
/* 0A7BF0 802E83F0 356C0020 */ ori $t4, $t3, 0x20
/* 0A7BF4 802E83F4 10000268 */ b .L802E8D98
/* 0A7BF8 802E83F8 A24C0000 */ sb $t4, ($s2)
glabel L802E83FC
/* 0A7BFC 802E83FC 0C0B9DA5 */ jal m64_read_s16
/* 0A7C00 802E8400 02202025 */ move $a0, $s1
/* 0A7C04 802E8404 922E0018 */ lbu $t6, 0x18($s1)
/* 0A7C08 802E8408 8E2D0000 */ lw $t5, ($s1)
/* 0A7C0C 802E840C 304BFFFF */ andi $t3, $v0, 0xffff
/* 0A7C10 802E8410 000E7880 */ sll $t7, $t6, 2
/* 0A7C14 802E8414 022FC021 */ addu $t8, $s1, $t7
/* 0A7C18 802E8418 AF0D0004 */ sw $t5, 4($t8)
/* 0A7C1C 802E841C 92390018 */ lbu $t9, 0x18($s1)
/* 0A7C20 802E8420 27290001 */ addiu $t1, $t9, 1
/* 0A7C24 802E8424 A2290018 */ sb $t1, 0x18($s1)
/* 0A7C28 802E8428 8E8A0014 */ lw $t2, 0x14($s4)
/* 0A7C2C 802E842C 014B6021 */ addu $t4, $t2, $t3
/* 0A7C30 802E8430 1000FFCD */ b .L802E8368
/* 0A7C34 802E8434 AE2C0000 */ sw $t4, ($s1)
glabel L802E8438
/* 0A7C38 802E8438 0C0B9DA0 */ jal m64_read_u8
/* 0A7C3C 802E843C 02202025 */ move $a0, $s1
/* 0A7C40 802E8440 922E0018 */ lbu $t6, 0x18($s1)
/* 0A7C44 802E8444 022E7821 */ addu $t7, $s1, $t6
/* 0A7C48 802E8448 A1E20014 */ sb $v0, 0x14($t7)
/* 0A7C4C 802E844C 92380018 */ lbu $t8, 0x18($s1)
/* 0A7C50 802E8450 8E2D0000 */ lw $t5, ($s1)
/* 0A7C54 802E8454 0018C880 */ sll $t9, $t8, 2
/* 0A7C58 802E8458 02394821 */ addu $t1, $s1, $t9
/* 0A7C5C 802E845C AD2D0004 */ sw $t5, 4($t1)
/* 0A7C60 802E8460 922A0018 */ lbu $t2, 0x18($s1)
/* 0A7C64 802E8464 254B0001 */ addiu $t3, $t2, 1
/* 0A7C68 802E8468 1000FFBF */ b .L802E8368
/* 0A7C6C 802E846C A22B0018 */ sb $t3, 0x18($s1)
glabel L802E8470
/* 0A7C70 802E8470 922C0018 */ lbu $t4, 0x18($s1)
/* 0A7C74 802E8474 022C1021 */ addu $v0, $s1, $t4
/* 0A7C78 802E8478 904E0013 */ lbu $t6, 0x13($v0)
/* 0A7C7C 802E847C 25CFFFFF */ addiu $t7, $t6, -1
/* 0A7C80 802E8480 A04F0013 */ sb $t7, 0x13($v0)
/* 0A7C84 802E8484 92240018 */ lbu $a0, 0x18($s1)
/* 0A7C88 802E8488 0224C021 */ addu $t8, $s1, $a0
/* 0A7C8C 802E848C 93190013 */ lbu $t9, 0x13($t8)
/* 0A7C90 802E8490 00801825 */ move $v1, $a0
/* 0A7C94 802E8494 00036880 */ sll $t5, $v1, 2
/* 0A7C98 802E8498 13200005 */ beqz $t9, .L802002B0
/* 0A7C9C 802E849C 248BFFFF */ addiu $t3, $a0, -1
/* 0A7CA0 802E84A0 022D4821 */ addu $t1, $s1, $t5
/* 0A7CA4 802E84A4 8D2A0000 */ lw $t2, ($t1)
/* 0A7CA8 802E84A8 1000FFAF */ b .L802E8368
/* 0A7CAC 802E84AC AE2A0000 */ sw $t2, ($s1)
.L802002B0:
/* 0A7CB0 802E84B0 1000FFAD */ b .L802E8368
/* 0A7CB4 802E84B4 A22B0018 */ sb $t3, 0x18($s1)
glabel L802E84B8
/* 0A7CB8 802E84B8 922C0018 */ lbu $t4, 0x18($s1)
/* 0A7CBC 802E84BC 258EFFFF */ addiu $t6, $t4, -1
/* 0A7CC0 802E84C0 1000FFA9 */ b .L802E8368
/* 0A7CC4 802E84C4 A22E0018 */ sb $t6, 0x18($s1)
glabel L802E84C8
/* 0A7CC8 802E84C8 0C0B9DA5 */ jal m64_read_s16
/* 0A7CCC 802E84CC 02202025 */ move $a0, $s1
/* 0A7CD0 802E84D0 240100FA */ li $at, 250
/* 0A7CD4 802E84D4 16010003 */ bne $s0, $at, .L802002E4
/* 0A7CD8 802E84D8 02001825 */ move $v1, $s0
/* 0A7CDC 802E84DC 1660FFA2 */ bnez $s3, .L802E8368
/* 0A7CE0 802E84E0 00000000 */ nop
.L802002E4:
/* 0A7CE4 802E84E4 240100F9 */ li $at, 249
/* 0A7CE8 802E84E8 54610004 */ bnel $v1, $at, .L802002FC
/* 0A7CEC 802E84EC 240100F5 */ li $at, 245
/* 0A7CF0 802E84F0 0661FF9D */ bgez $s3, .L802E8368
/* 0A7CF4 802E84F4 00000000 */ nop
/* 0A7CF8 802E84F8 240100F5 */ li $at, 245
.L802002FC:
/* 0A7CFC 802E84FC 54610004 */ bnel $v1, $at, .L80200310
/* 0A7D00 802E8500 8E8F0014 */ lw $t7, 0x14($s4)
/* 0A7D04 802E8504 0660FF98 */ bltz $s3, .L802E8368
/* 0A7D08 802E8508 00000000 */ nop
/* 0A7D0C 802E850C 8E8F0014 */ lw $t7, 0x14($s4)
.L80200310:
/* 0A7D10 802E8510 3058FFFF */ andi $t8, $v0, 0xffff
/* 0A7D14 802E8514 01F8C821 */ addu $t9, $t7, $t8
/* 0A7D18 802E8518 1000FF93 */ b .L802E8368
/* 0A7D1C 802E851C AE390000 */ sw $t9, ($s1)
glabel L802E8520
/* 0A7D20 802E8520 0C0B9DA0 */ jal m64_read_u8
/* 0A7D24 802E8524 02202025 */ move $a0, $s1
/* 0A7D28 802E8528 240100F3 */ li $at, 243
/* 0A7D2C 802E852C 16010003 */ bne $s0, $at, .L8020033C
/* 0A7D30 802E8530 02001825 */ move $v1, $s0
/* 0A7D34 802E8534 1660FF8C */ bnez $s3, .L802E8368
/* 0A7D38 802E8538 00000000 */ nop
.L8020033C:
/* 0A7D3C 802E853C 240100F2 */ li $at, 242
/* 0A7D40 802E8540 54610004 */ bnel $v1, $at, .L80200354
/* 0A7D44 802E8544 8E2D0000 */ lw $t5, ($s1)
/* 0A7D48 802E8548 0661FF87 */ bgez $s3, .L802E8368
/* 0A7D4C 802E854C 00000000 */ nop
/* 0A7D50 802E8550 8E2D0000 */ lw $t5, ($s1)
.L80200354:
/* 0A7D54 802E8554 00024E00 */ sll $t1, $v0, 0x18
/* 0A7D58 802E8558 00095603 */ sra $t2, $t1, 0x18
/* 0A7D5C 802E855C 01AA5821 */ addu $t3, $t5, $t2
/* 0A7D60 802E8560 1000FF81 */ b .L802E8368
/* 0A7D64 802E8564 AE2B0000 */ sw $t3, ($s1)
glabel L802E8568
/* 0A7D68 802E8568 26500084 */ addiu $s0, $s2, 0x84
/* 0A7D6C 802E856C 0C0B9671 */ jal note_pool_clear
/* 0A7D70 802E8570 02002025 */ move $a0, $s0
/* 0A7D74 802E8574 0C0B9DA0 */ jal m64_read_u8
/* 0A7D78 802E8578 02202025 */ move $a0, $s1
/* 0A7D7C 802E857C 02002025 */ move $a0, $s0
/* 0A7D80 802E8580 0C0B96C9 */ jal note_pool_fill
/* 0A7D84 802E8584 00402825 */ move $a1, $v0
/* 0A7D88 802E8588 1000FF77 */ b .L802E8368
/* 0A7D8C 802E858C 00000000 */ nop
glabel L802E8590
/* 0A7D90 802E8590 0C0B9671 */ jal note_pool_clear
/* 0A7D94 802E8594 26440084 */ addiu $a0, $s2, 0x84
/* 0A7D98 802E8598 1000FF73 */ b .L802E8368
/* 0A7D9C 802E859C 00000000 */ nop
glabel L802E85A0
/* 0A7DA0 802E85A0 0C0B9DA5 */ jal m64_read_s16
/* 0A7DA4 802E85A4 02202025 */ move $a0, $s1
/* 0A7DA8 802E85A8 8E8C0014 */ lw $t4, 0x14($s4)
/* 0A7DAC 802E85AC 304EFFFF */ andi $t6, $v0, 0xffff
/* 0A7DB0 802E85B0 018E7821 */ addu $t7, $t4, $t6
/* 0A7DB4 802E85B4 1000FF6C */ b .L802E8368
/* 0A7DB8 802E85B8 AE4F0034 */ sw $t7, 0x34($s2)
glabel L802E85BC
/* 0A7DBC 802E85BC 2401FFFF */ li $at, -1
/* 0A7DC0 802E85C0 1261FF69 */ beq $s3, $at, .L802E8368
/* 0A7DC4 802E85C4 00000000 */ nop
/* 0A7DC8 802E85C8 8E580034 */ lw $t8, 0x34($s2)
/* 0A7DCC 802E85CC 0013C840 */ sll $t9, $s3, 1
/* 0A7DD0 802E85D0 8E8C0014 */ lw $t4, 0x14($s4)
/* 0A7DD4 802E85D4 03191821 */ addu $v1, $t8, $t9
/* 0A7DD8 802E85D8 906D0000 */ lbu $t5, ($v1)
/* 0A7DDC 802E85DC 90690001 */ lbu $t1, 1($v1)
/* 0A7DE0 802E85E0 000D5200 */ sll $t2, $t5, 8
/* 0A7DE4 802E85E4 012A3821 */ addu $a3, $t1, $t2
/* 0A7DE8 802E85E8 30EBFFFF */ andi $t3, $a3, 0xffff
/* 0A7DEC 802E85EC 018B7021 */ addu $t6, $t4, $t3
/* 0A7DF0 802E85F0 1000FF5D */ b .L802E8368
/* 0A7DF4 802E85F4 AE4E0034 */ sw $t6, 0x34($s2)
glabel L802E85F8
/* 0A7DF8 802E85F8 0C0B9DA0 */ jal m64_read_u8
/* 0A7DFC 802E85FC 02202025 */ move $a0, $s1
/* 0A7E00 802E8600 928F0004 */ lbu $t7, 4($s4)
/* 0A7E04 802E8604 3C038023 */ lui $v1, %hi(gAlBankSets) # $v1, 0x8023
/* 0A7E08 802E8608 8C6397D0 */ lw $v1, %lo(gAlBankSets)($v1)
/* 0A7E0C 802E860C 000FC040 */ sll $t8, $t7, 1
/* 0A7E10 802E8610 3C048022 */ lui $a0, %hi(gBankLoadedPool) # $a0, 0x8022
/* 0A7E14 802E8614 0078C821 */ addu $t9, $v1, $t8
/* 0A7E18 802E8618 97270000 */ lhu $a3, ($t9)
/* 0A7E1C 802E861C 24842840 */ addiu $a0, %lo(gBankLoadedPool) # addiu $a0, $a0, 0x2840
/* 0A7E20 802E8620 24050002 */ li $a1, 2
/* 0A7E24 802E8624 00E36821 */ addu $t5, $a3, $v1
/* 0A7E28 802E8628 91A80000 */ lbu $t0, ($t5)
/* 0A7E2C 802E862C 00E84821 */ addu $t1, $a3, $t0
/* 0A7E30 802E8630 01225023 */ subu $t2, $t1, $v0
/* 0A7E34 802E8634 01435821 */ addu $t3, $t2, $v1
/* 0A7E38 802E8638 91700000 */ lbu $s0, ($t3)
/* 0A7E3C 802E863C 0C0B89CF */ jal get_bank_or_seq
/* 0A7E40 802E8640 02003025 */ move $a2, $s0
/* 0A7E44 802E8644 10400002 */ beqz $v0, .L802E8650
/* 0A7E48 802E8648 00000000 */ nop
/* 0A7E4C 802E864C A2500006 */ sb $s0, 6($s2)
glabel L802E8650
.L802E8650:
/* 0A7E50 802E8650 0C0B9DA0 */ jal m64_read_u8
/* 0A7E54 802E8654 02202025 */ move $a0, $s1
/* 0A7E58 802E8658 02402025 */ move $a0, $s2
/* 0A7E5C 802E865C 0C0BA080 */ jal set_instrument
/* 0A7E60 802E8660 304500FF */ andi $a1, $v0, 0xff
/* 0A7E64 802E8664 1000FF40 */ b .L802E8368
/* 0A7E68 802E8668 00000000 */ nop
glabel L802E866C
/* 0A7E6C 802E866C 924C0000 */ lbu $t4, ($s2)
/* 0A7E70 802E8670 318EFFFD */ andi $t6, $t4, 0xfffd
/* 0A7E74 802E8674 1000FF3C */ b .L802E8368
/* 0A7E78 802E8678 A24E0000 */ sb $t6, ($s2)
glabel L802E867C
/* 0A7E7C 802E867C 92580000 */ lbu $t8, ($s2)
/* 0A7E80 802E8680 37190002 */ ori $t9, $t8, 2
/* 0A7E84 802E8684 1000FF38 */ b .L802E8368
/* 0A7E88 802E8688 A2590000 */ sb $t9, ($s2)
glabel L802E868C
/* 0A7E8C 802E868C 0C0B9DA0 */ jal m64_read_u8
/* 0A7E90 802E8690 02202025 */ move $a0, $s1
/* 0A7E94 802E8694 02402025 */ move $a0, $s2
/* 0A7E98 802E8698 0C0BA0A5 */ jal sequence_channel_set_volume
/* 0A7E9C 802E869C 304500FF */ andi $a1, $v0, 0xff
/* 0A7EA0 802E86A0 92490001 */ lbu $t1, 1($s2)
/* 0A7EA4 802E86A4 352A0040 */ ori $t2, $t1, 0x40
/* 0A7EA8 802E86A8 1000FF2F */ b .L802E8368
/* 0A7EAC 802E86AC A24A0001 */ sb $t2, 1($s2)
glabel L802E86B0
/* 0A7EB0 802E86B0 0C0B9DA0 */ jal m64_read_u8
/* 0A7EB4 802E86B4 02202025 */ move $a0, $s1
/* 0A7EB8 802E86B8 44822000 */ mtc1 $v0, $f4
/* 0A7EBC 802E86BC 3C013C00 */ li $at, 0x3C000000 # 0.007812
/* 0A7EC0 802E86C0 44814000 */ mtc1 $at, $f8
/* 0A7EC4 802E86C4 468021A0 */ cvt.s.w $f6, $f4
/* 0A7EC8 802E86C8 924C0001 */ lbu $t4, 1($s2)
/* 0A7ECC 802E86CC 358E0040 */ ori $t6, $t4, 0x40
/* 0A7ED0 802E86D0 A24E0001 */ sb $t6, 1($s2)
/* 0A7ED4 802E86D4 46083282 */ mul.s $f10, $f6, $f8
/* 0A7ED8 802E86D8 1000FF23 */ b .L802E8368
/* 0A7EDC 802E86DC E64A0020 */ swc1 $f10, 0x20($s2)
glabel L802E86E0
/* 0A7EE0 802E86E0 0C0B9DA5 */ jal m64_read_s16
/* 0A7EE4 802E86E4 02202025 */ move $a0, $s1
/* 0A7EE8 802E86E8 304FFFFF */ andi $t7, $v0, 0xffff
/* 0A7EEC 802E86EC 448F8000 */ mtc1 $t7, $f16
/* 0A7EF0 802E86F0 3C014700 */ li $at, 0x47000000 # 32768.000000
/* 0A7EF4 802E86F4 44812000 */ mtc1 $at, $f4
/* 0A7EF8 802E86F8 468084A0 */ cvt.s.w $f18, $f16
/* 0A7EFC 802E86FC 92590001 */ lbu $t9, 1($s2)
/* 0A7F00 802E8700 372D0080 */ ori $t5, $t9, 0x80
/* 0A7F04 802E8704 A24D0001 */ sb $t5, 1($s2)
/* 0A7F08 802E8708 46049183 */ div.s $f6, $f18, $f4
/* 0A7F0C 802E870C 1000FF16 */ b .L802E8368
/* 0A7F10 802E8710 E6460030 */ swc1 $f6, 0x30($s2)
glabel L802E8714
/* 0A7F14 802E8714 0C0B9DA0 */ jal m64_read_u8
/* 0A7F18 802E8718 02202025 */ move $a0, $s1
/* 0A7F1C 802E871C 2449007F */ addiu $t1, $v0, 0x7f
/* 0A7F20 802E8720 312A00FF */ andi $t2, $t1, 0xff
/* 0A7F24 802E8724 924E0001 */ lbu $t6, 1($s2)
/* 0A7F28 802E8728 000A5880 */ sll $t3, $t2, 2
/* 0A7F2C 802E872C 3C018030 */ lui $at, %hi(gPitchBendFrequencyScale)
/* 0A7F30 802E8730 002B0821 */ addu $at, $at, $t3
/* 0A7F34 802E8734 C42806E8 */ lwc1 $f8, %lo(gPitchBendFrequencyScale)($at)
/* 0A7F38 802E8738 35CF0080 */ ori $t7, $t6, 0x80
/* 0A7F3C 802E873C A24F0001 */ sb $t7, 1($s2)
/* 0A7F40 802E8740 1000FF09 */ b .L802E8368
/* 0A7F44 802E8744 E6480030 */ swc1 $f8, 0x30($s2)
glabel L802E8748
/* 0A7F48 802E8748 0C0B9DA0 */ jal m64_read_u8
/* 0A7F4C 802E874C 02202025 */ move $a0, $s1
/* 0A7F50 802E8750 92590001 */ lbu $t9, 1($s2)
/* 0A7F54 802E8754 A2420009 */ sb $v0, 9($s2)
/* 0A7F58 802E8758 372D0020 */ ori $t5, $t9, 0x20
/* 0A7F5C 802E875C 1000FF02 */ b .L802E8368
/* 0A7F60 802E8760 A24D0001 */ sb $t5, 1($s2)
glabel L802E8764
/* 0A7F64 802E8764 0C0B9DA0 */ jal m64_read_u8
/* 0A7F68 802E8768 02202025 */ move $a0, $s1
/* 0A7F6C 802E876C 924A0001 */ lbu $t2, 1($s2)
/* 0A7F70 802E8770 A242000A */ sb $v0, 0xa($s2)
/* 0A7F74 802E8774 354B0020 */ ori $t3, $t2, 0x20
/* 0A7F78 802E8778 1000FEFB */ b .L802E8368
/* 0A7F7C 802E877C A24B0001 */ sb $t3, 1($s2)
glabel L802E8780
/* 0A7F80 802E8780 8E220000 */ lw $v0, ($s1)
/* 0A7F84 802E8784 80430000 */ lb $v1, ($v0)
/* 0A7F88 802E8788 244C0001 */ addiu $t4, $v0, 1
/* 0A7F8C 802E878C AE2C0000 */ sw $t4, ($s1)
/* 0A7F90 802E8790 1000FEF5 */ b .L802E8368
/* 0A7F94 802E8794 A643001E */ sh $v1, 0x1e($s2)
glabel L802E8798
/* 0A7F98 802E8798 0C0B9DA5 */ jal m64_read_s16
/* 0A7F9C 802E879C 02202025 */ move $a0, $s1
/* 0A7FA0 802E87A0 8E8E0014 */ lw $t6, 0x14($s4)
/* 0A7FA4 802E87A4 304FFFFF */ andi $t7, $v0, 0xffff
/* 0A7FA8 802E87A8 01CFC021 */ addu $t8, $t6, $t7
/* 0A7FAC 802E87AC 1000FEEE */ b .L802E8368
/* 0A7FB0 802E87B0 AE580080 */ sw $t8, 0x80($s2)
glabel L802E87B4
/* 0A7FB4 802E87B4 0C0B9DA0 */ jal m64_read_u8
/* 0A7FB8 802E87B8 02202025 */ move $a0, $s1
/* 0A7FBC 802E87BC 1000FEEA */ b .L802E8368
/* 0A7FC0 802E87C0 A242007C */ sb $v0, 0x7c($s2)
glabel L802E87C4
/* 0A7FC4 802E87C4 0C0B9DA0 */ jal m64_read_u8
/* 0A7FC8 802E87C8 02202025 */ move $a0, $s1
/* 0A7FCC 802E87CC 0002C8C0 */ sll $t9, $v0, 3
/* 0A7FD0 802E87D0 A6590012 */ sh $t9, 0x12($s2)
/* 0A7FD4 802E87D4 A640000E */ sh $zero, 0xe($s2)
/* 0A7FD8 802E87D8 1000FEE3 */ b .L802E8368
/* 0A7FDC 802E87DC A6400016 */ sh $zero, 0x16($s2)
glabel L802E87E0
/* 0A7FE0 802E87E0 0C0B9DA0 */ jal m64_read_u8
/* 0A7FE4 802E87E4 02202025 */ move $a0, $s1
/* 0A7FE8 802E87E8 00021940 */ sll $v1, $v0, 5
/* 0A7FEC 802E87EC A6430010 */ sh $v1, 0x10($s2)
/* 0A7FF0 802E87F0 A643000C */ sh $v1, 0xc($s2)
/* 0A7FF4 802E87F4 1000FEDC */ b .L802E8368
/* 0A7FF8 802E87F8 A6400014 */ sh $zero, 0x14($s2)
glabel L802E87FC
/* 0A7FFC 802E87FC 0C0B9DA0 */ jal m64_read_u8
/* 0A8000 802E8800 02202025 */ move $a0, $s1
/* 0A8004 802E8804 000268C0 */ sll $t5, $v0, 3
/* 0A8008 802E8808 A64D000E */ sh $t5, 0xe($s2)
/* 0A800C 802E880C 0C0B9DA0 */ jal m64_read_u8
/* 0A8010 802E8810 02202025 */ move $a0, $s1
/* 0A8014 802E8814 000248C0 */ sll $t1, $v0, 3
/* 0A8018 802E8818 A6490012 */ sh $t1, 0x12($s2)
/* 0A801C 802E881C 0C0B9DA0 */ jal m64_read_u8
/* 0A8020 802E8820 02202025 */ move $a0, $s1
/* 0A8024 802E8824 00025100 */ sll $t2, $v0, 4
/* 0A8028 802E8828 1000FECF */ b .L802E8368
/* 0A802C 802E882C A64A0016 */ sh $t2, 0x16($s2)
glabel L802E8830
/* 0A8030 802E8830 0C0B9DA0 */ jal m64_read_u8
/* 0A8034 802E8834 02202025 */ move $a0, $s1
/* 0A8038 802E8838 00025940 */ sll $t3, $v0, 5
/* 0A803C 802E883C A64B000C */ sh $t3, 0xc($s2)
/* 0A8040 802E8840 0C0B9DA0 */ jal m64_read_u8
/* 0A8044 802E8844 02202025 */ move $a0, $s1
/* 0A8048 802E8848 00026140 */ sll $t4, $v0, 5
/* 0A804C 802E884C A64C0010 */ sh $t4, 0x10($s2)
/* 0A8050 802E8850 0C0B9DA0 */ jal m64_read_u8
/* 0A8054 802E8854 02202025 */ move $a0, $s1
/* 0A8058 802E8858 00027100 */ sll $t6, $v0, 4
/* 0A805C 802E885C 1000FEC2 */ b .L802E8368
/* 0A8060 802E8860 A64E0014 */ sh $t6, 0x14($s2)
glabel L802E8864
/* 0A8064 802E8864 0C0B9DA0 */ jal m64_read_u8
/* 0A8068 802E8868 02202025 */ move $a0, $s1
/* 0A806C 802E886C 00027900 */ sll $t7, $v0, 4
/* 0A8070 802E8870 1000FEBD */ b .L802E8368
/* 0A8074 802E8874 A64F0018 */ sh $t7, 0x18($s2)
glabel L802E8878
/* 0A8078 802E8878 0C0B9DA0 */ jal m64_read_u8
/* 0A807C 802E887C 02202025 */ move $a0, $s1
/* 0A8080 802E8880 1000FEB9 */ b .L802E8368
/* 0A8084 802E8884 A2420004 */ sb $v0, 4($s2)
glabel L802E8888
/* 0A8088 802E8888 0C0B9DA0 */ jal m64_read_u8
/* 0A808C 802E888C 02202025 */ move $a0, $s1
/* 0A8090 802E8890 92980004 */ lbu $t8, 4($s4)
/* 0A8094 802E8894 3C038023 */ lui $v1, %hi(gAlBankSets) # $v1, 0x8023
/* 0A8098 802E8898 8C6397D0 */ lw $v1, %lo(gAlBankSets)($v1)
/* 0A809C 802E889C 0018C840 */ sll $t9, $t8, 1
/* 0A80A0 802E88A0 3C048022 */ lui $a0, %hi(gBankLoadedPool) # $a0, 0x8022
/* 0A80A4 802E88A4 00796821 */ addu $t5, $v1, $t9
/* 0A80A8 802E88A8 95A70000 */ lhu $a3, ($t5)
/* 0A80AC 802E88AC 24842840 */ addiu $a0, %lo(gBankLoadedPool) # addiu $a0, $a0, 0x2840
/* 0A80B0 802E88B0 24050002 */ li $a1, 2
/* 0A80B4 802E88B4 00E34821 */ addu $t1, $a3, $v1
/* 0A80B8 802E88B8 91280000 */ lbu $t0, ($t1)
/* 0A80BC 802E88BC 00E85021 */ addu $t2, $a3, $t0
/* 0A80C0 802E88C0 01425823 */ subu $t3, $t2, $v0
/* 0A80C4 802E88C4 01636021 */ addu $t4, $t3, $v1
/* 0A80C8 802E88C8 91900000 */ lbu $s0, ($t4)
/* 0A80CC 802E88CC 0C0B89CF */ jal get_bank_or_seq
/* 0A80D0 802E88D0 02003025 */ move $a2, $s0
/* 0A80D4 802E88D4 1040FEA4 */ beqz $v0, .L802E8368
/* 0A80D8 802E88D8 00000000 */ nop
/* 0A80DC 802E88DC 1000FEA2 */ b .L802E8368
/* 0A80E0 802E88E0 A2500006 */ sb $s0, 6($s2)
glabel L802E88E4
/* 0A80E4 802E88E4 326E00FF */ andi $t6, $s3, 0xff
/* 0A80E8 802E88E8 AFAE0034 */ sw $t6, 0x34($sp)
/* 0A80EC 802E88EC 0C0B9DA0 */ jal m64_read_u8
/* 0A80F0 802E88F0 02202025 */ move $a0, $s1
/* 0A80F4 802E88F4 305000FF */ andi $s0, $v0, 0xff
/* 0A80F8 802E88F8 0C0B9DA5 */ jal m64_read_s16
/* 0A80FC 802E88FC 02202025 */ move $a0, $s1
/* 0A8100 802E8900 8E8F0014 */ lw $t7, 0x14($s4)
/* 0A8104 802E8904 8FB90034 */ lw $t9, 0x34($sp)
/* 0A8108 802E8908 3058FFFF */ andi $t8, $v0, 0xffff
/* 0A810C 802E890C 01F81821 */ addu $v1, $t7, $t8
/* 0A8110 802E8910 03306821 */ addu $t5, $t9, $s0
/* 0A8114 802E8914 1000FE94 */ b .L802E8368
/* 0A8118 802E8918 A06D0000 */ sb $t5, ($v1)
glabel L802E891C
/* 0A811C 802E891C 0C0B9DA0 */ jal m64_read_u8
/* 0A8120 802E8920 02202025 */ move $a0, $s1
/* 0A8124 802E8924 240100C8 */ li $at, 200
/* 0A8128 802E8928 16010005 */ bne $s0, $at, .L80200740
/* 0A812C 802E892C 02001825 */ move $v1, $s0
/* 0A8130 802E8930 02629823 */ subu $s3, $s3, $v0
/* 0A8134 802E8934 00135E00 */ sll $t3, $s3, 0x18
/* 0A8138 802E8938 1000FE8B */ b .L802E8368
/* 0A813C 802E893C 000B9E03 */ sra $s3, $t3, 0x18
.L80200740:
/* 0A8140 802E8940 240100CC */ li $at, 204
/* 0A8144 802E8944 14610005 */ bne $v1, $at, .L8020075C
/* 0A8148 802E8948 02629824 */ and $s3, $s3, $v0
/* 0A814C 802E894C 00029E00 */ sll $s3, $v0, 0x18
/* 0A8150 802E8950 00137603 */ sra $t6, $s3, 0x18
/* 0A8154 802E8954 1000FE84 */ b .L802E8368
/* 0A8158 802E8958 01C09825 */ move $s3, $t6
.L8020075C:
/* 0A815C 802E895C 0013CE00 */ sll $t9, $s3, 0x18
/* 0A8160 802E8960 1000FE81 */ b .L802E8368
/* 0A8164 802E8964 00199E03 */ sra $s3, $t9, 0x18
glabel L802E8968
/* 0A8168 802E8968 0C0B9DA0 */ jal m64_read_u8
/* 0A816C 802E896C 02202025 */ move $a0, $s1
/* 0A8170 802E8970 1000FE7D */ b .L802E8368
/* 0A8174 802E8974 A2420003 */ sb $v0, 3($s2)
glabel L802E8978
/* 0A8178 802E8978 0C0B9DA5 */ jal m64_read_s16
/* 0A817C 802E897C 02202025 */ move $a0, $s1
/* 0A8180 802E8980 8E890014 */ lw $t1, 0x14($s4)
/* 0A8184 802E8984 304AFFFF */ andi $t2, $v0, 0xffff
/* 0A8188 802E8988 01535821 */ addu $t3, $t2, $s3
/* 0A818C 802E898C 012B6021 */ addu $t4, $t1, $t3
/* 0A8190 802E8990 1000FE75 */ b .L802E8368
/* 0A8194 802E8994 81930000 */ lb $s3, ($t4)
glabel L802E8998
/* 0A8198 802E8998 0C0B9DA0 */ jal m64_read_u8
/* 0A819C 802E899C 02202025 */ move $a0, $s1
/* 0A81A0 802E89A0 92590000 */ lbu $t9, ($s2)
/* 0A81A4 802E89A4 00027880 */ sll $t7, $v0, 2
/* 0A81A8 802E89A8 31F80004 */ andi $t8, $t7, 4
/* 0A81AC 802E89AC 332DFFFB */ andi $t5, $t9, 0xfffb
/* 0A81B0 802E89B0 030D5025 */ or $t2, $t8, $t5
/* 0A81B4 802E89B4 1000FE6C */ b .L802E8368
/* 0A81B8 802E89B8 A24A0000 */ sb $t2, ($s2)
glabel L802E89BC
/* 0A81BC 802E89BC 0C0B9DA0 */ jal m64_read_u8
/* 0A81C0 802E89C0 02202025 */ move $a0, $s1
/* 0A81C4 802E89C4 1000FE68 */ b .L802E8368
/* 0A81C8 802E89C8 A2420002 */ sb $v0, 2($s2)
glabel L802E89CC
/* 0A81CC 802E89CC 0C0B9DA0 */ jal m64_read_u8
/* 0A81D0 802E89D0 02202025 */ move $a0, $s1
/* 0A81D4 802E89D4 1000FE64 */ b .L802E8368
/* 0A81D8 802E89D8 A242007D */ sb $v0, 0x7d($s2)
glabel L802E89DC
/* 0A81DC 802E89DC 0C0B9DA0 */ jal m64_read_u8
/* 0A81E0 802E89E0 02202025 */ move $a0, $s1
/* 0A81E4 802E89E4 1000FE60 */ b .L802E8368
/* 0A81E8 802E89E8 A2420007 */ sb $v0, 7($s2)
glabel L802E89EC
/* 0A81EC 802E89EC 2401FFFF */ li $at, -1
/* 0A81F0 802E89F0 1261FE5D */ beq $s3, $at, .L802E8368
/* 0A81F4 802E89F4 00000000 */ nop
/* 0A81F8 802E89F8 92240018 */ lbu $a0, 0x18($s1)
/* 0A81FC 802E89FC 8E2B0000 */ lw $t3, ($s1)
/* 0A8200 802E8A00 8E490034 */ lw $t1, 0x34($s2)
/* 0A8204 802E8A04 00046080 */ sll $t4, $a0, 2
/* 0A8208 802E8A08 022C7021 */ addu $t6, $s1, $t4
/* 0A820C 802E8A0C ADCB0004 */ sw $t3, 4($t6)
/* 0A8210 802E8A10 922F0018 */ lbu $t7, 0x18($s1)
/* 0A8214 802E8A14 00131040 */ sll $v0, $s3, 1
/* 0A8218 802E8A18 01221821 */ addu $v1, $t1, $v0
/* 0A821C 802E8A1C 25F90001 */ addiu $t9, $t7, 1
/* 0A8220 802E8A20 A2390018 */ sb $t9, 0x18($s1)
/* 0A8224 802E8A24 906D0000 */ lbu $t5, ($v1)
/* 0A8228 802E8A28 90780001 */ lbu $t8, 1($v1)
/* 0A822C 802E8A2C 8E8C0014 */ lw $t4, 0x14($s4)
/* 0A8230 802E8A30 000D5200 */ sll $t2, $t5, 8
/* 0A8234 802E8A34 030A3821 */ addu $a3, $t8, $t2
/* 0A8238 802E8A38 30E9FFFF */ andi $t1, $a3, 0xffff
/* 0A823C 802E8A3C 01895821 */ addu $t3, $t4, $t1
/* 0A8240 802E8A40 1000FE49 */ b .L802E8368
/* 0A8244 802E8A44 AE2B0000 */ sw $t3, ($s1)
glabel L802E8A48
/* 0A8248 802E8A48 0C0B9DA0 */ jal m64_read_u8
/* 0A824C 802E8A4C 02202025 */ move $a0, $s1
/* 0A8250 802E8A50 1000FE45 */ b .L802E8368
/* 0A8254 802E8A54 A2420008 */ sb $v0, 8($s2)
glabel L802E8A58
/* 0A8258 802E8A58 0C0B9DA5 */ jal m64_read_s16
/* 0A825C 802E8A5C 02202025 */ move $a0, $s1
/* 0A8260 802E8A60 8E8E0014 */ lw $t6, 0x14($s4)
/* 0A8264 802E8A64 304FFFFF */ andi $t7, $v0, 0xffff
/* 0A8268 802E8A68 01CF1821 */ addu $v1, $t6, $t7
/* 0A826C 802E8A6C 90790000 */ lbu $t9, ($v1)
/* 0A8270 802E8A70 24630007 */ addiu $v1, $v1, 7
/* 0A8274 802E8A74 A2590003 */ sb $t9, 3($s2)
/* 0A8278 802E8A78 906DFFFA */ lbu $t5, -6($v1)
/* 0A827C 802E8A7C 92590001 */ lbu $t9, 1($s2)
/* 0A8280 802E8A80 A24D0002 */ sb $t5, 2($s2)
/* 0A8284 802E8A84 9078FFFB */ lbu $t8, -5($v1)
/* 0A8288 802E8A88 372D0020 */ ori $t5, $t9, 0x20
/* 0A828C 802E8A8C A2580005 */ sb $t8, 5($s2)
/* 0A8290 802E8A90 806AFFFC */ lb $t2, -4($v1)
/* 0A8294 802E8A94 A64A001E */ sh $t2, 0x1e($s2)
/* 0A8298 802E8A98 9069FFFD */ lbu $t1, -3($v1)
/* 0A829C 802E8A9C A2490009 */ sb $t1, 9($s2)
/* 0A82A0 802E8AA0 906CFFFE */ lbu $t4, -2($v1)
/* 0A82A4 802E8AA4 A24C000A */ sb $t4, 0xa($s2)
/* 0A82A8 802E8AA8 906BFFFF */ lbu $t3, -1($v1)
/* 0A82AC 802E8AAC A24B0004 */ sb $t3, 4($s2)
/* 0A82B0 802E8AB0 906E0000 */ lbu $t6, ($v1)
/* 0A82B4 802E8AB4 A24D0001 */ sb $t5, 1($s2)
/* 0A82B8 802E8AB8 1000FE2B */ b .L802E8368
/* 0A82BC 802E8ABC A24E0007 */ sb $t6, 7($s2)
glabel L802E8AC0
/* 0A82C0 802E8AC0 0C0B9DA0 */ jal m64_read_u8
/* 0A82C4 802E8AC4 02202025 */ move $a0, $s1
/* 0A82C8 802E8AC8 A2420003 */ sb $v0, 3($s2)
/* 0A82CC 802E8ACC 0C0B9DA0 */ jal m64_read_u8
/* 0A82D0 802E8AD0 02202025 */ move $a0, $s1
/* 0A82D4 802E8AD4 A2420002 */ sb $v0, 2($s2)
/* 0A82D8 802E8AD8 0C0B9DA0 */ jal m64_read_u8
/* 0A82DC 802E8ADC 02202025 */ move $a0, $s1
/* 0A82E0 802E8AE0 A2420005 */ sb $v0, 5($s2)
/* 0A82E4 802E8AE4 0C0B9DA0 */ jal m64_read_u8
/* 0A82E8 802E8AE8 02202025 */ move $a0, $s1
/* 0A82EC 802E8AEC 0002C600 */ sll $t8, $v0, 0x18
/* 0A82F0 802E8AF0 00185603 */ sra $t2, $t8, 0x18
/* 0A82F4 802E8AF4 A64A001E */ sh $t2, 0x1e($s2)
/* 0A82F8 802E8AF8 0C0B9DA0 */ jal m64_read_u8
/* 0A82FC 802E8AFC 02202025 */ move $a0, $s1
/* 0A8300 802E8B00 A2420009 */ sb $v0, 9($s2)
/* 0A8304 802E8B04 0C0B9DA0 */ jal m64_read_u8
/* 0A8308 802E8B08 02202025 */ move $a0, $s1
/* 0A830C 802E8B0C A242000A */ sb $v0, 0xa($s2)
/* 0A8310 802E8B10 0C0B9DA0 */ jal m64_read_u8
/* 0A8314 802E8B14 02202025 */ move $a0, $s1
/* 0A8318 802E8B18 A2420004 */ sb $v0, 4($s2)
/* 0A831C 802E8B1C 0C0B9DA0 */ jal m64_read_u8
/* 0A8320 802E8B20 02202025 */ move $a0, $s1
/* 0A8324 802E8B24 924C0001 */ lbu $t4, 1($s2)
/* 0A8328 802E8B28 A2420007 */ sb $v0, 7($s2)
/* 0A832C 802E8B2C 358B0020 */ ori $t3, $t4, 0x20
/* 0A8330 802E8B30 1000FE0D */ b .L802E8368
/* 0A8334 802E8B34 A24B0001 */ sb $t3, 1($s2)
glabel L802E8B38
/* 0A8338 802E8B38 3C013F80 */ li $at, 0x3F800000 # 1.000000
/* 0A833C 802E8B3C 44815000 */ mtc1 $at, $f10
/* 0A8340 802E8B40 A6400012 */ sh $zero, 0x12($s2)
/* 0A8344 802E8B44 A640000E */ sh $zero, 0xe($s2)
/* 0A8348 802E8B48 A6400016 */ sh $zero, 0x16($s2)
/* 0A834C 802E8B4C A6400010 */ sh $zero, 0x10($s2)
/* 0A8350 802E8B50 A640000C */ sh $zero, 0xc($s2)
/* 0A8354 802E8B54 A6400014 */ sh $zero, 0x14($s2)
/* 0A8358 802E8B58 1000FE03 */ b .L802E8368
/* 0A835C 802E8B5C E64A0030 */ swc1 $f10, 0x30($s2)
glabel L802E8B60
/* 0A8360 802E8B60 0C0B9DA0 */ jal m64_read_u8
/* 0A8364 802E8B64 02202025 */ move $a0, $s1
/* 0A8368 802E8B68 1000FDFF */ b .L802E8368
/* 0A836C 802E8B6C A2420005 */ sb $v0, 5($s2)
.L80200970:
/* 0A8370 802E8B70 306E00F0 */ andi $t6, $v1, 0xf0
/* 0A8374 802E8B74 3064000F */ andi $a0, $v1, 0xf
/* 0A8378 802E8B78 2DC100B1 */ sltiu $at, $t6, 0xb1
/* 0A837C 802E8B7C 1020FDFA */ beqz $at, .L802E8368
/* 0A8380 802E8B80 308800FF */ andi $t0, $a0, 0xff
/* 0A8384 802E8B84 000E7080 */ sll $t6, $t6, 2
/* 0A8388 802E8B88 3C018030 */ lui $at, %hi(jtbl_EU_80306810)
/* 0A838C 802E8B8C 002E0821 */ addu $at, $at, $t6
/* 0A8390 802E8B90 8C2E6810 */ lw $t6, %lo(jtbl_EU_80306810)($at)
/* 0A8394 802E8B94 01C00008 */ jr $t6
/* 0A8398 802E8B98 00000000 */ nop
glabel L802E8B9C
/* 0A839C 802E8B9C 308F00FF */ andi $t7, $a0, 0xff
/* 0A83A0 802E8BA0 000FC880 */ sll $t9, $t7, 2
/* 0A83A4 802E8BA4 02596821 */ addu $t5, $s2, $t9
/* 0A83A8 802E8BA8 8DA30048 */ lw $v1, 0x48($t5)
/* 0A83AC 802E8BAC 10600007 */ beqz $v1, .L802009CC
/* 0A83B0 802E8BB0 00000000 */ nop
/* 0A83B4 802E8BB4 8C730000 */ lw $s3, ($v1)
/* 0A83B8 802E8BB8 0013C040 */ sll $t8, $s3, 1
/* 0A83BC 802E8BBC 001857C2 */ srl $t2, $t8, 0x1f
/* 0A83C0 802E8BC0 000A4E00 */ sll $t1, $t2, 0x18
/* 0A83C4 802E8BC4 1000FDE8 */ b .L802E8368
/* 0A83C8 802E8BC8 00099E03 */ sra $s3, $t1, 0x18
.L802009CC:
/* 0A83CC 802E8BCC 1000FDE6 */ b .L802E8368
/* 0A83D0 802E8BD0 2413FFFF */ li $s3, -1
glabel L802E8BD4
/* 0A83D4 802E8BD4 308B00FF */ andi $t3, $a0, 0xff
/* 0A83D8 802E8BD8 024B7021 */ addu $t6, $s2, $t3
/* 0A83DC 802E8BDC 1000FDE2 */ b .L802E8368
/* 0A83E0 802E8BE0 A1D30058 */ sb $s3, 0x58($t6)
glabel L802E8BE4
/* 0A83E4 802E8BE4 308300FF */ andi $v1, $a0, 0xff
/* 0A83E8 802E8BE8 02432821 */ addu $a1, $s2, $v1
/* 0A83EC 802E8BEC 28610004 */ slti $at, $v1, 4
/* 0A83F0 802E8BF0 1020FDDD */ beqz $at, .L802E8368
/* 0A83F4 802E8BF4 80B30058 */ lb $s3, 0x58($a1)
/* 0A83F8 802E8BF8 240FFFFF */ li $t7, -1
/* 0A83FC 802E8BFC 1000FDDA */ b .L802E8368
/* 0A8400 802E8C00 A0AF0058 */ sb $t7, 0x58($a1)
glabel L802E8C04
/* 0A8404 802E8C04 309900FF */ andi $t9, $a0, 0xff
/* 0A8408 802E8C08 02596821 */ addu $t5, $s2, $t9
/* 0A840C 802E8C0C 81B80058 */ lb $t8, 0x58($t5)
/* 0A8410 802E8C10 02789823 */ subu $s3, $s3, $t8
/* 0A8414 802E8C14 00135600 */ sll $t2, $s3, 0x18
/* 0A8418 802E8C18 1000FDD3 */ b .L802E8368
/* 0A841C 802E8C1C 000A9E03 */ sra $s3, $t2, 0x18
glabel L802E8C20
/* 0A8420 802E8C20 308C00FF */ andi $t4, $a0, 0xff
/* 0A8424 802E8C24 1000005C */ b .L802E8D98
/* 0A8428 802E8C28 A64C001A */ sh $t4, 0x1a($s2)
glabel L802E8C2C
/* 0A842C 802E8C2C 0C0B9DA5 */ jal m64_read_s16
/* 0A8430 802E8C30 02202025 */ move $a0, $s1
/* 0A8434 802E8C34 02003025 */ move $a2, $s0
/* 0A8438 802E8C38 30C5000F */ andi $a1, $a2, 0xf
/* 0A843C 802E8C3C 00A03025 */ move $a2, $a1
/* 0A8440 802E8C40 AFA50034 */ sw $a1, 0x34($sp)
/* 0A8444 802E8C44 02402025 */ move $a0, $s2
/* 0A8448 802E8C48 0C0B9BDC */ jal seq_channel_set_layer
/* 0A844C 802E8C4C A7A20052 */ sh $v0, 0x52($sp)
/* 0A8450 802E8C50 8FA60034 */ lw $a2, 0x34($sp)
/* 0A8454 802E8C54 1440FDC4 */ bnez $v0, .L802E8368
/* 0A8458 802E8C58 97A70052 */ lhu $a3, 0x52($sp)
/* 0A845C 802E8C5C 8E8E0014 */ lw $t6, 0x14($s4)
/* 0A8460 802E8C60 0006C880 */ sll $t9, $a2, 2
/* 0A8464 802E8C64 02596821 */ addu $t5, $s2, $t9
/* 0A8468 802E8C68 8DB80048 */ lw $t8, 0x48($t5)
/* 0A846C 802E8C6C 01C77821 */ addu $t7, $t6, $a3
/* 0A8470 802E8C70 1000FDBD */ b .L802E8368
/* 0A8474 802E8C74 AF0F0050 */ sw $t7, 0x50($t8)
glabel L802E8C78
/* 0A8478 802E8C78 02002825 */ move $a1, $s0
/* 0A847C 802E8C7C 30AA000F */ andi $t2, $a1, 0xf
/* 0A8480 802E8C80 01402825 */ move $a1, $t2
/* 0A8484 802E8C84 0C0B9C2D */ jal seq_channel_layer_free
/* 0A8488 802E8C88 02402025 */ move $a0, $s2
/* 0A848C 802E8C8C 1000FDB6 */ b .L802E8368
/* 0A8490 802E8C90 00000000 */ nop
glabel L802E8C94
/* 0A8494 802E8C94 2401FFFF */ li $at, -1
/* 0A8498 802E8C98 1261FDB3 */ beq $s3, $at, .L802E8368
/* 0A849C 802E8C9C 02402025 */ move $a0, $s2
/* 0A84A0 802E8CA0 02003025 */ move $a2, $s0
/* 0A84A4 802E8CA4 30C5000F */ andi $a1, $a2, 0xf
/* 0A84A8 802E8CA8 00A03025 */ move $a2, $a1
/* 0A84AC 802E8CAC 0C0B9BDC */ jal seq_channel_set_layer
/* 0A84B0 802E8CB0 AFA50034 */ sw $a1, 0x34($sp)
/* 0A84B4 802E8CB4 2401FFFF */ li $at, -1
/* 0A84B8 802E8CB8 1041FDAB */ beq $v0, $at, .L802E8368
/* 0A84BC 802E8CBC 8FA60034 */ lw $a2, 0x34($sp)
/* 0A84C0 802E8CC0 8E4C0034 */ lw $t4, 0x34($s2)
/* 0A84C4 802E8CC4 00135840 */ sll $t3, $s3, 1
/* 0A84C8 802E8CC8 8E980014 */ lw $t8, 0x14($s4)
/* 0A84CC 802E8CCC 018B1821 */ addu $v1, $t4, $t3
/* 0A84D0 802E8CD0 90790000 */ lbu $t9, ($v1)
/* 0A84D4 802E8CD4 906E0001 */ lbu $t6, 1($v1)
/* 0A84D8 802E8CD8 00064880 */ sll $t1, $a2, 2
/* 0A84DC 802E8CDC 00196A00 */ sll $t5, $t9, 8
/* 0A84E0 802E8CE0 02496021 */ addu $t4, $s2, $t1
/* 0A84E4 802E8CE4 01CD3821 */ addu $a3, $t6, $t5
/* 0A84E8 802E8CE8 8D8B0048 */ lw $t3, 0x48($t4)
/* 0A84EC 802E8CEC 30EFFFFF */ andi $t7, $a3, 0xffff
/* 0A84F0 802E8CF0 030F5021 */ addu $t2, $t8, $t7
/* 0A84F4 802E8CF4 1000FD9C */ b .L802E8368
/* 0A84F8 802E8CF8 AD6A0050 */ sw $t2, 0x50($t3)
glabel L802E8CFC
/* 0A84FC 802E8CFC 0C0B9DA5 */ jal m64_read_s16
/* 0A8500 802E8D00 02202025 */ move $a0, $s1
/* 0A8504 802E8D04 8E8E0014 */ lw $t6, 0x14($s4)
/* 0A8508 802E8D08 02002825 */ move $a1, $s0
/* 0A850C 802E8D0C 30B9000F */ andi $t9, $a1, 0xf
/* 0A8510 802E8D10 304DFFFF */ andi $t5, $v0, 0xffff
/* 0A8514 802E8D14 03202825 */ move $a1, $t9
/* 0A8518 802E8D18 02802025 */ move $a0, $s4
/* 0A851C 802E8D1C 0C0B9CFA */ jal sequence_channel_enable
/* 0A8520 802E8D20 01CD3021 */ addu $a2, $t6, $t5
/* 0A8524 802E8D24 1000FD90 */ b .L802E8368
/* 0A8528 802E8D28 00000000 */ nop
glabel L802E8D2C
/* 0A852C 802E8D2C 3218000F */ andi $t8, $s0, 0xf
/* 0A8530 802E8D30 00184880 */ sll $t1, $t8, 2
/* 0A8534 802E8D34 02896021 */ addu $t4, $s4, $t1
/* 0A8538 802E8D38 0C0B9C41 */ jal sequence_channel_disable
/* 0A853C 802E8D3C 8D840030 */ lw $a0, 0x30($t4)
/* 0A8540 802E8D40 1000FD89 */ b .L802E8368
/* 0A8544 802E8D44 00000000 */ nop
glabel L802E8D48
/* 0A8548 802E8D48 02202025 */ move $a0, $s1
/* 0A854C 802E8D4C 0C0B9DA0 */ jal m64_read_u8
/* 0A8550 802E8D50 A3A80055 */ sb $t0, 0x55($sp)
/* 0A8554 802E8D54 93A80055 */ lbu $t0, 0x55($sp)
/* 0A8558 802E8D58 00085080 */ sll $t2, $t0, 2
/* 0A855C 802E8D5C 028A5821 */ addu $t3, $s4, $t2
/* 0A8560 802E8D60 8D790030 */ lw $t9, 0x30($t3)
/* 0A8564 802E8D64 03227021 */ addu $t6, $t9, $v0
/* 0A8568 802E8D68 1000FD7F */ b .L802E8368
/* 0A856C 802E8D6C A1D30058 */ sb $s3, 0x58($t6)
glabel L802E8D70
/* 0A8570 802E8D70 02202025 */ move $a0, $s1
/* 0A8574 802E8D74 0C0B9DA0 */ jal m64_read_u8
/* 0A8578 802E8D78 A3A80055 */ sb $t0, 0x55($sp)
/* 0A857C 802E8D7C 93A80055 */ lbu $t0, 0x55($sp)
/* 0A8580 802E8D80 00086880 */ sll $t5, $t0, 2
/* 0A8584 802E8D84 028D7821 */ addu $t7, $s4, $t5
/* 0A8588 802E8D88 8DF80030 */ lw $t8, 0x30($t7)
/* 0A858C 802E8D8C 03024821 */ addu $t1, $t8, $v0
/* 0A8590 802E8D90 1000FD75 */ b .L802E8368
/* 0A8594 802E8D94 81330058 */ lb $s3, 0x58($t1)
glabel L802E8D98
.L802E8D98:
/* 0A8598 802E8D98 02408825 */ move $s1, $s2
.L80200B9C:
/* 0A859C 802E8D9C 24120010 */ li $s2, 16
/* 0A85A0 802E8DA0 00008025 */ move $s0, $zero
.L80200BA4:
/* 0A85A4 802E8DA4 8E240048 */ lw $a0, 0x48($s1)
/* 0A85A8 802E8DA8 50800004 */ beql $a0, $zero, .L80200BBC
/* 0A85AC 802E8DAC 26100004 */ addiu $s0, $s0, 4
/* 0A85B0 802E8DB0 0C0B9DC2 */ jal seq_channel_layer_process_script
/* 0A85B4 802E8DB4 00000000 */ nop
/* 0A85B8 802E8DB8 26100004 */ addiu $s0, $s0, 4
.L80200BBC:
/* 0A85BC 802E8DBC 1612FFF9 */ bne $s0, $s2, .L80200BA4
/* 0A85C0 802E8DC0 26310004 */ addiu $s1, $s1, 4
.L80200BC4:
/* 0A85C4 802E8DC4 8FBF002C */ lw $ra, 0x2c($sp)
.L80200BC8:
/* 0A85C8 802E8DC8 8FB00018 */ lw $s0, 0x18($sp)
/* 0A85CC 802E8DCC 8FB1001C */ lw $s1, 0x1c($sp)
/* 0A85D0 802E8DD0 8FB20020 */ lw $s2, 0x20($sp)
/* 0A85D4 802E8DD4 8FB30024 */ lw $s3, 0x24($sp)
/* 0A85D8 802E8DD8 8FB40028 */ lw $s4, 0x28($sp)
/* 0A85DC 802E8DDC 03E00008 */ jr $ra
/* 0A85E0 802E8DE0 27BD0060 */ addiu $sp, $sp, 0x60
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_adc/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_adc/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_adc/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_adc/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_adc/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_adc/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_adc/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_adc/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
96flashbacks/springroll
| 155,284
|
sound/sequences/00_sound_player.s
|
#include "seq_macros.inc"
.section .rodata
.align 0
sequence_start:
seq_setmutebhv 0x60
seq_setmutescale 0
#if defined(VERSION_SH) || defined(VERSION_CN)
seq_setvol 100
#else
seq_setvol 127
#endif
seq_settempo 120
seq_initchannels 0x3ff
seq_startchannel 0, .channel0
seq_startchannel 1, .channel1
seq_startchannel 2, .channel2
seq_startchannel 3, .channel38
seq_startchannel 4, .channel4
seq_startchannel 5, .channel59
seq_startchannel 6, .channel6
seq_startchannel 7, .channel7
seq_startchannel 8, .channel38
seq_startchannel 9, .channel59
.seq_loop:
seq_delay 20000
seq_jump .seq_loop
.channel0:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel0_table
chan_jump .main_loop_023589
.channel2:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel2_table
chan_jump .main_loop_023589
.channel38:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel38_table
chan_jump .main_loop_023589
.channel59:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel59_table
chan_jump .main_loop_023589
// Main loop for standard, non-continuous sound effects
.main_loop_023589:
chan_delay1
chan_ioreadval 0
chan_bltz .main_loop_023589
.start_playing_023589:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_setval 0
chan_iowriteval 5
chan_ioreadval 4
chan_dyncall
// keep looping until layer 0 finishes or we are told to stop or to play something else
.poll_023589:
chan_delay1
chan_ioreadval 0
chan_bltz .skip_023589 // if we have a signal:
chan_beqz .force_stop_023589 // told to stop
chan_jump .start_playing_023589 // told to play something else
.skip_023589:
chan_testlayerfinished 0
chan_beqz .poll_023589 // if layer 0 hasn't finished, keep polling
chan_jump .main_loop_023589 // otherwise go back to the main loop
.force_stop_023589:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_jump .main_loop_023589
.channel1:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_setmutebhv 0x20
chan_stereoheadseteffects 1
chan_setdyntable .channel1_table
chan_jump .main_loop_146
.channel4:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_setmutebhv 0x20
chan_stereoheadseteffects 1
chan_setdyntable .channel4_table
chan_jump .main_loop_146
.channel6:
chan_largenoteson
chan_setinstr 0
chan_setpanmix 127
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_setmutebhv 0x20
chan_stereoheadseteffects 1
chan_setdyntable .channel6_table
chan_jump .main_loop_146
// Main loop for moving, env and air sound effects, which play continuously
.main_loop_146:
chan_delay1
chan_ioreadval 0
chan_bltz .main_loop_146
.start_playing_146:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_setvolscale 127
chan_setval 0
chan_iowriteval 5
chan_ioreadval 4
chan_dyncall
// keep looping until we are told to stop or to play something else
.poll_146:
chan_delay1
chan_ioreadval 0
chan_bltz .poll_146
chan_beqz .force_stop_146
chan_jump .start_playing_146
.force_stop_146:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_jump .main_loop_146
.channel7:
chan_largenoteson
chan_setinstr 0
chan_setnotepriority 14
chan_setval 0
chan_iowriteval 5
chan_stereoheadseteffects 1
chan_setdyntable .channel7_table
// Loop for menu sound effects
.main_loop_7:
chan_delay1
chan_ioreadval 0
chan_bltz .main_loop_7
.start_playing_7:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_setval 0
chan_iowriteval 5
chan_setreverb 0
chan_setpan 64
chan_setpanmix 127
chan_ioreadval 4
chan_dyncall
// keep looping until layer 0 finishes or we are told to stop or to play something else
.poll_7:
chan_delay1
chan_ioreadval 0
chan_bltz .skip_7 // if we have a signal:
chan_beqz .force_stop_7 // told to stop
chan_unreservenotes
chan_jump .start_playing_7 // told to play something else
.skip_7:
chan_testlayerfinished 0
chan_beqz .poll_7 // if layer 0 hasn't finished, keep polling
chan_unreservenotes
chan_jump .main_loop_7 // otherwise go back to the main loop
.force_stop_7:
chan_freelayer 0
chan_freelayer 1
chan_freelayer 2
chan_unreservenotes
chan_jump .main_loop_7
// Delay for a number of ticks (1-255) in an interruptible manner.
.delay:
chan_writeseq_nextinstr 0, 1
chan_loop 20
chan_delay1
chan_ioreadval 0
chan_iowriteval 1
chan_bgez .delay_interrupt
chan_loopend
chan_end
.delay_interrupt:
chan_setpanmix 127
chan_setvolscale 127
chan_setvibratoextent 0
chan_ioreadval 1 // IO slots 0-3 are reset to -1 when read; restore the value
chan_iowriteval 0
chan_break // break out of the loop
chan_break // force the caller to return immediately
chan_end
// Set reverb in way that takes area echo level and volume into account. This
// is done by writing to IO slot 5 and letting get_sound_reverb in external.c
// do the necessary math.
.set_reverb:
chan_writeseq_nextinstr 0, 1
chan_setreverb 10
chan_iowriteval 5
chan_end
.channel0_table:
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_grass
sound_ref .sound_action_jump_water
sound_ref .sound_action_jump_stone
sound_ref .sound_action_jump_spooky
sound_ref .sound_action_jump_snow
sound_ref .sound_action_jump_ice
sound_ref .sound_action_jump_sand
sound_ref .sound_action_landing_default
sound_ref .sound_action_landing_grass
sound_ref .sound_action_landing_water
sound_ref .sound_action_landing_stone
sound_ref .sound_action_landing_spooky
sound_ref .sound_action_landing_snow
sound_ref .sound_action_landing_ice
sound_ref .sound_action_landing_sand
sound_ref .sound_action_step_default
sound_ref .sound_action_step_grass
sound_ref .sound_action_step_water
sound_ref .sound_action_step_stone
sound_ref .sound_action_step_spooky
sound_ref .sound_action_step_snow
sound_ref .sound_action_step_ice
sound_ref .sound_action_step_sand
sound_ref .sound_action_body_hit_ground_default
sound_ref .sound_action_body_hit_ground_grass
sound_ref .sound_action_body_hit_ground_water
sound_ref .sound_action_body_hit_ground_stone
sound_ref .sound_action_body_hit_ground_spooky
sound_ref .sound_action_body_hit_ground_snow
sound_ref .sound_action_body_hit_ground_ice
sound_ref .sound_action_body_hit_ground_sand
sound_ref .sound_action_step_tiptoe_default
sound_ref .sound_action_step_tiptoe_grass
sound_ref .sound_action_step_tiptoe_water
sound_ref .sound_action_step_tiptoe_stone
sound_ref .sound_action_step_tiptoe_spooky
sound_ref .sound_action_step_tiptoe_snow
sound_ref .sound_action_step_tiptoe_ice
sound_ref .sound_action_step_tiptoe_sand
sound_ref .sound_action_metal_jump
sound_ref .sound_action_metal_landing
sound_ref .sound_action_metal_step
sound_ref .sound_action_metal_heavy_landing
sound_ref .sound_action_clap_hands_cold
sound_ref .sound_action_hanging_step
sound_ref .sound_action_quicksand_step
sound_ref .sound_action_metal_step_tiptoe
sound_ref .chan_4E5
sound_ref .chan_4F1
sound_ref .chan_4FD
sound_ref .sound_action_swim
sound_ref .chan_522
sound_ref .sound_action_throw
sound_ref .sound_action_key_swish
sound_ref .sound_action_spin
sound_ref .sound_action_spin
sound_ref .sound_action_spin
sound_ref .sound_action_climb_up_tree
sound_ref .sound_action_climb_down_tree
sound_ref .chan_582
sound_ref .chan_591
sound_ref .chan_5A3
sound_ref .sound_action_pat_back
sound_ref .sound_action_brush_hair
sound_ref .sound_action_climb_up_pole
sound_ref .sound_action_metal_bonk
sound_ref .sound_action_unstuck_from_ground
sound_ref .sound_action_hit
sound_ref .sound_action_bonk
sound_ref .sound_action_enter_bbh
sound_ref .sound_action_swim_fast
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_default
sound_ref .sound_action_stuck_in_ground_snow
sound_ref .sound_action_stuck_in_ground_sand
sound_ref .sound_action_stuck_in_ground_sand
sound_ref .sound_action_metal_jump_water
sound_ref .sound_action_metal_land_water
sound_ref .sound_action_metal_step_water
sound_ref .chan_731
sound_ref .chan_743
sound_ref .chan_756
sound_ref .sound_action_flying_fast
sound_ref .sound_action_teleport
sound_ref .chan_7A5
sound_ref .sound_action_bounce_off_object
sound_ref .chan_7ED
sound_ref .sound_action_read_sign
sound_ref .chan_810
#ifdef VERSION_JP
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
#else
sound_ref .chan_828
sound_ref .sound_action_intro_unk45e
sound_ref .sound_action_intro_unk45f
#endif
sound_ref .sound_action_heavy_landing_default
sound_ref .sound_action_heavy_landing_grass
sound_ref .sound_action_heavy_landing_water
sound_ref .sound_action_heavy_landing_stone
sound_ref .sound_action_heavy_landing_spooky
sound_ref .sound_action_heavy_landing_snow
sound_ref .sound_action_heavy_landing_ice
sound_ref .sound_action_heavy_landing_sand
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
sound_ref .sound_action_jump_default
.sound_action_jump_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_234
chan_end
.layer_234:
layer_note1 41, 0xc, 117
layer_note1 46, 0x18, 117
layer_end
.sound_action_jump_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_243
chan_end
.layer_243:
layer_note1 41, 0xc, 120
layer_note1 50, 0x18, 120
layer_end
.sound_action_jump_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_252
chan_end
.layer_252:
layer_note1 41, 0x6, 80
layer_note1 50, 0x18, 80
layer_end
.sound_action_jump_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_261
chan_end
.layer_261:
layer_note1 41, 0xc, 127
layer_note1 50, 0x18, 127
layer_end
.sound_action_jump_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_270
chan_end
.layer_270:
layer_note1 41, 0xc, 90
layer_note1 50, 0x18, 90
layer_end
.sound_action_jump_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_27F
chan_end
.layer_27F:
layer_note1 41, 0xc, 80
layer_note1 50, 0x18, 80
layer_end
.sound_action_jump_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_28E
chan_end
.layer_28E:
layer_note1 29, 0xc, 127
layer_note1 38, 0x18, 127
layer_end
.sound_action_jump_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_29D
chan_end
.layer_29D:
layer_note0 34, 0xc, 100, 127
layer_note0 43, 0x24, 100, 127
layer_end
.sound_action_landing_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_2AE
chan_end
.layer_2AE:
layer_note1 46, 0xc, 117
layer_note1 41, 0x18, 117
layer_end
.sound_action_landing_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_2BD
chan_end
.layer_2BD:
layer_note1 50, 0xc, 120
layer_note1 41, 0x18, 120
layer_end
.sound_action_landing_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_2CC
chan_end
.layer_2CC:
layer_note1 50, 0xc, 80
layer_note1 41, 0x18, 80
layer_end
.sound_action_landing_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_2DB
chan_end
.layer_2DB:
layer_note1 50, 0xc, 127
layer_note1 41, 0x18, 127
layer_end
.sound_action_landing_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_2EA
chan_end
.layer_2EA:
layer_note1 50, 0xc, 90
layer_note1 41, 0x18, 90
layer_end
.sound_action_landing_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_2F9
chan_end
.layer_2F9:
layer_note1 50, 0xc, 80
layer_note1 41, 0x18, 80
layer_end
.sound_action_landing_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_308
chan_end
.layer_308:
layer_note1 38, 0xc, 127
layer_note1 29, 0x18, 127
layer_end
.sound_action_landing_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_317
chan_end
.layer_317:
layer_note0 43, 0xc, 100, 127
layer_note0 34, 0x24, 100, 127
layer_end
.sound_action_step_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_328
chan_end
.layer_328:
layer_note1 39, 0x18, 85
layer_end
.sound_action_step_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_334
chan_end
.layer_334:
layer_note1 39, 0x18, 100
layer_end
.sound_action_step_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_340
chan_end
.layer_340:
layer_note1 43, 0x18, 63
layer_end
.sound_action_step_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_34C
chan_end
.layer_34C:
layer_note1 39, 0x18, 77
layer_end
.sound_action_step_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_358
chan_end
.layer_358:
layer_note1 39, 0x18, 70
layer_end
.sound_action_step_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_364
chan_end
.layer_364:
layer_note1 39, 0x18, 68
layer_end
.sound_action_step_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_370
chan_end
.layer_370:
layer_note1 39, 0x18, 100
layer_end
.sound_action_step_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_37C
chan_end
.layer_37C:
layer_note1 39, 0x18, 70
layer_end
.sound_action_body_hit_ground_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_388
chan_end
.layer_388:
layer_note1 17, 0xc, 117
layer_note1 19, 0x18, 117
layer_end
.sound_action_body_hit_ground_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_397
chan_end
.layer_397:
layer_note1 29, 0xc, 120
layer_note1 31, 0x18, 120
layer_end
.sound_action_body_hit_ground_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_3A6
chan_end
.layer_3A6:
layer_note1 34, 0xc, 80
layer_note1 39, 0x18, 80
layer_end
.sound_action_body_hit_ground_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_3B5
chan_end
.layer_3B5:
layer_note1 29, 0xc, 115
layer_note1 31, 0xc, 115
layer_end
.sound_action_body_hit_ground_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_3C4
chan_end
.layer_3C4:
layer_note1 29, 0xc, 90
layer_note1 31, 0x18, 90
layer_end
.sound_action_body_hit_ground_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_3D3
chan_end
.layer_3D3:
layer_note1 34, 0xc, 80
layer_note1 36, 0x18, 80
layer_end
.sound_action_body_hit_ground_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_3E2
chan_end
.layer_3E2:
layer_note1 29, 0xc, 127
layer_note1 31, 0x18, 127
layer_end
.sound_action_body_hit_ground_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_3F1
chan_end
.layer_3F1:
layer_note0 31, 0xc, 100, 127
layer_note0 32, 0x24, 100, 127
layer_end
.sound_action_step_tiptoe_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_402
chan_end
.layer_402:
layer_note1 37, 0x18, 63
layer_end
.sound_action_step_tiptoe_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_40E
chan_end
.layer_40E:
layer_note1 37, 0x18, 57
layer_end
.sound_action_step_tiptoe_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_41A
chan_end
.layer_41A:
layer_note1 39, 0x18, 39
layer_end
.sound_action_step_tiptoe_stone:
chan_setbank 1
chan_setinstr 3
chan_setlayer 0, .layer_426
chan_end
.layer_426:
layer_note1 37, 0x18, 49
layer_end
.sound_action_step_tiptoe_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_432
chan_end
.layer_432:
layer_note1 37, 0x18, 39
layer_end
.sound_action_step_tiptoe_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_43E
chan_end
.layer_43E:
layer_note1 37, 0x18, 39
layer_end
.sound_action_step_tiptoe_ice:
chan_setbank 1
chan_setinstr 6
chan_setlayer 0, .layer_44A
chan_end
.layer_44A:
layer_note1 37, 0x18, 70
layer_end
.sound_action_step_tiptoe_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_456
chan_end
.layer_456:
layer_note1 35, 0x18, 49
layer_end
.sound_action_metal_jump:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_462
chan_end
.layer_462:
layer_note1 29, 0xc, 100
layer_note1 38, 0x12, 100
layer_end
.sound_action_metal_landing:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_471
chan_end
.layer_471:
layer_note1 38, 0xc, 100
layer_note1 29, 0x18, 100
layer_end
.sound_action_metal_step:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_480
chan_end
.layer_480:
layer_portamento 0x85, 27, 255
layer_note1 31, 0x10, 100
layer_end
.sound_action_metal_heavy_landing:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_490
chan_end
.layer_490:
layer_note1 20, 0xc, 100
layer_note1 24, 0x18, 100
layer_end
.sound_action_clap_hands_cold:
chan_setbank 3
chan_setinstr 6
chan_setenvelope .envelope_3304
chan_setlayer 0, .layer_4A2
chan_end
.layer_4A2:
layer_note1 62, 0x6, 90
layer_note1 58, 0x7, 90
layer_end
.sound_action_hanging_step:
chan_setbank 0
chan_setinstr 2
chan_setlayer 0, .layer_4BD
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_end
.layer_4BD:
layer_note1 62, 0x4, 127
layer_note0 56, 0x3, 127, 80
layer_end
.sound_action_quicksand_step:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_4CD
chan_end
.layer_4CD:
layer_portamento 0x1, 29, 0x12
layer_note1 24, 0x12, 115
layer_end
.sound_action_metal_step_tiptoe:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_4DD
chan_end
.layer_4DD:
layer_portamento 0x85, 25, 255
layer_note1 29, 0x10, 70
layer_end
.chan_4E5:
chan_setbank 2
chan_setinstr 0
chan_setlayer 0, .layer_4ED
chan_end
.layer_4ED:
layer_note1 39, 0x7f, 100
layer_end
.chan_4F1:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_4F9
chan_end
.layer_4F9:
layer_note1 36, 0x64, 90
layer_end
.chan_4FD:
chan_setbank 2
chan_setlayer 0, .layer_503
chan_end
.layer_503:
layer_setinstr 2
layer_note1 36, 0xa, 80
layer_setinstr 0
layer_portamento 0x81, 36, 255
layer_note1 50, 0x32, 80
layer_end
.sound_action_swim:
chan_setbank 2
chan_setinstr 2
chan_setlayer 0, .layer_51A
chan_end
.layer_51A:
layer_portamento 0x81, 35, 255
layer_note1 30, 0x3c, 110
layer_end
.chan_522:
chan_setbank 2
chan_setinstr 2
chan_setlayer 0, .layer_52A
chan_end
.layer_52A:
layer_note1 39, 0x7f, 115
layer_end
.sound_action_throw:
chan_setbank 0
chan_setinstr 0
chan_setlayer 0, .layer_538
chan_end
.layer_536:
layer_transpose 1
.layer_538:
layer_portamento 0x81, 46, 255
layer_note1 31, 0xf, 100
layer_end
.sound_action_key_swish:
chan_setbank 0
chan_setinstr 0
chan_setlayer 0, .layer_548
chan_end
.layer_548:
layer_note1 39, 0x12, 100
layer_end
.sound_action_spin:
chan_setbank 0
chan_setinstr 0
chan_setdecayrelease 30
chan_setlayer 0, .layer_556
chan_end
.layer_556:
layer_portamento 0x81, 34, 255
layer_note1 41, 0xc, 127
layer_end
.sound_action_climb_up_tree:
chan_setbank 0
chan_setinstr 1
chan_setlayer 0, .layer_566
chan_end
.layer_566:
layer_note1 37, 0xa, 105
layer_portamento 0x81, 42, 255
layer_note1 37, 0x1e, 105
layer_end
.sound_action_climb_down_tree: // unused
chan_setbank 0
chan_setinstr 1
chan_setlayer 0, .layer_579
chan_end
.layer_579:
layer_portamento 0x81, 44, 255
layer_note1 40, 0xb4, 100
layer_end
.chan_582: // unused
chan_setbank 0
chan_setinstr 2
chan_setlayer 0, .layer_58A
chan_end
.layer_58A:
layer_note1 39, 0x4, 127
layer_note1 41, 0x12, 127
layer_end
.chan_591:
chan_setbank 1
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_59C
chan_end
.layer_59C:
layer_note1 38, 0x6, 127
layer_note1 41, 0x6, 127
layer_end
.chan_5A3:
chan_setbank 1
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_5AE
chan_end
.layer_5AE:
layer_note1 41, 0x6, 127
layer_note1 38, 0x6, 127
layer_end
.sound_action_pat_back:
chan_setbank 0
chan_setinstr 2
chan_setlayer 0, .layer_5BD
chan_end
.layer_5BD:
layer_note1 32, 0xa, 127
layer_end
.sound_action_brush_hair:
chan_setbank 0
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_5CC
chan_end
.layer_5CC:
layer_note1 39, 0x8, 90
layer_note1 41, 0x8, 90
layer_end
.sound_action_climb_up_pole:
chan_setbank 3
chan_setinstr 1
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_5DE
chan_end
.layer_5DE:
layer_portamento 0x85, 53, 255
layer_note1 55, 0xc, 127
layer_note1 53, 0x18, 127
layer_end
.sound_action_metal_bonk:
chan_setbank 1
chan_setinstr 7
chan_setlayer 0, .layer_5F1
chan_end
.layer_5F1:
layer_note1 39, 0x7, 100
layer_note1 20, 0x18, 115
layer_end
.sound_action_unstuck_from_ground:
chan_setbank 0
chan_setinstr 4
chan_setlayer 0, .layer_600
chan_end
.layer_600:
layer_note1 37, 0x48, 127
layer_end
.sound_action_hit:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_618
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_3314
chan_end
.layer_618:
layer_portamento 0x81, 27, 255
layer_note1 46, 0xb, 127
.layer_61F:
layer_somethingon
layer_portamento 0x85, 32, 255
layer_note1 44, 0x5, 100
layer_call .layer_fn_64A
layer_transpose 1
layer_call .layer_fn_64A
layer_transpose 3
layer_call .layer_fn_64A
layer_transpose 4
layer_call .layer_fn_64A
layer_transpose 6
layer_call .layer_fn_64A
layer_transpose 7
layer_call .layer_fn_64A
layer_transpose 9
layer_call .layer_fn_64A
layer_transpose 10
.layer_fn_64A:
layer_note1 20, 0x5, 115
layer_note1 32, 0x5, 115
layer_end
.sound_action_bonk:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_659
chan_end
.layer_659:
layer_portamento 0x82, 19, 255
layer_note1 34, 0x5, 110
layer_note1 39, 0x2, 110
layer_end
.sound_action_enter_bbh:
chan_setbank 3
chan_setinstr 3
chan_setval 50
chan_call .set_reverb
chan_setenvelope .envelope_3324
chan_setlayer 0, .layer_68F
chan_delay 1
chan_setlayer 1, .layer_6A1
chan_setbank 9
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_setdecayrelease 20
chan_delay 1
chan_setlayer 2, .layer_699
chan_setbank 4
chan_setinstr 14
chan_setdecayrelease 12
chan_setvibratoextent 10
chan_end
.layer_68F:
layer_transpose 36
layer_portamento 0x81, 62, 255
layer_note1 38, 0x7f, 127
layer_end
.layer_699:
layer_portamento 0x81, 39, 255
layer_note1 15, 0x7f, 127
layer_end
.layer_6A1:
layer_portamento 0x81, 62, 255
layer_note1 38, 0x7f, 100
layer_end
.sound_action_swim_fast:
chan_setbank 2
chan_setinstr 2
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_6C1
chan_setlayer 1, .layer_6B9
chan_end
.layer_6B9:
layer_portamento 0x81, 23, 255
layer_note1 59, 0x30, 120
layer_end
.layer_6C1:
layer_portamento 0x81, 35, 255
layer_note1 42, 0x3c, 110
layer_end
.sound_action_stuck_in_ground_default:
chan_setbank 1
chan_setinstr 0
chan_setlayer 0, .layer_6D1
chan_end
.layer_6D1:
layer_note1 17, 0x6, 127
layer_portamento 0x81, 31, 255
layer_note1 7, 0xc, 127
layer_end
.sound_action_stuck_in_ground_snow:
chan_setbank 1
chan_setinstr 5
chan_setlayer 0, .layer_6E4
chan_end
.layer_6E4:
layer_note1 23, 0x6, 127
layer_note1 25, 0xc, 127
layer_end
.sound_action_stuck_in_ground_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_6F3
chan_end
.layer_6F3:
layer_note1 17, 0x6, 127
layer_note1 19, 0xc, 127
layer_end
.sound_action_metal_jump_water:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_705
chan_end
.layer_705:
layer_note1 20, 0xf, 90
layer_note1 29, 0x17, 90
layer_end
.sound_action_metal_land_water:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_717
chan_end
.layer_717:
layer_note1 29, 0xf, 90
layer_note1 20, 0x1f, 90
layer_end
.sound_action_metal_step_water:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_729
chan_end
.layer_729:
layer_portamento 0x85, 18, 255
layer_note1 22, 0x15, 90
layer_end
.chan_731:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_73C
chan_end
.layer_73C:
layer_note1 11, 0xf, 90
layer_note1 15, 0x1f, 90
layer_end
.chan_743:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_74E
chan_end
.layer_74E:
layer_portamento 0x85, 18, 255
layer_note1 22, 0x10, 90
layer_end
.chan_756:
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_761
chan_end
.layer_761:
layer_transpose 8
layer_jump .layer_61F
.sound_action_flying_fast:
chan_setbank 5
chan_setinstr 6
chan_setenvelope .envelope_33AC
chan_setlayer 0, .layer_774
chan_setlayer 1, .layer_776
chan_end
.layer_774:
layer_transpose 12
.layer_776:
layer_somethingon
layer_portamento 0x85, 27, 255
layer_note1 51, 0x14, 127
layer_note1 36, 0x5a, 127
layer_end
.sound_action_teleport:
chan_setbank 9
chan_setinstr 3
chan_setvibratoextent 60
chan_setvibratorate 60
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_79D
chan_setlayer 1, .layer_79B
chan_setval 36
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_79B:
layer_transpose 1
.layer_79D:
layer_portamento 0x81, 20, 100
layer_note1 27, 0x30, 127
layer_end
.chan_7A5:
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_7B9
chan_setval 4
chan_call .delay
chan_setbank 9
chan_setinstr 3
chan_end
.layer_7B9:
layer_note1 43, 0x3, 115
layer_note1 48, 0x5, 115
layer_transpose 12
layer_note1 55, 0x6, 80
layer_end
.sound_action_bounce_off_object:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_7D9
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_3314
chan_end
.layer_7D9:
layer_portamento 0x81, 27, 255
layer_note1 41, 0xb, 127
layer_somethingon
layer_transpose -4
layer_portamento 0x85, 32, 255
layer_note1 44, 0x5, 100
layer_jump .layer_fn_64A
.chan_7ED:
chan_setbank 0
chan_setinstr 3
chan_setdecayrelease 30
chan_setlayer 0, .layer_7F7
chan_end
.layer_7F7:
layer_setinstr 0
layer_portamento 0x81, 32, 255
layer_note1 39, 0x24, 127
layer_end
.sound_action_read_sign:
chan_jump .sound_menu_read_sign
.heavy_landing_common:
chan_setbank 0
chan_setinstr 5
chan_setlayer 0, .layer_80C
chan_end
.layer_80C:
layer_note1 41, 0x3c, 127
layer_end
.chan_810:
chan_setbank 1
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_81B
chan_end
.layer_81B:
layer_note1 38, 0x8, 127
layer_note1 41, 0x9, 127
layer_note1 39, 0xa, 127
layer_note1 42, 0x8, 127
layer_end
#ifndef VERSION_JP
.chan_828: // unused
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_83C
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_3314
chan_end
.layer_83C:
layer_portamento 0x81, 27, 255
layer_note1 46, 0x7, 127
layer_portamento 0x85, 3, 255
layer_note1 39, 0xf, 100
layer_end
.sound_action_intro_unk45e:
chan_setbank 5
chan_setinstr 6
chan_setenvelope .envelope_33AC
chan_setlayer 0, .layer_859
chan_setlayer 1, .layer_85B
chan_end
.layer_859:
layer_transpose 12
.layer_85B:
layer_portamento 0x85, 26, 240
layer_note1 51, 0x53, 127
layer_end
.sound_action_intro_unk45f:
chan_setbank 5
chan_setinstr 6
chan_setenvelope .envelope_33AC
chan_setlayer 0, .layer_871
chan_setlayer 1, .layer_776
chan_end
.layer_871:
layer_transpose 8
layer_jump .layer_776
#endif
.sound_action_heavy_landing_default:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 0
chan_setlayer 1, .layer_388
chan_end
.sound_action_heavy_landing_grass:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 1
chan_setlayer 1, .layer_397
chan_end
.sound_action_heavy_landing_water:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 2
chan_setinstr 1
chan_setlayer 1, .layer_3A6
chan_end
.sound_action_heavy_landing_stone:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 3
chan_setlayer 1, .layer_3B5
chan_end
.sound_action_heavy_landing_spooky:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 4
chan_setlayer 1, .layer_3C4
chan_end
.sound_action_heavy_landing_snow:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 5
chan_setlayer 1, .layer_3D3
chan_end
.sound_action_heavy_landing_ice:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 6
chan_setlayer 1, .layer_3E2
chan_end
.sound_action_heavy_landing_sand:
chan_call .heavy_landing_common
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 8
chan_setlayer 1, .layer_3F1
chan_end
.channel1_table:
sound_ref .sound_moving_slide_default
sound_ref .sound_moving_slide_grass
sound_ref .sound_moving_slide_water
sound_ref .sound_moving_slide_stone
sound_ref .sound_moving_slide_spooky
sound_ref .sound_moving_slide_snow
sound_ref .sound_moving_slide_ice
sound_ref .sound_moving_slide_sand
sound_ref .sound_moving_slide_default
sound_ref .sound_moving_slide_grass
sound_ref .sound_moving_slide_water
sound_ref .sound_moving_slide_stone
sound_ref .sound_moving_slide_spooky
sound_ref .sound_moving_slide_snow
sound_ref .sound_moving_slide_ice
sound_ref .sound_moving_slide_sand
sound_ref .sound_moving_lava_burn
sound_ref .sound_moving_slide_down_pole
sound_ref .sound_moving_slide_down_tree
sound_ref .sound_general_coin
sound_ref .sound_moving_quicksand_death
sound_ref .sound_general_coin
sound_ref .sound_moving_shocked
sound_ref .sound_moving_flying
sound_ref .sound_moving_almost_drowning
sound_ref .sound_moving_aim_cannon
sound_ref .chan_AC3
sound_ref .sound_moving_slide_stone
sound_ref .sound_moving_slide_spooky
sound_ref .sound_moving_slide_snow
sound_ref .sound_moving_slide_ice
sound_ref .sound_moving_slide_sand
sound_ref .sound_moving_riding_shell_default
sound_ref .sound_moving_riding_shell_grass
sound_ref .sound_moving_riding_shell_water
sound_ref .sound_moving_riding_shell_stone
sound_ref .sound_moving_riding_shell_spooky
sound_ref .sound_moving_riding_shell_snow
sound_ref .sound_moving_riding_shell_ice
sound_ref .sound_moving_riding_shell_sand
sound_ref .sound_moving_riding_shell_lava
sound_ref .sound_moving_riding_shell_grass
sound_ref .sound_moving_riding_shell_water
sound_ref .sound_moving_riding_shell_stone
sound_ref .sound_moving_riding_shell_spooky
sound_ref .sound_moving_riding_shell_snow
sound_ref .sound_moving_riding_shell_ice
sound_ref .sound_moving_riding_shell_sand
sound_ref .sound_moving_riding_shell_default
sound_ref .sound_moving_riding_shell_grass
sound_ref .sound_moving_riding_shell_water
sound_ref .sound_moving_riding_shell_stone
sound_ref .sound_moving_riding_shell_spooky
sound_ref .sound_moving_riding_shell_snow
sound_ref .sound_moving_riding_shell_ice
sound_ref .sound_moving_riding_shell_sand
.sound_moving_slide_default:
chan_setbank 3
chan_setinstr 0
chan_setlayer 0, .layer_96E
chan_end
.layer_96E:
layer_somethingon
.layer_96F:
layer_note1 39, 0x12c, 80
layer_jump .layer_96F
layer_end
.sound_moving_slide_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_988
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 1
chan_end
.layer_988:
layer_note1 41, 0x8, 105
layer_somethingon
.layer_98C:
layer_note1 39, 0x12c, 70
layer_jump .layer_98C
layer_end
.sound_moving_slide_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_9A8
chan_setlayer 1, .layer_9B3
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 2
chan_end
.layer_9A8:
layer_delay 1
layer_somethingon
.layer_9AB:
layer_note1 39, 0x12c, 88
layer_jump .layer_9AB
layer_end
.layer_9B3:
layer_portamento 0x81, 39, 255
layer_note1 48, 0x32, 80
layer_end
.sound_moving_slide_stone:
chan_setbank 3
chan_setinstr 3
chan_setlayer 0, .layer_9C3
chan_end
.layer_9C3:
layer_somethingon
.layer_9C4:
layer_note1 39, 0x12c, 68
layer_jump .layer_9C4
layer_end
.sound_moving_slide_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_9DD
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 4
chan_end
.layer_9DD:
layer_note1 42, 0xc, 75
layer_somethingon
.layer_9E1:
layer_note1 39, 0x12c, 76
layer_jump .layer_9E1
layer_end
.sound_moving_slide_snow:
chan_setbank 3
chan_setinstr 5
chan_setlayer 0, .layer_9F1
chan_end
.layer_9F1:
layer_somethingon
.layer_9F2:
layer_note1 39, 0x12c, 80
layer_jump .layer_9F2
layer_end
.sound_moving_slide_ice:
chan_setbank 3
chan_setinstr 6
chan_setlayer 0, .layer_A02
chan_end
.layer_A02:
layer_somethingon
.layer_A03:
layer_note1 39, 0x12c, 100
layer_jump .layer_A03
layer_end
.sound_moving_slide_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_A1C
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 7
chan_end
.layer_A1C:
layer_note1 42, 0xc, 100
layer_somethingon
.layer_A20:
layer_note1 39, 0x12c, 81
layer_jump .layer_A20
layer_end
.sound_moving_lava_burn:
chan_setbank 3
chan_setinstr 8
chan_setlayer 0, .layer_A30
chan_end
.layer_A30:
layer_somethingon
.layer_A31:
layer_note1 39, 0x12c, 120
layer_jump .layer_A31
layer_end
.sound_moving_slide_down_pole:
chan_setbank 3
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_A44
chan_end
.layer_A44:
layer_somethingon
.layer_A45:
layer_note1 43, 0x12c, 80
layer_jump .layer_A45
layer_end
.sound_moving_slide_down_tree:
chan_setbank 0
chan_setinstr 1
chan_setlayer 0, .layer_A55
chan_end
.layer_A55:
layer_portamento 0x81, 44, 255
.layer_A59:
layer_somethingon
layer_note1 40, 0xb4, 100
layer_jump .layer_A59
layer_end
.sound_moving_quicksand_death:
chan_setbank 3
chan_setinstr 7
chan_setlayer 0, .layer_A6A
chan_end
.layer_A6A:
layer_somethingon
layer_portamento 0x85, 37, 255
.layer_A6F:
layer_note1 34, 0xc8, 127
layer_jump .layer_A6F
layer_end
.sound_moving_shocked:
chan_setbank 3
chan_setinstr 9
chan_setlayer 0, .layer_A84
chan_setlayer 1, .layer_A82
chan_end
.layer_A82:
layer_transpose 24
.layer_A84:
layer_note1_long 43, 0x6, 127
layer_jump .layer_A84
layer_end
.sound_moving_flying:
chan_setbank 5
chan_setinstr 6
chan_setlayer 0, .layer_A9B
chan_setlayer 1, .layer_A97
chan_end
.layer_A97:
layer_setinstr 13
layer_transpose -12
.layer_A9B:
layer_somethingon
.layer_A9C:
layer_note1 43, 0x12c, 105
layer_jump .layer_A9C
.sound_moving_almost_drowning:
chan_setbank 9
chan_setinstr 3
chan_setval 40
chan_call .set_reverb
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_AB3
chan_end
.layer_AB3:
layer_transpose 12
.layer_AB5:
layer_note0 60, 0xc, 100, 127
layer_note0 60, 0x30, 100, 127
layer_jump .layer_AB5
.sound_moving_aim_cannon:
chan_jump .chan_29C2
.chan_AC3:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3368
chan_setlayer 0, .layer_AD8
chan_setlayer 1, .layer_AD6
chan_setlayer 2, .layer_AD4
chan_end
.layer_AD4:
layer_delay 0x4
.layer_AD6:
layer_delay 0x4
.layer_AD8:
layer_transpose 24
.layer_ADA:
layer_portamento 0x85, 32, 40
layer_note1 39, 0x9, 100
layer_note1 44, 0x6, 50
layer_note1 51, 0x3, 20
layer_jump .layer_ADA
.sound_moving_riding_shell_default:
chan_setbank 3
chan_setinstr 0
chan_setlayer 0, .layer_AF2
chan_end
.layer_AF2:
layer_transpose 4
layer_jump .layer_96E
.sound_moving_riding_shell_grass:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_B08
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 1
chan_end
.layer_B08:
layer_transpose 4
layer_jump .layer_988
.sound_moving_riding_shell_water:
chan_setbank 2
chan_setinstr 1
chan_setlayer 0, .layer_B21
chan_setlayer 1, .layer_B26
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 2
chan_end
.layer_B21:
layer_transpose 4
layer_jump .layer_9A8
.layer_B26:
layer_transpose 4
layer_jump .layer_9B3
.sound_moving_riding_shell_stone:
chan_setbank 3
chan_setinstr 3
chan_setlayer 0, .layer_B33
chan_end
.layer_B33:
layer_transpose 4
layer_jump .layer_9C3
.sound_moving_riding_shell_spooky:
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_B49
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 4
chan_end
.layer_B49:
layer_transpose 4
layer_jump .layer_9DD
.sound_moving_riding_shell_snow:
chan_setbank 3
chan_setinstr 5
chan_setlayer 0, .layer_B56
chan_end
.layer_B56:
layer_transpose 4
layer_jump .layer_9F1
.sound_moving_riding_shell_ice:
chan_setbank 3
chan_setinstr 6
chan_setlayer 0, .layer_B63
chan_end
.layer_B63:
layer_transpose 4
layer_jump .layer_A02
.sound_moving_riding_shell_sand:
chan_setbank 1
chan_setinstr 8
chan_setlayer 0, .layer_B79
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 7
chan_end
.layer_B79:
layer_transpose 4
layer_jump .layer_A1C
.sound_moving_riding_shell_lava:
chan_setlayer 0, .layer_B9F
chan_setlayer 1, .layer_BA8
.chan_B84:
chan_setbank 3
chan_setinstr 2
chan_setval 1
chan_call .delay
chan_setdecayrelease 30
chan_setbank 2
chan_setinstr 1
chan_setenvelope .envelope_3334
chan_setval 1
chan_call .delay
chan_jump .chan_B84
chan_end
.layer_B9F:
layer_somethingon
.layer_BA0:
layer_note1 42, 0x12c, 88
layer_jump .layer_BA0
layer_end
.layer_BA8:
layer_delay 1
.layer_BAA:
layer_portamento 0x81, 41, 255
layer_note1 56, 0xa, 127
layer_jump .layer_BAA
.channel2_table:
sound_ref .sound_mario_jump_yah
sound_ref .sound_mario_jump_wah
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_hoohoo
sound_ref .sound_mario_yahoo
sound_ref .sound_mario_uh
sound_ref .sound_mario_hrmm
sound_ref .sound_mario_wah2
sound_ref .sound_mario_whoa
sound_ref .sound_mario_eeuh
sound_ref .sound_mario_attacked
sound_ref .sound_mario_ooof
sound_ref .sound_mario_here_we_go
sound_ref .sound_mario_yawning
sound_ref .sound_mario_snoring1
sound_ref .sound_mario_snoring2
sound_ref .sound_mario_waaaooow
sound_ref .sound_mario_haha
sound_ref .sound_mario_panting1
sound_ref .sound_mario_uh2
sound_ref .sound_mario_on_fire
sound_ref .sound_mario_dying
sound_ref .sound_mario_panting_cold
sound_ref .sound_mario_coughing3
sound_ref .sound_mario_panting1
sound_ref .sound_mario_panting2
sound_ref .sound_mario_panting3
sound_ref .sound_mario_coughing1
sound_ref .sound_mario_coughing2
sound_ref .sound_mario_coughing3
sound_ref .sound_mario_punch_yah
sound_ref .sound_mario_punch_hoo
sound_ref .sound_mario_mama_mia
sound_ref .sound_mario_okey_dokey
sound_ref .sound_mario_ground_pound_wah
sound_ref .sound_mario_drowning
sound_ref .sound_mario_punch_wah
sound_ref .sound_mario_uh
sound_ref .sound_mario_hrmm
sound_ref .sound_mario_wah2
#ifdef VERSION_JP
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
#else
sound_ref .sound_peach_dear_mario
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_jump_hoo
sound_ref .sound_mario_yahoo
sound_ref .sound_mario_yahoo
sound_ref .sound_mario_yahoo
sound_ref .sound_mario_waha
sound_ref .sound_mario_yippee
sound_ref .sound_mario_doh
sound_ref .sound_mario_game_over
sound_ref .sound_mario_hello
sound_ref .sound_mario_press_start_to_play
sound_ref .sound_mario_twirl_bounce
sound_ref .sound_mario_snoring3
sound_ref .sound_mario_so_longa_bowser
sound_ref .sound_mario_ima_tired
sound_ref .sound_peach_mario
sound_ref .sound_peach_power_of_the_stars
sound_ref .sound_peach_thanks_to_you
sound_ref .sound_peach_thank_you_mario
sound_ref .sound_peach_something_special
sound_ref .sound_peach_bake_a_cake
sound_ref .sound_peach_for_mario
sound_ref .sound_peach_mario2
#endif
.sound_mario_jump_hoo:
chan_setbank 8
chan_setinstr 0
chan_setlayer 0, .layer_C3C
chan_end
.layer_C3C:
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
layer_transpose 2
#endif
layer_portamento 0x82, 41, 127
layer_note1 37, 0x14, 127
layer_end
.sound_mario_jump_wah:
chan_setbank 8
chan_setinstr 1
chan_setlayer 0, .layer_C4C
chan_end
.layer_C4C:
layer_transpose -2
.layer_C4E:
layer_note1 38, 0x18, 127
layer_end
.sound_mario_jump_yah:
chan_setbank 10
chan_setinstr 9
chan_setlayer 0, .layer_C5A
chan_end
.layer_C5A:
layer_transpose -2
.layer_C5C:
layer_portamento 0x82, 39, 200
layer_note1 38, 0x24, 120
layer_end
.sound_mario_hoohoo:
chan_setbank 10
chan_setinstr 1
chan_setlayer 0, .layer_C6C
chan_end
.layer_C6C:
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
layer_transpose 1
#endif
layer_portamento 0x82, 44, 200
layer_note1 39, 0x30, 127
layer_end
.sound_mario_yahoo:
chan_setbank 8
chan_setinstr 25
chan_setlayer 0, .layer_C7C
chan_end
.layer_C7C:
layer_note1 39, 0x5a, 97
layer_end
.sound_mario_uh:
chan_setbank 8
chan_setinstr 5
chan_setlayer 0, .layer_C92
chan_end
.layer_C92:
layer_transpose -2
layer_portamento 0x81, 41, 255
layer_note1 38, 0x2b, 115
layer_end
.sound_mario_hrmm:
chan_setbank 8
chan_setinstr 6
chan_setlayer 0, .layer_CA4
chan_end
.layer_CA4:
layer_transpose -2
layer_note1 44, 0x1e, 110
layer_end
.sound_mario_wah2:
chan_setbank 8
chan_setinstr 7
chan_setlayer 0, .layer_CB2
chan_end
.layer_CB2:
layer_transpose -3
layer_note1 39, 0x1c, 127
layer_end
.sound_mario_whoa:
chan_setbank 8
chan_setinstr 8
chan_setlayer 0, .layer_CC0
chan_end
.layer_CC0:
layer_transpose -2
layer_note1 40, 0x30, 110
layer_end
.sound_mario_eeuh:
chan_setbank 8
chan_setinstr 9
chan_setlayer 0, .layer_CCE
chan_end
.layer_CCE:
layer_transpose -2
layer_note1 40, 0x44, 105
layer_end
.sound_mario_attacked:
chan_setbank 8
chan_setinstr 10
chan_setlayer 0, .layer_CDC
chan_end
.layer_CDC:
layer_transpose -2
layer_note1 41, 0x30, 120
layer_end
.sound_mario_ooof:
chan_setbank 8
chan_setinstr 11
chan_setlayer 0, .layer_CEA
chan_end
.layer_CEA:
layer_transpose -2
layer_note1 38, 0x30, 127
layer_end
.sound_mario_here_we_go:
chan_setbank 8
chan_setinstr 12
chan_setlayer 0, .layer_CF8
chan_end
.layer_CF8:
layer_portamento 0x81, 38, 200
layer_note1 41, 0x85, 127
layer_end
.sound_mario_yawning:
chan_setbank 8
chan_setinstr 13
chan_setlayer 0, .layer_D09
chan_end
.layer_D09:
layer_transpose -2
layer_note1 39, 0x7f, 105
layer_end
.sound_mario_snoring1:
chan_setbank 8
chan_setinstr 14
chan_setlayer 0, .layer_D17
chan_end
.layer_D17:
layer_transpose -2
layer_note1 39, 0x60, 64
layer_end
.sound_mario_snoring2:
chan_setbank 8
chan_setinstr 15
chan_setlayer 0, .layer_D25
chan_end
.layer_D25:
layer_transpose -2
layer_note1 39, 0x5c, 52
layer_end
.sound_mario_waaaooow:
chan_setbank 10
chan_setinstr 0
chan_setlayer 0, .layer_D33
chan_end
.layer_D33:
layer_transpose -2
layer_note1 39, 0xaa, 127
layer_end
.sound_mario_haha:
chan_setbank 8
chan_setinstr 3
chan_setlayer 0, .layer_D42
chan_end
.layer_D42:
layer_transpose -1
layer_note1 39, 0x4d, 120
layer_end
.sound_mario_uh2:
chan_setbank 10
chan_setinstr 6
chan_setlayer 0, .layer_D50
chan_end
.layer_D50:
layer_transpose -2
layer_note1 43, 0x1e, 105
layer_end
.sound_mario_on_fire:
chan_setbank 10
chan_setinstr 5
chan_setlayer 0, .layer_D5E
chan_end
.layer_D5E:
layer_transpose -2
layer_note1 39, 0xc8, 127
layer_end
.sound_mario_dying:
chan_setbank 10
chan_setinstr 4
chan_setlayer 0, .layer_D6D
chan_end
.layer_D6D:
layer_transpose -2
layer_note1 39, 0x8c, 110
layer_end
.sound_mario_panting_cold:
chan_setbank 10
chan_setinstr 2
chan_setlayer 0, .layer_D7C
chan_end
.layer_D7C:
layer_transpose -2
layer_portamento 0x82, 35, 255
layer_note1 38, 0x30, 127
layer_end
.sound_mario_panting1:
chan_setbank 10
chan_setinstr 2
chan_setlayer 0, .layer_D8E
chan_end
.layer_D8E:
layer_transpose -2
layer_note1 39, 0x3c, 100
layer_end
.sound_mario_panting2:
chan_setbank 10
chan_setinstr 2
chan_setlayer 0, .layer_D9C
chan_end
.layer_D9C:
layer_transpose -2
layer_delay 0x4
layer_note1 38, 0x3c, 100
layer_end
.sound_mario_panting3:
chan_setbank 10
chan_setinstr 2
chan_setlayer 0, .layer_DAC
chan_end
.layer_DAC:
layer_transpose -2
layer_delay 0x8
layer_note1 40, 0x3c, 100
layer_end
.sound_mario_coughing1:
chan_setbank 10
chan_setinstr 7
chan_setlayer 0, .layer_DBC
chan_end
.layer_DBC:
layer_transpose -2
layer_note1 39, 0x10, 115
layer_end
.sound_mario_coughing2:
chan_setbank 10
chan_setinstr 7
chan_setlayer 0, .layer_DCA
chan_end
.layer_DCA:
layer_transpose -2
layer_portamento 0x81, 38, 255
layer_note1 41, 0x18, 115
layer_end
.sound_mario_coughing3:
chan_setbank 10
chan_setinstr 7
chan_setlayer 0, .layer_DDC
chan_end
.layer_DDC:
layer_transpose -2
layer_somethingon
layer_portamento 0x85, 38, 255
layer_note1 41, 0xc, 115
layer_note1 35, 0x12, 115
layer_end
.sound_mario_punch_yah:
chan_setbank 10
chan_setinstr 9
chan_setlayer 0, .layer_DFE
chan_setval 1
chan_call .delay
chan_setbank 0
chan_setinstr 0
chan_setlayer 1, .layer_538
chan_end
.layer_DFE:
layer_transpose -2
layer_jump .layer_C5C
.sound_mario_punch_hoo:
chan_setbank 10
chan_setinstr 10
chan_setlayer 0, .layer_E17
chan_setval 1
chan_call .delay
chan_setbank 0
chan_setinstr 0
chan_setlayer 1, .layer_548
chan_end
.layer_E17:
layer_transpose -2
layer_portamento 0x81, 42, 255
layer_note1 38, 0x30, 115
layer_end
.sound_mario_mama_mia:
chan_setbank 10
chan_setinstr 11
chan_setlayer 0, .layer_E29
chan_end
.layer_E29:
layer_portamento 0x81, 38, 255
layer_note1 36, 0x8c, 115
layer_end
.sound_mario_okey_dokey:
chan_setbank 10
chan_setinstr 12
chan_setlayer 0, .layer_E3A
chan_end
.layer_E3A:
layer_note1 39, 0x60, 115
layer_end
.sound_mario_ground_pound_wah:
chan_jump .sound_mario_wah2
.sound_mario_drowning:
chan_setbank 10
chan_setinstr 13
chan_setlayer 0, .layer_E49
chan_end
.layer_E49:
layer_note1 38, 0x91, 127
layer_end
.sound_mario_punch_wah:
chan_setbank 8
chan_setinstr 1
chan_setlayer 0, .layer_E62
chan_setval 1
chan_call .delay
chan_setbank 0
chan_setinstr 0
chan_setlayer 1, .layer_536
chan_end
.layer_E62:
layer_transpose -1
layer_jump .layer_C4E
#ifndef VERSION_JP
.sound_peach_dear_mario:
chan_setbank 10
chan_setinstr 15
chan_setlayer 0, .layer_E6F
chan_end
.layer_E6F:
layer_note1 39, 0x2bc, 127
layer_end
.sound_mario_waha:
chan_setbank 8
chan_setinstr 24
chan_setlayer 0, .layer_E7C
chan_end
.layer_E7C:
layer_note1 39, 0x5a, 127
layer_end
.sound_mario_yippee:
chan_setbank 8
chan_setinstr 25
chan_setlayer 0, .layer_E88
chan_end
.layer_E88:
layer_note1 39, 0x5a, 97
layer_end
.sound_mario_doh:
chan_setbank 8
chan_setinstr 16
chan_setlayer 0, .layer_E94
chan_end
.layer_E94:
layer_note1 41, 0x46, 127
layer_end
.sound_mario_game_over:
chan_setbank 8
chan_setinstr 17
chan_setlayer 0, .layer_EA0
chan_end
.layer_EA0:
layer_note1 39, 0x55, 110
layer_end
.sound_mario_hello:
chan_setbank 8
chan_setinstr 18
chan_setlayer 0, .layer_EAC
chan_end
.layer_EAC:
layer_note1 39, 0x46, 127
layer_end
.sound_mario_press_start_to_play:
chan_setbank 8
chan_setinstr 19
chan_setlayer 0, .layer_EB8
chan_end
.layer_EB8:
layer_note1 39, 0x12c, 127
layer_end
.sound_mario_twirl_bounce:
chan_setbank 8
chan_setinstr 20
chan_setlayer 0, .layer_EC5
chan_end
.layer_EC5:
layer_note1 39, 0x30, 127
layer_end
.sound_mario_snoring3:
chan_setbank 8
chan_setlayer 0, .layer_ECF
chan_end
.layer_ECF:
layer_delay 0x4e
.layer_ED1:
layer_loop 50
layer_call .layer_fn_EE1
layer_loopend
layer_setinstr 21
layer_note1 39, 0x44c, 127
layer_jump .layer_ED1
layer_end
.layer_fn_EE1:
layer_setinstr 21
layer_note1 37, 0x53, 127
layer_setinstr 15
layer_note1 37, 0x4e, 64
layer_end
.sound_mario_so_longa_bowser:
chan_setbank 8
chan_setinstr 22
chan_setlayer 0, .layer_EF7
chan_setlayer 1, .layer_EF7
chan_end
.layer_EF7:
layer_portamento 0x82, 42, 200
layer_note1 39, 0xc8, 110
layer_end
.sound_mario_ima_tired:
chan_setbank 8
chan_setinstr 23
chan_setlayer 0, .layer_F08
chan_end
.layer_F08:
layer_note1 39, 0x96, 110
layer_end
.sound_peach_mario:
chan_setbank 10
chan_setinstr 16
chan_setlayer 0, .layer_F18
chan_setlayer 1, .layer_F18
chan_end
.layer_F18:
layer_note1 39, 0x46, 127
layer_end
.sound_peach_power_of_the_stars:
chan_setbank 10
chan_setinstr 17
chan_setlayer 0, .layer_F27
chan_setlayer 1, .layer_F27
chan_end
.layer_F27:
layer_note1 39, 0x15e, 127
layer_end
.sound_peach_thanks_to_you:
chan_setbank 10
chan_setinstr 18
chan_setlayer 0, .layer_F37
chan_setlayer 1, .layer_F37
chan_end
.layer_F37:
layer_note1 39, 0xb4, 127
layer_end
.sound_peach_thank_you_mario:
chan_setbank 10
chan_setinstr 19
chan_setlayer 0, .layer_F47
chan_setlayer 1, .layer_F47
chan_end
.layer_F47:
layer_note1 39, 0x64, 127
layer_end
.sound_peach_something_special:
chan_setbank 10
chan_setinstr 20
chan_setlayer 0, .layer_F56
chan_setlayer 1, .layer_F56
chan_end
.layer_F56:
layer_note1 39, 0xdc, 127
layer_end
.sound_peach_bake_a_cake:
chan_setbank 10
chan_setinstr 21
chan_setlayer 0, .layer_F66
chan_setlayer 1, .layer_F66
chan_end
.layer_F66:
layer_note1 39, 0x190, 127
layer_end
.sound_peach_for_mario:
chan_setbank 10
chan_setinstr 22
chan_setlayer 0, .layer_F76
chan_setlayer 1, .layer_F76
chan_end
.layer_F76:
layer_note1 39, 0x50, 127
layer_end
.sound_peach_mario2:
chan_setbank 10
chan_setinstr 23
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_F8A
chan_setlayer 1, .layer_F8A
chan_end
.layer_F8A:
layer_note1 39, 0x50, 127
layer_end
#endif
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
.chan_unused_F9A_eu:
chan_setbank 8
chan_setinstr 0
chan_setlayer 0, .layer_FA2_eu
chan_end
.layer_FA2_eu:
layer_delay 0x5
layer_end
#endif
.channel38_table:
sound_ref .sound_general_activate_cap_switch
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_enter_hole
sound_ref .sound_general_flame_out
sound_ref .sound_general_open_wood_door
sound_ref .sound_general_close_wood_door
sound_ref .sound_general_open_iron_door
sound_ref .sound_general_close_iron_door
sound_ref .sound_general_bubbles
sound_ref .sound_general_moving_water
sound_ref .sound_general_swish_water
sound_ref .sound_general_quiet_bubble
sound_ref .sound_general_volcano_explosion
sound_ref .sound_general_quiet_bubble2
sound_ref .sound_general_castle_trap_open
sound_ref .sound_general_wall_explosion
sound_ref .sound_general_coin
sound_ref .sound_general_coin
sound_ref .sound_general_coin_water
sound_ref .sound_general_coin_water
sound_ref .sound_general_coin_water
sound_ref .sound_general_coin_water
sound_ref .sound_general_short_star
sound_ref .sound_general_big_clock
sound_ref .sound_general_loud_pound
sound_ref .sound_general_loud_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_short_pound
sound_ref .sound_general_open_chest
sound_ref .sound_general_open_chest
sound_ref .sound_general_clam_shell1
sound_ref .sound_general_clam_shell1
sound_ref .sound_general_box_landing
sound_ref .chan_12EB
sound_ref .sound_general_clam_shell2
sound_ref .sound_general_clam_shell3
sound_ref .sound_general_painting_eject
sound_ref .sound_general_painting_eject
sound_ref .sound_general_painting_eject
sound_ref .sound_general_painting_eject
sound_ref .sound_menu_star_sound
sound_ref .sound_general_platform
sound_ref .sound_general_bobomb_explosion
sound_ref .sound_general_bowser_bomb_explosion
sound_ref .sound_general_coin_spurt
sound_ref .sound_general_explosion6
sound_ref .chan_13D4
sound_ref .sound_general_coin
sound_ref .sound_general_boat_tilt1
sound_ref .sound_general_boat_tilt2
sound_ref .sound_general_coin_drop
sound_ref .chan_1429
sound_ref .sound_general_pendulum_swing
sound_ref .sound_general_chain_chomp1
sound_ref .sound_general_chain_chomp2
sound_ref .sound_general_door_turn_key
sound_ref .sound_general_moving_in_sand
sound_ref .chan_1519
sound_ref .sound_general_moving_platform_switch
sound_ref .sound_general_cage_open
sound_ref .sound_general_quiet_pound1
sound_ref .sound_general_break_box
sound_ref .sound_general_door_insert_key
sound_ref .sound_general_quiet_pound2
sound_ref .sound_general_big_pound
sound_ref .chan_15CD
sound_ref .chan_15DA
sound_ref .sound_general_cannon_up
sound_ref .sound_general_grindel_spindel_roll
sound_ref .sound_general_explosion7
sound_ref .sound_general_shake_coffin
sound_ref .sound_general_pyramid_top_spin
sound_ref .sound_general_pyramid_top_explosion
sound_ref .sound_general_race_gun_shot
sound_ref .sound_general_star_door_open
sound_ref .sound_general_star_door_close
sound_ref .sound_general_bird_chirp2
sound_ref .sound_obj_bird_chirp3
sound_ref .sound_obj_bird_chirp1
sound_ref .sound_air_castle_outdoors_ambient
sound_ref .sound_general_switch_tick_fast
sound_ref .sound_general_switch_tick_slow
sound_ref .sound_general_pound_rock
sound_ref .sound_general_star_appears
sound_ref .sound_general_collect_1up
sound_ref .sound_general_rotating_block_alert
sound_ref .sound_general_button_press
sound_ref .sound_general_elevator_move
sound_ref .sound_general_swish_air
sound_ref .sound_general_haunted_chair
sound_ref .sound_general_soft_landing
sound_ref .sound_general_haunted_chair_move
sound_ref .sound_general_bowser_explode
sound_ref .sound_general_bowser_key
sound_ref .sound_general_bowser_platform
sound_ref .sound_general_1up_appear
sound_ref .sound_general_heart_spin
sound_ref .sound_general_pound_wood_post
sound_ref .sound_general_water_level_trig
sound_ref .sound_general_switch_door_open
sound_ref .sound_general_red_coin
sound_ref .sound_general_birds_fly_away
sound_ref .sound_general_right_answer
sound_ref .sound_general_metal_pound
sound_ref .sound_general_boing1
sound_ref .sound_general_boing2
sound_ref .sound_general_yoshi_walk
sound_ref .sound_general_enemy_alert1
sound_ref .sound_general_yoshi_talk
sound_ref .sound_general_splattering
sound_ref .sound_general_boing3
sound_ref .sound_general_grand_star
sound_ref .sound_general_grand_star_jump
sound_ref .sound_general_boat_rock
#ifdef VERSION_JP
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_enter_hole
sound_ref .sound_general_open_wood_door
sound_ref .sound_general_close_wood_door
sound_ref .sound_general_open_iron_door
sound_ref .sound_general_close_iron_door
sound_ref .sound_general_bubbles
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_enter_hole
#else
sound_ref .sound_general_vanish_sfx
sound_ref .sound_menu_enter_hole
sound_ref .sound_general_red_coin
sound_ref .sound_general_birds_fly_away
sound_ref .sound_general_right_answer
sound_ref .sound_general_metal_pound
sound_ref .sound_general_boing1
sound_ref .sound_general_boing2
sound_ref .sound_general_yoshi_walk
sound_ref .sound_general_enemy_alert1
#endif
.sound_general_activate_cap_switch:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_109F
chan_delay 1
chan_setbank 4
chan_setinstr 9
chan_setlayer 1, .layer_1537
chan_end
.layer_109F:
layer_portamento 0x1, 27, 0x28
layer_note1 37, 0x7f, 120
layer_end
.sound_menu_enter_hole:
chan_setbank 4
chan_setinstr 0
chan_setlayer 0, .layer_10AF
chan_end
.layer_10AF:
layer_note1 39, 0x30, 85
layer_end
.sound_general_flame_out:
chan_setbank 3
chan_setinstr 8
chan_setenvelope .envelope_3314
chan_setlayer 0, .layer_10BE
chan_end
.layer_10BE:
layer_somethingon
layer_portamento 0x85, 34, 255
layer_note1 43, 0x8, 127
layer_note1 27, 0x7f, 127
layer_end
.sound_general_open_wood_door:
chan_setbank 4
chan_setinstr 1
chan_setlayer 0, .layer_10D2
chan_end
.layer_10D2:
layer_note1 39, 0x18, 100
layer_setinstr 2
layer_note1 39, 0x48, 60
layer_end
.sound_general_close_wood_door:
chan_setbank 4
chan_setinstr 1
chan_setlayer 0, .layer_10E3
chan_end
.layer_10E3:
layer_note1 37, 0x6, 100
layer_note1 34, 0x18, 100
layer_end
.sound_general_open_iron_door:
chan_setbank 4
chan_setinstr 4
chan_setlayer 0, .layer_10FE
chan_setlayer 1, .layer_1108
chan_setval 6
chan_call .delay
chan_setbank 4
chan_setinstr 3
chan_end
.layer_10FE:
layer_delay 0xf
layer_portamento 0x81, 39, 255
layer_note1 44, 0x38, 115
layer_end
.layer_1108:
layer_portamento 0x81, 44, 255
layer_note1 34, 0x2c, 85
layer_end
.sound_general_close_iron_door:
chan_setbank 4
chan_setinstr 4
chan_setlayer 0, .layer_1118
chan_end
.layer_1118:
layer_note1 39, 0x30, 115
layer_end
.sound_general_bubbles:
chan_setbank 4
chan_setinstr 6
chan_setlayer 0, .layer_1124
chan_end
.layer_1124:
layer_transpose 24
layer_note1 39, 0xa, 65
layer_note1 39, 0x9, 70
layer_note1 39, 0x8, 75
layer_end
.sound_general_moving_water:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_1138
chan_end
.layer_1138:
layer_note1 39, 0x91, 127
layer_end
.sound_obj_sushi_shark_water_sound:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_1145
chan_end
.layer_1145:
layer_portamento 0x81, 27, 255
layer_note1 32, 0x60, 127
layer_end
.sound_general_quiet_bubble:
chan_setbank 4
chan_setinstr 6
chan_setlayer 0, .layer_1155
chan_end
.layer_1155:
layer_note1 39, 0x14, 70
layer_end
.sound_general_volcano_explosion:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_1161
chan_end
.layer_1161:
layer_note1 32, 0x18, 127
layer_portamento 0x81, 41, 255
layer_note1 27, 0x96, 127
layer_end
.sound_general_quiet_bubble2:
chan_setbank 4
chan_setinstr 6
chan_setlayer 0, .layer_1175
chan_end
.layer_1175:
layer_portamento 0x81, 34, 255
layer_note1 37, 0x18, 80
layer_end
.sound_general_castle_trap_open:
chan_setbank 4
chan_setinstr 8
chan_setlayer 0, .layer_1185
chan_end
.layer_1185:
layer_note1 39, 0x40, 120
layer_end
.sound_general_wall_explosion:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_109F
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 9
chan_setlayer 1, .layer_119D
chan_end
.layer_119D:
layer_transpose -12
.layer_fn_119F:
layer_portamento 0x83, 27, 255
layer_note0 55, 0x4, 127, 64
layer_note0 51, 0x5, 127, 64
layer_note0 48, 0x4, 127, 64
layer_note0 44, 0x6, 127, 64
layer_note0 41, 0x9, 127, 64
layer_note0 39, 0x6, 127, 64
.layer_11BB:
layer_note0 37, 0x7, 127, 64
layer_note0 34, 0x5, 127, 64
layer_note0 31, 0x8, 127, 64
layer_note0 29, 0x9, 127, 64
layer_note0 24, 0x8, 127, 64
layer_end
.sound_general_coin:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setvibratoextent 3
chan_setvibratorate 60
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_11E4
chan_end
.layer_11E4:
layer_transpose 24
.layer_fn_11E6:
layer_note1 25, 0x2, 40
layer_note1 37, 0x7, 85
layer_note1 30, 0x5, 40
layer_note1 42, 0x37, 85
layer_end
.sound_general_coin_water:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setvibratoextent 12
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_1242
chan_setlayer 1, .layer_1254
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 6
chan_setval 1
chan_call .delay
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setval 9
chan_call .delay
chan_setbank 4
chan_setinstr 6
chan_setval 3
chan_call .delay
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setval 6
chan_call .delay
chan_setbank 4
chan_setinstr 6
chan_setval 49
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_1242:
layer_delay 1
layer_setinstr 6
layer_transpose 22
layer_note1 39, 0xa, 55
layer_note1 39, 0x9, 60
layer_note1 39, 0x8, 65
layer_delay 0x29
layer_end
.layer_1254:
layer_transpose 23
layer_call .layer_fn_11E6
layer_end
.sound_general_short_star:
chan_setbank 4
chan_setinstr 14
chan_setenvelope .envelope_33FC
chan_setlayer 0, .layer_1265
chan_end
.layer_1265:
layer_portamento 0x81, 34, 127
layer_note1 38, 0x30, 127
layer_delay 0x30
layer_end
.sound_general_big_clock:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1277
chan_end
.layer_1277:
layer_note1 37, 0xa, 100
layer_note1 26, 0x12, 120
layer_end
.sound_general_loud_pound:
chan_setbank 4
chan_setinstr 10
chan_setlayer 0, .layer_1286
chan_end
.layer_1286:
layer_note1 39, 0xf, 120
layer_end
.sound_general_short_pound:
chan_setbank 4
chan_setinstr 10
chan_setlayer 0, .layer_1292
chan_end
.layer_1292:
layer_note1 37, 0x12, 120
layer_end
.sound_general_open_chest:
chan_setbank 7
chan_setinstr 1
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_12AF
chan_setlayer 1, .layer_12AF
chan_setval 6
chan_call .delay
chan_setbank 4
chan_setinstr 4
chan_end
.layer_12AF:
layer_note1 43, 0x5, 127
layer_note1 62, 0x9, 127
layer_setinstr 2
layer_portamento 0x81, 27, 255
layer_note1 25, 0x5a, 108
layer_end
.sound_general_clam_shell1:
chan_setbank 4
chan_setinstr 11
chan_setlayer 0, .layer_12C7
chan_end
.layer_12C7:
layer_note1 24, 0xa, 110
.layer_12CA:
layer_setinstr 5
layer_portamento 0x82, 27, 255
layer_note1 32, 0x73, 127
layer_end
.sound_general_box_landing:
chan_setbank 4
chan_setinstr 1
chan_setenvelope .envelope_33CC
chan_setlayer 0, .layer_12DF
chan_end
.layer_12DF:
layer_somethingon
layer_note1 39, 0x4, 127
layer_portamento 0x82, 36, 255
layer_note1 27, 0x9, 115
layer_end
.chan_12EB:
chan_setbank 4
chan_setinstr 2
chan_setenvelope .envelope_3454
chan_setlayer 0, .layer_12F9
chan_setlayer 1, .layer_12FB
chan_end
.layer_12F9:
layer_transpose 3
.layer_12FB:
layer_portamento 0x2, 17, 0x28
layer_note1 5, 0x60, 127
layer_end
.sound_general_clam_shell2:
chan_setbank 4
chan_setinstr 11
chan_setlayer 0, .layer_130B
chan_end
.layer_130B:
layer_note1 19, 0x6, 110
layer_note1 31, 0x6, 110
layer_transpose 8
layer_jump .layer_12CA
.sound_general_clam_shell3:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_131E
chan_end
.layer_131E:
layer_setinstr 11
layer_note1 31, 0x6, 127
layer_note1 19, 0x6, 127
layer_setinstr 5
layer_portamento 0x82, 20, 255
layer_note1 32, 0x5a, 127
layer_end
.sound_general_painting_eject:
chan_setbank 4
chan_setinstr 13
chan_setlayer 0, .layer_1338
chan_end
.layer_1338:
layer_note1 39, 0x73, 95
layer_end
.sound_menu_star_sound:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1344
chan_end
.layer_1344:
layer_note1 39, 0x7f, 115
layer_end
.sound_general_platform:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_1350
chan_end
.layer_1350:
layer_note0 36, 0xd, 115, 20
layer_note0 34, 0xe, 115, 20
layer_note0 32, 0xd, 115, 20
layer_note0 31, 0xa, 115, 20
layer_note0 30, 0x7, 115, 20
layer_note0 29, 0x60, 115, 20
layer_end
.sound_general_bobomb_explosion:
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_33EC
chan_setlayer 0, .layer_137B
chan_setlayer 1, .layer_1377
chan_end
.layer_1377:
layer_note1 15, 0x7f, 127
layer_end
.layer_137B:
layer_note1 55, 0x6, 115
layer_note1 43, 0xc, 115
layer_note1 34, 0x7f, 127
layer_end
.sound_general_bowser_bomb_explosion:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_1395
chan_setlayer 1, .layer_13A0
chan_setlayer 2, .layer_1393
chan_end
.layer_1393:
layer_transpose 6
.layer_1395:
layer_note1 44, 0x7, 127
layer_note1 39, 0x8, 127
layer_note1 36, 0x96, 127
layer_end
.layer_13A0:
layer_note1 22, 0x96, 127
layer_end
.sound_general_coin_spurt:
chan_setbank 9
chan_setinstr 3
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_13B2
chan_end
.layer_13B2:
layer_portamento 0x81, 36, 255
layer_note1 48, 0x6, 80
layer_end
.sound_general_explosion6:
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_33EC
chan_setlayer 0, .layer_13C8
chan_setlayer 1, .layer_13D0
chan_end
.layer_13C8:
layer_portamento 0x81, 56, 255
layer_note1 20, 0x78, 80
layer_end
.layer_13D0:
layer_note1 15, 0x78, 127
layer_end
.chan_13D4:
chan_setbank 4
chan_setinstr 6
chan_setlayer 0, .layer_13DC
chan_end
.layer_13DC:
layer_portamento 0x81, 37, 255
layer_note1 39, 0x8, 127
layer_setinstr 5
layer_portamento 0x81, 20, 255
layer_note1 25, 0x60, 127
layer_end
.sound_general_boat_tilt1:
chan_setbank 4
chan_setinstr 2
chan_setlayer 0, .layer_13F5
chan_end
.layer_13F5:
layer_portamento 0x81, 12, 255
layer_note1 13, 0x6e, 127
layer_end
.sound_general_boat_tilt2:
chan_setbank 4
chan_setinstr 2
chan_setlayer 0, .layer_1405
chan_end
.layer_1405:
layer_portamento 0x81, 15, 255
layer_note1 11, 0x6e, 127
layer_end
.sound_general_coin_drop:
chan_setbank 9
chan_setinstr 3
chan_setval 40
chan_call .set_reverb
#if defined(VERSION_SH) || defined(VERSION_CN)
chan_setreverb 40
#endif
chan_setlayer 0, .layer_141A
chan_end
.layer_141A:
layer_transpose 24
#if defined(VERSION_SH) || defined(VERSION_CN)
layer_note1 51, 0xc, 90
#endif
layer_note1 39, 0x4, 90
layer_note1 51, 0xc, 90
layer_note1 39, 0x4, 50
layer_note1 51, 0xc, 50
layer_end
.chan_1429:
chan_setbank 9
chan_setinstr 3
chan_setval 40
chan_call .set_reverb
chan_setlayer 0, .layer_1436
chan_end
.layer_1436:
layer_transpose 12
layer_note1 39, 0x3, 90
layer_note1 51, 0x3, 90
layer_note1 27, 0xa, 115
layer_note1 39, 0x3, 50
layer_note1 51, 0x3, 50
layer_note1 27, 0xa, 75
layer_end
.sound_general_pendulum_swing:
chan_setbank 4
chan_setinstr 9
chan_setval 50
chan_call .set_reverb
chan_setlayer 0, .layer_1463
chan_setval 13
chan_call .delay
chan_setdecayrelease 30
chan_setbank 4
chan_setinstr 2
chan_end
.layer_1463:
layer_note1 33, 0xc, 100
layer_note1 25, 0x28, 120
layer_portamento 0x81, 22, 255
layer_note1 15, 0x48, 80
layer_end
.sound_general_chain_chomp1:
chan_setbank 1
chan_setinstr 1
chan_setval 15
chan_call .set_reverb
chan_setlayer 0, .layer_148A
chan_setval 1
chan_call .delay
chan_setbank 1
chan_setinstr 7
chan_setenvelope .envelope_3368
chan_end
.layer_148A:
layer_note1 29, 0xc, 120
layer_transpose 12
layer_portamento 0x81, 51, 255
layer_note1 53, 0x6, 118
layer_portamento 0x81, 52, 255
layer_note1 54, 0x9, 118
layer_end
.sound_general_chain_chomp2:
chan_setbank 7
#ifdef VERSION_JP
chan_setinstr 8
#else
chan_setinstr 14
#endif
chan_setval 15
chan_call .set_reverb
chan_setlayer 0, .layer_14C6
chan_setlayer 1, .layer_14E3
#ifndef VERSION_JP
chan_setlayer 2, .layer_14E3
#endif
chan_setval 1
chan_call .delay
chan_setenvelope .envelope_3368
chan_setbank 1
chan_setinstr 7
chan_setval 13
chan_call .delay
chan_setbank 7
#ifdef VERSION_JP
chan_setinstr 8
#else
chan_setinstr 14
#endif
chan_end
.layer_14C6:
layer_delay 1
layer_transpose 12
layer_portamento 0x81, 54, 255
layer_note0 55, 0x6, 118, 127
layer_portamento 0x81, 55, 255
layer_note0 56, 0x5, 118, 127
layer_portamento 0x81, 57, 255
layer_note0 58, 0xc, 118, 127
layer_end
.layer_14E3:
layer_loop 2
#ifdef VERSION_JP
layer_portamento 0x81, 36, 255
layer_note1 24, 0x18, 127
#else
layer_note1 34, 0x19, 100
#endif
layer_loopend
layer_end
.sound_general_door_turn_key:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_14F2
chan_end
.layer_14F2:
layer_note0 31, 0x12, 80, 80
layer_portamento 0x82, 53, 255
layer_note1 44, 0x7, 88
layer_end
.sound_general_moving_in_sand:
chan_setbank 3
chan_setinstr 5
chan_setenvelope .envelope_32D4
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_150E
chan_end
.layer_150E:
layer_note1 41, 0x4, 100
layer_note0 34, 0x14, 100, 100
layer_note1 29, 0x6, 115
layer_end
.chan_1519:
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_152B
chan_setlayer 1, .layer_1529
chan_setbank 4
chan_setinstr 1
chan_end
.layer_1529:
layer_transpose 1
.layer_152B:
layer_note1 15, 0x2c, 127
layer_end
.sound_general_moving_platform_switch:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1539
chan_end
.layer_1537:
layer_transpose -3
.layer_1539:
layer_note1 39, 0x6, 120
layer_portamento 0x81, 15, 255
layer_note1 8, 0xc, 120
layer_portamento 0x81, 27, 255
layer_note1 3, 0x18, 120
layer_end
.sound_general_cage_open:
chan_setbank 4
chan_setinstr 3
chan_setval 30
chan_call .set_reverb
chan_setlayer 0, .layer_1558
chan_end
.layer_1558:
layer_portamento 0x81, 19, 40
layer_note1 22, 0xb4, 115
layer_end
.sound_general_quiet_pound1:
chan_setbank 5
chan_setinstr 5
chan_setenvelope .envelope_3344
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_1571
chan_end
.layer_1571:
layer_note1 14, 0x34, 110
layer_delay 0x14
layer_end
.sound_general_break_box:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_1582
chan_setlayer 1, .layer_1582
chan_end
.layer_1582:
layer_somethingon
layer_portamento 0x85, 39, 255
layer_note1 36, 0x14, 110
layer_note1 38, 0x10, 110
layer_note1 27, 0x64, 110
layer_end
.sound_general_door_insert_key:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1599
chan_end
.layer_1599:
layer_note0 36, 0xa, 80, 80
layer_note0 24, 0xa, 80, 80
layer_end
.sound_general_quiet_pound2:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_15AA
chan_end
.layer_15AA:
layer_somethingon
layer_portamento 0x85, 35, 255
layer_note1 34, 0x60, 127
layer_note1 32, 0x60, 127
layer_note1 32, 0x30, 127
layer_end
.sound_general_big_pound:
chan_setbank 6
chan_setinstr 1
chan_setval 55
chan_call .set_reverb
chan_setlayer 0, .layer_15C6
chan_end
.layer_15C6:
layer_note1 32, 0xc, 127
layer_note1 27, 0x30, 127
layer_end
.chan_15CD:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_15D5
chan_end
.layer_15D5:
layer_note1 31, 0xc0, 127
layer_end
.chan_15DA:
chan_setbank 7
chan_setinstr 1
chan_setlayer 0, .layer_15EB
chan_setval 1
chan_call .delay
chan_setbank 5
chan_setinstr 5
chan_end
.layer_15EB:
layer_note1 24, 0xc, 127
layer_note1 22, 0x48, 127
layer_end
.sound_general_cannon_up:
chan_setbank 6
chan_setinstr 10
chan_setlayer 0, .layer_15FA
chan_end
.layer_15FA:
layer_note1 44, 0xfa, 127
layer_end
.sound_general_grindel_spindel_roll:
chan_setbank 6
chan_setinstr 1
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_160C
chan_end
.layer_160C:
layer_note1 29, 0xc, 120
layer_note1 24, 0x24, 120
layer_end
.sound_general_explosion7:
chan_setbank 3
chan_setinstr 5
chan_setenvelope .envelope_3358
chan_setlayer 0, .layer_162D
chan_setlayer 1, .layer_1637
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_3358
chan_end
.layer_162D:
layer_delay 1
layer_note1 36, 0xc, 127
layer_note1 32, 0x96, 127
layer_end
.layer_1637:
layer_note1 24, 0x60, 127
layer_end
.sound_general_shake_coffin:
chan_setbank 6
chan_setinstr 15
chan_setenvelope .envelope_3304
chan_setlayer 0, .layer_1646
chan_end
.layer_1646:
layer_note1 31, 0xa, 127
layer_note1 43, 0x10, 127
layer_end
.sound_general_pyramid_top_spin:
chan_setbank 4
chan_setinstr 15
chan_setval 30
chan_call .set_reverb
chan_setlayer 0, .layer_1660
chan_setlayer 1, .layer_1669
chan_setlayer 2, .layer_1665
chan_end
.layer_1660:
layer_note1 20, 0x226, 0
layer_end
.layer_1665:
layer_delay 0x4
layer_transpose -12
.layer_1669:
layer_note1 27, 0x4f, 93
layer_note1 28, 0x41, 99
layer_note1 29, 0x36, 101
layer_note1 30, 0x31, 109
layer_note1 36, 0xe, 113
layer_note1 38, 0x3b, 123
layer_note1 32, 0x27, 105
layer_note1 35, 0x60, 92
layer_note1 32, 0xe, 100
layer_note1 36, 0xb, 105
layer_note1 39, 0x31, 116
layer_end
.sound_general_pyramid_top_explosion:
chan_setbank 4
chan_setinstr 15
chan_setval 30
chan_call .set_reverb
chan_setenvelope .envelope_338C
chan_setlayer 0, .layer_16A1
chan_setlayer 1, .layer_16AA
chan_setlayer 2, .layer_16A6
chan_end
.layer_16A1:
layer_note1 24, 0x12c, 127
layer_end
.layer_16A6:
layer_delay 0x4
layer_transpose -12
.layer_16AA:
layer_note1 46, 0xe, 116
layer_note1 44, 0xb, 121
layer_note1 48, 0x12, 101
layer_note1 41, 0xf, 109
layer_note1 43, 0xfa, 113
layer_end
.sound_general_race_gun_shot:
chan_setbank 5
chan_setinstr 0
chan_setval 127
chan_call .set_reverb
chan_setlayer 0, .layer_16CE
chan_setlayer 1, .layer_16CE
chan_setlayer 2, .layer_16D2
chan_end
.layer_16CE:
layer_note1 49, 0x3a, 127
layer_end
.layer_16D2:
layer_delay 0xa
layer_note1 48, 0x30, 85
layer_end
.sound_general_star_door_open:
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_16E3
chan_end
.layer_16E3:
layer_portamento 0x81, 51, 96
layer_note1 58, 0x40, 100
layer_end
.sound_general_star_door_close:
chan_setbank 6
chan_setinstr 10
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_16F6
chan_end
.layer_16F6:
layer_portamento 0x82, 51, 96
layer_note1 58, 0x40, 100
layer_end
.sound_general_pound_rock:
chan_setbank 6
chan_setinstr 1
chan_setval 55
chan_call .set_reverb
chan_setlayer 0, .layer_170B
chan_end
.layer_170B:
layer_note1 27, 0x7, 127
layer_note1 15, 0x12, 127
layer_end
.sound_general_star_appears:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_171A
chan_end
.layer_171A:
layer_portamento 0x81, 43, 127
layer_note1 31, 0x7f, 115
layer_end
.sound_general_collect_1up:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setlayer 0, .layer_1734
chan_setdecayrelease 50
chan_setlayer 1, .layer_1732
chan_end
.layer_1732:
layer_delay 0x4
.layer_1734:
layer_transpose 24
layer_note1 31, 0xc, 100
layer_note1 34, 0xc, 100
layer_note1 43, 0xc, 100
layer_note1 39, 0xc, 100
layer_note1 41, 0xc, 100
layer_note1 46, 0x18, 100
layer_end
.sound_general_rotating_block_alert:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1751
chan_end
.layer_1751:
layer_call .layer_fn_1756
layer_transpose -4
.layer_fn_1756:
layer_note1 27, 0x5, 105
layer_portamento 0x81, 15, 255
layer_note1 8, 0xa, 100
layer_end
.sound_general_button_press:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1769
chan_end
.layer_1769:
layer_note1 8, 0x5, 127
layer_note1 18, 0x12, 127
layer_end
.sound_general_elevator_move:
chan_setbank 4
chan_setinstr 9
chan_setenvelope .envelope_33BC
chan_setlayer 0, .layer_177B
chan_end
.layer_177B:
layer_portamento 0x82, 5, 255
layer_note1 8, 0xa, 127
layer_end
.sound_general_swish_air:
chan_setbank 0
chan_setinstr 0
chan_setlayer 0, .layer_178B
chan_end
.layer_178B:
layer_note1 44, 0x6, 100
layer_portamento 0x81, 44, 255
layer_note1 32, 0x12, 100
layer_end
.sound_general_haunted_chair:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_17A1
chan_end
.layer_17A1:
layer_transpose 12
layer_portamento 0x85, 62, 255
layer_note1 38, 0x78, 93
layer_end
.sound_general_soft_landing:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_17B3
chan_end
.layer_17B3:
layer_note1 29, 0xc, 127
layer_end
.sound_general_haunted_chair_move:
chan_setbank 4
chan_setinstr 1
chan_setlayer 0, .layer_17C4
chan_setlayer 1, .layer_17C2
chan_end
.layer_17C2:
layer_delay 1
.layer_17C4:
layer_note1 34, 0x6, 127
layer_note1 33, 0x7, 127
layer_note1 33, 0x6, 127
layer_note1 34, 0x6, 127
layer_end
.sound_general_bowser_explode:
chan_setbank 6
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_17E8
chan_setval 1
chan_call .delay
chan_setenvelope .envelope_32D4
chan_setlayer 1, .layer_17F3
chan_setlayer 2, .layer_17EF
chan_end
.layer_17E8:
layer_setinstr 10
layer_transpose 24
layer_jump .layer_17F5
.layer_17EF:
layer_delay 0x2
layer_transpose 12
.layer_17F3:
layer_setinstr 0
.layer_17F5:
layer_portamento 0x83, 3, 255
layer_note1 15, 0x30, 100
layer_note1 17, 0x2c, 100
layer_note1 19, 0x28, 100
layer_note1 20, 0x24, 100
layer_note1 22, 0x20, 100
layer_note1 24, 0x1c, 100
layer_note1 26, 0x18, 100
layer_note1 27, 0x14, 100
layer_note1 29, 0x11, 100
layer_note1 31, 0xe, 100
layer_note1 32, 0xc, 100
.layer_181A:
layer_note1 34, 0xa, 100
layer_jump .layer_181A
layer_end
.sound_general_bowser_key:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_171A
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_33EC
chan_setlayer 1, .layer_137B
chan_setval 100
chan_call .delay
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1844
chan_end
.layer_1844:
layer_transpose -6
layer_portamento 0x81, 43, 127
layer_note1 31, 0xfa, 115
layer_end
.sound_general_bowser_platform:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_185C
chan_setlayer 1, .layer_185A
chan_end
.layer_185A:
layer_transpose 2
.layer_185C:
layer_note1 39, 0xc, 127
layer_jump .layer_1350
.sound_general_1up_appear:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_186A
chan_end
.layer_186A:
layer_portamento 0x83, 39, 128
layer_note1 42, 0x2d, 115
layer_note1 42, 0x2d, 115
layer_note1 42, 0x2d, 115
layer_note1 44, 0x7f, 115
layer_end
.sound_general_heart_spin:
chan_setbank 9
chan_setinstr 3
chan_setval 30
chan_call .set_reverb
chan_setlayer 0, .layer_1888
chan_end
.layer_1888:
layer_transpose 12
layer_portamento 0x83, 3, 255
layer_note1 27, 0xa, 85
layer_note1 32, 0xa, 85
layer_note1 39, 0xa, 85
layer_note1 44, 0xa, 85
layer_note1 51, 0xa, 85
layer_note1 56, 0xa, 85
layer_note1 51, 0xa, 45
layer_note1 56, 0xa, 35
layer_end
.sound_general_pound_wood_post:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_18B8
chan_delay 1
chan_setbank 4
chan_setinstr 9
chan_setlayer 1, .layer_1537
chan_end
.layer_18B8:
layer_portamento 0x1, 27, 0x28
layer_note1 32, 0x32, 120
layer_end
.sound_general_water_level_trig:
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_2DBF
chan_setval 9
chan_call .delay
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3454
chan_setlayer 0, .layer_2D26
chan_end
.sound_general_switch_door_open:
chan_setbank 4
chan_setinstr 9
chan_setlayer 0, .layer_1539
chan_setval 12
chan_call .delay
chan_setbank 6
chan_setinstr 1
chan_setlayer 0, .layer_18EB
chan_end
.layer_18EB:
layer_portamento 0x82, 15, 255
layer_note1 31, 0x14, 127
layer_end
.sound_general_red_coin:
#ifdef VERSION_JP
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_1909
chan_setlayer 1, .layer_1902
chan_setlayer 2, .layer_1907
#else
#if defined(VERSION_EU) || defined(VERSION_SH) || defined(VERSION_CN)
chan_setbank 9
chan_setinstr 3
#else
chan_setinstr 128
#endif
chan_setenvelope .envelope_3378
// Small bugfix: .main_loop_023589 expects layer 0 to live the longest.
// I don't think this actually makes any audible difference given the
// silence at the end.
chan_setlayer 0, .layer_1907
chan_setlayer 1, .layer_1902
chan_setlayer 2, .layer_1909
#endif
chan_end
.layer_1902:
layer_transpose 7
layer_jump .layer_190B
.layer_1907:
layer_delay 0x6
.layer_1909:
layer_transpose 12
.layer_190B:
layer_note0 46, 0xc, 90, 20
layer_note0 45, 0xc, 90, 20
layer_note0 46, 0xc, 90, 20
layer_note0 58, 0x10, 100, 80
layer_note0 58, 0x10, 60, 80
layer_note0 58, 0x10, 40, 80
layer_note0 58, 0x10, 25, 80
// This small delay should not have any effect, but decreases the probability of
// encountering double red coin glitch. Without it, layer 0 finishes in 1.04
// seconds, and with some bad luck around scheduling/lag the sound spawner with
// a lifetime of 30 frames that creates the sound may deactivate on the same
// frame. That leads to double sound glitch on JP, see src/audio/external.c.
// With the delay, the same thing can still happen but requires more CPU lag.
layer_delay 0xa
layer_end
.sound_general_birds_fly_away:
chan_setbank 5
chan_setinstr 13
chan_setenvelope .envelope_33DC
chan_setval 20
chan_call .set_reverb
chan_setval 127
chan_iowriteval 7
chan_setlayer 0, .layer_195F
chan_setlayer 1, .layer_1986
chan_setlayer 2, .layer_1982
.chan_1942:
chan_setval 4
chan_call .delay
chan_ioreadval 7
chan_subtract 1
chan_beqz .chan_1957
chan_iowriteval 7
chan_writeseq_nextinstr 0, 1
chan_setvolscale 127
chan_jump .chan_1942
.chan_1957:
chan_setval 127
chan_call .delay
chan_jump .chan_1957
.layer_195F:
layer_setinstr 9
layer_note1 40, 0x6, 122
layer_note1 41, 0x4, 112
layer_note1 43, 0x5, 109
layer_note1 44, 0x6, 124
layer_note1 44, 0x4, 116
layer_note1 45, 0x7, 114
layer_delay 0x19
.layer_1975:
layer_note1 43, 0x7f, 122
layer_note1 43, 0xa, 127
layer_note1 43, 0x64, 114
layer_jump .layer_1975
layer_end
.layer_1982:
layer_transpose 4
layer_delay 0x2
.layer_1986:
layer_portamento 0x83, 39, 255
layer_loop 2
layer_note1 55, 0x6, 120
layer_note1 60, 0x9, 112
layer_delay 0x4
layer_loopend
layer_note1 56, 0x5, 125
layer_note1 62, 0xa, 109
layer_delay 0x5
layer_note1 56, 0x6, 123
layer_note1 62, 0x7, 119
layer_delay 0x8
.layer_19A5:
layer_loop 10
layer_note1 57, 0x5, 120
layer_note1 62, 0x8, 120
layer_delay 0x5
layer_loopend
layer_loop 10
layer_note1 59, 0x7, 115
layer_note1 60, 0x7, 113
layer_delay 0x2
layer_loopend
layer_loop 10
layer_note1 55, 0x8, 115
layer_note1 58, 0x6, 113
layer_delay 0x5
layer_loopend
layer_jump .layer_19A5
layer_end
.sound_general_right_answer:
chan_setbank 9
chan_setinstr 3
chan_setval 40
chan_call .set_reverb
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_19DA
chan_end
.layer_19DA:
layer_loop 2
layer_note1 62, 0x6, 110
layer_note1 62, 0x2, 45
layer_note1 58, 0x6, 110
layer_note1 58, 0x2, 45
layer_loopend
layer_end
.sound_general_metal_pound:
chan_setbank 7
chan_setinstr 1
chan_setlayer 0, .layer_1A00
chan_setlayer 1, .layer_19FE
chan_setval 1
chan_call .delay
chan_setbank 5
chan_setinstr 5
chan_end
.layer_19FE:
layer_transpose -6
.layer_1A00:
layer_note1 15, 0xc, 127
layer_note1 17, 0x3a, 127
layer_end
.sound_general_boing1:
chan_setbank 5
chan_setinstr 14
chan_setlayer 0, .layer_1A0F
chan_end
.layer_1A0F:
layer_portamento 0x82, 40, 127
layer_note1 38, 0x28, 100
layer_end
.sound_general_boing2:
chan_setbank 5
chan_setinstr 14
chan_setlayer 0, .layer_1A1F
chan_end
.layer_1A1F:
layer_portamento 0x82, 43, 127
layer_note1 39, 0x36, 100
layer_end
.sound_general_yoshi_walk:
chan_jump .sound_obj_koopa_the_quick_walk
.sound_general_enemy_alert1:
chan_jump .sound_obj_goomba_alert
.sound_general_yoshi_talk:
chan_setbank 0
chan_setinstr 3
chan_setlayer 0, .layer_1A35
chan_end
.layer_1A35:
layer_note1 39, 0x32, 127
layer_end
.sound_general_splattering:
chan_setbank 6
chan_setinstr 2
chan_setlayer 0, .layer_1A44
chan_setlayer 1, .layer_1A44
chan_end
.layer_1A44:
layer_transpose 7
layer_call .layer_fn_1A4B
layer_transpose -2
.layer_fn_1A4B:
layer_portamento 0x83, 31, 255
layer_note1 51, 0x6, 127
layer_note1 56, 0xc, 127
layer_end
.sound_general_boing3:
chan_setbank 9
chan_setinstr 6
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_1A66
chan_setlayer 1, .layer_1A66
chan_end
.layer_1A66:
layer_portamento 0x82, 39, 255
layer_note1 31, 0x60, 100
layer_end
.sound_general_grand_star:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1A79
chan_setlayer 1, .layer_1A7D
chan_end
.layer_1A79:
layer_transpose 3
layer_delay 0x5
.layer_1A7D:
layer_somethingon
layer_portamento 0x85, 31, 255
layer_note1 34, 0x12c, 127
layer_end
.sound_general_grand_star_jump:
chan_setbank 4
chan_setinstr 14
chan_setenvelope .envelope_3358
chan_setlayer 0, .layer_1AA0
chan_setval 1
chan_call .delay
chan_setenvelope .envelope_3358
chan_setlayer 1, .layer_1AAA
chan_setlayer 2, .layer_1AA8
chan_end
.layer_1AA0:
layer_portamento 0x81, 32, 64
layer_note1 38, 0x46, 127
layer_end
.layer_1AA8:
layer_delay 0x4
.layer_1AAA:
layer_delay 0x4
layer_portamento 0x81, 36, 40
layer_note1 41, 0xc, 127
layer_end
#ifdef VERSION_JP
.sound_general_boat_rock:
chan_setbank 9
chan_setinstr 0
chan_setenvelope .envelope_3438
chan_setvibratorate 25
chan_setvibratoextent 110
chan_setlayer 0, .layer_1943_jp
chan_setval 40
chan_call .delay
chan_end
.layer_1943_jp:
layer_portamento 0x1, 32, 0x7f
layer_note1 60, 0x28, 100
layer_end
#else
.sound_general_boat_rock:
chan_setbank 4
chan_setinstr 2
chan_setlayer 0, .layer_1AC1
chan_setlayer 1, .layer_1ABF
chan_end
.layer_1ABF:
layer_transpose 12
.layer_1AC1:
layer_portamento 0x81, 7, 255
layer_note1 15, 0x3c, 127
layer_portamento 0x81, 20, 200
layer_note1 7, 0x5a, 127
layer_end
.sound_general_vanish_sfx:
chan_setbank 9
chan_setinstr 3
chan_setvibratoextent 70
chan_setvibratorate 70
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_1AEB
chan_setlayer 1, .layer_1AE9
chan_setval 35
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_1AE9:
layer_transpose 1
.layer_1AEB:
layer_portamento 0x81, 19, 255
layer_note1 31, 0x32, 115
layer_end
#endif
.channel4_table:
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_elevator1
sound_ref .sound_env_droning1
sound_ref .sound_env_droning1
sound_ref .sound_env_wind1
sound_ref .sound_env_moving_sand_snow
sound_ref .chan_1BE5
sound_ref .sound_env_elevator2
sound_ref .sound_env_water
sound_ref .chan_1C46
sound_ref .sound_env_boat_rocking1
sound_ref .sound_env_elevator3
sound_ref .sound_env_elevator4
sound_ref .sound_env_movingsand
sound_ref .sound_env_merry_go_round_creaking
sound_ref .sound_env_wind2
sound_ref .sound_air_rough_slide
sound_ref .chan_1D42
sound_ref .sound_env_sliding
sound_ref .sound_env_star
sound_ref .chan_1D81
sound_ref .sound_env_water_drain
sound_ref .sound_env_metal_box_push
sound_ref .sound_env_sink_quicksand
sound_ref .sound_air_peach_twinkle
sound_ref .sound_env_elevator1
sound_ref .sound_env_droning1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_menu_enter_hole
sound_ref .sound_general_elevator_move
sound_ref .sound_env_elevator1
sound_ref .sound_env_droning1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
sound_ref .sound_env_waterfall1
.sound_env_waterfall1:
chan_setbank 5
chan_setinstr 1
chan_setval 25
chan_call .set_reverb
#ifdef VERSION_JP
chan_setenvelope .envelope_32E4
#else
chan_setenvelope .envelope_32C4
#endif
chan_setlayer 0, .layer_1B53
chan_end
.layer_1B53:
layer_somethingon
#ifdef VERSION_JP
layer_delay 0x6
#else
layer_delay 0x4
#endif
.layer_1B56:
layer_note1 41, 0x12c, 95
layer_jump .layer_1B56
.sound_env_elevator1:
chan_setbank 5
chan_setinstr 2
chan_setlayer 0, .layer_1B65
chan_end
.layer_1B65:
layer_somethingon
.layer_1B66:
layer_note1 39, 0x12c, 90
layer_jump .layer_1B66
.sound_env_droning1:
chan_setbank 5
chan_setinstr 3
chan_setlayer 0, .layer_1B75
chan_end
.layer_1B75:
layer_somethingon
.layer_1B76:
layer_note1 44, 0x12c, 105
layer_jump .layer_1B76
.sound_env_wind1:
chan_setbank 5
chan_setinstr 6
chan_setdecayrelease 13
chan_setlayer 0, .layer_1B8A
chan_setlayer 1, .layer_1B8C
chan_end
.layer_1B8A:
layer_transpose -12
.layer_1B8C:
layer_somethingon
layer_portamento 0x85, 39, 255
.layer_1B91:
layer_note1 44, 0x18, 110
layer_note1 38, 0x3c, 110
layer_note1 47, 0xa, 110
layer_note1 49, 0x32, 110
layer_note1 40, 0x4b, 110
layer_note1 37, 0x14, 110
layer_note1 46, 0xc, 110
layer_note1 48, 0x1f, 110
layer_note1 55, 0x18, 110
layer_note1 46, 0x40, 110
layer_note1 36, 0xc, 110
layer_note1 39, 0xa, 110
layer_note1 36, 0xe, 110
layer_note1 39, 0xc, 110
layer_note1 32, 0x54, 110
layer_note1 39, 0xa, 110
layer_note1 36, 0x2b, 110
layer_note1 41, 0x60, 110
layer_note1 39, 0x22, 110
layer_jump .layer_1B91
.sound_env_moving_sand_snow:
chan_setbank 3
chan_setinstr 2
chan_setlayer 0, .layer_1BD5
chan_end
.layer_1BD5:
layer_somethingon
layer_portamento 0x85, 36, 255
.layer_1BDA:
layer_note1 34, 0x12c, 95
layer_note1 36, 0x12c, 95
layer_jump .layer_1BDA
.chan_1BE5:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_1BED
chan_end
.layer_1BED:
layer_somethingon
layer_note1 43, 0xc, 127
layer_portamento 0x81, 44, 255
layer_note1 43, 0x50, 127
.layer_1BF8:
layer_note1 43, 0x12c, 127
layer_jump .layer_1BF8
.sound_env_elevator2:
chan_setbank 5
chan_setinstr 2
chan_setlayer 0, .layer_1C07
chan_end
.layer_1C07:
layer_somethingon
.layer_1C08:
layer_note1 27, 0x12c, 100
layer_jump .layer_1C08
.sound_env_water:
chan_setbank 4
chan_setinstr 5
chan_setenvelope .envelope_32E4
chan_setdecayrelease 25
chan_setlayer 0, .layer_1C1C
chan_end
.layer_1C1C:
layer_transpose 6
layer_portamento 0x85, 39, 255
.layer_1C22:
layer_note1 39, 0x18, 127
layer_note1 31, 0x36, 127
layer_note1 43, 0xc, 127
layer_note1 36, 0x32, 127
layer_note1 27, 0x50, 127
layer_note1 36, 0x37, 127
layer_note1 34, 0x40, 127
layer_note1 32, 0x3d, 127
layer_note1 29, 0x4a, 127
layer_note1 32, 0x31, 127
layer_note1 38, 0x1f, 127
layer_jump .layer_1C22
.chan_1C46:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_1C4E
chan_end
.layer_1C4E:
layer_somethingon
layer_portamento 0x85, 39, 255
layer_note1 42, 0x3c, 127
.layer_1C56:
layer_note1 41, 0x3c, 127
layer_note1 42, 0x3c, 127
layer_jump .layer_1C56
.sound_env_boat_rocking1:
chan_setbank 4
chan_setinstr 2
chan_setdecayrelease 30
chan_setlayer 0, .layer_1C69
chan_end
.layer_1C69:
layer_portamento 0x81, 15, 255
#ifdef VERSION_JP
layer_note1 11, 0x1f4, 100
#else
layer_note1 11, 0x1f4, 127
#endif
layer_end
.sound_env_elevator3:
chan_setbank 5
chan_setinstr 5
chan_setenvelope .envelope_3368
chan_setval 45
chan_call .set_reverb
chan_setlayer 0, .layer_1C82
chan_end
.layer_1C82:
layer_call .layer_fn_1CA3
layer_delay 0xb
layer_call .layer_fn_1CA3
layer_delay 0x9
layer_call .layer_fn_1CA3
layer_delay 0x8
layer_call .layer_fn_1CA3
layer_delay 0x6
layer_call .layer_fn_1CA3
layer_delay 0x5
.layer_1C9B:
layer_call .layer_fn_1CA3
layer_delay 0x3
layer_jump .layer_1C9B
.layer_fn_1CA3:
layer_transpose 0
layer_setinstr 4
layer_note1 22, 0x6, 127
layer_transpose 36
layer_setinstr 5
layer_somethingon
layer_portamento 0x85, 51, 255
layer_note1 41, 0x5, 77
layer_delay 0x4
layer_disableportamento
layer_somethingoff
layer_end
.sound_env_elevator4:
chan_setbank 4
chan_setinstr 2
chan_setlayer 0, .layer_1CC3
chan_end
.layer_1CC3:
layer_portamento 0x81, 19, 10
layer_note1 8, 0x9, 127
layer_jump .layer_1CC3
.sound_env_movingsand:
chan_setbank 3
chan_setinstr 7
chan_setdecayrelease 5
chan_setlayer 0, .layer_1CE2
chan_setlayer 1, .layer_1CDA
chan_end
.layer_1CDA:
layer_somethingon
.layer_1CDB:
layer_note1 47, 0x1f4, 90
layer_jump .layer_1CDB
.layer_1CE2:
layer_somethingon
.layer_1CE3:
layer_note1 46, 0x1f4, 90
layer_jump .layer_1CE3
.sound_env_merry_go_round_creaking:
chan_setbank 4
chan_setinstr 2
chan_setdecayrelease 30
chan_setlayer 0, .layer_1CF9
chan_setlayer 1, .layer_1CF7
chan_end
.layer_1CF7:
layer_transpose 6
.layer_1CF9:
layer_portamento 0x85, 7, 255
layer_note1_long 13, 0x46, 120
layer_jump .layer_1CF9
.sound_env_wind2:
chan_setbank 5
chan_setinstr 6
chan_setdecayrelease 13
chan_setlayer 0, .layer_1D11
chan_setlayer 1, .layer_1D13
chan_end
.layer_1D11:
layer_transpose -6
.layer_1D13:
layer_somethingon
layer_portamento 0x85, 34, 255
.layer_1D18:
layer_note1 51, 0x18, 110
layer_note1 43, 0x63, 110
layer_note1 47, 0xa, 110
layer_note1 49, 0x32, 110
layer_note1 41, 0x4b, 110
layer_note1 46, 0xc, 110
layer_note1 48, 0x1f, 110
layer_note1 55, 0x7f, 110
layer_note1 46, 0x63, 110
layer_note1 43, 0xa, 110
layer_note1 39, 0xc, 110
layer_note1 41, 0x60, 110
layer_note1 39, 0x22, 110
layer_jump .layer_1D18
.chan_1D42:
chan_setbank 4
chan_setinstr 2
chan_setbank 6
chan_setenvelope .envelope_3314
chan_setdecayrelease 200
chan_setlayer 0, .layer_1D51
chan_end
.layer_1D51:
layer_transpose 3
.layer_1D53:
layer_note0 62, 0x2, 127, 127
layer_jump .layer_1D53
.sound_env_sliding:
chan_setbank 3
chan_setinstr 1
chan_setenvelope .envelope_32E4
chan_setdecayrelease 15
chan_setlayer 0, .layer_1D67
chan_end
.layer_1D67:
layer_somethingon
.layer_1D68:
layer_note1 44, 0x12c, 95
layer_jump .layer_1D68
.sound_env_star:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1D77
chan_end
.layer_1D77:
layer_portamento 0x81, 38, 127
layer_note1 39, 0x9, 127
layer_jump .layer_1D77
.chan_1D81:
chan_setval 50
chan_call .set_reverb
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_1DA5
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 15
chan_setlayer 1, .layer_1DAD
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 15
chan_setdecayrelease 10
chan_end
.layer_1DA5:
layer_note1 21, 0xc, 127
layer_note1 18, 0x226, 127
layer_end
.layer_1DAD:
layer_transpose 24
layer_portamento 0x82, 19, 255
layer_note1 20, 0x1f4, 127
layer_end
.sound_env_water_drain:
chan_setbank 3
chan_setinstr 2
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_1DD4
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 5
chan_setdecayrelease 20
chan_setlayer 1, .layer_1DE4
chan_setlayer 2, .layer_1DE2
chan_end
.layer_1DD4:
layer_transpose -12
layer_somethingon
layer_portamento 0x82, 39, 255
.layer_1DDB:
layer_note1 46, 0x2710, 80
layer_jump .layer_1DDB
.layer_1DE2:
layer_transpose 6
.layer_1DE4:
layer_portamento 0x83, 20, 255
layer_note1 15, 0x5a, 127
layer_note1 32, 0x2d, 127
layer_note1 29, 0x46, 127
layer_note1 24, 0x78, 127
layer_note1 32, 0x44, 127
layer_note1 24, 0x74, 127
layer_transpose 7
layer_jump .layer_1DE4
.sound_env_metal_box_push:
chan_setbank 6
chan_setinstr 1
chan_setlayer 0, .layer_1E0C
chan_setlayer 1, .layer_1E12
chan_setdecayrelease 127
chan_end
.layer_1E0C:
layer_note1 24, 0xc, 85
layer_jump .layer_1E0C
.layer_1E12:
layer_setinstr 15
.layer_1E14:
layer_note1 39, 0x10, 115
layer_jump .layer_1E14
.sound_env_sink_quicksand:
chan_setbank 3
chan_setinstr 6
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_1E28
chan_setlayer 1, .layer_1E28
chan_end
.layer_1E28:
layer_portamento 0x81, 38, 80
layer_somethingon
.layer_1E2D:
layer_note1 35, 0x12c, 100
layer_jump .layer_1E2D
layer_end
.sound_air_peach_twinkle:
chan_setbank 5
chan_setinstr 15
chan_setenvelope .envelope_32E4
chan_setdecayrelease 8
chan_setlayer 0, .layer_1E42
chan_end
.layer_1E42:
layer_somethingon
layer_portamento 0x82, 20, 255
.layer_1E47:
layer_note1 43, 0x1b58, 63
layer_jump .layer_1E47
.channel59_table:
sound_ref .sound_obj_sushi_shark_water_sound
sound_ref .sound_obj_mri_shoot
sound_ref .sound_obj_baby_penguin_walk
sound_ref .sound_obj_bowser_walk
sound_ref .sound_obj_bowser_roar
sound_ref .sound_obj_bowser_tail_pickup
sound_ref .sound_obj_bowser_defeated
sound_ref .sound_obj_bowser_spinning
sound_ref .sound_obj_bowser_inhaling
sound_ref .sound_obj_big_penguin_walk
sound_ref .sound_obj_boo_bounce_top
sound_ref .sound_obj_boo_laugh_short
sound_ref .sound_obj_thwomp
sound_ref .sound_obj_cannon1
sound_ref .sound_obj_cannon2
sound_ref .sound_obj_cannon3
sound_ref .sound_obj_piranha_plant_bite
sound_ref .sound_obj_piranha_plant_dying
sound_ref .sound_obj_jump_walk_water
sound_ref .chan_20B2
sound_ref .sound_obj_mri_death
sound_ref .sound_obj_pounding1
sound_ref .sound_obj_king_bobomb
sound_ref .sound_obj_bully_metal
sound_ref .sound_obj_bully_explode
sound_ref .sound_obj_bowser_puzzle_piece_move
sound_ref .sound_obj_pounding_cannon
sound_ref .sound_obj_bully_walk
sound_ref .sound_obj_bully_attacked
sound_ref .chan_2177
sound_ref .chan_218E
sound_ref .sound_obj_baby_penguin_dive
sound_ref .sound_obj_goomba_walk
sound_ref .sound_obj_ukiki_chatter_long
sound_ref .sound_obj_monty_mole_lakitu_attack
sound_ref .chan_21FF
sound_ref .sound_obj_dying_enemy1
sound_ref .sound_obj_cannon4
sound_ref .sound_obj_dying_enemy2
sound_ref .sound_obj_bobomb_walk
sound_ref .sound_obj_something_landing
sound_ref .sound_obj_diving_in_water
sound_ref .sound_obj_snow_sand1
sound_ref .sound_obj_snow_sand2
sound_ref .sound_obj_default_death
sound_ref .sound_obj_big_penguin_yell
sound_ref .sound_obj_water_bomb_bouncing
sound_ref .sound_obj_goomba_alert
sound_ref .sound_obj_stomped
sound_ref .chan_233D
sound_ref .sound_obj_diving_into_water
sound_ref .sound_obj_piranha_plant_shrink
sound_ref .sound_obj_koopa_the_quick_walk
sound_ref .sound_obj_koopa_walk
sound_ref .sound_obj_bully_walking
sound_ref .sound_obj_dorrie
sound_ref .sound_obj_bowser_laugh
sound_ref .sound_obj_ukiki_chatter_short
sound_ref .sound_obj_ukiki_chatter_idle
sound_ref .sound_obj_ukiki_step_default
sound_ref .sound_obj_ukiki_step_leaves
sound_ref .sound_obj_koopa_talk
sound_ref .sound_obj_koopa_damage
sound_ref .sound_obj_klepto1
sound_ref .sound_obj_klepto2
sound_ref .sound_obj_king_bobomb_talk
sound_ref .sound_obj_king_bobomb_damage
sound_ref .sound_obj_scuttlebug_walk
sound_ref .sound_obj_scuttlebug_alert
sound_ref .sound_obj_baby_penguin_yell
sound_ref .sound_obj_king_bobomb_jump
sound_ref .sound_obj_king_whomp_death
sound_ref .sound_obj_boo_laugh_long
sound_ref .sound_obj_swoop
sound_ref .sound_obj_eel
sound_ref .sound_obj_eyerok_show_eye
sound_ref .sound_obj_mr_blizzard_alert
sound_ref .sound_obj_snufit_shoot
sound_ref .sound_obj_skeeter_walk
sound_ref .sound_obj_walking_water
sound_ref .sound_general_bird_chirp2
sound_ref .sound_obj_bird_chirp3
sound_ref .sound_obj_bird_chirp1
sound_ref .sound_air_castle_outdoors_ambient
sound_ref .sound_obj_piranha_plant_appear
sound_ref .sound_obj_flame_blown
sound_ref .sound_obj_mad_piano_chomping
sound_ref .sound_obj_large_bully_attacked
sound_ref .sound_obj_bobomb_buddy_talk
sound_ref .chan_26A9
sound_ref .sound_obj_eyerok_sound_short
sound_ref .sound_obj_eyerok_sound_long
sound_ref .sound_obj_wiggler_high_pitch
sound_ref .sound_obj_heaveho_tossed
sound_ref .sound_obj_wiggler_death
sound_ref .sound_obj_bowser_intro_laugh
sound_ref .sound_obj_enemy_death_high
sound_ref .sound_obj_enemy_death_low
sound_ref .sound_obj_swoop_death
sound_ref .sound_obj_koopa_flyguy_pokey_death
sound_ref .sound_obj_snowman_bounce
sound_ref .sound_obj_snowman_explode
sound_ref .sound_obj_bowser_teleport
sound_ref .sound_obj_monty_mole_appear
sound_ref .sound_obj_pounding_loud
sound_ref .sound_obj_boss_dialog_grunt
sound_ref .sound_obj_mips_rabbit
sound_ref .sound_obj_mri_spinning
sound_ref .sound_obj_mips_rabbit_water
sound_ref .sound_obj_eyerok_explode
sound_ref .sound_obj_chuckya_death
sound_ref .sound_obj_wiggler_talk
sound_ref .sound_obj_wiggler_attacked
sound_ref .sound_obj_wiggler_low_pitch
sound_ref .sound_obj_snufit_skeeter_death
sound_ref .sound_obj_bubba_chomp
sound_ref .sound_obj_enemy_defeat_shrink
sound_ref .sound_obj_bowser_tail_pickup
sound_ref .sound_obj_bowser_defeated
sound_ref .sound_obj_bowser_spinning
sound_ref .sound_obj_klepto2
sound_ref .sound_obj_king_bobomb_talk
sound_ref .sound_obj_baby_penguin_walk
sound_ref .sound_obj_bowser_walk
sound_ref .sound_obj_bowser_roar
sound_ref .sound_obj_bowser_tail_pickup
sound_ref .sound_obj_bowser_defeated
sound_ref .sound_obj_bowser_spinning
.sound_general_swish_water:
chan_setbank 6
chan_setinstr 5
chan_setlayer 0, .layer_1F56
chan_end
.layer_1F56:
layer_note1 27, 0x8, 90
layer_portamento 0x81, 43, 255
layer_note1 27, 0x21, 90
layer_end
.sound_obj_mri_shoot:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_1F72
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 0
chan_end
.layer_1F72:
layer_note1 43, 0xf, 90
layer_portamento 0x82, 27, 255
layer_note1 36, 0xb, 90
layer_end
.sound_obj_baby_penguin_walk:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_1F85
chan_end
.layer_1F85:
layer_portamento 0x81, 43, 255
layer_note1 48, 0x30, 110
layer_end
.sound_obj_bowser_walk:
chan_setbank 6
chan_setinstr 1
chan_setval 60
chan_call .set_reverb
chan_setlayer 0, .layer_1F9D
chan_setlayer 1, .layer_1FA6
chan_end
.layer_1F9D:
layer_note1 36, 0x8, 120
layer_note1 35, 0x28, 120
layer_delay 0x30
layer_end
.layer_1FA6:
layer_delay 0x18
layer_note1 0, 0x1e, 95
layer_end
.sound_obj_bowser_roar:
chan_setbank 6
chan_setinstr 2
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_1FC0
chan_setlayer 1, .layer_1FBC
chan_end
.layer_1FBC:
layer_delay 0x3
layer_transpose 5
.layer_1FC0:
layer_note1 39, 0x7f, 127
layer_end
.sound_obj_bowser_tail_pickup:
chan_setbank 6
chan_setinstr 2
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_1FD8
chan_setlayer 1, .layer_1FD4
chan_end
.layer_1FD4:
layer_delay 0x3
layer_transpose 5
.layer_1FD8:
layer_portamento 0x81, 45, 255
layer_note1 33, 0x30, 127
layer_end
.sound_obj_bowser_defeated:
chan_setbank 6
chan_setinstr 4
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_1FED
chan_end
.layer_1FED:
layer_note1 32, 0x104, 127
layer_end
.sound_obj_bowser_spinning:
chan_setbank 6
chan_setinstr 5
chan_setlayer 0, .layer_1FFA
chan_end
.layer_1FFA:
layer_note1 32, 0x28, 127
layer_end
.sound_obj_bowser_inhaling:
chan_setbank 6
chan_setinstr 6
chan_setlayer 0, .layer_2006
chan_end
.layer_2006:
layer_note1 36, 0x5a, 127
layer_end
.sound_obj_big_penguin_walk:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_2012
chan_end
.layer_2012:
layer_portamento 0x81, 39, 255
layer_note1 36, 0x26, 100
layer_end
.sound_obj_boo_bounce_top:
chan_setbank 6
chan_setinstr 8
chan_setlayer 0, .layer_2022
chan_end
.layer_2022:
layer_note1 39, 0x18, 127
layer_end
.sound_obj_boo_laugh_short:
chan_setbank 6
chan_setinstr 9
chan_setlayer 0, .layer_202E
chan_end
.layer_202E:
layer_note1 50, 0xa, 127
layer_note1 55, 0xa, 127
layer_end
.sound_obj_thwomp:
chan_setbank 7
chan_setinstr 12
chan_setval 55
chan_call .set_reverb
chan_setlayer 0, .layer_2055
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 1
chan_setlayer 1, .layer_204E
chan_end
.layer_204E:
layer_note1 37, 0xc, 127
layer_note1 31, 0x1e, 127
layer_end
.layer_2055:
layer_note1 31, 0x2a, 127
layer_end
.sound_obj_cannon1:
chan_setbank 6
chan_setinstr 10
chan_setlayer 0, .layer_2061
chan_end
.layer_2061:
layer_note1 39, 0xd2, 127
layer_end
.sound_obj_cannon2:
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_206E
chan_end
.layer_206E:
layer_note1 39, 0xd2, 127
layer_end
.sound_obj_cannon3:
chan_setbank 6
chan_setinstr 12
chan_setlayer 0, .layer_207B
chan_end
.layer_207B:
layer_note1 39, 0x24, 127
layer_end
.sound_obj_piranha_plant_bite:
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_2087
chan_end
.layer_2087:
layer_portamento 0x81, 33, 255
layer_note1 57, 0x4, 127
layer_transpose -4
layer_portamento 0x81, 57, 255
layer_note1 33, 0x6, 127
layer_delay 0x14
layer_end
.sound_obj_piranha_plant_dying:
chan_setbank 6
chan_setinstr 14
chan_setlayer 0, .layer_20A2
chan_end
.layer_20A2:
layer_note1 39, 0x48, 110
layer_end
.sound_obj_jump_walk_water:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_20AE
chan_end
.layer_20AE:
layer_note1 59, 0x24, 105
layer_end
.chan_20B2:
chan_setbank 6
chan_setinstr 15
chan_setlayer 0, .layer_20BA
chan_end
.layer_20BA:
layer_note1 39, 0x4c, 127
layer_end
.sound_obj_mri_death:
chan_setbank 7
chan_setinstr 0
chan_setlayer 0, .layer_20C6
chan_end
.layer_20C6:
layer_note1 39, 0x18, 105
layer_end
.sound_obj_pounding1:
chan_setbank 6
chan_setinstr 1
chan_setlayer 0, .layer_20D2
chan_end
.layer_20D2:
layer_portamento 0x81, 44, 255
#ifdef VERSION_JP
layer_note1 36, 0x18, 90
#else
layer_note1 36, 0x18, 115
#endif
layer_delay 0x32
layer_end
.sound_obj_king_bobomb:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_20F0
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 1
chan_setlayer 1, .layer_20F4
chan_end
.layer_20F0:
layer_note1 31, 0x26, 127
layer_end
.layer_20F4:
#ifdef VERSION_JP
layer_note1 38, 0x8, 120
layer_note1 33, 0x1e, 120
#else
layer_note1 38, 0x8, 127
layer_note1 33, 0x1e, 127
#endif
layer_end
.sound_obj_bully_metal:
chan_setbank 7
chan_setinstr 1
chan_setlayer 0, .layer_2103
chan_end
.layer_2103:
layer_note1 39, 0x24, 120
layer_end
.sound_obj_bully_explode:
chan_setbank 4
chan_setinstr 15
chan_setenvelope .envelope_33EC
chan_setlayer 0, .layer_211C
chan_setlayer 1, .layer_2126
chan_setlayer 2, .layer_2124
chan_setval 1
chan_setdecayrelease 10
chan_end
.layer_211C:
layer_portamento 0x81, 51, 255
layer_note1 20, 0x2e, 115
layer_end
.layer_2124:
layer_transpose 3
.layer_2126:
layer_setinstr 5
layer_delay 0xa
layer_note1 48, 0x23, 127
layer_end
.sound_obj_bowser_puzzle_piece_move:
chan_setbank 7
chan_setinstr 2
chan_setlayer 0, .layer_2136
chan_end
.layer_2136:
layer_note1 39, 0xc, 105
layer_end
.sound_obj_pounding_cannon:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_2142
chan_end
.layer_2142:
layer_note1 39, 0x68, 127
layer_end
.sound_obj_bully_walk:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_214E
chan_end
.layer_214E:
layer_portamento 0x82, 38, 127
layer_note1 51, 0x4, 80
layer_delay 0x1e
layer_end
.sound_obj_bully_attacked:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_2160
chan_end
.layer_2160:
layer_portamento 0x83, 33, 255
layer_note0 40, 0xf, 127, 127
layer_note1 26, 0x20, 127
layer_end
.layer_unused_216C:
layer_portamento 0x83, 27, 255
layer_note1 22, 0x9, 127
layer_note1 24, 0x1c, 127
layer_end
.chan_2177:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_217F
chan_end
.layer_217F:
layer_portamento 0x81, 27, 255
layer_note1 48, 0x9, 100
layer_portamento 0x81, 27, 255
layer_note1 48, 0x5, 100
layer_end
.chan_218E:
chan_setbank 6
chan_setinstr 5
chan_setlayer 0, .layer_2196
chan_end
.layer_2196:
layer_note1 36, 0x8, 90
layer_portamento 0x81, 43, 255
layer_note1 27, 0x14, 90
layer_end
.sound_obj_baby_penguin_dive:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_21A9
chan_end
.layer_21A9:
layer_portamento 0x81, 39, 255
layer_note1 44, 0xc, 110
layer_portamento 0x81, 46, 255
layer_note1 58, 0x30, 110
layer_end
.sound_obj_goomba_walk:
chan_setbank 6
chan_setinstr 12
chan_setlayer 0, .layer_21C9
chan_setval 1
chan_call .delay
chan_setbank 0
chan_setinstr 4
chan_end
.layer_21C9:
layer_portamento 0x82, 24, 255
layer_note1 12, 0x4, 100
layer_note1 51, 0x8, 80
layer_delay 0x1e
layer_end
.sound_obj_ukiki_chatter_long:
chan_setbank 7
chan_setinstr 7
chan_setdecayrelease 15
chan_setlayer 0, .layer_21E0
chan_end
.layer_21E0:
layer_note1 39, 0x30, 127
layer_end
.sound_obj_monty_mole_lakitu_attack:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setval 10
chan_call .set_reverb
chan_setlayer 0, .layer_21F4
chan_end
.layer_21F4:
layer_portamento 0x85, 48, 255
layer_note1 60, 0x7, 115
layer_note1 39, 0x23, 115
layer_end
.chan_21FF:
chan_setbank 4
chan_setinstr 13
chan_setlayer 0, .layer_2207
chan_end
.layer_2207:
layer_portamento 0x81, 27, 255
layer_note1 3, 0x14, 115
layer_delay 0x1e
layer_end
.sound_obj_dying_enemy1:
chan_setbank 7
chan_setinstr 0
chan_setlayer 0, .layer_2219
chan_end
.layer_2219:
layer_note1 43, 0x6, 105
layer_portamento 0x81, 32, 255
layer_note1 44, 0x18, 105
layer_end
.sound_obj_cannon4:
chan_setbank 7
chan_setinstr 3
chan_setval 15
chan_call .set_reverb
chan_setlayer 0, .layer_2231
chan_end
.layer_2231:
layer_note1 48, 0x55, 127
layer_end
.sound_obj_dying_enemy2:
chan_setbank 7
chan_setinstr 8
chan_setlayer 0, .layer_223D
chan_end
.layer_223D:
layer_note1 44, 0xc, 100
layer_portamento 0x81, 44, 255
layer_note1 32, 0x18, 105
layer_end
.sound_obj_bobomb_walk:
chan_setbank 9
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_2253
chan_end
.layer_2253:
layer_portamento 0x83, 46, 255
layer_note1 27, 0x5, 127
layer_note1 32, 0x3, 127
layer_delay 0x22
layer_end
.sound_obj_something_landing:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_226B
chan_end
.layer_226B:
layer_somethingon
layer_portamento 0x85, 62, 255
layer_note1 50, 0x24, 93
layer_note1 26, 0x3c, 93
layer_end
.sound_obj_diving_in_water:
chan_setbank 4
chan_setinstr 5
chan_setlayer 0, .layer_2288
chan_setval 1
chan_call .delay
chan_setbank 2
chan_setinstr 0
chan_end
.layer_2288:
layer_note1 62, 0x4, 105
layer_portamento 0x81, 43, 200
layer_note1 36, 0x4e, 127
layer_end
.sound_obj_snow_sand1:
chan_setbank 3
chan_setinstr 5
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_229E
chan_end
.layer_229E:
layer_note1 41, 0x6, 100
layer_note1 24, 0x1c, 100
layer_end
.sound_obj_snow_sand2:
chan_setbank 3
chan_setinstr 5
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_22B0
chan_end
.layer_22B0:
layer_note1 36, 0x5, 100
layer_note1 44, 0x18, 100
layer_end
.sound_obj_default_death:
chan_setbank 0
chan_setinstr 4
chan_setenvelope .envelope_32D4
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_22C7
chan_end
.layer_22C7:
layer_somethingon
layer_portamento 0x81, 39, 255
layer_note1 62, 0x1b, 107
layer_delay 0x12
layer_end
.sound_obj_big_penguin_yell:
chan_setbank 7
chan_setinstr 10
chan_setlayer 0, .layer_22DA
chan_end
.layer_22DA:
layer_somethingon
layer_portamento 0x85, 41, 255
layer_note1 45, 0x28, 127
layer_note1 41, 0xf, 127
layer_end
.sound_obj_water_bomb_bouncing:
chan_setbank 7
chan_setinstr 11
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_22F3
chan_end
.layer_unused_22F1:
layer_transpose -12
.layer_22F3:
layer_somethingon
layer_portamento 0x85, 39, 255
layer_note1 32, 0xc, 127
layer_note1 39, 0x60, 127
layer_end
.sound_obj_goomba_alert:
chan_setbank 9
chan_setinstr 3
chan_setval 20
chan_call .set_reverb
chan_setenvelope .envelope_33EC
chan_setlayer 0, .layer_230F
chan_end
.layer_230F:
layer_transpose -24
layer_somethingon
layer_portamento 0x85, 25, 255
layer_note1 3, 0xf, 85
layer_transpose 0
layer_note1 51, 0x1c, 85
layer_delay 0x19
layer_end
.sound_obj_stomped:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_232C
chan_end
.layer_232C:
layer_transpose -3
layer_somethingon
layer_portamento 0x85, 24, 255
layer_note1 17, 0xa, 100
layer_note1 32, 0xa, 100
layer_note1 27, 0x6, 100
layer_end
.chan_233D:
chan_setbank 6
chan_setinstr 5
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_2348
chan_end
.layer_2348:
layer_transpose 10
layer_call .layer_fn_2353
layer_call .layer_fn_2353
layer_delay 0x14
layer_end
.layer_fn_2353:
layer_portamento 0x85, 52, 255
layer_note1 48, 0x4, 115
layer_note1 52, 0x2, 115
layer_delay 0x2
layer_disableportamento
layer_end
.sound_obj_diving_into_water:
chan_setbank 2
chan_setlayer 0, .layer_236A
chan_setlayer 1, .layer_2374
chan_end
.layer_236A:
layer_setinstr 0
layer_portamento 0x82, 44, 255
layer_note1 43, 0x54, 100
layer_end
.layer_2374:
layer_setinstr 1
layer_portamento 0x82, 32, 255
layer_note1 31, 0x54, 100
layer_end
.sound_obj_piranha_plant_shrink:
chan_setbank 3
chan_setinstr 0
chan_setenvelope .envelope_3324
chan_setlayer 0, .layer_2389
chan_end
.layer_2389:
layer_portamento 0x81, 62, 255
layer_note1 38, 0x7f, 117
layer_end
.sound_obj_koopa_the_quick_walk:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_2399
chan_end
.layer_2399:
layer_note1 27, 0x6, 100
layer_note1 29, 0x3, 70
layer_delay 0x1e
layer_end
.sound_obj_koopa_walk:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_23AA
chan_end
.layer_23AA:
layer_note1 20, 0x4, 100
layer_delay 0x1e
layer_end
.sound_obj_bully_walking:
chan_setbank 7
chan_setinstr 3
chan_setlayer 0, .layer_23B8
chan_end
.layer_23B8:
layer_portamento 0x82, 29, 255
layer_note1 46, 0xc, 80
layer_end
.sound_obj_dorrie:
chan_setbank 6
chan_setinstr 4
chan_setenvelope .envelope_32F4
chan_setlayer 0, .layer_23CD
chan_end
.layer_unused_23CB:
layer_transpose 12
.layer_23CD:
layer_somethingon
layer_portamento 0x85, 36, 255
layer_note1 48, 0x8, 100
layer_note1 45, 0x4, 100
layer_note1 48, 0xa, 100
layer_note1 41, 0x48, 100
layer_end
.sound_obj_bowser_laugh:
chan_setbank 6
chan_setinstr 9
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_23EF
chan_setlayer 1, .layer_23EF
chan_end
.layer_23EF:
layer_portamento 0x81, 20, 255
layer_note1 26, 0x12c, 127
layer_end
.sound_obj_ukiki_chatter_short:
chan_setbank 7
chan_setinstr 7
chan_setlayer 0, .layer_2400
chan_end
.layer_2400:
layer_portamento 0x81, 32, 221
layer_note1 34, 0xa, 115
layer_end
.sound_obj_ukiki_chatter_idle:
chan_setbank 7
chan_setinstr 7
chan_setlayer 0, .layer_2410
chan_end
.layer_2410:
layer_portamento 0x81, 34, 221
layer_note1 38, 0xc, 127
layer_portamento 0x82, 34, 221
layer_note1 39, 0x12, 127
layer_end
.sound_obj_ukiki_step_default:
chan_setbank 1
chan_setinstr 1
chan_setlayer 0, .layer_2427
chan_end
.layer_2427:
layer_portamento 0x81, 58, 255
layer_note1 52, 0x6, 105
layer_end
.sound_obj_ukiki_step_leaves:
chan_setbank 0
chan_setinstr 1
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_243A
chan_end
.layer_243A:
layer_note1 43, 0x6, 90
layer_note1 44, 0x6, 90
layer_end
.sound_obj_koopa_talk:
chan_setbank 7
chan_setinstr 8
chan_setlayer 0, .layer_2449
chan_end
.layer_2449:
layer_transpose -8
layer_call .layer_fn_244E
.layer_fn_244E:
layer_portamento 0x85, 44, 255
layer_note1 51, 0x9, 100
layer_note1 39, 0xc, 100
layer_end
.sound_obj_koopa_damage:
chan_setbank 7
chan_setinstr 8
chan_setlayer 0, .layer_2461
chan_end
.layer_2461:
layer_transpose 10
layer_portamento 0x83, 32, 255
layer_note1 39, 0x6, 105
layer_note1 27, 0x12, 105
layer_end
.sound_obj_klepto1:
chan_setbank 7
chan_setinstr 9
chan_setlayer 0, .layer_2476
chan_end
.layer_2476:
layer_somethingon
layer_portamento 0x83, 39, 255
layer_note1 41, 0x6, 127
layer_note1 37, 0x24, 127
layer_end
.sound_obj_klepto2:
chan_setbank 7
chan_setinstr 9
chan_setlayer 0, .layer_248A
chan_end
.layer_248A:
layer_portamento 0x81, 48, 255
layer_note1 40, 0x24, 127
layer_end
.sound_obj_king_bobomb_talk:
chan_setbank 7
chan_setinstr 9
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_249F
chan_end
.layer_249F:
layer_transpose -5
layer_call .layer_fn_24AF
layer_delay 0xb
layer_transpose -8
layer_call .layer_fn_24AF
layer_delay 0xa
layer_transpose -10
.layer_fn_24AF:
layer_portamento 0x85, 29, 255
layer_note1 24, 0x2, 127
layer_note1 41, 0x10, 127
layer_end
.sound_obj_king_bobomb_damage:
chan_setbank 7
chan_setinstr 9
chan_setval 20
chan_call .set_reverb
chan_setlayer 0, .layer_24C7
chan_end
.layer_24C7:
layer_transpose -12
layer_portamento 0x85, 25, 255
layer_note1 39, 0x4, 127
layer_note1 29, 0x30, 127
layer_end
.sound_obj_scuttlebug_walk:
chan_setbank 7
chan_setinstr 2
chan_setlayer 0, .layer_24DC
chan_end
.layer_24DC:
layer_note1 44, 0x4, 127
layer_delay 0x14
layer_end
.sound_obj_scuttlebug_alert:
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_24EA
chan_end
.layer_24EA:
layer_portamento 0x81, 24, 255
layer_note1 53, 0x12, 80
layer_end
.sound_obj_baby_penguin_yell:
chan_setbank 7
chan_setinstr 10
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_24FD
chan_end
.layer_24FD:
layer_note1 50, 0x8, 105
layer_portamento 0x82, 46, 255
layer_note1 50, 0x30, 105
layer_end
.sound_obj_king_bobomb_jump:
chan_setbank 6
chan_setinstr 1
chan_setlayer 0, .layer_2510
chan_end
.layer_2510:
layer_portamento 0x81, 27, 255
layer_note1 43, 0x1e, 127
layer_end
.sound_obj_king_whomp_death:
chan_setbank 5
chan_setinstr 7
chan_setlayer 0, .layer_252C
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 12
chan_setlayer 1, .layer_26D7
chan_end
.layer_252C:
layer_note1 34, 0xaf, 127
layer_end
.sound_obj_boo_laugh_long:
chan_setbank 6
chan_setinstr 9
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_253E
chan_end
.layer_253E:
layer_note1 55, 0x32, 127
layer_end
.sound_obj_swoop:
chan_setbank 7
chan_setinstr 7
chan_setlayer 0, .layer_254A
chan_end
.layer_254A:
layer_portamento 0x82, 51, 127
layer_note1 48, 0x6, 127
layer_end
.sound_obj_eel:
chan_setbank 6
chan_setinstr 2
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_2564
chan_setlayer 1, .layer_2562
chan_end
.layer_2562:
layer_delay 0x4
.layer_2564:
layer_somethingon
layer_portamento 0x85, 31, 255
layer_note1 34, 0x18, 127
layer_note1 17, 0x48, 127
layer_end
.sound_obj_eyerok_show_eye:
chan_setbank 4
chan_setinstr 15
chan_setlayer 0, .layer_257D
chan_setlayer 1, .layer_257B
chan_end
.layer_257B:
layer_transpose 4
.layer_257D:
layer_jump .layer_11BB
.sound_obj_mr_blizzard_alert:
chan_setbank 9
chan_setinstr 3
chan_setval 24
chan_call .set_reverb
chan_setenvelope .envelope_3428
chan_setvibratoextent 80
chan_setvibratorate 60
chan_setlayer 0, .layer_259B
chan_setval 30
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_259B:
layer_somethingon
layer_portamento 0x85, 15, 255
layer_note1 3, 0x7, 100
layer_note1 36, 0x18, 100
layer_end
.sound_obj_snufit_shoot:
chan_setbank 6
chan_setinstr 0
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_25B2
chan_end
.layer_25B2:
layer_somethingon
layer_portamento 0x81, 44, 255
layer_note1 51, 0x8, 118
layer_end
.sound_obj_skeeter_walk:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_25CC
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 2
chan_end
.layer_25CC:
layer_portamento 0x81, 3, 255
layer_note1 39, 0x5, 127
layer_portamento 0x81, 27, 255
layer_note1 49, 0x6, 127
layer_end
.sound_obj_walking_water:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_25EC
chan_setval 1
chan_call .delay
chan_setbank 2
chan_setinstr 1
chan_end
.layer_25EC:
layer_portamento 0x81, 3, 255
layer_note1 39, 0x5, 127
layer_portamento 0x83, 36, 255
layer_note1 48, 0x6, 92
layer_note1 55, 0x30, 92
layer_end
.sound_obj_piranha_plant_appear:
chan_setbank 3
chan_setinstr 0
chan_setenvelope .envelope_3324
chan_setlayer 0, .layer_2609
chan_end
.layer_2609:
layer_portamento 0x82, 62, 255
layer_note1 38, 0x60, 117
layer_end
.sound_obj_flame_blown:
chan_setbank 7
chan_setinstr 5
chan_setenvelope .envelope_32F4
chan_setlayer 0, .layer_261C
chan_end
.layer_261C:
layer_portamento 0x85, 41, 255
layer_note1 36, 0x18, 127
layer_end
.sound_obj_mad_piano_chomping:
chan_call .sound_obj_piranha_plant_bite
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 13
chan_setlayer 1, .layer_2655
chan_setlayer 2, .layer_2659
chan_setval 11
chan_call .delay
chan_call .sound_general_elevator_move
chan_setval 20
chan_call .delay
chan_setbank 1
chan_setinstr 4
chan_setlayer 0, .layer_264B
chan_end
.layer_264B:
layer_note1 37, 0x8, 96
layer_note1 41, 0x6, 96
layer_note1 32, 0x18, 96
layer_end
.layer_2655:
layer_note1 46, 0x32, 127
layer_end
.layer_2659:
layer_note1 39, 0x32, 127
layer_end
.sound_obj_large_bully_attacked:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_2665
chan_end
.layer_2665:
layer_portamento 0x83, 27, 255
layer_note0 34, 0x12, 127, 127
layer_note1 20, 0x28, 127
layer_end
.sound_obj_bobomb_buddy_talk:
chan_setbank 8
chan_setinstr 12
chan_setvibratoextent 80
chan_setvibratorate 5
chan_setlayer 0, .layer_2684
chan_setval 88
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_2684:
layer_portamento 0x83, 44, 200
layer_note0 49, 0xc, 127, 127
layer_note0 40, 0x12, 127, 155
layer_note0 39, 0xb, 127, 127
layer_portamento 0x83, 41, 200
layer_note0 51, 0xa, 127, 127
layer_note0 48, 0x12, 127, 80
layer_note0 46, 0xa, 127, 127
layer_note0 48, 0xb, 127, 127
layer_end
.chan_26A9:
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_26B1
chan_end
.layer_26B1:
layer_portamento 0x85, 31, 255
layer_note1 8, 0x6, 100
layer_note1 32, 0xc, 100
layer_end
.sound_obj_eyerok_sound_short:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_26C7
chan_setlayer 1, .layer_26C7
chan_end
.layer_26C7:
layer_portamento 0x81, 32, 255
layer_note1 22, 0x24, 110
layer_end
.sound_obj_eyerok_sound_long:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_26D7
chan_end
.layer_26D7:
layer_portamento 0x81, 26, 255
layer_note1 19, 0x60, 127
layer_end
.sound_obj_wiggler_high_pitch:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_26E7
chan_end
.layer_26E7:
layer_transpose 3
layer_note0 31, 0x8, 127, 70
layer_note0 30, 0x9, 127, 70
layer_note0 29, 0x8, 127, 70
layer_note0 28, 0x9, 127, 70
layer_end
.sound_obj_heaveho_tossed:
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_2702
chan_end
.layer_2702:
layer_portamento 0x81, 12, 255
layer_note1 51, 0x24, 127
layer_end
.sound_obj_bowser_intro_laugh:
chan_setbank 6
chan_setinstr 9
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_271A
chan_setlayer 1, .layer_271A
chan_end
.layer_271A:
layer_delay 0xdc
.layer_271D:
layer_portamento 0x81, 20, 255
layer_note1 26, 0xc8, 110
layer_end
.sound_obj_enemy_death_high:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 8
chan_setlayer 1, .layer_223D
chan_end
.sound_obj_enemy_death_low:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 8
chan_setlayer 1, .layer_2746
chan_end
.layer_2746:
layer_note1 39, 0xe, 100
layer_portamento 0x81, 39, 255
layer_note1 27, 0x1c, 105
layer_end
.sound_obj_swoop_death:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 7
chan_setlayer 1, .layer_254A
chan_end
.sound_obj_koopa_flyguy_pokey_death:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 8
chan_setlayer 1, .layer_2461
chan_end
.sound_obj_wiggler_death:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 0
chan_setlayer 1, .layer_2219
chan_end
.sound_obj_snowman_bounce:
chan_call .sound_obj_water_bomb_bouncing
chan_setlayer 1, .layer_22F3
chan_end
.sound_obj_snowman_explode:
chan_call .sound_general_explosion7
chan_setval 12
chan_call .delay
chan_setbank 6
chan_setinstr 1
chan_setlayer 2, .layer_2798
chan_end
.layer_2798:
layer_note1 24, 0x46, 127
layer_end
.sound_obj_bowser_teleport:
chan_setbank 9
chan_setinstr 3
chan_setvibratoextent 80
chan_setvibratorate 60
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_27B7
chan_setlayer 1, .layer_27B5
chan_setval 56
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_27B5:
layer_transpose 1
.layer_27B7:
layer_note1 15, 0x48, 127
layer_end
.sound_obj_monty_mole_appear:
chan_setbank 4
chan_setinstr 15
chan_setval 40
chan_call .set_reverb
chan_setenvelope .envelope_33BC
chan_setlayer 0, .layer_27CB
chan_end
.layer_27CB:
layer_portamento 0x84, 3, 255
layer_note1 39, 0x7, 127
layer_note1 44, 0x8, 127
layer_note1 51, 0x7, 127
layer_note1 56, 0x8, 127
layer_end
.sound_obj_pounding_loud:
chan_setbank 6
chan_setinstr 1
chan_setval 55
chan_call .set_reverb
chan_setlayer 0, .layer_204E
chan_end
.sound_obj_boss_dialog_grunt:
chan_setbank 7
chan_setinstr 12
chan_setlayer 0, .layer_27F1
chan_end
.layer_27F1:
layer_note1 29, 0x7, 127
layer_note0 31, 0x18, 127, 127
layer_note1 27, 0x26, 127
layer_end
.sound_obj_mips_rabbit:
chan_setbank 6
chan_setinstr 0
chan_setlayer 0, .layer_2804
chan_end
.layer_2804:
layer_somethingon
layer_portamento 0x85, 32, 255
layer_note1 46, 0x9, 80
layer_note1 36, 0xa, 90
layer_end
.sound_obj_mri_spinning:
chan_setbank 6
chan_setinstr 11
chan_setenvelope .envelope_3304
chan_setlayer 0, .layer_281B
chan_end
.layer_281B:
layer_somethingon
layer_portamento 0x85, 19, 255
layer_note1 31, 0xe, 127
layer_note1 62, 0x8, 127
layer_end
.sound_obj_mips_rabbit_water:
chan_setbank 2
chan_setinstr 1
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_283E
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 0
chan_setlayer 1, .layer_2804
chan_end
.layer_283E:
layer_portamento 0x81, 47, 255
layer_note1 50, 0x18, 115
layer_end
.sound_obj_eyerok_explode:
chan_setbank 4
chan_setinstr 9
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_2854
chan_setlayer 1, .layer_2856
chan_end
.layer_2854:
layer_setinstr 15
.layer_2856:
layer_transpose 6
layer_call .layer_fn_119F
layer_transpose -9
layer_call .layer_fn_119F
layer_transpose -20
layer_jump .layer_fn_119F
.sound_obj_chuckya_death:
chan_call .sound_obj_king_whomp_death
chan_setlayer 1, .layer_288B
chan_setval 2
chan_call .delay
chan_setbank 8
chan_setinstr 10
chan_setlayer 2, .layer_2878
chan_end
.layer_2878:
layer_portamento 0x83, 43, 255
layer_note1 46, 0x9, 115
layer_somethingon
layer_portamento 0x85, 48, 255
layer_note1 50, 0x8, 127
layer_note1 44, 0x1e, 127
layer_end
.layer_288B:
layer_transpose 2
layer_jump .layer_252C
.sound_obj_wiggler_talk:
chan_setbank 7
chan_setinstr 10
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_289B
chan_end
.layer_289B:
layer_transpose 3
layer_portamento 0x81, 46, 255
layer_note1 55, 0xa, 105
layer_call .layer_fn_28BF
layer_delay 0xf
layer_portamento 0x81, 44, 255
layer_note0 53, 0xf, 105, 127
layer_portamento 0x81, 43, 255
layer_note1 51, 0xc, 105
layer_portamento 0x81, 46, 255
layer_note1 43, 0xe, 105
.layer_fn_28BF:
layer_portamento 0x81, 43, 255
layer_note1 51, 0xc, 105
layer_end
.sound_obj_wiggler_attacked:
chan_setbank 7
chan_setinstr 10
chan_setenvelope .envelope_3344
chan_setlayer 0, .layer_28D2
chan_end
.layer_28D2:
layer_transpose 6
layer_portamento 0x83, 53, 255
layer_note1 48, 0x8, 105
layer_note0 60, 0x9, 105, 100
layer_note1 39, 0xb, 105
layer_end
.sound_obj_wiggler_low_pitch:
chan_setbank 6
chan_setinstr 7
chan_setlayer 0, .layer_28EB
chan_end
.layer_28EB:
layer_transpose -2
layer_note0 31, 0xa, 127, 70
layer_note0 30, 0xb, 127, 70
layer_note0 29, 0xa, 127, 70
layer_note0 28, 0xc, 127, 70
layer_end
.sound_obj_snufit_skeeter_death:
chan_call .sound_obj_default_death
chan_setval 1
chan_call .delay
chan_setbank 7
chan_setinstr 10
chan_setenvelope .envelope_3344
chan_setlayer 1, .layer_2911
chan_end
.layer_2911:
layer_transpose 12
layer_portamento 0x83, 53, 255
layer_note1 48, 0x8, 105
layer_note0 60, 0x9, 105, 100
layer_note1 39, 0x14, 105
layer_end
.sound_obj_bubba_chomp:
chan_call .sound_obj_piranha_plant_bite
chan_setval 10
chan_call .delay
chan_setbank 9
chan_setinstr 0
chan_setenvelope .envelope_340C
chan_setlayer 0, .layer_2935
chan_end
.layer_2935:
layer_transpose 6
layer_portamento 0x85, 12, 255
layer_note1 0, 0x12, 127
layer_note1 10, 0x14, 127
layer_end
.sound_obj_enemy_defeat_shrink:
chan_setbank 7
chan_setinstr 0
chan_setlayer 0, .layer_2951
chan_setlayer 1, .layer_294D
chan_end
.layer_294D:
layer_transpose 5
layer_delay 0x3
.layer_2951:
layer_note1 43, 0x6, 105
layer_portamento 0x81, 32, 255
layer_note1 44, 0x8, 105
layer_portamento 0x81, 29, 255
layer_note1 41, 0xa, 105
layer_portamento 0x81, 26, 255
layer_note1 38, 0xd, 105
layer_portamento 0x81, 22, 255
layer_note1 34, 0x10, 105
layer_end
.channel6_table:
sound_ref .sound_air_bowser_spit_fire
sound_ref .chan_29C2
sound_ref .sound_air_lakitu_fly
sound_ref .sound_air_amp_buzz
sound_ref .sound_air_blow_fire
sound_ref .sound_air_rough_slide
sound_ref .sound_air_heaveho_move
sound_ref .chan_2A3D
sound_ref .sound_air_bobomb_lit_fuse
sound_ref .sound_air_howling_wind
sound_ref .sound_air_chuckya_move
sound_ref .sound_air_peach_twinkle
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_castle_outdoors_ambient
sound_ref .chan_29C2
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .chan_29C2
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
sound_ref .sound_air_bowser_spit_fire
.sound_air_bowser_spit_fire:
chan_setbank 7
chan_setinstr 5
chan_setlayer 0, .layer_29B9
chan_end
.layer_29B9:
layer_somethingon
.layer_29BA:
layer_note1 39, 0x12c, 127
layer_jump .layer_29BA
layer_end
.chan_29C2:
chan_setbank 7
chan_setinstr 6
chan_setlayer 0, .layer_29CA
chan_end
.layer_29CA:
layer_somethingon
.layer_29CB:
layer_note1 39, 0x12c, 90
layer_jump .layer_29CB
layer_end
.sound_air_lakitu_fly:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_29DE
chan_end
.layer_29DE:
layer_transpose 12
layer_somethingon
layer_portamento 0x85, 27, 255
.layer_29E5:
layer_note1 51, 0x16, 50
layer_note1 27, 0x16, 50
layer_jump .layer_29E5
layer_end
.sound_air_amp_buzz:
chan_setbank 3
chan_setinstr 9
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_29FA
chan_end
.layer_29FA:
layer_somethingon
.layer_29FB:
layer_note1 46, 0xc8, 92
layer_jump .layer_29FB
layer_end
.sound_air_blow_fire:
chan_setbank 7
chan_setinstr 5
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_2A0E
chan_end
.layer_2A0E:
layer_somethingon
.layer_2A0F:
layer_note1 44, 0x12c, 127
layer_jump .layer_2A0F
layer_end
.sound_air_rough_slide:
chan_setbank 3
chan_setinstr 6
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_2A22
chan_end
.layer_2A22:
layer_somethingon
.layer_2A23:
layer_note1 35, 0x12c, 127
layer_jump .layer_2A23
layer_end
.sound_air_heaveho_move:
chan_setbank 5
chan_setinstr 5
chan_setlayer 0, .layer_2A33
chan_end
.layer_2A33:
layer_note1 56, 0x4, 62
layer_note1 32, 0x3, 62
layer_jump .layer_2A33
layer_end
.chan_2A3D:
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_2A45
chan_end
.layer_2A45:
layer_portamento 0x81, 24, 255
layer_note1 56, 0x10, 55
layer_jump .layer_2A45
layer_end
.sound_air_bobomb_lit_fuse:
chan_setbank 3
chan_setinstr 5
chan_setlayer 0, .layer_2A61
chan_setval 1
chan_call .delay
chan_setbank 3
chan_setinstr 8
chan_end
.layer_2A61:
layer_note1 48, 0x6, 100
layer_somethingon
.layer_2A65:
layer_note1 44, 0x12c, 127
layer_jump .layer_2A65
layer_end
.chan_unused_2A6D:
chan_setbank 3
chan_setinstr 6
chan_setenvelope .envelope_32E4
chan_setlayer 0, .layer_2A78
chan_end
.layer_2A78:
layer_somethingon
layer_note1 35, 0x12c, 100
layer_jump .layer_2A23
layer_end
.sound_air_howling_wind:
chan_setlayer 0, .layer_2AA7
chan_setlayer 1, .layer_2AB7
chan_setpanmix 0
.chan_2A89:
chan_setbank 5
chan_setinstr 6
chan_setdecayrelease 3
chan_setval 1
chan_call .delay
chan_setbank 6
chan_setinstr 9
chan_setdecayrelease 3
chan_setval 199
chan_call .delay
chan_setval 100
chan_call .delay
chan_jump .chan_2A89
.layer_2AA7:
layer_somethingon
layer_portamento 0x85, 38, 255
.layer_2AAC:
layer_note1 41, 0x12c, 127
layer_note1 38, 0x12c, 127
layer_jump .layer_2AAC
.layer_2AB7:
layer_delay 1
layer_setpan 30
layer_note1 56, 0xc, 10
layer_delay 0x6c
layer_setpan 90
layer_note1 55, 0x1e, 35
layer_delay 0x3b
layer_setpan 55
layer_note1 56, 0x2e, 68
layer_delay 0x2d
layer_note1 58, 0x25, 34
layer_delay 0x2b
layer_setpan 91
layer_note1 53, 0x6, 55
layer_note1 55, 0x18, 70
layer_delay 0x2b
layer_setpan 21
layer_note1 56, 0x28, 52
layer_delay 0x1b
layer_note1 57, 0x18, 65
layer_delay 0x38
layer_setpan 75
layer_note1 53, 0x22, 67
layer_delay 0x4c
layer_setpan 105
layer_note1 53, 0x3, 54
layer_note1 55, 0x17, 61
layer_delay 0x43
layer_setpan 64
layer_note1 52, 0x28, 45
layer_delay 0x38
layer_jump .layer_2AB7
.sound_air_chuckya_move:
chan_setbank 5
chan_setinstr 5
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_2B0F
chan_end
.layer_2B0F:
layer_portamento 0x81, 56, 255
layer_note1 44, 0x3, 85
layer_note1 20, 0x2, 85
layer_jump .layer_2B0F
layer_end
.channel7_table:
sound_ref .sound_menu_change_select
sound_ref .sound_menu_reverse_pause
sound_ref .sound_menu_pause
sound_ref .sound_menu_pause
sound_ref .sound_menu_message_appear
sound_ref .sound_menu_message_disappear
sound_ref .sound_menu_camera_zoom_in
sound_ref .sound_menu_camera_zoom_out
sound_ref .sound_menu_pinch_mario_face
sound_ref .sound_menu_let_go_mario_face
sound_ref .sound_menu_hand_appear
sound_ref .sound_menu_hand_disappear
sound_ref .chan_2D18
sound_ref .sound_menu_power_meter
sound_ref .sound_menu_camera_buzz
sound_ref .sound_menu_camera_turn
sound_ref .chan_2DA8
sound_ref .sound_menu_click_file_select
sound_ref .sound_menu_read_sign
sound_ref .sound_menu_message_next_page
sound_ref .sound_menu_coin_its_a_me_mario
sound_ref .sound_menu_yoshi_gain_lives
sound_ref .sound_menu_enter_pipe
sound_ref .sound_menu_exit_pipe
sound_ref .sound_menu_bowser_laugh
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_click_change_view
sound_ref .sound_menu_camera_unused1
sound_ref .sound_menu_camera_unused2
sound_ref .sound_menu_mario_castle_warp
sound_ref .sound_menu_star_sound
sound_ref .sound_menu_thank_you_playing_my_game
sound_ref .sound_menu_read_a_sign
sound_ref .sound_menu_exit_a_sign
sound_ref .sound_menu_mario_castle_warp2
#ifdef VERSION_JP
sound_ref .sound_menu_message_next_page
sound_ref .sound_menu_coin_its_a_me_mario
sound_ref .sound_menu_yoshi_gain_lives
sound_ref .sound_menu_enter_pipe
sound_ref .sound_menu_exit_pipe
sound_ref .sound_menu_bowser_laugh
sound_ref .sound_menu_enter_hole
sound_ref .sound_menu_click_change_view
sound_ref .sound_menu_camera_unused1
sound_ref .sound_menu_camera_unused2
sound_ref .sound_menu_mario_castle_warp
sound_ref .sound_menu_star_sound
sound_ref .sound_menu_change_select
#else
sound_ref .sound_menu_star_sound_okey_dokey
sound_ref .sound_menu_star_sound_lets_a_go
sound_ref .sound_menu_yoshi_gain_lives
sound_ref .sound_menu_enter_pipe
sound_ref .sound_menu_exit_pipe
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_red_coin
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_collect_secret
sound_ref .sound_menu_pinch_mario_face
sound_ref .sound_menu_let_go_mario_face
sound_ref .sound_menu_hand_appear
sound_ref .sound_menu_hand_disappear
sound_ref .chan_2D18
sound_ref .sound_menu_power_meter
sound_ref .sound_menu_camera_buzz
sound_ref .sound_menu_camera_turn
#endif
.sound_menu_change_select:
chan_setbank 9
chan_setinstr 1
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setpanmix 0
chan_setenvelope .envelope_340C
chan_setlayer 0, .layer_2BB0
chan_setlayer 1, .layer_2BBD
chan_end
.layer_2BB0:
layer_portamento 0x1, 35, 0xa
layer_note1 41, 0xa, 80
layer_setpan 0
layer_note1 41, 0xa, 80
layer_end
.layer_2BBD:
layer_setpan 127
layer_delay 0xc
layer_note1 41, 0xa, 80
layer_end
.sound_menu_reverse_pause:
chan_setbank 9
chan_setinstr 1
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setpanmix 0
chan_setlayer 0, .layer_2BD5
chan_setlayer 1, .layer_2BEC
chan_end
.layer_2BD5:
layer_setpan 34
.layer_2BD7:
layer_note0 45, 0xc, 80, 63
layer_note0 41, 0xc, 80, 63
layer_note0 48, 0xc, 80, 63
layer_note0 41, 0xc, 38, 63
layer_note0 48, 0xc, 38, 63
layer_end
.layer_2BEC:
layer_setpan 94
layer_delay 0x2
layer_jump .layer_2BD7
.sound_menu_pause:
chan_setbank 9
chan_setinstr 1
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setpanmix 0
chan_setlayer 0, .layer_2C03
chan_setlayer 1, .layer_2C10
chan_end
.layer_2C03:
layer_note1 43, 0x9, 95
layer_note1 39, 0x9, 90
layer_note1 43, 0x9, 95
layer_note1 39, 0x9, 90
layer_end
.layer_2C10:
layer_delay 0x8
layer_setpan 40
layer_note1 43, 0x9, 35
layer_setpan 88
layer_note1 39, 0x9, 35
layer_setpan 36
layer_note1 43, 0x9, 30
layer_setpan 92
layer_note1 39, 0x9, 30
layer_setpan 28
layer_note1 43, 0x9, 25
layer_setpan 100
layer_note1 39, 0x9, 25
layer_end
.sound_menu_message_appear:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 2
chan_setlayer 0, .layer_2C3A
chan_end
.layer_2C3A:
layer_portamento 0x1, 32, 0x7f
layer_note1 56, 0x1e, 102
layer_end
.sound_menu_message_disappear:
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 0
chan_setenvelope .envelope_3438
chan_setlayer 0, .layer_2C4E
chan_end
.layer_2C4E:
layer_portamento 0x1, 32, 0x7f
layer_note1 53, 0x1e, 78
layer_end
.sound_menu_camera_zoom_out:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_341C
chan_setlayer 0, .layer_2C64
chan_end
.layer_2C64:
layer_portamento 0x1, 32, 0x8
layer_note1 27, 0x8, 127
layer_portamento 0x81, 39, 255
layer_note1 20, 0x28, 127
layer_end
.sound_menu_camera_zoom_in:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_2C81
chan_end
.layer_2C81:
layer_portamento 0x1, 27, 0x8
layer_note1 32, 0x8, 93
layer_portamento 0x81, 20, 255
layer_note1 39, 0x28, 93
layer_end
.sound_menu_pinch_mario_face:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 1
chan_setenvelope .envelope_3444
chan_setvibratorate 1
chan_setvibratoextent 100
chan_setlayer 0, .layer_2CA0
chan_end
.layer_2CA0:
layer_somethingon
layer_portamento 0x85, 27, 255
layer_note1 15, 0x6, 127
layer_note1 34, 0xc, 127
layer_end
.sound_menu_let_go_mario_face:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 1
chan_setenvelope .envelope_3454
chan_setvibratorate 25
chan_setvibratoextent 80
chan_setlayer 0, .layer_2CDA
chan_setlayer 1, .layer_2CD6
chan_setval 5
chan_call .delay
chan_setvibratorate 35
chan_setvibratoextent 115
chan_setval 55
chan_call .delay
chan_setvibratoextent 80
chan_setval 67
chan_call .delay
chan_setvibratoextent 0
chan_end
.layer_2CD6:
layer_transpose 12
layer_delay 0x3
.layer_2CDA:
layer_portamento 0x85, 24, 255
layer_note1 28, 0x5, 110
layer_note1 28, 0x78, 110
layer_end
.sound_menu_hand_appear:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 3
chan_setlayer 0, .layer_2CF3
chan_setlayer 1, .layer_2CF1
chan_end
.layer_2CF1:
layer_delay 0x2
.layer_2CF3:
layer_portamento 0x85, 47, 255
layer_note1 35, 0x8, 90
layer_note1 47, 0x10, 90
layer_end
.sound_menu_hand_disappear:
chan_setbank 9
chan_setnotepriority 14
chan_setinstr 3
chan_setlayer 0, .layer_2D0C
chan_setlayer 1, .layer_2D0A
chan_end
.layer_2D0A:
layer_delay 0x2
.layer_2D0C:
layer_portamento 0x85, 35, 255
layer_note1 47, 0x8, 90
layer_note1 35, 0x10, 90
layer_disableportamento
layer_end
.chan_2D18:
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_3454
chan_setlayer 0, .layer_2D26
chan_end
.layer_2D26:
layer_note1 45, 0x6, 100
layer_note1 57, 0x6, 100
layer_note1 57, 0xc, 100
layer_setpan 10
layer_note1 57, 0x6, 57
layer_note1 57, 0xc, 57
layer_setpan 117
layer_note1 57, 0x6, 38
layer_note1 57, 0xc, 38
layer_end
.sound_menu_power_meter:
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_3454
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_2D53
chan_end
.layer_2D53:
layer_setpan 30
layer_note1 44, 0x5, 105
layer_setpan 50
layer_note1 47, 0x5, 105
layer_setpan 77
layer_note1 52, 0x5, 105
layer_setpan 97
layer_note1 56, 0xa, 105
layer_setpan 30
layer_note1 52, 0x5, 45
layer_setpan 97
layer_note1 56, 0xa, 45
layer_setpan 30
layer_note1 52, 0x5, 32
layer_setpan 97
layer_note1 56, 0xa, 32
layer_end
.sound_menu_camera_buzz:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 4
chan_setlayer 0, .layer_2D87
chan_end
.layer_2D87:
layer_note1 39, 0x18, 105
layer_end
.sound_menu_camera_turn:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3428
chan_setlayer 0, .layer_2D99
chan_end
.layer_2D99:
layer_portamento 0x81, 23, 255
layer_note1 35, 0x9, 96
layer_portamento 0x81, 36, 255
layer_note1 43, 0x44, 100
layer_end
.chan_2DA8:
chan_setnotepriority 14
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_2DB1
chan_end
.layer_2DB1:
layer_delay 1
layer_end
.sound_menu_click_file_select:
chan_setmutebhv 0x0
chan_setnotepriority 14
chan_setbank 6
chan_setinstr 11
chan_setlayer 0, .layer_2DBF
chan_end
.layer_2DBF:
layer_portamento 0x81, 32, 255
layer_note0 39, 0x5, 115, 255
layer_portamento 0x81, 44, 255
layer_note0 51, 0x3, 115, 255
layer_end
.sound_menu_read_sign:
chan_setmutebhv 0x0
chan_setbank 9
chan_setinstr 1
chan_setval 60
chan_call .set_reverb
chan_setlayer 0, .layer_2DDF
chan_end
.layer_2DDF:
layer_note1 46, 0x3, 90
layer_note1 46, 0x3, 30
layer_note1 58, 0x3, 90
layer_note1 58, 0x3, 30
layer_note1 46, 0x3, 90
layer_note1 46, 0x3, 30
layer_end
.sound_menu_message_next_page:
chan_setbank 9
chan_setinstr 0
chan_setenvelope .envelope_32C4
chan_setlayer 0, .layer_2DFD
chan_end
.layer_2DFD:
layer_portamento 0x81, 15, 255
layer_note1 51, 0x5, 73
layer_end
.sound_menu_coin_its_a_me_mario:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_3358
chan_setvibratoextent 3
chan_setvibratorate 60
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_2E28
chan_setlayer 1, .layer_2E3D
chan_setlayer 2, .layer_2E34
chan_setval 70
chan_call .delay
chan_setbank 10
chan_setinstr 8
chan_end
.layer_2E28:
layer_call .layer_11E4
layer_delay 0x12
layer_transpose 0
layer_note1 39, 0xc8, 120
layer_end
.layer_2E34:
layer_delay 0x6e
layer_transpose 0
layer_note1 39, 0xc8, 31
layer_end
.layer_2E3D:
layer_transpose 24
layer_delay 0x1e
layer_note1 25, 0x2, 18
layer_note1 37, 0x7, 36
layer_note1 30, 0x5, 18
layer_note1 42, 0x37, 36
layer_end
.sound_menu_yoshi_gain_lives:
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_3454
chan_setval 25
chan_call .set_reverb
chan_setpanmix 0
chan_stereoheadseteffects 1
chan_setlayer 0, .layer_2E65
chan_end
.layer_2E65:
layer_note1 46, 0x5, 105
layer_note1 53, 0x5, 105
layer_note1 58, 0x5, 105
layer_setpan 30
layer_note1 53, 0x5, 50
layer_setpan 98
layer_note1 58, 0x5, 50
layer_setpan 20
layer_note1 53, 0x5, 20
layer_setpan 108
layer_note1 58, 0x5, 20
layer_end
.sound_menu_enter_pipe:
chan_reservenotes 4
chan_setbank 9
chan_setinstr 2
chan_setpanmix 0
chan_stereoheadseteffects 1
chan_setval 30
chan_call .set_reverb
chan_setenvelope .envelope_33BC
chan_setdecayrelease 220
chan_setlayer 0, .layer_2EA3
chan_setlayer 1, .layer_2E9E
chan_end
.layer_2E9E:
layer_transpose -12
layer_jump .layer_2EA5
.layer_2EA3:
layer_transpose -24
.layer_2EA5:
layer_call .layer_fn_2EAB
layer_call .layer_fn_2EAB
.layer_fn_2EAB:
layer_portamento 0x85, 60, 192
layer_setpan 117
layer_note1 60, 0x3, 126
layer_setpan 105
layer_note1 58, 0x3, 126
layer_setpan 93
layer_note1 55, 0x3, 126
layer_setpan 81
layer_note1 51, 0x3, 126
layer_setpan 46
layer_note1 50, 0x3, 126
layer_setpan 34
layer_note1 46, 0x3, 126
layer_setpan 22
layer_note1 44, 0x3, 126
layer_setpan 10
layer_note1 41, 0x3, 126
layer_end
.sound_menu_exit_pipe:
chan_reservenotes 4
chan_setbank 9
chan_setinstr 2
#if defined(VERSION_SH) || defined(VERSION_CN)
chan_setval 15
.set EXIT_PIPE_NOTE_VELOCITY, 106
#else
chan_setval 30
.set EXIT_PIPE_NOTE_VELOCITY, 126
#endif
chan_call .set_reverb
chan_setenvelope .envelope_3464
chan_setdecayrelease 220
chan_setlayer 0, .layer_2EF4
chan_setlayer 1, .layer_2EEF
chan_end
.layer_2EEF:
layer_transpose 24
layer_jump .layer_2EF6
.layer_2EF4:
layer_transpose 12
.layer_2EF6:
layer_portamento 0x85, 15, 128
layer_note1 15, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 19, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 22, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 27, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 22, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 27, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 31, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 34, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 39, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 34, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 23, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 27, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 30, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 35, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 30, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 35, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 39, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 42, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 47, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 42, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 25, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 29, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 32, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 37, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 32, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 37, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 41, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 44, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 49, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_note1 44, 0x3, EXIT_PIPE_NOTE_VELOCITY
layer_end
.sound_menu_bowser_laugh:
chan_setbank 6
chan_setinstr 9
chan_setval 25
chan_call .set_reverb
chan_setlayer 0, .layer_271D
chan_setlayer 1, .layer_271D
chan_end
.sound_menu_click_change_view:
chan_setbank 9
chan_setinstr 5
chan_setlayer 0, .layer_2F6D
chan_end
.layer_2F6D:
layer_note1 39, 0x30, 127
layer_end
.sound_menu_camera_unused1:
chan_setbank 9
chan_setinstr 3
chan_setenvelope .envelope_32D4
chan_setlayer 0, .layer_2F7C
chan_end
.layer_2F7C:
layer_transpose -12
layer_portamento 0x83, 3, 255
layer_note1 15, 0xa, 127
layer_somethingon
layer_transpose 0
layer_note1 46, 0x64, 127
layer_end
.sound_menu_camera_unused2:
chan_setbank 9
chan_setinstr 3
chan_setlayer 0, .layer_2F97
chan_setenvelope .envelope_32D4
chan_end
.layer_2F97:
layer_portamento 0x81, 3, 255
layer_note1 15, 0xc, 127
layer_portamento 0x81, 39, 255
layer_note1 3, 0x64, 127
layer_end
.sound_menu_mario_castle_warp:
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_340C
chan_setreverb 30
chan_setlayer 0, .layer_3032
chan_setlayer 1, .layer_2FB9
chan_end
.layer_2FB9:
layer_transpose -24
layer_setpan 24
layer_call .layer_fn_300D
layer_transpose -12
layer_setpan 44
layer_call .layer_fn_300D
layer_transpose 0
.layer_2FC9:
layer_setpan 64
layer_call .layer_fn_300D
layer_transpose 12
layer_setpan 84
layer_call .layer_fn_300D
layer_transpose 24
layer_setpan 104
layer_call .layer_fn_300D
layer_setpan 24
layer_note1 56, 0x2, 100
layer_note1 56, 0x1, 50
layer_setpan 104
layer_note1 60, 0x14, 70
layer_note1 60, 0xa, 30
layer_setpan 24
layer_note1 56, 0x2, 50
layer_note1 56, 0x1, 20
layer_setpan 104
layer_note1 60, 0x14, 30
layer_note1 60, 0xa, 10
layer_setpan 24
layer_note1 56, 0x2, 30
layer_note1 56, 0x1, 10
layer_setpan 104
layer_note1 60, 0x14, 20
layer_note1 60, 0xa, 7
layer_end
.layer_fn_300D:
layer_note1 51, 0x2, 50
layer_note1 39, 0x1, 40
layer_note1 39, 0x2, 20
layer_note1 55, 0x2, 50
layer_note1 43, 0x1, 40
layer_note1 43, 0x2, 20
layer_note1 56, 0x2, 50
layer_note1 44, 0x1, 40
layer_note1 44, 0x2, 20
layer_note1 60, 0x2, 50
layer_note1 48, 0x1, 40
layer_note1 48, 0x2, 20
layer_end
.layer_3032:
layer_transpose -24
layer_call .layer_fn_3072
layer_transpose -12
layer_call .layer_fn_3072
layer_transpose 0
layer_call .layer_fn_3072
.layer_3041:
layer_transpose 12
layer_call .layer_fn_3072
layer_transpose 24
layer_call .layer_fn_3072
layer_setpan 64
layer_note1 44, 0x1, 100
layer_note1 56, 0x2, 50
layer_note1 48, 0xa, 70
layer_note1 60, 0x14, 30
layer_note1 44, 0x1, 50
layer_note1 56, 0x2, 20
layer_note1 48, 0xa, 30
layer_note1 60, 0x14, 10
layer_note1 44, 0x1, 30
layer_note1 56, 0x2, 10
layer_note1 48, 0xa, 20
layer_note1 60, 0x14, 7
layer_end
.layer_fn_3072:
layer_setpan 54
layer_note1 39, 0x3, 100
layer_note1 51, 0x1, 50
layer_note1 51, 0x1, 20
layer_setpan 74
layer_note1 43, 0x3, 100
layer_note1 55, 0x1, 50
layer_note1 55, 0x1, 20
layer_setpan 54
layer_note1 44, 0x3, 100
layer_note1 56, 0x1, 50
layer_note1 56, 0x1, 20
layer_setpan 74
layer_note1 48, 0x3, 100
layer_note1 60, 0x1, 50
layer_note1 60, 0x1, 20
layer_end
.sound_menu_thank_you_playing_my_game:
chan_setbank 10
chan_setinstr 14
chan_setlayer 0, .layer_30AA
chan_setlayer 1, .layer_30AF
chan_end
.layer_30AA:
layer_note1 39, 0xfa, 127
layer_end
.layer_30AF:
layer_delay 0x9
layer_note1 39, 0xf1, 45
layer_end
.sound_menu_read_a_sign:
chan_setbank 9
chan_setinstr 1
chan_setlayer 0, .layer_30BE
chan_end
.layer_30BE:
layer_note1 46, 0x3, 90
layer_note1 46, 0x3, 30
layer_note1 58, 0x3, 90
layer_note1 58, 0x3, 30
layer_end
.sound_menu_exit_a_sign:
chan_setbank 9
chan_setinstr 1
chan_setlayer 0, .layer_30D3
chan_end
.layer_30D3:
layer_note1 58, 0x3, 90
layer_note1 58, 0x3, 30
layer_note1 46, 0x3, 90
layer_note1 46, 0x3, 30
layer_end
.sound_menu_mario_castle_warp2:
chan_reservenotes 6
chan_setbank 9
chan_setnotepriority 14
chan_setpanmix 0
chan_setinstr 3
chan_setenvelope .envelope_340C
chan_setreverb 30
chan_setlayer 0, .layer_3041
chan_setlayer 1, .layer_2FC9
chan_end
#ifndef VERSION_JP
.sound_menu_star_sound_okey_dokey:
chan_setbank 4
chan_setinstr 14
chan_setlayer 0, .layer_1344
chan_setval 1
chan_call .delay
chan_setbank 10
chan_setinstr 12
chan_setlayer 1, .layer_E3A
chan_end
.sound_menu_star_sound_lets_a_go:
chan_setbank 8
chan_setinstr 26
chan_setlayer 0, .layer_311D
chan_setval 1
chan_call .delay
chan_setbank 4
chan_setinstr 14
chan_setlayer 1, .layer_1344
chan_end
.layer_311D:
layer_note1 39, 0xb4, 127
layer_end
.sound_menu_collect_red_coin:
chan_setinstr 128
chan_setnotepriority 14
chan_setpanmix 0
chan_setenvelope .envelope_3378
chan_ioreadval 4
chan_subtract 0x28
chan_readseq .major_scale
chan_writeseq 0, .transpose_by_coin_index, 1
chan_setlayer 0, .layer_3146
chan_setlayer 1, .layer_3168
chan_setlayer 2, .layer_3148
chan_end
.major_scale:
.byte 0
.byte 2
.byte 4
.byte 5
.byte 7
.byte 9
.byte 11
.byte 12
.layer_3146:
layer_delay 0x6
#if defined(VERSION_SH) || defined(VERSION_CN)
.set RED_COIN_NOTE_VELOCITY_SUB, 10
#else
.set RED_COIN_NOTE_VELOCITY_SUB, 0
#endif
.layer_3148:
layer_call .transpose_by_coin_index
layer_note0 46, 0xc, (75 - RED_COIN_NOTE_VELOCITY_SUB), 20
layer_note0 45, 0xc, (75 - RED_COIN_NOTE_VELOCITY_SUB), 20
layer_note0 46, 0xc, (75 - RED_COIN_NOTE_VELOCITY_SUB), 20
layer_note0 58, 0x10, (80 - RED_COIN_NOTE_VELOCITY_SUB), 80
layer_note0 58, 0x10, (45 - RED_COIN_NOTE_VELOCITY_SUB), 80
layer_note0 58, 0x10, (20 - RED_COIN_NOTE_VELOCITY_SUB), 80
layer_note0 58, 0x10, (15 - RED_COIN_NOTE_VELOCITY_SUB), 80
layer_end
.layer_3168:
layer_call .transpose_by_coin_index
layer_note0 41, 0xc, (75 - RED_COIN_NOTE_VELOCITY_SUB), 20
layer_note0 40, 0xc, (75 - RED_COIN_NOTE_VELOCITY_SUB), 20
layer_note0 41, 0xc, (75 - RED_COIN_NOTE_VELOCITY_SUB), 20
layer_note0 53, 0x10, (80 - RED_COIN_NOTE_VELOCITY_SUB), 80
layer_note0 53, 0x10, (45 - RED_COIN_NOTE_VELOCITY_SUB), 80
layer_note0 53, 0x10, (20 - RED_COIN_NOTE_VELOCITY_SUB), 80
layer_note0 53, 0x10, (15 - RED_COIN_NOTE_VELOCITY_SUB), 80
layer_end
.transpose_by_coin_index:
layer_transpose 0
layer_end
.sound_menu_collect_secret:
chan_setbank 4
chan_setinstr 14
chan_setnotepriority 14
chan_setpanmix 0
chan_ioreadval 4
chan_subtract 0x30
chan_readseq .major_scale
chan_writeseq 0, .layer_31A0, 1
chan_setlayer 0, .layer_31A0
chan_end
.layer_31A0:
layer_transpose 0
layer_note1 32, 0x7f, 115
layer_end
#endif
.sound_general_bird_chirp2:
chan_setbank 5
chan_setinstr 9
chan_setval 40
chan_call .set_reverb
chan_setlayer 0, .layer_31B3
chan_end
.layer_31B3:
layer_delay 0x4b
layer_note0 39, 0xf5, 100, 127
layer_note0 39, 0xa, 85, 127
layer_note0 40, 0x123, 98, 127
layer_note0 39, 0x91, 75, 127
layer_note0 41, 0xbd, 84, 127
layer_note0 39, 0x4b, 73, 127
layer_note0 39, 0x96, 94, 127
layer_note0 36, 0x74, 78, 127
layer_jump .layer_31B3
layer_end
.sound_obj_bird_chirp3:
chan_setbank 5
chan_setinstr 10
chan_setval 60
chan_call .set_reverb
chan_setlayer 0, .layer_31EB
chan_end
.layer_31EB:
layer_delay 0x14
layer_note1 39, 0x71, 70
layer_note1 37, 0xd3, 62
layer_note1 39, 0x48, 84
layer_note1 40, 0x71, 49
layer_note1 39, 0xa8, 65
layer_note1 41, 0x86, 59
layer_note1 41, 0x31, 54
layer_note1 38, 0x6f, 51
layer_note1 39, 0xc7, 79
layer_note1 35, 0xe9, 74
layer_jump .layer_31EB
layer_end
.sound_obj_bird_chirp1:
chan_setbank 5
chan_setinstr 12
chan_setval 30
chan_call .set_reverb
chan_setlayer 0, .layer_3221
chan_end
.layer_3221:
layer_delay 0x32
layer_note1 41, 0x31, 66
layer_delay 0x9f
layer_note1 39, 0x31, 51
layer_delay 0xf9
layer_note1 38, 0x1d, 60
layer_note1 41, 0x4c, 77
layer_delay_long 0x64
layer_note1 42, 0x31, 59
layer_delay 0x159
layer_note1 36, 0x4f, 61
layer_delay 0xc6
layer_jump .layer_3221
layer_end
.sound_air_castle_outdoors_ambient:
chan_setbank 5
chan_setval 15
chan_call .set_reverb
chan_setlayer 0, .layer_3259
chan_setlayer 1, .layer_327F
chan_setlayer 2, .layer_3281
chan_end
.layer_3259:
layer_setinstr 8
layer_delay 0x18
layer_note1 41, 0x9, 26
layer_note1 37, 0xbc, 22
layer_note1 39, 0x71, 33
layer_note1 40, 0xd7, 33
layer_note1 39, 0x54, 39
layer_note1 39, 0x6f, 31
layer_note1 43, 0xa8, 26
layer_note1 40, 0xe1, 22
layer_note1 38, 0x74, 31
layer_jump .layer_3259
.layer_327F:
layer_transpose 12
.layer_3281:
layer_setinstr 13
layer_somethingon
layer_delay 0xf
.layer_3286:
layer_note1 39, 0x12c, 25
layer_jump .layer_3286
.sound_general_switch_tick_slow:
chan_setval 18
chan_jump .chan_3294
.sound_general_switch_tick_fast:
chan_setval 42
.chan_3294:
chan_writeseq 0, .layer_32BF, 1
chan_reservenotes 4
chan_setbank 4
chan_setinstr 2
chan_setenvelope .envelope_3314
chan_setdecayrelease 15
chan_setlayer 0, .layer_32B7
chan_setlayer 1, .layer_32B3
.chan_32A9:
chan_delay1
chan_ioreadval 0
chan_iowriteval 0
chan_subtract 255
chan_beqz .chan_32A9
chan_unreservenotes
chan_end
.layer_32B3:
layer_setinstr 9
layer_transpose 12
.layer_32B7:
layer_note0 50, 0x3, 127, 127
layer_note0 38, 0x3, 127, 127
.layer_32BF:
layer_delay 0x2a
layer_jump .layer_32B7
.align 2, 0
.envelope_32C4:
envelope_line 7 20000
envelope_line 6 32700
envelope_line 32700 32700
envelope_goto 2
.envelope_32D4:
envelope_line 9 15000
envelope_line 7 32700
envelope_line 32700 32700
envelope_goto 2
.envelope_32E4:
envelope_line 10 10000
envelope_line 100 32700
envelope_line 32700 32700
envelope_goto 2
.envelope_32F4:
envelope_line 35 32700
envelope_line 10 32700
envelope_line 300 0
envelope_goto 2
.envelope_3304:
envelope_line 15 20000
envelope_line 5 32700
envelope_line 32700 32700
envelope_goto 2
.envelope_3314:
envelope_line 8 32700
envelope_line 50 32700
envelope_line 300 0
envelope_goto 2
.envelope_3324:
envelope_line 100 25000
envelope_line 35 32700
envelope_line 300 5000
envelope_goto 2
.envelope_3334:
envelope_line 25 32700
envelope_line 4 22500
envelope_line 35 32700
envelope_goto 2
.envelope_3344:
envelope_line 1 32700
envelope_line 10 30000
envelope_line 50 30000
envelope_line 100 0
envelope_goto 3
.envelope_3358:
envelope_line 4 32700
envelope_line 100 15000
envelope_line 1000 0
envelope_goto 2
.envelope_3368:
envelope_line 10 32700
envelope_line 1 32700
envelope_line 10 0
envelope_goto 2
#ifndef VERSION_JP
.envelope_3378:
envelope_line 3 32700
envelope_line 10 30000
envelope_line 10 10000
envelope_line 100 0
envelope_goto 3
#endif
.envelope_338C:
envelope_line 1 32700
envelope_line 20 32700
envelope_line 600 6000
envelope_goto 2
.envelope_unused_339C:
envelope_line 1 32700
envelope_line 20 32700
envelope_line 100 18000
envelope_goto 2
.envelope_33AC:
envelope_line 1 32700
envelope_line 20 32700
envelope_line 300 6000
envelope_goto 2
.envelope_33BC:
envelope_line 7 18000
envelope_line 4 32760
envelope_line 30 0
envelope_goto 2
.envelope_33CC:
envelope_line 19 32700
envelope_line 5 32700
envelope_line 15 0
envelope_goto 2
.envelope_33DC:
envelope_line 25 32700
envelope_line 9 32700
envelope_line 9 0
envelope_goto 2
.envelope_33EC:
envelope_line 1 32700
envelope_line 100 32760
envelope_line 300 0
envelope_goto 2
.envelope_33FC:
envelope_line 22 32700
envelope_line 50 32760
envelope_line 70 0
envelope_goto 2
.envelope_340C:
envelope_line 5 32760
envelope_line 192 0
envelope_line 1000 1000
envelope_goto 2
.envelope_341C:
envelope_line 25 32760
envelope_line 60 10000
#if defined(VERSION_SH) || defined(VERSION_CN)
envelope_hang
#else
envelope_goto 2
#endif
.envelope_3428:
envelope_line 1 10000
envelope_line 1 10000
envelope_line 40 32760
envelope_goto 2
.envelope_3438:
envelope_line 23 32760
envelope_line 80 15000
envelope_goto 2
.envelope_3444:
envelope_line 22 32760
envelope_line 50 32760
envelope_line 100 25000
envelope_goto 2
.envelope_3454:
envelope_line 13 32760
envelope_line 50 32760
envelope_line 200 0
envelope_goto 2
.envelope_3464:
envelope_line 6 12000
envelope_line 4 32760
envelope_line 50 32760
envelope_line 200 0
envelope_goto 2
.envelope_unused_3478:
envelope_line 1 32700
envelope_line 1000 32700
envelope_line 10 16000
envelope_line 200 32760
envelope_goto 3
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_timer_ic_sr04/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_timer_ic_sr04/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_timer_ic_sr04/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_timer_ic_sr04/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_timer_ic_sr04/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_timer_ic_sr04/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_timer_ic_sr04/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_timer_ic_sr04/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_max30102/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_max30102/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_max30102/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_max30102/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_max30102/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_max30102/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_max30102/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_i2c_soft_max30102/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,352
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,346
|
stm32f103c8_drivers/stm32f103c8_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,458
|
stm32f103c8_drivers/stm32f103c8_exti/firmware/cmsis/device/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 12,079
|
stm32f103c8_drivers/stm32f103c8_exti/firmware/cmsis/device/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 13,758
|
stm32f103c8_drivers/stm32f103c8_exti/firmware/cmsis/device/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,398
|
stm32f103c8_drivers/stm32f103c8_exti/firmware/cmsis/device/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,145
|
stm32f103c8_drivers/stm32f103c8_exti/firmware/cmsis/device/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 15,597
|
stm32f103c8_drivers/stm32f103c8_exti/firmware/cmsis/device/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
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