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tactcomplabs/xbgas-binutils-gdb
| 2,391
|
gas/testsuite/gas/bfin/stack2.s
|
.EXTERN MY_LABEL2;
.section .text;
//
//5 STACK CONTROL
//
//[ -- SP ] = allreg ; /* predecrement SP (a) */
[--SP ] = R0;
[--SP ] = R6;
[--SP ] = P0;
[--SP ] = P4;
[--SP ] = I0;
[--SP ] = I1;
[--SP ] = M0;
[--SP ] = M1;
[--SP ] = L0;
[--SP ] = L1;
[--SP ] = B0;
[--SP ] = B1;
[--SP ] = A0.X;
[--SP ] = A1.X;
[--SP ] = A0.W;
[--SP ] = A1.W;
[--SP ] = ASTAT;
[--SP ] = RETS;
[--SP ] = RETI;
[--SP ] = RETX;
[--SP ] = RETN;
[--SP ] = RETE;
[--SP ] = LC0;
[--SP ] = LC1;
[--SP ] = LT0;
[--SP ] = LT1;
[--SP ] = LB0;
[--SP ] = LB1;
[--SP ] = CYCLES;
[--SP ] = CYCLES2;
//[--SP ] = EMUDAT;
[--SP ] = USP;
[--SP ] = SEQSTAT;
[--SP ] = SYSCFG;
//[ -- SP ] = ( R7 : Dreglim , P5 : Preglim ) ; /* Dregs and indexed Pregs (a) */
[--SP ] = ( R7:0, P5:0);
//[ -- SP ] = ( R7 : Dreglim ) ; /* Dregs, only (a) */
[--SP ] = ( R7:0);
//[ -- SP ] = ( P5 : Preglim ) ; /* indexed Pregs, only (a) */
[--SP ] = (P5:0);
//mostreg = [ SP ++ ] ; /* post-increment SP; does not apply to Data Registers and Pointer Registers (a) */
R0= [ SP ++ ] ;
R6= [ SP ++ ] ;
P0= [ SP ++ ] ;
P4= [ SP ++ ] ;
I0= [ SP ++ ] ;
I1= [ SP ++ ] ;
M0= [ SP ++ ] ;
M1= [ SP ++ ] ;
L0= [ SP ++ ] ;
L1= [ SP ++ ] ;
B0= [ SP ++ ] ;
B1= [ SP ++ ] ;
A0.X= [ SP ++ ] ;
A1.X= [ SP ++ ] ;
A0.W= [ SP ++ ] ;
A1.W= [ SP ++ ] ;
ASTAT= [ SP ++ ] ;
RETS= [ SP ++ ] ;
RETI= [ SP ++ ] ;
RETX= [ SP ++ ] ;
RETN= [ SP ++ ] ;
RETE= [ SP ++ ] ;
LC0= [ SP ++ ] ;
LC1= [ SP ++ ] ;
LT0= [ SP ++ ] ;
LT1= [ SP ++ ] ;
LB0= [ SP ++ ] ;
LB1= [ SP ++ ] ;
CYCLES= [ SP ++ ] ;
CYCLES2= [ SP ++ ] ;
//EMUDAT= [ SP ++ ] ;
USP= [ SP ++ ] ;
SEQSTAT= [ SP ++ ] ;
SYSCFG= [ SP ++ ] ;
//( R7 : Dreglim, P5 : Preglim ) = [ SP ++ ] ; /* Dregs and indexed Pregs (a) */
( R7:0, P5:0) = [ SP++ ];
//( R7 : Dreglim ) = [ SP ++ ] ; /* Dregs, only (a) */
( R7:0) = [ SP++ ];
//( P5 : Preglim ) = [ SP ++ ] ; /* indexed Pregs, only (a) */
( P5:0) = [ SP++ ];
//LINK uimm18m4 ; /* allocate a stack frame of specified size (b) */
LINK 0X0;
LINK 0X8;
LINK 0x3FFFC;
UNLINK ; /* de-allocate the stack frame (b)*/
L$L$foo: (R7:6,P5:3) = [SP++]; /* Pop multiple on the same line with a label */
|
tactcomplabs/xbgas-binutils-gdb
| 3,836
|
gas/testsuite/gas/bfin/parallel3.s
|
.section .text;
r4.h = r4.l = Sign (R1.h) * R5.h + Sign(r1.L) * R5.L|| [p0] = P0;
R7 = Vit_Max (R5, r2) (ASL)|| [p0++] = P0;
r0 = VIT_MAX (r0, r6) (asr)|| [p0--] = P0;
r5.l = vit_max (R3) (asL)|| [p0+4] = P0;
r2.L = VIT_Max (r2) (Asr)|| [p0+8] = P0;
R5 = ABS R5 (V)|| [p0+60] = P0;
r2 = abs r0 (v)|| [p0+56] = P0;
R5 = r3 +|+ R2|| [p0+52] = P0;
r5 = r3 +|+ r2 (Sco)|| [p1] = P0;
r7 = R0 -|+ r6|| [p1++] = P0;
r2 = R1 -|+ R3 (S)|| [p1--] = P0;
R4 = R0 +|- R2|| [p1+48] = P0;
R5 = r1 +|- r2 (CO)|| [p1+44] = P0;
r6 = r3 -|- R4|| [p1+40] = P0;
r7 = R5 -|- R6 (co)|| [p2] = P0;
r5 = r4 +|+ r3, R7 = r4 -|- r3 (Sco, ASR)|| [p2++] = P0;
R0 = R3 +|+ r6, R1 = R3 -|- R6 (ASL)|| [p2--] = P0;
R7 = R1 +|- R2, R6 = R1 -|+ R2 (S)|| [p2+36] = P0;
r1 = r2 +|- r3, r5 = r2 -|+ r3|| [p2+32] = P0;
R5 = R0 + R1, R6 = R0 - R1|| [p3] = P0;
r0 = r7 + r1, r3 = r7 - r1 (s)|| [p3++] = P0;
r7 = A1 + A0, r5 = A1 - A0|| [p3--] = P0;
r3 = a0 + a1, r6 = a0 - a1 (s)|| [p3+28] = P0;
R1 = R3 >>> 15 (V)|| [p3+24] = P0;
r4 = r0 >>> 4 (v)|| [p4] = P0;
r5 = r0 << 0 (v,s)|| [p4++] = P0;
r2 = r2 << 12 (v, S)|| [p4--] = P0;
R7 = ASHIFT R5 BY R2.L (V)|| [p4+24] = P0;
r0 = Ashift r2 by r0.L (v, s)|| [p4+20] = P0;
R5 = r2 >> 15 (V)|| [p4+16] = P0;
r0 = R1 << 2 (v)|| [p4+12] = P0;
R4 = lshift r1 by r2.L (v)|| [p5] = P0;
R6 = MAX (R0, R1) (V)|| [p5++] = P0;
r0 = min (r2, r7) (v)|| [p5--] = P0;
r2.h = r7.l * r6.h, r2.l = r7.h * r6.h|| [p5+8] = P0;
R4.L = R1.L * R0.L, R4.H = R1.H * R0.H|| [p5+4] = P0;
R0.h = R3.H * r2.l, r0.l=r3.l * r2.l|| [p5] = P0;
r5.h = r3.h * r2.h (M), r5.l = r3.L * r2.L (fu)|| [sp] = P0;
R0 = r4.l * r7.l, r1 = r4.h * r7.h (s2rnd)|| [sp++] = P0;
R7 = R2.l * r5.l, r6 = r2.h * r5.h|| [sp--] = P0;
R0.L = R7.L * R6.L, R0.H = R7.H * R6.H (ISS2)|| [sp+60] = P0;
r3.h = r0.h * r1.h, r3.l = r0.l * r1.l (is)|| [fp] = P0;
a1 = r2.l * r3.h, a0 = r2.h * R3.H|| [fp++] = P0;
A0 = R1.l * R0.L, A1 += R1.h * R0.h|| [fp--] = P0;
A1 = R5.h * R7.H, A0 += r5.L * r7.l (w32)|| [fp+0] = P0;
a1 += r0.H * r1.H, A0 = R0.L * R1.l (is)|| [fp+60] = P0;
a1 = r3.h * r4.h (m), a0 += r3.l * R4.L (FU)|| [p0] = P1;
A1 += r4.H * R4.L, a0 -= r4.h * r4.h|| [p0] = P2;
r0.l = (a0 += R7.l * R6.L), R0.H = (A1 += R7.H * R6.H) (Iss2)|| [p0] = P3;
r2.H = A1, r2.l = (a0 += r0.L * r1.L) (s2rnd)|| [p0] = P4;
r7.h = (a1 = r2.h * r1.h), a0 += r2.l * r1.l|| [p0] = P5;
R2.H = (A1 = R7.L * R6.H), R2.L = (A0 = R7.H * R6.h)|| [p0] = fp;
r6.L = (A0 = R3.L * r2.L), R6.H = (A1 += R3.H * R2.H)|| [p0] = sp;
R7.h = (a1 += r6.h * r5.l), r7.l = (a0=r6.h * r5.h)|| [p0] = r1;
r0.h = (A1 = r7.h * R4.l) (M), R0.l = (a0 += r7.l * r4.l)|| [p0++] = r2;
R5.H = (a1 = r3.h * r2.h) (m), r5.l= (a0 += r3.l * r2.l) (fu)|| [p1--] = r3;
r0.h = (A1 += R3.h * R2.h), R0.L = ( A0 = R3.L * R2.L) (is)|| [i0] = r0;
R3 = (A1 = R6.H * R7.H) (M), A0 -= R6.L * R7.L|| [i0++] = r1;
r1 = (a1 = r7.l * r4.l) (m), r0 = (a0 += r7.h * r4.h)|| [i0--] = r2;
R0 = (a0 += r7.l * r6.l), r1 = (a1+= r7.h * r6.h) (ISS2)|| [i1] = r3;
r4 = (a0 = r6.l * r7.l), r5 = (a1 += r6.h * r7.h)|| [i1++] = r3;
R7 = (A1 += r3.h * r5.H), R6 = (A0 -= r3.l * r5.l)|| [i1--] = r3;
r5 = (a1 -= r6.h * r7.h), a0 += r6.l * r7.l|| [i2] = r0;
R3 = (A1 = r6.h * R7.h), R2 = (A0 = R6.l * r7.l)|| [i2++] = r0;
R5 = (A1 = r3.h * r7.h) (M), r4 = (A0 += R3.l * r7.l) (fu)|| [i2--] = R0;
R3 = a1, r2 = (a0 += r0.l *r1.l) (s2rnd)|| [i3] = R7;
r1 = (a1 += r3.h * r2.h), r0 = (a0 = r3.l * r2.l) (is)|| [i3++] = R7;
R0 = - R1 (V)|| [i3--] = R6;
r7 = - r2 (v)|| [p0++p1] = R0;
R7 = Pack (r0.h, r1.l)|| [p0++p1] = R3;
r6 = PACK (r1.H, r6.H)|| [p0++p2] = r0;
R5 = pack (R2.L, R2.H)|| [p0++p3] = r4;
(R0, R1) = search R2 (lt)|| r2 = [p0+4];
(r6, r7) = Search r0 (LE)|| r5 = [p0--];
(r3, r6) = SEARCH r1 (Gt)|| r0 = [p0+20];
(r4, R5) = sEARch r3 (gE)|| r1 = [p0++];
|
tactcomplabs/xbgas-binutils-gdb
| 21,012
|
gas/testsuite/gas/bfin/vector2.s
|
.EXTERN MY_LABEL2;
.section .text;
//
//14 VECTOR OPERATIONS
//
//Dreg_hi = Dreg_lo = SIGN ( Dreg_hi ) * Dreg_hi + SIGN ( Dreg_lo ) * Dreg_lo ; /* (b) */
r7.h=r7.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ;
r0.h=r0.l=sign(r1.h)*r2.h+sign(r1.l)*r2.l ;
r3.h=r3.l=sign(r4.h)*r5.h+sign(r4.l)*r5.l ;
r6.h=r6.l=sign(r7.h)*r0.h+sign(r7.l)*r0.l ;
r1.h=r1.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ;
r4.h=r4.l=sign(r5.h)*r6.h+sign(r5.l)*r6.l ;
r7.h=r7.l=sign(r0.h)*r1.h+sign(r0.l)*r1.l ;
r2.h=r2.l=sign(r3.h)*r4.h+sign(r3.l)*r4.l ;
//Dual 16-Bit Operation
//Dreg = VIT_MAX ( Dreg , Dreg ) (ASL) ; /* shift history bits left (b) */
//Dreg = VIT_MAX ( Dreg , Dreg ) (ASR) ; /* shift history bits right (b) */
//Single 16-Bit Operation
//Dreg_lo = VIT_MAX ( Dreg ) (ASL) ; /* shift history bits left (b) */
//Dreg_lo = VIT_MAX ( Dreg ) (ASR) ; /* shift history bits right (b) */
r5 = vit_max(r3, r2)(asl) ; /* shift left, dual operation */
r7 = vit_max (r1, r0) (asr) ; /* shift right, dual operation */
r0 = vit_max(r1, r2)(asl) ; /* shift left, dual operation */
r3 = vit_max (r4, r5) (asr) ; /* shift right, dual operation */
r6 = vit_max(r7, r0)(asl) ; /* shift left, dual operation */
r1 = vit_max (r2, r3) (asr) ; /* shift right, dual operation */
r4 = vit_max(r5, r6)(asl) ; /* shift left, dual operation */
r7 = vit_max (r0, r1) (asr) ; /* shift right, dual operation */
r2 = vit_max(r3, r4)(asl) ; /* shift left, dual operation */
r5 = vit_max (r6, r7) (asr) ; /* shift right, dual operation */
r3.l = vit_max (r1)(asl) ; /* shift left, single operation */
r3.l = vit_max (r1)(asr) ; /* shift right, single operation */
r0.l = vit_max (r1)(asl) ; /* shift left, single operation */
r2.l = vit_max (r3)(asr) ; /* shift right, single operation */
r4.l = vit_max (r5)(asl) ; /* shift left, single operation */
r6.l = vit_max (r7)(asr) ; /* shift right, single operation */
r1.l = vit_max (r2)(asl) ; /* shift left, single operation */
r3.l = vit_max (r4)(asr) ; /* shift right, single operation */
r5.l = vit_max (r6)(asl) ; /* shift left, single operation */
r7.l = vit_max (r0)(asr) ; /* shift right, single operation */
//Dreg = ABS Dreg (V) ; /* (b) */
r3 = abs r1 (v) ;
r0 = abs r0 (v) ;
r0 = abs r1 (v) ;
r2 = abs r3 (v) ;
r4 = abs r5 (v) ;
r6 = abs r7 (v) ;
r1 = abs r0 (v) ;
r3 = abs r2 (v) ;
r5 = abs r4 (v) ;
r7 = abs r6 (v) ;
//Dual 16-Bit Operations
//Dreg = Dreg +|+ Dreg (opt_mode_0) ; /* add | add (b) */
r5=r3 +|+ r4 ; /* dual 16-bit operations, add|add */
r0=r1 +|+ r2 ;
r3=r4 +|+ r5 ;
r6=r7 +|+ r0 ;
r1=r2 +|+ r3 ;
r4=r3 +|+ r5 ;
r6=r3 +|+ r7 ;
r0=r1 +|+ r2 (S);
r3=r4 +|+ r5 (S);
r6=r7 +|+ r0 (S);
r1=r2 +|+ r3 (S);
r4=r3 +|+ r5 (S);
r6=r3 +|+ r7 (S);
r0=r1 +|+ r2 (CO);
r3=r4 +|+ r5 (CO);
r6=r7 +|+ r0 (CO) ;
r1=r2 +|+ r3 (CO);
r4=r3 +|+ r5 (CO);
r6=r3 +|+ r7 (CO);
r0=r1 +|+ r2 (SCO);
r3=r4 +|+ r5 (SCO);
r6=r7 +|+ r0 (SCO);
r1=r2 +|+ r3 (SCO);
r4=r3 +|+ r5 (SCO);
r6=r3 +|+ r7 (SCO);
//Dreg = Dreg -|+ Dreg (opt_mode_0) ; /* subtract | add (b) */
r6=r0 -|+ r1(s) ; /* same as above, subtract|add with saturation */
r0=r1 -|+ r2 ;
r3=r4 -|+ r5 ;
r6=r7 -|+ r0 ;
r1=r2 -|+ r3 ;
r4=r3 -|+ r5 ;
r6=r3 -|+ r7 ;
r0=r1 -|+ r2 (S);
r3=r4 -|+ r5 (S);
r6=r7 -|+ r0 (S);
r1=r2 -|+ r3 (S);
r4=r3 -|+ r5 (S);
r6=r3 -|+ r7 (S);
r0=r1 -|+ r2 (CO);
r3=r4 -|+ r5 (CO);
r6=r7 -|+ r0 (CO) ;
r1=r2 -|+ r3 (CO);
r4=r3 -|+ r5 (CO);
r6=r3 -|+ r7 (CO);
r0=r1 -|+ r2 (SCO);
r3=r4 -|+ r5 (SCO);
r6=r7 -|+ r0 (SCO);
r1=r2 -|+ r3 (SCO);
r4=r3 -|+ r5 (SCO);
r6=r3 -|+ r7 (SCO);
//Dreg = Dreg +|- Dreg (opt_mode_0) ; /* add | subtract (b) */
r0=r2 +|- r1(co) ; /* add|subtract with half-word results crossed over in the destination register */
r0=r1 +|- r2 ;
r3=r4 +|- r5 ;
r6=r7 +|- r0 ;
r1=r2 +|- r3 ;
r4=r3 +|- r5 ;
r6=r3 +|- r7 ;
r0=r1 +|- r2 (S);
r3=r4 +|- r5 (S);
r6=r7 +|- r0 (S);
r1=r2 +|- r3 (S);
r4=r3 +|- r5 (S);
r6=r3 +|- r7 (S);
r0=r1 +|- r2 (CO);
r3=r4 +|- r5 (CO);
r6=r7 +|- r0 (CO) ;
r1=r2 +|- r3 (CO);
r4=r3 +|- r5 (CO);
r6=r3 +|- r7 (CO);
r0=r1 +|- r2 (SCO);
r3=r4 +|- r5 (SCO);
r6=r7 +|- r0 (SCO);
r1=r2 +|- r3 (SCO);
r4=r3 +|- r5 (SCO);
r6=r3 +|- r7 (SCO);
//Dreg = Dreg -|- Dreg (opt_mode_0) ; /* subtract | subtract (b) */
r7=r3 -|- r6(sco) ; /* subtract|subtract with saturation and half-word results crossed over in the destination register */
r0=r1 -|- r2 ;
r3=r4 -|- r5 ;
r6=r7 -|- r0 ;
r1=r2 -|- r3 ;
r4=r3 -|- r5 ;
r6=r3 -|- r7 ;
r0=r1 -|- r2 (S);
r3=r4 -|- r5 (S);
r6=r7 -|- r0 (S);
r1=r2 -|- r3 (S);
r4=r3 -|- r5 (S);
r6=r3 -|- r7 (S);
r0=r1 -|- r2 (CO);
r3=r4 -|- r5 (CO);
r6=r7 -|- r0 (CO) ;
r1=r2 -|- r3 (CO);
r4=r3 -|- r5 (CO);
r6=r3 -|- r7 (CO);
r0=r1 -|- r2 (SCO);
r3=r4 -|- r5 (SCO);
r6=r7 -|- r0 (SCO);
r1=r2 -|- r3 (SCO);
r4=r3 -|- r5 (SCO);
r6=r3 -|- r7 (SCO);
//Quad 16-Bit Operations
//Dreg = Dreg +|+ Dreg, Dreg = Dreg -|- Dreg (opt_mode_0,opt_mode_2) ; /* add | add, subtract | subtract; the set of source registers must be the same for each operation (b) */
r5=r3 +|+ r4, r7=r3-|-r4 ; /* quad 16-bit operations, add|add, subtract|subtract */
r0=r1 +|+ r2, r7=r1 -|- r2;
r3=r4 +|+ r5, r6=r4 -|- r5;
r6=r7 +|+ r0, r5=r7 -|- r0;
r1=r2 +|+ r3, r4=r2 -|- r3;
r4=r3 +|+ r5, r3=r3 -|- r5;
r6=r3 +|+ r7, r2=r3 -|- r7;
r0=r1 +|+ r2, r7=r1 -|- r2(S);
r3=r4 +|+ r5, r6=r4 -|- r5(S);
r6=r7 +|+ r0, r5=r7 -|- r0(S);
r1=r2 +|+ r3, r4=r2 -|- r3(S);
r4=r3 +|+ r5, r3=r3 -|- r5(S);
r6=r3 +|+ r7, r2=r3 -|- r7(S);
r0=r1 +|+ r2, r7=r1 -|- r2(CO);
r3=r4 +|+ r5, r6=r4 -|- r5(CO);
r6=r7 +|+ r0, r5=r7 -|- r0(CO);
r1=r2 +|+ r3, r4=r2 -|- r3(CO);
r4=r3 +|+ r5, r3=r3 -|- r5(CO);
r6=r3 +|+ r7, r2=r3 -|- r7(CO);
r0=r1 +|+ r2, r7=r1 -|- r2(SCO);
r3=r4 +|+ r5, r6=r4 -|- r5(SCO);
r6=r7 +|+ r0, r5=r7 -|- r0(SCO);
r1=r2 +|+ r3, r4=r2 -|- r3(SCO);
r4=r3 +|+ r5, r3=r3 -|- r5(SCO);
r6=r3 +|+ r7, r2=r3 -|- r7(SCO);
r0=r1 +|+ r2, r7=r1 -|- r2(ASR);
r3=r4 +|+ r5, r6=r4 -|- r5(ASR);
r6=r7 +|+ r0, r5=r7 -|- r0(ASR);
r1=r2 +|+ r3, r4=r2 -|- r3(ASR);
r4=r3 +|+ r5, r3=r3 -|- r5(ASR);
r6=r3 +|+ r7, r2=r3 -|- r7(ASR);
r0=r1 +|+ r2, r7=r1 -|- r2(ASL);
r3=r4 +|+ r5, r6=r4 -|- r5(ASL);
r6=r7 +|+ r0, r5=r7 -|- r0(ASL);
r1=r2 +|+ r3, r4=r2 -|- r3(ASL);
r4=r3 +|+ r5, r3=r3 -|- r5(ASL);
r6=r3 +|+ r7, r2=r3 -|- r7(ASL);
r0=r1 +|+ r2, r7=r1 -|- r2(S,ASR);
r3=r4 +|+ r5, r6=r4 -|- r5(S,ASR);
r6=r7 +|+ r0, r5=r7 -|- r0(S,ASR);
r1=r2 +|+ r3, r4=r2 -|- r3(S,ASR);
r4=r3 +|+ r5, r3=r3 -|- r5(S,ASR);
r6=r3 +|+ r7, r2=r3 -|- r7(S,ASR);
r0=r1 +|+ r2, r7=r1 -|- r2(CO,ASR);
r3=r4 +|+ r5, r6=r4 -|- r5(CO,ASR);
r6=r7 +|+ r0, r5=r7 -|- r0(CO,ASR);
r1=r2 +|+ r3, r4=r2 -|- r3(CO,ASR);
r4=r3 +|+ r5, r3=r3 -|- r5(CO,ASR);
r6=r3 +|+ r7, r2=r3 -|- r7(CO,ASR);
r0=r1 +|+ r2, r7=r1 -|- r2(SCO,ASR);
r3=r4 +|+ r5, r6=r4 -|- r5(SCO,ASR);
r6=r7 +|+ r0, r5=r7 -|- r0(SCO,ASR);
r1=r2 +|+ r3, r4=r2 -|- r3(SCO,ASR);
r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASR);
r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASR);
r0=r1 +|+ r2, r7=r1 -|- r2(S,ASL);
r3=r4 +|+ r5, r6=r4 -|- r5(S,ASL);
r6=r7 +|+ r0, r5=r7 -|- r0(S,ASL);
r1=r2 +|+ r3, r4=r2 -|- r3(S,ASL);
r4=r3 +|+ r5, r3=r3 -|- r5(S,ASL);
r6=r3 +|+ r7, r2=r3 -|- r7(S,ASL);
r0=r1 +|+ r2, r7=r1 -|- r2(CO,ASL);
r3=r4 +|+ r5, r6=r4 -|- r5(CO,ASL);
r6=r7 +|+ r0, r5=r7 -|- r0(CO,ASL);
r1=r2 +|+ r3, r4=r2 -|- r3(CO,ASL);
r4=r3 +|+ r5, r3=r3 -|- r5(CO,ASL);
r6=r3 +|+ r7, r2=r3 -|- r7(CO,ASL);
r0=r1 +|+ r2, r7=r1 -|- r2(SCO,ASL);
r3=r4 +|+ r5, r6=r4 -|- r5(SCO,ASL);
r6=r7 +|+ r0, r5=r7 -|- r0(SCO,ASL);
r1=r2 +|+ r3, r4=r2 -|- r3(SCO,ASL);
r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASL);
r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASL);
//Dreg = Dreg +|- Dreg, Dreg = Dreg -|+ Dreg (opt_mode_0,opt_mode_2) ; /* add | subtract, subtract | add; the set of source registers must be the same for each operation (b) */
r5=r3 +|- r4, r7=r3 -|+ r4 ; /* quad 16-bit operations, add|subtract, subtract|add */
r0=r1 +|- r2, r7=r1 -|+ r2;
r3=r4 +|- r5, r6=r4 -|+ r5;
r6=r7 +|- r0, r5=r7 -|+ r0;
r1=r2 +|- r3, r4=r2 -|+ r3;
r4=r3 +|- r5, r3=r3 -|+ r5;
r6=r3 +|- r7, r2=r3 -|+ r7;
r0=r1 +|- r2, r7=r1 -|+ r2(S);
r3=r4 +|- r5, r6=r4 -|+ r5(S);
r6=r7 +|- r0, r5=r7 -|+ r0(S);
r1=r2 +|- r3, r4=r2 -|+ r3(S);
r4=r3 +|- r5, r3=r3 -|+ r5(S);
r6=r3 +|- r7, r2=r3 -|+ r7(S);
r0=r1 +|- r2, r7=r1 -|+ r2(CO);
r3=r4 +|- r5, r6=r4 -|+ r5(CO);
r6=r7 +|- r0, r5=r7 -|+ r0(CO);
r1=r2 +|- r3, r4=r2 -|+ r3(CO);
r4=r3 +|- r5, r3=r3 -|+ r5(CO);
r6=r3 +|- r7, r2=r3 -|+ r7(CO);
r0=r1 +|- r2, r7=r1 -|+ r2(SCO);
r3=r4 +|- r5, r6=r4 -|+ r5(SCO);
r6=r7 +|- r0, r5=r7 -|+ r0(SCO);
r1=r2 +|- r3, r4=r2 -|+ r3(SCO);
r4=r3 +|- r5, r3=r3 -|+ r5(SCO);
r6=r3 +|- r7, r2=r3 -|+ r7(SCO);
r0=r1 +|- r2, r7=r1 -|+ r2(ASR);
r3=r4 +|- r5, r6=r4 -|+ r5(ASR);
r6=r7 +|- r0, r5=r7 -|+ r0(ASR);
r1=r2 +|- r3, r4=r2 -|+ r3(ASR);
r4=r3 +|- r5, r3=r3 -|+ r5(ASR);
r6=r3 +|- r7, r2=r3 -|+ r7(ASR);
r0=r1 +|- r2, r7=r1 -|+ r2(ASL);
r3=r4 +|- r5, r6=r4 -|+ r5(ASL);
r6=r7 +|- r0, r5=r7 -|+ r0(ASL);
r1=r2 +|- r3, r4=r2 -|+ r3(ASL);
r4=r3 +|- r5, r3=r3 -|+ r5(ASL);
r6=r3 +|- r7, r2=r3 -|+ r7(ASL);
r0=r1 +|- r2, r7=r1 -|+ r2(S,ASR);
r3=r4 +|- r5, r6=r4 -|+ r5(S,ASR);
r6=r7 +|- r0, r5=r7 -|+ r0(S,ASR);
r1=r2 +|- r3, r4=r2 -|+ r3(S,ASR);
r4=r3 +|- r5, r3=r3 -|+ r5(S,ASR);
r6=r3 +|- r7, r2=r3 -|+ r7(S,ASR);
r0=r1 +|- r2, r7=r1 -|+ r2(CO,ASR);
r3=r4 +|- r5, r6=r4 -|+ r5(CO,ASR);
r6=r7 +|- r0, r5=r7 -|+ r0(CO,ASR);
r1=r2 +|- r3, r4=r2 -|+ r3(CO,ASR);
r4=r3 +|- r5, r3=r3 -|+ r5(CO,ASR);
r6=r3 +|- r7, r2=r3 -|+ r7(CO,ASR);
r0=r1 +|- r2, r7=r1 -|+ r2(SCO,ASR);
r3=r4 +|- r5, r6=r4 -|+ r5(SCO,ASR);
r6=r7 +|- r0, r5=r7 -|+ r0(SCO,ASR);
r1=r2 +|- r3, r4=r2 -|+ r3(SCO,ASR);
r4=r3 +|- r5, r3=r3 -|+ r5(SCO,ASR);
r6=r3 +|- r7, r2=r3 -|+ r7(SCO,ASR);
r0=r1 +|- r2, r7=r1 -|+ r2(S,ASL);
r3=r4 +|- r5, r6=r4 -|+ r5(S,ASL);
r6=r7 +|- r0, r5=r7 -|+ r0(S,ASL);
r1=r2 +|- r3, r4=r2 -|+ r3(S,ASL);
r4=r3 +|- r5, r3=r3 -|+ r5(S,ASL);
r6=r3 +|- r7, r2=r3 -|+ r7(S,ASL);
r0=r1 +|- r2, r7=r1 -|+ r2(CO,ASL);
r3=r4 +|- r5, r6=r4 -|+ r5(CO,ASL);
r6=r7 +|- r0, r5=r7 -|+ r0(CO,ASL);
r1=r2 +|- r3, r4=r2 -|+ r3(CO,ASL);
r4=r3 +|- r5, r3=r3 -|+ r5(CO,ASL);
r6=r3 +|- r7, r2=r3 -|+ r7(CO,ASL);
r0=r1 +|- r2, r7=r1 -|+ r2(SCO,ASL);
r3=r4 +|- r5, r6=r4 -|+ r5(SCO,ASL);
r6=r7 +|- r0, r5=r7 -|+ r0(SCO,ASL);
r1=r2 +|- r3, r4=r2 -|+ r3(SCO,ASL);
r4=r3 +|- r5, r3=r3 -|+ r5(SCO,ASL);
r6=r3 +|- r7, r2=r3 -|+ r7(SCO,ASL);
//Dual 32-Bit Operations
//Dreg = Dreg + Dreg, Dreg = Dreg - Dreg (opt_mode_1) ; /* add, subtract; the set of source registers must be the same for each operation (b) */
r2=r0+r1, r3=r0-r1 ; /* 32-bit operations */
r7=r0+r1, r0=r0-r1 ; /* 32-bit operations */
r6=r1+r2, r1=r1-r2 ; /* 32-bit operations */
r5=r2+r3, r2=r2-r3 ; /* 32-bit operations */
r4=r3+r4, r3=r3-r4 ; /* 32-bit operations */
r3=r4+r5, r4=r4-r5 ; /* 32-bit operations */
r2=r5+r6, r5=r5-r6 ; /* 32-bit operations */
r1=r6+r7, r6=r6-r7 ; /* 32-bit operations */
r0=r7+r0, r7=r7-r0 ; /* 32-bit operations */
r2=r0+r1, r3=r0-r1(s) ; /* dual 32-bit operations with saturation */
r7=r0+r1, r0=r0-r1 (s); /* 32-bit operations */
r6=r1+r2, r1=r1-r2 (s); /* 32-bit operations */
r5=r2+r3, r2=r2-r3 (s); /* 32-bit operations */
r4=r3+r4, r3=r3-r4(s) ; /* 32-bit operations */
r3=r4+r5, r4=r4-r5 (s); /* 32-bit operations */
r2=r5+r6, r5=r5-r6 (s); /* 32-bit operations */
r1=r6+r7, r6=r6-r7 (s); /* 32-bit operations */
r0=r7+r0, r7=r7-r0 (s); /* 32-bit operations */
//Dual 40-Bit Accumulator Operations
//Dreg = A1 + A0, Dreg = A1 - A0 (opt_mode_1) ; /* add, subtract Accumulators; subtract A0 from A1 (b) */
r0=a1+a0, r1=a1-a0 ;
r2=a1+a0, r3=a1-a0 ;
r4=a1+a0, r5=a1-a0 ;
r6=a1+a0, r7=a1-a0 ;
r1=a1+a0, r0=a1-a0 ;
r3=a1+a0, r2=a1-a0 ;
r5=a1+a0, r4=a1-a0 ;
r0=a1+a0, r1=a1-a0 (s);
r2=a1+a0, r3=a1-a0 (s);
r4=a1+a0, r5=a1-a0 (s);
r6=a1+a0, r7=a1-a0 (s);
r1=a1+a0, r0=a1-a0 (s);
r3=a1+a0, r2=a1-a0 (s);
r5=a1+a0, r4=a1-a0 (s);
//Dreg = A0 + A1, Dreg = A0 - A1 (opt_mode_1) ; /* add, subtract Accumulators; subtract A1 from A0 (b) */
r4=a0+a1, r6=a0-a1(s);
r0=a0+a1, r1=a0-a1 ;
r2=a0+a1, r3=a0-a1 ;
r4=a0+a1, r5=a0-a1 ;
r6=a0+a1, r7=a0-a1 ;
r1=a0+a1, r0=a0-a1 ;
r3=a0+a1, r2=a0-a1 ;
r5=a0+a1, r4=a0-a1 ;
r0=a0+a1, r1=a0-a1 (s);
r2=a0+a1, r3=a0-a1 (s);
r4=a0+a1, r5=a0-a1 (s);
r6=a0+a1, r7=a0-a1 (s);
r1=a0+a1, r0=a0-a1 (s);
r3=a0+a1, r2=a0-a1 (s);
r5=a0+a1, r4=a0-a1 (s);
//Constant Shift Magnitude
//Dreg = Dreg >>> uimm4 (V) ; /* arithmetic shift right, immediate (b) */
R0 = R0 >>> 5(V);
R0 = R1 >>> 5(V);
R2 = R3 >>> 5(V);
R4 = R5 >>> 5(V);
R6 = R7 >>> 5(V);
R1 = R0 >>> 5(V);
R3 = R2 >>> 5(V);
R5 = R4 >>> 5(V);
R7 = R6 >>> 5(V);
//Dreg = Dreg << uimm4 (V,S) ; /* arithmetic shift left, immediate with saturation (b) */
R0 = R1 << 5(V,S);
R2 = R3 << 5(V,S);
R4 = R5 << 5(V,S);
R6 = R7 << 5(V,S);
R1 = R0 << 5(V,S);
R3 = R2 << 5(V,S);
R5 = R4 << 5(V,S);
R7 = R6 << 5(V,S);
//Registered Shift Magnitude
//Dreg = ASHIFT Dreg BY Dreg_lo (V) ; /* arithmetic shift (b) */
r2=ashift r7 by r5.l (v) ;
R0 = ASHIFT R1 BY R2.L (V);
R3 = ASHIFT R4 BY R5.L (V);
R6 = ASHIFT R7 BY R0.L (V);
R1 = ASHIFT R2 BY R3.L (V);
R4 = ASHIFT R5 BY R6.L (V);
R7 = ASHIFT R0 BY R1.L (V);
R2 = ASHIFT R3 BY R4.L (V);
R5 = ASHIFT R6 BY R7.L (V);
//Dreg = ASHIFT Dreg BY Dreg_lo (V, S) ; /* arithmetic shift with saturation (b) */
R0 = ASHIFT R1 BY R2.L (V,S);
R3 = ASHIFT R4 BY R5.L (V,S);
R6 = ASHIFT R7 BY R0.L (V,S);
R1 = ASHIFT R2 BY R3.L (V,S);
R4 = ASHIFT R5 BY R6.L (V,S);
R7 = ASHIFT R0 BY R1.L (V,S);
R2 = ASHIFT R3 BY R4.L (V,S);
R5 = ASHIFT R6 BY R7.L (V,S);
//Constant Shift Magnitude
//Dreg = Dreg >> uimm4 (V) ; /* logical shift right, immediate (b) */
R0 = R1 >> 5(V);
R2 = R3 >> 5(V);
R4 = R5 >> 5(V);
R6 = R7 >> 5(V);
R1 = R0 >> 5(V);
R3 = R2 >> 5(V);
R5 = R4 >> 5(V);
R7 = R6 >> 5(V);
//Dreg = Dreg << uimm4 (V) ; /* logical shift left, immediate (b) */
R0 = R1 << 5(V);
R2 = R3 << 5(V);
R4 = R5 << 5(V);
R6 = R7 << 5(V);
R1 = R0 << 5(V);
R3 = R2 << 5(V);
R5 = R4 << 5(V);
R7 = R6 << 5(V);
//Registered Shift Magnitude
//Dreg = LSHIFT Dreg BY Dreg_lo (V) ; /* logical shift (b) */
R0 = LSHIFT R1 BY R2.L (V);
R3 = LSHIFT R4 BY R5.L (V);
R6 = LSHIFT R7 BY R0.L (V);
R1 = LSHIFT R2 BY R3.L (V);
R4 = LSHIFT R5 BY R6.L (V);
R7 = LSHIFT R0 BY R1.L (V);
R2 = LSHIFT R3 BY R4.L (V);
R5 = LSHIFT R6 BY R7.L (V);
//Dreg = MAX ( Dreg , Dreg ) (V) ; /* dual 16-bit operations (b) */
r7 = max (r1, r0) (v) ;
R0 = MAX (R1, R2) (V);
R3 = MAX (R4, R5) (V);
R6 = MAX (R7, R0) (V);
R1 = MAX (R2, R3) (V);
R4 = MAX (R5, R6) (V);
R7 = MAX (R0, R1) (V);
R2 = MAX (R3, R4) (V);
R5 = MAX (R6, R7) (V);
//Dreg = MIN ( Dreg , Dreg ) (V) ; /* dual 16-bit operation (b) */
R0 = MIN (R1, R2) (V);
R3 = MIN (R4, R5) (V);
R6 = MIN (R7, R0) (V);
R1 = MIN (R2, R3) (V);
R4 = MIN (R5, R6) (V);
R7 = MIN (R0, R1) (V);
R2 = MIN (R3, R4) (V);
R5 = MIN (R6, R7) (V);
r2.h=r7.l*r6.h, r2.l=r7.h*r6.h ;
/* simultaneous MAC0 and MAC1 execution, 16-bit results. Both
results are signed fractions. */
r4.l=r1.l*r0.l, r4.h=r1.h*r0.h ;
/* same as above. MAC order is arbitrary. */
r0.h=r3.h*r2.l (m), r0.l=r3.l*r2.l ;
a1=r2.l*r3.h, a0=r2.h*r3.h ;
/* both multiply signed fractions into separate Accumulators */
a0=r1.l*r0.l, a1+=r1.h*r0.h ;
/* same as above, but sum result into A1. MAC order is arbitrary.
*/
a1+=r3.h*r3.l, a0-=r3.h*r3.h ;
/* sum product into A1, subtract product from A0 */
a1=r3.h*r2.l (m), a0+=r3.l*r2.l ;
/* MAC1 multiplies a signed fraction in r3.h by an unsigned fraction
in r2.l. MAC0 multiplies two signed fractions. */
a1=r7.h*r4.h (m), a0+=r7.l*r4.l (fu) ;
/* MAC1 multiplies signed fraction by unsigned fraction. MAC0
multiplies and accumulates two unsigned fractions. */
a1+=r3.h*r2.h, a0=r3.l*r2.l (is) ;
/* both MACs perform signed integer multiplication */
a1=r6.h*r7.h, a0+=r6.l*r7.l (w32) ;
/* both MACs multiply signed fractions, sign extended, and saturate
both Accumulators at bit 31 */
r2.h=(a1=r7.l*r6.h), r2.l=(a0=r7.h*r6.h) ; /* simultaneous MAC0
and MAC1 execution, both are signed fractions, both products load
into the Accumulators,MAC1 into half-word registers. */
r4.l=(a0=r1.l*r0.l), r4.h=(a1+=r1.h*r0.h) ; /* same as above,
but sum result into A1. ; MAC order is arbitrary. */
r7.h=(a1+=r6.h*r5.l), r7.l=(a0=r6.h*r5.h) ; /* sum into A1,
subtract into A0 */
r0.h=(a1=r7.h*r4.l) (m), r0.l=(a0+=r7.l*r4.l) ; /* MAC1 multiplies
a signed fraction by an unsigned fraction. MAC0 multiplies
two signed fractions. */
r5.h=(a1=r3.h*r2.h) (m), r5.l=(a0+=r3.l*r2.l) (fu) ; /* MAC1
multiplies signed fraction by unsigned fraction. MAC0 multiplies
two unsigned fractions. */
r0.h=(a1+=r3.h*r2.h), r0.l=(a0=r3.l*r2.l) (is) ; /* both MACs
perform signed integer multiplication. */
r5.h=(a1=r2.h*r1.h), a0+=r2.l*r1.l ; /* both MACs multiply
signed fractions. MAC0 does not copy the accum result. */
r3.h=(a1=r2.h*r1.h) (m), a0=r2.l*r1.l ; /* MAC1 multiplies
signed fraction by unsigned fraction and uses all 40 bits of A1.
MAC0 multiplies two signed fractions. */
r3.h=a1, r3.l=(a0+=r0.l*r1.l) (s2rnd) ; /* MAC1 copies Accumulator
to register half. MAC0 multiplies signed fractions. Both
scale the result and round on the way to the destination register.
*/
r0.l=(a0+=r7.l*r6.l), r0.h=(a1+=r7.h*r6.h) (iss2) ; /* both
MACs process signed integer the way to the destination half-registers.
*/
r3=(a1=r6.h*r7.h), r2=(a0=r6.l*r7.l) ; /* simultaneous MAC0 and
MAC1 execution, both are signed fractions, both products load
into the Accumulators */
r4=(a0=r6.l*r7.l), r5=(a1+=r6.h*r7.h) ; /* same as above, but
sum result into A1. MAC order is arbitrary. */
r7=(a1+=r3.h*r5.h), r6=(a0-=r3.l*r5.l) ; /* sum into A1, subtract
into A0 */
r1=(a1=r7.l*r4.l) (m), r0=(a0+=r7.h*r4.h) ; /* MAC1 multiplies
a signed fraction by an unsigned fraction. MAC0 multiplies two
signed fractions. */
r5=(a1=r3.h*r7.h) (m), r4=(a0+=r3.l*r7.l) (fu) ; /* MAC1 multiplies
signed fraction by unsigned fraction. MAC0 multiplies two
unsigned fractions. */
r1=(a1+=r3.h*r2.h), r0=(a0=r3.l*r2.l) (is) ; /* both MACs perform
signed integer multiplication */
r5=(a1-=r6.h*r7.h), a0+=r6.l*r7.l ; /* both MACs multiply
signed fractions. MAC0 does not copy the accum result */
r3=(a1=r6.h*r7.h) (m), a0-=r6.l*r7.l ; /* MAC1 multiplies
signed fraction by unsigned fraction and uses all 40 bits of A1.
MAC0 multiplies two signed fractions. */
r3=a1, r2=(a0+=r0.l*r1.l) (s2rnd) ; /* MAC1 moves Accumulator
to register. MAC0 multiplies signed fractions. Both scale the
result and round on the way to the destination register. */
r0=(a0+=r7.l*r6.l), r1=(a1+=r7.h*r6.h) (iss2) ; /* both MACs
process signed integer operands and scale the result on the way
to the destination registers. */
r5 =-r3 (v) ; /* R5.H becomes the negative of R3.H and R5.L
becomes the negative of R3.L If r3 = 0x0004 7FFF the result is r5
= 0xFFFC 8001 */
r3=pack(r4.l, r5.l) ; /* pack low / low half-words */
r1=pack(r6.l, r4.h) ; /* pack low / high half-words */
r0=pack(r2.h, r4.l) ; /* pack high / low half-words */
r5=pack(r7.h, r2.h) ; /* pack high / high half-words */
(r1,r0) = SEARCH R2 (LE) || R2=[P0++];
/* search for the last minimum in all but the
last element of the array */
(r1,r0) = SEARCH R2 (LE);
saa (r1:0, r3:2) || r0=[i0++] || r2=[i1++] ;
saa (r1:0, r3:2)(r) || r1=[i0++] || r3=[i1++] ;
mnop || r1 = [i0++] || r3 = [i1++] ;
r7.h=r7.l=sign(r2.h)*r3.h + sign(r2.l)*r3.l || i0+=m3 || r0=[i0]
;
/* Add/subtract two vector values while incrementing an Ireg and
loading a data register. */
R2 = R2 +|+ R4, R4 = R2 -|- R4 (ASR) || I0 += M0 (BREV) || R1 = [I0] ;
/* Multiply and accumulate to Accumulator while loading a data
register and storing a data register using an Ireg pointer. */
A1=R2.L*R1.L, A0=R2.H*R1.H || R2.H=W[I2++] || [I3++]=R3 ;
/* Multiply and accumulate while loading two data registers. One
load uses an Ireg pointer. */
A1+=R0.L*R2.H,A0+=R0.L*R2.L || R2.L=W[I2++] || R0=[I1--] ;
R3.H=(A1+=R0.L*R1.H), R3.L=(A0+=R0.L*R1.L) || R0=[P0++] || R1=[I0] ;
/* Pack two vector values while storing a data register using an
Ireg pointer and loading another data register. */
R1=PACK(R1.H,R0.H) || [I0++]=R0 || R2.L=W[I2++] ;
/* Multiply-Accumulate to a Data register while incrementing an
Ireg. */
r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 ;
/* which the assembler expands into:
r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 || nop ; */
/* Test for ensure (m) is not thown away. */
r0.l=r3.l*r2.l, r0.h=r3.h*r2.l (m) ;
R2 = R7.L * R0.L, R3 = R7.L * R0.H (m);
R2 = (A0 = R7.L * R0.L), R3 = ( A1 = R7.L * R0.H) (m);
/* Both scalar instructions must share the same mode option. */
R0.H = (A1 = R4.L * R3.L), A0 = R4.H * R3.L (T);
R0.H = (A1 = R4.L * R3.L) (M), A0 = R4.H * R3.L (T);
A0 = R4.H * R3.L, R0.H = (A1 = R4.L * R3.L) (T);
A0 = R4.H * R3.L, R0.H = (A1 = R4.L * R3.L) (T,M);
A1 += R7.H * R4.H, R0.L = (A0 = R7.L * R4.H) (T);
|
tactcomplabs/xbgas-binutils-gdb
| 2,513
|
gas/testsuite/gas/bfin/expected_errors.s
|
.text
p0.H = 0x12345678;
P0.l = 0x12345678;
CC = R3 < 4;
CC = R3 < 7;
CC = R3 < 8;
CC = R3 <= 4;
CC = R3 <= 7;
CC = R3 <= 8;
A1 -= M2.h * R3.L, A0 -= M2.l * R3.L;
R1.H = (A1=R7.L*R5.L) , A0 += R1.L*R0.L (IS);
a0 += R2.L * R3.L (IU);
a0 += R2.L * R3.L (T);
a0 += R2.L * R3.L (TFU);
a0 += R2.L * R3.L (S2RND);
a0 += R2.L * R3.L (ISS2);
a0 += R2.L * R3.L (IH);
R0.H = (A1 = R4.L * R3.L) (T), A0 = R4.H * R3.L;
R0.L = (A0 = R7.L * R4.H) (T), A1 += R7.H * R4.H;
R0 = (A1 += R1.H * R3.H) (IU)
R0.L = (A1 += R1.H * R3.H) (IU)
R1 = (A0 += R1.H * R3.H) (IU)
R1.H = (A0 += R1.H * R3.H) (IU)
W [p0 + 1] = r0;
[p0 + 1] = r0;
[p0 + 2] = r0;
[p0 + 3] = r0;
B [p0 + 32768] = r0;
W [p0 + 65536] = r0;
[p0 + 131072] = r0;
B [p0 + -32769] = r0;
W [p0 + -65538] = r0;
[p0 + -131076] = r0;
r0 = W [p0 + 1] (x);
r0 = [p0 + 1];
r0 = [p0 + 2];
r0 = [p0 + 3];
r0 = [p0 + foo];
r0 = W [p0 + foo];
r0 = B [p0 + foo];
r0 = [p0 + 131076];
r0 = W [p0 + 65536];
r0 = B [p0 + 131076];
[ R0 ++ M2 ] = R2;
[ I0 ++ R2 ] = R2;
[ R0 ++ P2 ] = R2;
[ P0 ++ R2 ] = R2;
[ P0 ++ M2 ] = R2;
[ I0 ++ P2 ] = R2;
W [ R0 ++ M2 ] = R2.h;
W [ I0 ++ R2 ] = R2.h;
W [ R0 ++ P2 ] = R2.h;
W [ P0 ++ R2 ] = R2.h;
W [ P0 ++ M2 ] = R2.h;
W [ I0 ++ P2 ] = R2.h;
[ R0 ++ ] = R2;
[ I0 ++ ] = P2;
W [ R0 ++ ] = R2.h;
W [ I0 ++ ] = P2.h;
W [ R0 ++ ] = R2;
W [ I0 ++ ] = R2;
W [ P0 ++ ] = P2;
B [ R0 ++ ] = R2;
B [ I0 ++ ] = R2;
B [ P0 ++ ] = P2;
R2 = [ R0 ++ M2 ];
R2 = [ I0 ++ R2 ];
R2 = [ R0 ++ P2 ];
R2 = [ P0 ++ R2 ];
R2 = [ P0 ++ M2 ];
R2 = [ I0 ++ P2 ];
R2.h = W [ R0 ++ M2 ];
R2.h = W [ I0 ++ R2 ];
R2.h = W [ R0 ++ P2 ];
R2.h = W [ P0 ++ R2 ];
R2.h = W [ P0 ++ M2 ];
R2.h = W [ I0 ++ P2 ];
R2 = [ R0 ++ ];
P2 = [ I0 ++ ];
R0.l = B [ P0 ++ ];
R0.l = B [ I0 ++ ];
R0.l = W [ P0 ++ ];
R2.h = W [ R0 ++ ];
P2.h = W [ I0 ++ ];
R2 = W [ R0 ++ ] (X);
R2 = W [ I0 ++ ] (X);
P2 = W [ P0 ++ ] (X);
R2 = B [ R0 ++ ] (X);
R2 = B [ I0 ++ ] (X);
P2 = B [ P0 ++ ] (X);
(R3, R3) = SEARCH R0 (GE);
BITMUX (R4, R4, A0) (ASR);
R0 = A0, R3 = A1;
R0.L = A0, R1.H = A1;
R0 = A0, R1.H = A1;
R0 = R1 +|+ R2, R0 = R1 -|- R2;
R0 = R4 +|+ R5, R1 = R6 -|- R7;
R1 = R3 +|- R7, R1 = R3 -|+ R7;
R7 = R3 +|- R4, R1 = R1 -|+ R2;
R0 = R3 + R4, R1 = R5 - R6;
R7 = A1.L + A1.H, R7 = A0.L + A0.H;
(R0, R0) = BYTEOP16P (R1:0, R3:2);
(R7, R7) = BYTEOP16P (R1:0, R3:2);
(R1, R1) = BYTEOP16M (R1:0, R3:2);
(R4, R4) = BYTEOP16M (R1:0, R3:2);
(R5, R5) = BYTEUNPACK R3:2;
|
tactcomplabs/xbgas-binutils-gdb
| 7,136
|
gas/testsuite/gas/bfin/video2.s
|
.EXTERN MY_LABEL2;
.section .text;
//
//13 VIDEO PIXEL OPERATIONS
//
//Dreg = ALIGN8 ( Dreg, Dreg ) ; /* overlay 1 byte (b) */
R0 = ALIGN8(R0, R0);
R0 = ALIGN8(R0, R1);
R0 = ALIGN8(R1, R0);
R0 = ALIGN8(R1, R1);
R0 = ALIGN8(R1, R2);
R3 = ALIGN8(R4, R5);
R6 = ALIGN8(R7, R0);
R1 = ALIGN8(R2, R3);
R4 = ALIGN8(R5, R6);
R7 = ALIGN8(R0, R1);
R2 = ALIGN8(R3, R4);
R5 = ALIGN8(R6, R7);
//Dreg = ALIGN16 ( Dreg, Dreg ) ; /* overlay 2 bytes (b) */
R0 = ALIGN16(R0, R0);
R0 = ALIGN16(R0, R1);
R0 = ALIGN16(R1, R0);
R0 = ALIGN16(R1, R1);
R0 = ALIGN16(R1, R2);
R3 = ALIGN16(R4, R5);
R6 = ALIGN16(R7, R0);
R1 = ALIGN16(R2, R3);
R4 = ALIGN16(R5, R6);
R7 = ALIGN16(R0, R1);
R2 = ALIGN16(R3, R4);
R5 = ALIGN16(R6, R7);
//Dreg = ALIGN24 ( Dreg, Dreg ) ; /* overlay 3 bytes (b) */
R0 = ALIGN24(R0, R0);
R0 = ALIGN24(R0, R1);
R0 = ALIGN24(R1, R0);
R0 = ALIGN24(R1, R1);
R0 = ALIGN24(R1, R2);
R3 = ALIGN24(R4, R5);
R6 = ALIGN24(R7, R0);
R1 = ALIGN24(R2, R3);
R4 = ALIGN24(R5, R6);
R7 = ALIGN24(R0, R1);
R2 = ALIGN24(R3, R4);
R5 = ALIGN24(R6, R7);
DISALGNEXCPT ; /* (b) */
/* forward byte order operands */
//Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (LO) ; /* sum into low bytes (b) */
//Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (HI) ; /* sum into high bytes (b) */
/* reverse byte order operands */
//Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (LO, R) ; /* sum into low bytes (b) */
//Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (HI, R) ; /* sum into high bytes (b) */
r0 = byteop3p (r1:0, r3:2) (lo) ;
r1 = byteop3p (r1:0, r3:2) (hi) ;
r2 = byteop3p (r1:0, r3:2) (lo, r) ;
r3 = byteop3p (r1:0, r3:2) (hi, r) ;
r4 = byteop3p (r3:2, r1:0) (lo) ;
r5 = byteop3p (r3:2, r1:0) (hi) ;
r6 = byteop3p (r3:2, r1:0) (lo, r) ;
r7 = byteop3p (r3:2, r1:0) (hi, r) ;
//Dreg = A1.L + A1.H, Dreg = A0.L + A0.H ; /* (b) */
R0 = A1.L + A1.H, R1= A0.L + A0.H ;
R2 = A1.L + A1.H, R3= A0.L + A0.H ;
R4 = A1.L + A1.H, R5= A0.L + A0.H ;
R6 = A1.L + A1.H, R7= A0.L + A0.H ;
/* forward byte order operands */
//( Dreg, Dreg ) = BYTEOP16P ( Dreg_pair, Dreg_pair ) ; /* (b) */
(r7,r0) = BYTEOP16P ( r3:2,r1:0 ) ;
(r1,r2) = byteop16p (r3:2,r1:0) ;
(r0,r1) = BYTEOP16P ( r3:2,r1:0 ) ;
(r2,r3) = byteop16p (r3:2,r1:0) ;
(r7,r0) = BYTEOP16P (r1:0, r3:2) ;
(r1,r2) = byteop16p (r1:0,r3:2) ;
(r0,r1) = BYTEOP16P (r1:0, r3:2) ;
(r2,r3) = byteop16p (r1:0,r3:2) ;
/* reverse byte order operands */
//( Dreg, Dreg ) = BYTEOP16P ( Dreg_pair, Dreg_pair ) (R); /* (b) */
(r7,r0) = BYTEOP16P ( r3:2,r1:0 )(r) ;
(r1,r2) = byteop16p (r3:2,r1:0)(r) ;
(r0,r1) = BYTEOP16P ( r3:2,r1:0 )(r) ;
(r2,r3) = byteop16p (r3:2,r1:0)(r) ;
(r7,r0) = BYTEOP16P (r1:0, r3:2)(r) ;
(r1,r2) = byteop16p (r1:0,r3:2)(r) ;
(r0,r1) = BYTEOP16P (r1:0, r3:2)(r) ;
(r2,r3) = byteop16p (r1:0,r3:2)(r) ;
/* forward byte order operands */
//Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) ; /* (b) */
//Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (T) ; /* truncated (b)*/
/* reverse byte order operands */
//Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (R) ; /* (b) */
//Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (T, R) ; /* truncated (b) */
r3 = byteop1p (r1:0, r3:2) ;
r3 = byteop1p (r1:0, r3:2) (r) ;
r3 = byteop1p (r1:0, r3:2) (t) ;
r3 = byteop1p (r1:0, r3:2) (t,r) ;
r0 = byteop1p (r3:2,r1:0);
r1 = byteop1p (r3:2,r1:0)(r) ;
r2 = byteop1p (r3:2,r1:0)(t) ;
r3 = byteop1p (r3:2,r1:0)(t,r) ;
/* forward byte order operands */
//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDL) ;
/* round into low bytes (b) */
//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDH) ;
/* round into high bytes (b) */
//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TL) ;
/* truncate into low bytes (b) */
//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TH) ;
/* truncate into high bytes (b) */
/* reverse byte order operands */
//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDL, R) ;
/* round into low bytes (b) */
//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDH, R) ;
/* round into high bytes (b) */
//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TL, R) ;
/* truncate into low bytes (b) */
//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TH, R) ;
/* truncate into high bytes (b) */
r3 = byteop2p (r1:0, r3:2) (rndl) ;
r3 = byteop2p (r1:0, r3:2) (rndh) ;
r3 = byteop2p (r1:0, r3:2) (tl) ;
r3 = byteop2p (r1:0, r3:2) (th) ;
r3 = byteop2p (r1:0, r3:2) (rndl, r) ;
r3 = byteop2p (r1:0, r3:2) (rndh, r) ;
r3 = byteop2p (r1:0, r3:2) (tl, r) ;
r3 = byteop2p (r1:0, r3:2) (th, r) ;
r0 = byteop2p (r1:0, r3:2) (rndl) ;
r1 = byteop2p (r1:0, r3:2) (rndh) ;
r2 = byteop2p (r1:0, r3:2) (tl) ;
r3 = byteop2p (r1:0, r3:2) (th) ;
r4 = byteop2p (r1:0, r3:2) (rndl, r) ;
r5 = byteop2p (r1:0, r3:2) (rndh, r) ;
r6 = byteop2p (r1:0, r3:2) (tl, r) ;
r7 = byteop2p (r1:0, r3:2) (th, r) ;
r0 = byteop2p (r3:2, r3:2) (rndl) ;
r1 = byteop2p (r3:2, r3:2) (rndh) ;
r2 = byteop2p (r3:2, r3:2) (tl) ;
r3 = byteop2p (r3:2, r3:2) (th) ;
r4 = byteop2p (r3:2, r3:2) (rndl, r) ;
r5 = byteop2p (r3:2, r3:2) (rndh, r) ;
r6 = byteop2p (r3:2, r3:2) (tl, r) ;
r7 = byteop2p (r3:2, r3:2) (th, r) ;
//Dreg = BYTEPACK ( Dreg, Dreg ) ; /* (b) */
r0 = bytepack (r0,r0) ;
r1 = bytepack (r2,r3) ;
r4 = bytepack (r5,r6) ;
r7 = bytepack (r0,r1) ;
r2 = bytepack (r3,r4) ;
r5 = bytepack (r6,r7) ;
/* forward byte order operands */
//(Dreg, Dreg) = BYTEOP16M (Dreg_pair, Dreg_pair) ; /* (b */)
/* reverse byte order operands */
//(Dreg, Dreg) = BYTEOP16M (Dreg-pair, Dreg-pair) (R) ; /* (b) */
(r1,r2)= byteop16m (r3:2,r1:0) ;
(r1,r2)= byteop16m (r3:2,r1:0) (r) ;
(r0,r1)= byteop16m (r3:2,r1:0) ;
(r2,r3)= byteop16m (r3:2,r1:0) (r) ;
(r3,r5)= byteop16m (r3:2,r1:0) ;
(r6,r7)= byteop16m (r3:2,r1:0) (r) ;
(r1,r2)= byteop16m (r1:0,r1:0) ;
(r1,r2)= byteop16m (r1:0,r1:0) (r) ;
(r0,r1)= byteop16m (r1:0,r1:0) ;
(r2,r3)= byteop16m (r1:0,r1:0) (r) ;
(r3,r5)= byteop16m (r1:0,r1:0) ;
(r6,r7)= byteop16m (r1:0,r1:0) (r) ;
(r1,r2)= byteop16m (r1:0,r3:2) ;
(r1,r2)= byteop16m (r1:0,r3:2) (r) ;
(r0,r1)= byteop16m (r1:0,r3:2) ;
(r2,r3)= byteop16m (r1:0,r3:2) (r) ;
(r3,r5)= byteop16m (r1:0,r3:2) ;
(r6,r7)= byteop16m (r1:0,r3:2) (r) ;
(r1,r2)= byteop16m (r3:2,r3:2) ;
(r1,r2)= byteop16m (r3:2,r3:2) (r) ;
(r0,r1)= byteop16m (r3:2,r3:2) ;
(r2,r3)= byteop16m (r3:2,r3:2) (r) ;
(r3,r5)= byteop16m (r3:2,r3:2) ;
(r6,r7)= byteop16m (r3:2,r3:2) (r) ;
//SAA (Dreg_pair, Dreg_pair) ; /* forward byte order operands (b) */
//SAA (Dreg_pair, Dreg_pair) (R) ; /* reverse byte order operands (b) */
saa(r1:0, r3:2) || r0 = [i0++] || r2 = [i1++] ; /* parallel fill instructions */
saa (r1:0, r3:2) (R) || r1 = [i0++] || r3 = [i1++] ; /* reverse, parallel fill instructions */
saa (r1:0, r3:2) ; /* last SAA in a loop, no more fill required */
//( Dreg , Dreg ) = BYTEUNPACK Dreg_pair ; /* (b) */
//( Dreg , Dreg ) = BYTEUNPACK Dreg_pair (R) ; /* reverse source order (b) */
(r6,r5) = byteunpack r1:0 ; /* non-reversing sources */
(r6,r5) = byteunpack r1:0 (R) ; /* reversing sources case */
(r6,r5) = byteunpack r3:2 ; /* non-reversing sources */
(r6,r5) = byteunpack r3:2 (R) ; /* reversing sources case */
(r0,r1) = byteunpack r1:0 ; /* non-reversing sources */
(r2,r3) = byteunpack r1:0 (R) ; /* reversing sources case */
(r4,r5) = byteunpack r3:2 ; /* non-reversing sources */
(r6,r7) = byteunpack r3:2 (R) ; /* reversing sources case */
|
tactcomplabs/xbgas-binutils-gdb
| 1,599
|
gas/testsuite/gas/bfin/flow.s
|
.data
foodata: .word 42
.text
footext:
.text
.global jump
jump:
jump(P5);
Jump (pc + p3);
jUMp (0);
JumP.l (-16777216);
jumP.L (0x00fffffe);
JUMP.s (4094);
JUMP.L (0X00FF0000);
jump (footext);
.text
.global ccjump
ccjump:
if cc jump (-1024);
IF CC JUMP (1022) (BP);
if !cc jump (0xffffFc00) (Bp);
if !cc jumP (0x0112);
if cC JuMp (footext);
if CC jUmP (footext) (bp);
if !cc jump (FOOTEXT) (bP);
if !Cc JUMP (FooText);
.text
.global call
call:
call (P3);
Call (PC+p2);
cALL (0xff000000);
CalL(0x00FFFFFe);
CAll call_test;
.text
.global return
return:
rts;
rTi;
rtX;
Rtn;
RTE;
.text
.text
.global loop_lc0
loop_lc0:
loop first_loop lc0;
Loop_Begin first_loop;
R0 = [FP+-3604];
R1 = 9 (X);
R0 = [FP+-3604];
P0 = R0;
P2 = P0 << 2;
P2 = P2 + FP;
R0 = -1200 (X);
P1 = R0;
P2 = P2 + P1;
R0 = 0 (X);
[P2] = R0;
R0 = [FP+-3604];
R0 += 1;
[FP+-3604] = R0;
LOOP_END first_loop;
lOOP second_loop Lc0 = P4;
Loop_Begin second_loop;
NOP;
Loop_End second_loop;
LOOP third_loop lC0 = P1 >> 1;
Lsetup (4, 2046) Lc0;
LSETUP(30, 1024) LC0 = P5;
LSeTuP (30, 4) lc0 = p0 >> 1;
.global loop_lc1
loop_lc1:
loop my_loop lc1;
lOOP other_loop Lc1 = P4;
LOOP another_loop lC1 = P1 >> 1;
Lsetup (4, 2046) Lc1;
LSETUP (30, 1024) LC1 = P5;
LSeTuP (30, 4) lc1 = p0 >> 1;
Loop_Begin another_loop;
R0 = [FP+-3608];
P0 = R0;
P2 = P0 << 2;
P2 = P2 + FP;
R0 = -3600 (X);
P0 = R0;
P1 = P2 + P0;
R0 = [FP+-3608];
P0 = R0;
P2 = P0 << 2;
P2 = P2 + FP;
R0 = -1200 (X);
P0 = R0;
P2 = P2 + P0;
R0 = [P2];
[P1] = R0;
LOOP_END another_loop;
|
tactcomplabs/xbgas-binutils-gdb
| 6,412
|
gas/testsuite/gas/bfin/parallel.s
|
.section .text;
R5 = Deposit (r3, r2) || I0 += 2;
r0 = DEPOSIT (r7, R6) (X) || I1 += 4;
r4 = extract (r2, r1.L) (z) || I2 -= M0;
R2 = EXTRACT (r0, r2.l) (Z) || i3 += m1;
r7 = ExtracT (r3, r4.L) (X) || I3 += M1 (breV);
r5 = ExtRACt (R6, R1.L) (x) || i0 -= 2;
BITMUX(R1, R0, A0) (ASR) || I1 -= 4;
Bitmux (r2, R3, a0) (aSr) || I0 += 2;
bitmux (r4, r5, a0) (asl) || Sp = [P0];
BiTMux (R7, r6, a0) (ASl) || FP = [P1++];
R5.l = ones r0 || P0 = [fp--];
r7.L = Ones R2 || p1 = [P5 + 24];
a0 = abs a0 || p2 = [Sp+60] || r0 = [i0];
A0 = ABS A1 || P3 = [FP-60] || R1 = [I1++M0];
A1 = Abs a0 || P4 = [fp-4] || r2 = [i1++];
a1 = aBs A1 || fp = [sp] || r3 = [I2--];
A1 = abs a1, a0 = ABS A0 || R4=[p5+56] || r0.h = w [I0];
r0 = abs r2 || B[sp] = r0 || R1.H = W[I1++];
r4.L = R2.h + r0.L (s) || b [fp] = r0 || r2.H = w [i2--];
r5.H = R1.H + R1.L (S) || b [p0] = r0 || R3.l = W[I3];
r6.L = R6.L + r5.l (NS) || b [p1] = r0 || r4.L =w [i3++];
r4.l = r0 + r1 (RND20) || b [p2] = r0 || R5.l = W [i2--];
R3.H = r5 + r0 (rnd20) || r0 = b [p0] (x) || [i0] = R6;
r1.L = r7 - R5 (rND20) || r0 = b [p4] (z) || [I1++] = R7;
r2.L = R0 + R1 (rnd12) || r1 = b [sp] (x) || [I2--]= r7;
r7.H = r7 + r6 (RND12) || r1 = b [p0] (x)|| [I3++m1]=r6;
r5.l = r3 - R2 (rNd12) || r1 = b [p1] (z) || W [ i3 ] = r5.h;
r2.h = R1 - R2 (Rnd12) || r1 = b [p2] (z) || w [I2++] = R4.H;
r6.L = EXPADJ (r5, r4.l) || r1 = b [p3] (z) || W[I1--]=r3.h;
R5.l = ExpAdj (r0.h, r1.l) || r1 = b [p4] (z) || w[i0]=r2.l;
R4.L = expadj (R3, R5.L) (V) || r1 = b [p5] (z) || W [I0++] = R1.L;
R6 = MAX (r5, R2) || r2 = b [p0] (x) || W[i1--]=R0.l;
r0 = max (r1, r3) || b [p1] = r2 || NoP;
r5 = mIn (r2, R3) || b [p2] = r2 || r0 = [i1++];
R4 = Min (r7, R0) || b [p3] = r2 || r1 = [i1++];
A0 -= A1 || b [p4] = r2 || r2 = [i1++];
a0 -= a1 (w32) || b [p5] = r2 || r3 = [i1++];
a0 += a1 || b [sp] = r2 || r4 = [i1++];
A0 += A1 (w32) || b [fp] = r2 || r5 = [i1++];
r7 = ( a0 += a1) || b [sp] = r3 || r6 = [i1++];
r6.l = (A0 += a1) || b [fp] = r3 || r7 = [i1++];
R0.H = (a0 += A1) || b [p0] = r3 || r7 = [i0++];
R0.l = r1.h * r2.l || b [p1] = r3 || r1 = [i0++];
r1.L = r5.H * r0.H (s2rnd) || b [p2] = r3 || r2 = [i0++];
r7.l = r3.l * r3.H (FU) || b [p3] = r3 || r3 = [i0++];
r4 = r2.H * r5.H (iSS2) || b [p4] = r3 || r0 = [i0++];
r0 = r1.l * r3.l (is) || b [p5] = r3 || r5 = [i0++];
r6 = R5.H * r0.l || b [fp] = r4 || r7 = [i0++];
r2.h = r7.l * r6.H (M, iu) || b [sp] = r4 || r6 = [i0++];
r3.H = r5.H * r0.L || r4 = b [p0] (x) || [I0++M0] = R0;
R0.H = r1.L * r1.H (M) || r4 = b [p1] (x) || [i0++M0] = R1;
r1 = r7.H * r6.L (M, is) || r4 = b [p2] (x) || [i0++M0] = R2;
R5 = r0.l * r2.h || r4 = b [p3] (x) || [i0++m0] = R3;
r3 = r6.H * r0.H (m) || r4 = b [p4] (z) || [i0++m0] = R4;
a0 = r5.l * R7.H (w32) || r4 = b [p5] (z) || [i0++m0] = R5;
a0 = r0.h * r0.l || r5 = b [p0] (x) || [i0++M0] =R6;
A0 += R2.L * r3.H (FU) || r5 = b [p1] (z) || [i0++M0]=R7;
A0 += r4.h * r1.L || r5 = b [p2] (z) || [I1++M1] = R7;
a0 -= r7.l * r6.H (Is) || r5 = b [p3] (x) || [i1++m1] = r6;
A0 -= R5.H * r2.H || r5 = b [p4] (z) || [i1++m1]=r5;
a1 = r1.L * r0.H (M) || r5 = b [p5] (x) || [i1++m1]=r4;
A1 = r2.h * r0.L || r5 = b [sp] (z) || [i1++m1] = r3;
A1 = R7.H * R6.L (M, W32) || r5 = b [fp] (x) || [i1++m1] =r2;
a1 += r3.l * r2.l (fu) || r0.l = w [i0] || [i1++m1] = r1;
a1 += R6.H * r1.L || r1.l = w [i0] || [i1++m1] = R0;
A1 -= r0.L * R3.H (is) || r2.l = w [i0] || [i2++m2] = R0;
a1 -= r2.l * r7.h || r3.l = w [i0] || [I2++M2] =R1;
r7.l = (a0 = r6.H * r5.L) || r4.l = w [i0] || [i2++m2] = r2;
r0.L = (A0 = r1.h * R2.l) (tfu) || r5.l = w [i0] || [I2++m2] = R3;
R2.L = (a0 += r5.L * r4.L) || r6.l = w [i0] || [I2++m2] = R4;
r3.l = (A0 += r7.H * r6.h) (T) || r7.l = w [i0] || [ i2 ++ m2] = R5;
r0.l = (a0 -= r3.h * r2.h) || r7.l = w [i1++] || [i2++m2] = r6;
r1.l = (a0 -= r5.L * r4.L) (iH) || r6.l = w [i1++] || [i2++m2] = R7;
r1.H = (a1 = r1.l * R0.H) || r2.l = w [i1++] || [i3++m3] = R7;
r2.h = (A1 = r0.H * r3.L) (M, Iss2) || r3.l = w [i1++] || [i3++m3] = r6;
R6.H = (a1 += r7.l * r7.H) || r4.l = w [i1++] || [i3++m3] = R5;
r7.h = (a1 += R2.L * R3.L) (S2rnd) || r5.l = w [i1++] || [i3++m3] = r4;
r6.H = (A1 -= R4.h * r2.h) || r6.l = w [i1++] || [i3++m3] = r3;
r5.h = (a1 -= r3.H * r7.L) (M, tFu) || r7.l = w [i1++] || [i3++m3] = r2;
R0 = (A0 = R1.L * R2.L) || R1.L = W [I2--] || [i3++m3] = r1;
R2 = (A0 = r1.l * r2.l) (is) || R1.L = W [I2--] || [i3++m3] = r0;
r4 = (a0 += r7.h * r6.L) || R2.L = W [I2--] || r0.h = w[i0];
r6 = (A0 += R5.L * r3.h) (s2RND) || R3.L = W [I2--] || R1.H = w[i1];
R6 = (a0 -= r2.h * r7.l) || R4.L = W [I2--] || r2.h = w[i2];
r4 = (A0 -= R0.L * r6.H) (FU) || R5.L = W [I2--] || r3.h = w[i3];
r7 = (a1 = r0.h * r1.l) || R6.L = W [I2--] || r4.h = w[i3];
R5 = (A1 = r2.H * r3.H) (M, fu) || R7.L = W [I2--] || r4.h = W[i2];
R3 = (A1 += r7.l * r5.l) || w [p0] = r0.L || r6.h = W[i1];
r1 = (a1 += r2.h * r7.h) (iss2) || w [p0] = r1.L || r7.h = w[i0];
r3 = (A1 -= r0.l * R0.H) || w [p0] = r2.L || r7.L = w[I0++];
R5 = (a1 -= R2.l * R7.h) (m, is) || w [p0] = r3.L || R6.L = W [i1++];
r7 = -R2(s) || w [p0] = r4.L || r5.l = w[i2++];
A0 = -A0 || w [p0] = r5.L || r4.l = w[i3++];
a0 = -a1 || w [p0] = r6.L || r3.L = w [i3--];
A1 = -A0 || w [p0] = r7.L || r2.l = W [i1++];
a1 = -A1 || w [p1] = r0 || r1.L = w [i2--];
a1 = -a1, a0 = -a0 || w [p1] = r1 || r0.l = w [i1--];
R5.L = r3 (rnd) || w [p1] = r2 || r0 = [i0++m3];
r6.H = r0 (RND) || w [p1] = r3 || r1 = [i1++m2];
A0 = A0 (S) || w [p1] = r4 || r2 = [i2++m1];
a1 = a1 (s) || w [p1] = r5 || r3 = [i3++m0];
A1 = a1 (S), a0 = A0 (s) || r6 = w [p1] (z) || [i0] = r0;
R5.l = signbits r0 || r7 = w [p1] (z) || [i1] = R0;
r0.L = SIGNbits r7.H || r1 = w [p2++](x) || [I2] = r0;
r3.l = signBits A0 || r2 = w [p2++] (x) || [I3] = R0;
r7.L = SIGNBITS a1 || r3 = w [p2++] (z) || [i0] = R1;
r5.l = R6.H - R7.h (s) || r4 = w [p2++] (x) || [i1] = r1;
r0.H = r3.l - r3.h (NS) || r5 = w [p2++] (x) || [i2] = r2;
R1 = [I0++] || R2 = ABS R2 || NOP;
P0 = [FP+20] || R0 = [I2++];
R4.L = A0.x || R6 = [FP + 60] || R4.H = W[I1++] ;
R4.L = A0.x || R4.H = W[I1++] || W[I0] = R4.H ;
R4.L = A0.x || W[I1++] = R4.L || R4.H = W[I0--] ;
R4.L = A1.x || R6 = B[SP--] (Z) || R4.H = W[I1++] ;
A0 += A1 (W32) || R3.L = W[I0] || R0 = [I0++ M3] ;
A0 -= A1 || R0 = W[P0++] (X) || W[I0++] = R3.L ;
|
tactcomplabs/xbgas-binutils-gdb
| 1,591
|
gas/testsuite/gas/bfin/cache2.s
|
.EXTERN MY_LABEL2;
.section .text;
//
//12 CACHE CONTROL
//
//PREFETCH [ Preg ] ; /* indexed (a) */
PREFETCH [ P0 ] ;
PREFETCH [ P1 ] ;
PREFETCH [ P2 ] ;
PREFETCH [ P3 ] ;
PREFETCH [ P4 ] ;
PREFETCH [ P5 ] ;
PREFETCH [ SP ] ;
PREFETCH [ FP ] ;
//PREFETCH [ Preg ++ ] ; /* indexed, post increment (a) */
PREFETCH [ P0++ ] ;
PREFETCH [ P1++ ] ;
PREFETCH [ P2++ ] ;
PREFETCH [ P3++ ] ;
PREFETCH [ P4++ ] ;
PREFETCH [ P5++ ] ;
PREFETCH [ SP++ ] ;
PREFETCH [ FP++ ] ;
//FLUSH [ Preg ] ; /* indexed (a) */
FLUSH [ P0 ] ;
FLUSH [ P1 ] ;
FLUSH [ P2 ] ;
FLUSH [ P3 ] ;
FLUSH [ P4 ] ;
FLUSH [ P5 ] ;
FLUSH [ SP ] ;
FLUSH [ FP ] ;
//FLUSH [ Preg ++ ] ; /* indexed, post increment (a) */
FLUSH [ P0++ ] ;
FLUSH [ P1++ ] ;
FLUSH [ P2++ ] ;
FLUSH [ P3++ ] ;
FLUSH [ P4++ ] ;
FLUSH [ P5++ ] ;
FLUSH [ SP++ ] ;
FLUSH [ FP++ ] ;
//FLUSHINV [ Preg ] ; /* indexed (a) */
FLUSHINV [ P0 ] ;
FLUSHINV [ P1 ] ;
FLUSHINV [ P2 ] ;
FLUSHINV [ P3 ] ;
FLUSHINV [ P4 ] ;
FLUSHINV [ P5 ] ;
FLUSHINV [ SP ] ;
FLUSHINV [ FP ] ;
//FLUSHINV [ Preg ++ ] ; /* indexed, post increment (a) */
FLUSHINV [ P0++ ] ;
FLUSHINV [ P1++ ] ;
FLUSHINV [ P2++ ] ;
FLUSHINV [ P3++ ] ;
FLUSHINV [ P4++ ] ;
FLUSHINV [ P5++ ] ;
FLUSHINV [ SP++ ] ;
FLUSHINV [ FP++ ] ;
//IFLUSH [ Preg ] ; /* indexed (a) */
IFLUSH [ P0 ] ;
IFLUSH [ P1 ] ;
IFLUSH [ P2 ] ;
IFLUSH [ P3 ] ;
IFLUSH [ P4 ] ;
IFLUSH [ P5 ] ;
IFLUSH [ SP ] ;
IFLUSH [ FP ] ;
//IFLUSH [ Preg ++ ] ; /* indexed, post increment (a) */
IFLUSH [ P0++ ] ;
IFLUSH [ P1++ ] ;
IFLUSH [ P2++ ] ;
IFLUSH [ P3++ ] ;
IFLUSH [ P4++ ] ;
IFLUSH [ P5++ ] ;
IFLUSH [ SP++ ] ;
IFLUSH [ FP++ ] ;
|
tactcomplabs/xbgas-binutils-gdb
| 5,219
|
gas/testsuite/gas/fr30/allinsn.s
|
.data
foodata: .word 42
.text
footext:
.global add
add:
add r0, r1
add #0, r2
.global add2
add2:
add2 #-1, r3
.global addc
addc:
addc r4, r5
.global addn
addn:
addn r6, r7
addn #15, r8
.global addn2
addn2:
addn2 #-16, r9
.global sub
sub:
sub r10, r11
.global subc
subc:
subc r12, r13
.global subn
subn:
subn r14, r15
.global cmp
cmp:
cmp ac, fp
cmp #1, sp
.global cmp2
cmp2:
cmp2 #-15, r0
.global and
and:
and r1, r2
and r3, @r4
.global andh
andh:
andh r5, @r6
.global andb
andb:
andb r7, @r8
.global or
or:
or r9, r10
or r11, @r12
.global orh
orh:
orh r13, @r14
.global orb
orb:
orb r15, @ac
.global eor
eor:
eor fp, sp
eor r0, @r1
.global eorh
eorh:
eorh r2, @r3
.global eorb
eorb:
eorb r4, @r5
.global bandl
bandl:
bandl #15, @r6
.global bandh
nadh:
bandh #7, @r7
.global borl
borl:
borl #3, @r8
.global borh
borh:
borh #13, @r9
.global beorl
beorl:
beorl #15, @r10
.global beorh
beorh:
beorh #1, @r11
.global btstl
btstl:
btstl #0, @r12
.global btsth
btsth:
btsth #8, @r13
.global mul
mul:
mul r14, r15
.global mulu
mulu:
mulu ac, fp
.global muluh
muluh:
muluh sp, r0
.global mulh
mulh:
mulh r1, r2
.global div0s
div0s:
div0s r3
.global div0u
div0u:
div0u r4
.global div1
div1:
div1 r5
.global div2
div2:
div2 r6
.global div3
div3:
div3
.global div4s
div4s:
div4s
.global lsl
lsl:
lsl r7, r8
lsl #3, r9
.global lsl2
lsl2:
lsl2 #0, r10
.global lsr
lsr:
lsr r11, r12
lsr #15, r13
.global lsr2
lsr2:
lsr2 #15, r14
.global asr
asr:
asr r15, ac
asr #6, fp
.global asr2
asr2:
asr2 #7, sp
.global ldi_8
ldi_8:
ldi:8 #0xff, r2
.global ld
ld:
ld @r3, r4
ld @(R13, r5), r6
ld @(R14, 0x1fc), r7
ld @(R15, 0x3c), r8
ld @r15+, r9
ld @r15+, ps
ld @R15+, tbr
ld @r15+, rp
ld @R15+, ssp
.global lduh
lduh:
lduh @r10, r11
lduh @(r13, r12), r13
lduh @(r14, #-256), r15
.global ldub
ldub:
ldub @ac, fp
ldub @(r13, sp), r0
ldub @(r14, -128), r1
.global st
st:
st r2, @r3
st r4, @(r13, r5)
st r6, @(r14, -512)
st r7, @(r15, 0x3c)
st r8, @ - r15
st MDH, @-r15
st PS, @ - r15
.global lsth
sth:
sth r9, @r10
sth r11, @(r13, r12)
sth r13, @(r14, 128)
.global stb
stb:
STB r14, @r15
stb r0, @(r13, r1)
STB r2, @(r14, -128)
.global mov
mov:
mov r3, r4
MOV mdl, r5
mov ps, r6
mov r7, usp
mov r8, ps
.global jmp
jmp:
jmp @r9
.global ret
ret:
ret
.global bra
bra:
bra footext
.global bno
bno:
bno footext
.global beq
beq:
beq footext
.global bne
bne:
bne footext
.global bc
bc:
bc footext
.global bnc
bnc:
bnc footext
.global bn
bn:
bn footext
.global bp
bp:
bp footext
.global bv
bv:
bv footext
.global bnv
bnv:
bnv footext
.global blt
blt:
blt footext
.global bge
bge:
bge footext
.global ble
ble:
ble footext
.global bgt
bgt:
bgt footext
.global bls
bls:
bls footext
.global bhi
bhi:
bhi footext
delay_footext:
.global jmp_d
jmp_d:
jmp:d @r11
nop
.global ret_d
ret_d:
ret:d
nop
.global bra_d
bra_d:
bra:D delay_footext
nop
.global bno_d
bno_d:
bno:d delay_footext
nop
.global beq_d
beq_d:
beq:D delay_footext
nop
.global bne_d
bne_d:
bne:d delay_footext
nop
.global bc_d
bc_d:
bc:d delay_footext
nop
.global bnc_d
bnc_d:
bnc:d delay_footext
nop
.global bn_d
bn_d:
bn:d delay_footext
nop
.global bp_d
bp_d:
bp:d delay_footext
nop
.global bv_d
bv_d:
bv:d delay_footext
nop
.global bnv_d
bnv_d:
bnv:d delay_footext
nop
.global blt_d
blt_d:
blt:d delay_footext
nop
.global bge_d
bge_d:
bge:d delay_footext
nop
.global ble_d
ble_d:
ble:d delay_footext
nop
.global bgt_d
bgt_d:
bgt:d delay_footext
nop
.global bls_d
bls_d:
bls:d delay_footext
nop
.global bhi_d
bhi_d:
bhi:d delay_footext
nop
.global ldres
ldres:
ldres @r2+, #8
.global stres
stres:
stres #15, @r3+
.global nop
nop:
nop
.global andccr
andccr:
andccr #255
.global orccr
orccr:
orccr #125
.global stilm
stilm:
stilm #97
.global addsp
addsp:
addsp #-512
.global extsb
extsb:
extsb r9
.global extub
extub:
extub r10
.global extsh
extsh:
extsh r11
.global extuh
extuh:
extuh r12
.global enter
enter:
enter #1020
.global leave
leave:
leave
.global xchb
xchb:
xchb @r14, r15
.global ldi_32
ldi_32:
ldi:32 #0x12345678, r0
.global copop
copop:
copop #15, #1, cr3, cr4
copop #15, #4, cr5, cr6
copop #15, #255, cr7, cr0
.global copld
copld:
copld #0, #0, r4, cr0
.global copst
copst:
copst #7, #2, cr1, r5
.global copsv
copsv:
copsv #8, #3, cr2, r6
.global ldm0
ldm0:
ldm0 (r0, r2, r3, r7)
.global ldm1
ldm1:
ldm1 (r8, r11, r15)
.global stm0
stm0:
stm0 (r2, r3)
.global stm1
stm1:
stm1 (r13, r14)
.global call
call:
call footext
call @r10
.global call_d
call_d:
call:D footext
nop
call:d @r12
nop
.global dmov
dmov:
dmov @0x88, r13
dmov r13, @0x54
dmov @0x44, @r13+
dmov @R13+, @0x2
dmov @0x2c, @-r15
dmov @r15+, @38
.global dmovh
dmovh:
dmovh @0x88, r13
dmovh r13, @0x52
dmovh @0x34, @r13 +
dmovh @r13+, @0x52
.global dmovb
dmovb:
dmovb @0x91, r13
dmovb r13, @0x53
dmovb @71, @r13+
dmovb @r13+, @0x0
.global ldi_20
ldi_20:
ldi:20 #0x000fffff, r1
finish:
ldi:32 #0x8000,r0
mov r0,ssp
ldi:32 #1,r0
int #10
.global inte
inte:
inte
.global reti
reti:
reti
|
tactcomplabs/xbgas-binutils-gdb
| 1,260
|
gas/testsuite/gas/nds32/to-16bit-v1.s
|
foo:
move $r0, $r0
move $sp, $sp
movi $r0, -16
movi $sp, 15
add $r0, $r0, $r0
add $r19, $sp, $r19
sub $r0, $r0, $r0
sub $r19, $r19, $sp
addi $r0, $r0, 0
addi $r19, $r19, 31
srai $r0, $r0, 0
srai $r19, $r19, 31
srli $r0, $r0, 0
srli $r19, $r19, 31
slli $r0, $r0, 0
slli $r7, $r7, 7
zeb $r0, $r0
zeb $r7, $r7
zeh $r0, $r0
zeh $r7, $r7
seb $r0, $r0
seb $r7, $r7
seh $r0, $r0
seh $r7, $r7
andi $r0, $r0, 1
andi $r7, $r7, 0x7ff
add $r0, $r0, $r0
add $r7, $r7, $r7
sub $r0, $r0, $r0
sub $r7, $r7, $r7
addi $r0, $r0, 0
addi $r7, $r7, 7
lwi $r0, [$r0 + 0]
lwi $r7, [$r7 + 28]
lwi.bi $r0, [$r0], 0
lwi.bi $r7, [$r7], 28
lhi $r0, [$r0 + 0]
lhi $r7, [$r7 + 14]
lbi $r0, [$r0 + 0]
lbi $r7, [$r7 + 7]
swi $r0, [$r0 + 0]
swi $r7, [$r7 + 28]
swi.bi $r0, [$r0], 0
swi.bi $r7, [$r7], 28
shi $r0, [$r0 + 0]
shi $r7, [$r7 + 14]
sbi $r0, [$r0 + 0]
sbi $r7, [$r7 + 7]
lwi $r0, [$r0 + 0]
lwi $r19, [$sp + 0]
swi $r0, [$r0 + 0]
swi $r19, [$sp + 0]
lwi $r0, [$fp + 0]
lwi $r7, [$fp + 508]
swi $r0, [$fp + 0]
swi $r7, [$fp + 508]
jr $r0
jr $sp
ret $r0
ret $sp
jral $r0
jral $sp
slts $r15, $r0, $r0
slts $r15, $r19, $sp
slt $r15, $r0, $r0
slt $r15, $r19, $sp
sltsi $r15, $r0, 0
sltsi $r15, $r19, 31
slti $r15, $r0, 0
|
tactcomplabs/xbgas-binutils-gdb
| 2,066
|
gas/testsuite/gas/nds32/sys-reg.s
|
foo:
mfsr $r0 ,$CPU_VER
mfsr $r0 ,$CORE_ID
mfsr $r0 ,$ICM_CFG
mfsr $r0 ,$DCM_CFG
mfsr $r0 ,$MMU_CFG
mfsr $r0 ,$MSC_CFG
mfsr $r0 ,$PSW
mfsr $r0 ,$IPSW
mfsr $r0 ,$P_IPSW
mfsr $r0 ,$IVB
mfsr $r0 ,$INT_CTRL
mfsr $r0 ,$EVA
mfsr $r0 ,$P_EVA
mfsr $r0 ,$ITYPE
mfsr $r0 ,$P_ITYPE
mfsr $r0 ,$MERR
mfsr $r0 ,$IPC
mfsr $r0 ,$P_IPC
mfsr $r0 ,$OIPC
mfsr $r0 ,$P_P0
mfsr $r0 ,$P_P1
mfsr $r0 ,$INT_MASK
mfsr $r0 ,$INT_MASK2
mfsr $r0 ,$INT_PEND
mfsr $r0 ,$INT_PEND2
mfsr $r0 ,$INT_TRIGGER
mfsr $r0 ,$SP_USR
mfsr $r0 ,$SP_PRIV
mfsr $r0 ,$INT_PRI
mfsr $r0 ,$INT_PRI2
mfsr $r0 ,$MMU_CTL
mfsr $r0 ,$L1_PPTB
mfsr $r0 ,$TLB_VPN
mfsr $r0 ,$TLB_DATA
mfsr $r0 ,$TLB_MISC
mfsr $r0 ,$VLPT_IDX
mfsr $r0 ,$ILMB
mfsr $r0 ,$DLMB
mfsr $r0 ,$CACHE_CTL
mfsr $r0 ,$HSMP_SADDR
mfsr $r0 ,$HSMP_EADDR
mfsr $r0 ,$SDZ_CTL
mfsr $r0 ,$MISC_CTL
mfsr $r0 ,$BPC0
mfsr $r0 ,$BPC1
mfsr $r0 ,$BPC2
mfsr $r0 ,$BPC3
mfsr $r0 ,$BPC4
mfsr $r0 ,$BPC5
mfsr $r0 ,$BPC6
mfsr $r0 ,$BPC7
mfsr $r0 ,$BPA0
mfsr $r0 ,$BPA1
mfsr $r0 ,$BPA2
mfsr $r0 ,$BPA3
mfsr $r0 ,$BPA4
mfsr $r0 ,$BPA5
mfsr $r0 ,$BPA6
mfsr $r0 ,$BPA7
mfsr $r0 ,$BPAM0
mfsr $r0 ,$BPAM1
mfsr $r0 ,$BPAM2
mfsr $r0 ,$BPAM3
mfsr $r0 ,$BPAM4
mfsr $r0 ,$BPAM5
mfsr $r0 ,$BPAM6
mfsr $r0 ,$BPAM7
mfsr $r0 ,$BPV0
mfsr $r0 ,$BPV1
mfsr $r0 ,$BPV2
mfsr $r0 ,$BPV3
mfsr $r0 ,$BPV4
mfsr $r0 ,$BPV5
mfsr $r0 ,$BPV6
mfsr $r0 ,$BPV7
mfsr $r0 ,$BPCID0
mfsr $r0 ,$BPCID1
mfsr $r0 ,$BPCID2
mfsr $r0 ,$BPCID3
mfsr $r0 ,$BPCID4
mfsr $r0 ,$BPCID5
mfsr $r0 ,$BPCID6
mfsr $r0 ,$BPCID7
mfsr $r0 ,$EDM_CFG
mfsr $r0 ,$EDMSW
mfsr $r0 ,$EDM_CTL
mfsr $r0 ,$EDM_DTR
mfsr $r0 ,$BPMTC
mfsr $r0 ,$DIMBR
mfsr $r0 ,$TECR0
mfsr $r0 ,$TECR1
mfsr $r0 ,$PFMC0
mfsr $r0 ,$PFMC1
mfsr $r0 ,$PFMC2
mfsr $r0 ,$PFM_CTL
mfsr $r0 ,$PRUSR_ACC_CTL
mfsr $r0 ,$FUCOP_CTL
mfsr $r0 ,$DMA_CFG
mfsr $r0 ,$DMA_GCSW
mfsr $r0 ,$DMA_CHNSEL
mfsr $r0 ,$DMA_ACT
mfsr $r0 ,$DMA_SETUP
mfsr $r0 ,$DMA_ISADDR
mfsr $r0 ,$DMA_ESADDR
mfsr $r0 ,$DMA_TCNT
mfsr $r0 ,$DMA_STATUS
mfsr $r0 ,$DMA_2DSET
mfsr $r0 ,$DMA_2DSCTL
|
tactcomplabs/xbgas-binutils-gdb
| 6,161
|
gas/testsuite/gas/epiphany/regression.s
|
;; -*-asm-*-
TABLE=0x8000
RZ=r63
.macro FAIL
mov r0,#1
trap 3
.endm
.macro PASS
mov r0,#0
trap 3
.endm
.macro VERIFY ra,rb,ref,label
sub \ra,\rb,\ref
beq \label
FAIL
.endm
/*****************************************/
/*INITIALIZING REGISTERS */
/*****************************************/
/*Check that sum is correct*/
START: MOV R0, #TABLE ; //Setting R0 to TABLE
LSL R0,R0,#2 ; //Create 00020000
;; Load r1.63 with 1..63
.irpc num,63
mov r\num,#\num
.endr
;; Sum the registers
.irpc num,62
add r63,r63,r\num
.endr
mov r62,#2016 ;//Correct sum of 1..63 = 63*32 + 63
VERIFY r63,r63,R62,BRANCH1;//CHECK SUM
/*****************************************/
/*BRANCHING */
/*****************************************/
//Check that all condition codes work
BRANCH1: BEQ BRANCH2 ; //taken
FAIL ;
FAIL ;
FAIL ;
FAIL ;
BRANCH2: BNE FAIL_BRANCH ; //not taken
BRANCH3: BGT FAIL_BRANCH ; //not taken
BRANCH4: BGTE BRANCH5 ; //taken
FAIL ;
BRANCH5: BLTE BRANCH6 ; //taken
FAIL ;
BRANCH6: BLT FAIL_BRANCH ; //not taken
BRANCH8: B LONGJUMP ; //taken
FAIL ;
RETURN: bl FUNCTION ; //jump to subroutine
MOV R63,JARLAB ;//REGISTER JUMP
JR R63 ;
FAIL ;
JARLAB: MOV R63,FUNCTION ; //REGISTER CALL
JALR R63 ; //16 bit
B NEXT ; //jump over fail
FAIL ;
FAIL_BRANCH: FAIL ; //fail branch
/*****************************************/
/*LOAD-STORE DISPLACEMENT */
/*****************************************/
//Check max displacement value(0xf)
//Check that offset is correct
//all load/stores are aligned
//this gives greater range(2 more bits)
//offset is shifted by 2x bits
NEXT: STRB R4,[R0,#0x0] ;//Store Byte
LDRB R63,[R0,#0x0] ;//Load Byte
VERIFY R63,R63,R4,STOREB ;
STOREB: STRB R5,[R0,#0xf] ;//Store Byte
LDRB R63,[R0,#0xf] ;//Load Byte
VERIFY R63,R63,R5,STORES ;
STORES: STRH R4,[R0,#0x0] ;//Store Short
LDRH R63,[R0,#0x0] ;//Load Short
VERIFY R63,R63,R4,STORES2 ;
STORES2: STRH R5,[R0,#0xe] ;//Store Short
LDRH R63,[R0,#0xe] ;//Load Short
VERIFY R63,R63,R5,STORE ;
STORE: STR R4,[R0,#0x0] ;//Store Word
LDR R63,[R0,#0x0] ;//Load Word
VERIFY R63,R63,R4,STORE2 ;
STORE2: STR R5,[R0,#0xc] ;//Store Word
LDR R63,[R0,#0xc] ;//Load Word
VERIFY R63,R63,R5,STOREBI ;
/*****************************************/
/*LOAD-STORE INDEX */
/*****************************************/
STOREBI: STRB R4,[R0,R4] ;//Store Word
LDRB R63,[R0,R4] ;//Load Word
VERIFY R63,R63,R4,STORESI ;
STORESI: STRH R5,[R0,R4] ;//Store Word
LDRH R63,[R0,R4] ;//Load Word
VERIFY R63,R63,R5,STOREI ;
STOREI: STR R6,[R0,R4] ;//Store Word
LDR R63,[R0,R4] ;//Load Word
VERIFY R63,R63,R6,PMB ;
/*****************************************/
/*LOAD-STORE POSTMODIFY */
/*****************************************/
PMB: STRB R4,[R0],R4 ;//Store Word
SUB R0,R0,#0x4 ;//restoring R0
LDRB R63,[R0],R4 ;//Load Word
SUB R0,R0,#0x4 ;//restoring R0
VERIFY R63,R63,R4,PMS ;
PMS: STRH R5,[R0],R4 ;//Store Word
SUB R0,R0,#0x4 ;//restoring R0
LDRH R63,[R0],R4 ;//Load Word
VERIFY R63,R63,R5,PM ;
PM: SUB R0,R0,#0x4 ;//restoring R0
STR R6,[R0],R4 ;//Store Word
SUB R0,R0,#0x4 ;//restoring R0
LDR R63,[R0],R4 ;//Load Word
SUB R0,R0,#0x4 ;//restoring R0
VERIFY R63,R63,R6,MOVLAB ;
/*****************************************/
/*IMMEDIATE LOAD */
/*****************************************/
MOVLAB: MOV R63,#0xFF;
MOV R1,#0xFF;
VERIFY R63,R63,R1,ADDLAB ;
/*****************************************/
/*2 REG ADD/SUB PROCESSING */
/*****************************************/
ADDLAB: ADD R63,R2,#3; //2+3=5
VERIFY R63,R63,#5,SUBLAB ;
SUBLAB: SUB R63,R2,#1; //2+1=1
VERIFY R63,R63,#1,LSRLAB ;
/*****************************************/
/*SHIFTS */
/*****************************************/
//Note ASR does not work
//Immediates
LSRLAB: LSR R63,R6,#0x2 ; //6>>2=1
VERIFY R63,R63,#1,LSLLAB ;
LSLLAB: LSL R63,R3,#0x2 ; //3<<2=12
VERIFY R63,R63,#12,LSRILAB ;
//Registers
LSRILAB: LSR R63,R6,R2 ; //6>>2=1
VERIFY R63,R63,#1,LSLILAB ;
LSLILAB: LSL R63,R3,R2 ; //3<<2=12
VERIFY R63,R63,#12,ORRLAB ;
/*****************************************/
/*LOGICAL */
/*****************************************/
ORRLAB: ORR R5,R3,R4 ; //0x3 | 0x4 -->0x7
VERIFY R63,R5,#7,ANDLAB ;
ANDLAB: AND R5,R3,R4 ; //0x3 & 0x4 -->0
VERIFY R63,R5,#0,EORLAB ;
EORLAB: EOR R5,R3,R2 ; //0x3 ^ 0x2 -->1
VERIFY R63,R5,#1,ADD3LAB ;
/****************************************/
/*3-REGISTER ADD/SUB */
/*****************************************/
ADD3LAB: ADD R63,R2,R3 ; //3+2=5
VERIFY R63,R63,#5,SUB3LAB ;
SUB3LAB: SUB R63,R6,R4 ; //6-4=2
VERIFY R63,R63,#2,MOVRLAB ;
/*****************************************/
/*MOVE REGISTER */
/*****************************************/
MOVRLAB: MOV R63,R2 ;
VERIFY R63,R63,#2,NOPLAB ;
/*****************************************/
/*MOVE TO/FROM SPECIAL REGISTER */
/*****************************************/
MOVTFLAB: MOVTS status,R0 ;
MOVFS R63,status ;
VERIFY R63,R63,R0,MOVTFLAB ;
/*****************************************/
/*NOP */
/*****************************************/
NOPLAB: NOP ;
NOP ;
NOP ;
NOP ;
/*****************************************/
/*PASS INDICATOR */
/*****************************************/
PASSED: PASS;
IDLE;
/*****************************************/
/*FAIL INDICATOR */
/*****************************************/
FAILED: FAIL;
IDLE;
/*****************************************/
/*LONG JUMP INDICATOR */
/*****************************************/
LONGJUMP: B RETURN; //jump back to next
/*****************************************/
/*SUBROUTINE */
/*****************************************/
FUNCTION: RTS; //return from subroutine
|
tactcomplabs/xbgas-binutils-gdb
| 1,537
|
gas/testsuite/gas/epiphany/sample.s
|
.data
foodata: .hword 42
.text
footext:
.text
.macro test nm:req, args:vararg
\nm: \nm \args
.global \nm
.endm
;;; Basic Instruction Tests
1: ; All branches
test beq,1b
test bne,1b
test bgtu,1b
test bgteu,1b
test blteu,1b
test bltu,1b
test bgt,1b
test bgte,1b
test blt,1b
test blte,1b
test bbeq,1b
test bbne,1b
test bblt,1b
test b,1b
test bl,1b
;;; jumps
test jr,r1
jr r31
test jalr,r1
jalr r31
.macro test3i nm:req
test \nm,r1,r2,r3
\nm r32,r33,r34
\nm r1,r2,#3
\nm r11,r2,#16
.endm
test3i add
test3i sub
test3i asr
test3i lsr
test3i lsl
.macro test3 nm:req
test \nm,r1,r2,r3
\nm r11,r12,r13
.endm
test3 orr
test3 and
test3 eor
.macro testmem nm:req
\nm r0,[r1,#3]
\nm r10,[r1,#255]
\nm r0,[r1,r2]
\nm r0,[r1,r11]
\nm r0,[r3],r2
\nm r10,[r12],r13
.endm
testmem ldrb
testmem ldrh
testmem ldr
testmem ldrd
testmem strb
testmem strh
testmem str
testmem strd
test mov,r6,#255
mov r31,#65535
mov r0,#4098
.macro testmov cond:req
mov\cond r1,r2
mov\cond r11,r12
.endm
testmov eq
testmov ne
testmov gtu
testmov gteu
testmov lteu
testmov ltu
testmov gt
testmov gte
testmov lt
testmov lte
testmov beq
testmov bne
testmov blt
testmov blte
mov r1,r2
mov r11,r12
test nop
test idle
test bkpt
test3 fadd
test3 fsub
test3 fmul
test3 fmadd
test3 fmsub
movts config,r1
movts status,r31
movfs r1,imask
movfs r31,pc
test trap,#0 ; write syscall for simulator.
rti ; dummy instruction
|
tactcomplabs/xbgas-binutils-gdb
| 21,202
|
gas/testsuite/gas/epiphany/allinsn.s
|
.data
foodata: .hword 42
.text
footext:
.text
.global beq16
.text
.global beq
bgt16:
bgt 4
bgt 4
bgt -4
bgt footext
bgt foodata
bgt 4
bgt footext
bgt footext
.text
.global bgt
bgtu16:
bgtu 4
bgtu -4
bgtu footext
bgtu 4
bgtu -4
bgtu footext
bgtu footext
bgtu 4
.text
.global bgtu
bgte16:
bgte footext
bgte footext
bgte footext
bgte footext
bgte footext
bgte -4
bgte foodata
bgte foodata
.text
.global bgteu16
bgteu16:
bgteu 4
bgteu -4
bgteu foodata
bgteu 4
bgteu footext
bgteu 4
bgteu foodata
bgteu foodata
.text
.global bgteu
bgteu:
.text
.global blt16
blt16:
blt -4
blt 4
blt -4
blt 4
blt -4
blt 4
blt foodata
blt foodata
.text
.global blt
blt:
.text
.global bltu16
bltu16:
bltu -4
bltu 4
bltu -4
bltu footext
bltu footext
bltu footext
bltu 4
bltu foodata
.text
.global bltu
bltu:
.text
.global blte16
blte16:
blte footext
blte foodata
blte foodata
blte footext
blte -4
blte footext
blte footext
blte 4
.text
.global blte
blte:
.text
.global blteu16
blteu16:
blteu footext
blteu foodata
blteu footext
blteu foodata
blteu footext
blteu -4
blteu foodata
blteu foodata
.text
.global blteu
blteu:
.text
.global bbeq16
bbeq16:
bbeq footext
bbeq footext
bbeq foodata
bbeq footext
bbeq 4
bbeq foodata
bbeq foodata
bbeq 4
.text
.global bbeq
bbeq:
.text
.global bbne16
bbne16:
bbne foodata
bbne -4
bbne 4
bbne footext
bbne 4
bbne 4
bbne footext
bbne footext
.text
.global bbne
bbne:
.text
.global bblt16
bblt16:
bblt foodata
bblt 4
bblt 4
bblt 4
bblt -4
bblt 4
bblt footext
bblt -4
.text
.global bblt
bblt:
.text
.global bblte16
bblte16:
bblte 4
bblte 4
bblte footext
bblte footext
bblte 4
bblte -4
bblte foodata
bblte 4
.text
.global bblte
bblte:
.text
.global b16
b16:
b footext
b footext
b 4
b -4
b footext
b foodata
b foodata
b -4
.text
.global b
b:
.text
.global bl16
bl16:
bl -4
bl 4
bl footext
bl -4
bl footext
bl -4
bl -4
bl footext
.text
.global bl
bl:
.text
.global jr16
jr16:
jr ip
jr r3
jr r0
jr fp
jr sp
jr r0
jr r3
jr r0
.text
.global jr
jr:
jr ip
jr r59
jr r28
jr r27
jr sp
jr r51
jr r56
jr r45
.text
.global jalr16
jalr16:
jalr ip
jalr r3
jalr r0
jalr fp
jalr sp
jalr r3
jalr fp
jalr ip
.text
.global jalr
jalr:
jalr ip
jalr r59
jalr r28
jalr r27
jalr sp
jalr r11
jalr r28
jalr r59
.text
.global ldrbx16
ldrbx16:
ldrb ip,[ip,ip]
ldrb r3,[r3,r3]
ldrb r0,[r0,r0]
ldrb fp,[fp,fp]
ldrb sp,[sp,sp]
ldrb ip,[r0,r0]
ldrb r3,[r2,lr]
ldrb r2,[ip,r3]
.text
.global ldrbp16
ldrbp16:
ldrb sp,[r0],fp
ldrb lr,[r1],ip
ldrb fp,[r0],fp
.text
.global ldrbx
ldrbx:
ldrb ip,[ip,ip]
ldrb r59,[r59,r59]
ldrb r28,[r28,r28]
ldrb r27,[r27,r27]
ldrb sp,[sp,sp]
ldrb r41,[r18,r47]
ldrb r43,[r16,r21]
ldrb r32,[r8,r8]
.text
.global ldrbp
ldrbp:
ldrb r36,[r49],r18
ldrb r32,[r59],r50
ldrb r58,[r11],r25
.text
.global ldrbd16
ldrbd16:
ldrb ip,[ip,0]
ldrb r3,[r3,7]
ldrb r0,[r0,4]
ldrb fp,[fp,3]
ldrb sp,[sp,1]
ldrb lr,[sp,1]
ldrb r1,[r0,0]
ldrb r1,[r1,1]
.text
.global ldrbd
ldrbd:
ldrb ip,[ip,0]
ldrb r59,[r59,2047]
ldrb r28,[r28,1024]
ldrb r27,[r27,1023]
ldrb sp,[sp,1]
ldrb r7,[r33,1574]
ldrb r31,[r6,1957]
ldrb r10,[r0,1831]
.text
.global ldrhx16
ldrhx16:
ldrh ip,[ip,ip]
ldrh r3,[r3,r3]
ldrh r0,[r0,r0]
ldrh fp,[fp,fp]
ldrh sp,[sp,sp]
ldrh r0,[r0,lr]
ldrh lr,[lr,sp]
ldrh r0,[fp,fp]
.text
.global ldrhp16
ldrhp16:
ldrh r2,[sp],fp
ldrh r22,[sp],fp
.text
.global ldrhx
ldrhx:
ldrh ip,[ip,ip]
ldrh r59,[r59,r59]
ldrh r28,[r28,r28]
ldrh r27,[r27,r27]
ldrh sp,[sp,sp]
ldrh r46,[r17,r21]
ldrh r30,[r1,r47]
ldrh r43,[r19,r20]
.text
.global ldrhp
ldrhp:
ldrh r32,[r31],r29
ldrh r52,[r47],r10
ldrh r31,[r40],r3
.text
.global ldrhd16
ldrhd16:
ldrh ip,[ip,0]
ldrh r3,[r3,7]
ldrh r0,[r0,4]
ldrh fp,[fp,3]
ldrh sp,[sp,1]
ldrh lr,[r2,0]
ldrh r3,[r0,7]
ldrh r0,[r3,6]
.text
.global ldrhd
ldrhd:
ldrh ip,[ip,0]
ldrh r59,[r59,2047]
ldrh r28,[r28,1024]
ldrh r27,[r27,1023]
ldrh sp,[sp,1]
ldrh r45,[r24,1221]
ldrh r36,[r43,1738]
ldrh r42,[r48,25]
.text
.global ldrx16
ldrx16:
ldr ip,[ip,ip]
ldr r3,[r3,r3]
ldr r0,[r0,r0]
ldr fp,[fp,fp]
ldr sp,[sp,sp]
ldr r3,[fp,lr]
ldr ip,[lr,r2]
ldr r3,[r2,lr]
.text
.global ldrp16
ldrp16:
ldr lr,[fp],sp
ldr r0,[sp],r0
ldr fp,[r2],r1
.text
.global ldrx
ldrx:
ldr ip,[ip,ip]
ldr r59,[r59,r59]
ldr r28,[r28,r28]
ldr r27,[r27,r27]
ldr sp,[sp,sp]
ldr r24,[r16,r47]
ldr r22,[r41,r49]
ldr r14,[fp,r39]
.text
.global ldrp
ldrp:
ldr r21,[r5],r30
ldr r36,[r12],r14
ldr r12,[r4],r11
.text
.global ldrd16
ldrd16:
ldr ip,[ip,0]
ldr r3,[r3,7]
ldr r0,[r0,4]
ldr fp,[fp,3]
ldr sp,[sp,1]
ldr r0,[sp,0]
ldr ip,[r1,7]
ldr fp,[r1,1]
.text
.global ldrd
ldrd:
ldr ip,[ip,0]
ldr r59,[r59,2047]
ldr r28,[r28,1024]
ldr r27,[r27,1023]
ldr sp,[sp,1]
ldr r22,[r30,975]
ldr r7,[r44,1361]
ldr r23,[r19,1855]
.text
.global ldrdx16
ldrdx16:
ldrd ip,[ip,ip]
ldrd r4,[r3,r3]
ldrd r0,[r0,r0]
ldrd r14,[fp,fp]
ldrd r16,[sp,sp]
ldrd r30,[r2,ip]
ldrd r0,[fp,r3]
ldrd r20,[ip,lr]
.text
.global ldrdp16
ldrdp16:
ldrd r4,[r3],r3
ldrd r16,[fp],fp
ldrd r20,[sp],sp
ldrd r10,[ip],r1
ldrd r30,[fp],lr
ldrd r62,[lr],sp
.text
.global ldrdx
ldrdx:
ldrd ip,[ip,ip]
ldrd r58,[r59,r59]
ldrd r28,[r28,r28]
ldrd r26,[r27,r27]
ldrd r12,[sp,sp]
ldrd r32,[fp,r59]
ldrd r4,[r17,r6]
ldrd r32,[r40,r1]
.text
.global ldrdp
ldrdp:
ldrd r16,[sp],sp
ldrd r46,[r33],r30
ldrd r24,[r36],r59
ldrd r58,[r32],r11
.text
.global ldrdd16
ldrdd16:
ldrd ip,[ip,0]
ldrd r4,[r3,7]
ldrd r0,[r0,4]
ldrd r16,[fp,3]
ldrd r18,[sp,1]
ldrd r0,[fp,3]
ldrd lr,[fp,7]
ldrd lr,[ip,1]
.text
.global ldrdd
ldrdd:
ldrd ip,[ip,0]
ldrd r58,[r59,2047]
ldrd r28,[r28,1024]
ldrd r2,[r27,1023]
ldrd r16,[sp,1]
ldrd r4,[r21,761]
ldrd lr,[r41,1553]
ldrd r6,[r14,1922]
.text
.global strbx16
strbx16:
strb ip,[ip,ip]
strb r3,[r3,r3]
strb r0,[r0,r0]
strb fp,[fp,fp]
strb sp,[sp,sp]
strb r1,[lr,r3]
strb ip,[r3,lr]
strb lr,[ip,ip]
.text
.global strbx
strbx:
strb ip,[ip,ip]
strb r59,[r59,r59]
strb r28,[r28,r28]
strb r27,[r27,r27]
strb sp,[sp,sp]
strb r50,[r15,sp]
strb lr,[fp,r52]
strb r14,[r24,r51]
.text
.global strbp16
strbp16:
strb ip,[ip],ip
strb r3,[r3],r3
strb r0,[r0],r0
strb fp,[fp],fp
strb sp,[sp],sp
strb r2,[fp],ip
strb fp,[r0],r1
strb r2,[r2],r3
.text
.global strbp
strbp:
strb ip,[ip],ip
strb r59,[r59],r59
strb r28,[r28],r28
strb r27,[r27],r27
strb sp,[sp],sp
strb r14,[r51],r2
strb r6,[r44],r50
strb r44,[r9],r49
.text
.global strbd16
strbd16:
strb ip,[ip,0]
strb r3,[r3,7]
strb r0,[r0,4]
strb fp,[fp,3]
strb sp,[sp,1]
strb r0,[r2,1]
strb sp,[r2,3]
strb fp,[r2,4]
.text
.global strbd
strbd:
strb ip,[ip,0]
strb r59,[r59,2047]
strb r28,[r28,1024]
strb r27,[r27,1023]
strb sp,[sp,1]
strb r23,[r10,1404]
strb r12,[r35,1461]
strb r54,[r58,1090]
.text
.global strhx16
strhx16:
strh ip,[ip,ip]
strh r3,[r3,r3]
strh r0,[r0,r0]
strh fp,[fp,fp]
strh sp,[sp,sp]
strh r0,[r3,r1]
strh r1,[fp,r2]
strh r3,[r3,fp]
.text
.global strhx
strhx:
strh ip,[ip,ip]
strh r59,[r59,r59]
strh r28,[r28,r28]
strh r27,[r27,r27]
strh sp,[sp,sp]
strh r16,[r38,r31]
strh r32,[r12,r28]
strh r57,[r11,r9]
.text
.global strhp16
strhp16:
strh ip,[ip],ip
strh r3,[r3],r3
strh r0,[r0],r0
strh fp,[fp],fp
strh sp,[sp],sp
strh r0,[r2],sp
strh sp,[r3],r0
strh r1,[r0],r0
.text
.global strhp
strhp:
strh ip,[ip],ip
strh r59,[r59],r59
strh r28,[r28],r28
strh r27,[r27],r27
strh sp,[sp],sp
strh r3,[r37],r54
strh r4,[r54],r25
strh r5,[r32],r25
.text
.global strhd16
strhd16:
strh ip,[ip,0]
strh r3,[r3,7]
strh r0,[r0,4]
strh fp,[fp,3]
strh sp,[sp,1]
strh r3,[r0,3]
strh lr,[ip,7]
strh r3,[r2,7]
.text
.global strhd
strhd:
strh ip,[ip,0]
strh r59,[r59,2047]
strh r28,[r28,1024]
strh r27,[r27,1023]
strh sp,[sp,1]
strh r7,[r38,1181]
strh r25,[r4,77]
strh r11,[fp,631]
.text
.global strx16
strx16:
str ip,[ip,ip]
str r3,[r3,r3]
str r0,[r0,r0]
str fp,[fp,fp]
str sp,[sp,sp]
str lr,[r3,r3]
str r3,[fp,r0]
str ip,[sp,r1]
.text
.global strx
strx:
str ip,[ip,ip]
str r59,[r59,r59]
str r28,[r28,r28]
str r27,[r27,r27]
str sp,[sp,sp]
str r53,[r29,r28]
str r30,[r22,r34]
str r28,[r28,r44]
.text
.global strp16
strp16:
str ip,[ip],ip
str r3,[r3],r3
str r0,[r0],r0
str fp,[fp],fp
str sp,[sp],sp
str lr,[r0],r0
str fp,[r0],sp
str r3,[fp],r0
.text
.global strp
strp:
str ip,[ip],ip
str r59,[r59],r59
str r28,[r28],r28
str r27,[r27],r27
str sp,[sp],sp
str r22,[r36],r15
str r44,[r13],r47
str r19,[r48],sp
.text
.global strd16
strd16:
str ip,[ip,0]
str r3,[r3,7]
str r0,[r0,4]
str fp,[fp,3]
str sp,[sp,1]
str r3,[fp,3]
str sp,[ip,6]
str r1,[lr,3]
.text
.global strd
strd:
str ip,[ip,0]
str r59,[r59,2047]
str r28,[r28,1024]
str r27,[r27,1023]
str sp,[sp,1]
str r45,[r44,74]
str r58,[r50,370]
str r40,[r3,626]
.text
.global strdx16
strdx16:
strd ip,[ip,ip]
strd r2,[r3,r3]
strd r0,[r0,r0]
strd r16,[fp,fp]
strd r18,[sp,sp]
strd ip,[r3,r1]
strd r2,[lr,fp]
strd ip,[r2,r2]
.text
.global strdx
strdx:
strd ip,[ip,ip]
strd r58,[r59,r59]
strd r28,[r28,r28]
strd r26,[r27,r27]
strd r14,[sp,sp]
strd r38,[r53,lr]
strd r24,[r19,r43]
strd r12,[r10,r30]
.text
.global strdp16
strdp16:
strd ip,[ip],ip
strd r2,[r3],r3
strd r0,[r0],r0
strd r6,[fp],fp
strd r4,[sp],sp
strd r2,[r3],r0
strd r2,[r0],r1
strd r2,[lr],r1
.text
.global strdp
strdp:
strd ip,[ip],ip
strd r58,[r59],r59
strd r28,[r28],r28
strd r26,[r27],r27
strd r22,[sp],sp
strd r6,[r10],r44
strd r10,[r43],r5
strd r46,[r17],lr
.text
.global strdd16
strdd16:
strd r0,[ip,0]
strd r2,[r3,7]
strd r0,[r0,4]
strd r2,[fp,3]
strd r4,[sp,1]
strd r2,[r2,5]
strd r6,[r3,7]
strd r6,[r1,2]
.text
.global strdd
strdd:
strd ip,[ip,0]
strd r58,[r59,2047]
strd r28,[r28,1024]
strd r26,[r27,1023]
strd r14,[sp,1]
strd r28,[r52,719]
strd r40,[r53,1994]
strd r44,[r57,494]
.text
.global mov16EQ
mov16EQ:
moveq ip,ip
moveq r3,r3
moveq r0,r0
moveq fp,fp
moveq sp,sp
moveq ip,r2
moveq r2,fp
moveq fp,sp
.text
.global movEQ
movEQ:
moveq ip,ip
moveq r59,r59
moveq r28,r28
moveq r27,r27
moveq sp,sp
moveq r32,r30
moveq r43,r39
moveq r25,r33
.text
.global mov16NE
mov16NE:
movne ip,ip
movne r3,r3
movne r0,r0
movne fp,fp
movne sp,sp
movne r3,r3
movne r0,fp
movne fp,fp
.text
.global movNE
movNE:
movne ip,ip
movne r59,r59
movne r28,r28
movne r27,r27
movne sp,sp
movne r4,r3
movne r28,fp
movne r23,r39
.text
.global mov16GT
mov16GT:
movgt ip,ip
movgt r3,r3
movgt r0,r0
movgt fp,fp
movgt sp,sp
movgt r1,r3
movgt lr,r3
movgt r1,ip
.text
.global movGT
movGT:
movgt ip,ip
movgt r59,r59
movgt r28,r28
movgt r27,r27
movgt sp,sp
movgt r1,r21
movgt r13,r3
movgt r28,r43
.text
.global mov16GTU
mov16GTU:
movgtu ip,ip
movgtu r3,r3
movgtu r0,r0
movgtu fp,fp
movgtu sp,sp
movgtu ip,lr
movgtu sp,ip
movgtu ip,sp
.text
.global movGTU
movGTU:
movgtu ip,ip
movgtu r59,r59
movgtu r28,r28
movgtu r27,r27
movgtu sp,sp
movgtu r34,r33
movgtu r17,r48
movgtu r35,r24
.text
.global mov16GTE
mov16GTE:
movgte ip,ip
movgte r3,r3
movgte r0,r0
movgte fp,fp
movgte sp,sp
movgte r0,r0
movgte r2,sp
movgte lr,r2
.text
.global movGTE
movGTE:
movgte ip,ip
movgte r59,r59
movgte r28,r28
movgte r27,r27
movgte sp,sp
movgte ip,r59
movgte r37,r42
movgte r44,r26
.text
.global mov16GTEU
mov16GTEU:
movgteu ip,ip
movgteu r3,r3
movgteu r0,r0
movgteu fp,fp
movgteu sp,sp
movgteu lr,ip
movgteu sp,r1
movgteu ip,lr
.text
.global movGTEU
movGTEU:
movgteu ip,ip
movgteu r59,r59
movgteu r28,r28
movgteu r27,r27
movgteu sp,sp
movgteu r58,r47
movgteu r56,r5
movgteu r20,r52
.text
.global mov16LT
mov16LT:
movlt ip,ip
movlt r3,r3
movlt r0,r0
movlt fp,fp
movlt sp,sp
movlt r3,r3
movlt r2,r2
movlt ip,lr
.text
.global movLT
movLT:
movlt ip,ip
movlt r59,r59
movlt r28,r28
movlt r27,r27
movlt sp,sp
movlt r52,r12
movlt r57,r22
movlt r8,r7
.text
.global mov16LTU
mov16LTU:
movltu ip,ip
movltu r3,r3
movltu r0,r0
movltu fp,fp
movltu sp,sp
movltu ip,r2
movltu sp,ip
movltu r1,r0
.text
.global movLTU
movLTU:
movltu ip,ip
movltu r59,r59
movltu r28,r28
movltu r27,r27
movltu sp,sp
movltu r13,r31
movltu r43,ip
movltu r7,r56
.text
.global mov16LTE
mov16LTE:
movlte ip,ip
movlte r3,r3
movlte r0,r0
movlte fp,fp
movlte sp,sp
movlte r0,r3
movlte r3,ip
movlte r3,lr
.text
.global movLTE
movLTE:
movlte ip,ip
movlte r59,r59
movlte r28,r28
movlte r27,r27
movlte sp,sp
movlte r30,r27
movlte r35,r52
movlte r15,r53
.text
.global mov16LTEU
mov16LTEU:
movlteu ip,ip
movlteu r3,r3
movlteu r0,r0
movlteu fp,fp
movlteu sp,sp
movlteu ip,lr
movlteu r2,r2
movlteu r2,fp
.text
.global movLTEU
movLTEU:
movlteu ip,ip
movlteu r59,r59
movlteu r28,r28
movlteu r27,r27
movlteu sp,sp
movlteu r31,r36
movlteu r24,r50
movlteu r52,r54
.text
.global mov16B
mov16B:
mov ip,ip
mov r3,r3
mov r0,r0
mov fp,fp
mov sp,sp
mov ip,r1
mov ip,r0
mov r0,ip
.text
.global movB
movB:
mov ip,ip
mov r59,r59
mov r28,r28
mov r27,r27
mov sp,sp
mov r1,r59
mov r28,r12
mov r5,r42
.text
.global mov16BEQ
mov16BEQ:
movbeq ip,ip
movbeq r3,r3
movbeq r0,r0
movbeq fp,fp
movbeq sp,sp
movbeq lr,r2
movbeq fp,r2
movbeq ip,r1
.text
.global movBEQ
movBEQ:
movbeq ip,ip
movbeq r59,r59
movbeq r28,r28
movbeq r27,r27
movbeq sp,sp
movbeq r29,r16
movbeq r18,r46
movbeq lr,r1
.text
.global mov16BNE
mov16BNE:
movbne ip,ip
movbne r3,r3
movbne r0,r0
movbne fp,fp
movbne sp,sp
movbne r1,r2
movbne ip,r1
movbne ip,r3
.text
.global movBNE
movBNE:
movbne ip,ip
movbne r59,r59
movbne r28,r28
movbne r27,r27
movbne sp,sp
movbne r15,r7
movbne r24,r43
movbne r23,r52
.text
.global mov16BLT
mov16BLT:
movblt ip,ip
movblt r3,r3
movblt r0,r0
movblt fp,fp
movblt sp,sp
movblt sp,lr
movblt ip,lr
movblt lr,sp
.text
.global movBLT
movBLT:
movblt ip,ip
movblt r59,r59
movblt r28,r28
movblt r27,r27
movblt sp,sp
movblt r52,r44
movblt r57,r35
movblt r53,r33
.text
.global mov16BLTE
mov16BLTE:
movblte ip,ip
movblte r3,r3
movblte r0,r0
movblte fp,fp
movblte sp,sp
movblte sp,ip
movblte r0,fp
movblte r0,sp
.text
.global movBLTE
movBLTE:
movblte ip,ip
movblte r59,r59
movblte r28,r28
movblte r27,r27
movblte sp,sp
movblte r58,r44
movblte r35,r22
movblte r8,r2
.text
.global movts16
movts16:
movts config,ip
movts ipend,r3
movts iret,r0
movts debug,fp
movts status,sp
movts status,fp
movts pc,fp
movts imask,r0
.text
.global movts
movts:
movts config,ip
movts ipend,r59
movts iret,r28
movts debug,r27
movts status,sp
movts debug,r50
movts ipend,r33
movts status,ip
.text
.global movfs16
movfs16:
movfs ip,config
movfs r3,ipend
movfs r0,iret
movfs fp,debug
movfs sp,status
movfs r1,iret
movfs r2,status
movfs lr,debug
.text
.global movfs
movfs:
movfs ip,config
movfs r59,ipend
movfs r28,iret
movfs r27,debug
movfs sp,status
movfs r13,debug
movfs r15,status
movfs r16,imask
.text
.global nop
nop:
nop
.text
.global idle
idle:
idle
.text
.global bkpt
bkpt:
bkpt
.text
.global rti
rti:
rti
.text
.global trap16
trap16:
trap 0
trap 7
trap 4
trap 3
trap 1
trap 6
trap 3
trap 5
.text
.global add16
add16:
add ip,ip,ip
add r3,r3,r3
add r0,r0,r0
add fp,fp,fp
add sp,sp,sp
add sp,r2,lr
add r0,r2,r1
add ip,fp,fp
.text
.global add
add:
add ip,ip,ip
add r59,r59,r59
add r28,r28,r28
add r27,r27,r27
add sp,sp,sp
add r56,r10,r16
add r36,r25,r34
add r2,r49,r17
.text
.global sub16
sub16:
sub ip,ip,ip
sub r3,r3,r3
sub r0,r0,r0
sub fp,fp,fp
sub sp,sp,sp
sub r2,ip,lr
sub lr,lr,r0
sub r3,r3,r3
.text
.global sub
sub:
sub ip,ip,ip
sub r59,r59,r59
sub r28,r28,r28
sub r27,r27,r27
sub sp,sp,sp
sub ip,lr,r20
sub r48,r22,r47
sub r19,r48,r13
.text
.global and16
and16:
and ip,ip,ip
and r3,r3,r3
and r0,r0,r0
and fp,fp,fp
and sp,sp,sp
and fp,sp,r3
and r3,r3,r3
and ip,sp,sp
.text
.global and
and:
and ip,ip,ip
and r59,r59,r59
and r28,r28,r28
and r27,r27,r27
and sp,sp,sp
and r52,ip,r46
and r44,r40,r44
and r24,r58,r31
.text
.global orr16
orr16:
orr ip,ip,ip
orr r3,r3,r3
orr r0,r0,r0
orr fp,fp,fp
orr sp,sp,sp
orr lr,r1,sp
orr r3,lr,lr
orr r2,r3,r2
.text
.global orr
orr:
orr ip,ip,ip
orr r59,r59,r59
orr r28,r28,r28
orr r27,r27,r27
orr sp,sp,sp
orr r52,r5,r59
orr r15,r32,r43
orr r56,r29,r44
.text
.global eor16
eor16:
eor ip,ip,ip
eor r3,r3,r3
eor r0,r0,r0
eor fp,fp,fp
eor sp,sp,sp
eor ip,r3,r2
eor r3,sp,r2
eor fp,sp,r2
.text
.global eor
eor:
eor ip,ip,ip
eor r59,r59,r59
eor r28,r28,r28
eor r27,r27,r27
eor sp,sp,sp
eor r17,r56,r29
eor sp,r41,r27
eor r11,r10,r43
.text
.global asr16
asr16:
asr ip,ip,ip
asr r3,r3,r3
asr r0,r0,r0
asr fp,fp,fp
asr sp,sp,sp
asr r3,r0,r3
asr r3,r1,lr
asr r0,fp,sp
.text
.global asr
asr:
asr ip,ip,ip
asr r59,r59,r59
asr r28,r28,r28
asr r27,r27,r27
asr sp,sp,sp
asr r34,r9,r25
asr r51,r17,r33
asr ip,r7,r11
.text
.global lsr16
lsr16:
lsr ip,ip,ip
lsr r3,r3,r3
lsr r0,r0,r0
lsr fp,fp,fp
lsr sp,sp,sp
lsr sp,r3,fp
lsr fp,r1,lr
lsr lr,r2,r2
.text
.global lsr
lsr:
lsr ip,ip,ip
lsr r59,r59,r59
lsr r28,r28,r28
lsr r27,r27,r27
lsr sp,sp,sp
lsr r6,r25,r19
lsr r12,r54,r32
lsr r13,sp,ip
.text
.global lsl16
lsl16:
lsl ip,ip,ip
lsl r3,r3,r3
lsl r0,r0,r0
lsl fp,fp,fp
lsl sp,sp,sp
lsl ip,ip,ip
lsl lr,r1,ip
lsl lr,sp,r3
.text
.global lsl
lsl:
lsl ip,ip,ip
lsl r59,r59,r59
lsl r28,r28,r28
lsl r27,r27,r27
lsl sp,sp,sp
lsl r36,r43,r15
lsl r34,r39,r37
lsl r23,r33,r29
.text
.global addi16
addi16:
add ip,ip,0
add r3,r3,7
add r0,r0,4
add fp,fp,3
add sp,sp,1
add r3,r1,1
add r1,fp,3
add r0,fp,7
.text
.global addi
addi:
add ip,ip,0
add r59,r59,1023
add r28,r28,047
add r27,r27,1023
add sp,sp,1
add r49,r28,165
add r31,r2,623
add r16,r9,945
.text
.global subi16
subi16:
sub ip,ip,0
sub r3,r3,7
sub r0,r0,4
sub fp,fp,3
sub sp,sp,1
sub ip,r3,2
sub lr,r3,4
sub ip,r2,1
.text
.global subi
subi:
sub ip,ip,0
sub r59,r59,-2047
sub r28,r28,1023
sub r27,r27,1022
sub sp,sp,1
sub r51,r6,836
sub r47,r40,772
sub r55,r4,488
.text
.global lsri16
lsri16:
lsr ip,ip,0
lsr r3,r3,31
lsr r0,r0,16
lsr fp,fp,15
lsr sp,sp,1
lsr r0,r3,6
lsr r1,r2,8
lsr fp,lr,14
.text
.global lsri32
lsri32:
lsr ip,ip,0
lsr r59,r59,31
lsr r28,r28,16
lsr r27,r27,15
lsr sp,sp,1
lsr r30,r48,19
lsr r43,r7,23
lsr r28,r2,28
.text
.global lsli16
lsli16:
lsl ip,ip,0
lsl r3,r3,31
lsl r0,r0,16
lsl fp,fp,15
lsl sp,sp,1
lsl r2,r3,11
lsl lr,r2,6
lsl r0,r2,16
.text
.global lsli32
lsli32:
lsl ip,ip,0
lsl r59,r59,31
lsl r28,r28,16
lsl r27,r27,15
lsl sp,sp,1
lsl r56,r51,19
lsl r17,r39,19
lsl r2,r12,12
.text
.global asri16
asri16:
asr ip,ip,0
asr r3,r3,31
asr r0,r0,16
asr fp,fp,15
asr sp,sp,1
asr lr,ip,21
asr r3,r3,22
asr r3,r3,9
.text
.global asri32
asri32:
asr ip,ip,0
asr r59,r59,31
asr r28,r28,16
asr r27,r27,15
asr sp,sp,1
asr r52,r46,17
asr r23,r56,22
asr r21,r46,28
.text
.global mov8
mov8:
mov ip,0
mov r3,255
mov r0,128
mov fp,127
mov sp,1
mov lr,91
mov r0,77
mov fp,10
.text
.global mov16
mov16:
mov ip,0
mov r59,65535
mov r28,32768
mov r27,32767
mov sp,1
mov r53,61169
mov r18,52207
mov r16,36386
.text
.global faddf16
faddf16:
fadd ip,ip,ip
fadd r3,r3,r3
fadd r0,r0,r0
fadd fp,fp,fp
fadd sp,sp,sp
fadd sp,ip,r2
fadd sp,r2,r2
fadd sp,lr,fp
.text
.global faddf32
faddf32:
fadd ip,ip,ip
fadd r59,r59,r59
fadd r28,r28,r28
fadd r27,r27,r27
fadd sp,sp,sp
fadd r13,r29,r39
fadd r32,r40,r3
fadd r40,r29,lr
.text
.global fsubf16
fsubf16:
fsub ip,ip,ip
fsub r3,r3,r3
fsub r0,r0,r0
fsub fp,fp,fp
fsub sp,sp,sp
fsub r2,lr,sp
fsub r3,r1,ip
fsub r3,ip,r2
.text
.global fsubf32
fsubf32:
fsub ip,ip,ip
fsub r59,r59,r59
fsub r28,r28,r28
fsub r27,r27,r27
fsub sp,sp,sp
fsub r1,r56,r11
fsub r3,r22,r15
fsub r6,r48,r45
.text
.global fmulf16
fmulf16:
fmul ip,ip,ip
fmul r3,r3,r3
fmul r0,r0,r0
fmul fp,fp,fp
fmul sp,sp,sp
fmul r3,ip,fp
fmul lr,r1,r2
fmul sp,lr,lr
.text
.global fmulf32
fmulf32:
fmul ip,ip,ip
fmul r59,r59,r59
fmul r28,r28,r28
fmul r27,r27,r27
fmul sp,sp,sp
fmul r58,r23,r51
fmul r22,r2,r47
fmul r46,r14,r10
.text
.global fmaddf16
fmaddf16:
fmadd ip,ip,ip
fmadd r3,r3,r3
fmadd r0,r0,r0
fmadd fp,fp,fp
fmadd sp,sp,sp
fmadd sp,r1,r3
fmadd r3,r3,r0
fmadd r2,ip,ip
.text
.global fmaddf32
fmaddf32:
fmadd ip,ip,ip
fmadd r59,r59,r59
fmadd r28,r28,r28
fmadd r27,r27,r27
fmadd sp,sp,sp
fmadd r28,r54,r32
fmadd r12,r2,fp
fmadd fp,r40,r22
.text
.global fmsubf16
fmsubf16:
fmsub ip,ip,ip
fmsub r3,r3,r3
fmsub r0,r0,r0
fmsub fp,fp,fp
fmsub sp,sp,sp
fmsub sp,fp,r1
fmsub r1,fp,sp
fmsub r0,r3,r0
.text
.global fmsubf32
fmsubf32:
fmsub ip,ip,ip
fmsub r59,r59,r59
fmsub r28,r28,r28
fmsub r27,r27,r27
fmsub sp,sp,sp
fmsub r42,r20,r9
fmsub r22,r24,r42
fmsub r15,r22,r19
;; add some negative displacement ld/store
ldr r1,[r2,-12]
strh r22,[r30,-2047]
ldrd r12,[r14,2047]
;; add bitr
bitr r1,r0
bitr r31,r15
|
tactcomplabs/xbgas-binutils-gdb
| 3,752
|
gas/testsuite/gas/mips/mips64-dsp.s
|
# source file to test assembly of MIPS DSP ASE for MIPS64 instructions
.set noreorder
.set nomacro
.set noat
.text
text_label:
absq_s.pw $0,$1
absq_s.qh $30,$31
addq.pw $5,$6,$7
addq_s.pw $6,$7,$8
addq.qh $2,$3,$4
addq_s.qh $3,$4,$5
addu.ob $9,$10,$11
addu_s.ob $10,$11,$12
bposge64 text_label
nop
cmp.eq.pw $20,$21
cmp.lt.pw $21,$22
cmp.le.pw $22,$23
cmp.eq.qh $17,$18
cmp.lt.qh $18,$19
cmp.le.qh $19,$20
cmpu.eq.ob $14,$15
cmpu.lt.ob $15,$16
cmpu.le.ob $16,$17
cmpgu.eq.ob $8,$9,$10
cmpgu.lt.ob $9,$10,$11
cmpgu.le.ob $10,$11,$12
dextpdp $31,$ac3,0
dextpdp $31,$ac3,1
dextpdp $31,$ac3,31
dextpdpv $0,$ac0,$1
dextp $29,$ac1,0
dextp $29,$ac1,1
dextp $29,$ac1,31
dextpv $30,$ac2,$31
dextr.l $3,$ac3,0
dextr.l $3,$ac3,1
dextr.l $3,$ac3,31
dextr_r.l $4,$ac0,0
dextr_r.l $4,$ac0,1
dextr_r.l $4,$ac0,31
dextr_rs.l $5,$ac1,0
dextr_rs.l $5,$ac1,1
dextr_rs.l $5,$ac1,31
dextr_r.w $1,$ac1,0
dextr_r.w $1,$ac1,1
dextr_r.w $1,$ac1,31
dextr_rs.w $2,$ac2,0
dextr_rs.w $2,$ac2,1
dextr_rs.w $2,$ac2,31
dextr_s.h $2,$ac2,0
dextr_s.h $2,$ac2,1
dextr_s.h $2,$ac2,31
dextr.w $0,$ac0,0
dextr.w $0,$ac0,1
dextr.w $0,$ac0,31
dextrv.w $11,$ac3,$12
dextrv_r.w $12,$ac0,$13
dextrv_rs.w $13,$ac1,$14
dextrv.l $14,$ac2,$15
dextrv_r.l $15,$ac3,$16
dextrv_rs.l $16,$ac0,$17
dinsv $26,$27
dmadd $ac1,$20,$21
dmaddu $ac2,$21,$22
dmsub $ac3,$22,$23
dmsubu $ac0,$23,$24
dmthlip $4,$ac2
dpaq_sa.l.pw $ac1,$0,$1
dpaq_s.w.qh $ac2,$21,$22
dpau.h.obl $ac0,$15,$16
dpau.h.obr $ac1,$16,$17
dpsq_sa.l.pw $ac0,$3,$4
dpsq_s.w.qh $ac1,$24,$25
dpsu.h.obl $ac2,$17,$18
dpsu.h.obr $ac3,$18,$19
dshilo $ac3,-64
dshilo $ac3,63
dshilov $ac0,$2
ldx $16,$17($18)
maq_sa.w.qhll $ac3,$10,$11
maq_sa.w.qhlr $ac0,$11,$12
maq_sa.w.qhrl $ac1,$12,$13
maq_sa.w.qhrr $ac2,$13,$14
maq_s.l.pwl $ac1,$16,$17
maq_s.l.pwr $ac2,$17,$18
maq_s.w.qhll $ac3,$10,$11
maq_s.w.qhlr $ac0,$11,$12
maq_s.w.qhrl $ac1,$12,$13
maq_s.w.qhrr $ac2,$13,$14
muleq_s.pw.qhl $11,$12,$13
muleq_s.pw.qhr $12,$13,$14
muleu_s.qh.obl $4,$5,$6
muleu_s.qh.obr $5,$6,$7
mulq_rs.ph $6,$7,$8
mulq_rs.qh $8,$9,$10
mulsaq_s.w.qh $ac0,$27,$28
mulsaq_s.l.pw $ac2,$29,$30
packrl.pw $28,$29,$30
pick.ob $25,$26,$27
pick.qh $26,$27,$28
pick.pw $27,$28,$29
preceq.pw.qhl $14,$15
preceq.pw.qhr $15,$16
preceq.pw.qhla $16,$17
preceq.pw.qhra $17,$18
preceq.s.l.pwl $18,$19
preceq.s.l.pwr $19,$20
precequ.pw.qhl $24,$25
precequ.pw.qhr $25,$26
precequ.pw.qhla $26,$27
precequ.pw.qhra $27,$28
preceu.qh.obl $28,$29
preceu.qh.obr $29,$30
preceu.qh.obla $30,$31
preceu.qh.obra $31,$0
precrq.ob.qh $4,$5,$6
precrq.pw.l $7,$8,$9
precrq.qh.pw $5,$6,$7
precrq_rs.qh.pw $6,$7,$8
precrqu_s.ob.qh $9,$10,$11
raddu.l.ob $26,$27
repl.ob $29,0
repl.ob $29,255
replv.ob $30,$31
repl.qh $1,-512
repl.qh $1,511
replv.qh $2,$3
repl.pw $3,-512
repl.pw $3,511
replv.pw $4,$5
shll.ob $2,$3,0
shll.ob $2,$3,7
shllv.ob $3,$4,$5
shll.qh $8,$9,0
shll.qh $8,$9,15
shllv.qh $9,$10,$11
shll_s.qh $10,$11,0
shll_s.qh $10,$11,15
shllv_s.qh $11,$12,$13
shll.pw $14,$15,0
shll.pw $14,$15,31
shllv.pw $15,$16,$17
shll_s.pw $16,$17,0
shll_s.pw $16,$17,31
shllv_s.pw $17,$18,$19
shra.qh $28,$29,0
shra.qh $28,$29,15
shrav.qh $29,$30,$31
shra_r.qh $30,$31,0
shra_r.qh $30,$31,15
shrav_r.qh $31,$0,$1
shra.pw $0,$1,0
shra.pw $0,$1,31
shrav.pw $1,$2,$3
shra_r.pw $2,$3,0
shra_r.pw $2,$3,31
shrav_r.pw $3,$4,$5
shrl.ob $20,$21,0
shrl.ob $20,$21,7
shrlv.ob $21,$22,$23
subq.qh $16,$17,$18
subq_s.qh $17,$18,$19
subq.pw $18,$19,$20
subq_s.pw $19,$20,$21
subu.ob $20,$21,$22
subu_s.ob $21,$22,$23
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 4,857
|
gas/testsuite/gas/mips/vr4130.s
|
.macro check2 insn
mflo $2
\insn $3,$3
.endm
.macro check3 insn
mfhi $2
\insn $0,$3,$3
.endm
.macro main func
.ent \func
.type \func,@function
\func:
# PART A
#
# Check that mfhis and mflos in .set noreorder blocks are considered.
.set noreorder
mfhi $2
.set reorder
mult $3,$3
.set noreorder
mflo $2
.set reorder
mult $3,$3
# PART B
#
# Check for simple instances.
mfhi $2
mult $3,$3 # 4 nops
mfhi $2
addiu $3,1
mult $4,$4 # 3 nops
mfhi $2
addiu $3,1
addiu $4,1
mult $5,$5 # 2 nops
mfhi $2
addiu $3,1
addiu $4,1
addiu $5,1
mult $6,$6 # 1 nop
mfhi $2
addiu $3,1
addiu $4,1
addiu $5,1
addiu $6,1
mult $7,$7 # 0 nops
mfhi $2
.set noreorder
mult $3,$3 # 4 nops
.set reorder
mfhi $2
.set noreorder
addiu $3,1
mult $4,$4 # 3 nops before noreorder
.set reorder
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
mult $5,$5 # 2 nops before noreorder
.set reorder
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
addiu $5,1
mult $6,$6 # 1 nop before noreorder
.set reorder
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
addiu $5,1
addiu $6,1
mult $7,$7 # 0 nops
.set reorder
# PART C
#
# Check that no nops are inserted after the result has been read.
mfhi $2
addiu $2,1
addiu $3,1
addiu $4,1
mult $5,$5
mfhi $2
addiu $3,1
addiu $2,1
addiu $4,1
mult $5,$5
mfhi $2
addiu $3,1
addiu $4,1
addiu $2,1
mult $5,$5
mfhi $2
addiu $3,1
addiu $4,1
addiu $5,1
mult $2,$2
mfhi $2
.set noreorder
addiu $2,1
addiu $3,1
addiu $4,1
mult $5,$5
.set reorder
mfhi $2
.set noreorder
addiu $3,1
addiu $2,1
addiu $4,1
mult $5,$5
.set reorder
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
addiu $2,1
mult $5,$5
.set reorder
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
addiu $5,1
mult $2,$2
.set reorder
# PART D
#
# Check that we still insert the usual interlocking nops in cases
# where the VR4130 errata doesn't apply.
mfhi $2
mult $2,$2 # 2 nops
mfhi $2
addiu $2,1
mult $3,$3 # 1 nop
mfhi $2
addiu $3,1
mult $2,$2 # 1 nop
# PART E
#
# Check for branches whose targets might be affected.
mfhi $2
bnez $3,1f # 2 nops for normal mode, 3 for mips16
mfhi $2
addiu $3,1
bnez $3,1f # 1 nop for normal mode, 2 for mips16
mfhi $2
addiu $3,1
addiu $3,1
bnez $3,1f # 0 nops for normal mode, 1 for mips16
mfhi $2
addiu $3,1
addiu $3,1
addiu $3,1
bnez $3,1f # 0 nops
# PART F
#
# As above, but with no dependencies between the branch and
# the previous instruction. The final branch can use the
# preceding addiu as its delay slot.
mfhi $2
addiu $3,1
bnez $4,1f # 1 nop for normal mode, 2 for mips16
mfhi $2
addiu $3,1
addiu $4,1
bnez $5,1f # 0 nops for normal mode, 1 for mips16
mfhi $2
addiu $3,1
addiu $4,1
addiu $5,1
bnez $6,1f # 0 nops, fill delay slot in normal mode
1:
# PART G
#
# Like part B, but check that intervening .set noreorders don't
# affect the number of nops.
mfhi $2
.set noreorder
addiu $3,1
.set reorder
mult $4,$4 # 3 nops
mfhi $2
.set noreorder
addiu $3,1
.set reorder
addiu $4,1
mult $5,$5 # 2 nops
mfhi $2
addiu $3,1
.set noreorder
addiu $4,1
.set reorder
mult $5,$5 # 2 nops
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
.set reorder
mult $5,$5 # 2 nops
mfhi $2
addiu $3,1
.set noreorder
addiu $4,1
.set reorder
addiu $5,1
mult $6,$6 # 1 nop
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
addiu $5,1
.set reorder
mult $6,$6 # 1 nop
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
addiu $5,1
addiu $6,1
.set reorder
mult $7,$7 # 0 nops
# PART H
#
# Like part B, but the mult occurs in a .set noreorder block.
mfhi $2
.set noreorder
mult $3,$3 # 4 nops
.set reorder
mfhi $2
.set noreorder
addiu $3,1
mult $4,$4 # 3 nops
.set reorder
mfhi $2
addiu $3,1
.set noreorder
addiu $4,1
mult $5,$5 # 2 nops
.set reorder
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
addiu $5,1
mult $6,$6 # 1 nop
.set reorder
mfhi $2
.set noreorder
addiu $3,1
addiu $4,1
addiu $5,1
addiu $6,1
mult $7,$7 # 0 nops
.set reorder
# PART I
#
# Check every affected multiplication and division instruction.
check2 mult
check2 multu
check2 dmult
check2 dmultu
check3 div
check3 divu
check3 ddiv
check3 ddivu
.end \func
.endm
.set nomips16
main foo
# PART J
#
# Check every affected multiply-accumulate instruction.
check3 macc
check3 macchi
check3 macchis
check3 macchiu
check3 macchius
check3 maccs
check3 maccu
check3 maccus
check3 dmacc
check3 dmacchi
check3 dmacchis
check3 dmacchiu
check3 dmacchius
check3 dmaccs
check3 dmaccu
check3 dmaccus
# PART K
#
# Check that mtlo and mthi are exempt from the VR4130 errata,
# although the usual interlocking delay applies.
mflo $2
mtlo $3
mflo $2
mthi $3
mfhi $2
mtlo $3
mfhi $2
mthi $3
.set mips16
main bar
|
tactcomplabs/xbgas-binutils-gdb
| 1,323
|
gas/testsuite/gas/mips/unaligned-jump-mips16-1.s
|
.text
.set noreorder
.space 0x1000
.align 4
.set mips16
.ent foo
foo:
not $2, $2
jalx bar0
not $2, $2
jal bar0
not $2, $2
jalx bar1
not $2, $2
jal bar1
not $2, $2
jalx bar2
not $2, $2
jal bar2
not $2, $2
jalx bar3
not $2, $2
jal bar3
not $2, $2
jalx bar4
not $2, $2
jal bar4
not $2, $2
jalx bar4 + 1
not $2, $2
jal bar4 + 1
not $2, $2
jalx bar4 + 2
not $2, $2
jal bar4 + 2
not $2, $2
jalx bar4 + 3
not $2, $2
jal bar4 + 3
not $2, $2
jalx bar4 + 4
not $2, $2
jal bar4 + 4
not $2, $2
jalx bar16
not $2, $2
jal bar16
not $2, $2
jalx bar17
not $2, $2
jal bar17
not $2, $2
jalx bar18
not $2, $2
jal bar18
not $2, $2
jalx bar18 + 1
not $2, $2
jal bar18 + 1
not $2, $2
jalx bar18 + 2
not $2, $2
jal bar18 + 2
not $2, $2
jalx bar18 + 3
not $2, $2
jal bar18 + 3
not $2, $2
jalx bar18 + 4
not $2, $2
jal bar18 + 4
not $2, $2
jr $ra
not $2, $2
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 6,603
|
gas/testsuite/gas/mips/r6.s
|
.text
.set reorder
new: maddf.s $f0,$f1,$f2
maddf.d $f3,$f4,$f5
msubf.s $f6,$f7,$f8
msubf.d $f9,$f10,$f11
cmp.af.s $f0,$f1,$f2
cmp.af.d $f0,$f1,$f2
cmp.un.s $f0,$f1,$f2
cmp.un.d $f0,$f1,$f2
cmp.eq.s $f0,$f1,$f2
cmp.eq.d $f0,$f1,$f2
cmp.ueq.s $f0,$f1,$f2
cmp.ueq.d $f0,$f1,$f2
cmp.lt.s $f0,$f1,$f2
cmp.lt.d $f0,$f1,$f2
cmp.ult.s $f0,$f1,$f2
cmp.ult.d $f0,$f1,$f2
cmp.le.s $f0,$f1,$f2
cmp.le.d $f0,$f1,$f2
cmp.ule.s $f0,$f1,$f2
cmp.ule.d $f0,$f1,$f2
cmp.saf.s $f0,$f1,$f2
cmp.saf.d $f0,$f1,$f2
cmp.sun.s $f0,$f1,$f2
cmp.sun.d $f0,$f1,$f2
cmp.seq.s $f0,$f1,$f2
cmp.seq.d $f0,$f1,$f2
cmp.sueq.s $f0,$f1,$f2
cmp.sueq.d $f0,$f1,$f2
cmp.slt.s $f0,$f1,$f2
cmp.slt.d $f0,$f1,$f2
cmp.sult.s $f0,$f1,$f2
cmp.sult.d $f0,$f1,$f2
cmp.sle.s $f0,$f1,$f2
cmp.sle.d $f0,$f1,$f2
cmp.sule.s $f0,$f1,$f2
cmp.sule.d $f0,$f1,$f2
cmp.or.s $f0,$f1,$f2
cmp.or.d $f0,$f1,$f2
cmp.une.s $f0,$f1,$f2
cmp.une.d $f0,$f1,$f2
cmp.ne.s $f0,$f1,$f2
cmp.ne.d $f0,$f1,$f2
cmp.sor.s $f0,$f1,$f2
cmp.sor.d $f0,$f1,$f2
cmp.sune.s $f0,$f1,$f2
cmp.sune.d $f0,$f1,$f2
cmp.sne.s $f0,$f1,$f2
cmp.sne.d $f0,$f1,$f2
bc1eqz $f0,1f
bc1eqz $f31,1f
bc1eqz $f31,new
bc1eqz $f31,external_label
bc1nez $f0,1f
bc1nez $f31,1f
bc1nez $f31,new
bc1nez $f31,external_label
bc2eqz $0,1f
bc2eqz $31,1f
bc2eqz $31,new
bc2eqz $31,external_label
bc2nez $0,1f
bc2nez $31,1f
bc2nez $31,new
bc2nez $31,external_label
1: sel.s $f0,$f1,$f2
sel.d $f0,$f1,$f2
seleqz.s $f0,$f1,$f2
seleqz.d $f0,$f1,$f2
selnez.s $f0,$f1,$f2
selnez.d $f0,$f1,$f2
seleqz $2,$3,$4
selnez $2,$3,$4
mul $2,$3,$4
muh $2,$3,$4
mulu $2,$3,$4
muhu $2,$3,$4
div $2,$3,$4
mod $2,$3,$4
divu $2,$3,$4
modu $2,$3,$4
lwc2 $2,0($4)
lwc2 $2,-1024($4)
lwc2 $2,1023($4)
swc2 $2,0($4)
swc2 $2,-1024($4)
swc2 $2,1023($4)
ldc2 $2,0($4)
ldc2 $2,-1024($4)
ldc2 $2,1023($4)
sdc2 $2,0($4)
sdc2 $2,-1024($4)
sdc2 $2,1023($4)
lsa $2,$3,$4,1
lsa $2,$3,$4,4
clz $2,$3
clo $2,$3
sdbbp
sdbbp 0
sdbbp 1
sdbbp 1048575
lui $2,0xffff
pref 0, -256($0)
pref 31, 255($31)
ll $2,-256($3)
ll $2,255($3)
sc $2,-256($3)
sc $2,255($3)
cache 0,-256($3)
cache 31,255($3)
align $4, $2, $3, 0
align $4, $2, $3, 1
align $4, $2, $3, 2
align $4, $2, $3, 3
bitswap $4, $2
bovc $0, $0, ext
bovc $2, $0, ext
bovc $0, $2, ext
bovc $2, $4, ext
bovc $4, $2, ext
bovc $2, $4, . + 4 + (-32768 << 2)
bovc $2, $4, . + 4 + (32767 << 2)
bovc $2, $4, 1f
bovc $2, $2, ext
bovc $2, $2, . + 4 + (-32768 << 2)
beqzalc $2, ext
beqzalc $2, . + 4 + (-32768 << 2)
beqzalc $2, . + 4 + (32767 << 2)
beqzalc $2, 1f
beqc $3, $2, ext
beqc $2, $3, ext
beqc $3, $2, . + 4 + (-32768 << 2)
beqc $3, $2, . + 4 + (32767 << 2)
beqc $3, $2, 1f
bnvc $0, $0, ext
bnvc $2, $0, ext
bnvc $0, $2, ext
bnvc $2, $4, ext
bnvc $4, $2, ext
bnvc $2, $4, . + 4 + (-32768 << 2)
bnvc $2, $4, . + 4 + (32767 << 2)
bnvc $2, $4, 1f
bnvc $2, $2, ext
bnvc $2, $2, . + 4 + (-32768 << 2)
bnezalc $2, ext
bnezalc $2, . + 4 + (-32768 << 2)
bnezalc $2, . + 4 + (32767 << 2)
bnezalc $2, 1f
bnec $3, $2, ext
bnec $2, $3, ext
bnec $3, $2, . + 4 + (-32768 << 2)
bnec $3, $2, . + 4 + (32767 << 2)
bnec $3, $2, 1f
blezc $2, ext
blezc $2, . + 4 + (-32768 << 2)
blezc $2, . + 4 + (32767 << 2)
blezc $2, 1f
bgezc $2, ext
bgezc $2, . + 4 + (-32768 << 2)
bgezc $2, . + 4 + (32767 << 2)
bgezc $2, 1f
bgec $2, $3, ext
bgec $2, $3, . + 4 + (-32768 << 2)
bgec $2, $3, . + 4 + (32767 << 2)
bgec $2, $3, 1f
bgec $3, $2, 1f
bgtzc $2, ext
bgtzc $2, . + 4 + (-32768 << 2)
bgtzc $2, . + 4 + (32767 << 2)
bgtzc $2, 1f
bltzc $2, ext
bltzc $2, . + 4 + (-32768 << 2)
bltzc $2, . + 4 + (32767 << 2)
bltzc $2, 1f
bltc $2, $3, ext
bltc $2, $3, . + 4 + (-32768 << 2)
bltc $2, $3, . + 4 + (32767 << 2)
bltc $2, $3, 1f
bltc $3, $2, 1f
blezalc $2, ext
blezalc $2, . + 4 + (-32768 << 2)
blezalc $2, . + 4 + (32767 << 2)
blezalc $2, 1f
bgezalc $2, ext
bgezalc $2, . + 4 + (-32768 << 2)
bgezalc $2, . + 4 + (32767 << 2)
bgezalc $2, 1f
bgeuc $2, $3, ext
bgeuc $2, $3, . + 4 + (-32768 << 2)
bgeuc $2, $3, . + 4 + (32767 << 2)
bgeuc $2, $3, 1f
bgeuc $3, $2, 1f
bgtzalc $2, ext
bgtzalc $2, . + 4 + (-32768 << 2)
bgtzalc $2, . + 4 + (32767 << 2)
bgtzalc $2, 1f
bltzalc $2, ext
bltzalc $2, . + 4 + (-32768 << 2)
bltzalc $2, . + 4 + (32767 << 2)
bltzalc $2, 1f
bltuc $2, $3, ext
bltuc $2, $3, . + 4 + (-32768 << 2)
bltuc $2, $3, . + 4 + (32767 << 2)
bltuc $2, $3, 1f
bltuc $3, $2, 1f
bc ext
bc . + 4 + (-33554432 << 2)
bc . + 4 + (33554431 << 2)
bc 1f
balc ext
balc . + 4 + (-33554432 << 2)
balc . + 4 + (33554431 << 2)
balc 1f
beqzc $2, ext
beqzc $2, . + 4 + (-1048576 << 2)
beqzc $2, . + 4 + (1048575 << 2)
beqzc $2, 1f
jic $3,-32768
jic $3,32767
jrc $31
bnezc $2, ext
bnezc $2, . + 4 + (-1048576 << 2)
bnezc $2, . + 4 + (1048575 << 2)
bnezc $2, 1f
jialc $3,-32768
jialc $3,32767
aui $3, $2, 0xffff
lapc $3, 1f
lapc $4, .+(-262144 << 2)
lapc $4, .+(262143 << 2)
addiupc $4, (-262144 << 2)
addiupc $4, (262143 << 2)
auipc $3, 0xffff
aluipc $3, 0xffff
lwpc $4, 1f
lwpc $4, .+(-262144 << 2)
lwpc $4, .+(262143 << 2)
lw $4, (-262144 << 2)($pc)
lw $4, (262143 << 2)($pc)
1:
nop
addiu $4, $pc, (262143 << 2)
jalrc $4
nal
evp
dvp
evp $2
dvp $2
sigrie 0
sigrie 0xffff
llwp $5, $4, $6
scwp $5, $4, $6
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,121
|
gas/testsuite/gas/mips/loongson-3a-2.s
|
.text
.set noreorder
gsle $11,$12
gsgt $13,$14
gslble $2,$3,$4
gslbgt $5,$6,$7
gslhle $8,$9,$10
gslhgt $11,$12,$13
gslwle $14,$15,$16
gslwgt $17,$18,$19
gsldle $20,$21,$22
gsldgt $23,$24,$25
gssble $2,$3,$4
gssbgt $5,$6,$7
gsshle $8,$9,$10
gsshgt $11,$12,$13
gsswle $14,$15,$16
gsswgt $17,$18,$19
gssdle $20,$21,$22
gssdgt $23,$24,$25
gslwlec1 $f0,$2,$3
gslwgtc1 $f1,$4,$5
gsldlec1 $f2,$6,$7
gsldgtc1 $f3,$8,$9
gsswlec1 $f4,$10,$11
gsswgtc1 $f5,$12,$13
gssdlec1 $f6,$14,$15
gssdgtc1 $f7,$16,$17
gslwlc1 $f8,0($18)
gslwrc1 $f9,1($19)
gsldlc1 $f10,2($20)
gsldrc1 $f11,3($21)
gsswlc1 $f12,4($22)
gsswrc1 $f13,5($23)
gssdlc1 $f14,6($24)
gssdrc1 $f15,7($25)
gslbx $2,0($3,$4)
gslhx $5,-1($6,$7)
gslwx $8,-2($9,$10)
gsldx $11,-3($12,$13)
gssbx $14,-4($15,$16)
gsshx $17,-5($18,$19)
gsswx $20,-6($21,$22)
gssdx $23,-7($24,$25)
gslwxc1 $f16,127($2,$3)
gsldxc1 $f17,-128($4,$5)
gsswxc1 $f18,127($6,$7)
gssdxc1 $f19,-128($8,$9)
gslq $10,$11,4080($12)
gssq $13,$14,-4096($15)
gslqc1 $f20,$f21,4080($16)
gssqc1 $f22,$f23,-4096($17)
|
tactcomplabs/xbgas-binutils-gdb
| 1,268
|
gas/testsuite/gas/mips/pcrel-reloc-4.s
|
.text
.ifdef reverse
.ent baz
baz:
jalr $0, $ra
.end baz
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 16, 0
.space 16
.ent bar
bar:
jalr $0, $ra
.end bar
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.endif
.align 4, 0
.globl foo
.ent foo
.set noreorder
foo:
b bar
b bar
b bar
b bar
.set mips64r6
bc bar
bc bar
bc bar
bc bar
beqzc $2, bar
beqzc $2, bar
beqzc $2, bar
beqzc $2, bar
lwpc $2, bar
lwpc $2, bar
lwpc $2, bar
lwpc $2, bar
ldpc $2, bar
ldpc $2, bar
ldpc $2, bar
ldpc $2, bar
auipc $2, %pcrel_hi(baz)
addiu $2, %pcrel_lo(baz + 4)
auipc $2, %pcrel_hi(baz)
addiu $2, %pcrel_lo(baz + 4)
auipc $2, %pcrel_hi(baz)
addiu $2, %pcrel_lo(baz + 4)
auipc $2, %pcrel_hi(baz)
addiu $2, %pcrel_lo(baz + 4)
.set mips0
.set reorder
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.ifndef reverse
.ent bar
bar:
jalr $0, $ra
.end bar
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 16, 0
.space 16
.ent baz
baz:
jalr $0, $ra
.end baz
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.endif
|
tactcomplabs/xbgas-binutils-gdb
| 1,854
|
gas/testsuite/gas/mips/uld.s
|
# Source file used to test the uld macro.
.data
data_label:
.extern big_external_data_label,1000
.extern small_external_data_label,1
.comm big_external_common,1000
.comm small_external_common,1
.lcomm big_local_common,1000
.lcomm small_local_common,1
.text
uld $4,0
uld $4,1
uld $4,0x8000
uld $4,-0x8000
uld $4,0x10000
uld $4,0x1a5a5
uld $4,0($5)
uld $4,1($5)
uld $4,data_label
uld $4,big_external_data_label
uld $4,small_external_data_label
uld $4,big_external_common
uld $4,small_external_common
uld $4,big_local_common
uld $4,small_local_common
uld $4,data_label+1
uld $4,big_external_data_label+1
uld $4,small_external_data_label+1
uld $4,big_external_common+1
uld $4,small_external_common+1
uld $4,big_local_common+1
uld $4,small_local_common+1
uld $4,data_label+0x8000
uld $4,big_external_data_label+0x8000
uld $4,small_external_data_label+0x8000
uld $4,big_external_common+0x8000
uld $4,small_external_common+0x8000
uld $4,big_local_common+0x8000
uld $4,small_local_common+0x8000
uld $4,data_label-0x8000
uld $4,big_external_data_label-0x8000
uld $4,small_external_data_label-0x8000
uld $4,big_external_common-0x8000
uld $4,small_external_common-0x8000
uld $4,big_local_common-0x8000
uld $4,small_local_common-0x8000
uld $4,data_label+0x10000
uld $4,big_external_data_label+0x10000
uld $4,small_external_data_label+0x10000
uld $4,big_external_common+0x10000
uld $4,small_external_common+0x10000
uld $4,big_local_common+0x10000
uld $4,small_local_common+0x10000
uld $4,data_label+0x1a5a5
uld $4,big_external_data_label+0x1a5a5
uld $4,small_external_data_label+0x1a5a5
uld $4,big_external_common+0x1a5a5
uld $4,small_external_common+0x1a5a5
uld $4,big_local_common+0x1a5a5
uld $4,small_local_common+0x1a5a5
# Round to a 16 byte boundary, for ease in testing multiple targets.
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,966
|
gas/testsuite/gas/mips/loongson-2f-mmi.s
|
.text
.set noreorder
simd_insns:
packsshb $f0, $f1, $f2
packsswh $f3, $f4, $f5
packushb $f6, $f7, $f8
paddb $f9, $f10, $f11
paddh $f12, $f13, $f14
paddw $f15, $f16, $f17
paddd $f18, $f19, $f20
paddsb $f21, $f22, $f23
paddsh $f24, $f25, $f26
paddusb $f27, $f28, $f29
paddush $f0, $f1, $f2
pandn $f3, $f4, $f5
pavgb $f6, $f7, $f8
pavgh $f9, $f10, $f11
pcmpeqb $f12, $f13, $f14
pcmpeqh $f15, $f16, $f17
pcmpeqw $f18, $f19, $f20
pcmpgtb $f21, $f22, $f23
pcmpgth $f24, $f25, $f26
pcmpgtw $f27, $f28, $f29
pextrh $f0, $f1, $f2
pinsrh_0 $f3, $f4, $f5
pinsrh_1 $f6, $f7, $f8
pinsrh_2 $f9, $f10, $f11
pinsrh_3 $f12, $f13, $f14
pmaddhw $f15, $f16, $f17
pmaxsh $f18, $f19, $f20
pmaxub $f21, $f22, $f23
pminsh $f24, $f25, $f26
pminub $f27, $f28, $f29
pmovmskb $f0, $f1
pmulhuh $f2, $f3, $f4
pmulhh $f5, $f6, $f7
pmullh $f8, $f9, $f10
pmuluw $f11, $f12, $f13
pasubub $f14, $f15, $f16
biadd $f17, $f18
pshufh $f19, $f20, $f21
psllh $f22, $f23, $f24
psllw $f25, $f26, $f27
psrah $f28, $f29, $f30
psraw $f0, $f1, $f2
psrlh $f3, $f4, $f5
psrlw $f6, $f7, $f8
psubb $f9, $f10, $f11
psubh $f12, $f13, $f14
psubw $f15, $f16, $f17
psubd $f18, $f19, $f20
psubsb $f21, $f22, $f23
psubsh $f24, $f25, $f26
psubusb $f27, $f28, $f29
psubush $f0, $f1, $f2
punpckhbh $f3, $f4, $f5
punpckhhw $f6, $f7, $f8
punpckhwd $f9, $f10, $f11
punpcklbh $f12, $f13, $f14
punpcklhw $f15, $f16, $f17
punpcklwd $f18, $f19, $f20
fixed_point_insns:
add $f0, $f1, $f2
addu $f3, $f4, $f5
dadd $f6, $f7, $f8
sub $f9, $f10, $f11
subu $f12, $f13, $f14
dsub $f15, $f16, $f17
or $f18, $f19, $f20
sll $f21, $f22, $f23
dsll $f24, $f25, $f26
xor $f27, $f28, $f29
nor $f0, $f1, $f2
and $f3, $f4, $f5
srl $f6, $f7, $f8
dsrl $f9, $f10, $f11
sra $f12, $f13, $f14
dsra $f15, $f16, $f17
sequ $f18, $f19
sltu $f20, $f21
sleu $f22, $f23
seq $f24, $f25
slt $f26, $f27
sle $f28, $f29
|
tactcomplabs/xbgas-binutils-gdb
| 1,029
|
gas/testsuite/gas/mips/mips32-cp2.s
|
# source file to test assembly of mips32 cop2 instructions
.set noreorder
.set noat
.text
text_label:
# unprivileged coprocessor instructions.
# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
.ifndef r6
bc2f text_label
nop
bc2fl text_label
nop
bc2t text_label
nop
bc2tl text_label
nop
.endif
# XXX other BCzCond encodings not currently expressable
cfc2 $1, $2
cop2 0x1234567 # disassembles as c2 ...
ctc2 $2, $3
mfc2 $3, $4
mfc2 $4, $5, 0 # disassembles without sel
mfc2 $5, $6, 7
mtc2 $6, $7
mtc2 $7, $8, 0 # disassembles without sel
mtc2 $8, $9, 7
.ifndef r6
# Cop2 branches with cond code number, like bc1t/f
bc2f $cc0,text_label
nop
bc2fl $cc1,text_label
nop
bc2t $cc6,text_label
nop
bc2tl $cc7,text_label
nop
.endif
|
tactcomplabs/xbgas-binutils-gdb
| 43,124
|
gas/testsuite/gas/mips/mips16-intermix.s
|
.text
.align 2
.globl m32_l
.set nomips16
.ent m32_l
m32_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m32_l
.align 2
.globl m16_l
.set mips16
.ent m16_l
m16_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m16_l
.align 2
.set nomips16
.ent m32_static_l
m32_static_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m32_static_l
.align 2
.set mips16
.ent m16_static_l
m16_static_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m16_static_l
.align 2
.set nomips16
.ent m32_static1_l
m32_static1_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m32_static1_l
.align 2
.set mips16
.ent m16_static1_l
m16_static1_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m16_static1_l
.align 2
.set nomips16
.ent m32_static32_l
m32_static32_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m32_static32_l
.align 2
.set mips16
.ent m16_static32_l
m16_static32_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m16_static32_l
.align 2
.set nomips16
.ent m32_static16_l
m32_static16_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m32_static16_l
.align 2
.set mips16
.ent m16_static16_l
m16_static16_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
move $2,$4
.set macro
.set reorder
.end m16_static16_l
.align 2
.globl m32_d
.set nomips16
.ent m32_d
m32_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f12,$f12
j $31
mfc1 $2,$f12
.set macro
.set reorder
.end m32_d
.align 2
.globl m16_d
.set mips16
.ent m16_d
m16_d:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_fixdfsi
restore 24,$31
j $31
.end m16_d
# Stub function for m16_d (double)
.set nomips16
.section .mips16.fn.m16_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_d
__fn_stub_m16_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_d
.previous
.align 2
.set nomips16
.ent m32_static_d
m32_static_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f12,$f12
j $31
mfc1 $2,$f12
.set macro
.set reorder
.end m32_static_d
.align 2
.set mips16
.ent m16_static_d
m16_static_d:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_fixdfsi
restore 24,$31
j $31
.end m16_static_d
# Stub function for m16_static_d (double)
.set nomips16
.section .mips16.fn.m16_static_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_static_d
__fn_stub_m16_static_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static_d
.previous
.align 2
.set nomips16
.ent m32_static1_d
m32_static1_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f12,$f12
j $31
mfc1 $2,$f12
.set macro
.set reorder
.end m32_static1_d
.align 2
.set mips16
.ent m16_static1_d
m16_static1_d:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_fixdfsi
restore 24,$31
j $31
.end m16_static1_d
# Stub function for m16_static1_d (double)
.set nomips16
.section .mips16.fn.m16_static1_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_static1_d
__fn_stub_m16_static1_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static1_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static1_d
.previous
.align 2
.set nomips16
.ent m32_static32_d
m32_static32_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f12,$f12
j $31
mfc1 $2,$f12
.set macro
.set reorder
.end m32_static32_d
.align 2
.set mips16
.ent m16_static32_d
m16_static32_d:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_fixdfsi
restore 24,$31
j $31
.end m16_static32_d
# Stub function for m16_static32_d (double)
.set nomips16
.section .mips16.fn.m16_static32_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_static32_d
__fn_stub_m16_static32_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static32_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static32_d
.previous
.align 2
.set nomips16
.ent m32_static16_d
m32_static16_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f12,$f12
j $31
mfc1 $2,$f12
.set macro
.set reorder
.end m32_static16_d
.align 2
.set mips16
.ent m16_static16_d
m16_static16_d:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_fixdfsi
restore 24,$31
j $31
.end m16_static16_d
# Stub function for m16_static16_d (double)
.set nomips16
.section .mips16.fn.m16_static16_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_static16_d
__fn_stub_m16_static16_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static16_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static16_d
.previous
.align 2
.globl m32_ld
.set nomips16
.ent m32_ld
m32_ld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $7,$f2
mtc1 $6,$f3
trunc.w.d $f0,$f2
mfc1 $24,$f0
j $31
addu $2,$24,$4
.set macro
.set reorder
.end m32_ld
.align 2
.globl m16_ld
.set mips16
.ent m16_ld
m16_ld:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
move $16,$4
move $5,$7
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $4,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_ld
.align 2
.set nomips16
.ent m32_static_ld
m32_static_ld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $7,$f2
mtc1 $6,$f3
trunc.w.d $f0,$f2
mfc1 $24,$f0
j $31
addu $2,$24,$4
.set macro
.set reorder
.end m32_static_ld
.align 2
.set mips16
.ent m16_static_ld
m16_static_ld:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
move $16,$4
move $5,$7
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $4,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_static_ld
.align 2
.set nomips16
.ent m32_static1_ld
m32_static1_ld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $7,$f2
mtc1 $6,$f3
trunc.w.d $f0,$f2
mfc1 $24,$f0
j $31
addu $2,$24,$4
.set macro
.set reorder
.end m32_static1_ld
.align 2
.set mips16
.ent m16_static1_ld
m16_static1_ld:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
move $16,$4
move $5,$7
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $4,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_static1_ld
.align 2
.set nomips16
.ent m32_static32_ld
m32_static32_ld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $7,$f2
mtc1 $6,$f3
trunc.w.d $f0,$f2
mfc1 $24,$f0
j $31
addu $2,$24,$4
.set macro
.set reorder
.end m32_static32_ld
.align 2
.set mips16
.ent m16_static32_ld
m16_static32_ld:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
move $16,$4
move $5,$7
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $4,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_static32_ld
.align 2
.set nomips16
.ent m32_static16_ld
m32_static16_ld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $7,$f2
mtc1 $6,$f3
trunc.w.d $f0,$f2
mfc1 $24,$f0
j $31
addu $2,$24,$4
.set macro
.set reorder
.end m32_static16_ld
.align 2
.set mips16
.ent m16_static16_ld
m16_static16_ld:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
move $16,$4
move $5,$7
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $4,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_static16_ld
.align 2
.globl m32_dl
.set nomips16
.ent m32_dl
m32_dl:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f0,$f12
mfc1 $24,$f0
j $31
addu $2,$24,$6
.set macro
.set reorder
.end m32_dl
.align 2
.globl m16_dl
.set mips16
.ent m16_dl
m16_dl:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $16,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_dl
# Stub function for m16_dl (double)
.set nomips16
.section .mips16.fn.m16_dl,"ax",@progbits
.align 2
.ent __fn_stub_m16_dl
__fn_stub_m16_dl:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_dl
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_dl
.previous
.align 2
.set nomips16
.ent m32_static_dl
m32_static_dl:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f0,$f12
mfc1 $24,$f0
j $31
addu $2,$24,$6
.set macro
.set reorder
.end m32_static_dl
.align 2
.set mips16
.ent m16_static_dl
m16_static_dl:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $16,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_static_dl
# Stub function for m16_static_dl (double)
.set nomips16
.section .mips16.fn.m16_static_dl,"ax",@progbits
.align 2
.ent __fn_stub_m16_static_dl
__fn_stub_m16_static_dl:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static_dl
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static_dl
.previous
.align 2
.set nomips16
.ent m32_static1_dl
m32_static1_dl:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f0,$f12
mfc1 $24,$f0
j $31
addu $2,$24,$6
.set macro
.set reorder
.end m32_static1_dl
.align 2
.set mips16
.ent m16_static1_dl
m16_static1_dl:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $16,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_static1_dl
# Stub function for m16_static1_dl (double)
.set nomips16
.section .mips16.fn.m16_static1_dl,"ax",@progbits
.align 2
.ent __fn_stub_m16_static1_dl
__fn_stub_m16_static1_dl:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static1_dl
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static1_dl
.previous
.align 2
.set nomips16
.ent m32_static32_dl
m32_static32_dl:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f0,$f12
mfc1 $24,$f0
j $31
addu $2,$24,$6
.set macro
.set reorder
.end m32_static32_dl
.align 2
.set mips16
.ent m16_static32_dl
m16_static32_dl:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $16,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_static32_dl
# Stub function for m16_static32_dl (double)
.set nomips16
.section .mips16.fn.m16_static32_dl,"ax",@progbits
.align 2
.ent __fn_stub_m16_static32_dl
__fn_stub_m16_static32_dl:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static32_dl
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static32_dl
.previous
.align 2
.set nomips16
.ent m32_static16_dl
m32_static16_dl:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f0,$f12
mfc1 $24,$f0
j $31
addu $2,$24,$6
.set macro
.set reorder
.end m32_static16_dl
.align 2
.set mips16
.ent m16_static16_dl
m16_static16_dl:
.frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0
.mask 0x80010000,-4
.fmask 0x00000000,0
save 24,$16,$31
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $16,$6
.set macro
.set reorder
addu $2,$16
restore 24,$16,$31
j $31
.end m16_static16_dl
# Stub function for m16_static16_dl (double)
.set nomips16
.section .mips16.fn.m16_static16_dl,"ax",@progbits
.align 2
.ent __fn_stub_m16_static16_dl
__fn_stub_m16_static16_dl:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static16_dl
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static16_dl
.previous
.align 2
.globl m32_dlld
.set nomips16
.ent m32_dlld
m32_dlld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f1,$f12
mfc1 $4,$f1
addu $3,$4,$6
addu $2,$3,$7
ldc1 $f0,16($sp)
trunc.w.d $f2,$f0
mfc1 $24,$f2
j $31
addu $2,$2,$24
.set macro
.set reorder
.end m32_dlld
.align 2
.globl m16_dlld
.set mips16
.ent m16_dlld
m16_dlld:
.frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0
.mask 0x80030000,-4
.fmask 0x00000000,0
save 32,$16,$17,$31
move $16,$6
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $17,$7
.set macro
.set reorder
lw $5,52($sp)
lw $4,48($sp)
addu $16,$2,$16
.set noreorder
.set nomacro
jal __mips16_fixdfsi
addu $16,$17
.set macro
.set reorder
addu $2,$16,$2
restore 32,$16,$17,$31
j $31
.end m16_dlld
# Stub function for m16_dlld (double)
.set nomips16
.section .mips16.fn.m16_dlld,"ax",@progbits
.align 2
.ent __fn_stub_m16_dlld
__fn_stub_m16_dlld:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_dlld
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_dlld
.previous
.align 2
.set nomips16
.ent m32_static_dlld
m32_static_dlld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f1,$f12
mfc1 $4,$f1
addu $3,$4,$6
addu $2,$3,$7
ldc1 $f0,16($sp)
trunc.w.d $f2,$f0
mfc1 $24,$f2
j $31
addu $2,$2,$24
.set macro
.set reorder
.end m32_static_dlld
.align 2
.set mips16
.ent m16_static_dlld
m16_static_dlld:
.frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0
.mask 0x80030000,-4
.fmask 0x00000000,0
save 32,$16,$17,$31
move $16,$6
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $17,$7
.set macro
.set reorder
lw $5,52($sp)
lw $4,48($sp)
addu $16,$2,$16
.set noreorder
.set nomacro
jal __mips16_fixdfsi
addu $16,$17
.set macro
.set reorder
addu $2,$16,$2
restore 32,$16,$17,$31
j $31
.end m16_static_dlld
# Stub function for m16_static_dlld (double)
.set nomips16
.section .mips16.fn.m16_static_dlld,"ax",@progbits
.align 2
.ent __fn_stub_m16_static_dlld
__fn_stub_m16_static_dlld:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static_dlld
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static_dlld
.previous
.align 2
.set nomips16
.ent m32_static1_dlld
m32_static1_dlld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f1,$f12
mfc1 $4,$f1
addu $3,$4,$6
addu $2,$3,$7
ldc1 $f0,16($sp)
trunc.w.d $f2,$f0
mfc1 $24,$f2
j $31
addu $2,$2,$24
.set macro
.set reorder
.end m32_static1_dlld
.align 2
.set mips16
.ent m16_static1_dlld
m16_static1_dlld:
.frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0
.mask 0x80030000,-4
.fmask 0x00000000,0
save 32,$16,$17,$31
move $16,$6
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $17,$7
.set macro
.set reorder
lw $5,52($sp)
lw $4,48($sp)
addu $16,$2,$16
.set noreorder
.set nomacro
jal __mips16_fixdfsi
addu $16,$17
.set macro
.set reorder
addu $2,$16,$2
restore 32,$16,$17,$31
j $31
.end m16_static1_dlld
# Stub function for m16_static1_dlld (double)
.set nomips16
.section .mips16.fn.m16_static1_dlld,"ax",@progbits
.align 2
.ent __fn_stub_m16_static1_dlld
__fn_stub_m16_static1_dlld:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static1_dlld
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static1_dlld
.previous
.align 2
.set nomips16
.ent m32_static32_dlld
m32_static32_dlld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f1,$f12
mfc1 $4,$f1
addu $3,$4,$6
addu $2,$3,$7
ldc1 $f0,16($sp)
trunc.w.d $f2,$f0
mfc1 $24,$f2
j $31
addu $2,$2,$24
.set macro
.set reorder
.end m32_static32_dlld
.align 2
.set mips16
.ent m16_static32_dlld
m16_static32_dlld:
.frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0
.mask 0x80030000,-4
.fmask 0x00000000,0
save 32,$16,$17,$31
move $16,$6
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $17,$7
.set macro
.set reorder
lw $5,52($sp)
lw $4,48($sp)
addu $16,$2,$16
.set noreorder
.set nomacro
jal __mips16_fixdfsi
addu $16,$17
.set macro
.set reorder
addu $2,$16,$2
restore 32,$16,$17,$31
j $31
.end m16_static32_dlld
# Stub function for m16_static32_dlld (double)
.set nomips16
.section .mips16.fn.m16_static32_dlld,"ax",@progbits
.align 2
.ent __fn_stub_m16_static32_dlld
__fn_stub_m16_static32_dlld:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static32_dlld
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static32_dlld
.previous
.align 2
.set nomips16
.ent m32_static16_dlld
m32_static16_dlld:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
trunc.w.d $f1,$f12
mfc1 $4,$f1
addu $3,$4,$6
addu $2,$3,$7
ldc1 $f0,16($sp)
trunc.w.d $f2,$f0
mfc1 $24,$f2
j $31
addu $2,$2,$24
.set macro
.set reorder
.end m32_static16_dlld
.align 2
.set mips16
.ent m16_static16_dlld
m16_static16_dlld:
.frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0
.mask 0x80030000,-4
.fmask 0x00000000,0
save 32,$16,$17,$31
move $16,$6
.set noreorder
.set nomacro
jal __mips16_fixdfsi
move $17,$7
.set macro
.set reorder
lw $5,52($sp)
lw $4,48($sp)
addu $16,$2,$16
.set noreorder
.set nomacro
jal __mips16_fixdfsi
addu $16,$17
.set macro
.set reorder
addu $2,$16,$2
restore 32,$16,$17,$31
j $31
.end m16_static16_dlld
# Stub function for m16_static16_dlld (double)
.set nomips16
.section .mips16.fn.m16_static16_dlld,"ax",@progbits
.align 2
.ent __fn_stub_m16_static16_dlld
__fn_stub_m16_static16_dlld:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static16_dlld
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static16_dlld
.previous
.align 2
.globl m32_d_l
.set nomips16
.ent m32_d_l
m32_d_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $4,$f2
j $31
cvt.d.w $f0,$f2
.set macro
.set reorder
.end m32_d_l
.align 2
.globl m16_d_l
.set mips16
.ent m16_d_l
m16_d_l:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_floatsidf
jal __mips16_ret_df
restore 24,$31
j $31
.end m16_d_l
.align 2
.set nomips16
.ent m32_static_d_l
m32_static_d_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $4,$f2
j $31
cvt.d.w $f0,$f2
.set macro
.set reorder
.end m32_static_d_l
.align 2
.set mips16
.ent m16_static_d_l
m16_static_d_l:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_floatsidf
jal __mips16_ret_df
restore 24,$31
j $31
.end m16_static_d_l
.align 2
.set nomips16
.ent m32_static1_d_l
m32_static1_d_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $4,$f2
j $31
cvt.d.w $f0,$f2
.set macro
.set reorder
.end m32_static1_d_l
.align 2
.set mips16
.ent m16_static1_d_l
m16_static1_d_l:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_floatsidf
jal __mips16_ret_df
restore 24,$31
j $31
.end m16_static1_d_l
.align 2
.set nomips16
.ent m32_static32_d_l
m32_static32_d_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $4,$f2
j $31
cvt.d.w $f0,$f2
.set macro
.set reorder
.end m32_static32_d_l
.align 2
.set mips16
.ent m16_static32_d_l
m16_static32_d_l:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_floatsidf
jal __mips16_ret_df
restore 24,$31
j $31
.end m16_static32_d_l
.align 2
.set nomips16
.ent m32_static16_d_l
m32_static16_d_l:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
mtc1 $4,$f2
j $31
cvt.d.w $f0,$f2
.set macro
.set reorder
.end m32_static16_d_l
.align 2
.set mips16
.ent m16_static16_d_l
m16_static16_d_l:
.frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 24,$31
jal __mips16_floatsidf
jal __mips16_ret_df
restore 24,$31
j $31
.end m16_static16_d_l
.align 2
.globl m32_d_d
.set nomips16
.ent m32_d_d
m32_d_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
mov.d $f0,$f12
.set macro
.set reorder
.end m32_d_d
.align 2
.globl m16_d_d
.set mips16
.ent m16_d_d
m16_d_d:
.frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 8,$31
move $3,$5
.set noreorder
.set nomacro
jal __mips16_ret_df
move $2,$4
.set macro
.set reorder
restore 8,$31
j $31
.end m16_d_d
# Stub function for m16_d_d (double)
.set nomips16
.section .mips16.fn.m16_d_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_d_d
__fn_stub_m16_d_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_d_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_d_d
.previous
.align 2
.set nomips16
.ent m32_static_d_d
m32_static_d_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
mov.d $f0,$f12
.set macro
.set reorder
.end m32_static_d_d
.align 2
.set mips16
.ent m16_static_d_d
m16_static_d_d:
.frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 8,$31
move $3,$5
.set noreorder
.set nomacro
jal __mips16_ret_df
move $2,$4
.set macro
.set reorder
restore 8,$31
j $31
.end m16_static_d_d
# Stub function for m16_static_d_d (double)
.set nomips16
.section .mips16.fn.m16_static_d_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_static_d_d
__fn_stub_m16_static_d_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static_d_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static_d_d
.previous
.align 2
.set nomips16
.ent m32_static1_d_d
m32_static1_d_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
mov.d $f0,$f12
.set macro
.set reorder
.end m32_static1_d_d
.align 2
.set mips16
.ent m16_static1_d_d
m16_static1_d_d:
.frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 8,$31
move $3,$5
.set noreorder
.set nomacro
jal __mips16_ret_df
move $2,$4
.set macro
.set reorder
restore 8,$31
j $31
.end m16_static1_d_d
# Stub function for m16_static1_d_d (double)
.set nomips16
.section .mips16.fn.m16_static1_d_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_static1_d_d
__fn_stub_m16_static1_d_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static1_d_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static1_d_d
.previous
.align 2
.set nomips16
.ent m32_static32_d_d
m32_static32_d_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
mov.d $f0,$f12
.set macro
.set reorder
.end m32_static32_d_d
.align 2
.set mips16
.ent m16_static32_d_d
m16_static32_d_d:
.frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 8,$31
move $3,$5
.set noreorder
.set nomacro
jal __mips16_ret_df
move $2,$4
.set macro
.set reorder
restore 8,$31
j $31
.end m16_static32_d_d
# Stub function for m16_static32_d_d (double)
.set nomips16
.section .mips16.fn.m16_static32_d_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_static32_d_d
__fn_stub_m16_static32_d_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static32_d_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static32_d_d
.previous
.align 2
.set nomips16
.ent m32_static16_d_d
m32_static16_d_d:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
j $31
mov.d $f0,$f12
.set macro
.set reorder
.end m32_static16_d_d
.align 2
.set mips16
.ent m16_static16_d_d
m16_static16_d_d:
.frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
.mask 0x80000000,-4
.fmask 0x00000000,0
save 8,$31
move $3,$5
.set noreorder
.set nomacro
jal __mips16_ret_df
move $2,$4
.set macro
.set reorder
restore 8,$31
j $31
.end m16_static16_d_d
# Stub function for m16_static16_d_d (double)
.set nomips16
.section .mips16.fn.m16_static16_d_d,"ax",@progbits
.align 2
.ent __fn_stub_m16_static16_d_d
__fn_stub_m16_static16_d_d:
.set noreorder
mfc1 $4,$f13
mfc1 $5,$f12
.set noat
la $1,m16_static16_d_d
jr $1
.set at
nop
.set reorder
.end __fn_stub_m16_static16_d_d
.previous
.align 2
.globl f32
.set nomips16
.ent f32
f32:
.frame $sp,64,$31 # vars= 0, regs= 3/3, args= 24, gp= 0
.mask 0x80030000,-32
.fmask 0x03f00000,-8
.set noreorder
.set nomacro
addiu $sp,$sp,-64
sw $17,28($sp)
move $17,$4
sw $31,32($sp)
sdc1 $f24,56($sp)
sw $16,24($sp)
sdc1 $f22,48($sp)
sdc1 $f20,40($sp)
mtc1 $7,$f22
jal m32_static1_l
mtc1 $6,$f23
move $4,$17
jal m16_static1_l
move $16,$2
addu $16,$16,$2
jal m32_static1_d
mov.d $f12,$f22
addu $16,$16,$2
jal m16_static1_d
mov.d $f12,$f22
move $4,$17
mfc1 $7,$f22
mfc1 $6,$f23
jal m32_static1_ld
addu $16,$16,$2
move $4,$17
mfc1 $7,$f22
mfc1 $6,$f23
jal m16_static1_ld
addu $16,$16,$2
move $6,$17
mov.d $f12,$f22
jal m32_static1_dl
addu $16,$16,$2
move $6,$17
mov.d $f12,$f22
jal m16_static1_dl
addu $16,$16,$2
move $6,$17
move $7,$17
sdc1 $f22,16($sp)
mov.d $f12,$f22
jal m32_static1_dlld
addu $16,$16,$2
move $6,$17
move $7,$17
mov.d $f12,$f22
sdc1 $f22,16($sp)
jal m16_static1_dlld
addu $16,$16,$2
move $4,$17
jal m32_static1_d_l
addu $16,$16,$2
move $4,$17
jal m16_static1_d_l
mov.d $f20,$f0
add.d $f20,$f20,$f0
jal m32_static1_d_d
mov.d $f12,$f22
add.d $f20,$f20,$f0
jal m16_static1_d_d
mov.d $f12,$f22
move $4,$17
jal m32_static32_l
add.d $f20,$f20,$f0
move $4,$17
jal m16_static32_l
addu $16,$16,$2
addu $16,$16,$2
jal m32_static32_d
mov.d $f12,$f22
addu $16,$16,$2
jal m16_static32_d
mov.d $f12,$f22
move $4,$17
mfc1 $7,$f22
mfc1 $6,$f23
jal m32_static32_ld
addu $16,$16,$2
move $4,$17
mfc1 $7,$f22
mfc1 $6,$f23
jal m16_static32_ld
addu $16,$16,$2
move $6,$17
mov.d $f12,$f22
jal m32_static32_dl
addu $16,$16,$2
move $6,$17
mov.d $f12,$f22
jal m16_static32_dl
addu $16,$16,$2
move $6,$17
move $7,$17
sdc1 $f22,16($sp)
mov.d $f12,$f22
jal m32_static32_dlld
addu $16,$16,$2
move $6,$17
move $7,$17
mov.d $f12,$f22
sdc1 $f22,16($sp)
jal m16_static32_dlld
addu $16,$16,$2
move $4,$17
jal m32_static32_d_l
addu $16,$16,$2
move $4,$17
jal m16_static32_d_l
add.d $f20,$f20,$f0
add.d $f20,$f20,$f0
jal m32_static32_d_d
mov.d $f12,$f22
mtc1 $16,$f24
add.d $f20,$f20,$f0
jal m16_static32_d_d
mov.d $f12,$f22
lw $31,32($sp)
lw $17,28($sp)
lw $16,24($sp)
add.d $f20,$f20,$f0
ldc1 $f22,48($sp)
cvt.d.w $f0,$f24
ldc1 $f24,56($sp)
add.d $f0,$f0,$f20
ldc1 $f20,40($sp)
j $31
addiu $sp,$sp,64
.set macro
.set reorder
.end f32
# Stub function to call m32_static1_d (double)
.set nomips16
.section .mips16.call.m32_static1_d,"ax",@progbits
.align 2
.ent __call_stub_m32_static1_d
__call_stub_m32_static1_d:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m32_static1_d
jr $1
.set at
nop
.set reorder
.end __call_stub_m32_static1_d
.previous
# Stub function to call m16_static1_d (double)
.set nomips16
.section .mips16.call.m16_static1_d,"ax",@progbits
.align 2
.ent __call_stub_m16_static1_d
__call_stub_m16_static1_d:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m16_static1_d
jr $1
.set at
nop
.set reorder
.end __call_stub_m16_static1_d
.previous
# Stub function to call m32_static1_dl (double)
.set nomips16
.section .mips16.call.m32_static1_dl,"ax",@progbits
.align 2
.ent __call_stub_m32_static1_dl
__call_stub_m32_static1_dl:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m32_static1_dl
jr $1
.set at
nop
.set reorder
.end __call_stub_m32_static1_dl
.previous
# Stub function to call m16_static1_dl (double)
.set nomips16
.section .mips16.call.m16_static1_dl,"ax",@progbits
.align 2
.ent __call_stub_m16_static1_dl
__call_stub_m16_static1_dl:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m16_static1_dl
jr $1
.set at
nop
.set reorder
.end __call_stub_m16_static1_dl
.previous
# Stub function to call m32_static1_dlld (double)
.set nomips16
.section .mips16.call.m32_static1_dlld,"ax",@progbits
.align 2
.ent __call_stub_m32_static1_dlld
__call_stub_m32_static1_dlld:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m32_static1_dlld
jr $1
.set at
nop
.set reorder
.end __call_stub_m32_static1_dlld
.previous
# Stub function to call m16_static1_dlld (double)
.set nomips16
.section .mips16.call.m16_static1_dlld,"ax",@progbits
.align 2
.ent __call_stub_m16_static1_dlld
__call_stub_m16_static1_dlld:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m16_static1_dlld
jr $1
.set at
nop
.set reorder
.end __call_stub_m16_static1_dlld
.previous
# Stub function to call double m32_static1_d_l ()
.set nomips16
.section .mips16.call.fp.m32_static1_d_l,"ax",@progbits
.align 2
.ent __call_stub_fp_m32_static1_d_l
__call_stub_fp_m32_static1_d_l:
.set noreorder
move $18,$31
jal m32_static1_d_l
nop
mfc1 $2,$f1
mfc1 $3,$f0
j $18
nop
.set reorder
.end __call_stub_fp_m32_static1_d_l
.previous
# Stub function to call double m16_static1_d_l ()
.set nomips16
.section .mips16.call.fp.m16_static1_d_l,"ax",@progbits
.align 2
.ent __call_stub_fp_m16_static1_d_l
__call_stub_fp_m16_static1_d_l:
.set noreorder
move $18,$31
jal m16_static1_d_l
nop
mfc1 $2,$f1
mfc1 $3,$f0
j $18
nop
.set reorder
.end __call_stub_fp_m16_static1_d_l
.previous
# Stub function to call double m32_static1_d_d (double)
.set nomips16
.section .mips16.call.fp.m32_static1_d_d,"ax",@progbits
.align 2
.ent __call_stub_fp_m32_static1_d_d
__call_stub_fp_m32_static1_d_d:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
move $18,$31
jal m32_static1_d_d
nop
mfc1 $2,$f1
mfc1 $3,$f0
j $18
nop
.set reorder
.end __call_stub_fp_m32_static1_d_d
.previous
# Stub function to call double m16_static1_d_d (double)
.set nomips16
.section .mips16.call.fp.m16_static1_d_d,"ax",@progbits
.align 2
.ent __call_stub_fp_m16_static1_d_d
__call_stub_fp_m16_static1_d_d:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
move $18,$31
jal m16_static1_d_d
nop
mfc1 $2,$f1
mfc1 $3,$f0
j $18
nop
.set reorder
.end __call_stub_fp_m16_static1_d_d
.previous
# Stub function to call m32_static16_d (double)
.set nomips16
.section .mips16.call.m32_static16_d,"ax",@progbits
.align 2
.ent __call_stub_m32_static16_d
__call_stub_m32_static16_d:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m32_static16_d
jr $1
.set at
nop
.set reorder
.end __call_stub_m32_static16_d
.previous
# Stub function to call m16_static16_d (double)
.set nomips16
.section .mips16.call.m16_static16_d,"ax",@progbits
.align 2
.ent __call_stub_m16_static16_d
__call_stub_m16_static16_d:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m16_static16_d
jr $1
.set at
nop
.set reorder
.end __call_stub_m16_static16_d
.previous
# Stub function to call m32_static16_dl (double)
.set nomips16
.section .mips16.call.m32_static16_dl,"ax",@progbits
.align 2
.ent __call_stub_m32_static16_dl
__call_stub_m32_static16_dl:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m32_static16_dl
jr $1
.set at
nop
.set reorder
.end __call_stub_m32_static16_dl
.previous
# Stub function to call m16_static16_dl (double)
.set nomips16
.section .mips16.call.m16_static16_dl,"ax",@progbits
.align 2
.ent __call_stub_m16_static16_dl
__call_stub_m16_static16_dl:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m16_static16_dl
jr $1
.set at
nop
.set reorder
.end __call_stub_m16_static16_dl
.previous
# Stub function to call m32_static16_dlld (double)
.set nomips16
.section .mips16.call.m32_static16_dlld,"ax",@progbits
.align 2
.ent __call_stub_m32_static16_dlld
__call_stub_m32_static16_dlld:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m32_static16_dlld
jr $1
.set at
nop
.set reorder
.end __call_stub_m32_static16_dlld
.previous
# Stub function to call m16_static16_dlld (double)
.set nomips16
.section .mips16.call.m16_static16_dlld,"ax",@progbits
.align 2
.ent __call_stub_m16_static16_dlld
__call_stub_m16_static16_dlld:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
.set noat
la $1,m16_static16_dlld
jr $1
.set at
nop
.set reorder
.end __call_stub_m16_static16_dlld
.previous
# Stub function to call double m32_static16_d_l ()
.set nomips16
.section .mips16.call.fp.m32_static16_d_l,"ax",@progbits
.align 2
.ent __call_stub_fp_m32_static16_d_l
__call_stub_fp_m32_static16_d_l:
.set noreorder
move $18,$31
jal m32_static16_d_l
nop
mfc1 $2,$f1
mfc1 $3,$f0
j $18
nop
.set reorder
.end __call_stub_fp_m32_static16_d_l
.previous
# Stub function to call double m16_static16_d_l ()
.set nomips16
.section .mips16.call.fp.m16_static16_d_l,"ax",@progbits
.align 2
.ent __call_stub_fp_m16_static16_d_l
__call_stub_fp_m16_static16_d_l:
.set noreorder
move $18,$31
jal m16_static16_d_l
nop
mfc1 $2,$f1
mfc1 $3,$f0
j $18
nop
.set reorder
.end __call_stub_fp_m16_static16_d_l
.previous
# Stub function to call double m32_static16_d_d (double)
.set nomips16
.section .mips16.call.fp.m32_static16_d_d,"ax",@progbits
.align 2
.ent __call_stub_fp_m32_static16_d_d
__call_stub_fp_m32_static16_d_d:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
move $18,$31
jal m32_static16_d_d
nop
mfc1 $2,$f1
mfc1 $3,$f0
j $18
nop
.set reorder
.end __call_stub_fp_m32_static16_d_d
.previous
# Stub function to call double m16_static16_d_d (double)
.set nomips16
.section .mips16.call.fp.m16_static16_d_d,"ax",@progbits
.align 2
.ent __call_stub_fp_m16_static16_d_d
__call_stub_fp_m16_static16_d_d:
.set noreorder
mtc1 $4,$f13
mtc1 $5,$f12
move $18,$31
jal m16_static16_d_d
nop
mfc1 $2,$f1
mfc1 $3,$f0
j $18
nop
.set reorder
.end __call_stub_fp_m16_static16_d_d
.previous
.align 2
.globl f16
.set mips16
.ent f16
f16:
.frame $sp,104,$31 # vars= 64, regs= 4/0, args= 24, gp= 0
.mask 0x80070000,-4
.fmask 0x00000000,0
save 104,$16,$17,$18,$31
move $17,$4
sw $7,116($sp)
.set noreorder
.set nomacro
jal m32_static1_l
sw $6,112($sp)
.set macro
.set reorder
move $4,$17
.set noreorder
.set nomacro
jal m16_static1_l
move $16,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
.set noreorder
.set nomacro
jal m32_static1_d
addu $16,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
.set noreorder
.set nomacro
jal m16_static1_d
addu $16,$2
.set macro
.set reorder
lw $7,116($sp)
lw $6,112($sp)
move $4,$17
.set noreorder
.set nomacro
jal m32_static1_ld
addu $16,$2
.set macro
.set reorder
lw $7,116($sp)
lw $6,112($sp)
move $4,$17
.set noreorder
.set nomacro
jal m16_static1_ld
addu $16,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
move $6,$17
.set noreorder
.set nomacro
jal m32_static1_dl
addu $16,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
move $6,$17
.set noreorder
.set nomacro
jal m16_static1_dl
addu $16,$2
.set macro
.set reorder
lw $3,116($sp)
lw $6,112($sp)
sw $3,20($sp)
move $5,$3
sw $6,16($sp)
move $4,$6
move $7,$17
move $6,$17
.set noreorder
.set nomacro
jal m32_static1_dlld
addu $16,$2
.set macro
.set reorder
addu $16,$2
lw $7,112($sp)
lw $2,116($sp)
move $6,$17
move $5,$2
sw $7,16($sp)
move $4,$7
sw $2,20($sp)
.set noreorder
.set nomacro
jal m16_static1_dlld
move $7,$17
.set macro
.set reorder
move $4,$17
.set noreorder
.set nomacro
jal m32_static1_d_l
addu $16,$2
.set macro
.set reorder
move $4,$17
sw $3,28($sp)
.set noreorder
.set nomacro
jal m16_static1_d_l
sw $2,24($sp)
.set macro
.set reorder
lw $5,28($sp)
lw $4,24($sp)
move $7,$3
.set noreorder
.set nomacro
jal __mips16_adddf3
move $6,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
sw $3,36($sp)
.set noreorder
.set nomacro
jal m32_static1_d_d
sw $2,32($sp)
.set macro
.set reorder
lw $5,36($sp)
lw $4,32($sp)
move $7,$3
.set noreorder
.set nomacro
jal __mips16_adddf3
move $6,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
sw $3,44($sp)
.set noreorder
.set nomacro
jal m16_static1_d_d
sw $2,40($sp)
.set macro
.set reorder
lw $5,44($sp)
lw $4,40($sp)
move $7,$3
.set noreorder
.set nomacro
jal __mips16_adddf3
move $6,$2
.set macro
.set reorder
move $4,$17
sw $3,52($sp)
.set noreorder
.set nomacro
jal m32_static16_l
sw $2,48($sp)
.set macro
.set reorder
move $4,$17
.set noreorder
.set nomacro
jal m16_static16_l
addu $16,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
.set noreorder
.set nomacro
jal m32_static16_d
addu $16,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
.set noreorder
.set nomacro
jal m16_static16_d
addu $16,$2
.set macro
.set reorder
lw $7,116($sp)
lw $6,112($sp)
move $4,$17
.set noreorder
.set nomacro
jal m32_static16_ld
addu $16,$2
.set macro
.set reorder
lw $7,116($sp)
lw $6,112($sp)
move $4,$17
.set noreorder
.set nomacro
jal m16_static16_ld
addu $16,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
move $6,$17
.set noreorder
.set nomacro
jal m32_static16_dl
addu $16,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
move $6,$17
.set noreorder
.set nomacro
jal m16_static16_dl
addu $16,$2
.set macro
.set reorder
lw $4,116($sp)
lw $6,112($sp)
sw $4,20($sp)
sw $6,16($sp)
move $5,$4
move $7,$17
move $4,$6
move $6,$17
.set noreorder
.set nomacro
jal m32_static16_dlld
addu $16,$2
.set macro
.set reorder
addu $16,$2
lw $3,116($sp)
lw $2,112($sp)
move $6,$17
move $7,$17
sw $3,20($sp)
move $5,$3
sw $2,16($sp)
.set noreorder
.set nomacro
jal m16_static16_dlld
move $4,$2
.set macro
.set reorder
move $4,$17
.set noreorder
.set nomacro
jal m32_static16_d_l
addu $16,$2
.set macro
.set reorder
lw $5,52($sp)
lw $4,48($sp)
move $7,$3
.set noreorder
.set nomacro
jal __mips16_adddf3
move $6,$2
.set macro
.set reorder
move $4,$17
sw $3,60($sp)
.set noreorder
.set nomacro
jal m16_static16_d_l
sw $2,56($sp)
.set macro
.set reorder
lw $5,60($sp)
lw $4,56($sp)
move $7,$3
.set noreorder
.set nomacro
jal __mips16_adddf3
move $6,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
sw $3,68($sp)
.set noreorder
.set nomacro
jal m32_static16_d_d
sw $2,64($sp)
.set macro
.set reorder
lw $5,68($sp)
lw $4,64($sp)
move $7,$3
.set noreorder
.set nomacro
jal __mips16_adddf3
move $6,$2
.set macro
.set reorder
lw $5,116($sp)
lw $4,112($sp)
sw $3,76($sp)
.set noreorder
.set nomacro
jal m16_static16_d_d
sw $2,72($sp)
.set macro
.set reorder
lw $5,76($sp)
lw $4,72($sp)
move $7,$3
.set noreorder
.set nomacro
jal __mips16_adddf3
move $6,$2
.set macro
.set reorder
move $4,$16
sw $3,84($sp)
.set noreorder
.set nomacro
jal __mips16_floatsidf
sw $2,80($sp)
.set macro
.set reorder
lw $7,84($sp)
lw $6,80($sp)
move $5,$3
.set noreorder
.set nomacro
jal __mips16_adddf3
move $4,$2
.set macro
.set reorder
jal __mips16_ret_df
restore 104,$16,$17,$18,$31
j $31
.end f16
|
tactcomplabs/xbgas-binutils-gdb
| 1,092
|
gas/testsuite/gas/mips/mips16-reg-error.s
|
.text
.ent foo
.set mips16
foo:
ld $4, $3($2)
ld $4, $3($pc)
ld $4, $3($sp)
lw $4, $3($2)
lw $4, $3($pc)
lw $4, $3($sp)
lwu $4, $3($2)
lh $4, $3($2)
lhu $4, $3($2)
lb $4, $3($2)
lbu $4, $3($2)
sd $4, $3($2)
sd $4, $3($sp)
sd $ra, $3($sp)
sw $4, $3($2)
sw $4, $3($sp)
sw $ra, $3($sp)
sh $4, $3($2)
sb $4, $3($2)
addiu $3, $2
addiu $4, $3, $2
addiu $3, $pc, $2
addiu $sp, $2
addiu $3, $sp, $2
daddiu $3, $2
daddiu $4, $3, $2
daddiu $3, $pc, $2
daddiu $sp, $2
daddiu $3, $sp, $2
slti $3, $2
sltiu $3, $2
cmpi $3, $2
cmp $3, $2
li $3, $2
sll $3, $2, $2
sra $3, $2, $2
srl $3, $2, $2
dsll $3, $2, $2
dsra $3, $2
dsrl $3, $2
break $2
sdbbp $2
b $2
beqz $3, $2
bnez $3, $2
bteqz $2
btnez $2
jal $2
jalx $2
save $31, $16, $2
restore $31, $16, $2
asmacro 0, 0, 0, 0, 0, $2
asmacro 0, 0, 0, 0, $2, 0
asmacro 0, 0, 0, $2, 0, 0
asmacro 0, 0, $2, 0, 0, 0
asmacro 0, $2, 0, 0, 0, 0
asmacro $2, 0, 0, 0, 0, 0
nop
.set nomips16
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 3,125
|
gas/testsuite/gas/mips/ase-errors-1.s
|
.set nomicromips
.set mips32r2
.set fp=64
.set dsp # OK
lbux $4,$5($6) # OK
ldx $4,$5($6) # ERROR: 64-bit only
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set fp=32 # OK
.set mips32 # ERROR: too low
lbux $4,$5($6) # OK
ldx $4,$5($6) # ERROR: 64-bit only
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set nodsp
lbux $4,$5($6) # ERROR: dsp not enabled
ldx $4,$5($6) # ERROR: dsp not enabled
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips32r2
.set fp=64
.set dspr2 # OK
lbux $4,$5($6) # OK
ldx $4,$5($6) # ERROR: 64-bit only
absq_s.qb $3,$4 # OK
.set fp=32 # OK
.set mips32 # ERROR: too low
lbux $4,$5($6) # OK
ldx $4,$5($6) # ERROR: 64-bit only
absq_s.qb $3,$4 # OK
.set nodspr2
lbux $4,$5($6) # ERROR: dsp not enabled
ldx $4,$5($6) # ERROR: dsp not enabled
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips32r2
.set fp=64
.set mcu # OK
aclr 4,100($4) # OK
.set fp=32 # OK
.set mips32 # ERROR: too low
aclr 4,100($4) # OK
.set nomcu
aclr 4,100($4) # ERROR: mcu not enabled
.set mips32r2
.set fp=64
.set mdmx # ERROR: needs a 64-bit target
add.ob $f4,$f6,$f8 # OK
.set fp=32 # ERROR: needs fp=64
add.ob $f4,$f6,$f8 # OK
.set nomdmx
add.ob $f4,$f6,$f8 # ERROR: mdmx not enabled
.set mips32r2
.set fp=64
.set mips3d # OK
addr.ps $f4,$f6,$f8 # OK
.set fp=32 # ERROR: needs fp=64
.set mips32 # ERROR: too low
addr.ps $f4,$f6,$f8 # OK
.set nomips3d
addr.ps $f4,$f6,$f8 # ERROR: mips3d not enabled
.set mips32r2
.set fp=64
.set mt # OK
dmt # OK
.set fp=32 # OK
.set mips32 # ERROR: too low
dmt # OK
.set nomt
dmt # ERROR: mt not enabled
.set fp=32
.set mips32
.set smartmips # OK
maddp $4,$5 # OK
.set mips2 # ERROR: too low
maddp $4,$5 # OK
.set nosmartmips
maddp $4,$5 # ERROR: smartmips not enabled
.set mips32r2
.set fp=64
.set virt # OK
hypcall # OK
dmfgc0 $3, $29 # ERROR: 64-bit only
.set fp=32 # OK
.set mips32 # ERROR: too low
hypcall # OK
dmfgc0 $3, $29 # ERROR: 64-bit only
.set novirt
hypcall # ERROR: virt not enabled
dmfgc0 $3, $29 # ERROR: virt not enabled
.set mips32r2
.set fp=64
.set eva # OK
lbue $4,16($5) # OK
.set fp=32 # OK
.set mips32 # ERROR: too low
lbue $4,16($5) # OK
.set noeva
lbue $4,16($5) # ERROR: eva not enabled
.set mips32r6
.set crc # OK
crc32b $4,$7,$4 # OK
crc32d $4,$7,$4 # ERROR: 64-bit only
.set mips32r5 # ERROR: too low
crc32b $4,$7,$4 # OK
.set nocrc
crc32b $4,$7,$4 # ERROR: crc not enabled
.set mips32r6
.set ginv # OK
ginvi $a0 # OK
.set mips32r5 # ERROR: too low
ginvt $a0, 1 # OK
.set noginv
ginvi $a0 # ERROR: ginv not enabled
.set mips32r6
.set eva
llwpe $2, $3, $4 # OK
scwpe $2, $3, $4 # OK
.set noeva
llwpe $2, $3, $4 # ERROR: eva not enabled
scwpe $2, $3, $4 # ERROR: eva not enabled
.set mips32r5
.set eva
llwpe $2, $3, $4 # ERROR: only avaialable on R6
scwpe $2, $3, $4 # ERROR: only avaialable on R6
# There should be no errors after this.
.set fp=32
.set mips1
.set dsp
.set dspr2
.set mcu
.set mdmx
.set mips3d
.set mt
.set smartmips
.set eva
|
tactcomplabs/xbgas-binutils-gdb
| 1,749
|
gas/testsuite/gas/mips/relax-swap1.s
|
# Source file used to test branch relaxation with swapping.
.text
foo:
move $2, $4
b foo
move $2, $4
b bar
lw $2, ($4)
b foo
lw $2, ($4)
b bar
sw $2, ($4)
b foo
sw $2, ($4)
b bar
move $2, $4
beq $2, $3, foo
move $2, $4
beq $2, $3, bar
move $2, $4
beq $4, $5, foo
move $2, $4
beq $4, $5, bar
addiu $2, $4, 1
beq $2, $3, foo
addiu $2, $4, 1
beq $2, $3, bar
addiu $2, $4, 1
beq $4, $5, foo
addiu $2, $4, 1
beq $4, $5, bar
lw $2, ($4)
beq $2, $3, foo
lw $2, ($4)
beq $2, $3, bar
lw $2, ($4)
beq $4, $5, foo
lw $2, ($4)
beq $4, $5, bar
sw $2, ($4)
beq $2, $3, foo
sw $2, ($4)
beq $2, $3, bar
sw $2, ($4)
beq $4, $5, foo
sw $2, ($4)
beq $4, $5, bar
mfc1 $2, $0
move $6, $7
beq $2, $3, foo
mfc1 $2, $0
move $6, $7
beq $2, $3, bar
mfc1 $2, $0
move $6, $7
beq $4, $5, foo
mfc1 $2, $0
move $6, $7
beq $4, $5, bar
move $2, $4
bc1t foo
move $2, $4
bc1t bar
.set nomove
move $2, $4
b foo
move $2, $4
b bar
.set move
move $2, $4
0: b foo
move $2, $4
0: b bar
.set noreorder
move $6, $7
.set reorder
move $2, $4
b foo
.set noreorder
move $6, $7
.set reorder
move $2, $4
b bar
sw $2, 0f
0: b foo
sw $2, 0f
0: b bar
lwc1 $0, ($4)
b foo
lwc1 $0, ($4)
b bar
cfc1 $2, $31
b foo
cfc1 $2, $31
b bar
ctc1 $2, $31
b foo
ctc1 $2, $31
b bar
mtc1 $2, $31
b foo
mtc1 $2, $31
b bar
mfhi $2
b foo
mfhi $2
b bar
move $2, $4
jr $2
move $2, $4
jr $4
move $2, $4
jalr $2
move $2, $4
jalr $4
move $2, $31
jalr $3
move $31, $4
jalr $5
move $31, $4
jalr $2, $3
move $2, $31
jalr $2, $3
.space 0x20000 # to make a 128kb loop body
bar:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,310
|
gas/testsuite/gas/mips/c0.s
|
.text
foo:
c0 0x00
c0 0x01
c0 0x02
c0 0x03
c0 0x04
c0 0x05
c0 0x06
c0 0x07
c0 0x08
c0 0x09
c0 0x0a
c0 0x0b
c0 0x0c
c0 0x0d
c0 0x0e
c0 0x0f
c0 0x10
c0 0x11
c0 0x12
c0 0x13
c0 0x14
c0 0x15
c0 0x16
c0 0x17
c0 0x18
c0 0x19
c0 0x1a
c0 0x1b
c0 0x1c
c0 0x1d
c0 0x1e
c0 0x1f
c0 0x20
c0 0x21
c0 0x22
c0 0x23
c0 0x24
c0 0x25
c0 0x26
c0 0x27
c0 0x28
c0 0x29
c0 0x2a
c0 0x2b
c0 0x2c
c0 0x2d
c0 0x2e
c0 0x2f
c0 0x30
c0 0x31
c0 0x32
c0 0x33
c0 0x34
c0 0x35
c0 0x36
c0 0x37
c0 0x38
c0 0x39
c0 0x3a
c0 0x3b
c0 0x3c
c0 0x3d
c0 0x3e
c0 0x3f
c0 0x1000000
c0 0x1000001
c0 0x1000002
c0 0x1000003
c0 0x1000004
c0 0x1000005
c0 0x1000006
c0 0x1000007
c0 0x1000008
c0 0x1000009
c0 0x100000a
c0 0x100000b
c0 0x100000c
c0 0x100000d
c0 0x100000e
c0 0x100000f
c0 0x1000010
c0 0x1000011
c0 0x1000012
c0 0x1000013
c0 0x1000014
c0 0x1000015
c0 0x1000016
c0 0x1000017
c0 0x1000018
c0 0x1000019
c0 0x100001a
c0 0x100001b
c0 0x100001c
c0 0x100001d
c0 0x100001e
c0 0x100001f
c0 0x1000020
c0 0x1000021
c0 0x1000022
c0 0x1000023
c0 0x1000024
c0 0x1000025
c0 0x1000026
c0 0x1000027
c0 0x1000028
c0 0x1000029
c0 0x100002a
c0 0x100002b
c0 0x100002c
c0 0x100002d
c0 0x100002e
c0 0x100002f
c0 0x1000030
c0 0x1000031
c0 0x1000032
c0 0x1000033
c0 0x1000034
c0 0x1000035
c0 0x1000036
c0 0x1000037
c0 0x1000038
c0 0x1000039
c0 0x100003a
c0 0x100003b
c0 0x100003c
c0 0x100003d
c0 0x100003e
c0 0x100003f
cop0 0x00
cop0 0x01
cop0 0x02
cop0 0x03
cop0 0x04
cop0 0x05
cop0 0x06
cop0 0x07
cop0 0x08
cop0 0x09
cop0 0x0a
cop0 0x0b
cop0 0x0c
cop0 0x0d
cop0 0x0e
cop0 0x0f
cop0 0x10
cop0 0x11
cop0 0x12
cop0 0x13
cop0 0x14
cop0 0x15
cop0 0x16
cop0 0x17
cop0 0x18
cop0 0x19
cop0 0x1a
cop0 0x1b
cop0 0x1c
cop0 0x1d
cop0 0x1e
cop0 0x1f
cop0 0x20
cop0 0x21
cop0 0x22
cop0 0x23
cop0 0x24
cop0 0x25
cop0 0x26
cop0 0x27
cop0 0x28
cop0 0x29
cop0 0x2a
cop0 0x2b
cop0 0x2c
cop0 0x2d
cop0 0x2e
cop0 0x2f
cop0 0x30
cop0 0x31
cop0 0x32
cop0 0x33
cop0 0x34
cop0 0x35
cop0 0x36
cop0 0x37
cop0 0x38
cop0 0x39
cop0 0x3a
cop0 0x3b
cop0 0x3c
cop0 0x3d
cop0 0x3e
cop0 0x3f
cop0 0x1000000
cop0 0x1000001
cop0 0x1000002
cop0 0x1000003
cop0 0x1000004
cop0 0x1000005
cop0 0x1000006
cop0 0x1000007
cop0 0x1000008
cop0 0x1000009
cop0 0x100000a
cop0 0x100000b
cop0 0x100000c
cop0 0x100000d
cop0 0x100000e
cop0 0x100000f
cop0 0x1000010
cop0 0x1000011
cop0 0x1000012
cop0 0x1000013
cop0 0x1000014
cop0 0x1000015
cop0 0x1000016
cop0 0x1000017
cop0 0x1000018
cop0 0x1000019
cop0 0x100001a
cop0 0x100001b
cop0 0x100001c
cop0 0x100001d
cop0 0x100001e
cop0 0x100001f
cop0 0x1000020
cop0 0x1000021
cop0 0x1000022
cop0 0x1000023
cop0 0x1000024
cop0 0x1000025
cop0 0x1000026
cop0 0x1000027
cop0 0x1000028
cop0 0x1000029
cop0 0x100002a
cop0 0x100002b
cop0 0x100002c
cop0 0x100002d
cop0 0x100002e
cop0 0x100002f
cop0 0x1000030
cop0 0x1000031
cop0 0x1000032
cop0 0x1000033
cop0 0x1000034
cop0 0x1000035
cop0 0x1000036
cop0 0x1000037
cop0 0x1000038
cop0 0x1000039
cop0 0x100003a
cop0 0x100003b
cop0 0x100003c
cop0 0x100003d
cop0 0x100003e
cop0 0x100003f
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 1,217
|
gas/testsuite/gas/mips/octeon-ill.s
|
.text
.set noreorder
foo:
bbit032 $23,51,foo
nop
bbit0 $23,71,foo
nop
bbit132 $23,49,foo
nop
bbit1 $23,74,foo
nop
cins $2,0,37
cins32 $19,$31,39,12
cins32 $17,$20,7,25
cins $24,$10,64,8
cins $21,$30,50,14
c2 1
bc2f foo
bc2fl foo
bc2t foo
bc2tl foo
cfc2 $25,$12
ctc2 $12,$2
ldc2 $10,0($25)
lwc2 $11,12($31)
mfc2 $24,$1
mfhc2 $17,$20
mtc2 $2,$21
mthc2 $13,$25
sdc2 $22,8($4)
swc2 $2,24($2)
cop2 23
ldc2 $8,foo
lwc2 $16,foo+4
sdc2 $10,0x12345678
swc2 $16,0x12345($15)
dmfc2 $2,0x10000
dmtc2 $2,0x12345
dmfc2 $9,$12
dmfc2 $4,$15,4
dmtc2 $16,$8
dmtc2 $22,$7,$4
exts $26,26,32
exts32 $7,$21,32,10
exts32 $31,$13,3,29
exts $14,$29,70,14
exts $20,$16,39,25
seqi $14,$13,512
seqi $19,-771
snei $18,$30,615
snei $17,-513
|
tactcomplabs/xbgas-binutils-gdb
| 1,922
|
gas/testsuite/gas/mips/unaligned-branch-r6-3.s
|
.text
.set noreorder
.space 0x1000
.align 4
.set mips32r6
.ent foo
foo:
nor $0, $0
bc bar0
nor $0, $0
beqzc $2, bar0
nor $0, $0
beqz $2, bar0
nor $0, $0
bc bar1
nor $0, $0
beqzc $2, bar1
nor $0, $0
beqz $2, bar1
nor $0, $0
bc bar2
nor $0, $0
beqzc $2, bar2
nor $0, $0
beqz $2, bar2
nor $0, $0
bc bar3
nor $0, $0
beqzc $2, bar3
nor $0, $0
beqz $2, bar3
nor $0, $0
bc bar4
nor $0, $0
beqzc $2, bar4
nor $0, $0
beqz $2, bar4
nor $0, $0
bc bar4 + 1
nor $0, $0
beqzc $2, bar4 + 1
nor $0, $0
beqz $2, bar4 + 1
nor $0, $0
bc bar4 + 2
nor $0, $0
beqzc $2, bar4 + 2
nor $0, $0
beqz $2, bar4 + 2
nor $0, $0
bc bar4 + 3
nor $0, $0
beqzc $2, bar4 + 3
nor $0, $0
beqz $2, bar4 + 3
nor $0, $0
bc bar4 + 4
nor $0, $0
beqzc $2, bar4 + 4
nor $0, $0
beqz $2, bar4 + 4
nor $0, $0
bc bar16
nor $0, $0
beqzc $2, bar16
nor $0, $0
beqz $2, bar16
nor $0, $0
bc bar17
nor $0, $0
beqzc $2, bar17
nor $0, $0
beqz $2, bar17
nor $0, $0
bc bar18
nor $0, $0
beqzc $2, bar18
nor $0, $0
beqz $2, bar18
nor $0, $0
bc bar18 + 1
nor $0, $0
beqzc $2, bar18 + 1
nor $0, $0
beqz $2, bar18 + 1
nor $0, $0
bc bar18 + 2
nor $0, $0
beqzc $2, bar18 + 2
nor $0, $0
beqz $2, bar18 + 2
nor $0, $0
bc bar18 + 3
nor $0, $0
beqzc $2, bar18 + 3
nor $0, $0
beqz $2, bar18 + 3
nor $0, $0
bc bar18 + 4
nor $0, $0
beqzc $2, bar18 + 4
nor $0, $0
beqz $2, bar18 + 4
nor $0, $0
jalr $0, $ra
nor $0, $0
.end foo
.set mips0
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.globl bar\@
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.globl bar\@
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
.set micromips
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,795
|
gas/testsuite/gas/mips/mips64-mips3d.s
|
# source file to test assembly of mips64 MIPS-3D ASE instructions
.set noreorder
.set noat
.text
text_label:
addr.ps $f4, $f8, $f19
bc1any2f $fcc0, text_label
nop
bc1any2f $fcc2, text_label
nop
bc1any2t $fcc0, text_label
nop
bc1any2t $fcc4, text_label
nop
bc1any4f $fcc0, text_label
nop
bc1any4f $fcc4, text_label
nop
bc1any4t $fcc0, text_label
nop
bc1any4t $fcc4, text_label
nop
cabs.f.d $fcc0, $f8, $f19
cabs.f.d $fcc2, $f8, $f19
cabs.f.s $fcc0, $f8, $f19
cabs.f.s $fcc2, $f8, $f19
cabs.f.ps $fcc0, $f8, $f19
cabs.f.ps $fcc2, $f8, $f19
cabs.un.d $fcc0, $f8, $f19
cabs.un.d $fcc2, $f8, $f19
cabs.un.s $fcc0, $f8, $f19
cabs.un.s $fcc2, $f8, $f19
cabs.un.ps $fcc0, $f8, $f19
cabs.un.ps $fcc2, $f8, $f19
cabs.eq.d $fcc0, $f8, $f19
cabs.eq.d $fcc2, $f8, $f19
cabs.eq.s $fcc0, $f8, $f19
cabs.eq.s $fcc2, $f8, $f19
cabs.eq.ps $fcc0, $f8, $f19
cabs.eq.ps $fcc2, $f8, $f19
cabs.ueq.d $fcc0, $f8, $f19
cabs.ueq.d $fcc2, $f8, $f19
cabs.ueq.s $fcc0, $f8, $f19
cabs.ueq.s $fcc2, $f8, $f19
cabs.ueq.ps $fcc0, $f8, $f19
cabs.ueq.ps $fcc2, $f8, $f19
cabs.olt.d $fcc0, $f8, $f19
cabs.olt.d $fcc2, $f8, $f19
cabs.olt.s $fcc0, $f8, $f19
cabs.olt.s $fcc2, $f8, $f19
cabs.olt.ps $fcc0, $f8, $f19
cabs.olt.ps $fcc2, $f8, $f19
cabs.ult.d $fcc0, $f8, $f19
cabs.ult.d $fcc2, $f8, $f19
cabs.ult.s $fcc0, $f8, $f19
cabs.ult.s $fcc2, $f8, $f19
cabs.ult.ps $fcc0, $f8, $f19
cabs.ult.ps $fcc2, $f8, $f19
cabs.ole.d $fcc0, $f8, $f19
cabs.ole.d $fcc2, $f8, $f19
cabs.ole.s $fcc0, $f8, $f19
cabs.ole.s $fcc2, $f8, $f19
cabs.ole.ps $fcc0, $f8, $f19
cabs.ole.ps $fcc2, $f8, $f19
cabs.ule.d $fcc0, $f8, $f19
cabs.ule.d $fcc2, $f8, $f19
cabs.ule.s $fcc0, $f8, $f19
cabs.ule.s $fcc2, $f8, $f19
cabs.ule.ps $fcc0, $f8, $f19
cabs.ule.ps $fcc2, $f8, $f19
cabs.sf.d $fcc0, $f8, $f19
cabs.sf.d $fcc2, $f8, $f19
cabs.sf.s $fcc0, $f8, $f19
cabs.sf.s $fcc2, $f8, $f19
cabs.sf.ps $fcc0, $f8, $f19
cabs.sf.ps $fcc2, $f8, $f19
cabs.ngle.d $fcc0, $f8, $f19
cabs.ngle.d $fcc2, $f8, $f19
cabs.ngle.s $fcc0, $f8, $f19
cabs.ngle.s $fcc2, $f8, $f19
cabs.ngle.ps $fcc0, $f8, $f19
cabs.ngle.ps $fcc2, $f8, $f19
cabs.seq.d $fcc0, $f8, $f19
cabs.seq.d $fcc2, $f8, $f19
cabs.seq.s $fcc0, $f8, $f19
cabs.seq.s $fcc2, $f8, $f19
cabs.seq.ps $fcc0, $f8, $f19
cabs.seq.ps $fcc2, $f8, $f19
cabs.ngl.d $fcc0, $f8, $f19
cabs.ngl.d $fcc2, $f8, $f19
cabs.ngl.s $fcc0, $f8, $f19
cabs.ngl.s $fcc2, $f8, $f19
cabs.ngl.ps $fcc0, $f8, $f19
cabs.ngl.ps $fcc2, $f8, $f19
cabs.lt.d $fcc0, $f8, $f19
cabs.lt.d $fcc2, $f8, $f19
cabs.lt.s $fcc0, $f8, $f19
cabs.lt.s $fcc2, $f8, $f19
cabs.lt.ps $fcc0, $f8, $f19
cabs.lt.ps $fcc2, $f8, $f19
cabs.nge.d $fcc0, $f8, $f19
cabs.nge.d $fcc2, $f8, $f19
cabs.nge.s $fcc0, $f8, $f19
cabs.nge.s $fcc2, $f8, $f19
cabs.nge.ps $fcc0, $f8, $f19
cabs.nge.ps $fcc2, $f8, $f19
cabs.le.d $fcc0, $f8, $f19
cabs.le.d $fcc2, $f8, $f19
cabs.le.s $fcc0, $f8, $f19
cabs.le.s $fcc2, $f8, $f19
cabs.le.ps $fcc0, $f8, $f19
cabs.le.ps $fcc2, $f8, $f19
cabs.ngt.d $fcc0, $f8, $f19
cabs.ngt.d $fcc2, $f8, $f19
cabs.ngt.s $fcc0, $f8, $f19
cabs.ngt.s $fcc2, $f8, $f19
cabs.ngt.ps $fcc0, $f8, $f19
cabs.ngt.ps $fcc2, $f8, $f19
cvt.pw.ps $f4, $f19
cvt.ps.pw $f4, $f19
mulr.ps $f4, $f8, $f19
recip1.d $f8, $f19
recip1.s $f8, $f19
recip1.ps $f8, $f19
recip2.d $f4, $f8, $f19
recip2.s $f4, $f8, $f19
recip2.ps $f4, $f8, $f19
rsqrt1.d $f8, $f19
rsqrt1.s $f8, $f19
rsqrt1.ps $f8, $f19
rsqrt2.d $f4, $f8, $f19
rsqrt2.s $f4, $f8, $f19
rsqrt2.ps $f4, $f8, $f19
bc1any2f $fcc1, text_label # warns
nop
bc1any2t $fcc3, text_label # warns
nop
bc1any4f $fcc1, text_label # warns
nop
bc1any4t $fcc2, text_label # warns
nop
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,192
|
gas/testsuite/gas/mips/cp0m.s
|
.text
.set noreorder
foo:
lwc0 $0, 0($0)
lwc0 $1, 0($0)
lwc0 $2, 0($0)
lwc0 $3, 0($0)
lwc0 $4, 0($0)
lwc0 $5, 0($0)
lwc0 $6, 0($0)
lwc0 $7, 0($0)
lwc0 $8, 0($0)
lwc0 $9, 0($0)
lwc0 $10, 0($0)
lwc0 $11, 0($0)
lwc0 $12, 0($0)
lwc0 $13, 0($0)
lwc0 $14, 0($0)
lwc0 $15, 0($0)
lwc0 $16, 0($0)
lwc0 $17, 0($0)
lwc0 $18, 0($0)
lwc0 $19, 0($0)
lwc0 $20, 0($0)
lwc0 $21, 0($0)
lwc0 $22, 0($0)
lwc0 $23, 0($0)
lwc0 $24, 0($0)
lwc0 $25, 0($0)
lwc0 $26, 0($0)
lwc0 $27, 0($0)
lwc0 $28, 0($0)
lwc0 $29, 0($0)
lwc0 $30, 0($0)
lwc0 $31, 0($0)
swc0 $0, 0($0)
swc0 $1, 0($0)
swc0 $2, 0($0)
swc0 $3, 0($0)
swc0 $4, 0($0)
swc0 $5, 0($0)
swc0 $6, 0($0)
swc0 $7, 0($0)
swc0 $8, 0($0)
swc0 $9, 0($0)
swc0 $10, 0($0)
swc0 $11, 0($0)
swc0 $12, 0($0)
swc0 $13, 0($0)
swc0 $14, 0($0)
swc0 $15, 0($0)
swc0 $16, 0($0)
swc0 $17, 0($0)
swc0 $18, 0($0)
swc0 $19, 0($0)
swc0 $20, 0($0)
swc0 $21, 0($0)
swc0 $22, 0($0)
swc0 $23, 0($0)
swc0 $24, 0($0)
swc0 $25, 0($0)
swc0 $26, 0($0)
swc0 $27, 0($0)
swc0 $28, 0($0)
swc0 $29, 0($0)
swc0 $30, 0($0)
swc0 $31, 0($0)
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 9,323
|
gas/testsuite/gas/mips/set-arch.s
|
.text
.set noreorder
.set noat
.set arch=4010
flushi
flushd
flushid
madd $4,$5
maddu $5,$6
ffc $6,$7
ffs $7,$8
msub $8,$9
msubu $9,$10
selsl $10,$11,$12
selsr $11,$12,$13
waiti
wb 16($14)
addciu $14,$15,16
.set arch=4100
hibernate
standby
suspend
.set arch=4650
mad $4,$5
madu $5,$6
mul $6,$7,$8
# test mips4 instructions.
.set arch=mips4
text_label:
bc1f text_label
bc1f $fcc1,text_label
bc1fl $fcc1,text_label
bc1t $fcc1,text_label
bc1tl $fcc2,text_label
c.f.d $f4,$f6
c.f.d $fcc1,$f4,$f6
ldxc1 $f2,$4($5)
lwxc1 $f2,$4($5)
madd.d $f0,$f2,$f4,$f6
madd.s $f0,$f2,$f4,$f6
movf $4,$5,$fcc4
movf.d $f4,$f6,$fcc0
movf.s $f4,$f6,$fcc0
movn $4,$6,$6
movn.d $f4,$f6,$6
movn.s $f4,$f6,$6
movt $4,$5,$fcc4
movt.d $f4,$f6,$fcc0
movt.s $f4,$f6,$fcc0
movz $4,$6,$6
movz.d $f4,$f6,$6
movz.s $f4,$f6,$6
msub.d $f0,$f2,$f4,$f6
msub.s $f0,$f2,$f4,$f6
nmadd.d $f0,$f2,$f4,$f6
nmadd.s $f0,$f2,$f4,$f6
nmsub.d $f0,$f2,$f4,$f6
nmsub.s $f0,$f2,$f4,$f6
# We don't test pref because currently the disassembler will
# disassemble it as lwc3. lwc3 is correct for mips1 to mips3,
# while pref is correct for mips4. Unfortunately, the
# disassembler does not know which architecture it is
# disassembling for.
# pref 4,0($4)
prefx 4,$4($5)
recip.d $f4,$f6
recip.s $f4,$f6
rsqrt.d $f4,$f6
rsqrt.s $f4,$f6
sdxc1 $f4,$4($5)
swxc1 $f4,$4($5)
# test mips5 instructions.
.set arch=mips5
abs.ps $f0, $f2
add.ps $f2, $f4, $f6
alnv.ps $f6, $f8, $f10, $3
c.eq.ps $f8, $f10
c.eq.ps $fcc2, $f10, $f12
c.f.ps $f8, $f10
c.f.ps $fcc2, $f10, $f12
c.le.ps $f8, $f10
c.le.ps $fcc2, $f10, $f12
c.lt.ps $f8, $f10
c.lt.ps $fcc2, $f10, $f12
c.nge.ps $f8, $f10
c.nge.ps $fcc2, $f10, $f12
c.ngl.ps $f8, $f10
c.ngl.ps $fcc2, $f10, $f12
c.ngle.ps $f8, $f10
c.ngle.ps $fcc2, $f10, $f12
c.ngt.ps $f8, $f10
c.ngt.ps $fcc2, $f10, $f12
c.ole.ps $f8, $f10
c.ole.ps $fcc2, $f10, $f12
c.olt.ps $f8, $f10
c.olt.ps $fcc2, $f10, $f12
c.seq.ps $f8, $f10
c.seq.ps $fcc2, $f10, $f12
c.sf.ps $f8, $f10
c.sf.ps $fcc2, $f10, $f12
c.ueq.ps $f8, $f10
c.ueq.ps $fcc2, $f10, $f12
c.ule.ps $f8, $f10
c.ule.ps $fcc2, $f10, $f12
c.ult.ps $f8, $f10
c.ult.ps $fcc2, $f10, $f12
c.un.ps $f8, $f10
c.un.ps $fcc2, $f10, $f12
cvt.ps.s $f12, $f14, $f16
cvt.s.pl $f16, $f18
cvt.s.pu $f18, $f20
luxc1 $f20, $4($5)
madd.ps $f20, $f22, $f24, $f26
mov.ps $f24, $f26
movf.ps $f26, $f28, $fcc2
movn.ps $f26, $f28, $3
movt.ps $f28, $f30, $fcc4
movz.ps $f28, $f30, $5
msub.ps $f30, $f0, $f2, $f4
mul.ps $f2, $f4, $f6
neg.ps $f6, $f8
nmadd.ps $f6, $f8, $f10, $f12
nmsub.ps $f6, $f8, $f10, $f12
pll.ps $f10, $f12, $f14
plu.ps $f14, $f16, $f18
pul.ps $f16, $f18, $f20
puu.ps $f20, $f22, $f24
sub.ps $f22, $f24, $f26
suxc1 $f26, $6($7)
c.eq.ps $fcc3, $f10, $f12 # warns
movf.ps $f26, $f28, $fcc3 # warns
# test assembly of mips32 instructions
.set arch=mips32
# unprivileged CPU instructions
clo $1, $2
clz $3, $4
madd $5, $6
maddu $7, $8
msub $9, $10
msubu $11, $12
mul $13, $14, $15
pref 4, ($16)
pref 4, 32767($17)
pref 4, -32768($18)
ssnop
# unprivileged coprocessor instructions.
# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
bc2f text_label
nop
bc2fl text_label
nop
bc2t text_label
nop
bc2tl text_label
nop
# XXX other BCzCond encodings not currently expressable
cfc2 $1, $2
cop2 0x1234567 # disassembles as c2 ...
ctc2 $2, $3
mfc2 $3, $4
mfc2 $4, $5, 0 # disassembles without sel
mfc2 $5, $6, 7
mtc2 $6, $7
mtc2 $7, $8, 0 # disassembles without sel
mtc2 $8, $9, 7
# privileged instructions
cache 5, ($1)
cache 5, 32767($2)
cache 5, -32768($3)
eret
tlbp
tlbr
tlbwi
tlbwr
wait
wait 0 # disassembles without code
wait 0x56789
# For a while break for the mips32 ISA interpreted a single argument
# as a 20-bit code, placing it in the opcode differently to
# traditional ISAs. This turned out to cause problems, so it has
# been removed. This test is to assure consistent interpretation.
break
break 0 # disassembles without code
break 0x345
break 0x48,0x345 # this still specifies a 20-bit code
# Instructions in previous ISAs or CPUs which are now slightly
# different.
sdbbp
sdbbp 0 # disassembles without code
sdbbp 0x56789
# test assembly of mips32r2 instructions
.set arch=mips32r2
# unprivileged CPU instructions
ehb
ext $4, $5, 6, 8
ins $4, $5, 6, 8
jalr.hb $8
jalr.hb $20, $9
jr.hb $8
# Note, further testing of rdhwr is done in hwr-names-mips32r2.d
rdhwr $10, $0
rdhwr $11, $1
rdhwr $12, $2
rdhwr $13, $3
rdhwr $14, $4
rdhwr $15, $5
# This file checks that in fact HW rotate will
# be used for this arch, and checks assembly
# of the official MIPS mnemonics. (Note that disassembly
# uses the traditional "ror" and "rorv" mnemonics.)
# Additional rotate tests are done by rol-hw.d.
rotl $25, $10, 4
rotr $25, $10, 4
rotl $25, $10, $4
rotr $25, $10, $4
rotrv $25, $10, $4
seb $7
seb $8, $10
seh $7
seh $8, $10
synci 0x5555($10)
wsbh $7
wsbh $8, $10
# cp0 instructions
di
di $0
di $10
ei
ei $0
ei $10
rdpgpr $10, $25
wrpgpr $10, $25
# FPU (cp1) instructions
#
# Even registers are supported w/ 32-bit FPU, odd
# registers supported only for 64-bit FPU.
# Only the 32-bit FPU instructions are tested here.
mfhc1 $17, $f0
mthc1 $17, $f0
# cp2 instructions
mfhc2 $17, 0x5555
mthc2 $17, 0x5555
.set arch=mips64
# test assembly of mips64 instructions
# unprivileged CPU instructions
dclo $1, $2
dclz $3, $4
# unprivileged coprocessor instructions.
# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
dmfc2 $3, $4
dmfc2 $4, $5, 0 # disassembles without sel
dmfc2 $5, $6, 7
dmtc2 $6, $7
dmtc2 $7, $8, 0 # disassembles without sel
dmtc2 $8, $9, 7
.set arch=vr4111
dmadd16 $4,$5
madd16 $5,$6
.set arch=vr4120
# Include mflos to check for nop insertion.
mflo $4
dmacc $4,$5,$6
dmacchi $4,$5,$6
dmacchis $4,$5,$6
dmacchiu $4,$5,$6
dmacchius $4,$5,$6
dmaccs $4,$5,$6
dmaccu $4,$5,$6
dmaccus $4,$5,$6
mflo $4
macc $4,$5,$6
macchi $4,$5,$6
macchis $4,$5,$6
macchiu $4,$5,$6
macchius $4,$5,$6
maccs $4,$5,$6
maccu $4,$5,$6
maccus $4,$5,$6
.set arch=vr5400
/* Integer instructions. */
mulu $4,$5,$6
mulhi $4,$5,$6
mulhiu $4,$5,$6
muls $4,$5,$6
mulsu $4,$5,$6
mulshi $4,$5,$6
mulshiu $4,$5,$6
macc $4,$5,$6
maccu $4,$5,$6
macchi $4,$5,$6
macchiu $4,$5,$6
msac $4,$5,$6
msacu $4,$5,$6
msachi $4,$5,$6
msachiu $4,$5,$6
ror $4,$5,25
rorv $4,$5,$6
dror $4,$5,25
dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */
dror32 $4,$5,25
drorv $4,$5,$6
/* Debug instructions. */
dbreak
dret
mfdr $3,$3
mtdr $3,$3
/* Coprocessor 0 instructions, minus standard ISA 3 ones.
That leaves just the performance monitoring registers. */
mfpc $4,1
mfps $4,1
mtpc $4,1
mtps $4,1
/* Multimedia instructions. */
.macro nsel2 op
/* Test each form of each vector opcode. */
\op $f0,$f2
\op $f4,$f6[2]
\op $f6,15
.if 0 /* Which is right?? */
/* Test negative numbers in immediate-value slot. */
\op $f4,-3
.else
/* Test that it's recognized as an unsigned field. */
\op $f4,31
.endif
.endm
.macro nsel3 op
/* Test each form of each vector opcode. */
\op $f0,$f2,$f4
\op $f2,$f4,$f6[2]
\op $f6,$f4,15
.if 0 /* Which is right?? */
/* Test negative numbers in immediate-value slot. */
\op $f4,$f6,-3
.else
/* Test that it's recognized as an unsigned field. */
\op $f4,$f6,31
.endif
.endm
nsel3 add.ob
nsel3 and.ob
nsel2 c.eq.ob
nsel2 c.le.ob
nsel2 c.lt.ob
nsel3 max.ob
nsel3 min.ob
nsel3 mul.ob
nsel2 mula.ob
nsel2 mull.ob
nsel2 muls.ob
nsel2 mulsl.ob
nsel3 nor.ob
nsel3 or.ob
nsel3 pickf.ob
nsel3 pickt.ob
nsel3 sub.ob
nsel3 xor.ob
/* ALNI, SHFL: Vector only. */
alni.ob $f0,$f2,$f4,5
shfl.mixh.ob $f0,$f2,$f4
shfl.mixl.ob $f0,$f2,$f4
shfl.pach.ob $f0,$f2,$f4
shfl.pacl.ob $f0,$f2,$f4
/* SLL,SRL: Scalar or immediate. */
sll.ob $f2,$f4,$f6[3]
sll.ob $f4,$f6,14
srl.ob $f2,$f4,$f6[3]
srl.ob $f4,$f6,14
/* RZU: Immediate, must be 0, 8, or 16. */
rzu.ob $f2,13
/* No selector. */
rach.ob $f2
racl.ob $f2
racm.ob $f2
wach.ob $f2
wacl.ob $f2,$f4
ror $4,$5,$6
rol $4,$5,15
dror $4,$5,$6
drol $4,$5,31
drol $4,$5,62
.set arch=vr5500
/* Prefetch instructions. */
# We don't test pref because currently the disassembler will
# disassemble it as lwc3. lwc3 is correct for mips1 to mips3,
# while pref is correct for mips4. Unfortunately, the
# disassembler does not know which architecture it is
# disassembling for.
# pref 4,0($4)
prefx 4,$4($5)
/* Miscellaneous instructions. */
wait
wait 0 # disassembles without code
wait 0x56789
ssnop
clo $3,$4
dclo $3,$4
clz $3,$4
dclz $3,$4
luxc1 $f0,$4($2)
suxc1 $f2,$4($2)
tlbp
tlbr
.set arch=default
# make objdump print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 2,392
|
gas/testsuite/gas/mips/octeon.s
|
.text
.set noreorder
foo:
baddu $17,$18,$19
baddu $2,$3
bbit0 $19,22,foo
nop
bbit032 $30,11,foo
nop
bbit0 $8,42,foo
nop
bbit1 $3,31,foo
nop
bbit132 $24,10,foo
nop
bbit1 $14,46,foo
nop
cins $25,$10,22,2
cins $9,17,29
cins32 $15,$2,18,8
cins32 $22,9,22
cins $24,$31,32,31
cins $15,37,5
dmul $19,$24,$28
dmul $21,$25
exts $4,$28,27,15
exts $15,17,6
exts32 $4,$13,10,8
exts32 $15,11,20
exts $7,$4,54,9
exts $25,37,25
mfc0 $13,$25
mfc0 $13,$11,7
mtc0 $6,$2
mtc0 $21,$9,6
dmfc0 $3,$29
dmfc0 $11,$20,5
dmtc0 $23,$2
dmtc0 $7,$14,2
di
ei
dmfc2 $3,0x84
dmfc2 $6,0x800
dmfc2 $12,0x1
dmtc2 $8,0x4200
dmtc2 $7,0x2000
dmtc2 $2,0x4
mtm0 $26
mtm1 $19
mtm2 $18
mtp0 $16
mtp1 $25
mtp2 $9
pop $8,$19
pop $2
dpop $15,$22
dpop $12
seq $29,$23,$24
seq $6,$28
seqi $17,$15,-512
seqi $16,38
seq $5,$4,-274 # seqi
seq $12,511 # seqi
seq $30,$25,512 # xori $30,$25,512;sltiu $30,$30,1
seq $2,$12,-777 # daddiu $2,$12,777;sltiu $2,$2,1
seq $10,$30,0x10000 # lui $1,0x1; seq $10,$30,$1
seq $30,$25,-47366 # lui $1,0xffff; ori $1,$1,0x46fa; seq $30,$25,$1
sne $6,$2,$2
sne $23,$20
snei $4,$16,-313
snei $26,511
sne $21,$23,-512 # snei
sne $12,81 # snei
sne $4,$14,889 # xori $4,$14,889;sltu $4,$0,$4
sne $24,$13,-513 # daddiu $24,$13,513;sltu $24,$0,$24
sne $10,$30,119250 # lui $1,0x1; ori $1,$1,0xd1d2; sne $10,$30,$1
sne $30,$25,-0x8000 # li $1,-32768; sne $30,$25,$1
synciobdma
syncs
syncw
syncws
v3mulu $21,$10,$21
v3mulu $20,$10
vmm0 $3,$19,$16
vmm0 $31,$9
vmulu $29,$10,$17
vmulu $27,$6
|
tactcomplabs/xbgas-binutils-gdb
| 3,310
|
gas/testsuite/gas/mips/c2.s
|
.text
foo:
c2 0x00
c2 0x01
c2 0x02
c2 0x03
c2 0x04
c2 0x05
c2 0x06
c2 0x07
c2 0x08
c2 0x09
c2 0x0a
c2 0x0b
c2 0x0c
c2 0x0d
c2 0x0e
c2 0x0f
c2 0x10
c2 0x11
c2 0x12
c2 0x13
c2 0x14
c2 0x15
c2 0x16
c2 0x17
c2 0x18
c2 0x19
c2 0x1a
c2 0x1b
c2 0x1c
c2 0x1d
c2 0x1e
c2 0x1f
c2 0x20
c2 0x21
c2 0x22
c2 0x23
c2 0x24
c2 0x25
c2 0x26
c2 0x27
c2 0x28
c2 0x29
c2 0x2a
c2 0x2b
c2 0x2c
c2 0x2d
c2 0x2e
c2 0x2f
c2 0x30
c2 0x31
c2 0x32
c2 0x33
c2 0x34
c2 0x35
c2 0x36
c2 0x37
c2 0x38
c2 0x39
c2 0x3a
c2 0x3b
c2 0x3c
c2 0x3d
c2 0x3e
c2 0x3f
c2 0x1000000
c2 0x1000001
c2 0x1000002
c2 0x1000003
c2 0x1000004
c2 0x1000005
c2 0x1000006
c2 0x1000007
c2 0x1000008
c2 0x1000009
c2 0x100000a
c2 0x100000b
c2 0x100000c
c2 0x100000d
c2 0x100000e
c2 0x100000f
c2 0x1000010
c2 0x1000011
c2 0x1000012
c2 0x1000013
c2 0x1000014
c2 0x1000015
c2 0x1000016
c2 0x1000017
c2 0x1000018
c2 0x1000019
c2 0x100001a
c2 0x100001b
c2 0x100001c
c2 0x100001d
c2 0x100001e
c2 0x100001f
c2 0x1000020
c2 0x1000021
c2 0x1000022
c2 0x1000023
c2 0x1000024
c2 0x1000025
c2 0x1000026
c2 0x1000027
c2 0x1000028
c2 0x1000029
c2 0x100002a
c2 0x100002b
c2 0x100002c
c2 0x100002d
c2 0x100002e
c2 0x100002f
c2 0x1000030
c2 0x1000031
c2 0x1000032
c2 0x1000033
c2 0x1000034
c2 0x1000035
c2 0x1000036
c2 0x1000037
c2 0x1000038
c2 0x1000039
c2 0x100003a
c2 0x100003b
c2 0x100003c
c2 0x100003d
c2 0x100003e
c2 0x100003f
cop2 0x00
cop2 0x01
cop2 0x02
cop2 0x03
cop2 0x04
cop2 0x05
cop2 0x06
cop2 0x07
cop2 0x08
cop2 0x09
cop2 0x0a
cop2 0x0b
cop2 0x0c
cop2 0x0d
cop2 0x0e
cop2 0x0f
cop2 0x10
cop2 0x11
cop2 0x12
cop2 0x13
cop2 0x14
cop2 0x15
cop2 0x16
cop2 0x17
cop2 0x18
cop2 0x19
cop2 0x1a
cop2 0x1b
cop2 0x1c
cop2 0x1d
cop2 0x1e
cop2 0x1f
cop2 0x20
cop2 0x21
cop2 0x22
cop2 0x23
cop2 0x24
cop2 0x25
cop2 0x26
cop2 0x27
cop2 0x28
cop2 0x29
cop2 0x2a
cop2 0x2b
cop2 0x2c
cop2 0x2d
cop2 0x2e
cop2 0x2f
cop2 0x30
cop2 0x31
cop2 0x32
cop2 0x33
cop2 0x34
cop2 0x35
cop2 0x36
cop2 0x37
cop2 0x38
cop2 0x39
cop2 0x3a
cop2 0x3b
cop2 0x3c
cop2 0x3d
cop2 0x3e
cop2 0x3f
cop2 0x1000000
cop2 0x1000001
cop2 0x1000002
cop2 0x1000003
cop2 0x1000004
cop2 0x1000005
cop2 0x1000006
cop2 0x1000007
cop2 0x1000008
cop2 0x1000009
cop2 0x100000a
cop2 0x100000b
cop2 0x100000c
cop2 0x100000d
cop2 0x100000e
cop2 0x100000f
cop2 0x1000010
cop2 0x1000011
cop2 0x1000012
cop2 0x1000013
cop2 0x1000014
cop2 0x1000015
cop2 0x1000016
cop2 0x1000017
cop2 0x1000018
cop2 0x1000019
cop2 0x100001a
cop2 0x100001b
cop2 0x100001c
cop2 0x100001d
cop2 0x100001e
cop2 0x100001f
cop2 0x1000020
cop2 0x1000021
cop2 0x1000022
cop2 0x1000023
cop2 0x1000024
cop2 0x1000025
cop2 0x1000026
cop2 0x1000027
cop2 0x1000028
cop2 0x1000029
cop2 0x100002a
cop2 0x100002b
cop2 0x100002c
cop2 0x100002d
cop2 0x100002e
cop2 0x100002f
cop2 0x1000030
cop2 0x1000031
cop2 0x1000032
cop2 0x1000033
cop2 0x1000034
cop2 0x1000035
cop2 0x1000036
cop2 0x1000037
cop2 0x1000038
cop2 0x1000039
cop2 0x100003a
cop2 0x100003b
cop2 0x100003c
cop2 0x100003d
cop2 0x100003e
cop2 0x100003f
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 1,688
|
gas/testsuite/gas/mips/ase-errors-4.s
|
.set micromips
.set mips64r2
.set dsp # OK
lbux $4,$5($6) # OK
ldx $4,$5($6) # ERROR: micromips doesn't have 64-bit DSPr1
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips3 # OK (we assume r2 anyway)
.set nodsp
lbux $4,$5($6) # ERROR: dsp not enabled
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips64r2
.set dspr2 # OK
lbux $4,$5($6) # OK
absq_s.qb $3,$4 # OK
.set mips3 # OK (we assume r2 anyway)
.set nodspr2
lbux $4,$5($6) # ERROR: dsp not enabled
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips64r2
.set mcu # OK
aclr 4,100($4) # OK
.set mips3 # OK (we assume r2 anyway)
.set nomcu
aclr 4,100($4) # ERROR: mcu not enabled
.set mips64r2
.set mdmx # ERROR: not supported at all
add.ob $f4,$f6,$f8 # ERROR: not supported at all
.set nomdmx
.set mips64r2
.set mips3d # ERROR: not supported at all
addr.ps $f4,$f6,$f8 # ERROR: not supported at all
.set nomips3d
.set mips64r2
.set mt # ERROR: not supported at all
dmt # ERROR: not supported at all
.set nomt
.set mips64
.set smartmips # ERROR: not supported at all
maddp $4,$5 # ERROR: not supported at all
.set nosmartmips
.set mips64r2
.set virt # OK
hypcall # OK
dmfgc0 $3, $29 # OK
.set mips3 # OK (we assume r2 anyway)
.set novirt
hypcall # ERROR: virt not enabled
dmfgc0 $3, $29 # ERROR: virt not enabled
.set mips64r2
.set eva # OK
lbue $4,16($5) # OK
.set mips3 # OK (we assume r2 anyway)
lbue $4,16($5) # OK
.set noeva
lbue $4,16($5) # ERROR: eva not enabled
# There should be no errors after this.
.set fp=32
.set mips4
.set dsp
.set dspr2
.set mcu
.set mdmx
.set mips3d
.set mt
.set smartmips
.set eva
|
tactcomplabs/xbgas-binutils-gdb
| 1,351
|
gas/testsuite/gas/mips/unaligned-jump-mips16-2.s
|
.text
.set noreorder
.space 0x1000
.align 4
.set mips16
.ent foo
foo:
not $2, $2
jalx bar0
not $2, $2
jal bar0
not $2, $2
jalx bar1
not $2, $2
jal bar1
not $2, $2
jalx bar2
not $2, $2
jal bar2
not $2, $2
jalx bar3
not $2, $2
jal bar3
not $2, $2
jalx bar4
not $2, $2
jal bar4
not $2, $2
jalx bar4 + 1
not $2, $2
jal bar4 + 1
not $2, $2
jalx bar4 + 2
not $2, $2
jal bar4 + 2
not $2, $2
jalx bar4 + 3
not $2, $2
jal bar4 + 3
not $2, $2
jalx bar4 + 4
not $2, $2
jal bar4 + 4
not $2, $2
jalx bar16
not $2, $2
jal bar16
not $2, $2
jalx bar17
not $2, $2
jal bar17
not $2, $2
jalx bar18
not $2, $2
jal bar18
not $2, $2
jalx bar18 + 1
not $2, $2
jal bar18 + 1
not $2, $2
jalx bar18 + 2
not $2, $2
jal bar18 + 2
not $2, $2
jalx bar18 + 3
not $2, $2
jal bar18 + 3
not $2, $2
jalx bar18 + 4
not $2, $2
jal bar18 + 4
not $2, $2
jr $ra
not $2, $2
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.globl bar\@
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.globl bar\@
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,039
|
gas/testsuite/gas/mips/24k-triple-stores-4.s
|
# Range check for safe case after alignment its range >= 32.
foo:
sb $s3,10($t0)
sh $s3,1($t0)
sb $s3,32($t0)
break
sb $s3,10($t0)
sb $s3,1($t0)
sh $s3,32($t0)
break
sb $s3,33($t0)
sh $s3,55($t0)
sb $s3,64($t0)
break
sb $s3,33($t0)
sb $s3,55($t0)
sh $s3,64($t0)
break
sb $s3,12($t0)
sw $s3,1($t0)
sb $s3,32($t0)
break
sb $s3,12($t0)
sb $s3,1($t0)
sw $s3,32($t0)
break
sb $s3,35($t0)
sw $s3,55($t0)
sb $s3,64($t0)
break
sb $s3,35($t0)
sb $s3,55($t0)
sw $s3,64($t0)
break
sb $s3,16($t0)
sdc1 $f0,1($t0)
sb $s3,32($t0)
break
sb $s3,16($t0)
sb $s3,1($t0)
sdc1 $f0,32($t0)
break
sb $s3,39($t0)
sdc1 $f0,55($t0)
sb $s3,64($t0)
break
sb $s3,39($t0)
sb $s3,55($t0)
sdc1 $f0,64($t0)
break
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,294
|
gas/testsuite/gas/mips/mips32r2-ill.s
|
# source file to test illegal mips32r2 instructions
.set noreorder
.set noat
.text
text_label:
# insert and extract position/size checks:
# ext constraint: 0 <= pos < 32
ext $4, $5, -1, 1 # error
ext $4, $5, 0, 1
ext $4, $5, 31, 1
ext $4, $5, 32, 1 # error
# ext constraint: 0 < size <= 32
ext $4, $5, 0, 0 # error
ext $4, $5, 0, 1
ext $4, $5, 0, 32
ext $4, $5, 0, 33 # error
# ext constraint: 0 < (pos+size) <= 32
ext $4, $5, 0, 0 # error
ext $4, $5, 0, 1
ext $4, $5, 31, 1
ext $4, $5, 31, 2 # error
# ins constraint: 0 <= pos < 32
ins $4, $5, -1, 1 # error
ins $4, $5, 0, 1
ins $4, $5, 31, 1
ins $4, $5, 32, 1 # error
# ins constraint: 0 < size <= 32
ins $4, $5, 0, 0 # error
ins $4, $5, 0, 1
ins $4, $5, 0, 32
ins $4, $5, 0, 33 # error
# ins constraint: 0 < (pos+size) <= 32
ins $4, $5, 0, 0 # error
ins $4, $5, 0, 1
ins $4, $5, 31, 1
ins $4, $5, 31, 2 # error
# FP register checks.
#
# Even registers are supported w/ 32-bit FPU, odd
# registers supported only for 64-bit FPU.
# This file tests 32-bit FPU.
mfhc1 $17, $f0
mfhc1 $17, $f1 # warn
mthc1 $17, $f0
mthc1 $17, $f1 # warn
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,319
|
gas/testsuite/gas/mips/ldstla-sym32.s
|
dla $4,0xa800000000000000
dla $4,0xa800000000000000($3)
dla $4,0xffffffff80000000
dla $4,0xffffffff80000000($3)
dla $4,0x000000007fff7ff8
dla $4,0x000000007fff7ff8($3)
dla $4,0x000000007ffffff8
dla $4,0x000000007ffffff8($3)
dla $4,0x123456789abcdef0
dla $4,0x123456789abcdef0($3)
dla $4,small_comm
dla $4,small_comm($3)
dla $4,small_comm+3
dla $4,small_comm+3($3)
dla $4,big_comm
dla $4,big_comm($3)
dla $4,big_comm+3
dla $4,big_comm+3($3)
dla $4,small_data
dla $4,small_data($3)
dla $4,small_data+3
dla $4,small_data+3($3)
dla $4,big_data
dla $4,big_data($3)
dla $4,big_data+3
dla $4,big_data+3($3)
dla $4,extern
dla $4,extern($3)
dla $4,extern + 0x34000
dla $4,extern + 0x34000($3)
dla $4,extern - 0x34000
dla $4,extern - 0x34000($3)
lw $4,0xa800000000000000
lw $4,0xa800000000000000($3)
lw $4,0xffffffff80000000
lw $4,0xffffffff80000000($3)
lw $4,0x000000007fff7ff8
lw $4,0x000000007fff7ff8($3)
lw $4,0x000000007ffffff8
lw $4,0x000000007ffffff8($3)
lw $4,0x123456789abcdef0
lw $4,0x123456789abcdef0($3)
lw $4,small_comm
lw $4,small_comm($3)
lw $4,small_comm+3
lw $4,small_comm+3($3)
lw $4,big_comm
lw $4,big_comm($3)
lw $4,big_comm+3
lw $4,big_comm+3($3)
lw $4,small_data
lw $4,small_data($3)
lw $4,small_data+3
lw $4,small_data+3($3)
lw $4,big_data
lw $4,big_data($3)
lw $4,big_data+3
lw $4,big_data+3($3)
lw $4,extern
lw $4,extern($3)
lw $4,extern + 0x34000
lw $4,extern + 0x34000($3)
lw $4,extern - 0x34000
lw $4,extern - 0x34000($3)
sw $4,0xa800000000000000
sw $4,0xa800000000000000($3)
sw $4,0xffffffff80000000
sw $4,0xffffffff80000000($3)
sw $4,0x000000007fff7ff8
sw $4,0x000000007fff7ff8($3)
sw $4,0x000000007ffffff8
sw $4,0x000000007ffffff8($3)
sw $4,0x123456789abcdef0
sw $4,0x123456789abcdef0($3)
sw $4,small_comm
sw $4,small_comm($3)
sw $4,small_comm+3
sw $4,small_comm+3($3)
sw $4,big_comm
sw $4,big_comm($3)
sw $4,big_comm+3
sw $4,big_comm+3($3)
sw $4,small_data
sw $4,small_data($3)
sw $4,small_data+3
sw $4,small_data+3($3)
sw $4,big_data
sw $4,big_data($3)
sw $4,big_data+3
sw $4,big_data+3($3)
sw $4,extern
sw $4,extern($3)
sw $4,extern + 0x34000
sw $4,extern + 0x34000($3)
sw $4,extern - 0x34000
sw $4,extern - 0x34000($3)
usw $4,0xa800000000000000
usw $4,0xa800000000000000($3)
usw $4,0xffffffff80000000
usw $4,0xffffffff80000000($3)
usw $4,0x000000007fff7ff8
usw $4,0x000000007fff7ff8($3)
usw $4,0x000000007ffffff8
usw $4,0x000000007ffffff8($3)
usw $4,0x123456789abcdef0
usw $4,0x123456789abcdef0($3)
usw $4,small_comm
usw $4,small_comm($3)
usw $4,small_comm+3
usw $4,small_comm+3($3)
usw $4,big_comm
usw $4,big_comm($3)
usw $4,big_comm+3
usw $4,big_comm+3($3)
usw $4,small_data
usw $4,small_data($3)
usw $4,small_data+3
usw $4,small_data+3($3)
usw $4,big_data
usw $4,big_data($3)
usw $4,big_data+3
usw $4,big_data+3($3)
usw $4,extern
usw $4,extern($3)
usw $4,extern + 0x34000
usw $4,extern + 0x34000($3)
usw $4,extern - 0x34000
usw $4,extern - 0x34000($3)
.set nosym32
dla $4,extern
lw $4,extern
sw $4,extern
usw $4,extern
.set sym32
dla $4,extern
lw $4,extern
sw $4,extern
usw $4,extern
.section .sdata
.globl small_data
small_data:
.fill 16
.data
.globl big_data
big_data:
.fill 16
.comm small_comm,8
.comm big_comm,16
|
tactcomplabs/xbgas-binutils-gdb
| 92,111
|
gas/testsuite/gas/mips/micromips.s
|
.text
.align 3
.set micromips
.ifdef compact
.macro DSNOP
.endm
.else
.macro DSNOP
nop
.endm
.endif
.ent test
.globl test
test:
pref 0, 0
pref 0, 2047
pref 0, -2048
pref 0, 2048
pref 0, -2049
pref 0, ($0)
pref 0, 0($0)
pref 1, 0($0)
pref 2, 0($0)
pref 3, 0($0)
pref 4, 0($0)
pref 5, 0($0)
pref 6, 0($0)
pref 7, 0($0)
pref 7, 511($0)
pref 7, -512($0)
pref 31, 2047($0)
pref 31, -2048($0)
pref 31, 2048($0)
pref 31, -2049($0)
pref 3, 32767($0)
pref 3, -32768($0)
pref 31, 2047($2)
pref 31, -2048($2)
pref 31, 2048($2)
pref 31, -2049($2)
pref 3, 32767($2)
pref 3, -32768($2)
nop
.ifndef insn32
nop16
.endif
nop32
ssnop
ehb
pause
li $2, -1
li $3, -1
li $4, -1
li $5, -1
li $6, -1
li $7, -1
li $16, -1
li $17, -1
li $17, 0
li $17, 125
li $17, 126
li $17, 127
li32 $2, 0
li32 $2, 1
li $2, 32767
li $2, -32768
li $2, 65535
li $2, 65536
li $2, 0xffff8000
li $2, 0xffff8001
li $2, 0xffffffff
li $2, 0x12345678
move $0, $22
move $2, $22
move $3, $22
move $4, $22
move $5, $22
move $6, $22
move $7, $22
move $8, $22
move $9, $22
move $10, $22
move $30, $22
move $31, $22
move $0, $0
move $0, $2
move $0, $3
move $0, $4
move $0, $5
move $0, $6
move $0, $7
move $0, $8
move $0, $9
move $0, $10
move $0, $30
move $0, $31
move $22, $2
.ifndef insn32
move16 $2, $22
move16 $22, $2
.endif
move32 $2, $22
move32 $22, $2
b test
.ifndef insn32
b16 test
.endif
DSNOP
b32 test
DSNOP
b 1f
.ifndef insn32
b16 1f
.endif
DSNOP
b32 1f
1:
DSNOP
b 1b
.ifndef insn32
b16 1b
.endif
DSNOP
b32 1b
abs $2, $3
abs $2, $4
abs $2, $2
abs $2
add $2, $3, $4
add $29, $30, $31
add $2, $2, $4
add $2, $4
add $2, $2, 0
add $2, $2, 1
add $2, $2, 32767
add $2, $2, -32768
add $2, $2, 65535
addi $3, $4, -32768
addi $3, $4, 0
addi $3, $4, 32767
addi $3, $4, 65535
addi $3, $3, 65535
addi $3, 65535
addiu $0, -8
addiu $2, -8
addiu $3, -8
addiu $4, -8
addiu $5, -8
addiu $6, -8
addiu $7, -8
addiu $8, -8
addiu $9, -8
addiu $10, -8
addiu $30, -8
addiu $31, -8
addiu $31, -7
addiu $31, 0
addiu $31, 1
addiu $31, 6
addiu $31, 7
addiu $31, 8
addiu $29, -258 << 2
addiu $29, -257 << 2
addiu $29, -256 << 2
addiu $29, 255 << 2
addiu $29, 256 << 2
addiu $29, 257 << 2
addiu $29, $29, 257 << 2
addiu $29, $29, 258 << 2
addiu $2, $2, -1
addiu $2, $3, -1
addiu $2, $4, -1
addiu $2, $5, -1
addiu $2, $6, -1
addiu $2, $7, -1
addiu $2, $16, -1
addiu $2, $17, -1
addiu $2, $17, 1
addiu $2, $17, 4
addiu $2, $17, 8
addiu $2, $17, 12
addiu $2, $17, 16
addiu $2, $17, 20
addiu $2, $17, 24
addiu $3, $17, 24
addiu $4, $17, 24
addiu $5, $17, 24
addiu $6, $17, 24
addiu $7, $17, 24
addiu $16, $17, 24
addiu $17, $17, 24
addiu $2, $29, 0 << 2
addiu $2, $29, 1 << 2
addiu $2, $29, 62 << 2
addiu $2, $29, 63 << 2
addiu $2, $29, 64 << 2
addiu $2, $29, 63 << 2
addiu $3, $29, 63 << 2
addiu $4, $29, 63 << 2
addiu $5, $29, 63 << 2
addiu $6, $29, 63 << 2
addiu $7, $29, 63 << 2
addiu $16, $29, 63 << 2
addiu $17, $29, 63 << 2
addiu $3, $4, -32768
addiu $3, $4, 0
addiu $3, $4, 32767
addiu $3, $4, 65535
addiu $3, $3, 65535
addiu $3, 65535
addu $2, $22, $0
addu $22, $2, $0
addu $2, $0, $22
addu $22, $0, $2
addu $2, $3, $2
addu $2, $3, $3
addu $2, $3, $4
addu $2, $3, $5
addu $2, $3, $6
addu $2, $3, $7
addu $2, $3, $16
addu $2, $3, $17
addu $2, $2, $17
addu $2, $3, $17
addu $2, $4, $17
addu $2, $5, $17
addu $2, $6, $17
addu $2, $7, $17
addu $2, $16, $17
addu $2, $17, $17
addu $2, $2, $17
addu $3, $2, $17
addu $4, $2, $17
addu $5, $2, $17
addu $6, $2, $17
addu $7, $2, $17
addu $16, $2, $17
addu $17, $2, $17
addu $7, $7, $2
addu $7, $2
addu $7, $2, $7
addu $29, $30, $31
addu $2, $2, 0
addu $2, $2, 1
addu $2, $2, 32767
addu $2, $2, -32768
addu $2, $2, 65535
and $2, $2
and $2, $3
and $2, $4
and $2, $5
and $2, $6
and $2, $7
and $2, $16
and $2, $17
and $3, $2
and $4, $2
and $5, $2
and $6, $2
and $7, $2
and $16, $2
and $17, $2
and $2, $3
and $2, $2, $3
and $2, $3, $2
.ifndef insn32
and16 $2, $2, $3
.endif
and32 $2, $2, $3
andi $2,$2,1
andi $2,$2,2
andi $2,$2,3
andi $2,$2,4
andi $2,$2,7
andi $2,$2,8
andi $2,$2,15
andi $2,$2,16
andi $2,$2,31
andi $2,$2,32
andi $2,$2,63
andi $2,$2,64
andi $2,$2,128
andi $2,$2,255
andi $2,$2,32768
andi $2,$2,65535
andi $2,$3,65535
andi $2,$4,65535
andi $2,$5,65535
andi $2,$6,65535
andi $2,$7,65535
andi $2,$16,65535
andi $2,$17,65535
andi $3,$17,65535
andi $4,$17,65535
andi $5,$17,65535
andi $6,$17,65535
andi $7,$17,65535
andi $16,$17,65535
andi $17,$17,65535
andi $7,$7,65535
andi $7,65535
.ifndef insn32
andi16 $7,65535
.endif
andi32 $7,65535
and32 $2, $3, $4
and32 $2, $2, $4
and32 $2, $4
and $2, $3, 0
and $2, $3, 65535
and $2, $3, 65536
and $2, $3, 0xffff0001
bc2f test
bc2f $cc0, test
bc2f $cc1, test
bc2f $cc2, test
bc2f $cc3, test
bc2f $cc4, test
bc2f $cc5, test
bc2f $cc6, test
bc2f $cc7, test
bc2t test
bc2t $cc0, test
bc2t $cc1, test
bc2t $cc2, test
bc2t $cc3, test
bc2t $cc4, test
bc2t $cc5, test
bc2t $cc6, test
bc2t $cc7, test
.set noreorder
bc2fl $cc1, test
addu $3, $4, $5
bc2tl $cc2, test
addu $6, $7, $8
.set reorder
bc2fl $cc3, test
addu $3, $4, $5
bc2tl $cc4, test
addu $6, $7, $8
test2:
DSNOP
beqz $2, test2
DSNOP
beqz $3, test2
DSNOP
beqz $4, test2
DSNOP
beqz $5, test2
DSNOP
beqz $6, test2
DSNOP
beqz $7, test2
DSNOP
beqz $16, test2
DSNOP
beqz $17, test2
DSNOP
beq $2, $0, test2
DSNOP
beq $3, $0, test2
DSNOP
beq $4, $0, test2
DSNOP
beq $5, $0, test2
DSNOP
beq $6, $0, test2
DSNOP
beq $7, $0, test2
DSNOP
beq $16, $0, test2
DSNOP
beq $17, $0, test2
DSNOP
beq $0, $2, test2
DSNOP
beq $0, $3, test2
DSNOP
beq $0, $4, test2
DSNOP
beq $0, $5, test2
DSNOP
beq $0, $6, test2
DSNOP
beq $0, $7, test2
DSNOP
beq $0, $16, test2
DSNOP
beq $0, $17, test2
.ifndef insn32
beqz16 $16, test2
.endif
DSNOP
beqz32 $16, test2
DSNOP
beqz $17, test2
DSNOP
beqz32 $17, test2
beqzc $17, test2
DSNOP
beq $16, 0, test2
beq $16, 10, test2
beq $16, 32767, test2
beq $16, 65536, test2
.set noreorder
beql $16, $17, test2
addu $3, $4, $5
beql $16, $17, 1f
addu $3, $4, $5
beql $16, 0, test2
addu $3, $4, $5
beql $16, 0, 1f
addu $3, $4, $5
beql $16, 10, test2
addu $3, $4, $5
beql $16, 10, 1f
addu $3, $4, $5
beql $16, 32767, test2
addu $3, $4, $5
beql $16, 32767, 1f
addu $3, $4, $5
beql $16, 65535, test2
addu $3, $4, $5
beql $16, 65535, 1f
addu $3, $4, $5
beql $16, $17, test2
addu $3, $4, $29
beql $16, $17, 1f
addu $3, $4, $29
beql $16, 0, test2
addu $3, $4, $29
beql $16, 0, 1f
addu $3, $4, $29
beql $16, 10, test2
addu $3, $4, $29
beql $16, 10, 1f
addu $3, $4, $29
beql $16, 32767, test2
addu $3, $4, $29
beql $16, 32767, 1f
addu $3, $4, $29
beql $16, 65535, test2
addu $3, $4, $29
beql $16, 65535, 1f
addu $3, $4, $29
1:
.set reorder
beql $16, $17, test2
beqzl $17, test2
DSNOP
DSNOP
bnez $2, test3
DSNOP
bnez $3, test3
DSNOP
bnez $4, test3
DSNOP
bnez $5, test3
DSNOP
bnez $6, test3
DSNOP
bnez $7, test3
DSNOP
bnez $16, test3
DSNOP
bnez $17, test3
DSNOP
bne $2, $0, test3
DSNOP
bne $3, $0, test3
DSNOP
bne $4, $0, test3
DSNOP
bne $5, $0, test3
DSNOP
bne $6, $0, test3
DSNOP
bne $7, $0, test3
DSNOP
bne $16, $0, test3
DSNOP
bne $17, $0, test3
DSNOP
bne $0, $2, test3
DSNOP
bne $0, $3, test3
DSNOP
bne $0, $4, test3
DSNOP
bne $0, $5, test3
DSNOP
bne $0, $6, test3
DSNOP
bne $0, $7, test3
DSNOP
bne $0, $16, test3
DSNOP
bne $0, $17, test3
.ifndef insn32
bnez16 $16, test3
.endif
DSNOP
bnez32 $16, test3
DSNOP
bnez $17, test2
DSNOP
bnez32 $17, test2
test3:
bnezc $17, test2
break
break 0
break 1
break 2
break 3
break 4
break 5
break 6
break 7
break 8
break 9
break 10
break 11
break 12
break 13
break 14
break 15
break 63
break 64
break 1023
break 1023,1023
break32
break32 0
break32 1
break32 2
break32 15
break32 63
break32 64
break32 1023
break32 1023,1023
cache 0, 0
cache 0, -2048
cache 0, 2047
cache 0, -2049
cache 0, 2048
cache 0, 0($2)
cache 0, -2048($2)
cache 0, 2047($2)
cache 0, -2049($2)
cache 0, 2048($2)
cache 0, ($0)
cache 0, 0($0)
cache 1, 0($0)
cache 2, 0($0)
cache 3, 0($0)
cache 4, 0($0)
cache 5, 0($0)
cache 6, 0($0)
cache 31, 0($0)
cache 31, 2047($0)
cache 31, -2048($0)
cache 0, 2047($0)
cache 0, -2048($0)
cache 31, 65536($3)
cache 31, 2048($3)
cache 31, -2049($3)
cache 31, 65537($3)
cache 31, 0xffffffff($3)
cache 31, 0xffff0000($3)
cache 31, 0xffff0001($3)
cache 31, 0xffff($3)
cache 31, 65536($0)
cache 31, 2048($0)
cache 31, -2049($0)
cache 31, 65537($0)
cache 31, 0xffffffff($0)
cache 31, 0xffff0000($0)
cache 31, 0xffff0001($0)
cache 31, 0xffff($0)
clo $2, $3
clo $3, $2
clz $2, $3
clz $3, $2
deret
di
di $0
di $2
di $3
di $30
di $31
div $0, $2, $3
div $0, $30, $31
div $0, $3
div $0, $31
div $2, $3, $0
div $2, $3, $4
div $3, $4, 0
div $3, $4, 1
div $3, $4, -1
div $3, $4, 2
divu $0, $2, $3
divu $0, $30, $31
divu $0, $3
divu $0, $31
divu $2, $3, $0
divu $2, $3, $4
divu $3, $4, 0
divu $3, $4, 1
divu $3, $4, -1
divu $3, $4, 2
ei
ei $0
ei $2
ei $3
ei $30
ei $31
eret
ext $2, $3, 5, 15
ext $2, $3, 0, 32
ext $2, $3, 31, 1
ext $31, $30, 31, 1
ins $2, $3, 5, 15
ins $2, $3, 0, 32
ins $2, $3, 31, 1
ins $31, $30, 31, 1
jr $0
DSNOP
jr $2
DSNOP
jr $3
DSNOP
jr $4
DSNOP
jr $5
DSNOP
jr $6
DSNOP
jr $7
DSNOP
jr $8
DSNOP
jr $30
DSNOP
jr $31
jr32 $0
jr32 $2
jr32 $3
jr32 $4
jr32 $5
jr32 $6
jr32 $7
jr32 $8
jr32 $30
jr32 $31
jrc $0
jrc $2
jrc $3
jrc $4
jrc $5
jrc $6
jrc $7
jrc $8
jrc $30
jrc $31
jr.hb $0
jr.hb $2
jr.hb $3
jr.hb $4
jr.hb $5
jr.hb $6
jr.hb $7
jr.hb $8
jr.hb $30
jr.hb $31
DSNOP
j $0
DSNOP
j $2
DSNOP
j $3
DSNOP
j $4
DSNOP
j $5
DSNOP
j $6
DSNOP
j $7
DSNOP
j $8
DSNOP
j $30
DSNOP
j $31
jalr $31, $0
jalr $2
jalr $3
jalr $4
jalr $5
jalr $6
jalr $7
jalr $8
jalr $30
jalr32 $31, $0
jalr32 $2
jalr32 $3
jalr32 $4
jalr32 $5
jalr32 $6
jalr32 $7
jalr32 $8
jalr32 $30
jalr $31, $0
jalr $31, $2
jalr $31, $3
jalr $31, $4
jalr $31, $5
jalr $31, $6
jalr $31, $7
jalr $31, $8
jalr $31, $30
jalr $30, $31
jalr $2, $0
jalr $3, $2
jalr $2, $3
jalr $2, $4
jalr $2, $5
jalr $2, $6
jalr $2, $7
jalr $2, $8
jalr $2, $30
jalr $2, $31
jalr.hb $31, $0
jalr.hb $2
jalr.hb $3
jalr.hb $4
jalr.hb $5
jalr.hb $6
jalr.hb $7
jalr.hb $8
jalr.hb $30
#jalr.hb $31
jalr.hb $31, $0
jalr.hb $31, $2
jalr.hb $31, $3
jalr.hb $31, $4
jalr.hb $31, $5
jalr.hb $31, $6
jalr.hb $31, $7
jalr.hb $31, $8
jalr.hb $31, $30
jalr.hb $30, $31
jalr.hb $2, $0
jalr.hb $3, $2
jalr.hb $2, $3
jalr.hb $2, $4
jalr.hb $2, $5
jalr.hb $2, $6
jalr.hb $2, $7
jalr.hb $2, $8
jalr.hb $2, $30
jalr.hb $2, $31
jal $2, $3
jal $30, $31
jal $3
jal $31
jal test
jal test2
jalx test
jalx test4
la $2, test
lca $2, test
lb $3, 0
lb $3, 4
lb $3, 0($0)
lb $3, 4($0)
lb $3, 32767($0)
lb $3, -32768($0)
lb $3, 65535($0)
lb $3, 0xffff0000($0)
lb $3, 0xffff8000($0)
lb $3, 0xffff0001($0)
lb $3, 0xffff8001($0)
lb $3, 0xf0000000($0)
lb $3, 0xffffffff($0)
lb $3, 0x12345678($0)
lb $3, ($4)
lb $3, 0($4)
lb $3, 4($4)
lb $3, 32767($4)
lb $3, -32768($4)
lb $3, 65535($4)
lb $3, 0xffff0000($4)
lb $3, 0xffff8000($4)
lb $3, 0xffff0001($4)
lb $3, 0xffff8001($4)
lb $3, 0xf0000000($4)
lb $3, 0xffffffff($4)
lb $3, 0x12345678($4)
lbu $2, -1($3)
lbu $2, 0($3)
lbu $2, ($3)
lbu $2, 1($3)
lbu $2, 2($3)
lbu $2, 3($3)
lbu $2, 4($3)
lbu $2, 5($3)
lbu $2, 6($3)
lbu $2, 7($3)
lbu $2, 8($3)
lbu $2, 9($3)
lbu $2, 10($3)
lbu $2, 11($3)
lbu $2, 12($3)
lbu $2, 13($3)
lbu $2, 14($3)
lbu $2, 14($2)
lbu $2, 14($4)
lbu $2, 14($5)
lbu $2, 14($6)
lbu $2, 14($7)
lbu $2, 14($16)
lbu $2, 14($17)
lbu $3, 14($17)
lbu $4, 14($17)
lbu $5, 14($17)
lbu $6, 14($17)
lbu $7, 14($17)
lbu $16, 14($17)
lbu $17, 14($17)
lbu $3, 0
lbu $3, 4
lbu $3, 0($0)
lbu $3, 4($0)
lbu $3, 32767($0)
lbu $3, -32768($0)
lbu $3, 65535($0)
lbu $3, 0xffff0000($0)
lbu $3, 0xffff8000($0)
lbu $3, 0xffff0001($0)
lbu $3, 0xffff8001($0)
lbu $3, 0xf0000000($0)
lbu $3, 0xffffffff($0)
lbu $3, 0x12345678($0)
lbu $3, ($4)
lbu $3, 0($4)
lbu $3, 4($4)
lbu $3, 32767($4)
lbu $3, -32768($4)
lbu $3, 65535($4)
lbu $3, 0xffff0000($4)
lbu $3, 0xffff8000($4)
lbu $3, 0xffff0001($4)
lbu $3, 0xffff8001($4)
lbu $3, 0xf0000000($4)
lbu $3, 0xffffffff($4)
lbu $3, 0x12345678($4)
lh $3, 0
lh $3, 4
lh $3, 0($0)
lh $3, 4($0)
lh $3, 32767($0)
lh $3, -32768($0)
lh $3, 65535($0)
lh $3, 0xffff0000($0)
lh $3, 0xffff8000($0)
lh $3, 0xffff0001($0)
lh $3, 0xffff8001($0)
lh $3, 0xf0000000($0)
lh $3, 0xffffffff($0)
lh $3, 0x12345678($0)
lh $3, ($4)
lh $3, 0($4)
lh $3, 4($4)
lh $3, 32767($4)
lh $3, -32768($4)
lh $3, 65535($4)
lh $3, 0xffff0000($4)
lh $3, 0xffff8000($4)
lh $3, 0xffff0001($4)
lh $3, 0xffff8001($4)
lh $3, 0xf0000000($4)
lh $3, 0xffffffff($4)
lh $3, 0x12345678($4)
lhu $2, ($3)
lhu $2, 0<<1($3)
lhu $2, 1<<1($3)
lhu $2, 2<<1($3)
lhu $2, 3<<1($3)
lhu $2, 4<<1($3)
lhu $2, 5<<1($3)
lhu $2, 6<<1($3)
lhu $2, 7<<1($3)
lhu $2, 8<<1($3)
lhu $2, 9<<1($3)
lhu $2, 10<<1($3)
lhu $2, 11<<1($3)
lhu $2, 12<<1($3)
lhu $2, 13<<1($3)
lhu $2, 14<<1($3)
lhu $2, 15<<1($3)
lhu $2, 15<<1($4)
lhu $2, 15<<1($5)
lhu $2, 15<<1($6)
lhu $2, 15<<1($7)
lhu $2, 15<<1($2)
lhu $2, 15<<1($16)
lhu $2, 15<<1($17)
lhu $3, 15<<1($17)
lhu $4, 15<<1($17)
lhu $5, 15<<1($17)
lhu $6, 15<<1($17)
lhu $7, 15<<1($17)
lhu $16, 15<<1($17)
lhu $17, 15<<1($17)
lhu $3, 0
lhu $3, 4
lhu $3, 0($0)
lhu $3, 4($0)
lhu $3, 32767($0)
lhu $3, -32768($0)
lhu $3, 65535($0)
lhu $3, 0xffff0000($0)
lhu $3, 0xffff8000($0)
lhu $3, 0xffff0001($0)
lhu $3, 0xffff8001($0)
lhu $3, 0xf0000000($0)
lhu $3, 0xffffffff($0)
lhu $3, 0x12345678($0)
lhu $3, ($4)
lhu $3, 0($4)
lhu $3, 4($4)
lhu $3, 32767($4)
lhu $3, -32768($4)
lhu $3, 65535($4)
lhu $3, 0xffff0000($4)
lhu $3, 0xffff8000($4)
lhu $3, 0xffff0001($4)
lhu $3, 0xffff8001($4)
lhu $3, 0xf0000000($4)
lhu $3, 0xffffffff($4)
lhu $3, 0x12345678($4)
ll $3, 0
ll $3, 0($0)
ll $3, 4
ll $3, 4($0)
ll $3, 32767($0)
ll $3, -32768($0)
ll $3, 65535($0)
ll $3, 0xffff0000($0)
ll $3, 0xffff8000($0)
ll $3, 0xffff0001($0)
ll $3, 0xffff8001($0)
ll $3, 0xf0000000($0)
ll $3, 0xffffffff($0)
ll $3, 0x12345678($0)
ll $3, ($4)
ll $3, 0($4)
ll $3, 4($4)
ll $3, 32767($4)
ll $3, -32768($4)
ll $3, 65535($4)
ll $3, 0xffff0000($4)
ll $3, 0xffff8000($4)
ll $3, 0xffff0001($4)
ll $3, 0xffff8001($4)
ll $3, 0xf0000000($4)
ll $3, 0xffffffff($4)
ll $3, 0x12345678($4)
lui $3, 0
lui $3, 32767
lui $3, 65535
lw $2, ($4)
lw $2, 0($4)
lw $2, 1<<2($4)
lw $2, 2<<2($4)
lw $2, 3<<2($4)
lw $2, 4<<2($4)
lw $2, 5<<2($4)
lw $2, 6<<2($4)
lw $2, 7<<2($4)
lw $2, 8<<2($4)
lw $2, 9<<2($4)
lw $2, 10<<2($4)
lw $2, 11<<2($4)
lw $2, 12<<2($4)
lw $2, 13<<2($4)
lw $2, 14<<2($4)
lw $2, 15<<2($4)
lw $2, 15<<2($5)
lw $2, 15<<2($6)
lw $2, 15<<2($7)
lw $2, 15<<2($2)
lw $2, 15<<2($3)
lw $2, 15<<2($16)
lw $2, 15<<2($17)
lw $3, 15<<2($17)
lw $4, 15<<2($17)
lw $5, 15<<2($17)
lw $6, 15<<2($17)
lw $7, 15<<2($17)
lw $16, 15<<2($17)
lw $17, 15<<2($17)
lw $4, ($29)
lw $4, 0($29)
lw $4, 1<<2($29)
lw $4, 2<<2($29)
lw $4, 3<<2($29)
lw $4, 4<<2($29)
lw $4, 5<<2($29)
lw $4, 31<<2($29)
lw $2, 31<<2($29)
lw $2, 31<<2($29)
lw $3, 31<<2($29)
lw $4, 31<<2($29)
lw $5, 31<<2($29)
lw $6, 31<<2($29)
lw $7, 31<<2($29)
lw $8, 31<<2($29)
lw $9, 31<<2($29)
lw $10, 31<<2($29)
lw $30, 31<<2($29)
lw $31, 31<<2($29)
lw $4, 126<<2($29)
lw $4, 127<<2($29)
lw $16, 127<<2($29)
lw $17, 127<<2($29)
lw $18, 127<<2($29)
lw $19, 127<<2($29)
lw $20, 127<<2($29)
lw $21, 127<<2($29)
lw $31, 127<<2($29)
lw $3, 0
lw $3, 4
lw $3, ($0)
lw $3, 0($0)
lw $3, 0($0)
lw $3, 4($0)
lw $3, 32767($0)
lw $3, -32768($0)
lw $3, 65535($0)
lw $3, 0xffff0000($0)
lw $3, 0xffff8000($0)
lw $3, 0xffff0001($0)
lw $3, 0xffff8001($0)
lw $3, 0xf0000000($0)
lw $3, 0xffffffff($0)
lw $3, 0x12345678($0)
lw $3, ($4)
lw $3, 0($4)
lw $3, 4($4)
lw $3, 32767($4)
lw $3, -32768($4)
lw $3, 65535($4)
lw $3, 0xffff0000($4)
lw $3, 0xffff8000($4)
lw $3, 0xffff0001($4)
lw $3, 0xffff8001($4)
lw $3, 0xf0000000($4)
lw $3, 0xffffffff($4)
lw $3, 0x12345678($4)
lwm $s0, $ra, 12<<2($29)
lwm $s0, $s1, $ra, 12<<2($29)
lwm $s0-$s1, $ra, 12<<2($29)
lwm $s0, $s1, $s2, $ra, 12<<2($29)
lwm $s0-$s2, $ra, 12<<2($29)
lwm $s0, $s1, $s2, $s3, $ra, 12<<2($29)
lwm $s0-$s3, $ra, 12<<2($29)
lwm $s0, $ra, ($29)
lwm $s0, $ra, 0($29)
lwm $s0, $ra, 1<<2($29)
lwm $s0, $ra, 2<<2($29)
lwm $s0, $ra, 3<<2($29)
lwm $s0, $ra, 4<<2($29)
lwm $s0, $ra, 5<<2($29)
lwm $s0, $ra, 6<<2($29)
lwm $s0, $ra, 7<<2($29)
lwm $s0, $ra, 8<<2($29)
lwm $s0, $ra, 9<<2($29)
lwm $s0, $ra, 10<<2($29)
lwm $s0, $ra, 11<<2($29)
lwm $s0, $ra, 12<<2($29)
lwm $s0, $ra, 13<<2($29)
lwm $s0, $ra, 14<<2($29)
lwm $s0, $ra, 15<<2($29)
lwm $s0, 0
lwm $s0, 4
lwm $s0, ($5)
lwm $s0, 2047($5)
lwm $s0-$s1, 2047($5)
lwm $s0-$s2, 2047($5)
lwm $s0-$s3, 2047($5)
lwm $s0-$s4, 2047($5)
lwm $s0-$s5, 2047($5)
lwm $s0-$s6, 2047($5)
lwm $s0-$s7, 2047($5)
lwm $s0-$s8, 2047($5)
lwm $ra, 2047($5)
lwm $s0,$ra, ($5)
lwm $s0-$s1,$ra, ($5)
lwm $s0-$s2,$ra, ($5)
lwm $s0-$s3,$ra, ($5)
lwm $s0-$s4,$ra, ($5)
lwm $s0-$s5,$ra, ($5)
lwm $s0-$s6,$ra, ($5)
lwm $s0-$s7,$ra, ($5)
lwm $s0-$s8,$ra, ($5)
lwm $s0, -32768($0)
lwm $s0, 32767($0)
lwm $s0, 0($0)
lwm $s0, 65535($0)
lwm $s0, -32768($29)
lwm $s0, 32767($29)
lwm $s0, 0($29)
lwm $s0, 65535($29)
lwp $2, 0
lwp $2, 4
lwp $2, ($29)
lwp $2, 0($29)
lwp $2, -2048($3)
lwp $2, 2047($3)
lwp $2, -32768($3)
lwp $2, 32767($3)
lwp $2, 0($3)
lwp $2, 65535($3)
lwp $2, -32768($0)
lwp $2, 32767($0)
lwp $2, 65535($0)
lwl $3, 4
lwl $3, 4($0)
lwl $3, ($0)
lwl $3, 0($0)
lwl $3, 2047($0)
lwl $3, -2048($0)
lwl $3, 32767($0)
lwl $3, -32768($0)
lwl $3, 65535($0)
lwl $3, 0xffff0000($0)
lwl $3, 0xffff8000($0)
lwl $3, 0xffff0001($0)
lwl $3, 0xffff8001($0)
lwl $3, 0xf0000000($0)
lwl $3, 0xffffffff($0)
lwl $3, 0x12345678($0)
lwl $3, ($4)
lwl $3, 0($4)
lwl $3, 2047($4)
lwl $3, -2048($4)
lwl $3, 32767($4)
lwl $3, -32768($4)
lwl $3, 65535($4)
lwl $3, 0xffff0000($4)
lwl $3, 0xffff8000($4)
lwl $3, 0xffff0001($4)
lwl $3, 0xffff8001($4)
lwl $3, 0xf0000000($4)
lwl $3, 0xffffffff($4)
lwl $3, 0x12345678($4)
lcache $3, 4
lcache $3, 4($0)
lcache $3, ($0)
lcache $3, 0($0)
lcache $3, 2047($0)
lcache $3, -2048($0)
lcache $3, 32767($0)
lcache $3, -32768($0)
lcache $3, 65535($0)
lcache $3, 0xffff0000($0)
lcache $3, 0xffff8000($0)
lcache $3, 0xffff0001($0)
lcache $3, 0xffff8001($0)
lcache $3, 0xf0000000($0)
lcache $3, 0xffffffff($0)
lcache $3, 0x12345678($0)
lcache $3, ($4)
lcache $3, 0($4)
lcache $3, 2047($4)
lcache $3, -2048($4)
lcache $3, 32767($4)
lcache $3, -32768($4)
lcache $3, 65535($4)
lcache $3, 0xffff0000($4)
lcache $3, 0xffff8000($4)
lcache $3, 0xffff0001($4)
lcache $3, 0xffff8001($4)
lcache $3, 0xf0000000($4)
lcache $3, 0xffffffff($4)
lcache $3, 0x12345678($4)
lwr $3, 4
lwr $3, 4($0)
lwr $3, ($0)
lwr $3, 0($0)
lwr $3, 2047($0)
lwr $3, -2048($0)
lwr $3, 32767($0)
lwr $3, -32768($0)
lwr $3, 65535($0)
lwr $3, 0xffff0000($0)
lwr $3, 0xffff8000($0)
lwr $3, 0xffff0001($0)
lwr $3, 0xffff8001($0)
lwr $3, 0xf0000000($0)
lwr $3, 0xffffffff($0)
lwr $3, 0x12345678($0)
lwr $3, ($4)
lwr $3, 0($4)
lwr $3, 2047($4)
lwr $3, -2048($4)
lwr $3, 32767($4)
lwr $3, -32768($4)
lwr $3, 65535($4)
lwr $3, 0xffff0000($4)
lwr $3, 0xffff8000($4)
lwr $3, 0xffff0001($4)
lwr $3, 0xffff8001($4)
lwr $3, 0xf0000000($4)
lwr $3, 0xffffffff($4)
lwr $3, 0x12345678($4)
flush $3, 4
flush $3, 4($0)
flush $3, ($0)
flush $3, 0($0)
flush $3, 2047($0)
flush $3, -2048($0)
flush $3, 32767($0)
flush $3, -32768($0)
flush $3, 65535($0)
flush $3, 0xffff0000($0)
flush $3, 0xffff8000($0)
flush $3, 0xffff0001($0)
flush $3, 0xffff8001($0)
flush $3, 0xf0000000($0)
flush $3, 0xffffffff($0)
flush $3, 0x12345678($0)
flush $3, ($4)
flush $3, 0($4)
flush $3, 2047($4)
flush $3, -2048($4)
flush $3, 32767($4)
flush $3, -32768($4)
flush $3, 65535($4)
flush $3, 0xffff0000($4)
flush $3, 0xffff8000($4)
flush $3, 0xffff0001($4)
flush $3, 0xffff8001($4)
flush $3, 0xf0000000($4)
flush $3, 0xffffffff($4)
flush $3, 0x12345678($4)
lwxs $3, $4($5)
madd $4,$5
maddu $4,$5
mfc0 $2, $0
mfc0 $2, $1
mfc0 $2, $2
mfc0 $2, $3
mfc0 $2, $4
mfc0 $2, $5
mfc0 $2, $6
mfc0 $2, $7
mfc0 $2, $8
mfc0 $2, $9
mfc0 $2, $10
mfc0 $2, $11
mfc0 $2, $12
mfc0 $2, $13
mfc0 $2, $14
mfc0 $2, $15
mfc0 $2, $16
mfc0 $2, $17
mfc0 $2, $18
mfc0 $2, $19
mfc0 $2, $20
mfc0 $2, $21
mfc0 $2, $22
mfc0 $2, $23
mfc0 $2, $24
mfc0 $2, $25
mfc0 $2, $26
mfc0 $2, $27
mfc0 $2, $28
mfc0 $2, $29
mfc0 $2, $30
mfc0 $2, $31
mfc0 $2, $0, 0
mfc0 $2, $0, 1
mfc0 $2, $0, 2
mfc0 $2, $0, 3
mfc0 $2, $0, 4
mfc0 $2, $0, 5
mfc0 $2, $0, 6
mfc0 $2, $0, 7
mfc0 $2, $1, 0
mfc0 $2, $1, 1
mfc0 $2, $1, 2
mfc0 $2, $1, 3
mfc0 $2, $1, 4
mfc0 $2, $1, 5
mfc0 $2, $1, 6
mfc0 $2, $1, 7
mfc0 $2, $2, 0
mfc0 $2, $2, 1
mfc0 $2, $2, 2
mfc0 $2, $2, 3
mfc0 $2, $2, 4
mfc0 $2, $2, 5
mfc0 $2, $2, 6
mfc0 $2, $2, 7
mfhi $0
mfhi $2
mfhi $3
mfhi $4
mfhi $29
mfhi $30
mfhi $31
mfhi32 $0
mfhi32 $2
mfhi32 $3
mfhi32 $4
mfhi32 $29
mfhi32 $30
mfhi32 $31
mflo $0
mflo $2
mflo $3
mflo $4
mflo $29
mflo $30
mflo $31
mflo32 $0
mflo32 $2
mflo32 $3
mflo32 $4
mflo32 $29
mflo32 $30
mflo32 $31
movn $2, $3
movn $2, $2, $3
movn $2, $3, $4
movz $2, $3
movz $2, $2, $3
movz $2, $3, $4
msub $4,$5
msubu $4,$5
mtc0 $2, $0
mtc0 $2, $1
mtc0 $2, $2
mtc0 $2, $3
mtc0 $2, $4
mtc0 $2, $5
mtc0 $2, $6
mtc0 $2, $7
mtc0 $2, $8
mtc0 $2, $9
mtc0 $2, $10
mtc0 $2, $11
mtc0 $2, $12
mtc0 $2, $13
mtc0 $2, $14
mtc0 $2, $15
mtc0 $2, $16
mtc0 $2, $17
mtc0 $2, $18
mtc0 $2, $19
mtc0 $2, $20
mtc0 $2, $21
mtc0 $2, $22
mtc0 $2, $23
mtc0 $2, $24
mtc0 $2, $25
mtc0 $2, $26
mtc0 $2, $27
mtc0 $2, $28
mtc0 $2, $29
mtc0 $2, $30
mtc0 $2, $31
mtc0 $2, $0, 0
mtc0 $2, $0, 1
mtc0 $2, $0, 2
mtc0 $2, $0, 3
mtc0 $2, $0, 4
mtc0 $2, $0, 5
mtc0 $2, $0, 6
mtc0 $2, $0, 7
mtc0 $2, $1, 0
mtc0 $2, $1, 1
mtc0 $2, $1, 2
mtc0 $2, $1, 3
mtc0 $2, $1, 4
mtc0 $2, $1, 5
mtc0 $2, $1, 6
mtc0 $2, $1, 7
mtc0 $2, $2, 0
mtc0 $2, $2, 1
mtc0 $2, $2, 2
mtc0 $2, $2, 3
mtc0 $2, $2, 4
mtc0 $2, $2, 5
mtc0 $2, $2, 6
mtc0 $2, $2, 7
mthi $0
mthi $2
mthi $3
mthi $4
mthi $29
mthi $30
mthi $31
mtlo $0
mtlo $2
mtlo $3
mtlo $4
mtlo $29
mtlo $30
mtlo $31
mul $2, $3, $4
mul $29, $30, $31
mul $2, $2, $4
mul $2, $4
mul $2, $2, 0
mul $2, $2, 1
mul $2, $2, 32767
mul $2, $2, -32768
mul $2, $2, 65535
mulo $2, $3, $4
mulo $2, $3, 4
mulou $2, $3, $4
mulou $2, $3, 4
mult $2, $3
multu $2, $3
neg $2, $3
neg $2, $2
neg $2
negu $2, $3
negu $2, $2
negu $2
negu32 $2, $3
negu32 $2, $2
negu32 $2
not $2, $2
not $2, $2
not $2, $3
not $2, $4
not $2, $5
not $2, $6
not $2, $7
not $2, $16
not $2, $17
not $3, $17
not $4, $17
not $5, $17
not $6, $17
not $7, $17
not $16, $17
not $17, $17
nor $2, $7, $0
nor $2, $0, $7
nor32 $2, $3, $4
nor32 $29, $30, $31
nor32 $2, $2, $4
nor32 $2, $4
nor $2, $3, 32768
nor $2, $3, 65535
nor $2, $3, 65536
nor $2, $3, -32768
nor $2, $3, -32769
or $2, $22, $0
or $22, $2, $0
or $2, $0, $22
or $22, $0, $2
or $2, $2
or $2, $3
or $2, $4
or $2, $5
or $2, $6
or $2, $7
or $2, $16
or $2, $17
or $3, $2
or $4, $2
or $5, $2
or $6, $2
or $7, $2
or $16, $2
or $17, $2
or $2, $2
or $2, $2, $3
or $2, $3, $2
or32 $2, $3, $4
or32 $29, $30, $31
or32 $2, $2, $4
or32 $2, $4
or $2, $3, 32768
or $2, $3, 65535
or $2, $3, 65536
or $2, $3, -32768
or $2, $3, -32769
ori $3, $4, 0
ori $3, $4, 32767
ori $3, $4, 65535
ori $3, $3, 65535
ori $3, 65535
rdhwr $2, $0
rdhwr $2, $1
rdhwr $2, $2
rdhwr $2, $3
rdhwr $2, $4
rdhwr $2, $5
rdhwr $2, $6
rdhwr $2, $7
rdhwr $2, $8
rdhwr $2, $9
rdhwr $2, $10
rdpgpr $2, $3
rdpgpr $2, $2
rdpgpr $2
rem $0, $2, $3
rem $0, $30, $31
rem $0, $3
rem $0, $31
rem $2, $3, $0
rem $2, $3, $4
rem $3, $4, 0
rem $3, $4, 1
rem $3, $4, -1
rem $3, $4, 2
remu $0, $2, $3
remu $0, $30, $31
remu $0, $3
remu $0, $31
remu $2, $3, $0
remu $2, $3, $4
remu $3, $4, 0
remu $3, $4, 1
remu $3, $4, -1
remu $3, $4, 2
rol $2, $3, $4
rol $2, $2, $4
rol $2, $3, $3
rol $2, $3, $2
rol $2, $3, 0
rol $2, $3, 1
rol $2, $3, 31
rol $2, $2, 31
rol $2, 31
ror $2, $3, 0
ror $2, $3, 1
ror $2, $3, 31
ror $2, $2, 31
ror $2, 31
ror $2, $3, $4
ror $2, $2, $4
rotr $2, $3, $4
rotr $2, $2, $4
rorv $2, $3, $4
rorv $2, $2, $4
rotrv $2, $3, $4
rotrv $2, $2, $4
sb $0, ($3)
sb $0, 0($3)
sb $0, 1($3)
sb $0, 2($3)
sb $0, 3($3)
sb $0, 4($3)
sb $0, 5($3)
sb $0, 6($3)
sb $0, 7($3)
sb $0, 8($3)
sb $0, 9($3)
sb $0, 10($3)
sb $0, 11($3)
sb $0, 12($3)
sb $0, 13($3)
sb $0, 14($3)
sb $0, 15($3)
sb $2, 15($3)
sb $3, 15($3)
sb $4, 15($3)
sb $5, 15($3)
sb $6, 15($3)
sb $7, 15($3)
sb $17, 15($3)
sb $17, 15($4)
sb $17, 15($5)
sb $17, 15($6)
sb $17, 15($7)
sb $17, 15($2)
sb $17, 15($16)
sb $17, 15($17)
sb32 $3, 4
sb32 $3, 4($0)
sb32 $3, 32767($0)
sb32 $3, -32768($0)
sb $3, 65535($0)
sb $3, 0xffff0000($0)
sb $3, 0xffff8000($0)
sb $3, 0xffff0001($0)
sb $3, 0xffff8001($0)
sb $3, 0xf0000000($0)
sb $3, 0xffffffff($0)
sb $3, 0x12345678($0)
sb32 $3, ($4)
sb32 $3, 0($4)
sb32 $3, 32767($4)
sb32 $3, -32768($4)
sb $3, 65535($4)
sb $3, 0xffff0000($4)
sb $3, 0xffff8000($4)
sb $3, 0xffff0001($4)
sb $3, 0xffff8001($4)
sb $3, 0xf0000000($4)
sb $3, 0xffffffff($4)
sb $3, 0x12345678($4)
sc $3, 4
sc $3, 4($0)
sc $3, 2047($0)
sc $3, -2048($0)
sc $3, 32767($0)
sc $3, -32768($0)
sc $3, 65535($0)
sc $3, 0xffff0000($0)
sc $3, 0xffff8000($0)
sc $3, 0xffff0001($0)
sc $3, 0xffff8001($0)
sc $3, 0xf0000000($0)
sc $3, 0xffffffff($0)
sc $3, 0x12345678($0)
sc $3, ($4)
sc $3, 0($4)
sc $3, 2047($4)
sc $3, -2048($4)
sc $3, 32767($4)
sc $3, -32768($4)
sc $3, 65535($4)
sc $3, 0xffff0000($4)
sc $3, 0xffff8000($4)
sc $3, 0xffff0001($4)
sc $3, 0xffff8001($4)
sc $3, 0xf0000000($4)
sc $3, 0xffffffff($4)
sc $3, 0x12345678($4)
sdbbp
sdbbp 0
sdbbp 1
sdbbp 2
sdbbp 3
sdbbp 4
sdbbp 5
sdbbp 6
sdbbp 7
sdbbp 8
sdbbp 9
sdbbp 10
sdbbp 11
sdbbp 12
sdbbp 13
sdbbp 14
sdbbp 15
sdbbp32
sdbbp32 0
sdbbp32 1
sdbbp32 2
sdbbp32 255
seb $2, $3
seb $2, $2
seb $2
seh $2, $3
seh $2, $2
seh $2
seq $2, $3, $4
seq $2, $3, $0
seq $2, $0, $4
seq $2, $3, 0
seq $2, $3, 1
seq $2, $3, -1
seq $2, $3, -32769
sge $2, $3, $4
sge $2, $2, $4
sge $2, $4
sge $2, $3, 0
sge $2, $3, -32768
sge $2, $3, 0
sge $2, $3, 32767
sge $2, $3, 65535
sge $2, $3, 65536
sge $2, $3, -32769
sgeu $2, $3, $4
sgeu $2, $2, $4
sgeu $2, $4
sgeu $2, $3, 0
sgeu $2, $3, -32768
sgeu $2, $3, 0
sgeu $2, $3, 32767
sgeu $2, $3, 65535
sgeu $2, $3, 65536
sgeu $2, $3, -32769
sgt $2, $3, $4
sgt $2, $2, $4
sgt $2, $4
sgt $2, $3, 0
sgt $2, $3, -32768
sgt $2, $3, 0
sgt $2, $3, 32767
sgt $2, $3, 65535
sgt $2, $3, 65536
sgt $2, $3, -32769
sgtu $2, $3, $4
sgtu $2, $2, $4
sgtu $2, $4
sgtu $2, $3, 0
sgtu $2, $3, -32768
sgtu $2, $3, 0
sgtu $2, $3, 32767
sgtu $2, $3, 65535
sgtu $2, $3, 65536
sgtu $2, $3, -32769
sh $2, ($3)
sh $2, 0<<1($3)
sh $2, 1<<1($3)
sh $2, 2<<1($3)
sh $2, 3<<1($3)
sh $2, 4<<1($3)
sh $2, 5<<1($3)
sh $2, 6<<1($3)
sh $2, 7<<1($3)
sh $2, 8<<1($3)
sh $2, 9<<1($3)
sh $2, 10<<1($3)
sh $2, 11<<1($3)
sh $2, 12<<1($3)
sh $2, 13<<1($3)
sh $2, 14<<1($3)
sh $2, 15<<1($3)
sh $2, 15<<1($4)
sh $2, 15<<1($5)
sh $2, 15<<1($6)
sh $2, 15<<1($7)
sh $2, 15<<1($2)
sh $2, 15<<1($16)
sh $2, 15<<1($17)
sh $3, 15<<1($17)
sh $4, 15<<1($17)
sh $5, 15<<1($17)
sh $6, 15<<1($17)
sh $7, 15<<1($17)
sh $17, 15<<1($17)
sh $0, 15<<1($17)
sh32 $3, 4
sh32 $3, 4($0)
sh32 $3, 32767($0)
sh32 $3, -32768($0)
sh $3, 65535($0)
sh $3, 0xffff0000($0)
sh $3, 0xffff8000($0)
sh $3, 0xffff0001($0)
sh $3, 0xffff8001($0)
sh $3, 0xf0000000($0)
sh $3, 0xffffffff($0)
sh $3, 0x12345678($0)
sh32 $3, ($4)
sh32 $3, 0($4)
sh32 $3, 32767($4)
sh32 $3, -32768($4)
sh $3, 65535($4)
sh $3, 0xffff0000($4)
sh $3, 0xffff8000($4)
sh $3, 0xffff0001($4)
sh $3, 0xffff8001($4)
sh $3, 0xf0000000($4)
sh $3, 0xffffffff($4)
sh $3, 0x12345678($4)
sle $2, $3, $4
sle $2, $2, $4
sle $2, $4
sle $2, $3, 0
sle $2, $3, -32768
sle $2, $3, 0
sle $2, $3, 32767
sle $2, $3, 65535
sle $2, $3, 65536
sle $2, $3, -32769
sleu $2, $3, $4
sleu $2, $2, $4
sleu $2, $4
sleu $2, $3, 0
sleu $2, $3, -32768
sleu $2, $3, 0
sleu $2, $3, 32767
sleu $2, $3, 65535
sleu $2, $3, 65536
sleu $2, $3, -32769
sll $2, $2, 1
sll $2, $2, 2
sll $2, $2, 3
sll $2, $2, 4
sll $2, $2, 5
sll $2, $2, 6
sll $2, $2, 7
sll $2, $2, 8
sll $2, $3, 8
sll $2, $4, 8
sll $2, $5, 8
sll $2, $6, 8
sll $2, $7, 8
sll $2, $16, 8
sll $2, $17, 8
sll $3, $2, 8
sll $4, $2, 8
sll $5, $2, 8
sll $6, $2, 8
sll $7, $2, 8
sll $16, $2, 8
sll $17, $2, 8
sll $2, $2, 1
sll $3, 1
sllv $2, $3, $4
sllv $2, $2, $4
sll $2, $2, $4
sll $2, $4
sll32 $2, $4, 0
sll32 $2, $4, 1
sll32 $2, $4, 31
sll32 $2, $2, 31
sll32 $2, 31
slt $2, $3, $4
slt $2, $2, $4
slt $2, $4
slt $2, $3, 0
slt $2, $3, -32768
slt $2, $3, 0
slt $2, $3, 32767
slt $2, $3, 65535
slt $2, $3, 65536
slt $2, $3, -32769
slti $3, $4, -32768
slti $3, $4, 0
slti $3, $4, 32767
slti $3, $4, 65535
slti $3, $3, 65535
slti $3, 65535
sltiu $3, $4, -32768
sltiu $3, $4, 0
sltiu $3, $4, 32767
sltiu $3, $4, 65535
sltiu $3, $3, 65535
sltiu $3, 65535
sltu $2, $3, $4
sltu $2, $2, $4
sltu $2, $4
sltu $2, $3, 0
sltu $2, $3, -32768
sltu $2, $3, 0
sltu $2, $3, 32767
sltu $2, $3, 65535
sltu $2, $3, 65536
sltu $2, $3, -32769
sne $2, $3, $4
sne $2, $0, $4
sne $2, $3, $0
sne $2, $3, 0
sne $2, $3, 1
sne $2, $3, -1
sne $2, $3, -32769
srav $2, $3, $4
srav $2, $2, $4
sra $2, $2, $4
sra $2, $4
sra $2, $4, 0
sra $2, $4, 1
sra $2, $4, 31
sra $2, $2, 31
sra $2, 31
srlv $2, $3, $4
srlv $2, $2, $4
srl $2, $2, $4
srl $2, $4
srl $2, $4, 0
srl $2, $4, 1
srl $2, $4, 31
srl $2, $2, 31
srl $2, 31
srl $2, $2, 1
srl $2, $2, 2
srl $2, $2, 3
srl $2, $2, 4
srl $2, $2, 5
srl $2, $2, 6
srl $2, $2, 7
srl $2, $2, 8
srl $2, $3, 8
srl $2, $4, 8
srl $2, $5, 8
srl $2, $6, 8
srl $2, $7, 8
srl $2, $16, 8
srl $2, $17, 8
srl $2, $2, 8
srl $3, $2, 8
srl $4, $2, 8
srl $5, $2, 8
srl $6, $2, 8
srl $7, $2, 8
srl $16, $2, 8
srl $17, $2, 8
srl $3, $3, 1
srl $3, 1
sub $2, $3, $4
sub $29, $30, $31
sub $2, $2, $4
sub $2, $4
sub $2, $2, 0
sub $2, $2, 1
sub $2, $2, 32767
sub $2, $2, -32768
sub $2, $2, 65535
subu $2, $3, $2
subu $2, $3, $3
subu $2, $3, $4
subu $2, $3, $5
subu $2, $3, $6
subu $2, $3, $7
subu $2, $3, $16
subu $2, $3, $17
subu $2, $2, $17
subu $2, $4, $17
subu $2, $5, $17
subu $2, $6, $17
subu $2, $7, $17
subu $2, $16, $17
subu $2, $17, $17
subu $2, $2, $17
subu $3, $2, $17
subu $4, $2, $17
subu $5, $2, $17
subu $6, $2, $17
subu $7, $2, $17
subu $16, $2, $17
subu $17, $2, $17
subu $7, $7, $2
subu $7, $2
subu32 $2, $3, $4
subu32 $29, $30, $31
subu32 $2, $2, $4
subu32 $2, $4
subu $2, $2, 0
subu $2, $2, 1
subu $2, $2, 32767
subu $2, $2, -32768
subu $2, $2, 65535
sw $2, ($4)
sw $2, 0($4)
sw $2, 1<<2($4)
sw $2, 2<<2($4)
sw $2, 3<<2($4)
sw $2, 4<<2($4)
sw $2, 5<<2($4)
sw $2, 6<<2($4)
sw $2, 7<<2($4)
sw $2, 8<<2($4)
sw $2, 9<<2($4)
sw $2, 10<<2($4)
sw $2, 11<<2($4)
sw $2, 12<<2($4)
sw $2, 13<<2($4)
sw $2, 14<<2($4)
sw $2, 15<<2($4)
sw $2, 15<<2($5)
sw $2, 15<<2($6)
sw $2, 15<<2($7)
sw $2, 15<<2($16)
sw $2, 15<<2($17)
sw $2, 15<<2($2)
sw $2, 15<<2($3)
sw $3, 15<<2($3)
sw $4, 15<<2($3)
sw $5, 15<<2($3)
sw $6, 15<<2($3)
sw $7, 15<<2($3)
sw $17, 15<<2($3)
sw $0, 15<<2($3)
sw $0, ($29)
sw $0, 0($29)
sw $0, 1<<2($29)
sw $0, 2<<2($29)
sw $0, 3<<2($29)
sw $0, 4<<2($29)
sw $0, 5<<2($29)
sw $0, 30<<2($29)
sw $0, 31<<2($29)
sw $2, 31<<2($29)
sw $17, 31<<2($29)
sw $3, 31<<2($29)
sw $4, 31<<2($29)
sw $5, 31<<2($29)
sw $6, 31<<2($29)
sw $7, 31<<2($29)
sw $31, 31<<2($29)
sw32 $3, 4
sw32 $3, 4($0)
sw32 $3, 32767($0)
sw32 $3, -32768($0)
sw $3, 65535($0)
sw $3, 0xffff0000($0)
sw $3, 0xffff8000($0)
sw $3, 0xffff0001($0)
sw $3, 0xffff8001($0)
sw $3, 0xf0000000($0)
sw $3, 0xffffffff($0)
sw $3, 0x12345678($0)
sw32 $3, ($4)
sw32 $3, 0($4)
sw32 $3, 32767($4)
sw32 $3, -32768($4)
sw $3, 65535($4)
sw $3, 0xffff0000($4)
sw $3, 0xffff8000($4)
sw $3, 0xffff0001($4)
sw $3, 0xffff8001($4)
sw $3, 0xf0000000($4)
sw $3, 0xffffffff($4)
sw $3, 0x12345678($4)
swl $3, 4
swl $3, 4($0)
swl $3, 2047($0)
swl $3, -2048($0)
swl $3, 32767($0)
swl $3, -32768($0)
swl $3, 65535($0)
swl $3, 0xffff0000($0)
swl $3, 0xffff8000($0)
swl $3, 0xffff0001($0)
swl $3, 0xffff8001($0)
swl $3, 0xf0000000($0)
swl $3, 0xffffffff($0)
swl $3, 0x12345678($0)
swl $3, ($4)
swl $3, 0($4)
swl $3, 2047($4)
swl $3, -2048($4)
swl $3, 32767($4)
swl $3, -32768($4)
swl $3, 65535($4)
swl $3, 0xffff0000($4)
swl $3, 0xffff8000($4)
swl $3, 0xffff0001($4)
swl $3, 0xffff8001($4)
swl $3, 0xf0000000($4)
swl $3, 0xffffffff($4)
swl $3, 0x12345678($4)
swr $3, 4
swr $3, 4($0)
swr $3, 2047($0)
swr $3, -2048($0)
swr $3, 32767($0)
swr $3, -32768($0)
swr $3, 65535($0)
swr $3, 0xffff0000($0)
swr $3, 0xffff8000($0)
swr $3, 0xffff0001($0)
swr $3, 0xffff8001($0)
swr $3, 0xf0000000($0)
swr $3, 0xffffffff($0)
swr $3, 0x12345678($0)
swr $3, ($4)
swr $3, 0($4)
swr $3, 2047($4)
swr $3, -2048($4)
swr $3, 32767($4)
swr $3, -32768($4)
swr $3, 65535($4)
swr $3, 0xffff0000($4)
swr $3, 0xffff8000($4)
swr $3, 0xffff0001($4)
swr $3, 0xffff8001($4)
swr $3, 0xf0000000($4)
swr $3, 0xffffffff($4)
swr $3, 0x12345678($4)
scache $3, 4
scache $3, 4($0)
scache $3, 2047($0)
scache $3, -2048($0)
scache $3, 32767($0)
scache $3, -32768($0)
scache $3, 65535($0)
scache $3, 0xffff0000($0)
scache $3, 0xffff8000($0)
scache $3, 0xffff0001($0)
scache $3, 0xffff8001($0)
scache $3, 0xf0000000($0)
scache $3, 0xffffffff($0)
scache $3, 0x12345678($0)
scache $3, ($4)
scache $3, 0($4)
scache $3, 2047($4)
scache $3, -2048($4)
scache $3, 32767($4)
scache $3, -32768($4)
scache $3, 65535($4)
scache $3, 0xffff0000($4)
scache $3, 0xffff8000($4)
scache $3, 0xffff0001($4)
scache $3, 0xffff8001($4)
scache $3, 0xf0000000($4)
scache $3, 0xffffffff($4)
scache $3, 0x12345678($4)
invalidate $3, 4
invalidate $3, 4($0)
invalidate $3, 2047($0)
invalidate $3, -2048($0)
invalidate $3, 32767($0)
invalidate $3, -32768($0)
invalidate $3, 65535($0)
invalidate $3, 0xffff0000($0)
invalidate $3, 0xffff8000($0)
invalidate $3, 0xffff0001($0)
invalidate $3, 0xffff8001($0)
invalidate $3, 0xf0000000($0)
invalidate $3, 0xffffffff($0)
invalidate $3, 0x12345678($0)
invalidate $3, ($4)
invalidate $3, 0($4)
invalidate $3, 2047($4)
invalidate $3, -2048($4)
invalidate $3, 32767($4)
invalidate $3, -32768($4)
invalidate $3, 65535($4)
invalidate $3, 0xffff0000($4)
invalidate $3, 0xffff8000($4)
invalidate $3, 0xffff0001($4)
invalidate $3, 0xffff8001($4)
invalidate $3, 0xf0000000($4)
invalidate $3, 0xffffffff($4)
invalidate $3, 0x12345678($4)
swm $s0, $ra, 12<<2($29)
swm $s0, $s1, $ra, 12<<2($29)
swm $s0-$s1, $ra, 12<<2($29)
swm $s0, $s1, $s2, $ra, 12<<2($29)
swm $s0-$s2, $ra, 12<<2($29)
swm $s0, $s1, $s2, $s3, $ra, 12<<2($29)
swm $s0-$s3, $ra, 12<<2($29)
swm $s0, $ra, ($29)
swm $s0, $ra, 0($29)
swm $s0, $ra, 1<<2($29)
swm $s0, $ra, 2<<2($29)
swm $s0, $ra, 3<<2($29)
swm $s0, $ra, 4<<2($29)
swm $s0, $ra, 5<<2($29)
swm $s0, $ra, 6<<2($29)
swm $s0, $ra, 7<<2($29)
swm $s0, $ra, 8<<2($29)
swm $s0, $ra, 9<<2($29)
swm $s0, $ra, 10<<2($29)
swm $s0, $ra, 11<<2($29)
swm $s0, $ra, 12<<2($29)
swm $s0, $ra, 13<<2($29)
swm $s0, $ra, 14<<2($29)
swm $s0, $ra, 15<<2($29)
swm $s0, 0
swm $s0, 4
swm $s0, 2047
swm $s0, -2048
swm $s0, 2048
swm $s0, -2049
swm $s0, ($5)
swm $s0, 2047($5)
swm $s0, -2048($5)
swm $s0, 2048($5)
swm $s0, -2049($5)
swm $s0-$s1, 2047($5)
swm $s0-$s2, 2047($5)
swm $s0-$s3, 2047($5)
swm $s0-$s4, 2047($5)
swm $s0-$s5, 2047($5)
swm $s0-$s6, 2047($5)
swm $s0-$s7, 2047($5)
swm $s0-$s8, 2047($5)
swm $ra, 2047($5)
swm $s0,$ra, ($5)
swm $s0-$s1,$ra, ($5)
swm $s0-$s2,$ra, ($5)
swm $s0-$s3,$ra, ($5)
swm $s0-$s4,$ra, ($5)
swm $s0-$s5,$ra, ($5)
swm $s0-$s6,$ra, ($5)
swm $s0-$s7,$ra, ($5)
swm $s0-$s8,$ra, ($5)
swm $s0, -32768($29)
swm $s0, 32767($29)
swm $s0, 0($29)
swm $s0, 65535($29)
swp $2, 0
swp $2, 4
swp $2, 2047
swp $2, -2048
swp $2, 2048
swp $2, -2049
swp $2, ($29)
swp $2, 0($29)
swp $2, 2047($3)
swp $2, -2048($3)
swp $2, 2048($3)
swp $2, -2049($3)
swp $2, 32767($3)
swp $2, -32768($3)
swp $2, 0($3)
swp $2, 65535($3)
sync
sync 0
sync 1
sync 2
sync 3
sync 4
sync 30
sync 31
synci 0
synci ($0)
synci 0($0)
synci 2047($0)
synci -2048($0)
synci 2048($0)
synci -2049($0)
synci 32767($0)
synci -32768($0)
synci 0($2)
synci 0($3)
synci 2047($3)
synci -2048($3)
synci 2048($3)
synci -2049($3)
synci 32767($3)
synci -32768($3)
syscall
syscall 0
syscall 1
syscall 2
syscall 255
teqi $2, 0
teqi $2, -32768
teqi $2, 32767
teqi $2, 65535
teq $2, $3
teq $3, $2
teq $2, $3, 0
teq $2, $3, 1
teq $2, $3, 15
teq $2, 0
teq $2, -32768
teq $2, 32767
teq $2, 65535
tgei $2, 0
tgei $2, -32768
tgei $2, 32767
tgei $2, 65535
tge $2, $3
tge $3, $2
tge $2, $3, 0
tge $2, $3, 1
tge $2, $3, 15
tge $2, 0
tge $2, -32768
tge $2, 32767
tge $2, 65535
tgeiu $2, 0
tgeiu $2, -32768
tgeiu $2, 32767
tgeiu $2, 65535
tgeu $2, $3
tgeu $3, $2
tgeu $2, $3, 0
tgeu $2, $3, 1
tgeu $2, $3, 15
tgeu $2, 0
tgeu $2, -32768
tgeu $2, 32767
tgeu $2, 65535
tlbp
tlbr
tlbwi
tlbwr
tlti $2, 0
tlti $2, -32768
tlti $2, 32767
tlti $2, 65535
tlt $2, $3
tlt $3, $2
tlt $2, $3, 0
tlt $2, $3, 1
tlt $2, $3, 15
tlt $2, 0
tlt $2, -32768
tlt $2, 32767
tlt $2, 65535
tltiu $2, 0
tltiu $2, -32768
tltiu $2, 32767
tltiu $2, 65535
tltu $2, $3
tltu $3, $2
tltu $2, $3, 0
tltu $2, $3, 1
tltu $2, $3, 15
tltu $2, 0
tltu $2, -32768
tltu $2, 32767
tltu $2, 65535
tltu $2, 65536
tltu $2, 0xffffffff
tnei $2, 0
tnei $2, -32768
tnei $2, 32767
tnei $2, 65535
tne $2, $3
tne $3, $2
tne $2, $3, 0
tne $2, $3, 1
tne $2, $3, 15
tne $2, 0
tne $2, -32768
tne $2, 32767
tne $2, 65535
tne $2, 65536
tne $2, 0xffffffff
ulh $3, 4
ulh $3, 4($0)
ulh $3, ($4)
ulh $3, 0($4)
ulh $3, 32763($4)
ulh $3, -32768($4)
ulh $3, 65535($4)
ulh $3, 0xffff0000($4)
ulh $3, 0xffff8000($4)
ulh $3, 0xffff0001($4)
ulh $3, 0xffff8001($4)
ulh $3, 0xf0000000($4)
ulh $3, 0xffffffff($4)
ulhu $3, 4
ulhu $3, 4($0)
ulhu $3, ($4)
ulhu $3, 0($4)
ulhu $3, 32763($4)
ulhu $3, -32768($4)
ulhu $3, 65535($4)
ulhu $3, 0xffff0000($4)
ulhu $3, 0xffff8000($4)
ulhu $3, 0xffff0001($4)
ulhu $3, 0xffff8001($4)
ulhu $3, 0xf0000000($4)
ulhu $3, 0xffffffff($4)
ulw $3, 0
ulw $3, ($0)
ulw $3, 4
ulw $3, 4($0)
ulw $3, 2047
ulw $3, -2048
ulw $3, 2048
ulw $3, -2049
ulw $3, 32763($0)
ulw $3, -32768($0)
ulw $3, 65535($0)
ulw $3, 0xffff0000($0)
ulw $3, 0xffff8000($0)
ulw $3, 0xffff0001($0)
ulw $3, 0xffff8001($0)
ulw $3, 0xf0000000($0)
ulw $3, 0xffffffff($0)
ulw $3, 0x12345678($0)
ulw $3, 0($4)
ulw $3, 4($4)
ulw $3, 2047($4)
ulw $3, -2048($4)
ulw $3, 2048($4)
ulw $3, -2049($4)
ulw $3, 32763($4)
ulw $3, -32768($4)
ulw $3, 65535($4)
ulw $3, 0xffff0000($4)
ulw $3, 0xffff8000($4)
ulw $3, 0xffff0001($4)
ulw $3, 0xffff8001($4)
ulw $3, 0xf0000000($4)
ulw $3, 0xffffffff($4)
ulw $3, 0x12345678($4)
ush $3, 4
ush $3, 4($0)
ush $3, ($4)
ush $3, 0($4)
ush $3, 32763($4)
ush $3, -32768($4)
ush $3, 65535($4)
ush $3, 0xffff0000($4)
ush $3, 0xffff8000($4)
ush $3, 0xffff0001($4)
ush $3, 0xffff8001($4)
ush $3, 0xf0000000($4)
ush $3, 0xffffffff($4)
usw $3, 0
usw $3, ($0)
usw $3, 4
usw $3, 4($0)
usw $3, 2047
usw $3, -2048
usw $3, 2048
usw $3, -2049
usw $3, 32763($0)
usw $3, -32768($0)
usw $3, 65535($0)
usw $3, 0xffff0000($0)
usw $3, 0xffff8000($0)
usw $3, 0xffff0001($0)
usw $3, 0xffff8001($0)
usw $3, 0xf0000000($0)
usw $3, 0xffffffff($0)
usw $3, 0x12345678($0)
usw $3, 0($4)
usw $3, 4($4)
usw $3, 2047($4)
usw $3, -2048($4)
usw $3, 2048($4)
usw $3, -2049($4)
usw $3, 32763($4)
usw $3, -32768($4)
usw $3, 65535($4)
usw $3, 0xffff0000($4)
usw $3, 0xffff8000($4)
usw $3, 0xffff0001($4)
usw $3, 0xffff8001($4)
usw $3, 0xf0000000($4)
usw $3, 0xffffffff($4)
usw $3, 0x12345678($4)
wait
wait 0
wait 1
wait 255
wrpgpr $2, $3
wrpgpr $2, $4
wrpgpr $2, $2
wrpgpr $2
wsbh $2, $3
wsbh $2, $4
wsbh $2, $2
wsbh $2
xor $2, $2
xor $2, $3
xor $2, $4
xor $2, $5
xor $2, $6
xor $2, $7
xor $2, $16
xor $2, $17
xor $3, $17
xor $4, $17
xor $5, $17
xor $6, $17
xor $7, $17
xor $16, $17
xor $17, $17
xor $2, $3
xor $2, $2, $3
xor $2, $3, $2
xor32 $2, $3, $4
xor32 $29, $30, $31
xor32 $2, $2, $4
xor32 $2, $4
xor $2, $3, 32768
xor $2, $3, 65535
xor $2, $3, 65536
xor $2, $3, -32768
xor $2, $3, -32769
xori $3, $4, 0
xori $3, $4, 32767
xori $3, $4, 65535
xori $3, $3, 65535
xori $3, 65535
.set noreorder
beqz $9, test
addu $3, $4, $5
beq $9, $10, test
addu $3, $4, $5
beq $9, 0, test
addu $3, $4, $5
beq $9, 1, test
addu $3, $4, $5
bge $10, $0, test
addu $3, $4, $5
bge $10, $0, test
addu $3, $4, $5
bge $0, $10, test
addu $3, $4, $5
bge $10, $11, test
addu $3, $4, $5
bge $10, 0, test
addu $3, $4, $5
bge $10, 1, test
addu $3, $4, $5
bge $10, 2, test
addu $3, $4, $5
bge $10, 0x80000000, test
addu $3, $4, $5
bgeu $2, $0, test
addu $3, $4, $5
bgeu $0, $2, test
addu $3, $4, $5
bgeu $2, $3, test
addu $3, $4, $5
bgeu $2, 0, test
addu $3, $4, $5
bgeu $2, 1, test
addu $3, $4, $5
bgeu $2, 2, test
addu $3, $4, $5
bgez $2, test
addu $3, $4, $5
bgezal $2, test
addu $3, $4, $5
bgt $2, $0, test
addu $3, $4, $5
bgt $0, $2, test
addu $3, $4, $5
bgt $9, $10, test
addu $3, $4, $5
bgt $9, 0x7fffffff, test
addu $3, $4, $5
bgt $9, -1, test
addu $3, $4, $5
bgt $9, 0, test
addu $3, $4, $5
bgt $9, 1, test
addu $3, $4, $5
bgt $9, 0x80000000, test
addu $3, $4, $5
bgtu $9, $0, test
addu $3, $4, $5
bgtu $0, $9, test
addu $3, $4, $5
bgtu $9, $10, test
addu $3, $4, $5
bgtu $0, 0, test
addu $3, $4, $5
bgtu $9, 0xffffffff, test
addu $3, $4, $5
bgtu $9, -1, test
addu $3, $4, $5
bgtu $9, 0, test
addu $3, $4, $5
bgtu $9, 1, test
addu $3, $4, $5
bgtz $9, test
addu $3, $4, $5
ble $9, $0, test
addu $3, $4, $5
ble $0, $10, test
addu $3, $4, $5
ble $9, $10, test
addu $3, $4, $5
ble $9, 0x7fffffff, test
addu $3, $4, $5
ble $9, -1, test
addu $3, $4, $5
ble $9, 0, test
addu $3, $4, $5
ble $9, 1, test
addu $3, $4, $5
bleu $9, $0, test
addu $3, $4, $5
bleu $0, $10, test
addu $3, $4, $5
bleu $9, $10, test
addu $3, $4, $5
bleu $0, $10, test
addu $3, $4, $5
bleu $9, 0xffffffff, test
addu $3, $4, $5
bleu $9, 0, test
addu $3, $4, $5
bleu $9, 1, test
addu $3, $4, $5
blez $9, test
addu $3, $4, $5
blt $9, $0, test
addu $3, $4, $5
blt $0, $10, test
addu $3, $4, $5
blt $9, $10, test
addu $3, $4, $5
blt $9, 0, test
addu $3, $4, $5
blt $9, 1, test
addu $3, $4, $5
blt $9, 2, test
addu $3, $4, $5
bltu $9, $0, test
addu $3, $4, $5
bltu $0, $10, test
addu $3, $4, $5
bltu $9, $10, test
addu $3, $4, $5
bltu $9, 0, test
addu $3, $4, $5
bltu $9, 1, test
addu $3, $4, $5
bltu $9, 2, test
addu $3, $4, $5
bltz $9, test
addu $3, $4, $5
bltzal $9, test
addu $3, $4, $5
bnez $9, test
addu $3, $4, $5
bne $9, $10, test
addu $3, $4, $5
bne $9, 0, test
addu $3, $4, $5
bne $9, 1, test
addu $3, $4, $5
beqzl $9, test
addu $3, $4, $5
beql $9, $10, test
addu $3, $4, $5
beql $9, 0, test
addu $3, $4, $5
beql $9, 1, test
addu $3, $4, $5
bgel $10, $0, test
addu $3, $4, $5
bgel $10, $0, test
addu $3, $4, $5
bgel $0, $10, test
addu $3, $4, $5
bgel $10, $11, test
addu $3, $4, $5
bgel $10, 0, test
addu $3, $4, $5
bgel $10, 1, test
addu $3, $4, $5
bgel $10, 2, test
addu $3, $4, $5
bgel $10, 0x80000000, test
addu $3, $4, $5
bgeul $2, $0, test
addu $3, $4, $5
bgeul $0, $2, test
addu $3, $4, $5
bgeul $2, $3, test
addu $3, $4, $5
bgeul $2, 0, test
addu $3, $4, $5
bgeul $2, 1, test
addu $3, $4, $5
bgeul $2, 2, test
addu $3, $4, $5
bgezl $2, test
addu $3, $4, $5
bgezall $2, test
addu $3, $4, $5
bgtl $2, $0, test
addu $3, $4, $5
bgtl $0, $2, test
addu $3, $4, $5
bgtl $9, $10, test
addu $3, $4, $5
bgtl $9, 0x7fffffff, test
addu $3, $4, $5
bgtl $9, -1, test
addu $3, $4, $5
bgtl $9, 0, test
addu $3, $4, $5
bgtl $9, 1, test
addu $3, $4, $5
bgtl $9, 0x80000000, test
addu $3, $4, $5
bgtul $9, $0, test
addu $3, $4, $5
bgtul $0, $9, test
addu $3, $4, $5
bgtul $9, $10, test
addu $3, $4, $5
bgtul $0, 0, test
addu $3, $4, $5
bgtul $9, 0xffffffff, test
addu $3, $4, $5
bgtul $9, -1, test
addu $3, $4, $5
bgtul $9, 0, test
addu $3, $4, $5
bgtul $9, 1, test
addu $3, $4, $5
bgtzl $9, test
addu $3, $4, $5
blel $9, $0, test
addu $3, $4, $5
blel $0, $10, test
addu $3, $4, $5
blel $9, $10, test
addu $3, $4, $5
blel $9, 0x7fffffff, test
addu $3, $4, $5
blel $9, -1, test
addu $3, $4, $5
blel $9, 0, test
addu $3, $4, $5
blel $9, 1, test
addu $3, $4, $5
bleul $9, $0, test
addu $3, $4, $5
bleul $0, $10, test
addu $3, $4, $5
bleul $9, $10, test
addu $3, $4, $5
bleul $0, $10, test
addu $3, $4, $5
bleul $9, 0xffffffff, test
addu $3, $4, $5
bleul $9, 0, test
addu $3, $4, $5
bleul $9, 1, test
addu $3, $4, $5
blezl $9, test
addu $3, $4, $5
bltl $9, $0, test
addu $3, $4, $5
bltl $0, $10, test
addu $3, $4, $5
bltl $9, $10, test
addu $3, $4, $5
bltl $9, 0, test
addu $3, $4, $5
bltl $9, 1, test
addu $3, $4, $5
bltl $9, 2, test
addu $3, $4, $5
bltul $9, $0, test
addu $3, $4, $5
bltul $0, $10, test
addu $3, $4, $5
bltul $9, $10, test
addu $3, $4, $5
bltul $9, 0, test
addu $3, $4, $5
bltul $9, 1, test
addu $3, $4, $5
bltul $9, 2, test
addu $3, $4, $5
bltzl $9, test
addu $3, $4, $5
bltzall $9, test
addu $3, $4, $5
bnezl $9, test
addu $3, $4, $5
bnel $9, $10, test
addu $3, $4, $5
bnel $9, 0, test
addu $3, $4, $5
bnel $9, 1, test
addu $3, $4, $5
.ifndef insn32
addiur1sp $2, 0
addiur1sp $2, 1<<2
addiur1sp $2, 2<<2
addiur1sp $2, 3<<2
addiur1sp $2, 4<<2
addiur1sp $2, 63<<2
addiur1sp $3, 63<<2
addiur1sp $4, 63<<2
addiur1sp $5, 63<<2
addiur1sp $6, 63<<2
addiur1sp $7, 63<<2
addiur1sp $16, 63<<2
addiur1sp $17, 63<<2
addiur2 $2, $2, -1
addiur2 $2, $3, -1
addiur2 $2, $4, -1
addiur2 $2, $5, -1
addiur2 $2, $6, -1
addiur2 $2, $7, -1
addiur2 $2, $16, -1
addiur2 $2, $17, -1
addiur2 $3, $17, -1
addiur2 $4, $17, -1
addiur2 $5, $17, -1
addiur2 $6, $17, -1
addiur2 $7, $17, -1
addiur2 $16, $17, -1
addiur2 $17, $17, -1
addiur2 $17, $17, 1
addiur2 $17, $17, 4
addiur2 $17, $17, 8
addiur2 $17, $17, 12
addiur2 $17, $17, 16
addiur2 $17, $17, 20
addiur2 $17, $17, 24
addiusp 2 << 2
addiusp 3 << 2
addiusp 254 << 2
addiusp 255 << 2
addiusp 256 << 2
addiusp 257 << 2
addiusp -3 << 2
addiusp -4 << 2
addiusp -255 << 2
addiusp -256 << 2
addiusp -257 << 2
addiusp -258 << 2
addius5 $0, 0
addius5 $2, 0
addius5 $3, 0
addius5 $30, 0
addius5 $31, 0
addius5 $31, 1
addius5 $31, 2
addius5 $31, 3
addius5 $31, 7
addius5 $31, -6
addius5 $31, -7
addius5 $31, -8
.endif
sd $3, 4
sd $3, 4($0)
sd $3, 32767($0)
sd $3, -32768($0)
sd $3, 65535($0)
sd $3, 0xffff0000($0)
sd $3, 0xffff8000($0)
sd $3, 0xffff0001($0)
sd $3, 0xffff8001($0)
sd $3, 0xf0000000($0)
sd $3, 0xffffffff($0)
sd $3, 0x12345678($0)
sd $3, ($4)
sd $3, 0($4)
sd $3, 32767($4)
sd $3, -32768($4)
sd $3, 65535($4)
sd $3, 0xffff0000($4)
sd $3, 0xffff8000($4)
sd $3, 0xffff0001($4)
sd $3, 0xffff8001($4)
sd $3, 0xf0000000($4)
sd $3, 0xffffffff($4)
sd $3, 0x12345678($4)
ld $3, 4
ld $3, 4($0)
ld $3, 32767($0)
ld $3, -32768($0)
ld $3, 65535($0)
ld $3, 0xffff0000($0)
ld $3, 0xffff8000($0)
ld $3, 0xffff0001($0)
ld $3, 0xffff8001($0)
ld $3, 0xf0000000($0)
ld $3, 0xffffffff($0)
ld $3, 0x12345678($0)
ld $3, ($4)
ld $3, 0($4)
ld $3, 32767($4)
ld $3, -32768($4)
ld $3, 65535($4)
ld $3, 0xffff0000($4)
ld $3, 0xffff8000($4)
ld $3, 0xffff0001($4)
ld $3, 0xffff8001($4)
ld $3, 0xf0000000($4)
ld $3, 0xffffffff($4)
ld $3, 0x12345678($4)
jraddiusp 0 << 2
jraddiusp 1 << 2
jraddiusp 2 << 2
jraddiusp 3 << 2
jraddiusp 4 << 2
jraddiusp 5 << 2
jraddiusp 6 << 2
jraddiusp 7 << 2
jraddiusp 8 << 2
jraddiusp 9 << 2
jraddiusp 10 << 2
jraddiusp 30 << 2
jraddiusp 31 << 2
ldc2 $3, 0
ldc2 $3, ($0)
ldc2 $3, 4
ldc2 $3, 4($0)
ldc2 $3, ($4)
ldc2 $3, 0($4)
ldc2 $3, 32767($4)
ldc2 $3, -32768($4)
ldc2 $3, 65535($4)
ldc2 $3, 0xffff0000($4)
ldc2 $3, 0xffff8000($4)
ldc2 $3, 0xffff0001($4)
ldc2 $3, 0xffff8001($4)
ldc2 $3, 0xf0000000($4)
ldc2 $3, 0xffffffff($4)
ldc2 $3, 0x12345678($4)
lwc2 $3, 0
lwc2 $3, ($0)
lwc2 $3, 4
lwc2 $3, 4($0)
lwc2 $3, ($4)
lwc2 $3, 0($4)
lwc2 $3, 32767($4)
lwc2 $3, -32768($4)
lwc2 $3, 65535($4)
lwc2 $3, 0xffff0000($4)
lwc2 $3, 0xffff8000($4)
lwc2 $3, 0xffff0001($4)
lwc2 $3, 0xffff8001($4)
lwc2 $3, 0xf0000000($4)
lwc2 $3, 0xffffffff($4)
lwc2 $3, 0x12345678($4)
mfc2 $5, $0
mfc2 $5, $1
mfc2 $5, $2
mfc2 $5, $3
mfc2 $5, $4
mfc2 $5, $5
mfc2 $5, $6
mfc2 $5, $7
mfc2 $5, $8
mfc2 $5, $9
mfc2 $5, $10
mfc2 $5, $11
mfc2 $5, $12
mfc2 $5, $13
mfc2 $5, $14
mfc2 $5, $15
mfc2 $5, $16
mfc2 $5, $17
mfc2 $5, $18
mfc2 $5, $19
mfc2 $5, $20
mfc2 $5, $21
mfc2 $5, $22
mfc2 $5, $23
mfc2 $5, $24
mfc2 $5, $25
mfc2 $5, $26
mfc2 $5, $27
mfc2 $5, $28
mfc2 $5, $29
mfc2 $5, $30
mfc2 $5, $31
mfhc2 $5, $0
mfhc2 $5, $1
mfhc2 $5, $2
mfhc2 $5, $3
mfhc2 $5, $4
mfhc2 $5, $5
mfhc2 $5, $6
mfhc2 $5, $7
mfhc2 $5, $8
mfhc2 $5, $9
mfhc2 $5, $10
mfhc2 $5, $11
mfhc2 $5, $12
mfhc2 $5, $13
mfhc2 $5, $14
mfhc2 $5, $15
mfhc2 $5, $16
mfhc2 $5, $17
mfhc2 $5, $18
mfhc2 $5, $19
mfhc2 $5, $20
mfhc2 $5, $21
mfhc2 $5, $22
mfhc2 $5, $23
mfhc2 $5, $24
mfhc2 $5, $25
mfhc2 $5, $26
mfhc2 $5, $27
mfhc2 $5, $28
mfhc2 $5, $29
mfhc2 $5, $30
mfhc2 $5, $31
mtc2 $5, $0
mtc2 $5, $1
mtc2 $5, $2
mtc2 $5, $3
mtc2 $5, $4
mtc2 $5, $5
mtc2 $5, $6
mtc2 $5, $7
mtc2 $5, $8
mtc2 $5, $9
mtc2 $5, $10
mtc2 $5, $11
mtc2 $5, $12
mtc2 $5, $13
mtc2 $5, $14
mtc2 $5, $15
mtc2 $5, $16
mtc2 $5, $17
mtc2 $5, $18
mtc2 $5, $19
mtc2 $5, $20
mtc2 $5, $21
mtc2 $5, $22
mtc2 $5, $23
mtc2 $5, $24
mtc2 $5, $25
mtc2 $5, $26
mtc2 $5, $27
mtc2 $5, $28
mtc2 $5, $29
mtc2 $5, $30
mtc2 $5, $31
mthc2 $5, $0
mthc2 $5, $1
mthc2 $5, $2
mthc2 $5, $3
mthc2 $5, $4
mthc2 $5, $5
mthc2 $5, $6
mthc2 $5, $7
mthc2 $5, $8
mthc2 $5, $9
mthc2 $5, $10
mthc2 $5, $11
mthc2 $5, $12
mthc2 $5, $13
mthc2 $5, $14
mthc2 $5, $15
mthc2 $5, $16
mthc2 $5, $17
mthc2 $5, $18
mthc2 $5, $19
mthc2 $5, $20
mthc2 $5, $21
mthc2 $5, $22
mthc2 $5, $23
mthc2 $5, $24
mthc2 $5, $25
mthc2 $5, $26
mthc2 $5, $27
mthc2 $5, $28
mthc2 $5, $29
mthc2 $5, $30
mthc2 $5, $31
sdc2 $3, 0
sdc2 $3, ($0)
sdc2 $3, 4
sdc2 $3, 4($0)
sdc2 $3, ($4)
sdc2 $3, 0($4)
sdc2 $3, 32767($4)
sdc2 $3, -32768($4)
sdc2 $3, 65535($4)
sdc2 $3, 0xffff0000($4)
sdc2 $3, 0xffff8000($4)
sdc2 $3, 0xffff0001($4)
sdc2 $3, 0xffff8001($4)
sdc2 $3, 0xf0000000($4)
sdc2 $3, 0xffffffff($4)
sdc2 $3, 0x12345678($4)
swc2 $3, 0
swc2 $3, ($0)
swc2 $3, 4
swc2 $3, 4($0)
swc2 $3, ($4)
swc2 $3, 0($4)
swc2 $3, 32767($4)
swc2 $3, -32768($4)
swc2 $3, 65535($4)
swc2 $3, 0xffff0000($4)
swc2 $3, 0xffff8000($4)
swc2 $3, 0xffff0001($4)
swc2 $3, 0xffff8001($4)
swc2 $3, 0xf0000000($4)
swc2 $3, 0xffffffff($4)
swc2 $3, 0x12345678($4)
cache 0, %lo(test)($3)
lwp $2, %lo(test)($3)
swp $2, %lo(test)($3)
ll $2, %lo(test)($3)
sc $2, %lo(test)($3)
lwl $2, %lo(test)($3)
lwr $2, %lo(test)($3)
swl $2, %lo(test)($3)
swr $2, %lo(test)($3)
lwm $16, %lo(test)($3)
swm $16, %lo(test)($3)
lwc2 $16, %lo(test)($3)
swc2 $16, %lo(test)($3)
lcache $2, %lo(test)($3)
flush $2, %lo(test)($3)
scache $2, %lo(test)($3)
invalidate $2, %lo(test)($3)
sdbbp 1023
wait 1023
syscall 1023
cop2 0x7fffff
.end test
.set reorder
.align 3
.set micromips
.ent fp_test
.globl fp_test
fp_test:
prefx 0, $0($0)
prefx 0, $0($2)
prefx 0, $0($31)
prefx 0, $2($31)
prefx 0, $31($31)
prefx 1, $31($31)
prefx 2, $31($31)
prefx 31, $31($31)
abs.s $f0, $f1
abs.s $f30, $f31
abs.s $f2, $f2
abs.s $f2
abs.d $f0, $f1
abs.d $f30, $f31
abs.d $f2, $f2
abs.d $f2
abs.ps $f0, $f1
abs.ps $f30, $f31
abs.ps $f2, $f2
abs.ps $f2
add.s $f0, $f1, $f2
add.s $f29, $f30, $f31
add.s $f29, $f29, $f30
add.s $f29, $f30
add.d $f0, $f1, $f2
add.d $f29, $f30, $f31
add.d $f29, $f29, $f30
add.d $f29, $f30
add.ps $f0, $f1, $f2
add.ps $f29, $f30, $f31
add.ps $f29, $f29, $f30
add.ps $f29, $f30
alnv.ps $f0, $f1, $f2, $0
alnv.ps $f0, $f1, $f2, $2
alnv.ps $f0, $f1, $f2, $31
alnv.ps $f29, $f30, $f31, $31
alnv.ps $f29, $f29, $f31, $31
bc1f fp_test
bc1f $fcc0, fp_test
bc1f $fcc1, fp_test
bc1f $fcc2, fp_test
bc1f $fcc3, fp_test
bc1f $fcc4, fp_test
bc1f $fcc5, fp_test
bc1f $fcc6, fp_test
bc1f $fcc7, fp_test
bc1t fp_test
bc1t $fcc0, fp_test
bc1t $fcc1, fp_test
bc1t $fcc2, fp_test
bc1t $fcc3, fp_test
bc1t $fcc4, fp_test
bc1t $fcc5, fp_test
bc1t $fcc6, fp_test
bc1t $fcc7, fp_test
c.f.d $f0, $f1
c.f.d $f30, $f31
c.f.d $fcc0, $f30, $f31
c.f.d $fcc1, $f30, $f31
c.f.d $fcc7, $f30, $f31
c.f.s $f0, $f1
c.f.s $f30, $f31
c.f.s $fcc0, $f30, $f31
c.f.s $fcc1, $f30, $f31
c.f.s $fcc7, $f30, $f31
c.f.ps $f0, $f1
c.f.ps $f30, $f31
c.f.ps $fcc0, $f30, $f31
c.f.ps $fcc2, $f30, $f31
c.f.ps $fcc6, $f30, $f31
c.un.d $f0, $f1
c.un.d $f30, $f31
c.un.d $fcc0, $f30, $f31
c.un.d $fcc1, $f30, $f31
c.un.d $fcc7, $f30, $f31
c.un.s $f0, $f1
c.un.s $f30, $f31
c.un.s $fcc0, $f30, $f31
c.un.s $fcc1, $f30, $f31
c.un.s $fcc7, $f30, $f31
c.un.ps $f0, $f1
c.un.ps $f30, $f31
c.un.ps $fcc0, $f30, $f31
c.un.ps $fcc2, $f30, $f31
c.un.ps $fcc6, $f30, $f31
c.eq.d $f0, $f1
c.eq.d $f30, $f31
c.eq.d $fcc0, $f30, $f31
c.eq.d $fcc1, $f30, $f31
c.eq.d $fcc7, $f30, $f31
c.eq.s $f0, $f1
c.eq.s $f30, $f31
c.eq.s $fcc0, $f30, $f31
c.eq.s $fcc1, $f30, $f31
c.eq.s $fcc7, $f30, $f31
c.eq.ps $f0, $f1
c.eq.ps $f30, $f31
c.eq.ps $fcc0, $f30, $f31
c.eq.ps $fcc2, $f30, $f31
c.eq.ps $fcc6, $f30, $f31
c.ueq.d $f0, $f1
c.ueq.d $f30, $f31
c.ueq.d $fcc0, $f30, $f31
c.ueq.d $fcc1, $f30, $f31
c.ueq.d $fcc7, $f30, $f31
c.ueq.s $f0, $f1
c.ueq.s $f30, $f31
c.ueq.s $fcc0, $f30, $f31
c.ueq.s $fcc1, $f30, $f31
c.ueq.s $fcc7, $f30, $f31
c.ueq.ps $f0, $f1
c.ueq.ps $f30, $f31
c.ueq.ps $fcc0, $f30, $f31
c.ueq.ps $fcc2, $f30, $f31
c.ueq.ps $fcc6, $f30, $f31
c.olt.d $f0, $f1
c.olt.d $f30, $f31
c.olt.d $fcc0, $f30, $f31
c.olt.d $fcc1, $f30, $f31
c.olt.d $fcc7, $f30, $f31
c.olt.s $f0, $f1
c.olt.s $f30, $f31
c.olt.s $fcc0, $f30, $f31
c.olt.s $fcc1, $f30, $f31
c.olt.s $fcc7, $f30, $f31
c.olt.ps $f0, $f1
c.olt.ps $f30, $f31
c.olt.ps $fcc0, $f30, $f31
c.olt.ps $fcc2, $f30, $f31
c.olt.ps $fcc6, $f30, $f31
c.ult.d $f0, $f1
c.ult.d $f30, $f31
c.ult.d $fcc0, $f30, $f31
c.ult.d $fcc1, $f30, $f31
c.ult.d $fcc7, $f30, $f31
c.ult.s $f0, $f1
c.ult.s $f30, $f31
c.ult.s $fcc0, $f30, $f31
c.ult.s $fcc1, $f30, $f31
c.ult.s $fcc7, $f30, $f31
c.ult.ps $f0, $f1
c.ult.ps $f30, $f31
c.ult.ps $fcc0, $f30, $f31
c.ult.ps $fcc2, $f30, $f31
c.ult.ps $fcc6, $f30, $f31
c.ole.d $f0, $f1
c.ole.d $f30, $f31
c.ole.d $fcc0, $f30, $f31
c.ole.d $fcc1, $f30, $f31
c.ole.d $fcc7, $f30, $f31
c.ole.s $f0, $f1
c.ole.s $f30, $f31
c.ole.s $fcc0, $f30, $f31
c.ole.s $fcc1, $f30, $f31
c.ole.s $fcc7, $f30, $f31
c.ole.ps $f0, $f1
c.ole.ps $f30, $f31
c.ole.ps $fcc0, $f30, $f31
c.ole.ps $fcc2, $f30, $f31
c.ole.ps $fcc6, $f30, $f31
c.ule.d $f0, $f1
c.ule.d $f30, $f31
c.ule.d $fcc0, $f30, $f31
c.ule.d $fcc1, $f30, $f31
c.ule.d $fcc7, $f30, $f31
c.ule.s $f0, $f1
c.ule.s $f30, $f31
c.ule.s $fcc0, $f30, $f31
c.ule.s $fcc1, $f30, $f31
c.ule.s $fcc7, $f30, $f31
c.ule.ps $f0, $f1
c.ule.ps $f30, $f31
c.ule.ps $fcc0, $f30, $f31
c.ule.ps $fcc2, $f30, $f31
c.ule.ps $fcc6, $f30, $f31
c.sf.d $f0, $f1
c.sf.d $f30, $f31
c.sf.d $fcc0, $f30, $f31
c.sf.d $fcc1, $f30, $f31
c.sf.d $fcc7, $f30, $f31
c.sf.s $f0, $f1
c.sf.s $f30, $f31
c.sf.s $fcc0, $f30, $f31
c.sf.s $fcc1, $f30, $f31
c.sf.s $fcc7, $f30, $f31
c.sf.ps $f0, $f1
c.sf.ps $f30, $f31
c.sf.ps $fcc0, $f30, $f31
c.sf.ps $fcc2, $f30, $f31
c.sf.ps $fcc6, $f30, $f31
c.ngle.d $f0, $f1
c.ngle.d $f30, $f31
c.ngle.d $fcc0, $f30, $f31
c.ngle.d $fcc1, $f30, $f31
c.ngle.d $fcc7, $f30, $f31
c.ngle.s $f0, $f1
c.ngle.s $f30, $f31
c.ngle.s $fcc0, $f30, $f31
c.ngle.s $fcc1, $f30, $f31
c.ngle.s $fcc7, $f30, $f31
c.ngle.ps $f0, $f1
c.ngle.ps $f30, $f31
c.ngle.ps $fcc0, $f30, $f31
c.ngle.ps $fcc2, $f30, $f31
c.ngle.ps $fcc6, $f30, $f31
c.seq.d $f0, $f1
c.seq.d $f30, $f31
c.seq.d $fcc0, $f30, $f31
c.seq.d $fcc1, $f30, $f31
c.seq.d $fcc7, $f30, $f31
c.seq.s $f0, $f1
c.seq.s $f30, $f31
c.seq.s $fcc0, $f30, $f31
c.seq.s $fcc1, $f30, $f31
c.seq.s $fcc7, $f30, $f31
c.seq.ps $f0, $f1
c.seq.ps $f30, $f31
c.seq.ps $fcc0, $f30, $f31
c.seq.ps $fcc2, $f30, $f31
c.seq.ps $fcc6, $f30, $f31
c.ngl.d $f0, $f1
c.ngl.d $f30, $f31
c.ngl.d $fcc0, $f30, $f31
c.ngl.d $fcc1, $f30, $f31
c.ngl.d $fcc7, $f30, $f31
c.ngl.s $f0, $f1
c.ngl.s $f30, $f31
c.ngl.s $fcc0, $f30, $f31
c.ngl.s $fcc1, $f30, $f31
c.ngl.s $fcc7, $f30, $f31
c.ngl.ps $f0, $f1
c.ngl.ps $f30, $f31
c.ngl.ps $fcc0, $f30, $f31
c.ngl.ps $fcc2, $f30, $f31
c.ngl.ps $fcc6, $f30, $f31
c.lt.d $f0, $f1
c.lt.d $f30, $f31
c.lt.d $fcc0, $f30, $f31
c.lt.d $fcc1, $f30, $f31
c.lt.d $fcc7, $f30, $f31
c.lt.s $f0, $f1
c.lt.s $f30, $f31
c.lt.s $fcc0, $f30, $f31
c.lt.s $fcc1, $f30, $f31
c.lt.s $fcc7, $f30, $f31
c.lt.ps $f0, $f1
c.lt.ps $f30, $f31
c.lt.ps $fcc0, $f30, $f31
c.lt.ps $fcc2, $f30, $f31
c.lt.ps $fcc6, $f30, $f31
c.nge.d $f0, $f1
c.nge.d $f30, $f31
c.nge.d $fcc0, $f30, $f31
c.nge.d $fcc1, $f30, $f31
c.nge.d $fcc7, $f30, $f31
c.nge.s $f0, $f1
c.nge.s $f30, $f31
c.nge.s $fcc0, $f30, $f31
c.nge.s $fcc1, $f30, $f31
c.nge.s $fcc7, $f30, $f31
c.nge.ps $f0, $f1
c.nge.ps $f30, $f31
c.nge.ps $fcc0, $f30, $f31
c.nge.ps $fcc2, $f30, $f31
c.nge.ps $fcc6, $f30, $f31
c.le.d $f0, $f1
c.le.d $f30, $f31
c.le.d $fcc0, $f30, $f31
c.le.d $fcc1, $f30, $f31
c.le.d $fcc7, $f30, $f31
c.le.s $f0, $f1
c.le.s $f30, $f31
c.le.s $fcc0, $f30, $f31
c.le.s $fcc1, $f30, $f31
c.le.s $fcc7, $f30, $f31
c.le.ps $f0, $f1
c.le.ps $f30, $f31
c.le.ps $fcc0, $f30, $f31
c.le.ps $fcc2, $f30, $f31
c.le.ps $fcc6, $f30, $f31
c.ngt.d $f0, $f1
c.ngt.d $f30, $f31
c.ngt.d $fcc0, $f30, $f31
c.ngt.d $fcc1, $f30, $f31
c.ngt.d $fcc7, $f30, $f31
c.ngt.s $f0, $f1
c.ngt.s $f30, $f31
c.ngt.s $fcc0, $f30, $f31
c.ngt.s $fcc1, $f30, $f31
c.ngt.s $fcc7, $f30, $f31
c.ngt.ps $f0, $f1
c.ngt.ps $f30, $f31
c.ngt.ps $fcc0, $f30, $f31
c.ngt.ps $fcc2, $f30, $f31
c.ngt.ps $fcc6, $f30, $f31
ceil.l.d $f0, $f1
ceil.l.d $f30, $f31
ceil.l.d $f2, $f2
ceil.l.s $f0, $f1
ceil.l.s $f30, $f31
ceil.l.s $f2, $f2
ceil.w.d $f0, $f1
ceil.w.d $f30, $f31
ceil.w.d $f2, $f2
ceil.w.s $f0, $f1
ceil.w.s $f30, $f31
ceil.w.s $f2, $f2
cfc1 $5, $0
cfc1 $5, $1
cfc1 $5, $2
cfc1 $5, $3
cfc1 $5, $4
cfc1 $5, $5
cfc1 $5, $6
cfc1 $5, $7
cfc1 $5, $8
cfc1 $5, $9
cfc1 $5, $10
cfc1 $5, $11
cfc1 $5, $12
cfc1 $5, $13
cfc1 $5, $14
cfc1 $5, $15
cfc1 $5, $16
cfc1 $5, $17
cfc1 $5, $18
cfc1 $5, $19
cfc1 $5, $20
cfc1 $5, $21
cfc1 $5, $22
cfc1 $5, $23
cfc1 $5, $24
cfc1 $5, $25
cfc1 $5, $26
cfc1 $5, $27
cfc1 $5, $28
cfc1 $5, $29
cfc1 $5, $30
cfc1 $5, $31
cfc1 $5, $f0
cfc1 $5, $f1
cfc1 $5, $f2
cfc1 $5, $f3
cfc1 $5, $f4
cfc1 $5, $f5
cfc1 $5, $f6
cfc1 $5, $f7
cfc1 $5, $f8
cfc1 $5, $f9
cfc1 $5, $f10
cfc1 $5, $f11
cfc1 $5, $f12
cfc1 $5, $f13
cfc1 $5, $f14
cfc1 $5, $f15
cfc1 $5, $f16
cfc1 $5, $f17
cfc1 $5, $f18
cfc1 $5, $f19
cfc1 $5, $f20
cfc1 $5, $f21
cfc1 $5, $f22
cfc1 $5, $f23
cfc1 $5, $f24
cfc1 $5, $f25
cfc1 $5, $f26
cfc1 $5, $f27
cfc1 $5, $f28
cfc1 $5, $f29
cfc1 $5, $f30
cfc1 $5, $f31
cfc2 $5, $0
cfc2 $5, $1
cfc2 $5, $2
cfc2 $5, $3
cfc2 $5, $4
cfc2 $5, $5
cfc2 $5, $6
cfc2 $5, $7
cfc2 $5, $8
cfc2 $5, $9
cfc2 $5, $10
cfc2 $5, $11
cfc2 $5, $12
cfc2 $5, $13
cfc2 $5, $14
cfc2 $5, $15
cfc2 $5, $16
cfc2 $5, $17
cfc2 $5, $18
cfc2 $5, $19
cfc2 $5, $20
cfc2 $5, $21
cfc2 $5, $22
cfc2 $5, $23
cfc2 $5, $24
cfc2 $5, $25
cfc2 $5, $26
cfc2 $5, $27
cfc2 $5, $28
cfc2 $5, $29
cfc2 $5, $30
cfc2 $5, $31
ctc1 $5, $0
ctc1 $5, $1
ctc1 $5, $2
ctc1 $5, $3
ctc1 $5, $4
ctc1 $5, $5
ctc1 $5, $6
ctc1 $5, $7
ctc1 $5, $8
ctc1 $5, $9
ctc1 $5, $10
ctc1 $5, $11
ctc1 $5, $12
ctc1 $5, $13
ctc1 $5, $14
ctc1 $5, $15
ctc1 $5, $16
ctc1 $5, $17
ctc1 $5, $18
ctc1 $5, $19
ctc1 $5, $20
ctc1 $5, $21
ctc1 $5, $22
ctc1 $5, $23
ctc1 $5, $24
ctc1 $5, $25
ctc1 $5, $26
ctc1 $5, $27
ctc1 $5, $28
ctc1 $5, $29
ctc1 $5, $30
ctc1 $5, $31
ctc1 $5, $f0
ctc1 $5, $f1
ctc1 $5, $f2
ctc1 $5, $f3
ctc1 $5, $f4
ctc1 $5, $f5
ctc1 $5, $f6
ctc1 $5, $f7
ctc1 $5, $f8
ctc1 $5, $f9
ctc1 $5, $f10
ctc1 $5, $f11
ctc1 $5, $f12
ctc1 $5, $f13
ctc1 $5, $f14
ctc1 $5, $f15
ctc1 $5, $f16
ctc1 $5, $f17
ctc1 $5, $f18
ctc1 $5, $f19
ctc1 $5, $f20
ctc1 $5, $f21
ctc1 $5, $f22
ctc1 $5, $f23
ctc1 $5, $f24
ctc1 $5, $f25
ctc1 $5, $f26
ctc1 $5, $f27
ctc1 $5, $f28
ctc1 $5, $f29
ctc1 $5, $f30
ctc1 $5, $f31
ctc2 $5, $0
ctc2 $5, $1
ctc2 $5, $2
ctc2 $5, $3
ctc2 $5, $4
ctc2 $5, $5
ctc2 $5, $6
ctc2 $5, $7
ctc2 $5, $8
ctc2 $5, $9
ctc2 $5, $10
ctc2 $5, $11
ctc2 $5, $12
ctc2 $5, $13
ctc2 $5, $14
ctc2 $5, $15
ctc2 $5, $16
ctc2 $5, $17
ctc2 $5, $18
ctc2 $5, $19
ctc2 $5, $20
ctc2 $5, $21
ctc2 $5, $22
ctc2 $5, $23
ctc2 $5, $24
ctc2 $5, $25
ctc2 $5, $26
ctc2 $5, $27
ctc2 $5, $28
ctc2 $5, $29
ctc2 $5, $30
ctc2 $5, $31
cvt.d.l $f0, $f1
cvt.d.l $f30, $f31
cvt.d.l $f2, $f2
cvt.d.s $f0, $f1
cvt.d.s $f30, $f31
cvt.d.s $f2, $f2
cvt.d.w $f0, $f1
cvt.d.w $f30, $f31
cvt.d.w $f2, $f2
cvt.l.s $f0, $f1
cvt.l.s $f30, $f31
cvt.l.s $f2, $f2
cvt.l.d $f0, $f1
cvt.l.d $f30, $f31
cvt.l.d $f2, $f2
cvt.s.l $f0, $f1
cvt.s.l $f30, $f31
cvt.s.l $f2, $f2
cvt.s.d $f0, $f1
cvt.s.d $f30, $f31
cvt.s.d $f2, $f2
cvt.s.w $f0, $f1
cvt.s.w $f30, $f31
cvt.s.w $f2, $f2
cvt.s.pl $f0, $f1
cvt.s.pl $f30, $f31
cvt.s.pl $f2, $f2
cvt.s.pu $f0, $f1
cvt.s.pu $f30, $f31
cvt.s.pu $f2, $f2
cvt.w.s $f0, $f1
cvt.w.s $f30, $f31
cvt.w.s $f2, $f2
cvt.w.d $f0, $f1
cvt.w.d $f30, $f31
cvt.w.d $f2, $f2
cvt.ps.s $f0, $f1, $f2
cvt.ps.s $f29, $f30, $f31
cvt.ps.s $f29, $f29, $f31
cvt.ps.s $f29, $f31
div.d $f0, $f1, $f2
div.d $f29, $f30, $f31
div.d $f29, $f29, $f30
div.d $f29, $f30
div.s $f0, $f1, $f2
div.s $f29, $f30, $f31
div.s $f29, $f29, $f30
div.s $f29, $f30
floor.l.d $f0, $f1
floor.l.d $f30, $f31
floor.l.d $f2, $f2
floor.l.s $f0, $f1
floor.l.s $f30, $f31
floor.l.s $f2, $f2
floor.w.d $f0, $f1
floor.w.d $f30, $f31
floor.w.d $f2, $f2
floor.w.s $f0, $f1
floor.w.s $f30, $f31
floor.w.s $f2, $f2
ldc1 $3, 0
ldc1 $3, ($0)
ldc1 $3, 4
ldc1 $3, 4($0)
ldc1 $3, ($4)
ldc1 $3, 0($4)
ldc1 $3, 32767($4)
ldc1 $3, -32768($4)
ldc1 $3, 65535($4)
ldc1 $3, 0xffff0000($4)
ldc1 $3, 0xffff8000($4)
ldc1 $3, 0xffff0001($4)
ldc1 $3, 0xffff8001($4)
ldc1 $3, 0xf0000000($4)
ldc1 $3, 0xffffffff($4)
ldc1 $3, 0x12345678($4)
ldc1 $f3, 0
ldc1 $f3, ($0)
ldc1 $f3, 4
ldc1 $f3, 4($0)
ldc1 $f3, ($4)
ldc1 $f3, 0($4)
ldc1 $f3, 32767($4)
ldc1 $f3, -32768($4)
ldc1 $f3, 65535($4)
ldc1 $f3, 0xffff0000($4)
ldc1 $f3, 0xffff8000($4)
ldc1 $f3, 0xffff0001($4)
ldc1 $f3, 0xffff8001($4)
ldc1 $f3, 0xf0000000($4)
ldc1 $f3, 0xffffffff($4)
ldc1 $f3, 0x12345678($4)
l.d $f3, 0
l.d $f3, ($0)
l.d $f3, 4
l.d $f3, 4($0)
l.d $f3, ($4)
l.d $f3, 0($4)
l.d $f3, 32767($4)
l.d $f3, -32768($4)
ldxc1 $f0, $0($0)
ldxc1 $f0, $0($2)
ldxc1 $f0, $0($31)
ldxc1 $f0, $2($31)
ldxc1 $f0, $31($31)
ldxc1 $f1, $31($31)
ldxc1 $f2, $31($31)
ldxc1 $f31, $31($31)
luxc1 $f0, $0($0)
luxc1 $f0, $0($2)
luxc1 $f0, $0($31)
luxc1 $f0, $2($31)
luxc1 $f0, $31($31)
luxc1 $f1, $31($31)
luxc1 $f2, $31($31)
luxc1 $f31, $31($31)
lwc1 $3, 0
lwc1 $3, ($0)
lwc1 $3, 4
lwc1 $3, 4($0)
lwc1 $3, ($4)
lwc1 $3, 0($4)
lwc1 $3, 32767($4)
lwc1 $3, -32768($4)
lwc1 $3, 65535($4)
lwc1 $3, 0xffff0000($4)
lwc1 $3, 0xffff8000($4)
lwc1 $3, 0xffff0001($4)
lwc1 $3, 0xffff8001($4)
lwc1 $3, 0xf0000000($4)
lwc1 $3, 0xffffffff($4)
lwc1 $3, 0x12345678($4)
lwc1 $f3, 0
lwc1 $f3, ($0)
lwc1 $f3, 4
lwc1 $f3, 4($0)
lwc1 $f3, ($4)
lwc1 $f3, 0($4)
lwc1 $f3, 32767($4)
lwc1 $f3, -32768($4)
lwc1 $f3, 65535($4)
lwc1 $f3, 0xffff0000($4)
lwc1 $f3, 0xffff8000($4)
lwc1 $f3, 0xffff0001($4)
lwc1 $f3, 0xffff8001($4)
lwc1 $f3, 0xf0000000($4)
lwc1 $f3, 0xffffffff($4)
lwc1 $f3, 0x12345678($4)
l.s $f3, 0
l.s $f3, ($0)
l.s $f3, 4
l.s $f3, 4($0)
l.s $f3, ($4)
l.s $f3, 0($4)
l.s $f3, 32767($4)
l.s $f3, -32768($4)
l.s $f3, 65535($4)
l.s $f3, 0xffff0000($4)
l.s $f3, 0xffff8000($4)
l.s $f3, 0xffff0001($4)
l.s $f3, 0xffff8001($4)
l.s $f3, 0xf0000000($4)
l.s $f3, 0xffffffff($4)
l.s $f3, 0x12345678($4)
lwxc1 $f0, $0($0)
lwxc1 $f0, $0($2)
lwxc1 $f0, $0($31)
lwxc1 $f0, $2($31)
lwxc1 $f0, $31($31)
lwxc1 $f1, $31($31)
lwxc1 $f2, $31($31)
lwxc1 $f31, $31($31)
madd.d $f0, $f1, $f2, $f3
madd.d $f28, $f29, $f30, $f31
madd.s $f0, $f1, $f2, $f3
madd.s $f28, $f29, $f30, $f31
madd.ps $f0, $f1, $f2, $f3
madd.ps $f28, $f29, $f30, $f31
mfc1 $5, $0
mfc1 $5, $1
mfc1 $5, $2
mfc1 $5, $3
mfc1 $5, $4
mfc1 $5, $5
mfc1 $5, $6
mfc1 $5, $7
mfc1 $5, $8
mfc1 $5, $9
mfc1 $5, $10
mfc1 $5, $11
mfc1 $5, $12
mfc1 $5, $13
mfc1 $5, $14
mfc1 $5, $15
mfc1 $5, $16
mfc1 $5, $17
mfc1 $5, $18
mfc1 $5, $19
mfc1 $5, $20
mfc1 $5, $21
mfc1 $5, $22
mfc1 $5, $23
mfc1 $5, $24
mfc1 $5, $25
mfc1 $5, $26
mfc1 $5, $27
mfc1 $5, $28
mfc1 $5, $29
mfc1 $5, $30
mfc1 $5, $31
mfc1 $5, $f0
mfc1 $5, $f1
mfc1 $5, $f2
mfc1 $5, $f3
mfc1 $5, $f4
mfc1 $5, $f5
mfc1 $5, $f6
mfc1 $5, $f7
mfc1 $5, $f8
mfc1 $5, $f9
mfc1 $5, $f10
mfc1 $5, $f11
mfc1 $5, $f12
mfc1 $5, $f13
mfc1 $5, $f14
mfc1 $5, $f15
mfc1 $5, $f16
mfc1 $5, $f17
mfc1 $5, $f18
mfc1 $5, $f19
mfc1 $5, $f20
mfc1 $5, $f21
mfc1 $5, $f22
mfc1 $5, $f23
mfc1 $5, $f24
mfc1 $5, $f25
mfc1 $5, $f26
mfc1 $5, $f27
mfc1 $5, $f28
mfc1 $5, $f29
mfc1 $5, $f30
mfc1 $5, $f31
mfhc1 $5, $0
mfhc1 $5, $1
mfhc1 $5, $2
mfhc1 $5, $3
mfhc1 $5, $4
mfhc1 $5, $5
mfhc1 $5, $6
mfhc1 $5, $7
mfhc1 $5, $8
mfhc1 $5, $9
mfhc1 $5, $10
mfhc1 $5, $11
mfhc1 $5, $12
mfhc1 $5, $13
mfhc1 $5, $14
mfhc1 $5, $15
mfhc1 $5, $16
mfhc1 $5, $17
mfhc1 $5, $18
mfhc1 $5, $19
mfhc1 $5, $20
mfhc1 $5, $21
mfhc1 $5, $22
mfhc1 $5, $23
mfhc1 $5, $24
mfhc1 $5, $25
mfhc1 $5, $26
mfhc1 $5, $27
mfhc1 $5, $28
mfhc1 $5, $29
mfhc1 $5, $30
mfhc1 $5, $31
mfhc1 $5, $f0
mfhc1 $5, $f1
mfhc1 $5, $f2
mfhc1 $5, $f3
mfhc1 $5, $f4
mfhc1 $5, $f5
mfhc1 $5, $f6
mfhc1 $5, $f7
mfhc1 $5, $f8
mfhc1 $5, $f9
mfhc1 $5, $f10
mfhc1 $5, $f11
mfhc1 $5, $f12
mfhc1 $5, $f13
mfhc1 $5, $f14
mfhc1 $5, $f15
mfhc1 $5, $f16
mfhc1 $5, $f17
mfhc1 $5, $f18
mfhc1 $5, $f19
mfhc1 $5, $f20
mfhc1 $5, $f21
mfhc1 $5, $f22
mfhc1 $5, $f23
mfhc1 $5, $f24
mfhc1 $5, $f25
mfhc1 $5, $f26
mfhc1 $5, $f27
mfhc1 $5, $f28
mfhc1 $5, $f29
mfhc1 $5, $f30
mfhc1 $5, $f31
mov.d $f0, $f1
mov.d $f30, $f31
mov.s $f0, $f1
mov.s $f30, $f31
mov.ps $f0, $f1
mov.ps $f30, $f31
movf.d $f2, $f3, $fcc0
movf.d $f2, $f3, $fcc1
movf.d $f2, $f3, $fcc2
movf.d $f2, $f3, $fcc3
movf.d $f2, $f3, $fcc4
movf.d $f2, $f3, $fcc5
movf.d $f2, $f3, $fcc6
movf.d $f2, $f3, $fcc7
movf.d $f30, $f31, $fcc7
movf.s $f2, $f3, $fcc0
movf.s $f2, $f3, $fcc1
movf.s $f2, $f3, $fcc2
movf.s $f2, $f3, $fcc3
movf.s $f2, $f3, $fcc4
movf.s $f2, $f3, $fcc5
movf.s $f2, $f3, $fcc6
movf.s $f2, $f3, $fcc7
movf.s $f30, $f31, $fcc7
movf.ps $f2, $f3, $fcc0
movf.ps $f2, $f3, $fcc2
movf.ps $f2, $f3, $fcc4
movf.ps $f2, $f3, $fcc6
movf.ps $f2, $f3, $fcc6
movf.ps $f30, $f31, $fcc6
movn.d $f2, $f3, $0
movn.d $f2, $f3, $31
movn.s $f2, $f3, $0
movn.s $f2, $f3, $31
movn.ps $f2, $f3, $0
movn.ps $f2, $f3, $31
movt.ps $f2, $f3, $fcc0
movt.ps $f2, $f3, $fcc2
movt.ps $f2, $f3, $fcc4
movt.ps $f2, $f3, $fcc6
movt.ps $f2, $f3, $fcc6
movt.ps $f30, $f31, $fcc6
movz.d $f2, $f3, $0
movz.d $f2, $f3, $31
movz.s $f2, $f3, $0
movz.s $f2, $f3, $31
movz.ps $f2, $f3, $0
movz.ps $f2, $f3, $31
msub.d $f0, $f1, $f2, $f3
msub.d $f28, $f29, $f30, $f31
msub.s $f0, $f1, $f2, $f3
msub.s $f28, $f29, $f30, $f31
msub.ps $f0, $f1, $f2, $f3
msub.ps $f28, $f29, $f30, $f31
mtc1 $5, $0
mtc1 $5, $1
mtc1 $5, $2
mtc1 $5, $3
mtc1 $5, $4
mtc1 $5, $5
mtc1 $5, $6
mtc1 $5, $7
mtc1 $5, $8
mtc1 $5, $9
mtc1 $5, $10
mtc1 $5, $11
mtc1 $5, $12
mtc1 $5, $13
mtc1 $5, $14
mtc1 $5, $15
mtc1 $5, $16
mtc1 $5, $17
mtc1 $5, $18
mtc1 $5, $19
mtc1 $5, $20
mtc1 $5, $21
mtc1 $5, $22
mtc1 $5, $23
mtc1 $5, $24
mtc1 $5, $25
mtc1 $5, $26
mtc1 $5, $27
mtc1 $5, $28
mtc1 $5, $29
mtc1 $5, $30
mtc1 $5, $31
mtc1 $5, $f0
mtc1 $5, $f1
mtc1 $5, $f2
mtc1 $5, $f3
mtc1 $5, $f4
mtc1 $5, $f5
mtc1 $5, $f6
mtc1 $5, $f7
mtc1 $5, $f8
mtc1 $5, $f9
mtc1 $5, $f10
mtc1 $5, $f11
mtc1 $5, $f12
mtc1 $5, $f13
mtc1 $5, $f14
mtc1 $5, $f15
mtc1 $5, $f16
mtc1 $5, $f17
mtc1 $5, $f18
mtc1 $5, $f19
mtc1 $5, $f20
mtc1 $5, $f21
mtc1 $5, $f22
mtc1 $5, $f23
mtc1 $5, $f24
mtc1 $5, $f25
mtc1 $5, $f26
mtc1 $5, $f27
mtc1 $5, $f28
mtc1 $5, $f29
mtc1 $5, $f30
mtc1 $5, $f31
mthc1 $5, $0
mthc1 $5, $1
mthc1 $5, $2
mthc1 $5, $3
mthc1 $5, $4
mthc1 $5, $5
mthc1 $5, $6
mthc1 $5, $7
mthc1 $5, $8
mthc1 $5, $9
mthc1 $5, $10
mthc1 $5, $11
mthc1 $5, $12
mthc1 $5, $13
mthc1 $5, $14
mthc1 $5, $15
mthc1 $5, $16
mthc1 $5, $17
mthc1 $5, $18
mthc1 $5, $19
mthc1 $5, $20
mthc1 $5, $21
mthc1 $5, $22
mthc1 $5, $23
mthc1 $5, $24
mthc1 $5, $25
mthc1 $5, $26
mthc1 $5, $27
mthc1 $5, $28
mthc1 $5, $29
mthc1 $5, $30
mthc1 $5, $31
mthc1 $5, $f0
mthc1 $5, $f1
mthc1 $5, $f2
mthc1 $5, $f3
mthc1 $5, $f4
mthc1 $5, $f5
mthc1 $5, $f6
mthc1 $5, $f7
mthc1 $5, $f8
mthc1 $5, $f9
mthc1 $5, $f10
mthc1 $5, $f11
mthc1 $5, $f12
mthc1 $5, $f13
mthc1 $5, $f14
mthc1 $5, $f15
mthc1 $5, $f16
mthc1 $5, $f17
mthc1 $5, $f18
mthc1 $5, $f19
mthc1 $5, $f20
mthc1 $5, $f21
mthc1 $5, $f22
mthc1 $5, $f23
mthc1 $5, $f24
mthc1 $5, $f25
mthc1 $5, $f26
mthc1 $5, $f27
mthc1 $5, $f28
mthc1 $5, $f29
mthc1 $5, $f30
mthc1 $5, $f31
mul.s $f0, $f1, $f2
mul.s $f29, $f30, $f31
mul.s $f29, $f29, $f30
mul.s $f29, $f30
mul.d $f0, $f1, $f2
mul.d $f29, $f30, $f31
mul.d $f29, $f29, $f30
mul.d $f29, $f30
mul.ps $f0, $f1, $f2
mul.ps $f29, $f30, $f31
mul.ps $f29, $f29, $f30
mul.ps $f29, $f30
neg.s $f0, $f1
neg.s $f30, $f31
neg.s $f2, $f2
neg.s $f2
neg.d $f0, $f1
neg.d $f30, $f31
neg.d $f2, $f2
neg.d $f2
neg.ps $f0, $f1
neg.ps $f30, $f31
neg.ps $f2, $f2
neg.ps $f2
nmadd.d $f0, $f1, $f2, $f3
nmadd.d $f28, $f29, $f30, $f31
nmadd.s $f0, $f1, $f2, $f3
nmadd.s $f28, $f29, $f30, $f31
nmadd.ps $f0, $f1, $f2, $f3
nmadd.ps $f28, $f29, $f30, $f31
nmsub.d $f0, $f1, $f2, $f3
nmsub.d $f28, $f29, $f30, $f31
nmsub.s $f0, $f1, $f2, $f3
nmsub.s $f28, $f29, $f30, $f31
nmsub.ps $f0, $f1, $f2, $f3
nmsub.ps $f28, $f29, $f30, $f31
pll.ps $f0, $f1, $f2
pll.ps $f29, $f30, $f31
pll.ps $f29, $f29, $f30
pll.ps $f29, $f30
plu.ps $f0, $f1, $f2
plu.ps $f29, $f30, $f31
plu.ps $f29, $f29, $f30
plu.ps $f29, $f30
pul.ps $f0, $f1, $f2
pul.ps $f29, $f30, $f31
pul.ps $f29, $f29, $f30
pul.ps $f29, $f30
puu.ps $f0, $f1, $f2
puu.ps $f29, $f30, $f31
puu.ps $f29, $f29, $f30
puu.ps $f29, $f30
recip.s $f0, $f1
recip.s $f30, $f31
recip.s $f2, $f2
recip.d $f0, $f1
recip.d $f30, $f31
recip.d $f2, $f2
round.l.s $f0, $f1
round.l.s $f30, $f31
round.l.s $f2, $f2
round.l.d $f0, $f1
round.l.d $f30, $f31
round.l.d $f2, $f2
round.w.s $f0, $f1
round.w.s $f30, $f31
round.w.s $f2, $f2
round.w.d $f0, $f1
round.w.d $f30, $f31
round.w.d $f2, $f2
rsqrt.s $f0, $f1
rsqrt.s $f30, $f31
rsqrt.s $f2, $f2
rsqrt.d $f0, $f1
rsqrt.d $f30, $f31
rsqrt.d $f2, $f2
sdc1 $3, 0
sdc1 $3, ($0)
sdc1 $3, 4
sdc1 $3, 4($0)
sdc1 $3, ($4)
sdc1 $3, 0($4)
sdc1 $3, 32767($4)
sdc1 $3, -32768($4)
sdc1 $3, 65535($4)
sdc1 $3, 0xffff0000($4)
sdc1 $3, 0xffff8000($4)
sdc1 $3, 0xffff0001($4)
sdc1 $3, 0xffff8001($4)
sdc1 $3, 0xf0000000($4)
sdc1 $3, 0xffffffff($4)
sdc1 $3, 0x12345678($4)
sdc1 $f3, 0
sdc1 $f3, ($0)
sdc1 $f3, 4
sdc1 $f3, 4($0)
sdc1 $f3, ($4)
sdc1 $f3, 0($4)
sdc1 $f3, 32767($4)
sdc1 $f3, -32768($4)
sdc1 $f3, 65535($4)
sdc1 $f3, 0xffff0000($4)
sdc1 $f3, 0xffff8000($4)
sdc1 $f3, 0xffff0001($4)
sdc1 $f3, 0xffff8001($4)
sdc1 $f3, 0xf0000000($4)
sdc1 $f3, 0xffffffff($4)
sdc1 $f3, 0x12345678($4)
s.d $f3, 0
s.d $f3, ($0)
s.d $f3, 4
s.d $f3, 4($0)
s.d $f3, ($4)
s.d $f3, 0($4)
s.d $f3, 32767($4)
s.d $f3, -32768($4)
sdxc1 $f0, $0($0)
sdxc1 $f0, $0($2)
sdxc1 $f0, $0($31)
sdxc1 $f0, $2($31)
sdxc1 $f0, $31($31)
sdxc1 $f1, $31($31)
sdxc1 $f2, $31($31)
sdxc1 $f31, $31($31)
sqrt.s $f0, $f1
sqrt.s $f30, $f31
sqrt.s $f2, $f2
sqrt.d $f0, $f1
sqrt.d $f30, $f31
sqrt.d $f2, $f2
sub.s $f0, $f1, $f2
sub.s $f29, $f30, $f31
sub.s $f29, $f29, $f30
sub.s $f29, $f30
sub.d $f0, $f1, $f2
sub.d $f29, $f30, $f31
sub.d $f29, $f29, $f30
sub.d $f29, $f30
sub.ps $f0, $f1, $f2
sub.ps $f29, $f30, $f31
sub.ps $f29, $f29, $f30
sub.ps $f29, $f30
suxc1 $f0, $0($0)
suxc1 $f0, $0($2)
suxc1 $f0, $0($31)
suxc1 $f0, $2($31)
suxc1 $f0, $31($31)
suxc1 $f1, $31($31)
suxc1 $f2, $31($31)
suxc1 $f31, $31($31)
swc1 $3, 0
swc1 $3, ($0)
swc1 $3, 4
swc1 $3, 4($0)
swc1 $3, ($4)
swc1 $3, 0($4)
swc1 $3, 32767($4)
swc1 $3, -32768($4)
swc1 $3, 65535($4)
swc1 $3, 0xffff0000($4)
swc1 $3, 0xffff8000($4)
swc1 $3, 0xffff0001($4)
swc1 $3, 0xffff8001($4)
swc1 $3, 0xf0000000($4)
swc1 $3, 0xffffffff($4)
swc1 $3, 0x12345678($4)
swc1 $f3, 0
swc1 $f3, ($0)
swc1 $f3, 4
swc1 $f3, 4($0)
swc1 $f3, ($4)
swc1 $f3, 0($4)
swc1 $f3, 32767($4)
swc1 $f3, -32768($4)
swc1 $f3, 65535($4)
swc1 $f3, 0xffff0000($4)
swc1 $f3, 0xffff8000($4)
swc1 $f3, 0xffff0001($4)
swc1 $f3, 0xffff8001($4)
swc1 $f3, 0xf0000000($4)
swc1 $f3, 0xffffffff($4)
swc1 $f3, 0x12345678($4)
s.s $f3, 0
s.s $f3, ($0)
s.s $f3, 4
s.s $f3, 4($0)
s.s $f3, ($4)
s.s $f3, 0($4)
s.s $f3, 32767($4)
s.s $f3, -32768($4)
s.s $f3, 65535($4)
s.s $f3, 0xffff0000($4)
s.s $f3, 0xffff8000($4)
s.s $f3, 0xffff0001($4)
s.s $f3, 0xffff8001($4)
s.s $f3, 0xf0000000($4)
s.s $f3, 0xffffffff($4)
s.s $f3, 0x12345678($4)
swxc1 $f0, $0($0)
swxc1 $f0, $0($2)
swxc1 $f0, $0($31)
swxc1 $f0, $2($31)
swxc1 $f0, $31($31)
swxc1 $f1, $31($31)
swxc1 $f2, $31($31)
swxc1 $f31, $31($31)
trunc.l.s $f0, $f1
trunc.l.s $f30, $f31
trunc.l.s $f2, $f2
trunc.l.d $f0, $f1
trunc.l.d $f30, $f31
trunc.l.d $f2, $f2
trunc.w.s $f0, $f1
trunc.w.s $f30, $f31
trunc.w.s $f2, $f2
trunc.w.d $f0, $f1
trunc.w.d $f30, $f31
trunc.w.d $f2, $f2
movf $2, $3, $fcc0
movf $30, $31, $fcc0
movf $30, $31, $fcc1
movf $30, $31, $fcc2
movf $30, $31, $fcc3
movf $30, $31, $fcc4
movf $30, $31, $fcc5
movf $30, $31, $fcc6
movf $30, $31, $fcc7
movt $2, $3, $fcc0
movt $30, $31, $fcc0
movt $30, $31, $fcc1
movt $30, $31, $fcc2
movt $30, $31, $fcc3
movt $30, $31, $fcc4
movt $30, $31, $fcc5
movt $30, $31, $fcc6
movt $30, $31, $fcc7
.set noreorder
bc1fl $fcc1, test
addu $3, $4, $5
bc1tl $fcc2, test
addu $6, $7, $8
.set reorder
bc1fl $fcc3, test
addu $3, $4, $5
bc1tl $fcc4, test
addu $6, $7, $8
.end fp_test
.set mips64r2
.globl test_mips64
.ent test_mips64
test_mips64:
dabs $2, $3
dabs $2, $2
dabs $2
dadd $2, $3, $4
dadd $29, $30, $31
dadd $2, $2, $3
dadd $2, $3
dadd $2, $3, 0
dadd $2, $3, 1
dadd $2, $3, -512
dadd $2, $3, 511
dadd $2, $3, 32767
dadd $2, $3, -32768
dadd $2, $3, 65535
dadd $2, $3, 0x12345678
dadd $2, $3, 0x1234567887654321
daddi $2, $3, 0
daddi $2, $3, 1
daddi $2, $3, -512
daddi $2, $3, 511
daddi $2, $2, 511
daddi $2, 511
daddi $2, $3, 32767
daddi $2, $3, -32768
daddi $2, $3, 65535
daddi $2, $3, 0x12345678
daddiu $2, $3, 0
daddiu $2, $3, -32768
daddiu $2, $3, 32767
daddiu $2, $2, 32767
daddiu $2, 32767
daddu $2, $3, $4
daddu $29, $30, $31
daddu $2, $2, $3
daddu $2, $3
daddu $2, $3, $0
daddu $2, $3, 0
daddu $2, $3, 1
daddu $2, $3, 32767
daddu $2, $3, -32768
daddu $2, $3, 65535
dclo $2, $3
dclo $3, $2
dclz $2, $3
dclz $3, $2
ddiv $0, $2, $3
ddiv $0, $30, $31
ddiv $0, $3
ddiv $0, $31
ddiv $2, $3, $0
ddiv $2, $3, $4
ddiv $3, $4, 0
ddiv $3, $4, 1
ddiv $3, $4, -1
ddiv $3, $4, 2
ddivu $0, $2, $3
ddivu $0, $30, $31
ddivu $0, $3
ddivu $0, $31
ddivu $2, $3, $0
ddivu $2, $3, $4
ddivu $3, $4, 0
ddivu $3, $4, 1
ddivu $3, $4, -1
ddivu $3, $4, 2
dext $2, $3, 31, 1
dext $2, $3, 0, 32
dext $2, $3, 31, 33
dextm $2, $3, 31, 33
dext $2, $3, 33, 10
dextu $2, $3, 33, 10
dins $2, $3, 31, 1
dins $2, $3, 0, 32
dins $2, $3, 31, 33
dinsm $2, $3, 31, 33
dins $2, $3, 33, 10
dinsu $2, $3, 33, 10
dla $2, test
dlca $2, test
dli $2, -32768
dli $2, 32767
dli $2, 65535
dli $2, 0x12345678
dmfc0 $2, $0
dmfc0 $2, $1
dmfc0 $2, $2
dmfc0 $2, $3
dmfc0 $2, $4
dmfc0 $2, $5
dmfc0 $2, $6
dmfc0 $2, $7
dmfc0 $2, $8
dmfc0 $2, $9
dmfc0 $2, $10
dmfc0 $2, $11
dmfc0 $2, $12
dmfc0 $2, $13
dmfc0 $2, $14
dmfc0 $2, $15
dmfc0 $2, $16
dmfc0 $2, $17
dmfc0 $2, $18
dmfc0 $2, $19
dmfc0 $2, $20
dmfc0 $2, $21
dmfc0 $2, $22
dmfc0 $2, $23
dmfc0 $2, $24
dmfc0 $2, $25
dmfc0 $2, $26
dmfc0 $2, $27
dmfc0 $2, $28
dmfc0 $2, $29
dmfc0 $2, $30
dmfc0 $2, $31
dmfc0 $2, $0, 0
dmfc0 $2, $0, 1
dmfc0 $2, $0, 2
dmfc0 $2, $0, 3
dmfc0 $2, $0, 4
dmfc0 $2, $0, 5
dmfc0 $2, $0, 6
dmfc0 $2, $0, 7
dmfc0 $2, $1, 0
dmfc0 $2, $1, 1
dmfc0 $2, $1, 2
dmfc0 $2, $1, 3
dmfc0 $2, $1, 4
dmfc0 $2, $1, 5
dmfc0 $2, $1, 6
dmfc0 $2, $1, 7
dmfc0 $2, $2, 0
dmfc0 $2, $2, 1
dmfc0 $2, $2, 2
dmfc0 $2, $2, 3
dmfc0 $2, $2, 4
dmfc0 $2, $2, 5
dmfc0 $2, $2, 6
dmfc0 $2, $2, 7
dmtc0 $2, $0
dmtc0 $2, $1
dmtc0 $2, $2
dmtc0 $2, $3
dmtc0 $2, $4
dmtc0 $2, $5
dmtc0 $2, $6
dmtc0 $2, $7
dmtc0 $2, $8
dmtc0 $2, $9
dmtc0 $2, $10
dmtc0 $2, $11
dmtc0 $2, $12
dmtc0 $2, $13
dmtc0 $2, $14
dmtc0 $2, $15
dmtc0 $2, $16
dmtc0 $2, $17
dmtc0 $2, $18
dmtc0 $2, $19
dmtc0 $2, $20
dmtc0 $2, $21
dmtc0 $2, $22
dmtc0 $2, $23
dmtc0 $2, $24
dmtc0 $2, $25
dmtc0 $2, $26
dmtc0 $2, $27
dmtc0 $2, $28
dmtc0 $2, $29
dmtc0 $2, $30
dmtc0 $2, $31
dmtc0 $2, $0, 0
dmtc0 $2, $0, 1
dmtc0 $2, $0, 2
dmtc0 $2, $0, 3
dmtc0 $2, $0, 4
dmtc0 $2, $0, 5
dmtc0 $2, $0, 6
dmtc0 $2, $0, 7
dmtc0 $2, $1, 0
dmtc0 $2, $1, 1
dmtc0 $2, $1, 2
dmtc0 $2, $1, 3
dmtc0 $2, $1, 4
dmtc0 $2, $1, 5
dmtc0 $2, $1, 6
dmtc0 $2, $1, 7
dmtc0 $2, $2, 0
dmtc0 $2, $2, 1
dmtc0 $2, $2, 2
dmtc0 $2, $2, 3
dmtc0 $2, $2, 4
dmtc0 $2, $2, 5
dmtc0 $2, $2, 6
dmtc0 $2, $2, 7
dmfc1 $5, $0
dmfc1 $5, $1
dmfc1 $5, $2
dmfc1 $5, $3
dmfc1 $5, $4
dmfc1 $5, $5
dmfc1 $5, $6
dmfc1 $5, $7
dmfc1 $5, $8
dmfc1 $5, $9
dmfc1 $5, $10
dmfc1 $5, $11
dmfc1 $5, $12
dmfc1 $5, $13
dmfc1 $5, $14
dmfc1 $5, $15
dmfc1 $5, $16
dmfc1 $5, $17
dmfc1 $5, $18
dmfc1 $5, $19
dmfc1 $5, $20
dmfc1 $5, $21
dmfc1 $5, $22
dmfc1 $5, $23
dmfc1 $5, $24
dmfc1 $5, $25
dmfc1 $5, $26
dmfc1 $5, $27
dmfc1 $5, $28
dmfc1 $5, $29
dmfc1 $5, $30
dmfc1 $5, $31
dmfc1 $5, $f0
dmfc1 $5, $f1
dmfc1 $5, $f2
dmfc1 $5, $f3
dmfc1 $5, $f4
dmfc1 $5, $f5
dmfc1 $5, $f6
dmfc1 $5, $f7
dmfc1 $5, $f8
dmfc1 $5, $f9
dmfc1 $5, $f10
dmfc1 $5, $f11
dmfc1 $5, $f12
dmfc1 $5, $f13
dmfc1 $5, $f14
dmfc1 $5, $f15
dmfc1 $5, $f16
dmfc1 $5, $f17
dmfc1 $5, $f18
dmfc1 $5, $f19
dmfc1 $5, $f20
dmfc1 $5, $f21
dmfc1 $5, $f22
dmfc1 $5, $f23
dmfc1 $5, $f24
dmfc1 $5, $f25
dmfc1 $5, $f26
dmfc1 $5, $f27
dmfc1 $5, $f28
dmfc1 $5, $f29
dmfc1 $5, $f30
dmfc1 $5, $f31
dmtc1 $5, $0
dmtc1 $5, $1
dmtc1 $5, $2
dmtc1 $5, $3
dmtc1 $5, $4
dmtc1 $5, $5
dmtc1 $5, $6
dmtc1 $5, $7
dmtc1 $5, $8
dmtc1 $5, $9
dmtc1 $5, $10
dmtc1 $5, $11
dmtc1 $5, $12
dmtc1 $5, $13
dmtc1 $5, $14
dmtc1 $5, $15
dmtc1 $5, $16
dmtc1 $5, $17
dmtc1 $5, $18
dmtc1 $5, $19
dmtc1 $5, $20
dmtc1 $5, $21
dmtc1 $5, $22
dmtc1 $5, $23
dmtc1 $5, $24
dmtc1 $5, $25
dmtc1 $5, $26
dmtc1 $5, $27
dmtc1 $5, $28
dmtc1 $5, $29
dmtc1 $5, $30
dmtc1 $5, $31
dmtc1 $5, $f0
dmtc1 $5, $f1
dmtc1 $5, $f2
dmtc1 $5, $f3
dmtc1 $5, $f4
dmtc1 $5, $f5
dmtc1 $5, $f6
dmtc1 $5, $f7
dmtc1 $5, $f8
dmtc1 $5, $f9
dmtc1 $5, $f10
dmtc1 $5, $f11
dmtc1 $5, $f12
dmtc1 $5, $f13
dmtc1 $5, $f14
dmtc1 $5, $f15
dmtc1 $5, $f16
dmtc1 $5, $f17
dmtc1 $5, $f18
dmtc1 $5, $f19
dmtc1 $5, $f20
dmtc1 $5, $f21
dmtc1 $5, $f22
dmtc1 $5, $f23
dmtc1 $5, $f24
dmtc1 $5, $f25
dmtc1 $5, $f26
dmtc1 $5, $f27
dmtc1 $5, $f28
dmtc1 $5, $f29
dmtc1 $5, $f30
dmtc1 $5, $f31
dmfc2 $2, $0
dmfc2 $2, $1
dmfc2 $2, $2
dmfc2 $2, $3
dmfc2 $2, $4
dmfc2 $2, $5
dmfc2 $2, $6
dmfc2 $2, $7
dmfc2 $2, $8
dmfc2 $2, $9
dmfc2 $2, $10
dmfc2 $2, $11
dmfc2 $2, $12
dmfc2 $2, $13
dmfc2 $2, $14
dmfc2 $2, $15
dmfc2 $2, $16
dmfc2 $2, $17
dmfc2 $2, $18
dmfc2 $2, $19
dmfc2 $2, $20
dmfc2 $2, $21
dmfc2 $2, $22
dmfc2 $2, $23
dmfc2 $2, $24
dmfc2 $2, $25
dmfc2 $2, $26
dmfc2 $2, $27
dmfc2 $2, $28
dmfc2 $2, $29
dmfc2 $2, $30
dmfc2 $2, $31
/*
dmfc2 $2, $0, 0
dmfc2 $2, $0, 1
dmfc2 $2, $0, 2
dmfc2 $2, $0, 3
dmfc2 $2, $0, 4
dmfc2 $2, $0, 5
dmfc2 $2, $0, 6
dmfc2 $2, $0, 7
dmfc2 $2, $1, 0
dmfc2 $2, $1, 1
dmfc2 $2, $1, 2
dmfc2 $2, $1, 3
dmfc2 $2, $1, 4
dmfc2 $2, $1, 5
dmfc2 $2, $1, 6
dmfc2 $2, $1, 7
dmfc2 $2, $2, 0
dmfc2 $2, $2, 1
dmfc2 $2, $2, 2
dmfc2 $2, $2, 3
dmfc2 $2, $2, 4
dmfc2 $2, $2, 5
dmfc2 $2, $2, 6
dmfc2 $2, $2, 7
*/
dmtc2 $2, $0
dmtc2 $2, $1
dmtc2 $2, $2
dmtc2 $2, $3
dmtc2 $2, $4
dmtc2 $2, $5
dmtc2 $2, $6
dmtc2 $2, $7
dmtc2 $2, $8
dmtc2 $2, $9
dmtc2 $2, $10
dmtc2 $2, $11
dmtc2 $2, $12
dmtc2 $2, $13
dmtc2 $2, $14
dmtc2 $2, $15
dmtc2 $2, $16
dmtc2 $2, $17
dmtc2 $2, $18
dmtc2 $2, $19
dmtc2 $2, $20
dmtc2 $2, $21
dmtc2 $2, $22
dmtc2 $2, $23
dmtc2 $2, $24
dmtc2 $2, $25
dmtc2 $2, $26
dmtc2 $2, $27
dmtc2 $2, $28
dmtc2 $2, $29
dmtc2 $2, $30
dmtc2 $2, $31
/*
dmtc2 $2, $0, 0
dmtc2 $2, $0, 1
dmtc2 $2, $0, 2
dmtc2 $2, $0, 3
dmtc2 $2, $0, 4
dmtc2 $2, $0, 5
dmtc2 $2, $0, 6
dmtc2 $2, $0, 7
dmtc2 $2, $1, 0
dmtc2 $2, $1, 1
dmtc2 $2, $1, 2
dmtc2 $2, $1, 3
dmtc2 $2, $1, 4
dmtc2 $2, $1, 5
dmtc2 $2, $1, 6
dmtc2 $2, $1, 7
dmtc2 $2, $2, 0
dmtc2 $2, $2, 1
dmtc2 $2, $2, 2
dmtc2 $2, $2, 3
dmtc2 $2, $2, 4
dmtc2 $2, $2, 5
dmtc2 $2, $2, 6
dmtc2 $2, $2, 7
*/
dmult $2, $3
dmultu $2, $3
dmul $2, $3, $4
dmul $2, $3, 0x12345678
dmulo $2, $3, $4
dmulo $2, $3, 4
dmulou $2, $3, $4
dmulou $2, $3, 4
drem $3, $4, 0
drem $3, $4, 1
drem $3, $4, -1
drem $3, $4, 2
drem $0, $2, $3
drem $0, $30, $31
drem $0, $3
drem $0, $31
drem $3, $4, 0
drem $3, $4, 1
drem $3, $4, -1
drem $3, $4, 2
dremu $0, $2, $3
dremu $0, $30, $31
dremu $0, $3
dremu $0, $31
dremu $3, $4, 0
dremu $3, $4, 1
dremu $3, $4, -1
dremu $3, $4, 2
drol $2, $3, $4
drol $2, $2, $4
drol $2, $3, 4
dror $2, $3, $4
dror $2, $3, 4
dror $2, $3, 36
drorv $2, $3, $4
dror32 $2, $3, 4
drotl $2, $3, $4
drotl $2, $2, $4
drotl $2, $3, 4
drotr $2, $3, $4
drotr $2, $3, 4
drotr $2, $3, 36
drotrv $2, $3, $4
drotr32 $2, $3, 4
dsbh $2, $3
dsbh $2, $2
dsbh $2
dshd $2, $3
dshd $2, $2
dshd $2
dsllv $2, $3, $4
dsll32 $2, $3, 31
dsll $2, $3, $4
dsll $2, $3, 63
dsll $2, $3, 31
dsrav $2, $3, $4
dsra32 $2, $3, 4
dsra $2, $3, $4
dsra $2, $3, 36
dsra $2, $3, 4
dsrlv $2, $3, $4
dsrl32 $2, $3, 31
dsrl $2, $3, $4
dsrl $2, $3, 36
dsrl $2, $3, 4
dsub $2, $3, $4
dsub $29, $30, $31
dsub $2, $2, $3
dsub $2, $3
dsubu $2, $3, $4
dsubu $29, $30, $31
dsubu $2, $2, $3
dsubu $2, $3
dsubu $2, $3, 0x1234
dsubu $2, $3, 0x12345678
dsub $2, $3, 0
dsub $2, $3, 1
dsub $2, $3, 512
dsub $2, $3, -511
dsub $2, $3, -32768
dsub $2, $3, 32767
dsub $2, $3, 65535
dsub $2, $3, 0x12345678
dsub $2, $3, 0x8888111112345678
.set push
.set noreorder
.set nomacro
ld $2, 0
ld $2, 4
ld $2, ($0)
ld $2, 0($0)
ld $2, 4($0)
ld $2, 4($3)
ld $2, -32768($3)
ld $2, 32767($3)
.set pop
ldl $2, 0
ldl $2, 4
ldl $2, ($0)
ldl $2, 0($0)
ldl $2, 4($0)
ldl $2, 4($3)
ldl $2, -512($3)
ldl $2, 511($3)
ldl $2, -32768($3)
ldl $2, 0x12345678($3)
ldr $2, 0
ldr $2, 4
ldr $2, ($0)
ldr $2, 0($0)
ldr $2, 4($0)
ldr $2, 4($3)
ldr $2, -512($3)
ldr $2, 511($3)
ldr $2, -32768($3)
ldr $2, 0x12345678($3)
lld $2, 0
lld $2, 4
lld $2, ($0)
lld $2, 0($0)
lld $2, 4($0)
lld $2, 4($3)
lld $2, -512($3)
lld $2, 511($3)
lld $2, -32768($3)
lld $2, 0x12345678($3)
lwu $2, 0
lwu $2, 4
lwu $2, ($0)
lwu $2, 0($0)
lwu $2, 4($0)
lwu $2, 4($3)
lwu $2, -512($3)
lwu $2, 511($3)
lwu $2, -32768($3)
lwu $2, 0x12345678($3)
scd $2, 0
scd $2, 4
scd $2, ($0)
scd $2, 0($0)
scd $2, 4($0)
scd $2, 4($3)
scd $2, -512($3)
scd $2, 511($3)
scd $2, -32768($3)
scd $2, 0x12345678($3)
.set push
.set noreorder
.set nomacro
sd $2, 0
sd $2, 4
sd $2, ($0)
sd $2, 0($0)
sd $2, 4($0)
sd $2, 4($3)
sd $2, -32768($3)
sd $2, 32767($3)
.set pop
sdl $2, 0
sdl $2, 4
sdl $2, ($0)
sdl $2, 0($0)
sdl $2, 4($0)
sdl $2, 4($3)
sdl $2, -32768($3)
sdl $2, 32767($3)
sdl $2, 0x12345678($3)
sdr $2, 0
sdr $2, 4
sdr $2, ($0)
sdr $2, 0($0)
sdr $2, 4($0)
sdr $2, 4($3)
sdr $2, -32768($3)
sdr $2, 32767($3)
sdr $2, 0x12345678($3)
ldm $s0, 0
ldm $s0, 4
ldm $s0, ($5)
ldm $s0, 2047($5)
ldm $s0-$s1, 2047($5)
ldm $s0-$s2, 2047($5)
ldm $s0-$s3, 2047($5)
ldm $s0-$s4, 2047($5)
ldm $s0-$s5, 2047($5)
ldm $s0-$s6, 2047($5)
ldm $s0-$s7, 2047($5)
ldm $s0-$s8, 2047($5)
ldm $ra, 2047($5)
ldm $s0,$ra, ($5)
ldm $s0-$s1,$ra, ($5)
ldm $s0-$s2,$ra, ($5)
ldm $s0-$s3,$ra, ($5)
ldm $s0-$s4,$ra, ($5)
ldm $s0-$s5,$ra, ($5)
ldm $s0-$s6,$ra, ($5)
ldm $s0-$s7,$ra, ($5)
ldm $s0-$s8,$ra, ($5)
ldm $s0, -32768($0)
ldm $s0, 32767($0)
ldm $s0, 0($0)
ldm $s0, 65535($0)
ldm $s0, -32768($29)
ldm $s0, 32767($29)
ldm $s0, 0($29)
ldm $s0, 65535($29)
ldm $s0, 0x12345678($29)
ldp $2, 0
ldp $2, 4
ldp $2, ($29)
ldp $2, 0($29)
ldp $2, -2048($3)
ldp $2, 2047($3)
ldp $2, -32768($3)
ldp $2, 32767($3)
ldp $2, 0($3)
ldp $2, 65535($3)
ldp $2, -32768($0)
ldp $2, 32767($0)
ldp $2, 65535($0)
ldp $2, 0x12345678($0)
sdm $s0, 0
sdm $s0, 4
sdm $s0, ($5)
sdm $s0, 2047($5)
sdm $s0-$s1, 2047($5)
sdm $s0-$s2, 2047($5)
sdm $s0-$s3, 2047($5)
sdm $s0-$s4, 2047($5)
sdm $s0-$s5, 2047($5)
sdm $s0-$s6, 2047($5)
sdm $s0-$s7, 2047($5)
sdm $s0-$s8, 2047($5)
sdm $ra, 2047($5)
sdm $s0,$ra, ($5)
sdm $s0-$s1,$ra, ($5)
sdm $s0-$s2,$ra, ($5)
sdm $s0-$s3,$ra, ($5)
sdm $s0-$s4,$ra, ($5)
sdm $s0-$s5,$ra, ($5)
sdm $s0-$s6,$ra, ($5)
sdm $s0-$s7,$ra, ($5)
sdm $s0-$s8,$ra, ($5)
sdm $s0, -32768($0)
sdm $s0, 32767($0)
sdm $s0, 0($0)
sdm $s0, 65535($0)
sdm $s0, -32768($29)
sdm $s0, 32767($29)
sdm $s0, 0($29)
sdm $s0, 65535($29)
sdm $s0, 0x12345678($29)
sdp $2, 0
sdp $2, 4
sdp $2, ($29)
sdp $2, 0($29)
sdp $2, -2048($3)
sdp $2, 2047($3)
sdp $2, -32768($3)
sdp $2, 32767($3)
sdp $2, 0($3)
sdp $2, 65535($3)
sdp $2, -32768($0)
sdp $2, 32767($0)
sdp $2, 65535($0)
sdp $2, 0x12345678($0)
uld $3, 0
uld $3, ($0)
uld $3, 4
uld $3, 4($0)
uld $3, 2047
uld $3, -2048
uld $3, 2048
uld $3, -2049
uld $3, 32753($0)
uld $3, -32768($0)
uld $3, 65535($0)
uld $3, 0xffff0000($0)
uld $3, 0xffff8000($0)
uld $3, 0xffff0001($0)
uld $3, 0xffff8001($0)
uld $3, 0xf0000000($0)
uld $3, 0xffffffff($0)
uld $3, 0x12345678($0)
uld $3, 0($4)
uld $3, 4($4)
uld $3, 2047($4)
uld $3, -2048($4)
uld $3, 2048($4)
uld $3, -2049($4)
uld $3, 32753($4)
uld $3, -32768($4)
uld $3, 65535($4)
uld $3, 0xffff0000($4)
uld $3, 0xffff8000($4)
uld $3, 0xffff0001($4)
uld $3, 0xffff8001($4)
uld $3, 0xf0000000($4)
uld $3, 0xffffffff($4)
uld $3, 0x12345678($4)
usd $3, 0
usd $3, ($0)
usd $3, 4
usd $3, 4($0)
usd $3, 2047
usd $3, -2048
usd $3, 2048
usd $3, -2049
usd $3, 32753($0)
usd $3, -32768($0)
usd $3, 65535($0)
usd $3, 0xffff0000($0)
usd $3, 0xffff8000($0)
usd $3, 0xffff0001($0)
usd $3, 0xffff8001($0)
usd $3, 0xf0000000($0)
usd $3, 0xffffffff($0)
usd $3, 0x12345678($0)
usd $3, 0($4)
usd $3, 4($4)
usd $3, 2047($4)
usd $3, -2048($4)
usd $3, 2048($4)
usd $3, -2049($4)
usd $3, 32753($4)
usd $3, -32768($4)
usd $3, 65535($4)
usd $3, 0xffff0000($4)
usd $3, 0xffff8000($4)
usd $3, 0xffff0001($4)
usd $3, 0xffff8001($4)
usd $3, 0xf0000000($4)
usd $3, 0xffffffff($4)
usd $3, 0x12345678($4)
ldl $16, %lo(test)($3)
ldr $16, %lo(test)($3)
lld $16, %lo(test)($3)
lwu $16, %lo(test)($3)
scd $16, %lo(test)($3)
sdl $16, %lo(test)($3)
sdr $16, %lo(test)($3)
ldm $16, %lo(test)($3)
ldp $16, %lo(test)($3)
sdm $16, %lo(test)($3)
sdp $16, %lo(test)($3)
ldc2 $16, %lo(test)($3)
sdc2 $16, %lo(test)($3)
.end test_mips64
.set reorder
.ent test_delay_slot
test_delay_slot:
bal test_delay_slot
bgezal $3, test_delay_slot
bltzal $3, test_delay_slot
bgezall $3, test_delay_slot
bltzall $3, test_delay_slot
jal test_delay_slot
jalx test_delay_slot_ext
.ifndef insn32
jalr16 $2
.endif
jalr32 $2
.ifndef insn32
DSNOP
jr16 $2
.endif
jr32 $2
jalr.hb $2
jr.hb $2
.ifndef insn32
jals test_delay_slot
jalrs16 $2
jalrs32 $2
jrs $2
jalrs.hb $2
jrs.hb $2
.endif
.end test_delay_slot
.set noreorder
.ent test_spec102
test_spec102:
lw $2, -64<<2 ($28)
lw $3, -64<<2 ($28)
lw $4, -64<<2 ($28)
lw $5, -64<<2 ($28)
lw $6, -64<<2 ($28)
lw $7, -64<<2 ($28)
lw $16, -64<<2 ($28)
lw $17, -64<<2 ($28)
lw $17, -63<<2 ($28)
lw $17, -1<<2 ($28)
lw $17, 0<<2 ($28)
lw $17, 1<<2 ($28)
lw $17, 62<<2 ($28)
lw $17, 63<<2 ($28)
lw $17, 64<<2 ($28)
lw $17, -65<<2 ($28)
lw $17, 1 ($28)
lw $17, 2 ($28)
lw $17, 3 ($28)
lw $17, -1 ($28)
lw $17, -2 ($28)
lw $17, -3 ($28)
lw $17, 0 ($27)
addiu $2, $pc, 0
addiu $3, $pc, 0
addiu $4, $pc, 0
addiu $5, $pc, 0
addiu $6, $pc, 0
addiu $7, $pc, 0
addiu $16, $pc, 0
addiu $17, $pc, 0
addiu $17, $pc, 4194303 << 2
addiu $17, $pc, -4194304 << 2
addiupc $2, 0
addiupc $3, 0
addiupc $4, 0
addiupc $5, 0
addiupc $6, 0
addiupc $7, 0
addiupc $16, 0
addiupc $17, 0
addiupc $17, 4194303 << 2
addiupc $17, -4194304 << 2
.end test_spec102
.set noreorder
.ent test_spec107
test_spec107:
movep $5, $6, $0, $0
movep $5, $7, $0, $0
movep $6, $7, $0, $0
movep $4, $21, $0, $0
movep $4, $22, $0, $0
movep $4, $5, $0, $0
movep $4, $6, $0, $0
movep $4, $7, $0, $0
movep $4, $7, $17, $0
movep $4, $7, $2, $0
movep $4, $7, $3, $0
movep $4, $7, $16, $0
movep $4, $7, $18, $0
movep $4, $7, $19, $0
movep $4, $7, $20, $0
movep $4, $7, $20, $17
movep $4, $7, $20, $2
movep $4, $7, $20, $3
movep $4, $7, $20, $16
movep $4, $7, $20, $18
movep $4, $7, $20, $19
movep $4, $7, $20, $20
.ifndef insn32
bals test_spec107
nop
bgezals $2, test_spec107
nop
bltzals $2, test_spec107
nop
.endif
bal test_spec107
nop
bgezal $2, test_spec107
nop
bltzal $2, test_spec107
nop
.end test_spec107
|
tactcomplabs/xbgas-binutils-gdb
| 1,192
|
gas/testsuite/gas/mips/cp3d.s
|
.text
.set noreorder
foo:
ldc3 $0, 0($0)
ldc3 $1, 0($0)
ldc3 $2, 0($0)
ldc3 $3, 0($0)
ldc3 $4, 0($0)
ldc3 $5, 0($0)
ldc3 $6, 0($0)
ldc3 $7, 0($0)
ldc3 $8, 0($0)
ldc3 $9, 0($0)
ldc3 $10, 0($0)
ldc3 $11, 0($0)
ldc3 $12, 0($0)
ldc3 $13, 0($0)
ldc3 $14, 0($0)
ldc3 $15, 0($0)
ldc3 $16, 0($0)
ldc3 $17, 0($0)
ldc3 $18, 0($0)
ldc3 $19, 0($0)
ldc3 $20, 0($0)
ldc3 $21, 0($0)
ldc3 $22, 0($0)
ldc3 $23, 0($0)
ldc3 $24, 0($0)
ldc3 $25, 0($0)
ldc3 $26, 0($0)
ldc3 $27, 0($0)
ldc3 $28, 0($0)
ldc3 $29, 0($0)
ldc3 $30, 0($0)
ldc3 $31, 0($0)
sdc3 $0, 0($0)
sdc3 $1, 0($0)
sdc3 $2, 0($0)
sdc3 $3, 0($0)
sdc3 $4, 0($0)
sdc3 $5, 0($0)
sdc3 $6, 0($0)
sdc3 $7, 0($0)
sdc3 $8, 0($0)
sdc3 $9, 0($0)
sdc3 $10, 0($0)
sdc3 $11, 0($0)
sdc3 $12, 0($0)
sdc3 $13, 0($0)
sdc3 $14, 0($0)
sdc3 $15, 0($0)
sdc3 $16, 0($0)
sdc3 $17, 0($0)
sdc3 $18, 0($0)
sdc3 $19, 0($0)
sdc3 $20, 0($0)
sdc3 $21, 0($0)
sdc3 $22, 0($0)
sdc3 $23, 0($0)
sdc3 $24, 0($0)
sdc3 $25, 0($0)
sdc3 $26, 0($0)
sdc3 $27, 0($0)
sdc3 $28, 0($0)
sdc3 $29, 0($0)
sdc3 $30, 0($0)
sdc3 $31, 0($0)
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 2,507
|
gas/testsuite/gas/mips/micromips-branch-delay.s
|
# Source file used to test microMIPS branch delay slots.
.text
foo:
.set noreorder
bltzal $2, .
li $2, -1
bltzal $2, .
li $2, 0x7fff
bltzal $2, .
li $2, 0xffff
bltzal $2, .
li $2, 0x10000
bltzals $2, .
li $2, -1
bltzals $2, .
li $2, 0x7fff
bltzals $2, .
li $2, 0xffff
bltzals $2, .
li $2, 0x10000
bltzall $2, .
li $2, -1
bltzall $2, .
li $2, 0x7fff
bltzall $2, .
li $2, 0xffff
bltzall $2, .
li $2, 0x10000
bltzal $2, .
addiu $2, $29, -1
bltzal $2, .
addiu $2, $29, 8
bltzal $2, .
addiu $2, $29, 256
bltzal $2, .
addiu $2, $29, 0x7fff
bltzals $2, .
addiu $2, $29, -1
bltzals $2, .
addiu $2, $29, 8
bltzals $2, .
addiu $2, $29, 256
bltzals $2, .
addiu $2, $29, 0x7fff
bltzall $2, .
addiu $2, $29, -1
bltzall $2, .
addiu $2, $29, 8
bltzall $2, .
addiu $2, $29, 256
bltzall $2, .
addiu $2, $29, 0x7fff
bltzal $2, .
addiu $29, $29, -1
bltzal $2, .
addiu $29, $29, 8
bltzal $2, .
addiu $29, $29, 256
bltzal $2, .
addiu $29, $29, 0x7fff
bltzals $2, .
addiu $29, $29, -1
bltzals $2, .
addiu $29, $29, 8
bltzals $2, .
addiu $29, $29, 256
bltzals $2, .
addiu $29, $29, 0x7fff
bltzall $2, .
addiu $29, $29, -1
bltzall $2, .
addiu $29, $29, 8
bltzall $2, .
addiu $29, $29, 256
bltzall $2, .
addiu $29, $29, 0x7fff
bltzal $2, .
addu $2, $29, -1
bltzal $2, .
addu $2, $29, 8
bltzal $2, .
addu $2, $29, 256
bltzal $2, .
addu $2, $29, 0x7fff
bltzal $2, .
addu $2, $29, 0x10000
bltzals $2, .
addu $2, $29, -1
bltzals $2, .
addu $2, $29, 8
bltzals $2, .
addu $2, $29, 256
bltzals $2, .
addu $2, $29, 0x7fff
bltzals $2, .
addu $2, $29, 0x10000
bltzall $2, .
addu $2, $29, -1
bltzall $2, .
addu $2, $29, 8
bltzall $2, .
addu $2, $29, 256
bltzall $2, .
addu $2, $29, 0x7fff
bltzall $2, .
addu $2, $29, 0x10000
bltzal $2, .
addu $29, $29, -1
bltzal $2, .
addu $29, $29, 8
bltzal $2, .
addu $29, $29, 256
bltzal $2, .
addu $29, $29, 0x7fff
bltzal $2, .
addu $29, $29, 0x10000
bltzals $2, .
addu $29, $29, -1
bltzals $2, .
addu $29, $29, 8
bltzals $2, .
addu $29, $29, 256
bltzals $2, .
addu $29, $29, 0x7fff
bltzals $2, .
addu $29, $29, 0x10000
bltzall $2, .
addu $29, $29, -1
bltzall $2, .
addu $29, $29, 8
bltzall $2, .
addu $29, $29, 256
bltzall $2, .
addu $29, $29, 0x7fff
bltzall $2, .
addu $29, $29, 0x10000
.set reorder
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 4,686
|
gas/testsuite/gas/mips/mips64r2-ill.s
|
# source file to test illegal mips64r2 instructions
.set noreorder
.set noat
.text
text_label:
# dext macro position/size checks
# constraint: 0 <= pos < 64
dext $4, $5, -1, 1 # error (position)
dext $4, $5, 0, 1
dext $4, $5, 63, 1
dext $4, $5, 64, 1 # error (position)
# constraint: 0 < size <= 64
dext $4, $5, 0, 0 # error (size)
dext $4, $5, 0, 1
dext $4, $5, 0, 64
dext $4, $5, 0, 65 # error (size)
# constraint: 0 < (pos+size) <= 64
dext $4, $5, 0, 1
dext $4, $5, 0, 2
dext $4, $5, 0, 63
dext $4, $5, 0, 64
dext $4, $5, 1, 1
dext $4, $5, 1, 2
dext $4, $5, 1, 63
dext $4, $5, 1, 64 # error (size)
dext $4, $5, 63, 1
dext $4, $5, 63, 2 # error (size)
dext $4, $5, 63, 63 # error (size)
dext $4, $5, 63, 64 # error (size)
# dextm instruction position/size checks
# constraint: 0 <= pos < 32
dextm $4, $5, -1, 33 # error (position)
dextm $4, $5, 0, 33
dextm $4, $5, 31, 33
dextm $4, $5, 32, 33 # error (position)
# constraint: 32 < size <= 64
dextm $4, $5, 0, 32 # error (size)
dextm $4, $5, 0, 33
dextm $4, $5, 0, 64
dextm $4, $5, 0, 65 # error (size)
# constraint: 32 < (pos+size) <= 64
dextm $4, $5, 0, 33
dextm $4, $5, 0, 34
dextm $4, $5, 0, 63
dextm $4, $5, 0, 64
dextm $4, $5, 1, 33
dextm $4, $5, 1, 34
dextm $4, $5, 1, 63
dextm $4, $5, 1, 64 # error (size)
dextm $4, $5, 31, 33
dextm $4, $5, 31, 34 # error (size)
dextm $4, $5, 31, 63 # error (size)
dextm $4, $5, 31, 64 # error (size)
# dextu instruction position/size checks
# constraint: 32 <= pos < 64
dextu $4, $5, 31, 1 # error (position)
dextu $4, $5, 32, 1
dextu $4, $5, 63, 1
dextu $4, $5, 64, 1 # error (position)
# constraint: 0 < size <= 32
dextu $4, $5, 32, 0 # error (size)
dextu $4, $5, 32, 1
dextu $4, $5, 32, 32
dextu $4, $5, 32, 33 # error (size)
# constraint: 32 < (pos+size) <= 64
dextu $4, $5, 32, 1
dextu $4, $5, 32, 2
dextu $4, $5, 32, 31
dextu $4, $5, 32, 32
dextu $4, $5, 33, 1
dextu $4, $5, 33, 2
dextu $4, $5, 33, 31
dextu $4, $5, 33, 32 # error (size)
dextu $4, $5, 63, 1
dextu $4, $5, 63, 2 # error (size)
dextu $4, $5, 63, 31 # error (size)
dextu $4, $5, 63, 32 # error (size)
# dins macro position/size checks
# constraint: 0 <= pos < 64
dins $4, $5, -1, 1 # error (position)
dins $4, $5, 0, 1
dins $4, $5, 63, 1
dins $4, $5, 64, 1 # error (position)
# constraint: 0 < size <= 64
dins $4, $5, 0, 0 # error (size)
dins $4, $5, 0, 1
dins $4, $5, 0, 64
dins $4, $5, 0, 65 # error (size)
# constraint: 0 < (pos+size) <= 64
dins $4, $5, 0, 1
dins $4, $5, 0, 2
dins $4, $5, 0, 63
dins $4, $5, 0, 64
dins $4, $5, 1, 1
dins $4, $5, 1, 2
dins $4, $5, 1, 63
dins $4, $5, 1, 64 # error (size)
dins $4, $5, 63, 1
dins $4, $5, 63, 2 # error (size)
dins $4, $5, 63, 63 # error (size)
dins $4, $5, 63, 64 # error (size)
# dinsm instruction position/size checks
# constraint: 0 <= pos < 32
dinsm $4, $5, -1, 33 # error (position)
dinsm $4, $5, 0, 33
dinsm $4, $5, 31, 33
dinsm $4, $5, 32, 33 # error (position)
# constraint: 2 <= size <= 64
dinsm $4, $5, 31, 1 # error (size)
dinsm $4, $5, 31, 2
dinsm $4, $5, 0, 64
dinsm $4, $5, 0, 65 # error (size)
# constraint: 32 < (pos+size) <= 64
dinsm $4, $5, 0, 2 # error (size)
dinsm $4, $5, 0, 3 # error (size)
dinsm $4, $5, 0, 63
dinsm $4, $5, 0, 64
dinsm $4, $5, 1, 2 # error (size)
dinsm $4, $5, 1, 3 # error (size)
dinsm $4, $5, 1, 63
dinsm $4, $5, 1, 64 # error (size)
dinsm $4, $5, 30, 2 # error (size)
dinsm $4, $5, 30, 3
dinsm $4, $5, 30, 63 # error (size)
dinsm $4, $5, 30, 64 # error (size)
dinsm $4, $5, 31, 2
dinsm $4, $5, 31, 3
dinsm $4, $5, 31, 63 # error (size)
dinsm $4, $5, 31, 64 # error (size)
# dinsu instruction position/size checks
# constraint: 32 <= pos < 64
dinsu $4, $5, 31, 1 # error (position)
dinsu $4, $5, 32, 1
dinsu $4, $5, 63, 1
dinsu $4, $5, 64, 1 # error (position)
# constraint: 1 <= size <= 32
dinsu $4, $5, 32, 0 # error (size)
dinsu $4, $5, 32, 1
dinsu $4, $5, 32, 32
dinsu $4, $5, 32, 33 # error (size)
# constraint: 32 < (pos+size) <= 64
dinsu $4, $5, 32, 1
dinsu $4, $5, 32, 2
dinsu $4, $5, 32, 31
dinsu $4, $5, 32, 32
dinsu $4, $5, 33, 1
dinsu $4, $5, 33, 2
dinsu $4, $5, 33, 31
dinsu $4, $5, 33, 32 # error (size)
dinsu $4, $5, 62, 1
dinsu $4, $5, 62, 2
dinsu $4, $5, 62, 31 # error (size)
dinsu $4, $5, 62, 32 # error (size)
dinsu $4, $5, 63, 1
dinsu $4, $5, 63, 2 # error (size)
dinsu $4, $5, 63, 31 # error (size)
dinsu $4, $5, 63, 32 # error (size)
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 2,124
|
gas/testsuite/gas/mips/vr5400.s
|
.text
stuff:
.ent stuff
/* Integer instructions. */
mul $4,$5,$6
mulu $4,$5,$6
mulhi $4,$5,$6
mulhiu $4,$5,$6
muls $4,$5,$6
mulsu $4,$5,$6
mulshi $4,$5,$6
mulshiu $4,$5,$6
macc $4,$5,$6
maccu $4,$5,$6
macchi $4,$5,$6
macchiu $4,$5,$6
msac $4,$5,$6
msacu $4,$5,$6
msachi $4,$5,$6
msachiu $4,$5,$6
ror $4,$5,25
rorv $4,$5,$6
dror $4,$5,25
dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */
dror32 $4,$5,25
drorv $4,$5,$6
/* Debug instructions. */
dbreak
dret
mfdr $3,$3
mtdr $3,$3
/* Coprocessor 0 instructions, minus standard ISA 3 ones.
That leaves just the performance monitoring registers. */
mfpc $4,1
mfps $4,1
mtpc $4,1
mtps $4,1
/* Multimedia instructions. */
.macro nsel2 op
/* Test each form of each vector opcode. */
\op $f0,$f2
\op $f4,$f6[2]
\op $f6,15
.if 0 /* Which is right?? */
/* Test negative numbers in immediate-value slot. */
\op $f4,-3
.else
/* Test that it's recognized as an unsigned field. */
\op $f4,31
.endif
.endm
.macro nsel3 op
/* Test each form of each vector opcode. */
\op $f0,$f2,$f4
\op $f2,$f4,$f6[2]
\op $f6,$f4,15
.if 0 /* Which is right?? */
/* Test negative numbers in immediate-value slot. */
\op $f4,$f6,-3
.else
/* Test that it's recognized as an unsigned field. */
\op $f4,$f6,31
.endif
.endm
nsel3 add.ob
nsel3 and.ob
nsel2 c.eq.ob
nsel2 c.le.ob
nsel2 c.lt.ob
nsel3 max.ob
nsel3 min.ob
nsel3 mul.ob
nsel2 mula.ob
nsel2 mull.ob
nsel2 muls.ob
nsel2 mulsl.ob
nsel3 nor.ob
nsel3 or.ob
nsel3 pickf.ob
nsel3 pickt.ob
nsel3 sub.ob
nsel3 xor.ob
/* ALNI, SHFL: Vector only. */
alni.ob $f0,$f2,$f4,5
shfl.mixh.ob $f0,$f2,$f4
shfl.mixl.ob $f0,$f2,$f4
shfl.pach.ob $f0,$f2,$f4
shfl.pacl.ob $f0,$f2,$f4
/* SLL,SRL: Scalar or immediate. */
sll.ob $f2,$f4,$f6[3]
sll.ob $f4,$f6,14
srl.ob $f2,$f4,$f6[3]
srl.ob $f4,$f6,14
/* RZU: Immediate, must be 0, 8, or 16. */
rzu.ob $f2,13
/* No selector. */
rach.ob $f2
racl.ob $f2
racm.ob $f2
wach.ob $f2
wacl.ob $f2,$f4
ror $4,$5,$6
rol $4,$5,15
dror $4,$5,$6
drol $4,$5,31
drol $4,$5,62
.space 8
.end stuff
|
tactcomplabs/xbgas-binutils-gdb
| 2,865
|
gas/testsuite/gas/mips/micromips-branch-relax.s
|
.text
.set micromips
.set noreorder
test:
b32 test
addu $3, $4, $5
beqz32 $3, test
addu $3, $4, $5
bnez32 $3, test
addu $3, $4, $5
b test
addu $3, $4, $5
bc test
addu $3, $4, $5
bal test
addu $3, $4, $5
.ifndef insn32
bals test
addu $3, $4, $5
.endif
beqz $3, test
addu $3, $4, $5
bnez $3, test
addu $3, $4, $5
.ifndef insn32
b16 test2
addu $3, $4, $5
beqz16 $3, test2
addu $3, $4, $5
bnez16 $3, test2
addu $3, $4, $5
.endif
b test2
addu $3, $4, $5
bc test2
addu $3, $4, $5
bal test2
addu $3, $4, $5
.ifndef insn32
bals test2
addu $3, $4, $5
.endif
beqz $3, test2
addu $3, $4, $5
bnez $3, test2
addu $3, $4, $5
.ifndef insn32
b16 test3
addu $3, $4, $5
beqz16 $3, test3
addu $3, $4, $5
bnez16 $3, test3
addu $3, $4, $5
.endif
b32 test2
addu $3, $4, $5
bc32 test2
addu $3, $4, $5
bal32 test2
addu $3, $4, $5
.ifndef insn32
bals32 test2
addu $3, $4, $5
.endif
beqz32 $3, test2
addu $3, $4, $5
bnez32 $3, test2
addu $3, $4, $5
j test3
addu $3, $4, $5
jal test3
addu $3, $4, $5
b test3
addu $3, $4, $5
bc test3
addu $3, $4, $5
bal test3
addu $3, $4, $5
.ifndef insn32
bals test3
addu $3, $4, $5
.endif
beq $3, $4, test3
addu $3, $4, $5
bne $3, $4, test3
addu $3, $4, $5
bltz $3, test3
addu $3, $4, $5
bgez $3, test3
addu $3, $4, $5
blez $20, test3
addu $3, $4, $5
bgtz $20, test3
addu $3, $4, $5
beqzc $3, test3
addu $3, $4, $5
bnezc $3, test3
addu $3, $4, $5
bgezal $30, test3
addu $3, $4, $5
bltzal $30, test3
addu $3, $4, $5
.ifndef insn32
bgezals $30, test3
addu $3, $4, $5
bltzals $30, test3
addu $3, $4, $5
.endif
bc1f test3
addu $3, $4, $5
bc1t test3
addu $3, $4, $5
bc2f test3
addu $3, $4, $5
bc2t test3
addu $3, $4, $5
beql $3, $4, test3
addu $3, $4, $5
beqz $3, test3
xor $3, $4, $5
bge $3, $4, test3
xor $3, $4, $5
bgel $3, $4, test3
xor $3, $4, $5
bgeu $3, $4, test3
xor $3, $4, $5
bgeul $3, $4, test3
xor $3, $4, $5
bgezall $3, test3
xor $3, $4, $5
bgezl $3, test3
xor $3, $4, $5
bgt $3, $4, test3
xor $3, $4, $5
bgtl $3, $4, test3
xor $3, $4, $5
bgtu $3, $4, test3
xor $3, $4, $5
bgtul $3, $4, test3
xor $3, $4, $5
bgtzl $3, test3
xor $3, $4, $5
ble $3, $4, test3
xor $3, $4, $5
blel $3, $4, test3
xor $3, $4, $5
bleu $3, $4, test3
xor $3, $4, $5
bleul $3, $4, test3
xor $3, $4, $5
blezl $3, test3
xor $3, $4, $5
blt $3, $4, test3
xor $3, $4, $5
bltl $3, $4, test3
xor $3, $4, $5
bltu $3, $4, test3
xor $3, $4, $5
bltul $3, $4, test3
xor $3, $4, $5
bltzall $3, test3
xor $3, $4, $5
bltzl $3, test3
xor $3, $4, $5
bnel $3, $4, test3
xor $3, $4, $5
bnez $3, test3
xor $3, $4, $5
bnezl $3, test3
xor $3, $4, $5
.skip 511 << 1
test2:
.insn
.skip (32767 - 511) << 1
test3:
addu $3, $4, $5
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,436
|
gas/testsuite/gas/mips/lineno.s
|
.text
# some data
.word 0xdeadbeef
.word 0xdeadbeef
.word 0xdeadbeef
.word 0xdeadbeef
# some real code, compiled from a toy C program
.globl main
.ent main
main:
.frame $fp,24,$31 # vars= 16, regs= 2/0, args= 0, extra= 0
.mask 0xc0000000,-8
.fmask 0x00000000,0
subu $sp,$sp,24
sw $31,20($sp)
sw $fp,16($sp)
move $fp,$sp
jal __main
li $2,2 # 0x2
sw $2,0($fp)
lw $2,0($fp)
move $3,$2
sll $4,$3,1
addu $2,$4,$2
sw $2,4($fp)
lw $4,4($fp)
jal g
lw $3,0($fp)
move $2,$3
b $L1
$L1:
move $sp,$fp
lw $31,20($sp)
lw $fp,16($sp)
addu $sp,$sp,24
j $31
.end main
.align 2
.globl g
.ent g
g:
.frame $fp,24,$31 # vars= 16, regs= 1/0, args= 0, extra= 0
.mask 0x40000000,-16
.fmask 0x00000000,0
subu $sp,$sp,24
sw $fp,16($sp)
move $fp,$sp
sw $4,0($fp)
lw $2,0($fp)
addu $3,$2,1
move $2,$3
b $L2
$L2:
move $sp,$fp
lw $fp,16($sp)
addu $sp,$sp,24
j $31
.end g
|
tactcomplabs/xbgas-binutils-gdb
| 2,685
|
gas/testsuite/gas/mips/mips-gp32-fp32.s
|
.sdata
shared: .word 11
.data
unshared:
.word 1
.word 2
.word 3
.word 4
.text
func:
.set noreorder
li $4, 0x12345678 # 0000 lui a0,0x1234
# 0004 ori a0,a0,0x5678
la $4, shared # 0008 addiu a0,gp,shared
la $4, unshared # 000c lui a0,hi(unshared)
# 0010 addiu a0,a0,lo(unshared)
la $4, end # 0014 lui a0,hi(end)
# 0018 addiu a0,a0,lo(end)
j end # 001c j end
jal end # 0020 jal end
lw $4, shared # 0024 lw a0,shared(gp)
lw $4, unshared # 0028 lui a0,hi(unshared)
# 002c lw a0,lo(unshared)(a0)
lw $4, end # 0030 lui a0,hi(end)
# 0034 lw a0,lo(end)(a0)
ld $4, shared # 0038 lw a0,shared(gp)
# 003c lw a1,shared+4(gp)
ld $4, unshared # 0040 lui at,hi(unshared)
# 0044 lw a0,lo(unshared)(at)
# 0048 lw a1,lo(unshared)+4(at)
ld $4, end # 004c lui at,hi(end)
# 0050 lw a0,lo(end)(at)
# 0054 lw a1,lo(end)+4(at)
sw $4, shared # 0058 sw a0,shared(gp)
sw $4, unshared # 005c lui at,hi(unshared)
# 0060 sw a0,lo(unshared)(at)
sd $4, shared # 0064 sw a0,shared(gp)
# 0068 sw a1,shared+4(gp)
sd $4, unshared # 006c lui at,hi(unshared)
# 0070 sw a0,lo(unshared)(at)
# 0074 sw a1,lo(unshared)+4(at)
ulh $4, unshared # 0078 lui at,hi(unshared)
# 007c addiu at,at,lo(unshared)
# 0080 lb a0,0(at)
# 0084 lbu at,1(at)
# 0088 sll a0,a0,8
# 008c or a0,a0,at
ush $4, unshared # 0090 lui at,hi(unshared)
# 0094 addiu at,at,lo(unshared)
# 0098 sb a0,1(at)
# 009c srl a0,a0,8
# 00a0 sb a0,0(at)
# 00a4 lbu at,1(at)
# 00a8 sll a0,a0,8
# 00ac or a0,a0,at
ulw $4, unshared # 00b0 lui at,hi(unshared)
# 00b4 addiu at,at,lo(unshared)
# 00b8 lwl a0,0(at)
# 00bc lwr a0,3(at)
usw $4, unshared # 00c0 lui at,hi(unshared)
# 00c4 addiu at,at,lo(unshared)
# 00c8 swl a0,0(at)
# 00cc swr a0,3(at)
li.d $4, 1.0 # 00d0 lui a0,0x3ff0
# 00d4 move a1,zero
li.d $4, 1.9 # 00d8 lui at,hi(F1.9)
# 00dc lw a0,lo(F1.9)(at)
# 00e0 lw a1,lo(F1.9)+4(at)
li.d $f0, 1.0 # 00e4 lui at,0x3ff0
# 00e8 mtc1 at,$f1
# 00ec mtc1 zero,$f0
li.d $f0, 1.9 # 00f0 ldc1 $f0,L1.9(gp)
seq $4, $5, -100 # 00f4 addiu a0,a1,100
# 00f8 sltiu a0,a0,1
sne $4, $5, -100 # 00fc addiu a0,a1,100
# 0100 sltu a0,zero,a0
move $4, $5 # 0104 move a0,a1
# Not available in 32-bit mode
# dla $4, shared
# dla $4, unshared
# uld $4, unshared
# usd $4, unshared
# Should produce warnings given -mgp32
# bgt $4, 0x7fffffff, end
# bgtu $4, 0xffffffff, end
# ble $4, 0x7fffffff, end
# bleu $4, 0xffffffff, end
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
end:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,849
|
gas/testsuite/gas/mips/ush.s
|
# Source file used to test the ush macro.
.data
data_label:
.extern big_external_data_label,1000
.extern small_external_data_label,1
.comm big_external_common,1000
.comm small_external_common,1
.lcomm big_local_common,1000
.lcomm small_local_common,1
.text
ush $4,0
ush $4,1
ush $4,0x8000
ush $4,-0x8000
ush $4,0x10000
ush $4,0x1a5a5
ush $4,0($5)
ush $4,1($5)
ush $4,data_label
ush $4,big_external_data_label
ush $4,small_external_data_label
ush $4,big_external_common
ush $4,small_external_common
ush $4,big_local_common
ush $4,small_local_common
ush $4,data_label+1
ush $4,big_external_data_label+1
ush $4,small_external_data_label+1
ush $4,big_external_common+1
ush $4,small_external_common+1
ush $4,big_local_common+1
ush $4,small_local_common+1
ush $4,data_label+0x8000
ush $4,big_external_data_label+0x8000
ush $4,small_external_data_label+0x8000
ush $4,big_external_common+0x8000
ush $4,small_external_common+0x8000
ush $4,big_local_common+0x8000
ush $4,small_local_common+0x8000
ush $4,data_label-0x8000
ush $4,big_external_data_label-0x8000
ush $4,small_external_data_label-0x8000
ush $4,big_external_common-0x8000
ush $4,small_external_common-0x8000
ush $4,big_local_common-0x8000
ush $4,small_local_common-0x8000
ush $4,data_label+0x10000
ush $4,big_external_data_label+0x10000
ush $4,small_external_data_label+0x10000
ush $4,big_external_common+0x10000
ush $4,small_external_common+0x10000
ush $4,big_local_common+0x10000
ush $4,small_local_common+0x10000
ush $4,data_label+0x1a5a5
ush $4,big_external_data_label+0x1a5a5
ush $4,small_external_data_label+0x1a5a5
ush $4,big_external_common+0x1a5a5
ush $4,small_external_common+0x1a5a5
ush $4,big_local_common+0x1a5a5
ush $4,small_local_common+0x1a5a5
# Round to a 16 byte boundary, for ease in testing multiple targets.
nop
|
tactcomplabs/xbgas-binutils-gdb
| 2,750
|
gas/testsuite/gas/mips/r5900.s
|
.text
stuff:
.ent stuff
.set push
.set noreorder
.set noat
add $0, $0, $31
add $1, $10, $3
add $31, $31, $0
addi $31, $0, 0
addi $1, $10, 3
addi $0, $31, -1
addiu $31, $0, 0
addiu $1, $10, 3
addiu $31, $0, 0xFFFF
and $0, $0, $31
and $1, $10, $3
and $31, $31, $0
andi $31, $0, 0
andi $1, $10, 3
andi $0, $31, 0xFFFF
nop
# The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I.
c.lt.s $f0, $f31
c.lt.s $f31, $f0
# The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I.
c.le.s $f0, $f31
c.le.s $f31, $f0
c.eq.s $f0, $f31
c.eq.s $f31, $f0
c.f.s $f0, $f31
c.f.s $f31, $f0
# The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
# The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
# For compatibility the instruction trunc.w.s uses the opcode of cvt.w.s.
# cvt.w.s should not be used on R5900.
trunc.w.s $f0, $f31
trunc.w.s $f31, $f0
# 128 bit store instruction.
sq $0, 0($0)
sq $1, 0x7fff($1)
sq $8, -0x8000($8)
sq $31, -1($31)
# 128 bit load instruction.
lq $0, 0($0)
lq $1, 0x7fff($1)
lq $8, -0x8000($8)
lq $31, -1($31)
# Prefetch cache
pref 0, 0($0)
pref 1, 0x7fff($1)
pref 8, -0x8000($8)
pref 31, -1($31)
# Preformance counter registers
mfpc $31, 0
mfpc $0, 1
mfps $0, 0
mfps $31, 0
mtpc $31, 0
mtpc $0, 1
mtps $0, 0
mtps $31, 0
# Pipeline1
mfhi1 $0
mfhi1 $31
mthi1 $0
mthi1 $31
mflo1 $0
mflo1 $31
mtlo1 $0
mtlo1 $31
movn $0, $0, $31
movn $31, $31, $0
movz $0, $0, $31
movz $31, $31, $0
# Parallel instructions operating on 128 bit registers:
pcpyld $0, $0, $31
pcpyld $31, $31, $0
pextlh $0, $0, $31
pextlh $31, $31, $0
pextlw $0, $0, $31
pextlw $31, $31, $0
# G1 instructions
mult $0, $0, $31
mult $31, $31, $0
multu $0, $0, $31
multu $31, $31, $0
mul $0, $0, $31
mul $31, $31, $0
madd $0, $0, $31
madd $31, $31, $0
madd $0, $31
madd $31, $0
maddu $0, $0, $31
maddu $31, $31, $0
maddu $0, $31
maddu $31, $0
sync
.set pop
.set push
.set reorder
# Test the short loop fix with 3 loop instructions.
li $3, 300
short_loop3:
addi $3, -1
addi $4, -1
# A NOP will be inserted in the branch delay slot.
bne $3, $0, short_loop3
# Test the short loop fix with 6 loop instructions.
li $3, 300
short_loop6:
addi $3, -1
addi $4, -1
addi $5, -1
addi $6, -1
addi $7, -1
# A NOP will be inserted in the branch delay slot.
bne $3, $0, short_loop6
# Test the short loop fix with 7 loop instructions.
li $3, 300
short_loop7:
addi $3, -1
addi $4, -1
addi $5, -1
addi $6, -1
addi $7, -1
addi $8, -1
# The short loop fix does not apply for loops with
# more than 6 instructions.
bne $3, $0, short_loop7
li $4, 3
.set pop
.space 8
.end stuff
|
tactcomplabs/xbgas-binutils-gdb
| 2,679
|
gas/testsuite/gas/mips/mips-abi32.s
|
.sdata
shared: .word 11
.data
unshared:
.word 1
.word 2
.word 3
.word 4
.text
func:
.set noreorder
li $4, 0x12345678 # 0000 lui a0,0x1234
# 0004 ori a0,a0,0x5678
la $4, shared # 0008 addiu a0,gp,shared
la $4, unshared # 000c lui a0,hi(unshared)
# 0010 addiu a0,a0,lo(unshared)
la $4, end # 0014 lui a0,hi(end)
# 0018 addiu a0,a0,lo(end)
j end # 001c j end
jal end # 0020 jal end
lw $4, shared # 0024 lw a0,shared(gp)
lw $4, unshared # 0028 lui a0,hi(unshared)
# 002c lw a0,lo(unshared)(a0)
lw $4, end # 0030 lui a0,hi(end)
# 0034 lw a0,lo(end)(a0)
ld $4, shared # 0038 lw a0,shared(gp)
# 003c lw a1,shared+4(gp)
ld $4, unshared # 0040 lui at,hi(unshared)
# 0044 lw a0,lo(unshared)(at)
# 0048 lw a1,lo(unshared)+4(at)
ld $4, end # 004c lui at,hi(end)
# 0050 lw a0,lo(end)(at)
# 0054 lw a1,lo(end)+4(at)
sw $4, shared # 0058 sw a0,shared(gp)
sw $4, unshared # 005c lui at,hi(unshared)
# 0060 sw a0,lo(unshared)(at)
sd $4, shared # 0064 sw a0,shared(gp)
# 0068 sw a1,shared+4(gp)
sd $4, unshared # 006c lui at,hi(unshared)
# 0070 sw a0,lo(unshared)(at)
# 0074 sw a1,lo(unshared)+4(at)
ulh $4, unshared # 0078 lui at,hi(unshared)
# 007c addiu at,at,lo(unshared)
# 0080 lb a0,0(at)
# 0084 lbu at,1(at)
# 0088 sll a0,a0,8
# 008c or a0,a0,at
ush $4, unshared # 0090 lui at,hi(unshared)
# 0094 addiu at,at,lo(unshared)
# 0098 sb a0,1(at)
# 009c srl a0,a0,8
# 00a0 sb a0,0(at)
# 00a4 lbu at,1(at)
# 00a8 sll a0,a0,8
# 00ac or a0,a0,at
ulw $4, unshared # 00b0 lui at,hi(unshared)
# 00b4 addiu at,at,lo(unshared)
# 00b8 lwl a0,0(at)
# 00bc lwr a0,3(at)
usw $4, unshared # 00c0 lui at,hi(unshared)
# 00c4 addiu at,at,lo(unshared)
# 00c8 swl a0,0(at)
# 00cc swr a0,3(at)
li.d $4, 1.0 # 00d0 lui a0,0x3ff0
# 00d4 move a1,zero
li.d $4, 1.9 # 00d8 lui at,hi(F1.9)
# 00dc lw a0,lo(F1.9)(at)
# 00e0 lw a1,lo(F1.9)+4(at)
li.d $f0, 1.0 # 00e4 lui at,0x3ff0
# 00e8 mtc1 at,$f1
# 00ec mtc1 zero,$f0
li.d $f0, 1.9 # 00f0 ldc1 $f0,L1.9(gp)
seq $4, $5, -100 # 00f4 addiu a0,a1,100
# 00f8 sltiu a0,a0,1
sne $4, $5, -100 # 00fc addiu a0,a1,100
# 0100 sltu a0,zero,a0
move $4, $5 # 0104 move a0,a1
# Not available in 32-bit mode
# dla $4, shared
# dla $4, unshared
# uld $4, unshared
# usd $4, unshared
# Should produce warnings given -mgp32
# bgt $4, 0x7fffffff, end
# bgtu $4, 0xffffffff, end
# ble $4, 0x7fffffff, end
# bleu $4, 0xffffffff, end
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
end:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 4,014
|
gas/testsuite/gas/mips/cp0sel-names.s
|
# source file to test objdump's disassembly using various styles of
# CP0 (w/ non-zero select code) register names.
.set noreorder
.set noat
.globl text_label .text
text_label:
mtc0 $0, $0, 1
mtc0 $0, $0, 2
mtc0 $0, $0, 3
mtc0 $0, $0, 4
mtc0 $0, $0, 5
mtc0 $0, $0, 6
mtc0 $0, $0, 7
mtc0 $0, $1, 1
mtc0 $0, $1, 2
mtc0 $0, $1, 3
mtc0 $0, $1, 4
mtc0 $0, $1, 5
mtc0 $0, $1, 6
mtc0 $0, $1, 7
mtc0 $0, $2, 1
mtc0 $0, $2, 2
mtc0 $0, $2, 3
mtc0 $0, $2, 4
mtc0 $0, $2, 5
mtc0 $0, $2, 6
mtc0 $0, $2, 7
mtc0 $0, $3, 1
mtc0 $0, $3, 2
mtc0 $0, $3, 3
mtc0 $0, $3, 4
mtc0 $0, $3, 5
mtc0 $0, $3, 6
mtc0 $0, $3, 7
mtc0 $0, $4, 1
mtc0 $0, $4, 2
mtc0 $0, $4, 3
mtc0 $0, $4, 4
mtc0 $0, $4, 5
mtc0 $0, $4, 6
mtc0 $0, $4, 7
mtc0 $0, $5, 1
mtc0 $0, $5, 2
mtc0 $0, $5, 3
mtc0 $0, $5, 4
mtc0 $0, $5, 5
mtc0 $0, $5, 6
mtc0 $0, $5, 7
mtc0 $0, $6, 1
mtc0 $0, $6, 2
mtc0 $0, $6, 3
mtc0 $0, $6, 4
mtc0 $0, $6, 5
mtc0 $0, $6, 6
mtc0 $0, $6, 7
mtc0 $0, $7, 1
mtc0 $0, $7, 2
mtc0 $0, $7, 3
mtc0 $0, $7, 4
mtc0 $0, $7, 5
mtc0 $0, $7, 6
mtc0 $0, $7, 7
mtc0 $0, $8, 1
mtc0 $0, $8, 2
mtc0 $0, $8, 3
mtc0 $0, $8, 4
mtc0 $0, $8, 5
mtc0 $0, $8, 6
mtc0 $0, $8, 7
mtc0 $0, $9, 1
mtc0 $0, $9, 2
mtc0 $0, $9, 3
mtc0 $0, $9, 4
mtc0 $0, $9, 5
mtc0 $0, $9, 6
mtc0 $0, $9, 7
mtc0 $0, $10, 1
mtc0 $0, $10, 2
mtc0 $0, $10, 3
mtc0 $0, $10, 4
mtc0 $0, $10, 5
mtc0 $0, $10, 6
mtc0 $0, $10, 7
mtc0 $0, $11, 1
mtc0 $0, $11, 2
mtc0 $0, $11, 3
mtc0 $0, $11, 4
mtc0 $0, $11, 5
mtc0 $0, $11, 6
mtc0 $0, $11, 7
mtc0 $0, $12, 1
mtc0 $0, $12, 2
mtc0 $0, $12, 3
mtc0 $0, $12, 4
mtc0 $0, $12, 5
mtc0 $0, $12, 6
mtc0 $0, $12, 7
mtc0 $0, $13, 1
mtc0 $0, $13, 2
mtc0 $0, $13, 3
mtc0 $0, $13, 4
mtc0 $0, $13, 5
mtc0 $0, $13, 6
mtc0 $0, $13, 7
mtc0 $0, $14, 1
mtc0 $0, $14, 2
mtc0 $0, $14, 3
mtc0 $0, $14, 4
mtc0 $0, $14, 5
mtc0 $0, $14, 6
mtc0 $0, $14, 7
mtc0 $0, $15, 1
mtc0 $0, $15, 2
mtc0 $0, $15, 3
mtc0 $0, $15, 4
mtc0 $0, $15, 5
mtc0 $0, $15, 6
mtc0 $0, $15, 7
mtc0 $0, $16, 1
mtc0 $0, $16, 2
mtc0 $0, $16, 3
mtc0 $0, $16, 4
mtc0 $0, $16, 5
mtc0 $0, $16, 6
mtc0 $0, $16, 7
mtc0 $0, $17, 1
mtc0 $0, $17, 2
mtc0 $0, $17, 3
mtc0 $0, $17, 4
mtc0 $0, $17, 5
mtc0 $0, $17, 6
mtc0 $0, $17, 7
mtc0 $0, $18, 1
mtc0 $0, $18, 2
mtc0 $0, $18, 3
mtc0 $0, $18, 4
mtc0 $0, $18, 5
mtc0 $0, $18, 6
mtc0 $0, $18, 7
mtc0 $0, $19, 1
mtc0 $0, $19, 2
mtc0 $0, $19, 3
mtc0 $0, $19, 4
mtc0 $0, $19, 5
mtc0 $0, $19, 6
mtc0 $0, $19, 7
mtc0 $0, $20, 1
mtc0 $0, $20, 2
mtc0 $0, $20, 3
mtc0 $0, $20, 4
mtc0 $0, $20, 5
mtc0 $0, $20, 6
mtc0 $0, $20, 7
mtc0 $0, $21, 1
mtc0 $0, $21, 2
mtc0 $0, $21, 3
mtc0 $0, $21, 4
mtc0 $0, $21, 5
mtc0 $0, $21, 6
mtc0 $0, $21, 7
mtc0 $0, $22, 1
mtc0 $0, $22, 2
mtc0 $0, $22, 3
mtc0 $0, $22, 4
mtc0 $0, $22, 5
mtc0 $0, $22, 6
mtc0 $0, $22, 7
mtc0 $0, $23, 1
mtc0 $0, $23, 2
mtc0 $0, $23, 3
mtc0 $0, $23, 4
mtc0 $0, $23, 5
mtc0 $0, $23, 6
mtc0 $0, $23, 7
mtc0 $0, $24, 1
mtc0 $0, $24, 2
mtc0 $0, $24, 3
mtc0 $0, $24, 4
mtc0 $0, $24, 5
mtc0 $0, $24, 6
mtc0 $0, $24, 7
mtc0 $0, $25, 1
mtc0 $0, $25, 2
mtc0 $0, $25, 3
mtc0 $0, $25, 4
mtc0 $0, $25, 5
mtc0 $0, $25, 6
mtc0 $0, $25, 7
mtc0 $0, $26, 1
mtc0 $0, $26, 2
mtc0 $0, $26, 3
mtc0 $0, $26, 4
mtc0 $0, $26, 5
mtc0 $0, $26, 6
mtc0 $0, $26, 7
mtc0 $0, $27, 1
mtc0 $0, $27, 2
mtc0 $0, $27, 3
mtc0 $0, $27, 4
mtc0 $0, $27, 5
mtc0 $0, $27, 6
mtc0 $0, $27, 7
mtc0 $0, $28, 1
mtc0 $0, $28, 2
mtc0 $0, $28, 3
mtc0 $0, $28, 4
mtc0 $0, $28, 5
mtc0 $0, $28, 6
mtc0 $0, $28, 7
mtc0 $0, $29, 1
mtc0 $0, $29, 2
mtc0 $0, $29, 3
mtc0 $0, $29, 4
mtc0 $0, $29, 5
mtc0 $0, $29, 6
mtc0 $0, $29, 7
mtc0 $0, $30, 1
mtc0 $0, $30, 2
mtc0 $0, $30, 3
mtc0 $0, $30, 4
mtc0 $0, $30, 5
mtc0 $0, $30, 6
mtc0 $0, $30, 7
mtc0 $0, $31, 1
mtc0 $0, $31, 2
mtc0 $0, $31, 3
mtc0 $0, $31, 4
mtc0 $0, $31, 5
mtc0 $0, $31, 6
mtc0 $0, $31, 7
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,821
|
gas/testsuite/gas/mips/mips64r2.s
|
# source file to test assembly of mips64r2 instructions
# (assumes that mips32r2 instructions will be tested separately for mips64r2.)
.set noreorder
.set noat
.text
text_label:
# unprivileged CPU instructions
# Test macro's ability to turn "dext" into "dext", "dextm" and
# "dextu" as appropriate. Also, add some explicit tests of the
# actual instructions.
dext $2, $3, 0, 1 # dext
dext $2, $3, 0, 32 # dext
dext $2, $3, 0, 33 # dextm
dext $2, $3, 0, 64 # dextm
dext $2, $3, 31, 1 # dext
dext $2, $3, 31, 32 # dext
dext $2, $3, 31, 33 # dextm
dext $2, $3, 32, 1 # dextu
dext $2, $3, 32, 32 # dextu
dext $2, $3, 63, 1 # dextu
dextm $2, $3, 10, 44
dextu $2, $3, 42, 12
# Test macro's ability to turn "dins" into "dins", "dinsm" and
# "dinsu" as appropriate. Also, add some explicit tests of the
# non-macro instructions.
dins $2, $3, 0, 1 # dins
dins $2, $3, 0, 32 # dins
dins $2, $3, 0, 33 # dinsm
dins $2, $3, 0, 64 # dinsm
dins $2, $3, 31, 1 # dins
dins $2, $3, 31, 2 # dinsm
dins $2, $3, 31, 33 # dinsm
dins $2, $3, 32, 1 # dinsu
dins $2, $3, 32, 32 # dinsu
dins $2, $3, 63, 1 # dinsu
dinsm $2, $3, 10, 44
dinsu $2, $3, 42, 12
# This file checks that in fact HW rotate will
# be used for this arch, and checks assembly
# of the official MIPS mnemonics. (Note that disassembly
# uses the traditional "dror", "dror32" and "drorv"
# mnemonics.) Additional rotate tests are done by rol64-hw.d.
drotl $25, $10, 4 # dror32
drotr $25, $10, 4 # dror
drotl $25, $10, 36 # dror
drotr $25, $10, 36 # dror32
drotl $25, $10, $4 # neg / drorv
drotr $25, $10, $4 # drorv
drotr32 $25, $10, 4 # dror32
drotrv $25, $10, $4 # drorv
dsbh $7
dsbh $8, $10
dshd $7
dshd $8, $10
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,528
|
gas/testsuite/gas/mips/la.s
|
# Source file used to test the la macro.
.data
data_label:
.extern big_external_data_label,1000
.extern small_external_data_label,1
.comm big_external_common,1000
.comm small_external_common,1
.lcomm big_local_common,1000
.lcomm small_local_common,1
.text
la $4,0
la $4,1
la $4,0x8000
la $4,-0x8000
la $4,0x10000
la $4,0x1a5a5
la $4,0($5)
la $4,1($5)
la $4,0x8000($5)
la $4,-0x8000($5)
la $4,0x10000($5)
la $4,0x1a5a5($5)
la $4,data_label
la $4,big_external_data_label
la $4,small_external_data_label
la $4,big_external_common
la $4,small_external_common
la $4,big_local_common
la $4,small_local_common
la $4,data_label+1
la $4,big_external_data_label+1
la $4,small_external_data_label+1
la $4,big_external_common+1
la $4,small_external_common+1
la $4,big_local_common+1
la $4,small_local_common+1
la $4,data_label+0x8000
la $4,big_external_data_label+0x8000
la $4,small_external_data_label+0x8000
la $4,big_external_common+0x8000
la $4,small_external_common+0x8000
la $4,big_local_common+0x8000
la $4,small_local_common+0x8000
la $4,data_label-0x8000
la $4,big_external_data_label-0x8000
la $4,small_external_data_label-0x8000
la $4,big_external_common-0x8000
la $4,small_external_common-0x8000
la $4,big_local_common-0x8000
la $4,small_local_common-0x8000
la $4,data_label+0x10000
la $4,big_external_data_label+0x10000
la $4,small_external_data_label+0x10000
la $4,big_external_common+0x10000
la $4,small_external_common+0x10000
la $4,big_local_common+0x10000
la $4,small_local_common+0x10000
la $4,data_label+0x1a5a5
la $4,big_external_data_label+0x1a5a5
la $4,small_external_data_label+0x1a5a5
la $4,big_external_common+0x1a5a5
la $4,small_external_common+0x1a5a5
la $4,big_local_common+0x1a5a5
la $4,small_local_common+0x1a5a5
la $4,data_label($5)
la $4,big_external_data_label($5)
la $4,small_external_data_label($5)
la $4,big_external_common($5)
la $4,small_external_common($5)
la $4,big_local_common($5)
la $4,small_local_common($5)
la $4,data_label+1($5)
la $4,big_external_data_label+1($5)
la $4,small_external_data_label+1($5)
la $4,big_external_common+1($5)
la $4,small_external_common+1($5)
la $4,big_local_common+1($5)
la $4,small_local_common+1($5)
la $4,data_label+0x8000($5)
la $4,big_external_data_label+0x8000($5)
la $4,small_external_data_label+0x8000($5)
la $4,big_external_common+0x8000($5)
la $4,small_external_common+0x8000($5)
la $4,big_local_common+0x8000($5)
la $4,small_local_common+0x8000($5)
la $4,data_label-0x8000($5)
la $4,big_external_data_label-0x8000($5)
la $4,small_external_data_label-0x8000($5)
la $4,big_external_common-0x8000($5)
la $4,small_external_common-0x8000($5)
la $4,big_local_common-0x8000($5)
la $4,small_local_common-0x8000($5)
la $4,data_label+0x10000($5)
la $4,big_external_data_label+0x10000($5)
la $4,small_external_data_label+0x10000($5)
la $4,big_external_common+0x10000($5)
la $4,small_external_common+0x10000($5)
la $4,big_local_common+0x10000($5)
la $4,small_local_common+0x10000($5)
la $4,data_label+0x1a5a5($5)
la $4,big_external_data_label+0x1a5a5($5)
la $4,small_external_data_label+0x1a5a5($5)
la $4,big_external_common+0x1a5a5($5)
la $4,small_external_common+0x1a5a5($5)
la $4,big_local_common+0x1a5a5($5)
la $4,small_local_common+0x1a5a5($5)
la $4,($5)
la $4,(0x123456)
la $4,(0x123456)($5)
la $4,(big_external_data_label)
la $4,(big_external_data_label)($5)
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,192
|
gas/testsuite/gas/mips/cp3m.s
|
.text
.set noreorder
foo:
lwc3 $0, 0($0)
lwc3 $1, 0($0)
lwc3 $2, 0($0)
lwc3 $3, 0($0)
lwc3 $4, 0($0)
lwc3 $5, 0($0)
lwc3 $6, 0($0)
lwc3 $7, 0($0)
lwc3 $8, 0($0)
lwc3 $9, 0($0)
lwc3 $10, 0($0)
lwc3 $11, 0($0)
lwc3 $12, 0($0)
lwc3 $13, 0($0)
lwc3 $14, 0($0)
lwc3 $15, 0($0)
lwc3 $16, 0($0)
lwc3 $17, 0($0)
lwc3 $18, 0($0)
lwc3 $19, 0($0)
lwc3 $20, 0($0)
lwc3 $21, 0($0)
lwc3 $22, 0($0)
lwc3 $23, 0($0)
lwc3 $24, 0($0)
lwc3 $25, 0($0)
lwc3 $26, 0($0)
lwc3 $27, 0($0)
lwc3 $28, 0($0)
lwc3 $29, 0($0)
lwc3 $30, 0($0)
lwc3 $31, 0($0)
swc3 $0, 0($0)
swc3 $1, 0($0)
swc3 $2, 0($0)
swc3 $3, 0($0)
swc3 $4, 0($0)
swc3 $5, 0($0)
swc3 $6, 0($0)
swc3 $7, 0($0)
swc3 $8, 0($0)
swc3 $9, 0($0)
swc3 $10, 0($0)
swc3 $11, 0($0)
swc3 $12, 0($0)
swc3 $13, 0($0)
swc3 $14, 0($0)
swc3 $15, 0($0)
swc3 $16, 0($0)
swc3 $17, 0($0)
swc3 $18, 0($0)
swc3 $19, 0($0)
swc3 $20, 0($0)
swc3 $21, 0($0)
swc3 $22, 0($0)
swc3 $23, 0($0)
swc3 $24, 0($0)
swc3 $25, 0($0)
swc3 $26, 0($0)
swc3 $27, 0($0)
swc3 $28, 0($0)
swc3 $29, 0($0)
swc3 $30, 0($0)
swc3 $31, 0($0)
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 1,234
|
gas/testsuite/gas/mips/r5900-vu0.s
|
.text
.set noreorder
.set noat
.ent text_label
.global text_label
text_label:
# Floating point transfer to VU
lqc2 $0,0($0)
lqc2 $1, 0x7fff($1)
lqc2 $8, -0x8000($8)
lqc2 $31, -1($31)
.set at
lqc2 $0, 0x8000($2)
lqc2 $8, -0x8001($31)
lqc2 $31, 0xF1234567($4)
.set noat
# Floating point transfer from VU
sqc2 $0,0($0)
sqc2 $1, 0x7fff($1)
sqc2 $8, -0x8000($8)
sqc2 $31, -1($31)
.set at
sqc2 $0, 0x8000($2)
sqc2 $8, -0x8001($31)
sqc2 $31, 0xF1234567($4)
.set noat
# Integer transfer from VU
cfc2 $0,$0
cfc2 $0,$31
cfc2.i $0,$0
cfc2.i $0,$31
cfc2.ni $0,$0
cfc2.ni $0,$31
# Integer transfer to VU
ctc2 $0,$0
ctc2 $0,$31
ctc2.i $0,$0
ctc2.i $0,$31
ctc2.ni $0,$0
ctc2.ni $0,$31
# Floating point transfer from VU
qmfc2 $0,$0
qmfc2 $0,$31
qmfc2.i $0,$0
qmfc2.i $0,$31
qmfc2.ni $0,$0
qmfc2.ni $0,$31
# Floating point transfer to VU
qmtc2 $0,$0
qmtc2 $0,$31
qmtc2.i $0,$0
qmtc2.i $0,$31
qmtc2.ni $0,$0
qmtc2.ni $0,$31
# COP2 conditional branch instructions
branch_label:
bc2f branch_label
nop
bc2fl branch_label
nop
bc2t branch_label
nop
bc2tl branch_label
nop
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
.end text_label
|
tactcomplabs/xbgas-binutils-gdb
| 1,232
|
gas/testsuite/gas/mips/mips16-relax-unextended-1.s
|
.module mips3
.set mips16
.set autoextend
foo:
# Operand code:
sll.t $2, $3, 17 # <
sll.t $2, $3, bar
dsll.t $4, $5, 17 # [
dsll.t $4, $5, bar
dsrl.t $6, 17 # ]
dsrl.t $6, bar
lb.t $4, 0x1234($5) # 5
lb.t $4, bar($5)
lb.t $4, %hi(baz)($5)
slti.t $6, 0x5678 # 8
slti.t $6, bar
la.t $2, . + 0x1234 # A
la.t $2, . + bar
ld.t $3, . + 0x5678 # B
ld.t $3, . + bar
sd.t $31, 0x5678($29) # C
sd.t $31, bar($29)
sd.t $31, %lo(baz)($29)
sd.t $4, 0x5678($29) # D
sd.t $4, bar($29)
sd.t $4, %lo(baz)($29)
dla.t $5, . + 0x5678 # E
dla.t $5, . + bar
daddiu.t $2, $3, 0x5678 # F
daddiu.t $2, $3, bar
lh.t $6, 0x1234($7) # H
lh.t $6, bar($7)
lh.t $6, %lo(baz)($7)
addiu.t $29, 0x5678 # K
addiu.t $29, bar
addiu.t $29, %lo(baz)
cmpi.t $2, 0x1234 # U
cmpi.t $2, bar
cmpi.t $2, %hi(baz)
addiu.t $3, $pc, 0x5678 # V
addiu.t $3, $pc, bar
addiu.t $3, $pc, %lo(baz)
daddiu.t $4, $pc, 0x5678 # W
daddiu.t $4, $pc, bar
daddiu.t $4, $pc, %lo(baz)
daddiu.t $5, 0x5678 # j
daddiu.t $5, bar
daddiu.t $5, %lo(baz)
addiu.t $6, 0x1234 # k
addiu.t $6, bar
addiu.t $2, %lo(baz)
beqz.t $7, . + 0x5678 # p
b.t . + 0x1234 # q
.set bar, 0x5678
|
tactcomplabs/xbgas-binutils-gdb
| 20,563
|
gas/testsuite/gas/mips/r5900-error-vu0.s
|
.set noreorder
.set noat
.globl text_label .text
text_label:
# All instructions have at least one error in suffix or in register
# usage. All errors should be detected by the assembler.
vabs.w $vf0w, $vf0z
vabs.w $vf0z, $vf31w
vabs.xw $vf0xw, $vf0w
vabs.xw $vf0x, $vf31xw
vabs.xyzw $vf0xyz, $vf0xyzw
vaddai.w $ACCw, $vf0w, $Q
vaddai.w $ACCz, $vf0w, $Q
vaddai.xyzw $ACCxyw, $vf0xyzw, $I
vaddaq.w $ACCw, $vf31z, $Q
vaddaq.x $ACCx, $vf0w, $Q
vaddaq.x $ACCw, $vf1x, $Q
vaddaq.xw $ACCxw, $vf1z, $Q
vaddaq.xw $ACCw, $vf31xw, $Q
vaddaq.xyw $ACCxw, $vf0xyw, $Q
vaddaq.xyw $ACCxyw, $vf1yw, $Q
vaddaq.xyzw $ACCxyzw, $vf1yzw, $Q
vaddaq.z $ACCxz, $vf0xz, $Q
vaddaq.x $ACCxz, $vf1xz, $Q
vaddaq.xzw $ACCxw, $vf0xzw, $Q
vaddaq.y $ACCy, $vf0y, $R
vaddaq.y $ACCy, $vf1y, $I
vaddaq.yw $ACCxyw, $vf0yw, $Q
vaddaq.yw $ACCwy, $vf1yw, $Q
vaddaq.yw $ACCyw, $vf31wy, $Q
vaddaq.yz $ACCy, $vf0yz, $Q
vaddaq.yzw $ACCxyzw, $vf0yzw, $Q
vaddaq.yzw $ACCyzw, $vf1xyzw, $Q
vaddaq.yzw $ACCyzw, $vf31yzw, $Qyzw
vadda.w $ACCw, $vf1w, $vf2z
vadda.w $ACCw, $vf31w, $vf0x
vaddaw.xyzw $ACCxyzw, $vf0xyzw, $vf0x
vaddaw.xyzw $ACCxyzw, $vf0xyzw, $vf31xyzw
vaddaw.xz $ACCxyz, $vf0xz, $vf0w
vaddaw.xz $ACCxzw, $vf0xz, $vf31w
vaddaw.xz $ACCxz, $vf1xyz, $vf2w
vaddaw.xz $ACCxz, $vf31xzw, $vf0w
vaddaw.xz $ACCxz, $vf31z, $vf15w
vaddaw.xzw $ACCxyzw, $vf0xzw, $vf0w
vaddaw.xzw $ACC, $vf0, $vf31z
vaddaw.xzw $ACCxzw, $vf1xzw, $vf2z
vaddaw.xzw $ACCxzw, $vf31xzw, $vf0x
vaddaw.y $ACCy, $vf0y, $vf0z
vaddax.w $ACCw, $vf0w, $vf31z
vaddax.w $ACC, $vf1, $vf2z
vaddax.w $ACCw, $vf31w, $vf0w
vaddax.w $ACCw, $vf31w, $vf15y
vadda.xw $ACCxw, $vf0xw, $vf0xyw
vadda.xw $ACCxw, $vf0xw, $vf31wx
vaddax.x $ACCw, $vf0x, $vf0x
vaddax.x $ACCx, $vf0x, $vf31w
vaddax.x $ACCx, $vf1x, $vf2y
vaddax.x $ACCx, $vf31x, $vf0z
vaddax.xw $ACCxw, $vf0xw, $vf0y
vaddax.xw $ACCxw, $vf0xw, $vf31z
vaddax.xw $ACCxw, $vf1xw, $vf2w
vaddax.xw $ACCxw, $vf31wx, $vf0
vaddax.xyzw $ACC, $vf1, $vf2y
vaddax.xyzw $ACC, $vf31, $vf0z
vadda.zw $ACCzw, $vf0zw, $vf0wz
vadda.zw $ACCzw, $vf0w, $vf31zw
vadda.zw $ACCw, $vf1zw, $vf2zw
vadda.zw $ACCxzw, $vf31zw, $vf0zw
vadda.zw $ACCzw, $vf31xzw, $vf15zw
vadda.zw $ACCzw, $vf31zw, $vf31yzw
vaddaz.x $ACCx, $vf0x, $vf0x
vaddaz.x $ACCx, $vf0x, $vf31y
vaddaz.xw $ACCxw, $vf31w, $vf15z
vaddaz.xw $ACCx, $vf31xw, $vf31z
vaddaz.xy $ACCx, $vf0xy, $vf0z
vaddaz.xy $ACCxyz, $vf0xy, $vf31z
vaddaz.y $ACCx, $vf31y, $vf0z
vaddaz.yw $ACCyw, $vf0yw, $a0
vaddi.w $vf0w, $vf31w, $Q
vaddi.w $vf1w, $vf2w, $R
vaddi.w $vf31w, $vf0w, $ACC
vaddi.w $vf31w, $vf15w, $ACCw
vaddi.xzw $vf1xyzw, $vf2xzw, $I
vaddi.xzw $vf31xw, $vf0xzw, $I
vaddi.xzw $vf31xzw, $vf15xzw, $Ixzw
vaddq.w $vf1w, $vf2w, $Qw
vaddq.w $vf31w, $vf0w, $R
vaddq.w $vf31w, $vf15w, $ACCw
vaddq.w $vf31w, $vf31w, $ACC
vaddq.xyzw $vf31xyzw, $vf32xyzw, $Q
vaddq.xyzw $vf31xyzw, $32, $Q
vaddq.xz $vf0xz, $-1, $Q
vaddw.xyzw $vf31xyzw, $vf15xyzw, $vf7z
vaddx.yw $vf31yw, $vf31yw, $vf31y
vadd.xyz $vf0xyz, $vf0xyz, $vf0xz
vadd.xyz $vf0xyz, $vf0xyz, $vf31xyzw
vadd.xyz $vf0xyz, $vf31xyzw, $vf0xyz
vaddx.yz $vf0yz, $vf0xyz, $vf0x
vaddz.xyzw $vf31xyzw, $vf0xyzw, $vf0x
vaddz.xyzw $vf31xyzw, $vf15xyzw, $vf7y
vaddz.xyzw $vf31xyzw, $vf31xyzw, $vf31w
vcallms -1
vcallms -0x0080
vcallms 0x1
vcallms 0x7
vcallms 0x4
vcallms 0x2
vcallms 0x40000
vcallms 0x40008
vclipw.xyz $vf0xyz, $vf0x
vclipw.xyz $vf0xyz, $vf31y
vclipw.xyz $vf1xyz, $vf2z
vdiv $Q, $vf0x, $vf0xy
vdiv $Q, $vf0xyzw, $vf31y
vdiv $Q, $vf1, $vf2z
vdiv $Q, $vf31x, $vf15
vdiv $0, $vf31w, $vf31y
vdiv $Q, $vf32y, $vf0w
vftoi0.w $vf0w, $vf0x
vftoi0.w $vf0x, $vf31w
vftoi0.w $vf1xw, $vf2w
vftoi0.w $vf31wx, $vf0w
vftoi0.w $vf31w, $vf15wz
vftoi12.xw $vf0xw, $vf0w
vftoi12.xw $vf0x, $vf31xw
vftoi15.xyz $vf31xyzw, $vf15xyz
vftoi15.xyz $vf31xyz, $vf31xyzw
vftoi15.xyzw $vf0xyzw, $vf0xyz
vftoi15.y $vf1y, $vf2x
vftoi15.y $vf31y, $vf0w
viaddi $vi0, $vi0, -17
viaddi $vi1, $vi2, 16
viaddi $vi31, $vi0, 17
viaddi $vi31, $vi15, 32
viaddi $vi31, $vi31, 31
viand $vi0xyzw, $vi0, $vi0
viand $vi0, $vi0xyzw, $vi31
viand $vi0, $vi31, $vi0xyzw
viand $vi1, $vi2, $vi3x
viand $vi31, $vi0y, $vi0
viand $vi31w, $vi15, $vi7
viand $vi31, $vi31, $vi31x
vilwr.w $vi0, ($vi0x)
vilwr.w $vi0, ($vi31y)
vilwr.w $vi1, ($vi2z)
vilwr.w $vi31, ($vi0w)
vilwr.w $vi31, ($vi15xyzw)
vilwr.w $vi31x, ($vi31)
vilwr.x $vi0y, ($vi0)
vilwr.x $vi0z, ($vi31)
vilwr.x $vi1w, ($vi2)
vilwr.x $vi31xyzw, ($vi0)
vilwr.x $vi31xy, ($vi15)
vilwr.x $vi31zw, ($vi31)
vilwr.y $vi0wx, ($vi0)
vilwr.y $vi0xyzw, ($vi31)
vilwr.y $vi1y, ($vi2)
vilwr.y $vi31, ($vi0y)
vilwr.z $vi0z, ($vi0)
vilwr.z $vi0, ($vi31z)
vior $vi0x, $vi0, $vi0
vior $vi0, $vi0x, $vi31
vior $vi0, $vi31, $vi0x
vior $vi1y, $vi2, $vi3
vior $vi31, $vi0y, $vi0
vior $vi31, $vi15, $vi7y
vior $vi31xyzw, $vi31, $vi31
visub $vi0x, $vi0, $vi0
visub $vi0, $vi0y, $vi31
visub $vi0, $vi31, $vi0z
visub $vi1w, $vi2, $vi3
visub $vi31, $vi0xy, $vi0
visub $vi31, $vi15, $vi7zw
visub $vi31, $vi31, $vi31w
viswr.w $vi0, ($vi0w)
viswr.w $vi0w, ($vi31)
viswr.x $vi0x, ($vi31)
viswr.x $vi1, ($vi2x)
viswr.x $vi31x, ($vi0x)
viswr.y $vi31y, ($vi15)
viswr.y $vi31, ($vi31y)
viswr.z $vi0, ($vi0z)
viswr.z $vi0z, ($vi31)
viswr.z $vi1z, ($vi2z)
vitof0.w $vf1w, $vf2x
vitof0.w $vf31z, $vf0w
vitof0.xw $vf0xw, $vf0xyw
vitof0.xw $vf0xw, $vf31w
vitof12.xw $vf31xw, $vf0x
vitof12.xzw $vf0xzw, $vf31xz
vitof12.xzw $vf1xzw, $vf2xw
vitof12.xzw $vf31xzw, $vf0xyzw
vitof12.xzw $vf31xyzw, $vf15xzw
vitof12.xzw $vf31xw, $vf31xzw
vitof12.y $vf0y, $vf0w
vitof12.y $vf0x, $vf31y
vitof15.xyw $vf0xyw, $vf31xw
vitof15.xyw $vf1xyw, $vf2yxw
vitof15.xyw $vf31xwy, $vf15xyw
vitof15.xyzw $vf1.xyzw, $vf2xyzw
vitof15.xyzw $vf31xyzw, $vf0.xyzw
vitof4.xw $vf31xw, $31xw
vitof4.xy $0xy, $vf0xy
vitof4.xyzw $vf0yzw, $vf0xyzw
vitof4.yzw $vf1yzw, $vf2yw
vlqd.w $vf0, (--$vi0w)
vlqd.w $vf0, (--$vi31w)
vlqd.w $vf0x, (--$vi0)
vlqd.x $vf0w, (--$vi0x)
vlqd.x $vf0x, (--$vi31x)
vlqd.x $vf0w, (--$vi0)
vlqd.xw $vf0, (--$vi0xw)
vlqd.xy $vf0, (--$vi0xy)
vlqd.xyw $vf0, (--$vi0xyw)
vlqd.xyz $vf0, (--$vi0xyz)
vlqd.xyzw $vf0, (--$vi0xyzw)
vlqd.xz $vf0, (--$vi0xz)
vlqd.xzw $vf0, (--$vi0xzw)
vlqd.y $vf0, (--$vi0y)
vlqd.yw $vf0, (--$vi0yw)
vlqd.yz $vf0, (--$vi0yz)
vlqd.yzw $vf0, (--$vi0yzw)
vlqd.z $vf0, (--$vi0z)
vlqd.zw $vf0, (--$vi0zw)
vlqi.w $vf0, ($vi0w++)
vlqi.x $vf31, ($vi15x++)
vlqi.xw $vf0x, ($vi0++)
vlqi.xw $vf0, ($vi31xw++)
vlqi.xy $vf0, ($vi0xy++)
vlqi.xy $vf1, ($2xy++)
vlqi.xyw $vf0, ($vi0xyw++)
vlqi.xyz $vf0, ($vi0xyz++)
vlqi.xyzw $vf0, ($vi0xyzw++)
vlqi.xz $vf0, ($vi0xz++)
vlqi.xzw $vf0, ($vi0xzw++)
vlqi.y $vf0, ($vi0y++)
vlqi.yw $vf0, ($vi0yw++)
vlqi.yz $vf0yz, ($vi0yz++)
vlqi.yzw $vf0, ($vi0yzw++)
vlqi.z $vf0, ($vi0z++)
vlqi.zw $vf0, ($vi0zw++)
vmaddai.w $ACCw, $vf0w, $R
vmaddai.w $ACCw, $vf1w, $Iw
vmaddai.w $ACCw, $vf31w, $Q
vmaddai.x $ACCx, $vf0x, $ACC
vmaddai.x $ACCy, $vf1w, $I
vmaddai.x $ACCxy, $vf31x, $I
vmaddai.xw $ACCxw, $vf0xyw, $I
vmaddai.xy $ACCxy, $vf0xyw, $I
vmaddai.xy $ACCxy, $vf1xyz, $I
vmaddai.xy $ACCxyz, $vf31xy, $I
vmaddai.xyw $ACCxy, $vf0xyw, $I
vmaddai.yw $ACCyw, $vf1w, $I
vmaddai.yw $ACCyw, $vf31y, $I
vmaddai.yz $ACCyz, $vf0yz, $R
vmaddaq.xyz $ACCxyz, $vf0xyz, $R
vmaddaq.xyz $ACCxyz, $vf1xyz, $Qxyz
vmaddaq.xzw $ACCxzw, $vf31xzw, $Qxzw
vmaddaq.y $ACCy, $vf0y, $R
vmaddaq.y $ACCy, $vf1y, $ACCy
vmaddaq.y $ACCy, $vf31y, $ACC
vmaddaw.z $ACCz, $vf31z, $vf0x
vmaddaw.zw $ACCzw, $vf31zw, $vf15y
vmaddax.w $ACCw, $vf1w, $vf2w
vmadda.xw $ACCxw, $vf31xw, $vf31wx
vmaddax.xyz $ACCxyz, $vf0xyz, $vf0xyz
vmaddax.xyzw $ACCxyzw, $vf0xyzw, $vf0xyzw
vmaddax.xz $ACCxz, $vf0xz, $vf31xz
vmaddax.xzw $ACCxzw, $vf0xzw, $vf0xzw
vmaddax.z $ACCz, $vf31z, $vf15z
vmaddax.zw $ACCzw, $vf1zw, $vf2zw
vmadday.w $ACCw, $vf1w, $vf2w
vmadday.w $ACCw, $vf31y, $vf0y
vmadday.w $ACCy, $vf31w, $vf15y
vmadday.w $ACCy, $vf31y, $vf31y
vmadday.xyzw $ACCxyzw, $vf0xyzw, $vf0xyzw
vmadday.xyzw $ACCxyzw, $vf0y, $vf31y
vmadday.xyzw $ACCy, $vf1xyzw, $vf2y
vmadday.xyzw $ACCy, $vf31y, $vf0y
vmaddi.x $vf0x, $vf31x, $Ix
vmaddi.xw $vf1xw, $vf2xw, $Ixw
vmaddi.xy $vf31xy, $vf0xy, $Ixy
vmaddi.xyw $vf0xyw, $vf0xyw, $Ixyw
vmaddi.xyzw $vf1xyzw, $vf2xyzw, $Ixyzw
vmaddi.y $vf0y, $vf0y, $Iy
vmaddi.yw $vf0yw, $vf0yw, $Iyw
vmaddi.zw $vf0zw, $vf31zw, $0
vmaddq.w $vf0w, $vf0w, $0
vmadd.w $vf0w, $vf0w, $vf0y
vmaddw.xyz $vf31xyz, $vf15xyz
vmaddw.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
vmaddx.yw $vf1yw, $vf2yw, $vf3yw
vmaddy.xy $vf31xy, $vf15xy, $vf7xy
vmadd.z $vf1z, $vf2z, $vf3x
vmadd.z $vf31z, $vf0z, $vf0w
vmaddz.xyw $vf0xyw, $vf0xyw, $vf31x
vmaddz.xz $vf0xz, $vf31xz, $vf0xz
vmaddz.y $vf31y, $vf0y, $vf0y
vmaxi.w $vf31w, $vf15w, $Q
vmaxi.w $vf31w, $vf31w, $0
vmax.w $vf31w, $vf31w, $vf31x
vmaxw.w $vf0w, $vf0w, $vf0x
vmaxw.x $vf0x, $vf0x, $vf0x
vmaxw.x $vf0w, $vf0w, $vf31w
vmaxw.xw $vf0xw, $vf0xw, $vf0xw
vmaxw.xw $vf0w, $vf0w, $vf31w
vmaxw.xy $vf0xy, $vf31xy, $vf0xy
vmaxw.xy $vf1xy, $vf2w, $vf3w
vmaxw.xy $vf31w, $vf0xy, $vf0w
vmax.x $vf0x, $vf0x, $vf31w
vmaxx.w $vf0w, $vf0w, $vf31w
vmaxx.w $vf0x, $vf31x, $vf0x
vmaxx.w $vf31w, $vf0w, $vf0w
vmaxx.w $vf31x, $vf15x, $vf7x
vmax.xw $vf31xw, $vf15xw, $vf7w
vmaxx.x $vf0x, $vf0x, $vf0w
vmaxx.x $vf31w, $vf15x, $vf7x
vmaxx.x $vf31x, $vf31w, $vf31x
vmaxx.xw $vf31xw, $vf15xw, $vf7xw
vmaxx.xy $vf0xy, $vf31xy, $vf0xy
vmaxx.xyw $vf0xyw, $vf0xyw, $vf0xyw
vmaxx.xyz $vf0xyz, $vf0xyz, $vf0xyz
vmaxx.xyzw $vf0xyzw, $vf0xyzw, $vf0xyzw
vmaxx.xyzw $vf0xyzw, $vf0x, $vf31x
vmaxx.xyzw $vf0x, $vf31xyzw, $vf0x
vmaxx.xyzw $vf1x, $vf2x, $vf3x
vmaxx.xzw $vf31xzw, $vf15xzw, $vf7xzw
vmaxx.y $vf0y, $vf0y, $vf0y
vmaxx.y $vf0y, $vf0x, $vf31x
vmaxx.y $vf0x, $vf31y, $vf0x
vmaxx.yw $vf1yw, $vf2yw, $vf3yw
vmaxx.yz $vf0yz, $vf0yz, $vf0yz
vmaxx.yz $vf0x, $vf0x, $vf31x
vmaxx.z $vf31z, $vf0z, $vf0z
vmaxx.z $vf31z, $vf15x, $vf7x
vmaxx.z $vf31x, $vf31z, $vf31x
vmaxx.zw $vf1zw, $vf2zw, $vf3zw
vmax.y $vf0y, $vf0y, $vf31x
vmax.yw $vf0yw, $vf0yw, $vf31w
vmax.yw $vf0yw, $vf31yw, $vf0y
vmaxy.xz $vf31xz, $vf15xz, $vf7xz
vmaxy.xzw $vf1xzw, $vf2xzw, $vf3xzw
vmaxy.y $vf1y, $vf2y
vmaxy.yz $vf0yz, $vf31yz, $vf0yz
vmaxy.yzw $vf0yzw, $vf0yzw, $vf0yzw
vmaxy.yzw $vf31y, $vf15y, $vf7y
vmaxy.yzw $vf31yzw, $vf31yw, $vf31y
vmaxy.z $vf0z, $vf0z, $vf0z
vmaxy.z $vf0z, $vf0y, $vf31y
vmaxy.z $vf0y, $vf31z, $vf0y
vmaxz.xw $vf31xw, $vf31xw, $vf31xw
vmaxz.xy $vf0xy, $vf0xy, $vf0xy
vmaxz.xyw $vf0xyw, $vf0xyw, $vf0xyw
vmaxz.xyz $vf1xyz, $vf2xyz, $vf3xyz
vmaxz.xyz $vf31xyz, $vf0z, $vf0z
vmaxz.xyz $vf31z, $vf15xyz, $vf7z
vmaxz.xyz $vf31z, $vf31z, $vf31z
vmaxz.xyzw $vf0xyzw, $vf0xyzw, $vf0xyzw
vmaxz.xyzw $vf0xyzw, $vf0z, $vf31z
vmaxz.xyzw $vf0z, $vf31z, $vf0z
vmaxz.xyzw $vf1xyzw, $vf2xyzw, $vfz
vmaxz.xyzw $vf31xyzw, $vf0xyzw, $vf0xyzw
vmaxz.xz $vf0xz, $vf0xz, $vf0xz
vmaxz.y $vf31y, $vf15z, $vf7z
vmaxz.y $vf31y, $vf31y, $vf31y
vmaxz.yw $vf0yw, $vf0yw, $vf0yw
vmaxz.yzw $vf0yzw, $vf0yzw, $vf31yzw
vmaxz.yzw $vf0yzw, $vf31z, $vf0z
vmaxz.yzw $vf1z, $vf2yzw, $vf3z
vmaxz.yzw $vf31z, $vf0z, $vf0z
vmaxz.z $vf31z, $vf31z, $vf31x
vmfir.w $vf0w, $vi0w
vmfir.w $vf0, $vi31w
vmfir.x $vf0x, $vi0x
vmfir.x $vf0, $vi31x
vmfir.xw $vf0xw, $vi31xw
vmfir.xy $vf1xy, $vi2xy
vmfir.xy $vf31, $vi0xy
vmfir.xyw $vf0xyw, $vi31xyw
vmfir.xyw $vf31xyw, $vi0x
vmfir.xyz $vf0xyz, $vi0xyz
vmfir.xyzw $vf1xyzw, $vi2xyzw
vmfir.xz $vf0xz, $vi31xz
vmfir.xzw $vf0xzw, $vi31xzw
vmfir.y $vf0y, $vi0y
vmfir.yw $vf0yw, $vi0yw
vmfir.yz $vf0yz, $vi31yz
vmfir.yzw $vf0yzw, $vi0yzw
vmfir.z $vf0z, $vi0z
vmfir.z $0z, $vi31
vmfir.zw $vf0zw, $vi0zw
vminii.w $vf0w, $vf0w, $Iw
vminii.w $vf0w, $vf31x, $I
vminii.w $vf1x, $vf2w, $I
vminii.xw $vf0xw, $vf31xw, $Ixw
vminii.xw $vf1xw, $vf2w, $I
vminii.xw $vf31x, $vf0xw, $I
vminii.xyw $vf31xw, $vf0xyw, $I
vminii.xyz $vf0xy, $vf0xyz, $I
minii.xz $vf31z, $vf15xz, $I
vminii.xz $vf31xz, $vf31x, $I
vminii.xzw $vf0xzw, $vf0xw, $I
vminii.xzw $vf0zw, $vf31xzw, $I
vminii.xzw $vf1xyzw, $vf2xzw, $I
vminii.xzw $vf31xzw, $vf0xyzw, $I
vminii.yw $vf31yw, $vf31yw, $R
vminii.yz $vf0yz, $vf0yz, $Q
vminii.yz $vf0yz, $vf31yz, $ACC
vminii.yzw $vf31yzw, $vf0yzw, $R
vminii.yzw $vf31yzw, $vf15yzw, $ACC
vminii.yzw $vf31yzw, $vf31yzw, $Q
vmini.w $vf0w, $vf0w, $vf0x
vminiw.w $vf31w, $vf31w, $vf31x
vminiw.x $vf0x, $vf0x, $vf0x
vminiw.x $vf0x, $vf0w, $vf31w
vminiw.x $vf0w, $vf31x, $vf0w
vminiw.x $vf1w, $vf2w, $vf3w
vminiw.xw $vf0xw, $vf31xw, $vf0xw
vminiw.xw $vf1w, $vf2w, $vf3w
vminiw.xyzw $vf0xyzw, $vf0xyzw, $vf0xyzw
vminiw.xyzw $vf0xyzw, $vf0xxyzw, $vf31w
vminiw.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
vminiw.xyzw $vf1xyzw, $vf2xyzw, $vf3ww
vminiw.xz $vf31xz, $vf0xz, $vf0xz
vminiw.yw $vf0yw, $vf0yw, $vf0yw
vminiw.yz $vf31yz, $vf0yz, $vf0yz
vminiw.z $vf31z, $vf0z, $vf0z
vminiw.z $vf31z, $vf15w, $vf7w
vminiw.z $vf31w, $vf31z, $vf31w
vminix.xw $vf0xw, $vf31xw, $vf0xw
vminix.xyw $vf0xyw, $vf0xyw, $vf0xyw
vminix.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
vminix.yw $vf31yw, $vf31yw, $vf31yw
vminix.zw $vf31zw, $vf31zw, $vf31zw
vmini.y $vf0y, $vf0x, $vf0y
vminiy.w $vf0w, $vf31w, $vf0w
vminiy.x $vf31x, $vf15x, $vf7x
vminiy.x $vf31x, $vf31y, $vf31y
vminiy.xw $vf0y, $vf0xw, $vf0y
vminiy.xw $vf0xw, $vf0y, $vf31y
vminiy.xw $vf0xw, $vf31xw, $vf0xw
vminiy.xyz $vf31xyz, $vf31xyz, $vf31xyz
vminiy.xyzw $vf0xyzw, $vf0y, $vf0y
vminiy.xyzw $vf0y, $vf0xyzw, $vf31y
vminiy.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
vminiy.yw $vf1yw, $vf2yw, $vf3yw
vminiy.zw $vf1zw, $vf2zw, $vf3zw
vmini.z $vf0z, $vf0z, $vf0x
vminiz.x $vf0x, $vf31x, $vf0x
vminiz.xw $vf0xw, $vf31xw, $vf0xw
vminiz.xyw $vf31xyw, $vf0xyw, $vf0xyw
vminiz.xyw $vf31xyw, $vf15z, $vf7z
vmove.xyw $vf0xyw, $vf0xw
vmove.y $vf0y, $vf31x
vmr32.xw $vf0xw, $vf0w
vmr32.xw $vf0w, $vf31xw
vmsubai.xy $ACCxy, $vf31xy, $Q
vmsubai.xyw $ACCxyw, $vf0xyw, $0
vmsubai.xyw $ACCxyw, $vf1xyw, $ACC
vmsubai.xyw $ACCxyw, $vf31xw, $I
vmsubaq.y $ACCy, $vf31y, $Qy
vmsubaq.yw $ACCw, $vf0yw, $Q
vmsubaq.yw $ACCwy, $vf1yw, $Q
vmsubaw.x $ACCx, $vf31x, $vf0x
vmsubaw.x $ACCx, $vf31w, $vf15w
vmsubaw.x $ACCw, $vf31x, $vf31w
vmsubaw.xw $ACCw, $vf0xw, $vf0w
vmsubaw.xw $ACCxw, $vf0w, $vf31w
vmsubaw.xw $ACCxw, $vf1xw, $vf2xw
vmsubax.yzw $ACCyzw, $vf0yzw, $vf31yzw
vmsubax.z $ACCz, $vf31z, $vf0z
vmsuba.y $ACCy, $vf31y, $vf15a
vmsuba.yw $ACCyw, $vf31yw, $vf0w
vmsubay.x $ACCx, $vf31x, $vf15x
vmsubay.x $ACCx, $vf31y, $vf31y
vmsubay.xw $ACCxw, $vf0xw, $vf0xw
vmsubaz.xy $ACCxy, $vf0xy, $vf31xy
vmsubaz.yw $ACCyw, $vf31yw, $vf0yw
vmsubi.xyzw $vf31xyzw, $vf0xyzw, $R
vmsubw.xyw $vf0xyw, $vf0xyw, $vf0xyw
vmsubw.xzw $vf0xzw, $vf0xzw, $vf31xzw
vmsubw.y $vf31y, $vf31y, $vf31y
vmsubw.yw $vf0yw, $vf0y, $vf0w
vmsubw.yw $vf0w, $vf0yw, $vf31w
vmsubw.zw $vf0zw, $vf0zw, $vf31zw
vmsubx.w $vf0w, $vf0w, $vf0w
vmsub.y $vf31y, $vf15y, $vf7w
vmsuby.x $vf0x, $vf0x, $vf31x
vmsuby.x $vf0x, $vf31y, $vf0y
vmsubz.x $vf0x, $vf31x, $vf0x
vmulai.xyz $ACCxyz, $vf1xz, $I
vmulaq.zw $ACCzw, $vf31zw, $I
vmula.w $ACCw, $vf31w, $vf0x
vmulax.xz $ACCxz, $vf0xz, $vf31xz
vmulax.xz $ACCxz, $vf1x, $vf2x
vmulax.xz $ACCx, $vf31xz, $vf0x
vmulay.yzw $ACCyzw, $vf0yzw, $vf31yzw
vmulaz.w $ACCw, $vf0w, $vf31w
mulaz.xy $ACCz, $vf31xy, $vf0z
vmulaz.xy $ACCxy, $vf31z, $vf15z
vmulaz.z $ACCz, $vf1z, $vf2x
vmuli.x $vf31x, $vf15x, $ACC
vmulq.x $vf0x, $vf31x, $0
vmulq.x $vf1x, $vf2x, $ACC
vmulq.x $vf31x, $vf0x, $R
vmulq.x $vf31x, $vf15x, $I
vmulw.z $vf31z, $vf15z, $vf7z
vmulw.z $vf31z, $vf31w, $vf31w
vmulw.zw $vf0zw, $vf0zw, $vf0zw
vmuly.xyzw $vf0xyzw, $vf0y, $vf31y
vmuly.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
vmuly.xyzw $vf1xyzw, $vf2y, $vf3y
vmuly.xyzw $vf31y, $vf0xyzw, $vf0y
vmulz.y $vf0y, $vf31y, $vf0y
vmulz.y $vf1y, $vf2z, $vf3z
vmulz.y $vf31z, $vf0y, $vf0z
vmulz.y $vf31z, $vf15z, $vf7z
vopmsub $vf0x, $vf0, $vf31
vopmsub $vf0, $vf31x, $vf0
vopmsub $vf1, $vf2, $vf3x
vopmsub $ACC, $vf0, $vf0
vopmsub $vf31, $R, $vf7
vopmsub $vf31, $vf31, $I
vopmsub.xyz $vf0xyz, $vf0xyz, $vf0xy
vopmula $0, $vf0, $vf0
vopmula $Q, $vf0, $vf31
vopmula $R, $vf1, $vf2
vopmula $I, $vf31, $vf0
vopmula $ACCx, $vf31, $vf15
vopmula $ACCxyzw, $vf31, $vf31
vopmula.xyz $ACCxyzw, $vf0xyz, $vf0xyz
vopmula.xyzw $ACCxyzw, $vf0xyzw, $vf31xyzw
vrget.w $vf0w, $0
vrget.w $vf1w, $I
vrget.w $vf31w, $Q
vrget.x $vf0x, $ACC
vrget.x $vf1y, $R
vrget.xy $vf31x, $R
vrget.xyw $vf0xw, $R
vrget.xyw $vf1yw, $R
vrget.xyw $vf31xy, $R
vrget.xyz $vf0xy, $R
vrget.xyz $vf1xyzw, $R
vrget.xyz $vf31xyzw, $R
vrget.xyzw $vf0xyz, $R
vrget.xyzw $vf1xzw, $R
vrget.xyzw $vf31yzw, $R
vrget.xz $vf0xz, $0
vrget.xz $vf1z, $R
vrget.xzw $vf0xw, $R
vrget.y $vf0z, $R
vrget.y $vf1y, $I
vrget.z $vf31z, $Q
vrget.zw $vf0zw, $ACC
vrnext.xyzw $vf0xyz, $R
vrnext.xyzw $vf1xyzw, $0
vrnext.xyzw $vf31xyzw, $Rxyzw
vrnext.yz $vf31yz, $Ryz
vrnext.z $vf0z, $Rz
vrsqrt $Q, $vf0xz, $vf31y
vrsqrt $Q, $vf1z, $vf2xz
vrsqrt $Q, $vf31yx, $vf15w
vrsqrt $Qx, $vf31x, $vf31y
vrsqrt $0, $vf31y, $vf0w
vrxor $0, $vf0w
vrxor $R, $vf0xy
vrxor $R, $vf0zw
vrxor $R, $vf1yz
vrxor $ACC, $vf31x
vrxor $Q, $vf31y
vsqd.w $vf0, (--$vi0w)
vsqd.w $vf0, (--$vi31w)
vsqd.x $vf1, (--$vi2x)
vsqd.xw $vf0, (--$vi0xw)
vsqd.xy $vf0, (--$vi0xy)
vsqd.xyw $vf0, (--$vi0xyw)
vsqd.xyz $vf0, (--$vi31xyz)
vsqd.xyzw $vf0, (--$vi0xyzw)
vsqd.xz $vf0, (--$vi31xz)
vsqd.xzw $vf0, (--$vi0xzw)
vsqd.y $vf0, (--$vi0y)
vsqd.yw $vf0, (--$vi31yw)
vsqd.yz $vf0, (--$vi31yz)
vsqd.yzw $vf0, (--$vi31yzw)
vsqd.yzw $vf0yzw, (--$vi0x)
vsqd.z $vf1, (--$vi2z)
vsqd.zw $vf1, (--$vi2zw)
vsqi.w $vf0, ($vi0w++)
vsqi.x $vf0x, ($vi0x++)
vsqi.xw $vf0xw, ($vi0xw++)
vsqi.xw $vf1x, ($vi2++)
vsqi.xw $vf31w, ($vi0++)
vsqi.xy $vf0, ($vi31xy++)
vsqi.xyw $vf0x, ($vi0++)
vsqi.xyw $vf0, ($vi31xyw++)
vsqi.xyz $vf0xyz, ($vi0xyz++)
vsqi.xyzw $vf0, ($vi31xyzw++)
vsqi.xz $vf0xz, ($vi0xz++)
vsqi.xzw $vf0xzw, ($vi0xzw++)
vsqi.y $vf1, ($vi2y++)
vsqi.yw $vf0yw, ($vi0yw++)
vsqi.yz $vf1, ($vi2yz++)
vsqi.yzw $vf0yzw, ($vi0yzw++)
vsqi.z $vf0, ($vi31z++)
vsqi.zw $vf0zw, ($vi0zw++)
vsqrt $Q, $vf1zw
vsqrt $Q, $vf31xw
vsqrt $Q, $vf31xy
vsubai.w $ACCw, $vf0w, $0
vsubai.w $ACCw, $vf1x, $I
vsubai.w $ACCx, $vf31w, $I
vsubai.x $ACCw, $vf31x, $I
vsubai.xw $ACCw, $vf0xw, $I
vsubai.xw $ACCxw, $vf1x, $I
vsubai.xw $ACCxw, $vf31xw, $0
vsubai.xy $ACCxy, $vf0y, $I
vsubai.xy $ACCxy, $vf1x, $I
vsubai.xy $ACCxy, $vf311xy, $I
vsubai.xyz $ACCxyz, $vf1yz, $I
vsubai.xyz $ACCxyz, $vf31xyz, $ACC
vsubai.xyzw $ACCxyzw, $vf0xyzw, $R
vsubai.xyzw $ACCxyzw, $vf1xyzw, $Q
vsubai.xz $ACCxz, $vf1z, $I
vsubai.y $ACCy, $vf31, $3
vsubai.yw $ACCyw, $vf0yw, $Iyw
vsubai.zw $ACCzw, $vf1zw, $Izw
vsubai.zw $ACCzw, $vf31w, $I
vsubaq.w $ACCw, $Q, $Q
vsubaq.w $ACCw, $I, $Q
vsubaq.xyw $ACCxyw, $vf0xw, $Q
vsubaq.xyzw $ACCxyzw, $vf0xyz, $Q
vsubaq.xzw $ACCxzw, $vf1xw, $Q
vsubaq.yw $ACCyw, $vf31y, $Q
vsubaq.yz $ACCyz, $vf0yz, $ACC
vsubaq.yz $ACCyz, $vf1yz, $I
vsubax.w $ACCw, $vf0w, $vf0w
vsubax.w $ACCw, $vf0x, $vf31x
vsubax.w $ACCx, $vf1w, $vf2x
vsubax.w $ACCx, $vf31x, $vf0x
vsubax.xyzw $ACCxyzw, $vf31xyzw, $vf0xyzw
vsubax.xzw $ACCxzw, $vf1xzw, $vf2xzw
vsubax.y $ACCy, $vf31y, $vf0y
vsubax.yw $ACCyw, $vf0yw, $vf0yw
vsubay.yw $ACCyw, $vf0yw, $vf31yw
vsubay.yzw $ACCyzw, $vf0yzw, $vf31yzw
vsubay.z $ACCz, $vf0z, $vf31z
vsubay.zw $ACCzw, $vf0zw, $vf0zw
vsubaz.w $ACCw, $vf31w, $vf15w
vsubaz.x $ACCx, $vf0x, $vf31x
vsubaz.xy $ACCxy, $vf0xy, $vf0xy
vsubaz.xz $ACCxz, $vf31xz, $vf15xz
vsubaz.xz $ACCxz, $vf31z, $vf31z
vsubaz.xzw $ACCxw, $vf0xzw, $vf0z
vsubaz.xzw $ACCz, $vf0xzw, $vf31z
vsubaz.xzw $ACCxzw, $vf1z, $vf2z
vsubaz.yw $ACCyw, $vf1yw, $vf2yw
vsubi.w $vf31w, $vf15w, $0
vsubi.w $vf31w, $vf31w, $R
vsubi.x $vf0x, $vf0y, $I
vsubi.x $vf0x, $vf31x, $Ix
vsubi.xy $vf0xy, $vf31y, $I
vsubi.xy $vf1x, $vf2xy, $I
vsubq.x $vf31x, $vf15x, $Qx
vsubq.x $vf31x, $vf31y, $Q
vsubq.xw $vf0xw, $vf0xw, $0
vsubq.xw $vf0xw, $vf31xw, $2
vsubq.xyzw $vf1yzw, $vf2xyzw, $Q
vsubq.yw $vf31w, $vf15yw, $Q
vsubq.yw $vf31yw, $vf31y, $Q
vsubx.xyw $vf0xyw, $vf31xyw, $vf0xyw
vsubx.xzw $vf1xzw, $vf2xzw, $vf3xzw
vsuby.xw $vf0xw, $vf0xw, $vf0xw
vsuby.zw $vf0zw, $vf0zw, $vf0zw
vsub.z $vf0z, $vf31z, $vf0x
vsubz.xyw $vf31yw, $vf15xyw, $vf7z
vsubz.xyw $vf31xyw, $vf31yw, $vf31z
vsubz.xyz $vf0xyz, $vf0xyz, $vf0x
vwaitq $vf0x
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,676
|
gas/testsuite/gas/mips/mips-abi32-pic.s
|
.sdata
shared: .word 11
.data
unshared:
.word 1
.word 2
.word 3
.word 4
.text
.ent func
func:
.frame $sp,0,$31
.set noreorder
.cpload $25 # 0000 lui gp,hi(_gp_disp)
# 0004 addiu gp,gp,lo(_gp_disp)
# 0008 addu gp,gp,t9
.set reorder
.cprestore 8 # 000c sw gp,8(sp)
.cpadd $4 # 0010 addu a0,a0,gp
li $4, 0x12345678 # 0014 lui a0,0x1234
# 0018 ori a0,a0,0x5678
la $4, shared # 001c lw a0,got(.sdata)(gp)
# 0020 nop
# 0024 addiu a0,a0,lo(shared)
la $4, unshared # 0028 lw a0,got(.data)(gp)
# 002c nop
# 0030 addiu a0,a0,lo(unshared)
la $4, end # 0034 lw a0,got(.text)(gp)
# 0038 nop
# 003c addiu a0,a0,lo(end)
j end # 0040 b end
# 0044 nop
jal end # 0048 lw t9,got(.text)(gp)
# 004c nop
# 0050 addiu t9,t9,lo(end)
# 0054 jalr t9
# 0058 nop
# 005c lw gp,8(sp)
lw $4, shared # 0060 lw a0,got(.sdata)(gp)
# 0064 nop
# 0068 addiu a0,a0,lo(shared)
# 006c lw a0,(a0)
lw $4, unshared # 0070 lw a0,got(.data)(gp)
# 0074 nop
# 0078 addiu a0,a0,lo(unshared)
# 007c lw a0,(a0)
lw $4, end # 0080 lw a0,got(.text)(gp)
# 0084 nop
# 0088 addiu a0,a0,lo(end)
# 008c lw a0,(a0)
ld $4, shared # 0090 lw at,got(.sdata)(gp)
# 0094 nop
# 0098 lw a0,lo(shared)(at)
# 009c lw a1,lo(shared)+4(at)
ld $4, unshared # 00a0 lw at,got(.data)(gp)
# 00a4 nop
# 00a8 lw a0,lo(unshared)(at)
# 00ac lw a1,lo(unshared)+4(at)
ld $4, end # 00b0 lw at,got(.text)(gp)
# 00b4 nop
# 00b8 lw a0,lo(end)(at)
# 00bc lw a1,lo(end)+4(at)
sw $4, shared # 00c0 lw at,got(.sdata)(gp)
# 00c4 nop
# 00c8 addiu at,at,lo(shared)
# 00cc sw a0,0(at)
sw $4, unshared # 00d0 lw at,got(.data)(gp)
# 00d4 nop
# 00d8 addiu at,at,lo(unshared)
# 00dc sw a0,0(at)
sd $4, shared # 00e0 lw at,got(.sdata)(gp)
# 00e4 nop
# 00e8 sw a0,lo(shared)(at)
# 00ec sw a1,lo(shared)+4(at)
sd $4, unshared # 00f0 lw at,got(.data)(gp)
# 00f4 nop
# 00f8 sw a0,lo(unshared)(at)
# 00fc sw a1,lo(unshared)+4(at)
ulh $4, unshared # 0100 lw at,got(.data)(gp)
# 0104 nop
# 0108 addiu at,at,lo(unshared)
# 010c lb a0,0(at)
# 0110 lbu at,1(at)
# 0114 sll a0,a0,8
# 0118 or a0,a0,at
ush $4, unshared # 011c lw at,got(.data)(gp)
# 0120 nop
# 0124 addiu at,at,lo(unshared)
# 0128 sb a0,0(at)
# 012c srl a0,a0,8
# 0130 sb a0,1(at)
# 0134 lbu at,0(at)
# 0138 sll a0,a0,8
# 013c or a0,a0,at
ulw $4, unshared # 0140 lw at,got(.data)(gp)
# 0144 nop
# 0148 addiu at,at,lo(unshared)
# 014c lwl a0,0(at)
# 0150 lwr a0,3(at)
usw $4, unshared # 0154 lw at,got(.data)(gp)
# 0158 nop
# 015c addiu at,at,lo(unshared)
# 0160 swl a0,0(at)
# 0164 swr a0,3(at)
li.d $4, 1.0 # 0168 lui a0,0x3ff0
# 016c move a1,zero
li.d $4, 1.9 # 0170 lw at,got(.rodata)(gp)
# 0174 lw a0,lo(F1.9)(at)
# 0178 lw a1,lo(F1.9)+4(at)
li.d $f0, 1.0 # 017c lui at,0x3ff0
# 0180 mtc1 at,$f1
# 0184 mtc1 zero,$f0
li.d $f0, 1.9 # 0188 lw at,got(.rodata)(gp)
# 018c ldc1 $f0,lo(L1.9)(at)
seq $4, $5, -100 # 0190 addiu a0,a1,100
# 0194 sltiu a0,a0,1
sne $4, $5, -100 # 0198 addiu a0,a1,100
# 019c sltu a0,zero,a0
move $4, $5 # 01a0 move a0,a1
# Not available in 32-bit mode
# dla $4, shared
# dla $4, unshared
# uld $4, unshared
# usd $4, unshared
# Should produce warnings given -mgp32
# bgt $4, 0x7fffffff, end
# bgtu $4, 0xffffffff, end
# ble $4, 0x7fffffff, end
# bleu $4, 0xffffffff, end
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
.end func
end:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,037
|
gas/testsuite/gas/mips/mips32r2.s
|
# source file to test assembly of mips32r2 *non-fp* instructions
.set noreorder
.set noat
.text
text_label:
# unprivileged CPU instructions
ehb
ext $4, $5, 6, 8
ins $4, $5, 6, 8
jalr.hb $8
jalr.hb $20, $9
jr.hb $8
# Note, further testing of rdhwr is done in hwr-names-mips32r2.d
rdhwr $10, $0
rdhwr $11, $1
rdhwr $12, $2
rdhwr $13, $3
rdhwr $14, $4
rdhwr $15, $5
# This file checks that in fact HW rotate will
# be used for this arch, and checks assembly
# of the official MIPS mnemonics. (Note that disassembly
# uses the traditional "ror" and "rorv" mnemonics.)
# Additional rotate tests are done by rol-hw.d.
rotl $25, $10, 4
rotr $25, $10, 4
rotl $25, $10, $4
rotr $25, $10, $4
rotrv $25, $10, $4
seb $7
seb $8, $10
seh $7
seh $8, $10
synci 0x5555($10)
wsbh $7
wsbh $8, $10
# cp0 instructions
di
di $0
di $10
ei
ei $0
ei $10
rdpgpr $10, $25
wrpgpr $10, $25
pause
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 4,367
|
gas/testsuite/gas/mips/mips-gp64-fp64-pic.s
|
.sdata
shared: .word 11
.data
unshared:
.word 1
.word 2
.word 3
.word 4
.text
.ent func
func:
.frame $sp,0,$31
.set noreorder
.cpload $25 # 0000 lui gp,hi(_gp_disp)
# 0004 addiu gp,gp,lo(_gp_disp)
# 0008 addu gp,gp,t9
.set reorder
.cprestore 8 # 000c sw gp,8(sp)
.cpadd $4 # 0010 addu a0,a0,gp
li $4, 0x12345678 # 0014 lui a0,0x1234
# 0018 ori a0,a0,0x5678
la $4, shared # 001c lw a0,got(.sdata)(gp)
# 0020 nop
# 0024 addiu a0,a0,lo(shared)
la $4, unshared # 0028 lw a0,got(.data)(gp)
# 002c nop
# 0030 addiu a0,a0,lo(unshared)
la $4, end # 0034 lw a0,got(.text)(gp)
# 0038 nop
# 003c addiu a0,a0,lo(end)
j end # 0040 b end
# 0044 nop
jal end # 0048 lw t9,got(.text)(gp)
# 004c nop
# 0050 addiu t9,t9,lo(end)
# 0054 jalr t9
# 0058 nop
# 005c lw gp,8(sp)
lw $4, shared # 0060 lw a0,got(.sdata)(gp)
# 0064 nop
# 0068 addiu a0,a0,lo(shared)
# 006c lw a0,(a0)
lw $4, unshared # 0070 lw a0,got(.data)(gp)
# 0074 nop
# 0078 addiu a0,a0,lo(unshared)
# 007c lw a0,(a0)
lw $4, end # 0080 lw a0,got(.text)(gp)
# 0084 nop
# 0088 addiu a0,a0,lo(end)
# 008c lw a0,(a0)
ld $4, shared # 0090 lw a0,got(.sdata)(gp)
# 0094 nop
# 0098 addiu a0,a0,lo(shared)
# 009c ld a0,(a0)
ld $4, unshared # 00a0 lw a0,got(.data)(gp)
# 00a4 nop
# 00a8 addiu a0,a0,lo(unshared)
# 00ac ld a0,(a0)
ld $4, end # 00b0 lw a0,got(.text)(gp)
# 00b4 nop
# 00b8 addiu a0,a0,lo(end)
# 00bc ld a0,(a0)
sw $4, shared # 00c0 lw at,got(.sdata)(gp)
# 00c4 nop
# 00c8 addiu at,at,lo(shared)
# 00cc sw a0,0(at)
sw $4, unshared # 00d0 lw at,got(.data)(gp)
# 00d4 nop
# 00d8 addiu at,at,lo(unshared)
# 00dc sw a0,0(at)
sd $4, shared # 00e0 lw at,got(.sdata)(gp)
# 00e4 nop
# 00e8 addiu at,at,lo(shared)
# 00ec sd a0,(at)
sd $4, unshared # 00f0 lw at,got(.data)(gp)
# 00f4 nop
# 00f8 addiu at,at,lo(unshared)
# 00fc sd a0,(at)
ulh $4, unshared # 0100 lw at,got(.data)(gp)
# 0104 nop
# 0108 addiu at,at,lo(unshared)
# 010c lb a0,0(at)
# 0110 lbu at,1(at)
# 0114 sll a0,a0,8
# 0118 or a0,a0,at
ush $4, unshared # 011c lw at,got(.data)(gp)
# 0120 nop
# 0124 addiu at,at,lo(unshared)
# 0128 sb a0,0(at)
# 012c srl a0,a0,8
# 0130 sb a0,1(at)
# 0134 lbu at,0(at)
# 0138 sll a0,a0,8
# 013c or a0,a0,at
ulw $4, unshared # 0140 lw at,got(.data)(gp)
# 0144 nop
# 0148 addiu at,at,lo(unshared)
# 014c lwl a0,0(at)
# 0150 lwr a0,3(at)
usw $4, unshared # 0154 lw at,got(.data)(gp)
# 0158 nop
# 015c addiu at,at,lo(unshared)
# 0160 swl a0,0(at)
# 0164 swr a0,3(at)
li.d $4, 1.0 # 0168 li a0,0xffc0
# 016c dsll32 a0,a0,14
li.d $4, 1.9 # 0170 lw at,got(.rodata)(gp)
# 0174 ld a0,lo(F1.9)(at)
li.d $f0, 1.0 # 0178 li at,0xffc0
# 017c dsll32 at,at,14
# 0180 dmtc1 at,$f0
li.d $f0, 1.9 # 0184 lw at,got(.rodata)(gp)
# 0188 ldc1 $f0,lo(L1.9)(at)
seq $4, $5, -100 # 018c daddiu a0,a1,100
# 0190 sltiu a0,a0,1
sne $4, $5, -100 # 0194 daddiu a0,a1,100
# 0198 sltu a0,zero,a0
move $4, $5 # 019c move a0,a1
dla $4, shared # 01a0 lw a0,got(.sdata)(gp)
# 01a4 nop
# 01a8 addiu a0,a0,lo(shared)
dla $4, unshared # 01ac lw a0,got(.data)(gp)
# 01b0 nop
# 01b4 addiu a0,a0,lo(unshared)
uld $4, unshared # 01b8 lw at,got(.data)(gp)
# 01bc nop
# 01c0 addiu at,at,lo(unshared)
# 01c4 ldl a0,0(at)
# 01c8 ldr a0,7(at)
usd $4, unshared # 01cc lw at,got(.data)(gp)
# 01d0 nop
# 01d4 addiu at,at,lo(unshared)
# 01d8 sdl a0,0(at)
# 01dc sdr a0,7(at)
bgt $4, 0x7fffffff, end # 01e0 li at,0x8000
# 01e4 dsll at,at,0x10
# 01e8 slt at,a0,at
# 01ec beqz at,end
# 01f0 nop
bgtu $4, 0xffffffff, end # 01f4 li at,0x8000
# 01f8 dsll at,at,17
# 01fc sltu at,a0,at
# 0200 beqz at,end
# 0204 nop
ble $4, 0x7fffffff, end # 0208 li at,0x8000
# 020c dsll at,at,0x10
# 0210 slt at,a0,at
# 0214 bnez at,end
# 0218 nop
bleu $4, 0xffffffff, end # 021c li at,0x8000
# 0220 dsll at,at,17
# 0224 sltu at,a0,at
# 0228 bnez at,end
# 022c nop
add.d $f1, $f2, $f3 # 0230 add.d $f1,$f2,$f3
.end func
end:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 6,017
|
gas/testsuite/gas/mips/r5900-full-vu0.s
|
.set noreorder
.set noat
.globl text_label .text
text_label:
# VU Macromode instruction set
vabs.xyzw $vf0xyzw,$vf31xyzw
vadd.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
vaddi.xyzw $vf10xyzw,$vf31xyzw,$I
vaddq.xyzw $vf10xyzw,$vf31xyzw,$Q
vaddw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
vaddx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
vaddy.xyzw $vf10xyzw,$vf31xyzw,$vf1y
vaddz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
vadda.xyzw $ACCxyzw,$vf0xyzw,$vf31xyzw
vaddai.xyzw $ACCxyzw,$vf31xyzw,$I
vaddaq.xyzw $ACCxyzw,$vf31xyzw,$Q
vaddaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
vaddax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
vadday.xyzw $ACCxyzw,$vf31xyzw,$vf1y
vaddaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
vcallms 0x0
vcallms 0x340
vcallms 0xff8
vcallmsr $vi27
vclipw.xyz $vf31xyz,$vf1w
vclipw $vf31xyz,$vf1w
vdiv $Q,$vf1y,$vf11x
vftoi0.xyzw $vf0xyzw,$vf31xyzw
vftoi4.xyzw $vf0xyzw,$vf31xyzw
vftoi12.xyzw $vf0xyzw,$vf31xyzw
vftoi15.xyzw $vf0xyzw,$vf31xyzw
viadd $vi1,$vi15,$vi0
viaddi $vi0,$vi15,-1
viand $vi1,$vi15,$vi0
vilwr.w $vi0,($vi15)
vilwr.x $vi0,($vi15)
vilwr.y $vi0,($vi15)
vilwr.z $vi0,($vi15)
vior $vi1,$vi15,$vi0
viswr.w $vi0,($vi15)
viswr.x $vi0,($vi15)
viswr.y $vi0,($vi15)
viswr.z $vi0,($vi15)
visub $vi1,$vi15,$vi0
vitof0.xyzw $vf0xyzw,$vf31xyzw
vitof4.xyzw $vf0xyzw,$vf31xyzw
vitof12.xyzw $vf0xyzw,$vf31xyzw
vitof15.xyzw $vf0xyzw,$vf31xyzw
vlqd.xyzw $vf0xyzw,(--$vi15)
vlqi.xyzw $vf0xyzw,($vi15++)
vmadd.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
vmaddi.xyzw $vf10xyzw,$vf31xyzw,$I
vmaddq.xyzw $vf10xyzw,$vf31xyzw,$Q
vmaddw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
vmaddx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
vmaddy.xyzw $vf10xyzw,$vf31xyzw,$vf1y
vmaddz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
vmaddz $vf6, $vf3, $vf5
vmadda.xyzw $ACCxyzw,$vf31xyzw,$vf0xyzw
vmaddai.xyzw $ACCxyzw,$vf31xyzw,$I
vmaddaq.xyzw $ACCxyzw,$vf31xyzw,$Q
vmaddaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
vmaddax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
vmaddax $ACC, $vf1, $vf5
vmadday.xyzw $ACCxyzw,$vf31xyzw,$vf1y
vmadday $ACC, $vf2, $vf5
vmaddaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
vmax.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
vmaxi.xyzw $vf10xyzw,$vf31xyzw,$I
vmaxw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
vmaxx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
vmaxy.xyzw $vf10xyzw,$vf31xyzw,$vf1y
vmaxz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
vmfir.xyzw $vf0xyzw,$vi15
vmini.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
vminii.xyzw $vf10xyzw,$vf31xyzw,$I
vminiw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
vminix.xyzw $vf10xyzw,$vf31xyzw,$vf1x
vminiy.xyzw $vf10xyzw,$vf31xyzw,$vf1y
vminiz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
vmove.xyzw $vf0xyzw,$vf31xyzw
vmr32.xyzw $vf0xyzw,$vf31xyzw
vmsub.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
vmsubi.xyzw $vf10xyzw,$vf31xyzw,$I
vmsubq.xyzw $vf10xyzw,$vf31xyzw,$Q
vmsubw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
vmsubx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
vmsuby.xyzw $vf10xyzw,$vf31xyzw,$vf1y
vmsubz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
vmsuba.xyzw $ACCxyzw,$vf0xyzw,$vf31xyzw
vmsubai.xyzw $ACCxyzw,$vf31xyzw,$I
vmsubaq.xyzw $ACCxyzw,$vf31xyzw,$Q
vmsubaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
vmsubax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
vmsubay.xyzw $ACCxyzw,$vf31xyzw,$vf1y
vmsubaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
vmtir $vi0,$vf1z
vmul.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
vmuli.xyzw $vf10xyzw,$vf31xyzw,$I
vmulq.xyzw $vf10xyzw,$vf31xyzw,$Q
vmulw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
vmulx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
vmuly.xyzw $vf10xyzw,$vf31xyzw,$vf1y
vmulz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
vmula.xyzw $ACCxyzw,$vf31xyzw,$vf0xyzw
vmulai.xyzw $ACCxyzw,$vf31xyzw,$I
vmulaq.xyzw $ACCxyzw,$vf31xyzw,$Q
vmulaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
vmulaw $ACC, $vf4, $vf0
vmulax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
vmulay.xyzw $ACCxyzw,$vf31xyzw,$vf1y
vmulaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
vnop
vopmula.xyz $ACCxyz,$vf31xyz,$vf0xyz
vopmsub.xyz $vf10xyz,$vf31xyz,$vf0xyz
vrget.xyzw $vf0xyzw,$R
vrinit $R,$vf1w
vrnext.xyzw $vf0xyzw,$R
vrsqrt $Q,$vf1w,$vf11x
vrxor $R,$vf1x
vsqd.xyzw $vf31xyzw,(--$vi0)
vsqi.xyzw $vf31xyzw,($vi0++)
vsqrt $Q,$vf11z
vsub.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
vsubi.xyzw $vf10xyzw,$vf31xyzw,$I
vsubq.xyzw $vf10xyzw,$vf31xyzw,$Q
vsubw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
vsubx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
vsuby.xyzw $vf10xyzw,$vf31xyzw,$vf1y
vsubz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
vsuba.xyzw $ACCxyzw,$vf31xyzw,$vf0xyzw
vsubai.xyzw $ACCxyzw,$vf31xyzw,$I
vsubaq.xyzw $ACCxyzw,$vf31xyzw,$Q
vsubaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
vsubax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
vsubay.xyzw $ACCxyzw,$vf31xyzw,$vf1y
vsubaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
vwaitq
# Implicit suffixes
vadd.xyzw $vf10,$vf31,$vf0
vadd.xy $vf10,$vf31,$vf0
vadd.xyzw $vf10,$vf31,$vf0
vlqi.xy $vf0,($vi15++)
# VU floating point registers
vadd.xyzw $vf0,$vf1,$vf2
vadd.xyzw $vf3,$vf4,$vf5
vadd.xyzw $vf6,$vf7,$vf8
vadd.xyzw $vf9,$vf10,$vf11
vadd.xyzw $vf12,$vf13,$vf14
vadd.xyzw $vf15,$vf16,$vf17
vadd.xyzw $vf18,$vf19,$vf20
vadd.xyzw $vf21,$vf22,$vf23
vadd.xyzw $vf24,$vf25,$vf26
vadd.xyzw $vf27,$vf28,$vf29
vadd.xyzw $vf30,$vf31,$vf0
# VU integer registers
viadd $vi0,$vi1,$vi2
viadd $vi3,$vi4,$vi5
viadd $vi6,$vi7,$vi8
viadd $vi9,$vi10,$vi11
viadd $vi12,$vi13,$vi14
viadd $vi15,$vi16,$vi17
viadd $vi18,$vi19,$vi20
viadd $vi21,$vi22,$vi23
viadd $vi24,$vi25,$vi26
viadd $vi27,$vi28,$vi29
viadd $vi30,$vi31,$vi0
# Floating point transfer to VU
lqc2 $0,0($0)
lqc2 $1, 0x7fff($1)
lqc2 $8, -0x8000($8)
lqc2 $31, -1($31)
# Floating point transfer from VU
sqc2 $0,0($0)
sqc2 $1, 0x7fff($1)
sqc2 $8, -0x8000($8)
sqc2 $31, -1($31)
# Integer transfer from VU
cfc2 $0,$0
cfc2 $0,$31
cfc2.i $0,$0
cfc2.i $0,$31
cfc2.ni $0,$0
cfc2.ni $0,$31
# Integer transfer to VU
ctc2 $0,$0
ctc2 $0,$31
ctc2.i $0,$0
ctc2.i $0,$31
ctc2.ni $0,$0
ctc2.ni $0,$31
# Floating point transfer from VU
qmfc2 $0,$0
qmfc2 $0,$31
qmfc2.i $0,$0
qmfc2.i $0,$31
qmfc2.ni $0,$0
qmfc2.ni $0,$31
# Floating point transfer to VU
qmtc2 $0,$0
qmtc2 $0,$31
qmtc2.i $0,$0
qmtc2.i $0,$31
qmtc2.ni $0,$0
qmtc2.ni $0,$31
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,338
|
gas/testsuite/gas/mips/r6-64.s
|
.text
dmul $2,$3,$4
dmuh $2,$3,$4
ddiv $2,$3,$4
dmulu $2,$3,$4
dmuhu $2,$3,$4
dmod $2,$3,$4
ddivu $2,$3,$4
dmodu $2,$3,$4
dlsa $2,$3,$4,1
dlsa $2,$3,$4,4
dclz $2,$3
dclo $2,$3
lld $2,-256($3)
lld $2,255($3)
scd $2,-256($3)
scd $2,255($3)
dalign $4, $2, $3, 0
dalign $4, $2, $3, 1
dalign $4, $2, $3, 2
dalign $4, $2, $3, 3
dalign $4, $2, $3, 4
dalign $4, $2, $3, 5
dalign $4, $2, $3, 6
dalign $4, $2, $3, 7
dbitswap $4, $2
daui $3, $2, 0xffff
dahi $3, $3, 0xffff
dati $3, $3, 0xffff
lwupc $4, 1f
lwupc $4, .+(-262144 << 2)
lwupc $4, .+(262143 << 2)
lwu $4, (-262144 << 2)($pc)
lwu $4, (262143 << 2)($pc)
ldpc $4, 1f
ldpc $4, 1f
.align 3
3:
ldpc $4, 3b+(-131072 << 3)
ldpc $4, 3b+(-131072 << 3)
.align 3
3:
ldpc $4, 3b+(131071 << 3)
ldpc $4, 3b+(131071 << 3)
ld $4, (-131072 << 3)($pc)
ld $4, (-131072 << 3)($pc)
ld $4, (131071 << 3)($pc)
ld $4, (131071 << 3)($pc)
.align 3
1:
lldp $5, $4, $6
scdp $5, $4, $6
nop
nop
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,146
|
gas/testsuite/gas/mips/mips16-relax-unextended-2.s
|
.module mips3
.set mips16
.set noautoextend
foo:
# Operand code:
sll $2, $3, 17 # <
sll $2, $3, bar
dsll $4, $5, 17 # [
dsll $4, $5, bar
dsrl $6, 17 # ]
dsrl $6, bar
lb $4, 0x1234($5) # 5
lb $4, bar($5)
lb $4, %hi(baz)($5)
slti $6, 0x5678 # 8
slti $6, bar
la $2, . + 0x1234 # A
la $2, . + bar
ld $3, . + 0x5678 # B
ld $3, . + bar
sd $31, 0x5678($29) # C
sd $31, bar($29)
sd $31, %lo(baz)($29)
sd $4, 0x5678($29) # D
sd $4, bar($29)
sd $4, %lo(baz)($29)
dla $5, . + 0x5678 # E
dla $5, . + bar
daddiu $2, $3, 0x5678 # F
daddiu $2, $3, bar
lh $6, 0x1234($7) # H
lh $6, bar($7)
lh $6, %lo(baz)($7)
addiu $29, 0x5678 # K
addiu $29, bar
addiu $29, %lo(baz)
cmpi $2, 0x1234 # U
cmpi $2, bar
cmpi $2, %hi(baz)
addiu $3, $pc, 0x5678 # V
addiu $3, $pc, bar
addiu $3, $pc, %lo(baz)
daddiu $4, $pc, 0x5678 # W
daddiu $4, $pc, bar
daddiu $4, $pc, %lo(baz)
daddiu $5, 0x5678 # j
daddiu $5, bar
daddiu $5, %lo(baz)
addiu $6, 0x1234 # k
addiu $6, bar
addiu $2, %lo(baz)
beqz $7, . + 0x5678 # p
b . + 0x1234 # q
.set bar, 0x5678
|
tactcomplabs/xbgas-binutils-gdb
| 1,127
|
gas/testsuite/gas/mips/cp1-names.s
|
# source file to test objdump's disassembly using various styles of
# CP1 register names.
.set noreorder
.set noat
.globl text_label .text
text_label:
ctc1 $0, $0
ctc1 $0, $1
ctc1 $0, $2
ctc1 $0, $3
ctc1 $0, $4
ctc1 $0, $5
ctc1 $0, $6
ctc1 $0, $7
ctc1 $0, $8
ctc1 $0, $9
ctc1 $0, $10
ctc1 $0, $11
ctc1 $0, $12
ctc1 $0, $13
ctc1 $0, $14
ctc1 $0, $15
ctc1 $0, $16
ctc1 $0, $17
ctc1 $0, $18
ctc1 $0, $19
ctc1 $0, $20
ctc1 $0, $21
ctc1 $0, $22
ctc1 $0, $23
ctc1 $0, $24
ctc1 $0, $25
ctc1 $0, $26
ctc1 $0, $27
ctc1 $0, $28
ctc1 $0, $29
ctc1 $0, $30
ctc1 $0, $31
cfc1 $0, $0
cfc1 $0, $1
cfc1 $0, $2
cfc1 $0, $3
cfc1 $0, $4
cfc1 $0, $5
cfc1 $0, $6
cfc1 $0, $7
cfc1 $0, $8
cfc1 $0, $9
cfc1 $0, $10
cfc1 $0, $11
cfc1 $0, $12
cfc1 $0, $13
cfc1 $0, $14
cfc1 $0, $15
cfc1 $0, $16
cfc1 $0, $17
cfc1 $0, $18
cfc1 $0, $19
cfc1 $0, $20
cfc1 $0, $21
cfc1 $0, $22
cfc1 $0, $23
cfc1 $0, $24
cfc1 $0, $25
cfc1 $0, $26
cfc1 $0, $27
cfc1 $0, $28
cfc1 $0, $29
cfc1 $0, $30
cfc1 $0, $31
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,278
|
gas/testsuite/gas/mips/mips32r2-ill-fp64.s
|
# source file to test illegal mips32r2 instructions
.set noreorder
.set noat
.text
text_label:
# insert and extract position/size checks:
# ext constraint: 0 <= pos < 32
ext $4, $5, -1, 1 # error
ext $4, $5, 0, 1
ext $4, $5, 31, 1
ext $4, $5, 32, 1 # error
# ext constraint: 0 < size <= 32
ext $4, $5, 0, 0 # error
ext $4, $5, 0, 1
ext $4, $5, 0, 32
ext $4, $5, 0, 33 # error
# ext constraint: 0 < (pos+size) <= 32
ext $4, $5, 0, 0 # error
ext $4, $5, 0, 1
ext $4, $5, 31, 1
ext $4, $5, 31, 2 # error
# ins constraint: 0 <= pos < 32
ins $4, $5, -1, 1 # error
ins $4, $5, 0, 1
ins $4, $5, 31, 1
ins $4, $5, 32, 1 # error
# ins constraint: 0 < size <= 32
ins $4, $5, 0, 0 # error
ins $4, $5, 0, 1
ins $4, $5, 0, 32
ins $4, $5, 0, 33 # error
# ins constraint: 0 < (pos+size) <= 32
ins $4, $5, 0, 0 # error
ins $4, $5, 0, 1
ins $4, $5, 31, 1
ins $4, $5, 31, 2 # error
# FP register checks.
#
# Even registers are supported w/ 32-bit FPU, odd
# registers supported only for 64-bit FPU.
# This file tests 64-bit FPU.
mfhc1 $17, $f0
mfhc1 $17, $f1
mthc1 $17, $f0
mthc1 $17, $f1
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,241
|
gas/testsuite/gas/mips/mips16e2.s
|
.set mips16
.macro mem9pos op, ri, base
\op \ri,0(\base)
\op \ri,1(\base)
\op \ri,2(\base)
\op \ri,3(\base)
\op \ri,4(\base)
\op \ri,8(\base)
\op \ri,16(\base)
\op \ri,32(\base)
\op \ri,64(\base)
\op \ri,128(\base)
\op \ri,255(\base)
.endm
.macro mem9neg op, ri, base
\op \ri,-1(\base)
\op \ri,-2(\base)
\op \ri,-3(\base)
\op \ri,-4(\base)
\op \ri,-8(\base)
\op \ri,-16(\base)
\op \ri,-32(\base)
\op \ri,-64(\base)
\op \ri,-128(\base)
\op \ri,-256(\base)
.endm
.macro mem9 op, ri, base
mem9pos \op, \ri, \base
mem9neg \op, \ri, \base
.endm
.macro mem op, ri, base
mem9pos \op, \ri, \base
\op \ri,256(\base)
\op \ri,512(\base)
\op \ri,1024(\base)
\op \ri,2048(\base)
\op \ri,4096(\base)
\op \ri,8192(\base)
\op \ri,16384(\base)
\op \ri,32767(\base)
mem9neg \op, \ri, \base
\op \ri,-512(\base)
\op \ri,-1024(\base)
\op \ri,-2048(\base)
\op \ri,-4096(\base)
\op \ri,-8192(\base)
\op \ri,-16384(\base)
\op \ri,-32768(\base)
.endm
.macro alupos op, args:vararg
\op \args, 0
\op \args, 1
\op \args, 2
\op \args, 4
\op \args, 8
\op \args, 16
\op \args, 32
\op \args, 64
\op \args, 128
\op \args, 256
\op \args, 512
\op \args, 1024
\op \args, 2048
\op \args, 4096
\op \args, 8192
\op \args, 16384
\op \args, 32767
.endm
.macro aluneg op, args:vararg
\op \args, -1
\op \args, -2
\op \args, -4
\op \args, -8
\op \args, -16
\op \args, -32
\op \args, -64
\op \args, -128
\op \args, -256
\op \args, -512
\op \args, -1024
\op \args, -2048
\op \args, -4096
\op \args, -8192
\op \args, -16384
\op \args, -32768
.endm
.macro aluu op, args:vararg
alupos \op, \args
\op \args, 32768
\op \args, 65535
.endm
.macro alu op, args:vararg
alupos \op, \args
aluneg \op, \args
.endm
.macro bit op, ry, rx
\op \ry, \rx, 0, 32
\op \ry, \rx, 1, 25
\op \ry, \rx, 2, 17
\op \ry, \rx, 3, 13
\op \ry, \rx, 4, 9
\op \ry, \rx, 6, 7
\op \ry, \rx, 8, 5
\op \ry, \rx, 12, 4
\op \ry, \rx, 16, 3
\op \ry, \rx, 24, 2
\op \ry, \rx, 31, 1
.endm
foo:
mem lw, $2, $gp
mem lh, $2, $gp
mem lhu, $2, $gp
mem lb, $2, $gp
mem lbu, $2, $gp
mem sw, $2, $gp
mem sh, $2, $gp
mem sb, $2, $gp
mem9 ll, $2, $3
mem9 lwl, $2, $3
mem9 lwr, $2, $3
mem9 sc, $2, $3
mem9 swl, $2, $3
mem9 swr, $2, $3
mem9 cache, 2, $3
mem9 cache, 29, $3
mem9 pref, 8, $3
mem9 pref, 23, $3
alu addiu, $2, $gp
alu addu, $2, $gp
aluu lui, $2
aluu andi, $2
aluu ori, $2
aluu xori, $2
bit ext, $2, $3
bit ins, $2, $3
bit ins, $6, $0
movn $2, $3, $4
movn $4, $5, $2
movn $7, $6, $17
movn $2, $0, $4
movz $2, $3, $4
movz $4, $5, $2
movz $17, $6, $7
movz $2, $0, $4
movtn $2, $3
movtn $4, $5
movtn $7, $6
movtn $2, $0
movtz $2, $3
movtz $4, $5
movtz $17, $6
movtz $2, $0
ehb
pause
sync
sync 1
sync 4
sync 13
sync 31
sync_wmb
sync_mb
sync_acquire
sync_release
sync_rmb
rdhwr $2, $1
rdhwr $3, $5
rdhwr $4, $29
rdhwr $5, $31
di
di $0
di $2
ei
ei $0
ei $2
mfc0 $3, $5
mfc0 $5, $9, 0
mfc0 $7, $13, 3
mfc0 $17, $15, 1
mfc0 $2, $17, 7
mfc0 $6, $21
mtc0 $3, $5
mtc0 $5, $9, 0
mtc0 $7, $13, 3
mtc0 $17, $15, 1
mtc0 $2, $17, 7
mtc0 $6, $21
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 16
.align 4, 0
|
tactcomplabs/xbgas-binutils-gdb
| 1,607
|
gas/testsuite/gas/mips/mips5-fp.s
|
# Source file used to test -mips5 instructions.
text_label:
abs.ps $f0, $f2
add.ps $f2, $f4, $f6
alnv.ps $f6, $f8, $f10, $3
c.eq.ps $f8, $f10
c.eq.ps $fcc2, $f10, $f12
c.f.ps $f8, $f10
c.f.ps $fcc2, $f10, $f12
c.le.ps $f8, $f10
c.le.ps $fcc2, $f10, $f12
c.lt.ps $f8, $f10
c.lt.ps $fcc2, $f10, $f12
c.nge.ps $f8, $f10
c.nge.ps $fcc2, $f10, $f12
c.ngl.ps $f8, $f10
c.ngl.ps $fcc2, $f10, $f12
c.ngle.ps $f8, $f10
c.ngle.ps $fcc2, $f10, $f12
c.ngt.ps $f8, $f10
c.ngt.ps $fcc2, $f10, $f12
c.ole.ps $f8, $f10
c.ole.ps $fcc2, $f10, $f12
c.olt.ps $f8, $f10
c.olt.ps $fcc2, $f10, $f12
c.seq.ps $f8, $f10
c.seq.ps $fcc2, $f10, $f12
c.sf.ps $f8, $f10
c.sf.ps $fcc2, $f10, $f12
c.ueq.ps $f8, $f10
c.ueq.ps $fcc2, $f10, $f12
c.ule.ps $f8, $f10
c.ule.ps $fcc2, $f10, $f12
c.ult.ps $f8, $f10
c.ult.ps $fcc2, $f10, $f12
c.un.ps $f8, $f10
c.un.ps $fcc2, $f10, $f12
cvt.ps.s $f12, $f14, $f16
cvt.s.pl $f16, $f18
cvt.s.pu $f18, $f20
luxc1 $f20, $4($5)
madd.ps $f20, $f22, $f24, $f26
mov.ps $f24, $f26
movf.ps $f26, $f28, $fcc2
movn.ps $f26, $f28, $3
movt.ps $f28, $f30, $fcc4
movz.ps $f28, $f30, $5
msub.ps $f30, $f0, $f2, $f4
mul.ps $f2, $f4, $f6
neg.ps $f6, $f8
nmadd.ps $f6, $f8, $f10, $f12
nmsub.ps $f6, $f8, $f10, $f12
pll.ps $f10, $f12, $f14
plu.ps $f14, $f16, $f18
pul.ps $f16, $f18, $f20
puu.ps $f20, $f22, $f24
sub.ps $f22, $f24, $f26
suxc1 $f26, $6($7)
c.eq.ps $fcc3, $f10, $f12 # warns
movf.ps $f26, $f28, $fcc3 # warns
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,957
|
gas/testsuite/gas/mips/mips16-hilo-match.s
|
.align 2
.globl _pinit
.LFB84:
.set nomips16
.ent _pinit
_pinit:
lw $3,8($23)
li $5,1
lui $2,%hi(__var1)
ori $3,$3,0x1
lui $4,%hi(var4)
sw $3,8($23)
addiu $4,$4,%lo(var4)
lui $3,%hi(var5)
sw $5,%lo(__var1)($2)
lui $19,%hi(hilo_match)
.LVL100:
lui $2,%hi(__var3)
sw $5,%lo(var5)($3)
.set noreorder
.set nomacro
jal func4
sw $5,%lo(__var3)($2)
.set macro
.set reorder
lw $17,%lo(hilo_match)($19)
.LVL101:
lui $2,%hi(var6)
lui $3,%hi(var6+704)
addiu $16,$2,%lo(var6)
.LVL102:
addiu $18,$3,%lo(var6+704)
.set noreorder
.set nomacro
jal func3
sw $2,%lo(hilo_match)($19)
.end _pinit
.LFE84:
.size _pinit, .-_pinit
.align 2
.globl pdelt
.LFB120:
.set mips16
.ent pdelt
pdelt:
.set macro
.set reorder
li $2,16
.L321:
.LVL212:
j $31
.LVL213:
.L322:
lhu $2,36($17)
move $4,$16
li $16,%hi(var2)
sll $16,$16,8
addiu $2,1
sll $16,$16,8
addiu $16,%lo(var2)
.set noreorder
.set nomacro
jal func1
sh $2,36($17)
.set macro
.set reorder
.set noreorder
.set nomacro
jal func2
move $4,$16
.set macro
.set reorder
li $3,%hi(hilo_match)
sll $3,$3,8
sll $3,$3,8
lw $2,%lo(hilo_match)($3)
sw $2,0($17)
sw $17,%lo(hilo_match)($3)
.set noreorder
.set nomacro
jal func1
move $4,$16
.set macro
.set reorder
.LVL214:
.set noreorder
.set nomacro
j $31
li $2,0
.set macro
.set reorder
.end pdelt
.align 2
.weak __var3
.section .sbss,"aw",@nobits
.align 2
.type __var3, @object
.size __var3, 4
__var3:
.space 4
.weak __var1
.align 2
.type __var1, @object
.size __var1, 4
__var1:
.space 4
.data
.align 2
.weak __hilo_match
.align 2
.type __hilo_match, @object
.size __hilo_match, 4
__hilo_match:
.space 4
.data
.align 2
.align 2
.type var2, @object
.size var2, 32
var2:
.word 0
.word -1
.word 0
.byte 0
.byte 0
.byte 0
.byte 0
.word 0
.word 0
.half 0
.space 6
.align 2
.rdata
.align 2
.space 8
.local var5
.comm var5,4,4
.align 2
.local var6
.comm var6,704,4
|
tactcomplabs/xbgas-binutils-gdb
| 1,734
|
gas/testsuite/gas/mips/ase-errors-3.s
|
.set micromips
.set mips32r2
.set dsp # OK
lbux $4,$5($6) # OK
ldx $4,$5($6) # ERROR: micromips doesn't have 64-bit DSPr1
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips1 # OK (we assume r2 anyway)
.set nodsp
lbux $4,$5($6) # ERROR: dsp not enabled
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips32r2
.set dspr2 # OK
lbux $4,$5($6) # OK
absq_s.qb $3,$4 # OK
.set mips1 # OK (we assume r2 anyway)
.set nodspr2
lbux $4,$5($6) # ERROR: dsp not enabled
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips32r2
.set mcu # OK
aclr 4,100($4) # OK
.set mips1 # OK (we assume r2 anyway)
.set nomcu
aclr 4,100($4) # ERROR: mcu not enabled
.set mips32r2
.set mdmx # ERROR: not supported at all
add.ob $f4,$f6,$f8 # ERROR: not supported at all
.set nomdmx
.set mips32r2
.set mips3d # ERROR: not supported at all
addr.ps $f4,$f6,$f8 # ERROR: not supported at all
.set nomips3d
.set mips32r2
.set mt # ERROR: not supported at all
dmt # ERROR: not supported at all
.set nomt
.set mips32
.set smartmips # ERROR: not supported at all
maddp $4,$5 # ERROR: not supported at all
.set nosmartmips
.set mips32r2
.set virt # OK
hypcall # OK
dmfgc0 $3, $29 # ERROR: 64-bit only
.set mips1 # OK (we assume r2 anyway)
.set novirt
hypcall # ERROR: virt not enabled
dmfgc0 $3, $29 # ERROR: virt not enabled
.set mips32r2
.set fp=64
.set eva # OK
lbue $4,16($5) # OK
.set fp=32 # OK
.set mips1 # OK (we assume r2 anyway)
lbue $4,16($5) # OK
.set noeva
lbue $4,16($5) # ERROR: eva not enabled
# There should be no errors after this.
.set fp=32
.set mips1
.set dsp
.set dspr2
.set mcu
.set mdmx
.set mips3d
.set mt
.set smartmips
.set eva
|
tactcomplabs/xbgas-binutils-gdb
| 1,176
|
gas/testsuite/gas/mips/cp2d.s
|
.text
foo:
ldc2 $0, 0($0)
ldc2 $1, 0($0)
ldc2 $2, 0($0)
ldc2 $3, 0($0)
ldc2 $4, 0($0)
ldc2 $5, 0($0)
ldc2 $6, 0($0)
ldc2 $7, 0($0)
ldc2 $8, 0($0)
ldc2 $9, 0($0)
ldc2 $10, 0($0)
ldc2 $11, 0($0)
ldc2 $12, 0($0)
ldc2 $13, 0($0)
ldc2 $14, 0($0)
ldc2 $15, 0($0)
ldc2 $16, 0($0)
ldc2 $17, 0($0)
ldc2 $18, 0($0)
ldc2 $19, 0($0)
ldc2 $20, 0($0)
ldc2 $21, 0($0)
ldc2 $22, 0($0)
ldc2 $23, 0($0)
ldc2 $24, 0($0)
ldc2 $25, 0($0)
ldc2 $26, 0($0)
ldc2 $27, 0($0)
ldc2 $28, 0($0)
ldc2 $29, 0($0)
ldc2 $30, 0($0)
ldc2 $31, 0($0)
sdc2 $0, 0($0)
sdc2 $1, 0($0)
sdc2 $2, 0($0)
sdc2 $3, 0($0)
sdc2 $4, 0($0)
sdc2 $5, 0($0)
sdc2 $6, 0($0)
sdc2 $7, 0($0)
sdc2 $8, 0($0)
sdc2 $9, 0($0)
sdc2 $10, 0($0)
sdc2 $11, 0($0)
sdc2 $12, 0($0)
sdc2 $13, 0($0)
sdc2 $14, 0($0)
sdc2 $15, 0($0)
sdc2 $16, 0($0)
sdc2 $17, 0($0)
sdc2 $18, 0($0)
sdc2 $19, 0($0)
sdc2 $20, 0($0)
sdc2 $21, 0($0)
sdc2 $22, 0($0)
sdc2 $23, 0($0)
sdc2 $24, 0($0)
sdc2 $25, 0($0)
sdc2 $26, 0($0)
sdc2 $27, 0($0)
sdc2 $28, 0($0)
sdc2 $29, 0($0)
sdc2 $30, 0($0)
sdc2 $31, 0($0)
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 1,854
|
gas/testsuite/gas/mips/usw.s
|
# Source file used to test the usw macro.
.data
data_label:
.extern big_external_data_label,1000
.extern small_external_data_label,1
.comm big_external_common,1000
.comm small_external_common,1
.lcomm big_local_common,1000
.lcomm small_local_common,1
.text
usw $4,0
usw $4,1
usw $4,0x8000
usw $4,-0x8000
usw $4,0x10000
usw $4,0x1a5a5
usw $4,0($5)
usw $4,1($5)
usw $4,data_label
usw $4,big_external_data_label
usw $4,small_external_data_label
usw $4,big_external_common
usw $4,small_external_common
usw $4,big_local_common
usw $4,small_local_common
usw $4,data_label+1
usw $4,big_external_data_label+1
usw $4,small_external_data_label+1
usw $4,big_external_common+1
usw $4,small_external_common+1
usw $4,big_local_common+1
usw $4,small_local_common+1
usw $4,data_label+0x8000
usw $4,big_external_data_label+0x8000
usw $4,small_external_data_label+0x8000
usw $4,big_external_common+0x8000
usw $4,small_external_common+0x8000
usw $4,big_local_common+0x8000
usw $4,small_local_common+0x8000
usw $4,data_label-0x8000
usw $4,big_external_data_label-0x8000
usw $4,small_external_data_label-0x8000
usw $4,big_external_common-0x8000
usw $4,small_external_common-0x8000
usw $4,big_local_common-0x8000
usw $4,small_local_common-0x8000
usw $4,data_label+0x10000
usw $4,big_external_data_label+0x10000
usw $4,small_external_data_label+0x10000
usw $4,big_external_common+0x10000
usw $4,small_external_common+0x10000
usw $4,big_local_common+0x10000
usw $4,small_local_common+0x10000
usw $4,data_label+0x1a5a5
usw $4,big_external_data_label+0x1a5a5
usw $4,small_external_data_label+0x1a5a5
usw $4,big_external_common+0x1a5a5
usw $4,small_external_common+0x1a5a5
usw $4,big_local_common+0x1a5a5
usw $4,small_local_common+0x1a5a5
# Round to a 16 byte boundary, for ease in testing multiple targets.
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 2,130
|
gas/testsuite/gas/mips/unaligned-jump-micromips-1.s
|
.text
.set noreorder
.space 0x1000
.align 4
.set micromips
.ent foo
foo:
not $2, $3
jalx bar0
not $2, $3
jal bar0
not $2, $3
jals bar0
not $2, $3
j bar0
not $2, $3
jalx bar1
not $2, $3
jal bar1
not $2, $3
jals bar1
not $2, $3
j bar1
not $2, $3
jalx bar2
not $2, $3
jal bar2
not $2, $3
jals bar2
not $2, $3
j bar2
not $2, $3
jalx bar3
not $2, $3
jal bar3
not $2, $3
jals bar3
not $2, $3
j bar3
not $2, $3
jalx bar4
not $2, $3
jal bar4
not $2, $3
jals bar4
not $2, $3
j bar4
not $2, $3
jalx bar4 + 1
not $2, $3
jal bar4 + 1
not $2, $3
jals bar4 + 1
not $2, $3
j bar4 + 1
not $2, $3
jalx bar4 + 2
not $2, $3
jal bar4 + 2
not $2, $3
jals bar4 + 2
not $2, $3
j bar4 + 2
not $2, $3
jalx bar4 + 3
not $2, $3
jal bar4 + 3
not $2, $3
jals bar4 + 3
not $2, $3
j bar4 + 3
not $2, $3
jalx bar4 + 4
not $2, $3
jal bar4 + 4
not $2, $3
jals bar4 + 4
not $2, $3
j bar4 + 4
not $2, $3
jalx bar16
not $2, $3
jal bar16
not $2, $3
jals bar16
not $2, $3
j bar16
not $2, $3
jalx bar17
not $2, $3
jal bar17
not $2, $3
jals bar17
not $2, $3
j bar17
not $2, $3
jalx bar18
not $2, $3
jal bar18
not $2, $3
jals bar18
not $2, $3
j bar18
not $2, $3
jalx bar18 + 1
not $2, $3
jal bar18 + 1
not $2, $3
jals bar18 + 1
not $2, $3
j bar18 + 1
not $2, $3
jalx bar18 + 2
not $2, $3
jal bar18 + 2
not $2, $3
jals bar18 + 2
not $2, $3
j bar18 + 2
not $2, $3
jalx bar18 + 3
not $2, $3
jal bar18 + 3
not $2, $3
jals bar18 + 3
not $2, $3
j bar18 + 3
not $2, $3
jalx bar18 + 4
not $2, $3
jal bar18 + 4
not $2, $3
jals bar18 + 4
not $2, $3
j bar18 + 4
not $2, $3
jalr $0, $ra
not $2, $3
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,355
|
gas/testsuite/gas/mips/unaligned-branch-mips16-1.s
|
.text
.set noreorder
.space 0x1000
.align 4
.set mips16
.ent foo
foo:
not $2, $3
b bar0
not $2, $3
b bar1
not $2, $3
b bar2
not $2, $3
b bar3
not $2, $3
b bar4
not $2, $3
b bar4 + 1
not $2, $3
b bar4 + 2
not $2, $3
b bar4 + 3
not $2, $3
b bar4 + 4
not $2, $3
b bar16
not $2, $3
b bar17
not $2, $3
b bar18
not $2, $3
b bar18 + 1
not $2, $3
b bar18 + 2
not $2, $3
b bar18 + 3
not $2, $3
b bar18 + 4
not $2, $3
bnez $2, bar0
not $2, $3
bnez $2, bar1
not $2, $3
bnez $2, bar2
not $2, $3
bnez $2, bar3
not $2, $3
bnez $2, bar4
not $2, $3
bnez $2, bar4 + 1
not $2, $3
bnez $2, bar4 + 2
not $2, $3
bnez $2, bar4 + 3
not $2, $3
bnez $2, bar4 + 4
not $2, $3
bnez $2, bar16
not $2, $3
bnez $2, bar17
not $2, $3
bnez $2, bar18
not $2, $3
bnez $2, bar18 + 1
not $2, $3
bnez $2, bar18 + 2
not $2, $3
bnez $2, bar18 + 3
not $2, $3
bnez $2, bar18 + 4
not $2, $3
jr $ra
not $2, $3
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,084
|
gas/testsuite/gas/mips/mips16-macro-e.s
|
.set mips16
.ent foo
foo:
div.e $2,$3,$4
divu.e $3,$4,$5
ddiv.e $4,$5,$6
ddivu.e $5,$6,$7
rem.e $6,$7,$16
remu.e $6,$7,$17
drem.e $2,$3,$4
dremu.e $3,$4,$5
mul.e $4,$5,$6
dmul.e $5,$6,$7
subu.e $2,-32767
subu.e $3,16
subu.e $4,32768
subu.e $3,$7,-16383
subu.e $4,$16,4
subu.e $5,$17,16384
dsubu.e $4,-32767
dsubu.e $6,6
dsubu.e $7,32768
dsubu.e $2,$4,-16383
dsubu.e $3,$7,8
dsubu.e $4,$5,16384
1: beq.e $2,$3,1b
1: bne.e $4,$5,1b
1: blt.e $6,$7,1b
1: bltu.e $16,$17,1b
1: ble.e $4,$7,1b
1: bleu.e $5,$6,1b
1: bge.e $4,$16,1b
1: bgeu.e $5,$17,1b
1: bgt.e $4,$6,1b
1: bgtu.e $5,$7,1b
1: beq.e $2,1,1b
1: beq.e $3,65535,1b
1: bne.e $4,1,1b
1: bne.e $5,65535,1b
1: blt.e $6,-32768,1b
1: blt.e $7,32767,1b
1: bltu.e $16,-32768,1b
1: bltu.e $17,32767,1b
1: ble.e $2,-32769,1b
1: ble.e $3,32766,1b
1: bleu.e $4,-32769,1b
1: bleu.e $5,32766,1b
1: bge.e $6,-32768,1b
1: bge.e $7,32766,1b
1: bgeu.e $16,-32768,1b
1: bgeu.e $17,32767,1b
1: bgt.e $2,-32769,1b
1: bgt.e $3,32766,1b
1: bgtu.e $4,-32769,1b
1: bgtu.e $5,32766,1b
abs.e $2
abs.e $3,$3
abs.e $4,$5
.end foo
|
tactcomplabs/xbgas-binutils-gdb
| 2,620
|
gas/testsuite/gas/mips/mips-gp32-fp64.s
|
.sdata
shared: .word 11
.data
unshared:
.word 1
.word 2
.word 3
.word 4
.text
func:
.set noreorder
li $4, 0x12345678 # 0000 lui a0,0x1234
# 0004 ori a0,a0,0x5678
la $4, shared # 0008 addiu a0,gp,shared
la $4, unshared # 000c lui a0,hi(unshared)
# 0010 addiu a0,a0,lo(unshared)
la $4, end # 0014 lui a0,hi(end)
# 0018 addiu a0,a0,lo(end)
j end # 001c j end
jal end # 0020 jal end
lw $4, shared # 0024 lw a0,shared(gp)
lw $4, unshared # 0028 lui a0,hi(unshared)
# 002c lw a0,lo(unshared)(a0)
lw $4, end # 0030 lui a0,hi(end)
# 0034 lw a0,lo(end)(a0)
ld $4, shared # 0038 lw a0,shared(gp)
# 003c lw a1,shared+4(gp)
ld $4, unshared # 0040 lui at,hi(unshared)
# 0044 lw a0,lo(unshared)(at)
# 0048 lw a1,lo(unshared)+4(at)
ld $4, end # 004c lui at,hi(end)
# 0050 lw a0,lo(end)(at)
# 0054 lw a1,lo(end)+4(at)
sw $4, shared # 0058 sw a0,shared(gp)
sw $4, unshared # 005c lui at,hi(unshared)
# 0060 sw a0,lo(unshared)(at)
sd $4, shared # 0064 sw a0,shared(gp)
# 0068 sw a1,shared+4(gp)
sd $4, unshared # 006c lui at,hi(unshared)
# 0070 sw a0,lo(unshared)(at)
# 0074 sw a1,lo(unshared)+4(at)
ulh $4, unshared # 0078 lui at,hi(unshared)
# 007c addiu at,at,lo(unshared)
# 0080 lb a0,0(at)
# 0084 lbu at,1(at)
# 0088 sll a0,a0,8
# 008c or a0,a0,at
ush $4, unshared # 0090 lui at,hi(unshared)
# 0094 addiu at,at,lo(unshared)
# 0098 sb a0,1(at)
# 009c srl a0,a0,8
# 00a0 sb a0,0(at)
# 00a4 lbu at,1(at)
# 00a8 sll a0,a0,8
# 00ac or a0,a0,at
ulw $4, unshared # 00b0 lui at,hi(unshared)
# 00b4 addiu at,at,lo(unshared)
# 00b8 lwl a0,0(at)
# 00bc lwr a0,3(at)
usw $4, unshared # 00c0 lui at,hi(unshared)
# 00c4 addiu at,at,lo(unshared)
# 00c8 swl a0,0(at)
# 00cc swr a0,3(at)
li.d $4, 1.0 # 00d0 lui a0,0x3ff0
# 00d4 move a1,zero
li.d $4, 1.9 # 00d8 lui at,hi(F1.9)
# 00dc lw a0,lo(F1.9)(at)
# 00e0 lw a1,lo(F1.9)+4(at)
li.d $f0, 1.0 # 00e4 ldc1 $f0,L1.0(gp)
li.d $f0, 1.9 # 00e8 ldc1 $f0,L1.9(gp)
seq $4, $5, -100 # 00ec addiu a0,a1,100
# 00f0 sltiu a0,a0,1
sne $4, $5, -100 # 00f4 addiu a0,a1,100
# 00f8 sltu a0,zero,a0
move $4, $5 # 00fc move a0,a1
# Not available in 32-bit mode
# dla $4, shared
# dla $4, unshared
# uld $4, unshared
# usd $4, unshared
# Should produce warnings given -mgp32
# bgt $4, 0x7fffffff, end
# bgtu $4, 0xffffffff, end
# ble $4, 0x7fffffff, end
# bleu $4, 0xffffffff, end
add.d $f1, $f2, $f3 # 0100 add.d $f1,$f2,$f3
end:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,779
|
gas/testsuite/gas/mips/ldstla-32-mips3-1.s
|
.set mips3
.text
ld $2, 0xfffffffeffffffff($4)
ld $2, 0xfffffffe00000000($4)
ld $2, 0xabcdef0123456789($4)
ld $2, 0x0123456789abcdef($4)
ld $2, 0x00000001ffffffff($4)
ld $2, 0x0000000100000000($4)
ld $2, 0xfffffffeffffffff
ld $2, 0xfffffffe00000000
ld $2, 0xabcdef0123456789
ld $2, 0x0123456789abcdef
ld $2, 0x00000001ffffffff
ld $2, 0x0000000100000000
sd $2, 0xfffffffeffffffff($4)
sd $2, 0xfffffffe00000000($4)
sd $2, 0xabcdef0123456789($4)
sd $2, 0x0123456789abcdef($4)
sd $2, 0x00000001ffffffff($4)
sd $2, 0x0000000100000000($4)
sd $2, 0xfffffffeffffffff
sd $2, 0xfffffffe00000000
sd $2, 0xabcdef0123456789
sd $2, 0x0123456789abcdef
sd $2, 0x00000001ffffffff
sd $2, 0x0000000100000000
lw $2, 0xfffffffeffffffff($4)
lw $2, 0xfffffffe00000000($4)
lw $2, 0xabcdef0123456789($4)
lw $2, 0x0123456789abcdef($4)
lw $2, 0x00000001ffffffff($4)
lw $2, 0x0000000100000000($4)
lw $2, 0xfffffffeffffffff
lw $2, 0xfffffffe00000000
lw $2, 0xabcdef0123456789
lw $2, 0x0123456789abcdef
lw $2, 0x00000001ffffffff
lw $2, 0x0000000100000000
sw $2, 0xfffffffeffffffff($4)
sw $2, 0xfffffffe00000000($4)
sw $2, 0xabcdef0123456789($4)
sw $2, 0x0123456789abcdef($4)
sw $2, 0x00000001ffffffff($4)
sw $2, 0x0000000100000000($4)
sw $2, 0xfffffffeffffffff
sw $2, 0xfffffffe00000000
sw $2, 0xabcdef0123456789
sw $2, 0x0123456789abcdef
sw $2, 0x00000001ffffffff
sw $2, 0x0000000100000000
la $2, 0xfffffffeffffffff($4)
la $2, 0xfffffffe00000000($4)
la $2, 0xabcdef0123456789($4)
la $2, 0x0123456789abcdef($4)
la $2, 0x00000001ffffffff($4)
la $2, 0x0000000100000000($4)
la $2, 0xfffffffeffffffff
la $2, 0xfffffffe00000000
la $2, 0xabcdef0123456789
la $2, 0x0123456789abcdef
la $2, 0x00000001ffffffff
la $2, 0x0000000100000000
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,887
|
gas/testsuite/gas/mips/unaligned-branch-r6-2.s
|
.text
.set noreorder
.space 0x1000
.align 4
.set mips0
.ent foo
foo:
nor $0, $0
bc bar0
nor $0, $0
beqzc $2, bar0
nor $0, $0
beqz $2, bar0
nor $0, $0
bc bar1
nor $0, $0
beqzc $2, bar1
nor $0, $0
beqz $2, bar1
nor $0, $0
bc bar2
nor $0, $0
beqzc $2, bar2
nor $0, $0
beqz $2, bar2
nor $0, $0
bc bar3
nor $0, $0
beqzc $2, bar3
nor $0, $0
beqz $2, bar3
nor $0, $0
bc bar4
nor $0, $0
beqzc $2, bar4
nor $0, $0
beqz $2, bar4
nor $0, $0
bc bar4 + 1
nor $0, $0
beqzc $2, bar4 + 1
nor $0, $0
beqz $2, bar4 + 1
nor $0, $0
bc bar4 + 2
nor $0, $0
beqzc $2, bar4 + 2
nor $0, $0
beqz $2, bar4 + 2
nor $0, $0
bc bar4 + 3
nor $0, $0
beqzc $2, bar4 + 3
nor $0, $0
beqz $2, bar4 + 3
nor $0, $0
bc bar4 + 4
nor $0, $0
beqzc $2, bar4 + 4
nor $0, $0
beqz $2, bar4 + 4
nor $0, $0
bc bar16
nor $0, $0
beqzc $2, bar16
nor $0, $0
beqz $2, bar16
nor $0, $0
bc bar17
nor $0, $0
beqzc $2, bar17
nor $0, $0
beqz $2, bar17
nor $0, $0
bc bar18
nor $0, $0
beqzc $2, bar18
nor $0, $0
beqz $2, bar18
nor $0, $0
bc bar18 + 1
nor $0, $0
beqzc $2, bar18 + 1
nor $0, $0
beqz $2, bar18 + 1
nor $0, $0
bc bar18 + 2
nor $0, $0
beqzc $2, bar18 + 2
nor $0, $0
beqz $2, bar18 + 2
nor $0, $0
bc bar18 + 3
nor $0, $0
beqzc $2, bar18 + 3
nor $0, $0
beqz $2, bar18 + 3
nor $0, $0
bc bar18 + 4
nor $0, $0
beqzc $2, bar18 + 4
nor $0, $0
beqz $2, bar18 + 4
nor $0, $0
jalr $0, $ra
nor $0, $0
.end foo
.set mips0
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
.set mips0
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,676
|
gas/testsuite/gas/mips/r6-removed.s
|
.set reorder
.set eva
abs.ps $f0,$f2
add.ps $f0,$f2,$f2
addi $15,$16,256
alnv.ps $f0,$f2,$f2,$3
bc0f 1f
bc0fl 1f
bc0t 1f
bc0tl 1f
bc1f 1f
bc1fl 1f
bc1t 1f
bc1tl 1f
bc2f 1f
bc2fl 1f
bc2t 1f
bc2tl 1f
bc3f 1f
bc3fl 1f
bc3t 1f
bc3tl 1f
beql $28,$29,1f
bgezal $4,1f
bgezall $28,1f
bgezl $28,1f
bgtzl $28,1f
blezl $28,1f
bltzal $4,1f
bltzall $28,1f
bltzl $28,1f
bnel $28,$29,1f
c.f.s $f0,$f2
c.un.s $f0,$f2
c.eq.s $f0,$f2
c.ueq.s $f0,$f2
c.olt.s $f0,$f2
c.ult.s $f0,$f2
c.ole.s $f0,$f2
c.ule.s $f0,$f2
c.sf.s $f0,$f2
c.ngle.s $f0,$f2
c.seq.s $f0,$f2
c.ngl.s $f0,$f2
c.lt.s $f0,$f2
c.nge.s $f0,$f2
c.le.s $f0,$f2
c.ngt.s $f0,$f2
c.f.ps $f0,$f2
c.un.ps $f0,$f2
c.eq.ps $f0,$f2
c.ueq.ps $f0,$f2
c.olt.ps $f0,$f2
c.ult.ps $f0,$f2
c.ole.ps $f0,$f2
c.ule.ps $f0,$f2
c.sf.ps $f0,$f2
c.ngle.ps $f0,$f2
c.seq.ps $f0,$f2
c.ngl.ps $f0,$f2
c.lt.ps $f0,$f2
c.nge.ps $f0,$f2
c.le.ps $f0,$f2
c.ngt.ps $f0,$f2
c.f.d $f0,$f2
c.un.d $f0,$f2
c.eq.d $f0,$f2
c.ueq.d $f0,$f2
c.olt.d $f0,$f2
c.ult.d $f0,$f2
c.ole.d $f0,$f2
c.ule.d $f0,$f2
c.sf.d $f0,$f2
c.ngle.d $f0,$f2
c.seq.d $f0,$f2
c.ngl.d $f0,$f2
c.lt.d $f0,$f2
c.nge.d $f0,$f2
c.le.d $f0,$f2
c.ngt.d $f0,$f2
c.f.s $fcc2, $f0,$f2
c.un.s $fcc2, $f0,$f2
c.eq.s $fcc2, $f0,$f2
c.ueq.s $fcc2, $f0,$f2
c.olt.s $fcc2, $f0,$f2
c.ult.s $fcc2, $f0,$f2
c.ole.s $fcc2, $f0,$f2
c.ule.s $fcc2, $f0,$f2
c.sf.s $fcc2, $f0,$f2
c.ngle.s $fcc2, $f0,$f2
c.seq.s $fcc2, $f0,$f2
c.ngl.s $fcc2, $f0,$f2
c.lt.s $fcc2, $f0,$f2
c.nge.s $fcc2, $f0,$f2
c.le.s $fcc2, $f0,$f2
c.ngt.s $fcc2, $f0,$f2
c.f.ps $fcc2, $f0,$f2
c.un.ps $fcc2, $f0,$f2
c.eq.ps $fcc2, $f0,$f2
c.ueq.ps $fcc2, $f0,$f2
c.olt.ps $fcc2, $f0,$f2
c.ult.ps $fcc2, $f0,$f2
c.ole.ps $fcc2, $f0,$f2
c.ule.ps $fcc2, $f0,$f2
c.sf.ps $fcc2, $f0,$f2
c.ngle.ps $fcc2, $f0,$f2
c.seq.ps $fcc2, $f0,$f2
c.ngl.ps $fcc2, $f0,$f2
c.lt.ps $fcc2, $f0,$f2
c.nge.ps $fcc2, $f0,$f2
c.le.ps $fcc2, $f0,$f2
c.ngt.ps $fcc2, $f0,$f2
c.f.d $fcc2, $f0,$f2
c.un.d $fcc2, $f0,$f2
c.eq.d $fcc2, $f0,$f2
c.ueq.d $fcc2, $f0,$f2
c.olt.d $fcc2, $f0,$f2
c.ult.d $fcc2, $f0,$f2
c.ole.d $fcc2, $f0,$f2
c.ule.d $fcc2, $f0,$f2
c.sf.d $fcc2, $f0,$f2
c.ngle.d $fcc2, $f0,$f2
c.seq.d $fcc2, $f0,$f2
c.ngl.d $fcc2, $f0,$f2
c.lt.d $fcc2, $f0,$f2
c.nge.d $fcc2, $f0,$f2
c.le.d $fcc2, $f0,$f2
c.ngt.d $fcc2, $f0,$f2
cvt.ps.s $f2,$f3,$f4
jalx 1f
ldxc1 $f0,$0($2)
luxc1 $f0,$0($2)
lwl $2, 1($3)
lwle $4,0($6)
lwr $2, 1($3)
lwre $4,0($6)
lwxc1 $f0,$0($2)
madd $2,$3
maddu $2,$3
madd.s $f5,$f6,$f7,$f8
madd.d $f6,$f8,$f10,$f12
madd.ps $f6,$f8,$f10,$f12
mfhi $2
mflo $2
mov.ps $f10,$f20
movf $8,$9,$fcc0
movf.s $f8,$f9,$fcc0
movf.d $f8,$f10,$fcc0
movf.ps $f8,$f10,$fcc0
movn $2,$3,$4
movn.s $f0,$f2,$10
movn.d $f0,$f2,$10
movn.ps $f0,$f2,$10
movt $10,$11,$fcc2
movt.s $f20,$f21,$fcc2
movt.d $f20,$f22,$fcc2
movt.ps $f20,$f22,$fcc2
movz $5,$6,$7
movz.s $f0,$f2,$10
movz.d $f0,$f2,$10
movz.ps $f0,$f2,$10
msub $2,$3
msubu $2,$3
msub.s $f5,$f6,$f7,$f8
msub.d $f6,$f8,$f10,$f12
msub.ps $f6,$f8,$f10,$f12
mthi $2
mtlo $2
mul.ps $f10,$f20,$f22
mult $2,$3
multu $2,$3
neg.ps $f22,$f24
nmadd.s $f5,$f6,$f7,$f8
nmadd.d $f6,$f8,$f10,$f12
nmadd.ps $f6,$f8,$f10,$f12
nmsub.s $f5,$f6,$f7,$f8
nmsub.d $f6,$f8,$f10,$f12
nmsub.ps $f6,$f8,$f10,$f12
pll.ps $f24,$f20,$f26
plu.ps $f24,$f20,$f26
pul.ps $f24,$f20,$f26
puu.ps $f24,$f20,$f26
prefx 5, $3($5)
sdxc1 $f0,$0($2)
sub.ps $f20,$f28,$f26
suxc1 $f0,$0($2)
swl $2, 1($3)
swle $4,0($6)
swr $2, 1($3)
swre $4,0($6)
swxc1 $f0,$0($2)
teqi $11,1024
tgei $11,1024
tgeiu $11,1024
tlti $11,1024
tltiu $11,1024
tnei $11,1024
1:
|
tactcomplabs/xbgas-binutils-gdb
| 2,044
|
gas/testsuite/gas/mips/micromips-size-1.s
|
# Source file used to test microMIPS instruction size overrides (#1).
.text
foo:
# Smoke-test a trivial case.
nop
nop16
nop32
# Test ALU operations.
addu $2, $4
addu16 $2, $4
addu32 $2, $4
addu $12, $14
addu32 $12, $14
add.ps $f2, $f4
add32.ps $f2, $f4
addiusp 256
addiusp16 256
# Test jumps and branches.
jalr $4
jalr16 $4
jalr32 $4
jalr $24
jalr16 $24
jalr32 $24
jalr $31,$5
jalr16 $31,$5
jalr32 $31,$5
jalr $31,$25
jalr16 $31,$25
jalr32 $31,$25
jalr $30,$26
jalr32 $30,$26
nop
b bar
nop
b16 bar
nop
b32 bar
nop
beqz $7, bar
nop
beqz16 $7, bar
nop
beqz32 $7, bar
nop
beqz $27, bar
nop
beqz32 $27, bar
# Test branch delay slots.
.set noreorder
bltzal $2, bar
addu $16, $17
bltzal $2, bar
addu16 $16, $17
bltzal $2, bar
addu32 $16, $17
bltzals $2, bar
addu $16, $17
bltzals $2, bar
addu16 $16, $17
bltzals $2, bar
addu32 $16, $17
bltzal $2, bar
add.ps $f2, $f4
bltzal $2, bar
add32.ps $f2, $f4
bltzals $2, bar
add.ps $f2, $f4
bltzals $2, bar
add32.ps $f2, $f4
bltzal $2, bar
addiusp 256
bltzal $2, bar
addiusp16 256
bltzals $2, bar
addiusp 256
bltzals $2, bar
addiusp16 256
.set reorder
# Test macro delay slots.
.set noreorder
bltzall $2, bar
addu $16, $17
bltzall $2, bar
addu16 $16, $17
bltzall $2, bar
addu32 $16, $17
bltzall $2, bar
add.ps $f2, $f4
bltzall $2, bar
add32.ps $f2, $f4
bltzall $2, bar
addiusp 256
bltzall $2, bar
addiusp16 256
.set reorder
# Test shift instructions to complement 64-bit tests.
sll $2, $3, 5
sll16 $2, $3, 5
sll32 $2, $3, 5
sll $2, $3, 13
sll32 $2, $3, 13
sll $10, $11, 5
sll32 $10, $11, 5
# Test 64-bit instructions.
dsll $2, $3, 5
dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
dsll3232 $2, $3, 5
dsll $2, $3, 13
dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
dsll3232 $2, $3, 13
dsll $10, $11, 5
dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
dsll3232 $10, $11, 5
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 7,385
|
gas/testsuite/gas/mips/at-1.s
|
.text
foo:
.set at=$1
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$2
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$3
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$a0
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$a1
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$a2
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$a3
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$8
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$9
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$10
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$11
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$12
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$13
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$14
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$15
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$s0
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$s1
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$s2
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$s3
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$s4
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$s5
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$s6
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$s7
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$24
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$25
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$26
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$27
lw $26, 0x7fff($26)
sw $26, 0x7fff($26)
lw $26, -0x8000($26)
sw $26, -0x8000($26)
lw $26, 0x8000($26)
sw $26, 0x8000($26)
lw $26, -0x8001($26)
sw $26, -0x8001($26)
lw $26, symbol($26)
sw $26, symbol($26)
.set at=$gp
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$fp
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$sp
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at=$ra
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
.set at
lw $27, 0x7fff($27)
sw $27, 0x7fff($27)
lw $27, -0x8000($27)
sw $27, -0x8000($27)
lw $27, 0x8000($27)
sw $27, 0x8000($27)
lw $27, -0x8001($27)
sw $27, -0x8001($27)
lw $27, symbol($27)
sw $27, symbol($27)
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,064
|
gas/testsuite/gas/mips/cp2-64.s
|
.text
.set noreorder
foo:
dmtc2 $0, $0
dmtc2 $0, $1
dmtc2 $0, $2
dmtc2 $0, $3
dmtc2 $0, $4
dmtc2 $0, $5
dmtc2 $0, $6
dmtc2 $0, $7
dmtc2 $0, $8
dmtc2 $0, $9
dmtc2 $0, $10
dmtc2 $0, $11
dmtc2 $0, $12
dmtc2 $0, $13
dmtc2 $0, $14
dmtc2 $0, $15
dmtc2 $0, $16
dmtc2 $0, $17
dmtc2 $0, $18
dmtc2 $0, $19
dmtc2 $0, $20
dmtc2 $0, $21
dmtc2 $0, $22
dmtc2 $0, $23
dmtc2 $0, $24
dmtc2 $0, $25
dmtc2 $0, $26
dmtc2 $0, $27
dmtc2 $0, $28
dmtc2 $0, $29
dmtc2 $0, $30
dmtc2 $0, $31
dmfc2 $0, $0
dmfc2 $0, $1
dmfc2 $0, $2
dmfc2 $0, $3
dmfc2 $0, $4
dmfc2 $0, $5
dmfc2 $0, $6
dmfc2 $0, $7
dmfc2 $0, $8
dmfc2 $0, $9
dmfc2 $0, $10
dmfc2 $0, $11
dmfc2 $0, $12
dmfc2 $0, $13
dmfc2 $0, $14
dmfc2 $0, $15
dmfc2 $0, $16
dmfc2 $0, $17
dmfc2 $0, $18
dmfc2 $0, $19
dmfc2 $0, $20
dmfc2 $0, $21
dmfc2 $0, $22
dmfc2 $0, $23
dmfc2 $0, $24
dmfc2 $0, $25
dmfc2 $0, $26
dmfc2 $0, $27
dmfc2 $0, $28
dmfc2 $0, $29
dmfc2 $0, $30
dmfc2 $0, $31
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 1,206
|
gas/testsuite/gas/mips/mcu.s
|
.text
.set mcu
.ent foo
.globl foo
foo:
iret
aclr 0, 0
aclr 0, ($0)
aclr 0, 0($0)
aclr 1, 0($0)
aclr 2, 0($0)
aclr 3, 0($0)
aclr 4, 0($0)
aclr 5, 0($0)
aclr 6, 0($0)
aclr 7, 0($0)
aclr 7, 0($2)
aclr 7, 0($31)
aclr 7, 2047($31)
aclr 7, -2048($31)
aclr 7, 2048($31)
aclr 7, -2049($31)
aclr 7, 32767($31)
aclr 7, -32768($31)
aclr 7, 65535($4)
aclr 7, 65536($4)
aclr 7, 0xffff0000($4)
aclr 7, 0xffff8000($4)
aclr 7, 0xffff0001($4)
aclr 7, 0xffff8001($4)
aclr 7, 0xf0000000($4)
aclr 7, 0xffffffff($4)
aclr 7, 0x12345678($4)
aclr 1, %lo(foo)($3)
aset 1, %lo(foo)($3)
aset 0, 0
aset 0, ($0)
aset 0, 0($0)
aset 1, 0($0)
aset 2, 0($0)
aset 3, 0($0)
aset 4, 0($0)
aset 5, 0($0)
aset 6, 0($0)
aset 7, 0($0)
aset 7, 0($2)
aset 7, 0($31)
aset 7, 2047($31)
aset 7, -2048($31)
aset 7, 2048($31)
aset 7, -2049($31)
aset 7, 32767($31)
aset 7, -32768($31)
aset 7, 65535($4)
aset 7, 65536($4)
aset 7, 0xffff0000($4)
aset 7, 0xffff8000($4)
aset 7, 0xffff0001($4)
aset 7, 0xffff8001($4)
aset 7, 0xf0000000($4)
aset 7, 0xffffffff($4)
aset 7, 0x12345678($4)
.end foo
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 5,067
|
gas/testsuite/gas/mips/mips64-mdmx.s
|
# source file to test assembly of MIPS64 MDMX ASE instructions
.set noreorder
.set noat
.globl text_label .text
text_label:
movf.l $v1, $v12, $fcc5
movn.l $v1, $v12, $18
movt.l $v1, $v12, $fcc5
movz.l $v1, $v12, $18
add.ob $v1, $v12, 18
add.ob $v1, $v12, $v18
add.ob $v1, $v12, $v18[6]
add.qh $v1, $v12, 18
add.qh $v1, $v12, $v18
add.qh $v1, $v12, $v18[2]
adda.ob $v12, 18
adda.ob $v12, $v18
adda.ob $v12, $v18[6]
adda.qh $v12, 18
adda.qh $v12, $v18
adda.qh $v12, $v18[2]
addl.ob $v12, 18
addl.ob $v12, $v18
addl.ob $v12, $v18[6]
addl.qh $v12, 18
addl.qh $v12, $v18
addl.qh $v12, $v18[2]
alni.ob $v1, $v12, $v18, 6
alni.qh $v1, $v12, $v18, 2
alnv.ob $v1, $v12, $v18, $21
alnv.qh $v1, $v12, $v18, $21
and.ob $v1, $v12, 18
and.ob $v1, $v12, $v18
and.ob $v1, $v12, $v18[6]
and.qh $v1, $v12, 18
and.qh $v1, $v12, $v18
and.qh $v1, $v12, $v18[2]
c.eq.ob $v12, 18
c.eq.ob $v12, $v18
c.eq.ob $v12, $v18[6]
c.eq.qh $v12, 18
c.eq.qh $v12, $v18
c.eq.qh $v12, $v18[2]
c.le.ob $v12, 18
c.le.ob $v12, $v18
c.le.ob $v12, $v18[6]
c.le.qh $v12, 18
c.le.qh $v12, $v18
c.le.qh $v12, $v18[2]
c.lt.ob $v12, 18
c.lt.ob $v12, $v18
c.lt.ob $v12, $v18[6]
c.lt.qh $v12, 18
c.lt.qh $v12, $v18
c.lt.qh $v12, $v18[2]
max.ob $v1, $v12, 18
max.ob $v1, $v12, $v18
max.ob $v1, $v12, $v18[6]
max.qh $v1, $v12, 18
max.qh $v1, $v12, $v18
max.qh $v1, $v12, $v18[2]
min.ob $v1, $v12, 18
min.ob $v1, $v12, $v18
min.ob $v1, $v12, $v18[6]
min.qh $v1, $v12, 18
min.qh $v1, $v12, $v18
min.qh $v1, $v12, $v18[2]
msgn.qh $v1, $v12, 18
msgn.qh $v1, $v12, $v18
msgn.qh $v1, $v12, $v18[2]
mul.ob $v1, $v12, 18
mul.ob $v1, $v12, $v18
mul.ob $v1, $v12, $v18[6]
mul.qh $v1, $v12, 18
mul.qh $v1, $v12, $v18
mul.qh $v1, $v12, $v18[2]
mula.ob $v12, 18
mula.ob $v12, $v18
mula.ob $v12, $v18[6]
mula.qh $v12, 18
mula.qh $v12, $v18
mula.qh $v12, $v18[2]
mull.ob $v12, 18
mull.ob $v12, $v18
mull.ob $v12, $v18[6]
mull.qh $v12, 18
mull.qh $v12, $v18
mull.qh $v12, $v18[2]
muls.ob $v12, 18
muls.ob $v12, $v18
muls.ob $v12, $v18[6]
muls.qh $v12, 18
muls.qh $v12, $v18
muls.qh $v12, $v18[2]
mulsl.ob $v12, 18
mulsl.ob $v12, $v18
mulsl.ob $v12, $v18[6]
mulsl.qh $v12, 18
mulsl.qh $v12, $v18
mulsl.qh $v12, $v18[2]
nor.ob $v1, $v12, 18
nor.ob $v1, $v12, $v18
nor.ob $v1, $v12, $v18[6]
nor.qh $v1, $v12, 18
nor.qh $v1, $v12, $v18
nor.qh $v1, $v12, $v18[2]
or.ob $v1, $v12, 18
or.ob $v1, $v12, $v18
or.ob $v1, $v12, $v18[6]
or.qh $v1, $v12, 18
or.qh $v1, $v12, $v18
or.qh $v1, $v12, $v18[2]
pickf.ob $v1, $v12, 18
pickf.ob $v1, $v12, $v18
pickf.ob $v1, $v12, $v18[6]
pickf.qh $v1, $v12, 18
pickf.qh $v1, $v12, $v18
pickf.qh $v1, $v12, $v18[2]
pickt.ob $v1, $v12, 18
pickt.ob $v1, $v12, $v18
pickt.ob $v1, $v12, $v18[6]
pickt.qh $v1, $v12, 18
pickt.qh $v1, $v12, $v18
pickt.qh $v1, $v12, $v18[2]
rach.ob $v1
rach.qh $v1
racl.ob $v1
racl.qh $v1
racm.ob $v1
racm.qh $v1
rnas.qh $v1, 18
rnas.qh $v1, $v18
rnas.qh $v1, $v18[2]
rnau.ob $v1, 18
rnau.ob $v1, $v18
rnau.ob $v1, $v18[6]
rnau.qh $v1, 18
rnau.qh $v1, $v18
rnau.qh $v1, $v18[2]
rnes.qh $v1, 18
rnes.qh $v1, $v18
rnes.qh $v1, $v18[2]
rneu.ob $v1, 18
rneu.ob $v1, $v18
rneu.ob $v1, $v18[6]
rneu.qh $v1, 18
rneu.qh $v1, $v18
rneu.qh $v1, $v18[2]
rzs.qh $v1, 18
rzs.qh $v1, $v18
rzs.qh $v1, $v18[2]
rzu.ob $v1, 18
rzu.ob $v1, $v18
rzu.ob $v1, $v18[6]
rzu.qh $v1, 18
rzu.qh $v1, $v18
rzu.qh $v1, $v18[2]
shfl.bfla.qh $v1, $v12, $v18
shfl.mixh.ob $v1, $v12, $v18
shfl.mixh.qh $v1, $v12, $v18
shfl.mixl.ob $v1, $v12, $v18
shfl.mixl.qh $v1, $v12, $v18
shfl.pach.ob $v1, $v12, $v18
shfl.pach.qh $v1, $v12, $v18
shfl.repa.qh $v1, $v12, $v18
shfl.repb.qh $v1, $v12, $v18
shfl.upsl.ob $v1, $v12, $v18
sll.ob $v1, $v12, 18
sll.ob $v1, $v12, $v18
sll.ob $v1, $v12, $v18[6]
sll.qh $v1, $v12, 18
sll.qh $v1, $v12, $v18
sll.qh $v1, $v12, $v18[2]
sra.qh $v1, $v12, 18
sra.qh $v1, $v12, $v18
sra.qh $v1, $v12, $v18[2]
srl.ob $v1, $v12, 18
srl.ob $v1, $v12, $v18
srl.ob $v1, $v12, $v18[6]
srl.qh $v1, $v12, 18
srl.qh $v1, $v12, $v18
srl.qh $v1, $v12, $v18[2]
sub.ob $v1, $v12, 18
sub.ob $v1, $v12, $v18
sub.ob $v1, $v12, $v18[6]
sub.qh $v1, $v12, 18
sub.qh $v1, $v12, $v18
sub.qh $v1, $v12, $v18[2]
suba.ob $v12, 18
suba.ob $v12, $v18
suba.ob $v12, $v18[6]
suba.qh $v12, 18
suba.qh $v12, $v18
suba.qh $v12, $v18[2]
subl.ob $v12, 18
subl.ob $v12, $v18
subl.ob $v12, $v18[6]
subl.qh $v12, 18
subl.qh $v12, $v18
subl.qh $v12, $v18[2]
wach.ob $v12
wach.qh $v12
wacl.ob $v12, $v18
wacl.qh $v12, $v18
xor.ob $v1, $v12, 18
xor.ob $v1, $v12, $v18
xor.ob $v1, $v12, $v18[6]
xor.qh $v1, $v12, 18
xor.qh $v1, $v12, $v18
xor.qh $v1, $v12, $v18[2]
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,894
|
gas/testsuite/gas/mips/unaligned-branch-r6-1.s
|
.text
.set noreorder
.space 0x1000
.align 4
.set mips32r6
.ent foo
foo:
nor $0, $0
bc bar0
nor $0, $0
beqzc $2, bar0
nor $0, $0
beqz $2, bar0
nor $0, $0
bc bar1
nor $0, $0
beqzc $2, bar1
nor $0, $0
beqz $2, bar1
nor $0, $0
bc bar2
nor $0, $0
beqzc $2, bar2
nor $0, $0
beqz $2, bar2
nor $0, $0
bc bar3
nor $0, $0
beqzc $2, bar3
nor $0, $0
beqz $2, bar3
nor $0, $0
bc bar4
nor $0, $0
beqzc $2, bar4
nor $0, $0
beqz $2, bar4
nor $0, $0
bc bar4 + 1
nor $0, $0
beqzc $2, bar4 + 1
nor $0, $0
beqz $2, bar4 + 1
nor $0, $0
bc bar4 + 2
nor $0, $0
beqzc $2, bar4 + 2
nor $0, $0
beqz $2, bar4 + 2
nor $0, $0
bc bar4 + 3
nor $0, $0
beqzc $2, bar4 + 3
nor $0, $0
beqz $2, bar4 + 3
nor $0, $0
bc bar4 + 4
nor $0, $0
beqzc $2, bar4 + 4
nor $0, $0
beqz $2, bar4 + 4
nor $0, $0
bc bar16
nor $0, $0
beqzc $2, bar16
nor $0, $0
beqz $2, bar16
nor $0, $0
bc bar17
nor $0, $0
beqzc $2, bar17
nor $0, $0
beqz $2, bar17
nor $0, $0
bc bar18
nor $0, $0
beqzc $2, bar18
nor $0, $0
beqz $2, bar18
nor $0, $0
bc bar18 + 1
nor $0, $0
beqzc $2, bar18 + 1
nor $0, $0
beqz $2, bar18 + 1
nor $0, $0
bc bar18 + 2
nor $0, $0
beqzc $2, bar18 + 2
nor $0, $0
beqz $2, bar18 + 2
nor $0, $0
bc bar18 + 3
nor $0, $0
beqzc $2, bar18 + 3
nor $0, $0
beqz $2, bar18 + 3
nor $0, $0
bc bar18 + 4
nor $0, $0
beqzc $2, bar18 + 4
nor $0, $0
beqz $2, bar18 + 4
nor $0, $0
jalr $0, $ra
nor $0, $0
.end foo
.set mips0
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
.set micromips
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,564
|
gas/testsuite/gas/mips/lb.s
|
# Source file used to test the lb macro.
.data
data_label:
.extern big_external_data_label,1000
.extern small_external_data_label,1
.comm big_external_common,1000
.comm small_external_common,1
.lcomm big_local_common,1000
.lcomm small_local_common,1
.text
lb $4,0
lb $4,1
lb $4,0x8000
lb $4,-0x8000
lb $4,0x10000
lb $4,0x1a5a5
lb $4,0($5)
lb $4,1($5)
lb $4,0x8000($5)
lb $4,-0x8000($5)
lb $4,0x10000($5)
lb $4,0x1a5a5($5)
lb $4,data_label
lb $4,big_external_data_label
lb $4,small_external_data_label
lb $4,big_external_common
lb $4,small_external_common
lb $4,big_local_common
lb $4,small_local_common
lb $4,data_label+1
lb $4,big_external_data_label+1
lb $4,small_external_data_label+1
lb $4,big_external_common+1
lb $4,small_external_common+1
lb $4,big_local_common+1
lb $4,small_local_common+1
lb $4,data_label+0x8000
lb $4,big_external_data_label+0x8000
lb $4,small_external_data_label+0x8000
lb $4,big_external_common+0x8000
lb $4,small_external_common+0x8000
lb $4,big_local_common+0x8000
lb $4,small_local_common+0x8000
lb $4,data_label-0x8000
lb $4,big_external_data_label-0x8000
lb $4,small_external_data_label-0x8000
lb $4,big_external_common-0x8000
lb $4,small_external_common-0x8000
lb $4,big_local_common-0x8000
lb $4,small_local_common-0x8000
lb $4,data_label+0x10000
lb $4,big_external_data_label+0x10000
lb $4,small_external_data_label+0x10000
lb $4,big_external_common+0x10000
lb $4,small_external_common+0x10000
lb $4,big_local_common+0x10000
lb $4,small_local_common+0x10000
lb $4,data_label+0x1a5a5
lb $4,big_external_data_label+0x1a5a5
lb $4,small_external_data_label+0x1a5a5
lb $4,big_external_common+0x1a5a5
lb $4,small_external_common+0x1a5a5
lb $4,big_local_common+0x1a5a5
lb $4,small_local_common+0x1a5a5
lb $4,data_label($5)
lb $4,big_external_data_label($5)
lb $4,small_external_data_label($5)
lb $4,big_external_common($5)
lb $4,small_external_common($5)
lb $4,big_local_common($5)
lb $4,small_local_common($5)
lb $4,data_label+1($5)
lb $4,big_external_data_label+1($5)
lb $4,small_external_data_label+1($5)
lb $4,big_external_common+1($5)
lb $4,small_external_common+1($5)
lb $4,big_local_common+1($5)
lb $4,small_local_common+1($5)
lb $4,data_label+0x8000($5)
lb $4,big_external_data_label+0x8000($5)
lb $4,small_external_data_label+0x8000($5)
lb $4,big_external_common+0x8000($5)
lb $4,small_external_common+0x8000($5)
lb $4,big_local_common+0x8000($5)
lb $4,small_local_common+0x8000($5)
lb $4,data_label-0x8000($5)
lb $4,big_external_data_label-0x8000($5)
lb $4,small_external_data_label-0x8000($5)
lb $4,big_external_common-0x8000($5)
lb $4,small_external_common-0x8000($5)
lb $4,big_local_common-0x8000($5)
lb $4,small_local_common-0x8000($5)
lb $4,data_label+0x10000($5)
lb $4,big_external_data_label+0x10000($5)
lb $4,small_external_data_label+0x10000($5)
lb $4,big_external_common+0x10000($5)
lb $4,small_external_common+0x10000($5)
lb $4,big_local_common+0x10000($5)
lb $4,small_local_common+0x10000($5)
lb $4,data_label+0x1a5a5($5)
lb $4,big_external_data_label+0x1a5a5($5)
lb $4,small_external_data_label+0x1a5a5($5)
lb $4,big_external_common+0x1a5a5($5)
lb $4,small_external_common+0x1a5a5($5)
lb $4,big_local_common+0x1a5a5($5)
lb $4,small_local_common+0x1a5a5($5)
# Several macros are handled like lb. Sanity check them.
lbu $4,0
lh $4,0
lhu $4,0
lw $4,0
lwl $4,0
lwr $4,0
lwc0 $4,0
lwc1 $4,0
lwc2 $4,0
lwc3 $4,0
# Round to a 16 byte boundary, for ease in testing multiple targets.
nop
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,854
|
gas/testsuite/gas/mips/usd.s
|
# Source file used to test the usd macro.
.data
data_label:
.extern big_external_data_label,1000
.extern small_external_data_label,1
.comm big_external_common,1000
.comm small_external_common,1
.lcomm big_local_common,1000
.lcomm small_local_common,1
.text
usd $4,0
usd $4,1
usd $4,0x8000
usd $4,-0x8000
usd $4,0x10000
usd $4,0x1a5a5
usd $4,0($5)
usd $4,1($5)
usd $4,data_label
usd $4,big_external_data_label
usd $4,small_external_data_label
usd $4,big_external_common
usd $4,small_external_common
usd $4,big_local_common
usd $4,small_local_common
usd $4,data_label+1
usd $4,big_external_data_label+1
usd $4,small_external_data_label+1
usd $4,big_external_common+1
usd $4,small_external_common+1
usd $4,big_local_common+1
usd $4,small_local_common+1
usd $4,data_label+0x8000
usd $4,big_external_data_label+0x8000
usd $4,small_external_data_label+0x8000
usd $4,big_external_common+0x8000
usd $4,small_external_common+0x8000
usd $4,big_local_common+0x8000
usd $4,small_local_common+0x8000
usd $4,data_label-0x8000
usd $4,big_external_data_label-0x8000
usd $4,small_external_data_label-0x8000
usd $4,big_external_common-0x8000
usd $4,small_external_common-0x8000
usd $4,big_local_common-0x8000
usd $4,small_local_common-0x8000
usd $4,data_label+0x10000
usd $4,big_external_data_label+0x10000
usd $4,small_external_data_label+0x10000
usd $4,big_external_common+0x10000
usd $4,small_external_common+0x10000
usd $4,big_local_common+0x10000
usd $4,small_local_common+0x10000
usd $4,data_label+0x1a5a5
usd $4,big_external_data_label+0x1a5a5
usd $4,small_external_data_label+0x1a5a5
usd $4,big_external_common+0x1a5a5
usd $4,small_external_common+0x1a5a5
usd $4,big_local_common+0x1a5a5
usd $4,small_local_common+0x1a5a5
# Round to a 16 byte boundary, for ease in testing multiple targets.
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 11,088
|
gas/testsuite/gas/mips/eva.s
|
.text
.set nomips16
.set noreorder
test_eva:
lbue $0,-256($2)
lbue $3,-256
lbue $4,255($5)
lbue $6,255
lbue $7,-257($8)
lbue $9,-257
lbue $10,256($11)
lbue $12,256
lbue $13,-512($14)
lbue $15,-512
lbue $16,511($17)
lbue $18,511
lbue $19,-1024($20)
lbue $21,-1024
lbue $22,1023($23)
lbue $24,1023
lbue $25,-2048($26)
lbue $27,-2048
lbue $28,2047($29)
lbue $30,2047
lbue $31,-4096($0)
lbue $2,-4096
lbue $3,4095($4)
lbue $5,4095
lbue $6,-32768($7)
lbue $8,-32768
lbue $9,32767($10)
lbue $11,32767
lbue $12,-32769($13)
lbue $14,-32769
lbue $15,32768($16)
lbue $17,32768
lbue $18,-2147483648($19)
lbue $20,-2147483648
lbue $21,2147483647($22)
lbue $23,2147483647
lbue $24,($25)
lbue $26,MYDATA
lhue $27,-256($28)
lhue $29,-256
lhue $30,255($31)
lhue $0,255
lhue $2,-257($3)
lhue $4,-257
lhue $5,256($6)
lhue $7,256
lhue $8,-512($9)
lhue $10,-512
lhue $11,511($12)
lhue $13,511
lhue $14,-1024($15)
lhue $16,-1024
lhue $17,1023($18)
lhue $19,1023
lhue $20,-2048($21)
lhue $22,-2048
lhue $23,2047($24)
lhue $25,2047
lhue $26,-4096($27)
lhue $28,-4096
lhue $29,4095($30)
lhue $31,4095
lhue $0,-32768($2)
lhue $3,-32768
lhue $4,32767($5)
lhue $6,32767
lhue $7,-32769($8)
lhue $9,-32769
lhue $10,32768($11)
lhue $12,32768
lhue $13,-2147483648($14)
lhue $15,-2147483648
lhue $16,2147483647($17)
lhue $18,2147483647
lhue $19,($20)
lhue $21,MYDATA
lbe $22,-256($23)
lbe $24,-256
lbe $25,255($26)
lbe $27,255
lbe $28,-257($29)
lbe $30,-257
lbe $31,256($0)
lbe $2,256
lbe $3,-512($4)
lbe $5,-512
lbe $6,511($7)
lbe $8,511
lbe $9,-1024($10)
lbe $11,-1024
lbe $12,1023($13)
lbe $14,1023
lbe $15,-2048($16)
lbe $17,-2048
lbe $18,2047($19)
lbe $20,2047
lbe $21,-4096($22)
lbe $23,-4096
lbe $24,4095($25)
lbe $26,4095
lbe $27,-32768($28)
lbe $29,-32768
lbe $30,32767($31)
lbe $0,32767
lbe $2,-32769($3)
lbe $4,-32769
lbe $5,32768($6)
lbe $7,32768
lbe $8,-2147483648($9)
lbe $10,-2147483648
lbe $11,2147483647($12)
lbe $13,2147483647
lbe $14,($15)
lbe $16,MYDATA
lhe $17,-256($18)
lhe $19,-256
lhe $20,255($21)
lhe $22,255
lhe $23,-257($24)
lhe $25,-257
lhe $26,256($27)
lhe $28,256
lhe $29,-512($30)
lhe $31,-512
lhe $0,511($2)
lhe $3,511
lhe $4,-1024($5)
lhe $6,-1024
lhe $7,1023($8)
lhe $9,1023
lhe $10,-2048($11)
lhe $12,-2048
lhe $13,2047($14)
lhe $15,2047
lhe $16,-4096($17)
lhe $18,-4096
lhe $19,4095($20)
lhe $21,4095
lhe $22,-32768($23)
lhe $24,-32768
lhe $25,32767($26)
lhe $27,32767
lhe $28,-32769($29)
lhe $30,-32769
lhe $31,32768($0)
lhe $2,32768
lhe $3,-2147483648($4)
lhe $5,-2147483648
lhe $6,2147483647($7)
lhe $8,2147483647
lhe $9,($10)
lhe $11,MYDATA
lle $12,-256($13)
lle $14,-256
lle $15,255($16)
lle $17,255
lle $18,-257($19)
lle $20,-257
lle $21,256($22)
lle $23,256
lle $24,-512($25)
lle $26,-512
lle $27,511($28)
lle $29,511
lle $30,-1024($31)
lle $0,-1024
lle $2,1023($3)
lle $4,1023
lle $5,-2048($6)
lle $7,-2048
lle $8,2047($9)
lle $10,2047
lle $11,-4096($12)
lle $13,-4096
lle $14,4095($15)
lle $16,4095
lle $17,-32768($18)
lle $19,-32768
lle $20,32767($21)
lle $22,32767
lle $23,-32769($24)
lle $25,-32769
lle $26,32768($27)
lle $28,32768
lle $29,-2147483648($30)
lle $31,-2147483648
lle $0,2147483647($2)
lle $3,2147483647
lle $4,($5)
lle $6,MYDATA
lwe $7,-256($8)
lwe $9,-256
lwe $10,255($11)
lwe $12,255
lwe $13,-257($14)
lwe $15,-257
lwe $16,256($17)
lwe $18,256
lwe $19,-512($20)
lwe $21,-512
lwe $22,511($23)
lwe $24,511
lwe $25,-1024($26)
lwe $27,-1024
lwe $28,1023($29)
lwe $30,1023
lwe $31,-2048($0)
lwe $2,-2048
lwe $3,2047($4)
lwe $5,2047
lwe $6,-4096($7)
lwe $8,-4096
lwe $9,4095($10)
lwe $11,4095
lwe $12,-32768($13)
lwe $14,-32768
lwe $15,32767($16)
lwe $17,32767
lwe $18,-32769($19)
lwe $20,-32769
lwe $21,32768($22)
lwe $23,32768
lwe $24,-2147483648($25)
lwe $26,-2147483648
lwe $27,2147483647($28)
lwe $29,2147483647
lwe $30,($31)
lwe $0,MYDATA
.ifndef r6
lwle $2,-256($3)
lwle $4,-256
lwle $5,255($6)
lwle $7,255
lwle $8,-257($9)
lwle $10,-257
lwle $11,256($12)
lwle $13,256
lwle $14,-512($15)
lwle $16,-512
lwle $17,511($18)
lwle $19,511
lwle $20,-1024($21)
lwle $22,-1024
lwle $23,1023($24)
lwle $25,1023
lwle $26,-2048($27)
lwle $28,-2048
lwle $29,2047($30)
lwle $31,2047
lwle $0,-4096($2)
lwle $3,-4096
lwle $4,4095($5)
lwle $6,4095
lwle $7,-32768($8)
lwle $9,-32768
lwle $10,32767($11)
lwle $12,32767
lwle $13,-32769($14)
lwle $15,-32769
lwle $16,32768($17)
lwle $18,32768
lwle $19,-2147483648($20)
lwle $21,-2147483648
lwle $22,2147483647($23)
lwle $24,2147483647
lwle $25,($26)
lwle $27,MYDATA
lwre $28,-256($29)
lwre $30,-256
lwre $31,255($0)
lwre $2,255
lwre $3,-257($4)
lwre $5,-257
lwre $6,256($7)
lwre $8,256
lwre $9,-512($10)
lwre $11,-512
lwre $12,511($13)
lwre $14,511
lwre $15,-1024($16)
lwre $17,-1024
lwre $18,1023($19)
lwre $20,1023
lwre $21,-2048($22)
lwre $23,-2048
lwre $24,2047($25)
lwre $26,2047
lwre $27,-4096($28)
lwre $29,-4096
lwre $30,4095($31)
lwre $0,4095
lwre $2,-32768($3)
lwre $4,-32768
lwre $5,32767($6)
lwre $7,32767
lwre $8,-32769($9)
lwre $10,-32769
lwre $11,32768($12)
lwre $13,32768
lwre $14,-2147483648($15)
lwre $16,-2147483648
lwre $17,2147483647($18)
lwre $19,2147483647
lwre $20,($21)
lwre $22,MYDATA
.endif
sbe $23,-256($24)
sbe $25,-256
sbe $26,255($27)
sbe $28,255
sbe $29,-257($30)
sbe $31,-257
sbe $0,256($2)
sbe $3,256
sbe $4,-512($5)
sbe $6,-512
sbe $7,511($8)
sbe $9,511
sbe $10,-1024($11)
sbe $12,-1024
sbe $13,1023($14)
sbe $15,1023
sbe $16,-2048($17)
sbe $18,-2048
sbe $19,2047($20)
sbe $21,2047
sbe $22,-4096($23)
sbe $24,-4096
sbe $25,4095($26)
sbe $27,4095
sbe $28,-32768($29)
sbe $30,-32768
sbe $31,32767($0)
sbe $2,32767
sbe $3,-32769($4)
sbe $5,-32769
sbe $6,32768($7)
sbe $8,32768
sbe $9,-2147483648($10)
sbe $11,-2147483648
sbe $12,2147483647($13)
sbe $14,2147483647
sbe $15,($16)
sbe $17,MYDATA
sce $18,-256($19)
sce $20,-256
sce $21,255($22)
sce $23,255
sce $24,-257($25)
sce $26,-257
sce $27,256($28)
sce $29,256
sce $30,-512($31)
sce $0,-512
sce $2,511($3)
sce $4,511
sce $5,-1024($6)
sce $7,-1024
sce $8,1023($9)
sce $10,1023
sce $11,-2048($12)
sce $13,-2048
sce $14,2047($15)
sce $16,2047
sce $17,-4096($18)
sce $19,-4096
sce $20,4095($21)
sce $22,4095
sce $23,-32768($24)
sce $25,-32768
sce $26,32767($27)
sce $28,32767
sce $29,-32769($30)
sce $31,-32769
sce $0,32768($2)
sce $3,32768
sce $4,-2147483648($5)
sce $6,-2147483648
sce $7,2147483647($8)
sce $9,2147483647
sce $10,($11)
sce $12,MYDATA
she $13,-256($14)
she $15,-256
she $16,255($17)
she $18,255
she $19,-257($20)
she $21,-257
she $22,256($23)
she $24,256
she $25,-512($26)
she $27,-512
she $28,511($29)
she $30,511
she $31,-1024($0)
she $2,-1024
she $3,1023($4)
she $5,1023
she $6,-2048($7)
she $8,-2048
she $9,2047($10)
she $11,2047
she $12,-4096($13)
she $14,-4096
she $15,4095($16)
she $17,4095
she $18,-32768($19)
she $20,-32768
she $21,32767($22)
she $23,32767
she $24,-32769($25)
she $26,-32769
she $27,32768($28)
she $29,32768
she $30,-2147483648($31)
she $0,-2147483648
she $2,2147483647($3)
she $4,2147483647
she $5,($6)
she $7,MYDATA
swe $8,-256($9)
swe $10,-256
swe $11,255($12)
swe $13,255
swe $14,-257($15)
swe $16,-257
swe $17,256($18)
swe $19,256
swe $20,-512($21)
swe $22,-512
swe $23,511($24)
swe $25,511
swe $26,-1024($27)
swe $28,-1024
swe $29,1023($30)
swe $31,1023
swe $0,-2048($2)
swe $3,-2048
swe $4,2047($5)
swe $6,2047
swe $7,-4096($8)
swe $9,-4096
swe $10,4095($11)
swe $12,4095
swe $13,-32768($14)
swe $15,-32768
swe $16,32767($17)
swe $18,32767
swe $19,-32769($20)
swe $21,-32769
swe $22,32768($23)
swe $24,32768
swe $25,-2147483648($26)
swe $27,-2147483648
swe $28,2147483647($29)
swe $30,2147483647
swe $31,($0)
swe $2,MYDATA
.ifndef r6
swle $3,-256($4)
swle $5,-256
swle $6,255($7)
swle $8,255
swle $9,-257($10)
swle $11,-257
swle $12,256($13)
swle $14,256
swle $15,-512($16)
swle $17,-512
swle $18,511($19)
swle $20,511
swle $21,-1024($22)
swle $23,-1024
swle $24,1023($25)
swle $26,1023
swle $27,-2048($28)
swle $29,-2048
swle $30,2047($31)
swle $0,2047
swle $2,-4096($3)
swle $4,-4096
swle $5,4095($6)
swle $7,4095
swle $8,-32768($9)
swle $10,-32768
swle $11,32767($12)
swle $13,32767
swle $14,-32769($15)
swle $16,-32769
swle $17,32768($18)
swle $19,32768
swle $20,-2147483648($21)
swle $22,-2147483648
swle $23,2147483647($24)
swle $25,2147483647
swle $26,($27)
swle $28,MYDATA
swre $29,-256($30)
swre $31,-256
swre $0,255($2)
swre $3,255
swre $4,-257($5)
swre $6,-257
swre $7,256($8)
swre $9,256
swre $10,-512($11)
swre $12,-512
swre $13,511($14)
swre $15,511
swre $16,-1024($17)
swre $18,-1024
swre $19,1023($20)
swre $21,1023
swre $22,-2048($23)
swre $24,-2048
swre $25,2047($26)
swre $27,2047
swre $28,-4096($29)
swre $30,-4096
swre $31,4095($0)
swre $2,4095
swre $3,-32768($4)
swre $5,-32768
swre $6,32767($7)
swre $8,32767
swre $9,-32769($10)
swre $11,-32769
swre $12,32768($13)
swre $14,32768
swre $15,-2147483648($16)
swre $17,-2147483648
swre $18,2147483647($19)
swre $20,2147483647
swre $21,($22)
swre $23,MYDATA
.endif
cachee 24,-256($25)
cachee 26,-256
cachee 27,255($28)
cachee 29,255
cachee 30,-257($31)
cachee 0,-257
cachee 2,256($3)
cachee 4,256
cachee 5,-512($6)
cachee 7,-512
cachee 8,511($9)
cachee 10,511
cachee 11,-1024($12)
cachee 13,-1024
cachee 14,1023($15)
cachee 16,1023
cachee 17,-2048($18)
cachee 19,-2048
cachee 20,2047($21)
cachee 22,2047
cachee 23,-4096($24)
cachee 25,-4096
cachee 26,4095($27)
cachee 28,4095
cachee 29,-32768($30)
cachee 31,-32768
cachee 0,32767($2)
cachee 3,32767
cachee 4,-32769($5)
cachee 6,-32769
cachee 7,32768($8)
cachee 9,32768
cachee 10,-2147483648($11)
cachee 12,-2147483648
cachee 13,2147483647($14)
cachee 15,2147483647
cachee 16,($17)
cachee 18,MYDATA
prefe 19,-256($20)
prefe 21,-256
prefe 22,255($23)
prefe 24,255
prefe 25,-257($26)
prefe 27,-257
prefe 28,256($29)
prefe 30,256
prefe 31,-512($0)
prefe 2,-512
prefe 3,511($4)
prefe 5,511
prefe 6,-1024($7)
prefe 8,-1024
prefe 9,1023($10)
prefe 11,1023
prefe 12,-2048($13)
prefe 14,-2048
prefe 15,2047($16)
prefe 17,2047
prefe 18,-4096($19)
prefe 20,-4096
prefe 21,4095($22)
prefe 23,4095
prefe 24,-32768($25)
prefe 26,-32768
prefe 27,32767($28)
prefe 29,32767
prefe 30,-32769($31)
prefe 0,-32769
prefe 2,32768($3)
prefe 4,32768
prefe 5,-2147483648($6)
prefe 7,-2147483648
prefe 8,2147483647($9)
prefe 10,2147483647
prefe 11,($12)
prefe 13,MYDATA
prefe 5,%lo(foo)($6)
.ifdef r6
llwpe $2, $3, 0x1234
llwpe $2, $0, 0xabcd($0)
llwpe $0, $3, %lo(sync_mem)
llwpe $2, $2, 0xffffffff01234567($0)
llwpe $0, $0, sync_mem
scwpe $2, $3, 0x1234
scwpe $2, $0, 0xabcd($0)
scwpe $0, $3, %lo(sync_mem)
scwpe $2, $2, 0xffffffff01234567($0)
scwpe $0, $0, sync_mem
.endif
|
tactcomplabs/xbgas-binutils-gdb
| 1,506
|
gas/testsuite/gas/mips/24k-triple-stores-3.s
|
# Assume to be on the same line (within 32bytes)
# Check for individual different double words
foo:
# safe
sb $2,11($sp)
sb $3,11($sp)
sb $4,4($sp)
break
# safe
sb $2,0($sp)
sb $3,11($sp)
sb $4,5($sp)
break
# edge case
sb $2,7($sp)
sb $3,11($sp)
sb $4,16($sp)
break
# edge case (unaligned)
sb $2,0($8)
sb $3,8($8)
sb $4,9($8)
break
sh $2,0($sp)
sh $3,-31($sp)
sh $4,-30($sp)
break
# edge case
sh $2,6($sp)
sh $3,8($sp)
sh $4,16($sp)
break
# edge case (unaligned)
sh $2,1($8)
sh $3,3($8)
sh $4,11($8)
break
sw $2,8($sp)
sw $3,-8($sp)
sw $4,8($sp)
break
# edge case
sw $2,4($sp)
sw $3,8($sp)
sw $4,16($sp)
break
# edge case (unaligned)
sw $2,3($8)
sw $3,7($8)
sw $4,15($8)
break
.ifndef r6
swl $2,4($sp)
swl $3,10($sp)
swl $4,17($sp)
break
# edge case
swl $2,7($sp)
swl $3,12($sp)
swl $4,16($sp)
break
# edge case
swl $2,0($sp)
swl $3,12($sp)
swl $4,23($sp)
break
# edge case (unaligned)
swl $2,3($8)
swl $3,8($8)
swl $4,12($8)
break
# mix swl & swr
swl $2,0($sp)
swl $3,12($sp)
swr $4,23($sp)
break
# mix swl & swr
swl $2,5($8)
swl $3,17($8)
swr $4,28($8)
break
.endif
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 4,380
|
gas/testsuite/gas/mips/mips-gp64-fp32-pic.s
|
.sdata
shared: .word 11
.data
unshared:
.word 1
.word 2
.word 3
.word 4
.text
.ent func
func:
.frame $sp,0,$31
.set noreorder
.cpload $25 # 0000 lui gp,hi(_gp_disp)
# 0004 addiu gp,gp,lo(_gp_disp)
# 0008 addu gp,gp,t9
.set reorder
.cprestore 8 # 000c sw gp,8(sp)
.cpadd $4 # 0010 addu a0,a0,gp
li $4, 0x12345678 # 0014 lui a0,0x1234
# 0018 ori a0,a0,0x5678
la $4, shared # 001c lw a0,got(.sdata)(gp)
# 0020 nop
# 0024 addiu a0,a0,lo(shared)
la $4, unshared # 0028 lw a0,got(.data)(gp)
# 002c nop
# 0030 addiu a0,a0,lo(unshared)
la $4, end # 0034 lw a0,got(.text)(gp)
# 0038 nop
# 003c addiu a0,a0,lo(end)
j end # 0040 b end
# 0044 nop
jal end # 0048 lw t9,got(.text)(gp)
# 004c nop
# 0050 addiu t9,t9,lo(end)
# 0054 jalr t9
# 0058 nop
# 005c lw gp,8(sp)
lw $4, shared # 0060 lw a0,got(.sdata)(gp)
# 0064 nop
# 0068 addiu a0,a0,lo(shared)
# 006c lw a0,(a0)
lw $4, unshared # 0070 lw a0,got(.data)(gp)
# 0074 nop
# 0078 addiu a0,a0,lo(unshared)
# 007c lw a0,(a0)
lw $4, end # 0080 lw a0,got(.text)(gp)
# 0084 nop
# 0088 addiu a0,a0,lo(end)
# 008c lw a0,(a0)
ld $4, shared # 0090 lw a0,got(.sdata)(gp)
# 0094 nop
# 0098 addiu a0,a0,lo(shared)
# 009c ld a0,(a0)
ld $4, unshared # 00a0 lw a0,got(.data)(gp)
# 00a4 nop
# 00a8 addiu a0,a0,lo(unshared)
# 00ac ld a0,(a0)
ld $4, end # 00b0 lw a0,got(.text)(gp)
# 00b4 nop
# 00b8 addiu a0,a0,lo(end)
# 00bc ld a0,(a0)
sw $4, shared # 00c0 lw at,got(.sdata)(gp)
# 00c4 nop
# 00c8 addiu at,at,lo(shared)
# 00cc sw a0,0(at)
sw $4, unshared # 00d0 lw at,got(.data)(gp)
# 00d4 nop
# 00d8 addiu at,at,lo(unshared)
# 00dc sw a0,0(at)
sd $4, shared # 00e0 lw at,got(.sdata)(gp)
# 00e4 nop
# 00e8 addiu at,at,lo(shared)
# 00ec sd a0,(at)
sd $4, unshared # 00f0 lw at,got(.data)(gp)
# 00f4 nop
# 00f8 addiu at,at,lo(unshared)
# 00fc sd a0,(at)
ulh $4, unshared # 0100 lw at,got(.data)(gp)
# 0104 nop
# 0108 addiu at,at,lo(unshared)
# 010c lb a0,0(at)
# 0110 lbu at,1(at)
# 0114 sll a0,a0,8
# 0118 or a0,a0,at
ush $4, unshared # 011c lw at,got(.data)(gp)
# 0120 nop
# 0124 addiu at,at,lo(unshared)
# 0128 sb a0,0(at)
# 012c srl a0,a0,8
# 0130 sb a0,1(at)
# 0134 lbu at,0(at)
# 0138 sll a0,a0,8
# 013c or a0,a0,at
ulw $4, unshared # 0140 lw at,got(.data)(gp)
# 0144 nop
# 0148 addiu at,at,lo(unshared)
# 014c lwl a0,0(at)
# 0150 lwr a0,3(at)
usw $4, unshared # 0154 lw at,got(.data)(gp)
# 0158 nop
# 015c addiu at,at,lo(unshared)
# 0160 swl a0,0(at)
# 0164 swr a0,3(at)
li.d $4, 1.0 # 0168 li a0,0xffc0
# 016c dsll32 a0,a0,14
li.d $4, 1.9 # 0170 lw at,got(.rodata)(gp)
# 0174 ld a0,lo(F1.9)(at)
li.d $f0, 1.0 # 0178 lui at,0x3ff0
# 017c mtc1 at,$f1
# 0180 mtc1 zero,$f0
li.d $f0, 1.9 # 0184 lw at,got(.rodata)(gp)
# 0188 ldc1 $f0,lo(L1.9)(at)
seq $4, $5, -100 # 018c daddiu a0,a1,100
# 0190 sltiu a0,a0,1
sne $4, $5, -100 # 0194 daddiu a0,a1,100
# 0198 sltu a0,zero,a0
move $4, $5 # 019c move a0,a1
dla $4, shared # 01a0 lw a0,got(.sdata)(gp)
# 01a4 nop
# 01a8 addiu a0,a0,lo(shared)
dla $4, unshared # 01ac lw a0,got(.data)(gp)
# 01b0 nop
# 01b4 addiu a0,a0,lo(unshared)
uld $4, unshared # 01b8 lw at,got(.data)(gp)
# 01bc nop
# 01c0 addiu at,at,lo(unshared)
# 01c4 ldl a0,0(at)
# 01c8 ldr a0,7(at)
usd $4, unshared # 01cc lw at,got(.data)(gp)
# 01d0 nop
# 01d4 addiu at,at,lo(unshared)
# 01d8 sdl a0,0(at)
# 01dc sdr a0,7(at)
bgt $4, 0x7fffffff, end # 01e0 li at,0x8000
# 01e4 dsll at,at,0x10
# 01e8 slt at,a0,at
# 01ec beqz at,end
# 01f0 nop
bgtu $4, 0xffffffff, end # 01f4 li at,0x8000
# 01f8 dsll at,at,17
# 01fc sltu at,a0,at
# 0200 beqz at,end
# 0204 nop
ble $4, 0x7fffffff, end # 0208 li at,0x8000
# 020c dsll at,at,0x10
# 0210 slt at,a0,at
# 0214 bnez at,end
# 0218 nop
bleu $4, 0xffffffff, end # 021c li at,0x8000
# 0220 dsll at,at,17
# 0224 sltu at,a0,at
# 0228 bnez at,end
# 022c nop
# Should produce warnings given -mfp32
# add.d $f1, $f2, $f3
.end func
end:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 9,367
|
gas/testsuite/gas/mips/mips16-hilo.s
|
# Source file used to test li/addi on MIPS16
.set mips16
.data
data_label:
.word 0
data_label2:
.word 0
.extern big_external_data_label,1000
.extern small_external_data_label,1
.comm big_external_common,1000
.comm small_external_common,1
.lcomm big_local_common,1000
.lcomm small_local_common,1
.text
stuff:
li $4,%hi(0)
sll $4,16
addiu $4,%lo(0)
li $4,%hi(data_label)
sll $4,16
addiu $4,%lo(data_label)
li $4,%hi(data_label2)
sll $4,16
addiu $4,%lo(data_label2)
li $4,%hi(big_external_data_label)
sll $4,16
addiu $4,%lo(big_external_data_label)
li $4,%hi(small_external_data_label)
sll $4,16
addiu $4,%lo(small_external_data_label)
li $4,%hi(big_external_common)
sll $4,16
addiu $4,%lo(big_external_common)
li $4,%hi(small_external_common)
sll $4,16
addiu $4,%lo(small_external_common)
li $4,%hi(big_local_common)
sll $4,16
addiu $4,%lo(big_local_common)
li $4,%hi(small_local_common)
sll $4,16
addiu $4,%lo(small_local_common)
li $4,%hi(1)
sll $4,16
addiu $4,%lo(1)
li $4,%hi(data_label+1)
sll $4,16
addiu $4,%lo(data_label+1)
li $4,%hi(data_label2+1)
sll $4,16
addiu $4,%lo(data_label2+1)
li $4,%hi(big_external_data_label+1)
sll $4,16
addiu $4,%lo(big_external_data_label+1)
li $4,%hi(small_external_data_label+1)
sll $4,16
addiu $4,%lo(small_external_data_label+1)
li $4,%hi(big_external_common+1)
sll $4,16
addiu $4,%lo(big_external_common+1)
li $4,%hi(small_external_common+1)
sll $4,16
addiu $4,%lo(small_external_common+1)
li $4,%hi(big_local_common+1)
sll $4,16
addiu $4,%lo(big_local_common+1)
li $4,%hi(small_local_common+1)
sll $4,16
addiu $4,%lo(small_local_common+1)
li $4,%hi(0x8000)
sll $4,16
addiu $4,%lo(0x8000)
li $4,%hi(data_label+0x8000)
sll $4,16
addiu $4,%lo(data_label+0x8000)
li $4,%hi(data_label2+0x8000)
sll $4,16
addiu $4,%lo(data_label2+0x8000)
li $4,%hi(big_external_data_label+0x8000)
sll $4,16
addiu $4,%lo(big_external_data_label+0x8000)
li $4,%hi(small_external_data_label+0x8000)
sll $4,16
addiu $4,%lo(small_external_data_label+0x8000)
li $4,%hi(big_external_common+0x8000)
sll $4,16
addiu $4,%lo(big_external_common+0x8000)
li $4,%hi(small_external_common+0x8000)
sll $4,16
addiu $4,%lo(small_external_common+0x8000)
li $4,%hi(big_local_common+0x8000)
sll $4,16
addiu $4,%lo(big_local_common+0x8000)
li $4,%hi(small_local_common+0x8000)
sll $4,16
addiu $4,%lo(small_local_common+0x8000)
li $4,%hi(-0x8000)
sll $4,16
addiu $4,%lo(-0x8000)
li $4,%hi(data_label-0x8000)
sll $4,16
addiu $4,%lo(data_label-0x8000)
li $4,%hi(data_label2-0x8000)
sll $4,16
addiu $4,%lo(data_label2-0x8000)
li $4,%hi(big_external_data_label-0x8000)
sll $4,16
addiu $4,%lo(big_external_data_label-0x8000)
li $4,%hi(small_external_data_label-0x8000)
sll $4,16
addiu $4,%lo(small_external_data_label-0x8000)
li $4,%hi(big_external_common-0x8000)
sll $4,16
addiu $4,%lo(big_external_common-0x8000)
li $4,%hi(small_external_common-0x8000)
sll $4,16
addiu $4,%lo(small_external_common-0x8000)
li $4,%hi(big_local_common-0x8000)
sll $4,16
addiu $4,%lo(big_local_common-0x8000)
li $4,%hi(small_local_common-0x8000)
sll $4,16
addiu $4,%lo(small_local_common-0x8000)
li $4,%hi(0x10000)
sll $4,16
addiu $4,%lo(0x10000)
li $4,%hi(data_label+0x10000)
sll $4,16
addiu $4,%lo(data_label+0x10000)
li $4,%hi(data_label2+0x10000)
sll $4,16
addiu $4,%lo(data_label2+0x10000)
li $4,%hi(big_external_data_label+0x10000)
sll $4,16
addiu $4,%lo(big_external_data_label+0x10000)
li $4,%hi(small_external_data_label+0x10000)
sll $4,16
addiu $4,%lo(small_external_data_label+0x10000)
li $4,%hi(big_external_common+0x10000)
sll $4,16
addiu $4,%lo(big_external_common+0x10000)
li $4,%hi(small_external_common+0x10000)
sll $4,16
addiu $4,%lo(small_external_common+0x10000)
li $4,%hi(big_local_common+0x10000)
sll $4,16
addiu $4,%lo(big_local_common+0x10000)
li $4,%hi(small_local_common+0x10000)
sll $4,16
addiu $4,%lo(small_local_common+0x10000)
li $4,%hi(0x1a5a5)
sll $4,16
addiu $4,%lo(0x1a5a5)
li $4,%hi(data_label+0x1a5a5)
sll $4,16
addiu $4,%lo(data_label+0x1a5a5)
li $4,%hi(data_label2+0x1a5a5)
sll $4,16
addiu $4,%lo(data_label2+0x1a5a5)
li $4,%hi(big_external_data_label+0x1a5a5)
sll $4,16
addiu $4,%lo(big_external_data_label+0x1a5a5)
li $4,%hi(small_external_data_label+0x1a5a5)
sll $4,16
addiu $4,%lo(small_external_data_label+0x1a5a5)
li $4,%hi(big_external_common+0x1a5a5)
sll $4,16
addiu $4,%lo(big_external_common+0x1a5a5)
li $4,%hi(small_external_common+0x1a5a5)
sll $4,16
addiu $4,%lo(small_external_common+0x1a5a5)
li $4,%hi(big_local_common+0x1a5a5)
sll $4,16
addiu $4,%lo(big_local_common+0x1a5a5)
li $4,%hi(small_local_common+0x1a5a5)
sll $4,16
addiu $4,%lo(small_local_common+0x1a5a5)
li $5,%hi(0)
sll $5,16
lw $4,%hi(0)($5)
li $5,%hi(data_label)
sll $5,16
lw $4,%hi(data_label)($5)
li $5,%hi(data_label2)
sll $5,16
lw $4,%hi(data_label2)($5)
li $5,%hi(big_external_data_label)
sll $5,16
lw $4,%lo(big_external_data_label)($5)
li $5,%hi(small_external_data_label)
sll $5,16
lw $4,%lo(small_external_data_label)($5)
li $5,%hi(big_external_common)
sll $5,16
lw $4,%lo(big_external_common)($5)
li $5,%hi(small_external_common)
sll $5,16
lw $4,%lo(small_external_common)($5)
li $5,%hi(big_local_common)
sll $5,16
lw $4,%lo(big_local_common)($5)
li $5,%hi(small_local_common)
sll $5,16
lw $4,%lo(small_local_common)($5)
li $5,%hi(1)
sll $5,16
lw $4,%lo(1)($5)
li $5,%hi(data_label+1)
sll $5,16
lw $4,%lo(data_label+1)($5)
li $5,%hi(data_label2+1)
sll $5,16
lw $4,%lo(data_label2+1)($5)
li $5,%hi(big_external_data_label+1)
sll $5,16
lw $4,%lo(big_external_data_label+1)($5)
li $5,%hi(small_external_data_label+1)
sll $5,16
lw $4,%lo(small_external_data_label+1)($5)
li $5,%hi(big_external_common+1)
sll $5,16
lw $4,%lo(big_external_common+1)($5)
li $5,%hi(small_external_common+1)
sll $5,16
lw $4,%lo(small_external_common+1)($5)
li $5,%hi(big_local_common+1)
sll $5,16
lw $4,%lo(big_local_common+1)($5)
li $5,%hi(small_local_common+1)
sll $5,16
lw $4,%lo(small_local_common+1)($5)
li $5,%hi(0x8000)
sll $5,16
lw $4,%lo(0x8000)($5)
li $5,%hi(data_label+0x8000)
sll $5,16
lw $4,%lo(data_label+0x8000)($5)
li $5,%hi(data_label2+0x8000)
sll $5,16
lw $4,%lo(data_label2+0x8000)($5)
li $5,%hi(big_external_data_label+0x8000)
sll $5,16
lw $4,%lo(big_external_data_label+0x8000)($5)
li $5,%hi(small_external_data_label+0x8000)
sll $5,16
lw $4,%lo(small_external_data_label+0x8000)($5)
li $5,%hi(big_external_common+0x8000)
sll $5,16
lw $4,%lo(big_external_common+0x8000)($5)
li $5,%hi(small_external_common+0x8000)
sll $5,16
lw $4,%lo(small_external_common+0x8000)($5)
li $5,%hi(big_local_common+0x8000)
sll $5,16
lw $4,%lo(big_local_common+0x8000)($5)
li $5,%hi(small_local_common+0x8000)
sll $5,16
lw $4,%lo(small_local_common+0x8000)($5)
li $5,%hi(-0x8000)
sll $5,16
lw $4,%lo(-0x8000)($5)
li $5,%hi(data_label-0x8000)
sll $5,16
lw $4,%lo(data_label-0x8000)($5)
li $5,%hi(data_label2-0x8000)
sll $5,16
lw $4,%lo(data_label2-0x8000)($5)
li $5,%hi(big_external_data_label-0x8000)
sll $5,16
lw $4,%lo(big_external_data_label-0x8000)($5)
li $5,%hi(small_external_data_label-0x8000)
sll $5,16
lw $4,%lo(small_external_data_label-0x8000)($5)
li $5,%hi(big_external_common-0x8000)
sll $5,16
lw $4,%lo(big_external_common-0x8000)($5)
li $5,%hi(small_external_common-0x8000)
sll $5,16
lw $4,%lo(small_external_common-0x8000)($5)
li $5,%hi(big_local_common-0x8000)
sll $5,16
lw $4,%lo(big_local_common-0x8000)($5)
li $5,%hi(small_local_common-0x8000)
sll $5,16
lw $4,%lo(small_local_common-0x8000)($5)
li $5,%hi(0x10000)
sll $5,16
lw $4,%lo(0x10000)($5)
li $5,%hi(data_label+0x10000)
sll $5,16
lw $4,%lo(data_label+0x10000)($5)
li $5,%hi(data_label2+0x10000)
sll $5,16
lw $4,%lo(data_label2+0x10000)($5)
li $5,%hi(big_external_data_label+0x10000)
sll $5,16
lw $4,%lo(big_external_data_label+0x10000)($5)
li $5,%hi(small_external_data_label+0x10000)
sll $5,16
lw $4,%lo(small_external_data_label+0x10000)($5)
li $5,%hi(big_external_common+0x10000)
sll $5,16
lw $4,%lo(big_external_common+0x10000)($5)
li $5,%hi(small_external_common+0x10000)
sll $5,16
lw $4,%lo(small_external_common+0x10000)($5)
li $5,%hi(big_local_common+0x10000)
sll $5,16
lw $4,%lo(big_local_common+0x10000)($5)
li $5,%hi(small_local_common+0x10000)
sll $5,16
lw $4,%lo(small_local_common+0x10000)($5)
li $5,%hi(0x1a5a5)
sll $5,16
lw $4,%lo(0x1a5a5)($5)
li $5,%hi(data_label+0x1a5a5)
sll $5,16
lw $4,%lo(data_label+0x1a5a5)($5)
li $5,%hi(data_label2+0x1a5a5)
sll $5,16
lw $4,%lo(data_label2+0x1a5a5)($5)
li $5,%hi(big_external_data_label+0x1a5a5)
sll $5,16
lw $4,%lo(big_external_data_label+0x1a5a5)($5)
li $5,%hi(small_external_data_label+0x1a5a5)
sll $5,16
lw $4,%lo(small_external_data_label+0x1a5a5)($5)
li $5,%hi(big_external_common+0x1a5a5)
sll $5,16
lw $4,%lo(big_external_common+0x1a5a5)($5)
li $5,%hi(small_external_common+0x1a5a5)
sll $5,16
lw $4,%lo(small_external_common+0x1a5a5)($5)
li $5,%hi(big_local_common+0x1a5a5)
sll $5,16
lw $4,%lo(big_local_common+0x1a5a5)($5)
li $5,%hi(small_local_common+0x1a5a5)
sll $5,16
lw $4,%lo(small_local_common+0x1a5a5)($5)
# align section end to 16-byte boundary for easier testing on multiple targets
.p2align 4
|
tactcomplabs/xbgas-binutils-gdb
| 2,729
|
gas/testsuite/gas/mips/unaligned-branch-micromips-1.s
|
.text
.set noreorder
.space 0x1000
.align 4
.set micromips
.ent foo
foo:
not $2, $3
bal bar0
not $2, $3
bal bar1
not $2, $3
bal bar2
not $2, $3
bal bar3
not $2, $3
bal bar4
not $2, $3
bal bar4 + 1
not $2, $3
bal bar4 + 2
not $2, $3
bal bar4 + 3
not $2, $3
bal bar4 + 4
not $2, $3
bal bar16
not $2, $3
bal bar17
not $2, $3
bal bar18
not $2, $3
bal bar18 + 1
not $2, $3
bal bar18 + 2
not $2, $3
bal bar18 + 3
not $2, $3
bal bar18 + 4
not $2, $3
bals bar0
not $2, $3
bals bar1
not $2, $3
bals bar2
not $2, $3
bals bar3
not $2, $3
bals bar4
not $2, $3
bals bar4 + 1
not $2, $3
bals bar4 + 2
not $2, $3
bals bar4 + 3
not $2, $3
bals bar4 + 4
not $2, $3
bals bar16
not $2, $3
bals bar17
not $2, $3
bals bar18
not $2, $3
bals bar18 + 1
not $2, $3
bals bar18 + 2
not $2, $3
bals bar18 + 3
not $2, $3
bals bar18 + 4
not $2, $3
bne $2, $3, bar0
not $2, $3
bne $2, $3, bar1
not $2, $3
bne $2, $3, bar2
not $2, $3
bne $2, $3, bar3
not $2, $3
bne $2, $3, bar4
not $2, $3
bne $2, $3, bar4 + 1
not $2, $3
bne $2, $3, bar4 + 2
not $2, $3
bne $2, $3, bar4 + 3
not $2, $3
bne $2, $3, bar4 + 4
not $2, $3
bne $2, $3, bar16
not $2, $3
bne $2, $3, bar17
not $2, $3
bne $2, $3, bar18
not $2, $3
bne $2, $3, bar18 + 1
not $2, $3
bne $2, $3, bar18 + 2
not $2, $3
bne $2, $3, bar18 + 3
not $2, $3
bne $2, $3, bar18 + 4
not $2, $3
b bar0
not $2, $3
b bar1
not $2, $3
b bar2
not $2, $3
b bar3
not $2, $3
b bar4
not $2, $3
b bar4 + 1
not $2, $3
b bar4 + 2
not $2, $3
b bar4 + 3
not $2, $3
b bar4 + 4
not $2, $3
b bar16
not $2, $3
b bar17
not $2, $3
b bar18
not $2, $3
b bar18 + 1
not $2, $3
b bar18 + 2
not $2, $3
b bar18 + 3
not $2, $3
b bar18 + 4
not $2, $3
bnez $2, bar0
not $2, $3
bnez $2, bar1
not $2, $3
bnez $2, bar2
not $2, $3
bnez $2, bar3
not $2, $3
bnez $2, bar4
not $2, $3
bnez $2, bar4 + 1
not $2, $3
bnez $2, bar4 + 2
not $2, $3
bnez $2, bar4 + 3
not $2, $3
bnez $2, bar4 + 4
not $2, $3
bnez $2, bar16
not $2, $3
bnez $2, bar17
not $2, $3
bnez $2, bar18
not $2, $3
bnez $2, bar18 + 1
not $2, $3
bnez $2, bar18 + 2
not $2, $3
bnez $2, bar18 + 3
not $2, $3
bnez $2, bar18 + 4
not $2, $3
jalr $0, $ra
not $2, $3
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,707
|
gas/testsuite/gas/mips/unaligned-jump-1.s
|
.text
.set noreorder
.space 0x1000
.align 4
.ent foo
foo:
nor $0, $0
jalx bar0
nor $0, $0
jal bar0
nor $0, $0
j bar0
nor $0, $0
jalx bar1
nor $0, $0
jal bar1
nor $0, $0
j bar1
nor $0, $0
jalx bar2
nor $0, $0
jal bar2
nor $0, $0
j bar2
nor $0, $0
jalx bar3
nor $0, $0
jal bar3
nor $0, $0
j bar3
nor $0, $0
jalx bar4
nor $0, $0
jal bar4
nor $0, $0
j bar4
nor $0, $0
jalx bar4 + 1
nor $0, $0
jal bar4 + 1
nor $0, $0
j bar4 + 1
nor $0, $0
jalx bar4 + 2
nor $0, $0
jal bar4 + 2
nor $0, $0
j bar4 + 2
nor $0, $0
jalx bar4 + 3
nor $0, $0
jal bar4 + 3
nor $0, $0
j bar4 + 3
nor $0, $0
jalx bar4 + 4
nor $0, $0
jal bar4 + 4
nor $0, $0
j bar4 + 4
nor $0, $0
jalx bar16
nor $0, $0
jal bar16
nor $0, $0
j bar16
nor $0, $0
jalx bar17
nor $0, $0
jal bar17
nor $0, $0
j bar17
nor $0, $0
jalx bar18
nor $0, $0
jal bar18
nor $0, $0
j bar18
nor $0, $0
jalx bar18 + 1
nor $0, $0
jal bar18 + 1
nor $0, $0
j bar18 + 1
nor $0, $0
jalx bar18 + 2
nor $0, $0
jal bar18 + 2
nor $0, $0
j bar18 + 2
nor $0, $0
jalx bar18 + 3
nor $0, $0
jal bar18 + 3
nor $0, $0
j bar18 + 3
nor $0, $0
jalx bar18 + 4
nor $0, $0
jal bar18 + 4
nor $0, $0
j bar18 + 4
nor $0, $0
jalr $0, $ra
nor $0, $0
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
.set micromips
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,693
|
gas/testsuite/gas/mips/mips-gp32-fp64-pic.s
|
.sdata
shared: .word 11
.data
unshared:
.word 1
.word 2
.word 3
.word 4
.text
.ent func
func:
.frame $sp,0,$31
.set noreorder
.cpload $25 # 0000 lui gp,hi(_gp_disp)
# 0004 addiu gp,gp,lo(_gp_disp)
# 0008 addu gp,gp,t9
.set reorder
.cprestore 8 # 000c sw gp,8(sp)
.cpadd $4 # 0010 addu a0,a0,gp
li $4, 0x12345678 # 0014 lui a0,0x1234
# 0018 ori a0,a0,0x5678
la $4, shared # 001c lw a0,got(.sdata)(gp)
# 0020 nop
# 0024 addiu a0,a0,lo(shared)
la $4, unshared # 0028 lw a0,got(.data)(gp)
# 002c nop
# 0030 addiu a0,a0,lo(unshared)
la $4, end # 0034 lw a0,got(.text)(gp)
# 0038 nop
# 003c addiu a0,a0,lo(end)
j end # 0040 b end
# 0044 nop
jal end # 0048 lw t9,got(.text)(gp)
# 004c nop
# 0050 addiu t9,t9,lo(end)
# 0054 jalr t9
# 0058 nop
# 005c lw gp,8(sp)
lw $4, shared # 0060 lw a0,got(.sdata)(gp)
# 0064 nop
# 0068 addiu a0,a0,lo(shared)
# 006c lw a0,(a0)
lw $4, unshared # 0070 lw a0,got(.data)(gp)
# 0074 nop
# 0078 addiu a0,a0,lo(unshared)
# 007c lw a0,(a0)
lw $4, end # 0080 lw a0,got(.text)(gp)
# 0084 nop
# 0088 addiu a0,a0,lo(end)
# 008c lw a0,(a0)
ld $4, shared # 0090 lw at,got(.sdata)(gp)
# 0094 nop
# 0098 lw a0,lo(shared)(at)
# 009c lw a1,lo(shared)+4(at)
ld $4, unshared # 00a0 lw at,got(.data)(gp)
# 00a4 nop
# 00a8 lw a0,lo(unshared)(at)
# 00ac lw a1,lo(unshared)+4(at)
ld $4, end # 00b0 lw at,got(.text)(gp)
# 00b4 nop
# 00b8 lw a0,lo(end)(at)
# 00bc lw a1,lo(end)+4(at)
sw $4, shared # 00c0 lw at,got(.sdata)(gp)
# 00c4 nop
# 00c8 addiu at,at,lo(shared)
# 00cc sw a0,0(at)
sw $4, unshared # 00d0 lw at,got(.data)(gp)
# 00d4 nop
# 00d8 addiu at,at,lo(unshared)
# 00dc sw a0,0(at)
sd $4, shared # 00e0 lw at,got(.sdata)(gp)
# 00e4 nop
# 00e8 sw a0,lo(shared)(at)
# 00ec sw a1,lo(shared)+4(at)
sd $4, unshared # 00f0 lw at,got(.data)(gp)
# 00f4 nop
# 00f8 sw a0,lo(unshared)(at)
# 00fc sw a1,lo(unshared)+4(at)
ulh $4, unshared # 0100 lw at,got(.data)(gp)
# 0104 nop
# 0108 addiu at,at,lo(unshared)
# 010c lb a0,0(at)
# 0110 lbu at,1(at)
# 0114 sll a0,a0,8
# 0118 or a0,a0,at
ush $4, unshared # 011c lw at,got(.data)(gp)
# 0120 nop
# 0124 addiu at,at,lo(unshared)
# 0128 sb a0,0(at)
# 012c srl a0,a0,8
# 0130 sb a0,1(at)
# 0134 lbu at,0(at)
# 0138 sll a0,a0,8
# 013c or a0,a0,at
ulw $4, unshared # 0140 lw at,got(.data)(gp)
# 0144 nop
# 0148 addiu at,at,lo(unshared)
# 014c lwl a0,0(at)
# 0150 lwr a0,3(at)
usw $4, unshared # 0154 lw at,got(.data)(gp)
# 0158 nop
# 015c addiu at,at,lo(unshared)
# 0160 swl a0,0(at)
# 0164 swr a0,3(at)
li.d $4, 1.0 # 0168 lui a0,0x3ff0
# 016c move a1,zero
li.d $4, 1.9 # 0170 lw at,got(.rodata)(gp)
# 0174 lw a0,lo(F1.9)(at)
# 0178 lw a1,lo(F1.9)+4(at)
li.d $f0, 1.0 # 017c lw at,got(.rodata)(gp)
# 0180 ldc1 $f0,lo(L1.0)(at)
li.d $f0, 1.9 # 0184 lw at,got(.rodata)(gp)
# 0188 ldc1 $f0,lo(L1.9)(at)
seq $4, $5, -100 # 018c addiu a0,a1,100
# 0190 sltiu a0,a0,1
sne $4, $5, -100 # 0194 addiu a0,a1,100
# 0198 sltu a0,zero,a0
move $4, $5 # 019c move a0,a1
# Not available in 32-bit mode
# dla $4, shared
# dla $4, unshared
# uld $4, unshared
# usd $4, unshared
# Should produce warnings given -mgp32
# bgt $4, 0x7fffffff, end
# bgtu $4, 0xffffffff, end
# ble $4, 0x7fffffff, end
# bleu $4, 0xffffffff, end
# Should produce warnings given -mfp32
add.d $f1, $f2, $f3 # 01a0 add.d $f1,$f2,$f3
.end func
end:
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 3,039
|
gas/testsuite/gas/mips/ldstla-32-mips3.s
|
.set mips3
.text
ld $2, 0xffffffffffffffff($4)
ld $2, 0xffffffffabcdef01($4)
ld $2, 0xffffffff80000000($4)
ld $2, 0xffffffff7fffffff($4)
ld $2, 0xffffffff01234567($4)
ld $2, 0xffffffff00000000($4)
ld $2, 0xffffffff($4)
ld $2, 0xabcdef01($4)
ld $2, 0x80000000($4)
ld $2, 0x7fffffff($4)
ld $2, 0x01234567($4)
ld $2, 0x00000000($4)
ld $2, 0xffffffffffffffff
ld $2, 0xffffffffabcdef01
ld $2, 0xffffffff80000000
ld $2, 0xffffffff7fffffff
ld $2, 0xffffffff01234567
ld $2, 0xffffffff00000000
ld $2, 0xffffffff
ld $2, 0xabcdef01
ld $2, 0x80000000
ld $2, 0x7fffffff
ld $2, 0x01234567
ld $2, 0x00000000
sd $2, 0xffffffffffffffff($4)
sd $2, 0xffffffffabcdef01($4)
sd $2, 0xffffffff80000000($4)
sd $2, 0xffffffff7fffffff($4)
sd $2, 0xffffffff01234567($4)
sd $2, 0xffffffff00000000($4)
sd $2, 0xffffffff($4)
sd $2, 0xabcdef01($4)
sd $2, 0x80000000($4)
sd $2, 0x7fffffff($4)
sd $2, 0x01234567($4)
sd $2, 0x00000000($4)
sd $2, 0xffffffffffffffff
sd $2, 0xffffffffabcdef01
sd $2, 0xffffffff80000000
sd $2, 0xffffffff7fffffff
sd $2, 0xffffffff01234567
sd $2, 0xffffffff00000000
sd $2, 0xffffffff
sd $2, 0xabcdef01
sd $2, 0x80000000
sd $2, 0x7fffffff
sd $2, 0x01234567
sd $2, 0x00000000
lw $2, 0xffffffffffffffff($4)
lw $2, 0xffffffffabcdef01($4)
lw $2, 0xffffffff80000000($4)
lw $2, 0xffffffff7fffffff($4)
lw $2, 0xffffffff01234567($4)
lw $2, 0xffffffff00000000($4)
lw $2, 0xffffffff($4)
lw $2, 0xabcdef01($4)
lw $2, 0x80000000($4)
lw $2, 0x7fffffff($4)
lw $2, 0x01234567($4)
lw $2, 0x00000000($4)
lw $2, 0xffffffffffffffff
lw $2, 0xffffffffabcdef01
lw $2, 0xffffffff80000000
lw $2, 0xffffffff7fffffff
lw $2, 0xffffffff01234567
lw $2, 0xffffffff00000000
lw $2, 0xffffffff
lw $2, 0xabcdef01
lw $2, 0x80000000
lw $2, 0x7fffffff
lw $2, 0x01234567
lw $2, 0x00000000
sw $2, 0xffffffffffffffff($4)
sw $2, 0xffffffffabcdef01($4)
sw $2, 0xffffffff80000000($4)
sw $2, 0xffffffff7fffffff($4)
sw $2, 0xffffffff01234567($4)
sw $2, 0xffffffff00000000($4)
sw $2, 0xffffffff($4)
sw $2, 0xabcdef01($4)
sw $2, 0x80000000($4)
sw $2, 0x7fffffff($4)
sw $2, 0x01234567($4)
sw $2, 0x00000000($4)
sw $2, 0xffffffffffffffff
sw $2, 0xffffffffabcdef01
sw $2, 0xffffffff80000000
sw $2, 0xffffffff7fffffff
sw $2, 0xffffffff01234567
sw $2, 0xffffffff00000000
sw $2, 0xffffffff
sw $2, 0xabcdef01
sw $2, 0x80000000
sw $2, 0x7fffffff
sw $2, 0x01234567
sw $2, 0x00000000
la $2, 0xffffffffffffffff($4)
la $2, 0xffffffffabcdef01($4)
la $2, 0xffffffff80000000($4)
la $2, 0xffffffff7fffffff($4)
la $2, 0xffffffff01234567($4)
la $2, 0xffffffff00000000($4)
la $2, 0xffffffff($4)
la $2, 0xabcdef01($4)
la $2, 0x80000000($4)
la $2, 0x7fffffff($4)
la $2, 0x01234567($4)
la $2, 0x00000000($4)
la $2, 0xffffffffffffffff
la $2, 0xffffffffabcdef01
la $2, 0xffffffff80000000
la $2, 0xffffffff7fffffff
la $2, 0xffffffff01234567
la $2, 0xffffffff00000000
la $2, 0xffffffff
la $2, 0xabcdef01
la $2, 0x80000000
la $2, 0x7fffffff
la $2, 0x01234567
la $2, 0x00000000
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 2,500
|
gas/testsuite/gas/mips/ase-errors-2.s
|
.set nomicromips
.set mips64r2
.set dsp # OK
lbux $4,$5($6) # OK
ldx $4,$5($6) # OK
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips64 # ERROR: too low
lbux $4,$5($6) # OK
ldx $4,$5($6) # OK
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set nodsp
lbux $4,$5($6) # ERROR: dsp not enabled
ldx $4,$5($6) # ERROR: dsp not enabled
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips64r2
.set dspr2 # OK
lbux $4,$5($6) # OK
ldx $4,$5($6) # OK
absq_s.qb $3,$4 # OK
.set mips64 # ERROR: too low
lbux $4,$5($6) # OK
ldx $4,$5($6) # OK
absq_s.qb $3,$4 # OK
.set nodspr2
lbux $4,$5($6) # ERROR: dsp not enabled
ldx $4,$5($6) # ERROR: dsp not enabled
absq_s.qb $3,$4 # ERROR: dspr2 not enabled
.set mips64r2
.set mcu # OK
aclr 4,100($4) # OK
.set mips64 # ERROR: too low
aclr 4,100($4) # OK
.set nomcu
aclr 4,100($4) # ERROR: mcu not enabled
.set mips64
.set mdmx # OK
add.ob $f4,$f6,$f8 # OK
.set mips4 # ERROR: too low
add.ob $f4,$f6,$f8 # OK
.set nomdmx
add.ob $f4,$f6,$f8 # ERROR: mdmx not enabled
.set mips64
.set mips3d # OK
addr.ps $f4,$f6,$f8 # OK
.set mips4 # ERROR: too low
addr.ps $f4,$f6,$f8 # OK
.set nomips3d
addr.ps $f4,$f6,$f8 # ERROR: mips3d not enabled
.set mips64r2
.set mt # OK
dmt # OK
.set mips64 # ERROR: too low
dmt # OK
.set nomt
dmt # ERROR: mt not enabled
.set mips64
.set smartmips # OK
maddp $4,$5 # OK
.set mips4 # ERROR: too low
maddp $4,$5 # OK
.set nosmartmips
maddp $4,$5 # ERROR: smartmips not enabled
.set mips64r2
.set virt # OK
hypcall # OK
dmfgc0 $3, $29 # OK
.set mips64 # ERROR: too low
hypcall # OK
dmfgc0 $3, $29 # OK
.set novirt
hypcall # ERROR: virt not enabled
dmfgc0 $3, $29 # ERROR: virt not enabled
.set mips64r2
.set eva # OK
lbue $4,16($5) # OK
.set mips64 # ERROR: too low
lbue $4,16($5) # OK
.set noeva
lbue $4,16($5) # ERROR: eva not enabled
.set mips64r6
.set crc # OK
crc32b $4,$7,$4 # OK
crc32d $4,$7,$4 # OK
.set mips64r5 # ERROR: too low
crc32b $4,$7,$4 # OK
crc32d $4,$7,$4 # OK
.set nocrc
crc32b $4,$7,$4 # ERROR: crc not enabled
crc32d $4,$7,$4 # ERROR: crc not enabled
.set mips64r6
.set ginv # OK
ginvi $a0 # OK
.set mips64r5 # ERROR: too low
ginvt $a0,1 # OK
.set noginv
ginvi $a0 # ERROR: ginv not enabled
# There should be no errors after this.
.set fp=32
.set mips4
.set dsp
.set dspr2
.set mcu
.set mdmx
.set mips3d
.set mt
.set smartmips
.set eva
|
tactcomplabs/xbgas-binutils-gdb
| 1,735
|
gas/testsuite/gas/mips/unaligned-jump-2.s
|
.text
.set noreorder
.space 0x1000
.align 4
.ent foo
foo:
nor $0, $0
jalx bar0
nor $0, $0
jal bar0
nor $0, $0
j bar0
nor $0, $0
jalx bar1
nor $0, $0
jal bar1
nor $0, $0
j bar1
nor $0, $0
jalx bar2
nor $0, $0
jal bar2
nor $0, $0
j bar2
nor $0, $0
jalx bar3
nor $0, $0
jal bar3
nor $0, $0
j bar3
nor $0, $0
jalx bar4
nor $0, $0
jal bar4
nor $0, $0
j bar4
nor $0, $0
jalx bar4 + 1
nor $0, $0
jal bar4 + 1
nor $0, $0
j bar4 + 1
nor $0, $0
jalx bar4 + 2
nor $0, $0
jal bar4 + 2
nor $0, $0
j bar4 + 2
nor $0, $0
jalx bar4 + 3
nor $0, $0
jal bar4 + 3
nor $0, $0
j bar4 + 3
nor $0, $0
jalx bar4 + 4
nor $0, $0
jal bar4 + 4
nor $0, $0
j bar4 + 4
nor $0, $0
jalx bar16
nor $0, $0
jal bar16
nor $0, $0
j bar16
nor $0, $0
jalx bar17
nor $0, $0
jal bar17
nor $0, $0
j bar17
nor $0, $0
jalx bar18
nor $0, $0
jal bar18
nor $0, $0
j bar18
nor $0, $0
jalx bar18 + 1
nor $0, $0
jal bar18 + 1
nor $0, $0
j bar18 + 1
nor $0, $0
jalx bar18 + 2
nor $0, $0
jal bar18 + 2
nor $0, $0
j bar18 + 2
nor $0, $0
jalx bar18 + 3
nor $0, $0
jal bar18 + 3
nor $0, $0
j bar18 + 3
nor $0, $0
jalx bar18 + 4
nor $0, $0
jal bar18 + 4
nor $0, $0
j bar18 + 4
nor $0, $0
jalr $0, $ra
nor $0, $0
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
.macro obj n:req
.globl bar\@
.type bar\@, @object
bar\@ :
.byte 0
.size bar\@, . - bar\@
.if \n - 1
obj \n - 1
.endif
.endm
.macro fun n:req
.globl bar\@
.type bar\@, @function
bar\@ :
.insn
.hword 0
.size bar\@, . - bar\@
.if \n - 1
fun \n - 1
.endif
.endm
.align 4
.set micromips
obj 16
fun 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,246
|
gas/testsuite/gas/mips/mipsr6@mips32r2-ill.s
|
# source file to test illegal mips32r2 instructions
.set noreorder
.set noat
.text
text_label:
# insert and extract position/size checks:
# ext constraint: 0 <= pos < 32
ext $4, $5, -1, 1 # error
ext $4, $5, 0, 1
ext $4, $5, 31, 1
ext $4, $5, 32, 1 # error
# ext constraint: 0 < size <= 32
ext $4, $5, 0, 0 # error
ext $4, $5, 0, 1
ext $4, $5, 0, 32
ext $4, $5, 0, 33 # error
# ext constraint: 0 < (pos+size) <= 32
ext $4, $5, 0, 0 # error
ext $4, $5, 0, 1
ext $4, $5, 31, 1
ext $4, $5, 31, 2 # error
# ins constraint: 0 <= pos < 32
ins $4, $5, -1, 1 # error
ins $4, $5, 0, 1
ins $4, $5, 31, 1
ins $4, $5, 32, 1 # error
# ins constraint: 0 < size <= 32
ins $4, $5, 0, 0 # error
ins $4, $5, 0, 1
ins $4, $5, 0, 32
ins $4, $5, 0, 33 # error
# ins constraint: 0 < (pos+size) <= 32
ins $4, $5, 0, 0 # error
ins $4, $5, 0, 1
ins $4, $5, 31, 1
ins $4, $5, 31, 2 # error
# FP register checks.
#
# Even registers are supported w/ 32-bit FPU, odd
# registers supported only for 64-bit FPU.
# This file tests 32-bit FPU.
mfhc1 $17, $f0
mthc1 $17, $f0
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
|
tactcomplabs/xbgas-binutils-gdb
| 1,878
|
gas/testsuite/gas/mips/cp3.s
|
.text
.set noreorder
foo:
mtc3 $0, $0
mtc3 $0, $1
mtc3 $0, $2
mtc3 $0, $3
mtc3 $0, $4
mtc3 $0, $5
mtc3 $0, $6
mtc3 $0, $7
mtc3 $0, $8
mtc3 $0, $9
mtc3 $0, $10
mtc3 $0, $11
mtc3 $0, $12
mtc3 $0, $13
mtc3 $0, $14
mtc3 $0, $15
mtc3 $0, $16
mtc3 $0, $17
mtc3 $0, $18
mtc3 $0, $19
mtc3 $0, $20
mtc3 $0, $21
mtc3 $0, $22
mtc3 $0, $23
mtc3 $0, $24
mtc3 $0, $25
mtc3 $0, $26
mtc3 $0, $27
mtc3 $0, $28
mtc3 $0, $29
mtc3 $0, $30
mtc3 $0, $31
mfc3 $0, $0
mfc3 $0, $1
mfc3 $0, $2
mfc3 $0, $3
mfc3 $0, $4
mfc3 $0, $5
mfc3 $0, $6
mfc3 $0, $7
mfc3 $0, $8
mfc3 $0, $9
mfc3 $0, $10
mfc3 $0, $11
mfc3 $0, $12
mfc3 $0, $13
mfc3 $0, $14
mfc3 $0, $15
mfc3 $0, $16
mfc3 $0, $17
mfc3 $0, $18
mfc3 $0, $19
mfc3 $0, $20
mfc3 $0, $21
mfc3 $0, $22
mfc3 $0, $23
mfc3 $0, $24
mfc3 $0, $25
mfc3 $0, $26
mfc3 $0, $27
mfc3 $0, $28
mfc3 $0, $29
mfc3 $0, $30
mfc3 $0, $31
ctc3 $0, $0
ctc3 $0, $1
ctc3 $0, $2
ctc3 $0, $3
ctc3 $0, $4
ctc3 $0, $5
ctc3 $0, $6
ctc3 $0, $7
ctc3 $0, $8
ctc3 $0, $9
ctc3 $0, $10
ctc3 $0, $11
ctc3 $0, $12
ctc3 $0, $13
ctc3 $0, $14
ctc3 $0, $15
ctc3 $0, $16
ctc3 $0, $17
ctc3 $0, $18
ctc3 $0, $19
ctc3 $0, $20
ctc3 $0, $21
ctc3 $0, $22
ctc3 $0, $23
ctc3 $0, $24
ctc3 $0, $25
ctc3 $0, $26
ctc3 $0, $27
ctc3 $0, $28
ctc3 $0, $29
ctc3 $0, $30
ctc3 $0, $31
cfc3 $0, $0
cfc3 $0, $1
cfc3 $0, $2
cfc3 $0, $3
cfc3 $0, $4
cfc3 $0, $5
cfc3 $0, $6
cfc3 $0, $7
cfc3 $0, $8
cfc3 $0, $9
cfc3 $0, $10
cfc3 $0, $11
cfc3 $0, $12
cfc3 $0, $13
cfc3 $0, $14
cfc3 $0, $15
cfc3 $0, $16
cfc3 $0, $17
cfc3 $0, $18
cfc3 $0, $19
cfc3 $0, $20
cfc3 $0, $21
cfc3 $0, $22
cfc3 $0, $23
cfc3 $0, $24
cfc3 $0, $25
cfc3 $0, $26
cfc3 $0, $27
cfc3 $0, $28
cfc3 $0, $29
cfc3 $0, $30
cfc3 $0, $31
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb
| 1,542
|
gas/testsuite/gas/mips/vr4120-2.s
|
# Test workarounds selected by -mfix-vr4120.
# Note that we only work around bugs gcc may generate.
r21:
macc $4,$5,$6
div $0,$7,$8
or $4,$5
dmacc $4,$5,$6
div $0,$7,$8
or $4,$5
macc $4,$5,$6
divu $0,$7,$8
or $4,$5
dmacc $4,$5,$6
divu $0,$7,$8
or $4,$5
macc $4,$5,$6
ddiv $0,$7,$8
or $4,$5
dmacc $4,$5,$6
ddiv $0,$7,$8
or $4,$5
macc $4,$5,$6
ddivu $0,$7,$8
or $4,$5
dmacc $4,$5,$6
ddivu $0,$7,$8
or $4,$5
r23:
dmult $4,$5
dmult $6,$7
or $4,$5
dmultu $4,$5
dmultu $6,$7
or $4,$5
dmacc $4,$5,$6
dmacc $6,$7,$8
or $4,$5
dmult $4,$5
dmacc $6,$7,$8
or $4,$5
r24:
macc $4,$5,$6
mtlo $7
dmacc $4,$5,$6
mtlo $7
macc $4,$5,$6
mthi $7
dmacc $4,$5,$6
mthi $7
vr4181a_md1:
macc $4,$5,$6
mult $4,$5
or $4,$5
macc $4,$5,$6
multu $4,$5
or $4,$5
macc $4,$5,$6
dmult $4,$5
or $4,$5
macc $4,$5,$6
dmultu $4,$5
or $4,$5
dmacc $4,$5,$6
mult $4,$5
or $4,$5
dmacc $4,$5,$6
multu $4,$5
or $4,$5
dmacc $4,$5,$6
dmult $4,$5
or $4,$5
dmacc $4,$5,$6
dmultu $4,$5
or $4,$5
vr4181a_md4:
dmult $4,$5
macc $4,$5,$6
or $4,$5
dmultu $4,$5
macc $4,$5,$6
or $4,$5
div $0,$4,$5
macc $4,$5,$6
or $4,$5
divu $0,$4,$5
macc $4,$5,$6
or $4,$5
ddiv $0,$4,$5
macc $4,$5,$6
or $4,$5
ddivu $0,$4,$5
macc $4,$5,$6
or $4,$5
dmult $4,$5
dmacc $4,$5,$6
or $4,$5
dmultu $4,$5
dmacc $4,$5,$6
or $4,$5
div $0,$4,$5
dmacc $4,$5,$6
or $4,$5
divu $0,$4,$5
dmacc $4,$5,$6
or $4,$5
ddiv $0,$4,$5
dmacc $4,$5,$6
or $4,$5
ddivu $0,$4,$5
dmacc $4,$5,$6
or $4,$5
|
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