repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
georgevio/IoT-Embedded
| 7,653
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_resize.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
.align 2
.text
.global dl_esp32p4_s8_resize_nearest_2x2_c1
.type dl_esp32p4_s8_resize_nearest_2x2_c1, @function
dl_esp32p4_s8_resize_nearest_2x2_c1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: output_x_offset
# a4: output_y_offset
# a5: c_div_x
# t3: remainder
# t4: output_shift
# t5: output_scale
lw a3, 20(a2)
lw a4, 24(a2)
lw a5, 40(a2)
lw t3, 44(a2)
lw t4, 48(a2)
lw t5, 52(a2)
# t6 (0, 1)
# s0 (1, 0)
# s1 (1, 1)
add t6, a0, a3
add s0, a0, a4
add s1, t6, a4
sb t5, 0(sp)
add s8, sp, x0
esp.vldbc.8.ip q1, s8, 0 # all output_scale
esp.vld.128.ip q0, a1, 16
add t0, a5, x0
blez t0, 1f
0:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp.srcmb.s8.qacc q2, t4, 1
esp.vst.128.ip q2, a0, 16
esp.vst.128.ip q2, t6, 16
esp.vst.128.ip q2, s0, 16
esp.vst.128.ip q2, s1, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.text
.align 2
.global dl_esp32p4_s8_resize_nearest_c1
.type dl_esp32p4_s8_resize_nearest_c1, @function
.balign 4
.option norvc
dl_esp32p4_s8_resize_nearest_c1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: c_div_x
# a4: output_shift
# a5: output_scale address
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 40(a2)
lw a4, 48(a2)
blez a3, dl_esp32p4_s8_resize_nearest_c1_end
addi a5, a2, 52
esp.vldbc.8.ip q1, a5, 0 // load output_scale
esp.vld.128.ip q0, a1, 16
dl_esp32p4_s8_resize_nearest_c1_loop:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp32p4_s8_128b_vector_shift_result q2, a4
esp32p4_s8_128b_aligned_vector_store q2, a0
addi a3, a3, -1
bgtz a3, dl_esp32p4_s8_resize_nearest_c1_loop
dl_esp32p4_s8_resize_nearest_c1_end:
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1
.type dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1, @function
dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: output_x_offset
# a4: output_y_offset
# a5: c_div_x
# t3: remainder
# t4: output_shift
# t5: output_scale
lw a3, 20(a2)
lw a4, 24(a2)
lw a5, 40(a2)
lw t3, 44(a2)
lw t4, 48(a2)
lw t5, 52(a2)
# t6 (0, 1)
# s0 (1, 0)
# s1 (1, 1)
add t6, a0, a3
add s0, a0, a4
add s1, t6, a4
sb t5, 0(sp)
add s8, sp, x0
esp.vldbc.8.ip q3, s8, 0 # all output_scale
esp.ld.128.usar.ip q0, a1, 16
add t0, a5, x0
blez t0, 1f
0:
esp.zero.qacc
esp.ld.128.usar.ip q1, a1, 16
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp.srcmb.s8.qacc q4, t4, 1
esp32p4_s8_32b_unaligned_vector_store q4, a0, s8
esp32p4_s8_32b_unaligned_vector_store q4, t6, s8
esp32p4_s8_32b_unaligned_vector_store q4, s0, s8
esp32p4_s8_32b_unaligned_vector_store q4, s1, s8
addi t0, t0, -1
bgtz t0, 0b
1:
bnez t3, dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1_remainder
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1_remainder:
esp.zero.qacc
esp.ld.128.usar.ip q1, a1, 16
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp.srcmb.s8.qacc q4, t4, 1
dl_esp32p4_s8_store_remainder q4, t4, t5, s8, s9, t0, a0, t3
dl_esp32p4_s8_store_remainder q4, t4, t5, s8, s9, t0, t6, t3
dl_esp32p4_s8_store_remainder q4, t4, t5, s8, s9, t0, s0, t3
dl_esp32p4_s8_store_remainder q4, t4, t5, s8, s9, t0, s1, t3
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_resize_nearest_c1
.type dl_esp32p4_s8_unaligned_resize_nearest_c1, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_resize_nearest_c1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: c_div_x / tmp value
# a4: output_shift
# a5: output_scale address
# t3: c_remainder
# t4: output_sar_byte / tmp value
# t5: tmp value
# t6:
# a6(not for extension instructions): tmp value
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 40(a2)
lw a4, 48(a2)
lw t3, 44(a2)
blez a3, dl_esp32p4_s8_unaligned_resize_nearest_c1_remainder
addi a5, a2, 52
esp.vldbc.8.ip q3, a5, 0 // load output_scale
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q2, a0, 0
esp.movx.r.sar.bytes t4 // output_sar_byte
beqz t4, dl_esp32p4_s8_unaligned_resize_nearest_c1_128b_loop
li a6, 8
beq t4, a6, dl_esp32p4_s8_unaligned_resize_nearest_c1_64b_loop
dl_esp32p4_s8_unaligned_resize_nearest_c1_32b_loop:
esp.ld.128.usar.ip q1, a1, 16
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp32p4_s8_128b_vector_shift_result q2, a4
esp32p4_s8_32b_unaligned_vector_store q2, a0, t4
addi a3, a3, -1
bgtz a3, dl_esp32p4_s8_unaligned_resize_nearest_c1_32b_loop
j dl_esp32p4_s8_unaligned_resize_nearest_c1_remainder
dl_esp32p4_s8_unaligned_resize_nearest_c1_64b_loop:
esp.ld.128.usar.ip q1, a1, 16
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp32p4_s8_128b_vector_shift_result q2, a4
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi a3, a3, -1
bgtz a3, dl_esp32p4_s8_unaligned_resize_nearest_c1_64b_loop
j dl_esp32p4_s8_unaligned_resize_nearest_c1_remainder
dl_esp32p4_s8_unaligned_resize_nearest_c1_128b_loop:
esp.ld.128.usar.ip q1, a1, 16
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp32p4_s8_128b_vector_shift_result q2, a4
esp32p4_s8_128b_aligned_vector_store q2, a0
addi a3, a3, -1
bgtz a3, dl_esp32p4_s8_unaligned_resize_nearest_c1_128b_loop
dl_esp32p4_s8_unaligned_resize_nearest_c1_remainder:
beqz t3, dl_esp32p4_s8_unaligned_resize_nearest_c1_end
esp.ld.128.usar.xp q1, a1, t3
esp.zero.qacc
esp.src.q q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp32p4_s8_128b_vector_shift_result q2, a4
dl_esp32p4_s8_store_remainder q2, a3, a5, t4, t5, a6, a0, t3
dl_esp32p4_s8_unaligned_resize_nearest_c1_end:
ret
|
georgevio/IoT-Embedded
| 40,868
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_add2d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s8_add2d_11c series
####
############################################################################################################################################################
.macro dl_esp32p4_rescale_add_rescale_output input0, input1, output, output_scale, output_shift
esp.zero.qacc
esp.vmulas.s8.qacc \input0, \output_scale
esp.vmulas.s8.qacc \input1, \output_scale
esp.srcmb.s8.qacc \output, \output_shift, 1
.endm
.align 2
.text
.global dl_esp32p4_s8_add2d_11c
.type dl_esp32p4_s8_add2d_11c, @function
#.section .iram1
dl_esp32p4_s8_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x_1
lw a4, 68(a3)
lw a5, 72(a3)
li t0, 1
blt a4, t0, dl_esp32p4_s8_add2d_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp.vadd.s8 q5, q2, q3
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vst.128.ip q5, a0, 16
esp.vadd.s8 q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_add2d_small_channel: # channel < 3*s (16)
add t0, a5, x0
blez t0, 1f
0:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_rescale_add2d_11c
.type dl_esp32p4_s8_rescale_add2d_11c, @function
#.section .iram1
dl_esp32p4_s8_rescale_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr: >> shift or *scale) >> shift
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_add2d_output
dl_esp32p4_s8_rescale_add2d_output_scale: # *scale) >> shift
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
add t0, a4, x0
blez t0, 1f
0:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_rescale_add2d_output: # >> shift
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 3f
2:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s8.qacc q1, t4, 1
esp.ldqa.s8.128.ip a2, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc q0, q7
esp.srcmb.s8.qacc q1, t4, 1
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_add2d_11c_relu
.type dl_esp32p4_s8_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s8_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x_1
# s8: activation_alpha
# s9: activation_shift
lw a4, 68(a3)
lw a5, 72(a3)
lw s8, 52(a3)
lw s9, 60(a3)
li t0, 1
blt a4, t0, dl_esp32p4_s8_add2d_relu_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s8 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vrelu.s8 q5, s8, s9
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s8 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp.vadd.s8 q5, q2, q3
esp.vrelu.s8 q5, s8, s9
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s8 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vrelu.s8 q5, s8, s9
esp.vst.128.ip q5, a0, 16
esp.vadd.s8 q4, q0, q1
esp.vrelu.s8 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_add2d_relu_small_channel: # channel < 3*16byte
add t0, a5, x0
blez t0, 1f
0:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_rescale_add2d_11c_relu
.type dl_esp32p4_s8_rescale_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s8_rescale_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr: >> shift or *scale) >> shift
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
lw s8, 52(a3)
lw s9, 60(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_add2d_output_relu
dl_esp32p4_s8_rescale_add2d_output_scale_relu: # *scale) >> shift
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
add t0, a4, x0
blez t0, 1f
0:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vrelu.s8 q1, s8, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vrelu.s8 q1, s8, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_rescale_add2d_output_relu: # >> shift
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 1f
0:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s8.qacc q1, t4, 1
esp.vrelu.s8 q1, s8, s9
esp.ldqa.s8.128.ip a2, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc q0, q7
esp.srcmb.s8.qacc q1, t4, 1
esp.vrelu.s8 q1, s8, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_add2d_11c_prelu
.type dl_esp32p4_s8_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s8_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x_1
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 68(a3)
lw a5, 72(a3)
lw s8, 56(a3)
lw s9, 60(a3)
li t0, 1
blt a4, t0, dl_esp32p4_s8_add2d_prelu_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s8 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vprelu.s8 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s8 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q5, q2, q3
esp.vprelu.s8 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s8 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vprelu.s8 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q4, q0, q1
esp.vprelu.s8 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_add2d_prelu_small_channel: # channel < 3*s
add t0, a5, x0
blez t0, 1f
0:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q3, s8, 16
esp.vadd.s8 q2, q0, q1
esp.vprelu.s8 q2, q2, q3, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q3, s8, 16
esp.vadd.s8 q2, q0, q1
esp.vprelu.s8 q2, q2, q3, s9
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_rescale_add2d_11c_prelu
.type dl_esp32p4_s8_rescale_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s8_rescale_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr: >> shift or *scale) >> shift
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
lw s8, 56(a3)
lw s9, 60(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_add2d_output_prelu
dl_esp32p4_s8_rescale_add2d_output_scale_prelu: # *scale) >> shift
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
add t0, a4, x0
blez t0, 1f
0:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
esp.vld.128.ip q5, s8, 16
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vprelu.s8 q1, q1, q5, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
esp.vld.128.ip q5, s8, 16
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vprelu.s8 q1, q1, q5, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_rescale_add2d_output_prelu: # >> shift
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 1f
0:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q1, t4, 1
esp.vprelu.s8 q1, q1, q6, s9
esp.ldqa.s8.128.ip a2, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc q0, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q1, t4, 1
esp.vprelu.s8 q1, q1, q6, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
############################################################################################################################################################
####
#### esp32p4_s8_unaligned_add2d_11c series
####
############################################################################################################################################################
.align 2
.text
.global dl_esp32p4_s8_unaligned_add2d_11c
.type dl_esp32p4_s8_unaligned_add2d_11c, @function
#.section .iram1
dl_esp32p4_s8_unaligned_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_unaligned_add2d_11c_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_unaligned_add2d_11c_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_unaligned_add2d_11c_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_unaligned_add2d_11c_remainder
#output sar = 0
dl_esp32p4_s8_unaligned_add2d_11c_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_unaligned_add2d_11c_remainder
# #output sar = 8
dl_esp32p4_s8_unaligned_add2d_11c_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_unaligned_add2d_11c_remainder
dl_esp32p4_s8_unaligned_add2d_11c_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_unaligned_add2d_11c_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vadd.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s8_unaligned_rescale_add2d_11c:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_unaligned_add2d_output_shift
### rescaled to output by *scale) >> shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_scale:
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_scale_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_scale_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_scale_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_scale_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_shift:
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_shift_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_shift_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_shift_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_shift_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
# esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
dl_esp32p4_s8_store_remainder q5, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_add2d_11c_relu
.type dl_esp32p4_s8_unaligned_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s8_unaligned_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
lw s8, 52(a3)
lw s9, 60(a3)
bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c_relu
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_unaligned_add2d_11c_relu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_unaligned_add2d_11c_relu_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_unaligned_add2d_11c_relu_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_unaligned_add2d_11c_relu_remainder
#output sar = 0
dl_esp32p4_s8_unaligned_add2d_11c_relu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_unaligned_add2d_11c_relu_remainder
# #output sar = 8
dl_esp32p4_s8_unaligned_add2d_11c_relu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_unaligned_add2d_11c_relu_remainder
dl_esp32p4_s8_unaligned_add2d_11c_relu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_unaligned_add2d_11c_relu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_relu_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vrelu.s8 q2, s8, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_relu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s8_unaligned_rescale_add2d_11c_relu:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_unaligned_add2d_output_shift_relu
### rescaled to output by *scale) >> shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_scale_relu:
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_scale_relu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_scale_relu_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_scale_relu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_scale_relu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_relu_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vrelu.s8 q2, s8, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_relu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_shift_relu:
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_shift_relu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q5, s8, s9
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.vrelu.s8 q5, s8, s9
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_shift_relu_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_shift_relu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_shift_relu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_relu_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.vrelu.s8 q5, s8, s9
# esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
dl_esp32p4_s8_store_remainder q5, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_relu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_add2d_11c_prelu
.type dl_esp32p4_s8_unaligned_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s8_unaligned_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
lw s8, 56(a3)
lw s9, 60(a3)
bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c_prelu
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_unaligned_add2d_11c_prelu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_unaligned_add2d_11c_prelu_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_unaligned_add2d_11c_prelu_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q2, q2, q5
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_unaligned_add2d_11c_prelu_remainder
#output sar = 0
dl_esp32p4_s8_unaligned_add2d_11c_prelu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q2, q2, q5
esp.vprelu.s8 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_unaligned_add2d_11c_prelu_remainder
# #output sar = 8
dl_esp32p4_s8_unaligned_add2d_11c_prelu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q2, q2, q5
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_unaligned_add2d_11c_prelu_remainder
dl_esp32p4_s8_unaligned_add2d_11c_prelu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_unaligned_add2d_11c_prelu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_prelu_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q2, q2, q5
esp.vprelu.s8 q2, q2, q6, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_prelu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s8_unaligned_rescale_add2d_11c_prelu:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_unaligned_add2d_output_shift_prelu
### rescaled to output by *scale) >> shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_scale_prelu:
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_scale_prelu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
esp.vld.128.ip q6, s8, 16
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_scale_prelu_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_scale_prelu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_scale_prelu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_prelu_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
esp.vld.128.ip q6, s8, 16
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vprelu.s8 q2, q2, q6, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_prelu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_shift_prelu:
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_shift_prelu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q5, q5, q6, s9
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q5, t4, 1
esp.vprelu.s8 q5, q5, q6, s9
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_shift_prelu_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_shift_prelu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_shift_prelu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_prelu_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q5, t4, 1
esp.vprelu.s8 q5, q5, q6, s9
# esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
dl_esp32p4_s8_store_remainder q5, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_prelu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 7,815
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_requantize_linear.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
.text
.align 2
.global dl_esp32p4_s8_s8_requantize_linear
.type dl_esp32p4_s8_s8_requantize_linear, @function
.balign 4
.option norvc
dl_esp32p4_s8_s8_requantize_linear:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: size_div_x / tmp value
# a4: in_size_remainder
# a5: tmp value
# t3: output_shift / tmp value
# t4: output_scale / tmp value
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 8(a2) // size_div_x
lw a4, 12(a2) // in_size_remainder
lw t3, 20(a2) // output_shift
lw t4, 24(a2) // output_scale
bgtz t4, esp32p4_s8_s8_requantize_linear_left_shift
beqz a3, esp32p4_s8_s8_requantize_linear_right_shift_remainder
esp32p4_s8_s8_requantize_linear_right_shift_loop:
esp.ldqa.s8.128.ip a1, 16
addi a3, a3, -1
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
bnez a3, esp32p4_s8_s8_requantize_linear_right_shift_loop
esp32p4_s8_s8_requantize_linear_right_shift_remainder:
beqz a4, esp32p4_s8_s8_requantize_linear_end
esp.ldqa.s8.128.xp a1, a4
esp32p4_s8_128b_vector_shift_result q0, t3
dl_esp32p4_s8_store_remainder q0, a3, a5, t3, t4, t0, a0, a4
j esp32p4_s8_s8_requantize_linear_end
esp32p4_s8_s8_requantize_linear_left_shift:
addi t4, a2, 24
esp.vldbc.16.ip q2, t4, 0 // load output_scale
beqz a3, esp32p4_s8_s8_requantize_linear_left_shift_remainder
esp32p4_s8_s8_requantize_linear_left_shift_loop:
esp.vldext.s8.ip q0, q1, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
esp.vst.128.ip q0, a0, 16
addi a3, a3, -1
bnez a3, esp32p4_s8_s8_requantize_linear_left_shift_loop
esp32p4_s8_s8_requantize_linear_left_shift_remainder:
beqz a4, esp32p4_s8_s8_requantize_linear_end
esp.vldext.s8.xp q0, q1, a1, a4
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a5, t3, t4, t0, a0, a4
esp32p4_s8_s8_requantize_linear_end:
ret
.text
.align 2
.global dl_esp32p4_s8_s16_requantize_linear
.type dl_esp32p4_s8_s16_requantize_linear, @function
.balign 4
.option norvc
dl_esp32p4_s8_s16_requantize_linear:
# a0: int8_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: size_div_x / tmp value
# a4: in_size_remainder / tmp value
# a5: out_size_remainder
# t3: output_shift / tmp value
# t4: output_scale / tmp value
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 8(a2) // size_div_x
lw a4, 12(a2) // in_size_remainder
lw a5, 16(a2) // out_size_remainder
lw t3, 20(a2) // output_shift
lw t4, 24(a2) // output_scale
bgtz t4, esp32p4_s8_s16_requantize_linear_left_shift
beqz a3, esp32p4_s8_s16_requantize_linear_right_shift_remainder
esp32p4_s8_s16_requantize_linear_right_shift_loop:
esp.ldqa.s16.128.ip a1, 16
esp32p4_s8_128b_vector_shift_result q0, t3
esp.ldqa.s16.128.ip a1, 16
addi a3, a3, -1
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
esp.vst.128.ip q0, a0, 16
bnez a3, esp32p4_s8_s16_requantize_linear_right_shift_loop
esp32p4_s8_s16_requantize_linear_right_shift_remainder:
beqz a5, esp32p4_s8_s16_requantize_linear_end
li t0, 8
ble a5, t0, esp32p4_s8_s16_requantize_linear_right_shift_remainder_le8
esp.ldqa.s16.128.ip a1, 16
esp32p4_s8_128b_vector_shift_result q0, t3
esp.ldqa.s16.128.xp a1, a4
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a4, t3, t4, t0, a0, a5
j esp32p4_s8_s16_requantize_linear_end
esp32p4_s8_s16_requantize_linear_right_shift_remainder_le8:
esp.ldqa.s16.128.xp a1, a4
esp.zero.q q1
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a4, t3, t4, t0, a0, a5
j esp32p4_s8_s16_requantize_linear_end
esp32p4_s8_s16_requantize_linear_left_shift:
addi t4, a2, 24
esp.vldbc.16.ip q2, t4, 0 // load output_scale
beqz a3, esp32p4_s8_s16_requantize_linear_left_shift_remainder
esp32p4_s8_s16_requantize_linear_left_shift_loop:
esp.vld.128.ip q0, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vld.128.ip q1, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
esp.vst.128.ip q0, a0, 16
addi a3, a3, -1
bnez a3, esp32p4_s8_s16_requantize_linear_left_shift_loop
esp32p4_s8_s16_requantize_linear_left_shift_remainder:
beqz a5, esp32p4_s8_s16_requantize_linear_end
li t0, 8
ble a5, t0, esp32p4_s8_s16_requantize_linear_left_shift_remainder_le8
esp.vld.128.ip q0, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vld.128.xp q1, a1, a4
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a4, t3, t4, t0, a0, a5
j esp32p4_s8_s16_requantize_linear_end
esp32p4_s8_s16_requantize_linear_left_shift_remainder_le8:
esp.vld.128.xp q0, a1, a4
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.zero.q q1
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a4, t3, t4, t0, a0, a5
esp32p4_s8_s16_requantize_linear_end:
ret
|
georgevio/IoT-Embedded
| 15,550
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_greater.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_greater_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greater_w1_16_w2_16
.type dl_esp32p4_s8_greater_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_16_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
esp32p4_s8_greater_w1_16_w2_16_loop:
beq t0, a3, esp32p4_s8_greater_w1_16_w2_16_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greater_w1_16_w2_16_loop
esp32p4_s8_greater_w1_16_w2_16_end:
ret
#void dl_esp32p4_s8_greater_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greater_w1_16_w2_1
.type dl_esp32p4_s8_greater_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_16_w2_1:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s8_greater_w1_16_w2_1_loop:
beq t0, a3, esp32p4_s8_greater_w1_16_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greater_w1_16_w2_1_loop
esp32p4_s8_greater_w1_16_w2_1_end:
ret
#void dl_esp32p4_s8_greater_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greater_w1_1_w2_16
.type dl_esp32p4_s8_greater_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_1_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s8_greater_w1_1_w2_16_loop:
beq t0, a3, esp32p4_s8_greater_w1_1_w2_16_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greater_w1_1_w2_16_loop
esp32p4_s8_greater_w1_1_w2_16_end:
ret
.align 2
.text
.global dl_esp32p4_s8_greater_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_greater_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_greater_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_greater_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_greater_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_greater_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,525
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_xor4d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor
.type dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor
.type dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.8.ip q1, a2, 0
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor
.type dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.8.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned
.type dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_remainder
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.xorq q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned
.type dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_remainder
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a2, 0
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned
.type dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a2: int8_t *input0_ptr
# a1: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.xorq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.xorq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.xorq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_remainder
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a1, 0
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end___
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end___:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 3,750
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_prelu.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
.align 2
.text
.global dl_esp32p4_s8_prelu_11c
.type dl_esp32p4_s8_prelu_11c, @function
dl_esp32p4_s8_prelu_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: c_div_x = n_div_x
# s0: activation_alpha_ptr
# s1: activation_shift
# s8: output_shift
# s9: output_scale
lw a3, 96(a2) # n_div_x
lw s0, 80(a2) # activation_alpha_ptr
lw s1, 84(a2) # activation_shift
lw s8, 172(a2) # output_shift
lw s9, 176(a2) # output_scale
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, s0, 16
esp.zero.q q2 # all 0
addi a5, a2, 176
esp.vldbc.8.ip q3, a5, 0 # all output_scale
add t0, a3, x0
blez t0, 1f
0:
# neg part, alpha * input, right shift: output - alpha - input
esp.vprelu.s8 q4, q0, q1, s1
esp.vcmp.lt.s8 q6, q0, q2
esp.andq q4, q4, q6
# pos part, *scale, right shift: output - input
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q1, s0, 16, q0, q3
esp.srcmb.s8.qacc q5, s8, 1
esp.vcmp.gt.s8 q6, q0, q2
esp.andq q5, q5, q6
esp.vadd.s8.ld.incp q0, a1, q4, q4, q5
esp.vst.128.ip q4, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_prelu_11c
.type dl_esp32p4_s8_unaligned_prelu_11c, @function
dl_esp32p4_s8_unaligned_prelu_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: c_div_x = n_div_x
# a4: c_remainder
# s0: activation_alpha_ptr
# s1: activation_shift
# s8: output_shift
# s9: output_scale
lw a3, 96(a2) # c_div_x
lw a4, 136(a2) # c_remainder
lw s0, 80(a2) # activation_alpha_ptr
lw s1, 84(a2) # activation_shift
lw s8, 172(a2) # output_shift
lw s9, 176(a2) # output_scale
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q1, s0, 16
addi a5, a2, 176
esp.vldbc.8.ip q7, a5, 0 # all output_scale
add t0, a3, x0
blez t0, 1f
0:
esp.ld.128.usar.ip q2, a1, 16
esp.src.q.qup q4, q0, q2
esp.ld.128.usar.ip q3, s0, 16
esp.src.q.qup q5, q1, q3
# neg part, alpha * input, right shift: output - alpha - input
esp.vprelu.s8 q5, q4, q5, s1
esp.zero.q q2
esp.vcmp.lt.s8 q6, q4, q2
esp.andq q5, q5, q6
# pos part, *scale, right shift: output - input
esp.zero.qacc
esp.vmulas.s8.qacc q4, q7
esp.srcmb.s8.qacc q3, s8, 1
esp.vcmp.gt.s8 q6, q4, q2
esp.andq q3, q3, q6
esp.vadd.s8 q3, q3, q5
esp32p4_s8_32b_unaligned_vector_store q3, a0, t3
addi t0, t0, -1
bgtz t0, 0b
1:
bnez a4, dl_esp32p4_s8_unaligned_prelu_remainder
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_unaligned_prelu_remainder:
esp.ld.128.usar.ip q2, a1, 16
esp.src.q.qup q4, q0, q2
esp.ld.128.usar.ip q3, s0, 16
esp.src.q.qup q5, q1, q3
# neg part, alpha * input, right shift: output - alpha - input
esp.vprelu.s8 q5, q4, q5, s1
esp.zero.q q2
esp.vcmp.lt.s8 q6, q4, q2
esp.andq q5, q5, q6
# pos part, *scale, right shift: output - input
esp.zero.qacc
esp.vmulas.s8.qacc q4, q7
esp.srcmb.s8.qacc q3, s8, 1
esp.vcmp.gt.s8 q6, q4, q2
esp.andq q3, q3, q6
esp.vadd.s8 q3, q3, q5
dl_esp32p4_s8_store_remainder q3, a1, a2, a3, a5, a6, a0, a4
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 7,923
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8.S
|
############################################################################################################################################################
# result process for conv2d / depthwise_conv2d
############################################################################################################################################################
.macro esp32p4_s8_conv2d_128b_vector_bias bias_ptr
esp.ld.qacc.l.l.128.ip \bias_ptr, 16
esp.ld.qacc.l.h.128.ip \bias_ptr, 16
esp.ld.qacc.h.l.128.ip \bias_ptr, 16
esp.ld.qacc.h.h.128.ip \bias_ptr, 16
.endm
.macro esp32p4_s8_conv2d_element_bias bias_ptr, tmp
lw \tmp, 0(\bias_ptr)
addi \bias_ptr, \bias_ptr, 4
esp.movx.w.xacc.l \tmp
slti \tmp, \tmp, 0 // if tmp < 0, tmp = 1, otherwise tmp = 0
slli \tmp, \tmp, 31 // shift left to the sign bit.
srai \tmp, \tmp, 31 // extend the sign bit to all bits.
esp.movx.w.xacc.h \tmp
.endm
############################################################################################################################################################
# esp32p4_s8_32b_unaligned_vector series
############################################################################################################################################################
.macro esp32p4_s8_32b_unaligned_vector_store output_v, output_ptr, tmp
esp.movi.32.a \output_v, \tmp, 0
sw \tmp, 0(\output_ptr)
esp.movi.32.a \output_v, \tmp, 1
sw \tmp, 4(\output_ptr)
esp.movi.32.a \output_v, \tmp, 2
sw \tmp, 8(\output_ptr)
esp.movi.32.a \output_v, \tmp, 3
sw \tmp, 12(\output_ptr)
addi \output_ptr, \output_ptr, 16
.endm
############################################################################################################################################################
# esp32p4_s8_64b_unaligned_vector series
############################################################################################################################################################
.macro esp32p4_s8_64b_unaligned_vector_store output_v, output_ptr
esp.vst.l.64.ip \output_v, \output_ptr, 8
esp.vst.h.64.ip \output_v, \output_ptr, 8
.endm
############################################################################################################################################################
# esp32p4_s8_128b_vector series
############################################################################################################################################################
.macro esp32p4_s8_128b_vector_shift_result output_v, mac_shift
esp.srcmb.s8.qacc \output_v, \mac_shift, 1
.endm
.macro esp32p4_s8_128b_aligned_vector_store output_v, output_ptr
esp.vst.128.ip \output_v, \output_ptr, 16
.endm
.macro esp32p4_s8_128b_vector_relu output_v, activation_alpha, activation_shift
# LeakyReLU
esp.vrelu.s8 \output_v, \activation_alpha, \activation_shift
.endm
.macro esp32p4_s8_128b_vector_prelu output_v, activation_alpha_v, activation_alpha_ptr, activation_shift
esp.vld.128.ip \activation_alpha_v, \activation_alpha_ptr, 16
esp.vprelu.s8 \output_v, \output_v, \activation_alpha_v, \activation_shift
.endm
.macro dl_esp32p4_s8_last_store_data tmp_q, output_v, tmp_a, c_remainder_bytes
movi \tmp_a, 15
sub \tmp_a, \tmp_a, \c_remainder_bytes
movi \c_remainder_bytes, 0
esp.slcxxp.2q \tmp_q, \output_v, \tmp_a, \c_remainder_bytes #left shift to make the rest part 0
esp.srcxxp.2q \output_v, \tmp_q, \tmp_a, \c_remainder_bytes #right shift to lower bits
.endm
.macro dl_esp32p4_s8_store_remainder output_v, tmp_a0, tmp_a1, tmp_a2, tmp_a3, tmp_a4, output_ptr, remainder_c
esp.movi.32.a \output_v, \tmp_a0, 0
615: # remainder_c == 15, 0x1111
andi \tmp_a4, \remainder_c, 8
beqz \tmp_a4, 607f
esp.movi.32.a \output_v, \tmp_a1, 1
andi \tmp_a4, \remainder_c, 4
beqz \tmp_a4, 611f
esp.movi.32.a \output_v, \tmp_a2, 2
andi \tmp_a4, \remainder_c, 2
beqz \tmp_a4, 613f
esp.movi.32.a \output_v, \tmp_a3, 3
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 614f
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sw \tmp_a2, 8(\output_ptr)
sh \tmp_a3, 12(\output_ptr)
srai \tmp_a3, \tmp_a3, 16
sb \tmp_a3, 14(\output_ptr)
j 616f
614: # remainder_c == 14, 0x1110
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sw \tmp_a2, 8(\output_ptr)
sh \tmp_a3, 12(\output_ptr)
j 616f
613: # remainder_c == 13, 0x1101
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 612f
esp.movi.32.a \output_v, \tmp_a3, 3
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sw \tmp_a2, 8(\output_ptr)
sb \tmp_a3, 12(\output_ptr)
j 616f
612: # remainder_c == 12, 0x1100
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sw \tmp_a2, 8(\output_ptr)
j 616f
611: # remainder_c == 11, 0x1011
andi \tmp_a4, \remainder_c, 2
beqz \tmp_a4, 609f
esp.movi.32.a \output_v, \tmp_a2, 2
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 610f
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sh \tmp_a2, 8(\output_ptr)
srai \tmp_a2, \tmp_a2, 16
sb \tmp_a2, 10(\output_ptr)
j 616f
610: # remainder_c == 10, 0x1010
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sh \tmp_a2, 8(\output_ptr)
j 616f
609: # remainder_c == 9, 0x1001
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 608f
esp.movi.32.a \output_v, \tmp_a2, 2
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sb \tmp_a2, 8(\output_ptr)
j 616f
608: # remainder_c == 8, 0x1000
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
j 616f
607: # remainder == 7, 0x111
andi \tmp_a4, \remainder_c, 4
beqz \tmp_a4, 603f
andi \tmp_a4, \remainder_c, 2
beqz \tmp_a4, 605f
esp.movi.32.a \output_v, \tmp_a1, 1
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 606f
sw \tmp_a0, 0(\output_ptr)
sh \tmp_a1, 4(\output_ptr)
srai \tmp_a1, \tmp_a1, 16
sb \tmp_a1, 6(\output_ptr)
j 616f
606: # remainder == 6, 0x110
sw \tmp_a0, 0(\output_ptr)
sh \tmp_a1, 4(\output_ptr)
j 616f
605: # remainder == 4, 5
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 604f
# remainder == 5, 0x101
esp.movi.32.a \output_v, \tmp_a1, 1
sw \tmp_a0, 0(\output_ptr)
sb \tmp_a1, 4(\output_ptr)
j 616f
604: # remainder == 4, 0x100
sw \tmp_a0, 0(\output_ptr)
j 616f
603: # remainder == 1, 2, 3
andi \tmp_a4, \remainder_c, 2
beqz \tmp_a4, 601f
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 602f
# remainder == 3, 0x011
sh \tmp_a0, 0(\output_ptr)
srai \tmp_a0, \tmp_a0, 16
sb \tmp_a0, 2(\output_ptr)
j 616f
602: # remainder == 2, 0x010
sh \tmp_a0, 0(\output_ptr)
j 616f
601: # remainder == 1, 0x001
sb \tmp_a0, 0(\output_ptr)
616:
.endm
############################################################################################################################################################
# esp32p4_s8_element series
############################################################################################################################################################
.macro esp32p4_s8_element_result output, mac_shift
esp.srs.s.xacc \output, \mac_shift
.endm
.macro esp32p4_s8_element_store output_ptr, output
sb \output, 0(\output_ptr)
addi \output_ptr, \output_ptr, 1
.endm
.macro esp32p4_s8_element_leakyrelu output, alpha, shift
bgez \output, 0f
mul \output, \output, \alpha
sra \output, \output, \shift
0:
.endm
.macro esp32p4_s8_element_prelu output, alpha_ptr, shift
bgez \output, 0f
mul \output, \output, \alpha_ptr
sra \output, \output, \shift
addi \alpha_ptr, \alpha_ptr, 1
0:
.endm
|
georgevio/IoT-Embedded
| 15,882
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_greaterorequal.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_greaterorequal_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_8_w2_8
.type dl_esp32p4_s16_greaterorequal_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_8_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
esp32p4_s16_greaterorequal_w1_8_w2_8_loop:
beq t0, a3, esp32p4_s16_greaterorequal_w1_8_w2_8_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greaterorequal_w1_8_w2_8_loop
esp32p4_s16_greaterorequal_w1_8_w2_8_end:
ret
#void dl_esp32p4_s16_greaterorequal_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_8_w2_1
.type dl_esp32p4_s16_greaterorequal_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_8_w2_1:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s16_greaterorequal_w1_8_w2_1_loop:
beq t0, a3, esp32p4_s16_greaterorequal_w1_8_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greaterorequal_w1_8_w2_1_loop
esp32p4_s16_greaterorequal_w1_8_w2_1_end:
ret
#void dl_esp32p4_s16_greaterorequal_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_1_w2_8
.type dl_esp32p4_s16_greaterorequal_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_1_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s16_greaterorequal_w1_1_w2_8_loop:
beq t0, a3, esp32p4_s16_greaterorequal_w1_1_w2_8_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greaterorequal_w1_1_w2_8_loop
esp32p4_s16_greaterorequal_w1_1_w2_8_end:
ret
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
// esp.vst.128.ip q2, a0, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 32,480
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_depthwise_conv2d.S
|
#include "dl_esp32p4_s8.S"
############################################################################################################################################################
####
#### esp32p4_s8_depthwise_conv2d_33c1 series
####
############################################################################################################################################################
.macro esp32p4_s8_depthwise_conv2d_33s1 input_v0 filter_v0 input_v1 filter_v1 input_v2 filter_v2 input_ptr filter_ptr dilation_x_offset dilation_y_offset next_33s1
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_33s1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \next_33s1
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
.endm
.macro esp32p4_s8_depthwise_conv2d_33s1_last input_v0 filter_v0 input_v1 filter_v1 input_ptr filter_ptr dilation_x_offset dilation_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.ip \input_v0, \input_ptr, 0
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
# block one cycle here
esp.vmulas.s8.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s8_depthwise_conv2d_33c1_load_args args filter_ptr dilation_x_offset dilation_y_offset next_hwx1 c_div_x_1 mac_shift
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hwx1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
lw \filter_ptr, 48(\args)
lw \dilation_x_offset, 124(\args)
lw \dilation_y_offset, 128(\args)
lw \next_hwx1, 132(\args)
lw \c_div_x_1, 100(\args)
lw \mac_shift, 64 (\args)
.endm
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_bias
.type dl_esp32p4_s8_depthwise_conv2d_33c1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw t6, 68(a2) // bias
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_bias_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_bias_loop_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp.vst.128.ip q3, a0, 16
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_bias_relu
.type dl_esp32p4_s8_depthwise_conv2d_33c1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw t6, 68(a2) // bias
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_bias_relu_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_relu q3, s0, s1
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_bias_relu_loop_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_relu q3, s0, s1
esp.vst.128.ip q3, a0, 16
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_bias_prelu
.type dl_esp32p4_s8_depthwise_conv2d_33c1_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw t6, 68(a2) // bias
lw s0, 80(a2) // activation_alpha_ptr
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_bias_prelu_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_prelu q3, q4, s0, s1
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_bias_prelu_loop_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_prelu q3, q4, s0, s1
esp.vst.128.ip q3, a0, 16
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1
.type dl_esp32p4_s8_depthwise_conv2d_33c1, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_loop_last:
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp.vst.128.ip q3, a0, 16
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_relu
.type dl_esp32p4_s8_depthwise_conv2d_33c1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_relu_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_relu q3, s0, s1
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_relu_loop_last:
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_relu q3, s0, s1
esp.vst.128.ip q3, a0, 16
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_prelu
.type dl_esp32p4_s8_depthwise_conv2d_33c1_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw s0, 80(a2) // activation_alpha_ptr
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_prelu_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_prelu q3, q4, s0, s1
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_prelu_loop_last:
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_prelu q3, q4, s0, s1
esp.vst.128.ip q3, a0, 16
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
############################################################################################################################################################
####
#### esp32p4_s8_depthwise_conv2d_hwc1 series
####
############################################################################################################################################################
.macro esp32p4_s8_depthwise_conv2d_1ws1 input_v0, input_v1, input_v2, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, tmp_value, filter_w, filter_w_rs1_1, filter_y_offset
beqz \filter_w_rs1_1, 1f
# lp.setup 0, \filter_w_rs1_1, 0f
esp.lp.setup 0, \filter_w_rs1_1, 0f
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
0: esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
1:
andi \tmp_value, \filter_w, 0xFFFFFFFE
beq \tmp_value, \filter_w, 2f
# three 8-input-element left
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.xp \filter_v2, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
j 3f
2: # two 8-input-element left
esp.vmulas.s8.qacc.ld.xp \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \dilation_y_offset
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
3:
.endm
.macro esp32p4_s8_depthwise_conv2d_1ws1_last input_v0, input_v1, filter_v0, filter_v1, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, tmp_value, filter_w, filter_w_rs1_1, next_hws1, filter_y_offset
beqz \filter_w_rs1_1, 5f
# lp.setup 0, \filter_w_rs1_1, 4f
esp.lp.setup 0, \filter_w_rs1_1, 4f
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
4: esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
5:
andi \tmp_value, \filter_w, 0xFFFFFFFE
beq \tmp_value, \filter_w, 6f
# three 8-input-element left
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \next_hws1
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
# block one cyle here
esp.vmulas.s8.qacc \input_v0, \filter_v0
j 7f
6: # two 8-input-element left
esp.vmulas.s8.qacc.ld.xp \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \next_hws1
esp.vmulas.s8.qacc \input_v1, \filter_v1
7:
.endm
.macro esp32p4_s8_depthwise_conv2d_hws1 input_v0, input_v1, input_v2, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, next_hws1, filter_h, filter_w, filter_w_rs1_1, args, filter_offset_q, filter_y_offset, tmp_value
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hws1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
# filter_w_rs1_1
lw \filter_h, 52(\args) # filter_height
addi \tmp_value, \filter_w, -1
beqz \tmp_value, 10f
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
addi \filter_h, \filter_h, -1
beqz \filter_h, 9f
// lp.setup 1, \filter_h, 8f
// 8: esp32p4_s8_depthwise_conv2d_1ws1 \input_v0, \input_v1, \input_v2, \filter_v0, \filter_v1, \filter_v2, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \tmp_value, \filter_w, \filter_w_rs1_1, \filter_y_offset
8:
esp32p4_s8_depthwise_conv2d_1ws1 \input_v0, \input_v1, \input_v2, \filter_v0, \filter_v1, \filter_v2, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \tmp_value, \filter_w, \filter_w_rs1_1, \filter_y_offset
addi \filter_h, \filter_h, -1
bgtz \filter_h, 8b
9: # last y
esp32p4_s8_depthwise_conv2d_1ws1_last \input_v0, \input_v1, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \tmp_value, \filter_w, \filter_w_rs1_1, \next_hws1, \filter_y_offset
j 13f
10: # filter_w == 1
esp.vld.128.xp \filter_v0, \filter_ptr, \filter_y_offset
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
beqz \filter_h, 12f
// lp.setup 1, \filter_h, 11f
// esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
// 11: esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
11:
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bgtz \filter_h, 11b
12: # last y
esp.vmulas.s8.qacc \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset
add \input_ptr, \input_ptr, \next_hws1
13:
esp.movi.32.a \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.macro esp32p4_s8_depthwise_conv2d_hwc1_load_args args, filter_ptr, dilation_x_offset, dilation_y_offset, next_hws1, c_div_x_1, mac_shift, filter_w, filter_w_rs1_1
esp32p4_s8_depthwise_conv2d_33c1_load_args \args, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \next_hws1, \c_div_x_1, \mac_shift
lw \filter_w, 56(\args)
lw \filter_w_rs1_1, 148(\args)
.endm
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_bias
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset
# s10:
# s11: tmp_value
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s11, 0(sp)
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s0, 2
lw t6, 68(a2) // bias
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_bias_loop:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_bias_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s11, 0(sp) // restore s11
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_relu
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset / activation_alpha
# s10: activation_shift
# s11: tmp_value
addi sp, sp, -24
sw s0, 20(sp)
sw s1, 16(sp)
sw s8, 12(sp)
sw s9, 8(sp)
sw s10, 4(sp)
sw s11, 0(sp)
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp.movi.32.q q7, s9, 3
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s9, 1
esp.movi.32.q q7, s0, 2
lw t6, 68(a2) // bias
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_bias_relu_loop:
esp.zero.qacc
esp.movi.32.a q7, s9, 1 // filter_y_offset
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.movi.32.a q7, s9, 3 // activation_alpha
esp32p4_s8_128b_vector_relu q0, s9, s10
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_bias_relu_loop
lw s0, 20(sp) // restore s0
lw s1, 16(sp) // restore s1
lw s8, 12(sp) // restore s8
lw s9, 8(sp) // restore s9
lw s10, 4(sp) // restore s10
lw s11, 0(sp) // restore s11
addi sp, sp, 24
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset / activation_alpha
# s10: activation_shift
# s11: tmp_value
addi sp, sp, -24
sw s0, 20(sp)
sw s1, 16(sp)
sw s8, 12(sp)
sw s9, 8(sp)
sw s10, 4(sp)
sw s11, 0(sp)
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp.movi.32.q q7, s9, 3
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s9, 1
esp.movi.32.q q7, s0, 2
lw t6, 68(a2) // bias
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu_loop:
esp.zero.qacc
esp.movi.32.a q7, s9, 1 // filter_y_offset
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.movi.32.a q7, s9, 3 // activation_alpha_ptr
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu_loop
lw s0, 20(sp) // restore s0
lw s1, 16(sp) // restore s1
lw s8, 12(sp) // restore s8
lw s9, 8(sp) // restore s9
lw s10, 4(sp) // restore s10
lw s11, 0(sp) // restore s11
addi sp, sp, 24
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1
.type dl_esp32p4_s8_depthwise_conv2d_hwc1, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset
# s10:
# s11: tmp_value
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s11, 0(sp)
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s0, 2
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_loop:
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s11, 0(sp) // restore s11
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_relu
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset / activation_alpha
# s10: activation_shift
# s11: tmp_value
addi sp, sp, -24
sw s0, 20(sp)
sw s1, 16(sp)
sw s8, 12(sp)
sw s9, 8(sp)
sw s10, 4(sp)
sw s11, 0(sp)
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp.movi.32.q q7, s9, 3
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s9, 1
esp.movi.32.q q7, s0, 2
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_relu_loop:
esp.zero.qacc
esp.movi.32.a q7, s9, 1 // filter_y_offset
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.movi.32.a q7, s9, 3 // activation_alpha
esp32p4_s8_128b_vector_relu q0, s9, s10
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_relu_loop
lw s0, 20(sp) // restore s0
lw s1, 16(sp) // restore s1
lw s8, 12(sp) // restore s8
lw s9, 8(sp) // restore s9
lw s10, 4(sp) // restore s10
lw s11, 0(sp) // restore s11
addi sp, sp, 24
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_prelu
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset / activation_alpha
# s10: activation_shift
# s11: tmp_value
addi sp, sp, -24
sw s0, 20(sp)
sw s1, 16(sp)
sw s8, 12(sp)
sw s9, 8(sp)
sw s10, 4(sp)
sw s11, 0(sp)
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp.movi.32.q q7, s9, 3
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s9, 1
esp.movi.32.q q7, s0, 2
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_prelu_loop:
esp.zero.qacc
esp.movi.32.a q7, s9, 1 // filter_y_offset
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.movi.32.a q7, s9, 3 // activation_alpha_ptr
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_prelu_loop
lw s0, 20(sp) // restore s0
lw s1, 16(sp) // restore s1
lw s8, 12(sp) // restore s8
lw s9, 8(sp) // restore s9
lw s10, 4(sp) // restore s10
lw s11, 0(sp) // restore s11
addi sp, sp, 24
ret
|
georgevio/IoT-Embedded
| 33,602
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_conv2d.S
|
#include "dl_esp32p4_s8.S"
############################################################################################################################################################
####
#### esp32p4_s8_conv2d_11cn series
####
############################################################################################################################################################
.macro esp32p4_s8_conv2d_11c16 input_v0 input_ptr filter_v0 filter_v1 filter_ptr c_div_x_1
# scalar * vecter and accumulate into QACC
# input_ptr += (c_div_x_1 + 1) * 16 in the end
# filter_ptr point to the next 16 bytes in the end
# input_v0: 16 input elements
# filter_v0: 16 filter elements
# filter_v1: 16 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 16 - 1
esp.vld.128.ip \input_v0, \input_ptr, 16
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.ip \filter_v1, \filter_ptr, 16
beqz \c_div_x_1, 1f
# lp.setup 0, \c_div_x_1, 0f
esp.lp.setup 0, \c_div_x_1, 0f
# 0:
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 14
esp.vsmulas.s8.qacc.ld.incp \input_v0, \input_ptr, \filter_v1, \input_v0, 15
0: esp.vld.128.ip \filter_v1, \filter_ptr, 16
# addi \c_div_x_1, \c_div_x_1, -1
# bgtz \c_div_x_1, 0b
1:
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 14
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 15
.endm
############################################################################################################################################################
####
#### esp32p4_s8_conv2d_11cn
####
############################################################################################################################################################
.macro esp32p4_s8_conv2d_11cn_load_args args filter_ptr c_div_x_1 n_rs3 mac_shift
lw \n_rs3, 96(\args) // output_channel_div_8
lw \mac_shift, 64(\args) // mac_shift
lw \filter_ptr, 48(\args) // filter
lw \c_div_x_1, 100(\args) // input_channel / x - 1
.endm
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_bias
.type dl_esp32p4_s8_conv2d_11cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
# Because the subsequent esp.lp.setup loop instruction compares for a value >= 0 and cannot be negative, we subtract 1 in advance here.
# addi a4, a4, -1
lw t4, 68(a2) // bias
esp32p4_s8_conv2d_11cn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_bias_loop
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_bias_relu
.type dl_esp32p4_s8_conv2d_11cn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
lw t4, 68(a2) // bias
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp32p4_s8_conv2d_11cn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, s0, s1
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_bias_relu_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_bias_prelu
.type dl_esp32p4_s8_conv2d_11cn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
lw t4, 68(a2) // bias
lw s0, 80(a2) // activation_alpha_ptr
lw s1, 84(a2) // activation_shift
esp32p4_s8_conv2d_11cn_bias_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, s0, s1
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_bias_prelu_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn
.type dl_esp32p4_s8_conv2d_11cn, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
# Because the subsequent esp.lp.setup loop instruction compares for a value >= 0 and cannot be negative, we subtract 1 in advance here.
# addi a4, a4, -1
esp32p4_s8_conv2d_11cn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_loop
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_relu
.type dl_esp32p4_s8_conv2d_11cn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp32p4_s8_conv2d_11cn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, s0, s1
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_relu_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_prelu
.type dl_esp32p4_s8_conv2d_11cn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
lw s0, 80(a2) // activation_alpha_ptr
lw s1, 84(a2) // activation_shift
esp32p4_s8_conv2d_11cn_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, s0, s1
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_prelu_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
############################################################################################################################################################
####
#### esp32p4_s8_conv2d_33cn series
####
############################################################################################################################################################
.macro esp32p4_s8_conv2d_33c16 input_v0 filter_v0 filter_v1 input_ptr filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro esp32p4_s8_conv2d_hwcn_load_args args filter_ptr c_div_x_1 n_rs3 mac_shift dilation_x_offset dilation_y_offset
esp32p4_s8_conv2d_11cn_load_args \args, \filter_ptr, \c_div_x_1, \n_rs3, \mac_shift
lw \dilation_x_offset, 108(\args) // input dilation x offset
lw \dilation_y_offset, 112(\args) // input dilation y offset
.endm
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_bias
.type dl_esp32p4_s8_conv2d_33cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
esp32p4_s8_conv2d_33cn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_bias_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_bias_relu
.type dl_esp32p4_s8_conv2d_33cn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: activation_alpha/_address
# s9: activation_shift
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw s8, 76(a2) // activation_alpha
lw s9, 84(a2) // activation_shift
esp32p4_s8_conv2d_33cn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, s8, s9
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_bias_relu_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_bias_prelu
.type dl_esp32p4_s8_conv2d_33cn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: activation_alpha/_address
# s9: activation_shift
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw s8, 80(a2) // activation_alpha_ptr
lw s9, 84(a2) // activation_shift
esp32p4_s8_conv2d_33cn_bias_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, s8, s9
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_bias_prelu_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn
.type dl_esp32p4_s8_conv2d_33cn, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
esp32p4_s8_conv2d_33cn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_relu
.type dl_esp32p4_s8_conv2d_33cn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: activation_alpha/_address
# s9: activation_shift
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw s8, 76(a2) // activation_alpha
lw s9, 84(a2) // activation_shift
esp32p4_s8_conv2d_33cn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, s8, s9
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_relu_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_prelu
.type dl_esp32p4_s8_conv2d_33cn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: activation_alpha/_address
# s9: activation_shift
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw s8, 80(a2) // activation_alpha_ptr
lw s9, 84(a2) // activation_shift
esp32p4_s8_conv2d_33cn_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, s8, s9
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_prelu_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
############################################################################################################################################################
####
#### esp32p4_s8_conv2d_hwcn series
####
############################################################################################################################################################
.macro esp32p4_s8_conv2d_hwc16 input_v0 filter_v0 filter_v1 input_ptr filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset filter_h filter_w args filter_offset_q
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
# filter_h
# filter_w
lw \filter_h, 52(\args) # filter_height
2:
lw \filter_w, 56(\args) # filter_width
addi \filter_w, \filter_w, -1
beqz \filter_w, 4f
// lp.setup 1, \filter_w, 3f
// esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
// 3: add \input_ptr, \input_ptr, \dilation_x_offset
3:
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bgtz \filter_w, 3b
4:
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
esp.movi.32.a \filter_offset_q, \filter_w, 1
add \filter_ptr, \filter_ptr, \filter_w
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 2b
esp.movi.32.a \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_bias
.type dl_esp32p4_s8_conv2d_hwcn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_bias_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_bias_relu
.type dl_esp32p4_s8_conv2d_hwcn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6: activation_alpha/_address
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10: activation_shift
# s11:
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s10, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw t6, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, t6, s10
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_bias_relu_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s10, 0(sp) // restore s10
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_bias_prelu
.type dl_esp32p4_s8_conv2d_hwcn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6: activation_alpha/_address
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10: activation_shift
# s11:
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s10, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw t6, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_bias_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, t6, s10
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_bias_prelu_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s10, 0(sp) // restore s10
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn
.type dl_esp32p4_s8_conv2d_hwcn, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_relu
.type dl_esp32p4_s8_conv2d_hwcn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6: activation_alpha/_address
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10: activation_shift
# s11:
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s10, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t6, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, t6, s10
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_relu_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s10, 0(sp) // restore s10
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_prelu
.type dl_esp32p4_s8_conv2d_hwcn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6: activation_alpha/_address
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10: activation_shift
# s11:
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s10, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t6, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, t6, s10
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_prelu_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s10, 0(sp) // restore s10
addi sp, sp, 20
ret
|
georgevio/IoT-Embedded
| 39,676
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_add2d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s16_add2d_11c series
####
############################################################################################################################################################
.macro dl_esp32p4_s16_rescale_add_rescale_output input0, input1, output, output_scale, output_shift
esp.zero.qacc
esp.vmulas.s16.qacc \input0, \output_scale
esp.vmulas.s16.qacc \input1, \output_scale
esp.srcmb.s16.qacc \output, \output_shift, 1
.endm
.align 2
.text
.global dl_esp32p4_s16_add2d_11c
.type dl_esp32p4_s16_add2d_11c, @function
#.section .iram1
dl_esp32p4_s16_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x_1
lw a4, 68(a3)
lw a5, 72(a3)
li t0, 1
blt a4, t0, dl_esp32p4_s16_add2d_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q2, a1, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vadd.s16 q5, q2, q3
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q0, a1, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vst.128.ip q5, a0, 16
esp.vadd.s16 q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_add2d_small_channel:
bltz a5, 5f
add t0, a5, x0
blez t0, 3f
2:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_rescale_add2d_11c
.type dl_esp32p4_s16_rescale_add2d_11c, @function
#.section .iram1
dl_esp32p4_s16_rescale_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_add2d_output
dl_esp32p4_s16_rescale_add2d_output_scale:
sh t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
# addi a4, a4, 1
add t0, a4, x0
blez t0, 3f
2:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_rescale_add2d_output:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 5f
4:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.ldqa.s16.128.ip a2, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 4b
5:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_add2d_11c_relu
.type dl_esp32p4_s16_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s16_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x
# s8: activation_alpha
# s9: activation_shift
lw a4, 68(a3)
lw a5, 72(a3)
lw s8, 52(a3)
lw s9, 60(a3)
beqz a4, dl_esp32p4_s16_add2d_relu_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s16 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vrelu.s16 q5, s8, s9
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q2, a1, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s16 q4, s8, s9
esp.vst.128.ip q4, a0, 16
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vadd.s16 q5, q2, q3
esp.vrelu.s16 q5, s8, s9
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q0, a1, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vrelu.s16 q5, s8, s9
esp.vst.128.ip q5, a0, 16
esp.vadd.s16 q4, q0, q1
esp.vrelu.s16 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_add2d_relu_small_channel:
bltz a5, 5f
add t0, a5, x0
blez t0, 3f
2:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vrelu.s16 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vrelu.s16 q2, s8, s9
esp.vst.128.ip q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_rescale_add2d_11c_relu
.type dl_esp32p4_s16_rescale_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s16_rescale_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
lw s8, 52(a3)
lw s9, 60(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_add2d_output_relu
dl_esp32p4_s16_rescale_add2d_output_scale_relu:
sh t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
add t0, a4, x0
blez t0, 3f
2:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vrelu.s16 q1, s8, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vrelu.s16 q1, s8, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_rescale_add2d_output_relu:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 5f
4:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.ldqa.s16.128.ip a2, 16
esp.vrelu.s16 q1, s8, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 4b
5:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.vrelu.s16 q1, s8, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_add2d_11c_prelu
.type dl_esp32p4_s16_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s16_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 68(a3)
lw a5, 72(a3)
lw s8, 56(a3)
lw s9, 60(a3)
beqz a4, dl_esp32p4_s16_add2d_prelu_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s16 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vprelu.s16 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s16 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q5, q2, q3
esp.vprelu.s16 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vprelu.s16 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q4, q0, q1
esp.vprelu.s16 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_add2d_prelu_small_channel:
bltz a5, 5f
add t0, a5, x0
blez t0, 3f
2:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q0, q1
esp.vprelu.s16 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q0, q1
esp.vprelu.s16 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_rescale_add2d_11c_prelu
.type dl_esp32p4_s16_rescale_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s16_rescale_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
lw s8, 56(a3)
lw s9, 60(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_add2d_output_prelu
dl_esp32p4_s16_rescale_add2d_output_scale_prelu:
sh t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
# addi a4, a4, 1
add t0, a4, x0
blez t0, 3f
2:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vld.128.ip q5, s8, 16
esp.vprelu.s16 q1, q1, q5, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vld.128.ip q5, s8, 16
esp.vprelu.s16 q1, q1, q5, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_rescale_add2d_output_prelu:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 5f
4:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.vld.128.ip q6, s8, 16
esp.ldqa.s16.128.ip a2, 16
esp.vprelu.s16 q1, q1, q6, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 4b
5:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc q0, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s16.qacc q1, t4, 1
esp.vprelu.s16 q1, q1, q6, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
############################################################################################################################################################
####
#### esp32p4_s16_unaligned_add2d_11c series
####
############################################################################################################################################################
.align 2
.text
.global dl_esp32p4_s16_unaligned_add2d_11c
.type dl_esp32p4_s16_unaligned_add2d_11c, @function
#.section .iram1
dl_esp32p4_s16_unaligned_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_unaligned_add2d_11c_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_unaligned_add2d_11c_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_unaligned_add2d_11c_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_unaligned_add2d_11c_remainder
#output sar = 0
dl_esp32p4_s16_unaligned_add2d_11c_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_unaligned_add2d_11c_remainder
#output sar = 8
dl_esp32p4_s16_unaligned_add2d_11c_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_unaligned_add2d_11c_remainder
dl_esp32p4_s16_unaligned_add2d_11c_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_unaligned_add2d_11c_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vadd.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s16_unaligned_rescale_add2d_11c:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_unaligned_add2d_output_shift
### rescaled to output by *scale) >> shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_scale:
sw t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder
dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s0, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_shift:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder
dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q5, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_unaligned_add2d_11c_relu
.type dl_esp32p4_s16_unaligned_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s16_unaligned_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
lw s8, 52(a3)
lw s9, 60(a3)
bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c_relu
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_unaligned_add2d_11c_small_remainder_relu # channel < 8
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_unaligned_add2d_11c_relu_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_unaligned_add2d_11c_relu_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_relu
#output sar = 0
dl_esp32p4_s16_unaligned_add2d_11c_relu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vrelu.s16 q2, s8, s9
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_relu
#output sar = 8
dl_esp32p4_s16_unaligned_add2d_11c_relu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_relu
dl_esp32p4_s16_unaligned_add2d_11c_small_remainder_relu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_unaligned_add2d_11c_remainder_relu:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end_relu
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vrelu.s16 q2, s8, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end_relu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s16_unaligned_rescale_add2d_11c_relu:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_unaligned_add2d_output_shift_relu
### rescaled to output by *scale) >> shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_scale_relu:
sw t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder_relu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder_relu
dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder_relu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder_relu:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end_relu # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vrelu.s16 q2, s8, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end_relu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_shift_relu:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder_relu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q5, s8, s9
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.vrelu.s16 q5, s8, s9
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder_relu
dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder_relu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder_relu:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end_relu # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.vrelu.s16 q5, s8, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q5, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end_relu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_unaligned_add2d_11c_prelu
.type dl_esp32p4_s16_unaligned_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s16_unaligned_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
lw s8, 56(a3)
lw s9, 60(a3)
bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c_prelu
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_unaligned_add2d_11c_small_remainder_prelu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_unaligned_add2d_11c_prelu_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_unaligned_add2d_11c_prelu_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q2, q5
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_prelu
#output sar = 0
dl_esp32p4_s16_unaligned_add2d_11c_prelu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q2, q5
esp.vprelu.s16 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_prelu
#output sar = 8
dl_esp32p4_s16_unaligned_add2d_11c_prelu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q2, q5
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_prelu
dl_esp32p4_s16_unaligned_add2d_11c_small_remainder_prelu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_unaligned_add2d_11c_remainder_prelu:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end_prelu
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q2, q5
esp.vprelu.s16 q2, q2, q6, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end_prelu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s16_unaligned_rescale_add2d_11c_prelu:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_unaligned_add2d_output_shift_prelu
### rescaled to output by *scale) >> shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_scale_prelu:
sw t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
# ssr t4 #output shift
# li s1, 0
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder_prelu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
esp.vld.128.ip q6, s8, 16
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder_prelu
dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder_prelu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder_prelu:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end_prelu # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
esp.vld.128.ip q6, s8, 16
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vprelu.s16 q2, q2, q6, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end_prelu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_shift_prelu:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder_prelu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q5, q5, q6, s9
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s16.qacc q5, t4, 1
esp.vprelu.s16 q5, q5, q6, s9
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder_prelu
dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder_prelu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder_prelu:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end_prelu # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s16.qacc q5, t4, 1
esp.vprelu.s16 q5, q5, q6, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q5, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end_prelu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
gitwillsky/learning_rcore
| 1,074
|
ch2/src/link_app.S
|
.align 3
.section .data
.global _num_app
_num_app:
.quad 5
.quad app_0_start
.quad app_1_start
.quad app_2_start
.quad app_3_start
.quad app_4_start
.quad app_4_end
.section .data
.global app_0_start
.global app_0_end
app_0_start:
.incbin "../ch2_user/target/riscv64gc-unknown-none-elf/release/00hello_world.bin"
app_0_end:
.section .data
.global app_1_start
.global app_1_end
app_1_start:
.incbin "../ch2_user/target/riscv64gc-unknown-none-elf/release/01store_fault.bin"
app_1_end:
.section .data
.global app_2_start
.global app_2_end
app_2_start:
.incbin "../ch2_user/target/riscv64gc-unknown-none-elf/release/02power_3.bin"
app_2_end:
.section .data
.global app_3_start
.global app_3_end
app_3_start:
.incbin "../ch2_user/target/riscv64gc-unknown-none-elf/release/03priv_inst.bin"
app_3_end:
.section .data
.global app_4_start
.global app_4_end
app_4_start:
.incbin "../ch2_user/target/riscv64gc-unknown-none-elf/release/04sleep.bin"
app_4_end:
|
gitwillsky/learning_rcore
| 1,727
|
ch2/src/trap/trap.S
|
.altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text
.globl __alltraps
.globl __restore
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->kernel stack, sscratch->user stack
# allocate a TrapContext on kernel stack
addi sp, sp, -34*8
# save general-purpose registers
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they were saved on kernel stack
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it on the kernel stack
csrr t2, sscratch
sd t2, 2*8(sp)
# set input argument of trap_handler(cx: &mut TrapContext)
mv a0, sp
call trap_handler
__restore:
# case1: start running app by __restore
# case2: back to U after handling trap
mv sp, a0
# now sp->kernel stack(after allocated), sscratch->user stack
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
ld t2, 2*8(sp)
csrw sstatus, t0
csrw sepc, t1
csrw sscratch, t2
# restore general-purpuse registers except sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# release TrapContext on kernel stack
addi sp, sp, 34*8
# now sp->kernel stack, sscratch->user stack
csrrw sp, sscratch, sp
sret
|
gitwillsky/learning_rcore
| 2,629
|
ch5/src/link_app.S
|
.align 3
.section .data
.global _num_app
_num_app:
.quad 11
.quad app_0_start
.quad app_1_start
.quad app_2_start
.quad app_3_start
.quad app_4_start
.quad app_5_start
.quad app_6_start
.quad app_7_start
.quad app_8_start
.quad app_9_start
.quad app_10_start
.quad app_10_end
.global _app_names
_app_names:
.string "exit"
.string "fork"
.string "hello_world"
.string "initproc"
.string "power_3"
.string "priv_inst"
.string "sbrk_test"
.string "sleep"
.string "stackoverflow"
.string "store_fault"
.string "user_shell"
.section .data
.global app_0_start
.global app_0_end
.align 3
app_0_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/exit"
app_0_end:
.section .data
.global app_1_start
.global app_1_end
.align 3
app_1_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/fork"
app_1_end:
.section .data
.global app_2_start
.global app_2_end
.align 3
app_2_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/hello_world"
app_2_end:
.section .data
.global app_3_start
.global app_3_end
.align 3
app_3_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/initproc"
app_3_end:
.section .data
.global app_4_start
.global app_4_end
.align 3
app_4_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/power_3"
app_4_end:
.section .data
.global app_5_start
.global app_5_end
.align 3
app_5_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/priv_inst"
app_5_end:
.section .data
.global app_6_start
.global app_6_end
.align 3
app_6_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/sbrk_test"
app_6_end:
.section .data
.global app_7_start
.global app_7_end
.align 3
app_7_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/sleep"
app_7_end:
.section .data
.global app_8_start
.global app_8_end
.align 3
app_8_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/stackoverflow"
app_8_end:
.section .data
.global app_9_start
.global app_9_end
.align 3
app_9_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/store_fault"
app_9_end:
.section .data
.global app_10_start
.global app_10_end
.align 3
app_10_start:
.incbin "../ch5_user/target/riscv64gc-unknown-none-elf/release/user_shell"
app_10_end:
|
gitwillsky/learning_rcore
| 1,822
|
ch5/src/trap/trap.S
|
.altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text.trampoline
.globl __alltraps
.globl __restore
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->*TrapContext in user space, sscratch->user stack
# save other general purpose registers
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they have been saved in TrapContext
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it in TrapContext
csrr t2, sscratch
sd t2, 2*8(sp)
# load kernel_satp into t0
ld t0, 34*8(sp)
# load trap_handler into t1
ld t1, 36*8(sp)
# move to kernel_sp
ld sp, 35*8(sp)
# switch to kernel space
csrw satp, t0
sfence.vma
# jump to trap_handler
jr t1
__restore:
# a0: *TrapContext in user space(Constant); a1: user space token
# switch to user space
csrw satp, a1
sfence.vma
csrw sscratch, a0
mv sp, a0
# now sp points to TrapContext in user space, start restoring based on it
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
csrw sstatus, t0
csrw sepc, t1
# restore general purpose registers except x0/sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# back to user stack
ld sp, 2*8(sp)
sret
|
gitwillsky/learning_rcore
| 1,324
|
ch4/src/link_app.S
|
.align 3
.section .data
.global _num_app
_num_app:
.quad 6
.quad app_0_start
.quad app_1_start
.quad app_2_start
.quad app_3_start
.quad app_4_start
.quad app_5_start
.quad app_5_end
.section .data
.global app_0_start
.global app_0_end
.align 3
app_0_start:
.incbin "../ch4_user/target/riscv64gc-unknown-none-elf/release/00hello_world"
app_0_end:
.section .data
.global app_1_start
.global app_1_end
.align 3
app_1_start:
.incbin "../ch4_user/target/riscv64gc-unknown-none-elf/release/01store_fault"
app_1_end:
.section .data
.global app_2_start
.global app_2_end
.align 3
app_2_start:
.incbin "../ch4_user/target/riscv64gc-unknown-none-elf/release/02power_3"
app_2_end:
.section .data
.global app_3_start
.global app_3_end
.align 3
app_3_start:
.incbin "../ch4_user/target/riscv64gc-unknown-none-elf/release/03priv_inst"
app_3_end:
.section .data
.global app_4_start
.global app_4_end
.align 3
app_4_start:
.incbin "../ch4_user/target/riscv64gc-unknown-none-elf/release/04sleep"
app_4_end:
.section .data
.global app_5_start
.global app_5_end
.align 3
app_5_start:
.incbin "../ch4_user/target/riscv64gc-unknown-none-elf/release/05sbrk_test"
app_5_end:
|
gitwillsky/learning_rcore
| 1,822
|
ch4/src/trap/trap.S
|
.altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text.trampoline
.globl __alltraps
.globl __restore
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->*TrapContext in user space, sscratch->user stack
# save other general purpose registers
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they have been saved in TrapContext
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it in TrapContext
csrr t2, sscratch
sd t2, 2*8(sp)
# load kernel_satp into t0
ld t0, 34*8(sp)
# load trap_handler into t1
ld t1, 36*8(sp)
# move to kernel_sp
ld sp, 35*8(sp)
# switch to kernel space
csrw satp, t0
sfence.vma
# jump to trap_handler
jr t1
__restore:
# a0: *TrapContext in user space(Constant); a1: user space token
# switch to user space
csrw satp, a1
sfence.vma
csrw sscratch, a0
mv sp, a0
# now sp points to TrapContext in user space, start restoring based on it
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
csrw sstatus, t0
csrw sepc, t1
# restore general purpose registers except x0/sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# back to user stack
ld sp, 2*8(sp)
sret
|
gitwillsky/learning_rcore
| 1,074
|
ch3/src/link_app.S
|
.align 3
.section .data
.global _num_app
_num_app:
.quad 5
.quad app_0_start
.quad app_1_start
.quad app_2_start
.quad app_3_start
.quad app_4_start
.quad app_4_end
.section .data
.global app_0_start
.global app_0_end
app_0_start:
.incbin "../ch3_user/target/riscv64gc-unknown-none-elf/release/00hello_world.bin"
app_0_end:
.section .data
.global app_1_start
.global app_1_end
app_1_start:
.incbin "../ch3_user/target/riscv64gc-unknown-none-elf/release/01store_fault.bin"
app_1_end:
.section .data
.global app_2_start
.global app_2_end
app_2_start:
.incbin "../ch3_user/target/riscv64gc-unknown-none-elf/release/02power_3.bin"
app_2_end:
.section .data
.global app_3_start
.global app_3_end
app_3_start:
.incbin "../ch3_user/target/riscv64gc-unknown-none-elf/release/03priv_inst.bin"
app_3_end:
.section .data
.global app_4_start
.global app_4_end
app_4_start:
.incbin "../ch3_user/target/riscv64gc-unknown-none-elf/release/04sleep.bin"
app_4_end:
|
gitwillsky/learning_rcore
| 1,627
|
ch3/src/trap/trap.S
|
.altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text
.globl __alltraps
.globl __restore
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->kernel stack, sscratch->user stack
# allocate a TrapContext on kernel stack
addi sp, sp, -34*8
# save general-purpose registers
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they were saved on kernel stack
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it on the kernel stack
csrr t2, sscratch
sd t2, 2*8(sp)
# set input argument of trap_handler(cx: &mut TrapContext)
mv a0, sp
call trap_handler
__restore:
# now sp->kernel stack(after allocated), sscratch->user stack
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
ld t2, 2*8(sp)
csrw sstatus, t0
csrw sepc, t1
csrw sscratch, t2
# restore general-purpuse registers except sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# release TrapContext on kernel stack
addi sp, sp, 34*8
# now sp->kernel stack, sscratch->user stack
csrrw sp, sscratch, sp
sret
|
gk69-cz/Static-malware-analyser
| 23,728
|
executable/Ghidra/Processors/HCS08/data/test-vectors/HCS08_tv.s
|
.hcs08
.area DIRECT (PAG)
;.setdp 0, DIRECT
;low_data1:
;.ds 1
.area PROGRAM (ABS)
.org 0x80
LOW_SUB_TEST:
RTS
.org 0x2000
HIGH_SUB_TEST:
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1
ADC #0xFE
ADC *0xFE
ADC 0xFEDC
ADC 0xFEDC,X
ADC 0xFE,X
ADC ,X
; @if defined(HCS08) || defined(HC08)
; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP
ADC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP
ADC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1
ADD #0xFE
ADD *0xFE
ADD 0xFEDC
ADD 0xFEDC,X
ADD 0xFE,X
ADD ,X
; @if defined(HCS08) || defined(HC08)
; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP
ADD 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP
ADD 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : AIS iopr8is is op=0xA7; iopr8is
AIS #0x7F
AIS #-0x7F
; @if defined(HCS08) || defined(HC08)
; : AIX iopr8is is op=0xAF; iopr8is
AIX #0x7F
AIX #-0x7F
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1
AND #0xFE
AND *0xFE
AND 0xFEDC
AND 0xFEDC,X
AND 0xFE,X
AND ,X
; @if defined(HCS08) || defined(HC08)
; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP
AND 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP
AND 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLA is op=0x48
ASLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLX is op=0x58
ASLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
ASL *0xFE
ASL 0xFE,X
ASL ,X
; @if defined(HCS08) || defined(HC08)
; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP
ASL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRA is op=0x47
ASRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRX is op=0x57
ASRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1
ASR *0xFE
ASR 0xFE,X
ASR ,X
; @if defined(HCS08) || defined(HC08)
; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP
ASR 0xFE,S
BACKWARDS1:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCC REL is op=0x24; REL
BCC BACKWARDS1
BCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8
BCLR #0, *0xFE
BCLR #1, *0xED
BCLR #2, *0xDC
BCLR #3, *0xCB
BCLR #4, *0xBA
BCLR #5, *0xA9
BCLR #6, *0x98
BCLR #7, *0x87
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCS REL is op=0x25; REL
BCS BACKWARDS1
BCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BEQ REL is op=0x27; REL
BEQ BACKWARDS1
BEQ FORWARDS1
; @if defined(HCS08) || defined(HC08)
; : BGE REL is op=0x90; REL
BGE BACKWARDS1
BGE FORWARDS1
; @if defined(HCS08)
; : BGND is op=0x82
BGND
; @if defined(HCS08) || defined(HC08)
; : BGT REL is op=0x92; REL
BGT BACKWARDS1
BGT FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCC REL is op=0x28; REL
BHCC BACKWARDS1
BHCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCS REL is op=0x29; REL
BHCS BACKWARDS1
BHCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHI REL is op=0x22; REL
BHI BACKWARDS1
BHI FORWARDS1
; :BHS REL is op=0x24; REL See BCC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIH REL is op=0x2F; REL
BIH BACKWARDS1
BIH FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIL REL is op=0x2E; REL
BIL BACKWARDS1
BIL FORWARDS1
FORWARDS1:
BACKWARDS2:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1
BIT #0xFE
BIT *0xFE
BIT 0xFEDC
BIT 0xFEDC,X
BIT 0xFE,X
BIT ,X
; @if defined(HCS08) || defined(HC08)
; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP
BIT 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP
BIT 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : BLE REL is op=0x93; REL
BLE BACKWARDS2
BLE FORWARDS2
; :BLO REL is op=0x25; REL see BCS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BLS REL is op=0x23; REL
BLS BACKWARDS2
BLS FORWARDS2
; @if defined(HCS08) || defined(HC08)
; : BLT REL is op=0x91; REL
BLT BACKWARDS2
BLT FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMC REL is op=0x2C; REL
BMC BACKWARDS2
BMC FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMI REL is op=0x2B; REL
BMI BACKWARDS2
BMI FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMS REL is op=0x2D; REL
BMS BACKWARDS2
BMS FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BNE REL is op=0x26; REL
BNE BACKWARDS2
BNE FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BPL REL is op=0x2A; REL
BPL BACKWARDS2
BPL FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRA REL is op=0x20; REL
BRA BACKWARDS2
BRA FORWARDS2
FORWARDS2:
BACKWARDS3:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL
BRCLR #0, *0xFE,BACKWARDS3
BRCLR #1, *0xED,BACKWARDS3
BRCLR #2, *0xDC,BACKWARDS3
BRCLR #3, *0xCB,BACKWARDS3
BRCLR #4, *0xBA,BACKWARDS3
BRCLR #5, *0xA9,BACKWARDS3
BRCLR #6, *0x98,BACKWARDS3
BRCLR #7, *0x87,BACKWARDS3
BRCLR #0, *0xFE,FORWARDS3
BRCLR #1, *0xED,FORWARDS3
BRCLR #2, *0xDC,FORWARDS3
BRCLR #3, *0xCB,FORWARDS3
BRCLR #4, *0xBA,FORWARDS3
BRCLR #5, *0xA9,FORWARDS3
BRCLR #6, *0x98,FORWARDS3
BRCLR #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; branch never is a two-byte nop
; : BRN REL is op=0x21; REL
BRN BACKWARDS3
BRN FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL
BRSET #0, *0xFE,BACKWARDS3
BRSET #1, *0xED,BACKWARDS3
BRSET #2, *0xDC,BACKWARDS3
BRSET #3, *0xCB,BACKWARDS3
BRSET #4, *0xBA,BACKWARDS3
BRSET #5, *0xA9,BACKWARDS3
BRSET #6, *0x98,BACKWARDS3
BRSET #7, *0x87,BACKWARDS3
BRSET #0, *0xFE,FORWARDS3
BRSET #1, *0xED,FORWARDS3
BRSET #2, *0xDC,FORWARDS3
BRSET #3, *0xCB,FORWARDS3
BRSET #4, *0xBA,FORWARDS3
BRSET #5, *0xA9,FORWARDS3
BRSET #6, *0x98,FORWARDS3
BRSET #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8
BSET #0, *0xFE
BSET #1, *0xED
BSET #2, *0xDC
BSET #3, *0xCB
BSET #4, *0xBA
BSET #5, *0xA9
BSET #6, *0x98
BSET #7, *0x87
FORWARDS3:
BACKWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSR REL is op=0xAD; REL
BSR BACKWARDS4
BSR FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL
CBEQ *0xFE, BACKWARDS4
CBEQ *0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL
CBEQA #0xFE, BACKWARDS4
CBEQA #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL
CBEQX #0xFE, BACKWARDS4
CBEQX #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8, X"+", REL is (op=0x61) & X; oprx8; REL
CBEQ *0xFE, X+, BACKWARDS4
CBEQ *0xFE, X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ ","X"+", REL is (op=0x71) & X; REL
CBEQ ,X+, BACKWARDS4
CBEQ ,X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL
CBEQ 0xFE,S, BACKWARDS4
CBEQ 0xFE,S, FORWARDS4
FORWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLC is op=0x98
CLC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLI is op=0x9A
CLI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRA is op=0x4F
CLRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRX is op=0x5F
CLRX
; @if defined(HCS08) || defined(HC08)
; : CLRH is op=0x8C
CLRH
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1
CLR *0xFE
CLR 0xFE,X
CLR ,X
; @if defined(HCS08) || defined(HC08)
; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP
CLR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1
CMP #0xFE
CMP *0xFE
CMP 0xFEDC
CMP 0xFEDC,X
CMP 0xFE,X
CMP ,X
; @if defined(HCS08) || defined(HC08)
; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP
CMP 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP
CMP 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMA is op=0x43
COMA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMX is op=0x53
COMX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1
COM *0xFE
COM 0xFE,X
COM ,X
; @if defined(HCS08) || defined(HC08)
; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP
COM 0xFE,S
; @if defined(HCS08)
; : CPHX opr16a_16 is (op=0x3E); opr16a_16
CPHX 0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX iopr16i is (op=0x65); iopr16i
CPHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX opr8a_16 is (op=0x75); opr8a_16
CPHX *0xFE
; @if defined(HCS08)
; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP
CPHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1
CPX #0xFE
CPX *0xFE
CPX 0xFEDC
CPX 0xFEDC,X
CPX 0xFE,X
CPX ,X
; @if defined(HCS08) || defined(HC08)
; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP
CPX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP
CPX 0xFE,S
BACKWARDS5:
; @if defined(HCS08) || defined(HC08)
; : DAA is op=0x72
DAA
; @if defined(HCS08) || defined(HC08)
; : DBNZA REL is op=0x4B; REL
DBNZA BACKWARDS5
DBNZA FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZX REL is op=0x5B; REL
DBNZX BACKWARDS5
DBNZX FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL
DBNZ *0xFE, BACKWARDS5
DBNZ 0xFE,X, BACKWARDS5
DBNZ ,X, BACKWARDS5
DBNZ *0xFE, FORWARDS5
DBNZ 0xFE,X, FORWARDS5
DBNZ ,X, FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL
DBNZ 0xFE,S, BACKWARDS5
DBNZ 0xFE,S, FORWARDS5
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECA is op=0x4A
DECA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECX is op=0x5A
DECX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1
DEC *0xFE
DEC 0xFE,X
DEC ,X
; @if defined(HCS08) || defined(HC08)
; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP
DEC 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : DIV is op=0x52
DIV
FORWARDS5:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1
EOR #0xFE
EOR *0xFE
EOR 0xFEDC
EOR 0xFEDC,X
EOR 0xFE,X
EOR ,X
; @if defined(HCS08) || defined(HC08)
; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP
EOR 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP
EOR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCA is op=0x4C
INCA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCX is op=0x5C
INCX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1
INC *0xFE
INC 0xFE,X
INC ,X
; @if defined(HCS08) || defined(HC08)
; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP
INC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR
JMP *LOW_SUB_TEST
JMP HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI
JMP 0xFEDC,X
JMP 0xFE,X
JMP ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR
JSR *LOW_SUB_TEST
JSR HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI
JSR 0xFEDC,X
JSR 0xFE,X
JSR ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1
LDA #0xFE
LDA *0xFE
LDA 0xFEDC
LDA 0xFEDC,X
LDA 0xFE,X
LDA ,X
; @if defined(HCS08) || defined(HC08)
; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP
LDA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP
LDA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : LDHX iopr16i is (op=0x45); iopr16i
LDHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : LDHX opr8a_16 is (op=0x55); opr8a_16
LDHX *0xFE
; @if defined(HCS08)
; : LDHX opr16a_16 is (op=0x32); opr16a_16
LDHX 0xFEDC
; @if defined(HCS08)
; : LDHX ","X is (op16=0x9EAE) & X
LDHX ,X
; @if defined(HCS08)
; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X
LDHX 0xFEDC,X
; @if defined(HCS08)
; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X
LDHX 0xFE,X
; @if defined(HCS08)
; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP
LDHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1
LDX #0xFE
LDX *0xFE
LDX 0xFEDC
LDX 0xFEDC,X
LDX 0xFE,X
LDX ,X
; @if defined(HCS08) || defined(HC08)
; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP
LDX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP
LDX 0xFE,S
; ## Logical Shift left is same as arithmetic shift left
; :LSLA is op=0x48
; :LSLX is op=0x58
; :LSL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRA is op=0x44
LSRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRX is op=0x54
LSRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1
LSR *0xFE
LSR 0xFE,X
LSR ,X
; @if defined(HCS08) || defined(HC08)
; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP
LSR 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, op2_opr8a is (op=0x4E); opr8a_8; op2_opr8a
MOV *0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, X"+" is (op=0x5E); opr8a_8 & X
MOV 0xFE, X+
; @if defined(HCS08) || defined(HC08)
; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a
MOV #0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV ","X"+," op2_opr8a is (op=0x7E) & X; op2_opr8a
MOV ,X+, *0xFE
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : MUL is op=0x42
MUL
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGA is op=0x40
NEGA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGX is op=0x50
NEGX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1
NEG *0xFE
NEG 0xFE,X
NEG ,X
; @if defined(HCS08) || defined(HC08)
; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP
NEG 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NOP is op = 0x9D
NOP
; @if defined(HCS08) || defined(HC08)
; : NSA is op = 0x62
NSA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1
ORA #0xFE
ORA *0xFE
ORA 0xFEDC
ORA 0xFEDC,X
ORA 0xFE,X
ORA ,X
; @if defined(HCS08) || defined(HC08)
; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP
ORA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP
ORA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : PSHA is op = 0x87
PSHA
; @if defined(HCS08) || defined(HC08)
; : PSHH is op = 0x8B
PSHH
; @if defined(HCS08) || defined(HC08)
; : PSHX is op = 0x89
PSHX
; @if defined(HCS08) || defined(HC08)
; : PULA is op = 0x86
PULA
; @if defined(HCS08) || defined(HC08)
; : PULH is op = 0x8A
PULH
; @if defined(HCS08) || defined(HC08)
; : PULX is op = 0x88
PULX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLA is op=0x49
ROLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLX is op=0x59
ROLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1
ROL *0xFE
ROL 0xFE,X
ROL ,X
; @if defined(HCS08) || defined(HC08)
; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP
ROL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORA is op=0x46
RORA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORX is op=0x56
RORX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1
ROR *0xFE
ROR 0xFE,X
ROR ,X
; @if defined(HCS08) || defined(HC08)
; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP
ROR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RSP is op = 0x9C
RSP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTI is op = 0x80
RTI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTS is op = 0x81
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1
SBC #0xFE
SBC *0xFE
SBC 0xFEDC
SBC 0xFEDC,X
SBC 0xFE,X
SBC ,X
; @if defined(HCS08) || defined(HC08)
; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP
SBC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP
SBC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEC is op = 0x99
SEC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEI is op = 0x9B
SEI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1
STA *0xFE
STA 0xFEDC
STA 0xFEDC,X
STA 0xFE,X
STA ,X
; @if defined(HCS08) || defined(HC08)
; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP
STA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP
STA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : STHX opr8a_16 is (op=0x35); opr8a_16
STHX *0xFE
; @if defined(HCS08)
; : STHX opr16a_16 is (op=0x96); opr16a_16
STHX 0xFEDC
; @if defined(HCS08)
; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP
STHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STOP is op=0x8E
STOP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1
STX *0xFE
STX 0xFEDC
STX 0xFEDC,X
STX 0xFE,X
STX ,X
; @if defined(HCS08) || defined(HC08)
; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP
STX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP
STX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1
SUB #0xFE
SUB *0xFE
SUB 0xFEDC
SUB 0xFEDC,X
SUB 0xFE,X
SUB ,X
; @if defined(HCS08) || defined(HC08)
; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP
SUB 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP
SUB 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SWI is op=0x83
SWI
; @if defined(HCS08) || defined(HC08)
; : TAP is op=0x84
TAP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TAX is op=0x97
TAX
; @if defined(HCS08) || defined(HC08)
; : TPA is op=0x85
TPA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTA is op=0x4D
TSTA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTX is op=0x5D
TSTX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1
TST *0xFE
TST 0xFE,X
TST ,X
; @if defined(HCS08) || defined(HC08)
; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP
TST 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : TSX is op=0x95
TSX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TXA is op=0x9F
TXA
; @if defined(HCS08) || defined(HC08)
; : TXS is op=0x94
TXS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : WAIT is op=0x8f
WAIT
HERE:
BRA HERE
|
gk69-cz/Static-malware-analyser
| 23,835
|
executable/Ghidra/Processors/HCS08/data/test-vectors/HC05_tv.s
|
.hc05
.area DIRECT (PAG)
;.setdp 0, DIRECT
;low_data1:
;.ds 1
.area PROGRAM (ABS)
.org 0x80
LOW_SUB_TEST:
RTS
.org 0x2000
HIGH_SUB_TEST:
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1
ADC #0xFE
ADC *0xFE
ADC 0xFEDC
ADC 0xFEDC,X
ADC 0xFE,X
ADC ,X
; @if defined(HCS08) || defined(HC08)
; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP
; ADC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP
; ADC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1
ADD #0xFE
ADD *0xFE
ADD 0xFEDC
ADD 0xFEDC,X
ADD 0xFE,X
ADD ,X
; @if defined(HCS08) || defined(HC08)
; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP
; ADD 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP
; ADD 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : AIS iopr8is is op=0xA7; iopr8is
; AIS #0x7F
; AIS #-0x7F
; @if defined(HCS08) || defined(HC08)
; : AIX iopr8is is op=0xAF; iopr8is
; AIX #0x7F
; AIX #-0x7F
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1
AND #0xFE
AND *0xFE
AND 0xFEDC
AND 0xFEDC,X
AND 0xFE,X
AND ,X
; @if defined(HCS08) || defined(HC08)
; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP
; AND 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP
; AND 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLA is op=0x48
ASLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLX is op=0x58
ASLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
ASL *0xFE
ASL 0xFE,X
ASL ,X
; @if defined(HCS08) || defined(HC08)
; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP
; ASL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRA is op=0x47
ASRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRX is op=0x57
ASRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1
ASR *0xFE
ASR 0xFE,X
ASR ,X
; @if defined(HCS08) || defined(HC08)
; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP
; ASR 0xFE,S
BACKWARDS1:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCC REL is op=0x24; REL
BCC BACKWARDS1
BCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8
BCLR #0, *0xFE
BCLR #1, *0xED
BCLR #2, *0xDC
BCLR #3, *0xCB
BCLR #4, *0xBA
BCLR #5, *0xA9
BCLR #6, *0x98
BCLR #7, *0x87
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCS REL is op=0x25; REL
BCS BACKWARDS1
BCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BEQ REL is op=0x27; REL
BEQ BACKWARDS1
BEQ FORWARDS1
; @if defined(HCS08) || defined(HC08)
; : BGE REL is op=0x90; REL
; BGE BACKWARDS1
; BGE FORWARDS1
; @if defined(HCS08)
; : BGND is op=0x82
; BGND
; @if defined(HCS08) || defined(HC08)
; : BGT REL is op=0x92; REL
; BGT BACKWARDS1
; BGT FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCC REL is op=0x28; REL
BHCC BACKWARDS1
BHCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCS REL is op=0x29; REL
BHCS BACKWARDS1
BHCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHI REL is op=0x22; REL
BHI BACKWARDS1
BHI FORWARDS1
; :BHS REL is op=0x24; REL See BCC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIH REL is op=0x2F; REL
BIH BACKWARDS1
BIH FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIL REL is op=0x2E; REL
BIL BACKWARDS1
BIL FORWARDS1
FORWARDS1:
BACKWARDS2:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1
BIT #0xFE
BIT *0xFE
BIT 0xFEDC
BIT 0xFEDC,X
BIT 0xFE,X
BIT ,X
; @if defined(HCS08) || defined(HC08)
; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP
; BIT 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP
; BIT 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : BLE REL is op=0x93; REL
; BLE BACKWARDS2
; BLE FORWARDS2
; :BLO REL is op=0x25; REL see BCS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BLS REL is op=0x23; REL
BLS BACKWARDS2
BLS FORWARDS2
; @if defined(HCS08) || defined(HC08)
; : BLT REL is op=0x91; REL
; BLT BACKWARDS2
; BLT FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMC REL is op=0x2C; REL
BMC BACKWARDS2
BMC FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMI REL is op=0x2B; REL
BMI BACKWARDS2
BMI FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMS REL is op=0x2D; REL
BMS BACKWARDS2
BMS FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BNE REL is op=0x26; REL
BNE BACKWARDS2
BNE FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BPL REL is op=0x2A; REL
BPL BACKWARDS2
BPL FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRA REL is op=0x20; REL
BRA BACKWARDS2
BRA FORWARDS2
FORWARDS2:
BACKWARDS3:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL
BRCLR #0, *0xFE,BACKWARDS3
BRCLR #1, *0xED,BACKWARDS3
BRCLR #2, *0xDC,BACKWARDS3
BRCLR #3, *0xCB,BACKWARDS3
BRCLR #4, *0xBA,BACKWARDS3
BRCLR #5, *0xA9,BACKWARDS3
BRCLR #6, *0x98,BACKWARDS3
BRCLR #7, *0x87,BACKWARDS3
BRCLR #0, *0xFE,FORWARDS3
BRCLR #1, *0xED,FORWARDS3
BRCLR #2, *0xDC,FORWARDS3
BRCLR #3, *0xCB,FORWARDS3
BRCLR #4, *0xBA,FORWARDS3
BRCLR #5, *0xA9,FORWARDS3
BRCLR #6, *0x98,FORWARDS3
BRCLR #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; branch never is a two-byte nop
; : BRN REL is op=0x21; REL
BRN BACKWARDS3
BRN FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL
BRSET #0, *0xFE,BACKWARDS3
BRSET #1, *0xED,BACKWARDS3
BRSET #2, *0xDC,BACKWARDS3
BRSET #3, *0xCB,BACKWARDS3
BRSET #4, *0xBA,BACKWARDS3
BRSET #5, *0xA9,BACKWARDS3
BRSET #6, *0x98,BACKWARDS3
BRSET #7, *0x87,BACKWARDS3
BRSET #0, *0xFE,FORWARDS3
BRSET #1, *0xED,FORWARDS3
BRSET #2, *0xDC,FORWARDS3
BRSET #3, *0xCB,FORWARDS3
BRSET #4, *0xBA,FORWARDS3
BRSET #5, *0xA9,FORWARDS3
BRSET #6, *0x98,FORWARDS3
BRSET #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8
BSET #0, *0xFE
BSET #1, *0xED
BSET #2, *0xDC
BSET #3, *0xCB
BSET #4, *0xBA
BSET #5, *0xA9
BSET #6, *0x98
BSET #7, *0x87
FORWARDS3:
BACKWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSR REL is op=0xAD; REL
BSR BACKWARDS4
BSR FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL
; CBEQ *0xFE, BACKWARDS4
; CBEQ *0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL
; CBEQA #0xFE, BACKWARDS4
; CBEQA #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL
; CBEQX #0xFE, BACKWARDS4
; CBEQX #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8, X"+", REL is (op=0x61) & X; oprx8; REL
; CBEQ *0xFE, X+, BACKWARDS4
; CBEQ *0xFE, X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ ","X"+", REL is (op=0x71) & X; REL
; CBEQ ,X+, BACKWARDS4
; CBEQ ,X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL
; CBEQ 0xFE,S, BACKWARDS4
; CBEQ 0xFE,S, FORWARDS4
FORWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLC is op=0x98
CLC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLI is op=0x9A
CLI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRA is op=0x4F
CLRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRX is op=0x5F
CLRX
; @if defined(HCS08) || defined(HC08)
; : CLRH is op=0x8C
; CLRH
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1
CLR *0xFE
CLR 0xFE,X
CLR ,X
; @if defined(HCS08) || defined(HC08)
; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP
; CLR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1
CMP #0xFE
CMP *0xFE
CMP 0xFEDC
CMP 0xFEDC,X
CMP 0xFE,X
CMP ,X
; @if defined(HCS08) || defined(HC08)
; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP
; CMP 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP
; CMP 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMA is op=0x43
COMA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMX is op=0x53
COMX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1
COM *0xFE
COM 0xFE,X
COM ,X
; @if defined(HCS08) || defined(HC08)
; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP
; COM 0xFE,S
; @if defined(HCS08)
; : CPHX opr16a_16 is (op=0x3E); opr16a_16
; CPHX 0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX iopr16i is (op=0x65); iopr16i
; CPHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX opr8a_16 is (op=0x75); opr8a_16
; CPHX *0xFE
; @if defined(HCS08)
; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP
; CPHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1
CPX #0xFE
CPX *0xFE
CPX 0xFEDC
CPX 0xFEDC,X
CPX 0xFE,X
CPX ,X
; @if defined(HCS08) || defined(HC08)
; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP
; CPX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP
; CPX 0xFE,S
BACKWARDS5:
; @if defined(HCS08) || defined(HC08)
; : DAA is op=0x72
; DAA
; @if defined(HCS08) || defined(HC08)
; : DBNZA REL is op=0x4B; REL
; DBNZA BACKWARDS5
; DBNZA FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZX REL is op=0x5B; REL
; DBNZX BACKWARDS5
; DBNZX FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL
; DBNZ *0xFE, BACKWARDS5
; DBNZ 0xFE,X, BACKWARDS5
; DBNZ ,X, BACKWARDS5
; DBNZ *0xFE, FORWARDS5
; DBNZ 0xFE,X, FORWARDS5
; DBNZ ,X, FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL
; DBNZ 0xFE,S, BACKWARDS5
; DBNZ 0xFE,S, FORWARDS5
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECA is op=0x4A
DECA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECX is op=0x5A
DECX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1
DEC *0xFE
DEC 0xFE,X
DEC ,X
; @if defined(HCS08) || defined(HC08)
; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP
; DEC 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : DIV is op=0x52
; DIV
FORWARDS5:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1
EOR #0xFE
EOR *0xFE
EOR 0xFEDC
EOR 0xFEDC,X
EOR 0xFE,X
EOR ,X
; @if defined(HCS08) || defined(HC08)
; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP
; EOR 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP
; EOR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCA is op=0x4C
INCA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCX is op=0x5C
INCX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1
INC *0xFE
INC 0xFE,X
INC ,X
; @if defined(HCS08) || defined(HC08)
; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP
; INC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR
JMP *LOW_SUB_TEST
JMP HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI
JMP 0xFEDC,X
JMP 0xFE,X
JMP ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR
JSR *LOW_SUB_TEST
JSR HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI
JSR 0xFEDC,X
JSR 0xFE,X
JSR ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1
LDA #0xFE
LDA *0xFE
LDA 0xFEDC
LDA 0xFEDC,X
LDA 0xFE,X
LDA ,X
; @if defined(HCS08) || defined(HC08)
; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP
; LDA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP
; LDA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : LDHX iopr16i is (op=0x45); iopr16i
; LDHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : LDHX opr8a_16 is (op=0x55); opr8a_16
; LDHX *0xFE
; @if defined(HCS08)
; : LDHX opr16a_16 is (op=0x32); opr16a_16
; LDHX 0xFEDC
; @if defined(HCS08)
; : LDHX ","X is (op16=0x9EAE) & X
; LDHX ,X
; @if defined(HCS08)
; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X
; LDHX 0xFEDC,X
; @if defined(HCS08)
; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X
; LDHX 0xFE,X
; @if defined(HCS08)
; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP
; LDHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1
LDX #0xFE
LDX *0xFE
LDX 0xFEDC
LDX 0xFEDC,X
LDX 0xFE,X
LDX ,X
; @if defined(HCS08) || defined(HC08)
; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP
; LDX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP
; LDX 0xFE,S
; ## Logical Shift left is same as arithmetic shift left
; :LSLA is op=0x48
; :LSLX is op=0x58
; :LSL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRA is op=0x44
LSRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRX is op=0x54
LSRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1
LSR *0xFE
LSR 0xFE,X
LSR ,X
; @if defined(HCS08) || defined(HC08)
; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP
; LSR 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, op2_opr8a is (op=0x4E); opr8a_8; op2_opr8a
; MOV *0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, X"+" is (op=0x5E); opr8a_8 & X
; MOV 0xFE, X+
; @if defined(HCS08) || defined(HC08)
; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a
; MOV #0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV ","X"+," op2_opr8a is (op=0x7E) & X; op2_opr8a
; MOV ,X+, *0xFE
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : MUL is op=0x42
MUL
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGA is op=0x40
NEGA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGX is op=0x50
NEGX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1
NEG *0xFE
NEG 0xFE,X
NEG ,X
; @if defined(HCS08) || defined(HC08)
; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP
; NEG 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NOP is op = 0x9D
NOP
; @if defined(HCS08) || defined(HC08)
; : NSA is op = 0x62
; NSA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1
ORA #0xFE
ORA *0xFE
ORA 0xFEDC
ORA 0xFEDC,X
ORA 0xFE,X
ORA ,X
; @if defined(HCS08) || defined(HC08)
; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP
; ORA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP
; ORA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : PSHA is op = 0x87
; PSHA
; @if defined(HCS08) || defined(HC08)
; : PSHH is op = 0x8B
; PSHH
; @if defined(HCS08) || defined(HC08)
; : PSHX is op = 0x89
; PSHX
; @if defined(HCS08) || defined(HC08)
; : PULA is op = 0x86
; PULA
; @if defined(HCS08) || defined(HC08)
; : PULH is op = 0x8A
; PULH
; @if defined(HCS08) || defined(HC08)
; : PULX is op = 0x88
; PULX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLA is op=0x49
ROLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLX is op=0x59
ROLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1
ROL *0xFE
ROL 0xFE,X
ROL ,X
; @if defined(HCS08) || defined(HC08)
; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP
; ROL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORA is op=0x46
RORA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORX is op=0x56
RORX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1
ROR *0xFE
ROR 0xFE,X
ROR ,X
; @if defined(HCS08) || defined(HC08)
; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP
; ROR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RSP is op = 0x9C
RSP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTI is op = 0x80
RTI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTS is op = 0x81
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1
SBC #0xFE
SBC *0xFE
SBC 0xFEDC
SBC 0xFEDC,X
SBC 0xFE,X
SBC ,X
; @if defined(HCS08) || defined(HC08)
; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP
; SBC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP
; SBC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEC is op = 0x99
SEC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEI is op = 0x9B
SEI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1
STA *0xFE
STA 0xFEDC
STA 0xFEDC,X
STA 0xFE,X
STA ,X
; @if defined(HCS08) || defined(HC08)
; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP
; STA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP
; STA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : STHX opr8a_16 is (op=0x35); opr8a_16
; STHX *0xFE
; @if defined(HCS08)
; : STHX opr16a_16 is (op=0x96); opr16a_16
; STHX 0xFEDC
; @if defined(HCS08)
; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP
; STHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STOP is op=0x8E
STOP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1
STX *0xFE
STX 0xFEDC
STX 0xFEDC,X
STX 0xFE,X
STX ,X
; @if defined(HCS08) || defined(HC08)
; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP
; STX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP
; STX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1
SUB #0xFE
SUB *0xFE
SUB 0xFEDC
SUB 0xFEDC,X
SUB 0xFE,X
SUB ,X
; @if defined(HCS08) || defined(HC08)
; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP
; SUB 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP
; SUB 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SWI is op=0x83
SWI
; @if defined(HCS08) || defined(HC08)
; : TAP is op=0x84
; TAP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TAX is op=0x97
TAX
; @if defined(HCS08) || defined(HC08)
; : TPA is op=0x85
; TPA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTA is op=0x4D
TSTA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTX is op=0x5D
TSTX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1
TST *0xFE
TST 0xFE,X
TST ,X
; @if defined(HCS08) || defined(HC08)
; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP
; TST 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : TSX is op=0x95
; TSX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TXA is op=0x9F
TXA
; @if defined(HCS08) || defined(HC08)
; : TXS is op=0x94
; TXS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : WAIT is op=0x8f
WAIT
HERE:
BRA HERE
|
gk69-cz/Static-malware-analyser
| 23,737
|
executable/Ghidra/Processors/HCS08/data/test-vectors/HC08_tv.s
|
.hc08
.area DIRECT (PAG)
;.setdp 0, DIRECT
;low_data1:
;.ds 1
.area PROGRAM (ABS)
.org 0x80
LOW_SUB_TEST:
RTS
.org 0x2000
HIGH_SUB_TEST:
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1
ADC #0xFE
ADC *0xFE
ADC 0xFEDC
ADC 0xFEDC,X
ADC 0xFE,X
ADC ,X
; @if defined(HCS08) || defined(HC08)
; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP
ADC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP
ADC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1
ADD #0xFE
ADD *0xFE
ADD 0xFEDC
ADD 0xFEDC,X
ADD 0xFE,X
ADD ,X
; @if defined(HCS08) || defined(HC08)
; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP
ADD 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP
ADD 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : AIS iopr8is is op=0xA7; iopr8is
AIS #0x7F
AIS #-0x7F
; @if defined(HCS08) || defined(HC08)
; : AIX iopr8is is op=0xAF; iopr8is
AIX #0x7F
AIX #-0x7F
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1
AND #0xFE
AND *0xFE
AND 0xFEDC
AND 0xFEDC,X
AND 0xFE,X
AND ,X
; @if defined(HCS08) || defined(HC08)
; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP
AND 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP
AND 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLA is op=0x48
ASLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLX is op=0x58
ASLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
ASL *0xFE
ASL 0xFE,X
ASL ,X
; @if defined(HCS08) || defined(HC08)
; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP
ASL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRA is op=0x47
ASRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRX is op=0x57
ASRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1
ASR *0xFE
ASR 0xFE,X
ASR ,X
; @if defined(HCS08) || defined(HC08)
; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP
ASR 0xFE,S
BACKWARDS1:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCC REL is op=0x24; REL
BCC BACKWARDS1
BCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8
BCLR #0, *0xFE
BCLR #1, *0xED
BCLR #2, *0xDC
BCLR #3, *0xCB
BCLR #4, *0xBA
BCLR #5, *0xA9
BCLR #6, *0x98
BCLR #7, *0x87
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCS REL is op=0x25; REL
BCS BACKWARDS1
BCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BEQ REL is op=0x27; REL
BEQ BACKWARDS1
BEQ FORWARDS1
; @if defined(HCS08) || defined(HC08)
; : BGE REL is op=0x90; REL
BGE BACKWARDS1
BGE FORWARDS1
; @if defined(HCS08)
; : BGND is op=0x82
; BGND
; @if defined(HCS08) || defined(HC08)
; : BGT REL is op=0x92; REL
BGT BACKWARDS1
BGT FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCC REL is op=0x28; REL
BHCC BACKWARDS1
BHCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCS REL is op=0x29; REL
BHCS BACKWARDS1
BHCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHI REL is op=0x22; REL
BHI BACKWARDS1
BHI FORWARDS1
; :BHS REL is op=0x24; REL See BCC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIH REL is op=0x2F; REL
BIH BACKWARDS1
BIH FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIL REL is op=0x2E; REL
BIL BACKWARDS1
BIL FORWARDS1
FORWARDS1:
BACKWARDS2:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1
BIT #0xFE
BIT *0xFE
BIT 0xFEDC
BIT 0xFEDC,X
BIT 0xFE,X
BIT ,X
; @if defined(HCS08) || defined(HC08)
; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP
BIT 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP
BIT 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : BLE REL is op=0x93; REL
BLE BACKWARDS2
BLE FORWARDS2
; :BLO REL is op=0x25; REL see BCS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BLS REL is op=0x23; REL
BLS BACKWARDS2
BLS FORWARDS2
; @if defined(HCS08) || defined(HC08)
; : BLT REL is op=0x91; REL
BLT BACKWARDS2
BLT FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMC REL is op=0x2C; REL
BMC BACKWARDS2
BMC FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMI REL is op=0x2B; REL
BMI BACKWARDS2
BMI FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMS REL is op=0x2D; REL
BMS BACKWARDS2
BMS FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BNE REL is op=0x26; REL
BNE BACKWARDS2
BNE FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BPL REL is op=0x2A; REL
BPL BACKWARDS2
BPL FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRA REL is op=0x20; REL
BRA BACKWARDS2
BRA FORWARDS2
FORWARDS2:
BACKWARDS3:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL
BRCLR #0, *0xFE,BACKWARDS3
BRCLR #1, *0xED,BACKWARDS3
BRCLR #2, *0xDC,BACKWARDS3
BRCLR #3, *0xCB,BACKWARDS3
BRCLR #4, *0xBA,BACKWARDS3
BRCLR #5, *0xA9,BACKWARDS3
BRCLR #6, *0x98,BACKWARDS3
BRCLR #7, *0x87,BACKWARDS3
BRCLR #0, *0xFE,FORWARDS3
BRCLR #1, *0xED,FORWARDS3
BRCLR #2, *0xDC,FORWARDS3
BRCLR #3, *0xCB,FORWARDS3
BRCLR #4, *0xBA,FORWARDS3
BRCLR #5, *0xA9,FORWARDS3
BRCLR #6, *0x98,FORWARDS3
BRCLR #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; branch never is a two-byte nop
; : BRN REL is op=0x21; REL
BRN BACKWARDS3
BRN FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL
BRSET #0, *0xFE,BACKWARDS3
BRSET #1, *0xED,BACKWARDS3
BRSET #2, *0xDC,BACKWARDS3
BRSET #3, *0xCB,BACKWARDS3
BRSET #4, *0xBA,BACKWARDS3
BRSET #5, *0xA9,BACKWARDS3
BRSET #6, *0x98,BACKWARDS3
BRSET #7, *0x87,BACKWARDS3
BRSET #0, *0xFE,FORWARDS3
BRSET #1, *0xED,FORWARDS3
BRSET #2, *0xDC,FORWARDS3
BRSET #3, *0xCB,FORWARDS3
BRSET #4, *0xBA,FORWARDS3
BRSET #5, *0xA9,FORWARDS3
BRSET #6, *0x98,FORWARDS3
BRSET #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8
BSET #0, *0xFE
BSET #1, *0xED
BSET #2, *0xDC
BSET #3, *0xCB
BSET #4, *0xBA
BSET #5, *0xA9
BSET #6, *0x98
BSET #7, *0x87
FORWARDS3:
BACKWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSR REL is op=0xAD; REL
BSR BACKWARDS4
BSR FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL
CBEQ *0xFE, BACKWARDS4
CBEQ *0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL
CBEQA #0xFE, BACKWARDS4
CBEQA #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL
CBEQX #0xFE, BACKWARDS4
CBEQX #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8, X"+", REL is (op=0x61) & X; oprx8; REL
CBEQ *0xFE, X+, BACKWARDS4
CBEQ *0xFE, X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ ","X"+", REL is (op=0x71) & X; REL
CBEQ ,X+, BACKWARDS4
CBEQ ,X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL
CBEQ 0xFE,S, BACKWARDS4
CBEQ 0xFE,S, FORWARDS4
FORWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLC is op=0x98
CLC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLI is op=0x9A
CLI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRA is op=0x4F
CLRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRX is op=0x5F
CLRX
; @if defined(HCS08) || defined(HC08)
; : CLRH is op=0x8C
CLRH
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1
CLR *0xFE
CLR 0xFE,X
CLR ,X
; @if defined(HCS08) || defined(HC08)
; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP
CLR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1
CMP #0xFE
CMP *0xFE
CMP 0xFEDC
CMP 0xFEDC,X
CMP 0xFE,X
CMP ,X
; @if defined(HCS08) || defined(HC08)
; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP
CMP 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP
CMP 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMA is op=0x43
COMA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMX is op=0x53
COMX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1
COM *0xFE
COM 0xFE,X
COM ,X
; @if defined(HCS08) || defined(HC08)
; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP
COM 0xFE,S
; @if defined(HCS08)
; : CPHX opr16a_16 is (op=0x3E); opr16a_16
; CPHX 0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX iopr16i is (op=0x65); iopr16i
CPHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX opr8a_16 is (op=0x75); opr8a_16
CPHX *0xFE
; @if defined(HCS08)
; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP
; CPHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1
CPX #0xFE
CPX *0xFE
CPX 0xFEDC
CPX 0xFEDC,X
CPX 0xFE,X
CPX ,X
; @if defined(HCS08) || defined(HC08)
; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP
CPX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP
CPX 0xFE,S
BACKWARDS5:
; @if defined(HCS08) || defined(HC08)
; : DAA is op=0x72
DAA
; @if defined(HCS08) || defined(HC08)
; : DBNZA REL is op=0x4B; REL
DBNZA BACKWARDS5
DBNZA FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZX REL is op=0x5B; REL
DBNZX BACKWARDS5
DBNZX FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL
DBNZ *0xFE, BACKWARDS5
DBNZ 0xFE,X, BACKWARDS5
DBNZ ,X, BACKWARDS5
DBNZ *0xFE, FORWARDS5
DBNZ 0xFE,X, FORWARDS5
DBNZ ,X, FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL
DBNZ 0xFE,S, BACKWARDS5
DBNZ 0xFE,S, FORWARDS5
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECA is op=0x4A
DECA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECX is op=0x5A
DECX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1
DEC *0xFE
DEC 0xFE,X
DEC ,X
; @if defined(HCS08) || defined(HC08)
; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP
DEC 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : DIV is op=0x52
DIV
FORWARDS5:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1
EOR #0xFE
EOR *0xFE
EOR 0xFEDC
EOR 0xFEDC,X
EOR 0xFE,X
EOR ,X
; @if defined(HCS08) || defined(HC08)
; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP
EOR 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP
EOR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCA is op=0x4C
INCA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCX is op=0x5C
INCX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1
INC *0xFE
INC 0xFE,X
INC ,X
; @if defined(HCS08) || defined(HC08)
; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP
INC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR
JMP *LOW_SUB_TEST
JMP HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI
JMP 0xFEDC,X
JMP 0xFE,X
JMP ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR
JSR *LOW_SUB_TEST
JSR HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI
JSR 0xFEDC,X
JSR 0xFE,X
JSR ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1
LDA #0xFE
LDA *0xFE
LDA 0xFEDC
LDA 0xFEDC,X
LDA 0xFE,X
LDA ,X
; @if defined(HCS08) || defined(HC08)
; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP
LDA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP
LDA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : LDHX iopr16i is (op=0x45); iopr16i
LDHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : LDHX opr8a_16 is (op=0x55); opr8a_16
LDHX *0xFE
; @if defined(HCS08)
; : LDHX opr16a_16 is (op=0x32); opr16a_16
; LDHX 0xFEDC
; @if defined(HCS08)
; : LDHX ","X is (op16=0x9EAE) & X
; LDHX ,X
; @if defined(HCS08)
; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X
; LDHX 0xFEDC,X
; @if defined(HCS08)
; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X
; LDHX 0xFE,X
; @if defined(HCS08)
; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP
; LDHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1
LDX #0xFE
LDX *0xFE
LDX 0xFEDC
LDX 0xFEDC,X
LDX 0xFE,X
LDX ,X
; @if defined(HCS08) || defined(HC08)
; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP
LDX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP
LDX 0xFE,S
; ## Logical Shift left is same as arithmetic shift left
; :LSLA is op=0x48
; :LSLX is op=0x58
; :LSL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRA is op=0x44
LSRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRX is op=0x54
LSRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1
LSR *0xFE
LSR 0xFE,X
LSR ,X
; @if defined(HCS08) || defined(HC08)
; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP
LSR 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, op2_opr8a is (op=0x4E); opr8a_8; op2_opr8a
MOV *0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, X"+" is (op=0x5E); opr8a_8 & X
MOV 0xFE, X+
; @if defined(HCS08) || defined(HC08)
; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a
MOV #0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV ","X"+," op2_opr8a is (op=0x7E) & X; op2_opr8a
MOV ,X+, *0xFE
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : MUL is op=0x42
MUL
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGA is op=0x40
NEGA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGX is op=0x50
NEGX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1
NEG *0xFE
NEG 0xFE,X
NEG ,X
; @if defined(HCS08) || defined(HC08)
; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP
NEG 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NOP is op = 0x9D
NOP
; @if defined(HCS08) || defined(HC08)
; : NSA is op = 0x62
NSA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1
ORA #0xFE
ORA *0xFE
ORA 0xFEDC
ORA 0xFEDC,X
ORA 0xFE,X
ORA ,X
; @if defined(HCS08) || defined(HC08)
; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP
ORA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP
ORA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : PSHA is op = 0x87
PSHA
; @if defined(HCS08) || defined(HC08)
; : PSHH is op = 0x8B
PSHH
; @if defined(HCS08) || defined(HC08)
; : PSHX is op = 0x89
PSHX
; @if defined(HCS08) || defined(HC08)
; : PULA is op = 0x86
PULA
; @if defined(HCS08) || defined(HC08)
; : PULH is op = 0x8A
PULH
; @if defined(HCS08) || defined(HC08)
; : PULX is op = 0x88
PULX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLA is op=0x49
ROLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLX is op=0x59
ROLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1
ROL *0xFE
ROL 0xFE,X
ROL ,X
; @if defined(HCS08) || defined(HC08)
; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP
ROL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORA is op=0x46
RORA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORX is op=0x56
RORX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1
ROR *0xFE
ROR 0xFE,X
ROR ,X
; @if defined(HCS08) || defined(HC08)
; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP
ROR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RSP is op = 0x9C
RSP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTI is op = 0x80
RTI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTS is op = 0x81
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1
SBC #0xFE
SBC *0xFE
SBC 0xFEDC
SBC 0xFEDC,X
SBC 0xFE,X
SBC ,X
; @if defined(HCS08) || defined(HC08)
; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP
SBC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP
SBC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEC is op = 0x99
SEC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEI is op = 0x9B
SEI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1
STA *0xFE
STA 0xFEDC
STA 0xFEDC,X
STA 0xFE,X
STA ,X
; @if defined(HCS08) || defined(HC08)
; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP
STA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP
STA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : STHX opr8a_16 is (op=0x35); opr8a_16
STHX *0xFE
; @if defined(HCS08)
; : STHX opr16a_16 is (op=0x96); opr16a_16
; STHX 0xFEDC
; @if defined(HCS08)
; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP
; STHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STOP is op=0x8E
STOP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1
STX *0xFE
STX 0xFEDC
STX 0xFEDC,X
STX 0xFE,X
STX ,X
; @if defined(HCS08) || defined(HC08)
; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP
STX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP
STX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1
SUB #0xFE
SUB *0xFE
SUB 0xFEDC
SUB 0xFEDC,X
SUB 0xFE,X
SUB ,X
; @if defined(HCS08) || defined(HC08)
; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP
SUB 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP
SUB 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SWI is op=0x83
SWI
; @if defined(HCS08) || defined(HC08)
; : TAP is op=0x84
TAP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TAX is op=0x97
TAX
; @if defined(HCS08) || defined(HC08)
; : TPA is op=0x85
TPA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTA is op=0x4D
TSTA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTX is op=0x5D
TSTX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1
TST *0xFE
TST 0xFE,X
TST ,X
; @if defined(HCS08) || defined(HC08)
; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP
TST 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : TSX is op=0x95
TSX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TXA is op=0x9F
TXA
; @if defined(HCS08) || defined(HC08)
; : TXS is op=0x94
TXS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : WAIT is op=0x8f
WAIT
HERE:
BRA HERE
|
goetzr/embedded_learning
| 1,532
|
stm32/boards/stm32-f3discovery/projects/blink-led/asm/src/led.S
|
@ Registers
.set .LRCC_AHBENR, 0x40021014
.set .LGPIOE_MODER, 0x48001000
.set .LGPIOE_BSRR, 0x48001018
@ Bit fields
.set .LIOPEEN, 21
.set .LMODER8, 16
.set .LBS8, 8
.set .LBR8, 24
.section .text.led, "ax", %progbits
.align 1
.syntax unified
/*
Performs the initialization required to use the LED.
*/
.global init_led
.type init_led, %function
.thumb_func
init_led:
@ Enable AHB clock for Port E pins.
@ RCC_AHBENR |= 1 << IOPEEN
ldr r0, =.LRCC_AHBENR
ldr r1, [r0]
movs r2, 1
lsl r2, .LIOPEEN
orrs r1, r2
str r1, [r0]
@ Configure Port E Pin 8 as a push-pull output.
@ GPIOE_MODER &= ~(0b11 << MODER8)
@ GPIOE_MODER |= 1 << MODER8
ldr r0, =.LGPIOE_MODER
ldr r1, [r0]
movs r2, 3
lsl r2, .LMODER8
mvn r3, r2
ands r1, r3
movs r2, 1
lsl r2, .LMODER8
orrs r1, r2
str r1, [r0]
bx lr
.size init_led, . - init_led
/*
Set the state of the LED.
@param state (r0) The desired state of the LED.
0: LED off
1: LED on
*/
.global set_led
.type set_led, %function
.thumb_func
set_led:
ldr r1, =.LGPIOE_BSRR
ldr r2, [r1]
movs r3, 1
cmp r0, 1
bne 0f
@ Turn the LED on.
lsl r3, .LBS8
orrs r2, r3
str r2, [r1]
b 1f
0:
@ Turn the LED off.
lsl r3, .LBR8
orrs r2, r3
str r2, [r1]
1:
bx lr
.size set_led, . - set_led
|
goetzr/embedded_learning
| 2,474
|
stm32/boards/stm32-f3discovery/projects/blink-led/asm/src/delay.S
|
@ RCC
.set .LRCC_BASE, 0x40021000
.set .LRCC_CFGR, .LRCC_BASE + 0x04
.set .LPPRE1, 8
.set .LRCC_APB1ENR, .LRCC_BASE + 0x1C
.set .LTIM6EN, 4
@ TIM6
.set .LTIM6_BASE, 0x40001000
.set .LTIM6_CR1, .LTIM6_BASE + 0x00
.set .LUIFREMAP, 11
.set .LCEN, 0
.set .LTIM6_SR, .LTIM6_BASE + 0x10
.set .LUIF, 0
.set .LTIM6_CNT, .LTIM6_BASE + 0x24
.set .LUIFCPY, 31
.set .LTIM6_ARR, .LTIM6_BASE + 0x2C
.section .text.delay, "ax", %progbits
.align 1
.syntax unified
/*
Performs the initialization required to use the delay_ms function.
*/
.global init_delay
.type init_delay, %function
.thumb_func
init_delay:
@ NOTE: APB1CLK is always enabled.
@ Divide APB1CLK by 16 (RCC_CFGR.PPRE1 = 111).
@ SYSCLK is driven by HSI, which runs at 8 MHz.
@ The desired TIM6CLK is 1 MHz, but if APB1CLK is divided at all, it's multiplied by 2 prior to setting TIM6CLK.
@ Therefore, divide APB1CLK by 16 to get a TIM6CLK of 1 MHz.
ldr r10, =.LRCC_CFGR
ldr r0, [r10]
orrs r0, 0b111 << .LPPRE1
str r0, [r10]
@ Enable TIM6CLK.
ldr r10, =.LRCC_APB1ENR
ldr r0, [r10]
orrs r0, 1 << .LTIM6EN
str r0, [r10]
@ Set the auto-reload register to 1,000.
@ TIM6CLK runs at 1 MHz, which has a period of 1 microsecond. 1 millisecond has passed when the counter reaches 1,000.
ldr r10, =.LTIM6_ARR
movw r0, 1000
str r0, [r10]
@ The UIF status bit is copied to TIM6_CNT(31).
ldr r10, =.LTIM6_CR1
ldr r0, [r10]
orrs r0, 1 << .LUIFREMAP
str r0, [r10]
bx lr
.size init_delay, . - init_delay
/*
Delays execution for the specified number of milliseconds.
@param num_ms (r0) The number of milliseconds to delay execution.
*/
.global delay_ms
.type delay_ms, %function
.thumb_func
delay_ms:
ldr r10, =.LTIM6_CNT
ldr r11, =.LTIM6_CR1
ldr r12, =.LTIM6_SR
@ Reset the counter to 0.
movs r1, 0
str r1, [r10]
@ Enable the counter.
ldr r1, [r11]
orrs r1, 1 << .LCEN
str r1, [r11]
@ Wait for the update interrupt flag to be set.
0: ldr r1, [r10]
tst r1, 1 << .LUIFCPY
beq 0b
@ Clear the update interrupt flag.
ldr r2, [r12]
bic r2, 1 << .LUIF
str r2, [r12]
subs r0, 1
bne 0b
@ Disable the counter.
ldr r1, [r11]
bic r1, 1 << .LCEN
str r1, [r11]
bx lr
.size delay_ms, . - delay_ms
|
graves/dinoxor
| 7,228
|
reference/dinoxor.s
|
.global _dinoxor
.text
// Function: dinoxor
// Description: Orchestrates a series of operations to replicate a bitwise XOR
// operation using NEON registers. This function initializes a XOR truth table,
// calculates an index based on provided Xindex and Yindex, and creates a
// multiplication table to help calculate the index of each byte into the truth table.
// Arguments:
// - x0: First operand byte
// - x1: Second operand byte
// Returns: The result of the XOR operation between the two input bytes in w0.
_dinoxor:
// Prologue: Prepare the stack and save callee-saved registers
stp x29, x30, [sp, #-16]! // Save the frame pointer and return address on the stack
mov x29, sp // Update the frame pointer to the current stack pointer
mov x2, #0 // Initialize x2 to 0 (not used later)
eor v0.16b, v0.16b, v0.16b // Clear the contents of v0 (set all bits to 0)
bl spread_bits_to_bytes // Call the spread_bits_to_bytes function to load the first operand byte into the lower half of v2
mov x0, x1 // Move the second operand byte into x0
bl spread_bits_to_bytes // Call the spread_bits_to_bytes function to load the second operand byte into the lower half of v2 (shifting the previous value to upper)
// After the above operations
// For the inputs:
// x0 = 0b10101010
// x1 = 0b11111111
// v2 contains:
// v2 = {0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01}
bl prepare_xor_truth_table // Call the prepare_xor_truth_table function to initialize the XOR truth table in v0
// After the above operation, v0 contains:
// v0 = {0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x00}
bl prepare_multiplication_table // Call the prepare_multiplication_table function to initialize the multiplication table in v1
// After the above operation, v1 contains:
// v1 = {0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01}
bl calculate_xor_result // Call the calculate_xor_result function to calculate and store the XOR'd byte in w0.
// Epilogue: Restore the stack and callee-saved registers
ldp x29, x30, [sp], #16 // Restore the frame pointer and return address from the stack
ret // Return to the caller
// Function: spread_bits_to_bytes
// Description: Spreads the bits of a byte into separate bytes in a NEON register.
// Arguments:
// - x0: The input byte to be spread
// Returns: None (the result is stored in v2)
spread_bits_to_bytes:
// Clear the destination vector registers
eor v1.16b, v1.16b, v1.16b
eor v2.16b, v2.16b, v2.16b
mov w2, #0 // Initialize the counter for bit positions (0-7)
spread_bit_loop:
lsr w3, w0, w2 // Shift the input byte right by the current bit position to bring the target bit to the LSB
and w3, w3, #0x01 // Isolate the LSB (which is now the target bit)
mov w4, w3 // Move the processed bit to w4 (to ensure w4 is correctly updated before duplication)
ext v2.16b, v0.16b, v0.16b, #1 // Shift v0 left by one byte to make space for the new byte
ins v2.b[0], w4 // Insert the new byte at position 0 of v2
mov v0.16b, v2.16b // Move the temporary result back to v0
add w2, w2, #1 // Increment the bit position counter
cmp w2, #8 // Compare the counter with 8 (number of bits in a byte)
b.lt spread_bit_loop // If the counter is less than 8, continue the loop
ext v2.16b, v0.16b, v0.16b, #1 // Shift the last byte inserted into its final position in v2
ret
// Function: prepare_xor_truth_table
// Description: Prepares the XOR truth table in a NEON register.
// Arguments: None
// Returns: None (the truth table is stored in v0)
prepare_xor_truth_table:
// Load a pattern into a general-purpose register
movz w8, #0x0001, lsl #16 // Load 0x0001 into the upper half of w8 (bits 16-31)
movk w8, #0x0100 // Overlay 0x0100 into the lower half of w8 (bits 0-15)
dup v0.4s, w8 // Duplicate the 32-bit value in w8 across all lanes of v0
// After the above operation, v0 contains:
// v0 = {0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x00}
ret
// Function: prepare_multiplication_table
// Description: Sets up a multiplication table in v1 to help calculate the index of each byte into the truth table.
// Arguments: None
// Returns: None (the multiplication table is stored in v1)
prepare_multiplication_table:
// Load the patterns into NEON registers
movi v1.8b, #0x02 // Set the lower half of v1 to 0x02
movi v8.8b, #0x01 // Set the lower half of v8 to 0x01
mov v1.d[1], v8.d[0] // Move the lower half of v8 to the upper half of v1
// After the above operations, v1 contains:
// v1 = {0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01}
ret
// Function: calculate_xor_result
// Description: Calculates the XOR result using the prepared data in NEON registers.
// It multiplies the spread bits by the multiplication table to get the indices,
// performs a table lookup using the XOR truth table, and then multiplies the result
// by a predefined pattern to obtain the final XOR result.
// Arguments:
// - v0: The XOR truth table
// - v1: The multiplication table
// - v2: The spread bits of the input operands
// Returns: The XOR result of the input operands in w0
calculate_xor_result:
mul v3.16b, v2.16b, v1.16b // Multiply each byte in v2 (spread bits) by its corresponding byte in v1 (multiplication table)
// The upper half of v3 now contains the relevant Xindexes
mov v3.d[1], v2.d[1] // Move the upper half of v2 (Yindexes) to the lower half of v3
ext.16b v1, v3, v3, #8 // Extract the upper half of v3 and store it in v1
add.16b v1, v3, v1 // Add v3 and v1 to get the final indices for the truth table lookup
mov.d v1[1], xzr // Clear the upper half of v1 (set it to 0)
tbl.8b v1, {v0}, v1 // Perform a table lookup using the indices in v1 and the truth table in v0
// Store the result in v1
// Set up v0 with the desired values for the multiplication
movz x1, #0x0201, lsl #0 // Load the lower 16 bits of x1 with 0x0201
movk x1, #0x0804, lsl #16 // Load the next 16 bits of x1 with 0x0804
movk x1, #0x2010, lsl #32 // Load the next 16 bits of x1 with 0x2010
movk x1, #0x8040, lsl #48 // Load the upper 16 bits of x1 with 0x8040
mov v0.d[0], x1 // Move the 64-bit value from x1 to the lower half of v0
mul v1.16b, v1.16b, v0.16b // Multiply v1 (table lookup result) by v0 (predefined pattern) element-wise
addv b0, v1.8b // Sum the values in the lower half of v1 and store the result in b0
umov w0, v0.b[0] // Move the 8-bit scalar value from b0 to w0 (return value)
ret
|
GraySinclair/switch-cfw
| 1,253
|
Switch Backup 9:22/fusee-launcher/intermezzo.S
|
//
// Payload launcher stub.
//
.globl _start
.section ".text"
_start:
// First, we'll need to move ourselves _out_ of the target area.
// We'll copy down into the IRAM.
ldr r0, =INTERMEZZO_RELOCATED_ADDRESS
ldr r1, =post_relocation
ldr r2, =intermezzo_end
sub r2, r2, r1
bl copy
// Jump to the start of RAM, which should now contain the post-relocation code.
ldr r0, =INTERMEZZO_RELOCATED_ADDRESS
bx r0
.align 4
post_relocation:
// Next, we'll copy our payload down to the appropriate relocaiton address.
ldr r0, =RELOCATION_TARGET
ldr r1, =PAYLOAD_START_ADDR
ldr r2, =BEFORE_SPRAY_LENGTH
bl copy
ldr r0, =RELOCATION_TARGET
ldr r1, =BEFORE_SPRAY_LENGTH
add r0, r0, r1
ldr r1, =STACK_SPRAY_END
ldr r2, =AFTER_SPRAY_LENGTH
bl copy
// Finally, jump into the relocated target.
ldr r0, =ENTRY_POINT_ADDRESS
bx r0
//
// Simple block copy.
// r0 = destination address
// r1 = source address
// r2 = length in bytes
// Destroys r0-r3.
//
copy:
// Copy the word...
ldr r3, [r1], #4
str r3, [r0], #4
// And continue while we have words left to copy.
subs r2, r2, #4
bne copy
// Once we're done, return.
bx lr
|
gulybyte/algorithms
| 1,782
|
calc/nasm/main.s
|
%include 'utils.inc'
%include 'calc.inc'
section .data
msgOption db LF,'What is the option number to proceed? ', NULL
msgError db 'Invalid Option Value',LF, NULL
msgEnd db LF,'Program finished', LF, NULL
numVal1 db LF,'Value 1: ', NULL
numVal2 db LF,'Value 2: ', NULL
options db LF,'1. Addition',LF,'2. Subtraction',LF,'3. Multiplication',LF,'4. Division',LF,NULL
max_val_num equ 0x5 ; 4 digit
section .bss
optionCalc resb 1
; máx 5 digit
num1 resb 5
num2 resb 5
section .text
global _start
_start:
call get_values
call show_options
call get_input_option_as_int
jmp make_equation
show_options:
mov ecx, options
call output_value
ret
get_input_option_as_int:
call show_message_option
call get_input_option
call convert_option_in_int
call valid_size_option
ret
get_input_option:
mov eax, SYS_READ
mov ebx, STD_IN
mov ecx, optionCalc
mov edx, 0x1
int SYS_CALL
ret
show_message_option:
mov ecx, msgOption
call output_value
ret
convert_option_in_int:
mov ah, [optionCalc]
sub ah, '0'
ret
valid_size_option:
cmp ah, 4
jg validation_error
cmp ah, 1
jl validation_error
ret
validation_error:
mov ecx, msgError
call output_value
jmp end
get_values:
get_val1:
mov ecx, numVal1
call output_value
mov eax, SYS_READ
mov ebx, STD_IN
mov ecx, num1
mov edx, max_val_num
int SYS_CALL
call string_to_int
mov ebp, eax
get_val2:
mov ecx, numVal2
call output_value
mov eax, SYS_READ
mov ebx, STD_IN
mov ecx, num2
mov edx, max_val_num
int SYS_CALL
call string_to_int
mov edi, eax
ret
end:
mov ecx, msgEnd
call output_value
mov eax, SYS_EXIT
xor ebx, ebx
int SYS_CALL
|
guoraymon/rr-os
| 1,801
|
os/src/trap.S
|
.section .text
.global __trap
__trap:
csrrw sp, sscratch, sp # now sp is kernel stack
addi sp, sp, -34*8
csrr t0, sstatus
csrr t1, sepc
csrr t2, sscratch
sd t0, 32*8(sp) # sstatus
sd t1, 33*8(sp) # sepc
sd t2, 2*8(sp) # sp
sd x1, 1*8(sp)
sd x3, 3*8(sp)
sd x4, 4*8(sp)
sd x5, 5*8(sp)
sd x6, 6*8(sp)
sd x7, 7*8(sp)
sd x8, 8*8(sp)
sd x9, 9*8(sp)
sd x10, 10*8(sp)
sd x11, 11*8(sp)
sd x12, 12*8(sp)
sd x13, 13*8(sp)
sd x14, 14*8(sp)
sd x15, 15*8(sp)
sd x16, 16*8(sp)
sd x17, 17*8(sp)
sd x18, 18*8(sp)
sd x19, 19*8(sp)
sd x20, 20*8(sp)
sd x21, 21*8(sp)
sd x22, 22*8(sp)
sd x23, 23*8(sp)
sd x24, 24*8(sp)
sd x25, 25*8(sp)
sd x26, 26*8(sp)
sd x27, 27*8(sp)
sd x28, 28*8(sp)
sd x29, 29*8(sp)
sd x30, 30*8(sp)
sd x31, 31*8(sp)
mv a0, sp # a0 is TrapContext
call trap_handler
.global __restore
__restore:
ld x1, 1*8(sp)
ld x3, 3*8(sp)
ld x4, 4*8(sp)
ld x5, 5*8(sp)
ld x6, 6*8(sp)
ld x7, 7*8(sp)
ld x8, 8*8(sp)
ld x9, 9*8(sp)
ld x10, 10*8(sp)
ld x11, 11*8(sp)
ld x12, 12*8(sp)
ld x13, 13*8(sp)
ld x14, 14*8(sp)
ld x15, 15*8(sp)
ld x16, 16*8(sp)
ld x17, 17*8(sp)
ld x18, 18*8(sp)
ld x19, 19*8(sp)
ld x20, 20*8(sp)
ld x21, 21*8(sp)
ld x22, 22*8(sp)
ld x23, 23*8(sp)
ld x24, 24*8(sp)
ld x25, 25*8(sp)
ld x26, 26*8(sp)
ld x27, 27*8(sp)
ld x28, 28*8(sp)
ld x29, 29*8(sp)
ld x30, 30*8(sp)
ld x31, 31*8(sp)
ld t0, 32*8(sp) # sstatus
ld t1, 33*8(sp) # sepc
ld t2, 2*8(sp) # sp
csrw sstatus, t0
csrw sepc, t1
csrw sscratch, t2
addi sp, sp, 34*8
csrrw sp, sscratch, sp # now sp is user stack
sret
|
gustafla/compilers-project
| 8,454
|
src/asm/stdlib.s
|
# Copyright 2025 Martin Pärtel
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the “Software”), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
.global _start
.global print_int
.global print_bool
.global read_int
.extern main
.section .text
# BEGIN START (we skip this part when linking with C)
# ***** Function '_start' *****
# Calls function 'main' and halts the program
_start:
call main
movq $60, %rax
xorq %rdi, %rdi
syscall
# END START
# ***** Function 'print_int' *****
# Prints a 64-bit signed integer followed by a newline.
#
# We'll build up the digits to print on the stack.
# We generate the least significant digit first,
# and the stack grows downward, so that works out nicely.
#
# Algorithm:
# push(newline)
# if x < 0:
# negative = true
# x = -x
# while x > 0:
# push(digit for (x % 10))
# x = x / 10
# if negative:
# push(minus sign)
# syscall 'write' with pushed data
# return the original argument
#
# Registers:
# - rdi = our input number, which we divide down as we go
# - rsp = stack pointer, pointing to the next character to emit.
# - rbp = pointer to one after the last byte of our output (which grows downward)
# - r9 = whether the number was negative
# - r10 = a copy of the original input, so we can return it
# - rax, rcx and rdx are used by intermediate computations
print_int:
pushq %rbp # Save previous stack frame pointer
movq %rsp, %rbp # Set stack frame pointer
movq %rdi, %r10 # Back up original input
decq %rsp # Point rsp at first byte of output
# TODO: this non-alignment confuses debuggers. Use a different register?
# Add newline as the last output byte
movb $10, (%rsp) # ASCII newline = 10
decq %rsp
# Check for zero and negative cases
xorq %r9, %r9
xorq %rax, %rax
cmpq $0, %rdi
je .Ljust_zero
jge .Ldigit_loop
incq %r9 # If < 0, set %r9 to 1
.Ldigit_loop:
cmpq $0, %rdi
je .Ldigits_done # Loop done when input = 0
# Divide rdi by 10
movq %rdi, %rax
movq $10, %rcx
cqto
idivq %rcx # Sets rax = quotient and rdx = remainder
movq %rax, %rdi # The quotient becomes our remaining input
cmpq $0, %rdx # If the remainder is negative (because the input is), negate it
jge .Lnot_negative
negq %rdx
.Lnot_negative:
addq $48, %rdx # ASCII '0' = 48. Add the remainder to get the correct digit.
movb %dl, (%rsp) # Store the digit in the output
decq %rsp
jmp .Ldigit_loop
.Ljust_zero:
movb $48, (%rsp) # ASCII '0' = 48
decq %rsp
.Ldigits_done:
# Add minus sign if negative
cmpq $0, %r9
je .Lminus_done
movb $45, (%rsp) # ASCII '-' = 45
decq %rsp
.Lminus_done:
# Call syscall 'write'
movq $1, %rax # rax = syscall number for write
movq $1, %rdi # rdi = file handle for stdout
# rsi = pointer to message
movq %rsp, %rsi
incq %rsi
# rdx = number of bytes
movq %rbp, %rdx
subq %rsp, %rdx
decq %rdx
syscall
# Restore stack registers and return the original input
movq %rbp, %rsp
popq %rbp
movq %r10, %rax
ret
# ***** Function 'print_bool' *****
# Prints either 'true' or 'false', followed by a newline.
print_bool:
pushq %rbp # Save previous stack frame pointer
movq %rsp, %rbp # Set stack frame pointer
movq %rdi, %r10 # Back up original input
cmpq $0, %rdi # See if the argument is false (i.e. 0)
jne .Ltrue
movq $false_str, %rsi # If so, set %rsi to the address of the string for false
movq $false_str_len, %rdx # and %rdx to the length of that string,
jmp .Lwrite
.Ltrue:
movq $true_str, %rsi # otherwise do the same with the string for true.
movq $true_str_len, %rdx
.Lwrite:
# Call syscall 'write'
movq $1, %rax # rax = syscall number for write
movq $1, %rdi # rdi = file handle for stdout
# rsi = pointer to message (already set above)
# rdx = number of bytes (already set above)
syscall
# Restore stack registers and return the original input
movq %rbp, %rsp
popq %rbp
movq %r10, %rax
ret
true_str:
.ascii "true\n"
true_str_len = . - true_str
false_str:
.ascii "false\n"
false_str_len = . - false_str
# ***** Function 'read_int' *****
# Reads an integer from stdin, skipping non-digit characters, until a newline.
#
# To avoid the complexity of buffering, it very inefficiently
# makes a syscall to read each byte.
#
# It crashes the program if input could not be read.
read_int:
pushq %rbp # Save previous stack frame pointer
movq %rsp, %rbp # Set stack frame pointer
pushq %r12 # Back up r12 since it's callee-saved
pushq $0 # Reserve space for input
# (we only write the lowest byte,
# but loading 64-bits at once is easier)
xorq %r9, %r9 # Clear r9 - it'll store the minus sign
xorq %r10, %r10 # Clear r10 - it'll accumulate our output
# Skip r11 - syscalls destroy it
xorq %r12, %r12 # Clear r12 - it'll count the number of input bytes read.
# Loop until a newline or end of input is encountered
.Lloop:
# Call syscall 'read'
xorq %rax, %rax # syscall number for read = 0
xorq %rdi, %rdi # file handle for stdin = 0
movq %rsp, %rsi # rsi = pointer to buffer
movq $1, %rdx # rdx = buffer size
syscall # result in rax = number of bytes read,
# or 0 on end of input, -1 on error
# Check return value: either -1, 0 or 1.
cmpq $0, %rax
jg .Lno_error
je .Lend_of_input
jmp .Lerror
.Lend_of_input:
cmpq $0, %r12
je .Lerror # If we've read no input, it's an error.
jmp .Lend # Otherwise complete reading this input.
.Lno_error:
incq %r12 # Increment input byte counter
movq (%rsp), %r8 # Load input byte to r8
# If the input byte is 10 (newline), exit the loop
cmpq $10, %r8
je .Lend
# If the input byte is 45 (minus sign), negate r9
cmpq $45, %r8
jne .Lnegation_done
xorq $1, %r9
.Lnegation_done:
# If the input byte is not between 48 ('0') and 57 ('9')
# then skip it as a junk character.
cmpq $48, %r8
jl .Lloop
cmpq $57, %r8
jg .Lloop
# Subtract 48 to get a digit 0..9
subq $48, %r8
# Shift the digit onto the result
imulq $10, %r10
addq %r8, %r10
jmp .Lloop
.Lend:
# If it's a negative number, negate the result
cmpq $0, %r9
je .Lfinal_negation_done
neg %r10
.Lfinal_negation_done:
# Restore stack registers and return the result
popq %r12
movq %rbp, %rsp
popq %rbp
movq %r10, %rax
ret
.Lerror:
# Write error message to stderr with syscall 'write'
movq $1, %rax
movq $2, %rdi
movq $read_int_error_str, %rsi
movq $read_int_error_str_len, %rdx
syscall
# Exit the program
movq $60, %rax # Syscall number for exit = 60.
movq $1, %rdi # Set exit code 1.
syscall
read_int_error_str:
.ascii "Error: read_int() failed to read input\n"
read_int_error_str_len = . - read_int_error_str
|
hainakus/Xenomorph
| 5,802
|
crypto/muhash/src/keccakf1600_x86-64-osx.s
|
# Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.p2align 5
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp L$oop
.p2align 5
L$oop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz L$oop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.cfi_endproc
.globl _KeccakF1600
.p2align 5
_KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $200,%rsp
.cfi_adjust_cfa_offset 200
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
addq $200,%rsp
.cfi_adjust_cfa_offset -200
popq %r15
.cfi_adjust_cfa_offset -8
.cfi_restore %r15
popq %r14
.cfi_adjust_cfa_offset -8
.cfi_restore %r14
popq %r13
.cfi_adjust_cfa_offset -8
.cfi_restore %r13
popq %r12
.cfi_adjust_cfa_offset -8
.cfi_restore %r12
popq %rbp
.cfi_adjust_cfa_offset -8
.cfi_restore %rbp
popq %rbx
.cfi_adjust_cfa_offset -8
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.p2align 8
.quad 0,0,0,0,0,0,0,0
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
hainakus/Xenomorph
| 6,073
|
crypto/muhash/src/keccakf1600_x86-64.s
|
# Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.type __KeccakF1600,@function
.align 32
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.align 32
.Loop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz .Loop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.cfi_endproc
.size __KeccakF1600,.-__KeccakF1600
.globl KeccakF1600
.type KeccakF1600,@function
.align 32
KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $200,%rsp
.cfi_adjust_cfa_offset 200
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
addq $200,%rsp
.cfi_adjust_cfa_offset -200
popq %r15
.cfi_adjust_cfa_offset -8
.cfi_restore %r15
popq %r14
.cfi_adjust_cfa_offset -8
.cfi_restore %r14
popq %r13
.cfi_adjust_cfa_offset -8
.cfi_restore %r13
popq %r12
.cfi_adjust_cfa_offset -8
.cfi_restore %r12
popq %rbp
.cfi_adjust_cfa_offset -8
.cfi_restore %rbp
popq %rbx
.cfi_adjust_cfa_offset -8
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.size KeccakF1600,.-KeccakF1600
.align 256
.quad 0,0,0,0,0,0,0,0
.type iotas,@object
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.size iotas,.-iotas
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.section .note.gnu.property,"a",@note
.long 4,2f-1f,5
.byte 0x47,0x4E,0x55,0
1: .long 0xc0000002,4,3
.align 8
2:
|
hainakus/Xenomorph
| 5,802
|
crypto/hashes/src/keccakf1600_x86-64-osx.s
|
# Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.p2align 5
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp L$oop
.p2align 5
L$oop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz L$oop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.cfi_endproc
.globl _KeccakF1600
.p2align 5
_KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $200,%rsp
.cfi_adjust_cfa_offset 200
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
addq $200,%rsp
.cfi_adjust_cfa_offset -200
popq %r15
.cfi_adjust_cfa_offset -8
.cfi_restore %r15
popq %r14
.cfi_adjust_cfa_offset -8
.cfi_restore %r14
popq %r13
.cfi_adjust_cfa_offset -8
.cfi_restore %r13
popq %r12
.cfi_adjust_cfa_offset -8
.cfi_restore %r12
popq %rbp
.cfi_adjust_cfa_offset -8
.cfi_restore %rbp
popq %rbx
.cfi_adjust_cfa_offset -8
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.p2align 8
.quad 0,0,0,0,0,0,0,0
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
hainakus/Xenomorph
| 6,073
|
crypto/hashes/src/keccakf1600_x86-64.s
|
# Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.type __KeccakF1600,@function
.align 32
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.align 32
.Loop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz .Loop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.cfi_endproc
.size __KeccakF1600,.-__KeccakF1600
.globl KeccakF1600
.type KeccakF1600,@function
.align 32
KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $200,%rsp
.cfi_adjust_cfa_offset 200
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
addq $200,%rsp
.cfi_adjust_cfa_offset -200
popq %r15
.cfi_adjust_cfa_offset -8
.cfi_restore %r15
popq %r14
.cfi_adjust_cfa_offset -8
.cfi_restore %r14
popq %r13
.cfi_adjust_cfa_offset -8
.cfi_restore %r13
popq %r12
.cfi_adjust_cfa_offset -8
.cfi_restore %r12
popq %rbp
.cfi_adjust_cfa_offset -8
.cfi_restore %rbp
popq %rbx
.cfi_adjust_cfa_offset -8
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.size KeccakF1600,.-KeccakF1600
.align 256
.quad 0,0,0,0,0,0,0,0
.type iotas,@object
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.size iotas,.-iotas
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.section .note.gnu.property,"a",@note
.long 4,2f-1f,5
.byte 0x47,0x4E,0x55,0
1: .long 0xc0000002,4,3
.align 8
2:
|
Hammad-Izhar/reenix
| 2,154
|
src/boot/boot.S
|
.global _start
.set KERNEL_OFFSET, 0xC0000000
.set KERNEL_STACK_SIZE, 0x1000 // 4 KiB
.set KERNEL_STACK_START_PA, __kernel_stack_start - KERNEL_OFFSET
.set PML4_PA, pml4 - KERNEL_OFFSET
.set PDPT_PA, pdpt - KERNEL_OFFSET
.set PDT_PA, pdt - KERNEL_OFFSET
.section .bss
.align 0x1000
pml4:
.skip 0x1000
pdpt:
.skip 0x1000
pdt:
.skip 0x1000
__kernel_stack_end:
.skip KERNEL_STACK_SIZE
__kernel_stack_start:
.section .rodata
gdt64:
.quad 0
.quad (1<<43) | (1<<44) | (1<<47) | (1<<53)
gdt64_pointer:
.word gdt64_pointer - gdt64 - 1
.quad gdt64
.section .text
.code32
_start:
cli
mov esp, offset KERNEL_STACK_START_PA
mov ebp, offset KERNEL_STACK_START_PA
call setup_page_tables
call enable_paging
lgdt [gdt64_pointer]
ljmp 0x8, offset _start64
setup_page_tables:
mov eax, offset PDPT_PA
or eax, 0b11
mov [PML4_PA], eax
mov eax, offset PDT_PA
or eax, 0b11
mov [PDPT_PA], eax
mov [PDPT_PA + 3 * 8], eax
mov ecx, 0
.map_pdt:
mov eax, 0x200000
mul ecx
or eax, 0b10000011
mov [PDT_PA + ecx * 8], eax
inc ecx
cmp ecx, 512
jne .map_pdt
ret
enable_paging:
mov eax, offset PML4_PA
mov cr3, eax
mov eax, cr4
or eax, 1 << 5
mov cr4, eax
mov ecx, 0xC0000080
rdmsr
or eax, 1 << 8
wrmsr
mov eax, cr0
or eax, 1 << 31
mov cr0, eax
ret
error:
mov dword ptr [0xb8000], 0x4f524f45
mov dword ptr [0xb8004], 0x4f3a4f52
mov dword ptr [0xb8008], 0x4f204f20
mov byte ptr [0xb800a], al
hlt
.code64
_start64:
mov rax, KERNEL_OFFSET
add rsp, rax
add rbp, rax
mov ax, 0
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
.extern kmain
call kmain
call error
|
haohano/rust-sgx
| 1,266
|
intel-sgx/report-test/enclave/main.S
|
/* Copyright (c) Fortanix, Inc.
*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
.equ targetinfo, .+0x3000
.equ reportdata, targetinfo+512
.equ report, reportdata+512
/* extern "C" fn entry(report_out: *mut Report) */
mov %rcx, %r8 /* save user RIP */
/* call ENCLU[EREPORT] */
lea targetinfo(%rip), %rbx /* RBX = EREPORT TARGETINFO */
lea reportdata(%rip), %rcx /* RCX = EREPORT REPORTDATA */
lea report(%rip), %rdx /* RDX = EREPORT OUTPUT */
xor %eax, %eax /* ENCLU leaf 0 = EREPORT */
enclu
/* memcpy report to output buffer */
mov $432, %ecx /* ECX = REP MOVSB number of bytes */
mov %rdx, %rsi /* RSI = REP MOVSB source address */
/* keep %rdi */ /* RDI = REP MOVSB destination address */
rep movsb
/* call ENCLU[EEXIT] */
mov %r8, %rbx /* EEXIT Target = restored user RIP */
xor %rdi, %rdi /* RDI = 0 is normal (non-usercall) exit */
/* keep rsi */ /* RSI = return value, don't care */
/* keep rdx */ /* RDX = return value, don't care */
mov $4, %rax /* ENCLU leaf 4 = EEXIT */
enclu
|
haohano/rust-sgx
| 1,730
|
rs-libc/src/asm/x86_64/copysignl.S
|
.file "copysignl.c"
.text
..TXTST0:
# -- Begin copysignl
.text
.align 16,0x90
.globl copysignl
copysignl:
# parameter 1: 64 + %rsp
# parameter 2: 80 + %rsp
..B1.1:
.cfi_startproc
..___tag_value_copysignl.1:
..L2:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorb %sil, %sil
fldt 64(%rsp)
fstpt (%rsp)
..B1.2:
fnstcw 50(%rsp)
..B1.3:
movzwl 50(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.7
..B1.4:
orl $-64768, %edx
movw %dx, 48(%rsp)
..B1.5:
fldcw 48(%rsp)
..B1.6:
movb $1, %sil
..B1.7:
fldt 80(%rsp)
lea _ones(%rip), %rax
fldt (%rsp)
movb 89(%rsp), %dl
andb $-128, %dl
fldl (%rax)
fmul %st, %st(1)
fxch %st(1)
fstpt 32(%rsp)
fmulp %st, %st(1)
movb 41(%rsp), %cl
andb $127, %cl
orb %dl, %cl
fstpt 16(%rsp)
testb %sil, %sil
movb %cl, 41(%rsp)
je ..B1.9
..B1.8:
fldcw 50(%rsp)
..B1.9:
fldt 32(%rsp)
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.align 16,0x90
.cfi_endproc
.type copysignl,@function
.size copysignl,.-copysignl
.data
# -- End copysignl
.section .rodata, "a"
.align 4
.align 4
_ones:
.long 0
.long 1072693248
.long 0
.long 3220176896
.type _ones,@object
.size _ones,16
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
haohano/rust-sgx
| 1,799
|
rs-libc/src/asm/x86_64/frexp_gen.S
|
.file "frexp_gen.c"
.text
..TXTST0:
# -- Begin frexp
.text
.align 16,0x90
.globl frexp
frexp:
# parameter 1: %xmm0
# parameter 2: %rdi
..B1.1:
.cfi_startproc
..___tag_value_frexp.1:
..L2:
movsd %xmm0, -8(%rsp)
movl -4(%rsp), %eax
movl %eax, %edx
andl $2147483647, %edx
lea -1048576(%rdx), %ecx
cmpl $2145386496, %ecx
jb ..B1.6
..B1.2:
testl %ecx, %ecx
jge ..B1.5
..B1.3:
movl -8(%rsp), %eax
orl %eax, %edx
je ..B1.5
..B1.4:
lea _TWO_55(%rip), %rax
movsd -8(%rsp), %xmm0
mulsd (%rax), %xmm0
movsd %xmm0, -8(%rsp)
movl -4(%rsp), %edx
movl %edx, %ecx
andl $2147483647, %ecx
andl $-2146435073, %edx
shrl $20, %ecx
orl $1071644672, %edx
movl %edx, -4(%rsp)
addl $-1077, %ecx
movl %ecx, (%rdi)
movsd -8(%rsp), %xmm0
ret
..B1.5:
movl $0, (%rdi)
movsd -8(%rsp), %xmm0
ret
..B1.6:
andl $-2146435073, %eax
shrl $20, %ecx
orl $1071644672, %eax
movl %eax, -4(%rsp)
addl $-1021, %ecx
movl %ecx, (%rdi)
movsd -8(%rsp), %xmm0
ret
.align 16,0x90
.cfi_endproc
.type frexp,@function
.size frexp,.-frexp
.data
# -- End frexp
.section .rodata, "a"
.align 4
.align 4
_TWO_55:
.long 0
.long 1130364928
.type _TWO_55,@object
.size _TWO_55,8
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
haohano/rust-sgx
| 6,097
|
rs-libc/src/asm/x86_64/scalbnl.S
|
.file "scalbnl.c"
.text
..TXTST0:
# -- Begin scalbnl
.text
.align 16,0x90
.globl scalbnl
scalbnl:
# parameter 1: 32 + %rsp
# parameter 2: %edi
..B1.1:
.cfi_startproc
..___tag_value_scalbnl.1:
..L2:
subq $24, %rsp
.cfi_def_cfa_offset 32
..B1.2:
fnstcw 18(%rsp)
..B1.3:
movzwl 40(%rsp), %r8d
movl %r8d, %esi
andl $32767, %esi
cmpl $32767, %esi
je ..B1.39
..B1.4:
testl %esi, %esi
jne ..B1.12
..B1.5:
cmpq $0, 32(%rsp)
je ..B1.15
..B1.6:
movzwl 18(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.38
..B1.7:
orl $-64768, %edx
movw %dx, 16(%rsp)
..B1.8:
fldcw 16(%rsp)
..B1.9:
fldt 32(%rsp)
lea _TWO_75(%rip), %rax
fmull (%rax)
fstpt 32(%rsp)
..B1.10:
fldcw 18(%rsp)
..B1.11:
movzwl 40(%rsp), %r8d
movl %r8d, %esi
andl $32767, %esi
addl $-75, %esi
..B1.12:
movl $65536, %edx
cmpl $65536, %edi
cmovg %edx, %edi
movl $-65536, %ecx
xorb %al, %al
cmpl $-65536, %edi
cmovle %ecx, %edi
lea (%rsi,%rdi), %edx
testl %edx, %edx
jle ..B1.23
..B1.13:
cmpl $32767, %edx
jge ..B1.16
..B1.14:
andl $-32768, %r8d
andl $32767, %edx
orl %edx, %r8d
movw %r8w, 40(%rsp)
fldt 32(%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.15:
fldt 32(%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.16:
movzwl 18(%rsp), %ecx
movl %ecx, %edx
andl $768, %edx
cmpl $768, %edx
je ..B1.20
..B1.17:
orl $-64768, %ecx
movw %cx, 16(%rsp)
..B1.18:
fldcw 16(%rsp)
..B1.19:
movb $1, %al
..B1.20:
movb 41(%rsp), %dl
lea _large_value_80(%rip), %rsi
andb $-128, %dl
shrb $7, %dl
fldt (%rsi)
movzbl %dl, %ecx
shlq $4, %rcx
testb %al, %al
fldt (%rsi,%rcx)
fmulp %st, %st(1)
fstpt (%rsp)
je ..B1.22
..B1.21:
fldcw 18(%rsp)
..B1.22:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.23:
cmpl $-63, %edx
jl ..B1.31
..B1.24:
andl $-32768, %r8d
lea 75(%rsi,%rdi), %eax
andl $32767, %eax
orl %eax, %r8d
movzwl 18(%rsp), %eax
movl %eax, %edx
andl $768, %edx
movw %r8w, 40(%rsp)
cmpl $768, %edx
je ..B1.30
..B1.25:
orl $-64768, %eax
movw %ax, 16(%rsp)
..B1.26:
fldcw 16(%rsp)
..B1.27:
fldt 32(%rsp)
lea 8+_TWO_75(%rip), %rax
fmull (%rax)
fstpt (%rsp)
..B1.28:
fldcw 18(%rsp)
..B1.29:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.30:
fldt 32(%rsp)
lea 8+_TWO_75(%rip), %rax
fmull (%rax)
fstpt (%rsp)
jmp ..B1.29
..B1.31:
movzwl 18(%rsp), %ecx
movl %ecx, %edx
andl $768, %edx
cmpl $768, %edx
je ..B1.35
..B1.32:
orl $-64768, %ecx
movw %cx, 16(%rsp)
..B1.33:
fldcw 16(%rsp)
..B1.34:
movb $1, %al
..B1.35:
movb 41(%rsp), %dl
lea _small_value_80(%rip), %rsi
andb $-128, %dl
shrb $7, %dl
fldt (%rsi)
movzbl %dl, %ecx
shlq $4, %rcx
testb %al, %al
fldt (%rsi,%rcx)
fmulp %st, %st(1)
fstpt (%rsp)
je ..B1.37
..B1.36:
fldcw 18(%rsp)
..B1.37:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.38:
fldt 32(%rsp)
lea _TWO_75(%rip), %rax
fmull (%rax)
fstpt 32(%rsp)
jmp ..B1.11
..B1.39:
movzwl 18(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.45
..B1.40:
orl $-64768, %edx
movw %dx, 16(%rsp)
..B1.41:
fldcw 16(%rsp)
..B1.42:
fldt 32(%rsp)
fstpt (%rsp)
..B1.43:
fldcw 18(%rsp)
..B1.44:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.45:
fldt 32(%rsp)
fstpt (%rsp)
jmp ..B1.44
.align 16,0x90
.cfi_endproc
.type scalbnl,@function
.size scalbnl,.-scalbnl
.data
# -- End scalbnl
.section .rodata, "a"
.align 4
.align 4
_TWO_75:
.long 0
.long 1151336448
.long 0
.long 994050048
.type _TWO_75,@object
.size _TWO_75,16
.align 2
_large_value_80:
.word 0
.word 0
.word 0
.word 32768
.word 26383
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 32768
.word 59151
.word 0
.word 0
.word 0
.type _large_value_80,@object
.size _large_value_80,32
.align 2
_small_value_80:
.word 0
.word 0
.word 0
.word 32768
.word 6383
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 32768
.word 39151
.word 0
.word 0
.word 0
.type _small_value_80,@object
.size _small_value_80,32
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
haohano/rust-sgx
| 1,406
|
rs-libc/src/asm/x86_64/jmp.S
|
/* Copyright (c) Fortanix, Inc.
*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
// To be used with a jmp_buf of at least 70 bytes.
//
// Interesting discussion on what should be saved in setjmp/longjmp:
// https://lists.freebsd.org/pipermail/freebsd-amd64/2008-June/011284.html
// TL;DR: Almost all implementation are broken. What we do is correct.
.global setjmp, _setjmp
.type setjmp,@function
.equ _setjmp, setjmp
setjmp:
movq 0(%rsp), %rax
movq %rax, 0x00(%rdi)
movq %rbx, 0x08(%rdi)
movq %rsp, 0x10(%rdi)
movq %rbp, 0x18(%rdi)
movq %r12, 0x20(%rdi)
movq %r13, 0x28(%rdi)
movq %r14, 0x30(%rdi)
movq %r15, 0x38(%rdi)
stmxcsr 0x40(%rdi)
fstcw 0x44(%rdi)
xorq %rax, %rax
ret
1:
.size setjmp, 1b-setjmp
.global longjmp, _longjmp
.type longjmp,@function
.equ _longjmp, longjmp
longjmp:
movq 0x00(%rdi), %rax
movq 0x08(%rdi), %rbx
movq 0x10(%rdi), %rsp
movq 0x18(%rdi), %rbp
movq 0x20(%rdi), %r12
movq 0x28(%rdi), %r13
movq 0x30(%rdi), %r14
movq 0x38(%rdi), %r15
ldmxcsr 0x40(%rdi)
fldcw 0x44(%rdi)
movq %rax, 0(%rsp)
test %rsi, %rsi
movl $1, %eax
cmovnz %rsi, %rax
ret
2:
.size longjmp, 2b-longjmp
|
haohano/rust-sgx
| 6,124
|
rs-libc/src/asm/x86_64/scalblnl.S
|
.file "scalblnl.c"
.text
..TXTST0:
# -- Begin scalblnl
.text
.align 16,0x90
.globl scalblnl
scalblnl:
# parameter 1: 32 + %rsp
# parameter 2: %rdi
..B1.1:
.cfi_startproc
..___tag_value_scalblnl.1:
..L2:
subq $24, %rsp
.cfi_def_cfa_offset 32
..B1.2:
fnstcw 18(%rsp)
..B1.3:
movzwl 40(%rsp), %eax
movl %eax, %r9d
andq $32767, %r9
cmpq $32767, %r9
je ..B1.39
..B1.4:
testq %r9, %r9
jne ..B1.12
..B1.5:
cmpq $0, 32(%rsp)
je ..B1.15
..B1.6:
movzwl 18(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.38
..B1.7:
orl $-64768, %edx
movw %dx, 16(%rsp)
..B1.8:
fldcw 16(%rsp)
..B1.9:
fldt 32(%rsp)
lea _TWO_75(%rip), %rax
fmull (%rax)
fstpt 32(%rsp)
..B1.10:
fldcw 18(%rsp)
..B1.11:
movzwl 40(%rsp), %eax
movl %eax, %ecx
andl $32767, %ecx
movl %ecx, %r9d
addq $-75, %r9
..B1.12:
movl $65536, %esi
cmpq $65536, %rdi
cmovg %rsi, %rdi
movq $-65536, %r8
xorb %dl, %dl
cmpq $-65536, %rdi
cmovl %r8, %rdi
lea (%r9,%rdi), %rcx
testq %rcx, %rcx
jle ..B1.23
..B1.13:
cmpq $32767, %rcx
jge ..B1.16
..B1.14:
andl $-32768, %eax
andl $32767, %ecx
orl %ecx, %eax
movw %ax, 40(%rsp)
fldt 32(%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.15:
fldt 32(%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.16:
movzwl 18(%rsp), %ecx
movl %ecx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.20
..B1.17:
orl $-64768, %ecx
movw %cx, 16(%rsp)
..B1.18:
fldcw 16(%rsp)
..B1.19:
movb $1, %dl
..B1.20:
movb 41(%rsp), %al
lea _large_value_80(%rip), %rsi
andb $-128, %al
shrb $7, %al
fldt (%rsi)
movzbl %al, %ecx
shlq $4, %rcx
testb %dl, %dl
fldt (%rsi,%rcx)
fmulp %st, %st(1)
fstpt (%rsp)
je ..B1.22
..B1.21:
fldcw 18(%rsp)
..B1.22:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.23:
cmpq $-63, %rcx
jl ..B1.31
..B1.24:
andl $-32768, %eax
lea 75(%r9,%rdi), %rdx
andl $32767, %edx
orl %edx, %eax
movzwl 18(%rsp), %edx
movw %ax, 40(%rsp)
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.30
..B1.25:
orl $-64768, %edx
movw %dx, 16(%rsp)
..B1.26:
fldcw 16(%rsp)
..B1.27:
fldt 32(%rsp)
lea 8+_TWO_75(%rip), %rax
fmull (%rax)
fstpt (%rsp)
..B1.28:
fldcw 18(%rsp)
..B1.29:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.30:
fldt 32(%rsp)
lea 8+_TWO_75(%rip), %rax
fmull (%rax)
fstpt (%rsp)
jmp ..B1.29
..B1.31:
movzwl 18(%rsp), %ecx
movl %ecx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.35
..B1.32:
orl $-64768, %ecx
movw %cx, 16(%rsp)
..B1.33:
fldcw 16(%rsp)
..B1.34:
movb $1, %dl
..B1.35:
movb 41(%rsp), %al
lea _small_value_80(%rip), %rsi
andb $-128, %al
shrb $7, %al
fldt (%rsi)
movzbl %al, %ecx
shlq $4, %rcx
testb %dl, %dl
fldt (%rsi,%rcx)
fmulp %st, %st(1)
fstpt (%rsp)
je ..B1.37
..B1.36:
fldcw 18(%rsp)
..B1.37:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.38:
fldt 32(%rsp)
lea _TWO_75(%rip), %rax
fmull (%rax)
fstpt 32(%rsp)
jmp ..B1.11
..B1.39:
movzwl 18(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.45
..B1.40:
orl $-64768, %edx
movw %dx, 16(%rsp)
..B1.41:
fldcw 16(%rsp)
..B1.42:
fldt 32(%rsp)
fstpt (%rsp)
..B1.43:
fldcw 18(%rsp)
..B1.44:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.45:
fldt 32(%rsp)
fstpt (%rsp)
jmp ..B1.44
.align 16,0x90
.cfi_endproc
.type scalblnl,@function
.size scalblnl,.-scalblnl
.data
# -- End scalblnl
.section .rodata, "a"
.align 4
.align 4
_TWO_75:
.long 0
.long 1151336448
.long 0
.long 994050048
.type _TWO_75,@object
.size _TWO_75,16
.align 2
_large_value_80:
.word 0
.word 0
.word 0
.word 32768
.word 26383
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 32768
.word 59151
.word 0
.word 0
.word 0
.type _large_value_80,@object
.size _large_value_80,32
.align 2
_small_value_80:
.word 0
.word 0
.word 0
.word 32768
.word 6383
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 32768
.word 39151
.word 0
.word 0
.word 0
.type _small_value_80,@object
.size _small_value_80,32
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
haohano/rust-sgx
| 3,017
|
rs-libc/src/asm/x86_64/frexpl.S
|
.file "frexpl.c"
.text
..TXTST0:
# -- Begin frexpl
.text
.align 16,0x90
.globl frexpl
frexpl:
# parameter 1: 32 + %rsp
# parameter 2: %rdi
..B1.1:
.cfi_startproc
..___tag_value_frexpl.1:
..L2:
subq $24, %rsp
.cfi_def_cfa_offset 32
..B1.2:
fnstcw 18(%rsp)
..B1.3:
movzwl 40(%rsp), %edx
movl %edx, %eax
andl $32767, %eax
cmpl $32767, %eax
je ..B1.15
..B1.4:
testl %eax, %eax
jne ..B1.13
..B1.5:
cmpq $0, 32(%rsp)
je ..B1.12
..B1.6:
movzwl 18(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.14
..B1.7:
orl $-64768, %edx
movl $0, (%rdi)
movw %dx, 16(%rsp)
..B1.8:
fldcw 16(%rsp)
..B1.9:
fldt 32(%rsp)
lea _TWO_75(%rip), %rax
fmull (%rax)
fstpt 32(%rsp)
..B1.10:
fldcw 18(%rsp)
..B1.11:
movzwl 40(%rsp), %edx
movl %edx, %eax
andl $-32768, %edx
andl $32767, %eax
orl $-49154, %edx
addl $-16457, %eax
movw %dx, 40(%rsp)
fldt 32(%rsp)
movl %eax, (%rdi)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.12:
fldt 32(%rsp)
movl $0, (%rdi)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.13:
andl $-32768, %edx
addl $-16382, %eax
orl $-49154, %edx
movw %dx, 40(%rsp)
fldt 32(%rsp)
movl %eax, (%rdi)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.14:
fldt 32(%rsp)
lea _TWO_75(%rip), %rax
fmull (%rax)
fstpt 32(%rsp)
jmp ..B1.11
..B1.15:
movzwl 18(%rsp), %edx
movl %edx, %eax
andl $768, %eax
movl $0, (%rdi)
cmpl $768, %eax
je ..B1.21
..B1.16:
orl $-64768, %edx
movw %dx, 16(%rsp)
..B1.17:
fldcw 16(%rsp)
..B1.18:
fldt 32(%rsp)
fstpt (%rsp)
..B1.19:
fldcw 18(%rsp)
..B1.20:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.21:
fldt 32(%rsp)
fstpt (%rsp)
jmp ..B1.20
.align 16,0x90
.cfi_endproc
.type frexpl,@function
.size frexpl,.-frexpl
.data
# -- End frexpl
.section .rodata, "a"
.align 4
.align 4
_TWO_75:
.long 0
.long 1151336448
.long 0
.long 994050048
.type _TWO_75,@object
.size _TWO_75,16
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
haohano/rust-sgx
| 6,088
|
rs-libc/src/asm/x86_64/ldexpl.S
|
.file "ldexpl.c"
.text
..TXTST0:
# -- Begin ldexpl
.text
.align 16,0x90
.globl ldexpl
ldexpl:
# parameter 1: 32 + %rsp
# parameter 2: %edi
..B1.1:
.cfi_startproc
..___tag_value_ldexpl.1:
..L2:
subq $24, %rsp
.cfi_def_cfa_offset 32
..B1.2:
fnstcw 18(%rsp)
..B1.3:
movzwl 40(%rsp), %r8d
movl %r8d, %esi
andl $32767, %esi
cmpl $32767, %esi
je ..B1.39
..B1.4:
testl %esi, %esi
jne ..B1.12
..B1.5:
cmpq $0, 32(%rsp)
je ..B1.15
..B1.6:
movzwl 18(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.38
..B1.7:
orl $-64768, %edx
movw %dx, 16(%rsp)
..B1.8:
fldcw 16(%rsp)
..B1.9:
fldt 32(%rsp)
lea _TWO_75(%rip), %rax
fmull (%rax)
fstpt 32(%rsp)
..B1.10:
fldcw 18(%rsp)
..B1.11:
movzwl 40(%rsp), %r8d
movl %r8d, %esi
andl $32767, %esi
addl $-75, %esi
..B1.12:
movl $65536, %edx
cmpl $65536, %edi
cmovg %edx, %edi
movl $-65536, %ecx
xorb %al, %al
cmpl $-65536, %edi
cmovle %ecx, %edi
lea (%rsi,%rdi), %edx
testl %edx, %edx
jle ..B1.23
..B1.13:
cmpl $32767, %edx
jge ..B1.16
..B1.14:
andl $-32768, %r8d
andl $32767, %edx
orl %edx, %r8d
movw %r8w, 40(%rsp)
fldt 32(%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.15:
fldt 32(%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.16:
movzwl 18(%rsp), %ecx
movl %ecx, %edx
andl $768, %edx
cmpl $768, %edx
je ..B1.20
..B1.17:
orl $-64768, %ecx
movw %cx, 16(%rsp)
..B1.18:
fldcw 16(%rsp)
..B1.19:
movb $1, %al
..B1.20:
movb 41(%rsp), %dl
lea _large_value_80(%rip), %rsi
andb $-128, %dl
shrb $7, %dl
fldt (%rsi)
movzbl %dl, %ecx
shlq $4, %rcx
testb %al, %al
fldt (%rsi,%rcx)
fmulp %st, %st(1)
fstpt (%rsp)
je ..B1.22
..B1.21:
fldcw 18(%rsp)
..B1.22:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.23:
cmpl $-63, %edx
jl ..B1.31
..B1.24:
andl $-32768, %r8d
lea 75(%rsi,%rdi), %eax
andl $32767, %eax
orl %eax, %r8d
movzwl 18(%rsp), %eax
movl %eax, %edx
andl $768, %edx
movw %r8w, 40(%rsp)
cmpl $768, %edx
je ..B1.30
..B1.25:
orl $-64768, %eax
movw %ax, 16(%rsp)
..B1.26:
fldcw 16(%rsp)
..B1.27:
fldt 32(%rsp)
lea 8+_TWO_75(%rip), %rax
fmull (%rax)
fstpt (%rsp)
..B1.28:
fldcw 18(%rsp)
..B1.29:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.30:
fldt 32(%rsp)
lea 8+_TWO_75(%rip), %rax
fmull (%rax)
fstpt (%rsp)
jmp ..B1.29
..B1.31:
movzwl 18(%rsp), %ecx
movl %ecx, %edx
andl $768, %edx
cmpl $768, %edx
je ..B1.35
..B1.32:
orl $-64768, %ecx
movw %cx, 16(%rsp)
..B1.33:
fldcw 16(%rsp)
..B1.34:
movb $1, %al
..B1.35:
movb 41(%rsp), %dl
lea _small_value_80(%rip), %rsi
andb $-128, %dl
shrb $7, %dl
fldt (%rsi)
movzbl %dl, %ecx
shlq $4, %rcx
testb %al, %al
fldt (%rsi,%rcx)
fmulp %st, %st(1)
fstpt (%rsp)
je ..B1.37
..B1.36:
fldcw 18(%rsp)
..B1.37:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.38:
fldt 32(%rsp)
lea _TWO_75(%rip), %rax
fmull (%rax)
fstpt 32(%rsp)
jmp ..B1.11
..B1.39:
movzwl 18(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.45
..B1.40:
orl $-64768, %edx
movw %dx, 16(%rsp)
..B1.41:
fldcw 16(%rsp)
..B1.42:
fldt 32(%rsp)
fstpt (%rsp)
..B1.43:
fldcw 18(%rsp)
..B1.44:
fldt (%rsp)
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 32
..B1.45:
fldt 32(%rsp)
fstpt (%rsp)
jmp ..B1.44
.align 16,0x90
.cfi_endproc
.type ldexpl,@function
.size ldexpl,.-ldexpl
.data
# -- End ldexpl
.section .rodata, "a"
.align 4
.align 4
_TWO_75:
.long 0
.long 1151336448
.long 0
.long 994050048
.type _TWO_75,@object
.size _TWO_75,16
.align 2
_large_value_80:
.word 0
.word 0
.word 0
.word 32768
.word 26383
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 32768
.word 59151
.word 0
.word 0
.word 0
.type _large_value_80,@object
.size _large_value_80,32
.align 2
_small_value_80:
.word 0
.word 0
.word 0
.word 32768
.word 6383
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 32768
.word 39151
.word 0
.word 0
.word 0
.type _small_value_80,@object
.size _small_value_80,32
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
haohano/rust-sgx
| 1,934
|
rs-libc/src/asm/x86_64/frexpf.S
|
.file "frexpf.c"
.text
..TXTST0:
# -- Begin frexpf
.text
.align 16,0x90
.globl frexpf
frexpf:
# parameter 1: %xmm0
# parameter 2: %rdi
..B1.1:
.cfi_startproc
..___tag_value_frexpf.1:
..L2:
movd %xmm0, %edx
movss %xmm0, -8(%rsp)
movl %edx, %eax
andl $2147483647, %eax
lea -8388608(%rax), %ecx
cmpl $2130706432, %ecx
jb ..B1.5
..B1.2:
decl %eax
cmpl $2139095039, %eax
jae ..B1.6
..B1.3:
movl %edx, -20(%rsp)
orl $1056964608, %edx
movl %edx, -24(%rsp)
andl $-2147483648, %edx
orl $1056964608, %edx
movl %edx, -16(%rsp)
movss -24(%rsp), %xmm2
movss -20(%rsp), %xmm1
movss -20(%rsp), %xmm0
subss -16(%rsp), %xmm2
addss %xmm0, %xmm1
movd %xmm2, %eax
movss %xmm1, -20(%rsp)
movl %eax, %edx
andl $-2139095041, %eax
andl $2139095040, %edx
orl $1056964608, %eax
shrl $23, %edx
movl %eax, -24(%rsp)
addl $-251, %edx
movl %edx, (%rdi)
movss -24(%rsp), %xmm0
..B1.4:
ret
..B1.5:
andl $-2139095041, %edx
shrl $23, %ecx
orl $1056964608, %edx
movl %edx, -24(%rsp)
addl $-125, %ecx
movl %ecx, (%rdi)
movss -24(%rsp), %xmm0
ret
..B1.6:
movss -8(%rsp), %xmm0
movl $0, (%rdi)
addss %xmm0, %xmm0
ret
.align 16,0x90
.cfi_endproc
.type frexpf,@function
.size frexpf,.-frexpf
.data
# -- End frexpf
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
haohano/rust-sgx
| 3,538
|
rs-libc/src/asm/x86_64/scalbn_gen.S
|
.file "scalbn_gen.c"
.text
..TXTST0:
# -- Begin scalbn
.text
.align 16,0x90
.globl scalbn
scalbn:
# parameter 1: %xmm0
# parameter 2: %edi
..B1.1:
.cfi_startproc
..___tag_value_scalbn.1:
..L2:
movsd %xmm0, -8(%rsp)
movzwl -2(%rsp), %esi
movl %esi, %ecx
andl $32752, %ecx
shrl $4, %ecx
cmpl $2047, %ecx
je ..B1.17
..B1.2:
xorb %r8b, %r8b
testl %ecx, %ecx
jne ..B1.7
..B1.3:
testl $1048575, -4(%rsp)
jne ..B1.6
..B1.4:
cmpl $0, -8(%rsp)
jne ..B1.6
..B1.5:
movsd -8(%rsp), %xmm0
ret
..B1.6:
lea _TWO_55(%rip), %rax
movb $1, %r8b
movsd -8(%rsp), %xmm0
mulsd (%rax), %xmm0
movsd %xmm0, -8(%rsp)
movzwl -2(%rsp), %esi
movl %esi, %ecx
andl $32752, %ecx
shrl $4, %ecx
addl $-55, %ecx
..B1.7:
movl $65536, %eax
cmpl $65536, %edi
cmovg %eax, %edi
movl $-65536, %edx
cmpl $-65536, %edi
cmovle %edx, %edi
lea (%rcx,%rdi), %eax
testl %eax, %eax
jle ..B1.12
..B1.8:
cmpl $2047, %eax
jge ..B1.11
..B1.9:
andl $2047, %eax
andl $-32753, %esi
shll $4, %eax
orl %eax, %esi
movw %si, -2(%rsp)
movsd -8(%rsp), %xmm0
..B1.10:
ret
..B1.11:
movb -1(%rsp), %al
lea _large_value_64(%rip), %rcx
andb $-128, %al
shrb $7, %al
movzbl %al, %edx
movsd (%rcx,%rdx,8), %xmm0
mulsd (%rcx), %xmm0
ret
..B1.12:
cmpl $-52, %eax
jl ..B1.16
..B1.13:
lea 8+_TWO_55(%rip), %rdx
lea 55(%rcx,%rdi), %eax
andl $2047, %eax
andl $-32753, %esi
shll $4, %eax
orl %eax, %esi
movw %si, -2(%rsp)
testb %r8b, %r8b
movsd -8(%rsp), %xmm0
mulsd (%rdx), %xmm0
je ..B1.15
..B1.14:
testl %edi, %edi
jl ..B1.10
..B1.15:
ret
..B1.16:
movb -1(%rsp), %al
lea _small_value_64(%rip), %rcx
andb $-128, %al
shrb $7, %al
movzbl %al, %edx
movsd (%rcx,%rdx,8), %xmm0
mulsd (%rcx), %xmm0
ret
..B1.17:
lea _ones(%rip), %rax
movsd -8(%rsp), %xmm0
mulsd (%rax), %xmm0
ret
.align 16,0x90
.cfi_endproc
.type scalbn,@function
.size scalbn,.-scalbn
.data
# -- End scalbn
.section .rodata, "a"
.align 4
.align 4
_TWO_55:
.long 0
.long 1130364928
.long 0
.long 1015021568
.type _TWO_55,@object
.size _TWO_55,16
.align 4
_large_value_64:
.long 0
.long 2121269248
.long 0
.long 4268752896
.type _large_value_64,@object
.size _large_value_64,16
.align 4
_small_value_64:
.long 0
.long 24117248
.long 0
.long 2171600896
.type _small_value_64,@object
.size _small_value_64,16
.align 4
_ones:
.long 0
.long 1072693248
.long 0
.long 3220176896
.type _ones,@object
.size _ones,16
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
haohano/rust-sgx
| 5,960
|
rs-libc/src/asm/x86_64/fmodl.S
|
.file "fmodl.c"
.text
..TXTST0:
# -- Begin fmodl
.text
.align 16,0x90
.globl fmodl
fmodl:
# parameter 1: 80 + %rsp
# parameter 2: 96 + %rsp
..B1.1:
.cfi_startproc
..___tag_value_fmodl.1:
..L2:
subq $72, %rsp
.cfi_def_cfa_offset 80
xorb %dl, %dl
fldt 80(%rsp)
fstpt 32(%rsp)
fldt 96(%rsp)
fstpt 48(%rsp)
..B1.2:
fnstcw 66(%rsp)
..B1.3:
movzwl 104(%rsp), %ecx
andl $32767, %ecx
jne ..B1.6
..B1.4:
cmpl $0, 100(%rsp)
jne ..B1.6
..B1.5:
cmpl $0, 96(%rsp)
je ..B1.42
..B1.6:
movzwl 88(%rsp), %esi
andl $32767, %esi
cmpl $32767, %esi
je ..B1.40
..B1.7:
cmpl $32767, %ecx
je ..B1.17
..B1.8:
movzwl 66(%rsp), %ecx
movl %ecx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.12
..B1.9:
orl $-64768, %ecx
movw %cx, 64(%rsp)
..B1.10:
fldcw 64(%rsp)
..B1.11:
movb $1, %dl
..B1.12:
fldt 48(%rsp)
fldt 32(%rsp)
movq $1024, %rcx
.L_2TAG_PACKET_0.0.2:
fprem
fstsw %ax
andq %rcx, %rax
cmpq $1024, %rax
je .L_2TAG_PACKET_0.0.2
fstp %st(1)
fstpt 16(%rsp)
..B1.13:
testb %dl, %dl
je ..B1.15
..B1.14:
fldcw 66(%rsp)
..B1.15:
fldt 16(%rsp)
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 80
..B1.17:
movq $0x8000000000000000, %rax
cmpq 96(%rsp), %rax
je ..B1.25
..B1.18:
movzwl 66(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.24
..B1.19:
orl $-64768, %edx
movw %dx, 64(%rsp)
..B1.20:
fldcw 64(%rsp)
..B1.21:
fldt 80(%rsp)
fldt 96(%rsp)
fmulp %st, %st(1)
fstpt 16(%rsp)
..B1.22:
fldcw 66(%rsp)
..B1.23:
fldt 16(%rsp)
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 80
..B1.24:
fldt 80(%rsp)
fldt 96(%rsp)
fmulp %st, %st(1)
fstpt 16(%rsp)
jmp ..B1.23
..B1.25:
cmpl $32767, %esi
je ..B1.31
..B1.26:
testl %esi, %esi
jne ..B1.30
..B1.27:
cmpl $0, 84(%rsp)
jne ..B1.29
..B1.28:
cmpl $0, 80(%rsp)
je ..B1.30
..B1.29:
lea _smallest_value_64(%rip), %rax
movq (%rax), %rdx
movq %rdx, 8(%rsp)
..B1.30:
fldt 80(%rsp)
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 80
..B1.31:
cmpl $-2147483648, 84(%rsp)
jne ..B1.30
..B1.32:
cmpl $0, 80(%rsp)
jne ..B1.30
..B1.33:
movzwl 66(%rsp), %ecx
movl %ecx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.37
..B1.34:
orl $-64768, %ecx
movw %cx, 64(%rsp)
..B1.35:
fldcw 64(%rsp)
..B1.36:
movb $1, %dl
..B1.37:
lea _infs(%rip), %rax
lea _zeros(%rip), %rcx
testb %dl, %dl
movsd (%rax), %xmm0
mulsd (%rcx), %xmm0
movsd %xmm0, (%rsp)
fldl (%rsp)
fstpt 16(%rsp)
je ..B1.39
..B1.38:
fldcw 66(%rsp)
..B1.39:
fldt 16(%rsp)
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 80
..B1.40:
movq $0x8000000000000000, %rax
cmpq 80(%rsp), %rax
jne ..B1.18
..B1.41:
cmpl $32767, %ecx
je ..B1.17
jmp ..B1.25
..B1.42:
movzwl 66(%rsp), %ecx
movl %ecx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.46
..B1.43:
orl $-64768, %ecx
movw %cx, 64(%rsp)
..B1.44:
fldcw 64(%rsp)
..B1.45:
movb $1, %dl
..B1.46:
movzwl 88(%rsp), %eax
andl $32767, %eax
cmpl $32767, %eax
jne ..B1.49
..B1.47:
movq $0x8000000000000000, %rax
cmpq 80(%rsp), %rax
je ..B1.49
..B1.48:
fldt 80(%rsp)
lea _ones(%rip), %rax
fmull (%rax)
fstpt 16(%rsp)
jmp ..B1.50
..B1.49:
lea _infs(%rip), %rax
lea _zeros(%rip), %rcx
movsd (%rax), %xmm0
mulsd (%rcx), %xmm0
movsd %xmm0, (%rsp)
fldl (%rsp)
fstpt 16(%rsp)
..B1.50:
testb %dl, %dl
je ..B1.52
..B1.51:
fldcw 66(%rsp)
..B1.52:
fldt 16(%rsp)
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.align 16,0x90
.cfi_endproc
.type fmodl,@function
.size fmodl,.-fmodl
.data
# -- End fmodl
.section .rodata, "a"
.align 4
.align 4
_smallest_value_64:
.long 1
.long 0
.long 1
.long 2147483648
.type _smallest_value_64,@object
.size _smallest_value_64,16
.align 4
_infs:
.long 0
.long 2146435072
.long 0
.long 4293918720
.type _infs,@object
.size _infs,16
.align 4
_zeros:
.long 0
.long 0
.long 0
.long 2147483648
.type _zeros,@object
.size _zeros,16
.align 4
_ones:
.long 0
.long 1072693248
.long 0
.long 3220176896
.type _ones,@object
.size _ones,16
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
HaoLi555/os
| 2,008
|
os/src/trap/trap.S
|
.altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text.trampoline
.globl __alltraps
.globl __restore
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->*TrapContext in user space, sscratch->user stack
# save other general purpose registers
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they have been saved in TrapContext
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it in TrapContext
csrr t2, sscratch
sd t2, 2*8(sp)
# load kernel_satp into t0
ld t0, 34*8(sp)
# load trap_handler into t1
ld t1, 36*8(sp)
# move to kernel_sp
ld sp, 35*8(sp)
# switch to kernel space
csrw satp, t0
sfence.vma
# jump to trap_handler
jr t1
__restore:
# a0: *TrapContext in user space(Constant); a1: user space token
# switch to user space
csrw satp, a1
sfence.vma
csrw sscratch, a0
mv sp, a0
# now sp points to TrapContext in user space, start restoring based on it
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
csrw sstatus, t0
csrw sepc, t1
# restore general purpose registers except x0/sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# back to user stack
ld sp, 2*8(sp)
sret
.section .data
# emergency stack for kernel trap
# in order to print trap info even if the kernel stack is corrupted.
__emergency:
.align 4
.space 1024 * 4
__emergency_end:
.section .text
.globl __trap_from_kernel
# 2^2=4 bytes aligned for stvec
.align 2
__trap_from_kernel:
la sp, __emergency_end
j trap_from_kernel
|
haozixu/oscamp
| 4,857
|
arceos/exercises/simple_hv/src/guest.S
|
/// Enter the guest given in `VmCpuRegisters` from `a0`
.global _run_guest
_run_guest:
/* Save hypervisor state */
/* Save hypervisor GPRs (except T0-T6 and a0, which is GuestInfo and stashed in sscratch) */
sd ra, ({hyp_ra})(a0)
sd gp, ({hyp_gp})(a0)
sd tp, ({hyp_tp})(a0)
sd s0, ({hyp_s0})(a0)
sd s1, ({hyp_s1})(a0)
sd a1, ({hyp_a1})(a0)
sd a2, ({hyp_a2})(a0)
sd a3, ({hyp_a3})(a0)
sd a4, ({hyp_a4})(a0)
sd a5, ({hyp_a5})(a0)
sd a6, ({hyp_a6})(a0)
sd a7, ({hyp_a7})(a0)
sd s2, ({hyp_s2})(a0)
sd s3, ({hyp_s3})(a0)
sd s4, ({hyp_s4})(a0)
sd s5, ({hyp_s5})(a0)
sd s6, ({hyp_s6})(a0)
sd s7, ({hyp_s7})(a0)
sd s8, ({hyp_s8})(a0)
sd s9, ({hyp_s9})(a0)
sd s10, ({hyp_s10})(a0)
sd s11, ({hyp_s11})(a0)
sd sp, ({hyp_sp})(a0)
/* Swap in guest CSRs. */
ld t1, ({guest_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({hyp_sstatus})(a0)
ld t1, ({guest_hstatus})(a0)
csrrw t1, hstatus, t1
ld t1, ({guest_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({hyp_scounteren})(a0)
ld t1, ({guest_sepc})(a0)
csrw sepc, t1
/* Set stvec so that hypervisor resumes after the sret when the guest exits. */
la t1, _guest_exit
csrrw t1, stvec, t1
sd t1, ({hyp_stvec})(a0)
/* Save sscratch and replace with pointer to GuestInfo. */
csrrw t1, sscratch, a0
sd t1, ({hyp_sscratch})(a0)
/* Restore the gprs from this GuestInfo */
ld ra, ({guest_ra})(a0)
ld gp, ({guest_gp})(a0)
ld tp, ({guest_tp})(a0)
ld s0, ({guest_s0})(a0)
ld s1, ({guest_s1})(a0)
ld a1, ({guest_a1})(a0)
ld a2, ({guest_a2})(a0)
ld a3, ({guest_a3})(a0)
ld a4, ({guest_a4})(a0)
ld a5, ({guest_a5})(a0)
ld a6, ({guest_a6})(a0)
ld a7, ({guest_a7})(a0)
ld s2, ({guest_s2})(a0)
ld s3, ({guest_s3})(a0)
ld s4, ({guest_s4})(a0)
ld s5, ({guest_s5})(a0)
ld s6, ({guest_s6})(a0)
ld s7, ({guest_s7})(a0)
ld s8, ({guest_s8})(a0)
ld s9, ({guest_s9})(a0)
ld s10, ({guest_s10})(a0)
ld s11, ({guest_s11})(a0)
ld t0, ({guest_t0})(a0)
ld t1, ({guest_t1})(a0)
ld t2, ({guest_t2})(a0)
ld t3, ({guest_t3})(a0)
ld t4, ({guest_t4})(a0)
ld t5, ({guest_t5})(a0)
ld t6, ({guest_t6})(a0)
ld sp, ({guest_sp})(a0)
ld a0, ({guest_a0})(a0)
sret
.align 2
_guest_exit:
/* Pull GuestInfo out of sscratch, swapping with guest's a0 */
csrrw a0, sscratch, a0
/* Save guest GPRs. */
sd ra, ({guest_ra})(a0)
sd gp, ({guest_gp})(a0)
sd tp, ({guest_tp})(a0)
sd s0, ({guest_s0})(a0)
sd s1, ({guest_s1})(a0)
sd a1, ({guest_a1})(a0)
sd a2, ({guest_a2})(a0)
sd a3, ({guest_a3})(a0)
sd a4, ({guest_a4})(a0)
sd a5, ({guest_a5})(a0)
sd a6, ({guest_a6})(a0)
sd a7, ({guest_a7})(a0)
sd s2, ({guest_s2})(a0)
sd s3, ({guest_s3})(a0)
sd s4, ({guest_s4})(a0)
sd s5, ({guest_s5})(a0)
sd s6, ({guest_s6})(a0)
sd s7, ({guest_s7})(a0)
sd s8, ({guest_s8})(a0)
sd s9, ({guest_s9})(a0)
sd s10, ({guest_s10})(a0)
sd s11, ({guest_s11})(a0)
sd t0, ({guest_t0})(a0)
sd t1, ({guest_t1})(a0)
sd t2, ({guest_t2})(a0)
sd t3, ({guest_t3})(a0)
sd t4, ({guest_t4})(a0)
sd t5, ({guest_t5})(a0)
sd t6, ({guest_t6})(a0)
sd sp, ({guest_sp})(a0)
/* Save Guest a0 after recovering from sscratch. */
csrr t0, sscratch
sd t0, ({guest_a0})(a0)
_restore_csrs:
/* Swap in hypervisor CSRs. */
ld t1, ({hyp_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({guest_sstatus})(a0)
csrr t1, hstatus
sd t1, ({guest_hstatus})(a0)
ld t1, ({hyp_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({guest_scounteren})(a0)
ld t1, ({hyp_stvec})(a0)
csrw stvec, t1
ld t1, ({hyp_sscratch})(a0)
csrw sscratch, t1
/* Save guest EPC. */
csrr t1, sepc
sd t1, ({guest_sepc})(a0)
/* Restore hypervisor GPRs. */
ld ra, ({hyp_ra})(a0)
ld gp, ({hyp_gp})(a0)
ld tp, ({hyp_tp})(a0)
ld s0, ({hyp_s0})(a0)
ld s1, ({hyp_s1})(a0)
ld a1, ({hyp_a1})(a0)
ld a2, ({hyp_a2})(a0)
ld a3, ({hyp_a3})(a0)
ld a4, ({hyp_a4})(a0)
ld a5, ({hyp_a5})(a0)
ld a6, ({hyp_a6})(a0)
ld a7, ({hyp_a7})(a0)
ld s2, ({hyp_s2})(a0)
ld s3, ({hyp_s3})(a0)
ld s4, ({hyp_s4})(a0)
ld s5, ({hyp_s5})(a0)
ld s6, ({hyp_s6})(a0)
ld s7, ({hyp_s7})(a0)
ld s8, ({hyp_s8})(a0)
ld s9, ({hyp_s9})(a0)
ld s10, ({hyp_s10})(a0)
ld s11, ({hyp_s11})(a0)
ld sp, ({hyp_sp})(a0)
ret
|
haozixu/oscamp
| 1,827
|
arceos/modules/axhal/linker.lds.S
|
OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
. = ALIGN(4K);
_etext = .;
}
.rodata : ALIGN(4K) {
_srodata = .;
*(.rodata .rodata.*)
*(.srodata .srodata.*)
*(.sdata2 .sdata2.*)
. = ALIGN(4K);
_erodata = .;
}
.data : ALIGN(4K) {
_sdata = .;
*(.data.boot_page_table)
. = ALIGN(4K);
*(.data .data.*)
*(.sdata .sdata.*)
*(.got .got.*)
}
.tdata : ALIGN(0x10) {
_stdata = .;
*(.tdata .tdata.*)
_etdata = .;
}
.tbss : ALIGN(0x10) {
_stbss = .;
*(.tbss .tbss.*)
*(.tcommon)
_etbss = .;
}
. = ALIGN(4K);
_percpu_start = .;
_percpu_end = _percpu_start + SIZEOF(.percpu);
.percpu 0x0 : AT(_percpu_start) {
_percpu_load_start = .;
*(.percpu .percpu.*)
_percpu_load_end = .;
. = _percpu_load_start + ALIGN(64) * %SMP%;
}
. = _percpu_end;
. = ALIGN(4K);
_edata = .;
.bss : ALIGN(4K) {
boot_stack = .;
*(.bss.stack)
. = ALIGN(4K);
boot_stack_top = .;
_sbss = .;
*(.bss .bss.*)
*(.sbss .sbss.*)
*(COMMON)
. = ALIGN(4K);
_ebss = .;
}
_ekernel = .;
/DISCARD/ : {
*(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
}
}
SECTIONS {
linkme_IRQ : { *(linkme_IRQ) }
linkm2_IRQ : { *(linkm2_IRQ) }
linkme_PAGE_FAULT : { *(linkme_PAGE_FAULT) }
linkm2_PAGE_FAULT : { *(linkm2_PAGE_FAULT) }
linkme_SYSCALL : { *(linkme_SYSCALL) }
linkm2_SYSCALL : { *(linkm2_SYSCALL) }
}
INSERT AFTER .tbss;
|
haozixu/oscamp
| 4,307
|
arceos/modules/axhal/src/platform/x86_pc/multiboot.S
|
# Bootstrapping from 32-bit with the Multiboot specification.
# See https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section .text.boot
.code32
.global _start
_start:
mov edi, eax # arg1: magic: 0x2BADB002
mov esi, ebx # arg2: multiboot info
jmp bsp_entry32
.balign 4
.type multiboot_header, STT_OBJECT
multiboot_header:
.int {mb_hdr_magic} # magic: 0x1BADB002
.int {mb_hdr_flags} # flags
.int -({mb_hdr_magic} + {mb_hdr_flags}) # checksum
.int multiboot_header - {offset} # header_addr
.int _skernel - {offset} # load_addr
.int _edata - {offset} # load_end
.int _ebss - {offset} # bss_end_addr
.int _start - {offset} # entry_addr
# Common code in 32-bit, prepare states to enter 64-bit.
.macro ENTRY32_COMMON
# set data segment selectors
mov ax, 0x18
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
# set PAE, PGE bit in CR4
mov eax, {cr4}
mov cr4, eax
# load the temporary page table
lea eax, [.Ltmp_pml4 - {offset}]
mov cr3, eax
# set LME, NXE bit in IA32_EFER
mov ecx, {efer_msr}
mov edx, 0
mov eax, {efer}
wrmsr
# set protected mode, write protect, paging bit in CR0
mov eax, {cr0}
mov cr0, eax
.endm
# Common code in 64-bit
.macro ENTRY64_COMMON
# clear segment selectors
xor ax, ax
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
.endm
.code32
bsp_entry32:
lgdt [.Ltmp_gdt_desc - {offset}] # load the temporary GDT
ENTRY32_COMMON
ljmp 0x10, offset bsp_entry64 - {offset} # 0x10 is code64 segment
.code32
.global ap_entry32
ap_entry32:
ENTRY32_COMMON
ljmp 0x10, offset ap_entry64 - {offset} # 0x10 is code64 segment
.code64
bsp_entry64:
ENTRY64_COMMON
# set RSP to boot stack
movabs rsp, offset {boot_stack}
add rsp, {boot_stack_size}
# call rust_entry(magic, mbi)
movabs rax, offset {entry}
call rax
jmp .Lhlt
.code64
ap_entry64:
ENTRY64_COMMON
# set RSP to high address (already set in ap_start.S)
mov rax, {offset}
add rsp, rax
# call rust_entry_secondary(magic)
mov rdi, {mb_magic}
movabs rax, offset {entry_secondary}
call rax
jmp .Lhlt
.Lhlt:
hlt
jmp .Lhlt
.section .rodata
.balign 8
.Ltmp_gdt_desc:
.short .Ltmp_gdt_end - .Ltmp_gdt - 1 # limit
.long .Ltmp_gdt - {offset} # base
.section .data
.balign 16
.Ltmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Ltmp_gdt_end:
.balign 4096
.Ltmp_pml4:
# 0x0000_0000 ~ 0xffff_ffff
.quad .Ltmp_pdpt_low - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
.zero 8 * 510
# 0xffff_ff80_0000_0000 ~ 0xffff_ff80_ffff_ffff
.quad .Ltmp_pdpt_high - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
# FIXME: may not work on macOS using hvf as the CPU does not support 1GB page (pdpe1gb)
.Ltmp_pdpt_low:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
.Ltmp_pdpt_high:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
|
haozixu/oscamp
| 1,965
|
arceos/modules/axhal/src/platform/x86_pc/ap_start.S
|
# Boot application processors into the protected mode.
# Each non-boot CPU ("AP") is started up in response to a STARTUP
# IPI from the boot CPU. Section B.4.2 of the Multi-Processor
# Specification says that the AP will start in real mode with CS:IP
# set to XY00:0000, where XY is an 8-bit value sent with the
# STARTUP. Thus this code must start at a 4096-byte boundary.
#
# Because this code sets DS to zero, it must sit
# at an address in the low 2^16 bytes.
.equ pa_ap_start32, ap_start32 - ap_start + {start_page_paddr}
.equ pa_ap_gdt, .Lap_tmp_gdt - ap_start + {start_page_paddr}
.equ pa_ap_gdt_desc, .Lap_tmp_gdt_desc - ap_start + {start_page_paddr}
.equ stack_ptr, {start_page_paddr} + 0xff0
.equ entry_ptr, {start_page_paddr} + 0xff8
# 0x6000
.section .text
.code16
.p2align 12
.global ap_start
ap_start:
cli
wbinvd
xor ax, ax
mov ds, ax
mov es, ax
mov ss, ax
mov fs, ax
mov gs, ax
# load the 64-bit GDT
lgdt [pa_ap_gdt_desc]
# switch to protected-mode
mov eax, cr0
or eax, (1 << 0)
mov cr0, eax
# far jump to 32-bit code. 0x8 is code32 segment selector
ljmp 0x8, offset pa_ap_start32
.code32
ap_start32:
mov esp, [stack_ptr]
mov eax, [entry_ptr]
jmp eax
.balign 8
# .type multiboot_header, STT_OBJECT
.Lap_tmp_gdt_desc:
.short .Lap_tmp_gdt_end - .Lap_tmp_gdt - 1 # limit
.long pa_ap_gdt # base
.balign 16
.Lap_tmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Lap_tmp_gdt_end:
# 0x7000
.p2align 12
.global ap_end
ap_end:
|
haozixu/oscamp
| 1,839
|
arceos/modules/axhal/src/arch/riscv/trap.S
|
.macro SAVE_REGS, from_user
addi sp, sp, -{trapframe_size}
PUSH_GENERAL_REGS
csrr t0, sepc
csrr t1, sstatus
csrrw t2, sscratch, zero // save sscratch (sp) and zero it
STR t0, sp, 31 // tf.sepc
STR t1, sp, 32 // tf.sstatus
STR t2, sp, 1 // tf.regs.sp
.if \from_user == 1
LDR t0, sp, 2 // load supervisor gp
LDR t1, sp, 3 // load supervisor tp
STR gp, sp, 2 // save user gp and tp
STR tp, sp, 3
mv gp, t0
mv tp, t1
.endif
.endm
.macro RESTORE_REGS, from_user
.if \from_user == 1
LDR t1, sp, 2 // load user gp and tp
LDR t0, sp, 3
STR gp, sp, 2 // save supervisor gp
STR tp, sp, 3 // save supervisor gp and tp
mv gp, t1
mv tp, t0
addi t0, sp, {trapframe_size} // put supervisor sp to scratch
csrw sscratch, t0
.endif
LDR t0, sp, 31
LDR t1, sp, 32
csrw sepc, t0
csrw sstatus, t1
POP_GENERAL_REGS
LDR sp, sp, 1 // load sp from tf.regs.sp
.endm
.section .text
.balign 4
.global trap_vector_base
trap_vector_base:
// sscratch == 0: trap from S mode
// sscratch != 0: trap from U mode
csrrw sp, sscratch, sp // swap sscratch and sp
bnez sp, .Ltrap_entry_u
csrr sp, sscratch // put supervisor sp back
j .Ltrap_entry_s
.Ltrap_entry_s:
SAVE_REGS 0
mv a0, sp
li a1, 0
call riscv_trap_handler
RESTORE_REGS 0
sret
.Ltrap_entry_u:
SAVE_REGS 1
mv a0, sp
li a1, 1
call riscv_trap_handler
RESTORE_REGS 1
sret
|
haozixu/oscamp
| 1,505
|
arceos/modules/axhal/src/arch/x86_64/trap.S
|
.equ NUM_INT, 256
.altmacro
.macro DEF_HANDLER, i
.Ltrap_handler_\i:
.if \i == 8 || (\i >= 10 && \i <= 14) || \i == 17
# error code pushed by CPU
push \i # interrupt vector
jmp .Ltrap_common
.else
push 0 # fill in error code in TrapFrame
push \i # interrupt vector
jmp .Ltrap_common
.endif
.endm
.macro DEF_TABLE_ENTRY, i
.quad .Ltrap_handler_\i
.endm
.section .text
.code64
_trap_handlers:
.set i, 0
.rept NUM_INT
DEF_HANDLER %i
.set i, i + 1
.endr
.Ltrap_common:
test byte ptr [rsp + 3 * 8], 3 # swap GS if it comes from user space
jz 1f
swapgs
1:
push r15
push r14
push r13
push r12
push r11
push r10
push r9
push r8
push rdi
push rsi
push rbp
push rbx
push rdx
push rcx
push rax
mov rdi, rsp
call x86_trap_handler
pop rax
pop rcx
pop rdx
pop rbx
pop rbp
pop rsi
pop rdi
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
test byte ptr [rsp + 3 * 8], 3 # swap GS back if return to user space
jz 2f
swapgs
2:
add rsp, 16 # pop vector, error_code
iretq
.section .rodata
.global trap_handler_table
trap_handler_table:
.set i, 0
.rept NUM_INT
DEF_TABLE_ENTRY %i
.set i, i + 1
.endr
|
haozixu/oscamp
| 2,415
|
arceos/modules/axhal/src/arch/aarch64/trap.S
|
.macro SAVE_REGS
sub sp, sp, 34 * 8
stp x0, x1, [sp]
stp x2, x3, [sp, 2 * 8]
stp x4, x5, [sp, 4 * 8]
stp x6, x7, [sp, 6 * 8]
stp x8, x9, [sp, 8 * 8]
stp x10, x11, [sp, 10 * 8]
stp x12, x13, [sp, 12 * 8]
stp x14, x15, [sp, 14 * 8]
stp x16, x17, [sp, 16 * 8]
stp x18, x19, [sp, 18 * 8]
stp x20, x21, [sp, 20 * 8]
stp x22, x23, [sp, 22 * 8]
stp x24, x25, [sp, 24 * 8]
stp x26, x27, [sp, 26 * 8]
stp x28, x29, [sp, 28 * 8]
mrs x9, sp_el0
mrs x10, elr_el1
mrs x11, spsr_el1
stp x30, x9, [sp, 30 * 8]
stp x10, x11, [sp, 32 * 8]
.endm
.macro RESTORE_REGS
ldp x10, x11, [sp, 32 * 8]
ldp x30, x9, [sp, 30 * 8]
msr sp_el0, x9
msr elr_el1, x10
msr spsr_el1, x11
ldp x28, x29, [sp, 28 * 8]
ldp x26, x27, [sp, 26 * 8]
ldp x24, x25, [sp, 24 * 8]
ldp x22, x23, [sp, 22 * 8]
ldp x20, x21, [sp, 20 * 8]
ldp x18, x19, [sp, 18 * 8]
ldp x16, x17, [sp, 16 * 8]
ldp x14, x15, [sp, 14 * 8]
ldp x12, x13, [sp, 12 * 8]
ldp x10, x11, [sp, 10 * 8]
ldp x8, x9, [sp, 8 * 8]
ldp x6, x7, [sp, 6 * 8]
ldp x4, x5, [sp, 4 * 8]
ldp x2, x3, [sp, 2 * 8]
ldp x0, x1, [sp]
add sp, sp, 34 * 8
.endm
.macro INVALID_EXCP, kind, source
.p2align 7
SAVE_REGS
mov x0, sp
mov x1, \kind
mov x2, \source
bl invalid_exception
b .Lexception_return
.endm
.macro HANDLE_SYNC
.p2align 7
SAVE_REGS
mov x0, sp
bl handle_sync_exception
b .Lexception_return
.endm
.macro HANDLE_IRQ
.p2align 7
SAVE_REGS
mov x0, sp
bl handle_irq_exception
b .Lexception_return
.endm
.section .text
.p2align 11
.global exception_vector_base
exception_vector_base:
// current EL, with SP_EL0
INVALID_EXCP 0 0
INVALID_EXCP 1 0
INVALID_EXCP 2 0
INVALID_EXCP 3 0
// current EL, with SP_ELx
HANDLE_SYNC
HANDLE_IRQ
INVALID_EXCP 2 1
INVALID_EXCP 3 1
// lower EL, aarch64
HANDLE_SYNC
HANDLE_IRQ
INVALID_EXCP 2 2
INVALID_EXCP 3 2
// lower EL, aarch32
INVALID_EXCP 0 3
INVALID_EXCP 1 3
INVALID_EXCP 2 3
INVALID_EXCP 3 3
.Lexception_return:
RESTORE_REGS
eret
|
haozixu/oscamp
| 4,857
|
arceos/modules/riscv_vcpu/src/guest.S
|
/// Enter the guest given in `VmCpuRegisters` from `a0`
.global _run_guest
_run_guest:
/* Save hypervisor state */
/* Save hypervisor GPRs (except T0-T6 and a0, which is GuestInfo and stashed in sscratch) */
sd ra, ({hyp_ra})(a0)
sd gp, ({hyp_gp})(a0)
sd tp, ({hyp_tp})(a0)
sd s0, ({hyp_s0})(a0)
sd s1, ({hyp_s1})(a0)
sd a1, ({hyp_a1})(a0)
sd a2, ({hyp_a2})(a0)
sd a3, ({hyp_a3})(a0)
sd a4, ({hyp_a4})(a0)
sd a5, ({hyp_a5})(a0)
sd a6, ({hyp_a6})(a0)
sd a7, ({hyp_a7})(a0)
sd s2, ({hyp_s2})(a0)
sd s3, ({hyp_s3})(a0)
sd s4, ({hyp_s4})(a0)
sd s5, ({hyp_s5})(a0)
sd s6, ({hyp_s6})(a0)
sd s7, ({hyp_s7})(a0)
sd s8, ({hyp_s8})(a0)
sd s9, ({hyp_s9})(a0)
sd s10, ({hyp_s10})(a0)
sd s11, ({hyp_s11})(a0)
sd sp, ({hyp_sp})(a0)
/* Swap in guest CSRs. */
ld t1, ({guest_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({hyp_sstatus})(a0)
ld t1, ({guest_hstatus})(a0)
csrrw t1, hstatus, t1
ld t1, ({guest_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({hyp_scounteren})(a0)
ld t1, ({guest_sepc})(a0)
csrw sepc, t1
/* Set stvec so that hypervisor resumes after the sret when the guest exits. */
la t1, _guest_exit
csrrw t1, stvec, t1
sd t1, ({hyp_stvec})(a0)
/* Save sscratch and replace with pointer to GuestInfo. */
csrrw t1, sscratch, a0
sd t1, ({hyp_sscratch})(a0)
/* Restore the gprs from this GuestInfo */
ld ra, ({guest_ra})(a0)
ld gp, ({guest_gp})(a0)
ld tp, ({guest_tp})(a0)
ld s0, ({guest_s0})(a0)
ld s1, ({guest_s1})(a0)
ld a1, ({guest_a1})(a0)
ld a2, ({guest_a2})(a0)
ld a3, ({guest_a3})(a0)
ld a4, ({guest_a4})(a0)
ld a5, ({guest_a5})(a0)
ld a6, ({guest_a6})(a0)
ld a7, ({guest_a7})(a0)
ld s2, ({guest_s2})(a0)
ld s3, ({guest_s3})(a0)
ld s4, ({guest_s4})(a0)
ld s5, ({guest_s5})(a0)
ld s6, ({guest_s6})(a0)
ld s7, ({guest_s7})(a0)
ld s8, ({guest_s8})(a0)
ld s9, ({guest_s9})(a0)
ld s10, ({guest_s10})(a0)
ld s11, ({guest_s11})(a0)
ld t0, ({guest_t0})(a0)
ld t1, ({guest_t1})(a0)
ld t2, ({guest_t2})(a0)
ld t3, ({guest_t3})(a0)
ld t4, ({guest_t4})(a0)
ld t5, ({guest_t5})(a0)
ld t6, ({guest_t6})(a0)
ld sp, ({guest_sp})(a0)
ld a0, ({guest_a0})(a0)
sret
.align 2
_guest_exit:
/* Pull GuestInfo out of sscratch, swapping with guest's a0 */
csrrw a0, sscratch, a0
/* Save guest GPRs. */
sd ra, ({guest_ra})(a0)
sd gp, ({guest_gp})(a0)
sd tp, ({guest_tp})(a0)
sd s0, ({guest_s0})(a0)
sd s1, ({guest_s1})(a0)
sd a1, ({guest_a1})(a0)
sd a2, ({guest_a2})(a0)
sd a3, ({guest_a3})(a0)
sd a4, ({guest_a4})(a0)
sd a5, ({guest_a5})(a0)
sd a6, ({guest_a6})(a0)
sd a7, ({guest_a7})(a0)
sd s2, ({guest_s2})(a0)
sd s3, ({guest_s3})(a0)
sd s4, ({guest_s4})(a0)
sd s5, ({guest_s5})(a0)
sd s6, ({guest_s6})(a0)
sd s7, ({guest_s7})(a0)
sd s8, ({guest_s8})(a0)
sd s9, ({guest_s9})(a0)
sd s10, ({guest_s10})(a0)
sd s11, ({guest_s11})(a0)
sd t0, ({guest_t0})(a0)
sd t1, ({guest_t1})(a0)
sd t2, ({guest_t2})(a0)
sd t3, ({guest_t3})(a0)
sd t4, ({guest_t4})(a0)
sd t5, ({guest_t5})(a0)
sd t6, ({guest_t6})(a0)
sd sp, ({guest_sp})(a0)
/* Save Guest a0 after recovering from sscratch. */
csrr t0, sscratch
sd t0, ({guest_a0})(a0)
_restore_csrs:
/* Swap in hypervisor CSRs. */
ld t1, ({hyp_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({guest_sstatus})(a0)
csrr t1, hstatus
sd t1, ({guest_hstatus})(a0)
ld t1, ({hyp_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({guest_scounteren})(a0)
ld t1, ({hyp_stvec})(a0)
csrw stvec, t1
ld t1, ({hyp_sscratch})(a0)
csrw sscratch, t1
/* Save guest EPC. */
csrr t1, sepc
sd t1, ({guest_sepc})(a0)
/* Restore hypervisor GPRs. */
ld ra, ({hyp_ra})(a0)
ld gp, ({hyp_gp})(a0)
ld tp, ({hyp_tp})(a0)
ld s0, ({hyp_s0})(a0)
ld s1, ({hyp_s1})(a0)
ld a1, ({hyp_a1})(a0)
ld a2, ({hyp_a2})(a0)
ld a3, ({hyp_a3})(a0)
ld a4, ({hyp_a4})(a0)
ld a5, ({hyp_a5})(a0)
ld a6, ({hyp_a6})(a0)
ld a7, ({hyp_a7})(a0)
ld s2, ({hyp_s2})(a0)
ld s3, ({hyp_s3})(a0)
ld s4, ({hyp_s4})(a0)
ld s5, ({hyp_s5})(a0)
ld s6, ({hyp_s6})(a0)
ld s7, ({hyp_s7})(a0)
ld s8, ({hyp_s8})(a0)
ld s9, ({hyp_s9})(a0)
ld s10, ({hyp_s10})(a0)
ld s11, ({hyp_s11})(a0)
ld sp, ({hyp_sp})(a0)
ret
|
haozixu/oscamp
| 3,437
|
arceos/modules/riscv_vcpu/src/mem_extable.S
|
// Copyright (c) 2022 by Rivos Inc.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Very unoptimized memcpy() to/from guest memory functions, using the HLV/HSV instructions.
// Adds the instruction at 'lbl' to the exception table.
.macro add_extable lbl
.pushsection .extable, "a"
.balign 8
.quad \lbl
.popsection
.endm
.option push
.option arch, +h
.section .text
// memcpy() to a guest physical address using HSV.
.global _copy_to_guest
_copy_to_guest:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, _ret_from_copy
// _ret_from_copy assumes the return value is in t2.
mv t2, zero
1:
beq t2, a2, _ret_from_copy
lb t3, (a1)
2:
hsv.b t3, (a0)
add_extable 2b
addi a0, a0, 1
addi a1, a1, 1
addi t2, t2, 1
j 1b
// memcpy() from a guest physical address using HLV.
.global _copy_from_guest
_copy_from_guest:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, _ret_from_copy
// _ret_from_copy assumes the return value is in t2.
mv t2, zero
1:
beq t2, a2, _ret_from_copy
2:
hlv.b t3, (a1)
add_extable 2b
sb t3, (a0)
addi a0, a0, 1
addi a1, a1, 1
addi t2, t2, 1
j 1b
// Fetch an instruction from guest memory using HLVX. Only supports 2 or 4 byte instructions.
//
// Arguments:
// A0: Guest address of the instruction to fetch, using the translation modes/tables currently
// programmed in HGATP and VSATP.
// A1: Pointer to a u32 where the instruction will be written.
//
// Returns -1 on error.
.global _fetch_guest_instruction
_fetch_guest_instruction:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, 4f
1:
hlvx.hu t2, (a0)
add_extable 1b
sh t2, (a1)
addi a0, a0, 2
addi a1, a1, 2
// If it's a compressed instrution (bits [1:0] != 'b11) then we're done.
li t3, 3
and t2, t2, t3
bne t2, t3, 3f
// Load the next half-word.
2:
hlvx.hu t2, (a0)
add_extable 2b
sh t2, (a1)
3:
mv a0, zero
ret
4:
// Took a fault, return -1.
not a0, zero
ret
// memcpy() to a user address.
.global _copy_to_user
_copy_to_user:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, _ret_from_copy
// _ret_from_copy assumes the return value is in t2.
mv t2, zero
1:
beq t2, a2, _ret_from_copy
lb t3, (a1)
2:
sb t3, (a0)
add_extable 2b
addi a0, a0, 1
addi a1, a1, 1
addi t2, t2, 1
j 1b
// memcpy() from a user address.
.global _copy_from_user
_copy_from_user:
// handle_trap assumes t0 holds the address of where we want to jump to when we encounter
// a fault and will stick SCAUSE in t1.
la t0, _ret_from_copy
// _ret_from_copy assumes the return value is in t2.
mv t2, zero
1:
beq t2, a2, _ret_from_copy
2:
lb t3, (a1)
add_extable 2b
sb t3, (a0)
addi a0, a0, 1
addi a1, a1, 1
addi t2, t2, 1
j 1b
.align 2
_ret_from_copy:
mv a0, t2
ret
.option pop
|
haozixu/oscamp
| 2,544
|
arceos/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.s
|
// SPDX-License-Identifier: MIT OR Apache-2.0
//
// Copyright (c) 2021-2022 Andre Richter <andre.o.richter@gmail.com>
//--------------------------------------------------------------------------------------------------
// Definitions
//--------------------------------------------------------------------------------------------------
// Load the address of a symbol into a register, PC-relative.
//
// The symbol must lie within +/- 4 GiB of the Program Counter.
//
// # Resources
//
// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html
.macro ADR_REL register, symbol
adrp \register, \symbol
add \register, \register, #:lo12:\symbol
.endm
// Load the address of a symbol into a register, absolute.
//
// # Resources
//
// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html
.macro ADR_ABS register, symbol
movz \register, #:abs_g2:\symbol
movk \register, #:abs_g1_nc:\symbol
movk \register, #:abs_g0_nc:\symbol
.endm
//--------------------------------------------------------------------------------------------------
// Public Code
//--------------------------------------------------------------------------------------------------
.section .text._start
//------------------------------------------------------------------------------
// fn _start()
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.
// Initialize DRAM.
ADR_ABS x0, __bss_start
ADR_ABS x1, __bss_end_exclusive
.L_bss_init_loop:
cmp x0, x1
b.eq .L_relocate_binary
stp xzr, xzr, [x0], #16
b .L_bss_init_loop
// Next, relocate the binary.
.L_relocate_binary:
ADR_REL x0, __binary_nonzero_start // The address the binary got loaded to.
ADR_ABS x1, __binary_nonzero_start // The address the binary was linked to.
ADR_ABS x2, __binary_nonzero_end_exclusive
.L_copy_loop:
ldr x3, [x0], #8
str x3, [x1], #8
cmp x1, x2
b.lo .L_copy_loop
// Prepare the jump to Rust code.
// Set the stack pointer.
ADR_ABS x0, __boot_core_stack_end_exclusive
mov sp, x0
// Jump to the relocated Rust code.
ADR_ABS x1, _start_rust
br x1
// Infinitely wait for events (aka "park the core").
.L_parking_loop:
wfe
b .L_parking_loop
.size _start, . - _start
.type _start, function
.global _start
|
haozixu/oscamp
| 4,857
|
arceos/tour/h_1_0/src/guest.S
|
/// Enter the guest given in `VmCpuRegisters` from `a0`
.global _run_guest
_run_guest:
/* Save hypervisor state */
/* Save hypervisor GPRs (except T0-T6 and a0, which is GuestInfo and stashed in sscratch) */
sd ra, ({hyp_ra})(a0)
sd gp, ({hyp_gp})(a0)
sd tp, ({hyp_tp})(a0)
sd s0, ({hyp_s0})(a0)
sd s1, ({hyp_s1})(a0)
sd a1, ({hyp_a1})(a0)
sd a2, ({hyp_a2})(a0)
sd a3, ({hyp_a3})(a0)
sd a4, ({hyp_a4})(a0)
sd a5, ({hyp_a5})(a0)
sd a6, ({hyp_a6})(a0)
sd a7, ({hyp_a7})(a0)
sd s2, ({hyp_s2})(a0)
sd s3, ({hyp_s3})(a0)
sd s4, ({hyp_s4})(a0)
sd s5, ({hyp_s5})(a0)
sd s6, ({hyp_s6})(a0)
sd s7, ({hyp_s7})(a0)
sd s8, ({hyp_s8})(a0)
sd s9, ({hyp_s9})(a0)
sd s10, ({hyp_s10})(a0)
sd s11, ({hyp_s11})(a0)
sd sp, ({hyp_sp})(a0)
/* Swap in guest CSRs. */
ld t1, ({guest_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({hyp_sstatus})(a0)
ld t1, ({guest_hstatus})(a0)
csrrw t1, hstatus, t1
ld t1, ({guest_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({hyp_scounteren})(a0)
ld t1, ({guest_sepc})(a0)
csrw sepc, t1
/* Set stvec so that hypervisor resumes after the sret when the guest exits. */
la t1, _guest_exit
csrrw t1, stvec, t1
sd t1, ({hyp_stvec})(a0)
/* Save sscratch and replace with pointer to GuestInfo. */
csrrw t1, sscratch, a0
sd t1, ({hyp_sscratch})(a0)
/* Restore the gprs from this GuestInfo */
ld ra, ({guest_ra})(a0)
ld gp, ({guest_gp})(a0)
ld tp, ({guest_tp})(a0)
ld s0, ({guest_s0})(a0)
ld s1, ({guest_s1})(a0)
ld a1, ({guest_a1})(a0)
ld a2, ({guest_a2})(a0)
ld a3, ({guest_a3})(a0)
ld a4, ({guest_a4})(a0)
ld a5, ({guest_a5})(a0)
ld a6, ({guest_a6})(a0)
ld a7, ({guest_a7})(a0)
ld s2, ({guest_s2})(a0)
ld s3, ({guest_s3})(a0)
ld s4, ({guest_s4})(a0)
ld s5, ({guest_s5})(a0)
ld s6, ({guest_s6})(a0)
ld s7, ({guest_s7})(a0)
ld s8, ({guest_s8})(a0)
ld s9, ({guest_s9})(a0)
ld s10, ({guest_s10})(a0)
ld s11, ({guest_s11})(a0)
ld t0, ({guest_t0})(a0)
ld t1, ({guest_t1})(a0)
ld t2, ({guest_t2})(a0)
ld t3, ({guest_t3})(a0)
ld t4, ({guest_t4})(a0)
ld t5, ({guest_t5})(a0)
ld t6, ({guest_t6})(a0)
ld sp, ({guest_sp})(a0)
ld a0, ({guest_a0})(a0)
sret
.align 2
_guest_exit:
/* Pull GuestInfo out of sscratch, swapping with guest's a0 */
csrrw a0, sscratch, a0
/* Save guest GPRs. */
sd ra, ({guest_ra})(a0)
sd gp, ({guest_gp})(a0)
sd tp, ({guest_tp})(a0)
sd s0, ({guest_s0})(a0)
sd s1, ({guest_s1})(a0)
sd a1, ({guest_a1})(a0)
sd a2, ({guest_a2})(a0)
sd a3, ({guest_a3})(a0)
sd a4, ({guest_a4})(a0)
sd a5, ({guest_a5})(a0)
sd a6, ({guest_a6})(a0)
sd a7, ({guest_a7})(a0)
sd s2, ({guest_s2})(a0)
sd s3, ({guest_s3})(a0)
sd s4, ({guest_s4})(a0)
sd s5, ({guest_s5})(a0)
sd s6, ({guest_s6})(a0)
sd s7, ({guest_s7})(a0)
sd s8, ({guest_s8})(a0)
sd s9, ({guest_s9})(a0)
sd s10, ({guest_s10})(a0)
sd s11, ({guest_s11})(a0)
sd t0, ({guest_t0})(a0)
sd t1, ({guest_t1})(a0)
sd t2, ({guest_t2})(a0)
sd t3, ({guest_t3})(a0)
sd t4, ({guest_t4})(a0)
sd t5, ({guest_t5})(a0)
sd t6, ({guest_t6})(a0)
sd sp, ({guest_sp})(a0)
/* Save Guest a0 after recovering from sscratch. */
csrr t0, sscratch
sd t0, ({guest_a0})(a0)
_restore_csrs:
/* Swap in hypervisor CSRs. */
ld t1, ({hyp_sstatus})(a0)
csrrw t1, sstatus, t1
sd t1, ({guest_sstatus})(a0)
csrr t1, hstatus
sd t1, ({guest_hstatus})(a0)
ld t1, ({hyp_scounteren})(a0)
csrrw t1, scounteren, t1
sd t1, ({guest_scounteren})(a0)
ld t1, ({hyp_stvec})(a0)
csrw stvec, t1
ld t1, ({hyp_sscratch})(a0)
csrw sscratch, t1
/* Save guest EPC. */
csrr t1, sepc
sd t1, ({guest_sepc})(a0)
/* Restore hypervisor GPRs. */
ld ra, ({hyp_ra})(a0)
ld gp, ({hyp_gp})(a0)
ld tp, ({hyp_tp})(a0)
ld s0, ({hyp_s0})(a0)
ld s1, ({hyp_s1})(a0)
ld a1, ({hyp_a1})(a0)
ld a2, ({hyp_a2})(a0)
ld a3, ({hyp_a3})(a0)
ld a4, ({hyp_a4})(a0)
ld a5, ({hyp_a5})(a0)
ld a6, ({hyp_a6})(a0)
ld a7, ({hyp_a7})(a0)
ld s2, ({hyp_s2})(a0)
ld s3, ({hyp_s3})(a0)
ld s4, ({hyp_s4})(a0)
ld s5, ({hyp_s5})(a0)
ld s6, ({hyp_s6})(a0)
ld s7, ({hyp_s7})(a0)
ld s8, ({hyp_s8})(a0)
ld s9, ({hyp_s9})(a0)
ld s10, ({hyp_s10})(a0)
ld s11, ({hyp_s11})(a0)
ld sp, ({hyp_sp})(a0)
ret
|
haourgot123/STM32-PROJECT
| 12,040
|
Servo/MDK-ARM/startup_stm32f103xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 1,912
|
Servo/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S
|
#if defined (__CC_ARM)
#if (defined (ARM_MATH_CM0))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_CM0P))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_CM3))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_CM4))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_CM7))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_ARMV8MBL))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_ARMV8MML))
#include "ARMCC\startup_armv7-m.s"
#else
#error "No appropriate startup file found!"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if (defined (ARM_MATH_CM0))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM0P))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM3))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM4))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM7))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_ARMV8MBL))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_ARMV8MML))
#include "ARMCLANG\startup_armv7-m.S"
#else
#error "No appropriate startup file found!"
#endif
#elif defined (__GNUC__)
#if (defined (ARM_MATH_CM0))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM0P))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM3))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM4))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM7))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_ARMV8MBL))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_ARMV8MML))
#include "GCC\startup_armv7-m.S"
#else
#error "No appropriate startup file found!"
#endif
#else
#error "Compiler not supported!"
#endif
|
haourgot123/STM32-PROJECT
| 7,083
|
Servo/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s
|
;/* File: startup_armv7-m.s
; * Purpose: startup file for armv7-m architecture devices.
; * Should be used with ARMCC
; * Version: V2.00
; * Date: 16 November 2015
; *
; */
;/* Copyright (c) 2011 - 2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
BKPT #0
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
BKPT #0
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
BKPT #0
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
BKPT #0
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
BKPT #0
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
;/*
; __user_setup_stackheap() returns the:
; - heap base in r0 (if the program uses the heap)
; - stack base in sp
; - heap limit in r2 (if the program uses the heap and uses two-region memory).
; */
EXPORT __user_setup_stackheap
__user_setup_stackheap PROC
LDR R0, = __initial_sp
MOV SP, R0
IF Heap_Size > 0
LDR R2, = __heap_limit
LDR R0, = __heap_base
ELSE
MOV R0, #0
MOV R2, #0
ENDIF
BX LR
ENDP
;/*
;__user_initial_stackheap() returns the:
; - heap base in r0
; - stack base in r1, that is, the highest address in the stack region
; - heap limit in r2
; - stack limit in r3, that is, the lowest address in the stack region.
; */
;
;/* DEPRICATED
; EXPORT __user_initial_stackheap
;
;__user_initial_stackheap PROC
; LDR R0, = Heap_Mem
; LDR R1, =(Stack_Mem + Stack_Size)
; LDR R2, = (Heap_Mem + Heap_Size)
; LDR R3, = Stack_Mem
; BX LR
; ENDP
; */
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 6,394
|
Servo/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s
|
;/* File: startup_armv6-m.s
; * Purpose: startup file for armv7-m architecture devices.
; * Should be used with ARMCC
; * Version: V2.00
; * Date: 16 November 2015
; *
; */
;/* Copyright (c) 2011 - 2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
BKPT #0
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
BKPT #0
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
;/*
; __user_setup_stackheap() returns the:
; - heap base in r0 (if the program uses the heap)
; - stack base in sp
; - heap limit in r2 (if the program uses the heap and uses two-region memory).
; */
EXPORT __user_setup_stackheap
__user_setup_stackheap PROC
LDR R0, = __initial_sp
MOV SP, R0
IF Heap_Size > 0
LDR R2, = __heap_limit
LDR R0, = __heap_base
ELSE
MOV R0, #0
MOV R2, #0
ENDIF
BX LR
ENDP
;/*
;__user_initial_stackheap() returns the:
; - heap base in r0
; - stack base in r1, that is, the highest address in the stack region
; - heap limit in r2
; - stack limit in r3, that is, the lowest address in the stack region.
; */
;
;/* DEPRICATED
; EXPORT __user_initial_stackheap
;
;__user_initial_stackheap PROC
; LDR R0, = Heap_Mem
; LDR R1, =(Stack_Mem + Stack_Size)
; LDR R2, = (Heap_Mem + Heap_Size)
; LDR R3, = Stack_Mem
; BX LR
; ENDP
; */
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 7,347
|
Servo/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S
|
/* File: startup_armv7-m.S
* Purpose: startup file for armv7-m architecture devices.
* Should be used with GCC for ARM Embedded Processors
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
bkpt #0
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
.end
|
haourgot123/STM32-PROJECT
| 7,290
|
Servo/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S
|
/* File: startup_armv6-m.S
* Purpose: startup file for armv6-m architecture devices.
* Should be used with GCC for ARM Embedded Processors
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
blt .L_loop0_0_done
ldr r0, [r1, r3]
str r0, [r2, r3]
b .L_loop0_0
.L_loop0_0_done:
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
blt .L_loop2_0_done
str r0, [r1, r2]
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
bkpt #0
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
.end
|
haourgot123/STM32-PROJECT
| 6,458
|
Servo/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S
|
/* File: startup_armv7-m.S
* Purpose: startup file for armv7-m architecture devices.
* Should be used with ARMCLANG
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv6-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section STACK, "w"
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
__StackTop: /* formerly known as __initial_sp */
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.section HEAP, "w"
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
__HeapLimit:
.section RESET, "x"
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.text
.thumb
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
.thumb_func
Reset_Handler:
bl SystemInit
bl __main
.globl NMI_Handler
.weak NMI_Handler
.type NMI_Handler, %function
.thumb_func
NMI_Handler:
bkpt #0
b .
.globl HardFault_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
.thumb_func
HardFault_Handler:
bkpt #0
b .
.globl MemManage_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
.thumb_func
MemManage_Handler:
bkpt #0
b .
.globl BusFault_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
.thumb_func
BusFault_Handler:
bkpt #0
b .
.globl UsageFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
.thumb_func
UsageFault_Handler:
bkpt #0
b .
.globl SVC_Handler
.weak SVC_Handler
.type SVC_Handler, %function
.thumb_func
SVC_Handler:
bkpt #0
b .
.globl DebugMon_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
.thumb_func
DebugMon_Handler:
bkpt #0
b .
.globl PendSV_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
.thumb_func
PendSV_Handler:
bkpt #0
b .
.globl SysTick_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
.thumb_func
SysTick_Handler:
bkpt #0
b .
.global __use_two_region_memory
/*
__user_setup_stackheap() returns the:
- heap base in r0 (if the program uses the heap)
- stack base in sp
- heap limit in r2 (if the program uses the heap and uses two-region memory).
*/
.globl __user_setup_stackheap
.type __user_setup_stackheap, %function
.thumb_func
__user_setup_stackheap:
ldr r0, =__StackTop
mov sp, r0
.if Heap_Size
ldr r0, =__HeapBase
ldr r2, =__HeapLimit
.else
mov r0, #0
mov r2, #0
.endif
bx lr
/*
__user_initial_stackheap() returns the:
- heap base in r0
- stack base in r1, that is, the highest address in the stack region
- heap limit in r2
- stack limit in r3, that is, the lowest address in the stack region.
*/
/* DEPRICATED
.globl __user_initial_stackheap
.type __user_initial_stackheap, %function
.thumb_func
__user_initial_stackheap:
ldr r0, = __HeapBase
ldr r1, = __StackTop
ldr r2, = __HeapLimit
ldr r3, = __StackLimit
bx lr
*/
.end
|
haourgot123/STM32-PROJECT
| 5,756
|
Servo/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S
|
/* File: startup_armv6-m.S
* Purpose: startup file for armv6-m architecture devices.
* Should be used with ARMCLANG
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv6-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section STACK, "w"
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
__StackTop: /* formerly known as __initial_sp */
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.section HEAP, "w"
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
__HeapLimit:
.section RESET, "x"
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.text
.thumb
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
.thumb_func
Reset_Handler:
bl SystemInit
bl __main
.globl NMI_Handler
.weak NMI_Handler
.type NMI_Handler, %function
.thumb_func
NMI_Handler:
bkpt #0
b .
.globl HardFault_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
.thumb_func
HardFault_Handler:
bkpt #0
b .
.globl SVC_Handler
.weak SVC_Handler
.type SVC_Handler, %function
.thumb_func
SVC_Handler:
bkpt #0
b .
.globl PendSV_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
.thumb_func
PendSV_Handler:
bkpt #0
b .
.globl SysTick_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
.thumb_func
SysTick_Handler:
bkpt #0
b .
.global __use_two_region_memory
/*
__user_setup_stackheap() returns the:
- heap base in r0 (if the program uses the heap)
- stack base in sp
- heap limit in r2 (if the program uses the heap and uses two-region memory).
*/
.globl __user_setup_stackheap
.type __user_setup_stackheap, %function
.thumb_func
__user_setup_stackheap:
ldr r0, =__StackTop
mov sp, r0
.if Heap_Size
ldr r0, =__HeapBase
ldr r2, =__HeapLimit
.else
mov r0, #0
mov r2, #0
.endif
bx lr
/*
__user_initial_stackheap() returns the:
- heap base in r0
- stack base in r1, that is, the highest address in the stack region
- heap limit in r2
- stack limit in r3, that is, the lowest address in the stack region.
*/
/* DEPRICATED
.globl __user_initial_stackheap
.type __user_initial_stackheap, %function
.thumb_func
__user_initial_stackheap:
ldr r0, = __HeapBase
ldr r1, = __StackTop
ldr r2, = __HeapLimit
ldr r3, = __StackLimit
bx lr
*/
.end
|
haourgot123/STM32-PROJECT
| 5,360
|
Servo/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S
|
;/* ----------------------------------------------------------------------
; * Project: CMSIS DSP Library
; * Title: arm_bitreversal2.S
; * Description: arm_bitreversal_32 function done in assembly for maximum speed.
; * Called after doing an fft to reorder the output.
; * The function is loop unrolled by 2. arm_bitreversal_16 as well.
; *
; * $Date: 27. January 2017
; * $Revision: V.1.5.1
; *
; * Target Processor: Cortex-M cores
; * -------------------------------------------------------------------- */
;/*
; * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
#if defined ( __CC_ARM ) /* Keil */
#define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
#define LABEL
#elif defined ( __IASMARM__ ) /* IAR */
#define CODESECT SECTION `.text`:CODE
#define PROC
#define LABEL
#define ENDP
#define EXPORT PUBLIC
#elif defined ( __CSMC__ ) /* Cosmic */
#define CODESECT switch .text
#define THUMB
#define EXPORT xdef
#define PROC :
#define LABEL :
#define ENDP
#define arm_bitreversal_32 _arm_bitreversal_32
#elif defined ( __TI_ARM__ ) /* TI ARM */
#define THUMB .thumb
#define CODESECT .text
#define EXPORT .global
#define PROC : .asmfunc
#define LABEL :
#define ENDP .endasmfunc
#define END
#elif defined ( __GNUC__ ) /* GCC */
#define THUMB .thumb
#define CODESECT .section .text
#define EXPORT .global
#define PROC :
#define LABEL :
#define ENDP
#define END
.syntax unified
#endif
CODESECT
THUMB
;/*
;* @brief In-place bit reversal function.
;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type.
;* @param[in] bitRevLen bit reversal table length
;* @param[in] *pBitRevTab points to bit reversal table.
;* @return none.
;*/
EXPORT arm_bitreversal_32
EXPORT arm_bitreversal_16
#if defined ( __CC_ARM ) /* Keil */
#elif defined ( __IASMARM__ ) /* IAR */
#elif defined ( __CSMC__ ) /* Cosmic */
#elif defined ( __TI_ARM__ ) /* TI ARM */
#elif defined ( __GNUC__ ) /* GCC */
.type arm_bitreversal_16, %function
.type arm_bitreversal_32, %function
#endif
#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS) || defined(ARM_MATH_ARMV8MBL)
arm_bitreversal_32 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_32_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
LDR r5,[r2,#4]
LDR r4,[r6,#4]
STR r5,[r6,#4]
STR r4,[r2,#4]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r6}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_16_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
LSRS r2,r2,#1
LSRS r6,r6,#1
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r6}
BX lr
ENDP
#else
arm_bitreversal_32 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8
ADD r9,r0,r9
ADD r2,r0,r2
ADD r12,r0,r12
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
LDR r7,[r9,#4]
LDR r6,[r8,#4]
LDR r5,[r2,#4]
LDR r4,[r12,#4]
STR r6,[r9,#4]
STR r7,[r8,#4]
STR r5,[r12,#4]
STR r4,[r2,#4]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r9}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8,LSR #1
ADD r9,r0,r9,LSR #1
ADD r2,r0,r2,LSR #1
ADD r12,r0,r12,LSR #1
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r9}
BX lr
ENDP
#endif
END
|
haourgot123/STM32-PROJECT
| 11,653
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f102xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f102xb.s
;* Author : MCD Application Team
;* Description : STM32F102xB USB Line Devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 13,220
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f100xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f100xb.s
;* Author : MCD Application Team
;* Description : STM32F100xB Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 16,265
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f105xc.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics *******************
;* File Name : startup_stm32f105xc.s
;* Author : MCD Application Team
;* Description : STM32F105xC Connectivity line devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 11,217
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f101xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f101xb.s
;* Author : MCD Application Team
;* Description : STM32F101xB Access Line Devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD 0 ; Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 16,290
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f107xc.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics *******************
;* File Name : startup_stm32f107xc.s
;* Author : MCD Application Team
;* Description : STM32F107xC Connectivity line devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 12,299
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103x6.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103x6.s
;* Author : MCD Application Team
;* Description : STM32F103x6 Performance Line Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 11,326
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f102x6.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f102x6.s
;* Author : MCD Application Team
;* Description : STM32F102x6 USB Line Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 10,886
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f101x6.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f101x6.s
;* Author : MCD Application Team
;* Description : STM32F101x6 Access Line Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD 0 ; Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 16,083
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103xg.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xg.s
;* Author : MCD Application Team
;* Description : STM32F103xG Performances Line Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR address,
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 14,777
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f101xg.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f101xg.s
;* Author : MCD Application Team
;* Description : STM32F101xG Access Line Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM9_IRQHandler ; TIM9
DCD TIM10_IRQHandler ; TIM10
DCD TIM11_IRQHandler ; TIM11
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD 0 ; Reserved
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FSMC_IRQHandler ; FSMC
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM9_IRQHandler
B TIM9_IRQHandler
PUBWEAK TIM10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM10_IRQHandler
B TIM10_IRQHandler
PUBWEAK TIM11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM11_IRQHandler
B TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK TIM12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM12_IRQHandler
B TIM12_IRQHandler
PUBWEAK TIM13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM13_IRQHandler
B TIM13_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 13,822
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f101xe.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f101xe.s
;* Author : MCD Application Team
;* Description : STM32F101xE Access Line Devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FSMC_IRQHandler ; FSMC
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 15,855
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103xe.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xe.s
;* Author : MCD Application Team
;* Description : STM32F103xE Performance Line Devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 12,568
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Performance Line Devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 15,214
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f100xe.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f100xe.s
;* Author : MCD Application Team
;* Description : STM32F100xE Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 if MISC_REMAP is not set
; or DMA2 Channel4 if MISC_REMAP is set
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 if MISC_REMAP is set
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM12_IRQHandler
B TIM12_IRQHandler
PUBWEAK TIM13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM13_IRQHandler
B TIM13_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
END
|
haourgot123/STM32-PROJECT
| 11,504
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f102xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f102xb.s
;* Author : MCD Application Team
;* Description : STM32F102xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
EXTI9_5_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 13,340
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f100xb.s
;* Author : MCD Application Team
;* Description : STM32F100xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 14,817
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f105xc.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f105xc.s
;* Author : MCD Application Team
;* Description : STM32F105xC Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 11,177
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f101xb.s
;* Author : MCD Application Team
;* Description : STM32F101xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 14,993
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f107xc.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f107xc.s
;* Author : MCD Application Team
;* Description : STM32F107xC Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 11,680
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103x6.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103x6.s
;* Author : MCD Application Team
;* Description : STM32F103x6 Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 11,129
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f102x6.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f102x6.s
;* Author : MCD Application Team
;* Description : STM32F102x6 Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
EXTI9_5_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 10,814
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101x6.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f101x6.s
;* Author : MCD Application Team
;* Description : STM32F101x6 Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 15,017
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xg.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xg.s
;* Author : MCD Application Team
;* Description : STM32F103xG Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 13,994
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xg.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f101xg.s
;* Author : MCD Application Team
;* Description : STM32F101xG Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM9_IRQHandler ; TIM9
DCD TIM10_IRQHandler ; TIM10
DCD TIM11_IRQHandler ; TIM11
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD 0 ; Reserved
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FSMC_IRQHandler ; FSMC
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM9_IRQHandler [WEAK]
EXPORT TIM10_IRQHandler [WEAK]
EXPORT TIM11_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM9_IRQHandler
TIM10_IRQHandler
TIM11_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
FSMC_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 13,251
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xe.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f101xe.s
;* Author : MCD Application Team
;* Description : STM32F101xE Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FSMC_IRQHandler ; FSMC
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
FSMC_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 14,563
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xe.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xe.s
;* Author : MCD Application Team
;* Description : STM32F103xE Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 12,055
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xb.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 14,897
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f100xe.s
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f100xe.s
;* Author : MCD Application Team
;* Description : STM32F100xE Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
haourgot123/STM32-PROJECT
| 9,099
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f102xb.s
|
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f102xb.s
* @author MCD Application Team
* @brief STM32F102xB Value Line Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
haourgot123/STM32-PROJECT
| 10,073
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f100xb.s
|
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f100xb.s
* @author MCD Application Team
* @brief STM32F100xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word CEC_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x01CC. This is for boot in RAM mode for
STM32F10xB Value Line devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
|
haourgot123/STM32-PROJECT
| 11,753
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f105xc.s
|
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f105xc.s
* @author MCD Application Team
* @brief STM32F105xC Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word OTG_FS_WKUP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word OTG_FS_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x Connectivity line Devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler ,Default_Handler
|
haourgot123/STM32-PROJECT
| 8,809
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f101xb.s
|
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f101xb.s
* @author MCD Application Team
* @brief STM32F101xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
haourgot123/STM32-PROJECT
| 12,008
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f107xc.s
|
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f107xc.s
* @author MCD Application Team
* @brief STM32F107xC Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word OTG_FS_WKUP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ETH_IRQHandler
.word ETH_WKUP_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word OTG_FS_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x Connectivity line Devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler ,Default_Handler
|
haourgot123/STM32-PROJECT
| 9,272
|
Servo/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103x6.s
|
/**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f103x6.s
* @author MCD Application Team
* @brief STM32F103x6 Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word 0
.word 0
.word SPI1_IRQHandler
.word 0
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Low Density devices.*/
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.