repo_id
stringlengths 5
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georgevio/IoT-Embedded
| 7,653
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_resize.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
.align 2
.text
.global dl_esp32p4_s8_resize_nearest_2x2_c1
.type dl_esp32p4_s8_resize_nearest_2x2_c1, @function
dl_esp32p4_s8_resize_nearest_2x2_c1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: output_x_offset
# a4: output_y_offset
# a5: c_div_x
# t3: remainder
# t4: output_shift
# t5: output_scale
lw a3, 20(a2)
lw a4, 24(a2)
lw a5, 40(a2)
lw t3, 44(a2)
lw t4, 48(a2)
lw t5, 52(a2)
# t6 (0, 1)
# s0 (1, 0)
# s1 (1, 1)
add t6, a0, a3
add s0, a0, a4
add s1, t6, a4
sb t5, 0(sp)
add s8, sp, x0
esp.vldbc.8.ip q1, s8, 0 # all output_scale
esp.vld.128.ip q0, a1, 16
add t0, a5, x0
blez t0, 1f
0:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp.srcmb.s8.qacc q2, t4, 1
esp.vst.128.ip q2, a0, 16
esp.vst.128.ip q2, t6, 16
esp.vst.128.ip q2, s0, 16
esp.vst.128.ip q2, s1, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.text
.align 2
.global dl_esp32p4_s8_resize_nearest_c1
.type dl_esp32p4_s8_resize_nearest_c1, @function
.balign 4
.option norvc
dl_esp32p4_s8_resize_nearest_c1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: c_div_x
# a4: output_shift
# a5: output_scale address
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 40(a2)
lw a4, 48(a2)
blez a3, dl_esp32p4_s8_resize_nearest_c1_end
addi a5, a2, 52
esp.vldbc.8.ip q1, a5, 0 // load output_scale
esp.vld.128.ip q0, a1, 16
dl_esp32p4_s8_resize_nearest_c1_loop:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp32p4_s8_128b_vector_shift_result q2, a4
esp32p4_s8_128b_aligned_vector_store q2, a0
addi a3, a3, -1
bgtz a3, dl_esp32p4_s8_resize_nearest_c1_loop
dl_esp32p4_s8_resize_nearest_c1_end:
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1
.type dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1, @function
dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: output_x_offset
# a4: output_y_offset
# a5: c_div_x
# t3: remainder
# t4: output_shift
# t5: output_scale
lw a3, 20(a2)
lw a4, 24(a2)
lw a5, 40(a2)
lw t3, 44(a2)
lw t4, 48(a2)
lw t5, 52(a2)
# t6 (0, 1)
# s0 (1, 0)
# s1 (1, 1)
add t6, a0, a3
add s0, a0, a4
add s1, t6, a4
sb t5, 0(sp)
add s8, sp, x0
esp.vldbc.8.ip q3, s8, 0 # all output_scale
esp.ld.128.usar.ip q0, a1, 16
add t0, a5, x0
blez t0, 1f
0:
esp.zero.qacc
esp.ld.128.usar.ip q1, a1, 16
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp.srcmb.s8.qacc q4, t4, 1
esp32p4_s8_32b_unaligned_vector_store q4, a0, s8
esp32p4_s8_32b_unaligned_vector_store q4, t6, s8
esp32p4_s8_32b_unaligned_vector_store q4, s0, s8
esp32p4_s8_32b_unaligned_vector_store q4, s1, s8
addi t0, t0, -1
bgtz t0, 0b
1:
bnez t3, dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1_remainder
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_unaligned_resize_nearest_2x2_c1_remainder:
esp.zero.qacc
esp.ld.128.usar.ip q1, a1, 16
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp.srcmb.s8.qacc q4, t4, 1
dl_esp32p4_s8_store_remainder q4, t4, t5, s8, s9, t0, a0, t3
dl_esp32p4_s8_store_remainder q4, t4, t5, s8, s9, t0, t6, t3
dl_esp32p4_s8_store_remainder q4, t4, t5, s8, s9, t0, s0, t3
dl_esp32p4_s8_store_remainder q4, t4, t5, s8, s9, t0, s1, t3
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_resize_nearest_c1
.type dl_esp32p4_s8_unaligned_resize_nearest_c1, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_resize_nearest_c1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: c_div_x / tmp value
# a4: output_shift
# a5: output_scale address
# t3: c_remainder
# t4: output_sar_byte / tmp value
# t5: tmp value
# t6:
# a6(not for extension instructions): tmp value
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 40(a2)
lw a4, 48(a2)
lw t3, 44(a2)
blez a3, dl_esp32p4_s8_unaligned_resize_nearest_c1_remainder
addi a5, a2, 52
esp.vldbc.8.ip q3, a5, 0 // load output_scale
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q2, a0, 0
esp.movx.r.sar.bytes t4 // output_sar_byte
beqz t4, dl_esp32p4_s8_unaligned_resize_nearest_c1_128b_loop
li a6, 8
beq t4, a6, dl_esp32p4_s8_unaligned_resize_nearest_c1_64b_loop
dl_esp32p4_s8_unaligned_resize_nearest_c1_32b_loop:
esp.ld.128.usar.ip q1, a1, 16
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp32p4_s8_128b_vector_shift_result q2, a4
esp32p4_s8_32b_unaligned_vector_store q2, a0, t4
addi a3, a3, -1
bgtz a3, dl_esp32p4_s8_unaligned_resize_nearest_c1_32b_loop
j dl_esp32p4_s8_unaligned_resize_nearest_c1_remainder
dl_esp32p4_s8_unaligned_resize_nearest_c1_64b_loop:
esp.ld.128.usar.ip q1, a1, 16
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp32p4_s8_128b_vector_shift_result q2, a4
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi a3, a3, -1
bgtz a3, dl_esp32p4_s8_unaligned_resize_nearest_c1_64b_loop
j dl_esp32p4_s8_unaligned_resize_nearest_c1_remainder
dl_esp32p4_s8_unaligned_resize_nearest_c1_128b_loop:
esp.ld.128.usar.ip q1, a1, 16
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp32p4_s8_128b_vector_shift_result q2, a4
esp32p4_s8_128b_aligned_vector_store q2, a0
addi a3, a3, -1
bgtz a3, dl_esp32p4_s8_unaligned_resize_nearest_c1_128b_loop
dl_esp32p4_s8_unaligned_resize_nearest_c1_remainder:
beqz t3, dl_esp32p4_s8_unaligned_resize_nearest_c1_end
esp.ld.128.usar.xp q1, a1, t3
esp.zero.qacc
esp.src.q q2, q0, q1
esp.vmulas.s8.qacc q2, q3
esp32p4_s8_128b_vector_shift_result q2, a4
dl_esp32p4_s8_store_remainder q2, a3, a5, t4, t5, a6, a0, t3
dl_esp32p4_s8_unaligned_resize_nearest_c1_end:
ret
|
georgevio/IoT-Embedded
| 40,868
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_add2d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s8_add2d_11c series
####
############################################################################################################################################################
.macro dl_esp32p4_rescale_add_rescale_output input0, input1, output, output_scale, output_shift
esp.zero.qacc
esp.vmulas.s8.qacc \input0, \output_scale
esp.vmulas.s8.qacc \input1, \output_scale
esp.srcmb.s8.qacc \output, \output_shift, 1
.endm
.align 2
.text
.global dl_esp32p4_s8_add2d_11c
.type dl_esp32p4_s8_add2d_11c, @function
#.section .iram1
dl_esp32p4_s8_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x_1
lw a4, 68(a3)
lw a5, 72(a3)
li t0, 1
blt a4, t0, dl_esp32p4_s8_add2d_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp.vadd.s8 q5, q2, q3
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vst.128.ip q5, a0, 16
esp.vadd.s8 q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_add2d_small_channel: # channel < 3*s (16)
add t0, a5, x0
blez t0, 1f
0:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_rescale_add2d_11c
.type dl_esp32p4_s8_rescale_add2d_11c, @function
#.section .iram1
dl_esp32p4_s8_rescale_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr: >> shift or *scale) >> shift
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_add2d_output
dl_esp32p4_s8_rescale_add2d_output_scale: # *scale) >> shift
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
add t0, a4, x0
blez t0, 1f
0:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_rescale_add2d_output: # >> shift
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 3f
2:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s8.qacc q1, t4, 1
esp.ldqa.s8.128.ip a2, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc q0, q7
esp.srcmb.s8.qacc q1, t4, 1
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_add2d_11c_relu
.type dl_esp32p4_s8_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s8_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x_1
# s8: activation_alpha
# s9: activation_shift
lw a4, 68(a3)
lw a5, 72(a3)
lw s8, 52(a3)
lw s9, 60(a3)
li t0, 1
blt a4, t0, dl_esp32p4_s8_add2d_relu_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s8 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vrelu.s8 q5, s8, s9
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s8 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp.vadd.s8 q5, q2, q3
esp.vrelu.s8 q5, s8, s9
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q2, a1, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s8 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vrelu.s8 q5, s8, s9
esp.vst.128.ip q5, a0, 16
esp.vadd.s8 q4, q0, q1
esp.vrelu.s8 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_add2d_relu_small_channel: # channel < 3*16byte
add t0, a5, x0
blez t0, 1f
0:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_rescale_add2d_11c_relu
.type dl_esp32p4_s8_rescale_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s8_rescale_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr: >> shift or *scale) >> shift
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
lw s8, 52(a3)
lw s9, 60(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_add2d_output_relu
dl_esp32p4_s8_rescale_add2d_output_scale_relu: # *scale) >> shift
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
add t0, a4, x0
blez t0, 1f
0:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vrelu.s8 q1, s8, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vrelu.s8 q1, s8, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_rescale_add2d_output_relu: # >> shift
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 1f
0:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s8.qacc q1, t4, 1
esp.vrelu.s8 q1, s8, s9
esp.ldqa.s8.128.ip a2, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc q0, q7
esp.srcmb.s8.qacc q1, t4, 1
esp.vrelu.s8 q1, s8, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_add2d_11c_prelu
.type dl_esp32p4_s8_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s8_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x_1
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 68(a3)
lw a5, 72(a3)
lw s8, 56(a3)
lw s9, 60(a3)
li t0, 1
blt a4, t0, dl_esp32p4_s8_add2d_prelu_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s8 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vprelu.s8 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s8 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q5, q2, q3
esp.vprelu.s8 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s8 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8.ld.incp q1, a2, q5, q2, q3
esp.vprelu.s8 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q4, q0, q1
esp.vprelu.s8 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_add2d_prelu_small_channel: # channel < 3*s
add t0, a5, x0
blez t0, 1f
0:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q3, s8, 16
esp.vadd.s8 q2, q0, q1
esp.vprelu.s8 q2, q2, q3, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q3, s8, 16
esp.vadd.s8 q2, q0, q1
esp.vprelu.s8 q2, q2, q3, s9
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_rescale_add2d_11c_prelu
.type dl_esp32p4_s8_rescale_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s8_rescale_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr: >> shift or *scale) >> shift
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
lw s8, 56(a3)
lw s9, 60(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_add2d_output_prelu
dl_esp32p4_s8_rescale_add2d_output_scale_prelu: # *scale) >> shift
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
add t0, a4, x0
blez t0, 1f
0:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
esp.vld.128.ip q5, s8, 16
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vprelu.s8 q1, q1, q5, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s8.qacc q1, a5, 1
esp.vld.128.ip q5, s8, 16
dl_esp32p4_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vprelu.s8 q1, q1, q5, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_rescale_add2d_output_prelu: # >> shift
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
esp.ldqa.s8.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 1f
0:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q1, t4, 1
esp.vprelu.s8 q1, q1, q6, s9
esp.ldqa.s8.128.ip a2, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.srcmb.s8.qacc q1, a5, 1
esp.vmulas.s8.qacc q0, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q1, t4, 1
esp.vprelu.s8 q1, q1, q6, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
############################################################################################################################################################
####
#### esp32p4_s8_unaligned_add2d_11c series
####
############################################################################################################################################################
.align 2
.text
.global dl_esp32p4_s8_unaligned_add2d_11c
.type dl_esp32p4_s8_unaligned_add2d_11c, @function
#.section .iram1
dl_esp32p4_s8_unaligned_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_unaligned_add2d_11c_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_unaligned_add2d_11c_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_unaligned_add2d_11c_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_unaligned_add2d_11c_remainder
#output sar = 0
dl_esp32p4_s8_unaligned_add2d_11c_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_unaligned_add2d_11c_remainder
# #output sar = 8
dl_esp32p4_s8_unaligned_add2d_11c_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_unaligned_add2d_11c_remainder
dl_esp32p4_s8_unaligned_add2d_11c_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_unaligned_add2d_11c_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vadd.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s8_unaligned_rescale_add2d_11c:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_unaligned_add2d_output_shift
### rescaled to output by *scale) >> shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_scale:
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_scale_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_scale_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_scale_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_scale_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_shift:
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_shift_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_shift_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_shift_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_shift_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
# esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
dl_esp32p4_s8_store_remainder q5, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_add2d_11c_relu
.type dl_esp32p4_s8_unaligned_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s8_unaligned_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
lw s8, 52(a3)
lw s9, 60(a3)
bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c_relu
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_unaligned_add2d_11c_relu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_unaligned_add2d_11c_relu_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_unaligned_add2d_11c_relu_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_unaligned_add2d_11c_relu_remainder
#output sar = 0
dl_esp32p4_s8_unaligned_add2d_11c_relu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_unaligned_add2d_11c_relu_remainder
# #output sar = 8
dl_esp32p4_s8_unaligned_add2d_11c_relu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_unaligned_add2d_11c_relu_remainder
dl_esp32p4_s8_unaligned_add2d_11c_relu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_unaligned_add2d_11c_relu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_relu_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vrelu.s8 q2, s8, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_relu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s8_unaligned_rescale_add2d_11c_relu:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_unaligned_add2d_output_shift_relu
### rescaled to output by *scale) >> shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_scale_relu:
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_scale_relu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_scale_relu_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_scale_relu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_scale_relu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_relu_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vrelu.s8 q2, s8, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_relu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_shift_relu:
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_shift_relu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q5, s8, s9
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.vrelu.s8 q5, s8, s9
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_shift_relu_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_shift_relu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_shift_relu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_relu_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.vrelu.s8 q5, s8, s9
# esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
dl_esp32p4_s8_store_remainder q5, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_relu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_add2d_11c_prelu
.type dl_esp32p4_s8_unaligned_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s8_unaligned_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
lw s8, 56(a3)
lw s9, 60(a3)
bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c_prelu
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_unaligned_add2d_11c_prelu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_unaligned_add2d_11c_prelu_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_unaligned_add2d_11c_prelu_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q2, q2, q5
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_unaligned_add2d_11c_prelu_remainder
#output sar = 0
dl_esp32p4_s8_unaligned_add2d_11c_prelu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q2, q2, q5
esp.vprelu.s8 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_unaligned_add2d_11c_prelu_remainder
# #output sar = 8
dl_esp32p4_s8_unaligned_add2d_11c_prelu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q2, q2, q5
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_unaligned_add2d_11c_prelu_remainder
dl_esp32p4_s8_unaligned_add2d_11c_prelu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_unaligned_add2d_11c_prelu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_prelu_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s8 q2, q2, q5
esp.vprelu.s8 q2, q2, q6, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_prelu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s8_unaligned_rescale_add2d_11c_prelu:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s8_rescale_unaligned_add2d_output_shift_prelu
### rescaled to output by *scale) >> shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_scale_prelu:
sb t3, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_scale_prelu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
esp.vld.128.ip q6, s8, 16
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_scale_prelu_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_scale_prelu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_scale_prelu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_prelu_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q1, a5, 1
esp.vld.128.ip q6, s8, 16
dl_esp32p4_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vprelu.s8 q2, q2, q6, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s0
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_scale_prelu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s8_rescale_unaligned_add2d_output_shift_prelu:
li s1, 1
sb s1, 0(sp)
add s11, sp, x0
esp.vldbc.8.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s8_rescale_unaligned_add2d_shift_prelu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.srcmb.s8.qacc q5, t4, 1
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q5, q5, q6, s9
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q5, t4, 1
esp.vprelu.s8 q5, q5, q6, s9
esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
j dl_esp32p4_s8_rescale_unaligned_add2d_shift_prelu_remainder
dl_esp32p4_s8_rescale_unaligned_add2d_shift_prelu_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s8_rescale_unaligned_add2d_shift_prelu_remainder:
beqz t5, dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_prelu_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s8.qacc q5
esp.srcmb.s8.qacc q5, a5, 1
esp.vmulas.s8.qacc q2, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q5, t4, 1
esp.vprelu.s8 q5, q5, q6, s9
# esp32p4_s8_32b_unaligned_vector_store q5, a0, s1
dl_esp32p4_s8_store_remainder q5, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_rescale_add2d_output_shift_prelu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 7,815
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_requantize_linear.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
.text
.align 2
.global dl_esp32p4_s8_s8_requantize_linear
.type dl_esp32p4_s8_s8_requantize_linear, @function
.balign 4
.option norvc
dl_esp32p4_s8_s8_requantize_linear:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: size_div_x / tmp value
# a4: in_size_remainder
# a5: tmp value
# t3: output_shift / tmp value
# t4: output_scale / tmp value
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 8(a2) // size_div_x
lw a4, 12(a2) // in_size_remainder
lw t3, 20(a2) // output_shift
lw t4, 24(a2) // output_scale
bgtz t4, esp32p4_s8_s8_requantize_linear_left_shift
beqz a3, esp32p4_s8_s8_requantize_linear_right_shift_remainder
esp32p4_s8_s8_requantize_linear_right_shift_loop:
esp.ldqa.s8.128.ip a1, 16
addi a3, a3, -1
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
bnez a3, esp32p4_s8_s8_requantize_linear_right_shift_loop
esp32p4_s8_s8_requantize_linear_right_shift_remainder:
beqz a4, esp32p4_s8_s8_requantize_linear_end
esp.ldqa.s8.128.xp a1, a4
esp32p4_s8_128b_vector_shift_result q0, t3
dl_esp32p4_s8_store_remainder q0, a3, a5, t3, t4, t0, a0, a4
j esp32p4_s8_s8_requantize_linear_end
esp32p4_s8_s8_requantize_linear_left_shift:
addi t4, a2, 24
esp.vldbc.16.ip q2, t4, 0 // load output_scale
beqz a3, esp32p4_s8_s8_requantize_linear_left_shift_remainder
esp32p4_s8_s8_requantize_linear_left_shift_loop:
esp.vldext.s8.ip q0, q1, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
esp.vst.128.ip q0, a0, 16
addi a3, a3, -1
bnez a3, esp32p4_s8_s8_requantize_linear_left_shift_loop
esp32p4_s8_s8_requantize_linear_left_shift_remainder:
beqz a4, esp32p4_s8_s8_requantize_linear_end
esp.vldext.s8.xp q0, q1, a1, a4
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a5, t3, t4, t0, a0, a4
esp32p4_s8_s8_requantize_linear_end:
ret
.text
.align 2
.global dl_esp32p4_s8_s16_requantize_linear
.type dl_esp32p4_s8_s16_requantize_linear, @function
.balign 4
.option norvc
dl_esp32p4_s8_s16_requantize_linear:
# a0: int8_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: size_div_x / tmp value
# a4: in_size_remainder / tmp value
# a5: out_size_remainder
# t3: output_shift / tmp value
# t4: output_scale / tmp value
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 8(a2) // size_div_x
lw a4, 12(a2) // in_size_remainder
lw a5, 16(a2) // out_size_remainder
lw t3, 20(a2) // output_shift
lw t4, 24(a2) // output_scale
bgtz t4, esp32p4_s8_s16_requantize_linear_left_shift
beqz a3, esp32p4_s8_s16_requantize_linear_right_shift_remainder
esp32p4_s8_s16_requantize_linear_right_shift_loop:
esp.ldqa.s16.128.ip a1, 16
esp32p4_s8_128b_vector_shift_result q0, t3
esp.ldqa.s16.128.ip a1, 16
addi a3, a3, -1
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
esp.vst.128.ip q0, a0, 16
bnez a3, esp32p4_s8_s16_requantize_linear_right_shift_loop
esp32p4_s8_s16_requantize_linear_right_shift_remainder:
beqz a5, esp32p4_s8_s16_requantize_linear_end
li t0, 8
ble a5, t0, esp32p4_s8_s16_requantize_linear_right_shift_remainder_le8
esp.ldqa.s16.128.ip a1, 16
esp32p4_s8_128b_vector_shift_result q0, t3
esp.ldqa.s16.128.xp a1, a4
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a4, t3, t4, t0, a0, a5
j esp32p4_s8_s16_requantize_linear_end
esp32p4_s8_s16_requantize_linear_right_shift_remainder_le8:
esp.ldqa.s16.128.xp a1, a4
esp.zero.q q1
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a4, t3, t4, t0, a0, a5
j esp32p4_s8_s16_requantize_linear_end
esp32p4_s8_s16_requantize_linear_left_shift:
addi t4, a2, 24
esp.vldbc.16.ip q2, t4, 0 // load output_scale
beqz a3, esp32p4_s8_s16_requantize_linear_left_shift_remainder
esp32p4_s8_s16_requantize_linear_left_shift_loop:
esp.vld.128.ip q0, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vld.128.ip q1, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
esp.vst.128.ip q0, a0, 16
addi a3, a3, -1
bnez a3, esp32p4_s8_s16_requantize_linear_left_shift_loop
esp32p4_s8_s16_requantize_linear_left_shift_remainder:
beqz a5, esp32p4_s8_s16_requantize_linear_end
li t0, 8
ble a5, t0, esp32p4_s8_s16_requantize_linear_left_shift_remainder_le8
esp.vld.128.ip q0, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vld.128.xp q1, a1, a4
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s8_128b_vector_shift_result q1, t3
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a4, t3, t4, t0, a0, a5
j esp32p4_s8_s16_requantize_linear_end
esp32p4_s8_s16_requantize_linear_left_shift_remainder_le8:
esp.vld.128.xp q0, a1, a4
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s8_128b_vector_shift_result q0, t3
esp.zero.q q1
esp.vunzip.8 q0, q1
dl_esp32p4_s8_store_remainder q0, a3, a4, t3, t4, t0, a0, a5
esp32p4_s8_s16_requantize_linear_end:
ret
|
georgevio/IoT-Embedded
| 15,550
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_greater.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_greater_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greater_w1_16_w2_16
.type dl_esp32p4_s8_greater_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_16_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
esp32p4_s8_greater_w1_16_w2_16_loop:
beq t0, a3, esp32p4_s8_greater_w1_16_w2_16_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greater_w1_16_w2_16_loop
esp32p4_s8_greater_w1_16_w2_16_end:
ret
#void dl_esp32p4_s8_greater_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greater_w1_16_w2_1
.type dl_esp32p4_s8_greater_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_16_w2_1:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s8_greater_w1_16_w2_1_loop:
beq t0, a3, esp32p4_s8_greater_w1_16_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greater_w1_16_w2_1_loop
esp32p4_s8_greater_w1_16_w2_1_end:
ret
#void dl_esp32p4_s8_greater_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greater_w1_1_w2_16
.type dl_esp32p4_s8_greater_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_1_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s8_greater_w1_1_w2_16_loop:
beq t0, a3, esp32p4_s8_greater_w1_1_w2_16_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greater_w1_1_w2_16_loop
esp32p4_s8_greater_w1_1_w2_16_end:
ret
.align 2
.text
.global dl_esp32p4_s8_greater_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_greater_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greater_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_greater_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_greater_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s8 q2, q2, q5
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greater_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_greater_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_greater_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s8 q2, q5, q2
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greater_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,525
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_xor4d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor
.type dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor
.type dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.8.ip q1, a2, 0
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor
.type dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.8.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned
.type dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_remainder
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_16_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.xorq q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned
.type dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_remainder
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a2, 0
dl_esp32p4_s8_xor4d_bchw_w1_16_w2_1_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned
.type dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a2: int8_t *input0_ptr
# a1: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.xorq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.xorq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.xorq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_remainder
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a1, 0
dl_esp32p4_s8_xor4d_bchw_w1_1_w2_16_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end___
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end___:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 3,750
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_prelu.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
.align 2
.text
.global dl_esp32p4_s8_prelu_11c
.type dl_esp32p4_s8_prelu_11c, @function
dl_esp32p4_s8_prelu_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: c_div_x = n_div_x
# s0: activation_alpha_ptr
# s1: activation_shift
# s8: output_shift
# s9: output_scale
lw a3, 96(a2) # n_div_x
lw s0, 80(a2) # activation_alpha_ptr
lw s1, 84(a2) # activation_shift
lw s8, 172(a2) # output_shift
lw s9, 176(a2) # output_scale
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, s0, 16
esp.zero.q q2 # all 0
addi a5, a2, 176
esp.vldbc.8.ip q3, a5, 0 # all output_scale
add t0, a3, x0
blez t0, 1f
0:
# neg part, alpha * input, right shift: output - alpha - input
esp.vprelu.s8 q4, q0, q1, s1
esp.vcmp.lt.s8 q6, q0, q2
esp.andq q4, q4, q6
# pos part, *scale, right shift: output - input
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q1, s0, 16, q0, q3
esp.srcmb.s8.qacc q5, s8, 1
esp.vcmp.gt.s8 q6, q0, q2
esp.andq q5, q5, q6
esp.vadd.s8.ld.incp q0, a1, q4, q4, q5
esp.vst.128.ip q4, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_prelu_11c
.type dl_esp32p4_s8_unaligned_prelu_11c, @function
dl_esp32p4_s8_unaligned_prelu_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: c_div_x = n_div_x
# a4: c_remainder
# s0: activation_alpha_ptr
# s1: activation_shift
# s8: output_shift
# s9: output_scale
lw a3, 96(a2) # c_div_x
lw a4, 136(a2) # c_remainder
lw s0, 80(a2) # activation_alpha_ptr
lw s1, 84(a2) # activation_shift
lw s8, 172(a2) # output_shift
lw s9, 176(a2) # output_scale
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q1, s0, 16
addi a5, a2, 176
esp.vldbc.8.ip q7, a5, 0 # all output_scale
add t0, a3, x0
blez t0, 1f
0:
esp.ld.128.usar.ip q2, a1, 16
esp.src.q.qup q4, q0, q2
esp.ld.128.usar.ip q3, s0, 16
esp.src.q.qup q5, q1, q3
# neg part, alpha * input, right shift: output - alpha - input
esp.vprelu.s8 q5, q4, q5, s1
esp.zero.q q2
esp.vcmp.lt.s8 q6, q4, q2
esp.andq q5, q5, q6
# pos part, *scale, right shift: output - input
esp.zero.qacc
esp.vmulas.s8.qacc q4, q7
esp.srcmb.s8.qacc q3, s8, 1
esp.vcmp.gt.s8 q6, q4, q2
esp.andq q3, q3, q6
esp.vadd.s8 q3, q3, q5
esp32p4_s8_32b_unaligned_vector_store q3, a0, t3
addi t0, t0, -1
bgtz t0, 0b
1:
bnez a4, dl_esp32p4_s8_unaligned_prelu_remainder
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_unaligned_prelu_remainder:
esp.ld.128.usar.ip q2, a1, 16
esp.src.q.qup q4, q0, q2
esp.ld.128.usar.ip q3, s0, 16
esp.src.q.qup q5, q1, q3
# neg part, alpha * input, right shift: output - alpha - input
esp.vprelu.s8 q5, q4, q5, s1
esp.zero.q q2
esp.vcmp.lt.s8 q6, q4, q2
esp.andq q5, q5, q6
# pos part, *scale, right shift: output - input
esp.zero.qacc
esp.vmulas.s8.qacc q4, q7
esp.srcmb.s8.qacc q3, s8, 1
esp.vcmp.gt.s8 q6, q4, q2
esp.andq q3, q3, q6
esp.vadd.s8 q3, q3, q5
dl_esp32p4_s8_store_remainder q3, a1, a2, a3, a5, a6, a0, a4
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 7,923
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8.S
|
############################################################################################################################################################
# result process for conv2d / depthwise_conv2d
############################################################################################################################################################
.macro esp32p4_s8_conv2d_128b_vector_bias bias_ptr
esp.ld.qacc.l.l.128.ip \bias_ptr, 16
esp.ld.qacc.l.h.128.ip \bias_ptr, 16
esp.ld.qacc.h.l.128.ip \bias_ptr, 16
esp.ld.qacc.h.h.128.ip \bias_ptr, 16
.endm
.macro esp32p4_s8_conv2d_element_bias bias_ptr, tmp
lw \tmp, 0(\bias_ptr)
addi \bias_ptr, \bias_ptr, 4
esp.movx.w.xacc.l \tmp
slti \tmp, \tmp, 0 // if tmp < 0, tmp = 1, otherwise tmp = 0
slli \tmp, \tmp, 31 // shift left to the sign bit.
srai \tmp, \tmp, 31 // extend the sign bit to all bits.
esp.movx.w.xacc.h \tmp
.endm
############################################################################################################################################################
# esp32p4_s8_32b_unaligned_vector series
############################################################################################################################################################
.macro esp32p4_s8_32b_unaligned_vector_store output_v, output_ptr, tmp
esp.movi.32.a \output_v, \tmp, 0
sw \tmp, 0(\output_ptr)
esp.movi.32.a \output_v, \tmp, 1
sw \tmp, 4(\output_ptr)
esp.movi.32.a \output_v, \tmp, 2
sw \tmp, 8(\output_ptr)
esp.movi.32.a \output_v, \tmp, 3
sw \tmp, 12(\output_ptr)
addi \output_ptr, \output_ptr, 16
.endm
############################################################################################################################################################
# esp32p4_s8_64b_unaligned_vector series
############################################################################################################################################################
.macro esp32p4_s8_64b_unaligned_vector_store output_v, output_ptr
esp.vst.l.64.ip \output_v, \output_ptr, 8
esp.vst.h.64.ip \output_v, \output_ptr, 8
.endm
############################################################################################################################################################
# esp32p4_s8_128b_vector series
############################################################################################################################################################
.macro esp32p4_s8_128b_vector_shift_result output_v, mac_shift
esp.srcmb.s8.qacc \output_v, \mac_shift, 1
.endm
.macro esp32p4_s8_128b_aligned_vector_store output_v, output_ptr
esp.vst.128.ip \output_v, \output_ptr, 16
.endm
.macro esp32p4_s8_128b_vector_relu output_v, activation_alpha, activation_shift
# LeakyReLU
esp.vrelu.s8 \output_v, \activation_alpha, \activation_shift
.endm
.macro esp32p4_s8_128b_vector_prelu output_v, activation_alpha_v, activation_alpha_ptr, activation_shift
esp.vld.128.ip \activation_alpha_v, \activation_alpha_ptr, 16
esp.vprelu.s8 \output_v, \output_v, \activation_alpha_v, \activation_shift
.endm
.macro dl_esp32p4_s8_last_store_data tmp_q, output_v, tmp_a, c_remainder_bytes
movi \tmp_a, 15
sub \tmp_a, \tmp_a, \c_remainder_bytes
movi \c_remainder_bytes, 0
esp.slcxxp.2q \tmp_q, \output_v, \tmp_a, \c_remainder_bytes #left shift to make the rest part 0
esp.srcxxp.2q \output_v, \tmp_q, \tmp_a, \c_remainder_bytes #right shift to lower bits
.endm
.macro dl_esp32p4_s8_store_remainder output_v, tmp_a0, tmp_a1, tmp_a2, tmp_a3, tmp_a4, output_ptr, remainder_c
esp.movi.32.a \output_v, \tmp_a0, 0
615: # remainder_c == 15, 0x1111
andi \tmp_a4, \remainder_c, 8
beqz \tmp_a4, 607f
esp.movi.32.a \output_v, \tmp_a1, 1
andi \tmp_a4, \remainder_c, 4
beqz \tmp_a4, 611f
esp.movi.32.a \output_v, \tmp_a2, 2
andi \tmp_a4, \remainder_c, 2
beqz \tmp_a4, 613f
esp.movi.32.a \output_v, \tmp_a3, 3
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 614f
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sw \tmp_a2, 8(\output_ptr)
sh \tmp_a3, 12(\output_ptr)
srai \tmp_a3, \tmp_a3, 16
sb \tmp_a3, 14(\output_ptr)
j 616f
614: # remainder_c == 14, 0x1110
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sw \tmp_a2, 8(\output_ptr)
sh \tmp_a3, 12(\output_ptr)
j 616f
613: # remainder_c == 13, 0x1101
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 612f
esp.movi.32.a \output_v, \tmp_a3, 3
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sw \tmp_a2, 8(\output_ptr)
sb \tmp_a3, 12(\output_ptr)
j 616f
612: # remainder_c == 12, 0x1100
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sw \tmp_a2, 8(\output_ptr)
j 616f
611: # remainder_c == 11, 0x1011
andi \tmp_a4, \remainder_c, 2
beqz \tmp_a4, 609f
esp.movi.32.a \output_v, \tmp_a2, 2
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 610f
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sh \tmp_a2, 8(\output_ptr)
srai \tmp_a2, \tmp_a2, 16
sb \tmp_a2, 10(\output_ptr)
j 616f
610: # remainder_c == 10, 0x1010
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sh \tmp_a2, 8(\output_ptr)
j 616f
609: # remainder_c == 9, 0x1001
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 608f
esp.movi.32.a \output_v, \tmp_a2, 2
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
sb \tmp_a2, 8(\output_ptr)
j 616f
608: # remainder_c == 8, 0x1000
sw \tmp_a0, 0(\output_ptr)
sw \tmp_a1, 4(\output_ptr)
j 616f
607: # remainder == 7, 0x111
andi \tmp_a4, \remainder_c, 4
beqz \tmp_a4, 603f
andi \tmp_a4, \remainder_c, 2
beqz \tmp_a4, 605f
esp.movi.32.a \output_v, \tmp_a1, 1
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 606f
sw \tmp_a0, 0(\output_ptr)
sh \tmp_a1, 4(\output_ptr)
srai \tmp_a1, \tmp_a1, 16
sb \tmp_a1, 6(\output_ptr)
j 616f
606: # remainder == 6, 0x110
sw \tmp_a0, 0(\output_ptr)
sh \tmp_a1, 4(\output_ptr)
j 616f
605: # remainder == 4, 5
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 604f
# remainder == 5, 0x101
esp.movi.32.a \output_v, \tmp_a1, 1
sw \tmp_a0, 0(\output_ptr)
sb \tmp_a1, 4(\output_ptr)
j 616f
604: # remainder == 4, 0x100
sw \tmp_a0, 0(\output_ptr)
j 616f
603: # remainder == 1, 2, 3
andi \tmp_a4, \remainder_c, 2
beqz \tmp_a4, 601f
andi \tmp_a4, \remainder_c, 1
beqz \tmp_a4, 602f
# remainder == 3, 0x011
sh \tmp_a0, 0(\output_ptr)
srai \tmp_a0, \tmp_a0, 16
sb \tmp_a0, 2(\output_ptr)
j 616f
602: # remainder == 2, 0x010
sh \tmp_a0, 0(\output_ptr)
j 616f
601: # remainder == 1, 0x001
sb \tmp_a0, 0(\output_ptr)
616:
.endm
############################################################################################################################################################
# esp32p4_s8_element series
############################################################################################################################################################
.macro esp32p4_s8_element_result output, mac_shift
esp.srs.s.xacc \output, \mac_shift
.endm
.macro esp32p4_s8_element_store output_ptr, output
sb \output, 0(\output_ptr)
addi \output_ptr, \output_ptr, 1
.endm
.macro esp32p4_s8_element_leakyrelu output, alpha, shift
bgez \output, 0f
mul \output, \output, \alpha
sra \output, \output, \shift
0:
.endm
.macro esp32p4_s8_element_prelu output, alpha_ptr, shift
bgez \output, 0f
mul \output, \output, \alpha_ptr
sra \output, \output, \shift
addi \alpha_ptr, \alpha_ptr, 1
0:
.endm
|
georgevio/IoT-Embedded
| 15,882
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_greaterorequal.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_greaterorequal_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_8_w2_8
.type dl_esp32p4_s16_greaterorequal_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_8_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
esp32p4_s16_greaterorequal_w1_8_w2_8_loop:
beq t0, a3, esp32p4_s16_greaterorequal_w1_8_w2_8_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greaterorequal_w1_8_w2_8_loop
esp32p4_s16_greaterorequal_w1_8_w2_8_end:
ret
#void dl_esp32p4_s16_greaterorequal_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_8_w2_1
.type dl_esp32p4_s16_greaterorequal_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_8_w2_1:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s16_greaterorequal_w1_8_w2_1_loop:
beq t0, a3, esp32p4_s16_greaterorequal_w1_8_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greaterorequal_w1_8_w2_1_loop
esp32p4_s16_greaterorequal_w1_8_w2_1_end:
ret
#void dl_esp32p4_s16_greaterorequal_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_1_w2_8
.type dl_esp32p4_s16_greaterorequal_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_1_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s16_greaterorequal_w1_1_w2_8_loop:
beq t0, a3, esp32p4_s16_greaterorequal_w1_1_w2_8_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greaterorequal_w1_1_w2_8_loop
esp32p4_s16_greaterorequal_w1_1_w2_8_end:
ret
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
// esp.vst.128.ip q2, a0, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greaterorequal_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greaterorequal_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greaterorequal_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 32,480
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_depthwise_conv2d.S
|
#include "dl_esp32p4_s8.S"
############################################################################################################################################################
####
#### esp32p4_s8_depthwise_conv2d_33c1 series
####
############################################################################################################################################################
.macro esp32p4_s8_depthwise_conv2d_33s1 input_v0 filter_v0 input_v1 filter_v1 input_v2 filter_v2 input_ptr filter_ptr dilation_x_offset dilation_y_offset next_33s1
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_33s1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \next_33s1
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
.endm
.macro esp32p4_s8_depthwise_conv2d_33s1_last input_v0 filter_v0 input_v1 filter_v1 input_ptr filter_ptr dilation_x_offset dilation_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.ip \input_v0, \input_ptr, 0
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
# block one cycle here
esp.vmulas.s8.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s8_depthwise_conv2d_33c1_load_args args filter_ptr dilation_x_offset dilation_y_offset next_hwx1 c_div_x_1 mac_shift
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hwx1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
lw \filter_ptr, 48(\args)
lw \dilation_x_offset, 124(\args)
lw \dilation_y_offset, 128(\args)
lw \next_hwx1, 132(\args)
lw \c_div_x_1, 100(\args)
lw \mac_shift, 64 (\args)
.endm
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_bias
.type dl_esp32p4_s8_depthwise_conv2d_33c1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw t6, 68(a2) // bias
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_bias_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_bias_loop_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp.vst.128.ip q3, a0, 16
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_bias_relu
.type dl_esp32p4_s8_depthwise_conv2d_33c1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw t6, 68(a2) // bias
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_bias_relu_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_relu q3, s0, s1
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_bias_relu_loop_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_relu q3, s0, s1
esp.vst.128.ip q3, a0, 16
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_bias_prelu
.type dl_esp32p4_s8_depthwise_conv2d_33c1_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw t6, 68(a2) // bias
lw s0, 80(a2) // activation_alpha_ptr
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_bias_prelu_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_prelu q3, q4, s0, s1
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_bias_prelu_loop_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_prelu q3, q4, s0, s1
esp.vst.128.ip q3, a0, 16
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1
.type dl_esp32p4_s8_depthwise_conv2d_33c1, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_loop_last:
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp.vst.128.ip q3, a0, 16
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_relu
.type dl_esp32p4_s8_depthwise_conv2d_33c1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_relu_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_relu q3, s0, s1
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_relu_loop_last:
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_relu q3, s0, s1
esp.vst.128.ip q3, a0, 16
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_33c1_prelu
.type dl_esp32p4_s8_depthwise_conv2d_33c1_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_33c1_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_33s1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t4, t5
lw s0, 80(a2) // activation_alpha_ptr
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t4, esp32p4_s8_depthwise_conv2d_33c1_prelu_loop_last
# lp.setup 0, t4, 1f
esp.lp.setup 0, t4, 1f
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_prelu q3, q4, s0, s1
1: esp.vst.128.ip q3, a0, 16
esp32p4_s8_depthwise_conv2d_33c1_prelu_loop_last:
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s8_128b_vector_shift_result q3, t5
esp32p4_s8_128b_vector_prelu q3, q4, s0, s1
esp.vst.128.ip q3, a0, 16
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
############################################################################################################################################################
####
#### esp32p4_s8_depthwise_conv2d_hwc1 series
####
############################################################################################################################################################
.macro esp32p4_s8_depthwise_conv2d_1ws1 input_v0, input_v1, input_v2, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, tmp_value, filter_w, filter_w_rs1_1, filter_y_offset
beqz \filter_w_rs1_1, 1f
# lp.setup 0, \filter_w_rs1_1, 0f
esp.lp.setup 0, \filter_w_rs1_1, 0f
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
0: esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
1:
andi \tmp_value, \filter_w, 0xFFFFFFFE
beq \tmp_value, \filter_w, 2f
# three 8-input-element left
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.xp \filter_v2, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
j 3f
2: # two 8-input-element left
esp.vmulas.s8.qacc.ld.xp \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \dilation_y_offset
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
3:
.endm
.macro esp32p4_s8_depthwise_conv2d_1ws1_last input_v0, input_v1, filter_v0, filter_v1, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, tmp_value, filter_w, filter_w_rs1_1, next_hws1, filter_y_offset
beqz \filter_w_rs1_1, 5f
# lp.setup 0, \filter_w_rs1_1, 4f
esp.lp.setup 0, \filter_w_rs1_1, 4f
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
4: esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
5:
andi \tmp_value, \filter_w, 0xFFFFFFFE
beq \tmp_value, \filter_w, 6f
# three 8-input-element left
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \next_hws1
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
# block one cyle here
esp.vmulas.s8.qacc \input_v0, \filter_v0
j 7f
6: # two 8-input-element left
esp.vmulas.s8.qacc.ld.xp \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \next_hws1
esp.vmulas.s8.qacc \input_v1, \filter_v1
7:
.endm
.macro esp32p4_s8_depthwise_conv2d_hws1 input_v0, input_v1, input_v2, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, next_hws1, filter_h, filter_w, filter_w_rs1_1, args, filter_offset_q, filter_y_offset, tmp_value
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hws1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
# filter_w_rs1_1
lw \filter_h, 52(\args) # filter_height
addi \tmp_value, \filter_w, -1
beqz \tmp_value, 10f
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
addi \filter_h, \filter_h, -1
beqz \filter_h, 9f
// lp.setup 1, \filter_h, 8f
// 8: esp32p4_s8_depthwise_conv2d_1ws1 \input_v0, \input_v1, \input_v2, \filter_v0, \filter_v1, \filter_v2, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \tmp_value, \filter_w, \filter_w_rs1_1, \filter_y_offset
8:
esp32p4_s8_depthwise_conv2d_1ws1 \input_v0, \input_v1, \input_v2, \filter_v0, \filter_v1, \filter_v2, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \tmp_value, \filter_w, \filter_w_rs1_1, \filter_y_offset
addi \filter_h, \filter_h, -1
bgtz \filter_h, 8b
9: # last y
esp32p4_s8_depthwise_conv2d_1ws1_last \input_v0, \input_v1, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \tmp_value, \filter_w, \filter_w_rs1_1, \next_hws1, \filter_y_offset
j 13f
10: # filter_w == 1
esp.vld.128.xp \filter_v0, \filter_ptr, \filter_y_offset
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
beqz \filter_h, 12f
// lp.setup 1, \filter_h, 11f
// esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
// 11: esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
11:
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bgtz \filter_h, 11b
12: # last y
esp.vmulas.s8.qacc \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset
add \input_ptr, \input_ptr, \next_hws1
13:
esp.movi.32.a \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.macro esp32p4_s8_depthwise_conv2d_hwc1_load_args args, filter_ptr, dilation_x_offset, dilation_y_offset, next_hws1, c_div_x_1, mac_shift, filter_w, filter_w_rs1_1
esp32p4_s8_depthwise_conv2d_33c1_load_args \args, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \next_hws1, \c_div_x_1, \mac_shift
lw \filter_w, 56(\args)
lw \filter_w_rs1_1, 148(\args)
.endm
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_bias
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset
# s10:
# s11: tmp_value
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s11, 0(sp)
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s0, 2
lw t6, 68(a2) // bias
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_bias_loop:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_bias_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s11, 0(sp) // restore s11
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_relu
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset / activation_alpha
# s10: activation_shift
# s11: tmp_value
addi sp, sp, -24
sw s0, 20(sp)
sw s1, 16(sp)
sw s8, 12(sp)
sw s9, 8(sp)
sw s10, 4(sp)
sw s11, 0(sp)
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp.movi.32.q q7, s9, 3
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s9, 1
esp.movi.32.q q7, s0, 2
lw t6, 68(a2) // bias
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_bias_relu_loop:
esp.zero.qacc
esp.movi.32.a q7, s9, 1 // filter_y_offset
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.movi.32.a q7, s9, 3 // activation_alpha
esp32p4_s8_128b_vector_relu q0, s9, s10
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_bias_relu_loop
lw s0, 20(sp) // restore s0
lw s1, 16(sp) // restore s1
lw s8, 12(sp) // restore s8
lw s9, 8(sp) // restore s9
lw s10, 4(sp) // restore s10
lw s11, 0(sp) // restore s11
addi sp, sp, 24
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6: bias_ptr
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset / activation_alpha
# s10: activation_shift
# s11: tmp_value
addi sp, sp, -24
sw s0, 20(sp)
sw s1, 16(sp)
sw s8, 12(sp)
sw s9, 8(sp)
sw s10, 4(sp)
sw s11, 0(sp)
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp.movi.32.q q7, s9, 3
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s9, 1
esp.movi.32.q q7, s0, 2
lw t6, 68(a2) // bias
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu_loop:
esp.zero.qacc
esp.movi.32.a q7, s9, 1 // filter_y_offset
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.movi.32.a q7, s9, 3 // activation_alpha_ptr
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_bias_prelu_loop
lw s0, 20(sp) // restore s0
lw s1, 16(sp) // restore s1
lw s8, 12(sp) // restore s8
lw s9, 8(sp) // restore s9
lw s10, 4(sp) // restore s10
lw s11, 0(sp) // restore s11
addi sp, sp, 24
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1
.type dl_esp32p4_s8_depthwise_conv2d_hwc1, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset
# s10:
# s11: tmp_value
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s11, 0(sp)
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s0, 2
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_loop:
esp.zero.qacc
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s11, 0(sp) // restore s11
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_relu
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset / activation_alpha
# s10: activation_shift
# s11: tmp_value
addi sp, sp, -24
sw s0, 20(sp)
sw s1, 16(sp)
sw s8, 12(sp)
sw s9, 8(sp)
sw s10, 4(sp)
sw s11, 0(sp)
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp.movi.32.q q7, s9, 3
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s9, 1
esp.movi.32.q q7, s0, 2
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_relu_loop:
esp.zero.qacc
esp.movi.32.a q7, s9, 1 // filter_y_offset
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.movi.32.a q7, s9, 3 // activation_alpha
esp32p4_s8_128b_vector_relu q0, s9, s10
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_relu_loop
lw s0, 20(sp) // restore s0
lw s1, 16(sp) // restore s1
lw s8, 12(sp) // restore s8
lw s9, 8(sp) // restore s9
lw s10, 4(sp) // restore s10
lw s11, 0(sp) // restore s11
addi sp, sp, 24
ret
.text
.align 2
.global dl_esp32p4_s8_depthwise_conv2d_hwc1_prelu
.type dl_esp32p4_s8_depthwise_conv2d_hwc1_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_depthwise_conv2d_hwc1_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hws1
# t4: c_div_x_1
# t5: mac_shift
# t6:
# s0: filter_h / filter_n_offset
# s1: filter_w
# s8: filter_w_rs1_1
# s9: filter_y_offset / activation_alpha
# s10: activation_shift
# s11: tmp_value
addi sp, sp, -24
sw s0, 20(sp)
sw s1, 16(sp)
sw s8, 12(sp)
sw s9, 8(sp)
sw s10, 4(sp)
sw s11, 0(sp)
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp.movi.32.q q7, s9, 3
lw s9, 60(a2) // filter_y_offset
lw s0, 144(a2) // filter_n_offset
esp.movi.32.q q7, s9, 1
esp.movi.32.q q7, s0, 2
esp32p4_s8_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t4, t5, s1, s8
esp32p4_s8_depthwise_conv2d_hwc1_prelu_loop:
esp.zero.qacc
esp.movi.32.a q7, s9, 1 // filter_y_offset
esp32p4_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, s0, s1, s8, a2, q7, s9, s11
esp32p4_s8_128b_vector_shift_result q0, t5
esp.movi.32.a q7, s9, 3 // activation_alpha_ptr
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp.vst.128.ip q0, a0, 16
addi t4, t4, -1
bgez t4, esp32p4_s8_depthwise_conv2d_hwc1_prelu_loop
lw s0, 20(sp) // restore s0
lw s1, 16(sp) // restore s1
lw s8, 12(sp) // restore s8
lw s9, 8(sp) // restore s9
lw s10, 4(sp) // restore s10
lw s11, 0(sp) // restore s11
addi sp, sp, 24
ret
|
georgevio/IoT-Embedded
| 33,602
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_conv2d.S
|
#include "dl_esp32p4_s8.S"
############################################################################################################################################################
####
#### esp32p4_s8_conv2d_11cn series
####
############################################################################################################################################################
.macro esp32p4_s8_conv2d_11c16 input_v0 input_ptr filter_v0 filter_v1 filter_ptr c_div_x_1
# scalar * vecter and accumulate into QACC
# input_ptr += (c_div_x_1 + 1) * 16 in the end
# filter_ptr point to the next 16 bytes in the end
# input_v0: 16 input elements
# filter_v0: 16 filter elements
# filter_v1: 16 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 16 - 1
esp.vld.128.ip \input_v0, \input_ptr, 16
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.ip \filter_v1, \filter_ptr, 16
beqz \c_div_x_1, 1f
# lp.setup 0, \c_div_x_1, 0f
esp.lp.setup 0, \c_div_x_1, 0f
# 0:
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 14
esp.vsmulas.s8.qacc.ld.incp \input_v0, \input_ptr, \filter_v1, \input_v0, 15
0: esp.vld.128.ip \filter_v1, \filter_ptr, 16
# addi \c_div_x_1, \c_div_x_1, -1
# bgtz \c_div_x_1, 0b
1:
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 14
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 15
.endm
############################################################################################################################################################
####
#### esp32p4_s8_conv2d_11cn
####
############################################################################################################################################################
.macro esp32p4_s8_conv2d_11cn_load_args args filter_ptr c_div_x_1 n_rs3 mac_shift
lw \n_rs3, 96(\args) // output_channel_div_8
lw \mac_shift, 64(\args) // mac_shift
lw \filter_ptr, 48(\args) // filter
lw \c_div_x_1, 100(\args) // input_channel / x - 1
.endm
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_bias
.type dl_esp32p4_s8_conv2d_11cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
# Because the subsequent esp.lp.setup loop instruction compares for a value >= 0 and cannot be negative, we subtract 1 in advance here.
# addi a4, a4, -1
lw t4, 68(a2) // bias
esp32p4_s8_conv2d_11cn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_bias_loop
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_bias_relu
.type dl_esp32p4_s8_conv2d_11cn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
lw t4, 68(a2) // bias
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp32p4_s8_conv2d_11cn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, s0, s1
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_bias_relu_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_bias_prelu
.type dl_esp32p4_s8_conv2d_11cn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
lw t4, 68(a2) // bias
lw s0, 80(a2) // activation_alpha_ptr
lw s1, 84(a2) // activation_shift
esp32p4_s8_conv2d_11cn_bias_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, s0, s1
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_bias_prelu_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn
.type dl_esp32p4_s8_conv2d_11cn, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
# Because the subsequent esp.lp.setup loop instruction compares for a value >= 0 and cannot be negative, we subtract 1 in advance here.
# addi a4, a4, -1
esp32p4_s8_conv2d_11cn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_loop
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_relu
.type dl_esp32p4_s8_conv2d_11cn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp32p4_s8_conv2d_11cn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, s0, s1
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_relu_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_11cn_prelu
.type dl_esp32p4_s8_conv2d_11cn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_11cn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_11cn_load_args a2, a3, a4, a5, t3
lw s0, 80(a2) // activation_alpha_ptr
lw s1, 84(a2) // activation_shift
esp32p4_s8_conv2d_11cn_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_11c16 q0, t5, q1, q2, a3, a4
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, s0, s1
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_11cn_prelu_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
############################################################################################################################################################
####
#### esp32p4_s8_conv2d_33cn series
####
############################################################################################################################################################
.macro esp32p4_s8_conv2d_33c16 input_v0 filter_v0 filter_v1 input_ptr filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro esp32p4_s8_conv2d_hwcn_load_args args filter_ptr c_div_x_1 n_rs3 mac_shift dilation_x_offset dilation_y_offset
esp32p4_s8_conv2d_11cn_load_args \args, \filter_ptr, \c_div_x_1, \n_rs3, \mac_shift
lw \dilation_x_offset, 108(\args) // input dilation x offset
lw \dilation_y_offset, 112(\args) // input dilation y offset
.endm
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_bias
.type dl_esp32p4_s8_conv2d_33cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
esp32p4_s8_conv2d_33cn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_bias_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_bias_relu
.type dl_esp32p4_s8_conv2d_33cn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: activation_alpha/_address
# s9: activation_shift
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw s8, 76(a2) // activation_alpha
lw s9, 84(a2) // activation_shift
esp32p4_s8_conv2d_33cn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, s8, s9
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_bias_relu_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_bias_prelu
.type dl_esp32p4_s8_conv2d_33cn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: activation_alpha/_address
# s9: activation_shift
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw s8, 80(a2) // activation_alpha_ptr
lw s9, 84(a2) // activation_shift
esp32p4_s8_conv2d_33cn_bias_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, s8, s9
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_bias_prelu_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn
.type dl_esp32p4_s8_conv2d_33cn, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8:
# s9:
# s10:
# s11:
addi sp, sp, -8
sw s0, 4(sp)
sw s1, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
esp32p4_s8_conv2d_33cn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_loop
lw s0, 4(sp) // restore s0
lw s1, 0(sp) // restore s1
addi sp, sp, 8
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_relu
.type dl_esp32p4_s8_conv2d_33cn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: activation_alpha/_address
# s9: activation_shift
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw s8, 76(a2) // activation_alpha
lw s9, 84(a2) // activation_shift
esp32p4_s8_conv2d_33cn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, s8, s9
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_relu_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_33cn_prelu
.type dl_esp32p4_s8_conv2d_33cn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_33cn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: activation_alpha/_address
# s9: activation_shift
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw s8, 80(a2) // activation_alpha_ptr
lw s9, 84(a2) // activation_shift
esp32p4_s8_conv2d_33cn_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_33c16 q0, q1, q2, t5, a3, a4, s0, s1
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, s8, s9
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_33cn_prelu_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
############################################################################################################################################################
####
#### esp32p4_s8_conv2d_hwcn series
####
############################################################################################################################################################
.macro esp32p4_s8_conv2d_hwc16 input_v0 filter_v0 filter_v1 input_ptr filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset filter_h filter_w args filter_offset_q
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
# filter_h
# filter_w
lw \filter_h, 52(\args) # filter_height
2:
lw \filter_w, 56(\args) # filter_width
addi \filter_w, \filter_w, -1
beqz \filter_w, 4f
// lp.setup 1, \filter_w, 3f
// esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
// 3: add \input_ptr, \input_ptr, \dilation_x_offset
3:
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bgtz \filter_w, 3b
4:
esp32p4_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
esp.movi.32.a \filter_offset_q, \filter_w, 1
add \filter_ptr, \filter_ptr, \filter_w
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 2b
esp.movi.32.a \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_bias
.type dl_esp32p4_s8_conv2d_hwcn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_bias_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_bias_relu
.type dl_esp32p4_s8_conv2d_hwcn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6: activation_alpha/_address
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10: activation_shift
# s11:
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s10, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw t6, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, t6, s10
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_bias_relu_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s10, 0(sp) // restore s10
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_bias_prelu
.type dl_esp32p4_s8_conv2d_hwcn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4: bias_ptr
# t5: moving_input_ptr
# t6: activation_alpha/_address
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10: activation_shift
# s11:
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s10, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t4, 68(a2) // bias
lw t6, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_bias_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t4
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, t6, s10
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_bias_prelu_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s10, 0(sp) // restore s10
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn
.type dl_esp32p4_s8_conv2d_hwcn, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6:
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10:
# s11:
addi sp, sp, -16
sw s0, 12(sp)
sw s1, 8(sp)
sw s8, 4(sp)
sw s9, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_loop
lw s0, 12(sp) // restore s0
lw s1, 8(sp) // restore s1
lw s8, 4(sp) // restore s8
lw s9, 0(sp) // restore s9
addi sp, sp, 16
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_relu
.type dl_esp32p4_s8_conv2d_hwcn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6: activation_alpha/_address
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10: activation_shift
# s11:
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s10, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t6, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_relu q0, t6, s10
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_relu_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s10, 0(sp) // restore s10
addi sp, sp, 20
ret
.text
.align 2
.global dl_esp32p4_s8_conv2d_hwcn_prelu
.type dl_esp32p4_s8_conv2d_hwcn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_conv2d_hwcn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_div_x_1
# a5: n_rs3
# t3: mac_shift
# t4:
# t5: moving_input_ptr
# t6: activation_alpha/_address
# s0: input dilation x offset
# s1: input dilation y offset
# s8: filter_height
# s9: filter_width
# s10: activation_shift
# s11:
addi sp, sp, -20
sw s0, 16(sp)
sw s1, 12(sp)
sw s8, 8(sp)
sw s9, 4(sp)
sw s10, 0(sp)
esp32p4_s8_conv2d_hwcn_load_args a2, a3, a4, a5, t3, s0, s1
lw t6, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
lw s9, 60(a2) // filter_y_offset
lw s8, 144(a2)
esp.movi.32.q q6, s9, 1 // filter_y_offset
esp.movi.32.q q6, s8, 2 // filter_n_offset
esp32p4_s8_conv2d_hwcn_prelu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_hwc16 q0, q1, q2, t5, a3, a4, s0, s1, s8, s9, a2, q6
esp32p4_s8_128b_vector_shift_result q0, t3
esp32p4_s8_128b_vector_prelu q0, q1, t6, s10
esp.vst.128.ip q0, a0, 16
addi a5, a5, -1
bnez a5, esp32p4_s8_conv2d_hwcn_prelu_loop
lw s0, 16(sp) // restore s0
lw s1, 12(sp) // restore s1
lw s8, 8(sp) // restore s8
lw s9, 4(sp) // restore s9
lw s10, 0(sp) // restore s10
addi sp, sp, 20
ret
|
georgevio/IoT-Embedded
| 39,676
|
esp-idf/3-Level-Cloud/esp32-s3-websocket_server/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_add2d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s16_add2d_11c series
####
############################################################################################################################################################
.macro dl_esp32p4_s16_rescale_add_rescale_output input0, input1, output, output_scale, output_shift
esp.zero.qacc
esp.vmulas.s16.qacc \input0, \output_scale
esp.vmulas.s16.qacc \input1, \output_scale
esp.srcmb.s16.qacc \output, \output_shift, 1
.endm
.align 2
.text
.global dl_esp32p4_s16_add2d_11c
.type dl_esp32p4_s16_add2d_11c, @function
#.section .iram1
dl_esp32p4_s16_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x_1
lw a4, 68(a3)
lw a5, 72(a3)
li t0, 1
blt a4, t0, dl_esp32p4_s16_add2d_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q2, a1, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vst.128.ip q4, a0, 16
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vadd.s16 q5, q2, q3
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q0, a1, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vst.128.ip q5, a0, 16
esp.vadd.s16 q4, q0, q1
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_add2d_small_channel:
bltz a5, 5f
add t0, a5, x0
blez t0, 3f
2:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_rescale_add2d_11c
.type dl_esp32p4_s16_rescale_add2d_11c, @function
#.section .iram1
dl_esp32p4_s16_rescale_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_add2d_output
dl_esp32p4_s16_rescale_add2d_output_scale:
sh t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
# addi a4, a4, 1
add t0, a4, x0
blez t0, 3f
2:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_rescale_add2d_output:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 5f
4:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.ldqa.s16.128.ip a2, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 4b
5:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_add2d_11c_relu
.type dl_esp32p4_s16_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s16_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x
# s8: activation_alpha
# s9: activation_shift
lw a4, 68(a3)
lw a5, 72(a3)
lw s8, 52(a3)
lw s9, 60(a3)
beqz a4, dl_esp32p4_s16_add2d_relu_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s16 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vrelu.s16 q5, s8, s9
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q2, a1, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vrelu.s16 q4, s8, s9
esp.vst.128.ip q4, a0, 16
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vadd.s16 q5, q2, q3
esp.vrelu.s16 q5, s8, s9
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q0, a1, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vrelu.s16 q5, s8, s9
esp.vst.128.ip q5, a0, 16
esp.vadd.s16 q4, q0, q1
esp.vrelu.s16 q4, s8, s9
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_add2d_relu_small_channel:
bltz a5, 5f
add t0, a5, x0
blez t0, 3f
2:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vrelu.s16 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vrelu.s16 q2, s8, s9
esp.vst.128.ip q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_rescale_add2d_11c_relu
.type dl_esp32p4_s16_rescale_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s16_rescale_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
lw s8, 52(a3)
lw s9, 60(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_add2d_output_relu
dl_esp32p4_s16_rescale_add2d_output_scale_relu:
sh t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
add t0, a4, x0
blez t0, 3f
2:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vrelu.s16 q1, s8, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vrelu.s16 q1, s8, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_rescale_add2d_output_relu:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 5f
4:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.ldqa.s16.128.ip a2, 16
esp.vrelu.s16 q1, s8, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 4b
5:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.vrelu.s16 q1, s8, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_add2d_11c_prelu
.type dl_esp32p4_s16_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s16_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_2x_1
# a5: c_left_x
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 68(a3)
lw a5, 72(a3)
lw s8, 56(a3)
lw s9, 60(a3)
beqz a4, dl_esp32p4_s16_add2d_prelu_small_channel
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s16 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vprelu.s16 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vld.128.ip q2, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16.ld.incp q3, a2, q4, q0, q1
esp.vprelu.s16 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
li t0, 1
beq a5, t0, 2f #remainder == 2*16byte
li t0, 2
beq a5, t0, 3f #remainder == 3*16byte
2:
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q5, q2, q3
esp.vprelu.s16 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
3:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16.ld.incp q1, a2, q5, q2, q3
esp.vprelu.s16 q5, q5, q6, s9
esp.vst.128.ip q5, a0, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q4, q0, q1
esp.vprelu.s16 q4, q4, q6, s9
esp.vst.128.ip q4, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_add2d_prelu_small_channel:
bltz a5, 5f
add t0, a5, x0
blez t0, 3f
2:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q0, q1
esp.vprelu.s16 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q0, q1
esp.vprelu.s16 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_rescale_add2d_11c_prelu
.type dl_esp32p4_s16_rescale_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s16_rescale_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw a5, 88(a3)
lw t3, 96(a3)
lw t4, 92(a3)
lw s8, 56(a3)
lw s9, 60(a3)
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_add2d_output_prelu
dl_esp32p4_s16_rescale_add2d_output_scale_prelu:
sh t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
# addi a4, a4, 1
add t0, a4, x0
blez t0, 3f
2:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vld.128.ip q5, s8, 16
esp.vprelu.s16 q1, q1, q5, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q0, q1, q1, q7, t4
esp.vld.128.ip q5, s8, 16
esp.vprelu.s16 q1, q1, q5, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s16_rescale_add2d_output_prelu:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
esp.ldqa.s16.128.ip a2, 16
esp.vld.128.ip q0, a1, 16
add t0, a4, x0
blez t0, 5f
4:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc.ld.ip q0, a1, 16, q0, q7
esp.srcmb.s16.qacc q1, t4, 1
esp.vld.128.ip q6, s8, 16
esp.ldqa.s16.128.ip a2, 16
esp.vprelu.s16 q1, q1, q6, s9
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 4b
5:
esp.srcmb.s16.qacc q1, a5, 1
esp.vmulas.s16.qacc q0, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s16.qacc q1, t4, 1
esp.vprelu.s16 q1, q1, q6, s9
esp.vst.128.ip q1, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
############################################################################################################################################################
####
#### esp32p4_s16_unaligned_add2d_11c series
####
############################################################################################################################################################
.align 2
.text
.global dl_esp32p4_s16_unaligned_add2d_11c
.type dl_esp32p4_s16_unaligned_add2d_11c, @function
#.section .iram1
dl_esp32p4_s16_unaligned_add2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_unaligned_add2d_11c_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_unaligned_add2d_11c_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_unaligned_add2d_11c_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_unaligned_add2d_11c_remainder
#output sar = 0
dl_esp32p4_s16_unaligned_add2d_11c_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_unaligned_add2d_11c_remainder
#output sar = 8
dl_esp32p4_s16_unaligned_add2d_11c_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_unaligned_add2d_11c_remainder
dl_esp32p4_s16_unaligned_add2d_11c_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_unaligned_add2d_11c_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vadd.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s16_unaligned_rescale_add2d_11c:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_unaligned_add2d_output_shift
### rescaled to output by *scale) >> shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_scale:
sw t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder
dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s0, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_shift:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder
dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q5, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_unaligned_add2d_11c_relu
.type dl_esp32p4_s16_unaligned_add2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s16_unaligned_add2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
lw s8, 52(a3)
lw s9, 60(a3)
bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c_relu
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_unaligned_add2d_11c_small_remainder_relu # channel < 8
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_unaligned_add2d_11c_relu_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_unaligned_add2d_11c_relu_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_relu
#output sar = 0
dl_esp32p4_s16_unaligned_add2d_11c_relu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vrelu.s16 q2, s8, s9
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_relu
#output sar = 8
dl_esp32p4_s16_unaligned_add2d_11c_relu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_relu
dl_esp32p4_s16_unaligned_add2d_11c_small_remainder_relu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_unaligned_add2d_11c_remainder_relu:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end_relu
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vrelu.s16 q2, s8, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end_relu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s16_unaligned_rescale_add2d_11c_relu:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_unaligned_add2d_output_shift_relu
### rescaled to output by *scale) >> shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_scale_relu:
sw t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder_relu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vrelu.s16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder_relu
dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder_relu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder_relu:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end_relu # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vrelu.s16 q2, s8, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end_relu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_shift_relu:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder_relu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s16 q5, s8, s9
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.vrelu.s16 q5, s8, s9
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder_relu
dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder_relu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder_relu:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end_relu # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.vrelu.s16 q5, s8, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q5, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end_relu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_unaligned_add2d_11c_prelu
.type dl_esp32p4_s16_unaligned_add2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s16_unaligned_add2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw t5, 76(a3)
lw a5, 88(a3)
lw s8, 56(a3)
lw s9, 60(a3)
bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c_prelu
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_unaligned_add2d_11c_small_remainder_prelu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_unaligned_add2d_11c_prelu_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_unaligned_add2d_11c_prelu_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q2, q5
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_prelu
#output sar = 0
dl_esp32p4_s16_unaligned_add2d_11c_prelu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q2, q5
esp.vprelu.s16 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_prelu
#output sar = 8
dl_esp32p4_s16_unaligned_add2d_11c_prelu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q2, q5
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_unaligned_add2d_11c_remainder_prelu
dl_esp32p4_s16_unaligned_add2d_11c_small_remainder_prelu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_unaligned_add2d_11c_remainder_prelu:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end_prelu
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vld.128.ip q6, s8, 16
esp.vadd.s16 q2, q2, q5
esp.vprelu.s16 q2, q2, q6, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end_prelu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
## rescaled add
dl_esp32p4_s16_unaligned_rescale_add2d_11c_prelu:
lw t3, 96(a3) # output_scale
lw t4, 92(a3) # output_shift
li t0, 1
beq t3, t0, dl_esp32p4_s16_rescale_unaligned_add2d_output_shift_prelu
### rescaled to output by *scale) >> shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_scale_prelu:
sw t3, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all output_scale
# ssr t4 #output shift
# li s1, 0
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder_prelu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 7f
6:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s0
addi t0, t0, -1
bgtz t0, 6b
7:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
esp.vld.128.ip q6, s8, 16
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vprelu.s16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder_prelu
dl_esp32p4_s16_rescale_unaligned_add2d_scale_small_remainder_prelu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_scale_remainder_prelu:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end_prelu # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q1, a5, 1
esp.vld.128.ip q6, s8, 16
dl_esp32p4_s16_rescale_add_rescale_output q2, q1, q2, q7, t4
esp.vprelu.s16 q2, q2, q6, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_scale_end_prelu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
### rescaled to output by right shift
dl_esp32p4_s16_rescale_unaligned_add2d_output_shift_prelu:
li s1, 1
sh s1, 0(sp)
add s11, sp, x0
esp.vldbc.16.ip q7, s11, 0 # all 1
bltz a4, dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder_prelu # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
add t0, a4, x0
blez t0, 9f
8:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.srcmb.s16.qacc q5, t4, 1
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s16 q5, q5, q6, s9
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
addi t0, t0, -1
bgtz t0, 8b
9:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s16.qacc q5, t4, 1
esp.vprelu.s16 q5, q5, q6, s9
dl_esp32p4_128b_unaligned_store0 q5, a0, s1
j dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder_prelu
dl_esp32p4_s16_rescale_unaligned_add2d_shift_small_remainder_prelu:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6 #input0 sar
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0 #input1 sar
dl_esp32p4_s16_rescale_unaligned_add2d_shift_remainder_prelu:
beqz t5, dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end_prelu # c remainder
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.mov.s16.qacc q5
esp.srcmb.s16.qacc q5, a5, 1
esp.vmulas.s16.qacc q2, q7
esp.vld.128.ip q6, s8, 16
esp.srcmb.s16.qacc q5, t4, 1
esp.vprelu.s16 q5, q5, q6, s9
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q5, t5, s1, a0
dl_esp32p4_s16_unaligned_rescale_add2d_output_shift_end_prelu:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 2,187
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/tool/isa/tie728/dl_tie728_memcpy.S
|
.align 4
.text
.global dl_tie728_memcpy
.type dl_tie728_memcpy, @function
.section .iram1
dl_tie728_memcpy:
.align 4
entry sp, 32
# a2: store_ptr
# a3: load_ptr
# a4: length(bytes)
EE.LD.128.USAR.IP q0, a3, 0
RUR.SAR_BYTE a13
movi a11, 16
sub a11, a11, a13 # head unaligned bytes 1
EE.LD.128.USAR.IP q1, a2, 0
RUR.SAR_BYTE a9
movi a12, 16
sub a12, a12, a9 # head unaligned bytes 2
beqi a12, 16, 11f
min a12, a12, a4
srli a13, a12, 2
slli a14, a13, 2
sub a14, a12, a14
loopgtz a13, 9f
l32i a5, a3, 0
addi a3, a3, 4
s32i a5, a2, 0
addi a2, a2, 4
9:
loopgtz a14, 10f
l8ui a5, a3, 0
addi a3, a3, 1
s8i a5, a2, 0
addi a2, a2, 1
10:
sub a4, a4, a12
EE.LD.128.USAR.IP q0, a3, 0
RUR.SAR_BYTE a13
11:
beqz a13, 1f
srli a5, a4, 4 # len // 16
slli a6, a5, 4
sub a6, a4, a6 # remainder
srli a7, a5, 1 # len // 32
slli a8, a7, 1
sub a8, a5, a8 # odd_flag
srli a9, a6, 2 #remainder_4b
slli a10, a9, 2
sub a10, a6, a10 #remainder_1b
loopgtz a7, 12f
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.LD.128.USAR.IP q2, a3, 0
EE.SRC.Q q0, q0, q1
EE.SRC.Q q1, q1, q2
EE.VST.128.IP q0, a2, 16
EE.VST.128.IP q1, a2, 16
12:
beqz a8, 3f
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q1, a3, 0
EE.SRC.Q q0, q0, q1
EE.VST.128.IP q0, a2, 16
bnez a8, 3f
1:
srli a5, a4, 4 # len // 16
slli a6, a5, 4
sub a6, a4, a6 # remainder
srli a7, a5, 1 # len // 32
slli a8, a7, 1
sub a8, a5, a8 # odd_flag
srli a9, a6, 2 #remainder_4b
slli a10, a9, 2
sub a10, a6, a10 #remainder_1b
loopgtz a7, 2f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a3, 16
EE.VST.128.IP q0, a2, 16
EE.VST.128.IP q1, a2, 16
2:
beqz a8, 3f
EE.VLD.128.IP q0, a3, 16
EE.VST.128.IP q0, a2, 16
3:
loopgtz a9, 4f
l32i a5, a3, 0
addi a3, a3, 4
s32i a5, a2, 0
addi a2, a2, 4
4:
loopgtz a10, 5f
l8ui a5, a3, 0
addi a3, a3, 1
s8i a5, a2, 0
addi a2, a2, 1
5:
retw
|
georgevio/IoT-Embedded
| 2,647
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/tool/isa/tie728/dl_tie728_memset.S
|
.align 4
.text
.global dl_tie728_memset_8b
.type dl_tie728_memset_8b, @function
.section .iram1
dl_tie728_memset_8b:
.align 4
entry sp, 32
# a2: input_ptr
# a3: value
# a4: length(n)
s8i a3, a1, 0 // store to stack
mov a7, a1
EE.VLDBC.8 q0, a7
EE.LD.128.USAR.IP q1, a2, 0
RUR.SAR_BYTE a10
beqz a10, 2f
movi a11, 16
sub a11, a11, a10 # head unaligned bytes
min a11, a11, a4
loopgtz a11, 1f
s8i a3, a2, 0
addi a2, a2, 1
1:
sub a4, a4, a11
blti a4, 1, 4f
2:
srli a5, a4, 4 # len // 16
slli a6, a5, 4
sub a6, a4, a6 # remainder
loopgtz a5, 3f
EE.VST.128.IP q0, a2, 16
3:
loopgtz a6, 4f
s8i a3, a2, 0
addi a2, a2, 1
4:
retw
.align 4
.text
.global dl_tie728_memset_16b
.type dl_tie728_memset_16b, @function
.section .iram1
dl_tie728_memset_16b:
.align 4
entry sp, 32
# a2: input_ptr
# a3: value_ptr
# a4: length(n)
s16i a3, a1, 0 // store to stack
mov a7, a1
EE.VLDBC.16 q0, a7
EE.LD.128.USAR.IP q1, a2, 0
RUR.SAR_BYTE a10
beqz a10, 2f
movi a11, 16
sub a11, a11, a10 # head unaligned bytes
movi a8, 2
rems a9, a11, a8
beqz a9, 0f
loopgtz a4, 5f
s16i a3, a2, 0
addi a2, a2, 2
5:
retw
0:
srli a11, a11, 1
min a11, a11, a4
loopgtz a11, 1f
s16i a3, a2, 0
addi a2, a2, 2
1:
sub a4, a4, a11
blti a4, 1, 4f
2:
srli a5, a4, 3 # len // 8
slli a6, a5, 3
sub a6, a4, a6 # remainder
loopgtz a5, 3f
EE.VST.128.IP q0, a2, 16
3:
loopgtz a6, 4f
s16i a3, a2, 0
addi a2, a2, 2
4:
retw
.align 4
.text
.global dl_tie728_memset_32b
.type dl_tie728_memset_32b, @function
.section .iram1
dl_tie728_memset_32b:
.align 4
entry sp, 32
# a2: input_ptr
# a3: value_ptr
# a4: length(n)
s32i a3, a1, 0 // store to stack
mov a7, a1
EE.VLDBC.32 q0, a7
EE.LD.128.USAR.IP q1, a2, 0
RUR.SAR_BYTE a10
beqz a10, 2f
movi a11, 16
sub a11, a11, a10 # head unaligned bytes
movi a8, 4
rems a9, a11, a8
beqz a9, 0f
loopgtz a4, 5f
s32i a3, a2, 0
addi a2, a2, 4
5:
retw
0:
srli a11, a11, 2
min a11, a11, a4
loopgtz a11, 1f
s32i a3, a2, 0
addi a2, a2, 4
1:
sub a4, a4, a11
blti a4, 1, 4f
2:
srli a5, a4, 2 # len // 4
slli a6, a5, 2
sub a6, a4, a6 # remainder
loopgtz a5, 3f
EE.VST.128.IP q0, a2, 16
3:
loopgtz a6, 4f
s32i a3, a2, 0
addi a2, a2, 4
4:
retw
|
georgevio/IoT-Embedded
| 1,165
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/tool/isa/tie728/dl_tie728_bzero.S
|
.align 4
.text
.global dl_tie728_bzero_128b
.type dl_tie728_bzero_128b, @function
.section .iram1
dl_tie728_bzero_128b:
.align 4
entry sp, 32
# a2: ptr
# a3: n
srli a3, a3, 4 # a3: n // 16
EE.ZERO.Q q0
loopgtz a3, 1f
EE.VST.128.IP q0, a2, 16
1:
retw
.align 4
.text
.global dl_tie728_bzero
.type dl_tie728_bzero, @function
.section .iram1
dl_tie728_bzero:
.align 4
entry sp, 32
# a2: ptr
# a3: n(bytes)
movi a10, 0
EE.LD.128.USAR.IP q1, a2, 0
RUR.SAR_BYTE a8
beqz a8, 1f
movi a9, 16
sub a9, a9, a8 # head unaligned bytes
min a9, a9, a3
loopgtz a9, 0f
s8i a10, a2, 0
addi a2, a2, 1
0:
sub a3, a3, a9
blti a3, 1, 4f
1:
srli a4, a3, 4 # n // 16
slli a5, a4, 4
sub a5, a3, a5 # remainder
srli a6, a5, 2 #remainder_4b
slli a7, a6, 2
sub a7, a5, a7 #remainder_1b
EE.ZERO.Q q0
loopgtz a4, 2f
EE.VST.128.IP q0, a2, 16
2:
loopgtz a6, 3f
s32i a10, a2, 0
addi a2, a2, 4
3:
loopgtz a7, 4f
s8i a10, a2, 0
addi a2, a2, 1
4:
retw
|
georgevio/IoT-Embedded
| 3,242
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/tool/isa/esp32p4/dl_esp32p4_memcpy.S
|
.text
.align 2
.global dl_esp32p4_memcpy
.type dl_esp32p4_memcpy, @function
.balign 4
.option norvc
dl_esp32p4_memcpy:
# a0: void *store_ptr
# a1: const void *load_ptr
# a2: const int length(bytes)
# a3: length // 16
# a4: remainder
# a5: length // 32
# t3: odd_flag
# t4: store_ptr sar_bytes / remainder_4b
# t5: remainder_1b
# t6: load_ptr sar_bytes
# a6(not for extension instructions): head unaligned bytes 2
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp.ld.128.usar.ip q0, a1, 0
esp.movx.r.sar.bytes t6
esp.ld.128.usar.ip q1, a0, 0
esp.movx.r.sar.bytes t4
li a6, 16
sub a6, a6, t4 // head unaligned bytes 2
li t0, 16
beq a6, t0, 13f
blt a6, a2, dl_esp32p4_memcpy_done_min
mv a6, a2
dl_esp32p4_memcpy_done_min:
srli t6, a6, 2
slli a7, t6, 2
sub a7, a6, a7
mv t0, t6
blez t0, 10f
9:
lw a3, 0(a1)
addi a1, a1, 4
sw a3, 0(a0)
addi a0, a0, 4
addi t0, t0, -1
bgtz t0, 9b
10:
mv t0, a7
blez t0, 12f
11:
lbu a3, 0(a1)
addi a1, a1, 1
sb a3, 0(a0)
addi a0, a0, 1
addi t0, t0, -1
bgtz t0, 11b
12:
sub a2, a2, a6
esp.ld.128.usar.ip q0, a1, 0
esp.movx.r.sar.bytes t6
13:
beqz t6, 1f
srli a3, a2, 4 // len // 16
slli a4, a3, 4
sub a4, a2, a4 // remainder
srli a5, a3, 1 // len // 32
slli t3, a5, 1
sub t3, a3, t3 // odd_flag
srli t4, a4, 2 //remainder_4b
slli t5, t4, 2
sub t5, a4, t5 //remainder_1b
mv t0, a5
blez t0, 15f
14:
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.ip q2, a1, 0
esp.src.q q0, q0, q1
esp.src.q q1, q1, q2
esp.vst.128.ip q0, a0, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 14b
15:
beqz t3, 4f
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q1, a1, 0
esp.src.q q0, q0, q1
esp.vst.128.ip q0, a0, 16
bnez t3, 4f
1:
srli a3, a2, 4 // len // 16
slli a4, a3, 4
sub a4, a2, a4 // remainder
srli a5, a3, 1 // len // 32
slli t3, a5, 1
sub t3, a3, t3 // odd_flag
srli t4, a4, 2 //remainder_4b
slli t5, t4, 2
sub t5, a4, t5 //remainder_1b
mv t0, a5
blez t0, 3f
2:
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a1, 16
esp.vst.128.ip q0, a0, 16
esp.vst.128.ip q1, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
beqz t3, 4f
esp.vld.128.ip q0, a1, 16
esp.vst.128.ip q0, a0, 16
4:
mv t0, t4
blez t0, 6f
5:
lw a3, 0(a1)
addi a1, a1, 4
sw a3, 0(a0)
addi a0, a0, 4
addi t0, t0, -1
bgtz t0, 5b
6:
mv t0, t5
blez t0, 8f
7:
lbu a3, 0(a1)
addi a1, a1, 1
sb a3, 0(a0)
addi a0, a0, 1
addi t0, t0, -1
bgtz t0, 7b
8:
ret
|
georgevio/IoT-Embedded
| 14,031
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_greaterorequal.S
|
#include "dl_tie728_s8.S"
#include "dl_tie728_s16.S"
#void dl_tie728_s16_greaterorequal_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_greaterorequal_w1_8_w2_8
.type dl_tie728_s16_greaterorequal_w1_8_w2_8, @function
#.section .iram1
dl_tie728_s16_greaterorequal_w1_8_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
movi a14, 0
tie728_s16_greaterorequal_w1_8_w2_8_loop:
beq a14, a5, tie728_s16_greaterorequal_w1_8_w2_8_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.gt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s16 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s16 q2, q2, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_greaterorequal_w1_8_w2_8_loop
tie728_s16_greaterorequal_w1_8_w2_8_end:
retw
#void dl_tie728_s16_greaterorequal_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_greaterorequal_w1_8_w2_1
.type dl_tie728_s16_greaterorequal_w1_8_w2_1, @function
#.section .iram1
dl_tie728_s16_greaterorequal_w1_8_w2_1:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s16_greaterorequal_w1_8_w2_1_loop:
beq a14, a5, tie728_s16_greaterorequal_w1_8_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.gt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s16 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s16 q2, q2, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_greaterorequal_w1_8_w2_1_loop
tie728_s16_greaterorequal_w1_8_w2_1_end:
retw
#void dl_tie728_s16_greaterorequal_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_greaterorequal_w1_1_w2_8
.type dl_tie728_s16_greaterorequal_w1_1_w2_8, @function
#.section .iram1
dl_tie728_s16_greaterorequal_w1_1_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s16_greaterorequal_w1_1_w2_8_loop:
beq a14, a5, tie728_s16_greaterorequal_w1_1_w2_8_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.gt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s16 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s16 q2, q2, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_greaterorequal_w1_1_w2_8_loop
tie728_s16_greaterorequal_w1_1_w2_8_end:
retw
.align 4
.text
.global dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned
.type dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
// ee.vst.128.ip q2, a2, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned_remainder
dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_greaterorequal_w1_8_w2_8_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned
.type dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned_remainder
dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.gt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_greaterorequal_w1_8_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned
.type dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr broadcast
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned_remainder
dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.gt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_greaterorequal_w1_1_w2_8_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 36,841
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_add2d.S
|
#include "dl_tie728_s8.S"
############################################################################################################################################################
####
#### tie728_s8_add2d_11c series
####
############################################################################################################################################################
.macro dl_tie728_rescale_add_rescale_output input0, input1, output, output_scale, output_shift
EE.ZERO.QACC
EE.VMULAS.S8.QACC \input0, \output_scale
EE.VMULAS.S8.QACC \input1, \output_scale
EE.SRCMB.S8.QACC \output, \output_shift, 0
.endm
.align 4
.text
.global dl_tie728_s8_add2d_11c
.type dl_tie728_s8_add2d_11c, @function
# .section .iram1
dl_tie728_s8_add2d_11c:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x_1
l32i a6, a5, 68
l32i a7, a5, 72
blti a6, 1, dl_tie728_s8_add2d_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VADDS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VST.128.IP q5, a2, 16
0:
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
EE.VADDS.S8 q5, q2, q3
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VADDS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VST.128.IP q5, a2, 16
EE.VADDS.S8 q4, q0, q1
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s8_add2d_small_channel: # channel < 3*s (16)
loopgtz a7, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VADDS.S8 q2, q0, q1
EE.VST.128.IP q2, a2, 16
0:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VADDS.S8 q2, q0, q1
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_rescale_add2d_11c
.type dl_tie728_s8_rescale_add2d_11c, @function
# .section .iram1
dl_tie728_s8_rescale_add2d_11c:
.align 4
entry sp, 32
# a2: int8_t *output_ptr: >> shift or *scale) >> shift
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
beqi a8, 1, dl_tie728_s8_rescale_add2d_output
dl_tie728_s8_rescale_add2d_output_scale: # *scale) >> shift
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
loopgtz a6, 0f
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VST.128.IP q1, a2, 16
0:
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s8_rescale_add2d_output: # >> shift
movi a13, 1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all 1
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 1f
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7
EE.SRCMB.S8.QACC q1, a9, 0
EE.LDQA.S8.128.IP a4, 16
EE.VST.128.IP q1, a2, 16
1:
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC q0, q7
EE.SRCMB.S8.QACC q1, a9, 0
EE.VST.128.IP q1, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_add2d_11c_relu
.type dl_tie728_s8_add2d_11c_relu, @function
# .section .iram1
dl_tie728_s8_add2d_11c_relu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x_1
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 68
l32i a7, a5, 72
l32i a14, a5, 52
l32i a15, a5, 60
blti a6, 1, dl_tie728_s8_add2d_relu_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S8 q4, a14, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VADDS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VRELU.S8 q5, a14, a15
EE.VST.128.IP q5, a2, 16
0:
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S8 q4, a14, a15
EE.VST.128.IP q4, a2, 16
EE.VADDS.S8 q5, q2, q3
EE.VRELU.S8 q5, a14, a15
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S8 q4, a14, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VADDS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VRELU.S8 q5, a14, a15
EE.VST.128.IP q5, a2, 16
EE.VADDS.S8 q4, q0, q1
EE.VRELU.S8 q4, a14, a15
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s8_add2d_relu_small_channel: # channel < 3*16byte
loopgtz a7, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VADDS.S8 q2, q0, q1
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
0:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VADDS.S8 q2, q0, q1
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_rescale_add2d_11c_relu
.type dl_tie728_s8_rescale_add2d_11c_relu, @function
# .section .iram1
dl_tie728_s8_rescale_add2d_11c_relu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr: >> shift or *scale) >> shift
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a14, a5, 52
l32i a15, a5, 60
beqi a8, 1, dl_tie728_s8_rescale_add2d_output_relu
dl_tie728_s8_rescale_add2d_output_scale_relu: # *scale) >> shift
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
loopgtz a6, 0f #dl_tie728_s8_rescale_add2d_11c_output_relu
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
0:
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s8_rescale_add2d_output_relu: # >> shift
movi a13, 1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all 1
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 0f
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7
EE.SRCMB.S8.QACC q1, a9, 0
EE.VRELU.S8 q1, a14, a15
EE.LDQA.S8.128.IP a4, 16
EE.VST.128.IP q1, a2, 16
0:
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC q0, q7
EE.SRCMB.S8.QACC q1, a9, 0
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_add2d_11c_prelu
.type dl_tie728_s8_add2d_11c_prelu, @function
# .section .iram1
dl_tie728_s8_add2d_11c_prelu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x_1
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 68
l32i a7, a5, 72
l32i a14, a5, 56
l32i a15, a5, 60
blti a6, 1, dl_tie728_s8_add2d_prelu_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S8 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VPRELU.S8 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
0:
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S8 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8 q5, q2, q3
EE.VPRELU.S8 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S8 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VPRELU.S8 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8 q4, q0, q1
EE.VPRELU.S8 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s8_add2d_prelu_small_channel: # channel < 3*s
loopgtz a7, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q3, a14, 16
EE.VADDS.S8 q2, q0, q1
EE.VPRELU.S8 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
0:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q3, a14, 16
EE.VADDS.S8 q2, q0, q1
EE.VPRELU.S8 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_rescale_add2d_11c_prelu
.type dl_tie728_s8_rescale_add2d_11c_prelu, @function
# .section .iram1
dl_tie728_s8_rescale_add2d_11c_prelu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr: >> shift or *scale) >> shift
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr: input1 >> shift + input0 * 1
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a14, a5, 56
l32i a15, a5, 60
beqi a8, 1, dl_tie728_s8_rescale_add2d_output_prelu
dl_tie728_s8_rescale_add2d_output_scale_prelu: # *scale) >> shift
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
loopgtz a6, 0f
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
EE.VLD.128.IP q5, a14, 16
dl_tie728_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VPRELU.S8 q1, q1, q5, a15
EE.VST.128.IP q1, a2, 16
0:
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
EE.VLD.128.IP q5, a14, 16
dl_tie728_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VPRELU.S8 q1, q1, q5, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s8_rescale_add2d_output_prelu: # >> shift
movi a13, 1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all 1
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 0f
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S8.QACC q1, a9, 0
EE.VPRELU.S8 q1, q1, q6, a15
EE.LDQA.S8.128.IP a4, 16
EE.VST.128.IP q1, a2, 16
0:
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC q0, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S8.QACC q1, a9, 0
EE.VPRELU.S8 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_add2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s8_unaligned_add2d_11c
.type dl_tie728_s8_unaligned_add2d_11c, @function
# .section .iram1
dl_tie728_s8_unaligned_add2d_11c:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
bgei a7, 0, dl_tie728_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s8_unaligned_add2d_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s8_unaligned_add2d_11c_0
beqi a13, 8, dl_tie728_s8_unaligned_add2d_11c_1
loopgtz a6, 0f #dl_tie728_s8_unaligned_add2d_11c
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_add2d_11c_remainder
#output sar = 0
dl_tie728_s8_unaligned_add2d_11c_0:
loopgtz a6, 1f #dl_tie728_s8_unaligned_add2d_11c_loop0
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.VST.128.IP q2, a2, 16
j dl_tie728_s8_unaligned_add2d_11c_remainder
# #output sar = 8
dl_tie728_s8_unaligned_add2d_11c_1:
loopgtz a6, 2f #dl_tie728_s8_unaligned_add2d_11c_loop1
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_unaligned_add2d_11c_remainder
dl_tie728_s8_unaligned_add2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s8_unaligned_add2d_11c_remainder:
beqz a10, dl_tie728_s8_unaligned_add2d_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VADDS.S8 q2, q2, q5
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_add2d_end:
retw
## rescaled add
dl_tie728_s8_unaligned_rescale_add2d_11c:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s8_rescale_unaligned_add2d_output_shift
### rescaled to output by *scale) >> shift
dl_tie728_s8_rescale_unaligned_add2d_output_scale:
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
blti a6, 0, dl_tie728_s8_rescale_unaligned_add2d_scale_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s8_rescale_unaligned_add2d_11c_scale
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a12
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_rescale_unaligned_add2d_scale_remainder
dl_tie728_s8_rescale_unaligned_add2d_scale_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s8_rescale_unaligned_add2d_scale_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_add2d_output_scale_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
# dl_tie728_s8_unaligned_store0 q2, a2, a12
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_add2d_output_scale_end:
retw
### rescaled to output by right shift
dl_tie728_s8_rescale_unaligned_add2d_output_shift:
movi a13, 1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all 1
blti a6, 0, dl_tie728_s8_rescale_unaligned_add2d_shift_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s8_rescale_unaligned_add2d_11c_shift
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.SRCMB.S8.QACC q5, a9, 0
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.SRCMB.S8.QACC q5, a9, 0
dl_tie728_s8_unaligned_store0 q5, a2, a13
j dl_tie728_s8_rescale_unaligned_add2d_shift_remainder
dl_tie728_s8_rescale_unaligned_add2d_shift_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s8_rescale_unaligned_add2d_shift_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_add2d_output_shift_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.SRCMB.S8.QACC q5, a9, 0
# dl_tie728_s8_unaligned_store0 q5, a2, a13
dl_tie728_s8_store_remainder q5, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_add2d_output_shift_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_add2d_11c_relu
.type dl_tie728_s8_unaligned_add2d_11c_relu, @function
# .section .iram1
dl_tie728_s8_unaligned_add2d_11c_relu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a14, a5, 52
l32i a15, a5, 60
bgei a7, 0, dl_tie728_s8_unaligned_rescale_add2d_11c_relu
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s8_unaligned_add2d_11c_relu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s8_unaligned_add2d_11c_relu_0
beqi a13, 8, dl_tie728_s8_unaligned_add2d_11c_relu_1
loopgtz a6, 0f #dl_tie728_s8_unaligned_add2d_11c
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_add2d_11c_relu_remainder
#output sar = 0
dl_tie728_s8_unaligned_add2d_11c_relu_0:
loopgtz a6, 1f #dl_tie728_s8_unaligned_add2d_11c_loop0
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie728_s8_unaligned_add2d_11c_relu_remainder
# #output sar = 8
dl_tie728_s8_unaligned_add2d_11c_relu_1:
loopgtz a6, 2f #dl_tie728_s8_unaligned_add2d_11c_loop1
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_unaligned_add2d_11c_relu_remainder
dl_tie728_s8_unaligned_add2d_11c_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s8_unaligned_add2d_11c_relu_remainder:
beqz a10, dl_tie728_s8_unaligned_add2d_relu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_add2d_relu_end:
retw
## rescaled add
dl_tie728_s8_unaligned_rescale_add2d_11c_relu:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s8_rescale_unaligned_add2d_output_shift_relu
### rescaled to output by *scale) >> shift
dl_tie728_s8_rescale_unaligned_add2d_output_scale_relu:
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
blti a6, 0, dl_tie728_s8_rescale_unaligned_add2d_scale_relu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s8_rescale_unaligned_add2d_11c_scale
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a12
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_rescale_unaligned_add2d_scale_relu_remainder
dl_tie728_s8_rescale_unaligned_add2d_scale_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s8_rescale_unaligned_add2d_scale_relu_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_add2d_output_scale_relu_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VRELU.S8 q2, a14, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a12
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_add2d_output_scale_relu_end:
retw
### rescaled to output by right shift
dl_tie728_s8_rescale_unaligned_add2d_output_shift_relu:
movi a13, 1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all 1
blti a6, 0, dl_tie728_s8_rescale_unaligned_add2d_shift_relu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s8_rescale_unaligned_add2d_11c_shift
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.SRCMB.S8.QACC q5, a9, 0
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q5, a14, a15
dl_tie728_s8_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.SRCMB.S8.QACC q5, a9, 0
EE.VRELU.S8 q5, a14, a15
dl_tie728_s8_unaligned_store0 q5, a2, a13
j dl_tie728_s8_rescale_unaligned_add2d_shift_relu_remainder
dl_tie728_s8_rescale_unaligned_add2d_shift_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s8_rescale_unaligned_add2d_shift_relu_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_add2d_output_shift_relu_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.SRCMB.S8.QACC q5, a9, 0
EE.VRELU.S8 q5, a14, a15
# dl_tie728_s8_unaligned_store0 q5, a2, a13
dl_tie728_s8_store_remainder q5, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_add2d_output_shift_relu_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_add2d_11c_prelu
.type dl_tie728_s8_unaligned_add2d_11c_prelu, @function
# .section .iram1
dl_tie728_s8_unaligned_add2d_11c_prelu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a14, a5, 56
l32i a15, a5, 60
bgei a7, 0, dl_tie728_s8_unaligned_rescale_add2d_11c_prelu
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s8_unaligned_add2d_11c_prelu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s8_unaligned_add2d_11c_prelu_0
beqi a13, 8, dl_tie728_s8_unaligned_add2d_11c_prelu_1
loopgtz a6, 0f #dl_tie728_s8_unaligned_add2d_11c
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_add2d_11c_prelu_remainder
#output sar = 0
dl_tie728_s8_unaligned_add2d_11c_prelu_0:
loopgtz a6, 1f #dl_tie728_s8_unaligned_add2d_11c_loop0
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
j dl_tie728_s8_unaligned_add2d_11c_prelu_remainder
# #output sar = 8
dl_tie728_s8_unaligned_add2d_11c_prelu_1:
loopgtz a6, 2f #dl_tie728_s8_unaligned_add2d_11c_loop1
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S8 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_unaligned_add2d_11c_prelu_remainder
dl_tie728_s8_unaligned_add2d_11c_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s8_unaligned_add2d_11c_prelu_remainder:
beqz a10, dl_tie728_s8_unaligned_add2d_prelu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_add2d_prelu_end:
retw
## rescaled add
dl_tie728_s8_unaligned_rescale_add2d_11c_prelu:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s8_rescale_unaligned_add2d_output_shift_prelu
### rescaled to output by *scale) >> shift
dl_tie728_s8_rescale_unaligned_add2d_output_scale_prelu:
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
blti a6, 0, dl_tie728_s8_rescale_unaligned_add2d_scale_prelu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s8_rescale_unaligned_add2d_11c_scale
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a12
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
EE.VLD.128.IP q6, a14, 16
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_rescale_unaligned_add2d_scale_prelu_remainder
dl_tie728_s8_rescale_unaligned_add2d_scale_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s8_rescale_unaligned_add2d_scale_prelu_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_add2d_output_scale_prelu_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
EE.VLD.128.IP q6, a14, 16
dl_tie728_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VPRELU.S8 q2, q2, q6, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a12
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_add2d_output_scale_prelu_end:
retw
### rescaled to output by right shift
dl_tie728_s8_rescale_unaligned_add2d_output_shift_prelu:
movi a13, 1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all 1
blti a6, 0, dl_tie728_s8_rescale_unaligned_add2d_shift_prelu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s8_rescale_unaligned_add2d_11c_shift
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.SRCMB.S8.QACC q5, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q5, q5, q6, a15
dl_tie728_s8_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S8.QACC q5, a9, 0
EE.VPRELU.S8 q5, q5, q6, a15
dl_tie728_s8_unaligned_store0 q5, a2, a13
j dl_tie728_s8_rescale_unaligned_add2d_shift_prelu_remainder
dl_tie728_s8_rescale_unaligned_add2d_shift_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s8_rescale_unaligned_add2d_shift_prelu_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_add2d_output_shift_prelu_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
EE.VMULAS.S8.QACC q2, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S8.QACC q5, a9, 0
EE.VPRELU.S8 q5, q5, q6, a15
# dl_tie728_s8_unaligned_store0 q5, a2, a13
dl_tie728_s8_store_remainder q5, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_add2d_output_shift_prelu_end:
retw
|
georgevio/IoT-Embedded
| 15,133
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_mul2d.S
|
# include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_mul2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_mul2d_11c
.type dl_tie728_s16_mul2d_11c, @function
.section .iram1
dl_tie728_s16_mul2d_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
l32i a6, a5, 64
l32i a7, a5, 100
blti a6, 0, 5f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.ZERO.QACC
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.SRCMB.S16.QACC q2, a7, 0
EE.VST.128.IP q2, a2, 16
0:
EE.ZERO.QACC
EE.VMULAS.S16.QACC q0, q1
EE.SRCMB.S16.QACC q2, a7, 0
EE.VST.128.IP q2, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_mul2d_11c_relu
.type dl_tie728_s16_mul2d_11c_relu, @function
.section .iram1
dl_tie728_s16_mul2d_11c_relu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 100
l32i a8, a5, 76
l32i a14, a5, 52
l32i a15, a5, 60
blti a6, 0, 5f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.ZERO.QACC
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.SRCMB.S16.QACC q2, a7, 0
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
0:
EE.ZERO.QACC
EE.VMULAS.S16.QACC q0, q1
EE.SRCMB.S16.QACC q2, a7, 0
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_mul2d_11c_prelu
.type dl_tie728_s16_mul2d_11c_prelu, @function
.section .iram1
dl_tie728_s16_mul2d_11c_prelu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 100
l32i a14, a5, 56
l32i a15, a5, 60
blti a6, 0, 5f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.ZERO.QACC
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q3, a14, 16
EE.SRCMB.S16.QACC q2, a7, 0
EE.VPRELU.S16 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
0:
EE.ZERO.QACC
EE.VMULAS.S16.QACC q0, q1
EE.VLD.128.IP q3, a14, 16
EE.SRCMB.S16.QACC q2, a7, 0
EE.VPRELU.S16 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
5:
retw
############################################################################################################################################################
####
#### tie728_S16_unaligned_mul2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_unaligned_mul2d_11c
.type dl_tie728_s16_unaligned_mul2d_11c, @function
.section .iram1
dl_tie728_s16_unaligned_mul2d_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
# a8: mul_shift
l32i a6, a5, 64
l32i a7, a5, 76
l32i a8, a5, 100
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_S16_unaligned_mul2d_11c_small_remainder # channel < 8
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_S16_unaligned_mul2d_11c_0
beqi a13, 8, dl_tie718_S16_unaligned_mul2d_11c_1
loopgtz a6, 0f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie718_S16_unaligned_mul2d_11c_remainder
dl_tie718_S16_unaligned_mul2d_11c_0:
loopgtz a6, 1f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.VST.128.IP q2, a2, 16
j dl_tie718_S16_unaligned_mul2d_11c_remainder
dl_tie718_S16_unaligned_mul2d_11c_1:
loopgtz a6, 2f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie718_S16_unaligned_mul2d_11c_remainder
dl_tie718_S16_unaligned_mul2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_S16_unaligned_mul2d_11c_remainder:
beqz a7, dl_tie728_S16_unaligned_mul2d_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.ZERO.QACC
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
srli a7, a7, 1
dl_tie728_s16_store_remainder q2, a7, a12, a2
dl_tie728_S16_unaligned_mul2d_11c_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_mul2d_11c_relu
.type dl_tie728_s16_unaligned_mul2d_11c_relu, @function
.section .iram1
dl_tie728_s16_unaligned_mul2d_11c_relu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
# a8: mul_shift
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 76
l32i a8, a5, 100
l32i a14, a5, 52
l32i a15, a5, 60
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_S16_unaligned_mul2d_11c_relu_small_remainder # channel < 8
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_S16_unaligned_mul2d_11c_relu_0
beqi a13, 8, dl_tie718_S16_unaligned_mul2d_11c_relu_1
loopgtz a6, 0f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie718_S16_unaligned_mul2d_11c_relu_remainder
dl_tie718_S16_unaligned_mul2d_11c_relu_0:
loopgtz a6, 1f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_S16_unaligned_mul2d_11c_relu_remainder
dl_tie718_S16_unaligned_mul2d_11c_relu_1:
loopgtz a6, 2f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie718_S16_unaligned_mul2d_11c_relu_remainder
dl_tie718_S16_unaligned_mul2d_11c_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_S16_unaligned_mul2d_11c_relu_remainder:
beqz a7, dl_tie728_S16_unaligned_mul2d_11c_relu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.ZERO.QACC
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.VRELU.S16 q2, a14, a15
srli a7, a7, 1
dl_tie728_s16_store_remainder q2, a7, a12, a2
dl_tie728_S16_unaligned_mul2d_11c_relu_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_mul2d_11c_prelu
.type dl_tie728_s16_unaligned_mul2d_11c_prelu, @function
.section .iram1
dl_tie728_s16_unaligned_mul2d_11c_prelu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
# a8: mul_shift
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 76
l32i a8, a5, 100
l32i a14, a5, 56
l32i a15, a5, 60
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_S16_unaligned_mul2d_11c_prelu_small_remainder # channel < 8
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_S16_unaligned_mul2d_11c_prelu_0
beqi a13, 8, dl_tie718_S16_unaligned_mul2d_11c_prelu_1
loopgtz a6, 0f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q2, a8, 0
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie718_S16_unaligned_mul2d_11c_prelu_remainder
dl_tie718_S16_unaligned_mul2d_11c_prelu_0:
loopgtz a6, 1f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q2, a8, 0
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_S16_unaligned_mul2d_11c_prelu_remainder
dl_tie718_S16_unaligned_mul2d_11c_prelu_1:
loopgtz a6, 2f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.SRCMB.S16.QACC q2, a8, 0
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S16.QACC q2, q5
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q2, a8, 0
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie718_S16_unaligned_mul2d_11c_prelu_remainder
dl_tie718_S16_unaligned_mul2d_11c_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_S16_unaligned_mul2d_11c_prelu_remainder:
beqz a7, dl_tie728_S16_unaligned_mul2d_11c_prelu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.ZERO.QACC
EE.VMULAS.S16.QACC q2, q5
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q2, a8, 0
EE.VPRELU.S16 q2, q2, q6, a15
srli a7, a7, 1
dl_tie728_s16_store_remainder q2, a7, a12, a2
dl_tie728_S16_unaligned_mul2d_11c_prelu_end:
retw
|
georgevio/IoT-Embedded
| 13,301
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_max2d.S
|
#include "dl_tie728_s8.S"
############################################################################################################################################################
####
#### tie728_s8_max2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s8_max2d_11c
.type dl_tie728_s8_max2d_11c, @function
.section .iram1
dl_tie728_s8_max2d_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
l32i a6, a5, 64
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VMAX.S8.LD.INCP q0, a3, q2, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.VST.128.IP q2, a2, 16
0:
EE.VMAX.S8 q2, q0, q1
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_max2d_11c_relu
.type dl_tie728_s8_max2d_11c_relu, @function
.section .iram1
dl_tie728_s8_max2d_11c_relu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a14, a5, 52
l32i a15, a5, 60
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VMAX.S8.LD.INCP q0, a3, q2, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
0:
EE.VMAX.S8 q2, q0, q1
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_max2d_11c_prelu
.type dl_tie728_s8_max2d_11c_prelu, @function
.section .iram1
dl_tie728_s8_max2d_11c_prelu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 76
l32i a14, a5, 56
l32i a15, a5, 60
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VMAX.S8.LD.INCP q0, a3, q2, q0, q1
EE.VLD.128.IP q3, a14, 16
EE.VLD.128.IP q1, a4, 16
EE.VPRELU.S8 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
0:
EE.VLD.128.IP q3, a14, 16
EE.VMAX.S8 q2, q0, q1
EE.VPRELU.S8 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_max2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s8_unaligned_max2d_11c
.type dl_tie728_s8_unaligned_max2d_11c, @function
.section .iram1
dl_tie728_s8_unaligned_max2d_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
l32i a6, a5, 64
l32i a7, a5, 76
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s8_unaligned_max2d_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s8_unaligned_max2d_11c_0
beqi a13, 8, dl_tie718_s8_unaligned_max2d_11c_1
loopgtz a6, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie718_s8_unaligned_max2d_11c_remainder
dl_tie718_s8_unaligned_max2d_11c_0:
loopgtz a6, 1f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.VST.128.IP q2, a2, 16
j dl_tie718_s8_unaligned_max2d_11c_remainder
dl_tie718_s8_unaligned_max2d_11c_1:
loopgtz a6, 2f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie718_s8_unaligned_max2d_11c_remainder
dl_tie718_s8_unaligned_max2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s8_unaligned_max2d_11c_remainder:
beqz a7, dl_tie728_s8_unaligned_max2d_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VMAX.S8 q2, q2, q5
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a7
dl_tie728_s8_unaligned_max2d_11c_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_max2d_11c_relu
.type dl_tie728_s8_unaligned_max2d_11c_relu, @function
.section .iram1
dl_tie728_s8_unaligned_max2d_11c_relu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 76
l32i a14, a5, 52
l32i a15, a5, 60
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s8_unaligned_max2d_11c_relu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s8_unaligned_max2d_11c_relu_0
beqi a13, 8, dl_tie718_s8_unaligned_max2d_11c_relu_1
loopgtz a6, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie718_s8_unaligned_max2d_11c_relu_remainder
dl_tie718_s8_unaligned_max2d_11c_relu_0:
loopgtz a6, 1f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_s8_unaligned_max2d_11c_relu_remainder
dl_tie718_s8_unaligned_max2d_11c_relu_1:
loopgtz a6, 2f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie718_s8_unaligned_max2d_11c_relu_remainder
dl_tie718_s8_unaligned_max2d_11c_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s8_unaligned_max2d_11c_relu_remainder:
beqz a7, dl_tie728_s8_unaligned_max2d_11c_relu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a7
dl_tie728_s8_unaligned_max2d_11c_relu_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_max2d_11c_prelu
.type dl_tie728_s8_unaligned_max2d_11c_prelu, @function
.section .iram1
dl_tie728_s8_unaligned_max2d_11c_prelu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
# a14: activation_alpha
# a15: activation_shift_ptr
l32i a6, a5, 64
l32i a7, a5, 76
l32i a14, a5, 56
l32i a15, a5, 60
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s8_unaligned_max2d_11c_prelu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s8_unaligned_max2d_11c_prelu_0
beqi a13, 8, dl_tie718_s8_unaligned_max2d_11c_prelu_1
loopgtz a6, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VMAX.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie718_s8_unaligned_max2d_11c_prelu_remainder
dl_tie718_s8_unaligned_max2d_11c_prelu_0:
loopgtz a6, 1f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VMAX.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_s8_unaligned_max2d_11c_prelu_remainder
dl_tie718_s8_unaligned_max2d_11c_prelu_1:
loopgtz a6, 2f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S8 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VMAX.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie718_s8_unaligned_max2d_11c_prelu_remainder
dl_tie718_s8_unaligned_max2d_11c_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s8_unaligned_max2d_11c_prelu_remainder:
beqz a7, dl_tie728_s8_unaligned_max2d_11c_prelu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VMAX.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a7
dl_tie728_s8_unaligned_max2d_11c_prelu_end:
retw
|
georgevio/IoT-Embedded
| 35,916
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_add2d.S
|
# include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_add2d_11c series
####
############################################################################################################################################################
.macro dl_tie728_s16_rescale_add_rescale_output input0, input1, output, output_scale, output_shift
EE.ZERO.QACC
EE.VMULAS.s16.QACC \input0, \output_scale
EE.VMULAS.s16.QACC \input1, \output_scale
EE.SRCMB.S16.QACC \output, \output_shift, 0
.endm
.align 4
.text
.global dl_tie728_s16_add2d_11c
.type dl_tie728_s16_add2d_11c, @function
# .section .iram1
dl_tie728_s16_add2d_11c:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x_1
l32i a6, a5, 68
l32i a7, a5, 72
blti a6, 1, dl_tie728_s16_add2d_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VADDS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VST.128.IP q5, a2, 16
0:
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VADDS.S16 q5, q2, q3
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q0, a3, 16
EE.VADDS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VST.128.IP q5, a2, 16
EE.VADDS.S16 q4, q0, q1
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s16_add2d_small_channel:
blti a7, 0, 5f
loopgtz a7, 1f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VADDS.S16 q2, q0, q1
EE.VST.128.IP q2, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VADDS.S16 q2, q0, q1
EE.VST.128.IP q2, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_rescale_add2d_11c
.type dl_tie728_s16_rescale_add2d_11c, @function
# .section .iram1
dl_tie728_s16_rescale_add2d_11c:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
beqi a8, 1, dl_tie728_s16_rescale_add2d_output
dl_tie728_s16_rescale_add2d_output_scale:
s16i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
# addi a6, a6, 1
loopgtz a6, 1f
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VST.128.IP q1, a2, 16
1:
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_add2d_output:
movi a13, 1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all 1
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 2f
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.LDQA.S16.128.IP a4, 16
EE.VST.128.IP q1, a2, 16
2:
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VST.128.IP q1, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_add2d_11c_relu
.type dl_tie728_s16_add2d_11c_relu, @function
# .section .iram1
dl_tie728_s16_add2d_11c_relu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 68
l32i a7, a5, 72
l32i a14, a5, 52
l32i a15, a5, 60
beqz a6, dl_tie728_s16_add2d_relu_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S16 q4, a14, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VADDS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VRELU.S16 q5, a14, a15
EE.VST.128.IP q5, a2, 16
0:
EE.VLD.128.IP q2, a3, 16
EE.VADDS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S16 q4, a14, a15
EE.VST.128.IP q4, a2, 16
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VADDS.S16 q5, q2, q3
EE.VRELU.S16 q5, a14, a15
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q0, a3, 16
EE.VADDS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VRELU.S16 q5, a14, a15
EE.VST.128.IP q5, a2, 16
EE.VADDS.S16 q4, q0, q1
EE.VRELU.S16 q4, a14, a15
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s16_add2d_relu_small_channel:
blti a7, 0, 5f
loopgtz a7, 1f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VADDS.S16 q2, q0, q1
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VADDS.S16 q2, q0, q1
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_rescale_add2d_11c_relu
.type dl_tie728_s16_rescale_add2d_11c_relu, @function
# .section .iram1
dl_tie728_s16_rescale_add2d_11c_relu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a14, a5, 52
l32i a15, a5, 60
beqi a8, 1, dl_tie728_s16_rescale_add2d_output_relu
dl_tie728_s16_rescale_add2d_output_scale_relu:
s16i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
loopgtz a6, 1f
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
1:
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_add2d_output_relu:
movi a13, 1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all 1
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 2f
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.LDQA.S16.128.IP a4, 16
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
2:
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_add2d_11c_prelu
.type dl_tie728_s16_add2d_11c_prelu, @function
# .section .iram1
dl_tie728_s16_add2d_11c_prelu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 68
l32i a7, a5, 72
l32i a14, a5, 56
l32i a15, a5, 60
beqz a6, dl_tie728_s16_add2d_prelu_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S16 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VPRELU.S16 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
0:
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S16 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16 q5, q2, q3
EE.VPRELU.S16 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VPRELU.S16 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16 q4, q0, q1
EE.VPRELU.S16 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s16_add2d_prelu_small_channel:
blti a7, 0, 5f
loopgtz a7, 1f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16 q2, q0, q1
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16 q2, q0, q1
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_rescale_add2d_11c_prelu
.type dl_tie728_s16_rescale_add2d_11c_prelu, @function
# .section .iram1
dl_tie728_s16_rescale_add2d_11c_prelu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a14, a5, 56
l32i a15, a5, 60
beqi a8, 1, dl_tie728_s16_rescale_add2d_output_prelu
dl_tie728_s16_rescale_add2d_output_scale_prelu:
s16i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
# addi a6, a6, 1
loopgtz a6, 1f
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VLD.128.IP q5, a14, 16
EE.VPRELU.S16 q1, q1, q5, a15
EE.VST.128.IP q1, a2, 16
1:
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q0, q1, q1, q7, a9
EE.VLD.128.IP q5, a14, 16
EE.VPRELU.S16 q1, q1, q5, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_add2d_output_prelu:
movi a13, 1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all 1
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 2f
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LDQA.S16.128.IP a4, 16
EE.VPRELU.S16 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
2:
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC q0, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q1, a9, 0
EE.VPRELU.S16 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
retw
############################################################################################################################################################
####
#### tie728_s16_unaligned_add2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_unaligned_add2d_11c
.type dl_tie728_s16_unaligned_add2d_11c, @function
# .section .iram1
dl_tie728_s16_unaligned_add2d_11c:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
bgei a7, 0, dl_tie728_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s16_unaligned_add2d_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s16_unaligned_add2d_11c_0
beqi a13, 8, dl_tie728_s16_unaligned_add2d_11c_1
loopgtz a6, 0f #dl_tie728_s16_unaligned_add2d_11c
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_unaligned_add2d_11c_remainder
#output sar = 0
dl_tie728_s16_unaligned_add2d_11c_0:
loopgtz a6, 1f #dl_tie728_s16_unaligned_add2d_11c_loop0
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.VST.128.IP q2, a2, 16
j dl_tie728_s16_unaligned_add2d_11c_remainder
# #output sar = 8
dl_tie728_s16_unaligned_add2d_11c_1:
loopgtz a6, 2f #dl_tie728_s16_unaligned_add2d_11c_loop1
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_unaligned_add2d_11c_remainder
dl_tie728_s16_unaligned_add2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s16_unaligned_add2d_11c_remainder:
beqz a10, dl_tie728_s16_unaligned_add2d_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VADDS.S16 q2, q2, q5
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_add2d_end:
retw
## rescaled add
dl_tie728_s16_unaligned_rescale_add2d_11c:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s16_rescale_unaligned_add2d_output_shift
### rescaled to output by *scale) >> shift
dl_tie728_s16_rescale_unaligned_add2d_output_scale:
s32i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
blti a6, 0, dl_tie728_s16_rescale_unaligned_add2d_scale_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s16_rescale_unaligned_add2d_11c_scale
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a12
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_rescale_unaligned_add2d_scale_remainder
dl_tie728_s16_rescale_unaligned_add2d_scale_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s16_rescale_unaligned_add2d_scale_remainder:
beqz a10, dl_tie728_s16_unaligned_rescale_add2d_output_scale_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a12, a2
dl_tie728_s16_unaligned_rescale_add2d_output_scale_end:
retw
### rescaled to output by right shift
dl_tie728_s16_rescale_unaligned_add2d_output_shift:
movi a13, 1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all 1
blti a6, 0, dl_tie728_s16_rescale_unaligned_add2d_shift_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s16_rescale_unaligned_add2d_11c_shift
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.SRCMB.S16.QACC q5, a9, 0
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.SRCMB.S16.QACC q5, a9, 0
dl_tie728_128b_unaligned_store0 q5, a2, a13
j dl_tie728_s16_rescale_unaligned_add2d_shift_remainder
dl_tie728_s16_rescale_unaligned_add2d_shift_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s16_rescale_unaligned_add2d_shift_remainder:
beqz a10, dl_tie728_s16_unaligned_rescale_add2d_output_shift_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.SRCMB.S16.QACC q5, a9, 0
srli a10, a10, 1
dl_tie728_s16_store_remainder q5, a10, a13, a2
dl_tie728_s16_unaligned_rescale_add2d_output_shift_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_add2d_11c_relu
.type dl_tie728_s16_unaligned_add2d_11c_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_add2d_11c_relu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a14, a5, 52
l32i a15, a5, 60
bgei a7, 0, dl_tie728_s16_unaligned_rescale_add2d_11c_relu
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s16_unaligned_add2d_11c_small_remainder_relu # channel < 8
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s16_unaligned_add2d_11c_relu_0
beqi a13, 8, dl_tie728_s16_unaligned_add2d_11c_relu_1
loopgtz a6, 0f #dl_tie728_s16_unaligned_add2d_11c_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_unaligned_add2d_11c_remainder_relu
#output sar = 0
dl_tie728_s16_unaligned_add2d_11c_relu_0:
loopgtz a6, 1f #dl_tie728_s16_unaligned_add2d_11c_loop0_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie728_s16_unaligned_add2d_11c_remainder_relu
# #output sar = 8
dl_tie728_s16_unaligned_add2d_11c_relu_1:
loopgtz a6, 2f #dl_tie728_s16_unaligned_add2d_11c_loop1_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_unaligned_add2d_11c_remainder_relu
dl_tie728_s16_unaligned_add2d_11c_small_remainder_relu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s16_unaligned_add2d_11c_remainder_relu:
beqz a10, dl_tie728_s16_unaligned_add2d_end_relu
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.VRELU.S16 q2, a14, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_add2d_end_relu:
retw
## rescaled add
dl_tie728_s16_unaligned_rescale_add2d_11c_relu:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s16_rescale_unaligned_add2d_output_shift_relu
### rescaled to output by *scale) >> shift
dl_tie728_s16_rescale_unaligned_add2d_output_scale_relu:
s32i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
blti a6, 0, dl_tie728_s16_rescale_unaligned_add2d_scale_small_remainder_relu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s16_rescale_unaligned_add2d_11c_scale_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a12
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_rescale_unaligned_add2d_scale_remainder_relu
dl_tie728_s16_rescale_unaligned_add2d_scale_small_remainder_relu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s16_rescale_unaligned_add2d_scale_remainder_relu:
beqz a10, dl_tie728_s16_unaligned_rescale_add2d_output_scale_end_relu # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VRELU.S16 q2, a14, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_rescale_add2d_output_scale_end_relu:
retw
### rescaled to output by right shift
dl_tie728_s16_rescale_unaligned_add2d_output_shift_relu:
movi a13, 1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all 1
blti a6, 0, dl_tie728_s16_rescale_unaligned_add2d_shift_small_remainder_relu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s16_rescale_unaligned_add2d_11c_shift_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.SRCMB.S16.QACC q5, a9, 0
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q5, a14, a15
dl_tie728_128b_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.SRCMB.S16.QACC q5, a9, 0
EE.VRELU.S16 q5, a14, a15
dl_tie728_128b_unaligned_store0 q5, a2, a13
j dl_tie728_s16_rescale_unaligned_add2d_shift_remainder_relu
dl_tie728_s16_rescale_unaligned_add2d_shift_small_remainder_relu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s16_rescale_unaligned_add2d_shift_remainder_relu:
beqz a10, dl_tie728_s16_unaligned_rescale_add2d_output_shift_end_relu # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.SRCMB.S16.QACC q5, a9, 0
EE.VRELU.S16 q5, a14, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q5, a10, a13, a2
dl_tie728_s16_unaligned_rescale_add2d_output_shift_end_relu:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_add2d_11c_prelu
.type dl_tie728_s16_unaligned_add2d_11c_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_add2d_11c_prelu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a14, a5, 56
l32i a15, a5, 60
bgei a7, 0, dl_tie728_s16_unaligned_rescale_add2d_11c_prelu
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s16_unaligned_add2d_11c_small_remainder_prelu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s16_unaligned_add2d_11c_prelu_0
beqi a13, 8, dl_tie728_s16_unaligned_add2d_11c_prelu_1
loopgtz a6, 0f #dl_tie728_s16_unaligned_add2d_11c_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16 q2, q2, q5
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_unaligned_add2d_11c_remainder_prelu
#output sar = 0
dl_tie728_s16_unaligned_add2d_11c_prelu_0:
loopgtz a6, 1f #dl_tie728_s16_unaligned_add2d_11c_loop0_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16 q2, q2, q5
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
j dl_tie728_s16_unaligned_add2d_11c_remainder_prelu
# #output sar = 8
dl_tie728_s16_unaligned_add2d_11c_prelu_1:
loopgtz a6, 2f #dl_tie728_s16_unaligned_add2d_11c_loop1_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VADDS.S16 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16 q2, q2, q5
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_unaligned_add2d_11c_remainder_prelu
dl_tie728_s16_unaligned_add2d_11c_small_remainder_prelu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s16_unaligned_add2d_11c_remainder_prelu:
beqz a10, dl_tie728_s16_unaligned_add2d_end_prelu
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VADDS.S16 q2, q2, q5
EE.VPRELU.S16 q2, q2, q6, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_add2d_end_prelu:
retw
## rescaled add
dl_tie728_s16_unaligned_rescale_add2d_11c_prelu:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s16_rescale_unaligned_add2d_output_shift_prelu
### rescaled to output by *scale) >> shift
dl_tie728_s16_rescale_unaligned_add2d_output_scale_prelu:
s32i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
# ssr a9 #output shift
# movi a13, 0
blti a6, 0, dl_tie728_s16_rescale_unaligned_add2d_scale_small_remainder_prelu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s16_rescale_unaligned_add2d_11c_scale_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store0 q2, a2, a12
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
EE.VLD.128.IP q6, a14, 16
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_rescale_unaligned_add2d_scale_remainder_prelu
dl_tie728_s16_rescale_unaligned_add2d_scale_small_remainder_prelu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s16_rescale_unaligned_add2d_scale_remainder_prelu:
beqz a10, dl_tie728_s16_unaligned_rescale_add2d_output_scale_end_prelu # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
EE.VLD.128.IP q6, a14, 16
dl_tie728_s16_rescale_add_rescale_output q2, q1, q2, q7, a9
EE.VPRELU.S16 q2, q2, q6, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_rescale_add2d_output_scale_end_prelu:
retw
### rescaled to output by right shift
dl_tie728_s16_rescale_unaligned_add2d_output_shift_prelu:
movi a13, 1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all 1
blti a6, 0, dl_tie728_s16_rescale_unaligned_add2d_shift_small_remainder_prelu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s16_rescale_unaligned_add2d_11c_shift_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.SRCMB.S16.QACC q5, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q5, q5, q6, a15
dl_tie728_128b_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q5, a9, 0
EE.VPRELU.S16 q5, q5, q6, a15
dl_tie728_128b_unaligned_store0 q5, a2, a13
j dl_tie728_s16_rescale_unaligned_add2d_shift_remainder_prelu
dl_tie728_s16_rescale_unaligned_add2d_shift_small_remainder_prelu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12 #input1 sar
dl_tie728_s16_rescale_unaligned_add2d_shift_remainder_prelu:
beqz a10, dl_tie728_s16_unaligned_rescale_add2d_output_shift_end_prelu # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
EE.VMULAS.S16.QACC q2, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q5, a9, 0
EE.VPRELU.S16 q5, q5, q6, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q5, a10, a13, a2
dl_tie728_s16_unaligned_rescale_add2d_output_shift_end_prelu:
retw
|
georgevio/IoT-Embedded
| 4,450
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_max2d.S
|
#include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_max2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_max2d_11c
.type dl_tie728_s16_max2d_11c, @function
.section .iram1
dl_tie728_s16_max2d_11c:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
l32i a6, a5, 64
blti a6, 0, 5f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VMAX.S16.LD.INCP q0, a3, q2, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.VST.128.IP q2, a2, 16
0:
EE.VMAX.S16 q2, q0, q1
EE.VST.128.IP q2, a2, 16
5:
retw
############################################################################################################################################################
####
#### tie728_s16_unaligned_max2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_unaligned_max2d_11c
.type dl_tie728_s16_unaligned_max2d_11c, @function
.section .iram1
dl_tie728_s16_unaligned_max2d_11c:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
l32i a6, a5, 64
l32i a7, a5, 76
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s16_unaligned_max2d_11c_small_remainder # channel < 8
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s16_unaligned_max2d_11c_0
beqi a13, 8, dl_tie718_s16_unaligned_max2d_11c_1
loopgtz a6, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S16 q2, q2, q5
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie718_s16_unaligned_max2d_11c_remainder
dl_tie718_s16_unaligned_max2d_11c_0:
loopgtz a6, 1f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S16 q2, q2, q5
EE.VST.128.IP q2, a2, 16
j dl_tie718_s16_unaligned_max2d_11c_remainder
dl_tie718_s16_unaligned_max2d_11c_1:
loopgtz a6, 2f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMAX.S16 q2, q2, q5
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie718_s16_unaligned_max2d_11c_remainder
dl_tie718_s16_unaligned_max2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s16_unaligned_max2d_11c_remainder:
beqz a7, dl_tie728_s16_unaligned_max2d_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VMAX.S16 q2, q2, q5
srli a7, a7, 1
dl_tie728_s16_store_remainder q2, a7, a12, a2
dl_tie728_s16_unaligned_max2d_11c_end:
retw
|
georgevio/IoT-Embedded
| 3,511
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_relu.S
|
#include "dl_tie728_s8.S"
.align 4
.text
.global dl_tie728_s8_relu_11c
.type dl_tie728_s8_relu_11c, @function
.section .iram1
dl_tie728_s8_relu_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: c_rs1_1: c / 2x - 1
# a6: c_rs2_1: c_left_1
# a14: activation_alpha
# a15: activation_shift
l32i a5, a4, 88
l32i a6, a4, 92
l32i a7, a4, 136
l32i a14, a4, 76 # activation_alpha
l32i a15, a4, 84 # activation_shift
loopgtz a5, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a3, 16
EE.VRELU.S8 q0, a14, a15
EE.VST.128.IP q0, a2, 16
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
0:
loopgtz a6, 1f
EE.VLD.128.IP q0, a3, 16
EE.VRELU.S8 q0, a14, a15
EE.VST.128.IP q0, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VRELU.S8 q0, a14, a15
EE.VST.128.IP q0, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_unaligned_relu_11c
.type dl_tie728_s8_unaligned_relu_11c, @function
.section .iram1
dl_tie728_s8_unaligned_relu_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: c_div_x_1
# a6: c_remainder
# a14: activation_alpha
# a15: activation_shift
l32i a5, a4, 100
l32i a6, a4, 136
l32i a14, a4, 76 # activation_alpha
l32i a15, a4, 84 # activation_shift
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a5, 0, dl_tie718_s8_unaligned_relu_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s8_unaligned_relu_11c_0
beqi a13, 8, dl_tie718_s8_unaligned_relu_11c_1
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie718_s8_unaligned_relu_11c_remainder
dl_tie718_s8_unaligned_relu_11c_0:
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_s8_unaligned_relu_11c_remainder
dl_tie718_s8_unaligned_relu_11c_1:
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie718_s8_unaligned_relu_11c_remainder
dl_tie718_s8_unaligned_relu_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a6
rur.sar_byte a11
dl_tie718_s8_unaligned_relu_11c_remainder:
beqz a6, dl_tie728_s8_unaligned_relu_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.VRELU.S8 q2, a14, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a6
dl_tie728_s8_unaligned_relu_11c_end:
retw
|
georgevio/IoT-Embedded
| 15,685
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_lessorequal.S
|
#include "dl_tie728_s8.S"
#void dl_tie728_s8_lessorequal_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_lessorequal_w1_16_w2_16
.type dl_tie728_s8_lessorequal_w1_16_w2_16, @function
#.section .iram1
dl_tie728_s8_lessorequal_w1_16_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
movi a14, 0
tie728_s8_lessorequal_w1_16_w2_16_loop:
beq a14, a5, tie728_s8_lessorequal_w1_16_w2_16_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.lt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s8 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s8 q2, q2, q6
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_lessorequal_w1_16_w2_16_loop
tie728_s8_lessorequal_w1_16_w2_16_end:
retw
#void dl_tie728_s8_lessorequal_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_lessorequal_w1_16_w2_1
.type dl_tie728_s8_lessorequal_w1_16_w2_1, @function
#.section .iram1
dl_tie728_s8_lessorequal_w1_16_w2_1:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s8_lessorequal_w1_16_w2_1_loop:
beq a14, a5, tie728_s8_lessorequal_w1_16_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.lt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s8 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s8 q2, q2, q6
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_lessorequal_w1_16_w2_1_loop
tie728_s8_lessorequal_w1_16_w2_1_end:
retw
#void dl_tie728_s8_lessorequal_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_lessorequal_w1_1_w2_16
.type dl_tie728_s8_lessorequal_w1_1_w2_16, @function
#.section .iram1
dl_tie728_s8_lessorequal_w1_1_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s8_lessorequal_w1_1_w2_16_loop:
beq a14, a5, tie728_s8_lessorequal_w1_1_w2_16_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.lt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s8 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s8 q2, q2, q6
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_lessorequal_w1_1_w2_16_loop
tie728_s8_lessorequal_w1_1_w2_16_end:
retw
.align 4
.text
.global dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned
.type dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_remainder
dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_lessorequal_w1_16_w2_16_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned
.type dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_remainder
dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.lt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_lessorequal_w1_16_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned
.type dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr broadcast
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_remainder
dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.lt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_lessorequal_w1_1_w2_16_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 11,908
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_sub.S
|
#include "dl_tie728_s16.S"
#void dl_tie728_s16_sub_w1_8_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_sub_w1_8_w2_8
.type dl_tie728_s16_sub_w1_8_w2_8, @function
#.section .iram1
dl_tie728_s16_sub_w1_8_w2_8:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 3
movi a14, 0
tie728_s16_sub_w1_8_w2_8_loop:
beq a14, a5, tie728_s16_sub_w1_8_w2_8_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vsubs.s16 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s16_sub_w1_8_w2_8_loop
tie728_s16_sub_w1_8_w2_8_end:
retw
#void dl_tie728_s16_sub_w1_8_w2_1(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_sub_w1_8_w2_1
.type dl_tie728_s16_sub_w1_8_w2_1, @function
#.section .iram1
dl_tie728_s16_sub_w1_8_w2_1:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q1, a4, 0
movi a14, 0
tie728_s16_sub_w1_8_w2_1_loop:
beq a14, a5, tie728_s16_sub_w1_8_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vsubs.s16 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s16_sub_w1_8_w2_1_loop
tie728_s16_sub_w1_8_w2_1_end:
retw
#void dl_tie728_s16_sub_w1_1_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_sub_w1_1_w2_8
.type dl_tie728_s16_sub_w1_1_w2_8, @function
#.section .iram1
dl_tie728_s16_sub_w1_1_w2_8:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q0, a3, 0
movi a14, 0
tie728_s16_sub_w1_1_w2_8_loop:
beq a14, a5, tie728_s16_sub_w1_1_w2_8_end
ee.vld.128.ip q1, a4, 16
ee.vsubs.s16 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s16_sub_w1_1_w2_8_loop
tie728_s16_sub_w1_1_w2_8_end:
retw
.align 4
.text
.global dl_tie728_s16_sub_w1_8_w2_8_unaligned
.type dl_tie728_s16_sub_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_sub_w1_8_w2_8_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s16_sub_w1_8_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s16_sub_w1_8_w2_8_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_sub_w1_8_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s16 q2, q2, q5
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_sub_w1_8_w2_8_unaligned_remainder
// output sar = 0
dl_tie728_s16_sub_w1_8_w2_8_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s16 q2, q2, q5
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_sub_w1_8_w2_8_unaligned_remainder
// output sar = 8
dl_tie728_s16_sub_w1_8_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s16 q2, q2, q5
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_sub_w1_8_w2_8_unaligned_remainder
dl_tie728_s16_sub_w1_8_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_sub_w1_8_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vsubs.s16 q2, q2, q5
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_sub_w1_8_w2_8_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s16_sub_w1_8_w2_1_unaligned
.type dl_tie728_s16_sub_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s16_sub_w1_8_w2_1_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s16_sub_w1_8_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s16_sub_w1_8_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_sub_w1_8_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q2, q5
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_sub_w1_8_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s16_sub_w1_8_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q2, q5
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_sub_w1_8_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s16_sub_w1_8_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q2, q5
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_sub_w1_8_w2_1_unaligned_remainder
dl_tie728_s16_sub_w1_8_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s16_sub_w1_8_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vsubs.s16 q2, q2, q5
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_sub_w1_8_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s16_sub_w1_1_w2_8_unaligned
.type dl_tie728_s16_sub_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_sub_w1_1_w2_8_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr broadcast
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s16_sub_w1_1_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s16_sub_w1_1_w2_8_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_sub_w1_1_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q5, q2
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_sub_w1_1_w2_8_unaligned_remainder
// output sar = 0
dl_tie728_s16_sub_w1_1_w2_8_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q5, q2
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_sub_w1_1_w2_8_unaligned_remainder
// output sar = 8
dl_tie728_s16_sub_w1_1_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vsubs.s16 q2, q5, q2
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_sub_w1_1_w2_8_unaligned_remainder
dl_tie728_s16_sub_w1_1_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_sub_w1_1_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vsubs.s16 q2, q5, q2
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_sub_w1_1_w2_8_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 7,459
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_requantize_linear.S
|
#include "dl_tie728_s16.S"
.text
.align 4
.global dl_tie728_s16_s16_requantize_linear
.type dl_tie728_s16_s16_requantize_linear, @function
dl_tie728_s16_s16_requantize_linear:
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: size_div_x
# a6: in_size_remainder
# a7: tmp value
# a8: output_shift
# a9: output_scale
# a10:
# a11:
# a12(not for extension instructions):
# a13(not for extension instructions):
# a14(not for extension instructions): tmp value
# a15(not for extension instructions):
entry sp, 32
l32i a5, a4, 8 // size_div_x
l32i a6, a4, 12 // in_size_remainder
l32i a8, a4, 20 // output_shift
l32i a9, a4, 24 // output_scale
bgez a9, tie728_s16_s16_requantize_linear_left_shift
beqz a5, tie728_s16_s16_requantize_linear_right_shift_remainder
tie728_s16_s16_requantize_linear_right_shift_loop:
ee.ldqa.s16.128.ip a3, 16
addi a5, a5, -1
tie728_s16_vector_round_result q0, a8, a14, q3
ee.vst.128.ip q0, a2, 16
bnez a5, tie728_s16_s16_requantize_linear_right_shift_loop
tie728_s16_s16_requantize_linear_right_shift_remainder:
beqz a6, tie728_s16_s16_requantize_linear_end
ee.ldqa.s16.128.xp a3, a6
srli a6, a6, 1
tie728_s16_vector_round_result q0, a8, a14, q3
dl_tie728_s16_store_remainder q0, a6, a7, a2
j tie728_s16_s16_requantize_linear_end
tie728_s16_s16_requantize_linear_left_shift:
addi a9, a4, 24
ee.vldbc.16.ip q1, a9, 0 // load output_scale
beqz a5, tie728_s16_s16_requantize_linear_left_shift_remainder
tie728_s16_s16_requantize_linear_left_shift_loop:
ee.vld.128.ip q0, a3, 16
ee.zero.qacc
ee.vmulas.s16.qacc q0, q1
tie728_s16_vector_round_result q0, a8, a14, q3
ee.vst.128.ip q0, a2, 16
addi a5, a5, -1
bnez a5, tie728_s16_s16_requantize_linear_left_shift_loop
tie728_s16_s16_requantize_linear_left_shift_remainder:
beqz a6, tie728_s16_s16_requantize_linear_end
ee.vld.128.ip q0, a3, 16
ee.zero.qacc
ee.vmulas.s16.qacc q0, q1
tie728_s16_vector_round_result q0, a8, a14, q3
srli a6, a6, 1
dl_tie728_s16_store_remainder q0, a6, a7, a2
tie728_s16_s16_requantize_linear_end:
retw
.text
.align 4
.global dl_tie728_s16_s8_requantize_linear
.type dl_tie728_s16_s8_requantize_linear, @function
dl_tie728_s16_s8_requantize_linear:
# a2: int16_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: size_div_x
# a6: in_size_remainder
# a7: out_size_remainder
# a8: output_shift
# a9: output_scale
# a10:
# a11:
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions): tmp value
# a15(not for extension instructions):
entry sp, 32
l32i a5, a4, 8 // size_div_x
l32i a6, a4, 12 // in_size_remainder
l32i a7, a4, 16 // out_size_remainder
l32i a8, a4, 20 // output_shift
l32i a9, a4, 24 // output_scale
bgez a9, tie728_s16_s8_requantize_linear_left_shift
beqz a5, tie728_s16_s8_requantize_linear_right_shift_remainder
srli a12, a5, 1
tie728_s16_s8_requantize_linear_right_shift_loop:
ee.vld.128.ip q0, a3, 16
ee.zero.q q1
ee.vcmp.lt.s8 q1, q0, q1
ee.vzip.8 q0, q1
addi a12, a12, -1
ee.mov.s16.qacc q0
tie728_s16_vector_round_result q0, a8, a14, q3
ee.vst.128.ip q0, a2, 16
ee.mov.s16.qacc q1
tie728_s16_vector_round_result q1, a8, a14, q3
ee.vst.128.ip q1, a2, 16
bnez a12, tie728_s16_s8_requantize_linear_right_shift_loop
tie728_s16_s8_requantize_linear_right_shift_remainder:
beqz a6, tie728_s16_s8_requantize_linear_end
movi a14, 9
blt a6, a14, tie728_s16_s8_requantize_linear_right_shift_remainder_le8
ee.vld.128.xp q0, a3, a6
ee.zero.q q1
ee.vcmp.lt.s8 q1, q0, q1
ee.vzip.8 q0, q1
srli a7, a7, 1
ee.mov.s16.qacc q0
tie728_s16_vector_round_result q0, a8, a14, q3
ee.vst.128.ip q0, a2, 16
ee.mov.s16.qacc q1
tie728_s16_vector_round_result q1, a8, a14, q3
dl_tie728_s16_store_remainder q1, a7, a6, a2
j tie728_s16_s8_requantize_linear_end
tie728_s16_s8_requantize_linear_right_shift_remainder_le8:
ee.vld.128.xp q0, a3, a6
ee.zero.q q1
ee.vcmp.lt.s8 q1, q0, q1
ee.vzip.8 q0, q1
ee.mov.s16.qacc q0
tie728_s16_vector_round_result q0, a8, a14, q3
dl_tie728_s16_store_remainder q0, a6, a7, a2
j tie728_s16_s8_requantize_linear_end
tie728_s16_s8_requantize_linear_left_shift:
addi a9, a4, 24
ee.vldbc.16.ip q2, a9, 0 // load output_scale
beqz a5, tie728_s16_s8_requantize_linear_left_shift_remainder
srli a12, a5, 1
tie728_s16_s8_requantize_linear_left_shift_loop:
ee.vld.128.ip q0, a3, 16
ee.zero.q q1
ee.vcmp.lt.s8 q1, q0, q1
ee.vzip.8 q0, q1
ee.zero.qacc
ee.vmulas.s16.qacc q0, q2
tie728_s16_vector_round_result q0, a8, a14, q3
ee.vst.128.ip q0, a2, 16
ee.zero.qacc
ee.vmulas.s16.qacc q1, q2
tie728_s16_vector_round_result q1, a8, a14, q3
ee.vst.128.ip q1, a2, 16
addi a12, a12, -1
bnez a12, tie728_s16_s8_requantize_linear_left_shift_loop
tie728_s16_s8_requantize_linear_left_shift_remainder:
beqz a6, tie728_s16_s8_requantize_linear_end
movi a14, 9
blt a6, a14, tie728_s16_s8_requantize_linear_left_shift_remainder_le8
srli a7, a7, 1
ee.vld.128.xp q0, a3, a6
ee.zero.q q1
ee.vcmp.lt.s8 q1, q0, q1
ee.vzip.8 q0, q1
ee.zero.qacc
ee.vmulas.s16.qacc q0, q2
tie728_s16_vector_round_result q0, a8, a14, q3
ee.vst.128.ip q0, a2, 16
ee.zero.qacc
ee.vmulas.s16.qacc q1, q2
tie728_s16_vector_round_result q1, a8, a14, q3
dl_tie728_s16_store_remainder q1, a7, a6, a2
j tie728_s16_s8_requantize_linear_end
tie728_s16_s8_requantize_linear_left_shift_remainder_le8:
ee.vld.128.xp q0, a3, a6
ee.zero.q q1
ee.vcmp.lt.s8 q1, q0, q1
ee.vzip.8 q0, q1
ee.zero.qacc
ee.vmulas.s16.qacc q0, q2
tie728_s16_vector_round_result q0, a8, a14, q3
dl_tie728_s16_store_remainder q0, a6, a7, a2
tie728_s16_s8_requantize_linear_end:
retw
|
georgevio/IoT-Embedded
| 6,857
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_requantize_linear.S
|
#include "dl_tie728_s8.S"
.text
.align 4
.global dl_tie728_s8_s8_requantize_linear
.type dl_tie728_s8_s8_requantize_linear, @function
dl_tie728_s8_s8_requantize_linear:
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: size_div_x / tmp value
# a6: in_size_remainder
# a7: tmp value
# a8: output_shift / tmp value
# a9: output_scale / tmp value
# a10:
# a11:
# a12(not for extension instructions):
# a13(not for extension instructions):
# a14(not for extension instructions): tmp value
# a15(not for extension instructions):
entry sp, 32
l32i a5, a4, 8 // size_div_x
l32i a6, a4, 12 // in_size_remainder
l32i a8, a4, 20 // output_shift
l32i a9, a4, 24 // output_scale
bgez a9, tie728_s8_s8_requantize_linear_left_shift
beqz a5, tie728_s8_s8_requantize_linear_right_shift_remainder
tie728_s8_s8_requantize_linear_right_shift_loop:
ee.ldqa.s8.128.ip a3, 16
addi a5, a5, -1
tie728_s8_vector_round_result q0, a8, a14, q3
ee.vst.128.ip q0, a2, 16
bnez a5, tie728_s8_s8_requantize_linear_right_shift_loop
tie728_s8_s8_requantize_linear_right_shift_remainder:
beqz a6, tie728_s8_s8_requantize_linear_end
ee.ldqa.s8.128.xp a3, a6
tie728_s8_vector_round_result q0, a8, a14, q3
dl_tie728_s8_store_remainder q0, a5, a7, a8, a9, a2, a6
j tie728_s8_s8_requantize_linear_end
tie728_s8_s8_requantize_linear_left_shift:
addi a9, a4, 24
ee.vldbc.8.ip q1, a9, 0 // load output_scale
beqz a5, tie728_s8_s8_requantize_linear_left_shift_remainder
tie728_s8_s8_requantize_linear_left_shift_loop:
ee.vld.128.ip q0, a3, 16
ee.zero.qacc
ee.vmulas.s8.qacc q0, q1
tie728_s8_vector_round_result q0, a8, a14, q3
ee.vst.128.ip q0, a2, 16
addi a5, a5, -1
bnez a5, tie728_s8_s8_requantize_linear_left_shift_loop
tie728_s8_s8_requantize_linear_left_shift_remainder:
beqz a6, tie728_s8_s8_requantize_linear_end
ee.vld.128.xp q0, a3, a6
ee.zero.qacc
ee.vmulas.s8.qacc q0, q1
tie728_s8_vector_round_result q0, a8, a14, q3
dl_tie728_s8_store_remainder q0, a5, a7, a8, a9, a2, a6
tie728_s8_s8_requantize_linear_end:
retw
.text
.align 4
.global dl_tie728_s8_s16_requantize_linear
.type dl_tie728_s8_s16_requantize_linear, @function
dl_tie728_s8_s16_requantize_linear:
# a2: int8_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: size_div_x / tmp value
# a6: in_size_remainder / tmp value
# a7: out_size_remainder
# a8: output_shift / tmp value
# a9: output_scale / tmp value
# a10:
# a11:
# a12(not for extension instructions):
# a13(not for extension instructions):
# a14(not for extension instructions): tmp value
# a15(not for extension instructions):
entry sp, 32
l32i a5, a4, 8 // size_div_x
l32i a6, a4, 12 // in_size_remainder
l32i a7, a4, 16 // out_size_remainder
l32i a8, a4, 20 // output_shift
l32i a9, a4, 24 // output_scale
bgez a9, tie728_s8_s16_requantize_linear_left_shift
beqz a5, tie728_s8_s16_requantize_linear_right_shift_remainder
tie728_s8_s16_requantize_linear_right_shift_loop:
ee.ldqa.s16.128.ip a3, 16
tie728_s8_vector_round_result q0, a8, a14, q3
ee.ldqa.s16.128.ip a3, 16
addi a5, a5, -1
tie728_s8_vector_round_result q1, a8, a14, q3
ee.vunzip.8 q0, q1
ee.vst.128.ip q0, a2, 16
bnez a5, tie728_s8_s16_requantize_linear_right_shift_loop
tie728_s8_s16_requantize_linear_right_shift_remainder:
beqz a7, tie728_s8_s16_requantize_linear_end
movi a14, 9
blt a7, a14, tie728_s8_s16_requantize_linear_right_shift_remainder_le8
ee.ldqa.s16.128.ip a3, 16
tie728_s8_vector_round_result q0, a8, a14, q3
ee.ldqa.s16.128.xp a3, a6
tie728_s8_vector_round_result q1, a8, a14, q3
ee.vunzip.8 q0, q1
dl_tie728_s8_store_remainder q0, a5, a6, a8, a9, a2, a7
j tie728_s8_s16_requantize_linear_end
tie728_s8_s16_requantize_linear_right_shift_remainder_le8:
ee.ldqa.s16.128.xp a3, a6
ee.zero.q q1
tie728_s8_vector_round_result q0, a8, a14, q3
ee.vunzip.8 q0, q1
dl_tie728_s8_store_remainder q0, a5, a6, a8, a9, a2, a7
j tie728_s8_s16_requantize_linear_end
tie728_s8_s16_requantize_linear_left_shift:
addi a9, a4, 24
ee.vldbc.16.ip q2, a9, 0 // load output_scale
beqz a5, tie728_s8_s16_requantize_linear_left_shift_remainder
tie728_s8_s16_requantize_linear_left_shift_loop:
ee.vld.128.ip q0, a3, 16
ee.zero.qacc
ee.vmulas.s16.qacc q0, q2
tie728_s8_vector_round_result q0, a8, a14, q3
ee.vld.128.ip q1, a3, 16
ee.zero.qacc
ee.vmulas.s16.qacc q1, q2
tie728_s8_vector_round_result q1, a8, a14, q3
ee.vunzip.8 q0, q1
ee.vst.128.ip q0, a2, 16
addi a5, a5, -1
bnez a5, tie728_s8_s16_requantize_linear_left_shift_loop
tie728_s8_s16_requantize_linear_left_shift_remainder:
beqz a7, tie728_s8_s16_requantize_linear_end
movi a14, 9
blt a7, a14, tie728_s8_s16_requantize_linear_left_shift_remainder_le8
ee.vld.128.ip q0, a3, 16
ee.zero.qacc
ee.vmulas.s16.qacc q0, q2
tie728_s8_vector_round_result q0, a8, a14, q3
ee.vld.128.xp q1, a3, a6
ee.zero.qacc
ee.vmulas.s16.qacc q1, q2
tie728_s8_vector_round_result q1, a8, a14, q3
ee.vunzip.8 q0, q1
dl_tie728_s8_store_remainder q0, a5, a6, a8, a9, a2, a7
j tie728_s8_s16_requantize_linear_end
tie728_s8_s16_requantize_linear_left_shift_remainder_le8:
ee.vld.128.xp q0, a3, a6
ee.zero.qacc
ee.vmulas.s16.qacc q0, q2
tie728_s8_vector_round_result q0, a8, a14, q3
ee.zero.q q1
ee.vunzip.8 q0, q1
dl_tie728_s8_store_remainder q0, a5, a6, a8, a9, a2, a7
tie728_s8_s16_requantize_linear_end:
retw
|
georgevio/IoT-Embedded
| 11,908
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_add.S
|
#include "dl_tie728_s16.S"
#void dl_tie728_s16_add_w1_8_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_add_w1_8_w2_8
.type dl_tie728_s16_add_w1_8_w2_8, @function
#.section .iram1
dl_tie728_s16_add_w1_8_w2_8:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 3
movi a14, 0
tie728_s16_add_w1_8_w2_8_loop:
beq a14, a5, tie728_s16_add_w1_8_w2_8_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vadds.s16 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s16_add_w1_8_w2_8_loop
tie728_s16_add_w1_8_w2_8_end:
retw
#void dl_tie728_s16_add_w1_8_w2_1(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_add_w1_8_w2_1
.type dl_tie728_s16_add_w1_8_w2_1, @function
#.section .iram1
dl_tie728_s16_add_w1_8_w2_1:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q1, a4, 0
movi a14, 0
tie728_s16_add_w1_8_w2_1_loop:
beq a14, a5, tie728_s16_add_w1_8_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vadds.s16 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s16_add_w1_8_w2_1_loop
tie728_s16_add_w1_8_w2_1_end:
retw
#void dl_tie728_s16_add_w1_1_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_add_w1_1_w2_8
.type dl_tie728_s16_add_w1_1_w2_8, @function
#.section .iram1
dl_tie728_s16_add_w1_1_w2_8:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q0, a3, 0
movi a14, 0
tie728_s16_add_w1_1_w2_8_loop:
beq a14, a5, tie728_s16_add_w1_1_w2_8_end
ee.vld.128.ip q1, a4, 16
ee.vadds.s16 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s16_add_w1_1_w2_8_loop
tie728_s16_add_w1_1_w2_8_end:
retw
.align 4
.text
.global dl_tie728_s16_add_w1_8_w2_8_unaligned
.type dl_tie728_s16_add_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_add_w1_8_w2_8_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s16_add_w1_8_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s16_add_w1_8_w2_8_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_add_w1_8_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s16 q2, q2, q5
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_add_w1_8_w2_8_unaligned_remainder
// output sar = 0
dl_tie728_s16_add_w1_8_w2_8_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s16 q2, q2, q5
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_add_w1_8_w2_8_unaligned_remainder
// output sar = 8
dl_tie728_s16_add_w1_8_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s16 q2, q2, q5
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_add_w1_8_w2_8_unaligned_remainder
dl_tie728_s16_add_w1_8_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_add_w1_8_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vadds.s16 q2, q2, q5
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_add_w1_8_w2_8_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s16_add_w1_8_w2_1_unaligned
.type dl_tie728_s16_add_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s16_add_w1_8_w2_1_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s16_add_w1_8_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s16_add_w1_8_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_add_w1_8_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q2, q5
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_add_w1_8_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s16_add_w1_8_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q2, q5
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_add_w1_8_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s16_add_w1_8_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q2, q5
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_add_w1_8_w2_1_unaligned_remainder
dl_tie728_s16_add_w1_8_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s16_add_w1_8_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vadds.s16 q2, q2, q5
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_add_w1_8_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s16_add_w1_1_w2_8_unaligned
.type dl_tie728_s16_add_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_add_w1_1_w2_8_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr broadcast
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s16_add_w1_1_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s16_add_w1_1_w2_8_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_add_w1_1_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q5, q2
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_add_w1_1_w2_8_unaligned_remainder
// output sar = 0
dl_tie728_s16_add_w1_1_w2_8_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q5, q2
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_add_w1_1_w2_8_unaligned_remainder
// output sar = 8
dl_tie728_s16_add_w1_1_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vadds.s16 q2, q5, q2
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_add_w1_1_w2_8_unaligned_remainder
dl_tie728_s16_add_w1_1_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_add_w1_1_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vadds.s16 q2, q5, q2
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_add_w1_1_w2_8_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 12,249
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_max_pool2d.S
|
#include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### dl_tie728_s16_max_pool2d series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_max_pool2d_22c1
.type dl_tie728_s16_max_pool2d_22c1, @function
.section .iram1
dl_tie728_s16_max_pool2d_22c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: input_y_offset_bytes
# a6: input_x_offset_bytes
# a10: c_div_x_1
l32i a5, a4, 16 # input_y_offset_bytes
l32i a6, a4, 20 # input_x_offset_bytes
l32i a10, a4, 104 # c_div_x_1
add a7, a3, a6
add a8, a3, a5
add a9, a8, a6
0:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a7, 16
loopgtz a10, 1f
EE.VMAX.S16.LD.INCP q2, a8, q7, q0, q1
EE.VMAX.S16.LD.INCP q3, a9, q7, q7, q2
EE.VMAX.S16.LD.INCP q0, a3, q7, q7, q3
EE.VST.128.IP q7, a2, 16
EE.VLD.128.IP q1, a7, 16
1:
EE.VMAX.S16.LD.INCP q2, a8, q7, q0, q1
EE.VMAX.S16.LD.INCP q3, a9, q7, q7, q2
EE.VMAX.S16 q7, q7, q3
EE.VST.128.IP q7, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_unaligned_max_pool2d_22c1
.type dl_tie728_s16_unaligned_max_pool2d_22c1, @function
.section .iram1
dl_tie728_s16_unaligned_max_pool2d_22c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: input_y_offset_bytes
# a6: input_x_offset_bytes
# a10: c_div_x_1
# a12: c_remainder_bytes
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a10, a4, 104
l32i a12, a4, 60 # c_remainder
add a7, a3, a6
add a8, a3, a5
add a9, a8, a6
blti a10, 0, dl_tie728_s16_unaligned_max_pool2d_22c1_remainder
EE.LD.128.USAR.IP q0, a2, 0
RUR.SAR_BYTE a13
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q1, a3, 0
beqi a13, 0, 0f
beqi a13, 8, 8f
loopgtz a10, 1f
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMAX.S16 q7, q0, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMAX.S16 q7, q7, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMAX.S16 q7, q7, q2
dl_tie728_128b_unaligned_store0 q7, a2, a13
1:
j dl_tie728_s16_unaligned_max_pool2d_22c1_end
0:
loopgtz a10, 2f
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMAX.S16 q7, q0, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMAX.S16 q7, q7, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMAX.S16 q7, q7, q2
EE.VST.128.IP q7, a2, 16
2:
j dl_tie728_s16_unaligned_max_pool2d_22c1_end
8:
loopgtz a10, 3f
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMAX.S16 q7, q0, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMAX.S16 q7, q7, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMAX.S16 q7, q7, q2
dl_tie728_128b_unaligned_store1 q7, a2
3:
j dl_tie728_s16_unaligned_max_pool2d_22c1_end
dl_tie728_s16_unaligned_max_pool2d_22c1_end:
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMAX.S16 q7, q0, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMAX.S16 q7, q7, q4
EE.SRC.Q q2, q2, q3
EE.VMAX.S16 q7, q7, q2
dl_tie728_128b_unaligned_store0 q7, a2, a13
beqz a12, 4f
dl_tie728_s16_unaligned_max_pool2d_22c1_remainder:
EE.LD.128.USAR.XP q0, a3, a12
EE.VLD.128.IP q1, a3, 0
EE.SRC.Q q0, q0, q1
EE.LD.128.USAR.XP q2, a7, a12
EE.VLD.128.IP q3, a7, 0
EE.SRC.Q q2, q2, q3
EE.LD.128.USAR.XP q4, a8, a12
EE.VLD.128.IP q5, a8, 0
EE.VMAX.S16 q7, q0, q2
EE.SRC.Q q4, q4, q5
EE.LD.128.USAR.XP q0, a9, a12
EE.VLD.128.IP q1, a9, 0
EE.VMAX.S16 q7, q7, q4
EE.SRC.Q q0, q0, q1
EE.VMAX.S16 q7, q7, q0
srli a12, a12, 1
dl_tie728_s16_store_remainder q7, a12, a14, a2
4:
retw
.align 4
.text
.global dl_tie728_s16_max_pool2d_hwc1
.type dl_tie728_s16_max_pool2d_hwc1, @function
.section .iram1
dl_tie728_s16_max_pool2d_hwc1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: input_y_offset
# a6: input_x_offset
# a7: c_div_x_1
# a8: filter_height
# a9: filter_width
# a10: filter_width/2 - 1
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a7, a4, 104 # c_div_x_1
l32i a8, a4, 48 # filter_height
l32i a9, a4, 52 # filter_width
srli a10, a9, 1
addi a10, a10, -1 # w / 2 - 1
blti a9, 2, dl_tie728_s16_max_pool2d_h1c1_loop
blti a7, 1, dl_tie728_s16_max_pool2d_hwc1_small_channel
1: # loop c
mov a11, a3
mov a13, a11
EE.VLD.128.IP q7, a13, 0
mov a14, a8
2: # loop h
EE.VLD.128.XP q0, a13, a6
loopgtz a10, 3f # loop w
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.VLD.128.XP q0, a13, a6
EE.VMAX.S16 q7, q7, q1
3:
bbci a9, 0, 4f
# w left 3
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.VLD.128.XP q0, a13, a6
EE.VMAX.S16 q7, q7, q1
EE.VMAX.S16 q7, q7, q0
j 5f
4: # w left 2
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.VMAX.S16 q7, q7, q1
5:
addi a14, a14, -1
add a11, a11, a5
mov a13, a11
bnez a14, 2b
6:
EE.VST.128.IP q7, a2, 16
addi a3, a3, 16
addi a7, a7, -1
bnez a7, 1b
dl_tie728_s16_max_pool2d_hwc1_small_channel:
mov a11, a3
mov a13, a11
EE.VLD.128.IP q7, a13, 0
mov a14, a8
2: # loop h
EE.VLD.128.XP q0, a13, a6
loopgtz a10, 3f # loop w
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.VLD.128.XP q0, a13, a6
EE.VMAX.S16 q7, q7, q1
3:
bbci a9, 0, 4f
# w left 3
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.VLD.128.XP q0, a13, a6
EE.VMAX.S16 q7, q7, q1
EE.VMAX.S16 q7, q7, q0
j 5f
4: # w left 2
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.VMAX.S16 q7, q7, q1
5:
addi a14, a14, -1
add a11, a11, a5
mov a13, a11
bnez a14, 2b
6:
EE.VST.128.IP q7, a2, 16
retw
dl_tie728_s16_max_pool2d_h1c1_loop:
blti a7, 1, dl_tie728_s16_max_pool2d_h1c1_small_channel
1:
mov a13, a3
EE.VLD.128.IP q7, a13, 0
loopgtz a8, 2f
EE.VLD.128.XP q0, a13, a5
EE.VMAX.S16 q7, q7, q0
2:
EE.VST.128.IP q7, a2, 16
addi a3, a3, 16
addi a7, a7, -1
bnez a7, 1b
dl_tie728_s16_max_pool2d_h1c1_small_channel:
mov a13, a3
EE.VLD.128.IP q7, a13, 0
loopgtz a8, 1f
EE.VLD.128.XP q0, a13, a5
EE.VMAX.S16 q7, q7, q0
1:
EE.VST.128.IP q7, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_unaligned_max_pool2d_hwc1
.type dl_tie728_s16_unaligned_max_pool2d_hwc1, @function
.section .iram1
dl_tie728_s16_unaligned_max_pool2d_hwc1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: input_y_offset
# a6: input_x_offset
# a7: c_div_x_1
# a8: filter_height
# a9: filter_width
# a10: filter_width/2 - 1
# a12: c_remainder_bytes
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a7, a4, 104 # c_div_x_1
l32i a8, a4, 48 # filter_height
l32i a9, a4, 52 # filter_width
l32i a12, a4, 60 # c_remainder_bytes
srli a10, a9, 1
addi a10, a10, -1 # w/2-1
addi a6, a6, -16
EE.LD.128.USAR.IP q0, a2, 0
RUR.SAR_BYTE a15
addi a7, a7, 1
blti a9, 2, dl_tie728_s16_unaligned_max_pool2d_h1c1_loop
blti a7, 1, dl_tie728_s16_unaligned_max_pool2d_hwc1_small_channel
1: # loop c
mov a11, a3
mov a13, a11
EE.LD.128.USAR.IP q0, a13, 16
EE.LD.128.USAR.IP q1, a13, -16
EE.SRC.Q q7, q0, q1
mov a14, a8
2: # loop h
EE.LD.128.USAR.IP q0, a13, 16
EE.LD.128.USAR.XP q1, a13, a6
loopgtz a10, 3f # loop w
EE.SRC.Q.LD.IP q2, a13, 16, q0, q1
EE.LD.128.USAR.XP q3, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.SRC.Q.LD.IP q0, a13, 16, q2, q3
EE.LD.128.USAR.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q2
3:
bbci a9, 0, 4f
# w left 3
EE.SRC.Q.LD.IP q2, a13, 16, q0, q1
EE.LD.128.USAR.XP q3, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.SRC.Q.LD.IP q0, a13, 16, q2, q3
EE.LD.128.USAR.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q2
EE.SRC.Q q0, q0, q1
EE.VMAX.S16 q7, q7, q0
j 5f
4: # w left 2
EE.SRC.Q.LD.IP q2, a13, 16, q0, q1
EE.LD.128.USAR.XP q3, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.SRC.Q q2, q2, q3
EE.VMAX.S16 q7, q7, q2
5:
addi a14, a14, -1
add a11, a11, a5
mov a13, a11
bnez a14, 2b
6:
beqi a15, 0, 7f
beqi a15, 8, 8f
dl_tie728_128b_unaligned_store0 q7, a2, a14
j 9f
7:
EE.VST.128.IP q7, a2, 16
j 9f
8:
dl_tie728_128b_unaligned_store1 q7, a2
9:
addi a3, a3, 16
addi a7, a7, -1
bnez a7, 1b
dl_tie728_s16_unaligned_max_pool2d_hwc1_small_channel:
beqz a12, 9f
mov a11, a3
mov a13, a11
EE.LD.128.USAR.IP q0, a13, 16
EE.LD.128.USAR.IP q1, a13, -16
EE.SRC.Q q7, q0, q1
mov a14, a8
2: # loop h
EE.LD.128.USAR.IP q0, a13, 16
EE.LD.128.USAR.XP q1, a13, a6
loopgtz a10, 3f # loop w
EE.SRC.Q.LD.IP q2, a13, 16, q0, q1
EE.LD.128.USAR.XP q3, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.SRC.Q.LD.IP q0, a13, 16, q2, q3
EE.LD.128.USAR.XP q1, a13, a6
EE.VMAX.S16 q7, q7, q2
3:
bbci a9, 0, 4f
# w left 3
EE.SRC.Q.LD.IP q2, a13, 16, q0, q1
EE.LD.128.USAR.XP q3, a13, a6
EE.VMAX.S16 q7, q7, q0
EE.SRC.Q q2, q2, q3
EE.LD.128.USAR.XP q0, a13, a12
EE.VLD.128.IP q1, a13, 0
EE.VMAX.S16 q7, q7, q2
EE.SRC.Q q0, q0, q1
EE.VMAX.S16 q7, q7, q0
j 5f
4: # w left 2
EE.SRC.Q q0, q0, q1
EE.LD.128.USAR.XP q2, a13, a12
EE.VLD.128.IP q3, a13, 0
EE.VMAX.S16 q7, q7, q0
EE.SRC.Q q2, q2, q3
EE.VMAX.S16 q7, q7, q2
5:
addi a14, a14, -1
add a11, a11, a5
mov a13, a11
bnez a14, 2b
6:
srli a12, a12, 1
dl_tie728_s16_store_remainder q7, a12, a14, a2
9:
retw
dl_tie728_s16_unaligned_max_pool2d_h1c1_loop:
addi a5, a5, -16
blti a7, 1, dl_tie728_s16_unaligned_max_pool2d_h1c1_small_channel
1:
mov a13, a3
EE.LD.128.USAR.IP q0, a13, 16
EE.LD.128.USAR.IP q1, a13, -16
EE.SRC.Q q7, q0, q1
loopgtz a8, 2f
EE.LD.128.USAR.IP q0, a13, 16
EE.LD.128.USAR.XP q1, a13, a5
EE.SRC.Q q0, q0, q1
EE.VMAX.S16 q7, q7, q0
2:
beqi a15, 0, 3f
beqi a15, 8, 4f
dl_tie728_128b_unaligned_store0 q7, a2, a14
j 5f
3:
EE.VST.128.IP q7, a2, 16
j 5f
4:
dl_tie728_128b_unaligned_store1 q7, a2
5:
addi a3, a3, 16
addi a7, a7, -1
bnez a7, 1b
dl_tie728_s16_unaligned_max_pool2d_h1c1_small_channel:
beqz a12, 5f
mov a13, a3
EE.LD.128.USAR.XP q0, a13, a12
EE.VLD.128.IP q1, a13, 0
EE.SRC.Q q7, q0, q1
sub a13, a13, a12
addi a5, a5, 16
sub a5, a5, a12
loopgtz a8, 1f
EE.LD.128.USAR.XP q0, a13, a12
EE.VLD.128.XP q1, a13, a5
EE.SRC.Q q0, q0, q1
EE.VMAX.S16 q7, q7, q0
1:
srli a12, a12, 1
dl_tie728_s16_store_remainder q7, a12, a14, a2
5:
retw
|
georgevio/IoT-Embedded
| 27,267
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_conv2d.S
|
#include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_conv2d_11cn series
####
############################################################################################################################################################
.macro tie728_s16_conv2d_11c8 input_v0 filter_v0 filter_v1 input_ptr filter_ptr c_div_x_1
# scalar * vecter and accumulate into QACC
# input_ptr += (c_div_x_1 + 1) * 16 in the end
# filter_ptr point to the next 16 bytes in the end
# input_v0: 8 input elements
# filter_v0: 8 filter elements
# filter_v1: 8 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 8 - 1
EE.VLD.128.IP \input_v0, \input_ptr, 16
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
loopgtz \c_div_x_1, 0f
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S16.QACC.LD.INCP \input_v0, \input_ptr, \filter_v1, \input_v0, 7
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
0:
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S16.QACC \filter_v0, \input_v0, 6
EE.VSMULAS.S16.QACC \filter_v1, \input_v0, 7
.endm
.macro tie728_s16_conv2d_11cn_load_args args filter_ptr c_div_x_1 n_rs3 mac_shift
l32i \n_rs3, \args, 96 // output_channel_div_8
l32i \mac_shift, \args, 64 // mac_shift
l32i \filter_ptr, \args, 48 // filter
l32i \c_div_x_1, \args, 100 // input_channel / x - 1
.endm
.align 4
.text
.global dl_tie728_s16_conv2d_11cn_bias
.type dl_tie728_s16_conv2d_11cn_bias, @function
# .section .iram1
dl_tie728_s16_conv2d_11cn_bias:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_11cn_load_args a4, a5, a6, a7, a8
l32i a11, a4, 68 // bias
# l32i a12, a4, 76 // activation_alpha
# l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_11cn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_conv2d_11c8 q0, q1, q2, a15, a5, a6
tie728_s16_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_11cn_bias_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_11cn_bias_relu
.type dl_tie728_s16_conv2d_11cn_bias_relu, @function
# .section .iram1
dl_tie728_s16_conv2d_11cn_bias_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_11cn_load_args a4, a5, a6, a7, a8
l32i a11, a4, 68 // bias
l32i a12, a4, 76 // activation_alpha
l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_11cn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_conv2d_11c8 q0, q1, q2, a15, a5, a6
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_11cn_bias_relu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_11cn_bias_prelu
.type dl_tie728_s16_conv2d_11cn_bias_prelu, @function
# .section .iram1
dl_tie728_s16_conv2d_11cn_bias_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_11cn_load_args a4, a5, a6, a7, a8
l32i a11, a4, 68 // bias
l32i a12, a4, 80 // activation_alpha_ptr
l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_11cn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_conv2d_11c8 q0, q1, q2, a15, a5, a6
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_11cn_bias_prelu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_11cn
.type dl_tie728_s16_conv2d_11cn, @function
# .section .iram1
dl_tie728_s16_conv2d_11cn:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_11cn_load_args a4, a5, a6, a7, a8
# l32i a11, a4, 68 // bias
# l32i a12, a4, 76 // activation_alpha
# l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_11cn_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_11c8 q0, q1, q2, a15, a5, a6
tie728_s16_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_11cn_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_11cn_relu
.type dl_tie728_s16_conv2d_11cn_relu, @function
# .section .iram1
dl_tie728_s16_conv2d_11cn_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_11cn_load_args a4, a5, a6, a7, a8
# l32i a11, a4, 68 // bias
l32i a12, a4, 76 // activation_alpha
l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_11cn_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_11c8 q0, q1, q2, a15, a5, a6
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_11cn_relu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_11cn_prelu
.type dl_tie728_s16_conv2d_11cn_prelu, @function
# .section .iram1
dl_tie728_s16_conv2d_11cn_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_11cn_load_args a4, a5, a6, a7, a8
# l32i a11, a4, 68 // bias
l32i a12, a4, 80 // activation_alpha_ptr
l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_11cn_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_11c8 q0, q1, q2, a15, a5, a6
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_prelu q0, q1, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_11cn_prelu_loop
retw
############################################################################################################################################################
####
#### tie728_s16_conv2d_33cn series
####
############################################################################################################################################################
.macro tie728_s16_conv2d_33c8 input_v0 filter_v0 filter_v1 input_ptr filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro tie728_s16_conv2d_hwcn_load_args args filter_ptr c_div_x_1 n_rs3 mac_shift dilation_x_offset dilation_y_offset
tie728_s16_conv2d_11cn_load_args \args, \filter_ptr, \c_div_x_1, \n_rs3, \mac_shift
l32i \dilation_x_offset, \args, 108 // input dilation x offset
l32i \dilation_y_offset, \args, 112 // input dilation y offset
.endm
.align 4
.text
.global dl_tie728_s16_conv2d_33cn_bias
.type dl_tie728_s16_conv2d_33cn_bias, @function
# .section .iram1
dl_tie728_s16_conv2d_33cn_bias:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: bias_ptr
# a12:
# a13:
# a14
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a11, a4, 68 // bias
# l32i a12, a4, 76 // activation_alpha
# l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_33cn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_conv2d_33c8 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s16_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_33cn_bias_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_33cn_bias_relu
.type dl_tie728_s16_conv2d_33cn_bias_relu, @function
# .section .iram1
dl_tie728_s16_conv2d_33cn_bias_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: bias_ptr
# a12: activation_alpha
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a11, a4, 68 // bias
l32i a12, a4, 76 // activation_alpha
l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_33cn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_conv2d_33c8 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_33cn_bias_relu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_33cn_bias_prelu
.type dl_tie728_s16_conv2d_33cn_bias_prelu, @function
# .section .iram1
dl_tie728_s16_conv2d_33cn_bias_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: bias_ptr
# a12: activation_alpha_ptr
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a11, a4, 68 // bias
l32i a12, a4, 80 // activation_alpha_ptr
l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_33cn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_conv2d_33c8 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_33cn_bias_prelu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_33cn
.type dl_tie728_s16_conv2d_33cn, @function
# .section .iram1
dl_tie728_s16_conv2d_33cn:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11:
# a12:
# a13:
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
# l32i a11, a4, 68 // bias
# l32i a12, a4, 76 // activation_alpha
# l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_33cn_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_33c8 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s16_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_33cn_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_33cn_relu
.type dl_tie728_s16_conv2d_33cn_relu, @function
# .section .iram1
dl_tie728_s16_conv2d_33cn_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11:
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
# l32i a11, a4, 68 // bias
l32i a12, a4, 76 // activation_alpha
l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_33cn_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_33c8 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_33cn_relu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_33cn_prelu
.type dl_tie728_s16_conv2d_33cn_prelu, @function
# .section .iram1
dl_tie728_s16_conv2d_33cn_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11:
# a12: activation_alpha_ptr
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
# l32i a11, a4, 68 // bias
l32i a12, a4, 80 // activation_alpha_ptr
l32i a13, a4, 84 // activation_shift
tie728_s16_conv2d_33cn_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_33c8 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_prelu q0, q1, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_33cn_prelu_loop
retw
############################################################################################################################################################
####
#### tie728_s16_conv2d_hwcn series
####
############################################################################################################################################################
.macro tie728_s16_conv2d_hwc8 input_v0 filter_v0 filter_v1 input_ptr filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset filter_h filter_w args filter_offset_q
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
# filter_h
# filter_w
l32i \filter_h, \args, 52 # filter_height
1:
l32i \filter_w, \args, 56 # filter_width
beqi \filter_w, 1, 3f
2:
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bgei \filter_w, 2, 2b
3:
tie728_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
add \filter_ptr, \filter_ptr, \filter_w
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 1b
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.align 4
.text
.global dl_tie728_s16_conv2d_hwcn_bias
.type dl_tie728_s16_conv2d_hwcn_bias, @function
# .section .iram1
dl_tie728_s16_conv2d_hwcn_bias:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height
# a12: filter_width
# a13: bias_ptr
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a12, a4, 60 # filter_y_offset
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1 #filter_y_offset
EE.MOVI.32.Q q6, a11, 2 #filter_n_offset
l32i a13, a4, 68 // bias
tie728_s16_conv2d_hwcn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_conv2d_hwc8 q0, q1, q2, a15, a5, a6, a9, a10, a11, a12, a4, q6
tie728_s16_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_hwcn_bias_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_hwcn_bias_relu
.type dl_tie728_s16_conv2d_hwcn_bias_relu, @function
# .section .iram1
dl_tie728_s16_conv2d_hwcn_bias_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height
# a12: filter_width
# a13: bias_ptr
# a14: activation_alpha
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a12, a4, 60 # filter_y_offset
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1 #filter_y_offset
EE.MOVI.32.Q q6, a11, 2 #filter_n_offset
l32i a13, a4, 68 // bias
l32i a14, a4, 76 // activation_alpha
tie728_s16_conv2d_hwcn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_conv2d_hwc8 q0, q1, q2, a15, a5, a6, a9, a10, a11, a12, a4, q6
l32i a11, a4, 84 // activation_shift
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_relu q0, a14, a11
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_hwcn_bias_relu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_hwcn_bias_prelu
.type dl_tie728_s16_conv2d_hwcn_bias_prelu, @function
# .section .iram1
dl_tie728_s16_conv2d_hwcn_bias_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height
# a12: filter_width
# a13: bias_ptr
# a14: activation_alpha_ptr
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a12, a4, 60 # filter_y_offset
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1 #filter_y_offset
EE.MOVI.32.Q q6, a11, 2 #filter_n_offset
l32i a13, a4, 68 // bias_ptr
l32i a14, a4, 80 // activation_alpha_ptr
tie728_s16_conv2d_hwcn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_conv2d_hwc8 q0, q1, q2, a15, a5, a6, a9, a10, a11, a12, a4, q6
l32i a11, a4, 84 // activation_shift
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_prelu q0, q2, a14, a11
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_hwcn_bias_prelu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_hwcn
.type dl_tie728_s16_conv2d_hwcn, @function
# .section .iram1
dl_tie728_s16_conv2d_hwcn:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height
# a12: filter_width
# a13:
# a14:
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a12, a4, 60 # filter_y_offset
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1 #filter_y_offset
EE.MOVI.32.Q q6, a11, 2 #filter_n_offset
# l32i a13, a4, 68 // bias
tie728_s16_conv2d_hwcn_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_hwc8 q0, q1, q2, a15, a5, a6, a9, a10, a11, a12, a4, q6
tie728_s16_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_hwcn_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_hwcn_relu
.type dl_tie728_s16_conv2d_hwcn_relu, @function
# .section .iram1
dl_tie728_s16_conv2d_hwcn_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height
# a12: filter_width
# a13: activation_alpha
# a14: activation_shift
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a12, a4, 60 # filter_y_offset
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1 #filter_y_offset
EE.MOVI.32.Q q6, a11, 2 #filter_n_offset
l32i a13, a4, 76 // activation_alpha
l32i a14, a4, 84 // activation_shift
tie728_s16_conv2d_hwcn_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_hwc8 q0, q1, q2, a15, a5, a6, a9, a10, a11, a12, a4, q6
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_relu q0, a13, a14
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_hwcn_relu_loop
retw
.align 4
.text
.global dl_tie728_s16_conv2d_hwcn_prelu
.type dl_tie728_s16_conv2d_hwcn_prelu, @function
# .section .iram1
dl_tie728_s16_conv2d_hwcn_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height
# a12: filter_width
# a13: activation_prelu_ptr
# a14: activation_shift
# a15: moving_input_ptr
tie728_s16_conv2d_hwcn_load_args a4, a5, a6, a7, a8, a9, a10
l32i a12, a4, 60 # filter_y_offset
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1 #filter_y_offset
EE.MOVI.32.Q q6, a11, 2 #filter_n_offset
l32i a13, a4, 80 // activation_alpha_ptr
l32i a14, a4, 84 // activation_shift
tie728_s16_conv2d_hwcn_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_hwc8 q0, q1, q2, a15, a5, a6, a9, a10, a11, a12, a4, q6
tie728_s16_vector_round_result q0, a8, a15, q3
tie728_s16_conv2d_prelu q0, q1, a13, a14
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s16_conv2d_hwcn_prelu_loop
retw
|
georgevio/IoT-Embedded
| 17,114
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_mul.S
|
#include "dl_tie728_s8.S"
#void dl_tie728_s8_mul_w1_16_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_mul_w1_16_w2_16
.type dl_tie728_s8_mul_w1_16_w2_16, @function
#.section .iram1
dl_tie728_s8_mul_w1_16_w2_16:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a8:
# a9:
# a10:
# a11:
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a7, a5, 80
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
mov a14, a6
blti a14, 1, dl_tie728_s8_mul_w1_16_w2_16_loop_last
dl_tie728_s8_mul_w1_16_w2_16_loop:
ee.zero.qacc
ee.vmulas.s8.qacc.ld.ip q0, a3, 16, q0, q1
ee.vld.128.ip q1, a4, 16
tie728_s8_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, dl_tie728_s8_mul_w1_16_w2_16_loop
dl_tie728_s8_mul_w1_16_w2_16_loop_last:
ee.zero.qacc
ee.vmulas.s8.qacc q0, q1
tie728_s8_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
retw
#void dl_tie728_s8_mul_w1_16_w2_1(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_mul_w1_16_w2_1
.type dl_tie728_s8_mul_w1_16_w2_1, @function
#.section .iram1
dl_tie728_s8_mul_w1_16_w2_1:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a8:
# a9:
# a10:
# a11:
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a7, a5, 80
ee.vld.128.ip q0, a3, 16
ee.vldbc.8.ip q1, a4, 0 // input1 broadcast
mov a14, a6
blti a14, 1, dl_tie728_s8_mul_w1_16_w2_1_loop_last
dl_tie728_s8_mul_w1_16_w2_1_loop:
ee.zero.qacc
ee.vmulas.s8.qacc.ld.ip q0, a3, 16, q0, q1
tie728_s8_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, dl_tie728_s8_mul_w1_16_w2_1_loop
dl_tie728_s8_mul_w1_16_w2_1_loop_last:
ee.zero.qacc
ee.vmulas.s8.qacc q0, q1
tie728_s8_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
retw
#void dl_tie728_s8_mul_w1_1_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_mul_w1_1_w2_16
.type dl_tie728_s8_mul_w1_1_w2_16, @function
#.section .iram1
dl_tie728_s8_mul_w1_1_w2_16:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a8:
# a9:
# a10:
# a11:
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a7, a5, 80
ee.vldbc.8.ip q0, a3, 0 // input0 broadcast
ee.vld.128.ip q1, a4, 16
mov a14, a6
blti a14, 1, dl_tie728_s8_mul_w1_1_w2_16_loop_last
dl_tie728_s8_mul_w1_1_w2_16_loop:
ee.zero.qacc
ee.vmulas.s8.qacc.ld.ip q1, a4, 16, q0, q1
tie728_s8_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, dl_tie728_s8_mul_w1_1_w2_16_loop
dl_tie728_s8_mul_w1_1_w2_16_loop_last:
ee.zero.qacc
ee.vmulas.s8.qacc q0, q1
tie728_s8_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_mul_w1_16_w2_16_unaligned
.type dl_tie728_s8_mul_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_mul_w1_16_w2_16_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11: mul_shift
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
l32i a11, a5, 80
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s8_mul_w1_16_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_mul_w1_16_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_mul_w1_16_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_mul_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_mul_w1_16_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_mul_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_mul_w1_16_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_mul_w1_16_w2_16_unaligned_remainder
dl_tie728_s8_mul_w1_16_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_mul_w1_16_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.zero.qacc
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_mul_w1_16_w2_16_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s8_mul_w1_16_w2_1_unaligned
.type dl_tie728_s8_mul_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s8_mul_w1_16_w2_1_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11: mul_shift
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
l32i a11, a5, 80
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s8_mul_w1_16_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_mul_w1_16_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_mul_w1_16_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_mul_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s8_mul_w1_16_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_mul_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s8_mul_w1_16_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_mul_w1_16_w2_1_unaligned_remainder
dl_tie728_s8_mul_w1_16_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s8_mul_w1_16_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.zero.qacc
ee.src.q q2, q0, q1
ee.vmulas.s8.qacc q2, q5
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_mul_w1_16_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s8_mul_w1_1_w2_16_unaligned
.type dl_tie728_s8_mul_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_mul_w1_1_w2_16_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr broadcast
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11: mul_shift
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
l32i a11, a5, 80
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s8_mul_w1_1_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s8_mul_w1_1_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_mul_w1_1_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q5, q2
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q5, q2
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_mul_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_mul_w1_1_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q5, q2
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q5, q2
tie728_s8_vector_round_result q2, a11, a12, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_mul_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_mul_w1_1_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q5, q2
tie728_s8_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q5, q2
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_mul_w1_1_w2_16_unaligned_remainder
dl_tie728_s8_mul_w1_1_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_mul_w1_1_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.zero.qacc
ee.src.q q2, q0, q1
ee.vmulas.s8.qacc q5, q2
tie728_s8_vector_round_result q2, a11, a12, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_mul_w1_1_w2_16_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 13,784
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_avg_pool2d.S
|
############################################################################################################################################################
####
#### dl_tie728_s8_avg_pool2d series
####
############################################################################################################################################################
#include "dl_tie728_s8.S"
.align 4
.text
.global dl_tie728_s8_avg_pool2d_22c1
.type dl_tie728_s8_avg_pool2d_22c1, @function
.section .iram1
dl_tie728_s8_avg_pool2d_22c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a10, a4, 4 # input_channel
l32i a11, a4, 104 # c_div_x_1
l32i a13, a4, 56 # shift
addi a14, a4, 64
EE.VLDBC.8 q0, a14 # avg_pool_area_inv
add a7, a3, a6
add a8, a3, a5
add a9, a8, a6
EE.VLD.128.IP q1, a3, 16
EE.VLD.128.IP q2, a7, 16
loopgtz a11, 0f
EE.ZERO.QACC
EE.VMULAS.S8.QACC.LD.IP q3, a8, 16, q0, q1
EE.VMULAS.S8.QACC.LD.IP q4, a9, 16, q0, q2
EE.VMULAS.S8.QACC.LD.IP q1, a3, 16, q0, q3
EE.VMULAS.S8.QACC.LD.IP q2, a7, 16, q0, q4
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q6
EE.VST.128.IP q7, a2, 16
0:
EE.ZERO.QACC
EE.VMULAS.S8.QACC.LD.IP q3, a8, 16, q0, q1
EE.VMULAS.S8.QACC.LD.IP q4, a9, 16, q0, q2
EE.VMULAS.S8.QACC.LD.IP q1, a3, 16, q0, q3
EE.VMULAS.S8.QACC.LD.IP q2, a7, 16, q0, q4
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q6
EE.VST.128.IP q7, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_unaligned_avg_pool2d_22c1
.type dl_tie728_s8_unaligned_avg_pool2d_22c1, @function
.section .iram1
dl_tie728_s8_unaligned_avg_pool2d_22c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a10, a4, 4 # input_channel
l32i a11, a4, 104 # c_div_x_1
l32i a12, a4, 60 # c_remainder
l32i a13, a4, 56 # shift
addi a14, a4, 64
EE.VLDBC.8 q6, a14 # avg_pool_area_inv
add a7, a3, a6
add a8, a3, a5
add a9, a8, a6
blti a11, 0, dl_tie728_s8_unaligned_avg_pool2d_22c1_remainder #channel < 16
EE.LD.128.USAR.IP q7, a2, 0 #get output_ptr sar_byte
rur.sar_byte a15
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q1, a3, 0
beqi a15, 0, 1f
beqi a15, 8, 2f
loopgtz a11, 0f
EE.ZERO.QACC
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.VMULAS.S8.QACC q6, q0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMULAS.S8.QACC q6, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMULAS.S8.QACC q6, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMULAS.S8.QACC q6, q2
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
dl_tie728_s8_unaligned_store0 q7, a2, a14
0:
j dl_tie728_s8_unaligned_avg_pool2d_22c1_loop_end
1:
loopgtz a11, 0f
EE.ZERO.QACC
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.VMULAS.S8.QACC q6, q0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMULAS.S8.QACC q6, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMULAS.S8.QACC q6, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMULAS.S8.QACC q6, q2
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
EE.VST.128.IP q7, a2, 16
0:
j dl_tie728_s8_unaligned_avg_pool2d_22c1_loop_end
2:
loopgtz a11, 0f
EE.ZERO.QACC
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.VMULAS.S8.QACC q6, q0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMULAS.S8.QACC q6, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMULAS.S8.QACC q6, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMULAS.S8.QACC q6, q2
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
dl_tie728_s8_unaligned_store1 q7, a2
0:
dl_tie728_s8_unaligned_avg_pool2d_22c1_loop_end:
EE.ZERO.QACC
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.VMULAS.S8.QACC q6, q0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMULAS.S8.QACC q6, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMULAS.S8.QACC q6, q4
EE.SRC.Q q2, q2, q3
EE.VMULAS.S8.QACC q6, q2
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
dl_tie728_s8_unaligned_store0 q7, a2, a14
beqz a12, dl_tie728_s8_unaligned_avg_pool2d_22c1_end
dl_tie728_s8_unaligned_avg_pool2d_22c1_remainder:
EE.LD.128.USAR.XP q0, a3, a12
EE.VLD.128.IP q1, a3, 0
EE.ZERO.QACC
EE.SRC.Q q0, q0, q1
EE.LD.128.USAR.XP q2, a7, a12
EE.VLD.128.IP q3, a7, 0
EE.VMULAS.S8.QACC q6, q0
EE.SRC.Q q2, q2, q3
EE.LD.128.USAR.XP q4, a8, a12
EE.VLD.128.IP q5, a8, 0
EE.VMULAS.S8.QACC q6, q2
EE.SRC.Q q4, q4, q5
EE.LD.128.USAR.XP q2, a9, a12
EE.VLD.128.IP q3, a9, 0
EE.VMULAS.S8.QACC q6, q4
EE.SRC.Q q2, q2, q3
EE.VMULAS.S8.QACC q6, q2
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
dl_tie728_s8_store_remainder q7, a8, a9, a10, a11, a2, a12
dl_tie728_s8_unaligned_avg_pool2d_22c1_end:
retw
.align 4
.text
.global dl_tie728_s8_avg_pool2d_hwc1
.type dl_tie728_s8_avg_pool2d_hwc1, @function
.section .iram1
dl_tie728_s8_avg_pool2d_hwc1:
.align 4
entry sp, 16
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a7, a4, 4 # input_channel
l32i a8, a4, 48 # filter_height
l32i a9, a4, 52 # filter_width
l32i a11, a4, 104 # c_div_x_1
l32i a13, a4, 56 # shift
addi a14, a4, 64
EE.VLDBC.8 q0, a14 # avg_pool_area_inv
srli a10, a9, 1
addi a10, a10, -1 # filter_w / 2 - 1
beqi a9, 1, dl_tie728_s8_avg_pool2d_h1c1 #filter_width == 1
blti a11, 1, dl_tie728_s8_avg_pool2d_hw_small_channel
5:
mov a7, a3
mov a14, a7
mov a15, a8
EE.ZERO.QACC
4:
EE.VLD.128.XP q1, a14, a6
EE.VLD.128.XP q2, a14, a6
loopgtz a10, 0f
EE.VMULAS.S8.QACC.LD.XP q1, a14, a6, q0, q1
EE.VMULAS.S8.QACC.LD.XP q2, a14, a6, q0, q2
0:
bbci a9, 0, 2f
1:#three left
EE.VMULAS.S8.QACC.LD.XP q1, a14, a6, q0, q1
EE.VMULAS.S8.QACC q0, q2
EE.VMULAS.S8.QACC q0, q1
j 3f
2: # two left
EE.VMULAS.S8.QACC q0, q1
EE.VMULAS.S8.QACC q0, q2
3:
addi a15, a15, -1
add a7, a7, a5
mov a14, a7
bnez a15, 4b
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
EE.VST.128.IP q7, a2, 16
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 5b
dl_tie728_s8_avg_pool2d_hw_small_channel:
mov a7, a3
mov a14, a7
mov a15, a8
EE.ZERO.QACC
4:
EE.VLD.128.XP q1, a14, a6
EE.VLD.128.XP q2, a14, a6
loopgtz a10, 0f
EE.VMULAS.S8.QACC.LD.XP q1, a14, a6, q0, q1
EE.VMULAS.S8.QACC.LD.XP q2, a14, a6, q0, q2
0:
bbci a9, 0, 2f
1:#three left
EE.VMULAS.S8.QACC.LD.XP q1, a14, a6, q0, q1
EE.VMULAS.S8.QACC q0, q2
EE.VMULAS.S8.QACC q0, q1
j 3f
2: # two left
EE.VMULAS.S8.QACC q0, q1
EE.VMULAS.S8.QACC q0, q2
3:
addi a15, a15, -1
add a7, a7, a5
mov a14, a7
bnez a15, 4b
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
EE.VST.128.IP q7, a2, 16
retw
dl_tie728_s8_avg_pool2d_h1c1:
addi a8, a8, -1
blti a11, 1, dl_tie728_s8_max_pool2d_h1_small_channel
1:
mov a14, a3
EE.ZERO.QACC
EE.VLD.128.XP q1, a14, a5
loopgtz a8, 0f
EE.VMULAS.S8.QACC.LD.XP q1, a14, a5, q0, q1
0:
EE.VMULAS.S8.QACC q0, q1
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
EE.VST.128.IP q7, a2, 16
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 1b
dl_tie728_s8_max_pool2d_h1_small_channel:
mov a14, a3
EE.ZERO.QACC
EE.VLD.128.XP q1, a14, a5
loopgtz a8, 0f
EE.VMULAS.S8.QACC.LD.XP q1, a14, a5, q0, q1
0:
EE.VMULAS.S8.QACC q0, q1
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a15, q5
EE.VST.128.IP q7, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_unaligned_avg_pool2d_hwc1
.type dl_tie728_s8_unaligned_avg_pool2d_hwc1, @function
.section .iram1
dl_tie728_s8_unaligned_avg_pool2d_hwc1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a7, a4, 4 # input_channel
l32i a8, a4, 48 # filter_height
l32i a9, a4, 52 # filter_width
l32i a11, a4, 104 # c_div_x_1
l32i a12, a4, 60 # c_remainder
l32i a13, a4, 56 # shift
addi a14, a4, 64
EE.VLDBC.8 q6, a14 # avg_pool_area_inv
srli a10, a9, 1
addi a10, a10, -1 # filter_w / 2 - 1
addi a6, a6, -16
EE.LD.128.USAR.IP q7, a2, 0 #get output_ptr sar_byte
rur.sar_byte a15
addi a11, a11, 1
beqi a9, 1, dl_tie728_s8_unaligned_avg_pool2d_h1c1 #filter_width == 1
blti a11, 1, dl_tie728_s8_unaligned_avg_pool2d_hw_small_channel
9:
mov a7, a3
mov a14, a7
mov a12, a8
EE.ZERO.QACC
4:
EE.LD.128.USAR.IP q0, a14, 16
EE.LD.128.USAR.XP q1, a14, a6
loopgtz a10, 0f
EE.SRC.Q.LD.IP q2, a14, 16, q0, q1
EE.LD.128.USAR.XP q1, a14, a6
EE.VMULAS.S8.QACC q6, q0
EE.SRC.Q.LD.IP q0, a14, 16, q2, q1
EE.LD.128.USAR.XP q1, a14, a6
EE.VMULAS.S8.QACC q6, q2
0:
bbci a9, 0, 2f
1:#three left
EE.SRC.Q.LD.IP q2, a14, 16, q0, q1
EE.LD.128.USAR.XP q1, a14, a6
EE.VMULAS.S8.QACC q6, q0
EE.SRC.Q.LD.IP q0, a14, 16, q2, q1
EE.LD.128.USAR.XP q1, a14, a6
EE.VMULAS.S8.QACC q6, q2
EE.SRC.Q q0, q0, q1
EE.VMULAS.S8.QACC q6, q0
j 3f
2:# two left
EE.SRC.Q.LD.IP q2, a14, 16, q0, q1
EE.LD.128.USAR.XP q1, a14, a6
EE.VMULAS.S8.QACC q6, q0
EE.SRC.Q q2, q2, q1
EE.VMULAS.S8.QACC q6, q2
3:
addi a12, a12, -1
add a7, a7, a5
mov a14, a7
bnez a12, 4b
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a14, q5
beqi a15, 0, 5f
beqi a15, 8, 6f
dl_tie728_s8_unaligned_store0 q7, a2, a14
j 7f
5:
EE.VST.128.IP q7, a2, 16
j 7f
6:
dl_tie728_s8_unaligned_store1 q7, a2
7:
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 9b
dl_tie728_s8_unaligned_avg_pool2d_hw_small_channel:
l32i a12, a4, 60 # c_remainder
beqz a12, dl_tie728_s8_unaligned_avg_pool2d_hw_small_channel_end
mov a7, a3
mov a14, a7
mov a15, a8
addi a6, a6, 16
sub a6, a6, a12
EE.ZERO.QACC
1:
loopgtz a9, 0f
EE.LD.128.USAR.XP q0, a14, a12
EE.VLD.128.XP q1, a14, a6
EE.SRC.Q q0, q0, q1
EE.VMULAS.S8.QACC q6, q0
0:
addi a15, a15, -1
add a7, a7, a5
mov a14, a7
bnez a15, 1b
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a14, q5
dl_tie728_s8_store_remainder q7, a8, a9, a10, a11, a2, a12
dl_tie728_s8_unaligned_avg_pool2d_hw_small_channel_end:
retw
dl_tie728_s8_unaligned_avg_pool2d_h1c1:
addi a5, a5, -16
blti a11, 1, dl_tie728_s8_unaligned_avg_pool2d_h1_remainder
5:
mov a14, a3
EE.ZERO.QACC
loopgtz a8, 0f
EE.LD.128.USAR.IP q0, a14, 16
EE.VLD.128.XP q1, a14, a5
EE.SRC.Q q0, q0, q1
EE.VMULAS.S8.QACC q6, q0
0:
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a14, q5
beqi a15, 0, 1f
beqi a15, 8, 2f
dl_tie728_s8_unaligned_store0 q7, a2, a9
j 3f
1:
EE.VST.128.IP q7, a2, 16
j 3f
2:
dl_tie728_s8_unaligned_store1 q7, a2
3:
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 5b
dl_tie728_s8_unaligned_avg_pool2d_h1_remainder:
beqz a12, dl_tie728_s8_unaligned_avg_pool2d_hwc1_end
mov a14, a3
addi a5, a5, 16
sub a5, a5, a12
EE.ZERO.QACC
loopgtz a8, 0f
EE.LD.128.USAR.XP q0, a14, a12
EE.VLD.128.XP q1, a14, a5
EE.SRC.Q q0, q0, q1
EE.VMULAS.S8.QACC q6, q0
0:
# EE.SRCMB.S8.QACC q7, a13, 0
tie728_s8_vector_round_result q7, a13, a14, q5
dl_tie728_s8_store_remainder q7, a8, a9, a10, a11, a2, a12
dl_tie728_s8_unaligned_avg_pool2d_hwc1_end:
retw
|
georgevio/IoT-Embedded
| 4,437
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_min2d.S
|
#include "dl_tie728_s8.S"
############################################################################################################################################################
####
#### tie728_s8_min2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s8_min2d_11c
.type dl_tie728_s8_min2d_11c, @function
.section .iram1
dl_tie728_s8_min2d_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
l32i a6, a5, 64
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VMIN.S8.LD.INCP q0, a3, q2, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.VST.128.IP q2, a2, 16
0:
EE.VMIN.S8 q2, q0, q1
EE.VST.128.IP q2, a2, 16
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_min2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s8_unaligned_min2d_11c
.type dl_tie728_s8_unaligned_min2d_11c, @function
.section .iram1
dl_tie728_s8_unaligned_min2d_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
l32i a6, a5, 64
l32i a7, a5, 76
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s8_unaligned_min2d_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s8_unaligned_min2d_11c_0
beqi a13, 8, dl_tie718_s8_unaligned_min2d_11c_1
loopgtz a6, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie718_s8_unaligned_min2d_11c_remainder
dl_tie718_s8_unaligned_min2d_11c_0:
loopgtz a6, 1f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S8 q2, q2, q5
EE.VST.128.IP q2, a2, 16
j dl_tie718_s8_unaligned_min2d_11c_remainder
dl_tie718_s8_unaligned_min2d_11c_1:
loopgtz a6, 2f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S8 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie718_s8_unaligned_min2d_11c_remainder
dl_tie718_s8_unaligned_min2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s8_unaligned_min2d_11c_remainder:
beqz a7, dl_tie728_s8_unaligned_min2d_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VMIN.S8 q2, q2, q5
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a7
dl_tie728_s8_unaligned_min2d_11c_end:
retw
|
georgevio/IoT-Embedded
| 11,766
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_sub.S
|
#include "dl_tie728_s8.S"
#void dl_tie728_s8_sub_w1_16_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_sub_w1_16_w2_16
.type dl_tie728_s8_sub_w1_16_w2_16, @function
#.section .iram1
dl_tie728_s8_sub_w1_16_w2_16:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 4
movi a14, 0
tie728_s8_sub_w1_16_w2_16_loop:
beq a14, a5, tie728_s8_sub_w1_16_w2_16_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vsubs.s8 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_sub_w1_16_w2_16_loop
tie728_s8_sub_w1_16_w2_16_end:
retw
#void dl_tie728_s8_sub_w1_16_w2_1(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_sub_w1_16_w2_1
.type dl_tie728_s8_sub_w1_16_w2_1, @function
#.section .iram1
dl_tie728_s8_sub_w1_16_w2_1:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q1, a4, 0
movi a14, 0
tie728_s8_sub_w1_16_w2_1_loop:
beq a14, a5, tie728_s8_sub_w1_16_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vsubs.s8 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_sub_w1_16_w2_1_loop
tie728_s8_sub_w1_16_w2_1_end:
retw
#void dl_tie728_s8_sub_w1_1_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_sub_w1_1_w2_16
.type dl_tie728_s8_sub_w1_1_w2_16, @function
#.section .iram1
dl_tie728_s8_sub_w1_1_w2_16:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q0, a3, 0
movi a14, 0
tie728_s8_sub_w1_1_w2_16_loop:
beq a14, a5, tie728_s8_sub_w1_1_w2_16_end
ee.vld.128.ip q1, a4, 16
ee.vsubs.s8 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_sub_w1_1_w2_16_loop
tie728_s8_sub_w1_1_w2_16_end:
retw
.align 4
.text
.global dl_tie728_s8_sub_w1_16_w2_16_unaligned
.type dl_tie728_s8_sub_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_sub_w1_16_w2_16_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s8_sub_w1_16_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_sub_w1_16_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_sub_w1_16_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_sub_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_sub_w1_16_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s8 q2, q2, q5
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_sub_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_sub_w1_16_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vsubs.s8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_sub_w1_16_w2_16_unaligned_remainder
dl_tie728_s8_sub_w1_16_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_sub_w1_16_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vsubs.s8 q2, q2, q5
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_sub_w1_16_w2_16_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s8_sub_w1_16_w2_1_unaligned
.type dl_tie728_s8_sub_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s8_sub_w1_16_w2_1_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s8_sub_w1_16_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_sub_w1_16_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_sub_w1_16_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_sub_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s8_sub_w1_16_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q2, q5
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_sub_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s8_sub_w1_16_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_sub_w1_16_w2_1_unaligned_remainder
dl_tie728_s8_sub_w1_16_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s8_sub_w1_16_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vsubs.s8 q2, q2, q5
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_sub_w1_16_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s8_sub_w1_1_w2_16_unaligned
.type dl_tie728_s8_sub_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_sub_w1_1_w2_16_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr broadcast
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s8_sub_w1_1_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s8_sub_w1_1_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_sub_w1_1_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q5, q2
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_sub_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_sub_w1_1_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q5, q2
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_sub_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_sub_w1_1_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vsubs.s8 q2, q5, q2
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_sub_w1_1_w2_16_unaligned_remainder
dl_tie728_s8_sub_w1_1_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_sub_w1_1_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vsubs.s8 q2, q5, q2
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_sub_w1_1_w2_16_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 26,986
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_depthwise_conv2d_block.S
|
#include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_depthwise_conv2d_33c1 series
####
############################################################################################################################################################
.macro tie728_s16_depthwise_conv2d_3381 input_v0 filter_v0 input_v1 filter_v1 input_v2 filter_v2 input_ptr filter_ptr dilation_x_offset dilation_y_offset next_hw81
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hw81 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
# EE.ZERO.QACC
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v2, \input_ptr, \dilation_y_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v2, \input_ptr, \dilation_y_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v2, \input_ptr, \next_hw81
EE.VMULAS.S16.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
.endm
.macro tie728_s16_depthwise_conv2d_3381_last input_v0 filter_v0 input_v1 filter_v1 input_ptr filter_ptr dilation_x_offset dilation_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# EE.ZERO.QACC
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_y_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_y_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.IP \input_v0, \input_ptr, 0
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
# block one cycle here
EE.VMULAS.S16.QACC \input_v0, \filter_v0
.endm
.macro tie728_s16_depthwise_conv2d_33c1_load_args args filter_ptr dilation_x_offset dilation_y_offset next_hw81 c_div_x_1 mac_shift
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hw81 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
l32i \filter_ptr, \args, 48
l32i \dilation_x_offset, \args, 124
l32i \dilation_y_offset, \args, 128
l32i \next_hw81, \args, 132
l32i \c_div_x_1, \args, 100
l32i \mac_shift, \args, 64
.endm
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_33c1_bias
.type dl_tie728_s16_depthwise_conv2d_33c1_bias, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_33c1_bias:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: bias_ptr
# a12:
# a13:
# a14:
# a15:
tie728_s16_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9, a10
l32i a11, a4, 68 // bias_ptr
# l32i a12, a4, 76 // activation_alpha
# l32i a13, a4, 84 // activation_shift
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
loopgtz a9, 1f
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q6
EE.VST.128.IP q3, a2, 16
1:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s16_vector_round_result q3, a10, a15, q6
EE.VST.128.IP q3, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_33c1_bias_relu
.type dl_tie728_s16_depthwise_conv2d_33c1_bias_relu, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_33c1_bias_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15:
tie728_s16_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9, a10
l32i a11, a4, 68 // bias_ptr
l32i a12, a4, 76 // activation_alpha
l32i a13, a4, 84 // activation_shift
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
loopgtz a9, 1f
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q6
tie728_s16_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
1:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s16_vector_round_result q3, a10, a15, q6
tie728_s16_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_33c1_bias_prelu
.type dl_tie728_s16_depthwise_conv2d_33c1_bias_prelu, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_33c1_bias_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: bias_ptr
# a12: activation_alpha_ptr
# a13: activation_shift
# a14:
# a15:
tie728_s16_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9, a10
l32i a11, a4, 68 // bias_ptr
l32i a12, a4, 80 // activation_alpha_ptr
l32i a13, a4, 84 // activation_shift
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
loopgtz a9, 1f
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q6
tie728_s16_conv2d_prelu q3, q5, a12, a13
EE.VST.128.IP q3, a2, 16
1:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s16_vector_round_result q3, a10, a15, q6
tie728_s16_conv2d_prelu q3, q5, a12, a13
EE.VST.128.IP q3, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_33c1
.type dl_tie728_s16_depthwise_conv2d_33c1, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_33c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11:
# a12:
# a13:
# a14:
# a15:
tie728_s16_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9, a10
# l32i a11, a4, 68 // bias_ptr
# l32i a12, a4, 76 // activation_alpha
# l32i a13, a4, 84 // activation_shift
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
loopgtz a9, 1f
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q6
EE.VST.128.IP q3, a2, 16
1:
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s16_vector_round_result q3, a10, a15, q6
EE.VST.128.IP q3, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_33c1_relu
.type dl_tie728_s16_depthwise_conv2d_33c1_relu, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_33c1_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11:
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15:
tie728_s16_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9, a10
# l32i a11, a4, 68 // bias_ptr
l32i a12, a4, 76 // activation_alpha
l32i a13, a4, 84 // activation_shift
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
loopgtz a9, 1f
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q6
tie728_s16_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
1:
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s16_vector_round_result q3, a10, a15, q6
tie728_s16_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_33c1_prelu
.type dl_tie728_s16_depthwise_conv2d_33c1_prelu, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_33c1_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11:
# a12: activation_alpha_ptr
# a13: activation_shift
# a14:
# a15:
tie728_s16_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9, a10
# l32i a11, a4, 68 // bias_ptr
l32i a12, a4, 80 // activation_alpha_ptr
l32i a13, a4, 84 // activation_shift
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
loopgtz a9, 1f
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q6
tie728_s16_conv2d_prelu q3, q4, a12, a13
EE.VST.128.IP q3, a2, 16
1:
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s16_vector_round_result q3, a10, a15, q6
tie728_s16_conv2d_prelu q3, q4, a12, a13
EE.VST.128.IP q3, a2, 16
retw
############################################################################################################################################################
####
#### tie728_s16_depthwise_conv2d_hwcn series
####
############################################################################################################################################################
.macro tie728_s16_depthwise_conv2d_1w81 input_v0 input_v1 input_v2 filter_v0 filter_v1 filter_v2 input_ptr filter_ptr dilation_x_offset dilation_y_offset filter_h filter_w filter_w_rs1_1 filter_y_offset
loopgtz \filter_w_rs1_1, 1f
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
1:
bbci \filter_w, 0, 2f
# three 8-input-element left
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v2, \input_ptr, \dilation_y_offset
EE.VMULAS.S16.QACC.LD.XP \filter_v2, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2 # block one cyle here
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
j 3f
2: # two 8-input-element left
EE.VMULAS.S16.QACC.LD.XP \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \dilation_y_offset
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1 # block one cyle here
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
3:
.endm
.macro tie728_s16_depthwise_conv2d_1w81_last input_v0 input_v1 filter_v0 filter_v1 input_ptr filter_ptr dilation_x_offset dilation_y_offset filter_h filter_w filter_w_rs1_1 next_hw81 filter_y_offset
loopgtz \filter_w_rs1_1, 4f
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
4:
bbci \filter_w, 0, 5f
# three 8-input-element left
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \next_hw81
EE.VMULAS.S16.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
# block one cyle here
EE.VMULAS.S16.QACC \input_v0, \filter_v0
j 6f
5: # two 8-input-element left
EE.VMULAS.S16.QACC.LD.XP \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \next_hw81
EE.VMULAS.S16.QACC \input_v1, \filter_v1
6:
.endm
.macro tie728_s16_depthwise_conv2d_hw81 input_v0 input_v1 input_v2 filter_v0 filter_v1 filter_v2 input_ptr filter_ptr dilation_x_offset dilation_y_offset next_hw81 filter_h filter_w filter_w_rs1_1 args filter_offset_q filter_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hw81 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
# filter_w_rs1_1
# EE.ZERO.QACC
l32i \filter_h, \args, 52 # filter_height
blti \filter_w, 2, 9f
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
blti \filter_h, 2, 8f
7:
tie728_s16_depthwise_conv2d_1w81 \input_v0, \input_v1, \input_v2, \filter_v0, \filter_v1, \filter_v2, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \filter_h, \filter_w, \filter_w_rs1_1, \filter_y_offset
addi \filter_h, \filter_h, -1
bgei \filter_h, 2, 7b
8: # last y
tie728_s16_depthwise_conv2d_1w81_last \input_v0, \input_v1, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \filter_h, \filter_w, \filter_w_rs1_1, \next_hw81, \filter_y_offset
j 12f
# filter_w == 1
9:
EE.VLD.128.XP \filter_v0, \filter_ptr, \filter_y_offset
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_y_offset
blti \filter_h, 2, 11f
10:
EE.VMULAS.S16.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bgei \filter_h, 2, 10b
11: # last y
EE.VMULAS.S16.QACC \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset
add \input_ptr, \input_ptr, \next_hw81
12:
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.macro tie728_s16_depthwise_conv2d_hwc1_load_args args filter_ptr dilation_x_offset dilation_y_offset next_hw81 c_div_x_1 mac_shift filter_w filter_w_rs1_1
tie728_s16_depthwise_conv2d_33c1_load_args \args, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \next_hw81, \c_div_x_1, \mac_shift
l32i \filter_w, \args, 56
l32i \filter_w_rs1_1, \args, 148
.endm
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_hwc1_bias
.type dl_tie728_s16_depthwise_conv2d_hwc1_bias, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_hwc1_bias:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h, bias_ptr
# a12: filter_w
# a13: filter_w_rs1_1
# a14: bias_ptr
# a15:
l32i a11, a4, 144
l32i a15, a4, 60
EE.MOVI.32.Q q7, a11, 2
tie728_s16_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a10, a12, a13
l32i a14, a4, 68 // bias_ptr
# l32i a14, a4, 80 // activation_alpha_ptr
# l32i a15, a4, 84 // activation_shift
tie728_s16_depthwise_conv2d_hwc1_bias_loop:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s16_vector_round_result q0, a10, a11, q6
EE.VST.128.IP q0, a2, 16
addi a9, a9, -1
bgez a9, tie728_s16_depthwise_conv2d_hwc1_bias_loop
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_hwc1_bias_relu
.type dl_tie728_s16_depthwise_conv2d_hwc1_bias_relu, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_hwc1_bias_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h, activation_shift
# a12: filter_w
# a13: filter_w_rs1_1
# a14: bias_ptr
# a15: activation_alpha
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
tie728_s16_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a10, a12, a13
l32i a15, a4, 76 // activation_alpha
l32i a14, a4, 68 // bias_ptr
EE.MOVI.32.Q q7, a10, 3
tie728_s16_depthwise_conv2d_hwc1_bias_relu_loop:
EE.MOVI.32.A q7, a10, 1
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a10
EE.MOVI.32.A q7, a10, 3
tie728_s16_vector_round_result q0, a10, a11, q6
l32i a11, a4, 84 // activation_shift
tie728_s16_conv2d_relu q0, a15, a11
EE.VST.128.IP q0, a2, 16
addi a9, a9, -1
bgez a9, tie728_s16_depthwise_conv2d_hwc1_bias_relu_loop
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_hwc1_bias_prelu
.type dl_tie728_s16_depthwise_conv2d_hwc1_bias_prelu, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_hwc1_bias_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h, activation_shift
# a12: filter_w
# a13: filter_w_rs1_1
# a14: bias_ptr
# a15: activation_alpha_ptr
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
tie728_s16_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a10, a12, a13
l32i a15, a4, 80 // activation_alpha_ptr
l32i a14, a4, 68 // bias_ptr
EE.MOVI.32.Q q7, a10, 3
tie728_s16_depthwise_conv2d_hwc1_bias_prelu_loop:
EE.MOVI.32.A q7, a10, 1
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a10
EE.MOVI.32.A q7, a10, 3
tie728_s16_vector_round_result q0, a10, a11, q6
l32i a11, a4, 84 // activation_shift
tie728_s16_conv2d_prelu q0, q2, a15, a11
EE.VST.128.IP q0, a2, 16
addi a9, a9, -1
bgez a9, tie728_s16_depthwise_conv2d_hwc1_bias_prelu_loop
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_hwc1
.type dl_tie728_s16_depthwise_conv2d_hwc1, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_hwc1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h
# a12: filter_w
# a13: filter_w_rs1_1
# a14:
# a15:
l32i a11, a4, 144
l32i a15, a4, 60
EE.MOVI.32.Q q7, a11, 2
tie728_s16_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a10, a12, a13
# l32i a14, a4, 80 // activation_alpha_ptr
# l32i a15, a4, 84 // activation_shift
tie728_s16_depthwise_conv2d_hwc1_loop:
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s16_vector_round_result q0, a10, a11, q6
EE.VST.128.IP q0, a2, 16
addi a9, a9, -1
bgez a9, tie728_s16_depthwise_conv2d_hwc1_loop
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_hwc1_relu
.type dl_tie728_s16_depthwise_conv2d_hwc1_relu, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_hwc1_relu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h
# a12: filter_w
# a13: filter_w_rs1_1
# a14: activation_alpha
# a15: activation_shift
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
tie728_s16_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a10, a12, a13
l32i a14, a4, 76 // activation_alpha
l32i a15, a4, 84 // activation_shift
EE.MOVI.32.Q q7, a10, 3
tie728_s16_depthwise_conv2d_hwc1_relu_loop:
EE.MOVI.32.A q7, a10, 1
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a10
EE.MOVI.32.A q7, a10, 3
tie728_s16_vector_round_result q0, a10, a11, q6
tie728_s16_conv2d_relu q0, a14, a15
EE.VST.128.IP q0, a2, 16
addi a9, a9, -1
bgez a9, tie728_s16_depthwise_conv2d_hwc1_relu_loop
retw
.align 4
.text
.global dl_tie728_s16_depthwise_conv2d_hwc1_prelu
.type dl_tie728_s16_depthwise_conv2d_hwc1_prelu, @function
# .section .iram1
dl_tie728_s16_depthwise_conv2d_hwc1_prelu:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: int16_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hw81
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h, bias_ptr
# a12: filter_w
# a13: filter_w_rs1_1
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
tie728_s16_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a10, a12, a13
l32i a14, a4, 80 // activation_alpha_ptr
l32i a15, a4, 84 // activation_shift
EE.MOVI.32.Q q7, a10, 3
tie728_s16_depthwise_conv2d_hwc1_prelu_loop:
EE.MOVI.32.A q7, a10, 1
EE.ZERO.QACC
tie728_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a10
EE.MOVI.32.A q7, a10, 3
tie728_s16_vector_round_result q0, a10, a11, q6
tie728_s16_conv2d_prelu q0, q1, a14, a15
EE.VST.128.IP q0, a2, 16
addi a9, a9, -1
bgez a9, tie728_s16_depthwise_conv2d_hwc1_prelu_loop
retw
|
georgevio/IoT-Embedded
| 11,778
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_equal.S
|
#include "dl_tie728_s8.S"
#include "dl_tie728_s16.S"
#void dl_tie728_s16_equal_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_equal_w1_8_w2_8
.type dl_tie728_s16_equal_w1_8_w2_8, @function
#.section .iram1
dl_tie728_s16_equal_w1_8_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
movi a14, 0
tie728_s16_equal_w1_8_w2_8_loop:
beq a14, a5, tie728_s16_equal_w1_8_w2_8_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.eq.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_equal_w1_8_w2_8_loop
tie728_s16_equal_w1_8_w2_8_end:
retw
#void dl_tie728_s16_equal_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_equal_w1_8_w2_1
.type dl_tie728_s16_equal_w1_8_w2_1, @function
#.section .iram1
dl_tie728_s16_equal_w1_8_w2_1:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s16_equal_w1_8_w2_1_loop:
beq a14, a5, tie728_s16_equal_w1_8_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.eq.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_equal_w1_8_w2_1_loop
tie728_s16_equal_w1_8_w2_1_end:
retw
#void dl_tie728_s16_equal_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_equal_w1_1_w2_8
.type dl_tie728_s16_equal_w1_1_w2_8, @function
#.section .iram1
dl_tie728_s16_equal_w1_1_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s16_equal_w1_1_w2_8_loop:
beq a14, a5, tie728_s16_equal_w1_1_w2_8_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.eq.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_equal_w1_1_w2_8_loop
tie728_s16_equal_w1_1_w2_8_end:
retw
.align 4
.text
.global dl_tie728_s16_equal_w1_8_w2_8_unaligned
.type dl_tie728_s16_equal_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_equal_w1_8_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s16_equal_w1_8_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_equal_w1_8_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_equal_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_equal_w1_8_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
// ee.vst.128.ip q2, a2, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_equal_w1_8_w2_8_unaligned_remainder
dl_tie728_s16_equal_w1_8_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_equal_w1_8_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_equal_w1_8_w2_8_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s16_equal_w1_8_w2_1_unaligned
.type dl_tie728_s16_equal_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s16_equal_w1_8_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s16_equal_w1_8_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_equal_w1_8_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_equal_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_equal_w1_8_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_equal_w1_8_w2_1_unaligned_remainder
dl_tie728_s16_equal_w1_8_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s16_equal_w1_8_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.eq.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_equal_w1_8_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s16_equal_w1_1_w2_8_unaligned
.type dl_tie728_s16_equal_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_equal_w1_1_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr broadcast
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s16_equal_w1_1_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_equal_w1_1_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_equal_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_equal_w1_1_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_equal_w1_1_w2_8_unaligned_remainder
dl_tie728_s16_equal_w1_1_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_equal_w1_1_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.eq.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_equal_w1_1_w2_8_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 13,860
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_lessorequal.S
|
#include "dl_tie728_s8.S"
#include "dl_tie728_s16.S"
#void dl_tie728_s16_lessorequal_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_lessorequal_w1_8_w2_8
.type dl_tie728_s16_lessorequal_w1_8_w2_8, @function
#.section .iram1
dl_tie728_s16_lessorequal_w1_8_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
movi a14, 0
tie728_s16_lessorequal_w1_8_w2_8_loop:
beq a14, a5, tie728_s16_lessorequal_w1_8_w2_8_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.lt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s16 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s16 q2, q2, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_lessorequal_w1_8_w2_8_loop
tie728_s16_lessorequal_w1_8_w2_8_end:
retw
#void dl_tie728_s16_lessorequal_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_lessorequal_w1_8_w2_1
.type dl_tie728_s16_lessorequal_w1_8_w2_1, @function
#.section .iram1
dl_tie728_s16_lessorequal_w1_8_w2_1:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s16_lessorequal_w1_8_w2_1_loop:
beq a14, a5, tie728_s16_lessorequal_w1_8_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.lt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s16 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s16 q2, q2, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_lessorequal_w1_8_w2_1_loop
tie728_s16_lessorequal_w1_8_w2_1_end:
retw
#void dl_tie728_s16_lessorequal_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_lessorequal_w1_1_w2_8
.type dl_tie728_s16_lessorequal_w1_1_w2_8, @function
#.section .iram1
dl_tie728_s16_lessorequal_w1_1_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s16_lessorequal_w1_1_w2_8_loop:
beq a14, a5, tie728_s16_lessorequal_w1_1_w2_8_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.lt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s16 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s16 q2, q2, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_lessorequal_w1_1_w2_8_loop
tie728_s16_lessorequal_w1_1_w2_8_end:
retw
.align 4
.text
.global dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned
.type dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
// ee.vst.128.ip q2, a2, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned_remainder
dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_lessorequal_w1_8_w2_8_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned
.type dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned_remainder
dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.lt.s16 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_lessorequal_w1_8_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned
.type dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr broadcast
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned_remainder
dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.lt.s16 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s16 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s16 q2, q1, q6
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_lessorequal_w1_1_w2_8_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 5,490
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16.S
|
.macro dl_tie728_128b_unaligned_store0 output_v, output_ptr, tmp32
EE.MOVI.32.A \output_v, \tmp32, 0
s32i \tmp32, \output_ptr, 0
EE.MOVI.32.A \output_v, \tmp32, 1
s32i \tmp32, \output_ptr, 4
EE.MOVI.32.A \output_v, \tmp32, 2
s32i \tmp32, \output_ptr, 8
EE.MOVI.32.A \output_v, \tmp32, 3
s32i \tmp32, \output_ptr, 12
addi \output_ptr, \output_ptr, 16
.endm
.macro dl_tie728_128b_unaligned_l_store0 output_v, output_ptr, tmp32
EE.MOVI.32.A \output_v, \tmp32, 0
s32i \tmp32, \output_ptr, 0
EE.MOVI.32.A \output_v, \tmp32, 1
s32i \tmp32, \output_ptr, 4
addi \output_ptr, \output_ptr, 8
.endm
.macro dl_tie728_128b_unaligned_store1 output_v, output_ptr
EE.VST.L.64.IP \output_v, \output_ptr, 8
EE.VST.H.64.IP \output_v, \output_ptr, 8
.endm
.macro dl_tie728_128b_last_store_data tmp_q, output_v, tmp_a, c_remainder_bytes
beqi \c_remainder_bytes, 0, 600f
movi \tmp_a, 15
sub \tmp_a, \tmp_a, \c_remainder_bytes
movi \c_remainder_bytes, 0
EE.SLCXXP.2Q \tmp_q, \output_v, \tmp_a, \c_remainder_bytes #left shift to make the rest part 0
EE.SRCXXP.2Q \output_v, \tmp_q, \tmp_a, \c_remainder_bytes #right shift to lower bits
600:
.endm
.macro dl_tie728_s16_store_remainder remainder_data, c_remainder, tmp_a, output_ptr
607: # remainder == 1, 0x111
bbci \c_remainder, 2, 603f
bbci \c_remainder, 1, 605f
bbci \c_remainder, 0, 606f
EE.MOVI.32.A \remainder_data, \tmp_a, 0
s32i \tmp_a, \output_ptr, 0
EE.MOVI.32.A \remainder_data, \tmp_a, 1
s32i \tmp_a, \output_ptr, 4
EE.MOVI.32.A \remainder_data, \tmp_a, 2
s32i \tmp_a, \output_ptr, 8
EE.MOVI.32.A \remainder_data, \tmp_a, 3
s16i \tmp_a, \output_ptr, 12
j 600f
606: # remainder == 1, 0x110
EE.MOVI.32.A \remainder_data, \tmp_a, 0
s32i \tmp_a, \output_ptr, 0
EE.MOVI.32.A \remainder_data, \tmp_a, 1
s32i \tmp_a, \output_ptr, 4
EE.MOVI.32.A \remainder_data, \tmp_a, 2
s32i \tmp_a, \output_ptr, 8
j 600f
605: # remainder == 1, 0x101
bbci \c_remainder, 0, 604f
EE.MOVI.32.A \remainder_data, \tmp_a, 0
s32i \tmp_a, \output_ptr, 0
EE.MOVI.32.A \remainder_data, \tmp_a, 1
s32i \tmp_a, \output_ptr, 4
EE.MOVI.32.A \remainder_data, \tmp_a, 2
s16i \tmp_a, \output_ptr, 8
j 600f
604: # remainder == 1, 0x100
EE.MOVI.32.A \remainder_data, \tmp_a, 0
s32i \tmp_a, \output_ptr, 0
EE.MOVI.32.A \remainder_data, \tmp_a, 1
s32i \tmp_a, \output_ptr, 4
j 600f
603: # remainder == 1, 0x011
bbci \c_remainder, 1, 601f
bbci \c_remainder, 0, 602f
EE.MOVI.32.A \remainder_data, \tmp_a, 0
s32i \tmp_a, \output_ptr, 0
EE.MOVI.32.A \remainder_data, \tmp_a, 1
s16i \tmp_a, \output_ptr, 4
j 600f
602: # remainder == 1, 0x010
EE.MOVI.32.A \remainder_data, \tmp_a, 0
s32i \tmp_a, \output_ptr, 0
j 600f
601: # remainder == 1, 0x001
bbci \c_remainder, 0, 600f
EE.MOVI.32.A \remainder_data, \tmp_a, 0
s16i \tmp_a, \output_ptr, 0
600:
.endm
############################################################################################################################################################
# result process for Conv2D / Depthwise_Conv2D
############################################################################################################################################################
.macro tie728_s16_conv2d_per_layer_result output_v, mac_shift
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0
.endm
.macro tie728_s16_vector_round_result output_v mac_shift tmp tmp_q1
beqz \mac_shift, 500f
movi \tmp, 1 // 0000 0000 0000 0000 0000 0000 0000 0001
EE.MOVI.32.Q \output_v, \tmp, 0
EE.MOVI.32.Q \output_v, \tmp, 1
EE.MOVI.32.Q \output_v, \tmp, 2
EE.MOVI.32.Q \output_v, \tmp, 3
movi.n \tmp, 16
wsr.sar \tmp
EE.VSL.32 \tmp_q1, \output_v
EE.ORQ \tmp_q1, \tmp_q1, \output_v // 0000 0000 0000 0001 0000 0000 0000 0001
addi \tmp, \mac_shift, -1
EE.SRCMB.S16.QACC \output_v, \tmp, 0
movi.n \tmp, 1
EE.MOVI.32.Q \output_v, \tmp, 0
EE.VSMULAS.S16.QACC \tmp_q1, \output_v, 0 // qacc[0:16] += round
EE.SRCMB.S16.QACC \output_v, \tmp, 0
j 501f
500:
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0
501:
.endm
.macro tie728_s16_element_round_result output mac_shift tmp tmp_q1
beqz \mac_shift, 505f
addi \tmp, \mac_shift, -1
EE.SRS.ACCX \output, \tmp, 0
movi.n \tmp, 1
EE.ZERO.Q \tmp_q1
EE.MOVI.32.Q \tmp_q1, \tmp, 0
EE.VMULAS.S16.ACCX \tmp_q1, \tmp_q1
EE.SRS.ACCX \output, \tmp, 0
j 506f
505:
EE.SRS.ACCX \output, \mac_shift, 0
506:
.endm
.macro tie728_s16_conv2d_128b_vector_bias bias_ptr
EE.LD.QACC_L.L.128.IP \bias_ptr, 16
EE.LD.QACC_L.H.32.IP \bias_ptr, 16
EE.LD.QACC_H.L.128.IP \bias_ptr, 16
EE.LD.QACC_H.H.32.IP \bias_ptr, 16
.endm
.macro tie728_s16_conv2d_element_bias bias_ptr
EE.LD.ACCX.IP \bias_ptr, 8
.endm
.macro tie728_s16_conv2d_relu output_v, activation_alpha, activation_shift
# LeakyReLU
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift
.endm
.macro tie728_s16_conv2d_prelu output_v, activation_v, activation_alpha_ptr activation_shift
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
# PReLU
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift
.endm
|
georgevio/IoT-Embedded
| 22,778
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_unaligned.S
|
############################################################################################################################################################
# tie728_32b_aligned_vector series
############################################################################################################################################################
.macro tie728_32b_aligned_vector_store output_v, output_ptr, temp
EE.MOVI.32.A \output_v, \temp, 0
s32i \temp, \output_ptr, 0
EE.MOVI.32.A \output_v, \temp, 1
s32i \temp, \output_ptr, 4
EE.MOVI.32.A \output_v, \temp, 2
s32i \temp, \output_ptr, 8
EE.MOVI.32.A \output_v, \temp, 3
s32i \temp, \output_ptr, 12
addi \output_ptr, \output_ptr, 16
.endm
.macro tie728_s16_32b_aligned_vector_shift_bias_relu_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, activation_alpha, activation_shift, temp
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift # LeakyReLU
tie728_32b_aligned_vector_store \output_v, \output_ptr, \temp # store
.endm
.macro tie728_s16_32b_aligned_vector_shift_bias_prelu_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, activation_v, activation_alpha_ptr, activation_shift, temp
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift # PReLU
tie728_32b_aligned_vector_store \output_v, \output_ptr, \temp # store
.endm
.macro tie728_s16_32b_aligned_vector_shift_bias_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, temp
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
tie728_32b_aligned_vector_store \output_v, \output_ptr, \temp # store
.endm
.macro tie728_s16_32b_aligned_vector_shift_relu_store output_v, output_ptr, mac_shift, activation_alpha, activation_shift, temp
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift # LeakyReLU
tie728_32b_aligned_vector_store \output_v, \output_ptr, \temp # store
.endm
.macro tie728_s16_32b_aligned_vector_shift_prelu_store output_v, output_ptr, mac_shift, activation_v, activation_alpha_ptr, activation_shift, temp
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift # PReLU
tie728_32b_aligned_vector_store \output_v, \output_ptr, \temp # store
.endm
.macro tie728_s16_32b_aligned_vector_shift_store output_v, output_ptr, mac_shift, temp
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
tie728_32b_aligned_vector_store \output_v, \output_ptr, \temp # store
.endm
############################################################################################################################################################
# tie728_64b_aligned_vector series
############################################################################################################################################################
.macro tie728_64b_aligned_vector_store output_v, output_ptr
EE.VST.L.64.IP \output_v, \output_ptr, 8
EE.VST.H.64.IP \output_v, \output_ptr, 8
.endm
.macro tie728_s16_64b_aligned_vector_shift_bias_relu_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, activation_alpha, activation_shift
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift # LeakyReLU
tie728_64b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_64b_aligned_vector_shift_bias_prelu_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, activation_v, activation_alpha_ptr, activation_shift
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift # PReLU
tie728_64b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_64b_aligned_vector_shift_bias_store output_v, output_ptr, mac_shift, bias_v, bias_ptr
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
tie728_64b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_64b_aligned_vector_shift_relu_store output_v, output_ptr, mac_shift, activation_alpha, activation_shift
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift # LeakyReLU
tie728_64b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_64b_aligned_vector_shift_prelu_store output_v, output_ptr, mac_shift, activation_v, activation_alpha_ptr, activation_shift
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift # PReLU
tie728_64b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_64b_aligned_vector_shift_store output_v, output_ptr, mac_shift
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
tie728_64b_aligned_vector_store \output_v, \output_ptr # store
.endm
############################################################################################################################################################
# tie728_128b_aligned_vector series
############################################################################################################################################################
.macro tie728_128b_aligned_vector_store output_v, output_ptr
EE.VST.128.IP \output_v, \output_ptr, 16
.endm
.macro tie728_s16_128b_aligned_vector_shift_bias_relu_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, activation_alpha, activation_shift
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift # LeakyReLU
tie728_128b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_128b_aligned_vector_shift_bias_prelu_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, activation_v, activation_alpha_ptr, activation_shift
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift # PReLU
tie728_128b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_128b_aligned_vector_shift_bias_store output_v, output_ptr, mac_shift, bias_v, bias_ptr
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
tie728_128b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_128b_aligned_vector_shift_relu_store output_v, output_ptr, mac_shift, activation_alpha, activation_shift
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift # LeakyReLU
tie728_128b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_128b_aligned_vector_shift_prelu_store output_v, output_ptr, mac_shift, activation_v, activation_alpha_ptr, activation_shift
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift # PReLU
tie728_128b_aligned_vector_store \output_v, \output_ptr # store
.endm
.macro tie728_s16_128b_aligned_vector_shift_store output_v, output_ptr, mac_shift
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
tie728_128b_aligned_vector_store \output_v, \output_ptr # store
.endm
############################################################################################################################################################
# tie728_element series
############################################################################################################################################################
.macro tie728_s16_element_store output_ptr, output
clamps \output, \output, 15
s16i \output, \output_ptr, 0
addi \output_ptr, \output_ptr, 2
.endm
.macro tie728_s16_element_bias output, bias_ptr, bias
l16si \bias, \bias_ptr, 0
addi \bias_ptr, \bias_ptr, 2
add \output, \output, \bias
.endm
.macro tie728_s16_element_relu output
bgez \output, 0f
movi \output, 0
0:
.endm
.macro tie728_s16_element_leakyrelu output, alpha
bgez \output, 0f
mull \output, \output, \alpha
sra \output, \output
0:
.endm
.macro tie728_s16_element_prelu output, alpha_ptr, alpha
l16si \alpha, \alpha_ptr, 0
addi \alpha_ptr, \alpha_ptr, 2
bgez \output, 0f
mull \output, \output, \alpha
sra \output, \output
0:
.endm
.macro tie728_s16_element_shift_bias_relu_store output_ptr, mac_shift, bias_ptr, temp1, temp2
EE.SRS.ACCX \temp1, \mac_shift, 0 # shift
tie728_s16_element_bias \temp1, \bias_ptr, \temp2 # bias
tie728_s16_element_relu \temp1 # relu
tie728_s16_element_store \output_ptr, \temp1 # store
.endm
# DONNOT forget to set ssr before call this macro
.macro tie728_s16_element_shift_bias_leakyrelu_store output_ptr, mac_shift, bias_ptr, activation_alpha, temp1, temp2
EE.SRS.ACCX \temp1, \mac_shift, 0 # shift
tie728_s16_element_bias \temp1, \bias_ptr, \temp2 # bias
tie728_s16_element_leakyrelu \temp1, \activation_alpha # leakyrelu
tie728_s16_element_store \output_ptr, \temp1 # store
.endm
# DONNOT forget to set ssr before call this macro
.macro tie728_s16_element_shift_bias_prelu_store output_ptr, mac_shift, bias_ptr, activation_alpha_ptr, temp1, temp2
EE.SRS.ACCX \temp1, \mac_shift, 0 # shift
tie728_s16_element_bias \temp1, \bias_ptr, \temp2 # bias
tie728_s16_element_prelu \temp1, \activation_alpha_ptr, \temp2 # prelu
tie728_s16_element_store \output_ptr, \temp1 # store
.endm
.macro tie728_s16_element_shift_bias_store output_ptr, mac_shift, bias_ptr, temp1, temp2
EE.SRS.ACCX \temp1, \mac_shift, 0 # shift
tie728_s16_element_bias \temp1, \bias_ptr, \temp2 # bias
tie728_s16_element_store \output_ptr, \temp1 # store
.endm
.macro tie728_s16_element_shift_relu_store output_ptr, mac_shift, temp1
EE.SRS.ACCX \temp1, \mac_shift, 0 # shift
tie728_s16_element_relu \temp1 # relu
tie728_s16_element_store \output_ptr, \temp1 # store
.endm
# DONNOT forget to set ssr before call this macro
.macro tie728_s16_element_shift_leakyrelu_store output_ptr, mac_shift, activation_alpha, temp1
EE.SRS.ACCX \temp1, \mac_shift, 0 # shift
tie728_s16_element_leakyrelu \temp1, \activation_alpha # leakyrelu
tie728_s16_element_store \output_ptr, \temp1 # store
.endm
# DONNOT forget to set ssr before call this macro
.macro tie728_s16_element_shift_prelu_store output_ptr, mac_shift, activation_alpha_ptr, temp1, temp2
EE.SRS.ACCX \temp1, \mac_shift, 0 # shift
tie728_s16_element_prelu \temp1, \activation_alpha_ptr, \temp2 # prelu
tie728_s16_element_store \output_ptr, \temp1 # store
.endm
.macro tie728_s16_element_shift_store output_ptr, mac_shift, temp1
EE.SRS.ACCX \temp1, \mac_shift, 0 # shift
tie728_s16_element_store \output_ptr, \temp1 # store
.endm
############################################################################################################################################################
# tie728_s16_variable_vector series
############################################################################################################################################################
.macro tie728_s16_variable_vector_store output_ptr, vector, number, temp
7:
bbci \number, 2, 3f
bbci \number, 1, 5f
bbci \number, 0, 6f
# number == 0x111
EE.MOVI.32.A \vector, \temp, 0
s32i \temp, \output_ptr, 0
EE.MOVI.32.A \vector, \temp, 1
s32i \temp, \output_ptr, 4
EE.MOVI.32.A \vector, \temp, 2
s32i \temp, \output_ptr, 8
EE.MOVI.32.A \vector, \temp, 3
s16i \temp, \output_ptr, 12
j 0f
6:
# number == 0x110
EE.MOVI.32.A \vector, \temp, 0
s32i \temp, \output_ptr, 0
EE.MOVI.32.A \vector, \temp, 1
s32i \temp, \output_ptr, 4
EE.MOVI.32.A \vector, \temp, 2
s32i \temp, \output_ptr, 8
j 0f
5:
# number == 0x10_
bbci \number, 0, 4f
# number == 0x101
EE.MOVI.32.A \vector, \temp, 0
s32i \temp, \output_ptr, 0
EE.MOVI.32.A \vector, \temp, 1
s32i \temp, \output_ptr, 4
EE.MOVI.32.A \vector, \temp, 2
s16i \temp, \output_ptr, 8
j 0f
4:
# number == 0x100
EE.MOVI.32.A \vector, \temp, 0
s32i \temp, \output_ptr, 0
EE.MOVI.32.A \vector, \temp, 1
s32i \temp, \output_ptr, 4
j 0f
3:
# number == 0x0__
bbci \number, 1, 1f
bbci \number, 0, 2f
# number == 0x011
EE.MOVI.32.A \vector, \temp, 0
s32i \temp, \output_ptr, 0
EE.MOVI.32.A \vector, \temp, 1
s16i \temp, \output_ptr, 4
j 0f
2:
# number == 0x010
EE.MOVI.32.A \vector, \temp, 0
s32i \temp, \output_ptr, 0
j 0f
1:
# number == 0x001
EE.MOVI.32.A \vector, \temp, 0
s16i \temp, \output_ptr, 0
0:
.endm
.macro tie728_s16_variable_vector_shift_bias_relu_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, activation_alpha, activation_shift, number, temp
EE.VLD.128.IP \bias_v, \bias_ptr, 0 # load bias
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift # LeakyReLU
tie728_s16_variable_vector_store \output_ptr, \output_v, \number, \temp # store
.endm
.macro tie728_s16_variable_vector_shift_bias_prelu_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, activation_v, activation_alpha_ptr, activation_shift, number, temp
EE.VLD.128.IP \bias_v, \bias_ptr, 0 # load bias
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 0 # load PReLU alph
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift # PReLU
tie728_s16_variable_vector_store \output_ptr, \output_v, \number, \temp # store
.endm
.macro tie728_s16_variable_vector_shift_bias_store output_v, output_ptr, mac_shift, bias_v, bias_ptr, number, temp
EE.VLD.128.IP \bias_v, \bias_ptr, 0 # load bias
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VADDS.S16 \output_v, \output_v, \bias_v # bias
tie728_s16_variable_vector_store \output_ptr, \output_v, \number, \temp # store
.endm
.macro tie728_s16_variable_vector_shift_relu_store output_v, output_ptr, mac_shift, activation_alpha, activation_shift, number, temp
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VRELU.S16 \output_v, \activation_alpha, \activation_shift # LeakyReLU
tie728_s16_variable_vector_store \output_ptr, \output_v, \number, \temp # store
.endm
.macro tie728_s16_variable_vector_shift_prelu_store output_v, output_ptr, mac_shift, activation_v, activation_alpha_ptr, activation_shift, number, temp
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 0 # load PReLU alph
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
EE.VPRELU.S16 \output_v, \output_v, \activation_v, \activation_shift # PReLU
tie728_s16_variable_vector_store \output_ptr, \output_v, \number, \temp # store
.endm
.macro tie728_s16_variable_vector_shift_store output_v, output_ptr, mac_shift, number, temp
EE.SRCMB.S16.QACC \output_v, \mac_shift, 0 # QACC -> QR without round, roud operation is wrong in this instruction
tie728_s16_variable_vector_store \output_ptr, \output_v, \number, \temp # store
.endm
|
georgevio/IoT-Embedded
| 11,721
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_less.S
|
#include "dl_tie728_s8.S"
#include "dl_tie728_s16.S"
#void dl_tie728_s16_less_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_less_w1_8_w2_8
.type dl_tie728_s16_less_w1_8_w2_8, @function
#.section .iram1
dl_tie728_s16_less_w1_8_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
movi a14, 0
tie728_s16_less_w1_8_w2_8_loop:
beq a14, a5, tie728_s16_less_w1_8_w2_8_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.lt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_less_w1_8_w2_8_loop
tie728_s16_less_w1_8_w2_8_end:
retw
#void dl_tie728_s16_less_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_less_w1_8_w2_1
.type dl_tie728_s16_less_w1_8_w2_1, @function
#.section .iram1
dl_tie728_s16_less_w1_8_w2_1:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s16_less_w1_8_w2_1_loop:
beq a14, a5, tie728_s16_less_w1_8_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.lt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_less_w1_8_w2_1_loop
tie728_s16_less_w1_8_w2_1_end:
retw
#void dl_tie728_s16_less_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_less_w1_1_w2_8
.type dl_tie728_s16_less_w1_1_w2_8, @function
#.section .iram1
dl_tie728_s16_less_w1_1_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s16_less_w1_1_w2_8_loop:
beq a14, a5, tie728_s16_less_w1_1_w2_8_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.lt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_less_w1_1_w2_8_loop
tie728_s16_less_w1_1_w2_8_end:
retw
.align 4
.text
.global dl_tie728_s16_less_w1_8_w2_8_unaligned
.type dl_tie728_s16_less_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_less_w1_8_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s16_less_w1_8_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_less_w1_8_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_less_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_less_w1_8_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
// ee.vst.128.ip q2, a2, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_less_w1_8_w2_8_unaligned_remainder
dl_tie728_s16_less_w1_8_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_less_w1_8_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_less_w1_8_w2_8_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s16_less_w1_8_w2_1_unaligned
.type dl_tie728_s16_less_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s16_less_w1_8_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s16_less_w1_8_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_less_w1_8_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_less_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_less_w1_8_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_less_w1_8_w2_1_unaligned_remainder
dl_tie728_s16_less_w1_8_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s16_less_w1_8_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.lt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_less_w1_8_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s16_less_w1_1_w2_8_unaligned
.type dl_tie728_s16_less_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_less_w1_1_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr broadcast
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s16_less_w1_1_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_less_w1_1_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_less_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_less_w1_1_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_less_w1_1_w2_8_unaligned_remainder
dl_tie728_s16_less_w1_1_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_less_w1_1_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.lt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_less_w1_1_w2_8_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 75,115
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_unaligned_depthwise_conv2d.S
|
#include "dl_tie728_s16_unaligned.S"
#include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_unaligned_depthwise_conv2d_33c1 series
####
############################################################################################################################################################
.macro tie728_s16_unaligned_depthwise_conv2d_3381 input_v0, input_v1, input_v2, input_back, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_3381_16
# EE.ZERO.QACC
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_y_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_y_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \next_3381_16
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back
.endm
.macro tie728_s16_unaligned_depthwise_conv2d_3381_last input_v0, input_v1, input_v2, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_3381_16
# EE.ZERO.QACC
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_y_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v2, \filter_v0
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_y_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v1
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v1
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \next_3381_16
EE.VMULAS.S16.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q \input_v2, \input_v2, \input_back
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VMULAS.S16.QACC \input_v2, \filter_v0
.endm
.macro tie728_s16_unaligned_depthwise_conv2d_11r1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_remainder, forward
EE.LD.128.USAR.IP \input_v0, \input_ptr, 16
EE.VLD.128.XP \input_back, \input_ptr, \forward
EE.SRC.Q \input_v0, \input_v0, \input_back
EE.LD.128.USAR.XP \filter_v0, \filter_ptr, \c_remainder
EE.VLD.128.IP \filter_back, \filter_ptr, 0
EE.SRC.Q \filter_v0, \filter_v0, \filter_back
EE.VMULAS.S16.QACC \input_v0, \filter_v0
.endm
.macro tie728_s16_unaligned_depthwise_conv2d_33r1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, c_remainder
# EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_16
.endm
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_33c1
.type dl_tie728_s16_unaligned_depthwise_conv2d_33c1, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_33c1:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_3381 - 16
l32i a9, a4, 100 # a9: c_div_x_1
l32i a10, a4, 64 # a10: mac_shift
# l32i a11, a4, 68 # a11: bias_ptr
l32i a12, a4, 76 # a12: activation_alpha
l32i a13, a4, 84 # a13: activation_shift
blti a9, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_c_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q4, a5, 16, q0, q3 # q4: filter_v0; q0: input_v0
EE.LD.128.USAR.IP q1, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q2, a3, 16, q1, q3 # q2: input_v2; q1: input_v1
tie728_s16_unaligned_depthwise_conv2d_33c1_c_div_x:
beqi a15, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_128b
beqi a15, 8, tie728_s16_unaligned_depthwise_conv2d_33c1_64b
tie728_s16_unaligned_depthwise_conv2d_33c1_32b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_32b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_32b_aligned_vector_store q3, a2, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_32b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_32b_aligned_vector_store q3, a2, a15
j tie728_s16_unaligned_depthwise_conv2d_33c1_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_64b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_64b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_64b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_64b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_64b_aligned_vector_store q3, a2
j tie728_s16_unaligned_depthwise_conv2d_33c1_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_128b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_128b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_128b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_c_remainder:
l32i a9, a4, 136 # a9: c_remainder
beqz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_c_remainder_end
EE.ZERO.QACC
srli a14, a9, 1
tie728_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9
tie728_s16_vector_round_result q0, a10, a15, q5
tie728_s16_variable_vector_store a2, q0, a14, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_33c1_relu
.type dl_tie728_s16_unaligned_depthwise_conv2d_33c1_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_33c1_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_3381 - 16
l32i a9, a4, 100 # a9: c_div_x_1
l32i a10, a4, 64 # a10: mac_shift
# l32i a11, a4, 68 # a11: bias_ptr
l32i a12, a4, 76 # a12: activation_alpha
l32i a13, a4, 84 # a13: activation_shift
blti a9, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q4, a5, 16, q0, q3 # q4: filter_v0; q0: input_v0
EE.LD.128.USAR.IP q1, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q2, a3, 16, q1, q3 # q2: input_v2; q1: input_v1
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_c_div_x:
beqi a15, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_relu_128b
beqi a15, 8, tie728_s16_unaligned_depthwise_conv2d_33c1_relu_64b
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_32b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_relu_32b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_32b_aligned_vector_store q3, a2, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_32b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_32b_aligned_vector_store q3, a2, a15
j tie728_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_64b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_relu_64b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_64b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_64b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_64b_aligned_vector_store q3, a2
j tie728_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_128b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_relu_128b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_128b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder:
l32i a9, a4, 136 # a9: c_remainder
beqz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder_end
EE.ZERO.QACC
srli a14, a9, 1
tie728_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9
tie728_s16_vector_round_result q0, a10, a15, q5
tie728_s16_conv2d_relu q0, a12, a13
tie728_s16_variable_vector_store a2, q0, a14, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_33c1_prelu
.type dl_tie728_s16_unaligned_depthwise_conv2d_33c1_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_33c1_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_3381 - 16
l32i a9, a4, 100 # a9: c_div_x_1
l32i a10, a4, 64 # a10: mac_shift
# l32i a11, a4, 68 # a11: bias_ptr
l32i a12, a4, 80 # a12: activation_alpha_ptr
l32i a13, a4, 84 # a13: activation_shift
blti a9, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_c_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q4, a5, 16, q0, q3 # q4: filter_v0; q0: input_v0
EE.LD.128.USAR.IP q1, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q2, a3, 16, q1, q3 # q2: input_v2; q1: input_v1
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_c_div_x:
beqi a15, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_128b
beqi a15, 8, tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_64b
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_32b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_32b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_32b_aligned_vector_store q3, a2, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_32b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_32b_aligned_vector_store q3, a2, a15
j tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_64b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_64b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_64b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_64b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_64b_aligned_vector_store q3, a2
j tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_128b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_128b_last
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_128b_last:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_c_remainder:
l32i a9, a4, 136 # a9: c_remainder
beqz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_c_remainder_end
EE.ZERO.QACC
srli a14, a9, 1
tie728_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9
tie728_s16_vector_round_result q0, a10, a15, q5
tie728_s16_conv2d_prelu q0, q5, a12, a13
tie728_s16_variable_vector_store a2, q0, a14, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_prelu_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias
.type dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_3381 - 16
l32i a9, a4, 100 # a9: c_div_x_1
l32i a10, a4, 64 # a10: mac_shift
l32i a11, a4, 68 # a11: bias_ptr
# l32i a12, a4, 76 # a12: activation_alpha
# l32i a13, a4, 84 # a13: activation_shift
blti a9, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q4, a5, 16, q0, q3 # q4: filter_v0; q0: input_v0
EE.LD.128.USAR.IP q1, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q2, a3, 16, q1, q3 # q2: input_v2; q1: input_v1
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_c_div_x:
beqi a15, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_128b
beqi a15, 8, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_64b
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_32b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_32b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_32b_aligned_vector_store q3, a2, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_32b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_32b_aligned_vector_store q3, a2, a15
j tie728_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_64b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_64b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_64b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_64b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_64b_aligned_vector_store q3, a2
j tie728_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_128b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_128b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_128b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder:
l32i a9, a4, 136 # a9: c_remainder
beqz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder_end
EE.ZERO.QACC
srli a14, a9, 1
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9
tie728_s16_vector_round_result q0, a10, a15, q5
tie728_s16_variable_vector_store a2, q0, a14, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu
.type dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_3381 - 16
l32i a9, a4, 100 # a9: c_div_x_1
l32i a10, a4, 64 # a10: mac_shift
l32i a11, a4, 68 # a11: bias_ptr
l32i a12, a4, 76 # a12: activation_alpha
l32i a13, a4, 84 # a13: activation_shift
blti a9, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q4, a5, 16, q0, q3 # q4: filter_v0; q0: input_v0
EE.LD.128.USAR.IP q1, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q2, a3, 16, q1, q3 # q2: input_v2; q1: input_v1
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_div_x:
beqi a15, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b
beqi a15, 8, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_32b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_32b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_32b_aligned_vector_store q3, a2, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_32b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_32b_aligned_vector_store q3, a2, a15
j tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_64b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_64b_aligned_vector_store q3, a2
j tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_relu q3, a12, a13
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder:
l32i a9, a4, 136 # a9: c_remainder
beqz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder_end
EE.ZERO.QACC
srli a14, a9, 1
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9
tie728_s16_vector_round_result q0, a10, a15, q5
tie728_s16_conv2d_relu q0, a12, a13
tie728_s16_variable_vector_store a2, q0, a14, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu
.type dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_3381 - 16
l32i a9, a4, 100 # a9: c_div_x_1
l32i a10, a4, 64 # a10: mac_shift
l32i a11, a4, 68 # a11: bias_ptr
l32i a12, a4, 80 # a12: activation_alpha_ptr
l32i a13, a4, 84 # a13: activation_shift
blti a9, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_c_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q4, a5, 16, q0, q3 # q4: filter_v0; q0: input_v0
EE.LD.128.USAR.IP q1, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.SRC.Q.LD.IP q2, a3, 16, q1, q3 # q2: input_v2; q1: input_v1
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_c_div_x:
beqi a15, 0, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_128b
beqi a15, 8, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_64b
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_32b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_32b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_32b_aligned_vector_store q3, a2, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_32b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_32b_aligned_vector_store q3, a2, a15
j tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_64b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_64b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_64b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_64b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_64b_aligned_vector_store q3, a2
j tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_128b:
loopgtz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_128b_last
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_128b_last:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s16_vector_round_result q3, a10, a15, q5
tie728_s16_conv2d_prelu q3, q5, a12, a13
tie728_128b_aligned_vector_store q3, a2
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_c_remainder:
l32i a9, a4, 136 # a9: c_remainder
beqz a9, tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_c_remainder_end
EE.ZERO.QACC
srli a14, a9, 1
tie728_s16_conv2d_128b_vector_bias a11
tie728_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9
tie728_s16_vector_round_result q0, a10, a15, q5
tie728_s16_conv2d_prelu q0, q5, a12, a13
tie728_s16_variable_vector_store a2, q0, a14, a15
tie728_s16_unaligned_depthwise_conv2d_33c1_bias_prelu_c_remainder_end:
retw
############################################################################################################################################################
####
#### tie728_s16_unaligned_depthwise_conv2d_hwc1 series
####
############################################################################################################################################################
.macro tie728_s16_unaligned_depthwise_conv2d_1w81 input_v0, input_v1, input_back, input_ptr, filter_v0, filter_ptr, dilation_x_offset_16, dilation_y_offset, filter_w, filter_w_rs1_1 filter_y_offset
loopgtz \filter_w_rs1_1, 1f
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
1:
bbci \filter_w, 0, 2f
# three 8-input-element left
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_y_offset
EE.VMULAS.S16.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q \input_v0, \input_v1, \input_back
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
j 3f
2: # two 8-input-element left
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_y_offset
EE.VMULAS.S16.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
3:
.endm
.macro tie728_s16_unaligned_depthwise_conv2d_1w81_last input_v0 input_v1 input_back input_ptr filter_v0 filter_ptr dilation_x_offset_16 filter_w filter_w_rs1_1 next_hws1 filter_y_offset
loopgtz \filter_w_rs1_1, 4f
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back
4:
bbci \filter_w, 0, 5f
# three 8-input-element left
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VMULAS.S16.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back
EE.LD.128.USAR.XP \input_back, \input_ptr, \next_hws1
EE.VMULAS.S16.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v0
EE.SRC.Q \input_v0, \input_v0, \input_back
EE.VMULAS.S16.QACC \input_v0, \filter_v0
j 6f
5: # two 8-input-element left
EE.LD.128.USAR.XP \input_back, \input_ptr, \next_hws1
EE.VMULAS.S16.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
EE.SRC.Q \input_v1, \input_v1, \input_back
EE.VMULAS.S16.QACC \input_v1, \filter_v0
6:
.endm
.macro tie728_s16_unaligned_depthwise_conv2d_hw81 input_v0, input_v1, input_back, filter_v0, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_hws1, filter_h, filter_w, filter_w_rs1_1, args, filter_offset_q, filter_y_offset
l32i \filter_h, \args, 52 # filter_height
l32i \filter_w, \args, 56 # filter_width
# EE.ZERO.QACC
blti \filter_w, 2, 9f
# filter_w >= 2
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_x_offset_16
EE.VLD.128.IP \filter_v0, \filter_ptr, 16 # filter_v0
EE.SRC.Q \input_v0, \input_v1, \input_back # input_v0
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
blti \filter_h, 2, 8f
7:
tie728_s16_unaligned_depthwise_conv2d_1w81 \input_v0, \input_v1, \input_back, \input_ptr, \filter_v0, \filter_ptr, \dilation_x_offset_16, \dilation_y_offset_16, \filter_w, \filter_w_rs1_1, \filter_y_offset
addi \filter_h, \filter_h, -1
bgei \filter_h, 2, 7b
8: # last y
tie728_s16_unaligned_depthwise_conv2d_1w81_last \input_v0, \input_v1, \input_back, \input_ptr, \filter_v0, \filter_ptr, \dilation_x_offset_16, \filter_w, \filter_w_rs1_1, \next_hws1, \filter_y_offset
j 12f
9: # filter_w == 1
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_y_offset_16
EE.VLD.128.XP \filter_v0, \filter_ptr, \filter_y_offset # filter_v0
EE.SRC.Q \input_v0, \input_v1, \input_back # input_v0
blti \filter_h, 2, 11f
addi \filter_h, \filter_h, -1
loopgtz \filter_h, 10f
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
EE.LD.128.USAR.XP \input_back, \input_ptr, \dilation_y_offset_16
EE.VMULAS.S16.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
EE.SRC.Q \input_v0, \input_v1, \input_back
10:
11: # last y
EE.VMULAS.S16.QACC \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset_16
add \input_ptr, \input_ptr, \next_hws1
12:
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.macro tie728_s16_unaligned_depthwise_conv2d_11r1_padding input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_remainder, forward, filter_y_offset
EE.LD.128.USAR.IP \input_v0, \input_ptr, 16
EE.VLD.128.XP \input_back, \input_ptr, \forward
EE.SRC.Q \input_v0, \input_v0, \input_back
EE.LD.128.USAR.XP \filter_v0, \filter_ptr, \c_remainder
EE.VLD.128.XP \filter_back, \filter_ptr, \filter_y_offset
EE.SRC.Q \filter_v0, \filter_v0, \filter_back
EE.VMULAS.S16.QACC \input_v0, \filter_v0
.endm
.macro tie728_s16_unaligned_depthwise_conv2d_hwr1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, filter_h, filter_w, filter_w_rs1_1, c_remainder, args, filter_y_offset
l32i \filter_h, \args, 52 # filter_height
l32i \filter_w, \args, 56 # filter_width
# EE.ZERO.QACC
blti \filter_w, 2, 5f
4:
loopgtz \filter_w_rs1_1, 1f
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
1:
bbci \filter_w, 0, 2f
# 3 left
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_16, \filter_y_offset
j 3f
2:
# 2 left
tie728_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_16
tie728_s16_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_16, \filter_y_offset
3:
addi \filter_h, \filter_h, -1
bgei \filter_h, 1, 4b
j 7f
5:
# filter_w == 1
loopgtz \filter_h, 6f
tie728_s16_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_16, \filter_y_offset
6:
7:
.endm
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_hwc1
.type dl_tie728_s16_unaligned_depthwise_conv2d_hwc1, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_hwc1:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a11, a4, 144
l32i a15, a4, 60
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
# a9
# a10
l32i a11, a4, 148 # a11: filter_w_rs1_1
l32i a12, a4, 100 # a12: c_div_x_1
l32i a13, a4, 64 # a13: mac_shift
# l32i a14, a4, 76 # a14: activation_alpha
# l32i a15, a4, 84 # a15: activation_shift
blti a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_c_remainder
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_hw81 - 16
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a9 # a9: output_sar_byte
tie728_s16_unaligned_depthwise_conv2d_hwc1_c_div_x:
beqi a9, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_128b
beqi a9, 8, tie728_s16_unaligned_depthwise_conv2d_hwc1_64b
tie728_s16_unaligned_depthwise_conv2d_hwc1_32b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_32b_multiple_loop:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a15
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_32b_aligned_vector_store q0, a2, a9
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_32b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_64b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_64b_multiple_loop:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a15
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_64b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_128b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_128b_multiple_loop:
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a15
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_128b_multiple_loop
tie728_s16_unaligned_depthwise_conv2d_hwc1_c_remainder:
l32i a12, a4, 136 # a12: c_remainder
beqz a12, tie728_s16_unaligned_depthwise_conv2d_hwc1_c_remainder_end
EE.ZERO.QACC
srli a8, a12, 1
l32i a5, a4, 168 # filter_ptr unaligned
l32i a15, a4, 160
tie728_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9, a10, a11, a12, a4, a15
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_variable_vector_store a2, q0, a8, a9
tie728_s16_unaligned_depthwise_conv2d_hwc1_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_relu
.type dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
# a9
# a10
l32i a11, a4, 148 # a11: filter_w_rs1_1
l32i a12, a4, 100 # a12: c_div_x_1
l32i a13, a4, 64 # a13: mac_shift
l32i a14, a4, 76 # a14: activation_alpha
l32i a15, a4, 84 # a15: activation_shift
EE.MOVI.32.Q q7, a13, 3
blti a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_hw81 - 16
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a9 # a9: output_sar_byte
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_c_div_x:
beqi a9, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_128b
beqi a9, 8, tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_64b
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_32b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_32b_multiple_loop:
EE.MOVI.32.A q7, a13, 1
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_conv2d_relu q0, a14, a15
tie728_32b_aligned_vector_store q0, a2, a9
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_32b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_64b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_64b_multiple_loop:
EE.MOVI.32.A q7, a13, 1
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_conv2d_relu q0, a14, a15
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_64b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_128b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_128b_multiple_loop:
EE.MOVI.32.A q7, a13, 1
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_conv2d_relu q0, a14, a15
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_128b_multiple_loop
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder:
l32i a12, a4, 136 # a12: c_remainder
beqz a12, tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder_end
EE.ZERO.QACC
srli a8, a12, 1
l32i a5, a4, 168 # filter_ptr unaligned
l32i a13, a4, 160
tie728_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9, a10, a11, a12, a4, a13
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_conv2d_relu q0, a14, a15
tie728_s16_variable_vector_store a2, q0, a8, a9
tie728_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu
.type dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
# a9
# a10
l32i a11, a4, 148 # a11: filter_w_rs1_1
l32i a12, a4, 100 # a12: c_div_x_1
l32i a13, a4, 64 # a13: mac_shift
l32i a14, a4, 80 # a14: activation_alpha_ptr
l32i a15, a4, 84 # a15: activation_shift
EE.MOVI.32.Q q7, a13, 3
blti a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_c_remainder
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_hw81 - 16
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a9 # a9: output_sar_byte
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_c_div_x:
beqi a9, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_128b
beqi a9, 8, tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_64b
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_32b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_32b_multiple_loop:
EE.MOVI.32.A q7, a13, 1
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_conv2d_prelu q0, q5, a14, a15
tie728_32b_aligned_vector_store q0, a2, a9
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_32b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_64b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_64b_multiple_loop:
EE.MOVI.32.A q7, a13, 1
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_conv2d_prelu q0, q5, a14, a15
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_64b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_128b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_128b_multiple_loop:
EE.MOVI.32.A q7, a13, 1
EE.ZERO.QACC
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_conv2d_prelu q0, q5, a14, a15
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_128b_multiple_loop
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_c_remainder:
l32i a12, a4, 136 # a12: c_remainder
beqz a12, tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_c_remainder_end
EE.ZERO.QACC
srli a8, a12, 1
l32i a5, a4, 168 # filter_ptr unaligned
l32i a13, a4, 160
tie728_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9, a10, a11, a12, a4, a13
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_conv2d_prelu q0, q5, a14, a15
tie728_s16_variable_vector_store a2, q0, a8, a9
tie728_s16_unaligned_depthwise_conv2d_hwc1_prelu_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias
.type dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a11, a4, 144
l32i a15, a4, 60
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
# a9
# a10
l32i a11, a4, 148 # a11: filter_w_rs1_1
l32i a12, a4, 100 # a12: c_div_x_1
l32i a13, a4, 64 # a13: mac_shift
l32i a14, a4, 68 # a14: bias_ptr
# a15
blti a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_hw81 - 16
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a9 # a9: output_sar_byte
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_c_div_x:
beqi a9, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_128b
beqi a9, 8, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_64b
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_32b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_32b_multiple_loop:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a15
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_32b_aligned_vector_store q0, a2, a9
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_32b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_64b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_64b_multiple_loop:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a15
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_64b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_128b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_128b_multiple_loop:
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a15
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_128b_multiple_loop
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder:
l32i a12, a4, 136 # a12: c_remainder
beqz a12, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder_end
EE.ZERO.QACC
srli a8, a12, 1
l32i a5, a4, 168 # filter_ptr unaligned
l32i a15, a4, 160
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9, a10, a11, a12, a4, a15
tie728_s16_vector_round_result q0, a13, a9, q5
tie728_s16_variable_vector_store a2, q0, a8, a9
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu
.type dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
# a9
# a10
l32i a11, a4, 148 # a11: filter_w_rs1_1
l32i a12, a4, 100 # a12: c_div_x_1
l32i a13, a4, 64 # a13: mac_shift
l32i a14, a4, 68 # a14: bias_ptr
l32i a15, a4, 76 # a15: activation_alpha
EE.MOVI.32.Q q7, a13, 3
blti a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_hw81 - 16
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a9 # a9: output_sar_byte
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_div_x:
beqi a9, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_128b
beqi a9, 8, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_64b
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_32b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_32b_multiple_loop:
EE.ZERO.QACC
EE.MOVI.32.A q7, a13, 1
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
l32i a9, a4, 84 # a9: activation_shift
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a10, q5
tie728_s16_conv2d_relu q0, a15, a9
tie728_32b_aligned_vector_store q0, a2, a10
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_32b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_64b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_64b_multiple_loop:
EE.ZERO.QACC
EE.MOVI.32.A q7, a13, 1
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
l32i a9, a4, 84 # a9: activation_shift
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a10, q5
tie728_s16_conv2d_relu q0, a15, a9
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_64b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_128b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_128b_multiple_loop:
EE.ZERO.QACC
EE.MOVI.32.A q7, a13, 1
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
l32i a9, a4, 84 # a9: activation_shift
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a10, q5
tie728_s16_conv2d_relu q0, a15, a9
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_128b_multiple_loop
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder:
l32i a12, a4, 136 # a12: c_remainder
beqz a12, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder_end
EE.ZERO.QACC
srli a8, a12, 1
l32i a5, a4, 168 # filter_ptr unaligned
l32i a13, a4, 160
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9, a10, a11, a12, a4, a13
l32i a9, a4, 84 # a9: activation_shift
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a10, q5
tie728_s16_conv2d_relu q0, a15, a9
tie728_s16_variable_vector_store a2, q0, a8, a10
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu
.type dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 124
addi a6, a6, -16 # a6: dilation_x_offset - 16
l32i a7, a4, 128
addi a7, a7, -16 # a7: dilation_y_offset - 16
# a9
# a10
l32i a11, a4, 148 # a11: filter_w_rs1_1
l32i a12, a4, 100 # a12: c_div_x_1
l32i a13, a4, 64 # a13: mac_shift
l32i a14, a4, 68 # a14: bias_ptr
l32i a15, a4, 80 # a15: activation_alpha_ptr
EE.MOVI.32.Q q7, a13, 3
blti a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_c_remainder
l32i a8, a4, 132
addi a8, a8, -16 # a8: next_hw81 - 16
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a9 # a9: output_sar_byte
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_c_div_x:
beqi a9, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_128b
beqi a9, 8, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_64b
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_32b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_32b_multiple_loop:
EE.ZERO.QACC
EE.MOVI.32.A q7, a13, 1
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
l32i a9, a4, 84 # a9: activation_shift
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a10, q5
tie728_s16_conv2d_prelu q0, q5, a15, a9
tie728_32b_aligned_vector_store q0, a2, a10
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_32b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_64b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_64b_multiple_loop:
EE.ZERO.QACC
EE.MOVI.32.A q7, a13, 1
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
l32i a9, a4, 84 # a9: activation_shift
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a10, q5
tie728_s16_conv2d_prelu q0, q5, a15, a9
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_64b_multiple_loop
j tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_c_remainder
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_128b:
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_128b_multiple_loop:
EE.ZERO.QACC
EE.MOVI.32.A q7, a13, 1
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a3, a5, a6, a7, a8, a9, a10, a11, a4, q7, a13
l32i a9, a4, 84 # a9: activation_shift
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a10, q5
tie728_s16_conv2d_prelu q0, q5, a15, a9
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bgei a12, 0, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_128b_multiple_loop
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_c_remainder:
l32i a12, a4, 136 # a12: c_remainder
beqz a12, tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_c_remainder_end
EE.ZERO.QACC
srli a8, a12, 1
l32i a5, a4, 168 # filter_ptr unaligned
l32i a13, a4, 160
tie728_s16_conv2d_128b_vector_bias a14
tie728_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a9, a10, a11, a12, a4, a13
l32i a9, a4, 84 # a9: activation_shift
EE.MOVI.32.A q7, a13, 3
tie728_s16_vector_round_result q0, a13, a10, q5
tie728_s16_conv2d_prelu q0, q5, a15, a9
tie728_s16_variable_vector_store a2, q0, a8, a10
tie728_s16_unaligned_depthwise_conv2d_hwc1_bias_prelu_c_remainder_end:
retw
|
georgevio/IoT-Embedded
| 11,766
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_add.S
|
#include "dl_tie728_s8.S"
#void dl_tie728_s8_add_w1_16_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_add_w1_16_w2_16
.type dl_tie728_s8_add_w1_16_w2_16, @function
#.section .iram1
dl_tie728_s8_add_w1_16_w2_16:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 4
movi a14, 0
tie728_s8_add_w1_16_w2_16_loop:
beq a14, a5, tie728_s8_add_w1_16_w2_16_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vadds.s8 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_add_w1_16_w2_16_loop
tie728_s8_add_w1_16_w2_16_end:
retw
#void dl_tie728_s8_add_w1_16_w2_1(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_add_w1_16_w2_1
.type dl_tie728_s8_add_w1_16_w2_1, @function
#.section .iram1
dl_tie728_s8_add_w1_16_w2_1:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q1, a4, 0
movi a14, 0
tie728_s8_add_w1_16_w2_1_loop:
beq a14, a5, tie728_s8_add_w1_16_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vadds.s8 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_add_w1_16_w2_1_loop
tie728_s8_add_w1_16_w2_1_end:
retw
#void dl_tie728_s8_add_w1_1_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_add_w1_1_w2_16
.type dl_tie728_s8_add_w1_1_w2_16, @function
#.section .iram1
dl_tie728_s8_add_w1_1_w2_16:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q0, a3, 0
movi a14, 0
tie728_s8_add_w1_1_w2_16_loop:
beq a14, a5, tie728_s8_add_w1_1_w2_16_end
ee.vld.128.ip q1, a4, 16
ee.vadds.s8 q2, q0, q1
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_add_w1_1_w2_16_loop
tie728_s8_add_w1_1_w2_16_end:
retw
.align 4
.text
.global dl_tie728_s8_add_w1_16_w2_16_unaligned
.type dl_tie728_s8_add_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_add_w1_16_w2_16_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s8_add_w1_16_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_add_w1_16_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_add_w1_16_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_add_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_add_w1_16_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s8 q2, q2, q5
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_add_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_add_w1_16_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vadds.s8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_add_w1_16_w2_16_unaligned_remainder
dl_tie728_s8_add_w1_16_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_add_w1_16_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vadds.s8 q2, q2, q5
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_add_w1_16_w2_16_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s8_add_w1_16_w2_1_unaligned
.type dl_tie728_s8_add_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s8_add_w1_16_w2_1_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s8_add_w1_16_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_add_w1_16_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_add_w1_16_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_add_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s8_add_w1_16_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q2, q5
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_add_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s8_add_w1_16_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q2, q5
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_add_w1_16_w2_1_unaligned_remainder
dl_tie728_s8_add_w1_16_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s8_add_w1_16_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vadds.s8 q2, q2, q5
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_add_w1_16_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s8_add_w1_1_w2_16_unaligned
.type dl_tie728_s8_add_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_add_w1_1_w2_16_unaligned:
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr broadcast
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s8_add_w1_1_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s8_add_w1_1_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_add_w1_1_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q5, q2
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_add_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_add_w1_1_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q5, q2
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_add_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_add_w1_1_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q5, q2
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vadds.s8 q2, q5, q2
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_add_w1_1_w2_16_unaligned_remainder
dl_tie728_s8_add_w1_1_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_add_w1_1_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vadds.s8 q2, q5, q2
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_add_w1_1_w2_16_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 96,591
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_conv2d.S
|
#include "dl_tie728_s8.S"
############################################################################################################################################################
####
#### tie728_s8_conv2d_11cn series
####
############################################################################################################################################################
.macro tie728_s8_conv2d_11c16 input_v0 input_ptr filter_v0 filter_v1 filter_ptr c_div_x_1
# scalar * vecter and accumulate into QACC
# input_ptr += (c_div_x_1 + 1) * 16 in the end
# filter_ptr point to the next 16 bytes in the end
# input_v0: 16 input elements
# filter_v0: 16 filter elements
# filter_v1: 16 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 16 - 1
EE.VLD.128.IP \input_v0, \input_ptr, 16
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
loopgtz \c_div_x_1, 0f
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 14
EE.VSMULAS.S8.QACC.LD.INCP \input_v0, \input_ptr, \filter_v1, \input_v0, 15
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
0:
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 14
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 15
.endm
############################################################################################################################################################
####
#### tie728_s8_conv2d_11cn
####
############################################################################################################################################################
.macro tie728_s8_conv2d_11cn_load_args args filter_ptr c_div_x_1 n_rs3
l32i \n_rs3, \args, 96 // output_channel_div_8
l32i \filter_ptr, \args, 48 // filter
l32i \c_div_x_1, \args, 100 // input_channel / x - 1
.endm
.align 4
.text
.global dl_tie728_s8_conv2d_11cn
.type dl_tie728_s8_conv2d_11cn, @function
# .section .iram1
dl_tie728_s8_conv2d_11cn:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12:
# a13:
# a14:
# a15: moving_input_ptr
tie728_s8_conv2d_11cn_load_args a4, a5, a6, a7
l32i a11, a4, 68 # bias
l32i a8, a4, 64 # mac shift
blti a8, 0, dl_tie728_s8_conv2d_per_channel_11cn
dl_tie728_s8_conv2d_per_layer_11cn:
beqz a11, tie728_s8_conv2d_per_layer_11cn_no_bias_loop
tie728_s8_conv2d_per_layer_11cn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_11cn_bias_loop
retw
tie728_s8_conv2d_per_layer_11cn_no_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_11cn_no_bias_loop
retw
dl_tie728_s8_conv2d_per_channel_11cn:
l32i a8, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_conv2d_per_channel_11cn_no_bias_loop
tie728_s8_conv2d_per_channel_11cn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# tie728_s8_conv2d_bias q0, q1, a11
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a11, a15, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_11cn_bias_loop
retw
tie728_s8_conv2d_per_channel_11cn_no_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_11cn_no_bias_loop
retw
.align 4
.text
.global dl_tie728_s8_conv2d_11cn_relu
.type dl_tie728_s8_conv2d_11cn_relu, @function
# .section .iram1
dl_tie728_s8_conv2d_11cn_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12: activation_alpha
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s8_conv2d_11cn_load_args a4, a5, a6, a7
l32i a12, a4, 76 # activation_alpha
l32i a13, a4, 84 # activation_shift
l32i a11, a4, 68 # bias
l32i a8, a4, 64 # mac shift
blti a8, 0, dl_tie728_s8_conv2d_per_channel_11cn_relu
dl_tie728_s8_conv2d_per_layer_11cn_relu:
beqz a11, tie728_s8_conv2d_per_layer_11cn_no_bias_relu_loop
tie728_s8_conv2d_per_layer_11cn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_11cn_bias_relu_loop
retw
tie728_s8_conv2d_per_layer_11cn_no_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_11cn_no_bias_relu_loop
retw
dl_tie728_s8_conv2d_per_channel_11cn_relu:
l32i a8, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_conv2d_per_channel_11cn_no_bias_relu_loop
tie728_s8_conv2d_per_channel_11cn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# tie728_s8_conv2d_bias_relu q0, q1, a11, a12, a13
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a11, a15, q2
tie728_s8_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_11cn_bias_relu_loop
retw
tie728_s8_conv2d_per_channel_11cn_no_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
tie728_s8_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_11cn_no_bias_relu_loop
retw
.align 4
.text
.global dl_tie728_s8_conv2d_11cn_prelu
.type dl_tie728_s8_conv2d_11cn_prelu, @function
# .section .iram1
dl_tie728_s8_conv2d_11cn_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9:
# a10:
# a11: bias_ptr
# a12: activation_alpha
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s8_conv2d_11cn_load_args a4, a5, a6, a7
l32i a12, a4, 80 # activation_alpha_ptr
l32i a13, a4, 84 # activation_shift
l32i a11, a4, 68 # bias
l32i a8, a4, 64 # mac shift
blti a8, 0, dl_tie728_s8_conv2d_per_channel_11cn_prelu
dl_tie728_s8_conv2d_per_layer_11cn_prelu:
beqz a11, tie728_s8_conv2d_per_layer_11cn_no_bias_prelu_loop
tie728_s8_conv2d_per_layer_11cn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_11cn_bias_prelu_loop
retw
tie728_s8_conv2d_per_layer_11cn_no_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_11cn_no_bias_prelu_loop
retw
dl_tie728_s8_conv2d_per_channel_11cn_prelu:
l32i a8, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_conv2d_per_channel_11cn_no_bias_prelu_loop
tie728_s8_conv2d_per_channel_11cn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# tie728_s8_conv2d_bias_prelu q0, q1, a11, q2, a12, a13
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a11, a15, q2
tie728_s8_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_11cn_bias_prelu_loop
retw
tie728_s8_conv2d_per_channel_11cn_no_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_11c16 q0, a15, q1, q2, a5, a6
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
tie728_s8_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_11cn_no_bias_prelu_loop
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_conv2d_11cn
####
############################################################################################################################################################
.macro tie728_s8_conv2d_1_1_n_remainder_result operation_type output output_ptr mac_shift bias_ptr activation_alpha activation_shift tmp tmp_q1
#l16si a7, a1, 0
EE.MOVI.32.A \operation_type, \tmp, 0 # operation type in q7[0]
bbci \tmp, 3, 7f
bbci \tmp, 2, 11f
11: # per_channel bias + prelu, 0x1011
bbci \tmp, 1, 9f
bbci \tmp, 0, 10f
# l16si \tmp, \mac_shift, 0
# addi \mac_shift, \mac_shift, 2
# EE.SRS.ACCX \output, \tmp, 0
# # add bias
# l8ui \tmp, \bias_ptr, 0 # load bias
# addi \bias_ptr, \bias_ptr, 1
# sext \tmp, \tmp, 7
# add \output, \output, \tmp
movi \tmp, 4
EE.SRS.ACCX \output, \tmp, 0
l16si \tmp, \bias_ptr, 0 # load bias
addi \bias_ptr, \bias_ptr, 2
add \output, \output, \tmp # add bias
l16si \tmp, \mac_shift, 0
addi \mac_shift, \mac_shift, 2
addi \tmp, \tmp, -4
ssr \tmp # mac_shift-4
sra \output, \output
# prelu
bgez \output, 17f
l8ui \tmp, \activation_alpha, 0 # load PReLU alpha
sext \tmp, \tmp, 7
mull \output, \output, \tmp
ssr \activation_shift # activation_shift
sra \output, \output
j 17f # jump to 17f
10: # per_channel bias + relu, 0x1010
# l16si \tmp, \mac_shift, 0
# addi \mac_shift, \mac_shift, 2
# EE.SRS.ACCX \output, \tmp, 0
# # add bias
# l8ui \tmp, \bias_ptr, 0 # load bias
# addi \bias_ptr, \bias_ptr, 1
# sext \tmp, \tmp, 7
# add \output, \output, \tmp
movi \tmp, 4
EE.SRS.ACCX \output, \tmp, 0
l16si \tmp, \bias_ptr, 0 # load bias
addi \bias_ptr, \bias_ptr, 2
add \output, \output, \tmp # add bias
l16si \tmp, \mac_shift, 0
addi \mac_shift, \mac_shift, 2
addi \tmp, \tmp, -4
ssr \tmp # mac_shift-4
sra \output, \output
# Relu or LeakyRelu
bgez \output, 16f
mull \output, \output, \activation_alpha
ssr \activation_shift # activation_shift
sra \output, \output
j 16f # jump to 16f
9: # per_channel bias, 0x1001
bbci \tmp, 0, 8f
# l16si \tmp, \mac_shift, 0
# addi \mac_shift, \mac_shift, 2
# EE.SRS.ACCX \output, \tmp, 0
# # add bias
# l8ui \tmp, \bias_ptr, 0 # load bias
# addi \bias_ptr, \bias_ptr, 1
# sext \tmp, \tmp, 7
# add \output, \output, \tmp
movi \tmp, 4
EE.SRS.ACCX \output, \tmp, 0
l16si \tmp, \bias_ptr, 0 # load bias
addi \bias_ptr, \bias_ptr, 2
add \output, \output, \tmp # add bias
l16si \tmp, \mac_shift, 0
addi \mac_shift, \mac_shift, 2
addi \tmp, \tmp, -4
ssr \tmp # mac_shift-4
sra \output, \output
j 16f # jump to 16f
8: # per_channel no_bias + prelu, 0x1000
l16si \tmp, \mac_shift, 0
addi \mac_shift, \mac_shift, 2
EE.SRS.ACCX \output, \tmp, 0
# prelu
bgez \output, 17f
l8ui \tmp, \activation_alpha, 0 # load PReLU alpha
sext \tmp, \tmp, 7
mull \output, \output, \tmp
ssr \activation_shift # activation_shift
sra \output, \output
j 17f # jump to 16f
7: # per_channel no_bias + relu, 0x111
bbci \tmp, 2, 3f
bbci \tmp, 1, 5f
bbci \tmp, 0, 6f
l16si \tmp, \mac_shift, 0
addi \mac_shift, \mac_shift, 2
EE.SRS.ACCX \output, \tmp, 0
# Relu or LeakyRelu
bgez \output, 16f
mull \output, \output, \activation_alpha
ssr \activation_shift # activation_shift
sra \output, \output
j 16f # jump to 16f
6: # per_channel no_bias, 0x110
l16si \tmp, \mac_shift, 0
addi \mac_shift, \mac_shift, 2
EE.SRS.ACCX \output, \tmp, 0
j 16f # jump to 16f
5: # remainder == 4, 5
bbci \tmp, 0, 4f
# per_layer bias + prelu, 0x101
# EE.SRS.ACCX \output, \mac_shift, 0
tie728_s8_element_round_result \output, \mac_shift, \tmp, \tmp_q1
# bias will be preload
# # add bias
# l8ui \tmp, \bias_ptr, 0 # load bias
# addi \bias_ptr, \bias_ptr, 1
# sext \tmp, \tmp, 7
# add \output, \output, \tmp
# prelu
bgez \output, 17f
l8ui \tmp, \activation_alpha, 0 # load PReLU alpha
sext \tmp, \tmp, 7
mull \output, \output, \tmp
ssr \activation_shift # activation_shift
sra \output, \output
j 17f # jump to 17f
4: # per_layer bias + relu, 0x100
# EE.SRS.ACCX \output, \mac_shift, 0
tie728_s8_element_round_result \output, \mac_shift, \tmp, \tmp_q1
# bias will be preload
# # add bias
# l8ui \tmp, \bias_ptr, 0 # load bias
# addi \bias_ptr, \bias_ptr, 1
# sext \tmp, \tmp, 7
# add \output, \output, \tmp
# Relu or LeakyRelu
bgez \output, 16f
mull \output, \output, \activation_alpha
ssr \activation_shift # activation_shift
sra \output, \output
j 16f # jump to 16f
3: # remainder == 1, 2, 3
bbci \tmp, 1, 1f
bbci \tmp, 0, 2f
# per_layer bias, 0x011
# EE.SRS.ACCX \output, \mac_shift, 0
tie728_s8_element_round_result \output, \mac_shift, \tmp, \tmp_q1
# bias will be preload
# # add bias
# l8ui \tmp, \bias_ptr, 0 # load bias
# addi \bias_ptr, \bias_ptr, 1
# sext \tmp, \tmp, 7
# add \output, \output, \tmp
j 16f # jump to 16f
2: # per_layer no_bias + prelu, 0x010
# EE.SRS.ACCX \output, \mac_shift, 0
tie728_s8_element_round_result \output, \mac_shift, \tmp, \tmp_q1
# prelu
bgez \output, 17f
l8ui \tmp, \activation_alpha, 0 # load PReLU alpha
sext \tmp, \tmp, 7
mull \output, \output, \tmp
ssr \activation_shift # activation_shift
sra \output, \output
j 17f # jump to 17f
1: # per_layer no_bias + relu, 0x001
bbci \tmp, 0, 0f
# EE.SRS.ACCX \output, \mac_shift, 0
tie728_s8_element_round_result \output, \mac_shift, \tmp, \tmp_q1
# Relu or LeakyRelu
bgez \output, 16f
mull \output, \output, \activation_alpha
ssr \activation_shift # activation_shift
sra \output, \output
j 16f # jump to 16f
0: # per_layer no_bias
# EE.SRS.ACCX \output, \mac_shift, 0
tie728_s8_element_round_result \output, \mac_shift, \tmp, \tmp_q1
j 16f # jump to 16f
17: # update prelu ptr
addi \activation_alpha, \activation_alpha, 1
16:
clamps \output, \output, 7
s8i \output, \output_ptr, 0
addi \output_ptr, \output_ptr, 1
.endm
.macro tie728_s8_conv2d_1_1_unaligned_c input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_v1 filter_ptr c_div_x_1 remainder_c input_sar
# scalar * vecter and accumulate into QACC
# input_ptr += (c_div_x_1 + 1) * 16 in the end
# filter_ptr point to the next 16 bytes in the end
# input_v0: 16 input elements
# filter_v0: 16 filter elements
# filter_v1: 16 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 16 - 1
blti \c_div_x_1, 0, 17f # input_channel < 16
EE.LD.128.USAR.IP \input_front_aligned, \input_ptr, 16
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 16
loopgtz \c_div_x_1, 0f
# EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 16
EE.SRC.Q.QUP \input_v0, \input_front_aligned, \input_back_aligned
EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 16
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 14
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 15
0:
# EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \remainder_c
EE.SRC.Q.QUP \input_v0, \input_front_aligned, \input_back_aligned
addi \input_ptr, \input_ptr, -16
add \input_ptr, \input_ptr, \remainder_c #input_ptr and the end of c
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 14
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 15
beqz \remainder_c, 16f #no c_remainder
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
# rur.sar_byte \input_sar #input sar
# EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 0
# wur.sar_byte \input_sar #input sar
EE.VLD.128.IP \input_back_aligned, \input_ptr, 0
EE.SRC.Q \input_v0, \input_front_aligned, \input_back_aligned
j 15f
17: # input_channel < 16
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
EE.LD.128.USAR.XP \input_front_aligned, \input_ptr, \remainder_c
# rur.sar_byte \input_sar #input sar
# EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 0
# wur.sar_byte \input_sar #input sar
EE.VLD.128.IP \input_back_aligned, \input_ptr, 0
EE.SRC.Q \input_v0, \input_front_aligned, \input_back_aligned
15: # remainder_c == 15, 0x1111
bbci \remainder_c, 3, 7f
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
bbci \remainder_c, 2, 11f
bbci \remainder_c, 1, 13f
bbci \remainder_c, 0, 14f
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 13
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 14
j 16f # jump to 16f
14: # remainder_c == 14, 0x1110
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 12
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 13
j 16f # jump to 16f
13: # remainder_c == 13, 0x1101
bbci \remainder_c, 0, 12f
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 11
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 12
j 16f # jump to 16f
12: # remainder_c == 12, 0x1100
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 10
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 11
j 16f # jump to 16f
11: # remainder_c == 11, 0x1011
bbci \remainder_c, 1, 9f
bbci \remainder_c, 0, 10f
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 9
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 10
j 16f # jump to 16f
10: # remainder_c == 10, 0x1010
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 8
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 9
j 16f # jump to 16f
9: # remainder_c == 9, 0x1001
bbci \remainder_c, 0, 8f
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 7
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 8
j 16f # jump to 16f
8: # remainder_c == 8, 0x1000
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 6
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 7
j 16f # jump to 16f
7: # remainder == 7, 0x111
bbci \remainder_c, 2, 3f
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
bbci \remainder_c, 1, 5f
bbci \remainder_c, 0, 6f
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 5
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 6
j 16f # jump to 16f
6: # remainder == 6, 0x110
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 4
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 5
j 16f # jump to 16f
5: # remainder == 4, 5
bbci \remainder_c, 0, 4f
# remainder == 5, 0x101
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 3
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 4
j 16f # jump to 16f
4: # remainder == 4, 0x100
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 2
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 3
j 16f # jump to 16f
3: # remainder == 1, 2, 3
bbci \remainder_c, 1, 1f
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
bbci \remainder_c, 0, 2f
# remainder == 3, 0x011
EE.VSMULAS.S8.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 1
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 2
j 16f # jump to 16f
2: # remainder == 2, 0x010
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 0
EE.VSMULAS.S8.QACC \filter_v1, \input_v0, 1
j 16f # jump to 16f
1: # remainder == 1, 0x001
EE.VSMULAS.S8.QACC \filter_v0, \input_v0, 0
16:
.endm
.macro tie728_s8_conv2d_1_1_c_n_remainder input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_front_aligned filter_back_aligned filter_ptr c_div_x_1 remainder_c input_sar filter_sar
# scalar * vecter and accumulate into QACC
# input_ptr += (c_div_x_1 + 1) * 16 in the end
# filter_ptr point to the next 16 bytes in the end
# input_v0: 16 input elements
# filter_v0: 16 filter elements
# filter_v1: 16 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 16 - 1
blti \c_div_x_1, 0, 17f # input_channel < 16
EE.LD.128.USAR.IP \input_front_aligned, \input_ptr, 16
EE.LD.128.USAR.IP \filter_front_aligned, \filter_ptr, 16
EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 16
loopgtz \c_div_x_1, 0f
EE.SRC.Q.QUP \input_v0, \input_front_aligned, \input_back_aligned
EE.LD.128.USAR.IP \filter_back_aligned, \filter_ptr, 16
EE.SRC.Q.QUP \filter_v0, \filter_front_aligned, \filter_back_aligned
EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 16
EE.VMULAS.S8.ACCX \filter_v0, \input_v0
0:
# EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \remainder_c
EE.SRC.Q.QUP \input_v0, \input_front_aligned, \input_back_aligned
rur.sar_byte \input_sar #input sar
addi \input_ptr, \input_ptr, -16
EE.LD.128.USAR.XP \filter_back_aligned, \filter_ptr, \remainder_c
add \input_ptr, \input_ptr, \remainder_c #input_ptr and the end of c
EE.SRC.Q.QUP \filter_v0, \filter_front_aligned, \filter_back_aligned
EE.VMULAS.S8.ACCX \filter_v0, \input_v0
beqz \remainder_c, 16f #no remainder_c
# filter remainder is in one 128bit then filter_back_aligned = filter_front_aligned
# rur.sar_byte \filter_sar #filter sar
# EE.LD.128.USAR.IP \filter_back_aligned, \filter_ptr, 0
# wur.sar_byte \filter_sar #filter sar
EE.VLD.128.IP \filter_back_aligned, \filter_ptr, 0
EE.SRC.Q \filter_v0, \filter_front_aligned, \filter_back_aligned
# input remainder is in one 128bit then input_back_aligned = input_front_aligned
EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 0
wur.sar_byte \input_sar #input sar
EE.SRC.Q \input_v0, \input_front_aligned, \input_back_aligned #right shift delete the low sar_byte
#left shift to make the rest part(15 - remainder_c) 0 EE.SLXCCP left shift a0+1
movi \filter_sar, 15
sub \filter_sar, \filter_sar, \remainder_c
movi \input_sar, 0
EE.SLCXXP.2Q \input_back_aligned, \input_v0, \filter_sar, \input_sar #left shift to make the rest part 0
EE.SLCXXP.2Q \filter_back_aligned, \filter_v0, \filter_sar, \input_sar
EE.VMULAS.S8.ACCX \filter_v0, \input_v0
j 16f
17: # input_channel < 16
# filter remainder is in one 128bit then filter_back_aligned = filter_front_aligned
EE.LD.128.USAR.XP \filter_front_aligned, \filter_ptr, \remainder_c
# rur.sar_byte \filter_sar #filter sar
# EE.LD.128.USAR.IP \filter_back_aligned, \filter_ptr, 0
# wur.sar_byte \filter_sar #filter sar
EE.VLD.128.IP \filter_back_aligned, \filter_ptr, 0
EE.SRC.Q \filter_v0, \filter_front_aligned, \filter_back_aligned
# input remainder is in one 128bit then input_back_aligned = input_front_aligned
EE.LD.128.USAR.XP \input_front_aligned, \input_ptr, \remainder_c
# rur.sar_byte \input_sar #input sar
# EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 0
# wur.sar_byte \input_sar #input sar
EE.VLD.128.IP \input_back_aligned, \input_ptr, 0
EE.SRC.Q \input_v0, \input_front_aligned, \input_back_aligned
#left shift to make the rest part(15 - remainder_c) 0 EE.SLXCCP left shift a0+1
movi \filter_sar, 15
sub \filter_sar, \filter_sar, \remainder_c
movi \input_sar, 0
EE.SLCXXP.2Q \input_back_aligned, \input_v0, \filter_sar, \input_sar #left shift to make the rest part 0
EE.SLCXXP.2Q \filter_back_aligned, \filter_v0, \filter_sar, \input_sar
EE.VMULAS.S8.ACCX \filter_v0, \input_v0
16:
.endm
.align 4
.text
.global dl_tie728_s8_unaligned_conv2d_11cn
.type dl_tie728_s8_unaligned_conv2d_11cn, @function
# .section .iram1
dl_tie728_s8_unaligned_conv2d_11cn:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs4 / input_sar
# a8: channel_factor
# a9: c_remainder
# a10: operation_type / n_remainder
# a11: bias_ptr
# a12:
# a13:
# a14: input_sar
# a15: moving_input_ptr
tie728_s8_conv2d_11cn_load_args a4, a5, a6, a7
# l32i a7, a4, 96 // output_channel_div_8
# l32i a5, a4, 48 // filter
# l32i a6, a4, 100 // input_channel / x - 1
l32i a9, a4, 136 # c_remainder: c % 16
l32i a8, a4, 64 // mac_shift
l32i a11, a4, 68 // bias
#l32i a12, a4, 76 // activation_alpha
l32i a13, a4, 84 // activation_shift
l32i a12, a4, 80 // activation_alpha_ptr
tie728_s8_unaligned_conv2d_operation_type a10, a8, a11, a13, a12, a4
beqz a7, tie728_s8_conv2d_1_1_unaligned_c_n_loop_end # output_channel < 16
EE.LD.128.USAR.IP q1, a2, 0
rur.sar_byte a14
beqi a14, 0, tie728_s8_conv2d_1_1_unaligned_c_n_loop0
beqi a14, 8, tie728_s8_unaligned_conv2d_11cn_loop8
# output sar_byte != 0 && != 8
tie728_s8_unaligned_conv2d_11cn_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_conv2d_11cn_loop_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_conv2d_11cn_loop_no_preload_bias:
tie728_s8_conv2d_1_1_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a14
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a11, a12, a13, a15, q1, q2
# store to unaligned address
dl_tie728_s8_unaligned_store0 q0, a2, a14
addi a7, a7, -1
bnez a7, tie728_s8_unaligned_conv2d_11cn_loop
j tie728_s8_conv2d_1_1_unaligned_c_n_loop_end
# output sar_byte == 0
tie728_s8_conv2d_1_1_unaligned_c_n_loop0:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_1_1_unaligned_c_n_loop0_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_1_1_unaligned_c_n_loop0_no_preload_bias:
tie728_s8_conv2d_1_1_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a14
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a11, a12, a13, a15, q1, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_1_1_unaligned_c_n_loop0
j tie728_s8_conv2d_1_1_unaligned_c_n_loop_end
# output sar_byte == 8
tie728_s8_unaligned_conv2d_11cn_loop8:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_conv2d_11cn_loop8_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_conv2d_11cn_loop8_no_preload_bias:
tie728_s8_conv2d_1_1_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a14
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a11, a12, a13, a15, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store1 q0, a2
addi a7, a7, -1
bnez a7, tie728_s8_unaligned_conv2d_11cn_loop8
j tie728_s8_conv2d_1_1_unaligned_c_n_loop_end
tie728_s8_conv2d_1_1_unaligned_c_n_loop_end:
# handle the n remainder
# s16i a10, a1, 0
EE.MOVI.32.Q q7, a10, 0 # store operation type in q7[0]
l32i a10, a4, 140 # n % 16 remainder_n
beqz a10, dl_tie728_s8_unaligned_conv2d_11cn_end
# n_remainder
tie728_s8_conv2d_1_1_c_unaligned_n_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.ACCX
# complete one n in ACCX
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_1_1_c_unaligned_n_loop_no_preload_bias
tie728_s8_conv2d_element_bias a11
tie728_s8_conv2d_1_1_c_unaligned_n_loop_no_preload_bias:
tie728_s8_conv2d_1_1_c_n_remainder q0, q1, q2, a15, q3, q4, q5, a5, a6, a9, a14, a7
tie728_s8_conv2d_1_1_n_remainder_result q7, a7, a2, a8, a11, a12, a13, a14, q0
# l16si a7, a1, 0
# mov a14, a7
# EE.SRS.ACCX a14, a8, 0
# clamps a14, a14, 7
# s8i a14, a2, 0
# addi a2, a2, 1
addi a10, a10, -1
bnez a10, tie728_s8_conv2d_1_1_c_unaligned_n_loop
dl_tie728_s8_unaligned_conv2d_11cn_end:
retw
############################################################################################################################################################
####
#### tie728_s16_conv2d_33cn series
####
############################################################################################################################################################
.macro tie728_s8_conv2d_33c16 input_v0 filter_v0 filter_v1 input_ptr filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro tie728_s8_conv2d_hwcn_load_args args filter_ptr c_div_x_1 n_rs3 dilation_x_offset dilation_y_offset
l32i \n_rs3, \args, 96 // output_channel_div_8
l32i \filter_ptr, \args, 48 // filter
l32i \c_div_x_1, \args, 100 // input_channel / x - 1
l32i \dilation_x_offset, \args, 108 // input dilation x offset
l32i \dilation_y_offset, \args, 112 // input dilation y offset
.endm
.align 4
.text
.global dl_tie728_s8_conv2d_33cn
.type dl_tie728_s8_conv2d_33cn, @function
# .section .iram1
dl_tie728_s8_conv2d_33cn:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: bias_ptr
# a12:
# a13:
# a14:
# a15: moving_input_ptr
tie728_s8_conv2d_hwcn_load_args a4, a5, a6, a7, a9, a10
l32i a11, a4, 68 # bias
l32i a8, a4, 64 # mac shift
blti a8, 0, dl_tie728_s8_conv2d_per_channel_33cn
dl_tie728_s8_conv2d_per_layer_33cn:
beqz a11, tie728_s8_conv2d_per_layer_33cn_no_bias_loop
tie728_s8_conv2d_per_layer_33cn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_33cn_bias_loop
retw
tie728_s8_conv2d_per_layer_33cn_no_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_33cn_no_bias_loop
retw
dl_tie728_s8_conv2d_per_channel_33cn:
l32i a8, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_conv2d_per_channel_33cn_no_bias_loop
tie728_s8_conv2d_per_channel_33cn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# tie728_s8_conv2d_bias q0, q1, a11
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a11, a15, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_33cn_bias_loop
retw
tie728_s8_conv2d_per_channel_33cn_no_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_33cn_no_bias_loop
retw
.align 4
.text
.global dl_tie728_s8_conv2d_33cn_relu
.type dl_tie728_s8_conv2d_33cn_relu, @function
# .section .iram1
dl_tie728_s8_conv2d_33cn_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: bias_ptr
# a12: activation_alpha
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s8_conv2d_hwcn_load_args a4, a5, a6, a7, a9, a10
l32i a12, a4, 76 # activation_alpha
l32i a13, a4, 84 # activation_shift
l32i a11, a4, 68 # bias
l32i a8, a4, 64 # mac shift
blti a8, 0, dl_tie728_s8_conv2d_per_channel_33cn_relu
dl_tie728_s8_conv2d_per_layer_33cn_relu:
beqz a11, tie728_s8_conv2d_per_layer_33cn_no_bias_relu_loop
tie728_s8_conv2d_per_layer_33cn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_33cn_bias_relu_loop
retw
tie728_s8_conv2d_per_layer_33cn_no_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_33cn_no_bias_relu_loop
retw
dl_tie728_s8_conv2d_per_channel_33cn_relu:
l32i a8, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_conv2d_per_channel_33cn_no_bias_relu_loop
tie728_s8_conv2d_per_channel_33cn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# tie728_s8_conv2d_bias_relu q0, q1, a11, a12, a13
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a11, a15, q2
tie728_s8_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_33cn_bias_relu_loop
retw
tie728_s8_conv2d_per_channel_33cn_no_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
tie728_s8_conv2d_relu q0, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_33cn_no_bias_relu_loop
retw
.align 4
.text
.global dl_tie728_s8_conv2d_33cn_prelu
.type dl_tie728_s8_conv2d_33cn_prelu, @function
# .section .iram1
dl_tie728_s8_conv2d_33cn_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: bias_ptr
# a12: activation_alpha
# a13: activation_shift
# a14:
# a15: moving_input_ptr
tie728_s8_conv2d_hwcn_load_args a4, a5, a6, a7, a9, a10
l32i a12, a4, 80 # activation_alpha_ptr
l32i a13, a4, 84 # activation_shift
l32i a11, a4, 68 # bias
l32i a8, a4, 64 # mac shift
blti a8, 0, dl_tie728_s8_conv2d_per_channel_33cn_prelu
dl_tie728_s8_conv2d_per_layer_33cn_prelu:
beqz a11, tie728_s8_conv2d_per_layer_33cn_no_bias_prelu_loop
tie728_s8_conv2d_per_layer_33cn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_33cn_bias_prelu_loop
retw
tie728_s8_conv2d_per_layer_33cn_no_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_33cn_no_bias_prelu_loop
retw
dl_tie728_s8_conv2d_per_channel_33cn_prelu:
l32i a8, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_conv2d_per_channel_33cn_no_bias_prelu_loop
tie728_s8_conv2d_per_channel_33cn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# tie728_s8_conv2d_bias_prelu q0, q1, a11, q2, a12, a13
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a11, a15, q2
tie728_s8_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_33cn_bias_prelu_loop
retw
tie728_s8_conv2d_per_channel_33cn_no_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_33c16 q0, q1, q2, a15, a5, a6, a9, a10
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
tie728_s8_conv2d_prelu q0, q2, a12, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_33cn_no_bias_prelu_loop
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_conv2d_33cn
####
############################################################################################################################################################
.macro tie728_s8_conv2d_3_3_unaligned_c input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_v1 filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset remainder_c input_sar
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro tie728_s8_conv2d_3_3_c_n_remainder input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_front_aligned filter_back_aligned filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset remainder_c input_sar filter_sar
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \input_sar, \filter_sar
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.align 4
.text
.global dl_tie728_s8_unaligned_conv2d_33cn
.type dl_tie728_s8_unaligned_conv2d_33cn, @function
# .section .iram1
dl_tie728_s8_unaligned_conv2d_33cn:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs4 / input_sar
# a8: channel_factor
# a9: input dilation x offset
# a10: input dilation y offset
# a10: / c_remainder
# a11: bias_ptr
# a12: activation_alpha
# a13: activation_shift / n_remainder
# a14: tmp variable: input_sar / operation_type q7[0]
# a15: moving_input_ptr
tie728_s8_conv2d_hwcn_load_args a4, a5, a6, a7, a9, a10
# l32i a7, a4, 96 // output_channel_div_8
# l32i a5, a4, 48 // filter
# l32i a6, a4, 100 // input_channel / x - 1
l32i a8, a4, 64 // mac_shift
l32i a11, a4, 68 // bias
#l32i a12, a4, 76 // activation_alpha
l32i a13, a4, 84 // activation_shift
l32i a12, a4, 80 // activation_alpha_ptr
tie728_s8_unaligned_conv2d_operation_type a14, a8, a11, a13, a12, a4
EE.MOVI.32.Q q7, a14, 0 # operation_type q7[0]
beqz a7, tie728_s8_conv2d_3_3_unaligned_c_n_loop_end # output_channel < 16
EE.LD.128.USAR.IP q1, a2, 0 # output sar_byte
rur.sar_byte a14
bgez a13, tie728_s8_conv2d_3_3_unaligned_c_n_activation
l32i a13, a4, 136 # c_remainder: c % 16, replace activation_shift
EE.MOVI.32.A q7, a12, 0 # operation_type, replace activation_alpha
beqi a14, 0, tie728_s8_conv2d_3_3_unaligned_c_n_loop0
beqi a14, 8, tie728_s8_conv2d_3_3_unaligned_c_n_loop8
# output sar_byte != 0 && != 8
tie728_s8_conv2d_3_3_unaligned_c_n_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_3_3_unaligned_c_n_loop_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_3_3_unaligned_c_n_loop_no_preload_bias:
tie728_s8_conv2d_3_3_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a10, a13, a14
tie728_s8_conv2d_1_1_unaligned_c_result a12, q0, a8, a11, a12, a13, a15, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store0 q0, a2, a14
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_3_3_unaligned_c_n_loop
j tie728_s8_conv2d_3_3_unaligned_c_n_loop_end
# output sar_byte == 0
tie728_s8_conv2d_3_3_unaligned_c_n_loop0:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_3_3_unaligned_c_n_loop0_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_3_3_unaligned_c_n_loop0_no_preload_bias:
tie728_s8_conv2d_3_3_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a10, a13, a14
tie728_s8_conv2d_1_1_unaligned_c_result a12, q0, a8, a11, a12, a13, a15, q1, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_3_3_unaligned_c_n_loop0
j tie728_s8_conv2d_3_3_unaligned_c_n_loop_end
# output sar_byte == 8
tie728_s8_conv2d_3_3_unaligned_c_n_loop8:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_3_3_unaligned_c_n_loop8_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_3_3_unaligned_c_n_loop8_no_preload_bias:
tie728_s8_conv2d_3_3_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a10, a13, a14
tie728_s8_conv2d_1_1_unaligned_c_result a12, q0, a8, a11, a12, a13, a15, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store1 q0, a2
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_3_3_unaligned_c_n_loop8
j tie728_s8_conv2d_3_3_unaligned_c_n_loop_end
tie728_s8_conv2d_3_3_unaligned_c_n_activation:
beqi a14, 0, tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop0
beqi a14, 8, tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop8
# output sar_byte != 0 && != 8
tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop_no_preload_bias:
l32i a13, a4, 136 # c_remainder: c % 16, replace activation_shift
tie728_s8_conv2d_3_3_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a10, a13, a14
EE.MOVI.32.A q7, a14, 0 # operation_type
l32i a13, a4, 84 # activation_shift
tie728_s8_conv2d_1_1_unaligned_c_result a14, q0, a8, a11, a12, a13, a15, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store0 q0, a2, a14
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop
j tie728_s8_conv2d_3_3_unaligned_c_n_loop_end
# output sar_byte == 0
tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop0:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop0_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop0_no_preload_bias:
l32i a13, a4, 136 # c_remainder: c % 16, replace activation_shift
tie728_s8_conv2d_3_3_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a10, a13, a14
EE.MOVI.32.A q7, a14, 0 # operation_type
l32i a13, a4, 84 # activation_shift
tie728_s8_conv2d_1_1_unaligned_c_result a14, q0, a8, a11, a12, a13, a15, q1, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop0
j tie728_s8_conv2d_3_3_unaligned_c_n_loop_end
# output sar_byte == 8
tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop8:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop8_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop8_no_preload_bias:
l32i a13, a4, 136 # c_remainder: c % 16, replace activation_shift
tie728_s8_conv2d_3_3_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a9, a10, a13, a14
EE.MOVI.32.A q7, a14, 0 # operation_type
l32i a13, a4, 84 # activation_shift
tie728_s8_conv2d_1_1_unaligned_c_result a14, q0, a8, a11, a12, a13, a15, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store1 q0, a2
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_3_3_unaligned_c_n_activation_loop8
j tie728_s8_conv2d_3_3_unaligned_c_n_loop_end
tie728_s8_conv2d_3_3_unaligned_c_n_loop_end:
# handle the n remainder
l32i a13, a4, 140 # n % 16 remainder_n
beqz a13, dl_tie728_s8_unaligned_conv2d_33cn_end
l32i a14, a4, 84 # activation_shift
bgez a14, tie728_s8_conv2d_3_3_c_unaligned_n_activation
l32i a12, a4, 136 # c_remainder: c % 16, replace activation_shift
# n_remainder
tie728_s8_conv2d_3_3_c_unaligned_n_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.ACCX
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_3_3_c_unaligned_n_loop_no_preload_bias
tie728_s8_conv2d_element_bias a11
tie728_s8_conv2d_3_3_c_unaligned_n_loop_no_preload_bias:
# complete one n in ACCX
tie728_s8_conv2d_3_3_c_n_remainder q0, q1, q2, a15, q3, q4, q5, a5, a6, a9, a10, a12, a14, a7
tie728_s8_conv2d_1_1_n_remainder_result q7, a7, a2, a8, a11, a12, a13, a14, q0
addi a13, a13, -1
bnez a13, tie728_s8_conv2d_3_3_c_unaligned_n_loop
j dl_tie728_s8_unaligned_conv2d_33cn_end
tie728_s8_conv2d_3_3_c_unaligned_n_activation:
EE.MOVI.32.Q q6, a13, 0 # store remainder_n in q6[0]
# n_remainder
tie728_s8_conv2d_3_3_c_unaligned_n_activation_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.ACCX
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_conv2d_3_3_c_unaligned_n_activation_loop_no_preload_bias
tie728_s8_conv2d_element_bias a11
tie728_s8_conv2d_3_3_c_unaligned_n_activation_loop_no_preload_bias:
# complete one n in ACCX
l32i a13, a4, 136 # c_remainder: c % 16, replace activation_shift
tie728_s8_conv2d_3_3_c_n_remainder q0, q1, q2, a15, q3, q4, q5, a5, a6, a9, a10, a13, a14, a7
l32i a13, a4, 84 # activation_shift
tie728_s8_conv2d_1_1_n_remainder_result q7, a7, a2, a8, a11, a12, a13, a14, q0
EE.MOVI.32.A q6, a13, 0 # remainder_n in q6[0]
addi a13, a13, -1
EE.MOVI.32.Q q6, a13, 0
bnez a13, tie728_s8_conv2d_3_3_c_unaligned_n_activation_loop
dl_tie728_s8_unaligned_conv2d_33cn_end:
retw
############################################################################################################################################################
####
#### tie728_s8_conv2d_hwcn series
####
############################################################################################################################################################
.macro tie728_s8_conv2d_hwc16 input_v0 input_ptr filter_v0 filter_v1 filter_ptr c_div_x_1 dilation_x_offset dilation_y_offset filter_h filter_w filter_offset_q, args
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
# filter_h
# filter_w
l32i \filter_w, \args, 56 # filter_width
blti \filter_w, 2, 3f
l32i \filter_h, \args, 52 # filter_height
1:
l32i \filter_w, \args, 56 # filter_width
2:
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bgei \filter_w, 2, 2b
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
add \filter_ptr, \filter_ptr, \filter_w
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 1b
j 5f
# filter_w == 1
3:
l32i \filter_h, \args, 52 # filter_height
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
4:
tie728_s8_conv2d_11c16 \input_v0, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1
add \filter_ptr, \filter_ptr, \filter_w
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 4b
5:
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.align 4
.text
.global dl_tie728_s8_conv2d_hwcn
.type dl_tie728_s8_conv2d_hwcn, @function
# .section .iram1
dl_tie728_s8_conv2d_hwcn:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height
# a12: filter_width
# a13: bias_ptr
# a14: filter_y_offset
# a15: moving_input_ptr
tie728_s8_conv2d_hwcn_load_args a4, a5, a6, a7, a9, a10
l32i a13, a4, 68 # bias
l32i a8, a4, 64 # mac shift
l32i a12, a4, 60 # filter_y_offset
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1 #filter_y_offset
EE.MOVI.32.Q q6, a11, 2 #filter_n_offset
dl_tie728_s8_conv2d_per_layer_hwcn:
beqz a13, tie728_s8_conv2d_per_layer_hwcn_no_bias_loop
tie728_s8_conv2d_per_layer_hwcn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_hwcn_bias_loop
retw
tie728_s8_conv2d_per_layer_hwcn_no_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_vector_round_result q0, a8, a15, q3
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_hwcn_no_bias_loop
retw
dl_tie728_s8_conv2d_per_channel_hwcn:
l32i a8, a4, 104 # filter_channel_factor address
beqz a13, tie728_s8_conv2d_per_channel_hwcn_no_bias_loop
tie728_s8_conv2d_per_channel_hwcn_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# tie728_s8_conv2d_bias q0, q1, a13
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a13, a15, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_hwcn_bias_loop
retw
tie728_s8_conv2d_per_channel_hwcn_no_bias_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_hwcn_no_bias_loop
retw
.align 4
.text
.global dl_tie728_s8_conv2d_hwcn_relu
.type dl_tie728_s8_conv2d_hwcn_relu, @function
# .section .iram1
dl_tie728_s8_conv2d_hwcn_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs3
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height / activation_shift
# a12: filter_width
# a13: bias_ptr
# a14: activation_alpha
# a15: moving_input_ptr
tie728_s8_conv2d_hwcn_load_args a4, a5, a6, a7, a9, a10
l32i a14, a4, 76 # activation_alpha
# l32i a13, a4, 84 # activation_shift
l32i a13, a4, 68 # bias
l32i a8, a4, 64 # mac shift
l32i a12, a4, 60 # filter_y_offset
l32i a11, a4, 144 # filter_n_offset
EE.MOVI.32.Q q6, a12, 1
EE.MOVI.32.Q q6, a11, 2
blti a8, 0, dl_tie728_s8_conv2d_per_channel_hwcn_relu
dl_tie728_s8_conv2d_per_layer_hwcn_relu:
beqz a13, tie728_s8_conv2d_per_layer_hwcn_no_bias_relu
tie728_s8_conv2d_per_layer_hwcn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_vector_round_result q0, a8, a15, q3
l32i a11, a4, 84 # activation_shift
tie728_s8_conv2d_relu q0, a14, a11
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_hwcn_bias_relu_loop
retw
tie728_s8_conv2d_per_layer_hwcn_no_bias_relu:
l32i a13, a4, 84 # activation_shift
tie728_s8_conv2d_per_layer_hwcn_no_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_relu q0, a14, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_hwcn_no_bias_relu_loop
retw
dl_tie728_s8_conv2d_per_channel_hwcn_relu:
l32i a8, a4, 104 # filter_channel_factor address
beqz a13, tie728_s8_conv2d_per_channel_hwcn_no_bias_relu
tie728_s8_conv2d_per_channel_hwcn_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# l32i a11, a4, 84 # activation_shift
# tie728_s8_conv2d_bias_relu q0, q1, a13, a14, a11
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a13, a15, q2
l32i a11, a4, 84 # activation_shift
tie728_s8_conv2d_relu q0, a14, a11
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_hwcn_bias_relu_loop
retw
tie728_s8_conv2d_per_channel_hwcn_no_bias_relu:
l32i a13, a4, 84 # activation_shift
tie728_s8_conv2d_per_channel_hwcn_no_bias_relu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
tie728_s8_conv2d_relu q0, a14, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_hwcn_no_bias_relu_loop
retw
.align 4
.text
.global dl_tie728_s8_conv2d_hwcn_prelu
.type dl_tie728_s8_conv2d_hwcn_prelu, @function
# .section .iram1
dl_tie728_s8_conv2d_hwcn_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs4
# a8: mac_shift
# a9: input dilation x offset
# a10: input dilation y offset
# a11: filter_height / activation_shift
# a12: filter_width
# a13: bias_ptr
# a14: activation_alpha
# a15: moving_input_ptr
tie728_s8_conv2d_hwcn_load_args a4, a5, a6, a7, a9, a10
l32i a14, a4, 80 # activation_alpha_ptr
# l32i a13, a4, 84 # activation_shift
l32i a13, a4, 68 # bias
l32i a8, a4, 64 # mac shift
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1
EE.MOVI.32.Q q6, a11, 2
blti a8, 0, dl_tie728_s8_conv2d_per_channel_hwcn_prelu
dl_tie728_s8_conv2d_per_layer_hwcn_prelu:
beqz a13, tie728_s8_conv2d_per_layer_hwcn_no_bias_prelu
tie728_s8_conv2d_per_layer_hwcn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_vector_round_result q0, a8, a15, q3
l32i a11, a4, 84 # activation_shift
tie728_s8_conv2d_prelu q0, q2, a14, a11
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_hwcn_bias_prelu_loop
retw
tie728_s8_conv2d_per_layer_hwcn_no_bias_prelu:
l32i a13, a4, 84 # activation_shift
tie728_s8_conv2d_per_layer_hwcn_no_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_vector_round_result q0, a8, a15, q3
tie728_s8_conv2d_prelu q0, q2, a14, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_layer_hwcn_no_bias_prelu_loop
retw
dl_tie728_s8_conv2d_per_channel_hwcn_prelu:
l32i a8, a4, 104 # filter_channel_factor address
beqz a13, tie728_s8_conv2d_per_channel_hwcn_no_bias_prelu
tie728_s8_conv2d_per_channel_hwcn_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
# tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
# l32i a11, a4, 84 # activation_shift
# tie728_s8_conv2d_bias_prelu q0, q1, a13, q2, a14, a11
tie728_s8_conv2d_per_channel_with_bias_result q0, q1, a8, a13, a15, q2
l32i a11, a4, 84 # activation_shift
tie728_s8_conv2d_prelu q0, q2, a14, a11
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_hwcn_bias_prelu_loop
retw
tie728_s8_conv2d_per_channel_hwcn_no_bias_prelu:
l32i a13, a4, 84 # activation_shift
tie728_s8_conv2d_per_channel_hwcn_no_bias_prelu_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
tie728_s8_conv2d_hwc16 q0, a15, q1, q2, a5, a6, a9, a10, a11, a12, q6, a4
tie728_s8_conv2d_per_channel_result q0, q1, a8, a15, q2
tie728_s8_conv2d_prelu q0, q2, a14, a13
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_per_channel_hwcn_no_bias_prelu_loop
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_conv2d_hwcn series
####
############################################################################################################################################################
.macro tie728_s8_conv2d_h_w_unaligned_c input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_v1 filter_ptr c_div_x_1 filter_h filter_w args remainder_c tmp filter_offset_q
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
# filter_h
# filter_w
l32i \filter_w, \args, 56 # filter_width
blti \filter_w, 2, 23f
l32i \filter_h, \args, 52 # filter_height
21:
l32i \filter_w, \args, 56 # filter_width
22:
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \tmp
l32i \tmp, \args, 108 # input dilation x offset
add \input_ptr, \input_ptr, \tmp
addi \filter_w, \filter_w, -1
bgei \filter_w, 2, 22b
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \tmp
l32i \tmp, \args, 112 # input dilation y offset
add \input_ptr, \input_ptr, \tmp
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
add \filter_ptr, \filter_ptr, \filter_w
addi \filter_h, \filter_h, -1
bnez \filter_h, 21b
j 25f
# filter_w == 1
23:
l32i \filter_h, \args, 52 # filter_height
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
24:
tie728_s8_conv2d_1_1_unaligned_c \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \remainder_c, \tmp
l32i \tmp, \args, 112 # input dilation y offset
add \input_ptr, \input_ptr, \tmp
add \filter_ptr, \filter_ptr, \filter_w
addi \filter_h, \filter_h, -1
bnez \filter_h, 24b
25:
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.macro tie728_s8_conv2d_h_w_c_n_remainder input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_front_aligned filter_back_aligned filter_ptr c_div_x_1 args filter_h filter_w remainder_c tmp tmp1 filter_offset_q
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
# filter_h
# filter_w
l32i \filter_w, \args, 56 # filter_width
blti \filter_w, 2, 22f
l32i \filter_h, \args, 52 # filter_height
21:
l32i \filter_w, \args, 56 # filter_width
20:
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \tmp, \tmp1
l32i \tmp, \args, 108 # input dilation x offset
add \input_ptr, \input_ptr, \tmp
addi \filter_w, \filter_w, -1
bgei \filter_w, 2, 20b
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \tmp, \tmp1
l32i \tmp, \args, 112 # input dilation y offset
add \input_ptr, \input_ptr, \tmp
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
add \filter_ptr, \filter_ptr, \filter_w
addi \filter_h, \filter_h, -1
bnez \filter_h, 21b
j 24f
# filter_w == 1
22:
l32i \filter_h, \args, 52 # filter_height
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
23:
tie728_s8_conv2d_1_1_c_n_remainder \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \c_div_x_1, \remainder_c, \tmp, \tmp1
l32i \tmp, \args, 112 # input dilation y offset
add \input_ptr, \input_ptr, \tmp
add \filter_ptr, \filter_ptr, \filter_w
addi \filter_h, \filter_h, -1
bnez \filter_h, 23b
24:
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.align 4
.text
.global dl_tie728_s8_unaligned_conv2d_hwcn
.type dl_tie728_s8_unaligned_conv2d_hwcn, @function
# .section .iram1
dl_tie728_s8_unaligned_conv2d_hwcn:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: c_div_x_1
# a7: n_rs4
# a8: mac_shift
# a9: remainder_c
# a10: tmp / input dilation x offset / input dilation y offset
# a11: filter_height / activation_shift
# a12: filter_width
# a13: bias_ptr
# a14: activation_alpha_ptr
# a15: moving_input_ptr
tie728_s8_conv2d_hwcn_load_args a4, a5, a6, a7, a9, a10
# l32i a7, a4, 96 // output_channel_div_8
# l32i a5, a4, 48 // filter
# l32i a6, a4, 100 // input_channel / x - 1
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q6, a12, 1
EE.MOVI.32.Q q6, a11, 2
l32i a8, a4, 64 // mac_shift
l32i a13, a4, 68 // bias
#l32i a14, a4, 76 // activation_alpha
l32i a11, a4, 84 // activation_shift
l32i a14, a4, 80 // activation_alpha_ptr
tie728_s8_unaligned_conv2d_operation_type a12, a8, a13, a11, a14, a4
EE.MOVI.32.Q q7, a12, 0 # operation_type q7[0]
beqz a7, tie728_s8_conv2d_h_w_unaligned_c_n_loop_end # output_channel < 16
EE.LD.128.USAR.IP q1, a2, 0 # output sar_byte
rur.sar_byte a12
bgez a11, tie728_s8_conv2d_h_w_unaligned_c_n_activation
l32i a9, a4, 136 # c_remainder: c % 16
EE.MOVI.32.A q7, a10, 0 # operation_type
beqi a12, 0, tie728_s8_conv2d_h_w_unaligned_c_n_loop0
beqi a12, 8, tie728_s8_conv2d_h_w_unaligned_c_n_loop8
# output sar_byte != 0 && != 8
tie728_s8_conv2d_h_w_unaligned_c_n_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a13, tie728_s8_conv2d_h_w_unaligned_c_n_loop_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_h_w_unaligned_c_n_loop_no_preload_bias:
tie728_s8_conv2d_h_w_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a11, a12, a4, a9, a14, q6
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a13, a11, a11, a11, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store0 q0, a2, a14
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_h_w_unaligned_c_n_loop
j tie728_s8_conv2d_h_w_unaligned_c_n_loop_end
# output sar_byte == 0
tie728_s8_conv2d_h_w_unaligned_c_n_loop0:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a13, tie728_s8_conv2d_h_w_unaligned_c_n_loop0_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_h_w_unaligned_c_n_loop0_no_preload_bias:
tie728_s8_conv2d_h_w_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a11, a12, a4, a9, a14, q6
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a13, a11, a11, a11, q1, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_h_w_unaligned_c_n_loop0
j tie728_s8_conv2d_h_w_unaligned_c_n_loop_end
# output sar_byte == 8
tie728_s8_conv2d_h_w_unaligned_c_n_loop8:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a13, tie728_s8_conv2d_h_w_unaligned_c_n_loop8_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_h_w_unaligned_c_n_loop8_no_preload_bias:
tie728_s8_conv2d_h_w_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a11, a12, a4, a9, a14, q6
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a13, a11, a11, a11, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store1 q0, a2
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_h_w_unaligned_c_n_loop8
j tie728_s8_conv2d_h_w_unaligned_c_n_loop_end
tie728_s8_conv2d_h_w_unaligned_c_n_activation:
l32i a9, a4, 136 # c_remainder: c % 16
EE.LD.128.USAR.IP q1, a2, 0 # output sar_byte
rur.sar_byte a12
beqi a12, 0, tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop0
beqi a12, 8, tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop8
# output sar_byte != 0 && != 8
tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a13, tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop_no_preload_bias:
tie728_s8_conv2d_h_w_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a11, a12, a4, a9, a10, q6
EE.MOVI.32.A q7, a10, 0 # operation_type
l32i a11, a4, 84 # activation_shift
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a13, a14, a11, a15, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store0 q0, a2, a11
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop
j tie728_s8_conv2d_h_w_unaligned_c_n_loop_end
# output sar_byte == 0
tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop0:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a13, tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop0_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop0_no_preload_bias:
tie728_s8_conv2d_h_w_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a11, a12, a4, a9, a10, q6
EE.MOVI.32.A q7, a10, 0 # operation_type
l32i a11, a4, 84 # activation_shift
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a13, a14, a11, a15, q1, q2
EE.VST.128.IP q0, a2, 16
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop0
j tie728_s8_conv2d_h_w_unaligned_c_n_loop_end
# output sar_byte == 8
tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop8:
mov a15, a3 # reload input_ptr
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a13, tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop8_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a13
tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop8_no_preload_bias:
tie728_s8_conv2d_h_w_unaligned_c q0, q1, q2, a15, q3, q4, a5, a6, a11, a12, a4, a9, a10, q6
EE.MOVI.32.A q7, a10, 0 # operation_type
l32i a11, a4, 84 # activation_shift
tie728_s8_conv2d_1_1_unaligned_c_result a10, q0, a8, a13, a14, a11, a15, q1, q2
#store to unaligned address
dl_tie728_s8_unaligned_store1 q0, a2
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_h_w_unaligned_c_n_activation_loop8
j tie728_s8_conv2d_h_w_unaligned_c_n_loop_end
tie728_s8_conv2d_h_w_unaligned_c_n_loop_end:
# handle the n remainder
l32i a7, a4, 140 # n % 16 remainder_n
beqz a7, dl_tie728_s8_unaligned_conv2d_hwcn_end
l32i a5, a4, 160
l32i a11, a4, 164
EE.MOVI.32.Q q6, a5, 1
EE.MOVI.32.Q q6, a11, 2
l32i a5, a4, 168 # filter_ptr unaligned
l32i a11, a4, 84 # activation_shift
l32i a9, a4, 136 # c_remainder: c % 16
bgez a11, tie728_s8_conv2d_h_w_c_unaligned_n_activation
# n_remainder
tie728_s8_conv2d_h_w_c_unaligned_n_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.ACCX
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a13, tie728_s8_conv2d_h_w_c_unaligned_n_loop_no_preload_bias
tie728_s8_conv2d_element_bias a13
tie728_s8_conv2d_h_w_c_unaligned_n_loop_no_preload_bias:
# complete one n in ACCX
tie728_s8_conv2d_h_w_c_n_remainder q0, q1, q2, a15, q3, q4, q5, a5, a6, a4, a11, a12, a9, a10, a14, q6
tie728_s8_conv2d_1_1_n_remainder_result q7, a10, a2, a8, a13, a11, a11, a11, q0
addi a7, a7, -1
bnez a7, tie728_s8_conv2d_h_w_c_unaligned_n_loop
j dl_tie728_s8_unaligned_conv2d_hwcn_end
tie728_s8_conv2d_h_w_c_unaligned_n_activation:
EE.MOVI.32.Q q6, a7, 0 # store remainder_n in q6[0]
# n_remainder
tie728_s8_conv2d_h_w_c_unaligned_n_activation_loop:
mov a15, a3 # reload input_ptr
EE.ZERO.ACCX
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a13, tie728_s8_conv2d_h_w_c_unaligned_n_activation_loop_no_preload_bias
tie728_s8_conv2d_element_bias a13
tie728_s8_conv2d_h_w_c_unaligned_n_activation_loop_no_preload_bias:
# complete one n in ACCX
tie728_s8_conv2d_h_w_c_n_remainder q0, q1, q2, a15, q3, q4, q5, a5, a6, a4, a11, a12, a9, a10, a7, q6
l32i a11, a4, 84 # activation_shift
tie728_s8_conv2d_1_1_n_remainder_result q7, a10, a2, a8, a13, a14, a11, a15, q0
EE.MOVI.32.A q6, a7, 0
addi a7, a7, -1
EE.MOVI.32.Q q6, a7, 0 # store remainder_n in q6[0]
bnez a7, tie728_s8_conv2d_h_w_c_unaligned_n_activation_loop
dl_tie728_s8_unaligned_conv2d_hwcn_end:
retw
|
georgevio/IoT-Embedded
| 65,903
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_depthwise_conv2d.S
|
#include "dl_tie728_s8.S"
############################################################################################################################################################
####
#### tie728_s8_depthwise_conv2d_33c1 series
####
############################################################################################################################################################
.macro tie728_s8_depthwise_conv2d_33s1 input_v0 filter_v0 input_v1 filter_v1 input_v2 filter_v2 input_ptr filter_ptr dilation_x_offset dilation_y_offset next_33s1
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_33s1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
# EE.ZERO.QACC
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v2, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v2, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v2, \input_ptr, \next_33s1
EE.VMULAS.S8.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
.endm
.macro tie728_s8_depthwise_conv2d_33s1_last input_v0 filter_v0 input_v1 filter_v1 input_ptr filter_ptr dilation_x_offset dilation_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# EE.ZERO.QACC
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.IP \input_v0, \input_ptr, 0
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
# block one cycle here
EE.VMULAS.S8.QACC \input_v0, \filter_v0
.endm
.macro tie728_s8_depthwise_conv2d_33c1_load_args args filter_ptr dilation_x_offset dilation_y_offset next_33s1 c_div_x_1
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_33s1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
l32i \filter_ptr, \args, 48
l32i \dilation_x_offset, \args, 124
l32i \dilation_y_offset, \args, 128
l32i \next_33s1, \args, 132
l32i \c_div_x_1, \args, 100
.endm
.align 4
.text
.global dl_tie728_s8_depthwise_conv2d_33c1
.type dl_tie728_s8_depthwise_conv2d_33c1, @function
# .section .iram1
dl_tie728_s8_depthwise_conv2d_33c1:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_33s1
# a9: c_div_x_1
# a10: mac_shift
# a11: bias_ptr
# a12:
# a13:
# a14:
# a15:
tie728_s8_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9
l32i a10, a4, 64 # mac shift
l32i a11, a4, 68 # bias
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
blti a10, 0, dl_tie728_s8_depthwise_conv2d_per_channel_33c1
dl_tie728_s8_depthwise_conv2d_per_layer_33c1:
beqz a11, tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias
loopgtz a9, tie728_s8_depthwise_conv2d_per_layer_33c1_bias_loop
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_vector_round_result q3, a10, a15, q6
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_layer_33c1_bias_loop:
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_vector_round_result q3, a10, a15, q6
EE.VST.128.IP q3, a2, 16
retw
tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias:
loopgtz a9, tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_vector_round_result q3, a10, a15, q6
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_vector_round_result q3, a10, a15, q6
EE.VST.128.IP q3, a2, 16
retw
dl_tie728_s8_depthwise_conv2d_per_channel_33c1:
l32i a10, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias
loopgtz a9, tie728_s8_depthwise_conv2d_per_channel_33c1_bias_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
# tie728_s8_conv2d_bias q3, q4, a11
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a11, a15, q5
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_channel_33c1_bias_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
# tie728_s8_conv2d_bias q3, q4, a11
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a11, a15, q5
EE.VST.128.IP q3, a2, 16
retw
tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias:
loopgtz a9, tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
EE.VST.128.IP q3, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_depthwise_conv2d_33c1_relu
.type dl_tie728_s8_depthwise_conv2d_33c1_relu, @function
# .section .iram1
dl_tie728_s8_depthwise_conv2d_33c1_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_33s1
# a9: c_div_x_1
# a10: mac_shift
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15:
tie728_s8_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9
l32i a10, a4, 64 # mac shift
l32i a11, a4, 68 # bias
l32i a12, a4, 76 # activation_alpha
l32i a13, a4, 84 # activation_shift
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
blti a10, 0, dl_tie728_s8_depthwise_conv2d_per_channel_33c1_relu
dl_tie728_s8_depthwise_conv2d_per_layer_33c1_relu:
beqz a11, tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_relu
loopgtz a9, tie728_s8_depthwise_conv2d_per_layer_33c1_bias_relu_loop
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_vector_round_result q3, a10, a15, q6
tie728_s8_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_layer_33c1_bias_relu_loop:
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_vector_round_result q3, a10, a15, q6
tie728_s8_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
retw
tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_relu:
loopgtz a9, tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_relu_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_vector_round_result q3, a10, a15, q6
tie728_s8_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_relu_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_vector_round_result q3, a10, a15, q6
tie728_s8_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
retw
dl_tie728_s8_depthwise_conv2d_per_channel_33c1_relu:
l32i a10, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_relu
loopgtz a9, tie728_s8_depthwise_conv2d_per_channel_33c1_bias_relu_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
# tie728_s8_conv2d_bias_relu q3, q4, a11, a12, a13
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a11, a15, q5
tie728_s8_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_channel_33c1_bias_relu_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
# tie728_s8_conv2d_bias_relu q3, q4, a11, a12, a13
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a11, a15, q5
tie728_s8_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
retw
tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_relu:
loopgtz a9, tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_relu_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
tie728_s8_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_relu_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
tie728_s8_conv2d_relu q3, a12, a13
EE.VST.128.IP q3, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_depthwise_conv2d_33c1_prelu
.type dl_tie728_s8_depthwise_conv2d_33c1_prelu, @function
# .section .iram1
dl_tie728_s8_depthwise_conv2d_33c1_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_33s1
# a9: c_div_x_1
# a10: mac_shift
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15:
tie728_s8_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9
l32i a10, a4, 64 # mac shift
l32i a11, a4, 68 # bias
l32i a12, a4, 80 # activation_alpha_ptr
l32i a13, a4, 84 # activation_shift
EE.VLD.128.XP q0, a3, a6
EE.VLD.128.IP q1, a5, 16
EE.VLD.128.XP q2, a3, a6
blti a10, 0, dl_tie728_s8_depthwise_conv2d_per_channel_33c1_prelu
dl_tie728_s8_depthwise_conv2d_per_layer_33c1_prelu:
beqz a11, tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_prelu
loopgtz a9, tie728_s8_depthwise_conv2d_per_layer_33c1_bias_prelu_loop
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_vector_round_result q3, a10, a15, q6
tie728_s8_conv2d_prelu q3, q5, a12, a13
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_layer_33c1_bias_prelu_loop:
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_vector_round_result q3, a10, a15, q6
tie728_s8_conv2d_prelu q3, q5, a12, a13
EE.VST.128.IP q3, a2, 16
retw
tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_prelu:
loopgtz a9, tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_prelu_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_vector_round_result q3, a10, a15, q6
tie728_s8_conv2d_prelu q3, q5, a12, a13
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_layer_33c1_no_bias_prelu_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_vector_round_result q3, a10, a15, q6
tie728_s8_conv2d_prelu q3, q5, a12, a13
EE.VST.128.IP q3, a2, 16
retw
dl_tie728_s8_depthwise_conv2d_per_channel_33c1_prelu:
l32i a10, a4, 104 # filter_channel_factor address
beqz a11, tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_prelu
loopgtz a9, tie728_s8_depthwise_conv2d_per_channel_33c1_bias_prelu_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
# tie728_s8_conv2d_bias_prelu q3, q4, a11, q5, a12, a13
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a11, a15, q5
tie728_s8_conv2d_prelu q3, q5, a12, a13
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_channel_33c1_bias_prelu_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
# tie728_s8_conv2d_bias_prelu q3, q4, a11, q5, a12, a13
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a11, a15, q5
tie728_s8_conv2d_prelu q3, q5, a12, a13
EE.VST.128.IP q3, a2, 16
retw
tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_prelu:
loopgtz a9, tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_prelu_loop
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
tie728_s8_conv2d_prelu q3, q4, a12, a13
EE.VST.128.IP q3, a2, 16
tie728_s8_depthwise_conv2d_per_channel_33c1_no_bias_prelu_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, a5, a6, a7
tie728_s8_conv2d_per_channel_result q3, q4, a10, a15, q5
tie728_s8_conv2d_prelu q3, q4, a12, a13
EE.VST.128.IP q3, a2, 16
retw
.macro tie728_s8_unaligned_depthwise_conv2d_33s1 input_v0 input_v1 input_v2 input_back_aligned input_ptr filter_v0 filter_v1 filter_v2 filter_ptr dilation_x_offset dilation_y_offset next_33s1
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_33s1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
# EE.ZERO.QACC
# EE.LD.128.USAR.IP \input_v2, \input_ptr, 16
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \next_33s1
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back_aligned
.endm
.macro tie728_s8_unaligned_depthwise_conv2d_33s1_last input_v0 input_v1 input_v2 input_back_aligned input_ptr filter_v0 filter_v1 filter_ptr dilation_x_offset dilation_y_offset next_33s1
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# EE.ZERO.QACC
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v2, \filter_v0
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v1
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v2, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v1
EE.SRC.Q.LD.IP \input_v2, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \next_33s1
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q \input_v2, \input_v2, \input_back_aligned
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VMULAS.S8.QACC \input_v2, \filter_v0
.endm
.macro tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_front_aligned filter_back_aligned filter_ptr dilation_x_offset remainder_c
EE.LD.128.USAR.XP \input_front_aligned, \input_ptr, \remainder_c
# rur.sar_byte \input_sar #input sar
# EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
# wur.sar_byte \input_sar #input sar
EE.VLD.128.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.SRC.Q \input_v0, \input_front_aligned, \input_back_aligned
EE.LD.128.USAR.XP \filter_front_aligned, \filter_ptr, \remainder_c
# rur.sar_byte \filter_sar #filter sar
# EE.LD.128.USAR.IP \filter_back_aligned, \filter_ptr, 0
# wur.sar_byte \filter_sar #filter sar
EE.VLD.128.IP \filter_back_aligned, \filter_ptr, 0
EE.SRC.Q \filter_v0, \filter_front_aligned, \filter_back_aligned
EE.VMULAS.S8.QACC \input_v0, \filter_v0
.endm
.macro tie728_s8_depthwise_conv2d_unaligned_c_slice_updatey input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_front_aligned filter_back_aligned filter_ptr dilation_y_offset remainder_c
# input remainder is in one 128bit then input_back_aligned = input_front_aligned
EE.LD.128.USAR.XP \input_front_aligned, \input_ptr, \remainder_c
# rur.sar_byte \input_sar #input sar
# EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
# wur.sar_byte \input_sar #input sar
EE.VLD.128.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.SRC.Q \input_v0, \input_front_aligned, \input_back_aligned
EE.LD.128.USAR.XP \filter_front_aligned, \filter_ptr, \remainder_c
# rur.sar_byte \filter_sar #filter sar
# EE.LD.128.USAR.IP \filter_back_aligned, \filter_ptr, 0
# wur.sar_byte \filter_sar #filter sar
EE.VLD.128.IP \filter_back_aligned, \filter_ptr, 0
EE.SRC.Q \filter_v0, \filter_front_aligned, \filter_back_aligned
EE.VMULAS.S8.QACC \input_v0, \filter_v0
.endm
.macro tie728_s8_depthwise_conv2d_33s1_c_remainder input_v0 input_front_aligned input_back_aligned filter_v0 filter_front_aligned filter_back_aligned input_ptr filter_ptr dilation_x_offset dilation_y_offset remainder_c
# dilation_x_offset = input_channel_with_padding * dilation_x * remainder_c
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * remainder_c
# EE.ZERO.QACC
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatey \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_y_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatey \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_y_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
EE.LD.128.USAR.XP \input_front_aligned, \input_ptr, \remainder_c
# rur.sar_byte \input_sar #input sar
# EE.LD.128.USAR.IP \input_back_aligned, \input_ptr, 0
# wur.sar_byte \input_sar #input sar
EE.VLD.128.IP \input_back_aligned, \input_ptr, 0
EE.SRC.Q \input_v0, \input_front_aligned, \input_back_aligned
EE.LD.128.USAR.XP \filter_front_aligned, \filter_ptr, \remainder_c
# rur.sar_byte \filter_sar #filter sar
# EE.LD.128.USAR.IP \filter_back_aligned, \filter_ptr, 0
# wur.sar_byte \filter_sar #filter sar
EE.VLD.128.IP \filter_back_aligned, \filter_ptr, 0
EE.SRC.Q \filter_v0, \filter_front_aligned, \filter_back_aligned
EE.VMULAS.S8.QACC \input_v0, \filter_v0
.endm
.align 4
.text
.global dl_tie728_s8_unaligned_depthwise_conv2d_33c1
.type dl_tie728_s8_unaligned_depthwise_conv2d_33c1, @function
# .section .iram1
dl_tie728_s8_unaligned_depthwise_conv2d_33c1:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_33s1 / remainder_c
# a9: c_div_x_1
# a10: mac_shift
# a11: bias_ptr
# a12: activation_alpha/_address
# a13: activation_shift
# a14:
# a15: operation_type /
tie728_s8_depthwise_conv2d_33c1_load_args a4, a5, a6, a7, a8, a9
l32i a10, a4, 64 # mac_shift
l32i a11, a4, 68 # bias
#l32i a12, a4, 76 # activation_alpha
l32i a13, a4, 84 # activation_shift
l32i a12, a4, 80 # activation_alpha_ptr
tie728_s8_unaligned_conv2d_operation_type a15, a10, a11, a13, a12, a4
addi a6, a6, -16
addi a7, a7, -16
l32i a14, a4, 4
blti a14, 16, tie728_s8_unaligned_depthwise_conv2d_33c1_c_loop_end # input_channel < 16
EE.LD.128.USAR.IP q2, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
EE.VLD.128.IP q4, a5, 16 # filter_v0
EE.SRC.Q.QUP q0, q2, q3 # input_v0
EE.LD.128.USAR.IP q2, a3, 16
EE.LD.128.USAR.XP q3, a3, a6
addi a8, a8, -16
EE.SRC.Q.QUP q1, q2, q3 # input_v1
EE.LD.128.USAR.IP q2, a3, 16 # input_v2
EE.LD.128.USAR.IP q6, a2, 0 #get output_ptr sar_byte
rur.sar_byte a14
beqi a14, 0, tie728_s8_unaligned_depthwise_conv2d_33c1_0
beqi a14, 8, tie728_s8_unaligned_depthwise_conv2d_33c1_8
# output sar_byte != 0 && != 8
beqi a9, 0, tie728_s8_unaligned_depthwise_conv2d_33c1_loop_last
tie728_s8_unaligned_depthwise_conv2d_33c1_loop:
# loopgtz a9, tie728_s8_unaligned_depthwise_conv2d_33c1_loop # Internal error in istack_push_space
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_depthwise_conv2d_33c1_loop_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_depthwise_conv2d_33c1_loop_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, a3, q4, q5, q6, a5, a6, a7, a8
tie728_s8_conv2d_1_1_unaligned_c_result a15, q3, a10, a11, a12, a13, a14, q5, q6
# tie728_s8_conv2d_per_layer_result q3, a10
#store to unaligned address
dl_tie728_s8_unaligned_store0 q3, a2, a14
addi a9, a9, -1
bnez a9, tie728_s8_unaligned_depthwise_conv2d_33c1_loop
tie728_s8_unaligned_depthwise_conv2d_33c1_loop_last:
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_depthwise_conv2d_33c1_loop_last_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_depthwise_conv2d_33c1_loop_last_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, q4, q5, a5, a6, a7, a8
tie728_s8_conv2d_1_1_unaligned_c_result a15, q3, a10, a11, a12, a13, a14, q5, q6
#store to unaligned address
dl_tie728_s8_unaligned_store0 q3, a2, a14
j tie728_s8_unaligned_depthwise_conv2d_33c1_c_loop_end
# output sar_byte == 0
tie728_s8_unaligned_depthwise_conv2d_33c1_0:
beqi a9, 0, tie728_s8_unaligned_depthwise_conv2d_33c1_loop0_last
tie728_s8_unaligned_depthwise_conv2d_33c1_loop0:
# loopgtz a9, tie728_s8_unaligned_depthwise_conv2d_33c1_loop0
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_depthwise_conv2d_33c1_loop0_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_depthwise_conv2d_33c1_loop0_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, a3, q4, q5, q6, a5, a6, a7, a8
tie728_s8_conv2d_1_1_unaligned_c_result a15, q3, a10, a11, a12, a13, a14, q5, q6
EE.VST.128.IP q3, a2, 16
# tie728_s8_unaligned_depthwise_conv2d_33c1_loop0:
addi a9, a9, -1
bnez a9, tie728_s8_unaligned_depthwise_conv2d_33c1_loop0
tie728_s8_unaligned_depthwise_conv2d_33c1_loop0_last:
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_depthwise_conv2d_33c1_loop0_last_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_depthwise_conv2d_33c1_loop0_last_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, q4, q5, a5, a6, a7, a8
tie728_s8_conv2d_1_1_unaligned_c_result a15, q3, a10, a11, a12, a13, a14, q5, q6
EE.VST.128.IP q3, a2, 16
j tie728_s8_unaligned_depthwise_conv2d_33c1_c_loop_end
# output sar_byte == 8
tie728_s8_unaligned_depthwise_conv2d_33c1_8:
beqi a9, 0, tie728_s8_unaligned_depthwise_conv2d_33c1_loop8_last
tie728_s8_unaligned_depthwise_conv2d_33c1_loop8:
# loopgtz a9, tie728_s8_unaligned_depthwise_conv2d_33c1_loop8
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_depthwise_conv2d_33c1_loop8_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_depthwise_conv2d_33c1_loop8_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, a3, q4, q5, q6, a5, a6, a7, a8
tie728_s8_conv2d_1_1_unaligned_c_result a15, q3, a10, a11, a12, a13, a14, q5, q6
#store to unaligned address
dl_tie728_s8_unaligned_store1 q3, a2
addi a9, a9, -1
# tie728_s8_unaligned_depthwise_conv2d_33c1_loop8:
bnez a9, tie728_s8_unaligned_depthwise_conv2d_33c1_loop8
tie728_s8_unaligned_depthwise_conv2d_33c1_loop8_last:
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_depthwise_conv2d_33c1_loop8_last_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_depthwise_conv2d_33c1_loop8_last_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, a3, q4, q5, a5, a6, a7, a8
tie728_s8_conv2d_1_1_unaligned_c_result a15, q3, a10, a11, a12, a13, a14, q5, q6
dl_tie728_s8_unaligned_store1 q3, a2
tie728_s8_unaligned_depthwise_conv2d_33c1_c_loop_end:
l32i a8, a4, 136 # c_remainder
beqz a8, dl_tie728_s8_unaligned_depthwise_conv2d_33c1_end
# mov a9, a15 #operation_type
addi a6, a6, 16
addi a7, a7, 16
sub a6, a6, a8
sub a7, a7, a8
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a11, tie728_s8_unaligned_depthwise_conv2d_33c1_c_loop_end_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a11
tie728_s8_unaligned_depthwise_conv2d_33c1_c_loop_end_no_preload_bias:
tie728_s8_depthwise_conv2d_33s1_c_remainder q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8
tie728_s8_conv2d_1_1_unaligned_c_result a15, q3, a10, a11, a12, a13, a14, q4, q5
# store low remainder_c part
dl_tie728_s8_store_remainder q3, a10, a11, a12, a13, a2, a8
dl_tie728_s8_unaligned_depthwise_conv2d_33c1_end:
retw
############################################################################################################################################################
####
#### tie728_s8_depthwise_conv2d_hwc1 series
####
############################################################################################################################################################
.macro tie728_s8_depthwise_conv2d_1ws1 input_v0 input_v1 input_v2 filter_v0 filter_v1 filter_v2 input_ptr filter_ptr dilation_x_offset dilation_y_offset filter_h filter_w filter_w_rs1_1 filter_y_offset
loopgtz \filter_w_rs1_1, 1f
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
1:
bbci \filter_w, 0, 2f
# three 8-input-element left
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v2, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.XP \filter_v2, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2 # block one cyle here
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
j 3f
2: # two 8-input-element left
EE.VMULAS.S8.QACC.LD.XP \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \dilation_y_offset
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1 # block one cyle here
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
3:
.endm
.macro tie728_s8_depthwise_conv2d_1ws1_last input_v0 input_v1 filter_v0 filter_v1 input_ptr filter_ptr dilation_x_offset dilation_y_offset filter_h filter_w filter_w_rs1_1 next_hws1 filter_y_offset
loopgtz \filter_w_rs1_1, 4f
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
4:
bbci \filter_w, 0, 5f
# three 8-input-element left
EE.VMULAS.S8.QACC.LD.IP \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \next_hws1
EE.VMULAS.S8.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
# block one cyle here
EE.VMULAS.S8.QACC \input_v0, \filter_v0
j 6f
5: # two 8-input-element left
EE.VMULAS.S8.QACC.LD.XP \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \next_hws1
EE.VMULAS.S8.QACC \input_v1, \filter_v1
6:
.endm
.macro tie728_s8_depthwise_conv2d_hws1 input_v0 input_v1 input_v2 filter_v0 filter_v1 filter_v2 input_ptr filter_ptr dilation_x_offset dilation_y_offset next_hws1 filter_h filter_w filter_w_rs1_1 args filter_offset_q filter_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hws1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
# filter_w_rs1_1
# EE.ZERO.QACC
l32i \filter_h, \args, 52 # filter_height
blti \filter_w, 2, 9f
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_x_offset
EE.VLD.128.XP \input_v1, \input_ptr, \dilation_x_offset
blti \filter_h, 2, 8f
7:
tie728_s8_depthwise_conv2d_1ws1 \input_v0, \input_v1, \input_v2, \filter_v0, \filter_v1, \filter_v2, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \filter_h, \filter_w, \filter_w_rs1_1, \filter_y_offset
addi \filter_h, \filter_h, -1
bgei \filter_h, 2, 7b
8: # last y
tie728_s8_depthwise_conv2d_1ws1_last \input_v0, \input_v1, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \filter_h, \filter_w, \filter_w_rs1_1, \next_hws1, \filter_y_offset
j 12f
# filter_w == 1
9:
EE.VLD.128.XP \filter_v0, \filter_ptr, \filter_y_offset
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_y_offset
blti \filter_h, 2, 11f
10:
EE.VMULAS.S8.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
EE.VLD.128.XP \input_v0, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bgei \filter_h, 2, 10b
11: # last y
EE.VMULAS.S8.QACC \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset
add \input_ptr, \input_ptr, \next_hws1
12:
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.macro tie728_s8_depthwise_conv2d_hwc1_load_args args filter_ptr dilation_x_offset dilation_y_offset next_hws1 c_div_x_1 filter_w filter_w_rs1_1
tie728_s8_depthwise_conv2d_33c1_load_args \args, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \next_hws1, \c_div_x_1
l32i \filter_w, \args, 56
l32i \filter_w_rs1_1, \args, 148
.endm
.align 4
.text
.global dl_tie728_s8_depthwise_conv2d_hwc1
.type dl_tie728_s8_depthwise_conv2d_hwc1, @function
# .section .iram1
dl_tie728_s8_depthwise_conv2d_hwc1:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hws1
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h
# a12: filter_w
# a13: filter_w_rs1_1
# a14: bias_ptr
# a15:
l32i a15, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a11, 2
tie728_s8_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a12, a13
l32i a10, a4, 64 # mac shift
l32i a14, a4, 68 # bias
blti a10, 0, dl_tie728_s8_depthwise_conv2d_per_channel_hwc1
dl_tie728_s8_depthwise_conv2d_per_layer_hwc1:
beqz a14, tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias
tie728_s8_depthwise_conv2d_per_layer_hwc1_bias_loop:
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a14
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_vector_round_result q3, a10, a11, q6
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_layer_hwc1_bias_loop
retw
tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_vector_round_result q3, a10, a11, q6
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias
retw
dl_tie728_s8_depthwise_conv2d_per_channel_hwc1:
l32i a10, a4, 104 # filter_channel_factor address
beqz a14, tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias
tie728_s8_depthwise_conv2d_per_channel_hwc1_bias_loop:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a11, q5
# tie728_s8_conv2d_bias q3, q4, a14
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a14, a11, q5
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_channel_hwc1_bias_loop
retw
tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias:
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_conv2d_per_channel_result q3, q4, a10, a11, q5
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias
retw
.align 4
.text
.global dl_tie728_s8_depthwise_conv2d_hwc1_relu
.type dl_tie728_s8_depthwise_conv2d_hwc1_relu, @function
# .section .iram1
dl_tie728_s8_depthwise_conv2d_hwc1_relu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hws1
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h
# a12: filter_w
# a13: filter_w_rs1_1
# a14: bias_ptr
# a15: activation_alpha
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
tie728_s8_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a12, a13
l32i a10, a4, 64 # mac shift
l32i a15, a4, 76 # activation_alpha
l32i a14, a4, 68 # bias
EE.MOVI.32.Q q7, a15, 3
blti a10, 0, dl_tie728_s8_depthwise_conv2d_per_channel_hwc1_relu
dl_tie728_s8_depthwise_conv2d_per_layer_hwc1_relu:
beqz a14, tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias_relu
tie728_s8_depthwise_conv2d_per_layer_hwc1_bias_relu_loop:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a14
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_vector_round_result q3, a10, a11, q6
l32i a11, a4, 84 # activation_shift
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_relu q3, a15, a11
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_layer_hwc1_bias_relu_loop
retw
tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias_relu:
l32i a14, a4, 84 # activation_shift
tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias_relu_loop:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_vector_round_result q3, a10, a11, q6
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_relu q3, a15, a14
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias_relu_loop
retw
dl_tie728_s8_depthwise_conv2d_per_channel_hwc1_relu:
l32i a10, a4, 104 # filter_channel_factor address
beqz a14, tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias_relu
tie728_s8_depthwise_conv2d_per_channel_hwc1_bias_relu_loop:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a11, q5
# l32i a11, a4, 84 # activation_shift
# EE.MOVI.32.A q7, a15, 3
# tie728_s8_conv2d_bias_relu q3, q4, a14, a15, a11
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a14, a11, q5
l32i a11, a4, 84 # activation_shift
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_relu q3, a15, a11
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_channel_hwc1_bias_relu_loop
retw
tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias_relu:
l32i a14, a4, 84 # activation_shift
tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias_relu_loop:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_conv2d_per_channel_result q3, q4, a10, a11, q5
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_relu q3, a15, a14
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias_relu_loop
retw
.align 4
.text
.global dl_tie728_s8_depthwise_conv2d_hwc1_prelu
.type dl_tie728_s8_depthwise_conv2d_hwc1_prelu, @function
# .section .iram1
dl_tie728_s8_depthwise_conv2d_hwc1_prelu:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hws1
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h
# a12: filter_w
# a13: filter_w_rs1_1
# a14: bias_ptr
# a15: activation_alpha_ptr
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
tie728_s8_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a12, a13
l32i a10, a4, 64 # mac shift
l32i a15, a4, 80 # activation_alpha_ptr
l32i a14, a4, 68 # bias
EE.MOVI.32.Q q7, a15, 3
blti a10, 0, dl_tie728_s8_depthwise_conv2d_per_channel_hwc1_prelu
dl_tie728_s8_depthwise_conv2d_per_layer_hwc1_prelu:
beqz a14, tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias_prelu
tie728_s8_depthwise_conv2d_per_layer_hwc1_bias_prelu_loop:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
tie728_s8_conv2d_128b_vector_bias a14
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_vector_round_result q3, a10, a11, q6
l32i a11, a4, 84 # activation_shift
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_prelu q3, q5, a15, a11
EE.MOVI.32.Q q7, a15, 3
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_layer_hwc1_bias_prelu_loop
retw
tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias_prelu:
l32i a14, a4, 84 # activation_shift
tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias_prelu_loop:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_vector_round_result q3, a10, a11, q6
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_prelu q3, q5, a15, a14
EE.MOVI.32.Q q7, a15, 3
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_layer_hwc1_no_bias_prelu_loop
retw
dl_tie728_s8_depthwise_conv2d_per_channel_hwc1_prelu:
l32i a10, a4, 104 # filter_channel_factor address
beqz a14, tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias_prelu
tie728_s8_depthwise_conv2d_per_channel_hwc1_bias_prelu_loop:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
# tie728_s8_conv2d_per_channel_result q3, q4, a10, a11, q5
tie728_s8_conv2d_per_channel_with_bias_result q3, q4, a10, a14, a11, q5
l32i a11, a4, 84 # activation_shift
EE.MOVI.32.A q7, a15, 3
# tie728_s8_conv2d_bias_prelu q3, q4, a14, q5, a15, a11
tie728_s8_conv2d_prelu q3, q5, a15, a11
EE.MOVI.32.Q q7, a15, 3
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_channel_hwc1_bias_prelu_loop
retw
tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias_prelu:
l32i a14, a4, 84 # activation_shift
tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias_prelu_loop:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
tie728_s8_depthwise_conv2d_hws1 q0, q1, q2, q3, q4, q5, a3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
tie728_s8_conv2d_per_channel_result q3, q4, a10, a11, q5
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_prelu q3, q5, a15, a14
EE.MOVI.32.Q q7, a15, 3
EE.VST.128.IP q3, a2, 16
addi a9, a9, -1
bgez a9, tie728_s8_depthwise_conv2d_per_channel_hwc1_no_bias_prelu_loop
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_depthwise_conv2d_hwc1 series
####
############################################################################################################################################################
.macro tie728_s8_depthwise_conv2d_unaligned_c_slice_updatey_padding input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_front_aligned filter_back_aligned filter_ptr dilation_y_offset remainder_c filter_y_offset
EE.LD.128.USAR.XP \input_front_aligned, \input_ptr, \remainder_c
EE.VLD.128.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.SRC.Q \input_v0, \input_front_aligned, \input_back_aligned
EE.LD.128.USAR.XP \filter_front_aligned, \filter_ptr, \remainder_c
EE.VLD.128.XP \filter_back_aligned, \filter_ptr, \filter_y_offset
EE.SRC.Q \filter_v0, \filter_front_aligned, \filter_back_aligned
EE.VMULAS.S8.QACC \input_v0, \filter_v0
.endm
.macro tie728_s8_unaligned_depthwise_conv2d_1ws1 input_v0 input_v1 input_back_aligned input_ptr filter_v0 filter_ptr dilation_x_offset dilation_y_offset filter_w filter_w_rs1_1 filter_y_offset
loopgtz \filter_w_rs1_1, 1f
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
1:
bbci \filter_w, 0, 2f
# three 8-input-element left
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q \input_v0, \input_v1, \input_back_aligned
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
j 3f
2: # two 8-input-element left
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
3:
.endm
.macro tie728_s8_unaligned_depthwise_conv2d_1ws1_last input_v0 input_v1 input_back_aligned input_ptr filter_v0 filter_ptr dilation_x_offset filter_w filter_w_rs1_1 next_hws1 filter_y_offset
loopgtz \filter_w_rs1_1, 4f
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
EE.SRC.Q.LD.IP \input_v1, \input_ptr, 16, \input_v0, \input_back_aligned
4:
bbci \filter_w, 0, 5f
# three 16byte left
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VMULAS.S8.QACC.LD.IP \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
EE.SRC.Q.LD.IP \input_v0, \input_ptr, 16, \input_v1, \input_back_aligned
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \next_hws1
EE.VMULAS.S8.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v0
EE.SRC.Q \input_v0, \input_v0, \input_back_aligned
EE.VMULAS.S8.QACC \input_v0, \filter_v0
j 6f
5: # two 16byte left
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \next_hws1
EE.VMULAS.S8.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
EE.SRC.Q \input_v1, \input_v1, \input_back_aligned
EE.VMULAS.S8.QACC \input_v1, \filter_v0
6:
.endm
.macro tie728_s8_unaligned_depthwise_conv2d_hws1 input_v0 input_v1 input_back_aligned input_ptr filter_v0 filter_ptr dilation_x_offset dilation_y_offset next_hws1 filter_h filter_w filter_w_rs1_1 args filter_offset_q filter_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hws1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
# filter_w_rs1_1
# EE.ZERO.QACC
l32i \filter_h, \args, 52 # filter_height
blti \filter_w, 2, 9f
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_x_offset
EE.VLD.128.IP \filter_v0, \filter_ptr, 16 # filter_v0
EE.SRC.Q \input_v0, \input_v1, \input_back_aligned # input_v0
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
blti \filter_h, 2, 8f
7:
tie728_s8_unaligned_depthwise_conv2d_1ws1 \input_v0, \input_v1, \input_back_aligned, \input_ptr, \filter_v0, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \filter_w, \filter_w_rs1_1 \filter_y_offset
addi \filter_h, \filter_h, -1
bgei \filter_h, 2, 7b
8: # last y
tie728_s8_unaligned_depthwise_conv2d_1ws1_last \input_v0, \input_v1, \input_back_aligned, \input_ptr, \filter_v0, \filter_ptr, \dilation_x_offset, \filter_w, \filter_w_rs1_1, \next_hws1 \filter_y_offset
j 12f
# filter_w == 1
9:
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.VLD.128.XP \filter_v0, \filter_ptr, \filter_y_offset # filter_v0
EE.SRC.Q \input_v0, \input_v1, \input_back_aligned # input_v0
blti \filter_h, 2, 11f
addi \filter_h, \filter_h, -1
loopgtz \filter_h, 10f
EE.LD.128.USAR.IP \input_v1, \input_ptr, 16
EE.LD.128.USAR.XP \input_back_aligned, \input_ptr, \dilation_y_offset
EE.VMULAS.S8.QACC.LD.XP \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
EE.SRC.Q \input_v0, \input_v1, \input_back_aligned
10:
11: # last y
EE.VMULAS.S8.QACC \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset
add \input_ptr, \input_ptr, \next_hws1
12:
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.macro tie728_s8_unaligned_depthwise_conv2d_hws1_c_remainder input_v0 input_front_aligned input_back_aligned input_ptr filter_v0 filter_front_aligned filter_back_aligned filter_ptr dilation_x_offset dilation_y_offset filter_h filter_w filter_w_rs1_1 remainder_c args filter_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * remainder_c
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * remainder_c
# EE.ZERO.QACC
l32i \filter_h, \args, 52 # filter_height
blti \filter_w, 2, 5f
4:
loopgtz \filter_w_rs1_1, 1f
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
1:
bbci \filter_w, 0, 2f
# 3 left
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatey_padding \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_y_offset, \remainder_c, \filter_y_offset
j 3f
2:
# 2 left
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatex \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_x_offset, \remainder_c
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatey_padding \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_y_offset, \remainder_c, \filter_y_offset
3:
addi \filter_h, \filter_h, -1
bgei \filter_h, 1, 4b
j 7f
5:
# filter_w == 1
loopgtz \filter_h, 6f
tie728_s8_depthwise_conv2d_unaligned_c_slice_updatey_padding \input_v0, \input_front_aligned, \input_back_aligned, \input_ptr, \filter_v0, \filter_front_aligned, \filter_back_aligned, \filter_ptr, \dilation_y_offset, \remainder_c, \filter_y_offset
6:
7:
.endm
.align 4
.text
.global dl_tie728_s8_unaligned_depthwise_conv2d_hwc1
.type dl_tie728_s8_unaligned_depthwise_conv2d_hwc1, @function
# .section .iram1
dl_tie728_s8_unaligned_depthwise_conv2d_hwc1:
.align 4
entry sp, 128
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: int8_t *filter_ptr
# a6: input dilation x offset
# a7: input dilation y offset
# a8: next_hws1
# a9: c_div_x_1
# a10: mac_shift
# a11: filter_h
# a12: filter_w
# a13: filter_w_rs1_1
# a14: bias_ptr
# a15: activation_alpha_ptr
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a10, a4, 64 # mac shift
l32i a14, a4, 68 # bias
# l32i a12, a4, 76 # activation_alpha
l32i a11, a4, 84 # activation_shift
l32i a15, a4, 80 # activation_alpha_ptr
tie728_s8_unaligned_conv2d_operation_type a12, a10, a14, a11, a15, a4
EE.MOVI.32.Q q7, a12, 0 #operation type
EE.MOVI.32.Q q7, a15, 3
tie728_s8_depthwise_conv2d_hwc1_load_args a4, a5, a6, a7, a8, a9, a12, a13
addi a6, a6, -16
addi a7, a7, -16
addi a8, a8, -16
# EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
# rur.sar_byte a11
# beqi a9, 0, tie728_s8_unaligned_depthwise_conv2d_hwc1_loop_last
l32i a11, a4, 4 #input_channel
blti a11, 16, tie728_s8_unaligned_depthwise_conv2d_hwc1_c_loop_end #input_channel < 16
l32i a11, a4, 84 # activation_shift
blti a11, 0, tie728_s8_unaligned_depthwise_conv2d_hwc1_no_activation
tie728_s8_unaligned_depthwise_conv2d_hwc1_with_activation:
tie728_s8_unaligned_depthwise_conv2d_hwc1_loop:
l32i a13, a4, 148 # filter_w_rs1_1
l32i a12, a4, 56 # filter_w
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a14, tie728_s8_unaligned_depthwise_conv2d_hwc1_loop_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a14
tie728_s8_unaligned_depthwise_conv2d_hwc1_loop_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, a3, q3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
EE.MOVI.32.A q7, a13, 0 #operation type
l32i a12, a4, 84 # activation_shift
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_1_1_unaligned_c_result a13, q4, a10, a14, a15, a12, a11, q5, q6
EE.MOVI.32.Q q7, a15, 3
#store to unaligned address
dl_tie728_s8_unaligned_store0 q4, a2, a11
addi a9, a9, -1
bgez a9, tie728_s8_unaligned_depthwise_conv2d_hwc1_loop
j tie728_s8_unaligned_depthwise_conv2d_hwc1_c_loop_end
tie728_s8_unaligned_depthwise_conv2d_hwc1_no_activation:
# EE.MOVI.32.A q7, a15, 0 #operation type
tie728_s8_unaligned_depthwise_conv2d_hwc1_loop_no_act:
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a14, tie728_s8_unaligned_depthwise_conv2d_hwc1_loop_no_act_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a14
tie728_s8_unaligned_depthwise_conv2d_hwc1_loop_no_act_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, a3, q3, a5, a6, a7, a8, a11, a12, a13, a4, q7, a15
EE.MOVI.32.A q7, a15, 0
tie728_s8_conv2d_1_1_unaligned_c_result a15, q4, a10, a14, a11, a11, a11, q5, q6
#store to unaligned address
dl_tie728_s8_unaligned_store0 q4, a2, a11
addi a9, a9, -1
bgez a9, tie728_s8_unaligned_depthwise_conv2d_hwc1_loop_no_act
j tie728_s8_unaligned_depthwise_conv2d_hwc1_c_loop_end
tie728_s8_unaligned_depthwise_conv2d_hwc1_c_loop_end:
l32i a8, a4, 136 # c_remainder
beqz a8, dl_tie728_s8_unaligned_depthwise_conv2d_hwc1_end
l32i a12, a4, 160
l32i a5, a4, 168 # filter_ptr unaligned
EE.MOVI.32.Q q7, a12, 1
addi a6, a6, 16
addi a7, a7, 16
sub a6, a6, a8
sub a7, a7, a8
EE.MOVI.32.A q7, a9, 0 # operation type
l32i a13, a4, 148 # filter_w_rs1_1
l32i a12, a4, 56 # filter_w
EE.MOVI.32.A q7, a15, 1
EE.ZERO.QACC
# Without modifications specifically for per-channel, there may be issues with per-channel
beqz a14, tie728_s8_unaligned_depthwise_conv2d_hwc1_c_loop_end_no_preload_bias
tie728_s8_conv2d_128b_vector_bias a14
tie728_s8_unaligned_depthwise_conv2d_hwc1_c_loop_end_no_preload_bias:
tie728_s8_unaligned_depthwise_conv2d_hws1_c_remainder q0, q1, q2, a3, q3, q4, q5, a5, a6, a7, a11, a12, a13, a8, a4, a15
l32i a12, a4, 84 # activation_shift
EE.MOVI.32.A q7, a15, 3
tie728_s8_conv2d_1_1_unaligned_c_result a9, q3, a10, a14, a15, a12, a11, q4, q5
# store low remainder_c part
dl_tie728_s8_store_remainder q3, a10, a11, a12, a13, a2, a8
dl_tie728_s8_unaligned_depthwise_conv2d_hwc1_end:
# addi a2, a2, -16
retw
|
georgevio/IoT-Embedded
| 3,508
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_relu.S
|
#include "dl_tie728_s16.S"
.align 4
.text
.global dl_tie728_s16_relu_11c
.type dl_tie728_s16_relu_11c, @function
.section .iram1
dl_tie728_s16_relu_11c:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: c_rs1_1: c / 2x - 1
# a6: c_rs2_1: c_left_1
# a14: activation_alpha
# a15: activation_shift
l32i a5, a4, 88
l32i a6, a4, 92
l32i a14, a4, 76 # activation_alpha
l32i a15, a4, 84 # activation_shift
loopgtz a5, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a3, 16
EE.VRELU.S16 q0, a14, a15
EE.VST.128.IP q0, a2, 16
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
0:
blti a6, 0, 5f
loopgtz a6, 1f
EE.VLD.128.IP q0, a3, 16
EE.VRELU.S16 q0, a14, a15
EE.VST.128.IP q0, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VRELU.S16 q0, a14, a15
EE.VST.128.IP q0, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_relu_11c
.type dl_tie728_s16_unaligned_relu_11c, @function
.section .iram1
dl_tie728_s16_unaligned_relu_11c:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: c_div_x_1
# a6: c_remainder
# a14: activation_alpha
# a15: activation_shift
l32i a5, a4, 100
l32i a6, a4, 136
l32i a14, a4, 76 # activation_alpha
l32i a15, a4, 84 # activation_shift
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a5, 0, dl_tie718_s16_unaligned_relu_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s16_unaligned_relu_11c_0
beqi a13, 8, dl_tie718_s16_unaligned_relu_11c_1
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie718_s16_unaligned_relu_11c_remainder
dl_tie718_s16_unaligned_relu_11c_0:
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_s16_unaligned_relu_11c_remainder
dl_tie718_s16_unaligned_relu_11c_1:
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store1 q2, a2
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie718_s16_unaligned_relu_11c_remainder
dl_tie718_s16_unaligned_relu_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a6
rur.sar_byte a11
dl_tie718_s16_unaligned_relu_11c_remainder:
beqz a6, dl_tie728_s16_unaligned_relu_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.VRELU.S16 q2, a14, a15
srli a6, a6, 1
dl_tie728_s16_store_remainder q2, a6, a13, a2
dl_tie728_s16_unaligned_relu_11c_end:
retw
|
georgevio/IoT-Embedded
| 17,283
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_mul.S
|
#include "dl_tie728_s16.S"
#void dl_tie728_s16_mul_w1_8_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_mul_w1_8_w2_8
.type dl_tie728_s16_mul_w1_8_w2_8, @function
#.section .iram1
dl_tie728_s16_mul_w1_8_w2_8:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a8:
# a9:
# a10:
# a11:
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a7, a5, 80
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
mov a14, a6
blti a14, 1, dl_tie728_s16_mul_w1_8_w2_8_loop_last
dl_tie728_s16_mul_w1_8_w2_8_loop:
ee.zero.qacc
ee.vmulas.s16.qacc.ld.ip q0, a3, 16, q0, q1
ee.vld.128.ip q1, a4, 16
tie728_s16_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, dl_tie728_s16_mul_w1_8_w2_8_loop
dl_tie728_s16_mul_w1_8_w2_8_loop_last:
ee.zero.qacc
ee.vmulas.s16.qacc q0, q1
tie728_s16_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
retw
#void dl_tie728_s16_mul_w1_8_w2_1(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_mul_w1_8_w2_1
.type dl_tie728_s16_mul_w1_8_w2_1, @function
#.section .iram1
dl_tie728_s16_mul_w1_8_w2_1:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a8:
# a9:
# a10:
# a11:
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a7, a5, 80
ee.vld.128.ip q0, a3, 16
ee.vldbc.16.ip q1, a4, 0 // input1 broadcast
mov a14, a6
blti a14, 1, dl_tie728_s16_mul_w1_8_w2_1_loop_last
dl_tie728_s16_mul_w1_8_w2_1_loop:
ee.zero.qacc
ee.vmulas.s16.qacc.ld.ip q0, a3, 16, q0, q1
tie728_s16_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, dl_tie728_s16_mul_w1_8_w2_1_loop
dl_tie728_s16_mul_w1_8_w2_1_loop_last:
ee.zero.qacc
ee.vmulas.s16.qacc q0, q1
tie728_s16_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
retw
#void dl_tie728_s16_mul_w1_1_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_mul_w1_1_w2_8
.type dl_tie728_s16_mul_w1_1_w2_8, @function
#.section .iram1
dl_tie728_s16_mul_w1_1_w2_8:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a8:
# a9:
# a10:
# a11:
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions):
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a7, a5, 80
ee.vldbc.16.ip q0, a3, 0 // input0 broadcast
ee.vld.128.ip q1, a4, 16
mov a14, a6
blti a14, 1, dl_tie728_s16_mul_w1_1_w2_8_loop_last
dl_tie728_s16_mul_w1_1_w2_8_loop:
ee.zero.qacc
ee.vmulas.s16.qacc.ld.ip q1, a4, 16, q0, q1
tie728_s16_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, dl_tie728_s16_mul_w1_1_w2_8_loop
dl_tie728_s16_mul_w1_1_w2_8_loop_last:
ee.zero.qacc
ee.vmulas.s16.qacc q0, q1
tie728_s16_vector_round_result q2, a7, a12, q7
ee.vst.128.ip q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_mul_w1_8_w2_8_unaligned
.type dl_tie728_s16_mul_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_mul_w1_8_w2_8_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11: mul_shift
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions): tmp value
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
l32i a11, a5, 80
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s16_mul_w1_8_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s16_mul_w1_8_w2_8_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_mul_w1_8_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_mul_w1_8_w2_8_unaligned_remainder
// output sar = 0
dl_tie728_s16_mul_w1_8_w2_8_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_mul_w1_8_w2_8_unaligned_remainder
// output sar = 8
dl_tie728_s16_mul_w1_8_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.zero.qacc
ee.src.q.qup q5, q3, q4
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_mul_w1_8_w2_8_unaligned_remainder
dl_tie728_s16_mul_w1_8_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_mul_w1_8_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.zero.qacc
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_mul_w1_8_w2_8_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s16_mul_w1_8_w2_1_unaligned
.type dl_tie728_s16_mul_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s16_mul_w1_8_w2_1_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11: mul_shift
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions): tmp value
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
l32i a11, a5, 80
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s16_mul_w1_8_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s16_mul_w1_8_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_mul_w1_8_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_mul_w1_8_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s16_mul_w1_8_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_mul_w1_8_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s16_mul_w1_8_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_mul_w1_8_w2_1_unaligned_remainder
dl_tie728_s16_mul_w1_8_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s16_mul_w1_8_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.zero.qacc
ee.src.q q2, q0, q1
ee.vmulas.s16.qacc q2, q5
tie728_s16_vector_round_result q2, a11, a12, q7
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_mul_w1_8_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s16_mul_w1_1_w2_8_unaligned
.type dl_tie728_s16_mul_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_mul_w1_1_w2_8_unaligned:
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr broadcast
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11: mul_shift
# a12(not for extension instructions): tmp value
# a13(not for extension instructions):
# a14(not for extension instructions): tmp value
# a15(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
entry sp, 128
l32i a6, a5, 64
l32i a10, a5, 76
l32i a11, a5, 80
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s16_mul_w1_1_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s16_mul_w1_1_w2_8_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s16_mul_w1_1_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q5, q2
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q5, q2
tie728_s16_vector_round_result q2, a11, a12, q7
dl_tie728_128b_unaligned_store0 q2, a2, a7
j dl_tie728_s16_mul_w1_1_w2_8_unaligned_remainder
// output sar = 0
dl_tie728_s16_mul_w1_1_w2_8_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q5, q2
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q5, q2
tie728_s16_vector_round_result q2, a11, a12, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s16_mul_w1_1_w2_8_unaligned_remainder
// output sar = 8
dl_tie728_s16_mul_w1_1_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q5, q2
tie728_s16_vector_round_result q2, a11, a12, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s16.qacc q5, q2
tie728_s16_vector_round_result q2, a11, a12, q7
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_mul_w1_1_w2_8_unaligned_remainder
dl_tie728_s16_mul_w1_1_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_mul_w1_1_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.zero.qacc
ee.src.q q2, q0, q1
ee.vmulas.s16.qacc q5, q2
tie728_s16_vector_round_result q2, a11, a12, q7
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a8, a2
dl_tie728_s16_mul_w1_1_w2_8_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 11,892
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_greater.S
|
#include "dl_tie728_s8.S"
#include "dl_tie728_s16.S"
#void dl_tie728_s16_greater_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_greater_w1_8_w2_8
.type dl_tie728_s16_greater_w1_8_w2_8, @function
#.section .iram1
dl_tie728_s16_greater_w1_8_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
movi a14, 0
tie728_s16_greater_w1_8_w2_8_loop:
beq a14, a5, tie728_s16_greater_w1_8_w2_8_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.gt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_greater_w1_8_w2_8_loop
tie728_s16_greater_w1_8_w2_8_end:
retw
#void dl_tie728_s16_greater_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_greater_w1_8_w2_1
.type dl_tie728_s16_greater_w1_8_w2_1, @function
#.section .iram1
dl_tie728_s16_greater_w1_8_w2_1:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s16_greater_w1_8_w2_1_loop:
beq a14, a5, tie728_s16_greater_w1_8_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.gt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_greater_w1_8_w2_1_loop
tie728_s16_greater_w1_8_w2_1_end:
retw
#void dl_tie728_s16_greater_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s16_greater_w1_1_w2_8
.type dl_tie728_s16_greater_w1_1_w2_8, @function
#.section .iram1
dl_tie728_s16_greater_w1_1_w2_8:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.16.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 3
ee.vldbc.16.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s16_greater_w1_1_w2_8_loop:
beq a14, a5, tie728_s16_greater_w1_1_w2_8_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.gt.s16 q2, q0, q1
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, 1
j tie728_s16_greater_w1_1_w2_8_loop
tie728_s16_greater_w1_1_w2_8_end:
retw
.align 4
.text
.global dl_tie728_s16_greater_w1_8_w2_8_unaligned
.type dl_tie728_s16_greater_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_greater_w1_8_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s16_greater_w1_8_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_greater_w1_8_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_greater_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_greater_w1_8_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
// ee.vst.128.ip q2, a2, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_greater_w1_8_w2_8_unaligned_remainder
dl_tie728_s16_greater_w1_8_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_greater_w1_8_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_greater_w1_8_w2_8_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s16_greater_w1_8_w2_1_unaligned
.type dl_tie728_s16_greater_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s16_greater_w1_8_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s16_greater_w1_8_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_greater_w1_8_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_greater_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_greater_w1_8_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_greater_w1_8_w2_1_unaligned_remainder
dl_tie728_s16_greater_w1_8_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s16_greater_w1_8_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.gt.s16 q2, q2, q5
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_greater_w1_8_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s16_greater_w1_1_w2_8_unaligned
.type dl_tie728_s16_greater_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_tie728_s16_greater_w1_1_w2_8_unaligned:
# a2: bool *output_ptr
# a3: int16_t *input0_ptr broadcast
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14: tmp value
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.16.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.16.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s16_greater_w1_1_w2_8_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
movi a14, 7
and a14, a7, a14
beqz a14, dl_tie728_s16_greater_w1_1_w2_8_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
dl_tie728_128b_unaligned_l_store0 q2, a2, a7
j dl_tie728_s16_greater_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_tie728_s16_greater_w1_1_w2_8_unaligned_64b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.ld.128.usar.ip q1, a4, 16
ee.vst.l.64.ip q2, a2, 8
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
ee.vst.l.64.ip q2, a2, 8
// j dl_tie728_s16_greater_w1_1_w2_8_unaligned_remainder
dl_tie728_s16_greater_w1_1_w2_8_unaligned_remainder:
beqz a10, dl_tie728_s16_greater_w1_1_w2_8_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.gt.s16 q2, q5, q2
ee.andq q2, q2, q7
ee.vunzip.8 q2, q6
srli a10, a10, 1
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s16_greater_w1_1_w2_8_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 15,883
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_greaterorequal.S
|
#include "dl_tie728_s8.S"
#void dl_tie728_s8_greaterorequal_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_greaterorequal_w1_16_w2_16
.type dl_tie728_s8_greaterorequal_w1_16_w2_16, @function
#.section .iram1
dl_tie728_s8_greaterorequal_w1_16_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
movi a14, 0
tie728_s8_greaterorequal_w1_16_w2_16_loop:
beq a14, a5, tie728_s8_greaterorequal_w1_16_w2_16_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.gt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s8 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s8 q2, q2, q6
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_greaterorequal_w1_16_w2_16_loop
tie728_s8_greaterorequal_w1_16_w2_16_end:
retw
#void dl_tie728_s8_greaterorequal_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_greaterorequal_w1_16_w2_1
.type dl_tie728_s8_greaterorequal_w1_16_w2_1, @function
#.section .iram1
dl_tie728_s8_greaterorequal_w1_16_w2_1:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s8_greaterorequal_w1_16_w2_1_loop:
beq a14, a5, tie728_s8_greaterorequal_w1_16_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.gt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s8 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s8 q2, q2, q6
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_greaterorequal_w1_16_w2_1_loop
tie728_s8_greaterorequal_w1_16_w2_1_end:
retw
#void dl_tie728_s8_greaterorequal_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_greaterorequal_w1_1_w2_16
.type dl_tie728_s8_greaterorequal_w1_1_w2_16, @function
#.section .iram1
dl_tie728_s8_greaterorequal_w1_1_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s8_greaterorequal_w1_1_w2_16_loop:
beq a14, a5, tie728_s8_greaterorequal_w1_1_w2_16_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.gt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vcmp.eq.s8 q6, q0, q1
ee.andq q6, q6, q7
ee.vmax.s8 q2, q2, q6
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_greaterorequal_w1_1_w2_16_loop
tie728_s8_greaterorequal_w1_1_w2_16_end:
retw
.align 4
.text
.global dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned
.type dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_remainder
dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_greaterorequal_w1_16_w2_16_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned
.type dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_remainder
dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.gt.s8 q1, q2, q5
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q2, q5
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_greaterorequal_w1_16_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned
.type dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr broadcast
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_remainder
dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.gt.s8 q1, q5, q2
ee.andq q1, q1, q7
ee.vcmp.eq.s8 q6, q5, q2
ee.andq q6, q6, q7
ee.vmax.s8 q2, q1, q6
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_greaterorequal_w1_1_w2_16_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 4,458
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_min2d.S
|
#include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_min2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_min2d_11c
.type dl_tie728_s16_min2d_11c, @function
.section .iram1
dl_tie728_s16_min2d_11c:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
l32i a6, a5, 64
blti a6, 0, 5f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VMIN.s16.LD.INCP q0, a3, q2, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.VST.128.IP q2, a2, 16
0:
EE.VMIN.S16 q2, q0, q1
EE.VST.128.IP q2, a2, 16
5:
retw
############################################################################################################################################################
####
#### tie728_s16_unaligned_min2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_unaligned_min2d_11c
.type dl_tie728_s16_unaligned_min2d_11c, @function
.section .iram1
dl_tie728_s16_unaligned_min2d_11c:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
l32i a6, a5, 64
l32i a7, a5, 76
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s16_unaligned_min2d_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s16_unaligned_min2d_11c_0
beqi a13, 8, dl_tie718_s16_unaligned_min2d_11c_1
loopgtz a6, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S16 q2, q2, q5
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie718_s16_unaligned_min2d_11c_remainder
dl_tie718_s16_unaligned_min2d_11c_0:
loopgtz a6, 1f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S16 q2, q2, q5
EE.VST.128.IP q2, a2, 16
j dl_tie718_s16_unaligned_min2d_11c_remainder
dl_tie718_s16_unaligned_min2d_11c_1:
loopgtz a6, 2f
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMIN.S16 q2, q2, q5
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie718_s16_unaligned_min2d_11c_remainder
dl_tie718_s16_unaligned_min2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s16_unaligned_min2d_11c_remainder:
beqz a7, dl_tie728_s16_unaligned_min2d_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VMIN.S16 q2, q2, q5
srli a7, a7, 1
dl_tie728_s16_store_remainder q2, a7, a12, a2
dl_tie728_s16_unaligned_min2d_11c_end:
retw
|
georgevio/IoT-Embedded
| 12,997
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_equal.S
|
#include "dl_tie728_s8.S"
#void dl_tie728_s8_equal_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_equal_w1_16_w2_16
.type dl_tie728_s8_equal_w1_16_w2_16, @function
#.section .iram1
dl_tie728_s8_equal_w1_16_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
movi a14, 0
tie728_s8_equal_w1_16_w2_16_loop:
beq a14, a5, tie728_s8_equal_w1_16_w2_16_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.eq.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_equal_w1_16_w2_16_loop
tie728_s8_equal_w1_16_w2_16_end:
retw
#void dl_tie728_s8_equal_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_equal_w1_16_w2_1
.type dl_tie728_s8_equal_w1_16_w2_1, @function
#.section .iram1
dl_tie728_s8_equal_w1_16_w2_1:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s8_equal_w1_16_w2_1_loop:
beq a14, a5, tie728_s8_equal_w1_16_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.eq.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_equal_w1_16_w2_1_loop
tie728_s8_equal_w1_16_w2_1_end:
retw
#void dl_tie728_s8_equal_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_equal_w1_1_w2_16
.type dl_tie728_s8_equal_w1_1_w2_16, @function
#.section .iram1
dl_tie728_s8_equal_w1_1_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s8_equal_w1_1_w2_16_loop:
beq a14, a5, tie728_s8_equal_w1_1_w2_16_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.eq.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_equal_w1_1_w2_16_loop
tie728_s8_equal_w1_1_w2_16_end:
retw
.align 4
.text
.global dl_tie728_s8_equal_w1_16_w2_16_unaligned
.type dl_tie728_s8_equal_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_equal_w1_16_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s8_equal_w1_16_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_equal_w1_16_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_equal_w1_16_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_equal_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_equal_w1_16_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_equal_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_equal_w1_16_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_equal_w1_16_w2_16_unaligned_remainder
dl_tie728_s8_equal_w1_16_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_equal_w1_16_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_equal_w1_16_w2_16_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s8_equal_w1_16_w2_1_unaligned
.type dl_tie728_s8_equal_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s8_equal_w1_16_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s8_equal_w1_16_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_equal_w1_16_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_equal_w1_16_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_equal_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s8_equal_w1_16_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_equal_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s8_equal_w1_16_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_equal_w1_16_w2_1_unaligned_remainder
dl_tie728_s8_equal_w1_16_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s8_equal_w1_16_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.eq.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_equal_w1_16_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s8_equal_w1_1_w2_16_unaligned
.type dl_tie728_s8_equal_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_equal_w1_1_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr broadcast
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s8_equal_w1_1_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s8_equal_w1_1_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_equal_w1_1_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_equal_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_equal_w1_1_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_equal_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_equal_w1_1_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.eq.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_equal_w1_1_w2_16_unaligned_remainder
dl_tie728_s8_equal_w1_1_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_equal_w1_1_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.eq.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_equal_w1_1_w2_16_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 15,604
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8.S
|
.macro dl_tie728_s8_unaligned_store0 output_v, output_ptr, tmp32
EE.MOVI.32.A \output_v, \tmp32, 0
s32i \tmp32, \output_ptr, 0
EE.MOVI.32.A \output_v, \tmp32, 1
s32i \tmp32, \output_ptr, 4
EE.MOVI.32.A \output_v, \tmp32, 2
s32i \tmp32, \output_ptr, 8
EE.MOVI.32.A \output_v, \tmp32, 3
s32i \tmp32, \output_ptr, 12
addi \output_ptr, \output_ptr, 16
.endm
.macro dl_tie728_s8_unaligned_store1 output_v, output_ptr
EE.VST.L.64.IP \output_v, \output_ptr, 8
EE.VST.H.64.IP \output_v, \output_ptr, 8
.endm
.macro dl_tie728_s8_last_store_data tmp_q, output_v, tmp_a, c_remainder_bytes
movi \tmp_a, 15
sub \tmp_a, \tmp_a, \c_remainder_bytes
movi \c_remainder_bytes, 0
EE.SLCXXP.2Q \tmp_q, \output_v, \tmp_a, \c_remainder_bytes #left shift to make the rest part 0
EE.SRCXXP.2Q \output_v, \tmp_q, \tmp_a, \c_remainder_bytes #right shift to lower bits
.endm
.macro dl_tie728_s8_store_remainder output_v, tmp_a0, tmp_a1, tmp_a2, tmp_a3, output_ptr, remainder_c
EE.MOVI.32.A \output_v, \tmp_a0, 0
615: # remainder_c == 15, 0x1111
bbci \remainder_c, 3, 607f
EE.MOVI.32.A \output_v, \tmp_a1, 1
bbci \remainder_c, 2, 611f
EE.MOVI.32.A \output_v, \tmp_a2, 2
bbci \remainder_c, 1, 613f
EE.MOVI.32.A \output_v, \tmp_a3, 3
bbci \remainder_c, 0, 614f
s32i \tmp_a0, \output_ptr, 0
s32i \tmp_a1, \output_ptr, 4
s32i \tmp_a2, \output_ptr, 8
s16i \tmp_a3, \output_ptr, 12
srai \tmp_a3, \tmp_a3, 16
s8i \tmp_a3, \output_ptr, 14
j 616f
614: # remainder_c == 14, 0x1110
s32i \tmp_a0, \output_ptr, 0
s32i \tmp_a1, \output_ptr, 4
s32i \tmp_a2, \output_ptr, 8
s16i \tmp_a3, \output_ptr, 12
j 616f
613: # remainder_c == 13, 0x1101
bbci \remainder_c, 0, 612f
EE.MOVI.32.A \output_v, \tmp_a3, 3
s32i \tmp_a0, \output_ptr, 0
s32i \tmp_a1, \output_ptr, 4
s32i \tmp_a2, \output_ptr, 8
s8i \tmp_a3, \output_ptr, 12
j 616f
612: # remainder_c == 12, 0x1100
s32i \tmp_a0, \output_ptr, 0
s32i \tmp_a1, \output_ptr, 4
s32i \tmp_a2, \output_ptr, 8
j 616f
611: # remainder_c == 11, 0x1011
bbci \remainder_c, 1, 609f
EE.MOVI.32.A \output_v, \tmp_a2, 2
bbci \remainder_c, 0, 610f
s32i \tmp_a0, \output_ptr, 0
s32i \tmp_a1, \output_ptr, 4
s16i \tmp_a2, \output_ptr, 8
srai \tmp_a2, \tmp_a2, 16
s8i \tmp_a2, \output_ptr, 10
j 616f
610: # remainder_c == 10, 0x1010
s32i \tmp_a0, \output_ptr, 0
s32i \tmp_a1, \output_ptr, 4
s16i \tmp_a2, \output_ptr, 8
j 616f
609: # remainder_c == 9, 0x1001
bbci \remainder_c, 0, 608f
EE.MOVI.32.A \output_v, \tmp_a2, 2
s32i \tmp_a0, \output_ptr, 0
s32i \tmp_a1, \output_ptr, 4
s8i \tmp_a2, \output_ptr, 8
j 616f
608: # remainder_c == 8, 0x1000
s32i \tmp_a0, \output_ptr, 0
s32i \tmp_a1, \output_ptr, 4
j 616f
607: # remainder == 7, 0x111
bbci \remainder_c, 2, 603f
bbci \remainder_c, 1, 605f
EE.MOVI.32.A \output_v, \tmp_a1, 1
bbci \remainder_c, 0, 606f
s32i \tmp_a0, \output_ptr, 0
s16i \tmp_a1, \output_ptr, 4
srai \tmp_a1, \tmp_a1, 16
s8i \tmp_a1, \output_ptr, 6
j 616f
606: # remainder == 6, 0x110
s32i \tmp_a0, \output_ptr, 0
s16i \tmp_a1, \output_ptr, 4
j 616f
605: # remainder == 4, 5
bbci \remainder_c, 0, 604f
# remainder == 5, 0x101
EE.MOVI.32.A \output_v, \tmp_a1, 1
s32i \tmp_a0, \output_ptr, 0
s8i \tmp_a1, \output_ptr, 4
j 616f
604: # remainder == 4, 0x100
s32i \tmp_a0, \output_ptr, 0
j 616f
603: # remainder == 1, 2, 3
bbci \remainder_c, 1, 601f
bbci \remainder_c, 0, 602f
# remainder == 3, 0x011
s16i \tmp_a0, \output_ptr, 0
srai \tmp_a0, \tmp_a0, 16
s8i \tmp_a0, \output_ptr, 2
j 616f
602: # remainder == 2, 0x010
s16i \tmp_a0, \output_ptr, 0
j 616f
601: # remainder == 1, 0x001
s8i \tmp_a0, \output_ptr, 0
616:
.endm
############################################################################################################################################################
# result process for Conv2D / Depthwise_Conv2D
############################################################################################################################################################
.macro tie728_s8_conv2d_per_layer_result output_v mac_shift
EE.SRCMB.S8.QACC \output_v, \mac_shift, 0
.endm
.macro tie728_s8_vector_round_result output_v mac_shift tmp tmp_q1
beqz \mac_shift, 500f
MOVI \tmp, 257 // 0000 0000 0000 0000 0000 0001 0000 0001
EE.MOVI.32.Q \output_v, \tmp, 0
EE.MOVI.32.Q \output_v, \tmp, 1
EE.MOVI.32.Q \output_v, \tmp, 2
EE.MOVI.32.Q \output_v, \tmp, 3
movi.n \tmp, 16
wsr.sar \tmp
EE.VSL.32 \tmp_q1, \output_v
EE.ORQ \tmp_q1, \tmp_q1, \output_v // 0000 0001 0000 0001 0000 0001 0000 0001
addi \tmp, \mac_shift, -1
EE.SRCMB.S8.QACC \output_v, \tmp, 0
movi.n \tmp, 1
EE.MOVI.32.Q \output_v, \tmp, 0
EE.VSMULAS.S8.QACC \tmp_q1, \output_v, 0 // qacc[0:16] += round
EE.SRCMB.S8.QACC \output_v, \tmp, 0
j 501f
500:
EE.SRCMB.S8.QACC \output_v, \mac_shift, 0
501:
.endm
.macro tie728_s8_element_round_result output mac_shift tmp tmp_q1
beqz \mac_shift, 505f
addi \tmp, \mac_shift, -1
EE.SRS.ACCX \output, \tmp, 0
movi.n \tmp, 1
EE.ZERO.Q \tmp_q1
EE.MOVI.32.Q \tmp_q1, \tmp, 0
EE.VMULAS.S8.ACCX \tmp_q1, \tmp_q1
EE.SRS.ACCX \output, \tmp, 0
j 506f
505:
EE.SRS.ACCX \output, \mac_shift, 0
506:
.endm
# what if a1 not 16 byte aligned?
.macro tie728_s8_conv2d_per_channel_result output_v scale_q scale_factor tmp tmp_q1
# entry need to be 128
movi \tmp, 4
EE.SRCMB.S16.QACC \output_v, \tmp, 0 # get the lower 16 bit in QACC
mov \tmp, a1
EE.ST.QACC_L.L.128.IP \tmp, 16
EE.ST.QACC_L.H.32.IP \tmp, 16
EE.ST.QACC_H.L.128.IP \tmp, 16
EE.ST.QACC_H.H.32.IP \tmp, 4
movi \tmp, 20
EE.SRCMB.S16.QACC \tmp_q1, \tmp, 0 # \tmp_q1: even 16 bit
l16si \tmp, a1, 5 #re-arrange qacc odd 16 bit
s16i \tmp, a1, 2
l16si \tmp, a1, 10
s16i \tmp, a1, 4
l16si \tmp, a1, 15
s16i \tmp, a1, 6
l16si \tmp, a1, 32
s16i \tmp, a1, 8
l16si \tmp, a1, 37
s16i \tmp, a1, 10
l16si \tmp, a1, 42
s16i \tmp, a1, 12
l16si \tmp, a1, 47
s16i \tmp, a1, 14
EE.VLD.128.IP \output_v, a1, 0 # \output_v: odd 16 bit
EE.VZIP.16 \output_v, \tmp_q1
movi \tmp, 11
ssr \tmp
EE.VLD.128.IP \scale_q, \scale_factor, 16 # scale factor
movi \tmp, 0
EE.VMUL.S16 \output_v, \output_v, \scale_q
EE.VLD.128.IP \scale_q, \scale_factor, 16
EE.MOV.S16.QACC \output_v
EE.VMUL.S16 \tmp_q1, \tmp_q1, \scale_q
EE.SRCMB.S8.QACC \output_v, \tmp, 0
EE.MOV.S16.QACC \tmp_q1
EE.SRCMB.S8.QACC \tmp_q1, \tmp, 0
EE.VUNZIP.8 \output_v, \tmp_q1
.endm
.macro tie728_s8_conv2d_per_channel_with_bias_result output_v scale_q scale_factor bias_ptr tmp tmp_q1
# entry need to be 128
movi \tmp, 4
EE.SRCMB.S16.QACC \output_v, \tmp, 0 # get the lower 16 bit in QACC
mov \tmp, a1
EE.ST.QACC_L.L.128.IP \tmp, 16
EE.ST.QACC_L.H.32.IP \tmp, 16
EE.ST.QACC_H.L.128.IP \tmp, 16
EE.ST.QACC_H.H.32.IP \tmp, 4
movi \tmp, 20
EE.SRCMB.S16.QACC \tmp_q1, \tmp, 0 # \tmp_q1: even 16 bit
l16si \tmp, a1, 5 #re-arrange qacc odd 16 bit
s16i \tmp, a1, 2
l16si \tmp, a1, 10
s16i \tmp, a1, 4
l16si \tmp, a1, 15
s16i \tmp, a1, 6
l16si \tmp, a1, 32
s16i \tmp, a1, 8
l16si \tmp, a1, 37
s16i \tmp, a1, 10
l16si \tmp, a1, 42
s16i \tmp, a1, 12
l16si \tmp, a1, 47
s16i \tmp, a1, 14
EE.VLD.128.IP \output_v, a1, 0 # \output_v: odd 16 bit
EE.VZIP.16 \output_v, \tmp_q1
EE.VLD.128.IP \scale_q, \bias_ptr, 16 # load bias
movi \tmp, 11
EE.VADDS.S16 \output_v, \output_v, \scale_q # add int16 bias with exponent(input+filter-4)
EE.VLD.128.IP \scale_q, \bias_ptr, 16 # load bias
ssr \tmp
EE.VADDS.S16 \tmp_q1, \tmp_q1, \scale_q
EE.VLD.128.IP \scale_q, \scale_factor, 16 # scale factor
movi \tmp, 0
EE.VMUL.S16 \output_v, \output_v, \scale_q
EE.VLD.128.IP \scale_q, \scale_factor, 16
EE.MOV.S16.QACC \output_v
EE.VMUL.S16 \tmp_q1, \tmp_q1, \scale_q
EE.SRCMB.S8.QACC \output_v, \tmp, 0
EE.MOV.S16.QACC \tmp_q1
EE.SRCMB.S8.QACC \tmp_q1, \tmp, 0
EE.VUNZIP.8 \output_v, \tmp_q1
.endm
.macro tie728_s8_conv2d_128b_vector_bias bias_ptr
EE.LD.QACC_L.L.128.IP \bias_ptr, 16
EE.LD.QACC_L.H.32.IP \bias_ptr, 16
EE.LD.QACC_H.L.128.IP \bias_ptr, 16
EE.LD.QACC_H.H.32.IP \bias_ptr, 16
.endm
.macro tie728_s8_conv2d_element_bias bias_ptr
EE.LD.ACCX.IP \bias_ptr, 8
.endm
.macro tie728_s8_conv2d_bias output_v bias_v bias_ptr
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
# bias
EE.VADDS.S8 \output_v, \output_v, \bias_v
.endm
.macro tie728_s8_conv2d_bias_relu output_v bias_v bias_ptr activation_alpha activation_shift
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
# bias
EE.VADDS.S8 \output_v, \output_v, \bias_v
# LeakyReLU
EE.VRELU.S8 \output_v, \activation_alpha, \activation_shift
.endm
.macro tie728_s8_conv2d_bias_prelu output_v bias_v bias_ptr activation_v activation_alpha_ptr activation_shift
EE.VLD.128.IP \bias_v, \bias_ptr, 16 # load bias
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
# bias
EE.VADDS.S8 \output_v, \output_v, \bias_v
# PReLU
EE.VPRELU.S8 \output_v, \output_v, \activation_v, \activation_shift
.endm
.macro tie728_s8_conv2d_relu output_v activation_alpha activation_shift
# LeakyReLU
EE.VRELU.S8 \output_v, \activation_alpha, \activation_shift
.endm
.macro tie728_s8_conv2d_prelu output_v activation_v activation_alpha_ptr activation_shift
EE.VLD.128.IP \activation_v, \activation_alpha_ptr, 16 # load PReLU alph
# PReLU
EE.VPRELU.S8 \output_v, \output_v, \activation_v, \activation_shift
.endm
############################################################################################################################################################
####
#### tie728_s8_unaligned_conv2d / depthwise_conv2d
####
############################################################################################################################################################
.macro tie728_s8_unaligned_conv2d_operation_type operation_type mac_shift bias_ptr activation_shift activation_alpha args
movi \operation_type, 0
0: // per-layer or per-channel
bltz \mac_shift, 1f
j 2f
1: //per_channel
l32i \mac_shift, \args, 104 // filter_channel_factor address
addi \operation_type, \operation_type, 6
2: // bias
beqz \bias_ptr, 3f // no bias
addi \operation_type, \operation_type, 3
3: // activation dl_tie728_s8_unaligned_conv2d_activation
bltz \activation_shift, 5f // no activation
beqz \activation_alpha, 4f
addi \operation_type, \operation_type, 2
j 5f
4:
l32i \activation_alpha, \args, 76 // load activation_alpha
addi \operation_type, \operation_type, 1 // Relu or LeakyReLU
5: //put operation type in \operation_type
.endm
.macro tie728_s8_conv2d_1_1_unaligned_c_result operation_type output_v mac_shift bias_ptr activation_alpha activation_shift tmp tmp_q1 tmp_q2
bbci \operation_type, 3, 7f
bbci \operation_type, 2, 11f
11: # per_channel bias + prelu, 0x1011
bbci \operation_type, 1, 9f
bbci \operation_type, 0, 10f
# tie728_s8_conv2d_per_channel_result \output_v, \tmp_q2, \mac_shift, \tmp, \tmp_q1
# tie728_s8_conv2d_bias_prelu \output_v, \tmp_q1, \bias_ptr, \tmp_q2, \activation_alpha, \activation_shift
tie728_s8_conv2d_per_channel_with_bias_result \output_v, \tmp_q2, \mac_shift, \bias_ptr, \tmp, \tmp_q1
tie728_s8_conv2d_prelu \output_v, \tmp_q2, \activation_alpha, \activation_shift
j 16f # jump to 16f
10: # per_channel bias + relu, 0x1010
# tie728_s8_conv2d_per_channel_result \output_v, \tmp_q2, \mac_shift, \tmp, \tmp_q1
# tie728_s8_conv2d_bias_relu \output_v, \tmp_q1, \bias_ptr, \activation_alpha, \activation_shift
tie728_s8_conv2d_per_channel_with_bias_result \output_v, \tmp_q2, \mac_shift, \bias_ptr, \tmp, \tmp_q1
tie728_s8_conv2d_relu \output_v, \activation_alpha, \activation_shift
j 16f # jump to 16f
9: # per_channel bias, 0x1001
bbci \operation_type, 0, 8f
# tie728_s8_conv2d_per_channel_result \output_v, \tmp_q2, \mac_shift, \tmp, \tmp_q1
# tie728_s8_conv2d_bias \output_v, \tmp_q1, \bias_ptr
tie728_s8_conv2d_per_channel_with_bias_result \output_v, \tmp_q2, \mac_shift, \bias_ptr, \tmp, \tmp_q1
j 16f # jump to 16f
8: #per_channel no_bias + prelu, 0x1000
tie728_s8_conv2d_per_channel_result \output_v, \tmp_q2, \mac_shift, \tmp, \tmp_q1
tie728_s8_conv2d_prelu \output_v, \tmp_q2, \activation_alpha, \activation_shift
j 16f # jump to 16f
7: # per_channel no_bias + relu, 0x111
bbci \operation_type, 2, 3f
bbci \operation_type, 1, 5f
bbci \operation_type, 0, 6f
tie728_s8_conv2d_per_channel_result \output_v, \tmp_q2, \mac_shift, \tmp, \tmp_q1
tie728_s8_conv2d_relu \output_v, \activation_alpha, \activation_shift
j 16f # jump to 16f
6: # per_channel no_bias, 0x110
tie728_s8_conv2d_per_channel_result \output_v, \tmp_q2, \mac_shift, \tmp, \tmp_q1
j 16f # jump to 16f
5: # remainder == 4, 5
bbci \operation_type, 0, 4f
# per_layer bias + prelu, 0x101
# tie728_s8_conv2d_per_layer_result \output_v, \mac_shift
tie728_s8_vector_round_result \output_v, \mac_shift, \tmp, \tmp_q1
# tie728_s8_conv2d_bias_prelu \output_v, \tmp_q1, \bias_ptr, \tmp_q2, \activation_alpha, \activation_shift
# bias will be preload
tie728_s8_conv2d_prelu \output_v, \tmp_q2, \activation_alpha, \activation_shift
j 16f # jump to 16f
4: # per_layer bias + relu, 0x100
# tie728_s8_conv2d_per_layer_result \output_v, \mac_shift
tie728_s8_vector_round_result \output_v, \mac_shift, \tmp, \tmp_q1
# tie728_s8_conv2d_bias_relu \output_v, \tmp_q1, \bias_ptr, \activation_alpha, \activation_shift
# bias will be preload
tie728_s8_conv2d_relu \output_v, \activation_alpha, \activation_shift
j 16f # jump to 16f
3: # remainder == 1, 2, 3
bbci \operation_type, 1, 1f
bbci \operation_type, 0, 2f
# per_layer bias, 0x011
# tie728_s8_conv2d_per_layer_result \output_v, \mac_shift
tie728_s8_vector_round_result \output_v, \mac_shift, \tmp, \tmp_q1
# bias will be preload
# tie728_s8_conv2d_bias \output_v, \tmp_q1, \bias_ptr
j 16f # jump to 16f
2: # per_layer no_bias + prelu, 0x010
# tie728_s8_conv2d_per_layer_result \output_v, \mac_shift
tie728_s8_vector_round_result \output_v, \mac_shift, \tmp, \tmp_q1
tie728_s8_conv2d_prelu \output_v, \tmp_q2, \activation_alpha, \activation_shift
j 16f # jump to 16f
1: # no_bias + relu, 0x001
bbci \operation_type, 0, 0f
# tie728_s8_conv2d_per_layer_result \output_v, \mac_shift
tie728_s8_vector_round_result \output_v, \mac_shift, \tmp, \tmp_q1
tie728_s8_conv2d_relu \output_v, \activation_alpha, \activation_shift
j 16f # jump to 16f
0: # per_layer no_bias, 0x000
# tie728_s8_conv2d_per_layer_result \output_v, \mac_shift
tie728_s8_vector_round_result \output_v, \mac_shift, \tmp, \tmp_q1
16:
.endm
|
georgevio/IoT-Embedded
| 3,940
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_prelu.S
|
#include "dl_tie728_s16.S"
.align 4
.text
.global dl_tie728_s16_prelu_11c
.type dl_tie728_s16_prelu_11c, @function
.section .iram1
dl_tie728_s16_prelu_11c:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: c_rs1_1: c / 2x - 1
# a6: c_rs2_1: c_left_1
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a5, a4, 88
l32i a6, a4, 92
l32i a14, a4, 80 # activation_alpha_ptr
l32i a15, a4, 84 # activation_shift
loopgtz a5, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q2, a14, 16
EE.VLD.128.IP q1, a3, 16
EE.VLD.128.IP q3, a14, 16
EE.VPRELU.S16 q0, q0, q2, a15
EE.VST.128.IP q0, a2, 16
EE.VPRELU.S16 q1, q1, q3, a15
EE.VST.128.IP q1, a2, 16
0:
blti a6, 0, 5f
loopgtz a6, 1f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q2, a14, 16
EE.VPRELU.S16 q0, q0, q2, a15
EE.VST.128.IP q0, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q2, a14, 16
EE.VPRELU.S16 q0, q0, q2, a15
EE.VST.128.IP q0, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_prelu_11c
.type dl_tie728_s16_unaligned_prelu_11c, @function
.section .iram1
dl_tie728_s16_unaligned_prelu_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: c_div_x_1
# a6: c_remainder
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a5, a4, 100
l32i a6, a4, 136
l32i a14, a4, 80 # activation_alpha_ptr
l32i a15, a4, 84 # activation_shift
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a5, 0, dl_tie718_s16_unaligned_prelu_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s16_unaligned_prelu_11c_0
beqi a13, 8, dl_tie718_s16_unaligned_prelu_11c_1
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.VLD.128.IP q3, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q3, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.VLD.128.IP q3, a14, 16
EE.SRC.Q.QUP q2, q0, q1
EE.VPRELU.S16 q2, q2, q3, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie718_s16_unaligned_prelu_11c_remainder
dl_tie718_s16_unaligned_prelu_11c_0:
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.VLD.128.IP q3, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.VLD.128.IP q3, a14, 16
EE.SRC.Q.QUP q2, q0, q1
EE.VPRELU.S16 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_s16_unaligned_prelu_11c_remainder
dl_tie718_s16_unaligned_prelu_11c_1:
loopgtz a5, 0f
EE.SRC.Q.QUP q2, q0, q1
EE.VLD.128.IP q3, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q3, a15
dl_tie728_128b_unaligned_store1 q2, a2
0:
addi a3, a3, -16
add a3, a3, a6
rur.sar_byte a11
EE.VLD.128.IP q3, a14, 16
EE.SRC.Q.QUP q2, q0, q1
EE.VPRELU.S16 q2, q2, q3, a15
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie718_s16_unaligned_prelu_11c_remainder
dl_tie718_s16_unaligned_prelu_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a6
rur.sar_byte a11
dl_tie718_s16_unaligned_prelu_11c_remainder:
beqz a6, dl_tie728_s16_unaligned_prelu_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.VLD.128.IP q3, a14, 16
EE.VPRELU.S16 q2, q2, q3, a15
srli a6, a6, 1
dl_tie728_s16_store_remainder q2, a6, a13, a2
dl_tie728_s16_unaligned_prelu_11c_end:
retw
|
georgevio/IoT-Embedded
| 16,536
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_mul2d.S
|
#include "dl_tie728_s8.S"
############################################################################################################################################################
####
#### tie728_s8_mul2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s8_mul2d_11c
.type dl_tie728_s8_mul2d_11c, @function
.section .iram1
dl_tie728_s8_mul2d_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
l32i a6, a5, 64
l32i a7, a5, 100
l32i a8, a5, 76
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.ZERO.QACC
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q1
EE.VLD.128.IP q1, a4, 16
# EE.SRCMB.S8.QACC q2, a7, 0
tie728_s8_vector_round_result q2, a7, a10, q7
EE.VST.128.IP q2, a2, 16
0:
EE.ZERO.QACC
EE.VMULAS.S8.QACC q0, q1
# EE.SRCMB.S8.QACC q2, a7, 0
tie728_s8_vector_round_result q2, a7, a10, q7
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_mul2d_11c_relu
.type dl_tie728_s8_mul2d_11c_relu, @function
.section .iram1
dl_tie728_s8_mul2d_11c_relu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 100
l32i a8, a5, 76
l32i a14, a5, 52
l32i a15, a5, 60
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.ZERO.QACC
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q1
EE.VLD.128.IP q1, a4, 16
# EE.SRCMB.S8.QACC q2, a7, 0
tie728_s8_vector_round_result q2, a7, a10, q7
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
0:
EE.ZERO.QACC
EE.VMULAS.S8.QACC q0, q1
# EE.SRCMB.S8.QACC q2, a7, 0
tie728_s8_vector_round_result q2, a7, a10, q7
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_mul2d_11c_prelu
.type dl_tie728_s8_mul2d_11c_prelu, @function
.section .iram1
dl_tie728_s8_mul2d_11c_prelu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: mul_shift
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 100
l32i a14, a5, 56
l32i a15, a5, 60
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.ZERO.QACC
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q1
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q3, a14, 16
# EE.SRCMB.S8.QACC q2, a7, 0
tie728_s8_vector_round_result q2, a7, a10, q7
EE.VPRELU.S8 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
0:
EE.ZERO.QACC
EE.VMULAS.S8.QACC q0, q1
EE.VLD.128.IP q3, a14, 16
# EE.SRCMB.S8.QACC q2, a7, 0
tie728_s8_vector_round_result q2, a7, a10, q7
EE.VPRELU.S8 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_mul2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s8_unaligned_mul2d_11c
.type dl_tie728_s8_unaligned_mul2d_11c, @function
.section .iram1
dl_tie728_s8_unaligned_mul2d_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
# a8: mul_shift
l32i a6, a5, 64
l32i a7, a5, 76
l32i a8, a5, 100
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s8_unaligned_mul2d_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s8_unaligned_mul2d_11c_0
beqi a13, 8, dl_tie718_s8_unaligned_mul2d_11c_1
loopgtz a6, 0f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie718_s8_unaligned_mul2d_11c_remainder
dl_tie718_s8_unaligned_mul2d_11c_0:
loopgtz a6, 1f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VST.128.IP q2, a2, 16
j dl_tie718_s8_unaligned_mul2d_11c_remainder
dl_tie718_s8_unaligned_mul2d_11c_1:
loopgtz a6, 2f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie718_s8_unaligned_mul2d_11c_remainder
dl_tie718_s8_unaligned_mul2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s8_unaligned_mul2d_11c_remainder:
beqz a7, dl_tie728_s8_unaligned_mul2d_11c_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.ZERO.QACC
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a7
dl_tie728_s8_unaligned_mul2d_11c_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_mul2d_11c_relu
.type dl_tie728_s8_unaligned_mul2d_11c_relu, @function
.section .iram1
dl_tie728_s8_unaligned_mul2d_11c_relu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
# a8: mul_shift
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 76
l32i a8, a5, 100
l32i a14, a5, 52
l32i a15, a5, 60
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s8_unaligned_mul2d_11c_relu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s8_unaligned_mul2d_11c_relu_0
beqi a13, 8, dl_tie718_s8_unaligned_mul2d_11c_relu_1
loopgtz a6, 0f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie718_s8_unaligned_mul2d_11c_relu_remainder
dl_tie718_s8_unaligned_mul2d_11c_relu_0:
loopgtz a6, 1f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_s8_unaligned_mul2d_11c_relu_remainder
dl_tie718_s8_unaligned_mul2d_11c_relu_1:
loopgtz a6, 2f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie718_s8_unaligned_mul2d_11c_relu_remainder
dl_tie718_s8_unaligned_mul2d_11c_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s8_unaligned_mul2d_11c_relu_remainder:
beqz a7, dl_tie728_s8_unaligned_mul2d_11c_relu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.ZERO.QACC
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VRELU.S8 q2, a14, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a7
dl_tie728_s8_unaligned_mul2d_11c_relu_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_mul2d_11c_prelu
.type dl_tie728_s8_unaligned_mul2d_11c_prelu, @function
.section .iram1
dl_tie728_s8_unaligned_mul2d_11c_prelu:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: c_remainder
# a8: mul_shift
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 76
l32i a8, a5, 100
l32i a14, a5, 56
l32i a15, a5, 60
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie718_s8_unaligned_mul2d_11c_prelu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie718_s8_unaligned_mul2d_11c_prelu_0
beqi a13, 8, dl_tie718_s8_unaligned_mul2d_11c_prelu_1
loopgtz a6, 0f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
EE.VLD.128.IP q6, a14, 16
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie718_s8_unaligned_mul2d_11c_prelu_remainder
dl_tie718_s8_unaligned_mul2d_11c_prelu_0:
loopgtz a6, 1f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
EE.VLD.128.IP q6, a14, 16
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VPRELU.S8 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
j dl_tie718_s8_unaligned_mul2d_11c_prelu_remainder
dl_tie718_s8_unaligned_mul2d_11c_prelu_1:
loopgtz a6, 2f
EE.ZERO.QACC
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a7
EE.ZERO.QACC
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a7
rur.sar_byte a12 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.VMULAS.S8.QACC q2, q5
EE.VLD.128.IP q6, a14, 16
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie718_s8_unaligned_mul2d_11c_prelu_remainder
dl_tie718_s8_unaligned_mul2d_11c_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a7
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a7
rur.sar_byte a12
dl_tie718_s8_unaligned_mul2d_11c_prelu_remainder:
beqz a7, dl_tie728_s8_unaligned_mul2d_11c_prelu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.ZERO.QACC
EE.VMULAS.S8.QACC q2, q5
EE.VLD.128.IP q6, a14, 16
# EE.SRCMB.S8.QACC q2, a8, 0
tie728_s8_vector_round_result q2, a8, a10, q7
EE.VPRELU.S8 q2, q2, q6, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a7
dl_tie728_s8_unaligned_mul2d_11c_prelu_end:
retw
|
georgevio/IoT-Embedded
| 6,489
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_resize.S
|
#include "dl_tie728_s8.S"
.align 4
.text
.global dl_tie728_s8_resize_nearest_2x2_c1
.type dl_tie728_s8_resize_nearest_2x2_c1, @function
dl_tie728_s8_resize_nearest_2x2_c1:
.align 4
entry sp, 24
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: output_x_offset
# a6: output_y_offset
# a7: c_div_x
# a8: remainder
# a9: output_shift
# a10: output_scale
l32i a5, a4, 20
l32i a6, a4, 24
l32i a7, a4, 40
l32i a8, a4, 44
l32i a9, a4, 48
l32i a10, a4, 52
# a11 (0, 1)
# a12 (1, 0)
# a13 (1, 1)
add a11, a2, a5
add a12, a2, a6
add a13, a11, a6
s8i a10, sp, 0
ee.vldbc.8.ip q1, sp, 0 # all output_scale
ee.vld.128.ip q0, a3, 16
loopgtz a7, 0f
ee.zero.qacc
ee.vmulas.s8.qacc.ld.ip q0, a3, 16, q0, q1
tie728_s8_vector_round_result q2, a9, a14, q7
ee.vst.128.ip q2, a2, 16
ee.vst.128.ip q2, a11, 16
ee.vst.128.ip q2, a12, 16
ee.vst.128.ip q2, a13, 16
0:
retw
.text
.align 4
.global dl_tie728_s8_resize_nearest_c1
.type dl_tie728_s8_resize_nearest_c1, @function
# .balign 4
# .option norvc
dl_tie728_s8_resize_nearest_c1:
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: c_div_x
# a6: output_shift
# a7: output_scale address
# a8: tmp value
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 64
l32i a5, a4, 40
l32i a6, a4, 48
beqz a5, dl_tie728_s8_resize_nearest_c1_end
addi a7, a4, 52
ee.vldbc.8.ip q1, a7, 0 // load output_scale
ee.vld.128.ip q0, a3, 16
dl_tie728_s8_resize_nearest_c1_loop:
ee.zero.qacc
ee.vmulas.s8.qacc.ld.ip q0, a3, 16, q0, q1
tie728_s8_vector_round_result q2, a6, a8, q4
ee.vst.128.ip q2, a2, 16
addi a5, a5, -1
bgei a5, 1, dl_tie728_s8_resize_nearest_c1_loop
dl_tie728_s8_resize_nearest_c1_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_resize_nearest_2x2_c1
.type dl_tie728_s8_unaligned_resize_nearest_2x2_c1, @function
dl_tie728_s8_unaligned_resize_nearest_2x2_c1:
.align 4
entry sp, 24
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: output_x_offset
# a6: output_y_offset
# a7: c_div_x
# a8: remainder
# a9: output_shift
# a10: output_scale
l32i a5, a4, 20
l32i a6, a4, 24
l32i a7, a4, 40
l32i a8, a4, 44
l32i a9, a4, 48
l32i a10, a4, 52
# a11 (0, 1)
# a12 (1, 0)
# a13 (1, 1)
add a11, a2, a5
add a12, a2, a6
add a13, a11, a6
s8i a10, sp, 0
ee.vldbc.8.ip q3, sp, 0 # all output_scale
ee.ld.128.usar.ip q0, a3, 16
loopgtz a7, 0f
ee.zero.qacc
ee.ld.128.usar.ip q1, a3, 16
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q3
tie728_s8_vector_round_result q4, a9, a14, q7
dl_tie728_s8_unaligned_store0 q4, a2, a14
dl_tie728_s8_unaligned_store0 q4, a11, a14
dl_tie728_s8_unaligned_store0 q4, a12, a14
dl_tie728_s8_unaligned_store0 q4, a13, a14
0:
bnez a8, dl_tie728_s8_unaligned_resize_nearest_2x2_c1_remainder
retw
dl_tie728_s8_unaligned_resize_nearest_2x2_c1_remainder:
ee.zero.qacc
ee.ld.128.usar.ip q1, a3, 16
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q3
tie728_s8_vector_round_result q4, a9, a14, q7
dl_tie728_s8_store_remainder q4, a5, a6, a7, a10, a2, a8
dl_tie728_s8_store_remainder q4, a5, a6, a7, a10, a11, a8
dl_tie728_s8_store_remainder q4, a5, a6, a7, a10, a12, a8
dl_tie728_s8_store_remainder q4, a5, a6, a7, a10, a13, a8
retw
.text
.align 4
.global dl_tie728_s8_unaligned_resize_nearest_c1
.type dl_tie728_s8_unaligned_resize_nearest_c1, @function
# .balign 4
# .option norvc
dl_tie728_s8_unaligned_resize_nearest_c1:
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: c_div_x / tmp value
# a6: output_shift
# a7: output_scale address
# a8: c_remainder
# a9: output_sar_byte / tmp value
# a10: tmp value
# a11:
# a12: tmp value
# a13:
# a14:
# a15:
entry sp, 64
l32i a5, a4, 40
l32i a6, a4, 48
l32i a8, a4, 44
beqz a5, dl_tie728_s8_unaligned_resize_nearest_c1_remainder
addi a7, a4, 52
ee.vldbc.8.ip q3, a7, 0 // load output_scale
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q2, a2, 0
rur.sar_byte a9 // output_sar_byte
beqz a9, dl_tie728_s8_unaligned_resize_nearest_c1_128b_loop
movi a12, 8
beq a9, a12, dl_tie728_s8_unaligned_resize_nearest_c1_64b_loop
dl_tie728_s8_unaligned_resize_nearest_c1_32b_loop:
ee.ld.128.usar.ip q1, a3, 16
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q3
tie728_s8_vector_round_result q2, a6, a10, q4
dl_tie728_s8_unaligned_store0 q2, a2, a9
addi a5, a5, -1
bgei a5, 1, dl_tie728_s8_unaligned_resize_nearest_c1_32b_loop
j dl_tie728_s8_unaligned_resize_nearest_c1_remainder
dl_tie728_s8_unaligned_resize_nearest_c1_64b_loop:
ee.ld.128.usar.ip q1, a3, 16
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q3
tie728_s8_vector_round_result q2, a6, a10, q4
dl_tie728_s8_unaligned_store1 q2, a2
addi a5, a5, -1
bgei a5, 1, dl_tie728_s8_unaligned_resize_nearest_c1_64b_loop
j dl_tie728_s8_unaligned_resize_nearest_c1_remainder
dl_tie728_s8_unaligned_resize_nearest_c1_128b_loop:
ee.ld.128.usar.ip q1, a3, 16
ee.zero.qacc
ee.src.q.qup q2, q0, q1
ee.vmulas.s8.qacc q2, q3
tie728_s8_vector_round_result q2, a6, a10, q4
ee.vst.128.ip q2, a2, 16
addi a5, a5, -1
bgei a5, 1, dl_tie728_s8_unaligned_resize_nearest_c1_128b_loop
dl_tie728_s8_unaligned_resize_nearest_c1_remainder:
beqz a8, dl_tie728_s8_unaligned_resize_nearest_c1_end
ee.ld.128.usar.xp q1, a3, a8
ee.zero.qacc
ee.src.q q2, q0, q1
ee.vmulas.s8.qacc q2, q3
tie728_s8_vector_round_result q2, a6, a10, q4
dl_tie728_s8_store_remainder q2, a5, a7, a9, a10, a2, a8
dl_tie728_s8_unaligned_resize_nearest_c1_end:
retw
|
georgevio/IoT-Embedded
| 13,209
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_avg_pool2d.S
|
#include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### dl_tie728_s16_avg_pool2d series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_avg_pool2d_22c1
.type dl_tie728_s16_avg_pool2d_22c1, @function
.section .iram1
dl_tie728_s16_avg_pool2d_22c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: input_y_offset_bytes
# a6: input_x_offset_bytes
# a11: c_div_x_1
# a14: mac_shift
l32i a5, a4, 16 # input_y_offset_bytes
l32i a6, a4, 20 # input_x_offset_bytes
l32i a11, a4, 104 # c_div_x_1
add a7, a3, a6
add a8, a3, a5
add a9, a8, a6
addi a14, a4, 64
EE.VLDBC.16 q0, a14 # avg_pool_area_inv
l32i a14, a4, 56 # mac_shift
EE.VLD.128.IP q1, a3, 16
EE.VLD.128.IP q2, a7, 16
loopgtz a11, 1f
EE.ZERO.QACC
EE.VMULAS.S16.QACC.LD.IP q3, a8, 16, q0, q1
EE.VMULAS.S16.QACC.LD.IP q4, a9, 16, q0, q2
EE.VMULAS.S16.QACC.LD.IP q1, a3, 16, q0, q3
EE.VMULAS.S16.QACC.LD.IP q2, a7, 16, q0, q4
# EE.SRCMB.S16.QACC q7, a14, 0
tie728_s16_vector_round_result q7, a14, a15, q6
EE.VST.128.IP q7, a2, 16
1:
EE.ZERO.QACC
EE.VMULAS.S16.QACC.LD.IP q3, a8, 16, q0, q1
EE.VMULAS.S16.QACC.LD.IP q4, a9, 16, q0, q2
EE.VMULAS.S16.QACC q0, q3
EE.VMULAS.S16.QACC q0, q4
# EE.SRCMB.S16.QACC q7, a14, 0
tie728_s16_vector_round_result q7, a14, a15, q6
EE.VST.128.IP q7, a2, 0
retw
.align 4
.text
.global dl_tie728_s16_unaligned_avg_pool2d_22c1
.type dl_tie728_s16_unaligned_avg_pool2d_22c1, @function
.section .iram1
dl_tie728_s16_unaligned_avg_pool2d_22c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: input_y_offset_bytes
# a6: input_x_offset_bytes
# a11: c_div_x_1
# a12: c_remainder_bytes
# a13: mac_shift
l32i a5, a4, 16 # input_y_offset_bytes
l32i a6, a4, 20 # input_x_offset_bytes
l32i a11, a4, 104 # c_div_x_1
l32i a12, a4, 60 # c_remainder
l32i a13, a4, 56 # mac_shift
add a7, a3, a6
add a8, a3, a5
add a9, a8, a6
blti a11, 0, dl_tie728_s16_unaligned_avg_pool2d_22c1_remainder
EE.LD.128.USAR.IP q7, a2, 0
RUR.SAR_BYTE a15
addi a11, a11, 1
addi a14, a4, 64
EE.VLDBC.16 q0, a14 # avg_pool_area_inv
EE.LD.128.USAR.IP q1, a3, 16
EE.LD.128.USAR.IP q2, a3, 0
beqi a15, 0, 0f
beqi a15, 8, 8f
loopgtz a11, 3f
EE.ZERO.QACC
EE.SRC.Q.LD.IP q3, a7, 16, q1, q2
EE.LD.128.USAR.IP q4, a7, 0
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q.LD.IP q5, a8, 16, q3, q4
EE.LD.128.USAR.IP q6, a8, 0
EE.VMULAS.S16.QACC q0, q3
EE.SRC.Q.LD.IP q3, a9, 16, q5, q6
EE.LD.128.USAR.IP q4, a9, 0
EE.VMULAS.S16.QACC q0, q5
EE.SRC.Q.LD.IP q1, a3, 16, q3, q4
EE.LD.128.USAR.IP q2, a3, 0
EE.VMULAS.S16.QACC q0, q3
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a15, q6
dl_tie728_128b_unaligned_store0 q7, a2, a14
3:
j dl_tie728_s16_unaligned_avg_pool2d_22c1_remainder
0:
loopgtz a11, 4f
EE.ZERO.QACC
EE.SRC.Q.LD.IP q3, a7, 16, q1, q2
EE.LD.128.USAR.IP q4, a7, 0
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q.LD.IP q5, a8, 16, q3, q4
EE.LD.128.USAR.IP q6, a8, 0
EE.VMULAS.S16.QACC q0, q3
EE.SRC.Q.LD.IP q3, a9, 16, q5, q6
EE.LD.128.USAR.IP q4, a9, 0
EE.VMULAS.S16.QACC q0, q5
EE.SRC.Q.LD.IP q1, a3, 16, q3, q4
EE.LD.128.USAR.IP q2, a3, 0
EE.VMULAS.S16.QACC q0, q3
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a15, q6
EE.VST.128.IP q7, a2, 16
4:
j dl_tie728_s16_unaligned_avg_pool2d_22c1_remainder
8:
loopgtz a11, 5f
EE.ZERO.QACC
EE.SRC.Q.LD.IP q3, a7, 16, q1, q2
EE.LD.128.USAR.IP q4, a7, 0
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q.LD.IP q5, a8, 16, q3, q4
EE.LD.128.USAR.IP q6, a8, 0
EE.VMULAS.S16.QACC q0, q3
EE.SRC.Q.LD.IP q3, a9, 16, q5, q6
EE.LD.128.USAR.IP q4, a9, 0
EE.VMULAS.S16.QACC q0, q5
EE.SRC.Q.LD.IP q1, a3, 16, q3, q4
EE.LD.128.USAR.IP q2, a3, 0
EE.VMULAS.S16.QACC q0, q3
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a15, q6
dl_tie728_128b_unaligned_store1 q7, a2
5:
dl_tie728_s16_unaligned_avg_pool2d_22c1_remainder:
beqz a12, 6f
EE.ZERO.QACC
EE.SRC.Q.LD.IP q3, a7, 16, q1, q2
EE.LD.128.USAR.IP q4, a7, 0
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q.LD.IP q5, a8, 16, q3, q4
EE.LD.128.USAR.IP q6, a8, 0
EE.VMULAS.S16.QACC q0, q3
EE.SRC.Q q5, q5, q6
EE.LD.128.USAR.XP q3, a9, a12
EE.VLD.128.IP q4, a9, 0
EE.VMULAS.S16.QACC q0, q5
EE.SRC.Q q3, q3, q4
EE.VMULAS.S16.QACC q0, q3
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a15, q6
srli a12, a12, 1
dl_tie728_s16_store_remainder q7, a12, a14, a2
6:
retw
.align 4
.text
.global dl_tie728_s16_avg_pool2d_hwc1
.type dl_tie728_s16_avg_pool2d_hwc1, @function
.section .iram1
dl_tie728_s16_avg_pool2d_hwc1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: input_y_offset
# a6: input_x_offset
# a11: c_div_x_1
# a13: mac_shift
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a8, a4, 48 # filter_height
l32i a9, a4, 52 # filter_width
l32i a11, a4, 104 # c_div_x_1
l32i a13, a4, 56 # mac_shift
addi a14, a4, 64
EE.VLDBC.16 q0, a14 # avg_pool_area_inv
srli a10, a9, 1
addi a10, a10, -1 # filter_w / 2 - 1
blti a9, 2, dl_tie728_s16_avg_pool2d_h1c1_loop
blti a11, 1, dl_tie728_s16_avg_pool2d_hwc1_small_channel
1: # loop c
mov a7, a3
mov a14, a7 # input_ptr
mov a15, a8 # height
EE.ZERO.QACC
2: # loop h
EE.VLD.128.XP q1, a14, a6
EE.VLD.128.XP q2, a14, a6
loopgtz a10, 3f
EE.VMULAS.S16.QACC.LD.XP q1, a14, a6, q0, q1
EE.VMULAS.S16.QACC.LD.XP q2, a14, a6, q0, q2
3:
bbci a9, 0, 4f
# w left 3
EE.VMULAS.S16.QACC.LD.XP q1, a14, a6, q0, q1
EE.VMULAS.S16.QACC q0, q2
EE.VMULAS.S16.QACC q0, q1
j 5f
4: # w left 2
EE.VMULAS.S16.QACC q0, q1
EE.VMULAS.S16.QACC q0, q2
5:
addi a15, a15, -1
add a7, a7, a5
mov a14, a7
bnez a15, 2b
6:
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a15, q6
EE.VST.128.IP q7, a2, 16
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 1b
dl_tie728_s16_avg_pool2d_hwc1_small_channel:
mov a7, a3
mov a14, a7 # input_ptr
mov a15, a8 # height
EE.ZERO.QACC
2: # loop h
EE.VLD.128.XP q1, a14, a6
EE.VLD.128.XP q2, a14, a6
loopgtz a10, 3f
EE.VMULAS.S16.QACC.LD.XP q1, a14, a6, q0, q1
EE.VMULAS.S16.QACC.LD.XP q2, a14, a6, q0, q2
3:
bbci a9, 0, 4f
# w left 3
EE.VMULAS.S16.QACC.LD.XP q1, a14, a6, q0, q1
EE.VMULAS.S16.QACC q0, q2
EE.VMULAS.S16.QACC q0, q1
j 5f
4: # w left 2
EE.VMULAS.S16.QACC q0, q1
EE.VMULAS.S16.QACC q0, q2
5:
addi a15, a15, -1
add a7, a7, a5
mov a14, a7
bnez a15, 2b
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a15, q6
EE.VST.128.IP q7, a2, 0
retw
dl_tie728_s16_avg_pool2d_h1c1_loop:
blti a11, 1, dl_tie728_s16_max_pool2d_h1c1_small_channel
1:
mov a14, a3
EE.ZERO.QACC
EE.VLD.128.XP q1, a14, a5
loopgtz a8, 2f
EE.VMULAS.S16.QACC.LD.XP q1, a14, a5, q0, q1
2:
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a15, q6
EE.VST.128.IP q7, a2, 16
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 1b
dl_tie728_s16_max_pool2d_h1c1_small_channel:
mov a14, a3
EE.ZERO.QACC
EE.VLD.128.XP q1, a14, a5
loopgtz a8, 2f
EE.VMULAS.S16.QACC.LD.XP q1, a14, a5, q0, q1
2:
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a15, q6
EE.VST.128.IP q7, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_unaligned_avg_pool2d_hwc1
.type dl_tie728_s16_unaligned_avg_pool2d_hwc1, @function
.section .iram1
dl_tie728_s16_unaligned_avg_pool2d_hwc1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
# a5: input_y_offset
# a6: input_x_offset
# a11: c_div_x_1
# a12: c_remainder_bytes
# a13: mac_shift
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a8, a4, 48 # filter_height
l32i a9, a4, 52 # filter_width
l32i a11, a4, 104 # c_div_x_1
l32i a12, a4, 60 # c_remainder
l32i a13, a4, 56 # mac_shift
addi a14, a4, 64
EE.VLDBC.16 q0, a14 # avg_pool_area_inv
srli a10, a9, 1
addi a10, a10, -1 # filter_w / 2 - 1
addi a6, a6, -16
addi a11, a11, 1
EE.LD.128.USAR.IP q7, a2, 0
RUR.SAR_BYTE a15
blti a9, 2, dl_tie728_s16_unaligned_avg_pool2d_h1c1_loop
blti a11, 1, dl_tie728_s16_unaligned_avg_pool2d_hwc1_small_channel
1: # loop c
mov a7, a3
mov a14, a7 # input_ptr
mov a4, a8 # height
EE.ZERO.QACC
2: # loop h
EE.LD.128.USAR.IP q1, a14, 16
EE.LD.128.USAR.XP q2, a14, a6
loopgtz a10, 3f
EE.SRC.Q.LD.IP q3, a14, 16, q1, q2
EE.LD.128.USAR.XP q4, a14, a6
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q.LD.IP q1, a14, 16, q3, q4
EE.LD.128.USAR.XP q2, a14, a6
EE.VMULAS.S16.QACC q0, q3
3:
bbci a9, 0, 4f
# w left 3
EE.SRC.Q.LD.IP q3, a14, 16, q1, q2
EE.LD.128.USAR.XP q4, a14, a6
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q.LD.IP q1, a14, 16, q3, q4
EE.LD.128.USAR.XP q2, a14, a6
EE.VMULAS.S16.QACC q0, q3
EE.SRC.Q q1, q1, q2
EE.VMULAS.S16.QACC q0, q1
j 5f
4: # w left 2
EE.SRC.Q.LD.IP q3, a14, 16, q1, q2
EE.LD.128.USAR.XP q4, a14, a6
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q q3, q3, q4
EE.VMULAS.S16.QACC q0, q3
5:
addi a4, a4, -1
add a7, a7, a5
mov a14, a7
bnez a4, 2b
6:
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a14, q6
beqi a15, 0, 7f
beqi a15, 8, 8f
dl_tie728_128b_unaligned_store0 q7, a2, a14
j 9f
7:
EE.VST.128.IP q7, a2, 16
j 9f
8:
dl_tie728_128b_unaligned_store1 q7, a2
9:
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 1b
dl_tie728_s16_unaligned_avg_pool2d_hwc1_small_channel:
beqz a12, 9f
mov a7, a3
mov a14, a7 # input_ptr
mov a4, a8 # height
EE.ZERO.QACC
2: # loop h
EE.LD.128.USAR.IP q1, a14, 16
EE.LD.128.USAR.XP q2, a14, a6
loopgtz a10, 3f
EE.SRC.Q.LD.IP q3, a14, 16, q1, q2
EE.LD.128.USAR.XP q4, a14, a6
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q.LD.IP q1, a14, 16, q3, q4
EE.LD.128.USAR.XP q2, a14, a6
EE.VMULAS.S16.QACC q0, q3
3:
bbci a9, 0, 4f
# w left 3
EE.SRC.Q.LD.IP q3, a14, 16, q1, q2
EE.LD.128.USAR.XP q4, a14, a6
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q q3, q3, q4
EE.LD.128.USAR.XP q1, a14, a12
EE.VLD.128.IP q2, a14, 0
EE.VMULAS.S16.QACC q0, q3
EE.SRC.Q q1, q1, q2
EE.VMULAS.S16.QACC q0, q1
j 5f
4: # w left 2
EE.SRC.Q q1, q1, q2
EE.LD.128.USAR.XP q3, a14, a12
EE.VLD.128.IP q4, a14, 0
EE.VMULAS.S16.QACC q0, q1
EE.SRC.Q q3, q3, q4
EE.VMULAS.S16.QACC q0, q3
5:
addi a4, a4, -1
add a7, a7, a5
mov a14, a7
bnez a4, 2b
6:
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a14, q6
srli a12, a12, 1
dl_tie728_s16_store_remainder q7, a12, a14, a2
9:
retw
dl_tie728_s16_unaligned_avg_pool2d_h1c1_loop:
addi a5, a5, -16
blti a11, 1, dl_tie728_s16_unaligned_avg_pool2d_h1c1_small_channel
1:
mov a14, a3
EE.ZERO.QACC
loopgtz a8, 2f
EE.LD.128.USAR.IP q1, a14, 16
EE.VLD.128.XP q2, a14, a5
EE.SRC.Q q1, q1, q2
EE.VMULAS.S16.QACC q0, q1
2:
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a14, q6
beqi a15, 0, 3f
beqi a15, 8, 4f
dl_tie728_128b_unaligned_store0 q7, a2, a14
j 5f
3:
EE.VST.128.IP q7, a2, 16
j 5f
4:
dl_tie728_128b_unaligned_store1 q7, a2
5:
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 1b
dl_tie728_s16_unaligned_avg_pool2d_h1c1_small_channel:
beqz a12, 5f
1:
mov a14, a3
addi a5, a5, 16
sub a5, a5, a12
EE.ZERO.QACC
loopgtz a8, 2f
EE.LD.128.USAR.XP q1, a14, a12
EE.VLD.128.XP q2, a14, a5
EE.SRC.Q q1, q1, q2
EE.VMULAS.S16.QACC q0, q1
2:
# EE.SRCMB.S16.QACC q7, a13, 0
tie728_s16_vector_round_result q7, a13, a14, q6
srli a12, a12, 1
dl_tie728_s16_store_remainder q7, a12, a14, a2
5:
retw
|
georgevio/IoT-Embedded
| 11,744
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_max_pool2d.S
|
############################################################################################################################################################
####
#### dl_tie728_s8_max_pool2d series
####
############################################################################################################################################################
#include "dl_tie728_s8.S"
.align 4
.text
.global dl_tie728_s8_max_pool2d_22c1
.type dl_tie728_s8_max_pool2d_22c1, @function
.section .iram1
dl_tie728_s8_max_pool2d_22c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a11, a4, 104 # c_div_x_1
add a7, a3, a6
add a8, a3, a5
add a9, a8, a6
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a7, 16
EE.VLD.128.IP q2, a8, 16
loopgtz a11, 0f
EE.VMAX.S8.LD.INCP q3, a9, q7, q0, q1
EE.VMAX.S8.LD.INCP q0, a3, q7, q7, q2
EE.VMAX.S8.LD.INCP q1, a7, q7, q7, q3
EE.VLD.128.IP q2, a8, 16
EE.VST.128.IP q7, a2, 16
0:
EE.VMAX.S8.LD.INCP q3, a9, q7, q0, q1
EE.VMAX.S8 q7, q7, q2
EE.VMAX.S8 q7, q7, q3
EE.VST.128.IP q7, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_unaligned_max_pool2d_22c1
.type dl_tie728_s8_unaligned_max_pool2d_22c1, @function
.section .iram1
dl_tie728_s8_unaligned_max_pool2d_22c1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a10, a4, 4 # input_channel
l32i a11, a4, 104 # c_div_x_1
l32i a12, a4, 60 # c_remainder
add a7, a3, a6
add a8, a3, a5
add a9, a8, a6
blti a11, 0, dl_tie728_s8_unaligned_max_pool2d_22c1_remainder #channel < 16
EE.LD.128.USAR.IP q6, a2, 0 #get output_ptr sar_byte
rur.sar_byte a15
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q1, a3, 0
beqi a15, 0, 1f
beqi a15, 8, 2f
loopgtz a11, 0f
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMAX.S8 q7, q0, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMAX.S8 q7, q7, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMAX.S8 q7, q7, q2
dl_tie728_s8_unaligned_store0 q7, a2, a14
0:
j dl_tie728_s8_unaligned_max_pool2d_22c1_loop_end
1:
loopgtz a11, 0f
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMAX.S8 q7, q0, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMAX.S8 q7, q7, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMAX.S8 q7, q7, q2
EE.VST.128.IP q7, a2, 16
0:
j dl_tie728_s8_unaligned_max_pool2d_22c1_loop_end
2:
loopgtz a11, 0f
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMAX.S8 q7, q0, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMAX.S8 q7, q7, q4
EE.SRC.Q.LD.IP q0, a3, 16, q2, q3
EE.LD.128.USAR.IP q1, a3, 0
EE.VMAX.S8 q7, q7, q2
dl_tie728_s8_unaligned_store1 q7, a2
0:
dl_tie728_s8_unaligned_max_pool2d_22c1_loop_end:
EE.SRC.Q.LD.IP q2, a7, 16, q0, q1
EE.LD.128.USAR.IP q3, a7, 0
EE.SRC.Q.LD.IP q4, a8, 16, q2, q3
EE.LD.128.USAR.IP q5, a8, 0
EE.VMAX.S8 q7, q0, q2
EE.SRC.Q.LD.IP q2, a9, 16, q4, q5
EE.LD.128.USAR.IP q3, a9, 0
EE.VMAX.S8 q7, q7, q4
EE.SRC.Q q2, q2, q3
EE.VMAX.S8 q7, q7, q2
dl_tie728_s8_unaligned_store0 q7, a2, a14
beqz a12, dl_tie728_s8_unaligned_max_pool2d_22c1_end
dl_tie728_s8_unaligned_max_pool2d_22c1_remainder:
EE.LD.128.USAR.XP q0, a3, a12
EE.VLD.128.IP q1, a3, 0
EE.SRC.Q q0, q0, q1
EE.LD.128.USAR.XP q2, a7, a12
EE.VLD.128.IP q3, a7, 0
EE.SRC.Q q2, q2, q3
EE.LD.128.USAR.XP q4, a8, a12
EE.VLD.128.IP q5, a8, 0
EE.VMAX.S8 q7, q0, q2
EE.SRC.Q q4, q4, q5
EE.LD.128.USAR.XP q2, a9, a12
EE.VLD.128.IP q3, a9, 0
EE.VMAX.S8 q7, q7, q4
EE.SRC.Q q2, q2, q3
EE.VMAX.S8 q7, q7, q2
dl_tie728_s8_store_remainder q7, a8, a9, a10, a11, a2, a12
dl_tie728_s8_unaligned_max_pool2d_22c1_end:
retw
.macro dl_tie728_s8_max_pool2d_hw
4:
EE.VLD.128.XP q0, a13, a6
loopgtz a10, 0f
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S8 q7, q7, q0
EE.VLD.128.XP q0, a13, a6
EE.VMAX.S8 q7, q7, q1
0:
bbci a9, 0, 2f
1:#three left
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S8 q7, q7, q0
EE.VLD.128.XP q0, a13, a6
EE.VMAX.S8 q7, q7, q1
EE.VMAX.S8 q7, q7, q0
j 3f
2: # two left
EE.VLD.128.XP q1, a13, a6
EE.VMAX.S8 q7, q7, q0
EE.VMAX.S8 q7, q7, q1
3:
addi a14, a14, -1
add a7, a7, a5
mov a13, a7
bnez a14, 4b
.endm
.align 4
.text
.global dl_tie728_s8_max_pool2d_hwc1
.type dl_tie728_s8_max_pool2d, @function
.section .iram1
dl_tie728_s8_max_pool2d_hwc1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a7, a4, 4 # input_channel
l32i a8, a4, 48 # filter_height
l32i a9, a4, 52 # filter_width
l32i a11, a4, 104 # c_div_x_1
srli a10, a9, 1
addi a10, a10, -1 # filter_w / 2 - 1
beqi a9, 1, dl_tie728_s8_max_pool2d_h1c1 #filter_width == 1
blti a11, 1, dl_tie728_s8_max_pool2d_hw_small_channel
5:
mov a7, a3
mov a13, a7
EE.VLD.128.IP q7, a13, 0
mov a14, a8
dl_tie728_s8_max_pool2d_hw
EE.VST.128.IP q7, a2, 16
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 5b
dl_tie728_s8_max_pool2d_hw_small_channel:
mov a7, a3
mov a13, a7
EE.VLD.128.IP q7, a13, 0
mov a14, a8
dl_tie728_s8_max_pool2d_hw
EE.VST.128.IP q7, a2, 16
retw
dl_tie728_s8_max_pool2d_h1c1:
addi a8, a8, -1
blti a11, 1, dl_tie728_s8_max_pool2d_h1_small_channel
1:
mov a13, a3
EE.VLD.128.XP q7, a13, a5
loopgtz a8, 0f
EE.VLD.128.XP q0, a13, a5
EE.VMAX.S8 q7, q7, q0
0:
EE.VST.128.IP q7, a2, 16
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 1b
dl_tie728_s8_max_pool2d_h1_small_channel:
mov a13, a3
EE.VLD.128.XP q7, a13, a5
loopgtz a8, 0f
EE.VLD.128.XP q0, a13, a5
EE.VMAX.S8 q7, q7, q0
0:
EE.VST.128.IP q7, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_unaligned_max_pool2d_hwc1
.type dl_tie728_s8_unaligned_max_pool2d_hwc1, @function
.section .iram1
dl_tie728_s8_unaligned_max_pool2d_hwc1:
.align 4
entry sp, 16
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a5, a4, 16 # input_y_offset
l32i a6, a4, 20 # input_x_offset
l32i a7, a4, 4 # input_channel
l32i a8, a4, 48 # filter_height
l32i a9, a4, 52 # filter_width
l32i a11, a4, 104 # c_div_x_1
l32i a12, a4, 60 # c_remainder
srli a10, a9, 1
addi a10, a10, -1 # filter_w / 2 - 1
addi a6, a6, -16
EE.LD.128.USAR.IP q6, a2, 0 #get output_ptr sar_byte
rur.sar_byte a15
addi a11, a11, 1
beqi a9, 1, dl_tie728_s8_unaligned_max_pool2d_h1c1 #filter_width == 1
blti a11, 1, dl_tie728_s8_unaligned_max_pool2d_hw_remainder
9:
mov a7, a3
mov a13, a7
EE.LD.128.USAR.IP q6, a13, 16
EE.LD.128.USAR.IP q7, a13, -16
EE.SRC.Q q7, q6, q7
mov a14, a8
4:
EE.LD.128.USAR.IP q0, a13, 16
EE.LD.128.USAR.XP q1, a13, a6
loopgtz a10, 0f
EE.SRC.Q.LD.IP q2, a13, 16, q0, q1
EE.LD.128.USAR.XP q1, a13, a6
EE.VMAX.S8 q7, q7, q0
EE.SRC.Q.LD.IP q0, a13, 16, q2, q1
EE.LD.128.USAR.XP q1, a13, a6
EE.VMAX.S8 q7, q7, q2
0:
bbci a9, 0, 2f
1:#three left
EE.SRC.Q.LD.IP q2, a13, 16, q0, q1
EE.LD.128.USAR.XP q1, a13, a6
EE.VMAX.S8 q7, q7, q0
EE.SRC.Q.LD.IP q0, a13, 16, q2, q1
EE.LD.128.USAR.XP q1, a13, a6
EE.VMAX.S8 q7, q7, q2
EE.SRC.Q q0, q0, q1
EE.VMAX.S8 q7, q7, q0
j 3f
2:# two left
EE.SRC.Q.LD.IP q2, a13, 16, q0, q1
EE.LD.128.USAR.XP q1, a13, a6
EE.VMAX.S8 q7, q7, q0
EE.SRC.Q q2, q2, q1
EE.VMAX.S8 q7, q7, q2
3:
addi a14, a14, -1
add a7, a7, a5
mov a13, a7
bnez a14, 4b
beqi a15, 0, 5f
beqi a15, 8, 6f
dl_tie728_s8_unaligned_store0 q7, a2, a14
j 7f
5:
EE.VST.128.IP q7, a2, 16
j 7f
6:
dl_tie728_s8_unaligned_store1 q7, a2
7:
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 9b
dl_tie728_s8_unaligned_max_pool2d_hw_remainder:
beqz a12, dl_tie728_s8_unaligned_max_pool2d_hw_remainder_end
mov a7, a3
mov a13, a7
EE.LD.128.USAR.IP q6, a13, 16
EE.LD.128.USAR.IP q7, a13, -16
EE.SRC.Q q7, q6, q7
mov a14, a8
addi a6, a6, 16
sub a6, a6, a12
1:
loopgtz a9, 0f
EE.LD.128.USAR.XP q0, a13, a12
EE.VLD.128.XP q1, a13, a6
EE.SRC.Q q0, q0, q1
EE.VMAX.S8 q7, q7, q0
0:
addi a14, a14, -1
add a7, a7, a5
mov a13, a7
bnez a14, 1b
dl_tie728_s8_store_remainder q7, a8, a9, a10, a11, a2, a12
dl_tie728_s8_unaligned_max_pool2d_hw_remainder_end:
retw
dl_tie728_s8_unaligned_max_pool2d_h1c1:
addi a5, a5, -16
addi a8, a8, -1
blti a11, 1, dl_tie728_s8_unaligned_max_pool2d_h1_remainder
5:
mov a13, a3
EE.LD.128.USAR.IP q6, a13, 16
EE.VLD.128.XP q7, a13, a5
EE.SRC.Q q7, q6, q7
loopgtz a8, 0f
EE.LD.128.USAR.IP q0, a13, 16
EE.LD.128.USAR.XP q1, a13, a5
EE.SRC.Q q0, q0, q1
EE.VMAX.S8 q7, q7, q0
0:
beqi a15, 0, 1f
beqi a15, 8, 2f
dl_tie728_s8_unaligned_store0 q7, a2, a14
j 3f
1:
EE.VST.128.IP q7, a2, 16
j 3f
2:
dl_tie728_s8_unaligned_store1 q7, a2
3:
addi a3, a3, 16
addi a11, a11, -1
bnez a11, 5b
dl_tie728_s8_unaligned_max_pool2d_h1_remainder:
beqz a12, dl_tie728_s8_unaligned_max_pool2d_h1_remainder_end
addi a5, a5, 16
sub a5, a5, a12
mov a13, a3
EE.LD.128.USAR.XP q6, a13, a12
EE.VLD.128.XP q7, a13, a5
EE.SRC.Q q7, q6, q7
loopgtz a8, 0f
EE.LD.128.USAR.XP q0, a13, a12
EE.VLD.128.XP q1, a13, a5
EE.SRC.Q q0, q0, q1
EE.VMAX.S8 q7, q7, q0
0:
dl_tie728_s8_store_remainder q7, a8, a9, a10, a11, a2, a12
dl_tie728_s8_unaligned_max_pool2d_h1_remainder_end:
retw
|
georgevio/IoT-Embedded
| 3,674
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_prelu.S
|
#include "dl_tie728_s8.S"
.align 4
.text
.global dl_tie728_s8_prelu_11c
.type dl_tie728_s8_prelu_11c, @function
.section .iram1
dl_tie728_s8_prelu_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: c_div_x = n_div_x
# a12: activation_alpha_ptr
# a13: activation_shift
# a14: output_shift
# a15: output_scale
l32i a5, a4, 96 # n_div_x
l32i a12, a4, 80 # activation_alpha_ptr
l32i a13, a4, 84 # activation_shift
l32i a14, a4, 172 # output_shift
l32i a15, a4, 176 # output_scale
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a12, 16
ee.zero.q q2 # all 0
addi a7, a4, 176
ee.vldbc.8.ip q3, a7, 0 # all output_scale
loopgtz a5, 0f
# neg part, alpha * input, right shift: output - alpha - input
ee.zero.qacc
ee.vmulas.s8.qacc.ld.ip q1, a12, 16, q0, q1
tie728_s8_vector_round_result q4, a13, a6, q6
ee.vcmp.lt.s8 q6, q0, q2
ee.andq q4, q4, q6
# pos part, *scale, right shift: output - input
ee.zero.qacc
ee.vmulas.s8.qacc q0, q3
tie728_s8_vector_round_result q5, a14, a6, q6
ee.vcmp.gt.s8 q6, q0, q2
ee.andq q5, q5, q6
ee.vadds.s8.ld.incp q0, a3, q4, q4, q5
ee.vst.128.ip q4, a2, 16
0:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_prelu_11c
.type dl_tie728_s8_unaligned_prelu_11c, @function
.section .iram1
dl_tie728_s8_unaligned_prelu_11c:
.align 4
entry sp, 16
# a2: int8_t *output_ptr
# a3: int8_t *input_ptr
# a4: void *args
# a5: c_div_x = n_div_x
# a6: c_remainder
# a12: activation_alpha_ptr
# a13: activation_shift
# a14: output_shift
# a15: output_scale
l32i a5, a4, 96 # c_div_x
l32i a6, a4, 136 # c_remainder
l32i a12, a4, 80 # activation_alpha_ptr
l32i a13, a4, 84 # activation_shift
l32i a14, a4, 172 # output_shift
l32i a15, a4, 176 # output_scale
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q1, a12, 16
addi a7, a4, 176
ee.vldbc.8.ip q7, a7, 0 # all output_scale
loopgtz a5, 0f
ee.ld.128.usar.ip q2, a3, 16
ee.src.q.qup q4, q0, q2
ee.ld.128.usar.ip q3, a12, 16
ee.src.q.qup q5, q1, q3
# neg part, alpha * input, right shift: output - alpha - input
ee.zero.qacc
ee.vmulas.s8.qacc q4, q5
tie728_s8_vector_round_result q5, a13, a8, q6
ee.zero.q q2
ee.vcmp.lt.s8 q6, q4, q2
ee.andq q5, q5, q6
# pos part, *scale, right shift: output - input
ee.zero.qacc
ee.vmulas.s8.qacc q4, q7
tie728_s8_vector_round_result q3, a14, a8, q6
ee.vcmp.gt.s8 q6, q4, q2
ee.andq q3, q3, q6
ee.vadds.s8 q3, q3, q5
dl_tie728_s8_unaligned_store0 q3, a2, a8
0:
bnez a6, dl_tie728_s8_unaligned_prelu_remainder
retw
dl_tie728_s8_unaligned_prelu_remainder:
ee.ld.128.usar.ip q2, a3, 16
ee.src.q.qup q4, q0, q2
ee.ld.128.usar.ip q3, a12, 16
ee.src.q.qup q5, q1, q3
# neg part, alpha * input, right shift: output - alpha - input
ee.zero.qacc
ee.vmulas.s8.qacc q4, q5
tie728_s8_vector_round_result q5, a13, a8, q6
ee.zero.q q2
ee.vcmp.lt.s8 q6, q4, q2
ee.andq q5, q5, q6
# pos part, *scale, right shift: output - input
ee.zero.qacc
ee.vmulas.s8.qacc q4, q7
tie728_s8_vector_round_result q3, a14, a8, q6
ee.vcmp.gt.s8 q6, q4, q2
ee.andq q3, q3, q6
ee.vadds.s8 q3, q3, q5
dl_tie728_s8_store_remainder q3, a3, a4, a5, a7, a2, a6
retw
|
georgevio/IoT-Embedded
| 40,295
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_sub2d.S
|
# include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_sub2d_11c series
####
############################################################################################################################################################
.macro dl_tie728_s16_rescale_sub_rescale_output input0, input1, output, output_scale, output_shift, neg_output_scale, rescale_input
EE.ZERO.QACC
blti \rescale_input, 2, 100f
# input1 is in the front
EE.VMULAS.s16.QACC \input0, \neg_output_scale
EE.VMULAS.s16.QACC \input1, \output_scale
j 101f
100: #input0 is in the front
EE.VMULAS.s16.QACC \input0, \output_scale
EE.VMULAS.s16.QACC \input1, \neg_output_scale
101:
EE.SRCMB.S16.QACC \output, \output_shift, 0
.endm
.align 4
.text
.global dl_tie728_s16_sub2d_11c
.type dl_tie728_s16_sub2d_11c, @function
.section .iram1
dl_tie728_s16_sub2d_11c:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x
l32i a6, a5, 68
l32i a7, a5, 72
beqz a6, dl_tie728_s16_sub2d_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VSUBS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VST.128.IP q5, a2, 16
0:
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VSUBS.S16 q5, q2, q3
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q0, a3, 16
EE.VSUBS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VST.128.IP q5, a2, 16
EE.VSUBS.S16 q4, q0, q1
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s16_sub2d_small_channel:
blti a7, 0, 5f
loopgtz a7, 1f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VSUBS.S16 q2, q0, q1
EE.VST.128.IP q2, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VSUBS.S16 q2, q0, q1
EE.VST.128.IP q2, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_rescale_sub2d_11c
.type dl_tie728_s16_rescale_sub2d_11c, @function
.section .iram1
dl_tie728_s16_rescale_sub2d_11c:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a12: rescale_input
# a13: neg_output_scale_ptr
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a12, a5, 80
beqi a8, 1, dl_tie728_s16_rescale_sub2d_output
dl_tie728_s16_rescale_sub2d_output_scale:
s16i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
addi a13, a5, 104
EE.VLDBC.16 q4, a13 # all neg_output_scale
loopgtz a6, 1f
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VST.128.IP q1, a2, 16
1:
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_sub2d_output:
movi a13, -1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all -1
blti a12, 2, dl_tie728_s16_rescale_sub2d_output_0
#input1 in the front
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 3f
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.LDQA.S16.128.IP a4, 16
EE.VST.128.IP q1, a2, 16
3:
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_sub2d_output_0: #input0 in the front
EE.LDQA.S16.128.IP a4, 16
loopgtz a6, 2f
EE.SRCMB.S16.QACC q1, a7, 0
EE.LDQA.S16.128.IP a3, 16
EE.VMULAS.S16.QACC q1, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.LDQA.S16.128.IP a4, 16
EE.VST.128.IP q1, a2, 16
2:
EE.SRCMB.S16.QACC q1, a7, 0
EE.LDQA.S16.128.IP a3, 16
EE.VMULAS.S16.QACC q1, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VST.128.IP q1, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_sub2d_11c_relu
.type dl_tie728_s16_sub2d_11c_relu, @function
.section .iram1
dl_tie728_s16_sub2d_11c_relu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 68
l32i a7, a5, 72
l32i a14, a5, 52
l32i a15, a5, 60
beqz a6, dl_tie728_s16_sub2d_small_channel_relu
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S16 q4, a14, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VSUBS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VRELU.S16 q5, a14, a15
EE.VST.128.IP q5, a2, 16
0:
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S16 q4, a14, a15
EE.VST.128.IP q4, a2, 16
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VSUBS.S16 q5, q2, q3
EE.VRELU.S16 q5, a14, a15
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q0, a3, 16
EE.VSUBS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VRELU.S16 q5, a14, a15
EE.VST.128.IP q5, a2, 16
EE.VSUBS.S16 q4, q0, q1
EE.VRELU.S16 q4, a14, a15
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s16_sub2d_small_channel_relu:
blti a7, 0, 5f
loopgtz a7, 1f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VSUBS.S16 q2, q0, q1
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VSUBS.S16 q2, q0, q1
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_rescale_sub2d_11c_relu
.type dl_tie728_s16_rescale_sub2d_11c_relu, @function
.section .iram1
dl_tie728_s16_rescale_sub2d_11c_relu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a12: rescale_input
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a10, a5, 76
l32i a12, a5, 80
l32i a14, a5, 52
l32i a15, a5, 60
srli a10, a10, 1
beqi a8, 1, dl_tie728_s16_rescale_sub2d_output_relu
dl_tie728_s16_rescale_sub2d_output_scale_relu:
s16i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
addi a13, a5, 104
EE.VLDBC.16 q4, a13 # all neg_output_scale
loopgtz a6, 1f
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
1:
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_sub2d_output_relu:
movi a13, -1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all -1
blti a12, 2, dl_tie728_s16_rescale_sub2d_output_relu_0
#input1 in the front
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 3f
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.LDQA.S16.128.IP a4, 16
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
3:
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_sub2d_output_relu_0: #input0 in the front
EE.LDQA.S16.128.IP a4, 16
loopgtz a6, 2f
EE.SRCMB.S16.QACC q1, a7, 0
EE.LDQA.S16.128.IP a3, 16
EE.VMULAS.S16.QACC q1, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.LDQA.S16.128.IP a4, 16
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
2:
EE.SRCMB.S16.QACC q1, a7, 0
EE.LDQA.S16.128.IP a3, 16
EE.VMULAS.S16.QACC q1, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VRELU.S16 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
.align 4
.text
.global dl_tie728_s16_sub2d_11c_prelu
.type dl_tie728_s16_sub2d_11c_prelu, @function
.section .iram1
dl_tie728_s16_sub2d_11c_prelu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 68
l32i a7, a5, 72
l32i a8, a5, 76
l32i a14, a5, 56
l32i a15, a5, 60
srli a8, a8, 1
beqz a6, dl_tie728_s16_sub2d_small_channel_prelu
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S16 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VPRELU.S16 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
0:
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S16 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16 q5, q2, q3
EE.VPRELU.S16 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16.LD.INCP q1, a4, q5, q2, q3
EE.VPRELU.S16 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16 q4, q0, q1
EE.VPRELU.S16 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s16_sub2d_small_channel_prelu:
blti a7, 0, 5f
loopgtz a7, 1f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16 q2, q0, q1
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16 q2, q0, q1
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
5:
retw
.align 4
.text
.global dl_tie728_s16_rescale_sub2d_11c_prelu
.type dl_tie728_s16_rescale_sub2d_11c_prelu, @function
.section .iram1
dl_tie728_s16_rescale_sub2d_11c_prelu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a12: rescale_input
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a12, a5, 80
l32i a14, a5, 56
l32i a15, a5, 60
beqi a8, 1, dl_tie728_s16_rescale_sub2d_output_prelu
dl_tie728_s16_rescale_sub2d_output_scale_prelu:
s16i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
addi a13, a5, 104
EE.VLDBC.16 q4, a13 # all neg_output_scale
loopgtz a6, 1f
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
EE.VLD.128.IP q6, a14, 16
dl_tie728_s16_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VPRELU.S16 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
1:
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S16.QACC q1, a7, 0
EE.VLD.128.IP q6, a14, 16
dl_tie728_s16_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VPRELU.S16 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_sub2d_output_prelu:
movi a13, -1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all -1
blti a12, 2, dl_tie728_s16_rescale_sub2d_output_prelu_0
#input1 in the front
EE.LDQA.S16.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, 3f
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC.LD.IP q0, a3, 16, q0, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LDQA.S16.128.IP a4, 16
EE.VPRELU.S16 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
3:
EE.SRCMB.S16.QACC q1, a7, 0
EE.VMULAS.S16.QACC q0, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q1, a9, 0
EE.VPRELU.S16 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s16_rescale_sub2d_output_prelu_0: #input0 in the front
EE.LDQA.S16.128.IP a4, 16
loopgtz a6, 2f
EE.SRCMB.S16.QACC q1, a7, 0
EE.LDQA.S16.128.IP a3, 16
EE.VMULAS.S16.QACC q1, q7
EE.SRCMB.S16.QACC q1, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LDQA.S16.128.IP a4, 16
EE.VPRELU.S16 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
2:
EE.SRCMB.S16.QACC q1, a7, 0
EE.LDQA.S16.128.IP a3, 16
EE.VMULAS.S16.QACC q1, q7
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q1, a9, 0
EE.VPRELU.S16 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
retw
############################################################################################################################################################
####
#### tie728_s16_unaligned_sub2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s16_unaligned_sub2d_11c
.type dl_tie728_s16_unaligned_sub2d_11c, @function
.section .iram1
dl_tie728_s16_unaligned_sub2d_11c:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a12: rescale_input
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a12, a5, 80
bgei a7, 0, dl_tie728_s16_unaligned_rescale_sub2d_11c
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s16_unaligned_sub2d_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s16_unaligned_sub2d_11c_0
beqi a13, 8, dl_tie728_s16_unaligned_sub2d_11c_1
loopgtz a6, 0f #dl_tie728_s16_unaligned_sub2d_11c
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_unaligned_sub2d_11c_remainder
#output sar = 0
dl_tie728_s16_unaligned_sub2d_11c_0:
loopgtz a6, 1f #dl_tie728_s16_unaligned_sub2d_11c_loop0
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.VST.128.IP q2, a2, 16
j dl_tie728_s16_unaligned_sub2d_11c_remainder
# #output sar = 8
dl_tie728_s16_unaligned_sub2d_11c_1:
loopgtz a6, 2f #dl_tie728_s16_unaligned_sub2d_11c_loop1
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_unaligned_sub2d_11c_remainder
dl_tie728_s16_unaligned_sub2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s16_unaligned_sub2d_11c_remainder:
beqz a10, dl_tie728_s16_unaligned_sub2d_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_sub2d_end:
retw
## rescaled sub
dl_tie728_s16_unaligned_rescale_sub2d_11c:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s16_rescale_unaligned_sub2d_output_shift
### rescaled to output by *scale) >> shift (left shift)
dl_tie728_s16_rescale_unaligned_sub2d_output_scale:
s32i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
addi a13, a5, 104
EE.VLDBC.16 q6, a13
blti a6, 0, dl_tie728_s16_rescale_unaligned_sub2d_scale_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s16_rescale_unaligned_sub2d_11c_scale
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q2, a2, a11
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_rescale_unaligned_sub2d_scale_remainder
dl_tie728_s16_rescale_unaligned_sub2d_scale_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6 #input1 sar
dl_tie728_s16_rescale_unaligned_sub2d_scale_remainder:
beqz a10, dl_tie728_s16_unaligned_rescale_sub2d_output_scale_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a12, a2
dl_tie728_s16_unaligned_rescale_sub2d_output_scale_end:
retw
### rescaled to output by right shift
dl_tie728_s16_rescale_unaligned_sub2d_output_shift:
movi a13, -1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all -1
blti a6, 0, dl_tie728_s16_rescale_unaligned_sub2d_shift_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s16_rescale_unaligned_sub2d_11c_shift
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0 # input1 >> shift
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S16.QACC q5, a9, 0
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_128b_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S16.QACC q5, a9, 0
dl_tie728_128b_unaligned_store0 q5, a2, a13
j dl_tie728_s16_rescale_unaligned_sub2d_shift_remainder
dl_tie728_s16_rescale_unaligned_sub2d_shift_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6 #input1 sar
dl_tie728_s16_rescale_unaligned_sub2d_shift_remainder:
beqz a10, dl_tie728_s16_unaligned_rescale_sub2d_output_shift_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S16.QACC q5, a9, 0
srli a10, a10, 1
dl_tie728_s16_store_remainder q5, a10, a13, a2
dl_tie728_s16_unaligned_rescale_sub2d_output_shift_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_sub2d_11c_relu
.type dl_tie728_s16_unaligned_sub2d_11c_relu, @function
.section .iram1
dl_tie728_s16_unaligned_sub2d_11c_relu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a12: rescale_input
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a12, a5, 80
l32i a14, a5, 52
l32i a15, a5, 60
bgei a7, 0, dl_tie728_s16_unaligned_rescale_sub2d_11c_relu
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s16_unaligned_sub2d_11c_small_remainder_relu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s16_unaligned_sub2d_11c_relu_0
beqi a13, 8, dl_tie728_s16_unaligned_sub2d_11c_relu_1
loopgtz a6, 0f #dl_tie728_s16_unaligned_sub2d_11c_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_unaligned_sub2d_11c_remainder_relu
#output sar = 0
dl_tie728_s16_unaligned_sub2d_11c_relu_0:
loopgtz a6, 1f #dl_tie728_s16_unaligned_sub2d_11c_loop0_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.VRELU.S16 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie728_s16_unaligned_sub2d_11c_remainder_relu
# #output sar = 8
dl_tie728_s16_unaligned_sub2d_11c_relu_1:
loopgtz a6, 2f #dl_tie728_s16_unaligned_sub2d_11c_loop1_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_unaligned_sub2d_11c_remainder_relu
dl_tie728_s16_unaligned_sub2d_11c_small_remainder_relu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s16_unaligned_sub2d_11c_remainder_relu:
beqz a10, dl_tie728_s16_unaligned_sub2d_end_relu
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.VRELU.S16 q2, a14, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_sub2d_end_relu:
retw
## rescaled sub
dl_tie728_s16_unaligned_rescale_sub2d_11c_relu:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s16_rescale_unaligned_sub2d_output_shift_relu
### rescaled to output by *scale) >> shift
dl_tie728_s16_rescale_unaligned_sub2d_output_scale_relu:
s32i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
addi a13, a5, 104
EE.VLDBC.16 q6, a13
blti a6, 0, dl_tie728_s16_rescale_unaligned_sub2d_scale_small_remainder_relu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s16_rescale_unaligned_sub2d_11c_scale_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a11
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
EE.VRELU.S16 q2, a14, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_rescale_unaligned_sub2d_scale_remainder_relu
dl_tie728_s16_rescale_unaligned_sub2d_scale_small_remainder_relu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6 #input1 sar
dl_tie728_s16_rescale_unaligned_sub2d_scale_remainder_relu:
beqz a10, dl_tie728_s16_unaligned_rescale_sub2d_output_scale_end_relu # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
EE.VRELU.S16 q2, a14, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_rescale_sub2d_output_scale_end_relu:
retw
### rescaled to output by right shift
dl_tie728_s16_rescale_unaligned_sub2d_output_shift_relu:
movi a13, -1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all -1
blti a6, 0, dl_tie728_s16_rescale_unaligned_sub2d_shift_small_remainder_relu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s16_rescale_unaligned_sub2d_11c_shift_relu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0 # input1 >> shift
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S16.QACC q5, a9, 0
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S16 q5, a14, a15
dl_tie728_128b_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S16.QACC q5, a9, 0
EE.VRELU.S16 q5, a14, a15
dl_tie728_128b_unaligned_store0 q5, a2, a13
j dl_tie728_s16_rescale_unaligned_sub2d_shift_remainder_relu
dl_tie728_s16_rescale_unaligned_sub2d_shift_small_remainder_relu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6 #input1 sar
dl_tie728_s16_rescale_unaligned_sub2d_shift_remainder_relu:
beqz a10, dl_tie728_s16_unaligned_rescale_sub2d_output_shift_end_relu # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S16.QACC q5, a9, 0
EE.VRELU.S16 q5, a14, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q5, a10, a13, a2
dl_tie728_s16_unaligned_rescale_sub2d_output_shift_end_relu:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_sub2d_11c_prelu
.type dl_tie728_s16_unaligned_sub2d_11c_prelu, @function
.section .iram1
dl_tie728_s16_unaligned_sub2d_11c_prelu:
.align 4
entry sp, 32
# a2: int16_t *output_ptr
# a3: int16_t *input0_ptr
# a4: int16_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a12: rescale_input
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a12, a5, 80
l32i a14, a5, 56
l32i a15, a5, 60
bgei a7, 0, dl_tie728_s16_unaligned_rescale_sub2d_11c_prelu
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s16_unaligned_sub2d_11c_small_remainder_prelu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s16_unaligned_sub2d_11c_prelu_0
beqi a13, 8, dl_tie728_s16_unaligned_sub2d_11c_prelu_1
loopgtz a6, 0f #dl_tie728_s16_unaligned_sub2d_11c_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16 q2, q2, q5
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_unaligned_sub2d_11c_remainder_prelu
#output sar = 0
dl_tie728_s16_unaligned_sub2d_11c_prelu_0:
loopgtz a6, 1f #dl_tie728_s16_unaligned_sub2d_11c_loop0_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16 q2, q2, q5
EE.VPRELU.S16 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
j dl_tie728_s16_unaligned_sub2d_11c_remainder_prelu
# #output sar = 8
dl_tie728_s16_unaligned_sub2d_11c_prelu_1:
loopgtz a6, 2f #dl_tie728_s16_unaligned_sub2d_11c_loop1_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S16 q2, q2, q5
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16 q2, q2, q5
EE.VPRELU.S16 q2, q2, q6, a15
dl_tie728_128b_unaligned_store1 q2, a2
j dl_tie728_s16_unaligned_sub2d_11c_remainder_prelu
dl_tie728_s16_unaligned_sub2d_11c_small_remainder_prelu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s16_unaligned_sub2d_11c_remainder_prelu:
beqz a10, dl_tie728_s16_unaligned_sub2d_end_prelu
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S16 q2, q2, q5
EE.VPRELU.S16 q2, q2, q6, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_sub2d_end_prelu:
retw
## rescaled sub
dl_tie728_s16_unaligned_rescale_sub2d_11c_prelu:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s16_rescale_unaligned_sub2d_output_shift_prelu
### rescaled to output by *scale) >> shift
dl_tie728_s16_rescale_unaligned_sub2d_output_scale_prelu:
s32i a8, a1, 0
EE.VLDBC.16 q7, a1 # all output_scale
addi a13, a5, 104
EE.VLDBC.16 q6, a13
blti a6, 0, dl_tie728_s16_rescale_unaligned_sub2d_scale_small_remainder_prelu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s16_rescale_unaligned_sub2d_11c_scale_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
EE.VLD.128.IP q5, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q2, q2, q5, a15
dl_tie728_128b_unaligned_store0 q2, a2, a11
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
EE.VLD.128.IP q5, a14, 16
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
EE.VPRELU.S16 q2, q2, q5, a15
dl_tie728_128b_unaligned_store0 q2, a2, a13
j dl_tie728_s16_rescale_unaligned_sub2d_scale_remainder_prelu
dl_tie728_s16_rescale_unaligned_sub2d_scale_small_remainder_prelu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6 #input1 sar
dl_tie728_s16_rescale_unaligned_sub2d_scale_remainder_prelu:
beqz a10, dl_tie728_s16_unaligned_rescale_sub2d_output_scale_end_prelu # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q1, a7, 0
EE.VLD.128.IP q5, a14, 16
dl_tie728_s16_rescale_sub_rescale_output q2, q1, q2, q7, a9, q6, a12
EE.VPRELU.S16 q2, q2, q5, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q2, a10, a13, a2
dl_tie728_s16_unaligned_rescale_sub2d_output_scale_end_prelu:
retw
### rescaled to output by right shift
dl_tie728_s16_rescale_unaligned_sub2d_output_shift_prelu:
movi a13, -1
s16i a13, a1, 0
EE.VLDBC.16 q7, a1 # all -1
blti a6, 0, dl_tie728_s16_rescale_unaligned_sub2d_shift_small_remainder_prelu # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s16_rescale_unaligned_sub2d_11c_shift_prelu
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S16.QACC q5, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S16 q5, q5, q6, a15
dl_tie728_128b_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q5, a9, 0
EE.VPRELU.S16 q5, q5, q6, a15
dl_tie728_128b_unaligned_store0 q5, a2, a13
j dl_tie728_s16_rescale_unaligned_sub2d_shift_remainder_prelu
dl_tie728_s16_rescale_unaligned_sub2d_shift_small_remainder_prelu:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11 #input0 sar
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6 #input1 sar
dl_tie728_s16_rescale_unaligned_sub2d_shift_remainder_prelu:
beqz a10, dl_tie728_s16_unaligned_rescale_sub2d_output_shift_end_prelu # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S16.QACC q5
EE.SRCMB.S16.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S16.QACC q2, q7 # input0 - input1 >> shift
j 12f
11:
EE.MOV.S16.QACC q2
EE.VMULAS.S16.QACC q5, q7 # input0 - input1 >> shift
12:
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S16.QACC q5, a9, 0
EE.VPRELU.S16 q5, q5, q6, a15
srli a10, a10, 1
dl_tie728_s16_store_remainder q5, a10, a13, a2
dl_tie728_s16_unaligned_rescale_sub2d_output_shift_end_prelu:
retw
|
georgevio/IoT-Embedded
| 13,129
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_greater.S
|
#include "dl_tie728_s8.S"
#void dl_tie728_s8_greater_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_greater_w1_16_w2_16
.type dl_tie728_s8_greater_w1_16_w2_16, @function
#.section .iram1
dl_tie728_s8_greater_w1_16_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
movi a14, 0
tie728_s8_greater_w1_16_w2_16_loop:
beq a14, a5, tie728_s8_greater_w1_16_w2_16_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.gt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_greater_w1_16_w2_16_loop
tie728_s8_greater_w1_16_w2_16_end:
retw
#void dl_tie728_s8_greater_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_greater_w1_16_w2_1
.type dl_tie728_s8_greater_w1_16_w2_1, @function
#.section .iram1
dl_tie728_s8_greater_w1_16_w2_1:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s8_greater_w1_16_w2_1_loop:
beq a14, a5, tie728_s8_greater_w1_16_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.gt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_greater_w1_16_w2_1_loop
tie728_s8_greater_w1_16_w2_1_end:
retw
#void dl_tie728_s8_greater_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_greater_w1_1_w2_16
.type dl_tie728_s8_greater_w1_1_w2_16, @function
#.section .iram1
dl_tie728_s8_greater_w1_1_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s8_greater_w1_1_w2_16_loop:
beq a14, a5, tie728_s8_greater_w1_1_w2_16_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.gt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_greater_w1_1_w2_16_loop
tie728_s8_greater_w1_1_w2_16_end:
retw
.align 4
.text
.global dl_tie728_s8_greater_w1_16_w2_16_unaligned
.type dl_tie728_s8_greater_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_greater_w1_16_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s8_greater_w1_16_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_greater_w1_16_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_greater_w1_16_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_greater_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_greater_w1_16_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_greater_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_greater_w1_16_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_greater_w1_16_w2_16_unaligned_remainder
dl_tie728_s8_greater_w1_16_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_greater_w1_16_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_greater_w1_16_w2_16_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s8_greater_w1_16_w2_1_unaligned
.type dl_tie728_s8_greater_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s8_greater_w1_16_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s8_greater_w1_16_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_greater_w1_16_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_greater_w1_16_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_greater_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s8_greater_w1_16_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_greater_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s8_greater_w1_16_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_greater_w1_16_w2_1_unaligned_remainder
dl_tie728_s8_greater_w1_16_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s8_greater_w1_16_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.gt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_greater_w1_16_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s8_greater_w1_1_w2_16_unaligned
.type dl_tie728_s8_greater_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_greater_w1_1_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr broadcast
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s8_greater_w1_1_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s8_greater_w1_1_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_greater_w1_1_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_greater_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_greater_w1_1_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_greater_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_greater_w1_1_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.gt.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_greater_w1_1_w2_16_unaligned_remainder
dl_tie728_s8_greater_w1_1_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_greater_w1_1_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.gt.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_greater_w1_1_w2_16_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 12,931
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_less.S
|
#include "dl_tie728_s8.S"
#void dl_tie728_s8_less_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_less_w1_16_w2_16
.type dl_tie728_s8_less_w1_16_w2_16, @function
#.section .iram1
dl_tie728_s8_less_w1_16_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
movi a14, 0
tie728_s8_less_w1_16_w2_16_loop:
beq a14, a5, tie728_s8_less_w1_16_w2_16_end
ee.vld.128.ip q0, a3, 16
ee.vld.128.ip q1, a4, 16
ee.vcmp.lt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_less_w1_16_w2_16_loop
tie728_s8_less_w1_16_w2_16_end:
retw
#void dl_tie728_s8_less_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_less_w1_16_w2_1
.type dl_tie728_s8_less_w1_16_w2_1, @function
#.section .iram1
dl_tie728_s8_less_w1_16_w2_1:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q1, a4, 0 // input1 broadcast
movi a14, 0
tie728_s8_less_w1_16_w2_1_loop:
beq a14, a5, tie728_s8_less_w1_16_w2_1_end
ee.vld.128.ip q0, a3, 16
ee.vcmp.lt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_less_w1_16_w2_1_loop
tie728_s8_less_w1_16_w2_1_end:
retw
#void dl_tie728_s8_less_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 4
.text
.global dl_tie728_s8_less_w1_1_w2_16
.type dl_tie728_s8_less_w1_1_w2_16, @function
#.section .iram1
dl_tie728_s8_less_w1_1_w2_16:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args / length
# a6: tmp value
# a7:
# a8:
# a9:
# a10:
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a6, a5, 100
ee.vldbc.8.ip q7, a6, 0
l32i a6, a5, 44
srai a5, a6, 4
ee.vldbc.8.ip q0, a3, 0 // input0 broadcast
movi a14, 0
tie728_s8_less_w1_1_w2_16_loop:
beq a14, a5, tie728_s8_less_w1_1_w2_16_end
ee.vld.128.ip q1, a4, 16
ee.vcmp.lt.s8 q2, q0, q1
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
addi a14, a14, 1
j tie728_s8_less_w1_1_w2_16_loop
tie728_s8_less_w1_1_w2_16_end:
retw
.align 4
.text
.global dl_tie728_s8_less_w1_16_w2_16_unaligned
.type dl_tie728_s8_less_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_less_w1_16_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9:
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.ld.128.usar.ip q0, a3, 16
ee.ld.128.usar.ip q3, a4, 16
bltz a6, dl_tie728_s8_less_w1_16_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_less_w1_16_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_less_w1_16_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_less_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_less_w1_16_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_less_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_less_w1_16_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.ld.128.usar.ip q4, a4, 16
ee.src.q.qup q5, q3, q4
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_less_w1_16_w2_16_unaligned_remainder
dl_tie728_s8_less_w1_16_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_less_w1_16_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.ld.128.usar.xp q4, a4, a10
ee.src.q q5, q3, q4
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_less_w1_16_w2_16_unaligned_end:
addi a3, a3, -16
addi a4, a4, -16
retw
.align 4
.text
.global dl_tie728_s8_less_w1_16_w2_1_unaligned
.type dl_tie728_s8_less_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_tie728_s8_less_w1_16_w2_1_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr broadcast
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // get output_ptr sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a4, 0 // input1 broadcast
ee.ld.128.usar.ip q0, a3, 16
bltz a6, dl_tie728_s8_less_w1_16_w2_1_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a3, 16
beqz a7, dl_tie728_s8_less_w1_16_w2_1_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_less_w1_16_w2_1_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_less_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_tie728_s8_less_w1_16_w2_1_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_less_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_tie728_s8_less_w1_16_w2_1_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a3, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_less_w1_16_w2_1_unaligned_remainder
dl_tie728_s8_less_w1_16_w2_1_unaligned_remainder:
beqz a10, dl_tie728_s8_less_w1_16_w2_1_unaligned_end
ee.ld.128.usar.xp q1, a3, a10
ee.src.q q2, q0, q1
ee.vcmp.lt.s8 q2, q2, q5
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_less_w1_16_w2_1_unaligned_end:
addi a3, a3, -16
retw
.align 4
.text
.global dl_tie728_s8_less_w1_1_w2_16_unaligned
.type dl_tie728_s8_less_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_tie728_s8_less_w1_1_w2_16_unaligned:
# a2: bool *output_ptr
# a3: int8_t *input0_ptr broadcast
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: output sar_byte / tmp value
# a8: tmp value
# a9: tmp value
# a10: c_remainder
# a11:
# a12:
# a13:
# a14:
# a15:
entry sp, 128
addi a8, a5, 100
ee.vldbc.8.ip q7, a8, 0
l32i a6, a5, 64
l32i a10, a5, 76
// input0 exp = input1 exp = output exp
ee.ld.128.usar.ip q5, a2, 0 // output sar_byte
rur.sar_byte a7
ee.vldbc.8.ip q5, a3, 0 // input0 broadcast
ee.ld.128.usar.ip q0, a4, 16
bltz a6, dl_tie728_s8_less_w1_1_w2_16_unaligned_remainder // channel < 16
ee.ld.128.usar.ip q1, a4, 16
beqz a7, dl_tie728_s8_less_w1_1_w2_16_unaligned_128b
movi a14, 8
beq a7, a14, dl_tie728_s8_less_w1_1_w2_16_unaligned_64b
mov a14, a6
beqz a14, 1f
0:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store0 q2, a2, a7
addi a14, a14, -1
bgei a14, 1, 0b
1:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store0 q2, a2, a7
j dl_tie728_s8_less_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_tie728_s8_less_w1_1_w2_16_unaligned_128b:
mov a14, a6
beqz a14, 3f
2:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
ee.vst.128.ip q2, a2, 16
addi a14, a14, -1
bgei a14, 1, 2b
3:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.vst.128.ip q2, a2, 16
j dl_tie728_s8_less_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_tie728_s8_less_w1_1_w2_16_unaligned_64b:
mov a14, a6
beqz a14, 5f
4:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q5, q2
ee.andq q2, q2, q7
ee.ld.128.usar.ip q1, a4, 16
dl_tie728_s8_unaligned_store1 q2, a2
addi a14, a14, -1
bgei a14, 1, 4b
5:
ee.src.q.qup q2, q0, q1
ee.vcmp.lt.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_less_w1_1_w2_16_unaligned_remainder
dl_tie728_s8_less_w1_1_w2_16_unaligned_remainder:
beqz a10, dl_tie728_s8_less_w1_1_w2_16_unaligned_end
ee.ld.128.usar.xp q1, a4, a10
ee.src.q q2, q0, q1
ee.vcmp.lt.s8 q2, q5, q2
ee.andq q2, q2, q7
dl_tie728_s8_store_remainder q2, a9, a11, a7, a8, a2, a10
dl_tie728_s8_less_w1_1_w2_16_unaligned_end:
addi a4, a4, -16
retw
|
georgevio/IoT-Embedded
| 126,603
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s16_unaligned_conv2d.S
|
#include "dl_tie728_s16_unaligned.S"
#include "dl_tie728_s16.S"
############################################################################################################################################################
####
#### tie728_s16_unaligned_conv2d_11cn series
####
############################################################################################################################################################
.macro tie728_s16_unaligned_conv2d_11c8 input_v, input_front, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, c_remainder
# input_v: 8 input elements
# filter_v0: 8 filter elements
# filter_v1: 8 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 8 - 1
EE.LD.128.USAR.IP \input_front, \input_ptr, 16
blti \c_div_x_1, 0, 7f
EE.LD.128.USAR.IP \input_back, \input_ptr, 16
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
loopgtz \c_div_x_1, 8f
EE.SRC.Q.QUP \input_v, \input_front, \input_back
EE.LD.128.USAR.IP \input_back, \input_ptr, 16
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 3
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 4
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 5
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 6
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 7
8:
# last entire-128b
EE.SRC.Q.QUP \input_v, \input_front, \input_back
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 3
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 4
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 5
EE.VSMULAS.S16.QACC \filter_v0, \input_v, 6
EE.VSMULAS.S16.QACC \filter_v1, \input_v, 7
beqz \c_remainder, 0f # jump to c_remainder == 0
7:
# c_remainder
EE.LD.128.USAR.XP \input_back, \input_ptr, \c_remainder
EE.SRC.Q.QUP \input_v, \input_front, \input_back
EE.VLD.128.IP \filter_v0, \filter_ptr, 16
bbci \c_remainder, 3, 3f
# remainder == 0x1__0
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
bbci \c_remainder, 2, 5f
# remainder == 0x11_0
bbci \c_remainder, 1, 6f
# remainder == 0x1110, 7
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 3
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 4
EE.VSMULAS.S16.QACC \filter_v1, \input_v, 5
EE.VSMULAS.S16.QACC \filter_v0, \input_v, 6
j 0f
6: # remainder == 0x1100, 6
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 3
EE.VSMULAS.S16.QACC \filter_v0, \input_v, 4
EE.VSMULAS.S16.QACC \filter_v1, \input_v, 5
j 0f
5: # remainder == 0x10_0
bbci \c_remainder, 1, 4f
# remainder == 0x1010, 5
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
EE.VSMULAS.S16.QACC \filter_v1, \input_v, 3
EE.VSMULAS.S16.QACC \filter_v0, \input_v, 4
j 0f
4: # remainder == 0x1000, 4
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
EE.VSMULAS.S16.QACC.LD.INCP \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
EE.VSMULAS.S16.QACC \filter_v0, \input_v, 2
EE.VSMULAS.S16.QACC \filter_v1, \input_v, 3
j 0f
3: # remainder == 0x0__0
bbci \c_remainder, 2, 1f
# remainder == 0x01_0
EE.VLD.128.IP \filter_v1, \filter_ptr, 16
bbci \c_remainder, 1, 2f
# remainder == 0x0110, 3
EE.VSMULAS.S16.QACC.LD.INCP \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
EE.VSMULAS.S16.QACC \filter_v1, \input_v, 1
EE.VSMULAS.S16.QACC \filter_v0, \input_v, 2
j 0f
2: # remainder == 0x0100, 2
EE.VSMULAS.S16.QACC \filter_v0, \input_v, 0
EE.VSMULAS.S16.QACC \filter_v1, \input_v, 1
j 0f
1: # remainder == 0x0010, 1
EE.VSMULAS.S16.QACC \filter_v0, \input_v, 0
0:
addi \input_ptr, \input_ptr, -16
.endm
.macro tie728_s16_unaligned_conv2d_11c1 input_v, input_front, input_back, filter_v, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, temp, zero
# input_v: 8 input elements
# filter_v: 8 filter elements
# filter_v1: 8 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 8 - 1
EE.LD.128.USAR.IP \input_front, \input_ptr, 16
EE.LD.128.USAR.IP \filter_front, \filter_ptr, 16
blti \c_div_x_1, 0, 7f # input_channel < 8
EE.LD.128.USAR.IP \input_back, \input_ptr, 16
loopgtz \c_div_x_1, 8f
EE.SRC.Q.QUP \input_v, \input_front, \input_back
EE.LD.128.USAR.IP \filter_back, \filter_ptr, 16
EE.SRC.Q.QUP \filter_v, \filter_front, \filter_back
EE.LD.128.USAR.IP \input_back, \input_ptr, 16
EE.VMULAS.S16.ACCX \filter_v, \input_v
8:
# last entire-128b
EE.SRC.Q.QUP \input_v, \input_front, \input_back
EE.LD.128.USAR.IP \filter_back, \filter_ptr, 16
EE.SRC.Q.QUP \filter_v, \filter_front, \filter_back
EE.VMULAS.S16.ACCX \filter_v, \input_v
beqz \c_remainder, 0f
7:
# c_remainder > 0
EE.LD.128.USAR.XP \input_back, \input_ptr, \c_remainder
EE.SRC.Q.QUP \input_v, \input_front, \input_back
EE.LD.128.USAR.XP \filter_back, \filter_ptr, \c_remainder
EE.SRC.Q.QUP \filter_v, \filter_front, \filter_back
EE.SLCXXP.2Q \input_back, \input_v, \temp, \zero
EE.SLCXXP.2Q \filter_back, \filter_v, \temp, \zero
EE.VMULAS.S16.ACCX \filter_v, \input_v
0:
addi \input_ptr, \input_ptr, -16
addi \filter_ptr, \filter_ptr, -16
.endm
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_11cn
.type dl_tie728_s16_unaligned_conv2d_11cn, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_11cn:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 64 # a8: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a9, a4, 96 # a9: n_div_x = output_channel / (vector_width / element_width)
blti a9, 1, tie728_s16_unaligned_conv2d_11cn_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_11cn_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_11cn_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_11cn_64b
tie728_s16_unaligned_conv2d_11cn_32b:
tie728_s16_unaligned_conv2d_11cn_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_32b_aligned_vector_store q0, a2, a15
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_32b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_n_remainder
tie728_s16_unaligned_conv2d_11cn_64b:
tie728_s16_unaligned_conv2d_11cn_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_64b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_64b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_n_remainder
tie728_s16_unaligned_conv2d_11cn_128b:
tie728_s16_unaligned_conv2d_11cn_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_128b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_128b_multiple_loop
tie728_s16_unaligned_conv2d_11cn_n_remainder:
l32i a9, a4, 140 # a9: n_remainder
beqz a9, tie728_s16_unaligned_conv2d_11cn_n_remainder_end
movi a10, 15
sub a10, a10, a7 # a10: 15 - c_remainder
movi a11, 0 # a11: activation_shift = zero
tie728_s16_unaligned_conv2d_11cn_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a10, a11
tie728_s16_element_round_result a14, a8, a15, q0
tie728_s16_element_store a2, a14
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_n_remainder_loop
tie728_s16_unaligned_conv2d_11cn_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_11cn_relu
.type dl_tie728_s16_unaligned_conv2d_11cn_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_11cn_relu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 64 # a8: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a9, a4, 96 # a9: n_div_x = output_channel / (vector_width / element_width)
movi a10, 0 # a10: activation_alpha = zero
movi a11, 0 # a11: activation_shift = zero
blti a9, 1, tie728_s16_unaligned_conv2d_11cn_relu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_11cn_relu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_11cn_relu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_11cn_relu_64b
tie728_s16_unaligned_conv2d_11cn_relu_32b:
tie728_s16_unaligned_conv2d_11cn_relu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a10, a11
tie728_32b_aligned_vector_store q0, a2, a15
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_relu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_relu_n_remainder
tie728_s16_unaligned_conv2d_11cn_relu_64b:
tie728_s16_unaligned_conv2d_11cn_relu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a10, a11
tie728_64b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_relu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_relu_n_remainder
tie728_s16_unaligned_conv2d_11cn_relu_128b:
tie728_s16_unaligned_conv2d_11cn_relu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a10, a11
tie728_128b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_relu_128b_multiple_loop
tie728_s16_unaligned_conv2d_11cn_relu_n_remainder:
l32i a9, a4, 140 # a9: n_remainder
beqz a9, tie728_s16_unaligned_conv2d_11cn_relu_n_remainder_end
movi a10, 15
sub a10, a10, a7 # a10: 15 - c_remainder
tie728_s16_unaligned_conv2d_11cn_relu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a10, a11
tie728_s16_element_round_result a14, a8, a15, q0
tie728_s16_element_relu a14
tie728_s16_element_store a2, a14
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_relu_n_remainder_loop
tie728_s16_unaligned_conv2d_11cn_relu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_11cn_leakyrelu
.type dl_tie728_s16_unaligned_conv2d_11cn_leakyrelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_11cn_leakyrelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 64 # a8: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a9, a4, 96 # a9: n_div_x = output_channel / (vector_width / element_width)
l32i a10, a4, 76 # a10: activation_alpha
l32i a11, a4, 84 # a11: activation_shift
blti a9, 1, tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_11cn_leakyrelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_11cn_leakyrelu_64b
tie728_s16_unaligned_conv2d_11cn_leakyrelu_32b:
tie728_s16_unaligned_conv2d_11cn_leakyrelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a10, a11
tie728_32b_aligned_vector_store q0, a2, a15
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_leakyrelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_11cn_leakyrelu_64b:
tie728_s16_unaligned_conv2d_11cn_leakyrelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a10, a11
tie728_64b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_leakyrelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_11cn_leakyrelu_128b:
tie728_s16_unaligned_conv2d_11cn_leakyrelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a10, a11
tie728_128b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_leakyrelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_remainder:
l32i a9, a4, 140 # a9: n_remainder
beqz a9, tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_remainder_end
ssr a11 # ssr: activation_shift
movi a11, 15
sub a11, a11, a7 # a11: 15 - c_remainder
movi a12, 0 # a12: zero
tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a11, a12
tie728_s16_element_round_result a14, a8, a15, q0
tie728_s16_element_leakyrelu a14, a10
tie728_s16_element_store a2, a14
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_remainder_loop
tie728_s16_unaligned_conv2d_11cn_leakyrelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_11cn_prelu
.type dl_tie728_s16_unaligned_conv2d_11cn_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_11cn_prelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 64 # a8: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a9, a4, 96 # a9: n_div_x = output_channel / (vector_width / element_width)
l32i a10, a4, 80 # a10: activation_alpha_ptr
l32i a11, a4, 84 # a11: activation_shift
blti a9, 1, tie728_s16_unaligned_conv2d_11cn_prelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_11cn_prelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_11cn_prelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_11cn_prelu_64b
tie728_s16_unaligned_conv2d_11cn_prelu_32b:
tie728_s16_unaligned_conv2d_11cn_prelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_prelu q0, q1, a10, a11
tie728_32b_aligned_vector_store q0, a2, a15
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_prelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_prelu_n_remainder
tie728_s16_unaligned_conv2d_11cn_prelu_64b:
tie728_s16_unaligned_conv2d_11cn_prelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_prelu q0, q1, a10, a11
tie728_64b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_prelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_prelu_n_remainder
tie728_s16_unaligned_conv2d_11cn_prelu_128b:
tie728_s16_unaligned_conv2d_11cn_prelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_prelu q0, q1, a10, a11
tie728_128b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_prelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_11cn_prelu_n_remainder:
l32i a9, a4, 140 # a9: n_remainder
beqz a9, tie728_s16_unaligned_conv2d_11cn_prelu_n_remainder_end
ssr a11 # ssr: activation_shift
movi a11, 15
sub a11, a11, a7 # a11: 15 - c_remainder
movi a12, 0 # a12: zero
tie728_s16_unaligned_conv2d_11cn_prelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a11, a12
tie728_s16_element_round_result a14, a8, a15, q0
tie728_s16_element_prelu a14, a10, a15
tie728_s16_element_store a2, a14
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_prelu_n_remainder_loop
tie728_s16_unaligned_conv2d_11cn_prelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_11cn_bias
.type dl_tie728_s16_unaligned_conv2d_11cn_bias, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_11cn_bias:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 64 # a8: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a9, a4, 96 # a9: n_div_x = output_channel / (vector_width / element_width)
l32i a10, a4, 68 # a10: bias_ptr
blti a9, 1, tie728_s16_unaligned_conv2d_11cn_bias_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_11cn_bias_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_11cn_bias_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_11cn_bias_64b
tie728_s16_unaligned_conv2d_11cn_bias_32b:
tie728_s16_unaligned_conv2d_11cn_bias_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_32b_aligned_vector_store q0, a2, a15
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_32b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_bias_n_remainder
tie728_s16_unaligned_conv2d_11cn_bias_64b:
tie728_s16_unaligned_conv2d_11cn_bias_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_64b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_64b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_bias_n_remainder
tie728_s16_unaligned_conv2d_11cn_bias_128b:
tie728_s16_unaligned_conv2d_11cn_bias_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_128b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_128b_multiple_loop
tie728_s16_unaligned_conv2d_11cn_bias_n_remainder:
l32i a9, a4, 140 # a9: n_remainder
beqz a9, tie728_s16_unaligned_conv2d_11cn_bias_n_remainder_end
movi a11, 15
sub a11, a11, a7 # a11: 15 - c_remainder
movi a12, 0 # a12: zero
tie728_s16_unaligned_conv2d_11cn_bias_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_conv2d_element_bias a10
tie728_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a11, a12
tie728_s16_element_round_result a14, a8, a15, q0
tie728_s16_element_store a2, a14
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_n_remainder_loop
tie728_s16_unaligned_conv2d_11cn_bias_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_11cn_bias_relu
.type dl_tie728_s16_unaligned_conv2d_11cn_bias_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_11cn_bias_relu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 64 # a8: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a9, a4, 96 # a9: n_div_x = output_channel / (vector_width / element_width)
l32i a10, a4, 68 # a10: bias_ptr
movi a11, 0 # a11: activation_alpha = zero
movi a12, 0 # a12: activation_shift = zero
blti a9, 1, tie728_s16_unaligned_conv2d_11cn_bias_relu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_11cn_bias_relu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_11cn_bias_relu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_11cn_bias_relu_64b
tie728_s16_unaligned_conv2d_11cn_bias_relu_32b:
tie728_s16_unaligned_conv2d_11cn_bias_relu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a11, a12
tie728_32b_aligned_vector_store q0, a2, a15
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_relu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_bias_relu_n_remainder
tie728_s16_unaligned_conv2d_11cn_bias_relu_64b:
tie728_s16_unaligned_conv2d_11cn_bias_relu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a11, a12
tie728_64b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_relu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_bias_relu_n_remainder
tie728_s16_unaligned_conv2d_11cn_bias_relu_128b:
tie728_s16_unaligned_conv2d_11cn_bias_relu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a11, a12
tie728_128b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_relu_128b_multiple_loop
tie728_s16_unaligned_conv2d_11cn_bias_relu_n_remainder:
l32i a9, a4, 140 # a9: n_remainder
beqz a9, tie728_s16_unaligned_conv2d_11cn_bias_relu_n_remainder_end
movi a11, 15
sub a11, a11, a7 # a11: 15 - c_remainder
tie728_s16_unaligned_conv2d_11cn_bias_relu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_conv2d_element_bias a10
tie728_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a11, a12
tie728_s16_element_round_result a14, a8, a15, q0
tie728_s16_element_relu a14
tie728_s16_element_store a2, a14
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_relu_n_remainder_loop
tie728_s16_unaligned_conv2d_11cn_bias_relu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu
.type dl_tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 64 # a8: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a9, a4, 96 # a9: n_div_x = output_channel / (vector_width / element_width)
l32i a10, a4, 68 # a10: bias_ptr
l32i a11, a4, 76 # a11: activation_alpha
l32i a12, a4, 84 # a12: activation_shift
blti a9, 1, tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_64b
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_32b:
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a11, a12
tie728_32b_aligned_vector_store q0, a2, a15
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_64b:
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a11, a12
tie728_64b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_128b:
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_relu q0, a11, a12
tie728_128b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder:
l32i a9, a4, 140 # a9: n_remainder
beqz a9, tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder_end
ssr a12 # ssr: activation_shift
movi a12, 15
sub a12, a12, a7 # a12: 15 - c_remainder
movi a13, 0 # a13: zero
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_conv2d_element_bias a10
tie728_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a12, a13
tie728_s16_element_round_result a14, a8, a15, q0
tie728_s16_element_leakyrelu a14, a11
tie728_s16_element_store a2, a14
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder_loop
tie728_s16_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_11cn_bias_prelu
.type dl_tie728_s16_unaligned_conv2d_11cn_bias_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_11cn_bias_prelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 64 # a8: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a9, a4, 96 # a9: n_div_x = output_channel / (vector_width / element_width)
l32i a10, a4, 68 # a10: bias_ptr
l32i a11, a4, 80 # a11: activation_alpha_ptr
l32i a12, a4, 84 # a12: activation_shift
blti a9, 1, tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_11cn_bias_prelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_11cn_bias_prelu_64b
tie728_s16_unaligned_conv2d_11cn_bias_prelu_32b:
tie728_s16_unaligned_conv2d_11cn_bias_prelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_prelu q0, q1, a11, a12
tie728_32b_aligned_vector_store q0, a2, a15
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_prelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_remainder
tie728_s16_unaligned_conv2d_11cn_bias_prelu_64b:
tie728_s16_unaligned_conv2d_11cn_bias_prelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_prelu q0, q1, a11, a12
tie728_64b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_prelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_remainder
tie728_s16_unaligned_conv2d_11cn_bias_prelu_128b:
tie728_s16_unaligned_conv2d_11cn_bias_prelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a10
tie728_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, a15, a5, a6, a7
tie728_s16_vector_round_result q0, a8, a15, q1
tie728_s16_conv2d_prelu q0, q1, a11, a12
tie728_128b_aligned_vector_store q0, a2
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_prelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_remainder:
l32i a9, a4, 140 # a9: n_remainder
beqz a9, tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_remainder_end
ssr a12 # ssr: activation_shift
movi a12, 15
sub a12, a12, a7 # a12: 15 - c_remainder
movi a13, 0 # a13: zero
tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_conv2d_element_bias a10
tie728_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a12, a13
tie728_s16_element_round_result a14, a8, a15, q0
tie728_s16_element_prelu a14, a11, a15
tie728_s16_element_store a2, a14
addi a9, a9, -1
bnez a9, tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_remainder_loop
tie728_s16_unaligned_conv2d_11cn_bias_prelu_n_remainder_end:
retw
############################################################################################################################################################
####
#### tie728_s16_unaligned_conv2d_33cn series
####
############################################################################################################################################################
.macro tie728_s16_unaligned_conv2d_33c8 input_v0, input_front, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro tie728_s16_unaligned_conv2d_33c1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, temp, zero
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_y_offset
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_33cn
.type dl_tie728_s16_unaligned_conv2d_33cn, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_33cn:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 96 # a11: n_div_x = output_channel / (vector_width / element_width)
blti a11, 1, tie728_s16_unaligned_conv2d_33cn_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_33cn_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_33cn_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_33cn_64b
tie728_s16_unaligned_conv2d_33cn_32b:
tie728_s16_unaligned_conv2d_33cn_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_32b_aligned_vector_store q0, a2, a15
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_32b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_n_remainder
tie728_s16_unaligned_conv2d_33cn_64b:
tie728_s16_unaligned_conv2d_33cn_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_64b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_64b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_n_remainder
tie728_s16_unaligned_conv2d_33cn_128b:
tie728_s16_unaligned_conv2d_33cn_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_128b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_128b_multiple_loop
tie728_s16_unaligned_conv2d_33cn_n_remainder:
l32i a11, a4, 140 # a11: n_remainder
beqz a11, tie728_s16_unaligned_conv2d_33cn_n_remainder_end
movi a12, 15
sub a12, a12, a7 # a12: 15 - c_remainder
movi a13, 0 # a13: activation_shift = zero
tie728_s16_unaligned_conv2d_33cn_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a12, a13
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_store a2, a14
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_n_remainder_loop
tie728_s16_unaligned_conv2d_33cn_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_33cn_relu
.type dl_tie728_s16_unaligned_conv2d_33cn_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_33cn_relu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 96 # a11: n_div_x = output_channel / (vector_width / element_width)
movi a12, 0 # a12: activation_alpha = zero
movi a13, 0 # a13: activation_shift = zero
blti a11, 1, tie728_s16_unaligned_conv2d_33cn_relu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_33cn_relu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_33cn_relu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_33cn_relu_64b
tie728_s16_unaligned_conv2d_33cn_relu_32b:
tie728_s16_unaligned_conv2d_33cn_relu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a12, a13
tie728_32b_aligned_vector_store q0, a2, a15
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_relu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_relu_n_remainder
tie728_s16_unaligned_conv2d_33cn_relu_64b:
tie728_s16_unaligned_conv2d_33cn_relu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a12, a13
tie728_64b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_relu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_relu_n_remainder
tie728_s16_unaligned_conv2d_33cn_relu_128b:
tie728_s16_unaligned_conv2d_33cn_relu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a12, a13
tie728_128b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_relu_128b_multiple_loop
tie728_s16_unaligned_conv2d_33cn_relu_n_remainder:
l32i a11, a4, 140 # a11: n_remainder
beqz a11, tie728_s16_unaligned_conv2d_33cn_relu_n_remainder_end
movi a12, 15
sub a12, a12, a7 # a12: 15 - c_remainder
tie728_s16_unaligned_conv2d_33cn_relu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a12, a13
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_relu a14
tie728_s16_element_store a2, a14
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_relu_n_remainder_loop
tie728_s16_unaligned_conv2d_33cn_relu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_33cn_leakyrelu
.type dl_tie728_s16_unaligned_conv2d_33cn_leakyrelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_33cn_leakyrelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 96 # a11: n_div_x = output_channel / (vector_width / element_width)
l32i a12, a4, 76 # a12: activation_alpha
l32i a13, a4, 84 # a13: activation_shift
blti a11, 1, tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_33cn_leakyrelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_33cn_leakyrelu_64b
tie728_s16_unaligned_conv2d_33cn_leakyrelu_32b:
tie728_s16_unaligned_conv2d_33cn_leakyrelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a12, a13
tie728_32b_aligned_vector_store q0, a2, a15
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_leakyrelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_33cn_leakyrelu_64b:
tie728_s16_unaligned_conv2d_33cn_leakyrelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a12, a13
tie728_64b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_leakyrelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_33cn_leakyrelu_128b:
tie728_s16_unaligned_conv2d_33cn_leakyrelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a12, a13
tie728_128b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_leakyrelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_remainder:
l32i a11, a4, 140 # a11: n_remainder
beqz a11, tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_remainder_end
ssr a13 # ssr: activation_shift
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
# movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
movi a14, 0 # a14: zero
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a13, a14
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_leakyrelu a14, a12
tie728_s16_element_store a2, a14
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_remainder_loop
tie728_s16_unaligned_conv2d_33cn_leakyrelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_33cn_prelu
.type dl_tie728_s16_unaligned_conv2d_33cn_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_33cn_prelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 96 # a11: n_div_x = output_channel / (vector_width / element_width)
l32i a12, a4, 80 # a12: activation_alpha_ptr
l32i a13, a4, 84 # a13: activation_shift
blti a11, 1, tie728_s16_unaligned_conv2d_33cn_prelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_33cn_prelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_33cn_prelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_33cn_prelu_64b
tie728_s16_unaligned_conv2d_33cn_prelu_32b:
tie728_s16_unaligned_conv2d_33cn_prelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a12, a13
tie728_32b_aligned_vector_store q0, a2, a15
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_prelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_prelu_n_remainder
tie728_s16_unaligned_conv2d_33cn_prelu_64b:
tie728_s16_unaligned_conv2d_33cn_prelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a12, a13
tie728_64b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_prelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_prelu_n_remainder
tie728_s16_unaligned_conv2d_33cn_prelu_128b:
tie728_s16_unaligned_conv2d_33cn_prelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a12, a13
tie728_128b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_prelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_33cn_prelu_n_remainder:
l32i a11, a4, 140 # a11: n_remainder
beqz a11, tie728_s16_unaligned_conv2d_33cn_prelu_n_remainder_end
ssr a13 # ssr: activation_shift
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
tie728_s16_unaligned_conv2d_33cn_prelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a13, a14
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_prelu a14, a12, a15
tie728_s16_element_store a2, a14
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_prelu_n_remainder_loop
tie728_s16_unaligned_conv2d_33cn_prelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_33cn_bias
.type dl_tie728_s16_unaligned_conv2d_33cn_bias, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_33cn_bias:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 96 # a11: n_div_x = output_channel / (vector_width / element_width)
l32i a12, a4, 68 # a12: bias_ptr
blti a11, 1, tie728_s16_unaligned_conv2d_33cn_bias_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_33cn_bias_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_33cn_bias_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_33cn_bias_64b
tie728_s16_unaligned_conv2d_33cn_bias_32b:
tie728_s16_unaligned_conv2d_33cn_bias_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_32b_aligned_vector_store q0, a2, a15
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_32b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_bias_n_remainder
tie728_s16_unaligned_conv2d_33cn_bias_64b:
tie728_s16_unaligned_conv2d_33cn_bias_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_64b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_64b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_bias_n_remainder
tie728_s16_unaligned_conv2d_33cn_bias_128b:
tie728_s16_unaligned_conv2d_33cn_bias_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_128b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_128b_multiple_loop
tie728_s16_unaligned_conv2d_33cn_bias_n_remainder:
l32i a11, a4, 140 # a11: n_remainder
beqz a11, tie728_s16_unaligned_conv2d_33cn_bias_n_remainder_end
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
tie728_s16_unaligned_conv2d_33cn_bias_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_conv2d_element_bias a12
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a13, a14
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_store a2, a14
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_n_remainder_loop
tie728_s16_unaligned_conv2d_33cn_bias_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_33cn_bias_relu
.type dl_tie728_s16_unaligned_conv2d_33cn_bias_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_33cn_bias_relu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 96 # a11: n_div_x = output_channel / (vector_width / element_width)
l32i a12, a4, 68 # a12: bias_ptr
movi a13, 0 # a13: activation_alpha = zero
movi a14, 0 # a14: activation_shift = zero
blti a11, 1, tie728_s16_unaligned_conv2d_33cn_bias_relu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_33cn_bias_relu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_33cn_bias_relu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_33cn_bias_relu_64b
tie728_s16_unaligned_conv2d_33cn_bias_relu_32b:
tie728_s16_unaligned_conv2d_33cn_bias_relu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_32b_aligned_vector_store q0, a2, a15
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_relu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_bias_relu_n_remainder
tie728_s16_unaligned_conv2d_33cn_bias_relu_64b:
tie728_s16_unaligned_conv2d_33cn_bias_relu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_64b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_relu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_bias_relu_n_remainder
tie728_s16_unaligned_conv2d_33cn_bias_relu_128b:
tie728_s16_unaligned_conv2d_33cn_bias_relu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_128b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_relu_128b_multiple_loop
tie728_s16_unaligned_conv2d_33cn_bias_relu_n_remainder:
l32i a11, a4, 140 # a11: n_remainder
beqz a11, tie728_s16_unaligned_conv2d_33cn_bias_relu_n_remainder_end
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
tie728_s16_unaligned_conv2d_33cn_bias_relu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_conv2d_element_bias a12
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a13, a14
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_relu a14
tie728_s16_element_store a2, a14
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_relu_n_remainder_loop
tie728_s16_unaligned_conv2d_33cn_bias_relu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu
.type dl_tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 96 # a11: n_div_x = output_channel / (vector_width / element_width)
l32i a12, a4, 68 # a12: bias_ptr
l32i a13, a4, 76 # a13: activation_alpha
l32i a14, a4, 84 # a14: activation_shift
blti a11, 1, tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_64b
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_32b:
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_32b_aligned_vector_store q0, a2, a15
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_64b:
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_64b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_128b:
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_128b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder:
l32i a11, a4, 140 # a11: n_remainder
beqz a11, tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder_end
movi a10, 15
sub a10, a10, a7 # a10: 15 - c_remainder
ssr a14 # ssr: activation_shift
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_conv2d_element_bias a12
l32i a9, a4, 112 # a9: dilation_y_offset
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a14
l32i a9, a4, 64 # a9: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_element_round_result a14, a9, a15, q0
tie728_s16_element_leakyrelu a14, a13
tie728_s16_element_store a2, a14
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder_loop
tie728_s16_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_33cn_bias_prelu
.type dl_tie728_s16_unaligned_conv2d_33cn_bias_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_33cn_bias_prelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args, 15 - input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 96 # a11: n_div_x = output_channel / (vector_width / element_width)
l32i a12, a4, 68 # a12: bias_ptr
l32i a13, a4, 80 # a13: activation_alpha_ptr
l32i a14, a4, 84 # a14: activation_shift
blti a11, 1, tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_33cn_bias_prelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_33cn_bias_prelu_64b
tie728_s16_unaligned_conv2d_33cn_bias_prelu_32b:
tie728_s16_unaligned_conv2d_33cn_bias_prelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a13, a14
tie728_32b_aligned_vector_store q0, a2, a15
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_prelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_remainder
tie728_s16_unaligned_conv2d_33cn_bias_prelu_64b:
tie728_s16_unaligned_conv2d_33cn_bias_prelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a13, a14
tie728_64b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_prelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_remainder
tie728_s16_unaligned_conv2d_33cn_bias_prelu_128b:
tie728_s16_unaligned_conv2d_33cn_bias_prelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a12
tie728_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a13, a14
tie728_128b_aligned_vector_store q0, a2
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_prelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_remainder:
l32i a11, a4, 140 # a11: n_remainder
beqz a11, tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_remainder_end
movi a10, 15
sub a10, a10, a7 # a10: 15 - c_remainder
ssr a14 # ssr: activation_shift
tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
tie728_s16_conv2d_element_bias a12
l32i a9, a4, 112 # a9: dilation_y_offset
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a14
l32i a9, a4, 64 # a9: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_element_round_result a14, a9, a15, q0
tie728_s16_element_prelu a14, a13, a15
tie728_s16_element_store a2, a14
addi a11, a11, -1
bnez a11, tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_remainder_loop
tie728_s16_unaligned_conv2d_33cn_bias_prelu_n_remainder_end:
retw
############################################################################################################################################################
####
#### tie728_s16_unaligned_conv2d_hwcn series
####
############################################################################################################################################################
.macro tie728_s16_unaligned_conv2d_hwc8 input_v0, input_front, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, filter_h, filter_w, args, filter_offset_q
l32i \filter_h, \args, 52 # filter_height
10:
l32i \filter_w, \args, 56 # filter_width
beqi \filter_w, 1, 11f
9:
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bgei \filter_w, 2, 9b
11:
tie728_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
add \filter_ptr, \filter_ptr, \filter_w
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 10b
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.macro tie728_s16_unaligned_conv2d_hwc1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, filter_h, filter_w, args, temp, zero, filter_offset_q
l32i \filter_h, \args, 52 # filter_height
10:
l32i \filter_w, \args, 56 # filter_width
beqi \filter_w, 1, 11f
9:
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bgei \filter_w, 2, 9b
11:
tie728_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
EE.MOVI.32.A \filter_offset_q, \filter_w, 1
add \filter_ptr, \filter_ptr, \filter_w
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 10b
EE.MOVI.32.A \filter_offset_q, \filter_h, 2
add \filter_ptr, \filter_ptr, \filter_h
.endm
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_hwcn
.type dl_tie728_s16_unaligned_conv2d_hwcn, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_hwcn:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a12, a4, 96 # a12: n_div_x = output_channel / (vector_width / element_width)
l32i a13, a4, 64 # a13: mac_shift = output.exponent - filter.exponent - input.exponent
blti a12, 1, tie728_s16_unaligned_conv2d_hwcn_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_hwcn_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_hwcn_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_hwcn_64b
tie728_s16_unaligned_conv2d_hwcn_32b:
tie728_s16_unaligned_conv2d_hwcn_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
tie728_s16_vector_round_result q0, a13, a15, q1
tie728_32b_aligned_vector_store q0, a2, a15
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_32b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_n_remainder
tie728_s16_unaligned_conv2d_hwcn_64b:
tie728_s16_unaligned_conv2d_hwcn_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
tie728_s16_vector_round_result q0, a13, a15, q1
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_64b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_n_remainder
tie728_s16_unaligned_conv2d_hwcn_128b:
tie728_s16_unaligned_conv2d_hwcn_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
tie728_s16_vector_round_result q0, a13, a15, q1
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_128b_multiple_loop
tie728_s16_unaligned_conv2d_hwcn_n_remainder:
l32i a12, a4, 140 # a12: n_remainder
beqz a12, tie728_s16_unaligned_conv2d_hwcn_n_remainder_end
l32i a5, a4, 160
l32i a15, a4, 164
EE.MOVI.32.Q q7, a5, 1
EE.MOVI.32.Q q7, a15, 2
l32i a5, a4, 168 # filter_ptr unaligned
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
# movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_hwcn_n_remainder_loop:
mov a15, a3 # a15: input_ptr
movi a14, 0 # a14: zero
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a11, a4, a13, a14, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_store a2, a14
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_n_remainder_loop
tie728_s16_unaligned_conv2d_hwcn_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_hwcn_relu
.type dl_tie728_s16_unaligned_conv2d_hwcn_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_hwcn_relu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a12, a4, 96 # a12: n_div_x = output_channel / (vector_width / element_width)
movi a13, 0 # a13: zero
movi a14, 0 # a14: zero
blti a12, 1, tie728_s16_unaligned_conv2d_hwcn_relu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_hwcn_relu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_hwcn_relu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_hwcn_relu_64b
tie728_s16_unaligned_conv2d_hwcn_relu_32b:
tie728_s16_unaligned_conv2d_hwcn_relu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_32b_aligned_vector_store q0, a2, a15
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_relu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_relu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_relu_64b:
tie728_s16_unaligned_conv2d_hwcn_relu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_relu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_relu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_relu_128b:
tie728_s16_unaligned_conv2d_hwcn_relu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_relu_128b_multiple_loop
tie728_s16_unaligned_conv2d_hwcn_relu_n_remainder:
l32i a12, a4, 140 # a12: n_remainder
beqz a12, tie728_s16_unaligned_conv2d_hwcn_relu_n_remainder_end
l32i a5, a4, 160
l32i a15, a4, 164
EE.MOVI.32.Q q7, a5, 1
EE.MOVI.32.Q q7, a15, 2
l32i a5, a4, 168 # filter_ptr unaligned
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
tie728_s16_unaligned_conv2d_hwcn_relu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
movi a14, 0 # a14: zero
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a11, a4, a13, a14, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_relu a14
tie728_s16_element_store a2, a14
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_relu_n_remainder_loop
tie728_s16_unaligned_conv2d_hwcn_relu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_hwcn_leakyrelu
.type dl_tie728_s16_unaligned_conv2d_hwcn_leakyrelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_hwcn_leakyrelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a12, a4, 96 # a12: n_div_x = output_channel / (vector_width / element_width)
l32i a13, a4, 76 # a13: activation_alpha
l32i a14, a4, 84 # a14: activation_shift
blti a12, 1, tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_hwcn_leakyrelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_hwcn_leakyrelu_64b
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_32b:
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_32b_aligned_vector_store q0, a2, a15
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_leakyrelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_64b:
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_leakyrelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_128b:
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a13, a14
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_leakyrelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_remainder:
l32i a12, a4, 140 # a12: n_remainder
beqz a12, tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_remainder_end
l32i a5, a4, 160
l32i a15, a4, 164
EE.MOVI.32.Q q7, a5, 1
EE.MOVI.32.Q q7, a15, 2
l32i a5, a4, 168 # filter_ptr unaligned
EE.MOVI.32.Q q6, a13, 0 # q6[0]: activation_alpha
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
ssr a14 # ssr: activation_shift
# movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
movi a14, 0 # a14: zero
EE.ZERO.ACCX
tie728_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a11, a4, a13, a14, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
EE.MOVI.32.A q6, a11, 0 # a11: activation_alpha
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_leakyrelu a14, a11
tie728_s16_element_store a2, a14
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_remainder_loop
tie728_s16_unaligned_conv2d_hwcn_leakyrelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_hwcn_prelu
.type dl_tie728_s16_unaligned_conv2d_hwcn_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_hwcn_prelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a12, a4, 96 # a12: n_div_x = output_channel / (vector_width / element_width)
l32i a13, a4, 80 # a13: activation_alpha_ptr
l32i a14, a4, 84 # a14: activation_shift
blti a12, 1, tie728_s16_unaligned_conv2d_hwcn_prelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_hwcn_prelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_hwcn_prelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_hwcn_prelu_64b
tie728_s16_unaligned_conv2d_hwcn_prelu_32b:
tie728_s16_unaligned_conv2d_hwcn_prelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a13, a14
tie728_32b_aligned_vector_store q0, a2, a15
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_prelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_prelu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_prelu_64b:
tie728_s16_unaligned_conv2d_hwcn_prelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a13, a14
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_prelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_prelu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_prelu_128b:
tie728_s16_unaligned_conv2d_hwcn_prelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a13, a14
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_prelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_hwcn_prelu_n_remainder:
l32i a12, a4, 140 # a12: n_remainder
beqz a12, tie728_s16_unaligned_conv2d_hwcn_prelu_n_remainder_end
l32i a5, a4, 160
l32i a15, a4, 164
EE.MOVI.32.Q q7, a5, 1
EE.MOVI.32.Q q7, a15, 2
l32i a5, a4, 168 # filter_ptr unaligned
EE.MOVI.32.Q q6, a13, 0 # q6[0]: activation_alpha_ptr
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
ssr a14 # ssr: activation_shift
tie728_s16_unaligned_conv2d_hwcn_prelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a11, a4, a13, a14, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
EE.MOVI.32.A q6, a11, 0 # a11: activation_alpha_ptr
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_prelu a14, a11, a15
tie728_s16_element_store a2, a14
EE.MOVI.32.Q q6, a11, 0 # q6[0]: activation_alpha_ptr
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_prelu_n_remainder_loop
tie728_s16_unaligned_conv2d_hwcn_prelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_hwcn_bias
.type dl_tie728_s16_unaligned_conv2d_hwcn_bias, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_hwcn_bias:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a12, a4, 96 # a12: n_div_x = output_channel / (vector_width / element_width)
l32i a13, a4, 68 # a13: bias_ptr
l32i a14, a4, 64 # a14: mac_shift = output.exponent - filter.exponent - input.exponent
blti a12, 1, tie728_s16_unaligned_conv2d_hwcn_bias_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_hwcn_bias_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_hwcn_bias_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_hwcn_bias_64b
tie728_s16_unaligned_conv2d_hwcn_bias_32b:
tie728_s16_unaligned_conv2d_hwcn_bias_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
tie728_s16_vector_round_result q0, a14, a15, q1
tie728_32b_aligned_vector_store q0, a2, a15
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_32b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_bias_n_remainder
tie728_s16_unaligned_conv2d_hwcn_bias_64b:
tie728_s16_unaligned_conv2d_hwcn_bias_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
tie728_s16_vector_round_result q0, a14, a15, q1
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_64b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_bias_n_remainder
tie728_s16_unaligned_conv2d_hwcn_bias_128b:
tie728_s16_unaligned_conv2d_hwcn_bias_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
tie728_s16_vector_round_result q0, a14, a15, q1
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_128b_multiple_loop
tie728_s16_unaligned_conv2d_hwcn_bias_n_remainder:
l32i a12, a4, 140 # a12: n_remainder
beqz a12, tie728_s16_unaligned_conv2d_hwcn_bias_n_remainder_end
l32i a5, a4, 160
l32i a15, a4, 164
EE.MOVI.32.Q q7, a5, 1
EE.MOVI.32.Q q7, a15, 2
l32i a5, a4, 168 # filter_ptr unaligned
EE.MOVI.32.Q q6, a13, 1 # q6[1]: bias_ptr
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
l32i a15, a4, 84
ssr a15 # ssr: activation_shift
tie728_s16_unaligned_conv2d_hwcn_bias_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
EE.MOVI.32.A q6, a14, 1 # a14: bias_ptr
tie728_s16_conv2d_element_bias a14
EE.MOVI.32.Q q6, a14, 1 # q6[1]: bias_ptr
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a11, a4, a13, a14, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_store a2, a14
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_n_remainder_loop
tie728_s16_unaligned_conv2d_hwcn_bias_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_hwcn_bias_relu
.type dl_tie728_s16_unaligned_conv2d_hwcn_bias_relu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_hwcn_bias_relu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a12, a4, 96 # a12: n_div_x = output_channel / (vector_width / element_width)
l32i a13, a4, 68 # a13: bias_ptr
l32i a14, a4, 76 # a14: activation_alpha
blti a12, 1, tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_hwcn_bias_relu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_hwcn_bias_relu_64b
tie728_s16_unaligned_conv2d_hwcn_bias_relu_32b:
tie728_s16_unaligned_conv2d_hwcn_bias_relu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a14, a11
tie728_32b_aligned_vector_store q0, a2, a15
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_relu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_bias_relu_64b:
tie728_s16_unaligned_conv2d_hwcn_bias_relu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a14, a11
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_relu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_bias_relu_128b:
tie728_s16_unaligned_conv2d_hwcn_bias_relu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a14, a11
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_relu_128b_multiple_loop
tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder:
l32i a12, a4, 140 # a12: n_remainder
beqz a12, tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder_end
l32i a5, a4, 160
l32i a15, a4, 164
EE.MOVI.32.Q q7, a5, 1
EE.MOVI.32.Q q7, a15, 2
l32i a5, a4, 168 # filter_ptr unaligned
EE.MOVI.32.Q q6, a13, 1 # q6[1]: bias_ptr
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
l32i a15, a4, 84
ssr a15 # ssr: activation_shift
tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
EE.MOVI.32.A q6, a14, 1 # a14: bias_ptr
tie728_s16_conv2d_element_bias a14
EE.MOVI.32.Q q6, a14, 1 # q6[1]: bias_ptr
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a11, a4, a13, a14, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
tie728_s16_element_round_result a14, a10, a15, q0
tie728_s16_element_relu a14
tie728_s16_element_store a2, a14
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder_loop
tie728_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu
.type dl_tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a12, a4, 96 # a12: n_div_x = output_channel / (vector_width / element_width)
l32i a13, a4, 68 # a13: bias_ptr
l32i a14, a4, 76 # a14: activation_alpha
blti a12, 1, tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_64b
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_32b:
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a14, a11
tie728_32b_aligned_vector_store q0, a2, a15
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_64b:
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a14, a11
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_128b:
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_relu q0, a14, a11
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder:
l32i a12, a4, 140 # a12: n_remainder
beqz a12, tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder_end
l32i a5, a4, 160
l32i a15, a4, 164
EE.MOVI.32.Q q7, a5, 1
EE.MOVI.32.Q q7, a15, 2
l32i a5, a4, 168 # filter_ptr unaligned
EE.MOVI.32.Q q6, a13, 1 # q6[1]: bias_ptr
EE.MOVI.32.Q q6, a14, 0 # q6[0]: activation_alpha
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
l32i a15, a4, 84
ssr a15 # ssr: activation_shift
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
EE.MOVI.32.A q6, a14, 1 # a14: bias_ptr
tie728_s16_conv2d_element_bias a14
EE.MOVI.32.Q q6, a14, 1 # q6[1]: bias_ptr
l32i a9, a4, 112 # a9: dilation_y_offset
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a11, a4, a13, a14, q7
l32i a9, a4, 64 # a9: mac_shift = output.exponent - filter.exponent - input.exponent
EE.MOVI.32.A q6, a11, 0 # a11: activation_alpha
tie728_s16_element_round_result a14, a9, a15, q0
tie728_s16_element_leakyrelu a14, a11
tie728_s16_element_store a2, a14
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder_loop
tie728_s16_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder_end:
retw
.align 4
.text
.global dl_tie728_s16_unaligned_conv2d_hwcn_bias_prelu
.type dl_tie728_s16_unaligned_conv2d_hwcn_bias_prelu, @function
# .section .iram1
dl_tie728_s16_unaligned_conv2d_hwcn_bias_prelu:
.align 4
entry sp, 128
# a2: int16_t *output_ptr
# a3: int16_t *input_ptr
# a4: void *args
l32i a12, a4, 60
l32i a11, a4, 144
EE.MOVI.32.Q q7, a12, 1
EE.MOVI.32.Q q7, a11, 2
l32i a5, a4, 48 # a5: filter_ptr
l32i a6, a4, 100 # a6: c_div_x_1 = input_channel / (vector_width / element_width) - 1
l32i a7, a4, 136 # a7: c_remainder = input_channel % (vector_width / element_width) * sizeof(feature_t)
l32i a8, a4, 108 # a8: dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(feature_t)
l32i a9, a4, 112 # a9: dilation_y_offset
l32i a12, a4, 96 # a12: n_div_x = output_channel / (vector_width / element_width)
l32i a13, a4, 68 # a13: bias_ptr
l32i a14, a4, 80 # a14: activation_alpha_ptr
blti a12, 1, tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_remainder
EE.LD.128.USAR.IP q0, a2, 0
rur.sar_byte a15 # a15: output_sar_byte
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_div_x:
beqi a15, 0, tie728_s16_unaligned_conv2d_hwcn_bias_prelu_128b
beqi a15, 8, tie728_s16_unaligned_conv2d_hwcn_bias_prelu_64b
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_32b:
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_32b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a14, a11
tie728_32b_aligned_vector_store q0, a2, a15
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_prelu_32b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_64b:
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_64b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a14, a11
tie728_64b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_prelu_64b_multiple_loop
j tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_remainder
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_128b:
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_128b_multiple_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.QACC
tie728_s16_conv2d_128b_vector_bias a13
tie728_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, a15, a5, a6, a7, a8, a9, a10, a11, a4, q7
l32i a10, a4, 64 # a10: mac_shift = output.exponent - filter.exponent - input.exponent
l32i a11, a4, 84 # a11: activation_shift
tie728_s16_vector_round_result q0, a10, a15, q1
tie728_s16_conv2d_prelu q0, q1, a14, a11
tie728_128b_aligned_vector_store q0, a2
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_prelu_128b_multiple_loop
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_remainder:
l32i a12, a4, 140 # a12: n_remainder
beqz a12, tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_remainder_end
l32i a5, a4, 160
l32i a15, a4, 164
EE.MOVI.32.Q q7, a5, 1
EE.MOVI.32.Q q7, a15, 2
l32i a5, a4, 168 # filter_ptr unaligned
EE.MOVI.32.Q q6, a13, 1 # q6[1]: bias_ptr
EE.MOVI.32.Q q6, a14, 0 # q6[0]: activation_alpha_ptr
movi a13, 15
sub a13, a13, a7 # a13: 15 - c_remainder
l32i a15, a4, 84
ssr a15 # ssr: activation_shift
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_remainder_loop:
mov a15, a3 # a15: input_ptr
EE.ZERO.ACCX
EE.MOVI.32.A q6, a14, 1 # a14: bias_ptr
tie728_s16_conv2d_element_bias a14
EE.MOVI.32.Q q6, a14, 1 # q6[1]: bias_ptr
l32i a9, a4, 112 # a9: dilation_y_offset
movi a14, 0 # a14: zero
tie728_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, a15, a5, a6, a7, a8, a9, a10, a11, a4, a13, a14, q7
l32i a9, a4, 64 # a9: mac_shift = output.exponent - filter.exponent - input.exponent
EE.MOVI.32.A q6, a11, 0 # a11: activation_alpha_ptr
tie728_s16_element_round_result a14, a9, a15, q0
tie728_s16_element_prelu a14, a11, a15
tie728_s16_element_store a2, a14
EE.MOVI.32.Q q6, a11, 0 # q6[0]: activation_alpha_ptr
addi a12, a12, -1
bnez a12, tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_remainder_loop
tie728_s16_unaligned_conv2d_hwcn_bias_prelu_n_remainder_end:
retw
|
georgevio/IoT-Embedded
| 41,644
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/tie728/dl_tie728_s8_sub2d.S
|
#include "dl_tie728_s8.S"
############################################################################################################################################################
####
#### tie728_s8_sub2d_11c series
####
############################################################################################################################################################
.macro dl_tie728_rescale_sub_rescale_output input0, input1, output, output_scale, output_shift, tmpq, rescale_input
EE.ZERO.Q \tmpq
EE.VSUBS.S8 \tmpq, \tmpq, \output_scale
EE.ZERO.QACC
blti \rescale_input, 2, 10f
# input1 is in the front
EE.VMULAS.S8.QACC \input1, \output_scale
EE.VMULAS.S8.QACC \input0, \tmpq
EE.SRCMB.S8.QACC \output, \output_shift, 0
j 11f
10: # input0 is in the front
EE.VMULAS.S8.QACC \input0, \output_scale
EE.VMULAS.S8.QACC \input1, \tmpq
EE.SRCMB.S8.QACC \output, \output_shift, 0
11:
.endm
.align 4
.text
.global dl_tie728_s8_sub2d_11c
.type dl_tie728_s8_sub2d_11c, @function
.section .iram1
dl_tie728_s8_sub2d_11c:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x_1
l32i a6, a5, 68
l32i a7, a5, 72
blti a6, 1, dl_tie728_s8_sub2d_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VSUBS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VST.128.IP q5, a2, 16
0:
beqi a7, 1, 2f # remainder == 2*16byte
beqi a7, 2, 3f # remainder == 3*16byte
2:
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
EE.VSUBS.S8 q5, q2, q3
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VSUBS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VST.128.IP q5, a2, 16
EE.VSUBS.S8 q4, q0, q1
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s8_sub2d_small_channel: # channel < 3*s (16)
loopgtz a7, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VSUBS.S8 q2, q0, q1
EE.VST.128.IP q2, a2, 16
0:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VSUBS.S8 q2, q0, q1
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_rescale_sub2d_11c
.type dl_tie728_s8_rescale_sub2d_11c, @function
.section .iram1
dl_tie728_s8_rescale_sub2d_11c:
.align 4
entry sp, 32
# a2: int8_t *output_ptr: >> shift or *scale) >> shift
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr: the one need to be rescaled
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a12: rescale_input
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a12, a5, 80
beqi a8, 1, dl_tie728_s8_rescale_sub2d_output
dl_tie728_s8_rescale_sub2d_output_scale: # *scale) >> shift
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_output
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_output:
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s8_rescale_sub2d_output: # >> shift
movi a13, -1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all -1
blti a12, 2, dl_tie728_s8_rescale_sub2d_output_0
# input1 in the front
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_1
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7 # input1 >> shift - input0
EE.SRCMB.S8.QACC q1, a9, 0
EE.LDQA.S8.128.IP a4, 16
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_1:
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7 # input1 >> shift - input0
EE.SRCMB.S8.QACC q1, a9, 0
EE.VST.128.IP q1, a2, 16
retw
# input0 in the front
dl_tie728_s8_rescale_sub2d_output_0:
EE.LDQA.S8.128.IP a4, 16
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_0
EE.SRCMB.S8.QACC q1, a7, 0
EE.LDQA.S8.128.IP a3, 16
EE.VMULAS.S8.QACC q1, q7 # input0 - input1 >> shift
EE.SRCMB.S8.QACC q1, a9, 0
EE.LDQA.S8.128.IP a4, 16
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_0:
EE.SRCMB.S8.QACC q1, a7, 0
EE.LDQA.S8.128.IP a3, 16
EE.VMULAS.S8.QACC q1, q7 # input0 - input1 >> shift
EE.SRCMB.S8.QACC q1, a9, 0
EE.VST.128.IP q1, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_sub2d_11c_relu
.type dl_tie728_s8_sub2d_11c_relu, @function
.section .iram1
dl_tie728_s8_sub2d_11c_relu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x_1
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 68
l32i a7, a5, 72
l32i a14, a5, 52
l32i a15, a5, 60
blti a6, 1, dl_tie728_s8_sub2d_relu_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S8 q4, a14, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VSUBS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VRELU.S8 q5, a14, a15
EE.VST.128.IP q5, a2, 16
0:
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S8 q4, a14, a15
EE.VST.128.IP q4, a2, 16
EE.VSUBS.S8 q5, q2, q3
EE.VRELU.S8 q5, a14, a15
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q2, a3, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VRELU.S8 q4, a14, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VSUBS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VRELU.S8 q5, a14, a15
EE.VST.128.IP q5, a2, 16
EE.VSUBS.S8 q4, q0, q1
EE.VRELU.S8 q4, a14, a15
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s8_sub2d_relu_small_channel: # channel < 3*s
loopgtz a7, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VSUBS.S8 q2, q0, q1
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
0:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VSUBS.S8 q2, q0, q1
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_rescale_sub2d_11c_relu
.type dl_tie728_s8_rescale_sub2d_11c_relu, @function
.section .iram1
dl_tie728_s8_rescale_sub2d_11c_relu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr: >> shift or *scale) >> shift
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr: the one need to be rescaled
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a12: rescale_input
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a12, a5, 80
l32i a14, a5, 52
l32i a15, a5, 60
beqi a8, 1, dl_tie728_s8_rescale_sub2d_output_relu
dl_tie728_s8_rescale_sub2d_output_scale_relu: # *scale) >> shift
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_output_relu
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_output_relu:
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s8_rescale_sub2d_output_relu: # >> shift
movi a13, -1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all -1
blti a12, 2, dl_tie728_s8_rescale_sub2d_output_relu_0
# input1 in the front
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_relu_1
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7 # input1 >> shift - input0
EE.SRCMB.S8.QACC q1, a9, 0
EE.LDQA.S8.128.IP a4, 16
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_relu_1:
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7 # input1 >> shift - input0
EE.SRCMB.S8.QACC q1, a9, 0
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
# input0 in the front
dl_tie728_s8_rescale_sub2d_output_relu_0:
EE.LDQA.S8.128.IP a4, 16
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_relu_0
EE.SRCMB.S8.QACC q1, a7, 0
EE.LDQA.S8.128.IP a3, 16
EE.VMULAS.S8.QACC q1, q7 # input0 - input1 >> shift
EE.SRCMB.S8.QACC q1, a9, 0
EE.LDQA.S8.128.IP a4, 16
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_relu_0:
EE.SRCMB.S8.QACC q1, a7, 0
EE.LDQA.S8.128.IP a3, 16
EE.VMULAS.S8.QACC q1, q7 # input0 - input1 >> shift
EE.SRCMB.S8.QACC q1, a9, 0
EE.VRELU.S8 q1, a14, a15
EE.VST.128.IP q1, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_sub2d_11c_prelu
.type dl_tie728_s8_sub2d_11c_prelu, @function
.section .iram1
dl_tie728_s8_sub2d_11c_prelu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_2x_1
# a7: c_left_x_1
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 68
l32i a7, a5, 72
l32i a14, a5, 56
l32i a15, a5, 60
blti a6, 1, dl_tie728_s8_sub2d_prelu_small_channel
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
loopgtz a6, 0f
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S8 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VPRELU.S8 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
0:
beqi a7, 1, 2f #remainder == 2*16byte
beqi a7, 2, 3f #remainder == 3*16byte
2:
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S8 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q5, q2, q3
EE.VPRELU.S8 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
retw
3:
EE.VLD.128.IP q2, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8.LD.INCP q3, a4, q4, q0, q1
EE.VPRELU.S8 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8.LD.INCP q1, a4, q5, q2, q3
EE.VPRELU.S8 q5, q5, q6, a15
EE.VST.128.IP q5, a2, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q4, q0, q1
EE.VPRELU.S8 q4, q4, q6, a15
EE.VST.128.IP q4, a2, 16
retw
dl_tie728_s8_sub2d_prelu_small_channel: # channel < 3*s
loopgtz a7, 0f
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q3, a14, 16
EE.VSUBS.S8 q2, q0, q1
EE.VPRELU.S8 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
0:
EE.VLD.128.IP q0, a3, 16
EE.VLD.128.IP q1, a4, 16
EE.VLD.128.IP q3, a14, 16
EE.VSUBS.S8 q2, q0, q1
EE.VPRELU.S8 q2, q2, q3, a15
EE.VST.128.IP q2, a2, 16
retw
.align 4
.text
.global dl_tie728_s8_rescale_sub2d_11c_prelu
.type dl_tie728_s8_rescale_sub2d_11c_prelu, @function
.section .iram1
dl_tie728_s8_rescale_sub2d_11c_prelu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr: >> shift or *scale) >> shift
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr: the one need to be rescaled
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a12: rescale_input
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a7, a5, 88
l32i a8, a5, 96
l32i a9, a5, 92
l32i a12, a5, 80
l32i a14, a5, 56
l32i a15, a5, 60
beqi a8, 1, dl_tie728_s8_rescale_sub2d_output_prelu
dl_tie728_s8_rescale_sub2d_output_scale_prelu: # *scale) >> shift
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_output_prelu
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
EE.VLD.128.IP q5, a14, 16
dl_tie728_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VPRELU.S8 q1, q1, q5, a15
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_output_prelu:
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
EE.SRCMB.S8.QACC q1, a7, 0
EE.VLD.128.IP q5, a14, 16
dl_tie728_rescale_sub_rescale_output q0, q1, q1, q7, a9, q4, a12
EE.VPRELU.S8 q1, q1, q5, a15
EE.VST.128.IP q1, a2, 16
retw
dl_tie728_s8_rescale_sub2d_output_prelu: # >> shift
movi a13, -1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all -1
blti a12, 2, dl_tie728_s8_rescale_sub2d_output_prelu_0
# input1 in the front
EE.LDQA.S8.128.IP a4, 16
EE.VLD.128.IP q0, a3, 16
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_prelu_1
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7 # input1 >> shift - input0
EE.SRCMB.S8.QACC q1, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LDQA.S8.128.IP a4, 16
EE.VPRELU.S8 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_prelu_1:
EE.SRCMB.S8.QACC q1, a7, 0
EE.VMULAS.S8.QACC.LD.IP q0, a3, 16, q0, q7 # input1 >> shift - input0
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S8.QACC q1, a9, 0
EE.VPRELU.S8 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
retw
# input0 in the front
dl_tie728_s8_rescale_sub2d_output_prelu_0:
EE.LDQA.S8.128.IP a4, 16
loopgtz a6, dl_tie728_s8_rescale_sub2d_11c_prelu_0
EE.SRCMB.S8.QACC q1, a7, 0
EE.LDQA.S8.128.IP a3, 16
EE.VMULAS.S8.QACC q1, q7 # input0 - input1 >> shift
EE.SRCMB.S8.QACC q1, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LDQA.S8.128.IP a4, 16
EE.VPRELU.S8 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
dl_tie728_s8_rescale_sub2d_11c_prelu_0:
EE.SRCMB.S8.QACC q1, a7, 0
EE.LDQA.S8.128.IP a3, 16
EE.VMULAS.S8.QACC q1, q7 # input0 - input1 >> shift
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S8.QACC q1, a9, 0
EE.VPRELU.S8 q1, q1, q6, a15
EE.VST.128.IP q1, a2, 16
retw
############################################################################################################################################################
####
#### tie728_s8_unaligned_sub2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_tie728_s8_unaligned_sub2d_11c
.type dl_tie728_s8_unaligned_sub2d_11c, @function
.section .iram1
dl_tie728_s8_unaligned_sub2d_11c:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a12: rescale_input
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a12, a5, 80
bgei a7, 0, dl_tie728_s8_unaligned_rescale_sub2d
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s8_unaligned_sub2d_11c_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s8_unaligned_sub2d_11c_0
beqi a13, 8, dl_tie728_s8_unaligned_sub2d_11c_1
loopgtz a6, 0f #dl_tie728_s8_unaligned_sub2d_11c
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VSUBS.S8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S8 q2, q2, q5
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_sub2d_11c_remainder
#output sar = 0
dl_tie728_s8_unaligned_sub2d_11c_0:
loopgtz a6, 1f #dl_tie728_s8_unaligned_sub2d_11c_loop0
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VSUBS.S8 q2, q2, q5
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S8 q2, q2, q5
EE.VST.128.IP q2, a2, 16
j dl_tie728_s8_unaligned_sub2d_11c_remainder
# #output sar = 8
dl_tie728_s8_unaligned_sub2d_11c_1:
loopgtz a6, 2f #dl_tie728_s8_unaligned_sub2d_11c_loop1
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VSUBS.S8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S8 q2, q2, q5
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_unaligned_sub2d_11c_remainder
dl_tie728_s8_unaligned_sub2d_11c_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s8_unaligned_sub2d_11c_remainder:
beqz a10, dl_tie728_s8_unaligned_sub2d_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VSUBS.S8 q2, q2, q5
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_sub2d_end:
retw
# rescaled sub
dl_tie728_s8_unaligned_rescale_sub2d:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s8_rescale_unaligned_sub2d_output_shift
# rescaled to output by *scale) >> shift
dl_tie728_s8_rescale_unaligned_sub2d_output_scale:
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
blti a6, 0, dl_tie728_s8_unaligned_sub2d_scale_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s8_rescale_unaligned_sub2d_11c_scale
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store0 q2, a2, a11
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_sub2d_scale_remainder
dl_tie728_s8_unaligned_sub2d_scale_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6
dl_tie728_s8_unaligned_sub2d_scale_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_sub2d_output_scale_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
# dl_tie728_s8_unaligned_store0 q2, a2, a9
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_sub2d_output_scale_end:
retw
# rescaled to output by right shift
dl_tie728_s8_rescale_unaligned_sub2d_output_shift:
movi a13, -1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all -1
blti a6, 0, dl_tie728_s8_unaligned_sub2d_shift_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s8_rescale_unaligned_sub2d_11c_shift
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0 # input1 >> shift
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S8.QACC q5, a9, 0
EE.LD.128.USAR.IP q1, a3, 16
dl_tie728_s8_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S8.QACC q5, a9, 0
dl_tie728_s8_unaligned_store0 q5, a2, a13
j dl_tie728_s8_unaligned_sub2d_shift_remainder
dl_tie728_s8_unaligned_sub2d_shift_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6
dl_tie728_s8_unaligned_sub2d_shift_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_sub2d_output_shift_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S8.QACC q5, a9, 0
# dl_tie728_s8_unaligned_store0 q5, a2, a13
dl_tie728_s8_store_remainder q5, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_sub2d_output_shift_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_sub2d_11c_relu
.type dl_tie728_s8_unaligned_sub2d_11c_relu, @function
.section .iram1
dl_tie728_s8_unaligned_sub2d_11c_relu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a12: rescale_input
# a14: activation_alpha
# a15: activation_shift
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a12, a5, 80
l32i a14, a5, 52
l32i a15, a5, 60
bgei a7, 0, dl_tie728_s8_unaligned_rescale_sub2d_relu
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s8_unaligned_sub2d_11c_relu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s8_unaligned_sub2d_11c_relu_0
beqi a13, 8, dl_tie728_s8_unaligned_sub2d_11c_relu_1
loopgtz a6, 0f #dl_tie728_s8_unaligned_sub2d_11c
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VSUBS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_sub2d_11c_relu_remainder
#output sar = 0
dl_tie728_s8_unaligned_sub2d_11c_relu_0:
loopgtz a6, 1f #dl_tie728_s8_unaligned_sub2d_11c_loop0
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VSUBS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
EE.VST.128.IP q2, a2, 16
j dl_tie728_s8_unaligned_sub2d_11c_relu_remainder
# #output sar = 8
dl_tie728_s8_unaligned_sub2d_11c_relu_1:
loopgtz a6, 2f #dl_tie728_s8_unaligned_sub2d_11c_loop1
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VSUBS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VSUBS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_unaligned_sub2d_11c_relu_remainder
dl_tie728_s8_unaligned_sub2d_11c_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s8_unaligned_sub2d_11c_relu_remainder:
beqz a10, dl_tie728_s8_unaligned_sub2d_relu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VSUBS.S8 q2, q2, q5
EE.VRELU.S8 q2, a14, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_sub2d_relu_end:
retw
# rescaled sub
dl_tie728_s8_unaligned_rescale_sub2d_relu:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s8_rescale_unaligned_sub2d_output_shift_relu
# rescaled to output by *scale) >> shift
dl_tie728_s8_rescale_unaligned_sub2d_output_scale_relu:
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
blti a6, 0, dl_tie728_s8_unaligned_sub2d_scale_relu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s8_rescale_unaligned_sub2d_11c_scale
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a11
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
EE.VRELU.S8 q2, a14, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_sub2d_scale_relu_remainder
dl_tie728_s8_unaligned_sub2d_scale_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6
dl_tie728_s8_unaligned_sub2d_scale_relu_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_sub2d_output_scale_relu_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
EE.VRELU.S8 q2, a14, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a9
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_sub2d_output_scale_relu_end:
retw
# rescaled to output by right shift
dl_tie728_s8_rescale_unaligned_sub2d_output_shift_relu:
movi a13, -1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all -1
blti a6, 0, dl_tie728_s8_unaligned_sub2d_shift_relu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s8_rescale_unaligned_sub2d_11c_shift
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0 # input1 >> shift
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S8.QACC q5, a9, 0
EE.LD.128.USAR.IP q1, a3, 16
EE.VRELU.S8 q5, a14, a15
dl_tie728_s8_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S8.QACC q5, a9, 0
EE.VRELU.S8 q5, a14, a15
dl_tie728_s8_unaligned_store0 q5, a2, a13
j dl_tie728_s8_unaligned_sub2d_shift_relu_remainder
dl_tie728_s8_unaligned_sub2d_shift_relu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6
dl_tie728_s8_unaligned_sub2d_shift_relu_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_sub2d_output_shift_relu_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S8.QACC q5, a9, 0
EE.VRELU.S8 q5, a14, a15
# dl_tie728_s8_unaligned_store0 q5, a2, a13
dl_tie728_s8_store_remainder q5, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_sub2d_output_shift_relu_end:
retw
.align 4
.text
.global dl_tie728_s8_unaligned_sub2d_11c_prelu
.type dl_tie728_s8_unaligned_sub2d_11c_prelu, @function
.section .iram1
dl_tie728_s8_unaligned_sub2d_11c_prelu:
.align 4
entry sp, 32
# a2: int8_t *output_ptr
# a3: int8_t *input0_ptr
# a4: int8_t *input1_ptr
# a5: void *args
# a6: c_div_x_1
# a7: input_shift
# a8: output_scale
# a9: output_shift
# a10: c_remainder
# a12: rescale_input
# a14: activation_alpha_ptr
# a15: activation_shift
l32i a6, a5, 64
l32i a10, a5, 76
l32i a7, a5, 88
l32i a12, a5, 80
l32i a14, a5, 56
l32i a15, a5, 60
bgei a7, 0, dl_tie728_s8_unaligned_rescale_sub2d_prelu
# input0 exp = input1 exp = output exp
EE.LD.128.USAR.IP q5, a2, 0 #get output_ptr sar_byte
rur.sar_byte a13
blti a6, 0, dl_tie728_s8_unaligned_sub2d_11c_prelu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
beqi a13, 0, dl_tie728_s8_unaligned_sub2d_11c_prelu_0
beqi a13, 8, dl_tie728_s8_unaligned_sub2d_11c_prelu_1
loopgtz a6, 0f #dl_tie728_s8_unaligned_sub2d_11c
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
0:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_sub2d_11c_prelu_remainder
#output sar = 0
dl_tie728_s8_unaligned_sub2d_11c_prelu_0:
loopgtz a6, 1f #dl_tie728_s8_unaligned_sub2d_11c_loop0
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
1:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
EE.VST.128.IP q2, a2, 16
j dl_tie728_s8_unaligned_sub2d_11c_prelu_remainder
# #output sar = 8
dl_tie728_s8_unaligned_sub2d_11c_prelu_1:
loopgtz a6, 2f #dl_tie728_s8_unaligned_sub2d_11c_loop1
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.LD.128.USAR.IP q1, a3, 16
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store1 q2, a2
2:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a12
EE.SRC.Q.QUP q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store1 q2, a2
j dl_tie728_s8_unaligned_sub2d_11c_prelu_remainder
dl_tie728_s8_unaligned_sub2d_11c_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a12
dl_tie728_s8_unaligned_sub2d_11c_prelu_remainder:
beqz a10, dl_tie728_s8_unaligned_sub2d_prelu_end
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a12
EE.SRC.Q q5, q3, q4
EE.VLD.128.IP q6, a14, 16
EE.VSUBS.S8 q2, q2, q5
EE.VPRELU.S8 q2, q2, q6, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a13
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_sub2d_prelu_end:
retw
# rescaled sub
dl_tie728_s8_unaligned_rescale_sub2d_prelu:
l32i a8, a5, 96 # output_scale
l32i a9, a5, 92 # output_shift
beqi a8, 1, dl_tie728_s8_rescale_unaligned_sub2d_output_shift_prelu
# rescaled to output by *scale) >> shift
dl_tie728_s8_rescale_unaligned_sub2d_output_scale_prelu:
s8i a8, a1, 0
EE.VLDBC.8 q7, a1 # all output_scale
blti a6, 0, dl_tie728_s8_unaligned_sub2d_scale_prelu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 3f #dl_tie728_s8_rescale_unaligned_sub2d_11c_scale
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a11
3:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
EE.VLD.128.IP q6, a14, 16
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
EE.VPRELU.S8 q2, q2, q6, a15
dl_tie728_s8_unaligned_store0 q2, a2, a13
j dl_tie728_s8_unaligned_sub2d_scale_prelu_remainder
dl_tie728_s8_unaligned_sub2d_scale_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6
dl_tie728_s8_unaligned_sub2d_scale_prelu_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_sub2d_output_scale_prelu_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q1, a7, 0
EE.VLD.128.IP q6, a14, 16
dl_tie728_rescale_sub_rescale_output q2, q1, q2, q7, a9, q4, a12
EE.VPRELU.S8 q2, q2, q6, a15
# dl_tie728_s8_unaligned_store0 q2, a2, a9
dl_tie728_s8_store_remainder q2, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_sub2d_output_scale_prelu_end:
retw
# rescaled to output by right shift
dl_tie728_s8_rescale_unaligned_sub2d_output_shift_prelu:
movi a13, -1
s8i a13, a1, 0
EE.VLDBC.8 q7, a1 # all -1
blti a6, 0, dl_tie728_s8_unaligned_sub2d_shift_prelu_small_remainder # channel < 16
EE.LD.128.USAR.IP q0, a3, 16
EE.LD.128.USAR.IP q3, a4, 16
EE.LD.128.USAR.IP q1, a3, 16
loopgtz a6, 4f #dl_tie728_s8_rescale_unaligned_sub2d_11c_shift
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 16
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0 # input1 >> shift
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.SRCMB.S8.QACC q5, a9, 0
EE.VLD.128.IP q6, a14, 16
EE.LD.128.USAR.IP q1, a3, 16
EE.VPRELU.S8 q5, q5, q6, a15
dl_tie728_s8_unaligned_store0 q5, a2, a13
4:
addi a3, a3, -16
add a3, a3, a10
rur.sar_byte a11 #input0 sar
EE.SRC.Q.QUP q2, q0, q1
EE.LD.128.USAR.XP q4, a4, a10
rur.sar_byte a6 #input1 sar
EE.SRC.Q.QUP q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S8.QACC q5, a9, 0
EE.VPRELU.S8 q5, q5, q6, a15
dl_tie728_s8_unaligned_store0 q5, a2, a13
j dl_tie728_s8_unaligned_sub2d_shift_prelu_remainder
dl_tie728_s8_unaligned_sub2d_shift_prelu_small_remainder:
EE.LD.128.USAR.XP q0, a3, a10
rur.sar_byte a11
EE.LD.128.USAR.XP q3, a4, a10
rur.sar_byte a6
dl_tie728_s8_unaligned_sub2d_shift_prelu_remainder:
beqz a10, dl_tie728_s8_unaligned_rescale_sub2d_output_shift_prelu_end # c remainder
EE.LD.128.USAR.IP q1, a3, 0
wur.sar_byte a11
EE.SRC.Q q2, q0, q1
EE.LD.128.USAR.IP q4, a4, 0
wur.sar_byte a6
EE.SRC.Q q5, q3, q4
EE.MOV.S8.QACC q5
EE.SRCMB.S8.QACC q5, a7, 0
blti a12, 2, 11f
EE.VMULAS.S8.QACC q2, q7 # input1 >> shift - input0
j 12f
11:
EE.MOV.S8.QACC q2
EE.VMULAS.S8.QACC q5, q7 # input0 - input1 >> shift
12:
EE.VLD.128.IP q6, a14, 16
EE.SRCMB.S8.QACC q5, a9, 0
EE.VPRELU.S8 q5, q5, q6, a15
# dl_tie728_s8_unaligned_store0 q5, a2, a13
dl_tie728_s8_store_remainder q5, a9, a11, a12, a13, a2, a10
dl_tie728_s8_unaligned_rescale_sub2d_output_shift_prelu_end:
retw
|
georgevio/IoT-Embedded
| 22,990
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/xtensa/dl_xtensa_s16_block.S
|
############################################################################################################################################################
# xtensa general tools
############################################################################################################################################################
.macro xtensa_clear_accumulator zero
# zero: any a-register equals 0
wsr \zero, acchi
wsr \zero, acclo
.endm
.macro xtensa_fetch_accumulator output temp
# output: output value
# temp: temporary variable
rsr \output, acchi
rsr \temp, acclo
src \output, \output, \temp
.endm
.macro xtensa_saturation x
# x: any a-register
clamps \x, \x, 15
.endm
.macro xtensa_bias x bias_address temp
# x: a variable to be added
# bias_address:
# temp: a temporary variable keep bias element value
l16si \temp, \bias_address, 0
addi \bias_address, \bias_address, 2
add \x, \x, \temp
.endm
.macro xtensa_store output_address x
# output_address:
# x: a variable to be stored
s16i \x, \output_address, 0
addi \output_address, \output_address, 2
.endm
.macro xtensa_relu x zero
# x: varaible
# zero: any a-register equals to 0
max \x, \x, \zero
.endm
############################################################################################################################################################
# xtensa_s16_conv2d_11c1
############################################################################################################################################################
.macro xtensa_s16_conv2d_11c1 input__v0 input__v1 filter_v0 filter_v1 input__ptr filter_ptr c c_rs2_1
# input__v0: 2 input elements
# input__v1: 2 input elements
# filter_v0: 2 filter elements
# filter_v1: 2 filter elements
# input__ptr:
# filter_ptr:
# c: input_channel
# c_rs2_1: input_channel >> 2 - 1
bgei \c, 4, 5f
beqi \c, 3, 3f
beqi \c, 2, 2f
# c == 1
ldinc \input__v0, \input__ptr
ldinc \filter_v0, \filter_ptr
mula.dd.ll \input__v0, \filter_v0
addi \input__ptr, \input__ptr, -2
addi \filter_ptr, \filter_ptr, -2
j 1f
2:
# c == 2
ldinc \input__v0, \input__ptr
ldinc \filter_v0, \filter_ptr
mula.dd.ll \input__v0, \filter_v0
mula.dd.hh \input__v0, \filter_v0
j 1f
3:
# c == 3
ldinc \input__v0, \input__ptr
ldinc \filter_v0, \filter_ptr
ldinc \input__v1, \input__ptr
mula.dd.ll.ldinc \filter_v1, \filter_ptr, \input__v0, \filter_v0
mula.dd.hh \input__v0, \filter_v0
mula.dd.ll \input__v1, \filter_v1
addi \input__ptr, \input__ptr, -2
addi \filter_ptr, \filter_ptr, -2
j 1f
5:
# c >= 4
ldinc \input__v0, \input__ptr
ldinc \filter_v0, \filter_ptr
ldinc \input__v1, \input__ptr
mula.dd.ll.ldinc \filter_v1, \filter_ptr, \input__v0, \filter_v0
loopgtz \c_rs2_1, 4f
mula.dd.hh.ldinc \input__v0, \input__ptr, \input__v0, \filter_v0
mula.dd.ll.ldinc \filter_v0, \filter_ptr, \input__v1, \filter_v1
mula.dd.hh.ldinc \input__v1, \input__ptr, \input__v1, \filter_v1
mula.dd.ll.ldinc \filter_v1, \filter_ptr, \input__v0, \filter_v0
4:
mula.dd.hh \input__v0, \filter_v0
mula.dd.ll \input__v1, \filter_v1
mula.dd.hh \input__v1, \filter_v1
bbci \c, 1, 6f
# c % 4 == 2 or 3
ldinc \input__v0, \input__ptr
ldinc \filter_v0, \filter_ptr
mula.dd.hh \input__v0, \filter_v0
mula.dd.ll \input__v0, \filter_v0
6:
bbci \c, 0, 1f
# c % 2 == 1
ldinc \input__v0, \input__ptr
ldinc \filter_v0, \filter_ptr
mula.dd.ll \input__v0, \filter_v0
addi \input__ptr, \input__ptr, -2
addi \filter_ptr, \filter_ptr, -2
1:
.endm
.macro xtensa_load_args input__ptr args filter_ptr c n c_rs2_1 mac_shift
l32i \c, \args, 4 // input_channel
l32i \n, \args, 36 // output_channel
l32i \filter_ptr, \args, 48 // filter
l32i \mac_shift, \args, 64 // mac_shift
l32i \c_rs2_1, \args, 92 // input_channel >> 2 - 1
addi \filter_ptr, \filter_ptr, -4 // ldinc will bump up pointer first then load
addi \input__ptr, \input__ptr, -4 // ldinc will bump up pointer first then load
ssr \mac_shift
movi \mac_shift, 0
.endm
.align 4
.text
.global dl_xtensa_s16_conv2d_11cn_bias
.type dl_xtensa_s16_conv2d_11cn_bias, @function
.section .iram1
dl_xtensa_s16_conv2d_11cn_bias:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
xtensa_load_args a3, a4, a5, a6, a7, a8, a9
# a10: bias_address
# a11:
# a12:
# a13: output variable
# a14: temporary variable
# a15: moving_input_address
l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_11cn_bias_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_11c1 m0, m1, m2, m3, a15, a5, a6, a8
xtensa_fetch_accumulator a13, a14
xtensa_bias a13, a10, a14
# xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_11cn_bias_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_11cn_bias_relu
.type dl_xtensa_s16_conv2d_11cn_bias_relu, @function
.section .iram1
dl_xtensa_s16_conv2d_11cn_bias_relu:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
xtensa_load_args a3, a4, a5, a6, a7, a8, a9
# a10: bias_address
# a11:
# a12:
# a13: output variable
# a14: temporary variable
# a15: moving_input_address
l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_11cn_bias_relu_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_11c1 m0, m1, m2, m3, a15, a5, a6, a8
xtensa_fetch_accumulator a13, a14
xtensa_bias a13, a10, a14
xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_11cn_bias_relu_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_11cn
.type dl_xtensa_s16_conv2d_11cn, @function
.section .iram1
dl_xtensa_s16_conv2d_11cn:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
xtensa_load_args a3, a4, a5, a6, a7, a8, a9
# a10: bias_address
# a11:
# a12:
# a13: output variable
# a14: temporary variable
# a15: moving_input_address
# l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_11cn_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_11c1 m0, m1, m2, m3, a15, a5, a6, a8
xtensa_fetch_accumulator a13, a14
# xtensa_bias a13, a10, a14
# xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_11cn_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_11cn_relu
.type dl_xtensa_s16_conv2d_11cn_relu, @function
.section .iram1
dl_xtensa_s16_conv2d_11cn_relu:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
xtensa_load_args a3, a4, a5, a6, a7, a8, a9
# a10: bias_address
# a11:
# a12:
# a13: output variable
# a14: temporary variable
# a15: moving_input_address
# l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_11cn_relu_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_11c1 m0, m1, m2, m3, a15, a5, a6, a8
xtensa_fetch_accumulator a13, a14
# xtensa_bias a13, a10, a14
xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_11cn_relu_loop
retw
############################################################################################################################################################
# xtensa_s16_conv2d_33c1
############################################################################################################################################################
.macro xtensa_s16_conv2d_33c1 input__v0 input__v1 filter_v0 filter_v1 input__ptr filter_ptr c c_rs2_1 dilation_x_offset dilation_y_offset
# input__v0: 2 input elements
# input__v1: 2 input elements
# filter_v0: 2 filter elements
# filter_v1: 2 filter elements
# input__ptr:
# filter_ptr:
# c: input_channel
# c_rs2_1: input_channel >> 2 - 1
# dilation_x_offset: (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset: (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_x_offset # go to the next input__ptr
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_x_offset # go to the next input__ptr
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_y_offset # go to the next input__ptr
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_x_offset # go to the next input__ptr
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_x_offset # go to the next input__ptr
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_y_offset # go to the next input__ptr
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_x_offset # go to the next input__ptr
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_x_offset # go to the next input_ptr
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
.endm
.macro xtensa_load_hwcn_args input__ptr args filter_ptr c n c_rs2_1 mac_shift dilation_x_offset dilation_y_offset
xtensa_load_args \input__ptr, \args, \filter_ptr, \c, \n, \c_rs2_1, \mac_shift
l32i \dilation_x_offset, \args, 108 // input dilation x offset
l32i \dilation_y_offset, \args, 112 // input dilation y offset
.endm
.align 4
.text
.global dl_xtensa_s16_conv2d_33cn_bias
.type dl_xtensa_s16_conv2d_33cn_bias, @function
.section .iram1
dl_xtensa_s16_conv2d_33cn_bias:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
# a10: bias_address
# a11: input dilation x offset
# a12: input dilation y offset
# a13: output variable
# a14: temporary variable
# a15: moving_input_address
xtensa_load_hwcn_args a3, a4, a5, a6, a7, a8, a9, a11, a12
l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_33cn_bias_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_33c1 m0, m1, m2, m3, a15, a5, a6, a8, a11, a12
xtensa_fetch_accumulator a13, a14
xtensa_bias a13, a10, a14
# xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_33cn_bias_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_33cn_bias_relu
.type dl_xtensa_s16_conv2d_33cn_bias_relu, @function
.section .iram1
dl_xtensa_s16_conv2d_33cn_bias_relu:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
# a10: bias_address
# a11: input dilation x offset
# a12: input dilation y offset
# a13: output variable
# a14: temporary variable
# a15: moving_input_address
xtensa_load_hwcn_args a3, a4, a5, a6, a7, a8, a9, a11, a12
l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_33cn_bias_relu_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_33c1 m0, m1, m2, m3, a15, a5, a6, a8, a11, a12
xtensa_fetch_accumulator a13, a14
xtensa_bias a13, a10, a14
xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_33cn_bias_relu_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_33cn
.type dl_xtensa_s16_conv2d_33cn, @function
.section .iram1
dl_xtensa_s16_conv2d_33cn:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
# a10: bias_address
# a11: input dilation x offset
# a12: input dilation y offset
# a13: output variable
# a14: temporary variable
# a15: moving_input_address
xtensa_load_hwcn_args a3, a4, a5, a6, a7, a8, a9, a11, a12
# l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_33cn_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_33c1 m0, m1, m2, m3, a15, a5, a6, a8, a11, a12
xtensa_fetch_accumulator a13, a14
# xtensa_bias a13, a10, a14
# xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_33cn_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_33cn_relu
.type dl_xtensa_s16_conv2d_33cn_relu, @function
.section .iram1
dl_xtensa_s16_conv2d_33cn_relu:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
# a10:
# a11: input dilation x offset
# a12: input dilation y offset
# a13: output variable
# a14: temporary variable
# a15: moving_input_address
xtensa_load_hwcn_args a3, a4, a5, a6, a7, a8, a9, a11, a12
# l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_33cn_relu_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_33c1 m0, m1, m2, m3, a15, a5, a6, a8, a11, a12
xtensa_fetch_accumulator a13, a14
# xtensa_bias a13, a10, a14
xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_33cn_relu_loop
retw
############################################################################################################################################################
# xtensa_s16_conv2d_hwc1
############################################################################################################################################################
.macro xtensa_s16_conv2d_hwc1 input__v0 input__v1 filter_v0 filter_v1 input__ptr filter_ptr c c_rs2_1 dilation_x_offset dilation_y_offset filter_h filter_w args
# input__v0: 2 input elements
# input__v1: 2 input elements
# filter_v0: 2 filter elements
# filter_v1: 2 filter elements
# input__ptr:
# filter_ptr:
# c: input_channel
# c_rs2_1: input_channel >> 2 - 1
# dilation_x_offset: dilation_x * input_channel_with_padding - input_channel
# dilation_y_offset: dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)
# filter_h: filter height
# filter_w: filter width
l32i \filter_h, \args, 52 # filter_height
7:
l32i \filter_w, \args, 56 # filter_width
beqi \filter_w, 1, 9f
8:
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
add \input__ptr, \input__ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bgei \filter_w, 2, 8b
9:
xtensa_s16_conv2d_11c1 \input__v0 \input__v1 \filter_v0 \filter_v1 \input__ptr \filter_ptr \c \c_rs2_1
l32i \filter_w, \args, 60 # filter_y_offset
add \input__ptr, \input__ptr, \dilation_y_offset
add \filter_ptr, \filter_ptr, \filter_w
addi \filter_h, \filter_h, -1
bnez \filter_h, 7b
l32i \filter_h, \args, 144 # filter_n_offset
add \filter_ptr, \filter_ptr, \filter_h
.endm
.align 4
.text
.global dl_xtensa_s16_conv2d_hwcn_bias
.type dl_xtensa_s16_conv2d_hwcn_bias, @function
.section .iram1
dl_xtensa_s16_conv2d_hwcn_bias:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
# a10: bias_address
# a11: input dilation x offset
# a12: input dilation y offset
# a13: filter_height, output variable
# a14: filter_width, temporary variable
# a15: moving_input_address
xtensa_load_hwcn_args a3, a4, a5, a6, a7, a8, a9, a11, a12
l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_hwcn_bias_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_hwc1 m0, m1, m2, m3, a15, a5, a6, a8, a11, a12, a13, a14, a4
xtensa_fetch_accumulator a13, a14
xtensa_bias a13, a10, a14
# xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_hwcn_bias_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_hwcn_bias_relu
.type dl_xtensa_s16_conv2d_hwcn_bias_relu, @function
.section .iram1
dl_xtensa_s16_conv2d_hwcn_bias_relu:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
# a10: bias_address
# a11: input dilation x offset
# a12: input dilation y offset
# a13: filter_height, output variable
# a14: filter_width, temporary variable
# a15: moving_input_address
xtensa_load_hwcn_args a3, a4, a5, a6, a7, a8, a9, a11, a12
l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_hwcn_bias_relu_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_hwc1 m0, m1, m2, m3, a15, a5, a6, a8, a11, a12, a13, a14, a4
xtensa_fetch_accumulator a13, a14
xtensa_bias a13, a10, a14
xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_hwcn_bias_relu_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_hwcn
.type dl_xtensa_s16_conv2d_hwcn, @function
.section .iram1
dl_xtensa_s16_conv2d_hwcn:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
# a10:
# a11: input dilation x offset
# a12: input dilation y offset
# a13: filter_height, output variable
# a14: filter_width, temporary variable
# a15: moving_input_address
xtensa_load_hwcn_args a3, a4, a5, a6, a7, a8, a9, a11, a12
# l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_hwcn_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_hwc1 m0, m1, m2, m3, a15, a5, a6, a8, a11, a12, a13, a14, a4
xtensa_fetch_accumulator a13, a14
# xtensa_bias a13, a10, a14
# xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_hwcn_loop
retw
.align 4
.text
.global dl_xtensa_s16_conv2d_hwcn_relu
.type dl_xtensa_s16_conv2d_hwcn_relu, @function
.section .iram1
dl_xtensa_s16_conv2d_hwcn_relu:
.align 4
entry sp, 16
# a2: int16_t *output_address
# a3: int16_t *input__ptr
# a4: void *args
# a5: filter_ptr
# a6: c
# a7: n
# a8: c_rs2_1
# a9: mac_shift (after set srr a9 will be 0)
# a10: bias_address
# a11: input dilation x offset
# a12: input dilation y offset
# a13: filter_height, output variable
# a14: filter_width, temporary variable
# a15: moving_input_address
xtensa_load_hwcn_args a3, a4, a5, a6, a7, a8, a9, a11, a12
# l32i a10, a4, 68 # bias_address
xtensa_s16_conv2d_hwcn_relu_loop:
mov a15, a3 # reload input__ptr
xtensa_clear_accumulator a9
xtensa_s16_conv2d_hwc1 m0, m1, m2, m3, a15, a5, a6, a8, a11, a12, a13, a14, a4
xtensa_fetch_accumulator a13, a14
# xtensa_bias a13, a10, a14
xtensa_relu a13, a9
xtensa_saturation a13
xtensa_store a2, a13
addi a7, a7, -1 # bump up pointer
bnez a7, xtensa_s16_conv2d_hwcn_relu_loop
retw
|
georgevio/IoT-Embedded
| 14,399
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_or4d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor
.type dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor, @function
#.section .iram1
dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.orq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor
.type dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor, @function
#.section .iram1
dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.8.ip q1, a2, 0
esp.orq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor
.type dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor, @function
#.section .iram1
dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.8.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.orq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned
.type dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_remainder
dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_or4d_bchw_w1_16_w2_16_simdor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.orq q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned
.type dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.orq q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.orq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.orq q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_remainder
dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a2, 0
dl_esp32p4_s8_or4d_bchw_w1_16_w2_1_simdor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.orq q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned
.type dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned, @function
#.section .iram1
dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a2: int8_t *input0_ptr
# a1: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.orq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.orq q2, q5, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.orq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.orq q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.orq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.orq q2, q5, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_remainder
dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a1, 0
dl_esp32p4_s8_or4d_bchw_w1_1_w2_16_simdor_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end___
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.orq q2, q5, q2
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end___:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 14,722
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_max4d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax
.type dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax, @function
#.section .iram1
dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vmax.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax
.type dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax, @function
#.section .iram1
dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.16.ip q1, a2, 0
esp.vmax.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax
.type dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax, @function
#.section .iram1
dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.16.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.vmax.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned
.type dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned, @function
#.section .iram1
dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmax.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmax.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmax.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_remainder
dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_max4d_bchw_w1_8_w2_8_simdmax_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vmax.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned
.type dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned, @function
#.section .iram1
dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.vmax.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.vmax.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.vmax.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_remainder
dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a2, 0
dl_esp32p4_s16_max4d_bchw_w1_8_w2_1_simdmax_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.vmax.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned
.type dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned, @function
#.section .iram1
dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a2: int16_t *input0_ptr
# a1: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.vmax.s16 q2, q5, q2 #esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.vmax.s16 q2, q5, q2 #esp.vmax.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.vmax.s16 q2, q5, q2 #esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.vmax.s16 q2, q5, q2 #esp.vmax.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.vmax.s16 q2, q5, q2 #esp.vmax.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.vmax.s16 q2, q5, q2 #esp.vmax.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_remainder
dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a1, 0
dl_esp32p4_s16_max4d_bchw_w1_1_w2_8_simdmax_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_endtest
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.vmax.s16 q2, q5, q2 #esp.vmax.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_endtest:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 14,056
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_less.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_less_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_less_w1_8_w2_8
.type dl_esp32p4_s16_less_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_less_w1_8_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
esp32p4_s16_less_w1_8_w2_8_loop:
beq t0, a3, esp32p4_s16_less_w1_8_w2_8_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.lt.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_less_w1_8_w2_8_loop
esp32p4_s16_less_w1_8_w2_8_end:
ret
#void dl_esp32p4_s16_less_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_less_w1_8_w2_1
.type dl_esp32p4_s16_less_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_less_w1_8_w2_1:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s16_less_w1_8_w2_1_loop:
beq t0, a3, esp32p4_s16_less_w1_8_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.lt.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_less_w1_8_w2_1_loop
esp32p4_s16_less_w1_8_w2_1_end:
ret
#void dl_esp32p4_s16_less_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_less_w1_1_w2_8
.type dl_esp32p4_s16_less_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_less_w1_1_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s16_less_w1_1_w2_8_loop:
beq t0, a3, esp32p4_s16_less_w1_1_w2_8_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.lt.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_less_w1_1_w2_8_loop
esp32p4_s16_less_w1_1_w2_8_end:
ret
.align 2
.text
.global dl_esp32p4_s16_less_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_less_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_less_w1_8_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_less_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_less_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_less_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_less_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
// esp.vst.128.ip q2, a0, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_less_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_less_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_less_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_less_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_less_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_less_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_less_w1_8_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_less_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_less_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_less_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_less_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_less_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_less_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_less_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.lt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_less_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_less_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_less_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_less_w1_1_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_less_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_less_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_less_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_less_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_less_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_less_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_less_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.lt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_less_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,465
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_or4d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor
.type dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor, @function
#.section .iram1
dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.orq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor
.type dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor, @function
#.section .iram1
dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.16.ip q1, a2, 0
esp.orq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor
.type dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor, @function
#.section .iram1
dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.16.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.orq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned
.type dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned, @function
#.section .iram1
dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.orq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_remainder
dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_or4d_bchw_w1_8_w2_8_simdor_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.orq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned
.type dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned, @function
#.section .iram1
dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.orq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.orq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.orq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_remainder
dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a2, 0
dl_esp32p4_s16_or4d_bchw_w1_8_w2_1_simdor_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.orq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned
.type dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned, @function
#.section .iram1
dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a2: int16_t *input0_ptr
# a1: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.orq q2, q5, q2 #esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.orq q2, q5, q2 #esp.orq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.orq q2, q5, q2 #esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.orq q2, q5, q2 #esp.orq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.orq q2, q5, q2 #esp.orq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.orq q2, q5, q2 #esp.orq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_remainder
dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a1, 0
dl_esp32p4_s16_or4d_bchw_w1_1_w2_8_simdor_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_endtest
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.orq q2, q5, q2 #esp.orq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_endtest:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 15,711
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_lessorequal.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_lessorequal_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_lessorequal_w1_8_w2_8
.type dl_esp32p4_s16_lessorequal_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_lessorequal_w1_8_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
esp32p4_s16_lessorequal_w1_8_w2_8_loop:
beq t0, a3, esp32p4_s16_lessorequal_w1_8_w2_8_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.lt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_lessorequal_w1_8_w2_8_loop
esp32p4_s16_lessorequal_w1_8_w2_8_end:
ret
#void dl_esp32p4_s16_lessorequal_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_lessorequal_w1_8_w2_1
.type dl_esp32p4_s16_lessorequal_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_lessorequal_w1_8_w2_1:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s16_lessorequal_w1_8_w2_1_loop:
beq t0, a3, esp32p4_s16_lessorequal_w1_8_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.lt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_lessorequal_w1_8_w2_1_loop
esp32p4_s16_lessorequal_w1_8_w2_1_end:
ret
#void dl_esp32p4_s16_lessorequal_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_lessorequal_w1_1_w2_8
.type dl_esp32p4_s16_lessorequal_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_lessorequal_w1_1_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s16_lessorequal_w1_1_w2_8_loop:
beq t0, a3, esp32p4_s16_lessorequal_w1_1_w2_8_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.lt.s16 q2, q0, q1
esp.vcmp.eq.s16 q6, q0, q1
esp.vmax.u16 q2, q2, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_lessorequal_w1_1_w2_8_loop
esp32p4_s16_lessorequal_w1_1_w2_8_end:
ret
.align 2
.text
.global dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
// esp.vst.128.ip q2, a0, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_lessorequal_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.lt.s16 q1, q2, q5
esp.vcmp.eq.s16 q6, q2, q5
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_lessorequal_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.lt.s16 q1, q5, q2
esp.vcmp.eq.s16 q6, q5, q2
esp.vmax.u16 q2, q1, q6
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_lessorequal_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 7,472
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_requantize_linear.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
.text
.align 2
.global dl_esp32p4_s16_s16_requantize_linear
.type dl_esp32p4_s16_s16_requantize_linear, @function
.balign 4
.option norvc
dl_esp32p4_s16_s16_requantize_linear:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: size_div_x
# a4: in_size_remainder
# a5: tmp value
# t3: output_shift
# t4: output_scale
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 8(a2) // size_div_x
lw a4, 12(a2) // in_size_remainder
lw t3, 20(a2) // output_shift
lw t4, 24(a2) // output_scale
bgtz t4, esp32p4_s16_s16_requantize_linear_left_shift
beqz a3, esp32p4_s16_s16_requantize_linear_right_shift_remainder
esp32p4_s16_s16_requantize_linear_right_shift_loop:
esp.ldqa.s16.128.ip a1, 16
addi a3, a3, -1
esp32p4_s16_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
bnez a3, esp32p4_s16_s16_requantize_linear_right_shift_loop
esp32p4_s16_s16_requantize_linear_right_shift_remainder:
beqz a4, esp32p4_s16_s16_requantize_linear_end
esp.ldqa.s16.128.xp a1, a4
srli a4, a4, 1
esp32p4_s16_128b_vector_shift_result q0, t3
dl_esp32p4_s16_store_remainder q0, a4, a5, a0
j esp32p4_s16_s16_requantize_linear_end
esp32p4_s16_s16_requantize_linear_left_shift:
addi t4, a2, 24
esp.vldbc.16.ip q1, t4, 0 // load output_scale
beqz a3, esp32p4_s16_s16_requantize_linear_left_shift_remainder
esp32p4_s16_s16_requantize_linear_left_shift_loop:
esp.vld.128.ip q0, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q1
esp32p4_s16_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
addi a3, a3, -1
bnez a3, esp32p4_s16_s16_requantize_linear_left_shift_loop
esp32p4_s16_s16_requantize_linear_left_shift_remainder:
beqz a4, esp32p4_s16_s16_requantize_linear_end
esp.vld.128.ip q0, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q1
esp32p4_s16_128b_vector_shift_result q0, t3
srli a4, a4, 1
dl_esp32p4_s16_store_remainder q0, a4, a5, a0
esp32p4_s16_s16_requantize_linear_end:
ret
.text
.align 2
.global dl_esp32p4_s16_s8_requantize_linear
.type dl_esp32p4_s16_s8_requantize_linear, @function
.balign 4
.option norvc
dl_esp32p4_s16_s8_requantize_linear:
# a0: int16_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: size_div_x
# a4: in_size_remainder
# a5: out_size_remainder
# t3: output_shift
# t4: output_scale
# t5:
# t6:
# a6(not for extension instructions): tmp value
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a3, 8(a2) // size_div_x
lw a4, 12(a2) // in_size_remainder
lw a5, 16(a2) // out_size_remainder
lw t3, 20(a2) // output_shift
lw t4, 24(a2) // output_scale
bgtz t4, esp32p4_s16_s8_requantize_linear_left_shift
beqz a3, esp32p4_s16_s8_requantize_linear_right_shift_remainder
srli a6, a3, 1
esp32p4_s16_s8_requantize_linear_right_shift_loop:
esp.vldext.s8.ip q0, q1, a1, 16
addi a6, a6, -1
esp.mov.s16.qacc q0
esp32p4_s16_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
esp.mov.s16.qacc q1
esp32p4_s16_128b_vector_shift_result q1, t3
esp.vst.128.ip q1, a0, 16
bnez a6, esp32p4_s16_s8_requantize_linear_right_shift_loop
esp32p4_s16_s8_requantize_linear_right_shift_remainder:
beqz a4, esp32p4_s16_s8_requantize_linear_end
li t0, 8
ble a4, t0, esp32p4_s16_s8_requantize_linear_right_shift_remainder_le8
esp.vldext.s8.xp q0, q1, a1, a4
srli a5, a5, 1
esp.mov.s16.qacc q0
esp32p4_s16_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
esp.mov.s16.qacc q1
esp32p4_s16_128b_vector_shift_result q1, t3
dl_esp32p4_s16_store_remainder q1, a5, a4, a0
j esp32p4_s16_s8_requantize_linear_end
esp32p4_s16_s8_requantize_linear_right_shift_remainder_le8:
esp.vldext.s8.xp q0, q1, a1, a4
esp.mov.s16.qacc q0
esp32p4_s16_128b_vector_shift_result q0, t3
dl_esp32p4_s16_store_remainder q0, a4, a5, a0
j esp32p4_s16_s8_requantize_linear_end
esp32p4_s16_s8_requantize_linear_left_shift:
addi t4, a2, 24
esp.vldbc.16.ip q2, t4, 0 // load output_scale
beqz a3, esp32p4_s16_s8_requantize_linear_left_shift_remainder
srli a6, a3, 1
esp32p4_s16_s8_requantize_linear_left_shift_loop:
esp.vldext.s8.ip q0, q1, a1, 16
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s16_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s16_128b_vector_shift_result q1, t3
esp.vst.128.ip q1, a0, 16
addi a6, a6, -1
bnez a6, esp32p4_s16_s8_requantize_linear_left_shift_loop
esp32p4_s16_s8_requantize_linear_left_shift_remainder:
beqz a4, esp32p4_s16_s8_requantize_linear_end
li t0, 8
ble a4, t0, esp32p4_s16_s8_requantize_linear_left_shift_remainder_le8
srli a5, a5, 1
esp.vldext.s8.xp q0, q1, a1, a4
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s16_128b_vector_shift_result q0, t3
esp.vst.128.ip q0, a0, 16
esp.zero.qacc
esp.vmulas.s16.qacc q1, q2
esp32p4_s16_128b_vector_shift_result q1, t3
dl_esp32p4_s16_store_remainder q1, a5, a4, a0
j esp32p4_s16_s8_requantize_linear_end
esp32p4_s16_s8_requantize_linear_left_shift_remainder_le8:
esp.vldext.s8.xp q0, q1, a1, a4
esp.zero.qacc
esp.vmulas.s16.qacc q0, q2
esp32p4_s16_128b_vector_shift_result q0, t3
dl_esp32p4_s16_store_remainder q0, a4, a5, a0
esp32p4_s16_s8_requantize_linear_end:
ret
|
georgevio/IoT-Embedded
| 14,136
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_sub.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_sub_w1_16_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_sub_w1_16_w2_16
.type dl_esp32p4_s8_sub_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_sub_w1_16_w2_16:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
esp32p4_s8_sub_w1_16_w2_16_loop:
beq t0, a3, esp32p4_s8_sub_w1_16_w2_16_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vsub.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_sub_w1_16_w2_16_loop
esp32p4_s8_sub_w1_16_w2_16_end:
ret
#void dl_esp32p4_s8_sub_w1_16_w2_1(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_sub_w1_16_w2_1
.type dl_esp32p4_s8_sub_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_sub_w1_16_w2_1:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q1, a2, 0
li t0, 0
esp32p4_s8_sub_w1_16_w2_1_loop:
beq t0, a3, esp32p4_s8_sub_w1_16_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vsub.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_sub_w1_16_w2_1_loop
esp32p4_s8_sub_w1_16_w2_1_end:
ret
#void dl_esp32p4_s8_sub_w1_1_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_sub_w1_1_w2_16
.type dl_esp32p4_s8_sub_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_sub_w1_1_w2_16:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q0, a1, 0
li t0, 0
esp32p4_s8_sub_w1_1_w2_16_loop:
beq t0, a3, esp32p4_s8_sub_w1_1_w2_16_end
esp.vld.128.ip q1, a2, 16
esp.vsub.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_sub_w1_1_w2_16_loop
esp32p4_s8_sub_w1_1_w2_16_end:
ret
.align 2
.text
.global dl_esp32p4_s8_sub_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_sub_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_sub_w1_16_w2_16_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vsub.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_sub_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_sub_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_sub_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_sub_w1_16_w2_1_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vsub.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_sub_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_sub_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_sub_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_sub_w1_1_w2_16_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q5, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vsub.s8 q2, q5, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vsub.s8 q2, q5, q2
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_sub_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 26,212
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_depthwise_conv2d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s16_depthwise_conv2d_33c1 series
####
############################################################################################################################################################
.macro esp32p4_s16_depthwise_conv2d_3381 input_v0, filter_v0, input_v1, filter_v1, input_v2, filter_v2, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, next_hw81
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(t)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(t)
# next_hw81 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(t) + 16
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s16.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s16.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \next_hw81
esp.vmulas.s16.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
.endm
.macro esp32p4_s16_depthwise_conv2d_3381_last input_v0, filter_v0, input_v1, filter_v1, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(t)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(t)
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_y_offset
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.ip \input_v0, \input_ptr, 0
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
# block one cycle here
esp.vmulas.s16.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s16_depthwise_conv2d_33c1_load_args args, filter_ptr, dilation_x_offset, dilation_y_offset, next_hw81, c_div_x_1, mac_shift
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(t)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(t)
# next_hw81 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(t) + 16
lw \filter_ptr, 48 (\args)
lw \dilation_x_offset, 124(\args)
lw \dilation_y_offset, 128(\args)
lw \next_hw81, 132(\args)
lw \c_div_x_1, 100(\args)
lw \mac_shift, 64 (\args)
.endm
.text
.align 2
.global dl_esp32p4_s16_depthwise_conv2d_33c1_bias
.type dl_esp32p4_s16_depthwise_conv2d_33c1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_depthwise_conv2d_33c1_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hw81
# t4: mac_shift
# t5: c_div_x_1
# t6: bias_ptr
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw t6, 68(a2) // bias
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t5, esp32p4_s16_depthwise_conv2d_33c1_bias_loop_last
// esp.lp.setup 0, t5, 1f
1:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp.vst.128.ip q3, a0, 16
addi t5, t5, -1
bgtz t5, 1b
esp32p4_s16_depthwise_conv2d_33c1_bias_loop_last:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s16_128b_vector_shift_result q3, t4
esp.vst.128.ip q3, a0, 16
ret
.text
.align 2
.global dl_esp32p4_s16_depthwise_conv2d_33c1_bias_relu
.type dl_esp32p4_s16_depthwise_conv2d_33c1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_depthwise_conv2d_33c1_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hw81
# t4: mac_shift
# t5: c_div_x_1
# t6: bias_ptr
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
esp32p4_push_8_stacks_2r s0, s1
esp32p4_s16_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw t6, 68(a2) // bias
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t5, esp32p4_s16_depthwise_conv2d_33c1_bias_relu_loop_last
// esp.lp.setup 0, t5, 1f
1:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp.vst.128.ip q3, a0, 16
addi t5, t5, -1
bgtz t5, 1b
esp32p4_s16_depthwise_conv2d_33c1_bias_relu_loop_last:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp.vst.128.ip q3, a0, 16
esp32p4_pop_8_stacks_2r s0, s1
ret
.text
.align 2
.global dl_esp32p4_s16_depthwise_conv2d_33c1
.type dl_esp32p4_s16_depthwise_conv2d_33c1, @function
.balign 4
.option norvc
dl_esp32p4_s16_depthwise_conv2d_33c1:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hw81
# t4: mac_shift
# t5: c_div_x_1
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t5, esp32p4_s16_depthwise_conv2d_33c1_loop_last
// esp.lp.setup 0, t5, 1f
1:
esp.zero.qacc
esp32p4_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp.vst.128.ip q3, a0, 16
addi t5, t5, -1
bgtz t5, 1b
esp32p4_s16_depthwise_conv2d_33c1_loop_last:
esp.zero.qacc
esp32p4_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s16_128b_vector_shift_result q3, t4
esp.vst.128.ip q3, a0, 16
ret
.text
.align 2
.global dl_esp32p4_s16_depthwise_conv2d_33c1_relu
.type dl_esp32p4_s16_depthwise_conv2d_33c1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_depthwise_conv2d_33c1_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hw81
# t4: mac_shift
# t5: c_div_x_1
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
esp32p4_push_8_stacks_2r s0, s1
esp32p4_s16_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
esp.vld.128.xp q0, a1, a4
esp.vld.128.ip q1, a3, 16
esp.vld.128.xp q2, a1, a4
beqz t5, esp32p4_s16_depthwise_conv2d_33c1_relu_loop_last
// esp.lp.setup 0, t5, 1f
1:
esp.zero.qacc
esp32p4_s16_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp.vst.128.ip q3, a0, 16
addi t5, t5, -1
bgtz t5, 1b
esp32p4_s16_depthwise_conv2d_33c1_relu_loop_last:
esp.zero.qacc
esp32p4_s16_depthwise_conv2d_3381_last q0, q1, q2, q3, a1, a3, a4, a5
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp.vst.128.ip q3, a0, 16
esp32p4_pop_8_stacks_2r s0, s1
ret
############################################################################################################################################################
####
#### esp32p4_s16_depthwise_conv2d_hwcn series
####
############################################################################################################################################################
.macro esp32p4_s16_depthwise_conv2d_1w81 input_v0, input_v1, input_v2, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, filter_w, filter_w_rs1_1, filter_y_offset, tmp
beqz \filter_w_rs1_1, 2f
// esp.lp.setup 0, \filter_w_rs1_1, (1f - 4)
mv \tmp, \filter_w_rs1_1
1:
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
addi \tmp, \tmp, -1
bgtz \tmp, 1b
2:
andi \tmp, \filter_w, 0xfffffffe
beq \filter_w, \tmp, 3f
# three 8-input-element left
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v2, \input_ptr, \dilation_y_offset
esp.vmulas.s16.qacc.ld.xp \filter_v2, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2 # block one cyle here
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
j 4f
3: # two 8-input-element left
esp.vmulas.s16.qacc.ld.xp \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \dilation_y_offset
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1 # block one cyle here
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
4:
.endm
.macro esp32p4_s16_depthwise_conv2d_1w81_last input_v0, input_v1, filter_v0, filter_v1, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, filter_w, filter_w_rs1_1, next_hw81, filter_y_offset, tmp
beqz \filter_w_rs1_1, 2f
// esp.lp.setup 0, \filter_w_rs1_1, (1f - 4)
mv \tmp, \filter_w_rs1_1
1:
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
addi \tmp, \tmp, -1
bgtz \tmp, 1b
2:
andi \tmp, \filter_w, 0xfffffffe
beq \filter_w, \tmp, 3f
# three 8-input-element left
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \next_hw81
esp.vmulas.s16.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v1
# block one cyle here
esp.vmulas.s16.qacc \input_v0, \filter_v0
j 4f
3: # two 8-input-element left
esp.vmulas.s16.qacc.ld.xp \filter_v1, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_x_offset
add \input_ptr, \input_ptr, \next_hw81
esp.vmulas.s16.qacc \input_v1, \filter_v1
4:
.endm
.macro esp32p4_s16_depthwise_conv2d_hw81 input_v0, input_v1, input_v2, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset, dilation_y_offset, next_hw81, filter_h, filter_w, filter_w_rs1_1, args, filter_y_offset, filter_n_offset, tmp
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(t)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(t)
# next_hw81 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(t) + 16
# filter_w_rs1_1
lw \filter_h, 52(\args) # filter_height
addi \tmp, \filter_w, -1
beqz \tmp, 9f
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.xp \input_v0, \input_ptr, \dilation_x_offset
esp.vld.128.xp \input_v1, \input_ptr, \dilation_x_offset
addi \filter_h, \filter_h, -1
beqz \filter_h, 8f
// esp.lp.setup 1, \filter_h, (7f - 4)
7:
esp32p4_s16_depthwise_conv2d_1w81 \input_v0, \input_v1, \input_v2, \filter_v0, \filter_v1, \filter_v2, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \filter_w, \filter_w_rs1_1, \filter_y_offset, \tmp
addi \filter_h, \filter_h, -1
bgtz \filter_h, 7b
8: # last y
esp32p4_s16_depthwise_conv2d_1w81_last \input_v0, \input_v1, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \filter_w, \filter_w_rs1_1, \next_hw81, \filter_y_offset, \tmp
j 12f
9: # filter_w == 1
esp.vld.128.xp \filter_v0, \filter_ptr, \filter_y_offset
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
beqz \filter_h, 11f
// esp.lp.setup 1, \filter_h, (10f - 4)
10:
esp.vmulas.s16.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.vld.128.xp \input_v0, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bgtz \filter_h, 10b
11: # last y
esp.vmulas.s16.qacc \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset
add \input_ptr, \input_ptr, \next_hw81
12:
add \filter_ptr, \filter_ptr, \filter_n_offset
.endm
.macro esp32p4_s16_depthwise_conv2d_hwc1_load_args args, filter_ptr, dilation_x_offset, dilation_y_offset, next_hw81, c_div_x_1, mac_shift, filter_w, filter_w_rs1_1
esp32p4_s16_depthwise_conv2d_33c1_load_args \args, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \next_hw81, \c_div_x_1, \mac_shift
lw \filter_w, 56(\args)
lw \filter_w_rs1_1, 148(\args)
.endm
.text
.align 2
.global dl_esp32p4_s16_depthwise_conv2d_hwc1_bias
.type dl_esp32p4_s16_depthwise_conv2d_hwc1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_depthwise_conv2d_hwc1_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hw81
# t4: mac_shift
# t5: filter_y_offset
# t6: bias_ptr
# a6(not for extension instructions): filter_w
# a7(not for extension instructions): filter_w_rs1_1
# t0(not for extension instructions): filter_n_offset
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): filter_h
# s2(not for extension instructions): tmp value
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_push_4_stacks_1r s2
esp32p4_s16_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t1, t4, a6, a7
lw t6, 68(a2) // bias
lw t5, 60 (a2) // filter_y_offset
lw t0, 144(a2) // filter_n_offset
esp32p4_s16_depthwise_conv2d_hwc1_bias_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, t2, a6, a7, a2, t5, t0, s2
esp32p4_s16_128b_vector_shift_result q0, t4
esp.vst.128.ip q0, a0, 16
addi t1, t1, -1
bgez t1, esp32p4_s16_depthwise_conv2d_hwc1_bias_loop
esp32p4_pop_4_stacks_1r s2
ret
.text
.align 2
.global dl_esp32p4_s16_depthwise_conv2d_hwc1_bias_relu
.type dl_esp32p4_s16_depthwise_conv2d_hwc1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_depthwise_conv2d_hwc1_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hw81
# t4: mac_shift
# t5: filter_y_offset
# t6: bias_ptr
# a6(not for extension instructions): filter_w
# a7(not for extension instructions): filter_w_rs1_1
# t0(not for extension instructions): filter_n_offset
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): filter_h
# s2(not for extension instructions): tmp value
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s2
esp32p4_s16_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t1, t4, a6, a7
lw t6, 68(a2) // bias
lw t5, 60 (a2) // filter_y_offset
lw t0, 144(a2) // filter_n_offset
lw s0, 76 (a2) // activation_alpha
lw s1, 84 (a2) // activation_shift
esp32p4_s16_depthwise_conv2d_hwc1_bias_relu_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, t2, a6, a7, a2, t5, t0, s2
esp32p4_s16_128b_vector_shift_result q0, t4
esp32p4_s16_128b_vector_relu q0, s0, s1
esp.vst.128.ip q0, a0, 16
addi t1, t1, -1
bgez t1, esp32p4_s16_depthwise_conv2d_hwc1_bias_relu_loop
esp32p4_pop_12_stacks_3r s0, s1, s2
ret
.text
.align 2
.global dl_esp32p4_s16_depthwise_conv2d_hwc1
.type dl_esp32p4_s16_depthwise_conv2d_hwc1, @function
.balign 4
.option norvc
dl_esp32p4_s16_depthwise_conv2d_hwc1:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hw81
# t4: mac_shift
# t5: filter_y_offset
# t6:
# a6(not for extension instructions): filter_w
# a7(not for extension instructions): filter_w_rs1_1
# t0(not for extension instructions): filter_n_offset
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): filter_h
# s2(not for extension instructions): tmp value
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_push_4_stacks_1r s2
esp32p4_s16_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t1, t4, a6, a7
lw t5, 60 (a2) // filter_y_offset
lw t0, 144(a2) // filter_n_offset
esp32p4_s16_depthwise_conv2d_hwc1_loop:
esp.zero.qacc
esp32p4_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, t2, a6, a7, a2, t5, t0, s2
esp32p4_s16_128b_vector_shift_result q0, t4
esp.vst.128.ip q0, a0, 16
addi t1, t1, -1
bgez t1, esp32p4_s16_depthwise_conv2d_hwc1_loop
esp32p4_pop_4_stacks_1r s2
ret
.text
.align 2
.global dl_esp32p4_s16_depthwise_conv2d_hwc1_relu
.type dl_esp32p4_s16_depthwise_conv2d_hwc1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_depthwise_conv2d_hwc1_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: input dilation x offset
# a5: input dilation y offset
# t3: next_hw81
# t4: mac_shift
# t5: filter_y_offset
# t6:
# a6(not for extension instructions): filter_w
# a7(not for extension instructions): filter_w_rs1_1
# t0(not for extension instructions): filter_n_offset
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): filter_h
# s2(not for extension instructions): tmp value
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s2
esp32p4_s16_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, t1, t4, a6, a7
lw t5, 60 (a2) // filter_y_offset
lw t0, 144(a2) // filter_n_offset
lw s0, 76 (a2) // activation_alpha
lw s1, 84 (a2) // activation_shift
esp32p4_s16_depthwise_conv2d_hwc1_relu_loop:
esp.zero.qacc
esp32p4_s16_depthwise_conv2d_hw81 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3, t2, a6, a7, a2, t5, t0, s2
esp32p4_s16_128b_vector_shift_result q0, t4
esp32p4_s16_128b_vector_relu q0, s0, s1
esp.vst.128.ip q0, a0, 16
addi t1, t1, -1
bgez t1, esp32p4_s16_depthwise_conv2d_hwc1_relu_loop
esp32p4_pop_12_stacks_3r s0, s1, s2
ret
|
georgevio/IoT-Embedded
| 14,598
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_and4d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand
.type dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand, @function
#.section .iram1
dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.andq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand
.type dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand, @function
#.section .iram1
dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.16.ip q1, a2, 0
esp.andq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand
.type dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand, @function
#.section .iram1
dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.16.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.andq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned
.type dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned, @function
#.section .iram1
dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_remainder
dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_and4d_bchw_w1_8_w2_8_simdand_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.andq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned
.type dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned, @function
#.section .iram1
dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.andq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.andq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.andq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_remainder
dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a2, 0
dl_esp32p4_s16_and4d_bchw_w1_8_w2_1_simdand_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.andq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned
.type dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned, @function
#.section .iram1
dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a2: int16_t *input0_ptr
# a1: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.andq q2, q5, q2 #esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.andq q2, q5, q2 #esp.andq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.andq q2, q5, q2 #esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.andq q2, q5, q2 #esp.andq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.andq q2, q5, q2 #esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.andq q2, q5, q2 #esp.andq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_remainder
dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a1, 0
dl_esp32p4_s16_and4d_bchw_w1_1_w2_8_simdand_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_endtest
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.andq q2, q5, q2 #esp.andq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_endtest:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 69,234
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_unaligned_depthwise_conv2d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s16_unaligned_depthwise_conv2d_33c1 series
####
############################################################################################################################################################
.macro esp32p4_s16_unaligned_depthwise_conv2d_3381 input_v0, input_v1, input_v2, input_back, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_3381_16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \next_3381_16
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_3381_last input_v0, input_v1, input_v2, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_3381_16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v2, \filter_v0
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v1
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v1, \filter_v0
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v1
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \next_3381_16
esp.vmulas.s16.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q \input_v2, \input_v2, \input_back
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vmulas.s16.qacc \input_v2, \filter_v0
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_11r1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_remainder, forward
esp.ld.128.usar.xp \input_v0, \input_ptr, \c_remainder
esp.vld.128.xp \input_back, \input_ptr, \forward
esp.src.q \input_v0, \input_v0, \input_back
esp.ld.128.usar.xp \filter_v0, \filter_ptr, \c_remainder
esp.vld.128.ip \filter_back, \filter_ptr, 0
esp.src.q \filter_v0, \filter_v0, \filter_back
esp.vmulas.s16.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_33r1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, dilation_x_offset_c_remainder, dilation_y_offset_c_remainder, c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
// esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder
esp.ld.128.usar.xp \input_v0, \input_ptr, \c_remainder
esp.vld.128.ip \input_back, \input_ptr, 0
esp.src.q \input_v0, \input_v0, \input_back
esp.ld.128.usar.xp \filter_v0, \filter_ptr, \c_remainder
esp.vld.128.ip \filter_back, \filter_ptr, 0
esp.src.q \filter_v0, \filter_v0, \filter_back
esp.vmulas.s16.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_33c1_load_args args, filter_ptr, dilation_x_offset, dilation_y_offset, next_hwx1, c_div_x_1, mac_shift
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hwx1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
lw \filter_ptr, 48(\args)
lw \dilation_x_offset, 124(\args)
lw \dilation_y_offset, 128(\args)
lw \next_hwx1, 132(\args)
lw \c_div_x_1, 100(\args)
lw \mac_shift, 64 (\args)
.endm
.text
.align 2
.global dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias
.type dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: dilation_x_offset - 16 / dilation_x_offset - c_remainder
# a5: dilation_y_offset - 16 / dilation_y_offset - c_remainder
# t3: next_3381 - 16
# t4: mac_shift
# t5: c_div_x_1 / c_remainder
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): tmp value / moving c_div_x_1
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8: bias_ptr
# s9:
# s10:
# s11:
esp32p4_push_4_stacks_1r s8
esp32p4_s16_unaligned_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw s8, 68(a2) // bias
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
addi t3, t3, -16 // t3: next_3381 - 16
bltz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q4, a3, 16, q0, q3 // q4: filter_v0; q0: input_v0
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q2, a1, 16, q1, q3 // q2: input_v2; q1: input_v1
beqz t6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_128b
li a6, 8
beq t6, a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_64b
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_32b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_32b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_32b_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_32b_unaligned_vector_store q3, a0, t6
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_32b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_32b_last:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_32b_unaligned_vector_store q3, a0, t6
j esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_64b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_64b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_64b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_64b_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_64b_unaligned_vector_store q3, a0
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_64b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_64b_last:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_64b_unaligned_vector_store q3, a0
j esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_128b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_128b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_128b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_128b_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_aligned_vector_store q3, a0
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_128b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_128b_last:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_aligned_vector_store q3, a0
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder:
lw t5, 136(a2) // t5: c_remainder
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder_end
esp.zero.qacc
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t5 // a4: dilation_x_offset - c_remainder
sub a5, a5, t5 // a5: dilation_y_offset - c_remainder
srli t0, t5, 1
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t5
esp32p4_s16_128b_vector_shift_result q0, t4
dl_esp32p4_s16_store_remainder q0, t0, t6, a0
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_c_remainder_end:
esp32p4_pop_4_stacks_1r s8
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu
.type dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: dilation_x_offset - 16 / dilation_x_offset - c_remainder
# a5: dilation_y_offset - 16 / dilation_y_offset - c_remainder
# t3: next_3381 - 16
# t4: mac_shift
# t5: c_div_x_1 / c_remainder
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): tmp value / moving c_div_x_1
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8: bias_ptr
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8
esp32p4_s16_unaligned_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw s8, 68(a2) // bias
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
addi t3, t3, -16 // t3: next_3381 - 16
bltz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q4, a3, 16, q0, q3 // q4: filter_v0; q0: input_v0
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q2, a1, 16, q1, q3 // q2: input_v2; q1: input_v1
beqz t6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b
li a6, 8
beq t6, a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_32b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_32b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_32b_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_32b_unaligned_vector_store q3, a0, t6
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_32b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_32b_last:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_32b_unaligned_vector_store q3, a0, t6
j esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_64b_unaligned_vector_store q3, a0
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_64b_last:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_64b_unaligned_vector_store q3, a0
j esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_128b_aligned_vector_store q3, a0
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_128b_last:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_128b_aligned_vector_store q3, a0
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder:
lw t5, 136(a2) // t5: c_remainder
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder_end
esp.zero.qacc
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t5 // a4: dilation_x_offset - c_remainder
sub a5, a5, t5 // a5: dilation_y_offset - c_remainder
srli t0, t5, 1
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t5
esp32p4_s16_128b_vector_shift_result q0, t4
esp32p4_s16_128b_vector_relu q0, s0, s1
dl_esp32p4_s16_store_remainder q0, t0, t6, a0
esp32p4_s16_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1
.type dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: dilation_x_offset - 16 / dilation_x_offset - c_remainder
# a5: dilation_y_offset - 16 / dilation_y_offset - c_remainder
# t3: next_3381 - 16
# t4: mac_shift
# t5: c_div_x_1 / c_remainder
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): tmp value / moving c_div_x_1
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_unaligned_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
addi t3, t3, -16 // t3: next_3381 - 16
bltz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_c_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q4, a3, 16, q0, q3 // q4: filter_v0; q0: input_v0
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q2, a1, 16, q1, q3 // q2: input_v2; q1: input_v1
beqz t6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_128b
li a6, 8
beq t6, a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_64b
# esp32p4_s16_unaligned_depthwise_conv2d_33c1_32b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_32b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_32b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_32b_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_32b_unaligned_vector_store q3, a0, t6
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_32b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_32b_last:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_32b_unaligned_vector_store q3, a0, t6
j esp32p4_s16_unaligned_depthwise_conv2d_33c1_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_33c1_64b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_64b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_64b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_64b_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_64b_unaligned_vector_store q3, a0
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_64b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_64b_last:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_64b_unaligned_vector_store q3, a0
j esp32p4_s16_unaligned_depthwise_conv2d_33c1_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_33c1_128b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_128b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_128b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_128b_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_aligned_vector_store q3, a0
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_128b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_128b_last:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_aligned_vector_store q3, a0
esp32p4_s16_unaligned_depthwise_conv2d_33c1_c_remainder:
lw t5, 136(a2) // t5: c_remainder
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_c_remainder_end
esp.zero.qacc
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t5 // a4: dilation_x_offset - c_remainder
sub a5, a5, t5 // a5: dilation_y_offset - c_remainder
srli t0, t5, 1
esp32p4_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t5
esp32p4_s16_128b_vector_shift_result q0, t4
dl_esp32p4_s16_store_remainder q0, t0, t6, a0
esp32p4_s16_unaligned_depthwise_conv2d_33c1_c_remainder_end:
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu
.type dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: dilation_x_offset - 16 / dilation_x_offset - c_remainder
# a5: dilation_y_offset - 16 / dilation_y_offset - c_remainder
# t3: next_3381 - 16
# t4: mac_shift
# t5: c_div_x_1 / c_remainder
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): tmp value / moving c_div_x_1
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
esp32p4_push_8_stacks_2r s0, s1
esp32p4_s16_unaligned_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
addi t3, t3, -16 // t3: next_3381 - 16
bltz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q4, a3, 16, q0, q3 // q4: filter_v0; q0: input_v0
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q2, a1, 16, q1, q3 // q2: input_v2; q1: input_v1
beqz t6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_128b
li a6, 8
beq t6, a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_64b
# esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_32b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_32b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_32b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_32b_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_32b_unaligned_vector_store q3, a0, t6
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_32b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_32b_last:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_32b_unaligned_vector_store q3, a0, t6
j esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_64b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_64b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_64b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_64b_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_64b_unaligned_vector_store q3, a0
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_64b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_64b_last:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_64b_unaligned_vector_store q3, a0
j esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_128b:
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_128b_last
// esp.lp.setup 0, t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_128b_loop_end
mv a6, t5
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_128b_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_128b_aligned_vector_store q3, a0
addi a6, a6, -1
bgtz a6, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_128b_loop
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_128b_last:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_3381_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s16_128b_vector_shift_result q3, t4
esp32p4_s16_128b_vector_relu q3, s0, s1
esp32p4_s16_128b_aligned_vector_store q3, a0
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder:
lw t5, 136(a2) // t5: c_remainder
beqz t5, esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder_end
esp.zero.qacc
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t5 // a4: dilation_x_offset - c_remainder
sub a5, a5, t5 // a5: dilation_y_offset - c_remainder
srli t0, t5, 1
esp32p4_s16_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t5
esp32p4_s16_128b_vector_shift_result q0, t4
esp32p4_s16_128b_vector_relu q0, s0, s1
dl_esp32p4_s16_store_remainder q0, t0, t6, a0
esp32p4_s16_unaligned_depthwise_conv2d_33c1_relu_c_remainder_end:
esp32p4_pop_8_stacks_2r s0, s1
ret
############################################################################################################################################################
####
#### esp32p4_s16_unaligned_depthwise_conv2d_hwc1 series
####
############################################################################################################################################################
.macro esp32p4_s16_unaligned_depthwise_conv2d_1w81 input_v0, input_v1, input_back, input_ptr, filter_v0, filter_ptr, dilation_x_offset_16, dilation_y_offset, filter_w, filter_w_rs1_1, filter_y_offset, temp
blez \filter_w_rs1_1, 1f
// esp.lp.setup 0, \filter_w_rs1_1, 0f
mv \temp, \filter_w_rs1_1
0:
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
addi \temp, \temp, -1
bgtz \temp, 0b
1:
andi \temp, \filter_w, 0xfffffffe
beq \filter_w, \temp, 2f
# three 8-input-element left
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset
esp.vmulas.s16.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v0
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q \input_v0, \input_v1, \input_back
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
j 3f
2: # two 8-input-element left
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset
esp.vmulas.s16.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
3:
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_1w81_last input_v0, input_v1, input_back, input_ptr, filter_v0, filter_ptr, dilation_x_offset_16, filter_w, filter_w_rs1_1, next_hws1, filter_y_offset, temp
blez \filter_w_rs1_1, 5f
// esp.lp.setup 0, \filter_w_rs1_1, 4f
mv \temp, \filter_w_rs1_1
4:
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
addi \temp, \temp, -1
bgtz \temp, 4b
5:
andi \temp, \filter_w, 0xfffffffe
beq \filter_w, \temp, 6f
# three 8-input-element left
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s16.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \next_hws1
esp.vmulas.s16.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v0
esp.src.q \input_v0, \input_v0, \input_back
esp.vmulas.s16.qacc \input_v0, \filter_v0
j 7f
6: # two 8-input-element left
esp.ld.128.usar.xp \input_back, \input_ptr, \next_hws1
esp.vmulas.s16.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.src.q \input_v1, \input_v1, \input_back
esp.vmulas.s16.qacc \input_v1, \filter_v0
7:
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_hw81 input_v0, input_v1, input_back, filter_v0, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_hws1, filter_h, filter_w, filter_w_rs1_1, args, filter_y_offset, filter_n_offset, temp
lw \filter_h, 52(\args) # filter_height
lw \filter_w, 56(\args) # filter_width
addi \temp, \filter_w, -1
beqz \temp, 10f
# filter_w >= 2
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vld.128.ip \filter_v0, \filter_ptr, 16 # filter_v0
esp.src.q \input_v0, \input_v1, \input_back # input_v0
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
addi \filter_h, \filter_h, -1
beqz \filter_h, 9f
8:
esp32p4_s16_unaligned_depthwise_conv2d_1w81 \input_v0, \input_v1, \input_back, \input_ptr, \filter_v0, \filter_ptr, \dilation_x_offset_16, \dilation_y_offset_16, \filter_w, \filter_w_rs1_1, \filter_y_offset, \temp
addi \filter_h, \filter_h, -1
bgtz \filter_h, 8b
9: # last y
esp32p4_s16_unaligned_depthwise_conv2d_1w81_last \input_v0, \input_v1, \input_back, \input_ptr, \filter_v0, \filter_ptr, \dilation_x_offset_16, \filter_w, \filter_w_rs1_1, \next_hws1, \filter_y_offset, \temp
j 13f
10: # filter_w == 1
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vld.128.xp \filter_v0, \filter_ptr, \filter_y_offset # filter_v0
esp.src.q \input_v0, \input_v1, \input_back # input_v0
addi \filter_h, \filter_h, -1
beqz \filter_h, 12f
// esp.lp.setup 0, \filter_h, 11f
11:
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s16.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.src.q \input_v0, \input_v1, \input_back
addi \filter_h, \filter_h, -1
bgtz \filter_h, 11b
12: # last y
esp.vmulas.s16.qacc \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset_16
add \input_ptr, \input_ptr, \next_hws1
13:
add \filter_ptr, \filter_ptr, \filter_n_offset
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_11r1_padding input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_remainder, forward, filter_y_offset
esp.ld.128.usar.xp \input_v0, \input_ptr, \c_remainder
esp.vld.128.xp \input_back, \input_ptr, \forward
esp.src.q \input_v0, \input_v0, \input_back
esp.ld.128.usar.xp \filter_v0, \filter_ptr, \c_remainder
esp.vld.128.xp \filter_back, \filter_ptr, \filter_y_offset
esp.src.q \filter_v0, \filter_v0, \filter_back
esp.vmulas.s16.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_hwr1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, dilation_x_offset_c_remainder, dilation_y_offset_c_remainder, filter_h, filter_w, filter_w_rs1_1, c_remainder, args, filter_y_offset, temp
lw \filter_h, 52(\args) # filter_height
lw \filter_w, 56(\args) # filter_width
addi \temp, \filter_w, -1
beqz \temp, 5f
4:
beqz \filter_w_rs1_1, 1f
// esp.lp.setup 0, \filter_w_rs1_1, 1f
mv \temp, \filter_w_rs1_1
0:
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
addi \temp, \temp, -1
bgtz \temp, 0b
1:
andi \temp, \filter_w, 0xfffffffe
beq \temp, \filter_w, 2f
# 3 left
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder, \filter_y_offset
j 3f
2:
# 2 left
esp32p4_s16_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder, \filter_y_offset
3:
addi \filter_h, \filter_h, -1
// blt x0, \filter_h, 4b
bgtz \filter_h, 4b
j 7f
5:
# filter_w == 1
beqz \filter_h, 7f
// esp.lp.setup 0, \filter_h, 6f
mv \temp, \filter_h
6:
esp32p4_s16_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder, \filter_y_offset
addi \temp, \temp, -1
bgtz \temp, 6b
7:
.endm
.macro esp32p4_s16_unaligned_depthwise_conv2d_hwc1_load_args args, filter_ptr, dilation_x_offset, dilation_y_offset, next_hwx1, c_div_x_1, mac_shift, filter_w, filter_w_rs1_1
esp32p4_s16_unaligned_depthwise_conv2d_33c1_load_args \args, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \next_hwx1, \c_div_x_1, \mac_shift
lw \filter_w, 56(\args)
lw \filter_w_rs1_1, 148(\args)
.endm
.text
.align 2
.global dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias
.type dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr / unaligned_filter_ptr
# a4: dilation_x_offset - 16 / dilation_x_offset - c_remainder
# a5: dilation_y_offset - 16 / dilation_y_offset - c_remainder
# t3: next_hw81 - 16 / c_remainder
# t4: filter_y_offset / unaligned_filter_y_offset
# t5: mac_shift
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): filter_n_offset / c_remainder number
# a7(not for extension instructions): c_div_x_1
# t0(not for extension instructions): filter_h
# t1(not for extension instructions): filter_w
# t2(not for extension instructions): filter_w_rs1_1
# s2(not for extension instructions): tmp value
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8: bias_ptr
# s9:
# s10:
# s11:
esp32p4_push_8_stacks_2r s2, s8
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, a7, t5, t1, t2
lw s8, 68(a2) // bias
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
lw a6, 144(a2) // a6: filter_n_offset
bltz a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
esp.ld.128.usar.ip q0, a0, 0
addi t3, t3, -16 // t3: next_hw81 - 16
lw t4, 60(a2) // t4: filter_y_offset
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_c_div_x:
beqz t6, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_128b
li s2, 8
beq t6, s2, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_64b
# esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_32b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_32b_multiple_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_32b_unaligned_vector_store q0, a0, t6
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_32b_multiple_loop
j esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_64b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_64b_multiple_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_64b_multiple_loop
j esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_128b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_128b_multiple_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_aligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_128b_multiple_loop
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder:
lw t3, 136(a2) // t3: c_remainder
beqz t3, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder_end
esp.zero.qacc
srli a6, t3, 1
lw a3, 168(a2) // a3: unaligned_filter_ptr
lw t4, 160(a2) // t4: unaligned_filter_y_offset
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t3 // a4: dilation_x_offset - c_remainder
sub a5, a5, t3 // a5: dilation_y_offset - c_remainder
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t0, t1, t2, t3, a2, t4, t6
esp32p4_s16_128b_vector_shift_result q0, t5
dl_esp32p4_s16_store_remainder q0, a6, t6, a0
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_c_remainder_end:
esp32p4_pop_8_stacks_2r s2, s8
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu
.type dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr / unaligned_filter_ptr
# a4: dilation_x_offset - 16 / dilation_x_offset - c_remainder
# a5: dilation_y_offset - 16 / dilation_y_offset - c_remainder
# t3: next_hw81 - 16 / c_remainder
# t4: filter_y_offset / unaligned_filter_y_offset
# t5: mac_shift
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): filter_n_offset / c_remainder number
# a7(not for extension instructions): c_div_x_1
# t0(not for extension instructions): filter_h
# t1(not for extension instructions): filter_w
# t2(not for extension instructions): filter_w_rs1_1
# s2(not for extension instructions): tmp value
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8: bias_ptr
# s9:
# s10:
# s11:
esp32p4_push_16_stacks_4r s0, s1, s2, s8
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, a7, t5, t1, t2
lw s8, 68(a2) // bias
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
lw a6, 144(a2) // a6: filter_n_offset
bltz a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
esp.ld.128.usar.ip q0, a0, 0
addi t3, t3, -16 // t3: next_hw81 - 16
lw t4, 60(a2) // t4: filter_y_offset
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_div_x:
beqz t6, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_128b
li s2, 8
beq t6, s2, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_64b
# esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_32b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_32b_multiple_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_vector_relu q0, s0, s1
esp32p4_s16_32b_unaligned_vector_store q0, a0, t6
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_32b_multiple_loop
j esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_64b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_64b_multiple_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_vector_relu q0, s0, s1
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_64b_multiple_loop
j esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_128b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_128b_multiple_loop:
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_vector_relu q0, s0, s1
esp32p4_s16_128b_aligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_128b_multiple_loop
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder:
lw t3, 136(a2) // t3: c_remainder
beqz t3, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder_end
esp.zero.qacc
srli a6, t3, 1
lw a3, 168(a2) // a3: unaligned_filter_ptr
lw t4, 160(a2) // t4: unaligned_filter_y_offset
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t3 // a4: dilation_x_offset - c_remainder
sub a5, a5, t3 // a5: dilation_y_offset - c_remainder
esp32p4_s16_conv2d_128b_vector_bias s8
esp32p4_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t0, t1, t2, t3, a2, t4, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_vector_relu q0, s0, s1
dl_esp32p4_s16_store_remainder q0, a6, t6, a0
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder_end:
esp32p4_pop_16_stacks_4r s0, s1, s2, s8
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1
.type dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr / unaligned_filter_ptr
# a4: dilation_x_offset - 16 / dilation_x_offset - c_remainder
# a5: dilation_y_offset - 16 / dilation_y_offset - c_remainder
# t3: next_hw81 - 16 / c_remainder
# t4: filter_y_offset / unaligned_filter_y_offset
# t5: mac_shift
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): filter_n_offset / c_remainder number
# a7(not for extension instructions): c_div_x_1
# t0(not for extension instructions): filter_h
# t1(not for extension instructions): filter_w
# t2(not for extension instructions): filter_w_rs1_1
# s2(not for extension instructions): tmp value
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_push_4_stacks_1r s2
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, a7, t5, t1, t2
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
lw a6, 144(a2) // a6: filter_n_offset
bltz a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_c_remainder
esp.ld.128.usar.ip q0, a0, 0
addi t3, t3, -16 // t3: next_hw81 - 16
lw t4, 60(a2) // t4: filter_y_offset
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_c_div_x:
beqz t6, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_128b
li s2, 8
beq t6, s2, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_64b
# esp32p4_s16_unaligned_depthwise_conv2d_hwc1_32b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_32b_multiple_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_32b_unaligned_vector_store q0, a0, t6
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_32b_multiple_loop
j esp32p4_s16_unaligned_depthwise_conv2d_hwc1_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_64b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_64b_multiple_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_64b_multiple_loop
j esp32p4_s16_unaligned_depthwise_conv2d_hwc1_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_128b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_128b_multiple_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_aligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_128b_multiple_loop
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_c_remainder:
lw t3, 136(a2) // t3: c_remainder
beqz t3, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_c_remainder_end
esp.zero.qacc
srli a6, t3, 1
lw a3, 168(a2) // a3: unaligned_filter_ptr
lw t4, 160(a2) // t4: unaligned_filter_y_offset
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t3 // a4: dilation_x_offset - c_remainder
sub a5, a5, t3 // a5: dilation_y_offset - c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t0, t1, t2, t3, a2, t4, t6
esp32p4_s16_128b_vector_shift_result q0, t5
dl_esp32p4_s16_store_remainder q0, a6, t6, a0
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_c_remainder_end:
esp32p4_pop_4_stacks_1r s2
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu
.type dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr / unaligned_filter_ptr
# a4: dilation_x_offset - 16 / dilation_x_offset - c_remainder
# a5: dilation_y_offset - 16 / dilation_y_offset - c_remainder
# t3: next_hw81 - 16 / c_remainder
# t4: filter_y_offset / unaligned_filter_y_offset
# t5: mac_shift
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): filter_n_offset / c_remainder number
# a7(not for extension instructions): c_div_x_1
# t0(not for extension instructions): filter_h
# t1(not for extension instructions): filter_w
# t2(not for extension instructions): filter_w_rs1_1
# s2(not for extension instructions): tmp value
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s2
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, a7, t5, t1, t2
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
lw a6, 144(a2) // a6: filter_n_offset
bltz a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
esp.ld.128.usar.ip q0, a0, 0
addi t3, t3, -16 // t3: next_hw81 - 16
lw t4, 60(a2) // t4: filter_y_offset
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_c_div_x:
beqz t6, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_128b
li s2, 8
beq t6, s2, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_64b
# esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_32b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_32b_multiple_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_vector_relu q0, s0, s1
esp32p4_s16_32b_unaligned_vector_store q0, a0, t6
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_32b_multiple_loop
j esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_64b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_64b_multiple_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_vector_relu q0, s0, s1
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_64b_multiple_loop
j esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_128b:
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_128b_multiple_loop:
esp.zero.qacc
esp32p4_s16_unaligned_depthwise_conv2d_hw81 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_vector_relu q0, s0, s1
esp32p4_s16_128b_aligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_128b_multiple_loop
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder:
lw t3, 136(a2) // t3: c_remainder
beqz t3, esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder_end
esp.zero.qacc
srli a6, t3, 1
lw a3, 168(a2) // a3: unaligned_filter_ptr
lw t4, 160(a2) // t4: unaligned_filter_y_offset
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t3 // a4: dilation_x_offset - c_remainder
sub a5, a5, t3 // a5: dilation_y_offset - c_remainder
esp32p4_s16_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t0, t1, t2, t3, a2, t4, t6
esp32p4_s16_128b_vector_shift_result q0, t5
esp32p4_s16_128b_vector_relu q0, s0, s1
dl_esp32p4_s16_store_remainder q0, a6, t6, a0
esp32p4_s16_unaligned_depthwise_conv2d_hwc1_relu_c_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s2
ret
|
georgevio/IoT-Embedded
| 65,977
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_unaligned_depthwise_conv2d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s8_unaligned_depthwise_conv2d_33c1 series
####
############################################################################################################################################################
.macro esp32p4_s8_unaligned_depthwise_conv2d_33s1 input_v0, input_v1, input_v2, input_back, filter_v0, filter_v1, filter_v2, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_33s1_16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \next_33s1_16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v2, \filter_ptr, 16, \input_v1, \filter_v1
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v2
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_33s1_last input_v0, input_v1, input_v2, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_33s1_16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v2, \filter_v0
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v1
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v2, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v1, \filter_v0
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v2, \filter_v1
esp.src.q.ld.ip \input_v2, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \next_33s1_16
esp.vmulas.s8.qacc.ld.ip \filter_v1, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q \input_v2, \input_v2, \input_back
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v1
esp.vmulas.s8.qacc \input_v2, \filter_v0
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_11r1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_remainder, forward
esp.ld.128.usar.xp \input_v0, \input_ptr, \c_remainder
esp.vld.128.xp \input_back, \input_ptr, \forward
esp.src.q \input_v0, \input_v0, \input_back
esp.ld.128.usar.xp \filter_v0, \filter_ptr, \c_remainder
esp.vld.128.ip \filter_back, \filter_ptr, 0
esp.src.q \filter_v0, \filter_v0, \filter_back
esp.vmulas.s8.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_33r1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, dilation_x_offset_c_remainder, dilation_y_offset_c_remainder, c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
// esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder
esp.ld.128.usar.xp \input_v0, \input_ptr, \c_remainder
esp.vld.128.ip \input_back, \input_ptr, 0
esp.src.q \input_v0, \input_v0, \input_back
esp.ld.128.usar.xp \filter_v0, \filter_ptr, \c_remainder
esp.vld.128.ip \filter_back, \filter_ptr, 0
esp.src.q \filter_v0, \filter_v0, \filter_back
esp.vmulas.s8.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_33c1_load_args args, filter_ptr, dilation_x_offset, dilation_y_offset, next_hwx1, c_div_x_1, mac_shift
# dilation_x_offset = input_channel_with_padding * dilation_x * sizeof(T)
# dilation_y_offset = (-(filter_width - 1) * dilation_x * input_channel_with_padding + dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T)
# next_hwx1 = (-(filter_width - 1) * dilation_x * input_channel_with_padding - (filter_height - 1) * dilation_y * input_width_with_padding * input_channel_with_padding) * sizeof(T) + 16
lw \filter_ptr, 48(\args)
lw \dilation_x_offset, 124(\args)
lw \dilation_y_offset, 128(\args)
lw \next_hwx1, 132(\args)
lw \c_div_x_1, 100(\args)
lw \mac_shift, 64 (\args)
.endm
.text
.align 2
.global dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias
.type dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr / tmp value
# a4: input dilation x offset / tmp value
# a5: input dilation y offset / tmp value
# t3: next_33s1 / tmp value
# t4: mac_shift
# t5: c_div_x_1 / c_remainder
# t6: output_sar_byte
# a6(not for extension instructions): tmp value
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8: bias_ptr
# s9:
# s10:
# s11:
esp32p4_push_4_stacks_1r s8
esp32p4_s8_unaligned_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw s8, 68(a2) // bias
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
addi t3, t3, -16 // t3: next_33s1 - 16
bltz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_c_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q4, a3, 16, q0, q3 // q4: filter_v0; q0: input_v0
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q2, a1, 16, q1, q3 // q2: input_v2; q1: input_v1
beqz t6, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_128b
li a6, 8
beq t6, a6, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_64b
// esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_32b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_32b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_32b_loop_end
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_32b_unaligned_vector_store q3, a0, t6
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_32b_loop_end:
nop
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_32b_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_32b_unaligned_vector_store q3, a0, t6
j esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_64b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_64b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_64b_loop_end
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_64b_unaligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_64b_loop_end:
nop
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_64b_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_64b_unaligned_vector_store q3, a0
j esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_128b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_128b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_128b_loop_end
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_128b_loop_end:
esp32p4_s8_128b_aligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_128b_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_aligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_c_remainder:
lw t5, 136(a2) // t5: c_remainder
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_c_remainder_end
esp.zero.qacc
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t5 // a4: dilation_x_offset - c_remainder
sub a5, a5, t5 // a5: dilation_y_offset - c_remainder
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t5
esp32p4_s8_128b_vector_shift_result q0, t4
dl_esp32p4_s8_store_remainder q0, a3, a4, a5, t3, t0, a0, t5
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_c_remainder_end:
esp32p4_pop_4_stacks_1r s8
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu
.type dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr / tmp value
# a4: input dilation x offset / tmp value
# a5: input dilation y offset / tmp value
# t3: next_33s1 / tmp value
# t4: mac_shift
# t5: c_div_x_1 / c_remainder
# t6: output_sar_byte
# a6(not for extension instructions): tmp value
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8: bias_ptr
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8
esp32p4_s8_unaligned_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
lw s8, 68(a2) // bias
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
addi t3, t3, -16 // t3: next_33s1 - 16
bltz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q4, a3, 16, q0, q3 // q4: filter_v0; q0: input_v0
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q2, a1, 16, q1, q3 // q2: input_v2; q1: input_v1
beqz t6, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_128b
li a6, 8
beq t6, a6, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_64b
// esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_32b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_32b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_32b_loop_end
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_32b_unaligned_vector_store q3, a0, t6
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_32b_loop_end:
nop
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_32b_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_32b_unaligned_vector_store q3, a0, t6
j esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_64b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_64b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_64b_loop_end
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_64b_unaligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_64b_loop_end:
nop
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_64b_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_64b_unaligned_vector_store q3, a0
j esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_128b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_128b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_128b_loop_end
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_128b_loop_end:
esp32p4_s8_128b_aligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_128b_last:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_128b_aligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder:
lw t5, 136(a2) // t5: c_remainder
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder_end
esp.zero.qacc
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t5 // a4: dilation_x_offset - c_remainder
sub a5, a5, t5 // a5: dilation_y_offset - c_remainder
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t5
esp32p4_s8_128b_vector_shift_result q0, t4
esp32p4_s8_128b_vector_relu q0, s0, s1
dl_esp32p4_s8_store_remainder q0, a3, a4, a5, t3, t0, a0, t5
esp32p4_s8_unaligned_depthwise_conv2d_33c1_bias_relu_c_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1
.type dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr / tmp value
# a4: input dilation x offset / tmp value
# a5: input dilation y offset / tmp value
# t3: next_33s1 / tmp value
# t4: mac_shift
# t5: c_div_x_1 / c_remainder
# t6: output_sar_byte
# a6(not for extension instructions): tmp value
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s8_unaligned_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
addi t3, t3, -16 // t3: next_33s1 - 16
bltz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_c_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q4, a3, 16, q0, q3 // q4: filter_v0; q0: input_v0
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q2, a1, 16, q1, q3 // q2: input_v2; q1: input_v1
beqz t6, esp32p4_s8_unaligned_depthwise_conv2d_33c1_128b
li a6, 8
beq t6, a6, esp32p4_s8_unaligned_depthwise_conv2d_33c1_64b
// esp32p4_s8_unaligned_depthwise_conv2d_33c1_32b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_32b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_32b_loop_end
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_32b_unaligned_vector_store q3, a0, t6
esp32p4_s8_unaligned_depthwise_conv2d_33c1_32b_loop_end:
nop
esp32p4_s8_unaligned_depthwise_conv2d_33c1_32b_last:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_32b_unaligned_vector_store q3, a0, t6
j esp32p4_s8_unaligned_depthwise_conv2d_33c1_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33c1_64b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_64b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_64b_loop_end
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_64b_unaligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_64b_loop_end:
nop
esp32p4_s8_unaligned_depthwise_conv2d_33c1_64b_last:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_64b_unaligned_vector_store q3, a0
j esp32p4_s8_unaligned_depthwise_conv2d_33c1_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33c1_128b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_128b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_128b_loop_end
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_unaligned_depthwise_conv2d_33c1_128b_loop_end:
esp32p4_s8_128b_aligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_128b_last:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_aligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_c_remainder:
lw t5, 136(a2) // t5: c_remainder
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_c_remainder_end
esp.zero.qacc
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t5 // a4: dilation_x_offset - c_remainder
sub a5, a5, t5 // a5: dilation_y_offset - c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t5
esp32p4_s8_128b_vector_shift_result q0, t4
dl_esp32p4_s8_store_remainder q0, a3, a4, a5, t3, t0, a0, t5
esp32p4_s8_unaligned_depthwise_conv2d_33c1_c_remainder_end:
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu
.type dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr / tmp value
# a4: input dilation x offset / tmp value
# a5: input dilation y offset / tmp value
# t3: next_33s1 / tmp value
# t4: mac_shift
# t5: c_div_x_1 / c_remainder
# t6: output_sar_byte
# a6(not for extension instructions): tmp value
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8
esp32p4_s8_unaligned_depthwise_conv2d_33c1_load_args a2, a3, a4, a5, t3, t5, t4
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
addi t3, t3, -16 // t3: next_33s1 - 16
bltz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_c_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q4, a3, 16, q0, q3 // q4: filter_v0; q0: input_v0
esp.ld.128.usar.ip q1, a1, 16
esp.ld.128.usar.xp q3, a1, a4
esp.src.q.ld.ip q2, a1, 16, q1, q3 // q2: input_v2; q1: input_v1
beqz t6, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_128b
li a6, 8
beq t6, a6, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_64b
// esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_32b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_32b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_32b_loop_end
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_32b_unaligned_vector_store q3, a0, t6
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_32b_loop_end:
nop
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_32b_last:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_32b_unaligned_vector_store q3, a0, t6
j esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_64b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_64b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_64b_loop_end
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_64b_unaligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_64b_loop_end:
nop
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_64b_last:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_64b_unaligned_vector_store q3, a0
j esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_128b:
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_128b_last
esp.lp.setup 0, t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_128b_loop_end
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1 q0, q1, q2, q3, q4, q5, q6, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_128b_loop_end:
esp32p4_s8_128b_aligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_128b_last:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_33s1_last q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t3
esp32p4_s8_128b_vector_shift_result q3, t4
esp32p4_s8_128b_vector_relu q3, s0, s1
esp32p4_s8_128b_aligned_vector_store q3, a0
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_c_remainder:
lw t5, 136(a2) // t5: c_remainder
beqz t5, esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_c_remainder_end
esp.zero.qacc
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t5 // a4: dilation_x_offset - c_remainder
sub a5, a5, t5 // a5: dilation_y_offset - c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_33r1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t5
esp32p4_s8_128b_vector_shift_result q0, t4
esp32p4_s8_128b_vector_relu q0, s0, s1
dl_esp32p4_s8_store_remainder q0, a3, a4, a5, t3, t0, a0, t5
esp32p4_s8_unaligned_depthwise_conv2d_33c1_relu_c_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8
ret
############################################################################################################################################################
####
#### esp32p4_s8_unaligned_depthwise_conv2d_hwc1 series
####
############################################################################################################################################################
.macro esp32p4_s8_unaligned_depthwise_conv2d_1ws1 input_v0, input_v1, input_back, input_ptr, filter_v0, filter_ptr, dilation_x_offset_16, dilation_y_offset, filter_w, filter_w_rs1_1, filter_y_offset, temp
blez \filter_w_rs1_1, 1f
esp.lp.setup 0, \filter_w_rs1_1, 0f
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
0: esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
1:
andi \temp, \filter_w, 0xfffffffe
beq \filter_w, \temp, 2f
# three 8-input-element left
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v0
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q \input_v0, \input_v1, \input_back
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
j 3f
2: # two 8-input-element left
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
3:
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_1ws1_last input_v0, input_v1, input_back, input_ptr, filter_v0, filter_ptr, dilation_x_offset_16, filter_w, filter_w_rs1_1, next_hws1, filter_y_offset, temp
blez \filter_w_rs1_1, 5f
esp.lp.setup 0, \filter_w_rs1_1, 4f
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v1, \filter_v0
4: esp.src.q.ld.ip \input_v1, \input_ptr, 16, \input_v0, \input_back
5:
andi \temp, \filter_w, 0xfffffffe
beq \filter_w, \temp, 6f
# three 8-input-element left
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vmulas.s8.qacc.ld.ip \filter_v0, \filter_ptr, 16, \input_v0, \filter_v0
esp.src.q.ld.ip \input_v0, \input_ptr, 16, \input_v1, \input_back
esp.ld.128.usar.xp \input_back, \input_ptr, \next_hws1
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v1, \filter_v0
esp.src.q \input_v0, \input_v0, \input_back
esp.vmulas.s8.qacc \input_v0, \filter_v0
j 7f
6: # two 8-input-element left
esp.ld.128.usar.xp \input_back, \input_ptr, \next_hws1
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.src.q \input_v1, \input_v1, \input_back
esp.vmulas.s8.qacc \input_v1, \filter_v0
7:
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_hws1 input_v0, input_v1, input_back, filter_v0, input_ptr, filter_ptr, dilation_x_offset_16, dilation_y_offset_16, next_hws1, filter_h, filter_w, filter_w_rs1_1, args, filter_y_offset, filter_n_offset, temp
lw \filter_h, 52(\args) # filter_height
// lw \filter_w, 56(\args) # filter_width
addi \temp, \filter_w, -1
beqz \temp, 10f
// filter_w >= 2
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_x_offset_16
esp.vld.128.ip \filter_v0, \filter_ptr, 16 // filter_v0
esp.src.q \input_v0, \input_v1, \input_back // input_v0
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
addi \filter_h, \filter_h, -1
beqz \filter_h, 9f
8:
esp32p4_s8_unaligned_depthwise_conv2d_1ws1 \input_v0, \input_v1, \input_back, \input_ptr, \filter_v0, \filter_ptr, \dilation_x_offset_16, \dilation_y_offset_16, \filter_w, \filter_w_rs1_1, \filter_y_offset, \temp
addi \filter_h, \filter_h, -1
bgtz \filter_h, 8b
9: // last y
esp32p4_s8_unaligned_depthwise_conv2d_1ws1_last \input_v0, \input_v1, \input_back, \input_ptr, \filter_v0, \filter_ptr, \dilation_x_offset_16, \filter_w, \filter_w_rs1_1, \next_hws1, \filter_y_offset, \temp
j 13f
10: // filter_w == 1
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vld.128.xp \filter_v0, \filter_ptr, \filter_y_offset // filter_v0
esp.src.q \input_v0, \input_v1, \input_back // input_v0
addi \filter_h, \filter_h, -1
beqz \filter_h, 12f
// esp.lp.setup 0, \filter_h, 11f
11:
esp.ld.128.usar.ip \input_v1, \input_ptr, 16
esp.ld.128.usar.xp \input_back, \input_ptr, \dilation_y_offset_16
esp.vmulas.s8.qacc.ld.xp \filter_v0, \filter_ptr, \filter_y_offset, \input_v0, \filter_v0
esp.src.q \input_v0, \input_v1, \input_back
addi \filter_h, \filter_h, -1
bgtz \filter_h, 11b
12: // last y
esp.vmulas.s8.qacc \input_v0, \filter_v0
sub \input_ptr, \input_ptr, \dilation_y_offset_16
add \input_ptr, \input_ptr, \next_hws1
13:
add \filter_ptr, \filter_ptr, \filter_n_offset
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_11r1_padding input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_remainder, forward, filter_y_offset
esp.ld.128.usar.xp \input_v0, \input_ptr, \c_remainder
esp.vld.128.xp \input_back, \input_ptr, \forward
esp.src.q \input_v0, \input_v0, \input_back
esp.ld.128.usar.xp \filter_v0, \filter_ptr, \c_remainder
esp.vld.128.xp \filter_back, \filter_ptr, \filter_y_offset
esp.src.q \filter_v0, \filter_v0, \filter_back
esp.vmulas.s8.qacc \input_v0, \filter_v0
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_hwr1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, dilation_x_offset_c_remainder, dilation_y_offset_c_remainder, filter_h, filter_w, filter_w_rs1_1, c_remainder, args, filter_y_offset, temp
lw \filter_h, 52(\args) // filter_height
// lw \filter_w, 56(\args) // filter_width
addi \temp, \filter_w, -1
beqz \temp, 19f
18:
beqz \filter_w_rs1_1, 15f
esp.lp.setup 0, \filter_w_rs1_1, 14f
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
14: nop
15:
andi \temp, \filter_w, 0xfffffffe
beq \temp, \filter_w, 16f
# 3 left
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder, \filter_y_offset
j 17f
16:
# 2 left
esp32p4_s8_unaligned_depthwise_conv2d_11r1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_x_offset_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder, \filter_y_offset
17:
addi \filter_h, \filter_h, -1
bgtz \filter_h, 18b
j 21f
19:
# filter_w == 1
beqz \filter_h, 21f
esp.lp.setup 0, \filter_h, 20f
esp32p4_s8_unaligned_depthwise_conv2d_11r1_padding \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_remainder, \dilation_y_offset_c_remainder, \filter_y_offset
20: nop
21:
.endm
.macro esp32p4_s8_unaligned_depthwise_conv2d_hwc1_load_args args, filter_ptr, dilation_x_offset, dilation_y_offset, next_hwx1, c_div_x_1, mac_shift, filter_w, filter_w_rs1_1
esp32p4_s8_unaligned_depthwise_conv2d_33c1_load_args \args, \filter_ptr, \dilation_x_offset, \dilation_y_offset, \next_hwx1, \c_div_x_1, \mac_shift
lw \filter_w, 56(\args)
lw \filter_w_rs1_1, 148(\args)
.endm
.text
.align 2
.global dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias
.type dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr / unaligned_filter_ptr / tmp value
# a4: input dilation x offset / tmp value
# a5: input dilation y offset / tmp value
# t3: next_hwx1 / c_remainder
# t4: filter_y_offset / unaligned_filter_y_offset / tmp value
# t5: mac_shift
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): filter_n_offset
# a7(not for extension instructions): c_div_x_1
# t0(not for extension instructions): filter_h / tmp value
# t1(not for extension instructions): filter_w
# t2(not for extension instructions): filter_w_rs1_1
# s2(not for extension instructions): tmp value = 8
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8: bias_ptr
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s2, s0, s8
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, a7, t5, t1, t2
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
lw a6, 144(a2) // a6: filter_n_offset
lw s8, 68(a2) // bias
bltz a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
esp.ld.128.usar.ip q0, a0, 0
addi t3, t3, -16 // t3: next_hws1 - 16
lw t4, 60(a2) // t4: filter_y_offset
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_c_div_x:
beqz t6, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_128b
li s2, 8
beq t6, s2, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_64b
# esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_32b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_32b_multiple_loop:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_32b_unaligned_vector_store q0, a0, t6
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_32b_multiple_loop
j esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_64b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_64b_multiple_loop:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_64b_multiple_loop
j esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_128b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_128b_multiple_loop:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_aligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_128b_multiple_loop
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_c_remainder:
lw t3, 136(a2) // t3: c_remainder
beqz t3, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_c_remainder_end
lw a3, 168(a2) // a3: unaligned_filter_ptr
lw t4, 160(a2) // t4: unaligned_filter_y_offset
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t3 // a4: dilation_x_offset - c_remainder
sub a5, a5, t3 // a5: dilation_y_offset - c_remainder
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t0, t1, t2, t3, a2, t4, t6
esp32p4_s8_128b_vector_shift_result q0, t5
dl_esp32p4_s8_store_remainder q0, a3, a4, a5, t4, t0, a0, t3
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_c_remainder_end:
esp32p4_pop_12_stacks_3r s2, s0, s8
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu
.type dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr / unaligned_filter_ptr / tmp value
# a4: input dilation x offset / tmp value
# a5: input dilation y offset / tmp value
# t3: next_hwx1 / c_remainder
# t4: filter_y_offset / unaligned_filter_y_offset / tmp value
# t5: mac_shift
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): filter_n_offset
# a7(not for extension instructions): c_div_x_1
# t0(not for extension instructions): filter_h / tmp value
# t1(not for extension instructions): filter_w
# t2(not for extension instructions): filter_w_rs1_1
# s2(not for extension instructions): tmp value = 8
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8: bias_ptr
# s9:
# s10:
# s11:
esp32p4_push_20_stacks_5r s2, s0, s1, s8, s9
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, a7, t5, t1, t2
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
lw a6, 144(a2) // a6: filter_n_offset
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
lw s8, 68(a2) // bias
bltz a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
esp.ld.128.usar.ip q0, a0, 0
addi t3, t3, -16 // t3: next_hws1 - 16
lw t4, 60(a2) // t4: filter_y_offset
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_c_div_x:
beqz t6, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_128b
li s2, 8
beq t6, s2, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_64b
# esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_32b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_32b_multiple_loop:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_vector_relu q0, s0, s1
esp32p4_s8_32b_unaligned_vector_store q0, a0, t6
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_32b_multiple_loop
j esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_64b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_64b_multiple_loop:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_vector_relu q0, s0, s1
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_64b_multiple_loop
j esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_128b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_128b_multiple_loop:
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_vector_relu q0, s0, s1
esp32p4_s8_128b_aligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_128b_multiple_loop
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder:
lw t3, 136(a2) // t3: c_remainder
beqz t3, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder_end
lw a3, 168(a2) // a3: unaligned_filter_ptr
lw t4, 160(a2) // t4: unaligned_filter_y_offset
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t3 // a4: dilation_x_offset - c_remainder
sub a5, a5, t3 // a5: dilation_y_offset - c_remainder
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias s8
esp32p4_s8_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t0, t1, t2, t3, a2, t4, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_vector_relu q0, s0, s1
dl_esp32p4_s8_store_remainder q0, a3, a4, a5, t4, t0, a0, t3
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_bias_relu_c_remainder_end:
esp32p4_pop_20_stacks_5r s2, s0, s1, s8, s9
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1
.type dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr / unaligned_filter_ptr / tmp value
# a4: input dilation x offset / tmp value
# a5: input dilation y offset / tmp value
# t3: next_hwx1 / c_remainder
# t4: filter_y_offset / unaligned_filter_y_offset / tmp value
# t5: mac_shift
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): filter_n_offset
# a7(not for extension instructions): c_div_x_1
# t0(not for extension instructions): filter_h / tmp value
# t1(not for extension instructions): filter_w
# t2(not for extension instructions): filter_w_rs1_1
# s2(not for extension instructions): tmp value = 8
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_push_4_stacks_1r s2
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, a7, t5, t1, t2
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
lw a6, 144(a2) // a6: filter_n_offset
bltz a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_c_remainder
esp.ld.128.usar.ip q0, a0, 0
addi t3, t3, -16 // t3: next_hws1 - 16
lw t4, 60(a2) // t4: filter_y_offset
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_c_div_x:
beqz t6, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_128b
li s2, 8
beq t6, s2, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_64b
# esp32p4_s8_unaligned_depthwise_conv2d_hwc1_32b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_32b_multiple_loop:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_32b_unaligned_vector_store q0, a0, t6
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_32b_multiple_loop
j esp32p4_s8_unaligned_depthwise_conv2d_hwc1_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_64b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_64b_multiple_loop:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_64b_multiple_loop
j esp32p4_s8_unaligned_depthwise_conv2d_hwc1_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_128b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_128b_multiple_loop:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_aligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_128b_multiple_loop
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_c_remainder:
lw t3, 136(a2) // t3: c_remainder
beqz t3, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_c_remainder_end
lw a3, 168(a2) // a3: unaligned_filter_ptr
lw t4, 160(a2) // t4: unaligned_filter_y_offset
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t3 // a4: dilation_x_offset - c_remainder
sub a5, a5, t3 // a5: dilation_y_offset - c_remainder
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t0, t1, t2, t3, a2, t4, t6
esp32p4_s8_128b_vector_shift_result q0, t5
dl_esp32p4_s8_store_remainder q0, a3, a4, a5, t4, t0, a0, t3
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_c_remainder_end:
esp32p4_pop_4_stacks_1r s2
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu
.type dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr / unaligned_filter_ptr / tmp value
# a4: input dilation x offset / tmp value
# a5: input dilation y offset / tmp value
# t3: next_hwx1 / c_remainder
# t4: filter_y_offset / unaligned_filter_y_offset / tmp value
# t5: mac_shift
# t6: output_sar_byte / tmp value
# a6(not for extension instructions): filter_n_offset
# a7(not for extension instructions): c_div_x_1
# t0(not for extension instructions): filter_h / tmp value
# t1(not for extension instructions): filter_w
# t2(not for extension instructions): filter_w_rs1_1
# s2(not for extension instructions): tmp value = 8
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: activation_alpha/_address
# s1: activation_shift
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s2, s0, s1
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_load_args a2, a3, a4, a5, t3, a7, t5, t1, t2
addi a4, a4, -16 // a4: dilation_x_offset - 16
addi a5, a5, -16 // a5: dilation_y_offset - 16
lw a6, 144(a2) // a6: filter_n_offset
lw s0, 76(a2) // activation_alpha
lw s1, 84(a2) // activation_shift
bltz a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
esp.ld.128.usar.ip q0, a0, 0
addi t3, t3, -16 // t3: next_hws1 - 16
lw t4, 60(a2) // t4: filter_y_offset
esp.movx.r.sar.bytes t6 // t6: output_sar_byte
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_c_div_x:
beqz t6, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_128b
li s2, 8
beq t6, s2, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_64b
# esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_32b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_32b_multiple_loop:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_vector_relu q0, s0, s1
esp32p4_s8_32b_unaligned_vector_store q0, a0, t6
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_32b_multiple_loop
j esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_64b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_64b_multiple_loop:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_vector_relu q0, s0, s1
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_64b_multiple_loop
j esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_c_remainder
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_128b:
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_128b_multiple_loop:
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_hws1 q0, q1, q2, q3, a1, a3, a4, a5, t3, t0, t1, t2, a2, t4, a6, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_vector_relu q0, s0, s1
esp32p4_s8_128b_aligned_vector_store q0, a0
addi a7, a7, -1
bgez a7, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_128b_multiple_loop
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_c_remainder:
lw t3, 136(a2) // t3: c_remainder
beqz t3, esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_c_remainder_end
lw a3, 168(a2) // a3: unaligned_filter_ptr
lw t4, 160(a2) // t4: unaligned_filter_y_offset
addi a4, a4, 16
addi a5, a5, 16
sub a4, a4, t3 // a4: dilation_x_offset - c_remainder
sub a5, a5, t3 // a5: dilation_y_offset - c_remainder
esp.zero.qacc
esp32p4_s8_unaligned_depthwise_conv2d_hwr1 q0, q1, q2, q3, q4, q5, a1, a3, a4, a5, t0, t1, t2, t3, a2, t4, t6
esp32p4_s8_128b_vector_shift_result q0, t5
esp32p4_s8_128b_vector_relu q0, s0, s1
dl_esp32p4_s8_store_remainder q0, a3, a4, a5, t4, t0, a0, t3
esp32p4_s8_unaligned_depthwise_conv2d_hwc1_relu_c_remainder_end:
esp32p4_pop_12_stacks_3r s2, s0, s1
ret
|
georgevio/IoT-Embedded
| 15,417
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_equal.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_equal_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_equal_w1_16_w2_16
.type dl_esp32p4_s8_equal_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_equal_w1_16_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
esp32p4_s8_equal_w1_16_w2_16_loop:
beq t0, a3, esp32p4_s8_equal_w1_16_w2_16_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.eq.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_equal_w1_16_w2_16_loop
esp32p4_s8_equal_w1_16_w2_16_end:
ret
#void dl_esp32p4_s8_equal_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_equal_w1_16_w2_1
.type dl_esp32p4_s8_equal_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_equal_w1_16_w2_1:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s8_equal_w1_16_w2_1_loop:
beq t0, a3, esp32p4_s8_equal_w1_16_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.eq.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_equal_w1_16_w2_1_loop
esp32p4_s8_equal_w1_16_w2_1_end:
ret
#void dl_esp32p4_s8_equal_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_equal_w1_1_w2_16
.type dl_esp32p4_s8_equal_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_equal_w1_1_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s8_equal_w1_1_w2_16_loop:
beq t0, a3, esp32p4_s8_equal_w1_1_w2_16_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.eq.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_equal_w1_1_w2_16_loop
esp32p4_s8_equal_w1_1_w2_16_end:
ret
.align 2
.text
.global dl_esp32p4_s8_equal_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_equal_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_equal_w1_16_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_equal_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_equal_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_equal_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_equal_w1_16_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.eq.s8 q2, q2, q5
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_equal_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_equal_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_equal_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_equal_w1_1_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q5, q2
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s8 q2, q5, q2
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.eq.s8 q2, q5, q2
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_equal_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 16,815
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_mul2d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s16_mul2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_esp32p4_s16_mul2d_11c
.type dl_esp32p4_s16_mul2d_11c, @function
#.section .iram1
dl_esp32p4_s16_mul2d_11c:
.align 4
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
lw a4, 64(a3)
lw a5, 100(a3)
bltz a4, 5f
ESP.VLD.128.IP q0, a1, 16
ESP.VLD.128.IP q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC.LD.IP q0, a1, 16, q0, q1
ESP.VLD.128.IP q1, a2, 16
ESP.SRCMB.S16.QACC q2, a5, 1
ESP.VST.128.IP q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC q0, q1
ESP.SRCMB.S16.QACC q2, a5, 1
ESP.VST.128.IP q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 4
.text
.global dl_esp32p4_s16_mul2d_11c_relu
.type dl_esp32p4_s16_mul2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s16_mul2d_11c_relu:
.align 4
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw a5, 100(a3)
lw t3, 76(a3)
lw s8, 52(a3)
lw s9, 60(a3)
bltz a4, 5f
ESP.VLD.128.IP q0, a1, 16
ESP.VLD.128.IP q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC.LD.IP q0, a1, 16, q0, q1
ESP.VLD.128.IP q1, a2, 16
ESP.SRCMB.S16.QACC q2, a5, 1
ESP.VRELU.S16 q2, s8, s9
ESP.VST.128.IP q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC q0, q1
ESP.SRCMB.S16.QACC q2, a5, 1
ESP.VRELU.S16 q2, s8, s9
ESP.VST.128.IP q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 4
.text
.global dl_esp32p4_s16_mul2d_11c_prelu
.type dl_esp32p4_s16_mul2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s16_mul2d_11c_prelu:
.align 4
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw a5, 100(a3)
lw s8, 56(a3)
lw s9, 60(a3)
bltz a4, 5f
ESP.VLD.128.IP q0, a1, 16
ESP.VLD.128.IP q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC.LD.IP q0, a1, 16, q0, q1
ESP.VLD.128.IP q1, a2, 16
ESP.VLD.128.IP q3, s8, 16
ESP.SRCMB.S16.QACC q2, a5, 1
ESP.VPRELU.S16 q2, q2, q3, s9
ESP.VST.128.IP q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC q0, q1
ESP.VLD.128.IP q3, s8, 16
ESP.SRCMB.S16.QACC q2, a5, 1
ESP.VPRELU.S16 q2, q2, q3, s9
ESP.VST.128.IP q2, a0, 16
5:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
############################################################################################################################################################
####
#### esp32p4_S16_unaligned_mul2d_11c series
####
############################################################################################################################################################
.align 4
.text
.global dl_esp32p4_s16_unaligned_mul2d_11c
.type dl_esp32p4_s16_unaligned_mul2d_11c, @function
#.section .iram1
dl_esp32p4_s16_unaligned_mul2d_11c:
.align 4
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: c_remainder
# t3: mul_shift
lw a4, 64(a3)
lw a5, 76(a3)
lw t3, 100(a3)
ESP.LD.128.USAR.IP q5, a0, 0 #get output_ptr sar_byte
ESP.MOVX.R.SAR.BYTES s1
bltz a4, dl_tie718_S16_unaligned_mul2d_11c_small_remainder # channel < 8
ESP.LD.128.USAR.IP q0, a1, 16
ESP.LD.128.USAR.IP q3, a2, 16
ESP.LD.128.USAR.IP q1, a1, 16
beqz s1, dl_tie718_S16_unaligned_mul2d_11c_0
li t0, 8
beq s1, t0, dl_tie718_S16_unaligned_mul2d_11c_1
add t0, a4, x0
blez t0, 1f
0:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.LD.128.USAR.IP q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_tie718_S16_unaligned_mul2d_11c_remainder
dl_tie718_S16_unaligned_mul2d_11c_0:
add t0, a4, x0
blez t0, 3f
2:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.LD.128.USAR.IP q1, a1, 16
ESP.VST.128.IP q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VST.128.IP q2, a0, 16
j dl_tie718_S16_unaligned_mul2d_11c_remainder
dl_tie718_S16_unaligned_mul2d_11c_1:
add t0, a4, x0
blez t0, 5f
4:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.LD.128.USAR.IP q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_tie718_S16_unaligned_mul2d_11c_remainder
dl_tie718_S16_unaligned_mul2d_11c_small_remainder:
ESP.LD.128.USAR.XP q0, a1, a5
ESP.MOVX.R.SAR.BYTES t6
ESP.LD.128.USAR.XP q3, a2, a5
ESP.MOVX.R.SAR.BYTES s0
dl_tie718_S16_unaligned_mul2d_11c_remainder:
beqz a5, dl_esp32p4_S16_unaligned_mul2d_11c_end
ESP.LD.128.USAR.IP q1, a1, 0
ESP.MOVX.W.SAR.BYTES t6
ESP.SRC.Q q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 0
ESP.MOVX.W.SAR.BYTES s0
ESP.SRC.Q q5, q3, q4
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
srli a5, a5, 1
dl_esp32p4_s16_store_remainder q2, a5, s0, a0
dl_esp32p4_S16_unaligned_mul2d_11c_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 4
.text
.global dl_esp32p4_s16_unaligned_mul2d_11c_relu
.type dl_esp32p4_s16_unaligned_mul2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s16_unaligned_mul2d_11c_relu:
.align 4
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: c_remainder
# t3: mul_shift
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw a5, 76(a3)
lw t3, 100(a3)
lw s8, 52(a3)
lw s9, 60(a3)
ESP.LD.128.USAR.IP q5, a0, 0 #get output_ptr sar_byte
ESP.MOVX.R.SAR.BYTES s1
bltz a4, dl_tie718_S16_unaligned_mul2d_11c_relu_small_remainder # channel < 8
ESP.LD.128.USAR.IP q0, a1, 16
ESP.LD.128.USAR.IP q3, a2, 16
ESP.LD.128.USAR.IP q1, a1, 16
beqz s1, dl_tie718_S16_unaligned_mul2d_11c_relu_0
li t0, 8
beq s1, t0, dl_tie718_S16_unaligned_mul2d_11c_relu_1
add t0, a4, x0
blez t0, 1f
0:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.LD.128.USAR.IP q1, a1, 16
ESP.VRELU.S16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VRELU.S16 q2, s8, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_tie718_S16_unaligned_mul2d_11c_relu_remainder
dl_tie718_S16_unaligned_mul2d_11c_relu_0:
add t0, a4, x0
blez t0, 3f
2:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.LD.128.USAR.IP q1, a1, 16
ESP.VRELU.S16 q2, s8, s9
ESP.VST.128.IP q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VRELU.S16 q2, s8, s9
ESP.VST.128.IP q2, a0, 16
j dl_tie718_S16_unaligned_mul2d_11c_relu_remainder
dl_tie718_S16_unaligned_mul2d_11c_relu_1:
add t0, a4, x0
blez t0, 5f
4:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.LD.128.USAR.IP q1, a1, 16
ESP.VRELU.S16 q2, s8, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VRELU.S16 q2, s8, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_tie718_S16_unaligned_mul2d_11c_relu_remainder
dl_tie718_S16_unaligned_mul2d_11c_relu_small_remainder:
ESP.LD.128.USAR.XP q0, a1, a5
ESP.MOVX.R.SAR.BYTES t6
ESP.LD.128.USAR.XP q3, a2, a5
ESP.MOVX.R.SAR.BYTES s0
dl_tie718_S16_unaligned_mul2d_11c_relu_remainder:
beqz a5, dl_esp32p4_S16_unaligned_mul2d_11c_relu_end
ESP.LD.128.USAR.IP q1, a1, 0
ESP.MOVX.W.SAR.BYTES t6
ESP.SRC.Q q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 0
ESP.MOVX.W.SAR.BYTES s0
ESP.SRC.Q q5, q3, q4
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VRELU.S16 q2, s8, s9
srli a5, a5, 1
dl_esp32p4_s16_store_remainder q2, a5, s0, a0
dl_esp32p4_S16_unaligned_mul2d_11c_relu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 4
.text
.global dl_esp32p4_s16_unaligned_mul2d_11c_prelu
.type dl_esp32p4_s16_unaligned_mul2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s16_unaligned_mul2d_11c_prelu:
.align 4
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: c_remainder
# t3: mul_shift
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw a5, 76(a3)
lw t3, 100(a3)
lw s8, 56(a3)
lw s9, 60(a3)
ESP.LD.128.USAR.IP q5, a0, 0 #get output_ptr sar_byte
ESP.MOVX.R.SAR.BYTES s1
bltz a4, dl_tie718_S16_unaligned_mul2d_11c_prelu_small_remainder # channel < 8
ESP.LD.128.USAR.IP q0, a1, 16
ESP.LD.128.USAR.IP q3, a2, 16
ESP.LD.128.USAR.IP q1, a1, 16
beqz s1, dl_tie718_S16_unaligned_mul2d_11c_prelu_0
li t0, 8
beq s1, t0, dl_tie718_S16_unaligned_mul2d_11c_prelu_1
add t0, a4, x0
blez t0, 1f
0:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VLD.128.IP q6, s8, 16
ESP.LD.128.USAR.IP q1, a1, 16
ESP.VPRELU.S16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.VLD.128.IP q6, s8, 16
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VPRELU.S16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_tie718_S16_unaligned_mul2d_11c_prelu_remainder
dl_tie718_S16_unaligned_mul2d_11c_prelu_0:
add t0, a4, x0
blez t0, 3f
2:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VLD.128.IP q6, s8, 16
ESP.LD.128.USAR.IP q1, a1, 16
ESP.VPRELU.S16 q2, q2, q6, s9
ESP.VST.128.IP q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.VLD.128.IP q6, s8, 16
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VPRELU.S16 q2, q2, q6, s9
ESP.VST.128.IP q2, a0, 16
j dl_tie718_S16_unaligned_mul2d_11c_prelu_remainder
dl_tie718_S16_unaligned_mul2d_11c_prelu_1:
add t0, a4, x0
blez t0, 5f
4:
ESP.ZERO.QACC
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 16
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VLD.128.IP q6, s8, 16
ESP.LD.128.USAR.IP q1, a1, 16
ESP.VPRELU.S16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, a5
ESP.ZERO.QACC
ESP.MOVX.R.SAR.BYTES t6 #input0 sar
ESP.SRC.Q.QUP q2, q0, q1
ESP.LD.128.USAR.XP q4, a2, a5
ESP.MOVX.R.SAR.BYTES s0 #input1 sar
ESP.SRC.Q.QUP q5, q3, q4
ESP.VMULAS.S16.QACC q2, q5
ESP.VLD.128.IP q6, s8, 16
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VPRELU.S16 q2, q2, q6, s9
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_tie718_S16_unaligned_mul2d_11c_prelu_remainder
dl_tie718_S16_unaligned_mul2d_11c_prelu_small_remainder:
ESP.LD.128.USAR.XP q0, a1, a5
ESP.MOVX.R.SAR.BYTES t6
ESP.LD.128.USAR.XP q3, a2, a5
ESP.MOVX.R.SAR.BYTES s0
dl_tie718_S16_unaligned_mul2d_11c_prelu_remainder:
beqz a5, dl_esp32p4_S16_unaligned_mul2d_11c_prelu_end
ESP.LD.128.USAR.IP q1, a1, 0
ESP.MOVX.W.SAR.BYTES t6
ESP.SRC.Q q2, q0, q1
ESP.LD.128.USAR.IP q4, a2, 0
ESP.MOVX.W.SAR.BYTES s0
ESP.SRC.Q q5, q3, q4
ESP.ZERO.QACC
ESP.VMULAS.S16.QACC q2, q5
ESP.VLD.128.IP q6, s8, 16
ESP.SRCMB.S16.QACC q2, t3, 1
ESP.VPRELU.S16 q2, q2, q6, s9
srli a5, a5, 1
dl_esp32p4_s16_store_remainder q2, a5, s0, a0
dl_esp32p4_S16_unaligned_mul2d_11c_prelu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 75,413
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_unaligned_conv2d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s16_unaligned_conv2d_11cn series
####
############################################################################################################################################################
.macro esp32p4_s16_unaligned_conv2d_11c8 input_v, input_front, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, c_remainder, temp
# input_v: 8 input elements
# filter_v0: 8 filter elements
# filter_v1: 8 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 8 - 1
esp.ld.128.usar.ip \input_front, \input_ptr, 16
bltz \c_div_x_1, 7f
esp.ld.128.usar.ip \input_back, \input_ptr, 16
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.ip \filter_v1, \filter_ptr, 16
beqz \c_div_x_1, 8f
mv \temp, \c_div_x_1
// esp.lp.setup 0, \c_div_x_1, 9f
9:
esp.src.q.qup \input_v, \input_front, \input_back
esp.ld.128.usar.ip \input_back, \input_ptr, 16
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 3
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 4
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 5
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 6
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 7
addi \temp, \temp, -1
bgtz \temp, 9b
8:
# last entire-128b
esp.src.q.qup \input_v, \input_front, \input_back
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 3
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 4
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 5
esp.vsmulas.s16.qacc \filter_v0, \input_v, 6
esp.vsmulas.s16.qacc \filter_v1, \input_v, 7
beqz \c_remainder, 0f # jump to c_remainder == 0
# c_remainder
7:
esp.ld.128.usar.xp \input_back, \input_ptr, \c_remainder
esp.src.q.qup \input_v, \input_front, \input_back
esp.vld.128.ip \filter_v0, \filter_ptr, 16
li \temp, 8
blt \c_remainder, \temp, 3f
# remainder == 0x1__0
esp.vld.128.ip \filter_v1, \filter_ptr, 16
li \temp, 12
blt \c_remainder, \temp, 5f
# remainder == 0x11_0
li \temp, 14
blt \c_remainder, \temp, 6f
# remainder == 0x1110, 7
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 3
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 4
esp.vsmulas.s16.qacc \filter_v1, \input_v, 5
esp.vsmulas.s16.qacc \filter_v0, \input_v, 6
j 0f
6: # remainder == 0x1100, 6
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 3
esp.vsmulas.s16.qacc \filter_v0, \input_v, 4
esp.vsmulas.s16.qacc \filter_v1, \input_v, 5
j 0f
5:
li \temp, 10
blt \c_remainder, \temp, 4f
# remainder == 0x1010, 5
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 2
esp.vsmulas.s16.qacc \filter_v1, \input_v, 3
esp.vsmulas.s16.qacc \filter_v0, \input_v, 4
j 0f
4: # remainder == 0x1000, 4
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v, 1
esp.vsmulas.s16.qacc \filter_v0, \input_v, 2
esp.vsmulas.s16.qacc \filter_v1, \input_v, 3
j 0f
3: # remainder == 0x0__0
li \temp, 4
blt \c_remainder, \temp, 1f
# remainder == 0x01_0
esp.vld.128.ip \filter_v1, \filter_ptr, 16
li \temp, 6
blt \c_remainder, \temp, 2f
# remainder == 0x0110, 3
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v, 0
esp.vsmulas.s16.qacc \filter_v1, \input_v, 1
esp.vsmulas.s16.qacc \filter_v0, \input_v, 2
j 0f
2: # remainder == 0x0100, 2
esp.vsmulas.s16.qacc \filter_v0, \input_v, 0
esp.vsmulas.s16.qacc \filter_v1, \input_v, 1
j 0f
1: # remainder == 0x0010, 1
esp.vsmulas.s16.qacc \filter_v0, \input_v, 0
0:
addi \input_ptr, \input_ptr, -16
.endm
.macro esp32p4_s16_unaligned_conv2d_11c1 input_v, input_front, input_back, filter_v, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, temp, zero
# input_v: 8 input elements
# filter_v: 8 filter elements
# filter_v1: 8 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 8 - 1
esp.ld.128.usar.ip \input_front, \input_ptr, 16
esp.ld.128.usar.ip \filter_front, \filter_ptr, 16
bltz \c_div_x_1, 7f // input_channel < 8
esp.ld.128.usar.ip \input_back, \input_ptr, 16
beqz \c_div_x_1, 8f
// esp.lp.setup 0, \c_div_x_1, (8f - 4)
# Use the zero register as a loop counter, and the value remains zero after the loop is complete.
mv \zero, \c_div_x_1
9:
esp.src.q.qup \input_v, \input_front, \input_back
esp.ld.128.usar.ip \filter_back, \filter_ptr, 16
esp.src.q.qup \filter_v, \filter_front, \filter_back
esp.ld.128.usar.ip \input_back, \input_ptr, 16
esp.vmulas.s16.xacc \filter_v, \input_v
addi \zero, \zero, -1
bgtz \zero, 9b
8:
# last entire-128b
esp.src.q.qup \input_v, \input_front, \input_back
esp.ld.128.usar.ip \filter_back, \filter_ptr, 16
esp.src.q.qup \filter_v, \filter_front, \filter_back
esp.vmulas.s16.xacc \filter_v, \input_v
beqz \c_remainder, 0f
7:
# c_remainder > 0
esp.ld.128.usar.xp \input_back, \input_ptr, \c_remainder
esp.src.q.qup \input_v, \input_front, \input_back
esp.ld.128.usar.xp \filter_back, \filter_ptr, \c_remainder
esp.src.q.qup \filter_v, \filter_front, \filter_back
esp.slcxxp.2q \input_back, \input_v, \temp, \zero
esp.slcxxp.2q \filter_back, \filter_v, \temp, \zero
esp.vmulas.s16.xacc \filter_v, \input_v
0:
addi \input_ptr, \input_ptr, -16
addi \filter_ptr, \filter_ptr, -16
.endm
.macro esp32p4_s16_unaligned_conv2d_11cn_load_args args, filter_ptr, c_div_x_1, n_div_x, mac_shift, c_remainder
lw \filter_ptr, 48(\args) // filter
lw \c_div_x_1, 100(\args) // input_channel / x - 1
lw \n_div_x, 96(\args) // output_channel / x
lw \mac_shift, 64(\args) // mac_shift
lw \c_remainder, 136(\args) // input_channel % (vector_width / element_width) * sizeof(feature_t)
.endm
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_11cn_bias
.type dl_esp32p4_s16_unaligned_conv2d_11cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_11cn_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value
# t4: 15 - c_remainder
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8 // push stacks
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
esp32p4_s16_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
lw t6, 68(a2) // bias
beqz t1, esp32p4_s16_unaligned_conv2d_11cn_bias_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_11cn_bias_128b
li t2, 8
beq t3, t2, esp32p4_s16_unaligned_conv2d_11cn_bias_64b
esp32p4_s16_unaligned_conv2d_11cn_bias_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_bias_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_11cn_bias_n_remainder
esp32p4_s16_unaligned_conv2d_11cn_bias_64b:
esp32p4_s16_unaligned_conv2d_11cn_bias_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_bias_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_11cn_bias_n_remainder
esp32p4_s16_unaligned_conv2d_11cn_bias_128b:
esp32p4_s16_unaligned_conv2d_11cn_bias_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_bias_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_11cn_bias_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_11cn_bias_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s16_unaligned_conv2d_11cn_bias_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s16_conv2d_element_bias t6
esp32p4_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s16_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s16_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_bias_n_remainder_loop
esp32p4_s16_unaligned_conv2d_11cn_bias_n_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_11cn_bias_relu
.type dl_esp32p4_s16_unaligned_conv2d_11cn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_11cn_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value
# t4: 15 - c_remainder
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10 // push stacks
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s16_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
lw t6, 68(a2) // bias
beqz t1, esp32p4_s16_unaligned_conv2d_11cn_bias_relu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_11cn_bias_relu_128b
li t2, 8
beq t3, t2, esp32p4_s16_unaligned_conv2d_11cn_bias_relu_64b
esp32p4_s16_unaligned_conv2d_11cn_bias_relu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_bias_relu_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_11cn_bias_relu_n_remainder
esp32p4_s16_unaligned_conv2d_11cn_bias_relu_64b:
esp32p4_s16_unaligned_conv2d_11cn_bias_relu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_bias_relu_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_11cn_bias_relu_n_remainder
esp32p4_s16_unaligned_conv2d_11cn_bias_relu_128b:
esp32p4_s16_unaligned_conv2d_11cn_bias_relu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_bias_relu_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_11cn_bias_relu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_11cn_bias_relu_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s16_unaligned_conv2d_11cn_bias_relu_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s16_conv2d_element_bias t6
esp32p4_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s16_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s16_element_leakyrelu s0, s9, s10
esp32p4_s16_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_bias_relu_n_remainder_loop
esp32p4_s16_unaligned_conv2d_11cn_bias_relu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_11cn
.type dl_esp32p4_s16_unaligned_conv2d_11cn, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_11cn:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value
# t4: 15 - c_remainder
# t5: zero
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8 // push stacks
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
esp32p4_s16_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
beqz t1, esp32p4_s16_unaligned_conv2d_11cn_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_11cn_128b
li t2, 8
beq t3, t2, esp32p4_s16_unaligned_conv2d_11cn_64b
esp32p4_s16_unaligned_conv2d_11cn_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_11cn_n_remainder
esp32p4_s16_unaligned_conv2d_11cn_64b:
esp32p4_s16_unaligned_conv2d_11cn_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_11cn_n_remainder
esp32p4_s16_unaligned_conv2d_11cn_128b:
esp32p4_s16_unaligned_conv2d_11cn_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_11cn_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_11cn_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s16_unaligned_conv2d_11cn_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s16_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s16_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_n_remainder_loop
esp32p4_s16_unaligned_conv2d_11cn_n_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_11cn_relu
.type dl_esp32p4_s16_unaligned_conv2d_11cn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_11cn_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value
# t4: 15 - c_remainder
# t5: zero
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10 // push stacks
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s16_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
beqz t1, esp32p4_s16_unaligned_conv2d_11cn_relu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_11cn_relu_128b
li t2, 8
beq t3, t2, esp32p4_s16_unaligned_conv2d_11cn_relu_64b
esp32p4_s16_unaligned_conv2d_11cn_relu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_relu_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_11cn_relu_n_remainder
esp32p4_s16_unaligned_conv2d_11cn_relu_64b:
esp32p4_s16_unaligned_conv2d_11cn_relu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_relu_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_11cn_relu_n_remainder
esp32p4_s16_unaligned_conv2d_11cn_relu_128b:
esp32p4_s16_unaligned_conv2d_11cn_relu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_11c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_relu_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_11cn_relu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_11cn_relu_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s16_unaligned_conv2d_11cn_relu_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s16_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s16_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s16_element_leakyrelu s0, s9, s10
esp32p4_s16_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_11cn_relu_n_remainder_loop
esp32p4_s16_unaligned_conv2d_11cn_relu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10 // restore registers
ret
############################################################################################################################################################
####
#### esp32p4_s16_unaligned_conv2d_33cn series
####
############################################################################################################################################################
.macro esp32p4_s16_unaligned_conv2d_33c8 input_v0, input_front, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, temp
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro esp32p4_s16_unaligned_conv2d_33c1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, temp, zero
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro esp32p4_s16_unaligned_conv2d_hwcn_load_args args, filter_ptr, c_div_x_1, n_div_x, mac_shift, c_remainder, dilation_x_offset, dilation_y_offset
esp32p4_s16_unaligned_conv2d_11cn_load_args \args, \filter_ptr, \c_div_x_1, \n_div_x, \mac_shift, \c_remainder
lw \dilation_x_offset, 108(\args) // input dilation x offset
lw \dilation_y_offset, 112(\args) // input dilation y offset
.endm
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_33cn_bias
.type dl_esp32p4_s16_unaligned_conv2d_33cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_33cn_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value
# t4: 15 - c_remainder
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): tmp value
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8 // push stacks
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
esp32p4_s16_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s16_unaligned_conv2d_33cn_bias_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_33cn_bias_128b
li a7, 8
beq t3, a7, esp32p4_s16_unaligned_conv2d_33cn_bias_64b
esp32p4_s16_unaligned_conv2d_33cn_bias_32b:
esp32p4_s16_unaligned_conv2d_33cn_bias_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_bias_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_33cn_bias_n_remainder
esp32p4_s16_unaligned_conv2d_33cn_bias_64b:
esp32p4_s16_unaligned_conv2d_33cn_bias_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_bias_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_33cn_bias_n_remainder
esp32p4_s16_unaligned_conv2d_33cn_bias_128b:
esp32p4_s16_unaligned_conv2d_33cn_bias_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_bias_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_33cn_bias_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_33cn_bias_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s16_unaligned_conv2d_33cn_bias_n_remainder_loop:
mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s16_conv2d_element_bias t6
esp32p4_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s16_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s16_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_bias_n_remainder_loop
esp32p4_s16_unaligned_conv2d_33cn_bias_n_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_33cn_bias_relu
.type dl_esp32p4_s16_unaligned_conv2d_33cn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_33cn_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value
# t4: 15 - c_remainder
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): tmp value
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10 // push stacks
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s16_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s16_unaligned_conv2d_33cn_bias_relu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_33cn_bias_relu_128b
li a7, 8
beq t3, a7, esp32p4_s16_unaligned_conv2d_33cn_bias_relu_64b
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_32b:
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_bias_relu_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_33cn_bias_relu_n_remainder
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_64b:
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_bias_relu_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_33cn_bias_relu_n_remainder
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_128b:
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_bias_relu_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_33cn_bias_relu_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_n_remainder_loop:
mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s16_conv2d_element_bias t6
esp32p4_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s16_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s16_element_leakyrelu s0, s9, s10
esp32p4_s16_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_bias_relu_n_remainder_loop
esp32p4_s16_unaligned_conv2d_33cn_bias_relu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_33cn
.type dl_esp32p4_s16_unaligned_conv2d_33cn, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_33cn:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value
# t4: 15 - c_remainder
# t5: zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): tmp value
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8 // push stacks
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
esp32p4_s16_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s16_unaligned_conv2d_33cn_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_33cn_128b
li a7, 8
beq t3, a7, esp32p4_s16_unaligned_conv2d_33cn_64b
esp32p4_s16_unaligned_conv2d_33cn_32b:
esp32p4_s16_unaligned_conv2d_33cn_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_33cn_n_remainder
esp32p4_s16_unaligned_conv2d_33cn_64b:
esp32p4_s16_unaligned_conv2d_33cn_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_33cn_n_remainder
esp32p4_s16_unaligned_conv2d_33cn_128b:
esp32p4_s16_unaligned_conv2d_33cn_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_33cn_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_33cn_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s16_unaligned_conv2d_33cn_n_remainder_loop:
mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s16_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s16_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_n_remainder_loop
esp32p4_s16_unaligned_conv2d_33cn_n_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_33cn_relu
.type dl_esp32p4_s16_unaligned_conv2d_33cn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_33cn_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value
# t4: 15 - c_remainder
# t5: zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): tmp value
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10 // push stacks
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s16_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s16_unaligned_conv2d_33cn_relu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_33cn_relu_128b
li a7, 8
beq t3, a7, esp32p4_s16_unaligned_conv2d_33cn_relu_64b
esp32p4_s16_unaligned_conv2d_33cn_relu_32b:
esp32p4_s16_unaligned_conv2d_33cn_relu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_relu_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_33cn_relu_n_remainder
esp32p4_s16_unaligned_conv2d_33cn_relu_64b:
esp32p4_s16_unaligned_conv2d_33cn_relu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_relu_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_33cn_relu_n_remainder
esp32p4_s16_unaligned_conv2d_33cn_relu_128b:
esp32p4_s16_unaligned_conv2d_33cn_relu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_33c8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_relu_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_33cn_relu_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_33cn_relu_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s16_unaligned_conv2d_33cn_relu_n_remainder_loop:
mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s16_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s16_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s16_element_leakyrelu s0, s9, s10
esp32p4_s16_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_33cn_relu_n_remainder_loop
esp32p4_s16_unaligned_conv2d_33cn_relu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10 // restore registers
ret
############################################################################################################################################################
####
#### esp32p4_s16_unaligned_conv2d_hwcn series
####
############################################################################################################################################################
.macro esp32p4_s16_unaligned_conv2d_hwc8 input_v0, input_front, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, filter_h, filter_w, args, filter_y_offset, filter_n_offset, temp
lw \filter_h, 52(\args) # filter_height
11:
lw \filter_w, 56(\args) # filter_width
addi \filter_w, \filter_w, -1
beqz \filter_w, 12f
10:
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bnez \filter_w, 10b
12:
esp32p4_s16_unaligned_conv2d_11c8 \input_v0, \input_front, \input_back, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \filter_ptr, \filter_ptr, \filter_y_offset
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 11b
add \filter_ptr, \filter_ptr, \filter_n_offset
.endm
.macro esp32p4_s16_unaligned_conv2d_hwc1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, filter_h, filter_w, args, temp, zero, filter_y_offset, filter_n_offset
lw \filter_h, 52(\args) # filter_height
11:
lw \filter_w, 56(\args) # filter_width
addi \filter_w, \filter_w, -1
beqz \filter_w, 12f
10:
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bnez \filter_w, 10b
12:
esp32p4_s16_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \temp, \zero
add \filter_ptr, \filter_ptr, \filter_y_offset
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 11b
add \filter_ptr, \filter_ptr, \filter_n_offset
.endm
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_hwcn_bias
.type dl_esp32p4_s16_unaligned_conv2d_hwcn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_hwcn_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value / output
# t4: 15 - c_remainder
# t5: tmp value / zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions):
# s0:
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_20_stacks_5r s1, s2, s3, s4, s8
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
esp32p4_s16_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_hwcn_bias_128b
li t5, 8
beq t3, t5, esp32p4_s16_unaligned_conv2d_hwcn_bias_64b
# esp32p4_s16_unaligned_conv2d_hwcn_bias_32b:
esp32p4_s16_unaligned_conv2d_hwcn_bias_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_hwcn_bias_n_remainder
esp32p4_s16_unaligned_conv2d_hwcn_bias_64b:
esp32p4_s16_unaligned_conv2d_hwcn_bias_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_hwcn_bias_n_remainder
esp32p4_s16_unaligned_conv2d_hwcn_bias_128b:
esp32p4_s16_unaligned_conv2d_hwcn_bias_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_hwcn_bias_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_n_remainder_end
lw s3, 160(a2) // s3: filter_y_offset_unaligned
lw s4, 164(a2) // s4: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s16_unaligned_conv2d_hwcn_bias_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s16_conv2d_element_bias t6
esp32p4_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s16_element_result t3, a5
esp32p4_clamp t3, s1, s8
esp32p4_s16_element_store a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_n_remainder_loop
esp32p4_s16_unaligned_conv2d_hwcn_bias_n_remainder_end:
esp32p4_pop_20_stacks_5r s1, s2, s3, s4, s8
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_hwcn_bias_relu
.type dl_esp32p4_s16_unaligned_conv2d_hwcn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_hwcn_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value / output
# t4: 15 - c_remainder
# t5: tmp value / zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions):
# s0:
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_28_stacks_7r s1, s2, s3, s4, s8, s9, s10
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s16_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_128b
li t5, 8
beq t3, t5, esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_64b
# esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_32b:
esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder
esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_64b:
esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder
esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_128b:
esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias t6
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder_end
lw s3, 160(a2) // s3: filter_y_offset_unaligned
lw s4, 164(a2) // s4: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s16_conv2d_element_bias t6
esp32p4_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s16_element_result t3, a5
esp32p4_clamp t3, s1, s8
esp32p4_s16_element_leakyrelu t3, s9, s10
esp32p4_s16_element_store a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder_loop
esp32p4_s16_unaligned_conv2d_hwcn_bias_relu_n_remainder_end:
esp32p4_pop_28_stacks_7r s1, s2, s3, s4, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_hwcn
.type dl_esp32p4_s16_unaligned_conv2d_hwcn, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_hwcn:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value / output
# t4: 15 - c_remainder
# t5: tmp value / zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions):
# s0:
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_20_stacks_5r s1, s2, s3, s4, s8
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
esp32p4_s16_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s16_unaligned_conv2d_hwcn_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_hwcn_128b
li t5, 8
beq t3, t5, esp32p4_s16_unaligned_conv2d_hwcn_64b
# esp32p4_s16_unaligned_conv2d_hwcn_32b:
esp32p4_s16_unaligned_conv2d_hwcn_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_hwcn_n_remainder
esp32p4_s16_unaligned_conv2d_hwcn_64b:
esp32p4_s16_unaligned_conv2d_hwcn_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_hwcn_n_remainder
esp32p4_s16_unaligned_conv2d_hwcn_128b:
esp32p4_s16_unaligned_conv2d_hwcn_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_hwcn_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_hwcn_n_remainder_end
lw s3, 160(a2) // s3: filter_y_offset_unaligned
lw s4, 164(a2) // s4: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s16_unaligned_conv2d_hwcn_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s16_element_result t3, a5
esp32p4_clamp t3, s1, s8
esp32p4_s16_element_store a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_n_remainder_loop
esp32p4_s16_unaligned_conv2d_hwcn_n_remainder_end:
esp32p4_pop_20_stacks_5r s1, s2, s3, s4, s8
ret
.text
.align 2
.global dl_esp32p4_s16_unaligned_conv2d_hwcn_relu
.type dl_esp32p4_s16_unaligned_conv2d_hwcn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_unaligned_conv2d_hwcn_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving input_ptr / tmp value / output
# t4: 15 - c_remainder
# t5: tmp value / zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions):
# s0:
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_28_stacks_7r s1, s2, s3, s4, s8, s9, s10
li s1, -32768 // clamp min value
li s8, 32767 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s16_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s16_unaligned_conv2d_hwcn_relu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s16_unaligned_conv2d_hwcn_relu_128b
li t5, 8
beq t3, t5, esp32p4_s16_unaligned_conv2d_hwcn_relu_64b
# esp32p4_s16_unaligned_conv2d_hwcn_relu_32b:
esp32p4_s16_unaligned_conv2d_hwcn_relu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_relu_32b_multiple_loop
j esp32p4_s16_unaligned_conv2d_hwcn_relu_n_remainder
esp32p4_s16_unaligned_conv2d_hwcn_relu_64b:
esp32p4_s16_unaligned_conv2d_hwcn_relu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_relu_64b_multiple_loop
j esp32p4_s16_unaligned_conv2d_hwcn_relu_n_remainder
esp32p4_s16_unaligned_conv2d_hwcn_relu_128b:
esp32p4_s16_unaligned_conv2d_hwcn_relu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s16_unaligned_conv2d_hwc8 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, t5
esp32p4_s16_128b_vector_shift_result q0, a5
esp32p4_s16_128b_vector_relu q0, s9, s10
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_relu_128b_multiple_loop
esp32p4_s16_unaligned_conv2d_hwcn_relu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s16_unaligned_conv2d_hwcn_relu_n_remainder_end
lw s3, 160(a2) // s3: filter_y_offset_unaligned
lw s4, 164(a2) // s4: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s16_unaligned_conv2d_hwcn_relu_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s16_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s16_element_result t3, a5
esp32p4_clamp t3, s1, s8
esp32p4_s16_element_leakyrelu t3, s9, s10
esp32p4_s16_element_store a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s16_unaligned_conv2d_hwcn_relu_n_remainder_loop
esp32p4_s16_unaligned_conv2d_hwcn_relu_n_remainder_end:
esp32p4_pop_28_stacks_7r s1, s2, s3, s4, s8, s9, s10
ret
|
georgevio/IoT-Embedded
| 17,107
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_mul.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_mul_w1_8_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_mul_w1_8_w2_8
.type dl_esp32p4_s16_mul_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_mul_w1_8_w2_8:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw a5, 80(a3)
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
mv t0, a4
blez t0, dl_esp32p4_s16_mul_w1_8_w2_8_loop_last
dl_esp32p4_s16_mul_w1_8_w2_8_loop:
esp.zero.qacc
esp.vmulas.s16.qacc.ld.ip q0, a1, 16, q0, q1
esp.vld.128.ip q1, a2, 16
esp32p4_s16_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, dl_esp32p4_s16_mul_w1_8_w2_8_loop
dl_esp32p4_s16_mul_w1_8_w2_8_loop_last:
esp.zero.qacc
esp.vmulas.s16.qacc q0, q1
esp32p4_s16_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
ret
#void dl_esp32p4_s16_mul_w1_8_w2_1(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_mul_w1_8_w2_1
.type dl_esp32p4_s16_mul_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_mul_w1_8_w2_1:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw a5, 80(a3)
esp.vld.128.ip q0, a1, 16
esp.vldbc.16.ip q1, a2, 0 // input1 broadcast
mv t0, a4
blez t0, dl_esp32p4_s16_mul_w1_8_w2_1_loop_last
dl_esp32p4_s16_mul_w1_8_w2_1_loop:
esp.zero.qacc
esp.vmulas.s16.qacc.ld.ip q0, a1, 16, q0, q1
esp32p4_s16_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, dl_esp32p4_s16_mul_w1_8_w2_1_loop
dl_esp32p4_s16_mul_w1_8_w2_1_loop_last:
esp.zero.qacc
esp.vmulas.s16.qacc q0, q1
esp32p4_s16_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
ret
#void dl_esp32p4_s16_mul_w1_1_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_mul_w1_1_w2_8
.type dl_esp32p4_s16_mul_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_mul_w1_1_w2_8:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw a5, 80(a3)
esp.vldbc.16.ip q0, a1, 0 // input0 broadcast
esp.vld.128.ip q1, a2, 16
mv t0, a4
blez t0, dl_esp32p4_s16_mul_w1_1_w2_8_loop_last
dl_esp32p4_s16_mul_w1_1_w2_8_loop:
esp.zero.qacc
esp.vmulas.s16.qacc.ld.ip q1, a2, 16, q0, q1
esp32p4_s16_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, dl_esp32p4_s16_mul_w1_1_w2_8_loop
dl_esp32p4_s16_mul_w1_1_w2_8_loop_last:
esp.zero.qacc
esp.vmulas.s16.qacc q0, q1
esp32p4_s16_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
ret
.align 2
.text
.global dl_esp32p4_s16_mul_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_mul_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_mul_w1_8_w2_8_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6: mul_shift
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
lw t6, 80(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.zero.qacc
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_mul_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_mul_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_mul_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_mul_w1_8_w2_1_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6: mul_shift
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
lw t6, 80(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.zero.qacc
esp.src.q q2, q0, q1
esp.vmulas.s16.qacc q2, q5
esp32p4_s16_128b_vector_shift_result q2, t6
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_mul_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_mul_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_mul_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_mul_w1_1_w2_8_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6: mul_shift
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
lw t6, 80(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q5, q2
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q5, q2
esp32p4_s16_128b_vector_shift_result q2, t6
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q5, q2
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q5, q2
esp32p4_s16_128b_vector_shift_result q2, t6
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q5, q2
esp32p4_s16_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s16.qacc q5, q2
esp32p4_s16_128b_vector_shift_result q2, t6
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.zero.qacc
esp.src.q q2, q0, q1
esp.vmulas.s16.qacc q5, q2
esp32p4_s16_128b_vector_shift_result q2, t6
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_mul_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,598
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_xor4d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor
.type dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor, @function
#.section .iram1
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor
.type dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor, @function
#.section .iram1
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.16.ip q1, a2, 0
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor
.type dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor, @function
#.section .iram1
dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.16.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.xorq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned
.type dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.xorq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_remainder
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_8_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.xorq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned
.type dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_remainder
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a2, 0
dl_esp32p4_s16_xor4d_bchw_w1_8_w2_1_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.xorq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned
.type dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned, @function
#.section .iram1
dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a2: int16_t *input0_ptr
# a1: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.xorq q2, q5, q2 #esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2 #esp.xorq q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.xorq q2, q5, q2 #esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2 #esp.xorq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.xorq q2, q5, q2 #esp.xorq q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2 #esp.xorq q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_remainder
dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a1, 0
dl_esp32p4_s16_xor4d_bchw_w1_1_w2_8_simdxor_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_endtest
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.xorq q2, q5, q2 #esp.xorq q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_endtest:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 14,266
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_sub.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_sub_w1_8_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_sub_w1_8_w2_8
.type dl_esp32p4_s16_sub_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_sub_w1_8_w2_8:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
esp32p4_s16_sub_w1_8_w2_8_loop:
beq t0, a3, esp32p4_s16_sub_w1_8_w2_8_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vsub.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s16_sub_w1_8_w2_8_loop
esp32p4_s16_sub_w1_8_w2_8_end:
ret
#void dl_esp32p4_s16_sub_w1_8_w2_1(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_sub_w1_8_w2_1
.type dl_esp32p4_s16_sub_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_sub_w1_8_w2_1:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q1, a2, 0
li t0, 0
esp32p4_s16_sub_w1_8_w2_1_loop:
beq t0, a3, esp32p4_s16_sub_w1_8_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vsub.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s16_sub_w1_8_w2_1_loop
esp32p4_s16_sub_w1_8_w2_1_end:
ret
#void dl_esp32p4_s16_sub_w1_1_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_sub_w1_1_w2_8
.type dl_esp32p4_s16_sub_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_sub_w1_1_w2_8:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q0, a1, 0
li t0, 0
esp32p4_s16_sub_w1_1_w2_8_loop:
beq t0, a3, esp32p4_s16_sub_w1_1_w2_8_end
esp.vld.128.ip q1, a2, 16
esp.vsub.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s16_sub_w1_1_w2_8_loop
esp32p4_s16_sub_w1_1_w2_8_end:
ret
.align 2
.text
.global dl_esp32p4_s16_sub_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_sub_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_sub_w1_8_w2_8_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s16 q2, q2, q5
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vsub.s16 q2, q2, q5
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vsub.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_sub_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_sub_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_sub_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_sub_w1_8_w2_1_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q2, q5
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q2, q5
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vsub.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_sub_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_sub_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_sub_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_sub_w1_1_w2_8_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q5, q2
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vsub.s16 q2, q5, q2
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vsub.s16 q2, q5, q2
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_sub_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,266
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_add.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_add_w1_8_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_add_w1_8_w2_8
.type dl_esp32p4_s16_add_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_add_w1_8_w2_8:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
esp32p4_s16_add_w1_8_w2_8_loop:
beq t0, a3, esp32p4_s16_add_w1_8_w2_8_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s16_add_w1_8_w2_8_loop
esp32p4_s16_add_w1_8_w2_8_end:
ret
#void dl_esp32p4_s16_add_w1_8_w2_1(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_add_w1_8_w2_1
.type dl_esp32p4_s16_add_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_add_w1_8_w2_1:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q1, a2, 0
li t0, 0
esp32p4_s16_add_w1_8_w2_1_loop:
beq t0, a3, esp32p4_s16_add_w1_8_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vadd.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s16_add_w1_8_w2_1_loop
esp32p4_s16_add_w1_8_w2_1_end:
ret
#void dl_esp32p4_s16_add_w1_1_w2_8(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_add_w1_1_w2_8
.type dl_esp32p4_s16_add_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_add_w1_1_w2_8:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q0, a1, 0
li t0, 0
esp32p4_s16_add_w1_1_w2_8_loop:
beq t0, a3, esp32p4_s16_add_w1_1_w2_8_end
esp.vld.128.ip q1, a2, 16
esp.vadd.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s16_add_w1_1_w2_8_loop
esp32p4_s16_add_w1_1_w2_8_end:
ret
.align 2
.text
.global dl_esp32p4_s16_add_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_add_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_add_w1_8_w2_8_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_add_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s16_add_w1_8_w2_8_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_add_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_add_w1_8_w2_8_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_add_w1_8_w2_8_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_add_w1_8_w2_8_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_add_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s16 q2, q2, q5
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_add_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_add_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_add_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vadd.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_add_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_add_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_add_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_add_w1_8_w2_1_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_add_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s16_add_w1_8_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_add_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q2, q5
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_add_w1_8_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_add_w1_8_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_add_w1_8_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_add_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q2, q5
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_add_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_add_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_add_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vadd.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_add_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_add_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_add_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_add_w1_1_w2_8_unaligned:
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_add_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s16_add_w1_1_w2_8_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s16_add_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q5, q2
esp32p4_s16_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s16_add_w1_1_w2_8_unaligned_remainder
// output sar = 0
dl_esp32p4_s16_add_w1_1_w2_8_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_add_w1_1_w2_8_unaligned_remainder
// output sar = 8
dl_esp32p4_s16_add_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vadd.s16 q2, q5, q2
esp32p4_s16_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s16_add_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_add_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_add_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vadd.s16 q2, q5, q2
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, t3, a0
dl_esp32p4_s16_add_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,584
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_avg_pool2d.S
|
############################################################################################################################################################
####
#### dl_esp32p4_s8_avg_pool2d series
####
############################################################################################################################################################
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
.align 2
.text
.global dl_esp32p4_s8_avg_pool2d_22c1
.type dl_esp32p4_s8_avg_pool2d_22c1, @function
#.section .iram1
dl_esp32p4_s8_avg_pool2d_22c1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
lw a3, 16(a2) # input_y_offset
lw a4, 20(a2) # input_x_offset
lw t5, 4(a2) # input_channel
lw t6, 104(a2) # c_div_x_1
lw s1, 56(a2) # shift
addi s8, a2, 64
esp.vldbc.8.ip q0, s8, 0 # avg_pool_area_inv
add a5, a1, a4
add t3, a1, a3
add t4, t3, a4
esp.vld.128.ip q1, a1, 16
esp.vld.128.ip q2, a5, 16
add t0, t6, x0
blez t0, 1f
0:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q3, t3, 16, q0, q1
esp.vmulas.s8.qacc.ld.ip q4, t4, 16, q0, q2
esp.vmulas.s8.qacc.ld.ip q1, a1, 16, q0, q3
esp.vmulas.s8.qacc.ld.ip q2, a5, 16, q0, q4
esp.srcmb.s8.qacc q7, s1, 1
esp.vst.128.ip q7, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q3, t3, 16, q0, q1
esp.vmulas.s8.qacc.ld.ip q4, t4, 16, q0, q2
esp.vmulas.s8.qacc.ld.ip q1, a1, 16, q0, q3
esp.vmulas.s8.qacc.ld.ip q2, a5, 16, q0, q4
esp.srcmb.s8.qacc q7, s1, 1
esp.vst.128.ip q7, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_avg_pool2d_22c1
.type dl_esp32p4_s8_unaligned_avg_pool2d_22c1, @function
#.section .iram1
dl_esp32p4_s8_unaligned_avg_pool2d_22c1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
lw a3, 16(a2) # input_y_offset
lw a4, 20(a2) # input_x_offset
lw t5, 4(a2) # input_channel
lw t6, 104(a2) # c_div_x_1
lw s0, 60(a2) # c_remainder
lw s1, 56(a2) # shift
addi s8, a2, 64
esp.vldbc.8.ip q6, s8, 0 # avg_pool_area_inv
add a5, a1, a4
add t3, a1, a3
add t4, t3, a4
bltz t6, dl_esp32p4_s8_unaligned_avg_pool2d_22c1_remainder #channel < 16
esp.ld.128.usar.ip q7, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s9
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q1, a1, 0
beqz s9, 2f
li t0, 8
beq s9, t0, 3f
add t0, t6, x0
blez t0, 1f
0:
esp.zero.qacc
esp.src.q.ld.ip q2, a5, 16, q0, q1
esp.ld.128.usar.ip q3, a5, 0
esp.vmulas.s8.qacc q6, q0
esp.src.q.ld.ip q4, t3, 16, q2, q3
esp.ld.128.usar.ip q5, t3, 0
esp.vmulas.s8.qacc q6, q2
esp.src.q.ld.ip q2, t4, 16, q4, q5
esp.ld.128.usar.ip q3, t4, 0
esp.vmulas.s8.qacc q6, q4
esp.src.q.ld.ip q0, a1, 16, q2, q3
esp.ld.128.usar.ip q1, a1, 0
esp.vmulas.s8.qacc q6, q2
esp.srcmb.s8.qacc q7, s1, 1
esp32p4_s8_32b_unaligned_vector_store q7, a0, s8
addi t0, t0, -1
bgtz t0, 0b
1:
j dl_esp32p4_s8_unaligned_avg_pool2d_22c1_loop_end
2:
add t0, t6, x0
blez t0, 1f
0:
esp.zero.qacc
esp.src.q.ld.ip q2, a5, 16, q0, q1
esp.ld.128.usar.ip q3, a5, 0
esp.vmulas.s8.qacc q6, q0
esp.src.q.ld.ip q4, t3, 16, q2, q3
esp.ld.128.usar.ip q5, t3, 0
esp.vmulas.s8.qacc q6, q2
esp.src.q.ld.ip q2, t4, 16, q4, q5
esp.ld.128.usar.ip q3, t4, 0
esp.vmulas.s8.qacc q6, q4
esp.src.q.ld.ip q0, a1, 16, q2, q3
esp.ld.128.usar.ip q1, a1, 0
esp.vmulas.s8.qacc q6, q2
esp.srcmb.s8.qacc q7, s1, 1
esp.vst.128.ip q7, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
j dl_esp32p4_s8_unaligned_avg_pool2d_22c1_loop_end
3:
add t0, t6, x0
blez t0, 1f
0:
esp.zero.qacc
esp.src.q.ld.ip q2, a5, 16, q0, q1
esp.ld.128.usar.ip q3, a5, 0
esp.vmulas.s8.qacc q6, q0
esp.src.q.ld.ip q4, t3, 16, q2, q3
esp.ld.128.usar.ip q5, t3, 0
esp.vmulas.s8.qacc q6, q2
esp.src.q.ld.ip q2, t4, 16, q4, q5
esp.ld.128.usar.ip q3, t4, 0
esp.vmulas.s8.qacc q6, q4
esp.src.q.ld.ip q0, a1, 16, q2, q3
esp.ld.128.usar.ip q1, a1, 0
esp.vmulas.s8.qacc q6, q2
esp.srcmb.s8.qacc q7, s1, 1
esp32p4_s8_64b_unaligned_vector_store q7, a0
addi t0, t0, -1
bgtz t0, 0b
1:
dl_esp32p4_s8_unaligned_avg_pool2d_22c1_loop_end:
esp.zero.qacc
esp.src.q.ld.ip q2, a5, 16, q0, q1
esp.ld.128.usar.ip q3, a5, 0
esp.vmulas.s8.qacc q6, q0
esp.src.q.ld.ip q4, t3, 16, q2, q3
esp.ld.128.usar.ip q5, t3, 0
esp.vmulas.s8.qacc q6, q2
esp.src.q.ld.ip q2, t4, 16, q4, q5
esp.ld.128.usar.ip q3, t4, 0
esp.vmulas.s8.qacc q6, q4
esp.src.q q2, q2, q3
esp.vmulas.s8.qacc q6, q2
esp.srcmb.s8.qacc q7, s1, 1
esp32p4_s8_32b_unaligned_vector_store q7, a0, s8
beqz s0, dl_esp32p4_s8_unaligned_avg_pool2d_22c1_end
dl_esp32p4_s8_unaligned_avg_pool2d_22c1_remainder:
esp.ld.128.usar.xp q0, a1, s0
esp.vld.128.ip q1, a1, 0
esp.zero.qacc
esp.src.q q0, q0, q1
esp.ld.128.usar.xp q2, a5, s0
esp.vld.128.ip q3, a5, 0
esp.vmulas.s8.qacc q6, q0
esp.src.q q2, q2, q3
esp.ld.128.usar.xp q4, t3, s0
esp.vld.128.ip q5, t3, 0
esp.vmulas.s8.qacc q6, q2
esp.src.q q4, q4, q5
esp.ld.128.usar.xp q2, t4, s0
esp.vld.128.ip q3, t4, 0
esp.vmulas.s8.qacc q6, q4
esp.src.q q2, q2, q3
esp.vmulas.s8.qacc q6, q2
esp.srcmb.s8.qacc q7, s1, 1
dl_esp32p4_s8_store_remainder q7, t3, t4, t5, t6, t0, a0, s0
dl_esp32p4_s8_unaligned_avg_pool2d_22c1_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_avg_pool2d_hwc1
.type dl_esp32p4_s8_avg_pool2d_hwc1, @function
#.section .iram1
dl_esp32p4_s8_avg_pool2d_hwc1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
lw a3, 16(a2) # input_y_offset
lw a4, 20(a2) # input_x_offset
lw a5, 4(a2) # input_channel
lw t3, 48(a2) # filter_height
lw t4, 52(a2) # filter_width
lw t6, 104(a2) # c_div_x_1
lw s1, 56(a2) # shift
addi s8, a2, 64
esp.vldbc.8.ip q0, s8, 0 # avg_pool_area_inv
srli t5, t4, 1
addi t5, t5, -1 # filter_w / 2 - 1
li t0, 1
beq t4, t0, dl_esp32p4_s8_avg_pool2d_h1c1 #filter_width == 1
li t0, 1
blt t6, t0, dl_esp32p4_s8_avg_pool2d_hw_small_channel
6:
add a5, a1, x0
add s8, a5, x0
add s9, t3, x0
esp.zero.qacc
5:
esp.vld.128.xp q1, s8, a4
esp.vld.128.xp q2, s8, a4
add t0, t5, x0
blez t0, 1f
0:
esp.vmulas.s8.qacc.ld.xp q1, s8, a4, q0, q1
esp.vmulas.s8.qacc.ld.xp q2, s8, a4, q0, q2
addi t0, t0, -1
bgtz t0, 0b
1:
andi t0, t4, 1
beqz t0, 3f
2:#three left
esp.vmulas.s8.qacc.ld.xp q1, s8, a4, q0, q1
esp.vmulas.s8.qacc q0, q2
esp.vmulas.s8.qacc q0, q1
j 4f
3: # two left
esp.vmulas.s8.qacc q0, q1
esp.vmulas.s8.qacc q0, q2
4:
addi s9, s9, -1
add a5, a5, a3
add s8, a5, x0
bnez s9, 5b
esp.srcmb.s8.qacc q7, s1, 1
esp.vst.128.ip q7, a0, 16
addi a1, a1, 16
addi t6, t6, -1
bnez t6, 6b
dl_esp32p4_s8_avg_pool2d_hw_small_channel:
add a5, a1, x0
add s8, a5, x0
add s9, t3, x0
esp.zero.qacc
5:
esp.vld.128.xp q1, s8, a4
esp.vld.128.xp q2, s8, a4
add t0, t5, x0
blez t0, 1f
0:
esp.vmulas.s8.qacc.ld.xp q1, s8, a4, q0, q1
esp.vmulas.s8.qacc.ld.xp q2, s8, a4, q0, q2
addi t0, t0, -1
bgtz t0, 0b
1:
andi t0, t4, 1
beqz t0, 2f
2:#three left
esp.vmulas.s8.qacc.ld.xp q1, s8, a4, q0, q1
esp.vmulas.s8.qacc q0, q2
esp.vmulas.s8.qacc q0, q1
j 4f
3: # two left
esp.vmulas.s8.qacc q0, q1
esp.vmulas.s8.qacc q0, q2
4:
addi s9, s9, -1
add a5, a5, a3
add s8, a5, x0
bnez s9, 5b
esp.srcmb.s8.qacc q7, s1, 1
esp.vst.128.ip q7, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_avg_pool2d_h1c1:
addi t3, t3, -1
li t0, 1
blt t6, t0, dl_esp32p4_s8_max_pool2d_h1_small_channel
2:
add s8, a1, x0
esp.zero.qacc
esp.vld.128.xp q1, s8, a3
add t0, t3, x0
blez t0, 1f
0:
esp.vmulas.s8.qacc.ld.xp q1, s8, a3, q0, q1
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vmulas.s8.qacc q0, q1
esp.srcmb.s8.qacc q7, s1, 1
esp.vst.128.ip q7, a0, 16
addi a1, a1, 16
addi t6, t6, -1
bnez t6, 2b
dl_esp32p4_s8_max_pool2d_h1_small_channel:
add s8, a1, x0
esp.zero.qacc
esp.vld.128.xp q1, s8, a3
add t0, t3, x0
blez t0, 1f
0:
esp.vmulas.s8.qacc.ld.xp q1, s8, a3, q0, q1
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vmulas.s8.qacc q0, q1
esp.srcmb.s8.qacc q7, s1, 1
esp.vst.128.ip q7, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_avg_pool2d_hwc1
.type dl_esp32p4_s8_unaligned_avg_pool2d_hwc1, @function
#.section .iram1
dl_esp32p4_s8_unaligned_avg_pool2d_hwc1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
lw a3, 16(a2) # input_y_offset
lw a4, 20(a2) # input_x_offset
lw a5, 4(a2) # input_channel
lw t3, 48(a2) # filter_height
lw t4, 52(a2) # filter_width
lw t6, 104(a2) # c_div_x_1
lw s0, 60(a2) # c_remainder
lw s1, 56(a2) # shift
addi s8, a2, 64
esp.vldbc.8.ip q6, s8, 0 # avg_pool_area_inv
srli t5, t4, 1
addi t5, t5, -1 # filter_w / 2 - 1
addi a4, a4, -16
esp.ld.128.usar.ip q7, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s9
addi t6, t6, 1
li t0, 1
beq t4, t0, dl_esp32p4_s8_unaligned_avg_pool2d_h1c1 #filter_width == 1
li t0, 1
blt t6, t0, dl_esp32p4_s8_unaligned_avg_pool2d_hw_small_channel
9:
add a5, a1, x0
add s8, a5, x0
add s0, t3, x0
esp.zero.qacc
5:
esp.ld.128.usar.ip q0, s8, 16
esp.ld.128.usar.xp q1, s8, a4
add t0, t5, x0
blez t0, 1f
0:
esp.src.q.ld.ip q2, s8, 16, q0, q1
esp.ld.128.usar.xp q1, s8, a4
esp.vmulas.s8.qacc q6, q0
esp.src.q.ld.ip q0, s8, 16, q2, q1
esp.ld.128.usar.xp q1, s8, a4
esp.vmulas.s8.qacc q6, q2
addi t0, t0, -1
bgtz t0, 0b
1:
andi t0, t4, 1
beqz t0, 2f
2:#three left
esp.src.q.ld.ip q2, s8, 16, q0, q1
esp.ld.128.usar.xp q1, s8, a4
esp.vmulas.s8.qacc q6, q0
esp.src.q.ld.ip q0, s8, 16, q2, q1
esp.ld.128.usar.xp q1, s8, a4
esp.vmulas.s8.qacc q6, q2
esp.src.q q0, q0, q1
esp.vmulas.s8.qacc q6, q0
j 4f
3:# two left
esp.src.q.ld.ip q2, s8, 16, q0, q1
esp.ld.128.usar.xp q1, s8, a4
esp.vmulas.s8.qacc q6, q0
esp.src.q q2, q2, q1
esp.vmulas.s8.qacc q6, q2
4:
addi s0, s0, -1
add a5, a5, a3
add s8, a5, x0
bnez s0, 5b
esp.srcmb.s8.qacc q7, s1, 1
beqz s9, 6f
li t0, 8
beq s9, t0, 7f
esp32p4_s8_32b_unaligned_vector_store q7, a0, s8
j 8f
6:
esp.vst.128.ip q7, a0, 16
j 8f
7:
esp32p4_s8_64b_unaligned_vector_store q7, a0
8:
addi a1, a1, 16
addi t6, t6, -1
bnez t6, 9b
dl_esp32p4_s8_unaligned_avg_pool2d_hw_small_channel:
lw s0, 60(a2) # c_remainder
beqz s0, dl_esp32p4_s8_unaligned_avg_pool2d_hw_small_channel_end
add a5, a1, x0
add s8, a5, x0
add s9, t3, x0
addi a4, a4, 16
sub a4, a4, s0
esp.zero.qacc
2:
add t0, t4, x0
blez t0, 1f
0:
esp.ld.128.usar.xp q0, s8, s0
esp.vld.128.xp q1, s8, a4
esp.src.q q0, q0, q1
esp.vmulas.s8.qacc q6, q0
addi t0, t0, -1
bgtz t0, 0b
1:
addi s9, s9, -1
add a5, a5, a3
add s8, a5, x0
bnez s9, 2b
esp.srcmb.s8.qacc q7, s1, 1
dl_esp32p4_s8_store_remainder q7, t3, t4, t5, t6, t0, a0, s0
dl_esp32p4_s8_unaligned_avg_pool2d_hw_small_channel_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_unaligned_avg_pool2d_h1c1:
addi a3, a3, -16
li t0, 1
blt t6, t0, dl_esp32p4_s8_unaligned_avg_pool2d_h1_remainder
5:
add s8, a1, x0
esp.zero.qacc
add t0, t3, x0
blez t0, 1f
0:
esp.ld.128.usar.ip q0, s8, 16
esp.vld.128.xp q1, s8, a3
esp.src.q q0, q0, q1
esp.vmulas.s8.qacc q6, q0
addi t0, t0, -1
bgtz t0, 0b
1:
esp.srcmb.s8.qacc q7, s1, 1
beqz s9, 2f
li t0, 8
beq s9, t0, 2f
esp32p4_s8_32b_unaligned_vector_store q7, a0, t4
j 3f
2:
esp.vst.128.ip q7, a0, 16
j 4f
3:
esp32p4_s8_64b_unaligned_vector_store q7, a0
4:
addi a1, a1, 16
addi t6, t6, -1
bnez t6, 5b
dl_esp32p4_s8_unaligned_avg_pool2d_h1_remainder:
beqz s0, dl_esp32p4_s8_unaligned_avg_pool2d_hwc1_end
add s8, a1, x0
addi a3, a3, 16
sub a3, a3, s0
esp.zero.qacc
add t0, t3, x0
blez t0, 1f
0:
esp.ld.128.usar.xp q0, s8, s0
esp.vld.128.xp q1, s8, a3
esp.src.q q0, q0, q1
esp.vmulas.s8.qacc q6, q0
addi t0, t0, -1
bgtz t0, 0b
1:
esp.srcmb.s8.qacc q7, s1, 1
dl_esp32p4_s8_store_remainder q7, t3, t4, t5, t6, t0, a0, s0
dl_esp32p4_s8_unaligned_avg_pool2d_hwc1_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 25,923
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_conv2d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s16_conv2d_11cn series
####
############################################################################################################################################################
.macro esp32p4_s16_conv2d_11c8 input_v0, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, tmp
# scalar * vecter and accumulate into qacc
# input_ptr += (c_div_x_1 + 1) * 16 in the end
# filter_ptr point to the next 16 bytes in the end
# input_v0: 8 input elements
# filter_v0: 8 filter elements
# filter_v1: 8 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 8 - 1
esp.vld.128.ip \input_v0, \input_ptr, 16
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.ip \filter_v1, \filter_ptr, 16
beqz \c_div_x_1, 1f
# esp.lp.setup 0, \c_div_x_1, 0f
mv \tmp, \c_div_x_1
0:
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s16.qacc.ld.incp \input_v0, \input_ptr, \filter_v1, \input_v0, 7
esp.vld.128.ip \filter_v1, \filter_ptr, 16
addi \tmp, \tmp, -1
bgtz \tmp, 0b
1:
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s16.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s16.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s16.qacc \filter_v0, \input_v0, 6
esp.vsmulas.s16.qacc \filter_v1, \input_v0, 7
.endm
.macro esp32p4_s16_conv2d_11cn_load_args args, filter_ptr, c_div_x_1, n_rs3, mac_shift
lw \n_rs3, 96(\args) // output_channel_div_8
lw \mac_shift, 64(\args) // mac_shift
lw \filter_ptr, 48(\args) // filter
lw \c_div_x_1, 100(\args) // input_channel / x - 1
.endm
.text
.align 2
.global dl_esp32p4_s16_conv2d_11cn_bias
.type dl_esp32p4_s16_conv2d_11cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_11cn_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5: bias_ptr
# t3:
# t4:
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp_value
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_conv2d_11cn_load_args a2, a3, t1, t6, a4
lw a5, 68(a2) // bias
esp32p4_s16_conv2d_11cn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias a5
esp32p4_s16_conv2d_11c8 q0, q1, q2, t5, a3, t1, t0
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_11cn_bias_loop
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_11cn_bias_relu
.type dl_esp32p4_s16_conv2d_11cn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_11cn_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5: bias_ptr
# t3: activation_alpha/_address
# t4: activation_shift
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp_value
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_conv2d_11cn_load_args a2, a3, t1, t6, a4
lw a5, 68(a2) // bias
lw t3, 76(a2) // activation_alpha
lw t4, 84(a2) // activation_shift
esp32p4_s16_conv2d_11cn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias a5
esp32p4_s16_conv2d_11c8 q0, q1, q2, t5, a3, t1, t0
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_vector_relu q0, t3, t4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_11cn_bias_relu_loop
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_11cn
.type dl_esp32p4_s16_conv2d_11cn, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_11cn:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5:
# t3:
# t4:
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp_value
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_conv2d_11cn_load_args a2, a3, t1, t6, a4
esp32p4_s16_conv2d_11cn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_11c8 q0, q1, q2, t5, a3, t1, t0
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_11cn_loop
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_11cn_relu
.type dl_esp32p4_s16_conv2d_11cn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_11cn_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5:
# t3: activation_alpha/_address
# t4: activation_shift
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp_value
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_conv2d_11cn_load_args a2, a3, t1, t6, a4
lw t3, 76(a2) // activation_alpha
lw t4, 84(a2) // activation_shift
esp32p4_s16_conv2d_11cn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_11c8 q0, q1, q2, t5, a3, t1, t0
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_vector_relu q0, t3, t4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_11cn_relu_loop
ret
############################################################################################################################################################
####
#### esp32p4_s16_conv2d_33cn series
####
############################################################################################################################################################
.macro esp32p4_s16_conv2d_33c8 input_v0, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, dilation_x_offset, dilation_y_offset, tmp
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro esp32p4_s16_conv2d_hwcn_load_args args, filter_ptr, c_div_x_1, n_rs3, mac_shift, dilation_x_offset, dilation_y_offset
esp32p4_s16_conv2d_11cn_load_args \args, \filter_ptr, \c_div_x_1, \n_rs3, \mac_shift
lw \dilation_x_offset, 108(\args) // input dilation x offset
lw \dilation_y_offset, 112(\args) // input dilation y offset
.endm
.text
.align 2
.global dl_esp32p4_s16_conv2d_33cn_bias
.type dl_esp32p4_s16_conv2d_33cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_33cn_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5: bias_ptr
# t3:
# t4:
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions): input dilation y offset
# a7(not for extension instructions):
# t0(not for extension instructions): tmp_value
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): input dilation x offset
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_conv2d_hwcn_load_args a2, a3, t1, t6, a4, t2, a6
lw a5, 68(a2) // bias
esp32p4_s16_conv2d_33cn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias a5
esp32p4_s16_conv2d_33c8 q0, q1, q2, t5, a3, t1, t2, a6, t0
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_33cn_bias_loop
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_33cn_bias_relu
.type dl_esp32p4_s16_conv2d_33cn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_33cn_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5: bias_ptr
# t3: activation_alpha/_address
# t4: activation_shift
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions): input dilation y offset
# a7(not for extension instructions):
# t0(not for extension instructions): tmp_value
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): input dilation x offset
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_conv2d_hwcn_load_args a2, a3, t1, t6, a4, t2, a6
lw a5, 68(a2) // bias
lw t3, 76(a2) // activation_alpha
lw t4, 84(a2) // activation_shift
esp32p4_s16_conv2d_33cn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias a5
esp32p4_s16_conv2d_33c8 q0, q1, q2, t5, a3, t1, t2, a6, t0
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_vector_relu q0, t3, t4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_33cn_bias_relu_loop
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_33cn
.type dl_esp32p4_s16_conv2d_33cn, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_33cn:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5:
# t3:
# t4:
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions): input dilation y offset
# a7(not for extension instructions):
# t0(not for extension instructions): tmp_value
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): input dilation x offset
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_conv2d_hwcn_load_args a2, a3, t1, t6, a4, t2, a6
esp32p4_s16_conv2d_33cn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_33c8 q0, q1, q2, t5, a3, t1, t2, a6, t0
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_33cn_loop
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_33cn_relu
.type dl_esp32p4_s16_conv2d_33cn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_33cn_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5:
# t3: activation_alpha/_address
# t4: activation_shift
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions): input dilation y offset
# a7(not for extension instructions):
# t0(not for extension instructions): tmp_value
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): input dilation x offset
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_s16_conv2d_hwcn_load_args a2, a3, t1, t6, a4, t2, a6
lw t3, 76(a2) // activation_alpha
lw t4, 84(a2) // activation_shift
esp32p4_s16_conv2d_33cn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_33c8 q0, q1, q2, t5, a3, t1, t2, a6, t0
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_vector_relu q0, t3, t4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_33cn_relu_loop
ret
############################################################################################################################################################
####
#### esp32p4_s16_conv2d_hwcn series
####
############################################################################################################################################################
.macro esp32p4_s16_conv2d_hwc8 input_v0, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, dilation_x_offset, dilation_y_offset, filter_h, filter_w, args, filter_y_offset, filter_n_offset, tmp
# dilation_x_offset = (dilation_x * input_channel_with_padding - input_channel) * sizeof(output_t)
# dilation_y_offset = (dilation_y * input_width_with_padding * input_channel_with_padding - input_channel - dilation_x * input_channel_with_padding * (filter_width - 1)) * sizeof(output_t)
# filter_h
# filter_w
lw \filter_h, 52(\args) # filter_height
2:
lw \filter_w, 56(\args) # filter_width
addi \filter_w, \filter_w, -1
beqz \filter_w, 4f
// lp.setup 1, \filter_w, 3f
// esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
// 3: add \input_ptr, \input_ptr, \dilation_x_offset
3:
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bgtz \filter_w, 3b
4:
esp32p4_s16_conv2d_11c8 \input_v0, \filter_v0, \filter_v1, \input_ptr, \filter_ptr, \c_div_x_1, \tmp
add \filter_ptr, \filter_ptr, \filter_y_offset
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 2b
add \filter_ptr, \filter_ptr, \filter_n_offset
.endm
.text
.align 2
.global dl_esp32p4_s16_conv2d_hwcn_bias
.type dl_esp32p4_s16_conv2d_hwcn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_hwcn_bias:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5: bias_ptr
# t3:
# t4:
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions): input dilation y offset
# a7(not for extension instructions): filter_height
# t0(not for extension instructions): filter_width
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): input dilation x offset
# s2(not for extension instructions): filter_y_offset
# s3(not for extension instructions): filter_n_offset
# s4(not for extension instructions): tmp_value
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s2, s3, s4
esp32p4_s16_conv2d_hwcn_load_args a2, a3, t1, t6, a4, t2, a6
lw s2, 60(a2) // filter_y_offset
lw s3, 144(a2) // filter_n_offset
lw a5, 68(a2) // bias
esp32p4_s16_conv2d_hwcn_bias_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias a5
esp32p4_s16_conv2d_hwc8 q0, q1, q2, t5, a3, t1, t2, a6, a7, t0, a2, s2, s3, s4
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_hwcn_bias_loop
esp32p4_pop_12_stacks_3r s2, s3, s4
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_hwcn_bias_relu
.type dl_esp32p4_s16_conv2d_hwcn_bias_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_hwcn_bias_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5: bias_ptr
# t3: activation_alpha/_address
# t4: activation_shift
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions): input dilation y offset
# a7(not for extension instructions): filter_height
# t0(not for extension instructions): filter_width
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): input dilation x offset
# s2(not for extension instructions): filter_y_offset
# s3(not for extension instructions): filter_n_offset
# s4(not for extension instructions): tmp_value
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s2, s3, s4
esp32p4_s16_conv2d_hwcn_load_args a2, a3, t1, t6, a4, t2, a6
lw s2, 60(a2) // filter_y_offset
lw s3, 144(a2) // filter_n_offset
lw a5, 68(a2) // bias
lw t3, 76(a2) // activation_alpha
lw t4, 84(a2) // activation_shift
esp32p4_s16_conv2d_hwcn_bias_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_128b_vector_bias a5
esp32p4_s16_conv2d_hwc8 q0, q1, q2, t5, a3, t1, t2, a6, a7, t0, a2, s2, s3, s4
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_vector_relu q0, t3, t4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_hwcn_bias_relu_loop
esp32p4_pop_12_stacks_3r s2, s3, s4
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_hwcn
.type dl_esp32p4_s16_conv2d_hwcn, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_hwcn:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5:
# t3:
# t4:
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions): input dilation y offset
# a7(not for extension instructions): filter_height
# t0(not for extension instructions): filter_width
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): input dilation x offset
# s2(not for extension instructions): filter_y_offset
# s3(not for extension instructions): filter_n_offset
# s4(not for extension instructions): tmp_value
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s2, s3, s4
esp32p4_s16_conv2d_hwcn_load_args a2, a3, t1, t6, a4, t2, a6
lw s2, 60(a2) // filter_y_offset
lw s3, 144(a2) // filter_n_offset
esp32p4_s16_conv2d_hwcn_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_hwc8 q0, q1, q2, t5, a3, t1, t2, a6, a7, t0, a2, s2, s3, s4
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_hwcn_loop
esp32p4_pop_12_stacks_3r s2, s3, s4
ret
.text
.align 2
.global dl_esp32p4_s16_conv2d_hwcn_relu
.type dl_esp32p4_s16_conv2d_hwcn_relu, @function
.balign 4
.option norvc
dl_esp32p4_s16_conv2d_hwcn_relu:
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
# a3: int16_t *filter_ptr
# a4: mac_shift
# a5:
# t3: activation_alpha/_address
# t4: activation_shift
# t5: moving_input_ptr
# t6: n_rs3
# a6(not for extension instructions): input dilation y offset
# a7(not for extension instructions): filter_height
# t0(not for extension instructions): filter_width
# t1(not for extension instructions): c_div_x_1
# t2(not for extension instructions): input dilation x offset
# s2(not for extension instructions): filter_y_offset
# s3(not for extension instructions): filter_n_offset
# s4(not for extension instructions): tmp_value
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s2, s3, s4
esp32p4_s16_conv2d_hwcn_load_args a2, a3, t1, t6, a4, t2, a6
lw s2, 60(a2) // filter_y_offset
lw s3, 144(a2) // filter_n_offset
lw t3, 76(a2) // activation_alpha
lw t4, 84(a2) // activation_shift
esp32p4_s16_conv2d_hwcn_relu_loop:
mv t5, a1 // reload input_ptr
esp.zero.qacc
esp32p4_s16_conv2d_hwc8 q0, q1, q2, t5, a3, t1, t2, a6, a7, t0, a2, s2, s3, s4
esp32p4_s16_128b_vector_shift_result q0, a4
esp32p4_s16_128b_vector_relu q0, t3, t4
esp32p4_s16_128b_aligned_vector_store q0, a0
addi t6, t6, -1
bnez t6, esp32p4_s16_conv2d_hwcn_relu_loop
esp32p4_pop_12_stacks_3r s2, s3, s4
ret
|
georgevio/IoT-Embedded
| 16,885
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_mul2d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s8_mul2d_11c series
####
############################################################################################################################################################
.align 2
.text
.global dl_esp32p4_s8_mul2d_11c
.type dl_esp32p4_s8_mul2d_11c, @function
#.section .iram1
dl_esp32p4_s8_mul2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
lw a4, 64(a3)
lw a5, 100(a3)
lw t3, 76(a3)
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp.vld.128.ip q1, a2, 16
esp.srcmb.s8.qacc q2, a5, 1
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.zero.qacc
esp.vmulas.s8.qacc q0, q1
esp.srcmb.s8.qacc q2, a5, 1
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_mul2d_11c_relu
.type dl_esp32p4_s8_mul2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s8_mul2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw a5, 100(a3)
lw t3, 76(a3)
lw s8, 52(a3)
lw s9, 60(a3)
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp.vld.128.ip q1, a2, 16
esp.srcmb.s8.qacc q2, a5, 1
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.zero.qacc
esp.vmulas.s8.qacc q0, q1
esp.srcmb.s8.qacc q2, a5, 1
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_mul2d_11c_prelu
.type dl_esp32p4_s8_mul2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s8_mul2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw a5, 100(a3)
lw s8, 56(a3)
lw s9, 60(a3)
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
add t0, a4, x0
blez t0, 1f
0:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp.vld.128.ip q1, a2, 16
esp.vld.128.ip q3, s8, 16
esp.srcmb.s8.qacc q2, a5, 1
esp.vprelu.s8 q2, q2, q3, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.zero.qacc
esp.vmulas.s8.qacc q0, q1
esp.vld.128.ip q3, s8, 16
esp.srcmb.s8.qacc q2, a5, 1
esp.vprelu.s8 q2, q2, q3, s9
esp.vst.128.ip q2, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
############################################################################################################################################################
####
#### esp32p4_s8_unaligned_mul2d_11c series
####
############################################################################################################################################################
.align 2
.text
.global dl_esp32p4_s8_unaligned_mul2d_11c
.type dl_esp32p4_s8_unaligned_mul2d_11c, @function
#.section .iram1
dl_esp32p4_s8_unaligned_mul2d_11c:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: c_remainder
# t3: mul_shift
lw a4, 64(a3)
lw a5, 76(a3)
lw t3, 100(a3)
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_tie718_s8_unaligned_mul2d_11c_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_tie718_s8_unaligned_mul2d_11c_0
li t0, 8
beq s1, t0, dl_tie718_s8_unaligned_mul2d_11c_1
add t0, a4, x0
blez t0, 1f
0:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_tie718_s8_unaligned_mul2d_11c_remainder
dl_tie718_s8_unaligned_mul2d_11c_0:
add t0, a4, x0
blez t0, 3f
2:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.vst.128.ip q2, a0, 16
j dl_tie718_s8_unaligned_mul2d_11c_remainder
dl_tie718_s8_unaligned_mul2d_11c_1:
add t0, a4, x0
blez t0, 5f
4:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_tie718_s8_unaligned_mul2d_11c_remainder
dl_tie718_s8_unaligned_mul2d_11c_small_remainder:
esp.ld.128.usar.xp q0, a1, a5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, a5
esp.movx.r.sar.bytes s0
dl_tie718_s8_unaligned_mul2d_11c_remainder:
beqz a5, dl_esp32p4_s8_unaligned_mul2d_11c_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.zero.qacc
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, a5
dl_esp32p4_s8_unaligned_mul2d_11c_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_mul2d_11c_relu
.type dl_esp32p4_s8_unaligned_mul2d_11c_relu, @function
#.section .iram1
dl_esp32p4_s8_unaligned_mul2d_11c_relu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: c_remainder
# t3: mul_shift
# s8: activation_alpha
# s9: activation_shift
lw a4, 64(a3)
lw a5, 76(a3)
lw t3, 100(a3)
lw s8, 52(a3)
lw s9, 60(a3)
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_tie718_s8_unaligned_mul2d_11c_relu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_tie718_s8_unaligned_mul2d_11c_relu_0
li t0, 8
beq s1, t0, dl_tie718_s8_unaligned_mul2d_11c_relu_1
add t0, a4, x0
blez t0, 1f
0:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_tie718_s8_unaligned_mul2d_11c_relu_remainder
dl_tie718_s8_unaligned_mul2d_11c_relu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.vrelu.s8 q2, s8, s9
esp.vst.128.ip q2, a0, 16
j dl_tie718_s8_unaligned_mul2d_11c_relu_remainder
dl_tie718_s8_unaligned_mul2d_11c_relu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.ld.128.usar.ip q1, a1, 16
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.vrelu.s8 q2, s8, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_tie718_s8_unaligned_mul2d_11c_relu_remainder
dl_tie718_s8_unaligned_mul2d_11c_relu_small_remainder:
esp.ld.128.usar.xp q0, a1, a5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, a5
esp.movx.r.sar.bytes s0
dl_tie718_s8_unaligned_mul2d_11c_relu_remainder:
beqz a5, dl_esp32p4_s8_unaligned_mul2d_11c_relu_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.zero.qacc
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.vrelu.s8 q2, s8, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, a5
dl_esp32p4_s8_unaligned_mul2d_11c_relu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_mul2d_11c_prelu
.type dl_esp32p4_s8_unaligned_mul2d_11c_prelu, @function
#.section .iram1
dl_esp32p4_s8_unaligned_mul2d_11c_prelu:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: c_remainder
# t3: mul_shift
# s8: activation_alpha_ptr
# s9: activation_shift
lw a4, 64(a3)
lw a5, 76(a3)
lw t3, 100(a3)
lw s8, 56(a3)
lw s9, 60(a3)
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_tie718_s8_unaligned_mul2d_11c_prelu_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_tie718_s8_unaligned_mul2d_11c_prelu_0
li t0, 8
beq s1, t0, dl_tie718_s8_unaligned_mul2d_11c_prelu_1
add t0, a4, x0
blez t0, 1f
0:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q2, t3, 1
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_tie718_s8_unaligned_mul2d_11c_prelu_remainder
dl_tie718_s8_unaligned_mul2d_11c_prelu_0:
add t0, a4, x0
blez t0, 3f
2:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q2, t3, 1
esp.vprelu.s8 q2, q2, q6, s9
esp.vst.128.ip q2, a0, 16
j dl_tie718_s8_unaligned_mul2d_11c_prelu_remainder
dl_tie718_s8_unaligned_mul2d_11c_prelu_1:
add t0, a4, x0
blez t0, 5f
4:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.srcmb.s8.qacc q2, t3, 1
esp.vld.128.ip q6, s8, 16
esp.ld.128.usar.ip q1, a1, 16
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, a5
esp.zero.qacc
esp.movx.r.sar.bytes t6 #input0 sar
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, a5
esp.movx.r.sar.bytes s0 #input1 sar
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q2, t3, 1
esp.vprelu.s8 q2, q2, q6, s9
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_tie718_s8_unaligned_mul2d_11c_prelu_remainder
dl_tie718_s8_unaligned_mul2d_11c_prelu_small_remainder:
esp.ld.128.usar.xp q0, a1, a5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, a5
esp.movx.r.sar.bytes s0
dl_tie718_s8_unaligned_mul2d_11c_prelu_remainder:
beqz a5, dl_esp32p4_s8_unaligned_mul2d_11c_prelu_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.zero.qacc
esp.vmulas.s8.qacc q2, q5
esp.vld.128.ip q6, s8, 16
esp.srcmb.s8.qacc q2, t3, 1
esp.vprelu.s8 q2, q2, q6, s9
# esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, a5
dl_esp32p4_s8_unaligned_mul2d_11c_prelu_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 14,113
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_equal.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_equal_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_equal_w1_8_w2_8
.type dl_esp32p4_s16_equal_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_equal_w1_8_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
esp32p4_s16_equal_w1_8_w2_8_loop:
beq t0, a3, esp32p4_s16_equal_w1_8_w2_8_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.eq.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_equal_w1_8_w2_8_loop
esp32p4_s16_equal_w1_8_w2_8_end:
ret
#void dl_esp32p4_s16_equal_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_equal_w1_8_w2_1
.type dl_esp32p4_s16_equal_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_equal_w1_8_w2_1:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s16_equal_w1_8_w2_1_loop:
beq t0, a3, esp32p4_s16_equal_w1_8_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.eq.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_equal_w1_8_w2_1_loop
esp32p4_s16_equal_w1_8_w2_1_end:
ret
#void dl_esp32p4_s16_equal_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_equal_w1_1_w2_8
.type dl_esp32p4_s16_equal_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_equal_w1_1_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s16_equal_w1_1_w2_8_loop:
beq t0, a3, esp32p4_s16_equal_w1_1_w2_8_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.eq.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_equal_w1_1_w2_8_loop
esp32p4_s16_equal_w1_1_w2_8_end:
ret
.align 2
.text
.global dl_esp32p4_s16_equal_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_equal_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_equal_w1_8_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_equal_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_equal_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_equal_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_equal_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
// esp.vst.128.ip q2, a0, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_equal_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_equal_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_equal_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_equal_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_equal_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_equal_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_equal_w1_8_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_equal_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_equal_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_equal_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_equal_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_equal_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_equal_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_equal_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.eq.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_equal_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_equal_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_equal_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_equal_w1_1_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_equal_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_equal_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_equal_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_equal_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.eq.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_equal_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_equal_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_equal_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.eq.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_equal_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 17,652
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_greaterorequal.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_greaterorequal_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greaterorequal_w1_16_w2_16
.type dl_esp32p4_s8_greaterorequal_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_greaterorequal_w1_16_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
esp32p4_s8_greaterorequal_w1_16_w2_16_loop:
beq t0, a3, esp32p4_s8_greaterorequal_w1_16_w2_16_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.vcmp.eq.s8 q6, q0, q1
esp.vmax.u8 q2, q2, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greaterorequal_w1_16_w2_16_loop
esp32p4_s8_greaterorequal_w1_16_w2_16_end:
ret
#void dl_esp32p4_s8_greaterorequal_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greaterorequal_w1_16_w2_1
.type dl_esp32p4_s8_greaterorequal_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_greaterorequal_w1_16_w2_1:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s8_greaterorequal_w1_16_w2_1_loop:
beq t0, a3, esp32p4_s8_greaterorequal_w1_16_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.vcmp.eq.s8 q6, q0, q1
esp.vmax.u8 q2, q2, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greaterorequal_w1_16_w2_1_loop
esp32p4_s8_greaterorequal_w1_16_w2_1_end:
ret
#void dl_esp32p4_s8_greaterorequal_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_greaterorequal_w1_1_w2_16
.type dl_esp32p4_s8_greaterorequal_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_greaterorequal_w1_1_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s8_greaterorequal_w1_1_w2_16_loop:
beq t0, a3, esp32p4_s8_greaterorequal_w1_1_w2_16_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s8 q2, q0, q1
esp.vcmp.eq.s8 q6, q0, q1
esp.vmax.u8 q2, q2, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_greaterorequal_w1_1_w2_16_loop
esp32p4_s8_greaterorequal_w1_1_w2_16_end:
ret
.align 2
.text
.global dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greaterorequal_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greaterorequal_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_greaterorequal_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 13,292
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_max_pool2d.S
|
############################################################################################################################################################
####
#### dl_esp32p4_s8_max_pool2d series
####
############################################################################################################################################################
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
.align 2
.text
.global dl_esp32p4_s8_max_pool2d_22c1
.type dl_esp32p4_s8_max_pool2d_22c1, @function
#.section .iram1
dl_esp32p4_s8_max_pool2d_22c1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
lw a3, 16(a2) # input_y_offset
lw a4, 20(a2) # input_x_offset
lw t6, 104(a2) # c_div_x_1
add a5, a1, a4
add t3, a1, a3
add t4, t3, a4
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a5, 16
esp.vld.128.ip q2, t3, 16
add t0, t6, x0
blez t0, 1f
0:
esp.vmax.s8.ld.incp q3, t4, q7, q0, q1
esp.vmax.s8.ld.incp q0, a1, q7, q7, q2
esp.vmax.s8.ld.incp q1, a5, q7, q7, q3
esp.vld.128.ip q2, t3, 16
esp.vst.128.ip q7, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vmax.s8.ld.incp q3, t4, q7, q0, q1
esp.vmax.s8 q7, q7, q2
esp.vmax.s8 q7, q7, q3
esp.vst.128.ip q7, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_max_pool2d_22c1
.type dl_esp32p4_s8_unaligned_max_pool2d_22c1, @function
#.section .iram1
dl_esp32p4_s8_unaligned_max_pool2d_22c1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
lw a3, 16(a2) # input_y_offset
lw a4, 20(a2) # input_x_offset
lw t5, 4(a2) # input_channel
lw t6, 104(a2) # c_div_x_1
lw s0, 60(a2) # c_remainder
add a5, a1, a4
add t3, a1, a3
add t4, t3, a4
bltz t6, dl_esp32p4_s8_unaligned_max_pool2d_22c1_remainder #channel < 16
esp.ld.128.usar.ip q6, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s9
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q1, a1, 0
beqz s9, 2f
li t0, 8
beq s9, t0, 3f
add t0, t6, x0
blez t0, 1f
0:
esp.src.q.ld.ip q2, a5, 16, q0, q1
esp.ld.128.usar.ip q3, a5, 0
esp.src.q.ld.ip q4, t3, 16, q2, q3
esp.ld.128.usar.ip q5, t3, 0
esp.vmax.s8 q7, q0, q2
esp.src.q.ld.ip q2, t4, 16, q4, q5
esp.ld.128.usar.ip q3, t4, 0
esp.vmax.s8 q7, q7, q4
esp.src.q.ld.ip q0, a1, 16, q2, q3
esp.ld.128.usar.ip q1, a1, 0
esp.vmax.s8 q7, q7, q2
esp32p4_s8_32b_unaligned_vector_store q7, a0, s8
addi t0, t0, -1
bgtz t0, 0b
1:
j dl_esp32p4_s8_unaligned_max_pool2d_22c1_loop_end
2:
add t0, t6, x0
blez t0, 1f
0:
esp.src.q.ld.ip q2, a5, 16, q0, q1
esp.ld.128.usar.ip q3, a5, 0
esp.src.q.ld.ip q4, t3, 16, q2, q3
esp.ld.128.usar.ip q5, t3, 0
esp.vmax.s8 q7, q0, q2
esp.src.q.ld.ip q2, t4, 16, q4, q5
esp.ld.128.usar.ip q3, t4, 0
esp.vmax.s8 q7, q7, q4
esp.src.q.ld.ip q0, a1, 16, q2, q3
esp.ld.128.usar.ip q1, a1, 0
esp.vmax.s8 q7, q7, q2
esp.vst.128.ip q7, a0, 16
addi t0, t0, -1
bgtz t0, 0b
1:
j dl_esp32p4_s8_unaligned_max_pool2d_22c1_loop_end
3:
add t0, t6, x0
blez t0, 1f
0:
esp.src.q.ld.ip q2, a5, 16, q0, q1
esp.ld.128.usar.ip q3, a5, 0
esp.src.q.ld.ip q4, t3, 16, q2, q3
esp.ld.128.usar.ip q5, t3, 0
esp.vmax.s8 q7, q0, q2
esp.src.q.ld.ip q2, t4, 16, q4, q5
esp.ld.128.usar.ip q3, t4, 0
esp.vmax.s8 q7, q7, q4
esp.src.q.ld.ip q0, a1, 16, q2, q3
esp.ld.128.usar.ip q1, a1, 0
esp.vmax.s8 q7, q7, q2
esp32p4_s8_64b_unaligned_vector_store q7, a0
addi t0, t0, -1
bgtz t0, 0b
1:
dl_esp32p4_s8_unaligned_max_pool2d_22c1_loop_end:
esp.src.q.ld.ip q2, a5, 16, q0, q1
esp.ld.128.usar.ip q3, a5, 0
esp.src.q.ld.ip q4, t3, 16, q2, q3
esp.ld.128.usar.ip q5, t3, 0
esp.vmax.s8 q7, q0, q2
esp.src.q.ld.ip q2, t4, 16, q4, q5
esp.ld.128.usar.ip q3, t4, 0
esp.vmax.s8 q7, q7, q4
esp.src.q q2, q2, q3
esp.vmax.s8 q7, q7, q2
esp32p4_s8_32b_unaligned_vector_store q7, a0, s8
beqz s0, dl_esp32p4_s8_unaligned_max_pool2d_22c1_end
dl_esp32p4_s8_unaligned_max_pool2d_22c1_remainder:
esp.ld.128.usar.xp q0, a1, s0
esp.vld.128.ip q1, a1, 0
esp.src.q q0, q0, q1
esp.ld.128.usar.xp q2, a5, s0
esp.vld.128.ip q3, a5, 0
esp.src.q q2, q2, q3
esp.ld.128.usar.xp q4, t3, s0
esp.vld.128.ip q5, t3, 0
esp.vmax.s8 q7, q0, q2
esp.src.q q4, q4, q5
esp.ld.128.usar.xp q2, t4, s0
esp.vld.128.ip q3, t4, 0
esp.vmax.s8 q7, q7, q4
esp.src.q q2, q2, q3
esp.vmax.s8 q7, q7, q2
dl_esp32p4_s8_store_remainder q7, t3, t4, t5, t6, t0, a0, s0
dl_esp32p4_s8_unaligned_max_pool2d_22c1_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.macro dl_esp32p4_s8_max_pool2d_hw
4:
esp.vld.128.xp q0, s1, a4
add t0, t5, x0
blez t0, 1f
0:
esp.vld.128.xp q1, s1, a4
esp.vmax.s8 q7, q7, q0
esp.vld.128.xp q0, s1, a4
esp.vmax.s8 q7, q7, q1
addi t0, t0, -1
bgtz t0, 0b
1:
andi t0, t4, 1
beqz t0, 2f
#three left
esp.vld.128.xp q1, s1, a4
esp.vmax.s8 q7, q7, q0
esp.vld.128.xp q0, s1, a4
esp.vmax.s8 q7, q7, q1
esp.vmax.s8 q7, q7, q0
j 3f
2: # two left
esp.vld.128.xp q1, s1, a4
esp.vmax.s8 q7, q7, q0
esp.vmax.s8 q7, q7, q1
3:
addi s8, s8, -1
add a5, a5, a3
add s1, a5, x0
bnez s8, 4b
.endm
.align 2
.text
.global dl_esp32p4_s8_max_pool2d_hwc1
.type dl_esp32p4_s8_max_pool2d, @function
#.section .iram1
dl_esp32p4_s8_max_pool2d_hwc1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
lw a3, 16(a2) # input_y_offset
lw a4, 20(a2) # input_x_offset
lw a5, 4(a2) # input_channel
lw t3, 48(a2) # filter_height
lw t4, 52(a2) # filter_width
lw t6, 104(a2) # c_div_x_1
srli t5, t4, 1
addi t5, t5, -1 # filter_w / 2 - 1
li t0, 1
beq t4, t0, dl_esp32p4_s8_max_pool2d_h1c1 #filter_width == 1
li t0, 1
blt t6, t0, dl_esp32p4_s8_max_pool2d_hw_small_channel
5:
add a5, a1, x0
add s1, a5, x0
esp.vld.128.ip q7, s1, 0
add s8, t3, x0
dl_esp32p4_s8_max_pool2d_hw
esp.vst.128.ip q7, a0, 16
addi a1, a1, 16
addi t6, t6, -1
bnez t6, 5b
dl_esp32p4_s8_max_pool2d_hw_small_channel:
add a5, a1, x0
add s1, a5, x0
esp.vld.128.ip q7, s1, 0
add s8, t3, x0
dl_esp32p4_s8_max_pool2d_hw
esp.vst.128.ip q7, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_max_pool2d_h1c1:
addi t3, t3, -1
li t0, 1
blt t6, t0, dl_esp32p4_s8_max_pool2d_h1_small_channel
2:
add s1, a1, x0
esp.vld.128.xp q7, s1, a3
add t0, t3, x0
blez t0, 1f
0:
esp.vld.128.xp q0, s1, a3
esp.vmax.s8 q7, q7, q0
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vst.128.ip q7, a0, 16
addi a1, a1, 16
addi t6, t6, -1
bnez t6, 2b
dl_esp32p4_s8_max_pool2d_h1_small_channel:
add s1, a1, x0
esp.vld.128.xp q7, s1, a3
add t0, t3, x0
blez t0, 1f
0:
esp.vld.128.xp q0, s1, a3
esp.vmax.s8 q7, q7, q0
addi t0, t0, -1
bgtz t0, 0b
1:
esp.vst.128.ip q7, a0, 16
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_unaligned_max_pool2d_hwc1
.type dl_esp32p4_s8_unaligned_max_pool2d_hwc1, @function
#.section .iram1
dl_esp32p4_s8_unaligned_max_pool2d_hwc1:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input_ptr
# a2: void *args
lw a3, 16(a2) # input_y_offset
lw a4, 20(a2) # input_x_offset
lw a5, 4(a2) # input_channel
lw t3, 48(a2) # filter_height
lw t4, 52(a2) # filter_width
lw t6, 104(a2) # c_div_x_1
lw s0, 60(a2) # c_remainder
srli t5, t4, 1
addi t5, t5, -1 # filter_w / 2 - 1
addi a4, a4, -16
esp.ld.128.usar.ip q6, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s9
addi t6, t6, 1
li t0, 1
beq t4, t0, dl_esp32p4_s8_unaligned_max_pool2d_h1c1 #filter_width == 1
li t0, 1
blt t6, t0, dl_esp32p4_s8_unaligned_max_pool2d_hw_remainder
9:
add a5, a1, x0
add s1, a5, x0
esp.ld.128.usar.ip q6, s1, 16
esp.ld.128.usar.ip q7, s1, -16
esp.src.q q7, q6, q7
add s8, t3, x0
4:
esp.ld.128.usar.ip q0, s1, 16
esp.ld.128.usar.xp q1, s1, a4
add t0, t5, x0
blez t0, 1f
0:
esp.src.q.ld.ip q2, s1, 16, q0, q1
esp.ld.128.usar.xp q1, s1, a4
esp.vmax.s8 q7, q7, q0
esp.src.q.ld.ip q0, s1, 16, q2, q1
esp.ld.128.usar.xp q1, s1, a4
esp.vmax.s8 q7, q7, q2
addi t0, t0, -1
bgtz t0, 0b
1:
andi t0, t4, 1
beqz t0, 2f
#three left
esp.src.q.ld.ip q2, s1, 16, q0, q1
esp.ld.128.usar.xp q1, s1, a4
esp.vmax.s8 q7, q7, q0
esp.src.q.ld.ip q0, s1, 16, q2, q1
esp.ld.128.usar.xp q1, s1, a4
esp.vmax.s8 q7, q7, q2
esp.src.q q0, q0, q1
esp.vmax.s8 q7, q7, q0
j 3f
2:# two left
esp.src.q.ld.ip q2, s1, 16, q0, q1
esp.ld.128.usar.xp q1, s1, a4
esp.vmax.s8 q7, q7, q0
esp.src.q q2, q2, q1
esp.vmax.s8 q7, q7, q2
3:
addi s8, s8, -1
add a5, a5, a3
add s1, a5, x0
bnez s8, 4b
beqz s9, 5f
li t0, 8
beq s9, t0, 6f
esp32p4_s8_32b_unaligned_vector_store q7, a0, s8
j 7f
5:
esp.vst.128.ip q7, a0, 16
j 7f
6:
esp32p4_s8_64b_unaligned_vector_store q7, a0
7:
addi a1, a1, 16
addi t6, t6, -1
bnez t6, 9b
dl_esp32p4_s8_unaligned_max_pool2d_hw_remainder:
beqz s0, dl_esp32p4_s8_unaligned_max_pool2d_hw_remainder_end
add a5, a1, x0
add s1, a5, x0
esp.ld.128.usar.ip q6, s1, 16
esp.ld.128.usar.ip q7, s1, -16
esp.src.q q7, q6, q7
add s8, t3, x0
addi a4, a4, 16
sub a4, a4, s0
2:
add t0, t4, x0
blez t0, 1f
0:
esp.ld.128.usar.xp q0, s1, s0
esp.vld.128.xp q1, s1, a4
esp.src.q q0, q0, q1
esp.vmax.s8 q7, q7, q0
addi t0, t0, -1
bgtz t0, 0b
1:
addi s8, s8, -1
add a5, a5, a3
add s1, a5, x0
bnez s8, 2b
dl_esp32p4_s8_store_remainder q7, t3, t4, t5, t6, t0, a0, s0
dl_esp32p4_s8_unaligned_max_pool2d_hw_remainder_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
dl_esp32p4_s8_unaligned_max_pool2d_h1c1:
addi a3, a3, -16
addi t3, t3, -1
li t0, 1
blt t6, t0, dl_esp32p4_s8_unaligned_max_pool2d_h1_remainder
5:
add s1, a1, x0
esp.ld.128.usar.ip q6, s1, 16
esp.vld.128.xp q7, s1, a3
esp.src.q q7, q6, q7
add t0, t3, x0
blez t0, 1f
0:
esp.ld.128.usar.ip q0, s1, 16
esp.ld.128.usar.xp q1, s1, a3
esp.src.q q0, q0, q1
esp.vmax.s8 q7, q7, q0
addi t0, t0, -1
bgtz t0, 0b
1:
beqz s9, 2f
li t0, 8
beq s9, t0, 3f
esp32p4_s8_32b_unaligned_vector_store q7, a0, s8
j 4f
2:
esp.vst.128.ip q7, a0, 16
j 4f
3:
esp32p4_s8_64b_unaligned_vector_store q7, a0
4:
addi a1, a1, 16
addi t6, t6, -1
bnez t6, 5b
dl_esp32p4_s8_unaligned_max_pool2d_h1_remainder:
beqz s0, dl_esp32p4_s8_unaligned_max_pool2d_h1_remainder_end
addi a3, a3, 16
sub a3, a3, s0
add s1, a1, x0
esp.ld.128.usar.xp q6, s1, s0
esp.vld.128.xp q7, s1, a3
esp.src.q q7, q6, q7
add t0, t3, x0
blez t0, 1f
0:
esp.ld.128.usar.xp q0, s1, s0
esp.vld.128.xp q1, s1, a3
esp.src.q q0, q0, q1
esp.vmax.s8 q7, q7, q0
addi t0, t0, -1
bgtz t0, 0b
1:
dl_esp32p4_s8_store_remainder q7, t3, t4, t5, t6, t0, a0, s0
dl_esp32p4_s8_unaligned_max_pool2d_h1_remainder_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 4,668
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_not4d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq
.type dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq, @function
#.section .iram1
dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a2)
srai a3, a4, 4
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.notq q2, q0
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
.align 2
.text
.global dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned
.type dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned, @function
#.section .iram1
dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr no use
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a2)
lw t5, 76(a2)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_remainder
dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
dl_esp32p4_s8_notq4d_bchw_w1_16_w2_16_simdnotq_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.notq q2, q2
lui s0, 0 #
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 4,562
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_not4d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq(int16_t *output_ptr, int16_t *input0_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq
.type dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq, @function
#.section .iram1
dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: length
lw a4, 44(a2)
srai a3, a4, 3
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.notq q2, q0
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
.align 2
.text
.global dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned
.type dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned, @function
#.section .iram1
dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr no use
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a2)
lw t5, 76(a2)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.notq q2, q2
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_remainder
dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
dl_esp32p4_s16_notq4d_bchw_w1_8_w2_8_simdnotq_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3
esp.notq q2, q2
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 15,350
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_less.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_less_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_less_w1_16_w2_16
.type dl_esp32p4_s8_less_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_less_w1_16_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
esp32p4_s8_less_w1_16_w2_16_loop:
beq t0, a3, esp32p4_s8_less_w1_16_w2_16_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.lt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_less_w1_16_w2_16_loop
esp32p4_s8_less_w1_16_w2_16_end:
ret
#void dl_esp32p4_s8_less_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_less_w1_16_w2_1
.type dl_esp32p4_s8_less_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_less_w1_16_w2_1:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s8_less_w1_16_w2_1_loop:
beq t0, a3, esp32p4_s8_less_w1_16_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.lt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_less_w1_16_w2_1_loop
esp32p4_s8_less_w1_16_w2_1_end:
ret
#void dl_esp32p4_s8_less_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_less_w1_1_w2_16
.type dl_esp32p4_s8_less_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_less_w1_1_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s8_less_w1_1_w2_16_loop:
beq t0, a3, esp32p4_s8_less_w1_1_w2_16_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.lt.s8 q2, q0, q1
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_less_w1_1_w2_16_loop
esp32p4_s8_less_w1_1_w2_16_end:
ret
.align 2
.text
.global dl_esp32p4_s8_less_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_less_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_less_w1_16_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_less_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_less_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_less_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_less_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_less_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_less_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_less_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_less_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_less_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_less_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_less_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_less_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_less_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_less_w1_16_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_less_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_less_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_less_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_less_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_less_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_less_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_less_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_less_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_less_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_less_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.lt.s8 q2, q2, q5
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_less_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_less_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_less_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_less_w1_1_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_less_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_less_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_less_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_less_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_less_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_less_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_less_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q2, q5, q2
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_less_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_less_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_less_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.lt.s8 q2, q5, q2
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_less_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,136
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_add.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_add_w1_16_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_add_w1_16_w2_16
.type dl_esp32p4_s8_add_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_add_w1_16_w2_16:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
esp32p4_s8_add_w1_16_w2_16_loop:
beq t0, a3, esp32p4_s8_add_w1_16_w2_16_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_add_w1_16_w2_16_loop
esp32p4_s8_add_w1_16_w2_16_end:
ret
#void dl_esp32p4_s8_add_w1_16_w2_1(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_add_w1_16_w2_1
.type dl_esp32p4_s8_add_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_add_w1_16_w2_1:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q1, a2, 0
li t0, 0
esp32p4_s8_add_w1_16_w2_1_loop:
beq t0, a3, esp32p4_s8_add_w1_16_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vadd.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_add_w1_16_w2_1_loop
esp32p4_s8_add_w1_16_w2_1_end:
ret
#void dl_esp32p4_s8_add_w1_1_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_add_w1_1_w2_16
.type dl_esp32p4_s8_add_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_add_w1_1_w2_16:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q0, a1, 0
li t0, 0
esp32p4_s8_add_w1_1_w2_16_loop:
beq t0, a3, esp32p4_s8_add_w1_1_w2_16_end
esp.vld.128.ip q1, a2, 16
esp.vadd.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_add_w1_1_w2_16_loop
esp32p4_s8_add_w1_1_w2_16_end:
ret
.align 2
.text
.global dl_esp32p4_s8_add_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_add_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_add_w1_16_w2_16_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_add_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_add_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_add_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_add_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_add_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_add_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_add_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vadd.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_add_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_add_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_add_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vadd.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_add_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_add_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_add_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_add_w1_16_w2_1_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_add_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_add_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_add_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_add_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_add_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_add_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_add_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_add_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_add_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_add_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vadd.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_add_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_add_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_add_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_add_w1_1_w2_16_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_add_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_add_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_add_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q5, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_add_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_add_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_add_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_add_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vadd.s8 q2, q5, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_add_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_add_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_add_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vadd.s8 q2, q5, q2
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_add_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,597
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_max4d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax
.type dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax, @function
#.section .iram1
dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vmax.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax
.type dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax, @function
#.section .iram1
dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.8.ip q1, a2, 0
esp.vmax.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax
.type dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax, @function
#.section .iram1
dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.8.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.vmax.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned
.type dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned, @function
#.section .iram1
dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmax.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmax.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmax.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmax.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmax.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmax.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_remainder
dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_max4d_bchw_w1_16_w2_16_simdmax_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vmax.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned
.type dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned, @function
#.section .iram1
dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.vmax.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.vmax.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.vmax.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.vmax.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.vmax.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.vmax.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_remainder
dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a2, 0
dl_esp32p4_s8_max4d_bchw_w1_16_w2_1_simdmax_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.vmax.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned
.type dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned, @function
#.section .iram1
dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a2: int8_t *input0_ptr
# a1: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.vmax.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.vmax.s8 q2, q5, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.vmax.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.vmax.s8 q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.vmax.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.vmax.s8 q2, q5, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_remainder
dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a1, 0
dl_esp32p4_s8_max4d_bchw_w1_1_w2_16_simdmax_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end___
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.vmax.s8 q2, q5, q2
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end___:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 5,522
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_common.S
|
############################################################################################################################################################
# esp32p4_common series
############################################################################################################################################################
.macro esp32p4_push_4_stacks_1r value_0
# The order of register arguments for push and pop must be consistent.
addi sp, sp, -4
sw \value_0, 0(sp)
.endm
.macro esp32p4_pop_4_stacks_1r value_0
# The order of register arguments for push and pop must be consistent.
lw \value_0, 0(sp)
addi sp, sp, 4
.endm
.macro esp32p4_push_8_stacks_2r value_0, value_1
# The order of register arguments for push and pop must be consistent.
addi sp, sp, -8
sw \value_0, 4(sp)
sw \value_1, 0(sp)
.endm
.macro esp32p4_pop_8_stacks_2r value_0, value_1
# The order of register arguments for push and pop must be consistent.
lw \value_0, 4(sp)
lw \value_1, 0(sp)
addi sp, sp, 8
.endm
.macro esp32p4_push_12_stacks_3r value_0, value_1, value_2
# The order of register arguments for push and pop must be consistent.
addi sp, sp, -12
sw \value_0, 8(sp)
sw \value_1, 4(sp)
sw \value_2, 0(sp)
.endm
.macro esp32p4_pop_12_stacks_3r value_0, value_1, value_2
# The order of register arguments for push and pop must be consistent.
lw \value_0, 8(sp)
lw \value_1, 4(sp)
lw \value_2, 0(sp)
addi sp, sp, 12
.endm
.macro esp32p4_push_16_stacks_4r value_0, value_1, value_2, value_3
# The order of register arguments for push and pop must be consistent.
addi sp, sp, -16
sw \value_0, 12(sp)
sw \value_1, 8(sp)
sw \value_2, 4(sp)
sw \value_3, 0(sp)
.endm
.macro esp32p4_pop_16_stacks_4r value_0, value_1, value_2, value_3
# The order of register arguments for push and pop must be consistent.
lw \value_0, 12(sp)
lw \value_1, 8(sp)
lw \value_2, 4(sp)
lw \value_3, 0(sp)
addi sp, sp, 16
.endm
.macro esp32p4_push_20_stacks_5r value_0, value_1, value_2, value_3, value_4
# The order of register arguments for push and pop must be consistent.
addi sp, sp, -20
sw \value_0, 16(sp)
sw \value_1, 12(sp)
sw \value_2, 8(sp)
sw \value_3, 4(sp)
sw \value_4, 0(sp)
.endm
.macro esp32p4_pop_20_stacks_5r value_0, value_1, value_2, value_3, value_4
# The order of register arguments for push and pop must be consistent.
lw \value_0, 16(sp)
lw \value_1, 12(sp)
lw \value_2, 8(sp)
lw \value_3, 4(sp)
lw \value_4, 0(sp)
addi sp, sp, 20
.endm
.macro esp32p4_push_28_stacks_7r value_0, value_1, value_2, value_3, value_4, value_5, value_6
# The order of register arguments for push and pop must be consistent.
addi sp, sp, -28
sw \value_0, 24(sp)
sw \value_1, 20(sp)
sw \value_2, 16(sp)
sw \value_3, 12(sp)
sw \value_4, 8(sp)
sw \value_5, 4(sp)
sw \value_6, 0(sp)
.endm
.macro esp32p4_pop_28_stacks_7r value_0, value_1, value_2, value_3, value_4, value_5, value_6
# The order of register arguments for push and pop must be consistent.
lw \value_0, 24(sp)
lw \value_1, 20(sp)
lw \value_2, 16(sp)
lw \value_3, 12(sp)
lw \value_4, 8(sp)
lw \value_5, 4(sp)
lw \value_6, 0(sp)
addi sp, sp, 28
.endm
.macro esp32p4_push_36_stacks_9r value_0, value_1, value_2, value_3, value_4, value_5, value_6, value_7, value_8
# The order of register arguments for push and pop must be consistent.
addi sp, sp, -36
sw \value_0, 32(sp)
sw \value_1, 28(sp)
sw \value_2, 24(sp)
sw \value_3, 20(sp)
sw \value_4, 16(sp)
sw \value_5, 12(sp)
sw \value_6, 8(sp)
sw \value_7, 4(sp)
sw \value_8, 0(sp)
.endm
.macro esp32p4_pop_36_stacks_9r value_0, value_1, value_2, value_3, value_4, value_5, value_6, value_7, value_8
# The order of register arguments for push and pop must be consistent.
lw \value_0, 32(sp)
lw \value_1, 28(sp)
lw \value_2, 24(sp)
lw \value_3, 20(sp)
lw \value_4, 16(sp)
lw \value_5, 12(sp)
lw \value_6, 8(sp)
lw \value_7, 4(sp)
lw \value_8, 0(sp)
addi sp, sp, 36
.endm
.macro esp32p4_push_128_stacks_4r value_0, value_1, value_2, value_3
# The order of register arguments for push and pop must be consistent.
addi sp, sp, -128
sw \value_0, 124(sp)
sw \value_1, 120(sp)
sw \value_2, 116(sp)
sw \value_3, 112(sp)
.endm
.macro esp32p4_pop_128_stacks_4r value_0, value_1, value_2, value_3
# The order of register arguments for push and pop must be consistent.
lw \value_0, 124(sp)
lw \value_1, 120(sp)
lw \value_2, 116(sp)
lw \value_3, 112(sp)
addi sp, sp, 128
.endm
.macro esp32p4_clamp input, min, max
// check input and min
blt \input, \min, 0f // if input < min
// check input and max
blt \max, \input, 1f // if max < input
// If the input value is already within the range, there is no need for clamping; proceed directly to the end.
j 2f
0:
// If the input value is less than the minimum value, assign the minimum value to the result register.
mv \input, \min
j 2f
1:
// If the input value exceeds the maximum value, assign the maximum value to the result register.
mv \input, \max
2:
.endm
|
georgevio/IoT-Embedded
| 112,801
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_unaligned_conv2d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
############################################################################################################################################################
####
#### esp32p4_s8_unaligned_conv2d_11cn series
####
############################################################################################################################################################
.macro esp32p4_s8_unaligned_conv2d_11c16 input_v0, input_front_aligned, input_back_aligned, input_ptr, filter_v0, filter_v1, filter_ptr, c_div_x_1, remainder_c, tmp
# scalar * vecter and accumulate into qacc
# input_ptr += (c_div_x_1 + 1) * 16 in the end
# filter_ptr point to the next 16 bytes in the end
# input_v0: 16 input elements
# filter_v0: 16 filter elements
# filter_v1: 16 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 16 - 1
bltz \c_div_x_1, 17f # input_channel < 16
esp.ld.128.usar.ip \input_front_aligned, \input_ptr, 16
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.ip \filter_v1, \filter_ptr, 16
esp.ld.128.usar.ip \input_back_aligned, \input_ptr, 16
beqz \c_div_x_1, 19f
# lp.setup 0, \c_div_x_1, 18f
esp.lp.setup 0, \c_div_x_1, 18f
esp.src.q.qup \input_v0, \input_front_aligned, \input_back_aligned
esp.ld.128.usar.ip \input_back_aligned, \input_ptr, 16
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 14
18: esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 15
19:
esp.src.q.qup \input_v0, \input_front_aligned, \input_back_aligned
addi \input_ptr, \input_ptr, -16
add \input_ptr, \input_ptr, \remainder_c #input_ptr and the end of c
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 13
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 14
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 15
beqz \remainder_c, 16f #no c_remainder
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.vld.128.ip \input_back_aligned, \input_ptr, 0
esp.src.q \input_v0, \input_front_aligned, \input_back_aligned
j 15f
17: # input_channel < 16
esp.vld.128.ip \filter_v0, \filter_ptr, 16
esp.ld.128.usar.xp \input_front_aligned, \input_ptr, \remainder_c
esp.vld.128.ip \input_back_aligned, \input_ptr, 0
esp.src.q \input_v0, \input_front_aligned, \input_back_aligned
15: # remainder_c == 15, 0x1111
andi \tmp, \remainder_c, 8
beqz \tmp, 7f
esp.vld.128.ip \filter_v1, \filter_ptr, 16
andi \tmp, \remainder_c, 4
beqz \tmp, 11f
andi \tmp, \remainder_c, 2
beqz \tmp, 13f
andi \tmp, \remainder_c, 1
beqz \tmp, 14f
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 12
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 13
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 14
j 16f # jump to 16f
14: # remainder_c == 14, 0x1110
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 12
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 13
j 16f # jump to 16f
13: # remainder_c == 13, 0x1101
andi \tmp, \remainder_c, 1
beqz \tmp, 12f
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 11
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 12
j 16f # jump to 16f
12: # remainder_c == 12, 0x1100
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 10
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 11
j 16f # jump to 16f
11: # remainder_c == 11, 0x1011
andi \tmp, \remainder_c, 2
beqz \tmp, 9f
andi \tmp, \remainder_c, 1
beqz \tmp, 10f
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 9
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 10
j 16f # jump to 16f
10: # remainder_c == 10, 0x1010
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 8
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 9
j 16f # jump to 16f
9: # remainder_c == 9, 0x1001
andi \tmp, \remainder_c, 1
beqz \tmp, 8f
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 7
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 8
j 16f # jump to 16f
8: # remainder_c == 8, 0x1000
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 6
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 7
j 16f # jump to 16f
7: # remainder == 7, 0x111
andi \tmp, \remainder_c, 4
beqz \tmp, 3f
esp.vld.128.ip \filter_v1, \filter_ptr, 16
andi \tmp, \remainder_c, 2
beqz \tmp, 5f
andi \tmp, \remainder_c, 1
beqz \tmp, 6f
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 5
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 6
j 16f # jump to 16f
6: # remainder == 6, 0x110
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 4
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 5
j 16f # jump to 16f
5: # remainder == 4, 5
andi \tmp, \remainder_c, 1
beqz \tmp, 4f
# remainder == 5, 0x101
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 3
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 4
j 16f # jump to 16f
4: # remainder == 4, 0x100
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc.ld.incp \filter_v1, \filter_ptr, \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 2
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 3
j 16f # jump to 16f
3: # remainder == 1, 2, 3
andi \tmp, \remainder_c, 2
beqz \tmp, 1f
esp.vld.128.ip \filter_v1, \filter_ptr, 16
andi \tmp, \remainder_c, 1
beqz \tmp, 2f
# remainder == 3, 0x011
esp.vsmulas.s8.qacc.ld.incp \filter_v0, \filter_ptr, \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 1
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 2
j 16f # jump to 16f
2: # remainder == 2, 0x010
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 0
esp.vsmulas.s8.qacc \filter_v1, \input_v0, 1
j 16f # jump to 16f
1: # remainder == 1, 0x001
esp.vsmulas.s8.qacc \filter_v0, \input_v0, 0
16:
.endm
.macro esp32p4_s8_unaligned_conv2d_11c1 input_v, input_front, input_back, filter_v, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, c_remainder_shift, zero
# input_v: 16 input elements
# filter_v: 16 filter elements
# input_ptr: input_ptr
# filter_ptr: filter_ptr
# c_div_x_1: input_channel // 16 - 1
# c_remainder: input_channel % 16
# c_remainder_shift: 15 - c_remainder
esp.ld.128.usar.ip \input_front, \input_ptr, 16
esp.ld.128.usar.ip \filter_front, \filter_ptr, 16
bltz \c_div_x_1, 11f // input_channel < 16
esp.ld.128.usar.ip \input_back, \input_ptr, 16
beqz \c_div_x_1, 10f
# esp.lp.setup 0, \c_div_x_1, 9f
# Use the zero register as a loop counter, and the value remains zero after the loop is complete.
mv \zero, \c_div_x_1
9:
esp.src.q.qup \input_v, \input_front, \input_back
esp.ld.128.usar.ip \filter_back, \filter_ptr, 16
esp.src.q.qup \filter_v, \filter_front, \filter_back
esp.ld.128.usar.ip \input_back, \input_ptr, 16
esp.vmulas.s8.xacc \filter_v, \input_v
addi \zero, \zero, -1
bgtz \zero, 9b
10:
// last entire-128b
esp.src.q.qup \input_v, \input_front, \input_back
esp.ld.128.usar.ip \filter_back, \filter_ptr, 16
esp.src.q.qup \filter_v, \filter_front, \filter_back
esp.vmulas.s8.xacc \filter_v, \input_v
beqz \c_remainder, 12f
11:
// c_remainder > 0
esp.ld.128.usar.xp \input_back, \input_ptr, \c_remainder
esp.src.q.qup \input_v, \input_front, \input_back
esp.ld.128.usar.xp \filter_back, \filter_ptr, \c_remainder
esp.src.q.qup \filter_v, \filter_front, \filter_back
esp.slcxxp.2q \input_back, \input_v, \c_remainder_shift, \zero
esp.slcxxp.2q \filter_back, \filter_v, \c_remainder_shift, \zero
esp.vmulas.s8.xacc \filter_v, \input_v
12:
addi \input_ptr, \input_ptr, -16
addi \filter_ptr, \filter_ptr, -16
.endm
.macro esp32p4_s8_unaligned_conv2d_11cn_load_args args, filter_ptr, c_div_x_1, n_div_x, mac_shift, c_remainder
lw \filter_ptr, 48(\args) // filter
lw \c_div_x_1, 100(\args) // input_channel / x - 1
lw \n_div_x, 96(\args) // output_channel / x
lw \mac_shift, 64(\args) // mac_shift
lw \c_remainder, 136(\args) // input_channel % (vector_width / element_width) * sizeof(feature_t)
.endm
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_11cn_bias
.type dl_esp32p4_s8_unaligned_conv2d_11cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_11cn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr / n_remainder bias tmp value
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): temp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8 // push stacks
li s1, -128 // clamp min value
li s8, 127 // clamp max value
esp32p4_s8_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_bias_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_11cn_bias_128b
li t2, 8
beq t3, t2, esp32p4_s8_unaligned_conv2d_11cn_bias_64b
esp32p4_s8_unaligned_conv2d_11cn_bias_32b_multiple_loop: // esp32p4_s8_unaligned_conv2d_11cn_bias_32b
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_bias_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_bias_64b:
esp32p4_s8_unaligned_conv2d_11cn_bias_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_bias_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_bias_128b:
esp32p4_s8_unaligned_conv2d_11cn_bias_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_11cn_bias_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_bias_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_11cn_bias_n_remainder_loop:
// mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_n_remainder_loop
esp32p4_s8_unaligned_conv2d_11cn_bias_n_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu
.type dl_esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr / n_remainder bias tmp value
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): temp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_128b
li t2, 8
beq t3, t2, esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_64b
esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_32b_multiple_loop: // esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_32b
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_64b:
esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_128b:
esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder_loop:
// mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_leakyrelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_11cn_bias_leakyrelu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_11cn_bias_prelu
.type dl_esp32p4_s8_unaligned_conv2d_11cn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_11cn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr / n_remainder bias tmp value
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): temp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_128b
li t2, 8
beq t3, t2, esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_64b
esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_32b_multiple_loop: // esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_32b
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_64b:
esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_128b:
esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_n_remainder_loop:
// mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_prelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_11cn_bias_prelu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_11cn
.type dl_esp32p4_s8_unaligned_conv2d_11cn, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_11cn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): temp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8 // push stacks
li s1, -128 // clamp min value
li s8, 127 // clamp max value
esp32p4_s8_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_11cn_128b
li t2, 8
beq t3, t2, esp32p4_s8_unaligned_conv2d_11cn_64b
esp32p4_s8_unaligned_conv2d_11cn_32b_multiple_loop: // esp32p4_s8_unaligned_conv2d_11cn_32b
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_64b:
esp32p4_s8_unaligned_conv2d_11cn_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_128b:
esp32p4_s8_unaligned_conv2d_11cn_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_11cn_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_11cn_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_n_remainder_loop
esp32p4_s8_unaligned_conv2d_11cn_n_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_11cn_leakyrelu
.type dl_esp32p4_s8_unaligned_conv2d_11cn_leakyrelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_11cn_leakyrelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): temp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_128b
li t2, 8
beq t3, t2, esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_64b
esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_32b_multiple_loop: // esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_32b
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_64b:
esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_128b:
esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_leakyrelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_11cn_leakyrelu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_11cn_prelu
.type dl_esp32p4_s8_unaligned_conv2d_11cn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_11cn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): temp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_11cn_load_args a2, a3, t0, t1, a5, a4
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_prelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_11cn_prelu_128b
li t2, 8
beq t3, t2, esp32p4_s8_unaligned_conv2d_11cn_prelu_64b
esp32p4_s8_unaligned_conv2d_11cn_prelu_32b_multiple_loop: // esp32p4_s8_unaligned_conv2d_11cn_prelu_32b
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_prelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_prelu_64b:
esp32p4_s8_unaligned_conv2d_11cn_prelu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_prelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_11cn_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_11cn_prelu_128b:
esp32p4_s8_unaligned_conv2d_11cn_prelu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_11c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_prelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_11cn_prelu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_11cn_prelu_n_remainder_end
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_11cn_prelu_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_11c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_prelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_11cn_prelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_11cn_prelu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10
ret
############################################################################################################################################################
####
#### esp32p4_s8_unaligned_conv2d_33cn series
####
############################################################################################################################################################
.macro esp32p4_s8_unaligned_conv2d_33c16 input_v0, input_front, input_back, input_ptr, filter_v0, filter_v1, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, temp
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro esp32p4_s8_unaligned_conv2d_33c1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, c_remainder_shift, zero
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_y_offset
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
# add \input_ptr, \input_ptr, \dilation_y_offset
.endm
.macro esp32p4_s8_unaligned_conv2d_hwcn_load_args args, filter_ptr, c_div_x_1, n_div_x, mac_shift, c_remainder, dilation_x_offset, dilation_y_offset
esp32p4_s8_unaligned_conv2d_11cn_load_args \args, \filter_ptr, \c_div_x_1, \n_div_x, \mac_shift, \c_remainder
lw \dilation_x_offset, 108(\args) // input dilation x offset
lw \dilation_y_offset, 112(\args) // input dilation y offset
.endm
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_33cn_bias
.type dl_esp32p4_s8_unaligned_conv2d_33cn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_33cn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr / n_remainder bias tmp value
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8 // push stacks
li s1, -128 // clamp min value
li s8, 127 // clamp max value
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_bias_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 # t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_33cn_bias_128b
li a7, 8
beq t3, a7, esp32p4_s8_unaligned_conv2d_33cn_bias_64b
esp32p4_s8_unaligned_conv2d_33cn_bias_32b:
esp32p4_s8_unaligned_conv2d_33cn_bias_32b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_bias_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_bias_64b:
esp32p4_s8_unaligned_conv2d_33cn_bias_64b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_bias_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_bias_128b:
esp32p4_s8_unaligned_conv2d_33cn_bias_128b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_33cn_bias_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_bias_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_33cn_bias_n_remainder_loop:
// mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_n_remainder_loop
esp32p4_s8_unaligned_conv2d_33cn_bias_n_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu
.type dl_esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 # t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_128b
li a7, 8
beq t3, a7, esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_64b
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_32b:
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_32b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_64b:
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_64b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_128b:
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_128b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder_loop:
// mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_leakyrelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_33cn_bias_leakyrelu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_33cn_bias_prelu
.type dl_esp32p4_s8_unaligned_conv2d_33cn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_33cn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 # t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_128b
li a7, 8
beq t3, a7, esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_64b
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_32b:
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_32b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_64b:
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_64b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_128b:
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_128b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_n_remainder_loop:
// mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_prelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_33cn_bias_prelu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_33cn
.type dl_esp32p4_s8_unaligned_conv2d_33cn, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_33cn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_12_stacks_3r s0, s1, s8 // push stacks
li s1, -128 // clamp min value
li s8, 127 // clamp max value
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 # t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_33cn_128b
li a7, 8
beq t3, a7, esp32p4_s8_unaligned_conv2d_33cn_64b
esp32p4_s8_unaligned_conv2d_33cn_32b:
esp32p4_s8_unaligned_conv2d_33cn_32b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_64b:
esp32p4_s8_unaligned_conv2d_33cn_64b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_128b:
esp32p4_s8_unaligned_conv2d_33cn_128b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_33cn_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_33cn_n_remainder_loop:
mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_n_remainder_loop
esp32p4_s8_unaligned_conv2d_33cn_n_remainder_end:
esp32p4_pop_12_stacks_3r s0, s1, s8 // restore registers
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_33cn_leakyrelu
.type dl_esp32p4_s8_unaligned_conv2d_33cn_leakyrelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_33cn_leakyrelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 # t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_128b
li a7, 8
beq t3, a7, esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_64b
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_32b:
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_32b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_64b:
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_64b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_128b:
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_128b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_n_remainder_loop:
mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_leakyrelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_33cn_leakyrelu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_33cn_prelu
.type dl_esp32p4_s8_unaligned_conv2d_33cn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_33cn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_20_stacks_5r s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_prelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
esp.movx.r.sar.bytes t3 # t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_33cn_prelu_128b
li a7, 8
beq t3, a7, esp32p4_s8_unaligned_conv2d_33cn_prelu_64b
esp32p4_s8_unaligned_conv2d_33cn_prelu_32b:
esp32p4_s8_unaligned_conv2d_33cn_prelu_32b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_prelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_prelu_64b:
esp32p4_s8_unaligned_conv2d_33cn_prelu_64b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_prelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_33cn_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_33cn_prelu_128b:
esp32p4_s8_unaligned_conv2d_33cn_prelu_128b_multiple_loop:
mv t3, a1 # t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_33c16 q0, q1, q2, t3, q3, q4, a3, t0, a4, t2, a6, a7
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_prelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_33cn_prelu_n_remainder:
lw t1, 140(a2) # t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_33cn_prelu_n_remainder_end
li t4, 15
sub t4, t4, a4 # t4: 15 - c_remainder
li t5, 0 # t5: activation_shift = zero
esp32p4_s8_unaligned_conv2d_33cn_prelu_n_remainder_loop:
mv t3, a1 # t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_33c1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, t4, t5
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_prelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_33cn_prelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_33cn_prelu_n_remainder_end:
esp32p4_pop_20_stacks_5r s0, s1, s8, s9, s10
ret
############################################################################################################################################################
####
#### esp32p4_s8_unaligned_conv2d_hwcn series
####
############################################################################################################################################################
.macro esp32p4_s8_unaligned_conv2d_hwc16 input_v0, input_front, input_back, filter_v0, filter_v1, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, filter_h, filter_w, args, filter_y_offset, filter_n_offset, temp
lw \filter_h, 52(\args) // filter_height
21:
lw \filter_w, 56(\args) // filter_width
addi \filter_w, \filter_w, -1
beqz \filter_w, 22f
20:
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bnez \filter_w, 20b
22:
esp32p4_s8_unaligned_conv2d_11c16 \input_v0, \input_front, \input_back, \input_ptr, \filter_v0, \filter_v1, \filter_ptr, \c_div_x_1, \c_remainder, \temp
add \filter_ptr, \filter_ptr, \filter_y_offset
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 21b
add \filter_ptr, \filter_ptr, \filter_n_offset
.endm
.macro esp32p4_s8_unaligned_conv2d_hwc1 input_v0, input_front, input_back, filter_v0, filter_front, filter_back, input_ptr, filter_ptr, c_div_x_1, c_remainder, dilation_x_offset, dilation_y_offset, filter_h, filter_w, args, c_remainder_shift, zero, filter_y_offset, filter_n_offset
lw \filter_h, 52(\args) // filter_height
21:
lw \filter_w, 56(\args) // filter_width
addi \filter_w, \filter_w, -1
beqz \filter_w, 22f
20:
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \input_ptr, \input_ptr, \dilation_x_offset
addi \filter_w, \filter_w, -1
bnez \filter_w, 20b
22:
esp32p4_s8_unaligned_conv2d_11c1 \input_v0, \input_front, \input_back, \filter_v0, \filter_front, \filter_back, \input_ptr, \filter_ptr, \c_div_x_1, \c_remainder, \c_remainder_shift, \zero
add \filter_ptr, \filter_ptr, \filter_y_offset
add \input_ptr, \input_ptr, \dilation_y_offset
addi \filter_h, \filter_h, -1
bnez \filter_h, 21b
add \filter_ptr, \filter_ptr, \filter_n_offset
.endm
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_hwcn_bias
.type dl_esp32p4_s8_unaligned_conv2d_hwcn_bias, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_hwcn_bias:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr / n_remainder bias tmp value
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions): tmp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_28_stacks_7r s2, s3, s4, s5, s0, s1, s8
li s1, -128 // clamp min value
li s8, 127 // clamp max value
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_hwcn_bias_128b
li s5, 8
beq t3, s5, esp32p4_s8_unaligned_conv2d_hwcn_bias_64b
// esp32p4_s8_unaligned_conv2d_hwcn_bias_32b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_bias_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_bias_64b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_bias_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_bias_128b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_hwcn_bias_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_n_remainder_end
lw s3, 160(a2) // a3: filter_y_offset_unaligned
lw s4, 164(a2) // t3: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s8_unaligned_conv2d_hwcn_bias_n_remainder_loop:
// mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_n_remainder_loop
esp32p4_s8_unaligned_conv2d_hwcn_bias_n_remainder_end:
esp32p4_pop_28_stacks_7r s2, s3, s4, s5, s0, s1, s8
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu
.type dl_esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr / n_remainder bias tmp value
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions): tmp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_36_stacks_9r s2, s3, s4, s5, s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_128b
li s5, 8
beq t3, s5, esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_64b
// esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_32b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_64b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_128b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder_end
lw s3, 160(a2) // a3: filter_y_offset_unaligned
lw s4, 164(a2) // t3: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder_loop:
// mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_leakyrelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_hwcn_bias_leakyrelu_n_remainder_end:
esp32p4_pop_36_stacks_9r s2, s3, s4, s5, s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu
.type dl_esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr / n_remainder bias tmp value
# t4: c_remainder_shift
# t5: zero
# t6: bias_ptr
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions): tmp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_36_stacks_9r s2, s3, s4, s5, s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
lw t6, 68(a2) // bias
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_128b
li s5, 8
beq t3, s5, esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_64b
// esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_32b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_64b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_128b:
esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_conv2d_128b_vector_bias t6
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_n_remainder_end
lw s3, 160(a2) // a3: filter_y_offset_unaligned
lw s4, 164(a2) // t3: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_n_remainder_loop:
// mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_conv2d_element_bias t6, t3 // t3: tmp for bias
mv t3, a1 // t3: input_ptr
esp32p4_s8_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_prelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_hwcn_bias_prelu_n_remainder_end:
esp32p4_pop_36_stacks_9r s2, s3, s4, s5, s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_hwcn
.type dl_esp32p4_s8_unaligned_conv2d_hwcn, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_hwcn:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions): tmp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9:
# s10:
# s11:
esp32p4_push_28_stacks_7r s2, s3, s4, s5, s0, s1, s8
li s1, -128 // clamp min value
li s8, 127 // clamp max value
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_hwcn_128b
li s5, 8
beq t3, s5, esp32p4_s8_unaligned_conv2d_hwcn_64b
// esp32p4_s8_unaligned_conv2d_hwcn_32b:
esp32p4_s8_unaligned_conv2d_hwcn_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_64b:
esp32p4_s8_unaligned_conv2d_hwcn_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_128b:
esp32p4_s8_unaligned_conv2d_hwcn_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_hwcn_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_n_remainder_end
lw s3, 160(a2) // a3: filter_y_offset_unaligned
lw s4, 164(a2) // t3: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s8_unaligned_conv2d_hwcn_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_n_remainder_loop
esp32p4_s8_unaligned_conv2d_hwcn_n_remainder_end:
esp32p4_pop_28_stacks_7r s2, s3, s4, s5, s0, s1, s8
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu
.type dl_esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions): tmp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_36_stacks_9r s2, s3, s4, s5, s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 76(a2) // activation_alpha
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_128b
li s5, 8
beq t3, s5, esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_64b
// esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_32b:
esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_64b:
esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_128b:
esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_relu q0, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_n_remainder_end
lw s3, 160(a2) // a3: filter_y_offset_unaligned
lw s4, 164(a2) // t3: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_leakyrelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_hwcn_leakyrelu_n_remainder_end:
esp32p4_pop_36_stacks_9r s2, s3, s4, s5, s0, s1, s8, s9, s10
ret
.text
.align 2
.global dl_esp32p4_s8_unaligned_conv2d_hwcn_prelu
.type dl_esp32p4_s8_unaligned_conv2d_hwcn_prelu, @function
.balign 4
.option norvc
dl_esp32p4_s8_unaligned_conv2d_hwcn_prelu:
# a0: int8_t *output_ptr
# a1: int8_t *input_ptr
# a2: void *args
# a3: int8_t *filter_ptr
# a4: c_remainder
# a5: mac_shift
# t3: output_sar_byte / moving_input_ptr
# t4: c_remainder_shift
# t5: zero
# t6:
# a6(not for extension instructions): dilation_y_offset
# a7(not for extension instructions): filter_h
# t0(not for extension instructions): c_div_x_1
# t1(not for extension instructions): n_div_x / n_remainder
# t2(not for extension instructions): dilation_x_offset
# s2(not for extension instructions): filter_w
# s3(not for extension instructions): filter_y_offset
# s4(not for extension instructions): filter_n_offset
# s5(not for extension instructions): tmp value
# s0: output
# s1: clamp min value
# s8: clamp max value
# s9: activation_alpha/_address
# s10: activation_shift
# s11:
esp32p4_push_36_stacks_9r s2, s3, s4, s5, s0, s1, s8, s9, s10
li s1, -128 // clamp min value
li s8, 127 // clamp max value
lw s9, 80(a2) // activation_alpha_ptr
lw s10, 84(a2) // activation_shift
esp32p4_s8_unaligned_conv2d_hwcn_load_args a2, a3, t0, t1, a5, a4, t2, a6
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_prelu_n_remainder
esp.ld.128.usar.ip q0, a0, 0
lw s3, 60(a2) // s3: filter_y_offset
lw s4, 144(a2) // s4: filter_n_offset
esp.movx.r.sar.bytes t3 // t3: output_sar_byte
beqz t3, esp32p4_s8_unaligned_conv2d_hwcn_prelu_128b
li s5, 8
beq t3, s5, esp32p4_s8_unaligned_conv2d_hwcn_prelu_64b
// esp32p4_s8_unaligned_conv2d_hwcn_prelu_32b:
esp32p4_s8_unaligned_conv2d_hwcn_prelu_32b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_32b_unaligned_vector_store q0, a0, t3
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_prelu_32b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_prelu_64b:
esp32p4_s8_unaligned_conv2d_hwcn_prelu_64b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_64b_unaligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_prelu_64b_multiple_loop
j esp32p4_s8_unaligned_conv2d_hwcn_prelu_n_remainder
esp32p4_s8_unaligned_conv2d_hwcn_prelu_128b:
esp32p4_s8_unaligned_conv2d_hwcn_prelu_128b_multiple_loop:
mv t3, a1 // t3: input_ptr
esp.zero.qacc
esp32p4_s8_unaligned_conv2d_hwc16 q0, q1, q2, q3, q4, t3, a3, t0, a4, t2, a6, a7, s2, a2, s3, s4, s5
esp32p4_s8_128b_vector_shift_result q0, a5
esp32p4_s8_128b_vector_prelu q0, q1, s9, s10
esp32p4_s8_128b_aligned_vector_store q0, a0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_prelu_128b_multiple_loop
esp32p4_s8_unaligned_conv2d_hwcn_prelu_n_remainder:
lw t1, 140(a2) // t1: n_remainder
beqz t1, esp32p4_s8_unaligned_conv2d_hwcn_prelu_n_remainder_end
lw s3, 160(a2) // a3: filter_y_offset_unaligned
lw s4, 164(a2) // t3: filter_n_offset_unaligned
lw a3, 168(a2) // a3: filter_ptr_unaligned
li t4, 15
sub t4, t4, a4 // t4: 15 - c_remainder
li t5, 0 // t5: zero
esp32p4_s8_unaligned_conv2d_hwcn_prelu_n_remainder_loop:
mv t3, a1 // t3: input_ptr
esp.zero.xacc
esp32p4_s8_unaligned_conv2d_hwc1 q0, q1, q2, q3, q4, q5, t3, a3, t0, a4, t2, a6, a7, s2, a2, t4, t5, s3, s4
esp32p4_s8_element_result s0, a5
esp32p4_clamp s0, s1, s8
esp32p4_s8_element_prelu s0, s9, s10
esp32p4_s8_element_store a0, s0
addi t1, t1, -1
bnez t1, esp32p4_s8_unaligned_conv2d_hwcn_prelu_n_remainder_loop
esp32p4_s8_unaligned_conv2d_hwcn_prelu_n_remainder_end:
esp32p4_pop_36_stacks_9r s2, s3, s4, s5, s0, s1, s8, s9, s10
ret
|
georgevio/IoT-Embedded
| 6,608
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16.S
|
############################################################################################################################################################
# result process for conv2d / depthwise_conv2d
############################################################################################################################################################
.macro esp32p4_s16_conv2d_128b_vector_bias bias_ptr
esp.ld.qacc.l.l.128.ip \bias_ptr, 16
esp.ld.qacc.l.h.128.ip \bias_ptr, 16
esp.ld.qacc.h.l.128.ip \bias_ptr, 16
esp.ld.qacc.h.h.128.ip \bias_ptr, 16
.endm
.macro esp32p4_s16_conv2d_element_bias bias_ptr
esp.ld.xacc.ip \bias_ptr, 8
.endm
############################################################################################################################################################
# esp32p4_s16_32b_unaligned_vector series
############################################################################################################################################################
.macro esp32p4_s16_32b_unaligned_vector_store output_v, output_ptr, tmp
esp.movi.32.a \output_v, \tmp, 0
sw \tmp, 0(\output_ptr)
esp.movi.32.a \output_v, \tmp, 1
sw \tmp, 4(\output_ptr)
esp.movi.32.a \output_v, \tmp, 2
sw \tmp, 8(\output_ptr)
esp.movi.32.a \output_v, \tmp, 3
sw \tmp, 12(\output_ptr)
addi \output_ptr, \output_ptr, 16
.endm
.macro esp32p4_s16_32b_unaligned_l_vector_store output_v, output_ptr, tmp
esp.movi.32.a \output_v, \tmp, 0
sw \tmp, 0(\output_ptr)
esp.movi.32.a \output_v, \tmp, 1
sw \tmp, 4(\output_ptr)
addi \output_ptr, \output_ptr, 8
.endm
############################################################################################################################################################
# esp32p4_s16_64b_unaligned_vector series
############################################################################################################################################################
.macro esp32p4_s16_64b_unaligned_vector_store output_v, output_ptr
esp.vst.l.64.ip \output_v, \output_ptr, 8
esp.vst.h.64.ip \output_v, \output_ptr, 8
.endm
############################################################################################################################################################
# esp32p4_s16_128b_vector series
############################################################################################################################################################
.macro esp32p4_s16_128b_vector_shift_result output_v, mac_shift
esp.srcmb.s16.qacc \output_v, \mac_shift, 1
.endm
.macro esp32p4_s16_128b_aligned_vector_store output_v, output_ptr
esp.vst.128.ip \output_v, \output_ptr, 16
.endm
.macro esp32p4_s16_128b_vector_relu output_v, activation_alpha, activation_shift
# LeakyReLU
esp.vrelu.s16 \output_v, \activation_alpha, \activation_shift
.endm
.macro dl_esp32p4_128b_unaligned_store0 output_v, output_ptr, tmp32
esp.movi.32.a \output_v, \tmp32, 0
sw \tmp32, 0(\output_ptr)
esp.movi.32.a \output_v, \tmp32, 1
sw \tmp32, 4(\output_ptr)
esp.movi.32.a \output_v, \tmp32, 2
sw \tmp32, 8(\output_ptr)
esp.movi.32.a \output_v, \tmp32, 3
sw \tmp32, 12(\output_ptr)
addi \output_ptr, \output_ptr, 16
.endm
.macro dl_esp32p4_128b_unaligned_store1 output_v, output_ptr
esp.vst.l.64.ip \output_v, \output_ptr, 8
esp.vst.h.64.ip \output_v, \output_ptr, 8
.endm
.macro dl_esp32p4_128b_last_store_data tmp_q, output_v, tmp_a, c_remainder_bytes
beqz \c_remainder_bytes, 600f
li \tmp_a, 15
sub \tmp_a, \tmp_a, \c_remainder_bytes
li \c_remainder_bytes, 0
esp.slcxxp.2q \tmp_q, \output_v, \tmp_a, \c_remainder_bytes #left shift to make the rest part 0
esp.srcxxp.2q \output_v, \tmp_q, \tmp_a, \c_remainder_bytes #right shift to lower bits
600:
.endm
.macro dl_esp32p4_s16_store_remainder vector_data, c_remainder, tmp_a, output_ptr
607: # remainder == 7, 0x111
andi \tmp_a, \c_remainder, 4
beqz \tmp_a, 603f
andi \tmp_a, \c_remainder, 2
beqz \tmp_a, 605f
andi \tmp_a, \c_remainder, 1
beqz \tmp_a, 606f
esp.movi.32.a \vector_data, \tmp_a, 0
sw \tmp_a, 0(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 1
sw \tmp_a, 4(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 2
sw \tmp_a, 8(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 3
sh \tmp_a, 12(\output_ptr)
j 600f
606: # remainder == 6, 0x110
esp.movi.32.a \vector_data, \tmp_a, 0
sw \tmp_a, 0(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 1
sw \tmp_a, 4(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 2
sw \tmp_a, 8(\output_ptr)
j 600f
605: # remainder == 5, 0x101
andi \tmp_a, \c_remainder, 1
beqz \tmp_a, 604f
esp.movi.32.a \vector_data, \tmp_a, 0
sw \tmp_a, 0(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 1
sw \tmp_a, 4(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 2
sh \tmp_a, 8(\output_ptr)
j 600f
604: # remainder == 4, 0x100
esp.movi.32.a \vector_data, \tmp_a, 0
sw \tmp_a, 0(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 1
sw \tmp_a, 4(\output_ptr)
j 600f
603: # remainder == 3, 0x011
andi \tmp_a, \c_remainder, 2
beqz \tmp_a, 601f
andi \tmp_a, \c_remainder, 1
beqz \tmp_a, 602f
esp.movi.32.a \vector_data, \tmp_a, 0
sw \tmp_a, 0(\output_ptr)
esp.movi.32.a \vector_data, \tmp_a, 1
sh \tmp_a, 4(\output_ptr)
j 600f
602: # remainder == 2, 0x010
esp.movi.32.a \vector_data, \tmp_a, 0
sw \tmp_a, 0(\output_ptr)
j 600f
601: # remainder == 1, 0x001
andi \tmp_a, \c_remainder, 1
beqz \tmp_a, 600f
esp.movi.32.a \vector_data, \tmp_a, 0
sh \tmp_a, 0(\output_ptr)
600:
.endm
############################################################################################################################################################
# esp32p4_s16_element series
############################################################################################################################################################
.macro esp32p4_s16_element_result output, mac_shift
esp.srs.s.xacc \output, \mac_shift
.endm
.macro esp32p4_s16_element_store output_ptr, output
sh \output, 0(\output_ptr)
addi \output_ptr, \output_ptr, 2
.endm
.macro esp32p4_s16_element_leakyrelu output, alpha, shift
bgez \output, 0f
mul \output, \output, \alpha
sra \output, \output, \shift
0:
.endm
|
georgevio/IoT-Embedded
| 14,227
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_greater.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_greater_w1_8_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greater_w1_8_w2_8
.type dl_esp32p4_s16_greater_w1_8_w2_8, @function
#.section .iram1
dl_esp32p4_s16_greater_w1_8_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
esp32p4_s16_greater_w1_8_w2_8_loop:
beq t0, a3, esp32p4_s16_greater_w1_8_w2_8_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greater_w1_8_w2_8_loop
esp32p4_s16_greater_w1_8_w2_8_end:
ret
#void dl_esp32p4_s16_greater_w1_8_w2_1(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greater_w1_8_w2_1
.type dl_esp32p4_s16_greater_w1_8_w2_1, @function
#.section .iram1
dl_esp32p4_s16_greater_w1_8_w2_1:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s16_greater_w1_8_w2_1_loop:
beq t0, a3, esp32p4_s16_greater_w1_8_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greater_w1_8_w2_1_loop
esp32p4_s16_greater_w1_8_w2_1_end:
ret
#void dl_esp32p4_s16_greater_w1_1_w2_8(bool *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_greater_w1_1_w2_8
.type dl_esp32p4_s16_greater_w1_1_w2_8, @function
#.section .iram1
dl_esp32p4_s16_greater_w1_1_w2_8:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.16.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 3
esp.vldbc.16.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s16_greater_w1_1_w2_8_loop:
beq t0, a3, esp32p4_s16_greater_w1_1_w2_8_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.gt.s16 q2, q0, q1
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, 1
j esp32p4_s16_greater_w1_1_w2_8_loop
esp32p4_s16_greater_w1_1_w2_8_end:
ret
.align 2
.text
.global dl_esp32p4_s16_greater_w1_8_w2_8_unaligned
.type dl_esp32p4_s16_greater_w1_8_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greater_w1_8_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s16_greater_w1_8_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greater_w1_8_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greater_w1_8_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greater_w1_8_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
// esp.vst.128.ip q2, a0, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greater_w1_8_w2_8_unaligned_remainder
dl_esp32p4_s16_greater_w1_8_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greater_w1_8_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greater_w1_8_w2_8_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s16_greater_w1_8_w2_1_unaligned
.type dl_esp32p4_s16_greater_w1_8_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greater_w1_8_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s16_greater_w1_8_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greater_w1_8_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greater_w1_8_w2_1_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greater_w1_8_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greater_w1_8_w2_1_unaligned_remainder
dl_esp32p4_s16_greater_w1_8_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greater_w1_8_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s16 q2, q2, q5
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greater_w1_8_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s16_greater_w1_1_w2_8_unaligned
.type dl_esp32p4_s16_greater_w1_1_w2_8_unaligned, @function
#.section .iram1
dl_esp32p4_s16_greater_w1_1_w2_8_unaligned:
# a0: bool *output_ptr
# a1: int16_t *input0_ptr broadcast
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions): tmp value
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.16.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.16.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s16_greater_w1_1_w2_8_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
andi t0, a5, 7
beqz t0, dl_esp32p4_s16_greater_w1_1_w2_8_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp32p4_s16_32b_unaligned_l_vector_store q2, a0, a5
j dl_esp32p4_s16_greater_w1_1_w2_8_unaligned_remainder
// output sar = 0 or output sar = 8
dl_esp32p4_s16_greater_w1_1_w2_8_unaligned_64b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.ld.128.usar.ip q1, a2, 16
esp.vst.l.64.ip q2, a0, 8
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.gt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
esp.vst.l.64.ip q2, a0, 8
// j dl_esp32p4_s16_greater_w1_1_w2_8_unaligned_remainder
dl_esp32p4_s16_greater_w1_1_w2_8_unaligned_remainder:
beqz t5, dl_esp32p4_s16_greater_w1_1_w2_8_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.gt.s16 q2, q5, q2
esp.andq q2, q2, q7
esp.vunzip.8 q2, q6
srli t5, t5, 1
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s16_greater_w1_1_w2_8_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 14,525
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_and4d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand
.type dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand, @function
#.section .iram1
dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.andq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand
.type dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand, @function
#.section .iram1
dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.8.ip q1, a2, 0
esp.andq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand
.type dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand, @function
#.section .iram1
dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.8.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.andq q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned
.type dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned, @function
#.section .iram1
dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.andq q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_remainder
dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_and4d_bchw_w1_16_w2_16_simdand_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.andq q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned
.type dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned, @function
#.section .iram1
dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.andq q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.andq q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.andq q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.andq q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_remainder
dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a2, 0
dl_esp32p4_s8_and4d_bchw_w1_16_w2_1_simdand_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.andq q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned
.type dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned, @function
#.section .iram1
dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a2: int8_t *input0_ptr
# a1: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.andq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.andq q2, q5, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.andq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.andq q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.andq q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.andq q2, q5, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_remainder
dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a1, 0
dl_esp32p4_s8_and4d_bchw_w1_1_w2_16_simdand_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end___
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.andq q2, q5, q2
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end___:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 14,722
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s16_min4d.S
|
#include "dl_esp32p4_s16.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin
.type dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin, @function
#.section .iram1
dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vmin.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin
.type dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin, @function
#.section .iram1
dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.16.ip q1, a2, 0
esp.vmin.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin(int16_t *output_ptr, int16_t *input0_ptr, int16_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin
.type dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin, @function
#.section .iram1
dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin:
.align 2
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 3
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.16.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.vmin.s16 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned
.type dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned, @function
#.section .iram1
dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmin.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmin.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmin.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_remainder
dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s16_min4d_bchw_w1_8_w2_8_simdmin_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vmin.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned
.type dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned, @function
#.section .iram1
dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a1: int16_t *input0_ptr
# a2: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.vmin.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.vmin.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.vmin.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_remainder
dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a2, 0
dl_esp32p4_s16_min4d_bchw_w1_8_w2_1_simdmin_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a2, 0
addi s0, a2, 0
esp.vmin.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned
.type dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned, @function
#.section .iram1
dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int16_t *output_ptr
# a2: int16_t *input0_ptr
# a1: int16_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s16_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.vmin.s16 q2, q5, q2 #esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.vmin.s16 q2, q5, q2 #esp.vmin.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store0 q2, a0, s1
j dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_remainder
#output sar = 0
dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.vmin.s16 q2, q5, q2 #esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.vmin.s16 q2, q5, q2 #esp.vmin.s16 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_remainder
#output sar = 8
dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
esp.vmin.s16 q2, q5, q2 #esp.vmin.s16 q2, q2, q5
esp.ld.128.usar.ip q1, a2, 16
dl_esp32p4_128b_unaligned_store1 q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.vmin.s16 q2, q5, q2 #esp.vmin.s16 q2, q2, q5
dl_esp32p4_128b_unaligned_store1 q2, a0
j dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_remainder
dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.16.ip q5, a1, 0
dl_esp32p4_s16_min4d_bchw_w1_1_w2_8_simdmin_unaligned_remainder:
beqz t5, dl_esp32p4_s16_unaligned_add2d_endtest
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.16.ip q5, a1, 0
addi s0, a1, 0
esp.vmin.s16 q2, q5, q2 #esp.vmin.s16 q2, q2, q5
srli t5, t5, 1
dl_esp32p4_s16_store_remainder q2, t5, s1, a0
dl_esp32p4_s16_unaligned_add2d_endtest:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 14,597
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_min4d.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin
.type dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin, @function
#.section .iram1
dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop:
beq t0, a3, end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vmin.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop
end:
ret
#void dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin
.type dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin, @function
#.section .iram1
dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop_:
beq t0, a3, end_
esp.vld.128.ip q0, a1, 16
esp.vldbc.8.ip q1, a2, 0
esp.vmin.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop_
end_:
ret
#void dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin
.type dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin, @function
#.section .iram1
dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin:
.align 2
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: length
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
loop__:
beq t0, a3, end__
esp.vldbc.8.ip q0, a1, 0
esp.vld.128.ip q1, a2, 16
esp.vmin.s8 q2, q0, q1
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j loop__
end__:
ret
.align 2
.text
.global dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned
.type dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned, @function
#.section .iram1
dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmin.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmin.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmin.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmin.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vmin.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.movx.r.sar.bytes s0
esp.src.q.qup q5, q3, q4
esp.vmin.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_remainder
dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
esp.ld.128.usar.xp q3, a2, t5
esp.movx.r.sar.bytes s0
dl_esp32p4_s8_min4d_bchw_w1_16_w2_16_simdmin_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
esp.ld.128.usar.ip q4, a2, 0
esp.movx.w.sar.bytes s0
esp.src.q q5, q3, q4
esp.vmin.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned
.type dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned, @function
#.section .iram1
dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a1, 16
#esp.ld.128.usar.ip q3, a2, 16
esp.ld.128.usar.ip q1, a1, 16
beqz s1, dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.vmin.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.vmin.s8 q2, q2, q5
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.vmin.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.vmin.s8 q2, q2, q5
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
esp.vmin.s8 q2, q2, q5
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a1, a1, -16
add a1, a1, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a2, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.vmin.s8 q2, q2, q5
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_remainder
dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a1, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a2, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a2, 0
dl_esp32p4_s8_min4d_bchw_w1_16_w2_1_simdmin_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end__
esp.ld.128.usar.ip q1, a1, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a2, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a2, 0
addi s0, a2, 0
esp.vmin.s8 q2, q2, q5
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end__:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
.align 2
.text
.global dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned
.type dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned, @function
#.section .iram1
dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned:
.align 2
esp32p4_push_128_stacks_4r s0, s1, s8, s9
# a0: int8_t *output_ptr
# a2: int8_t *input0_ptr
# a1: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: input_shift
# t3: output_scale
# t4: output_shift
# t5: c_remainder
lw a4, 64(a3)
lw t5, 76(a3)
#lw a5, 88(a3)
#bgez a5, dl_esp32p4_s8_unaligned_rescale_add2d_11c
# input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 #get output_ptr sar_byte
esp.movx.r.sar.bytes s1
bltz a4, dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_small_remainder # channel < 16
esp.ld.128.usar.ip q0, a2, 16
#esp.ld.128.usar.ip q3, a1, 16
esp.ld.128.usar.ip q1, a2, 16
beqz s1, dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_0
li t0, 8
beq s1, t0, dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_1
add t0, a4, x0
blez t0, 1f
0:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.vmin.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
addi t0, t0, -1
bgtz t0, 0b
1:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.vmin.s8 q2, q5, q2
esp32p4_s8_32b_unaligned_vector_store q2, a0, s1
j dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_remainder
#output sar = 0
dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_0:
add t0, a4, x0
blez t0, 3f
2:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.vmin.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.vmin.s8 q2, q5, q2
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_remainder
# #output sar = 8
dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_1:
add t0, a4, x0
blez t0, 5f
4:
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 16
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
esp.vmin.s8 q2, q5, q2
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
addi a2, a2, -16
add a2, a2, t5
esp.movx.r.sar.bytes t6
esp.src.q.qup q2, q0, q1
#esp.ld.128.usar.xp q4, a1, t5
#esp.movx.r.sar.bytes s0
#esp.src.q.qup q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.vmin.s8 q2, q5, q2
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_remainder
dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_small_remainder:
esp.ld.128.usar.xp q0, a2, t5
esp.movx.r.sar.bytes t6
#esp.ld.128.usar.xp q3, a1, t5
#esp.movx.r.sar.bytes s0
esp.vldbc.8.ip q5, a1, 0
dl_esp32p4_s8_min4d_bchw_w1_1_w2_16_simdmin_unaligned_remainder:
beqz t5, dl_esp32p4_s8_unaligned_add2d_end___
esp.ld.128.usar.ip q1, a2, 0
esp.movx.w.sar.bytes t6
esp.src.q q2, q0, q1
#esp.ld.128.usar.ip q4, a1, 0
#esp.movx.w.sar.bytes s0
#esp.src.q q5, q3, q4
esp.vldbc.8.ip q5, a1, 0
addi s0, a1, 0
esp.vmin.s8 q2, q5, q2
dl_esp32p4_s8_store_remainder q2, t4, t6, s0, s1, t0, a0, t5
dl_esp32p4_s8_unaligned_add2d_end___:
esp32p4_pop_128_stacks_4r s0, s1, s8, s9
ret
|
georgevio/IoT-Embedded
| 16,950
|
esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_mul.S
|
#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_mul_w1_16_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_mul_w1_16_w2_16
.type dl_esp32p4_s8_mul_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_mul_w1_16_w2_16:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw a5, 80(a3)
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
mv t0, a4
blez t0, dl_esp32p4_s8_mul_w1_16_w2_16_loop_last
dl_esp32p4_s8_mul_w1_16_w2_16_loop:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp.vld.128.ip q1, a2, 16
esp32p4_s8_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, dl_esp32p4_s8_mul_w1_16_w2_16_loop
dl_esp32p4_s8_mul_w1_16_w2_16_loop_last:
esp.zero.qacc
esp.vmulas.s8.qacc q0, q1
esp32p4_s8_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
ret
#void dl_esp32p4_s8_mul_w1_16_w2_1(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_mul_w1_16_w2_1
.type dl_esp32p4_s8_mul_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_mul_w1_16_w2_1:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw a5, 80(a3)
esp.vld.128.ip q0, a1, 16
esp.vldbc.8.ip q1, a2, 0 // input1 broadcast
mv t0, a4
blez t0, dl_esp32p4_s8_mul_w1_16_w2_1_loop_last
dl_esp32p4_s8_mul_w1_16_w2_1_loop:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q0, a1, 16, q0, q1
esp32p4_s8_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, dl_esp32p4_s8_mul_w1_16_w2_1_loop
dl_esp32p4_s8_mul_w1_16_w2_1_loop_last:
esp.zero.qacc
esp.vmulas.s8.qacc q0, q1
esp32p4_s8_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
ret
#void dl_esp32p4_s8_mul_w1_1_w2_16(int8_t *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_mul_w1_1_w2_16
.type dl_esp32p4_s8_mul_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_mul_w1_1_w2_16:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: mul_shift
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw a5, 80(a3)
esp.vldbc.8.ip q0, a1, 0 // input0 broadcast
esp.vld.128.ip q1, a2, 16
mv t0, a4
blez t0, dl_esp32p4_s8_mul_w1_1_w2_16_loop_last
dl_esp32p4_s8_mul_w1_1_w2_16_loop:
esp.zero.qacc
esp.vmulas.s8.qacc.ld.ip q1, a2, 16, q0, q1
esp32p4_s8_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, dl_esp32p4_s8_mul_w1_1_w2_16_loop
dl_esp32p4_s8_mul_w1_1_w2_16_loop_last:
esp.zero.qacc
esp.vmulas.s8.qacc q0, q1
esp32p4_s8_128b_vector_shift_result q2, a5
esp.vst.128.ip q2, a0, 16
ret
.align 2
.text
.global dl_esp32p4_s8_mul_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_mul_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_mul_w1_16_w2_16_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6: mul_shift
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
lw t6, 80(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.zero.qacc
esp.src.q.qup q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.zero.qacc
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_mul_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_mul_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_mul_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_mul_w1_16_w2_1_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6: mul_shift
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
lw t6, 80(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.zero.qacc
esp.src.q q2, q0, q1
esp.vmulas.s8.qacc q2, q5
esp32p4_s8_128b_vector_shift_result q2, t6
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_mul_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_mul_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_mul_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_mul_w1_1_w2_16_unaligned:
# a0: int8_t *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6: mul_shift
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
lw a4, 64(a3)
lw t5, 76(a3)
lw t6, 80(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q5, q2
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q5, q2
esp32p4_s8_128b_vector_shift_result q2, t6
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q5, q2
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q5, q2
esp32p4_s8_128b_vector_shift_result q2, t6
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q5, q2
esp32p4_s8_128b_vector_shift_result q2, t6
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.zero.qacc
esp.src.q.qup q2, q0, q1
esp.vmulas.s8.qacc q5, q2
esp32p4_s8_128b_vector_shift_result q2, t6
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.zero.qacc
esp.src.q q2, q0, q1
esp.vmulas.s8.qacc q5, q2
esp32p4_s8_128b_vector_shift_result q2, t6
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_mul_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
|
georgevio/IoT-Embedded
| 17,451
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esp-idf/esp32-s3-face-recogn/managed_components/espressif__esp-dl/dl/base/isa/esp32p4/dl_esp32p4_s8_lessorequal.S
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#include "dl_esp32p4_s8.S"
#include "dl_esp32p4_common.S"
#void dl_esp32p4_s8_lessorequal_w1_16_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_lessorequal_w1_16_w2_16
.type dl_esp32p4_s8_lessorequal_w1_16_w2_16, @function
#.section .iram1
dl_esp32p4_s8_lessorequal_w1_16_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
li t0, 0
esp32p4_s8_lessorequal_w1_16_w2_16_loop:
beq t0, a3, esp32p4_s8_lessorequal_w1_16_w2_16_end
esp.vld.128.ip q0, a1, 16
esp.vld.128.ip q1, a2, 16
esp.vcmp.lt.s8 q2, q0, q1
esp.vcmp.eq.s8 q6, q0, q1
esp.vmax.u8 q2, q2, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_lessorequal_w1_16_w2_16_loop
esp32p4_s8_lessorequal_w1_16_w2_16_end:
ret
#void dl_esp32p4_s8_lessorequal_w1_16_w2_1(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_lessorequal_w1_16_w2_1
.type dl_esp32p4_s8_lessorequal_w1_16_w2_1, @function
#.section .iram1
dl_esp32p4_s8_lessorequal_w1_16_w2_1:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q1, a2, 0 // input1 broadcast
li t0, 0
esp32p4_s8_lessorequal_w1_16_w2_1_loop:
beq t0, a3, esp32p4_s8_lessorequal_w1_16_w2_1_end
esp.vld.128.ip q0, a1, 16
esp.vcmp.lt.s8 q2, q0, q1
esp.vcmp.eq.s8 q6, q0, q1
esp.vmax.u8 q2, q2, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_lessorequal_w1_16_w2_1_loop
esp32p4_s8_lessorequal_w1_16_w2_1_end:
ret
#void dl_esp32p4_s8_lessorequal_w1_1_w2_16(bool *output_ptr, int8_t *input0_ptr, int8_t *input1_ptr, int lenght);
.align 2
.text
.global dl_esp32p4_s8_lessorequal_w1_1_w2_16
.type dl_esp32p4_s8_lessorequal_w1_1_w2_16, @function
#.section .iram1
dl_esp32p4_s8_lessorequal_w1_1_w2_16:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args / length
# a4: tmp value
# a5:
# t3:
# t4:
# t5:
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi a4, a3, 100
esp.vldbc.8.ip q7, a4, 0
lw a4, 44(a3)
srai a3, a4, 4
esp.vldbc.8.ip q0, a1, 0 // input0 broadcast
li t0, 0
esp32p4_s8_lessorequal_w1_1_w2_16_loop:
beq t0, a3, esp32p4_s8_lessorequal_w1_1_w2_16_end
esp.vld.128.ip q1, a2, 16
esp.vcmp.lt.s8 q2, q0, q1
esp.vcmp.eq.s8 q6, q0, q1
esp.vmax.u8 q2, q2, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
addi t0, t0, 1
j esp32p4_s8_lessorequal_w1_1_w2_16_loop
esp32p4_s8_lessorequal_w1_1_w2_16_end:
ret
.align 2
.text
.global dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned
.type dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4:
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.ld.128.usar.ip q0, a1, 16
esp.ld.128.usar.ip q3, a2, 16
bltz a4, dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.ld.128.usar.ip q4, a2, 16
esp.src.q.qup q5, q3, q4
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_remainder
dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.ld.128.usar.xp q4, a2, t5
esp.src.q q5, q3, q4
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_lessorequal_w1_16_w2_16_unaligned_end:
addi a1, a1, -16
addi a2, a2, -16
ret
.align 2
.text
.global dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned
.type dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned, @function
#.section .iram1
dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr
# a2: int8_t *input1_ptr broadcast
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // get output_ptr sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a2, 0 // input1 broadcast
esp.ld.128.usar.ip q0, a1, 16
bltz a4, dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a1, 16
beqz a5, dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a1, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_remainder
dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_remainder:
beqz t5, dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_end
esp.ld.128.usar.xp q1, a1, t5
esp.src.q q2, q0, q1
esp.vcmp.lt.s8 q1, q2, q5
esp.vcmp.eq.s8 q6, q2, q5
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_lessorequal_w1_16_w2_1_unaligned_end:
addi a1, a1, -16
ret
.align 2
.text
.global dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned
.type dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned, @function
#.section .iram1
dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned:
# a0: bool *output_ptr
# a1: int8_t *input0_ptr broadcast
# a2: int8_t *input1_ptr
# a3: void *args
# a4: c_div_x_1
# a5: output sar_byte / tmp value
# t3: tmp value
# t4: tmp value
# t5: c_remainder
# t6:
# a6(not for extension instructions):
# a7(not for extension instructions):
# t0(not for extension instructions):
# t1(not for extension instructions):
# t2(not for extension instructions):
# s2(not for extension instructions):
# s3(not for extension instructions):
# s4(not for extension instructions):
# s5(not for extension instructions):
# s0:
# s1:
# s8:
# s9:
# s10:
# s11:
addi t3, a3, 100
esp.vldbc.8.ip q7, t3, 0
lw a4, 64(a3)
lw t5, 76(a3)
// input0 exp = input1 exp = output exp
esp.ld.128.usar.ip q5, a0, 0 // output sar_byte
esp.movx.r.sar.bytes a5
esp.vldbc.8.ip q5, a1, 0 // input0 broadcast
esp.ld.128.usar.ip q0, a2, 16
bltz a4, dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_remainder // channel < 16
esp.ld.128.usar.ip q1, a2, 16
beqz a5, dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_128b
li t0, 8
beq a5, t0, dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_64b
mv t0, a4
beqz t0, 1f
0:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
addi t0, t0, -1
bgtz t0, 0b
1:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_32b_unaligned_vector_store q2, a0, a5
j dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_remainder
// output sar = 0
dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_128b:
mv t0, a4
beqz t0, 3f
2:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp.vst.128.ip q2, a0, 16
addi t0, t0, -1
bgtz t0, 2b
3:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.vst.128.ip q2, a0, 16
j dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_remainder
// output sar = 8
dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_64b:
mv t0, a4
beqz t0, 5f
4:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp.ld.128.usar.ip q1, a2, 16
esp32p4_s8_64b_unaligned_vector_store q2, a0
addi t0, t0, -1
bgtz t0, 4b
5:
esp.src.q.qup q2, q0, q1
esp.vcmp.lt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
esp32p4_s8_64b_unaligned_vector_store q2, a0
j dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_remainder
dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_remainder:
beqz t5, dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_end
esp.ld.128.usar.xp q1, a2, t5
esp.src.q q2, q0, q1
esp.vcmp.lt.s8 q1, q5, q2
esp.vcmp.eq.s8 q6, q5, q2
esp.vmax.u8 q2, q1, q6
esp.andq q2, q2, q7
dl_esp32p4_s8_store_remainder q2, t4, t6, a5, t3, t0, a0, t5
dl_esp32p4_s8_lessorequal_w1_1_w2_16_unaligned_end:
addi a2, a2, -16
ret
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