repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
stsp/newlib-ia16
| 1,932
|
libgloss/msp430/ciosyscalls.S
|
/* Copyright (c) 2012, 2013 Red Hat, Inc. All rights reserved.
This copyrighted material is made available to anyone wishing to use, modify,
copy, or redistribute it subject to the terms and conditions of the BSD
License. This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY expressed or implied, including the implied warranties
of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. A copy of this license
is available at http://www.opensource.org/licenses. Any Red Hat trademarks that
are incorporated in the source code or documentation are not subject to the BSD
License and may only be used or replicated with the express permission of
Red Hat, Inc.
*/
/* Empty syscall definitions for when we run on real hardware. */
#include "../syscall.h"
#include "memmodel.h"
#define ENOSYS 88
.macro sc,a
sc2 \a,\a
.endm
.macro START_FUNC name1, name2=foo
.pushsection .text.\name1,"ax",@progbits
.p2align 1
.weak \name1
.global \name1
\name1:
.ifnc \name2,foo
.weak \name2
.global \name2
\name2:
.endif
.endm
.macro END_FUNC name1, name2=foo
.type \name1 , @function
.size \name1 , . - \name1
.ifnc \name2,foo
.type \name2 , @function
.size \name2 , . - \name2
.endif
.popsection
.endm
START_FUNC exit, _exit
/* For some reason, the board fails to stop at a breakpoint
placed on top of a software breakpoint instruction. */
/* MOV.B #0,R3 ; this is a software breakpoint instruction */
1: br_ #1b
END_FUNC exit, _exit
START_FUNC isatty,_isatty
MOV #1,R12
ret_
END_FUNC isatty,_isatty
START_FUNC getpid
MOV #42,R12
ret_
END_FUNC getpid
.macro sc2,name,num
START_FUNC \name
call_ #__errno
movx_ #ENOSYS, @R12
MOV.W #-1,R12
ret_
END_FUNC \name
.endm
#define SC(n) sc2 n,SYS_##n
SC (open)
SC (close)
SC (read)
/* SC (write)*/
SC (fstat)
SC (lseek)
SC (kill)
|
stsp/newlib-ia16
| 1,756
|
libgloss/iq2000/crt0.S
|
##==============================================================================
##
## crt0.S
##
## IQ2000 startup code
##
##==============================================================================
##
## Copyright (c) 2000, Cygnus Solutions, A Red Hat Company
##
## The authors hereby grant permission to use, copy, modify, distribute,
## and license this software and its documentation for any purpose, provided
## that existing copyright notices are retained in all copies and that this
## notice is included verbatim in any distributions. No written agreement,
## license, or royalty fee is required for any of the authorized uses.
## Modifications to this software may be copyrighted by their authors
## and need not follow the licensing terms described here, provided that
## the new terms are clearly indicated on the first page of each file where
## they apply.
##
##------------------------------------------------------------------------------
.file "crt0.S"
##------------------------------------------------------------------------------
## Startup code
.section .text
.global _start
_start:
lui %29,%hi(__stack)
ori %29,%29,%lo(__stack)
lui %24,%hi(_edata) # get start of bss
ori %24,%24,%lo(_edata)
lui %25,%hi(_end) # get end of bss
ori %25,%25,%lo(_end)
beq %24,%25,.L0 # check if end and start are the same
# do nothing if no bss
.L1:
sb %0,0(%24) # clear a byte and bump pointer
addi %24,%24,1
bne %24,%25,.L1
nop
.L0:
jal _main # call _main to run ctors/dtors
nop
xor %4,%4,%4
jal main # call main program
xor %5,%5,%5
jal exit # all done, no need to return or
or %4,%0,%2 # exit with main's return value
.section .data
.global __dso_handle
.weak __dso_handle
__dso_handle:
.long 0
|
stsp/newlib-ia16
| 1,767
|
libgloss/i386/cygmon-crt0.S
|
/*
* crt0 startup code for user programs running under Cygmon
*
* Copyright (c) 1998, 2000 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#define _S2(P,X) P ## X
#define _S1(P,X) _S2(P,X)
#define SYM(X) _S1(__USER_LABEL_PREFIX__,X)
.data
.align 8
SYM(environ):
.long 0
SYM(argc):
.long 0
.text
.align 4
.globl __start
__start:
/* see if the stack is already setup. if not, then default
* to using the value of %sp as set by the ROM monitor
*/
movl $__stack, %eax
testl %eax, %eax
jz 1f
movl %eax, %esp
1:
mov $0, %ebp
movl $__bss_start, %edi
movl $__bss_end, %ecx
subl %edi, %ecx
xorl %eax, %eax
rep; stosb
pushl $SYM(__sigtramp)
pushl $0
call SYM(__install_signal_handler)
popl %eax
pushl $SYM(__do_global_dtors)
call SYM(atexit)
popl %eax
call SYM(__do_global_ctors)
pushl $SYM(argc)
call SYM(__get_program_arguments)
popl %ecx
movl SYM(argc), %ecx
pushl %eax
pushl %ecx
call SYM(main)
popl %ecx
popl %edx
/* call exit from the C library so atexit gets called, and the
* C++ destructors get run. This calls our exit routine below
* when it's done.
*/
pushl %eax
call SYM(exit)
3:
jmp 3b
|
stsp/newlib-ia16
| 2,967
|
libgloss/or1k/sync-asm.S
|
#include "include/or1k-asm.h"
#include "include/or1k-sprs.h"
.section .text
.global or1k_has_multicore_support
.type or1k_has_multicore_support,@function
or1k_has_multicore_support:
#ifdef __OR1K_MULTICORE__
// Return 1
OR1K_DELAYED(
OR1K_INST(l.ori r11,r0,1),
OR1K_INST(l.jr r9)
)
#else
// Return 0
OR1K_DELAYED(
OR1K_INST(l.or r11,r0,r0),
OR1K_INST(l.jr r9)
)
#endif
.global or1k_coreid
.type or1k_coreid,@function
or1k_coreid:
#ifdef __OR1K_MULTICORE__
// Return SPR with core identifier
OR1K_DELAYED(
OR1K_INST(l.mfspr r11,r0,OR1K_SPR_SYS_COREID_ADDR),
OR1K_INST(l.jr r9)
)
#else
// Return 0
OR1K_DELAYED(
OR1K_INST(l.or r11,r0,r0),
OR1K_INST(l.jr r9)
)
#endif
.global or1k_numcores
.type or1k_numcores,@function
or1k_numcores:
#ifdef __OR1K_MULTICORE__
// Return SPR with number of cores
OR1K_DELAYED(
OR1K_INST(l.mfspr r11,r0,OR1K_SPR_SYS_NUMCORES_ADDR),
OR1K_INST(l.jr r9)
)
#else
// Return 1
OR1K_DELAYED(
OR1K_INST(l.ori r11,r0,1),
OR1K_INST(l.jr r9)
)
#endif
.global or1k_sync_ll
.type or1k_sync_ll,@function
or1k_sync_ll:
#ifdef __OR1K_MULTICORE__
// Load word atomic
OR1K_DELAYED(
OR1K_INST(l.lwa r11, 0(r3)),
OR1K_INST(l.jr r9)
)
#else
// Simply load word, TODO: throw exception? which?
OR1K_DELAYED(
OR1K_INST(l.lwz r11, 0(r3)),
OR1K_INST(l.jr r9)
)
#endif
.global or1k_sync_sc
.type or1k_sync_sc,@function
or1k_sync_sc:
#ifdef __OR1K_MULTICORE__
// swa sets the flag if it was succesfull
// Store the value to address and set flag
l.swa 0(r3),r4
OR1K_DELAYED(
// Set return to success speculatively (may go to delay slot)
OR1K_INST(l.ori r11,r0,1),
// If the swa was successfull, jump to end
OR1K_INST(l.bf .or1k_sync_sc_done)
)
// If the swa was not successfull, set
l.or r11,r0,r0
.or1k_sync_sc_done:
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
#else
// Simply store word, TODO: throw exception? which?
OR1K_DELAYED(
OR1K_INST(l.sw 0(r3),r4),
OR1K_INST(l.jr r9)
)
#endif
.global or1k_sync_cas
.type or1k_sync_sc,@function
or1k_sync_cas:
#ifdef __OR1K_MULTICORE__
/* Load linked address value to return register */
l.lwa r11,0(r3)
/* Compare value to parameter */
l.sfeq r11,r4
/* If not equal: abort and return the read value */
OR1K_DELAYED_NOP(OR1K_INST(l.bnf .or1k_sync_cas_done))
/* If compare was successfull: try writing */
l.swa 0(r3),r5
/* If writing was not successful: restart */
OR1K_DELAYED_NOP(OR1K_INST(l.bnf or1k_sync_cas))
.or1k_sync_cas_done:
/* Return value is the original read value */
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
#else
// Non-atomic CAS, TODO: throw exception? which?
l.lwz r11,0(r3)
l.sfeq r11,r4
OR1K_DELAYED_NOP(OR1K_INST(l.bnf .or1k_sync_cas_done))
l.sw 0(r3),r5
.or1k_sync_cas_done:
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
#endif
.global or1k_sync_tsl
.type or1k_sync_tsl,@function
or1k_sync_tsl:
l.or r4,r0,r0
OR1K_DELAYED(
OR1K_INST(l.addi r5,r0,1),
OR1K_INST(l.j or1k_sync_cas)
)
|
stsp/newlib-ia16
| 1,070
|
libgloss/or1k/outbyte.S
|
/* outbyte.S -- Write one byte for OpenRISC 1000.
*
* Copyright (c) 2014 Authors
*
* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "include/or1k-asm.h"
.global _or1k_outbyte
.text
_or1k_outbyte:
LOAD_SYMBOL_2_GPR(r4,_or1k_board_uart_base)
l.lwz r4, 0(r4)
l.sfeq r4, r0
OR1K_DELAYED_NOP(l.bf .Lnouart)
.Luart:
OR1K_DELAYED_NOP(l.j _or1k_uart_write)
.Lnouart:
OR1K_DELAYED(
OR1K_INST(l.nop 0x4),
OR1K_INST(l.jr r9)
)
|
stsp/newlib-ia16
| 2,265
|
libgloss/or1k/mmu-asm.S
|
/* mmu-asm.S -- MMU handling for OpenRISC 1000.
*
* Copyright (c) 2011, 2014 Authors
*
* Contributor Julius Baxter <juliusbaxter@gmail.com>
* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* -------------------------------------------------------------------------- */
/*!Function to control MMU
*/
/* -------------------------------------------------------------------------- */
#include "include/or1k-asm.h"
#include "include/or1k-sprs.h"
/* MMU control functions always switch MMU control with a l.rfe to return
from function */
.section .text
.global or1k_dmmu_enable
or1k_dmmu_enable:
l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR
l.ori r3,r3,OR1K_SPR_SYS_SR_DME_MASK
l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE
l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE
OR1K_DELAYED_NOP(OR1K_INST(l.rfe))
.global or1k_dmmu_disable
or1k_dmmu_disable:
l.ori r3,r0,OR1K_SPR_SYS_SR_DME_MASK
l.xori r4,r3,0xffff
l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR
l.and r3,r4,r3
l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE
l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE
OR1K_DELAYED_NOP(OR1K_INST(l.rfe))
.global or1k_immu_enable
or1k_immu_enable:
l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR
l.ori r3,r3,OR1K_SPR_SYS_SR_IME_MASK
l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE
l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE
OR1K_DELAYED_NOP(OR1K_INST(l.rfe))
.global or1k_immu_disable
or1k_immu_disable:
l.ori r3,r0,OR1K_SPR_SYS_SR_IME_MASK
l.xori r4,r3,0xffff
l.mfspr r3,r0,OR1K_SPR_SYS_SR_ADDR
l.and r3,r4,r3
l.mtspr r0,r3,OR1K_SPR_SYS_ESR_BASE
l.mtspr r0,r9,OR1K_SPR_SYS_EPCR_BASE
OR1K_DELAYED_NOP(OR1K_INST(l.rfe))
|
stsp/newlib-ia16
| 7,018
|
libgloss/or1k/exceptions-asm.S
|
/* exceptions-asm.S -- exception handling for OpenRISC 1000.
*
* Copyright (c) 2011, 2014 Authors
*
* Contributor Julius Baxter <juliusbaxter@gmail.com>
* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "include/or1k-asm.h"
#include "include/or1k-sprs.h"
/* -------------------------------------------------------------------------- */
/*!Generic exception handler function
*/
/* -------------------------------------------------------------------------- */
// Warning - this must be the same as specified in crt0.S
#define EXCEPTION_STACK_SIZE 136
.extern _or1k_exception_handler_table
.extern _or1k_exception_level
/* -------------------------------------------------------------------------- */
/*!Function to call appropriate exception handler
*/
/* -------------------------------------------------------------------------- */
.section .text
.global _or1k_exception_handler
.type _or1k_exception_handler,@function
/*
r3 = address of exception vector
r4 = address where exception occurred
*/
#define GPR_BUF_OFFSET(x) (x << 2)
_or1k_exception_handler:
/* Store remainder of state (r3,r4 stored in vector entry)*/
l.sw GPR_BUF_OFFSET(2)(r1),r2
l.sw GPR_BUF_OFFSET(5)(r1),r5
l.sw GPR_BUF_OFFSET(6)(r1),r6
l.sw GPR_BUF_OFFSET(7)(r1),r7
l.sw GPR_BUF_OFFSET(8)(r1),r8
l.sw GPR_BUF_OFFSET(9)(r1),r9
l.sw GPR_BUF_OFFSET(10)(r1),r10
l.sw GPR_BUF_OFFSET(11)(r1),r11
l.sw GPR_BUF_OFFSET(12)(r1),r12
l.sw GPR_BUF_OFFSET(13)(r1),r13
l.sw GPR_BUF_OFFSET(14)(r1),r14
l.sw GPR_BUF_OFFSET(15)(r1),r15
l.sw GPR_BUF_OFFSET(16)(r1),r16
l.sw GPR_BUF_OFFSET(17)(r1),r17
l.sw GPR_BUF_OFFSET(18)(r1),r18
l.sw GPR_BUF_OFFSET(19)(r1),r19
l.sw GPR_BUF_OFFSET(20)(r1),r20
l.sw GPR_BUF_OFFSET(21)(r1),r21
l.sw GPR_BUF_OFFSET(22)(r1),r22
l.sw GPR_BUF_OFFSET(23)(r1),r23
l.sw GPR_BUF_OFFSET(24)(r1),r24
l.sw GPR_BUF_OFFSET(25)(r1),r25
l.sw GPR_BUF_OFFSET(26)(r1),r26
l.sw GPR_BUF_OFFSET(27)(r1),r27
l.sw GPR_BUF_OFFSET(28)(r1),r28
l.sw GPR_BUF_OFFSET(29)(r1),r29
l.sw GPR_BUF_OFFSET(30)(r1),r30
l.sw GPR_BUF_OFFSET(31)(r1),r31
l.mfspr r14,r0,OR1K_SPR_SYS_EPCR_BASE
l.sw 0x80(r1),r14
l.mfspr r14,r0,OR1K_SPR_SYS_ESR_BASE
l.sw 0x84(r1),r14
/* Replace impure pointer for exception */
l.movhi r20,hi(_or1k_exception_impure_ptr)
l.ori r20,r20,lo(_or1k_exception_impure_ptr)
#ifdef __OR1K_MULTICORE__
l.lwz r20,0(r20)
l.mfspr r22,r0,OR1K_SPR_SYS_COREID_ADDR
l.slli r22,r22,2
l.add r20,r20,r22
#endif
l.lwz r20,0(r20)
l.movhi r21,hi(_or1k_current_impure_ptr)
l.ori r21,r21,lo(_or1k_current_impure_ptr)
#ifdef __OR1K_MULTICORE__
l.lwz r21,0(r21)
l.add r21,r21,r22
#endif
l.sw 0(r21),r20
/* Determine offset in table of exception handler using r3*/
l.andi r13,r3,0xff00
l.srli r13,r13,6
/* Substract 2 words, as we have no vector at 0 and no reset handler */
l.addi r13,r13,-8
/* r13 now contains offset in or1k_exception_handler_table for
function
*/
/* Get or1k_exception_handler_table address */
l.movhi r14,hi(_or1k_exception_handler_table)
l.ori r14,r14,lo(_or1k_exception_handler_table)
#ifdef __OR1K_MULTICORE__
/* Read the address of the array of cores */
/* r14 = (*or1k_exception_handler_table) */
l.lwz r14,0(r14)
/* Generate core offset in array (off = coreid*30*4 = coreid*120) */
/* r15 = coreid */
l.mfspr r15,r0,OR1K_SPR_SYS_COREID_ADDR
/* r16 = coreid * 128 */
l.slli r16,r15,7
/* r15 = coreid * 8 */
l.slli r15,r15,3
/* r15 = coreid*128 - coreid*8 = coreid*120 = off */
l.sub r15,r16,r15
/* r14 = (*or1k_exception_handler_table)[coreid] = r14 + off */
l.add r14,r14,r15
#endif
/* r14 now contains base of exception handler table */
/* add offset of exception vector */
l.add r14,r14,r13
/* load handler address from table */
l.lwz r13, 0(r14)
/* Check to see if this handler has been set yet */
l.sfne r13,r0
OR1K_DELAYED_NOP(OR1K_INST(l.bnf exception_exit))
/* Call exception handler, copy EPCR to r3 */
OR1K_DELAYED(
OR1K_INST(l.or r3,r4,r4),
OR1K_INST(l.jalr r13)
)
/* Restore impure pointer */
l.movhi r20,hi(_or1k_impure_ptr)
l.ori r20,r20,lo(_or1k_impure_ptr)
#ifdef __OR1K_MULTICORE__
l.lwz r20,0(r20)
l.mfspr r22,r0,OR1K_SPR_SYS_COREID_ADDR
l.slli r22,r22,2
l.add r20,r20,r22
#endif
l.lwz r20,0(r20)
l.movhi r21,hi(_or1k_current_impure_ptr)
l.ori r21,r21,lo(_or1k_current_impure_ptr)
#ifdef __OR1K_MULTICORE__
l.lwz r21,0(r21)
l.add r21,r21,r22
#endif
l.sw 0(r21),r20
/* Decrement the exception nesting level */
// Load the exception level entry
l.movhi r2,hi(_or1k_exception_level)
l.ori r2,r2,lo(_or1k_exception_level)
#ifdef __OR1K_MULTICORE__
// In multicore this is the pointer to an array
// Load pointer value
l.lwz r2,0(r2)
// Add word offset of this core's nesting level
l.add r2,r2,r22
#endif
// Load the nesting level entry
l.lwz r3,0(r2)
// Decrement nesting level
l.addi r3,r3,-1
// Store back the nesting level
l.sw 0(r2),r3
/* Restore state */
l.lwz r2,0x80(r1)
l.mtspr r0,r2,OR1K_SPR_SYS_EPCR_BASE
l.lwz r2,0x84(r1)
l.mtspr r0,r2,OR1K_SPR_SYS_ESR_BASE
l.lwz r2,GPR_BUF_OFFSET(2)(r1)
l.lwz r3,GPR_BUF_OFFSET(3)(r1)
l.lwz r4,GPR_BUF_OFFSET(4)(r1)
l.lwz r5,GPR_BUF_OFFSET(5)(r1)
l.lwz r6,GPR_BUF_OFFSET(6)(r1)
l.lwz r7,GPR_BUF_OFFSET(7)(r1)
l.lwz r8,GPR_BUF_OFFSET(8)(r1)
l.lwz r9,GPR_BUF_OFFSET(9)(r1)
l.lwz r10,GPR_BUF_OFFSET(10)(r1)
l.lwz r11,GPR_BUF_OFFSET(11)(r1)
l.lwz r12,GPR_BUF_OFFSET(12)(r1)
l.lwz r13,GPR_BUF_OFFSET(13)(r1)
l.lwz r14,GPR_BUF_OFFSET(14)(r1)
l.lwz r15,GPR_BUF_OFFSET(15)(r1)
l.lwz r16,GPR_BUF_OFFSET(16)(r1)
l.lwz r17,GPR_BUF_OFFSET(17)(r1)
l.lwz r18,GPR_BUF_OFFSET(18)(r1)
l.lwz r19,GPR_BUF_OFFSET(19)(r1)
l.lwz r20,GPR_BUF_OFFSET(20)(r1)
l.lwz r21,GPR_BUF_OFFSET(21)(r1)
l.lwz r22,GPR_BUF_OFFSET(22)(r1)
l.lwz r23,GPR_BUF_OFFSET(23)(r1)
l.lwz r24,GPR_BUF_OFFSET(24)(r1)
l.lwz r25,GPR_BUF_OFFSET(25)(r1)
l.lwz r26,GPR_BUF_OFFSET(26)(r1)
l.lwz r27,GPR_BUF_OFFSET(27)(r1)
l.lwz r28,GPR_BUF_OFFSET(28)(r1)
l.lwz r29,GPR_BUF_OFFSET(29)(r1)
l.lwz r30,GPR_BUF_OFFSET(30)(r1)
l.lwz r31,GPR_BUF_OFFSET(31)(r1)
// Restore original stack
l.lwz r1,GPR_BUF_OFFSET(1)(r1)
l.rfe
l.nop
exception_exit:
/* Exception handler not set, exit */
OR1K_DELAYED(
OR1K_INST(l.or r3,r4,r4),
OR1K_INST(l.jal exit)
)
|
stsp/newlib-ia16
| 20,330
|
libgloss/or1k/crt0.S
|
/* crt0.S -- startup file for OpenRISC 1000.
*
* Copyright (c) 2011, 2014 Authors
*
* Contributor Julius Baxter <juliusbaxter@gmail.com>
* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* -------------------------------------------------------------------------- */
/* Coding convention:
Assembly is hard to read per se, so please follow the following coding
conventions to keep it consistent and ease reading:
* internal jump labels start with L, no identation
* assemble lines have one tab identation
* attributes (.section, .global, ..) are indented with one tab
* code is structured using tabs, i.e., use 'l.sw\t0(r1),r1' with a single
tab. libgloss assumes 8 space tab width, so that might look unstructured
with tab widths below 6. Nevertheless don't use spaces or two tabs.
* no space after comma
* use the defined macros if possible as they reduce errors
* use OR1K_INST with OR1K_DELAYED(_NOP)
* OR1K_DELAYED is multiline for better readability, the inner parts are
indented with another tab.
* COMMENT! Try to accompy every line with a meaningful comment. If possible
use pseudo code to describe the code. Also mention intentions and not only
the obvious things.. */
/* -------------------------------------------------------------------------- */
#include "include/or1k-asm.h"
#include "include/or1k-sprs.h"
/* -------------------------------------------------------------------------- */
// Stack definitions
/* -------------------------------------------------------------------------- */
// Stacks
// Memory layout:
// +--------------------+ <- board_mem_base+board_mem_size/exception_stack_top
// | exception stack(s) |
// +--------------------+ <- stack_top
// | stack(s) |
// +--------------------+ <- stack_bottom
// | heap |
// +--------------------+
// | text, data, bss.. |
// +--------------------+
// Reserved stack size
#define STACK_SIZE 8192
// Reserved stack size for exceptions (can usually be smaller than normal stack)
#define EXCEPTION_STACK_SIZE 8192
// Size of space required to store state
// This value must match that in the support library or1k_exception_handler
// function
#define EXCEPTION_STACK_FRAME 136
#define REDZONE 128
.extern _or1k_stack_top /* points to the next address after the stack */
.extern _or1k_stack_bottom /* points to the last address in the stack */
.extern _or1k_exception_stack_top
.extern _or1k_exception_stack_bottom
.extern _or1k_exception_level /* Nesting level of exceptions */
.section .data
.global _or1k_stack_size /* reserved stack size */
.global _or1k_exception_stack_size
.global _or1k_exception_level
_or1k_stack_size: .word STACK_SIZE
_or1k_exception_stack_size: .word EXCEPTION_STACK_SIZE
#ifdef __OR1K_MULTICORE__
.extern _or1k_stack_core
.extern _or1k_exception_stack_core
#endif
#define SHADOW_REG(x) (OR1K_SPR_SYS_GPR_BASE + 32 + x)
/* -------------------------------------------------------------------------- */
/*!Macro to handle exceptions.
Load NPC into r3, EPCR into r4
*/
/* -------------------------------------------------------------------------- */
#define GPR_BUF_OFFSET(x) (x << 2)
#ifndef __OR1K_MULTICORE__
#define CALL_EXCEPTION_HANDLER(id) \
/* Store current stack pointer to address 4 */ \
l.sw 0x4(r0),r1; \
/* Load address of exception nesting level */ \
l.movhi r1,hi(_or1k_exception_level); \
l.ori r1,r1,lo(_or1k_exception_level); \
/* Load the current nesting level */ \
l.lwz r1,0(r1); \
/* Set flag if this is the outer (first) exception */ \
l.sfeq r1,r0; \
/* Branch to the code for nested exceptions */ \
OR1K_DELAYED_NOP( \
OR1K_INST(l.bnf .Lnested_##id) \
); \
/* Load top of the exception stack */ \
l.movhi r1,hi(_or1k_exception_stack_top); \
l.ori r1,r1,lo(_or1k_exception_stack_top); \
OR1K_DELAYED( \
/* Load value from array to stack pointer */ \
OR1K_INST(l.lwz r1,0(r1)), \
/* and jump over the nested code */ \
OR1K_INST(l.j .Lnesting_done_##id) \
); \
.Lnested_##id: \
/* Load back the stack pointer */ \
l.lwz r1,0x4(r0); \
/* Add redzone, nesting needs this */ \
l.addi r1,r1,-REDZONE; \
.Lnesting_done_##id: \
/* Reserve red zone and context space */ \
l.addi r1,r1,-EXCEPTION_STACK_FRAME; \
/* Store GPR3 in context */ \
l.sw GPR_BUF_OFFSET(3)(r1),r3; \
/* Load back software's stack pointer */ \
l.lwz r3,0x4(r0); \
/* Store this in the context */ \
l.sw GPR_BUF_OFFSET(1)(r1),r3; \
/* Store GPR4 in the context */ \
l.sw GPR_BUF_OFFSET(4)(r1),r4; \
/* Load address of the exception level */ \
l.movhi r3,hi(_or1k_exception_level); \
l.ori r3,r3,lo(_or1k_exception_level); \
/* Load current value */ \
l.lwz r4,0(r3); \
/* Increment level */ \
l.addi r4,r4,1; \
/* Store back */ \
l.sw 0(r3),r4; \
/* Copy the current program counter as first */ \
/* argument for the exception handler. This */ \
/* is then used to determine the exception. */ \
l.mfspr r3,r0,OR1K_SPR_SYS_NPC_ADDR; \
OR1K_DELAYED( \
/* Copy program counter of exception as */ \
/* second argument to the exception handler */ \
OR1K_INST(l.mfspr r4,r0,OR1K_SPR_SYS_EPCR_BASE),\
/* Jump to exception handler. This will rfe */ \
OR1K_INST(l.j _or1k_exception_handler) \
)
#else
#define CALL_EXCEPTION_HANDLER(id) \
/* Store current stack pointer to shadow reg */ \
l.mtspr r0,r1,SHADOW_REG(1); \
/* Store current GPR3 for temporary use */ \
l.mtspr r0,r3,SHADOW_REG(2); \
/* Store current GPR2 for the level pointer */ \
l.mtspr r0,r4,SHADOW_REG(3); \
/* Load nesting level of exceptions */ \
l.movhi r4,hi(_or1k_exception_level); \
l.ori r4,r4,lo(_or1k_exception_level); \
/* Load array pointer */ \
l.lwz r4,0(r4); \
/* Get core id */ \
l.mfspr r3,r0,OR1K_SPR_SYS_COREID_ADDR; \
/* Generate offset */ \
l.slli r3,r3,2; \
/* Generate core nesting level address */ \
l.add r4,r4,r3; \
/* Load nesting level */ \
l.lwz r3,0(r4); \
/* Increment nesting level */ \
l.addi r3,r3,1; \
/* Write back nesting level */ \
l.sw 0(r4),r3; \
/* Set flag if this is the outer (first) exception */ \
l.sfeqi r3,1; \
/* Branch to the code for nested exceptions */ \
OR1K_DELAYED_NOP( \
OR1K_INST(l.bnf .Lnested_##id) \
); \
/* Load pointer to exception stack array */ \
l.movhi r1,hi(_or1k_exception_stack_core); \
l.ori r1,r1,lo(_or1k_exception_stack_core); \
l.lwz r1,0(r1); \
/* Get core id */ \
l.mfspr r3,r0,OR1K_SPR_SYS_COREID_ADDR; \
/* Calculate offset in array */ \
l.slli r3,r3,2; \
l.add r1,r1,r3; \
OR1K_DELAYED( \
/* Load value from array to stack pointer */ \
OR1K_INST(l.lwz r1,0(r1)), \
/* and jump over nested exception pointer */ \
OR1K_INST(l.j .Lnesting_done_##id) \
); \
.Lnested_##id: \
/* The stack pointer is still active */ \
/* Add redzone, nesting needs this */ \
l.addi r1,r1,-REDZONE; \
.Lnesting_done_##id: \
/* Reserve context space */ \
l.addi r1,r1,-EXCEPTION_STACK_FRAME; \
/* Load back software's stack pointer */ \
l.mfspr r3,r0,SHADOW_REG(1); \
/* Store this in the context */ \
l.sw GPR_BUF_OFFSET(1)(r1),r3; \
/* Load back GPR3 */ \
l.mfspr r3,r0,SHADOW_REG(2); \
/* Store this in the context */ \
l.sw GPR_BUF_OFFSET(3)(r1),r3; \
/* Load back GPR4 */ \
l.mfspr r4,r0,SHADOW_REG(3); \
/* Store GPR4 in the context */ \
l.sw GPR_BUF_OFFSET(4)(r1),r4; \
/* Copy the current program counter as first */ \
/* argument for the exception handler. This */ \
/* is then used to determine the exception. */ \
l.mfspr r3,r0,OR1K_SPR_SYS_NPC_ADDR; \
OR1K_DELAYED( \
/* Copy program counter of exception as */ \
/* second argument to the exception handler */ \
OR1K_INST(l.mfspr r4,r0,OR1K_SPR_SYS_EPCR_BASE),\
/* Jump to exception handler. This will rfe */ \
OR1K_INST(l.j _or1k_exception_handler) \
)
#endif
/* -------------------------------------------------------------------------- */
/*!Exception vectors */
/* -------------------------------------------------------------------------- */
.section .vectors,"ax"
/* 0x100: RESET exception */
.org 0x100
_or1k_reset:
l.movhi r0,0
#ifdef __OR1K_MULTICORE__
// This is a hack that relies on the fact, that all cores start at the
// same time and they are similarily fast
l.sw 0x4(r0),r0
// Similarly, we use address 8 to signal how many cores have exit'ed
l.sw 0x8(r0),r0
#endif
l.movhi r1,0
l.movhi r2,0
l.movhi r3,0
l.movhi r4,0
l.movhi r5,0
l.movhi r6,0
l.movhi r7,0
l.movhi r8,0
l.movhi r9,0
l.movhi r10,0
l.movhi r11,0
l.movhi r12,0
l.movhi r13,0
l.movhi r14,0
l.movhi r15,0
l.movhi r16,0
l.movhi r17,0
l.movhi r18,0
l.movhi r19,0
l.movhi r20,0
l.movhi r21,0
l.movhi r22,0
l.movhi r23,0
l.movhi r24,0
l.movhi r25,0
l.movhi r26,0
l.movhi r27,0
l.movhi r28,0
l.movhi r29,0
l.movhi r30,0
l.movhi r31,0
/* Clear status register, set supervisor mode */
l.ori r1,r0,OR1K_SPR_SYS_SR_SM_MASK
l.mtspr r0,r1,OR1K_SPR_SYS_SR_ADDR
/* Clear timer mode register*/
l.mtspr r0,r0,OR1K_SPR_TICK_TTMR_ADDR
/* Jump to program initialisation code */
LOAD_SYMBOL_2_GPR(r4, _or1k_start)
OR1K_DELAYED_NOP(OR1K_INST(l.jr r4))
.org 0x200
CALL_EXCEPTION_HANDLER(2)
/* 0x300: Data Page Fault exception */
.org 0x300
CALL_EXCEPTION_HANDLER(3)
/* 0x400: Insn Page Fault exception */
.org 0x400
CALL_EXCEPTION_HANDLER(4)
/* 0x500: Timer exception */
.org 0x500
CALL_EXCEPTION_HANDLER(5)
/* 0x600: Aligment exception */
.org 0x600
CALL_EXCEPTION_HANDLER(6)
/* 0x700: Illegal insn exception */
.org 0x700
CALL_EXCEPTION_HANDLER(7)
/* 0x800: External interrupt exception */
.org 0x800
CALL_EXCEPTION_HANDLER(8)
/* 0x900: DTLB miss exception */
.org 0x900
CALL_EXCEPTION_HANDLER(9)
/* 0xa00: ITLB miss exception */
.org 0xa00
CALL_EXCEPTION_HANDLER(10)
/* 0xb00: Range exception */
.org 0xb00
CALL_EXCEPTION_HANDLER(11)
/* 0xc00: Syscall exception */
.org 0xc00
CALL_EXCEPTION_HANDLER(12)
/* 0xd00: Floating point exception */
.org 0xd00
CALL_EXCEPTION_HANDLER(13)
/* 0xe00: Trap exception */
.org 0xe00
CALL_EXCEPTION_HANDLER(14)
/* 0xf00: Reserved exceptions */
.org 0xf00
CALL_EXCEPTION_HANDLER(15)
.org 0x1000
CALL_EXCEPTION_HANDLER(16)
.org 0x1100
CALL_EXCEPTION_HANDLER(17)
.org 0x1200
CALL_EXCEPTION_HANDLER(18)
.org 0x1300
CALL_EXCEPTION_HANDLER(19)
.org 0x1400
CALL_EXCEPTION_HANDLER(20)
.org 0x1500
CALL_EXCEPTION_HANDLER(21)
.org 0x1600
CALL_EXCEPTION_HANDLER(22)
.org 0x1700
CALL_EXCEPTION_HANDLER(23)
.org 0x1800
CALL_EXCEPTION_HANDLER(24)
.org 0x1900
CALL_EXCEPTION_HANDLER(25)
.org 0x1a00
CALL_EXCEPTION_HANDLER(26)
.org 0x1b00
CALL_EXCEPTION_HANDLER(27)
.org 0x1c00
CALL_EXCEPTION_HANDLER(28)
.org 0x1d00
CALL_EXCEPTION_HANDLER(29)
.org 0x1e00
CALL_EXCEPTION_HANDLER(30)
.org 0x1f00
CALL_EXCEPTION_HANDLER(31)
/* Pad to the end */
.org 0x1ffc
l.nop
/* -------------------------------------------------------------------------- */
/*!Main entry point
This is the initialization code of the library. It performs these steps:
* Call early board initialization:
Before anything happened, the board support may do some very early
initialization. This is at maximum some very basic stuff that would
otherwise prevent the following code from functioning. Other initialization
of peripherals etc. is done later (before calling main).
See the description below and README.board for details.
* Initialize the stacks:
Two stacks are configured: The system stack is used by the software and
the exception stack is used when an exception occurs. We added this as
this should be flexible with respect to the usage of virtual memory.
* Activate the caches:
If available the caches are initiliazed and activated.
* Clear BSS:
The BSS are essentially the uninitialized C variables. They are set to 0
by default. This is performed by this function.
* Initialize the impure data structure:
Similarly, we need two library contexts, one for the normal software and
one that is used during exceptions. The impure data structure holds
the context information of the library. The called C function will setup
both data structures. There is furthermore a pointer to the currently
active impure data structure, which is initially set to the normal one.
* Initialize or1k support library reentrant data structures
* Initialize constructors:
Call the static and global constructors
* Set up destructors to call from exit
The library will call the function set via atexit() during exit(). We set
it to call the _fini function which performs destruction.
* Call board initialization:
The board initialization can perform board specific initializations such as
configuring peripherals etc.
* Jump to main
Call main with argc = 0 and *argv[] = 0
* Call exit after main returns
Now we call exit()
* Loop forever
We are dead.
*/
/* -------------------------------------------------------------------------- */
.section .text
/* Following externs from board-specific object passed at link time */
.extern _or1k_board_mem_base
.extern _or1k_board_mem_size
.extern _or1k_board_uart_base
/* The early board initialization may for example read the memory size and
set the mem_base and mem_size or do some preliminary board
initialization. As we do not have a stack at this time, the function may
not use the stack (and therefore be a or call a C function. But it can
safely use all registers.
We define a default implementation, which allows board files in C. As
described above, this can only be used in assembly (board_*.S) as at
the early stage not stack is available. A board that needs early
initialization can overwrite the function with .global _board_init_early.
Recommendation: Only use when you really need it! */
.weak _or1k_board_init_early
_or1k_board_init_early:
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
/* The board initialization is then called after the C library and UART
are initialized. It can then be used to configure UART or other
devices before the actual main function is called. */
.extern _or1k_board_init
.global _or1k_start
.type _or1k_start,@function
_or1k_start:
/* It is good to initialize and enable the caches before we do anything,
otherwise the cores will continuously access the bus during the wait
time for the boot barrier (0x4).
Fortunately or1k_cache_init does not need a stack */
OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_cache_init))
#ifdef __OR1K_MULTICORE__
// All but core 0 have to wait
l.mfspr r1, r0, OR1K_SPR_SYS_COREID_ADDR
l.sfeq r1, r0
OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lcore0))
.Lspin:
/* r1 will be used by the other cores to check for the boot variable
Check if r1 is still zero, core 0 will set it to 1 once it booted
As the cache is already turned on, this will not create traffic on
the bus, but the change is snooped by cache coherency then */
l.lwz r1,0x4(r0)
l.sfeq r1, r0
OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lspin))
/* Initialize core i stack */
// _or1k_stack_core is the array of stack pointers
LOAD_SYMBOL_2_GPR(r2,_or1k_stack_core)
// Load the base address
l.lwz r2,0(r2)
// Generate offset in array
l.mfspr r1,r0,OR1K_SPR_SYS_COREID_ADDR
l.slli r1,r1,2
// Add to array base
l.add r2,r2,r1
// Load pointer to the stack top and set frame pointer
l.lwz r1,0(r2)
l.or r2,r1,r1
// The slave cores are done, jump to main part
OR1K_DELAYED_NOP(OR1K_INST(l.j .Linit_done));
/* Only core 0 executes the initialization code */
.Lcore0:
#endif
/* Call early board initialization */
OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_board_init_early))
/* Clear BSS */
.Lclear_bss:
LOAD_SYMBOL_2_GPR(r3,__bss_start)
LOAD_SYMBOL_2_GPR(r4,end)
.Lclear_bss_loop:
l.sw (0)(r3),r0
l.sfltu r3,r4
OR1K_DELAYED(
OR1K_INST(l.addi r3,r3,4),
OR1K_INST(l.bf .Lclear_bss_loop)
)
/* Initialise stack and frame pointer (set to same value) */
LOAD_SYMBOL_2_GPR(r1,_or1k_board_mem_base)
l.lwz r1,0(r1)
LOAD_SYMBOL_2_GPR(r2,_or1k_board_mem_size)
l.lwz r2,0(r2)
l.add r1,r1,r2
/* Store exception stack top address */
LOAD_SYMBOL_2_GPR(r3,_or1k_exception_stack_top)
l.sw 0(r3),r1
/* Store exception stack bottom address */
// calculate bottom address
// r3 = *exception stack size
LOAD_SYMBOL_2_GPR(r3,_or1k_exception_stack_size)
// r3 = exception stack size
l.lwz r3,0(r3)
#ifdef __OR1K_MULTICORE__
l.mfspr r4,r0,OR1K_SPR_SYS_NUMCORES_ADDR
l.mul r3,r4,r3
#endif
// r4 = exception stack top - exception stack size = exception stack bottom
l.sub r4,r1,r3
// r5 = *exception stack bottom
LOAD_SYMBOL_2_GPR(r5,_or1k_exception_stack_bottom)
// store
l.sw 0(r5),r4
// Move stack pointer accordingly
l.or r1,r0,r4
l.or r2,r1,r1
/* Store stack top address */
LOAD_SYMBOL_2_GPR(r3,_or1k_stack_top)
l.sw 0(r3),r1
/* Store stack bottom address */
// calculate bottom address
// r3 = stack size
LOAD_SYMBOL_2_GPR(r3,_or1k_stack_size)
l.lwz r3,0(r3)
#ifdef __OR1K_MULTICORE__
l.mfspr r4, r0, OR1K_SPR_SYS_NUMCORES_ADDR
l.mul r3, r4, r3
#endif
// r4 = stack top - stack size = stack bottom
// -> stack bottom
l.sub r4,r1,r3
// r5 = *exception stack bottom
LOAD_SYMBOL_2_GPR(r5,_or1k_stack_bottom)
// store to variable
l.sw 0(r5),r4
/* Reinitialize the or1k support library */
OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_init))
/* Reinitialize the reentrancy structure */
OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_libc_impure_init))
/* Call global and static constructors */
OR1K_DELAYED_NOP(OR1K_INST(l.jal _init))
/* Set up destructors to be called from exit if main ever returns */
l.movhi r3,hi(_fini)
OR1K_DELAYED(
OR1K_INST(l.ori r3,r3,lo(_fini)),
OR1K_INST(l.jal atexit)
)
/* Check if UART is to be initialised */
LOAD_SYMBOL_2_GPR(r4,_or1k_board_uart_base)
l.lwz r4,0(r4)
/* Is base set? If not, no UART */
l.sfne r4,r0
l.bnf .Lskip_uart
l.or r3,r0,r0
OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_uart_init))
.Lskip_uart:
/* Board initialization */
OR1K_DELAYED_NOP(OR1K_INST(l.jal _or1k_board_init))
#ifdef __OR1K_MULTICORE__
// Start other cores
l.ori r3, r0, 1
l.sw 0x4(r0), r3
#endif
.Linit_done:
/* Jump to main program entry point (argc = argv = envp = 0) */
l.or r3,r0,r0
l.or r4,r0,r0
OR1K_DELAYED(
OR1K_INST(l.or r5,r0,r0),
OR1K_INST(l.jal main)
)
#ifdef __OR1K_MULTICORE__
.incrementexit:
/* Atomically increment number of finished cores */
l.lwa r3,0x8(r0)
l.addi r3,r3,1
l.swa 0x8(r0),r3
OR1K_DELAYED_NOP(OR1K_INST(l.bnf .incrementexit));
/* Compare to number of cores in this cluster */
l.mfspr r4,r0, OR1K_SPR_SYS_NUMCORES_ADDR
/* Compare to number of finished tasks */
l.sfeq r3,r4
/* Last core needs to desctruct library etc. */
OR1K_DELAYED_NOP(OR1K_INST(l.bf .exitcorelast));
OR1K_DELAYED(
OR1K_INST(l.addi r3,r11,0),
OR1K_INST(l.jal _exit)
)
.exitcorelast:
#endif
/* If program exits, call exit routine */
OR1K_DELAYED(
OR1K_INST(l.addi r3,r11,0),
OR1K_INST(l.jal exit)
)
/* Loop forever */
.Lloop_forever:
OR1K_DELAYED_NOP(OR1K_INST(l.j .Lloop_forever))
.size _or1k_start,.-_or1k_start
|
stsp/newlib-ia16
| 5,196
|
libgloss/or1k/interrupts-asm.S
|
/* interrupts-asm.S -- interrupt handling for OpenRISC 1000.
*
* Copyright (c) 2011, 2012, 2014 Authors
*
* Contributor Julius Baxter <juliusbaxter@gmail.com>
* Contributor Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* -------------------------------------------------------------------------- */
/*!Generic interrupt handler function for or1k
*/
/* -------------------------------------------------------------------------- */
#include "include/or1k-asm.h"
#include "include/or1k-sprs.h"
.extern _or1k_interrupt_handler_table
.extern _or1k_interrupt_handler_data_ptr_table
/* -------------------------------------------------------------------------- */
/*!Function to call appropriate interrupt handler
*/
/* -------------------------------------------------------------------------- */
.section .text
.global _or1k_interrupt_handler
.type _or1k_interrupt_handler,@function
_or1k_interrupt_handler:
/* Make room on stack, save link address register */
l.addi r1,r1,-4
l.sw 0(r1),r9
/* Read PICSR */
l.mfspr r20,r0,OR1K_SPR_PIC_PICSR_ADDR
/* Load handler table base address */
// Needs to be callee-saved register
l.movhi r16,hi(_or1k_interrupt_handler_table)
l.ori r16,r16,lo(_or1k_interrupt_handler_table)
/* Load data pointer table base address */
// Needs to be callee-saved register
l.movhi r18,hi(_or1k_interrupt_handler_data_ptr_table)
l.ori r18,r18,lo(_or1k_interrupt_handler_data_ptr_table)
#ifdef __OR1K_MULTICORE__
/* Read the addresses of the arrays of cores */
/* r7 = (*or1k_interrupt_handler_table) */
l.lwz r16,0(r16)
/* r12 = (*or1k_interrupt_handler_data_ptr_table) */
l.lwz r18,0(r18)
/* Generate offset in arrays */
/* r14 = coreid */
l.mfspr r14,r0,OR1K_SPR_SYS_COREID_ADDR
/* r14 = coreid*32*4 = off */
l.slli r14,r14,7
/* r7 = (*or1k_exception_handler_table)[coreid] */
l.add r16,r16,r14
/* r12 = (*or1k_exception_handler_table)[coreid] */
l.add r18,r18,r14
#endif
.L0:
/* Find first set bit in PICSR */
l.ff1 r4,r20
/* Any bits set? */
l.sfne r4,r0
/* If none, finish */
OR1K_DELAYED_NOP(OR1K_INST(l.bnf .L2))
/* What is IRQ function table offset? */
l.addi r22,r4,-1
l.slli r6,r22,2
/* Add this to table bases */
l.add r14,r6,r16
l.add r13,r6,r18
/* Fetch handler function address */
l.lwz r14,0(r14)
/* Double check it's valid, compare against INTERRUPT_HANDLER_NOT_SET */
l.sfne r14,r0
/* Skip if no handler: TODO: Indicate interrupt fired but no handler*/
OR1K_DELAYED_NOP(OR1K_INST(l.bnf .L1))
/* Call handler, load data pointer */
OR1K_DELAYED(
OR1K_INST(l.lwz r3,0(r13)),
OR1K_INST(l.jalr r14)
)
.L1:
/* Clear bit from PICSR, return to start of checking loop */
l.ori r6,r0,1
l.sll r6,r6,r22
OR1K_DELAYED(
OR1K_INST(l.xor r20,r20,r6),
OR1K_INST(l.j .L0)
)
.L2:
/* Finish up - write PICSR back, restore r9*/
l.lwz r9,0(r1)
l.mtspr r0,r20,OR1K_SPR_PIC_PICSR_ADDR
OR1K_DELAYED(
OR1K_INST(l.addi r1,r1,4),
OR1K_INST(l.jr r9)
)
/* -------------------------------------------------------------------------- */
/*!Function to enable an interrupt handler in the PICMR
*/
/* -------------------------------------------------------------------------- */
.global or1k_interrupt_enable
.type or1k_interrupt_enable,@function
/* r3 should have IRQ line for peripheral */
or1k_interrupt_enable:
l.addi r1,r1,-4
l.sw 0(r1),r4
l.ori r4,r0,0x1
l.sll r4,r4,r3
l.mfspr r3,r0,OR1K_SPR_PIC_PICMR_ADDR
l.or r3,r3,r4
l.mtspr r0,r3,OR1K_SPR_PIC_PICMR_ADDR
l.lwz r4,0(r1)
OR1K_DELAYED(
OR1K_INST(l.addi r1,r1,4),
OR1K_INST(l.jr r9)
)
/* -------------------------------------------------------------------------- */
/*!Function to disable an interrupt handler in the PICMR
*/
/* -------------------------------------------------------------------------- */
.global or1k_interrupt_disable
.type or1k_interrupt_disable,@function
/* r3 should have IRQ line for peripheral */
or1k_interrupt_disable:
l.addi r1,r1,-4
l.sw 0(r1),r4
l.ori r4,r0,0x1
l.sll r4,r4,r3
l.xori r4,r4,0xffff
l.mfspr r3,r0,OR1K_SPR_PIC_PICMR_ADDR
l.and r3,r3,r4
l.mtspr r0,r3,OR1K_SPR_PIC_PICMR_ADDR
l.lwz r4,0(r1)
OR1K_DELAYED(
OR1K_INST(l.addi r1,r1,4),
OR1K_INST(l.jr r9)
)
|
stsp/newlib-ia16
| 6,959
|
libgloss/or1k/caches-asm.S
|
/* caches-asm.S -- cache manipulation for OpenRISC 1000.
*
* Copyright (c) 2011, 2014 Authors
*
* Contributor Julius Baxter <juliusbaxter@gmail.com>
* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "include/or1k-asm.h"
#include "include/or1k-sprs.h"
/* -------------------------------------------------------------------------- */
/*!Function used at reset to clear and enable all caches
*/
/* -------------------------------------------------------------------------- */
.global _or1k_cache_init
.type _or1k_cache_init,@function
_or1k_cache_init:
/* Instruction cache enable */
/* Check if IC present and skip enabling otherwise */
l.mfspr r3,r0,OR1K_SPR_SYS_UPR_ADDR
l.andi r4,r3,OR1K_SPR_SYS_UPR_ICP_MASK
l.sfeq r4,r0
OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lnoic))
/* Disable IC */
l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR
l.addi r5,r0,-1
l.xori r5,r5,OR1K_SPR_SYS_SR_ICE_MASK
l.and r5,r6,r5
l.mtspr r0,r5,OR1K_SPR_SYS_SR_ADDR
/* Establish cache block size
If BS=0, 16;
If BS=1, 32;
r14 contain block size
*/
l.mfspr r3,r0,OR1K_SPR_SYS_ICCFGR_ADDR
l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_CBS_MASK
l.srli r7,r4,7
l.ori r8,r0,16
l.sll r14,r8,r7
/* Establish number of cache sets
r13 contains number of cache sets
r7 contains log(# of cache sets)
*/
l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_NCS_MASK
l.srli r7,r4,3
l.ori r8,r0,1
l.sll r13,r8,r7
/* Invalidate IC */
l.addi r6,r0,0
l.sll r5,r14,r7
.Linvi: l.mtspr r0,r6,OR1K_SPR_ICACHE_ICBIR_ADDR
l.sfne r6,r5
OR1K_DELAYED(
OR1K_INST(l.add r6,r6,r14),
OR1K_INST(l.bf .Linvi)
)
/* Enable IC */
l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR
l.ori r6,r6,OR1K_SPR_SYS_SR_ICE_MASK
l.mtspr r0,r6,OR1K_SPR_SYS_SR_ADDR
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
/* Data cache enable */
/* Check if DC present and skip enabling otherwise */
.Lnoic: l.mfspr r3,r0,OR1K_SPR_SYS_UPR_ADDR
l.andi r4,r3,OR1K_SPR_SYS_UPR_DCP_MASK
l.sfeq r4,r0
OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lnodc))
/* Disable DC */
l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR
l.addi r5,r0,-1
l.xori r5,r5,OR1K_SPR_SYS_SR_DCE_MASK
l.and r5,r6,r5
l.mtspr r0,r5,OR1K_SPR_SYS_SR_ADDR
/* Establish cache block size
If BS=0, 16;
If BS=1, 32;
r14 contain block size */
l.mfspr r3,r0,OR1K_SPR_SYS_DCCFGR_ADDR
l.andi r4,r3,OR1K_SPR_SYS_DCCFGR_CBS_MASK
l.srli r7,r4,7
l.ori r8,r0,16
l.sll r14,r8,r7
/* Establish number of cache sets
r13 contains number of cache sets
r7 contains log(# of cache sets) */
l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_NCS_MASK
l.srli r7,r4,3
l.ori r8,r0,1
l.sll r13,r8,r7
/* Invalidate DC */
l.addi r6,r0,0
l.sll r5,r14,r7
.Linvd: l.mtspr r0,r6,OR1K_SPR_DCACHE_DCBIR_ADDR
l.sfne r6,r5
OR1K_DELAYED(
OR1K_INST(l.add r6,r6,r14),
OR1K_INST(l.bf .Linvd)
)
/* Enable DC */
l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR
l.ori r6,r6,OR1K_SPR_SYS_SR_DCE_MASK
l.mtspr r0,r6,OR1K_SPR_SYS_SR_ADDR
.Lnodc:
/* Return */
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
/* -------------------------------------------------------------------------- */
/*!Function to enable instruction cache
*/
/* -------------------------------------------------------------------------- */
.global or1k_icache_enable
.type or1k_icache_enable,@function
or1k_icache_enable:
/* Enable IC */
l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR
l.ori r13,r13,OR1K_SPR_SYS_SR_ICE_MASK
l.mtspr r0,r13,OR1K_SPR_SYS_SR_ADDR
l.nop
l.nop
l.nop
l.nop
l.nop
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
/* -------------------------------------------------------------------------- */
/*!Function to disable instruction cache
*/
/* -------------------------------------------------------------------------- */
.global or1k_icache_disable
.type or1k_icache_disable,@function
or1k_icache_disable:
/* Disable IC */
l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR
l.addi r12,r0,-1
l.xori r12,r12,OR1K_SPR_SYS_SR_ICE_MASK
l.and r12,r13,r12
l.mtspr r0,r12,OR1K_SPR_SYS_SR_ADDR
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
/* -------------------------------------------------------------------------- */
/*!Function to flush address of instruction cache
*/
/* -------------------------------------------------------------------------- */
.global or1k_icache_flush
.type or1k_icache_flush,@function
or1k_icache_flush:
OR1K_DELAYED(
OR1K_INST(l.mtspr r0,r3,OR1K_SPR_ICACHE_ICBIR_ADDR),
/* Push r3 into IC invalidate reg */
OR1K_INST(l.jr r9)
)
/* -------------------------------------------------------------------------- */
/*!Function to enable data cache
*/
/* -------------------------------------------------------------------------- */
.global or1k_dcache_enable
.type or1k_dcache_enable,@function
or1k_dcache_enable:
/* Enable DC */
l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR
l.ori r13,r13,OR1K_SPR_SYS_SR_DCE_MASK
l.mtspr r0,r13,OR1K_SPR_SYS_SR_ADDR
l.nop
l.nop
l.nop
l.nop
l.nop
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
/* -------------------------------------------------------------------------- */
/*!Function to disable data cache
*/
/* -------------------------------------------------------------------------- */
.global or1k_dcache_disable
.type or1k_dcache_disable,@function
or1k_dcache_disable:
/* Disable DC */
l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR
l.addi r12,r0,-1
l.xori r12,r12,OR1K_SPR_SYS_SR_DCE_MASK
l.and r12,r13,r12
l.mtspr r0,r12,OR1K_SPR_SYS_SR_ADDR
OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
/* -------------------------------------------------------------------------- */
/*!Function to flush address of data cache
*/
/* -------------------------------------------------------------------------- */
.global or1k_dcache_flush
.type or1k_dcache_flush,@function
or1k_dcache_flush:
OR1K_DELAYED(
OR1K_INST(l.mtspr r0,r3,OR1K_SPR_DCACHE_DCBIR_ADDR),
/* Push r3 into DC invalidate reg */
OR1K_INST(l.jr r9)
)
|
stsp/newlib-ia16
| 1,553
|
libgloss/cr16/crtn.S
|
/* Specialized code needed to support construction and destruction of
file-scope objects in C++ and Java code, and to support exception handling.
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* As a special exception, if you link this library with files
compiled with GCC to produce an executable, this does not cause
the resulting executable to be covered by the GNU General Public License.
This exception does not however invalidate any other reasons why
the executable file might be covered by the GNU General Public License. */
/*
* This file supplies function epilogues for the .init and .fini sections.
* It is linked in after all other files.
*/
.file "crtn.o"
.ident "GNU C crtn.o"
.section .init
popret ra
.section .fini
popret ra
|
stsp/newlib-ia16
| 4,105
|
libgloss/cr16/crt1.S
|
##############################################################################
# crt0.s -- CR16 default start-up routine #
# #
# Copyright (c) 2004 National Semiconductor Corporation #
# #
# The authors hereby grant permission to use, copy, modify, distribute, #
# and license this software and its documentation for any purpose, provided #
# that existing copyright notices are retained in all copies and that this #
# notice is included verbatim in any distributions. No written agreement, #
# license, or royalty fee is required for any of the authorized uses. #
# Modifications to this software may be copyrighted by their authors #
# and need not follow the licensing terms described here, provided that #
# the new terms are clearly indicated on the first page of each file where #
# they apply. #
# #
# This is the start routine of your CR16 program. #
# It is linked with your application automatically. You can use #
# this routine as a template and modify it to your needs, yet this #
# file must be supplied for the compiler. #
# It is assumed that the following symbols are defined in your linker #
# script: __STACK_START, __ISTACK_START #
##############################################################################
.text
#ifdef __CR16CP__
.align 4
#else
.align 2
#endif
.global _main
.global _atexit
.global _exit
.global _start
.global __fini
.global __init
.global __STACK_START
.global __ISTACK_START
_start:
#----------------------------------------------------------------------------#
# Initialize the stack pointers. The constants __STACK_START and #
# __ISTACK_START should be defined in the linker script. #
movd $__STACK_START, (sp)
movd $__ISTACK_START, (r1,r0)
lprd (r1,r0), isp
#----------------------------------------------------------------------------#
# Initialize the default sections according to the linker script. #
# bal (ra), __init_bss_data
#----------------------------------------------------------------------#
# Set the Extended Dispatch bit in the CFG register. This is the #
# default configuration for CR16C. #
spr cfg, r0 # Set dispatch table width
orw $0x100, r0
lpr r0, cfg
#----------------------------------------------------------------------------#
#----------------------------------------------------------------------------#
# Handle global and static constructurs execution and setup #
# destructors to be called from exit. #
bal (ra),__init
movd $__fini@c, (r3,r2)
bal (ra), _atexit
#----------------------------------------------------------------------------#
# Jump to the main function in your application. #
#ifdef __INT32__
movd $0, (r3,r2) # Number of arguments
movd $0, (r5,r4) # conatins pointer to argument string.
#else
movw $0, r2 # Number of arguments
movd $0, (r4,r3) # conatins pointer to argument string.
#endif
bal (ra), _main
#----------------------------------------------------------------------------#
# Upon returning from the main function (if it isn't an infinite loop), #
# jump to the exit function. The exit function is located in the #
# library 'libc.a'. #
#ifdef __INT32__
movd (r1,r0), (r3,r2) # _main return value gets forwarded.
#else
movw r0, r2 # _main return value gets forwarded.
#endif
br _exit # returns control to the functional simulator.
|
stsp/newlib-ia16
| 1,646
|
libgloss/cr16/crti.S
|
/* Specialized code needed to support construction and destruction of
file-scope objects in C++ and Java code, and to support exception handling.
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* As a special exception, if you link this library with files
compiled with GCC to produce an executable, this does not cause
the resulting executable to be covered by the GNU General Public License.
This exception does not however invalidate any other reasons why
the executable file might be covered by the GNU General Public License. */
/*
* This file just supplies function prologues for the .init and .fini
* sections. It is linked in before crtbegin.o.
*/
.file "crti.o"
.ident "GNU C crti.o"
.section .init
.globl _init
.type _init,@function
_init:
push ra
.section .fini
.globl _fini
.type _fini,@function
_fini:
push ra
|
stsp/newlib-ia16
| 2,752
|
libgloss/visium/crt0.S
|
/* crt0.S for the Visium processor.
Copyright (c) 2015 Rolls-Royce Controls and Data Services Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Rolls-Royce Controls and Data Services Limited nor
the names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE. */
.weak _get_cmdline
.text
.align 4
.global __start
__start:
/* Initialize the stack pointer. */
moviu r1,%u _estack
movil r1,%l _estack
move.l r23,r1
/* Terminate the frame chain. */
moviq r22,0
/* Zero the .bss segment. */
moviu r1,%u __bss_start
movil r1,%l __bss_start
moviu r2,%u __bss_end
movil r2,%l __bss_end
.L0:
cmp.l r1,r1
brr eq,.L1
nop
write.b (r1),r0
brr tr,.L0
addi r1,1
.L1:
/* Register __fini (destructors) with atexit. */
moviu r1,%u __fini
moviu r2,%u atexit
movil r2,%l atexit
bra tr,r2,r21
movil r1,%l __fini
/* Call __init (constructors). */
moviu r1,%u __init
movil r1,%l __init
bra tr,r1,r21
nop
/* Set up argc and argv. */
moviu r3,%u _get_cmdline
movil r3,%l _get_cmdline
cmp.l r3,r0
moviq r1,0
bra ne,r3,r21
moviq r2,0
/* Call the main program. */
moviu r3,%u main
movil r3,%l main
bra tr,r3,r21
nop
/* Call exit in case the main program didn't. */
moviu r2,%u exit
movil r2,%l exit
bra tr,r2,r21
nop
.end
|
stsp/newlib-ia16
| 1,509
|
libgloss/m32c/read.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(read)
|
stsp/newlib-ia16
| 1,509
|
libgloss/m32c/kill.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(kill)
|
stsp/newlib-ia16
| 1,510
|
libgloss/m32c/chmod.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(chmod)
|
stsp/newlib-ia16
| 1,512
|
libgloss/m32c/argvlen.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(argvlen)
|
stsp/newlib-ia16
| 1,511
|
libgloss/m32c/unlink.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(unlink)
|
stsp/newlib-ia16
| 1,545
|
libgloss/m32c/heaptop.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
#define SYS__set_heaptop 11
S(_set_heaptop)
|
stsp/newlib-ia16
| 1,510
|
libgloss/m32c/times.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(times)
|
stsp/newlib-ia16
| 1,510
|
libgloss/m32c/fstat.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(fstat)
|
stsp/newlib-ia16
| 1,509
|
libgloss/m32c/stat.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(stat)
|
stsp/newlib-ia16
| 1,517
|
libgloss/m32c/gettimeofday.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(gettimeofday)
|
stsp/newlib-ia16
| 1,856
|
libgloss/m32c/crtn.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
#define A16
#define A(n,w) n
#define W w
#else
#define A24
#define A(n,w) w
#define W l
#endif
.section .init,"ax",@progbits
jsr.a _m32c_run_preinit_array
jsr.a _m32c_run_init_array
exitd
.global __m32c_init_end
__m32c_init_end:
.section .fini,"ax",@progbits
exitd
.global __m32c_fini_end
__m32c_fini_end:
.text
|
stsp/newlib-ia16
| 1,799
|
libgloss/m32c/abort.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
.global _abort
_abort:
/* This is for debuggers. The simulator stops here too. */
brk
/* Else, fall back on the simulator's "kill me" option. */
#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
mov.w #42,r1
#else
mov.w #42,r0
#endif
SYSCALL(SYS_kill)
/* Else, exit. */
jmp.a __exit
|
stsp/newlib-ia16
| 1,509
|
libgloss/m32c/time.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(time)
|
stsp/newlib-ia16
| 4,301
|
libgloss/m32c/crt0.S
|
/*
Copyright (c) 2005,2008 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
#define A16
#define A(n,w) n
#define W w
#define ALIGN 1
#else
#define A24
#define A(n,w) w
#define W l
#define ALIGN 2
#endif
.section ".resetvec","ax",@progbits
.long _start
.text
.global _start
_start:
.LFB2:
fclr U /* One stack for user and interrupts */
ldc #__stack,sp
#ifdef A16
mov.b #%hi8(__romdatastart),r1h
mov.w #%lo16(__romdatastart),a0
mov.w #__datastart,a1
#else
mov.l #__romdatastart,a0
mov.l #__datastart,a1
#endif
mov.w #__romdatacopysize,r3
shl.w #-1,r3
smovf.w
#ifdef A16
mov.w #__bssstart,a1
#else
mov.l #__bssstart,a1
#endif
mov.w #__bsssize,r3
shl.w #-1,r3
mov.w #0,r0
sstr.w
#ifdef A16
ldc #%lo16(__var_vects),intbl
ldc #%hi16(__var_vects),intbh
#else
ldc #__var_vects,intb
#endif
fset I
jsr.a __m32c_init
jsr.a _main
.LFE2:
#ifdef A24
/* rv in r0, ok for arg0 */
#else
mov.w r0,r1
#endif
jsr.a _exit
.text
.global _m32c_run_preinit_array
.type _m32c_run_preinit_array,@function
_m32c_run_preinit_array:
mov.W #__preinit_array_start,a0
mov.W #__preinit_array_end,a1
jmp.w _m32c_run_inilist
.global _m32c_run_init_array
.type _m32c_run_init_array,@function
_m32c_run_init_array:
mov.W #__init_array_start,a0
mov.W #__init_array_end,a1
jmp.w _m32c_run_inilist
.global _m32c_run_fini_array
.type _m32c_run_fini_array,@function
_m32c_run_fini_array:
mov.W #__fini_array_start,a0
mov.W #__fini_array_end,a1
/* fall through */
_m32c_run_inilist:
next_inilist:
cmp.W a0,a1
jeq done_inilist
pushm a0,a1
mov.W [a0],a0
#ifdef A16
mov.b:s #0,a1 /* zero extends */
jsri.a a1a0
#else
jsri.a a0
#endif
popm a0,a1
add.W A(#2,#4),a0
jmp.b next_inilist
done_inilist:
rts
.section .init,"ax",@progbits
.global __m32c_init
__m32c_init:
enter #0
.section .fini,"ax",@progbits
.global __m32c_fini
__m32c_fini:
enter #0
jsr.a _m32c_run_fini_array
;;; Provide Dwarf unwinding information that will help GDB stop
;;; backtraces at the right place. This is stolen from assembly
;;; code generated by GCC with -dA.
.section .debug_frame,"",@progbits
.Lframe0:
.4byte .LECIE0-.LSCIE0 ; Length of Common Information Entry
.LSCIE0:
.4byte 0xffffffff ; CIE Identifier Tag
.byte 0x1 ; CIE Version
.ascii "\0" ; CIE Augmentation
.uleb128 0x1 ; CIE Code Alignment Factor
.sleb128 -1 ; CIE Data Alignment Factor
.byte 0xd ; CIE RA Column
.byte 0xc ; DW_CFA_def_cfa
.uleb128 0xc
.uleb128 0x3
.byte 0x8d ; DW_CFA_offset, column 0xd
.uleb128 0x3
.p2align ALIGN
.LECIE0:
.LSFDE0:
.4byte .LEFDE0-.LASFDE0 ; FDE Length
.LASFDE0:
.4byte .Lframe0 ; FDE CIE offset
.4byte .LFB2 ; FDE initial location
.4byte .LFE2-.LFB2 ; FDE address range
.byte 0xf ; DW_CFA_def_cfa_expression
.uleb128 1 ; length of expression
.byte 0x30 ; DW_OP_lit0
.p2align ALIGN
.LEFDE0:
.text
|
stsp/newlib-ia16
| 1,510
|
libgloss/m32c/utime.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(utime)
|
stsp/newlib-ia16
| 1,510
|
libgloss/m32c/close.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(close)
|
stsp/newlib-ia16
| 1,655
|
libgloss/m32c/varvects.S
|
/*
Copyright (c) 2008 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* This works with varvects.h
*/
.section ".var_vects","aw",@progbits
.global __var_vects
.type __var_vects,@object
.size __var_vects, 256
__var_vects:
.zero 256
.text
|
stsp/newlib-ia16
| 1,525
|
libgloss/m32c/isatty.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.global _isatty
_isatty:
mov.w #1,r0
rts
|
stsp/newlib-ia16
| 1,510
|
libgloss/m32c/lseek.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(lseek)
|
stsp/newlib-ia16
| 1,510
|
libgloss/m32c/write.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(write)
|
stsp/newlib-ia16
| 1,509
|
libgloss/m32c/open.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(open)
|
stsp/newlib-ia16
| 1,509
|
libgloss/m32c/argv.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(argv)
|
stsp/newlib-ia16
| 1,511
|
libgloss/m32c/getpid.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(getpid)
|
stsp/newlib-ia16
| 1,588
|
libgloss/m32c/exit.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
.global __exit
__exit:
pushm r0,r1
jsr.a __m32c_fini
popm r0,r1
SYSCALL(SYS_exit)
|
stsp/newlib-ia16
| 1,509
|
libgloss/m32c/link.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(link)
|
stsp/newlib-ia16
| 1,510
|
libgloss/m32c/chdir.S
|
/*
Copyright (c) 2005 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "m32csys.h"
S(chdir)
|
stsp/newlib-ia16
| 11,133
|
libgloss/hp74x/debugger.s
|
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
.space $TEXT$
.subspa $CODE$,access=0x2c
#if 1
#include "diagnose.h"
#endif
i13BREAK .equ 0xa5a ; im13 field for specified functions
i5REG .equ 0x06 ; Init registers
i5BP .equ 0x09 ; GDB breakpoin
i5PSW .equ 0x0b ; Get PSW
i5INLINE .equ 0x0e ; Get INLINE
R_gr0 .equ 0
R_gr1 .equ 4
R_gr2 .equ 8
R_gr3 .equ 12
R_gr4 .equ 16
R_gr5 .equ 20
R_gr6 .equ 24
R_gr7 .equ 28
R_gr8 .equ 32
R_gr9 .equ 36
R_gr10 .equ 40
R_gr11 .equ 44
R_gr12 .equ 48
R_gr13 .equ 52
R_gr14 .equ 56
R_gr15 .equ 60
R_gr16 .equ 64
R_gr17 .equ 68
R_gr18 .equ 72
R_gr19 .equ 76
R_gr20 .equ 80
R_gr21 .equ 84
R_gr22 .equ 88
R_gr23 .equ 92
R_gr24 .equ 96
R_gr25 .equ 100
R_gr26 .equ 104
R_gr27 .equ 108
R_gr28 .equ 112
R_gr29 .equ 116
R_gr30 .equ 120
R_gr31 .equ 124
R_sr0 .equ 128
R_sr1 .equ 132
R_sr2 .equ 136
R_sr3 .equ 140
R_sr4 .equ 144
R_sr5 .equ 148
R_sr6 .equ 152
R_sr7 .equ 156
R_cr0 .equ 160
R_cr1 .equ 164
R_cr2 .equ 168
R_cr3 .equ 172
R_cr4 .equ 176
R_cr5 .equ 180
R_cr6 .equ 184
R_cr7 .equ 188
R_cr8 .equ 192
R_cr9 .equ 196
R_cr10 .equ 200
R_cr11 .equ 204
R_cr12 .equ 208
R_cr13 .equ 212
R_cr14 .equ 216
R_cr15 .equ 220
R_cr16 .equ 224
R_cr17H .equ 228
R_cr18H .equ 232
R_cr19 .equ 236
R_cr20 .equ 240
R_cr21 .equ 244
R_cr22 .equ 248
R_cr23 .equ 252
R_cr24 .equ 256
R_cr25 .equ 260
R_cr26 .equ 264
R_cr27 .equ 268
R_cr28 .equ 272
R_cr29 .equ 276
R_cr30 .equ 280
R_cr31 .equ 284
R_cr17T .equ 288
R_cr18T .equ 292
R_cpu0 .equ 296
R_SIZE .equ 300
min_stack .equ 64
.import handle_exception
.import $global$, data
.IMPORT putnum, code
.IMPORT led_putnum, code
.IMPORT delay, code
.export FICE
.export DEBUG_GO
.export DEBUG_SS
.export STUB_RESTORE
.export save_regs
.export RegBlk
.export Exception_index
;-------------------------------------------------------------------------------
.EXPORT breakpoint,ENTRY,ARGW0=GR,RTNVAL=GR
breakpoint
.PROC
.CALLINFO CALLER,FRAME=128,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30) ; stash the return pointer
ldo 128(%r30),%r30 ; push up the stack pointer
;;; debug
ldi 6, %r26
bl,n led_putnum,%r2
nop
ldil L'900000,%r26
ldo R'900000(%r26),%r26
bl,n delay,%r2
nop
;;;
break i5INLINE,i13BREAK
;;; more debug
ldi 7, %r26
bl,n led_putnum,%r2
nop
ldil L'900000,%r26
ldo R'900000(%r26),%r26
bl,n delay,%r2
nop
;;;
FICE fice 0(0,%r26) ; Flush the i cache entry
sync
ldw -148(0,%r30),%r2 ; retrieve the return pointer
ldo -128(%r30),%r30 ; reset the stack pointer
bv,n 0(%r2) ; return to caller
nop
.EXIT
.PROCEND
;-------------------------------------------------------------------------------
DEBUG_GO
or,tr %r0,%r0,%r10 ; if go, do not set R-bit to 1
DEBUG_SS
ldi 1,%r10 ; else set R-bit to 1
DEBUG_EXEC
bl DGO_0,%r8 ; r8 points to register block
addil L%RegBlk-DGO_0,%r8
DGO_0
ldo R%RegBlk-DGO_0(%r1),%r8
; load space registers
ldw R_sr0(%r8),%r1
mtsp %r1,%sr0
ldw R_sr1(%r8),%r1
mtsp %r1,%sr1
ldw R_sr2(%r8),%r1
mtsp %r1,%sr2
ldw R_sr3(%r8),%r1
mtsp %r1,%sr3
ldw R_sr4(%r8),%r1
mtsp %r1,%sr4
ldw R_sr5(%r8),%r1
mtsp %r1,%sr5
ldw R_sr6(%r8),%r1
mtsp %r1,%sr6
ldw R_sr7(%r8),%r1
mtsp %r1,%sr7
; clear Q-bit for rfi
rsm 0x08,%r0
; load control registers
ldw R_cr0(%r8),%r1
or,= %r10,%r0,%r0 ; if single step
copy %r0,%r1 ; set %cr0 to 0
mtctl %r1,%cr0
ldw R_cr8(%r8),%r1
mtctl %r1,%cr8
ldw R_cr9(%r8),%r1
mtctl %r1,%cr9
ldw R_cr10(%r8),%r1
mtctl %r1,%cr10
ldw R_cr11(%r8),%r1
mtctl %r1,%cr11
ldw R_cr12(%r8),%r1
mtctl %r1,%cr12
ldw R_cr13(%r8),%r1
mtctl %r1,%cr13
ldw R_cr14(%r8),%r1
mtctl %r1,%cr14
ldw R_cr15(%r8),%r1
mtctl %r1,%cr15
ldw R_cr16(%r8),%r1
mtctl %r1,%cr16
ldw R_cr17H(%r8),%r1 ; load iiasq.head
mtctl %r1,%cr17
ldw R_cr18H(%r8),%r1 ; load iiaoq.head
mtctl %r1,%cr18
ldw R_cr17T(%r8),%r1 ; load iiasq.tail
mtctl %r1,%cr17
ldw R_cr18T(%r8),%r1 ; load iiaoq.tail
mtctl %r1,%cr18
ldw R_cr19(%r8),%r1
mtctl %r1,%cr19
ldw R_cr20(%r8),%r1
mtctl %r1,%cr20
ldw R_cr21(%r8),%r1
mtctl %r1,%cr21
ldw R_cr22(%r8),%r1
dep %r10,27,1,%r1 ; set R-bit if applicable
mtctl %r1,%cr22
ldw R_cr23(%r8),%r1
mtctl %r1,%cr23
ldw R_cr24(%r8),%r1
mtctl %r1,%cr24
ldw R_cr25(%r8),%r1
mtctl %r1,%cr25
ldw R_cr26(%r8),%r1
mtctl %r1,%cr26
ldw R_cr27(%r8),%r1
mtctl %r1,%cr27
ldw R_cr28(%r8),%r1
mtctl %r1,%cr28
ldw R_cr29(%r8),%r1
mtctl %r1,%cr29
ldw R_cr30(%r8),%r1
mtctl %r1,%cr30
ldw R_cr31(%r8),%r1
mtctl %r1,%cr31
; load diagnose registers
ldw R_cpu0(%r8),%r1
ldil L%CPU0_MASK,%r2
ldo R%CPU0_MASK(%r2),%r2
xor %r1,%r2,%r1 ; xor the read/clear bits
nop
mtcpu %r1,0
mtcpu %r1,0
; load general registers
ldw R_gr1(%r8),%r1
ldw R_gr2(%r8),%r2
ldw R_gr3(%r8),%r3
ldw R_gr4(%r8),%r4
ldw R_gr5(%r8),%r5
ldw R_gr6(%r8),%r6
ldw R_gr7(%r8),%r7
ldw R_gr9(%r8),%r9
ldw R_gr10(%r8),%r10
ldw R_gr11(%r8),%r11
ldw R_gr12(%r8),%r12
ldw R_gr13(%r8),%r13
ldw R_gr14(%r8),%r14
ldw R_gr15(%r8),%r15
ldw R_gr16(%r8),%r16
ldw R_gr17(%r8),%r17
ldw R_gr18(%r8),%r18
ldw R_gr19(%r8),%r19
ldw R_gr20(%r8),%r20
ldw R_gr21(%r8),%r21
ldw R_gr22(%r8),%r22
ldw R_gr23(%r8),%r23
ldw R_gr24(%r8),%r24
ldw R_gr25(%r8),%r25
ldw R_gr26(%r8),%r26
ldw R_gr27(%r8),%r27
ldw R_gr28(%r8),%r28
ldw R_gr29(%r8),%r29
ldw R_gr30(%r8),%r30
ldw R_gr31(%r8),%r31
ldw R_gr8(%r8),%r8
; execute user program
nop
rfi ; switch to user code
nop
;-------------------------------------------------------------------------------
STUB_RESTORE
copy %r1,%r9 ; save exception index
bl SR_00,%r8
addil L%Exception_index-SR_00,%r8
SR_00
ldo R%Exception_index-SR_00(%r1),%r8
stw %r9,(%r8)
bl save_regs,%r25
nop
#ifdef DEBUG_DEBUGGER1
stwm %r1,8(%sp)
bl putc,%rp
ldi CR,%arg0
bl putc,%rp
ldi LF,%arg0
bl printit,%mrp
mfctl %pcoq,%arg0
mfctl %pcoq,%r1
mtctl %r1,%pcoq
mfctl %pcoq,%arg0
bl printit,%mrp
mtctl %arg0,%pcoq
bl printit,%mrp
ldw -8(%sp),%arg0
ldwm -8(%sp),%r1
#endif
#ifdef DEBUG_DEBUGGER2
stwm %r1,8(%sp)
bl putc,%rp
ldi LF,%arg0
ldwm -8(%sp),%r1
#endif
#ifdef DEBUG_DEBUGGER3
bl printit,%mrp
copy iptr,%arg0
bl printit,%mrp
copy rstack,%arg0
bl printit,%mrp
copy gspace,%arg0
bl printit,%mrp
copy dstack,%arg0
bl printit,%mrp
copy nextptr,%arg0
bl printit,%mrp
copy %dp,%arg0
bl printit,%mrp
copy %sp,%arg0
bl printit,%mrp
mfctl %rctr,%arg0
bl printit,%mrp
mfctl %iva,%arg0
bl printit,%mrp
mfctl %eiem,%arg0
bl printit,%mrp
mfctl %ipsw,%arg0
bl printit,%mrp
copy %r0,%arg0
#endif
bl SR_1,%sp
addil L%Stub_stack-SR_1,%sp
SR_1
ldo R%Stub_stack-SR_1(%r1),%sp ; set the stack pointer
bl SR_2,%arg0
addil L%RegBlk-SR_2,%arg0
SR_2
ldo R%RegBlk-SR_2(%r1),%arg0 ; set arg0 (save register area)
bl SR_3,%arg1
addil L%Exception_index-SR_3,%arg1 ; set arg1 address
SR_3
ldo R%Exception_index-SR_3(%r1),%arg1 ; set arg1 address
addi min_stack,%sp,%sp ; allocate min stack frame
bl handle_exception,%r2
ldw 0(%arg1),%arg1 ; load arg1
addi -min_stack,%sp,%sp ; de allocate min stack frame
b DEBUG_EXEC ;
copy %r28,%r10
;-------------------------------------------------------------------------------
save_regs ; return address is in %r25
bl SR_0,%r1 ; r1 points to Register block
addil L%RegBlk-SR_0,%r1
SR_0
ldo R%RegBlk-SR_0(%r1),%r1
; save general registers
stw %r0,R_gr0(%r1)
; don't store %r1 yet
stw %r2,R_gr2(%r1)
stw %r3,R_gr3(%r1)
stw %r4,R_gr4(%r1)
stw %r5,R_gr5(%r1)
stw %r6,R_gr6(%r1)
stw %r7,R_gr7(%r1)
; don't store %r8 yet
; don't store %r9 yet
stw %r10,R_gr10(%r1)
stw %r11,R_gr11(%r1)
stw %r12,R_gr12(%r1)
stw %r13,R_gr13(%r1)
stw %r14,R_gr14(%r1)
stw %r15,R_gr15(%r1)
; don't store %r16 yet
; don't store %r17 yet
stw %r18,R_gr18(%r1)
stw %r19,R_gr19(%r1)
stw %r20,R_gr20(%r1)
stw %r21,R_gr21(%r1)
stw %r22,R_gr22(%r1)
stw %r23,R_gr23(%r1)
; don't store %r24 yet
; don't store %r25 yet
stw %r26,R_gr26(%r1)
stw %r27,R_gr27(%r1)
stw %r28,R_gr28(%r1)
stw %r29,R_gr29(%r1)
stw %r30,R_gr30(%r1)
stw %r31,R_gr31(%r1)
; restore general registers from shadow registers and save them
copy %r1,%r10 ; hold Register block pointer
copy %r25,%rp ; hold return pointer
shdw_gr
shdw_gr
stw %r1,R_gr1(%r10)
stw %r8,R_gr8(%r10)
stw %r9,R_gr9(%r10)
stw %r16,R_gr16(%r10)
stw %r17,R_gr17(%r10)
stw %r24,R_gr24(%r10)
stw %r25,R_gr25(%r10)
; save control registers
mfctl %cr0,%r1
stw %r1,R_cr0(%r10)
stw %r0,R_cr1(%r10)
stw %r0,R_cr2(%r10)
stw %r0,R_cr3(%r10)
stw %r0,R_cr4(%r10)
stw %r0,R_cr5(%r10)
stw %r0,R_cr6(%r10)
stw %r0,R_cr7(%r10)
mfctl %cr8,%r1
stw %r1,R_cr8(%r10)
mfctl %cr9,%r1
stw %r1,R_cr9(%r10)
mfctl %cr10,%r1
stw %r1,R_cr10(%r10)
mfctl %cr11,%r1
stw %r1,R_cr11(%r10)
mfctl %cr12,%r1
stw %r1,R_cr12(%r10)
mfctl %cr13,%r1
stw %r1,R_cr13(%r10)
mfctl %cr14,%r1
stw %r1,R_cr14(%r10)
mfctl %cr15,%r1
stw %r1,R_cr15(%r10)
mfctl %cr16,%r1
stw %r1,R_cr16(%r10)
mfctl %cr17,%r1
stw %r1,R_cr17H(%r10)
mtctl %r1,%cr17
mfctl %cr17,%r1
stw %r1,R_cr17T(%r10)
mtctl %r1,%cr17
mfctl %cr18,%r1
stw %r1,R_cr18H(%r10)
mtctl %r1,%cr18
mfctl %cr18,%r1
stw %r1,R_cr18T(%r10)
mtctl %r1,%cr18
mfctl %cr19,%r1
stw %r1,R_cr19(%r10)
mfctl %cr20,%r1
stw %r1,R_cr20(%r10)
mfctl %cr21,%r1
stw %r1,R_cr21(%r10)
mfctl %cr22,%r1
stw %r1,R_cr22(%r10)
mfctl %cr23,%r1
stw %r1,R_cr23(%r10)
mfctl %cr24,%r1
stw %r1,R_cr24(%r10)
mfctl %cr25,%r1
stw %r1,R_cr25(%r10)
mfctl %cr26,%r1
stw %r1,R_cr26(%r10)
mfctl %cr27,%r1
stw %r1,R_cr27(%r10)
mfctl %cr28,%r1
stw %r1,R_cr28(%r10)
mfctl %cr29,%r1
stw %r1,R_cr29(%r10)
mfctl %cr30,%r1
stw %r1,R_cr30(%r10)
mfctl %cr31,%r1
stw %r1,R_cr31(%r10)
; save diagnose registers
mfcpu_c 0,%r1
mfcpu_c 0,%r1
stw %r1,R_cpu0(%r10)
; save space registers
mfsp %sr0,%r1
stw %r1,R_sr0(%r10)
mfsp %sr1,%r1
stw %r1,R_sr1(%r10)
mfsp %sr2,%r1
stw %r1,R_sr2(%r10)
mfsp %sr3,%r1
stw %r1,R_sr3(%r10)
mfsp %sr4,%r1
stw %r1,R_sr4(%r10)
mfsp %sr5,%r1
stw %r1,R_sr5(%r10)
mfsp %sr6,%r1
stw %r1,R_sr6(%r10)
mfsp %sr7,%r1
bv (%rp)
stw %r1,R_sr7(%r10)
#ifdef DEBUG_DEBUGGER
;-------------------------------------------------------------------------------
printit
mtctl %rp,%tr0
mtctl %r1,%tr1
bl putnum,%rp
copy %rp,%arg0
mtctl %mrp,%tr2
bl putc,%rp
ldi CR,%arg0
bl putc,%rp
ldi LF,%arg0
mfctl %tr2,%mrp
mfctl %tr1,%r1
bv (%mrp)
mfctl %tr0,%rp
#endif
.space $PRIVATE$
.subspa $DATA$,align=4,access=0x1f
Exception_index
.word 0
RegBlk
.block R_SIZE ; register block
Stub_stack
.block 1024
.end
|
stsp/newlib-ia16
| 19,211
|
libgloss/hp74x/iva_table.s
|
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
.space $TEXT$
.subspa $CODE$,access=0x2c
#include "diagnose.h"
#if 0
#include "iva_table.h"
#endif
R_gr0 .equ 0
R_gr1 .equ 4
R_gr2 .equ 8
R_gr3 .equ 12
R_gr4 .equ 16
R_gr5 .equ 20
R_gr6 .equ 24
R_gr7 .equ 28
R_gr8 .equ 32
R_gr9 .equ 36
R_gr10 .equ 40
R_gr11 .equ 44
R_gr12 .equ 48
R_gr13 .equ 52
R_gr14 .equ 56
R_gr15 .equ 60
R_gr16 .equ 64
R_gr17 .equ 68
R_gr18 .equ 72
R_gr19 .equ 76
R_gr20 .equ 80
R_gr21 .equ 84
R_gr22 .equ 88
R_gr23 .equ 92
R_gr24 .equ 96
R_gr25 .equ 100
R_gr26 .equ 104
R_gr27 .equ 108
R_gr28 .equ 112
R_gr29 .equ 116
R_gr30 .equ 120
R_gr31 .equ 124
R_rctr .equ 160
R_cpu0 .equ 164
R_pidr1 .equ 168
R_pidr2 .equ 172
R_ccr .equ 176
R_sar .equ 180
R_pidr3 .equ 184
R_pidr4 .equ 188
R_iva .equ 192
R_eiem .equ 196
R_itmr .equ 200
R_pcsqH .equ 204
R_pcoqH .equ 208
R_iir .equ 212
R_pcsqT .equ 216
R_pcoqT .equ 220
R_isr .equ 224
R_ior .equ 228
R_ipsw .equ 232
R_eirr .equ 236
R_tr0 .equ 240
R_tr1 .equ 244
R_tr2 .equ 248
R_tr3 .equ 252
R_tr4 .equ 256
R_tr5 .equ 260
R_tr6 .equ 264
R_tr7 .equ 268
R_SIZE .equ 300
.import putc,code
.import puts,code
.import putnum,code
.import put_led,code
.import save_regs,code
.import STUB_RESTORE,code
.import RegBlk,data
.export iva_table,data
.IMPORT led_putnum,code
.IMPORT delay,code
.IMPORT putnum,code
.IMPORT outbyte,code
.IMPORT print,code
.align 2048
iva_table
.blockz 32 ; entry 0 is reserved
.align 32
hpmc
nop
b,n hpmc_handler
nop
.word 0
.word 0
.word 0
.word hpmc_handler
.word 0
.align 32
power_fail
; PrintString Str02,0x2
ldi 1,%r26
bl,n putnum,%r2
nop
.align 32
recovery
;; PrintString Str03,0x3
ldi 2,%r26
bl,n putnum,%r2
nop
ldi 3,%r1
b,n handle_rcc
nop
.align 32
external
; PrintString Str04,0x4
ldi 3,%r26
bl,n putnum,%r2
nop
.align 32
lpmc
; PrintString Str05,0x5
ldi 4,%r26
bl,n putnum,%r2
nop
.align 32
itlb_miss
; PrintString Str06,0x6
ldi 5,%r26
bl,n putnum,%r2
nop
.align 32
imem_protection
; PrintString Str07,0x7
ldi 6,%r26
bl,n putnum,%r2
nop
.align 32
illegal_inst
; PrintString Str08,0x8
ldi 7,%r26
bl,n putnum,%r2
nop
.align 32
break
b,n break_handler
nop
.align 32
privileged_op
; PrintString Str0a,0xa
ldi 8,%r26
bl,n putnum,%r2
nop
.align 32
privileged_reg
; PrintString Str0b,0xb
ldi 9,%r26
bl,n putnum,%r2
nop
.align 32
overflow
; PrintString Str0c,0xc
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
conditional
; PrintString Str0d,0xd
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
assist_excep
; PrintString Str0e,0xe
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
dtlb_miss
; PrintString Str0f,0xf
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
na_itlb
; PrintString Str10,0x10
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
na_dtlb
; PrintString Str11,0x11
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
dmem_protection
; PrintString Str12,0x12
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
dmem_break
; PrintString Str13,0x13
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
tlb_dirty
; PrintString Str14,0x14
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
page_ref
; PrintString Str15,0x15
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
assist_emul
; PrintString Str16,0x16
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
high_priv
; PrintString Str17,0x17
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
low_priv
; PrintString Str18,0x18
ldi 32,%r26
bl,n putnum,%r2
nop
.align 32
branch_taken
; PrintString Str19,0x19
ldi 32,%r26
bl,n putnum,%r2
nop
/*
* foobar -- debug procedure calling between C and assembler
*/
.EXPORT foobar,ENTRY,ARGW0=GR,RTNVAL=GR
foobar
.PROC
.CALLINFO CALLER,FRAME=128,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30) ; stash the return pointer
ldo 128(%r30),%r30 ; push up the stack pointer
ldi 8, %r26
bl,n led_putnum,%r2
nop
ldil L'900000,%r26
ldo R'900000(%r26),%r26
bl,n delay,%r2
nop
ldi 8, %r26
bl,n led_putnum,%r2
nop
ldil L'900000,%r26
ldo R'900000(%r26),%r26
bl,n delay,%r2
nop
;; copy %r26,%r26
;; bl,n putnum,%r2
nop
ldw -148(0,%r30),%r2 ; retrieve the return pointer
ldo -128(%r30),%r30 ; reset the stack pointer
bv,n 0(%r2)
nop
.EXIT
.PROCEND
/*
* setup_vectors -- add vectors for GDB to the vector table.
* %r3 - current vector table
* %r4 - new vector table
*/
.EXPORT setup_vectors,ENTRY,ARGW0=GR,RTNVAL=GR
setup_vectors
.PROC
.CALLINFO CALLER,FRAME=128,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30) ; stash the return pointer
ldo 128(%r30),%r30 ; push up the stack pointer
mfctl %iva,%r3
ldil L%iva_table,%r4 ; Get the new vector table
ldo R%iva_table(%r4),%r4 ; address
ldil L%break_handler,%r5 ; Get the breakpoint
ldo R%break_handler(%r5),%r5 ; handler vector
ldil L%break_default,%r6 ; Get the default handler
ldo R%break_default(%r6),%r6 ; vector
stw %r6,4(%r4) ; ad the default vector
stw %r5,36(%r4) ; add the break vector
mtctl %r4,%iva
ldw -148(0,%r30),%r2 ; retrieve the return pointer
ldo -128(%r30),%r30 ; reset the stack pointer
bv,n 0(%r2)
nop
.EXIT
.PROCEND
;-------------------------------------------------------------------------------
hpmc_handler
bl,n save_state,%r25
nop
bl print_intr,%rp
ldi Str01-Str01,%arg0
bl print_state,%rp
nop
ldil L%0xf0000000,%r1
ldw (%r1),%r1 ; read from ROM to reset HPMC
mfcpu_c 0,%r1
mfcpu_c 0,%r1
depi 0,CPU_DIAG_0_PREV_HPMC_PREP_BIT,1,%r1 ; clear Prev HPMC bit
#ifdef PCXL
depi 0,CPU_DIAG_0_L2DHPMC_BIT,1,%r1
depi 0,CPU_DIAG_0_L2IHPMC_BIT,1,%r1
depi 0,CPU_DIAG_0_L1IHPMC_BIT,1,%r1
depi 0,CPU_DIAG_0_L2PARERR_BIT,4,%r1
#else /* PCXT */
depi 0,CPU_DIAG_0_DHPMC_BIT,1,%r1 ; don't clear DHPMC
depi 0,CPU_DIAG_0_ILPMC_BIT,1,%r1 ; don't clear ILPMC
depi 0,CPU_DIAG_0_HTOC_BIT,1,%r1 ; don't clear HTOC
#endif
mtcpu %r1,0
mtcpu %r1,0
b,n restore_to_STUB
ldi 0x1,%r1
/*
* break_handler -- this is the main entry point for an exception
*/
.ALIGN 2048
break_handler
mfctl %iir,%r1 ; r1 = break instruction
extru %r1,18,13,%r8
ldo -i13BREAK(%r8),%r8 ; if im13 field doesn't match
comb,<>,n %r8,%r0,break_default ; go to default operation
extru %r1,31,5,%r8
ldi 0x9,%r1 ; set exception index
comib,=,n i5BP,%r8,break_breakpoint
comib,=,n i5PSW,%r8,break_psw
comib,=,n i5REG,%r8,break_reg_init
comib,=,n i5INLINE,%r8,break_breakpoint
; fall through to break_default
break_default
; PrintString Str09,0x9
ldi 32,%r26
bl,n putnum,%r2
nop
break_reg_init
bl setup_vectors,%r25
nop
bl save_regs,%r25
nop
; fall through to advance past break instruction
break_psw
b,n recover
break_breakpoint
b,n STUB_RESTORE
;-------------------------------------------------------------------------------
handle_rcc
mfctl %ipsw,%r1
bb,>=,n %r1,10,do_restore ; check nullify bit
dep %r0,10,1,%r1
mtctl %r1,%ipsw ; clear nullify bit
;; was the AdvancePCOQ .macro
mtctl %r0,%pcoq ; throw away iiaoq head pointer, tail->head
mfctl %pcoq,%r1 ; get tail pointer
mtctl %r1,%pcoq ; insert tail pointer
ldo 4(%r1),%r1 ; advance tail pointer
mtctl %r1,%pcoq ; insert new tail pointer, former tail->head
do_restore
b,n STUB_RESTORE
nop
;-------------------------------------------------------------------------------
print_intr
; %dp may be messed up, so do self-relocating to reach Save_area
blr %r0,%r1
addil L%Str01-pr_intr_0,%r1
pr_intr_0
ldo R%Str01-pr_intr_0(%r1),%r1 ; r1 points to Save_area
b puts ; print string--return through rp
add %r1,%arg0,%arg0
;-------------------------------------------------------------------------------
halt
; %dp may be messed up, so do self-relocating to reach Save_area
blr %r0,%r1
addil L%HaltStr-halt_0,%r1
halt_0
bl puts,%rp ; print halt message
ldo R%HaltStr-halt_0(%r1),%arg0
nop
b,n . ; loop forever
nop
;-------------------------------------------------------------------------------
recover
;; was the AdvancePCOQ .macro
mtctl %r0,%pcoq ; throw away iiaoq head pointer, tail->head
mfctl %pcoq,%r1 ; get tail pointer
mtctl %r1,%pcoq ; insert tail pointer
ldo 4(%r1),%r1 ; advance tail pointer
mtctl %r1,%pcoq ; insert new tail pointer, former tail->head
rfir
;-------------------------------------------------------------------------------
save_state ; %r25 is return pointer
; %dp may be messed up, so do self-relocating to reach Save_area
blr %r0,%r1
addil L%Save_area-sa_st_0,%r1
sa_st_0
ldo R%Save_area-sa_st_0(%r1),%r1 ; r1 points to Save_area
; save general registers
stw %r0,R_gr0(%r1)
; don't save %r1 until restored
stw %r2,R_gr2(%r1)
stw %r3,R_gr3(%r1)
stw %r4,R_gr4(%r1)
stw %r5,R_gr5(%r1)
stw %r6,R_gr6(%r1)
stw %r7,R_gr7(%r1)
; don't save %r8, %r9 until restored
stw %r10,R_gr10(%r1)
stw %r11,R_gr11(%r1)
stw %r12,R_gr12(%r1)
stw %r13,R_gr13(%r1)
stw %r14,R_gr14(%r1)
stw %r15,R_gr15(%r1)
; don't save %r16, %r17 until restored
stw %r18,R_gr18(%r1)
stw %r19,R_gr19(%r1)
stw %r20,R_gr20(%r1)
stw %r21,R_gr21(%r1)
stw %r22,R_gr22(%r1)
stw %r23,R_gr23(%r1)
; don't save %r24, %r25 until restored
stw %r26,R_gr26(%r1)
stw %r27,R_gr27(%r1)
stw %r28,R_gr28(%r1)
stw %r29,R_gr29(%r1)
copy %r25,%rp ; copy return pointer to %rp
stw %r30,R_gr30(%r1)
copy %r1,%r19 ; save Save_area pointer in %r19
stw %r31,R_gr31(%r1)
shdw_gr ; restore %r1 and %r25 (et al.) from shadow regs
shdw_gr
stw %r1,R_gr1(%r19) ; save %r1
stw %r8,R_gr8(%r19)
stw %r9,R_gr9(%r19)
stw %r16,R_gr16(%r19)
stw %r17,R_gr17(%r19)
stw %r24,R_gr24(%r19)
; save control registers
mfctl %rctr,%r1
stw %r1,R_rctr(%r19)
mfctl %pidr1,%r1
stw %r1,R_pidr1(%r19)
mfctl %pidr2,%r1
stw %r1,R_pidr2(%r19)
mfctl %ccr,%r1
stw %r1,R_ccr(%r19)
mfctl %sar,%r1
stw %r1,R_sar(%r19)
mfctl %pidr3,%r1
stw %r1,R_pidr3(%r19)
mfctl %pidr4,%r1
stw %r1,R_pidr4(%r19)
mfctl %iva,%r1
stw %r1,R_iva(%r19)
mfctl %eiem,%r1
stw %r1,R_eiem(%r19)
mfctl %itmr,%r1
stw %r1,R_itmr(%r19)
mfctl %pcsq,%r1
mtctl %r1,%pcsq
stw %r1,R_pcsqH(%r19)
mfctl %pcsq,%r1
mtctl %r1,%pcsq
stw %r1,R_pcsqT(%r19)
mfctl %pcoq,%r1
mtctl %r1,%pcoq
stw %r1,R_pcoqH(%r19)
mfctl %pcoq,%r1
mtctl %r1,%pcoq
stw %r1,R_pcoqT(%r19)
mfctl %iir,%r1
stw %r1,R_iir(%r19)
mfctl %isr,%r1
stw %r1,R_isr(%r19)
mfctl %ior,%r1
stw %r1,R_ior(%r19)
mfctl %ipsw,%r1
stw %r1,R_ipsw(%r19)
mfctl %eirr,%r1
stw %r1,R_eirr(%r19)
mfctl %tr0,%r1
stw %r1,R_tr0(%r19)
mfctl %tr1,%r1
stw %r1,R_tr1(%r19)
mfctl %tr2,%r1
stw %r1,R_tr2(%r19)
mfctl %tr3,%r1
stw %r1,R_tr3(%r19)
mfctl %tr4,%r1
stw %r1,R_tr4(%r19)
mfctl %tr5,%r1
stw %r1,R_tr5(%r19)
mfctl %tr6,%r1
stw %r1,R_tr6(%r19)
mfctl %tr7,%r1
stw %r1,R_tr7(%r19)
; save diagnose registers
mfcpu_c 0,%r1
mfcpu_c 0,%r1
stw %r1,R_cpu0(%r19)
#ifdef PRINT_SPACE
stw %r25,R_gr25(%r19)
; save space registers
mfsp %sr0,%r1
stw %r1,R_sr0(%r19)
mfsp %sr1,%r1
stw %r1,R_sr1(%r19)
mfsp %sr2,%r1
stw %r1,R_sr2(%r19)
mfsp %sr3,%r1
stw %r1,R_sr3(%r19)
mfsp %sr4,%r1
stw %r1,R_sr4(%r19)
mfsp %sr5,%r1
stw %r1,R_sr5(%r19)
mfsp %sr6,%r1
stw %r1,R_sr6(%r19)
mfsp %sr7,%r1
bv (%rp)
stw %r1,R_sr7(%r19)
#else
bv (%rp)
stw %r25,R_gr25(%r19)
#endif
;-------------------------------------------------------------------------------
restore_to_STUB ; doesn't return--goes to STUB_RESTORE
; Note--STUB_RESTORE executes rfir,
; so we don't need to
copy %r1,%r8 ; save exception index
; %dp may be messed up, so do self-relocating to reach Save_area
bl re_st_0,%r1
addil L%Save_area-re_st_0,%r1
re_st_0
ldo R%Save_area-re_st_0(%r1),%r1 ; r1 points to Save_area
; restore general registers
ldw R_gr2(%r1),%r2
ldw R_gr3(%r1),%r3
ldw R_gr4(%r1),%r4
ldw R_gr5(%r1),%r5
ldw R_gr6(%r1),%r6
ldw R_gr7(%r1),%r7
; ldw R_gr8(%r1),%r8 don't smash the exception index
ldw R_gr9(%r1),%r9
ldw R_gr10(%r1),%r10
ldw R_gr11(%r1),%r11
ldw R_gr12(%r1),%r12
ldw R_gr13(%r1),%r13
ldw R_gr14(%r1),%r14
ldw R_gr15(%r1),%r15
ldw R_gr16(%r1),%r16
ldw R_gr17(%r1),%r17
ldw R_gr18(%r1),%r18
ldw R_gr19(%r1),%r19
ldw R_gr20(%r1),%r20
ldw R_gr21(%r1),%r21
ldw R_gr22(%r1),%r22
ldw R_gr23(%r1),%r23
ldw R_gr24(%r1),%r24
ldw R_gr25(%r1),%r25
ldw R_gr26(%r1),%r26
ldw R_gr27(%r1),%r27
ldw R_gr28(%r1),%r28
ldw R_gr29(%r1),%r29
ldw R_gr30(%r1),%r30
ldw R_gr31(%r1),%r31
ldw R_gr1(%r1),%r1
b STUB_RESTORE
copy %r8,%r1 ; restore the exception index
;-------------------------------------------------------------------------------
#define HoldPtr %r10
#define SavePtr %r11
#define StrPtr %r12
#define Count %r13
#define Hold_Hold 0*4 /* First word of hold area */
#define Hold_Save 1*4 /* Second word of hold area */
#define Hold_Str 2*4 /* Third word of hold area */
#define Hold_Count 3*4 /* Fourth word of hold area */
#define Hold_rp 4*4 /* Fifth word of hold area */
print_state
; %dp may be messed up, so do self-relocating to reach Save_area
blr %r0,%mrp
addil L%Hold_area-pr_st_0,%mrp
pr_st_0
ldo R%Hold_area-pr_st_0(%r1),%r1 ; r1 points to Hold_area
; save working registers
stw HoldPtr,Hold_Hold(%r1)
copy %r1,HoldPtr ; HoldPtr = &Hold_area
stw SavePtr,Hold_Save(HoldPtr)
ldo Save_area-Hold_area(HoldPtr),SavePtr ; SavePtr = &Save_area
stw StrPtr,Hold_Str(HoldPtr)
addil L%PrintLabels-pr_st_0,%mrp
stw Count,Hold_Count(HoldPtr)
ldo R%PrintLabels-pr_st_0(%r1),StrPtr
stw %rp,Hold_rp(HoldPtr)
#ifdef PRINT_SPACE
ldi 68,Count
#else
ldo R_gr0(SavePtr),SavePtr
ldi 60,Count
#endif
; print register values
print_loop
bl puts,%rp ; print label
ldo 1(StrPtr),%arg0 ; advance past length byte
bl putnum,%rp ; print register value
ldwm 4(SavePtr),%arg0
ldbs,ma 1(StrPtr),%r1
addib,> -1,Count,print_loop
add %r1,StrPtr,StrPtr
; skip to next line
bl puts,%rp ; print label
ldo 1(StrPtr),%arg0 ; advance past length byte
; restore working registers
ldw Hold_rp(HoldPtr),%rp
ldw Hold_Count(HoldPtr),Count
ldw Hold_Str(HoldPtr),StrPtr
ldw Hold_Save(HoldPtr),SavePtr
bv (%rp)
ldw Hold_Hold(HoldPtr),HoldPtr
#undef SavePtr
#undef HoldPtr
#undef StrPtr
#undef Count
#undef Hold_Save
#undef Hold_Scr
#undef Hold_Str
#undef Hold_Count
#undef Hold_rp
;-------------------------------------------------------------------------------
.space $PRIVATE$
.subspa $DATA$,align=4,access=0x1f
/* Used to save machine registers before printing */
Save_area
.block R_SIZE ; Used to store registers
/* Used to hold callee-save registers */
Hold_area
.block 8*4 ; 8 words to store temp. registers
HaltStr
.stringz "\r\nHalted\r\n"
RebootStr
.stringz "\r\nRebooting . . .\r\n"
Str01
.stringz "\r\nHPMC\r\n"
Str02
.stringz "\r\nPower Fail\r\n"
Str03
.stringz "\r\nRecovery Counter Trap\r\n"
Str04
.stringz "\r\nExternal Interrupt\r\n"
Str05
.stringz "\r\nLPMC\r\n"
Str06
.stringz "\r\nITLB Miss\r\n"
Str07
.stringz "\r\nInstruction Memory Protection Trap\r\n"
Str08
.stringz "\r\nIllegal Instruction\r\n"
Str09
.stringz "\r\nBreak Trap\r\n"
Str0a
.stringz "\r\nPrivileged Operation\r\n"
Str0b
.stringz "\r\nPrivileged Register\r\n"
Str0c
.stringz "\r\nOverflow Trap\r\n"
Str0d
.stringz "\r\nConditional Trap\r\n"
Str0e
.stringz "\r\nAssist Exception\r\n"
Str0f
.stringz "\r\nData TLB Miss\r\n"
Str10
.stringz "\r\nNon-access ITLB Miss\r\n"
Str11
.stringz "\r\nNon-access DTLB Miss\r\n"
Str12
.stringz "\r\nData Memory Protection Trap\r\n"
Str13
.stringz "\r\nData Memory Break\r\n"
Str14
.stringz "\r\nTLB Dirty Bit Trap\r\n"
Str15
.stringz "\r\nPage Reference Trap\r\n"
Str16
.stringz "\r\nAssist Emulation Trap\r\n"
Str17
.stringz "\r\nHigher-privilege Trap\r\n"
Str18
.stringz "\r\nLower-privilege Trap\r\n"
Str19
.stringz "\r\nTaken Branch Trap\r\n"
Str20
.stringz "\r\nHere I am!\r\n"
PrintLabels
#ifdef PRINT_SPACE
.byte 10
.stringz "sr 0 = 0x"
.byte 13
.stringz "sr 1 = 0x"
.byte 13
.stringz "sr 2 = 0x"
.byte 13
.stringz " sr 3 = 0x"
.byte 12
.stringz "\r\nsr 4 = 0x"
.byte 13
.stringz " sr 5 = 0x"
.byte 13
.stringz " sr 6 = 0x"
.byte 13
.stringz " sr 7 = 0x"
.byte 13
.stringz "\r\n\ngr 0 = 0x"
#else
.byte 10
.stringz "gr 0 = 0x"
#endif
.byte 13
.stringz " gr 1 = 0x"
.byte 13
.stringz " gr 2 = 0x"
.byte 13
.stringz " gr 3 = 0x"
.byte 12
.stringz "\r\ngr 4 = 0x"
.byte 13
.stringz " gr 5 = 0x"
.byte 13
.stringz " gr 6 = 0x"
.byte 13
.stringz " gr 7 = 0x"
.byte 12
.stringz "\r\ngr 8 = 0x"
.byte 13
.stringz " gr 9 = 0x"
.byte 13
.stringz " gr10 = 0x"
.byte 13
.stringz " gr11 = 0x"
.byte 12
.stringz "\r\ngr12 = 0x"
.byte 13
.stringz " gr13 = 0x"
.byte 13
.stringz " gr14 = 0x"
.byte 13
.stringz " gr15 = 0x"
.byte 12
.stringz "\r\ngr16 = 0x"
.byte 13
.stringz " gr17 = 0x"
.byte 13
.stringz " gr18 = 0x"
.byte 13
.stringz " gr19 = 0x"
.byte 12
.stringz "\r\ngr20 = 0x"
.byte 13
.stringz " gr21 = 0x"
.byte 13
.stringz " gr22 = 0x"
.byte 13
.stringz " gr23 = 0x"
.byte 12
.stringz "\r\ngr24 = 0x"
.byte 13
.stringz " gr25 = 0x"
.byte 13
.stringz " gr26 = 0x"
.byte 13
.stringz " gr27 = 0x"
.byte 12
.stringz "\r\ngr28 = 0x"
.byte 13
.stringz " gr29 = 0x"
.byte 13
.stringz " gr30 = 0x"
.byte 13
.stringz " gr31 = 0x"
.byte 13
.stringz "\r\n\nrctr = 0x"
.byte 53
.stringz " cpu0 = 0x"
.byte 12
.stringz "\r\npid1 = 0x"
.byte 13
.stringz " pid2 = 0x"
.byte 13
.stringz " ccr = 0x"
.byte 13
.stringz " sar = 0x"
.byte 12
.stringz "\r\npid3 = 0x"
.byte 13
.stringz " pid4 = 0x"
.byte 13
.stringz " iva = 0x"
.byte 13
.stringz " eiem = 0x"
.byte 12
.stringz "\r\nitmr = 0x"
.byte 13
.stringz " iasq = 0x"
.byte 13
.stringz " iaoq = 0x"
.byte 13
.stringz " iir = 0x"
.byte 32
.stringz "\r\n iasq = 0x"
.byte 13
.stringz " iaoq = 0x"
.byte 12
.stringz "\r\n isr = 0x"
.byte 13
.stringz " ior = 0x"
.byte 13
.stringz " ipsw = 0x"
.byte 13
.stringz " eirr = 0x"
.byte 12
.stringz "\r\ncr24 = 0x"
.byte 13
.stringz " cr25 = 0x"
.byte 13
.stringz " cr26 = 0x"
.byte 13
.stringz " cr27 = 0x"
.byte 12
.stringz "\r\ncr28 = 0x"
.byte 13
.stringz " cr29 = 0x"
.byte 13
.stringz " cr30 = 0x"
.byte 13
.stringz " cr31 = 0x"
.byte 4
.stringz "\r\n\n"
.end
|
stsp/newlib-ia16
| 4,595
|
libgloss/hp74x/crt0.s
|
/*
* crt0.S -- startup file for hppa.
* rob@cygnus.com (Rob Savoye)
*/
.VERSION "0.2"
.COPYRIGHT "crt0.S for hppa"
;sp .equ %r30 ; stack pointer
;dp .equ %r27 ; global data pointer
;arg0 .equ %r26 ; argument
;arg1 .equ %r25 ; argument or high part of double argument
;arg2 .equ %r24 ; argument
;arg3 .equ %r23 ; argument or high part of double argument
#define IMM(a,b) ldil L%a,b ! ldo R%a(b),b
#define imm(i,t) ldil LS%i,t ! addi RS%i,t,t
.DATA
/****
* FIXME: these are just a gross hack so this will assemble
****/
_bss_start .WORD
_bss_end .WORD
_foobar
.STRINGZ "Foo Bar...\r\n"
;;_SYSTEM_ID .WORD
;; .EXPORT _SYSTEM_ID ; FIXME this is only so it'll
; link
/*
* Set up the standard spaces (sections) These definitions come
* from /lib/pcc_prefix.s.
*/
.space $TEXT$,0
.SUBSPA $BOOT$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=4
.IMPORT _start
/*
* stuff we need that's defined elsewhere.
*/
.IMPORT main, CODE
.IMPORT _bss_start, DATA
.IMPORT _bss_end, DATA
.IMPORT environ, DATA
/*
* start -- set things up so the application will run.
*
*/
.PROC
.CALLINFO SAVE_SP, FRAME=48
.EXPORT $START$,ENTRY
$START$
/* FIXME: this writes to page zero */
;; setup the %30 (stack pointer) with some memory
ldil L%_stack+48,%r30
ldo R%_stack+48(%r30),%r30 ; should be %r30 (sp) but then
; we'd kill our test program :-)
;; we need to set %r27 (global data pointer) here too
ldil L%$global$,%r27
ldo R%$global$(%r27),%r27 ; same problem as above
/*
* zerobss -- zero out the bss section
*/
; load the start of bss
ldil L%_bss_start,%r4
ldo R%_bss_start(%r4),%r4
; load the end of bss
ldil L%_bss_end,%r5
ldo R%_bss_end(%r5),%r5
bssloop
addi -1,%r5,%r5 ; decrement _bss_end
stb %r0,0(0,%r5) ; we do this by bytes for now even
; though it's slower, it's safer
combf,= %r4,%r5, bssloop
nop
ldi 1,%ret0
/*
* Call the main routine from the application to get it going.
* main (argc, argv, environ)
* We pass argv as a pointer to NULL.
*/
bl main,%r2
nop
.PROCEND
/*
* _exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run, but with
* this monitor we can't. Still, "C" wants this symbol, it
* should be here. Jumping to 0xF0000004 jumps back into the
* firmware, while writing a 5 to 0xFFFE0030 causes a reset.
*/
.EXPORT _exit, ENTRY
_exit
.PROC
.CALLINFO
.ENTRY
;; ldil L%0xf0000004,%r1
;; bl %r1, %r2
ldil L'4026531844,%r19
ldo R'4026531844(%r19),%r19
blr %r19, %r2
nop
;; This just causes a breakpoint exception
;; break 0x0e,0xa5a
;; bv,n (%rp)
nop
.EXIT
.PROCEND
.subspa $UNWIND_START$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=56
.export $UNWIND_START
$UNWIND_START
.subspa $UNWIND$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=64
.subspa $UNWIND_END$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=72
.export $UNWIND_END
$UNWIND_END
.subspa $RECOVER_START$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=73
.export $RECOVER_START
$RECOVER_START
.subspa $RECOVER$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=80
.subspa $RECOVER_END$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=88
.export $RECOVER_END
$RECOVER_END
; The following declarations are, by default in the data space ($PRIVATE$)
;; .space $PRIVATE$,1
/*
* Here we set up the standard date sub spaces.
* _dp is for the WinBond board.
*
* Set up some room for a stack. We just grab a chunk of memory.
* We also setup some space for the global variable space, which
* must be done using the reserved name "$global$" so "C" code
* can find it. The stack grows towards the higher addresses.
*/
.subspa $DATA$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=16
.subspa $SHORTDATA$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=24
.subspa $GLOBAL$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=40
.export $global$
.export _dp
$global$
_dp
.subspa $SHORTBSS$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=80,ZERO
.subspa $BSS$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82,ZERO
.subspa $STACK$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=88,ZERO
.export _stack
_stack
.BLOCK 0x2000
/*
* The heap follows the stack. To use dynamic memory routines in an
* application, some space MUST be assigned to the stack.
*/
.subspa $HEAP$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=96,ZERO
.export _heap
_heap
.end
|
stsp/newlib-ia16
| 1,553
|
libgloss/crx/crtn.S
|
/* Specialized code needed to support construction and destruction of
file-scope objects in C++ and Java code, and to support exception handling.
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* As a special exception, if you link this library with files
compiled with GCC to produce an executable, this does not cause
the resulting executable to be covered by the GNU General Public License.
This exception does not however invalidate any other reasons why
the executable file might be covered by the GNU General Public License. */
/*
* This file supplies function epilogues for the .init and .fini sections.
* It is linked in after all other files.
*/
.file "crtn.o"
.ident "GNU C crtn.o"
.section .init
popret ra
.section .fini
popret ra
|
stsp/newlib-ia16
| 4,414
|
libgloss/crx/crt0.S
|
##############################################################################
# crt0.S -- CRX default start-up routine #
# #
# Copyright (c) 2004 National Semiconductor Corporation #
# #
# The authors hereby grant permission to use, copy, modify, distribute, #
# and license this software and its documentation for any purpose, provided #
# that existing copyright notices are retained in all copies and that this #
# notice is included verbatim in any distributions. No written agreement, #
# license, or royalty fee is required for any of the authorized uses. #
# Modifications to this software may be copyrighted by their authors #
# and need not follow the licensing terms described here, provided that #
# the new terms are clearly indicated on the first page of each file where #
# they apply. #
# #
# This is the start routine of your CRX program. #
# It is linked with your application automatically. You can use #
# this routine as a template and modify it to your needs, yet this #
# file must be supplied for the compiler. #
# It is assumed that the following symbols are defined in your linker #
# script: __STACK_START, __ISTACK_START, __DATA_START, __DATA_END, #
# __DATA_IMAGE_START, __BSS_START, __BSS_END. #
##############################################################################
.text
.align 4
.globl _main
.globl _start
.globl _atexit
.globl _exit
.globl __dispatch_table
_start:
#----------------------------------------------------------------------------#
# Initialize the stack pointers. The constants __STACK_START and #
# __ISTACK_START should be defined in the linker script. #
movd $__STACK_START, sp
movd $__ISTACK_START, r0
mtpr r0, isp
#----------------------------------------------------------------------------#
# Initialize the default sections according to the linker script. #
movd $__DATA_END, r4
subd $__DATA_START, r4
movd $__DATA_START, r2
movd $__DATA_IMAGE_START, r3
bal ra, _memcpy
movd $__BSS_END, r4
subd $__BSS_START, r4
movd $__BSS_START, r2
movd $0, r3
bal ra, _memset
#----------------------------------------------------------------------------#
# Initialize the intbase (pointer to the dispatch table). #
movd $__dispatch_table, r0
mtpr r0, intbase
#----------------------------------------------------------------------------#
# Handle global and static constructurs execution and setup #
# destructors to be called from exit. #
bal ra, _init
movd $_fini, r2
bal ra, _atexit
#----------------------------------------------------------------------------#
# Here you may add initializations that are specific to your #
# environment. For example: #
# 1. Configure wait states and other BIU parameters in order to get #
# the best performance out of your target (see the specification #
# document). #
# 2. Enable maskable interrupts that should be enabled when your #
# program starts to execute. #
#----------------------------------------------------------------------------#
# Jump to the main function in your application. #
bal ra, _main
#----------------------------------------------------------------------------#
# Upon returning from the main function (if it isn't an infinite loop), #
# jump to the exit function. The exit function is located in the #
# library 'libc.a'. #
movd r0, r2 # _main return value is passed as a
# parameter to exit.
br _exit # returns control to the debugger.
|
stsp/newlib-ia16
| 1,646
|
libgloss/crx/crti.S
|
/* Specialized code needed to support construction and destruction of
file-scope objects in C++ and Java code, and to support exception handling.
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Charles-Antoine Gauthier (charles.gauthier@iit.nrc.ca).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* As a special exception, if you link this library with files
compiled with GCC to produce an executable, this does not cause
the resulting executable to be covered by the GNU General Public License.
This exception does not however invalidate any other reasons why
the executable file might be covered by the GNU General Public License. */
/*
* This file just supplies function prologues for the .init and .fini
* sections. It is linked in before crtbegin.o.
*/
.file "crti.o"
.ident "GNU C crti.o"
.section .init
.globl _init
.type _init,@function
_init:
push ra
.section .fini
.globl _fini
.type _fini,@function
_fini:
push ra
|
stsp/newlib-ia16
| 1,460
|
libgloss/d30v/crt0.S
|
/*
* crt0.S -- startup file for D30V systems.
*
* Copyright (c) 1997 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
.file "crt0.S"
.text
.globl _start
.extern main
.extern exit
.extern __stack
.extern __sbss_start
.extern __sbss_end
.extern __ebss_start
.extern __ebss_end
.extern __bss_start
.extern __bss_end
.extern memset
.type _start,@function
_start: or.l sp,r0,__stack
/* Zero the .sbss area */
or.l r2,r0,__sbss_start
or.l r4,r0,__sbss_end
sub r4,r4,r2 || or.s r3,r0,0
bsrtnz.l r4,(memset)
/* Zero the .ebss area */
or.l r2,r0,__ebss_start
or.l r4,r0,__ebss_end
sub r4,r4,r2 || or.s r3,r0,0
bsrtnz.l r4,(memset)
/* Zero the .bss area */
or.l r2,r0,__bss_start
or.l r4,r0,__bss_end
sub r4,r4,r2 || or.s r3,r0,0
bsrtnz.l r4,(memset)
or.s r2,r0,0 || or.s r3,r0,0
or r4,r0,0 || nop
jsr.l (main)
jsr.l (exit)
.size _start,.-_start
|
stsp/newlib-ia16
| 1,250
|
libgloss/m32r/crt0.S
|
.text
.balign 4
.global _start
_start:
seth sp, #shigh(_stack)
add3 sp, sp, #low(_stack)
ldi fp, #0
# Clear the BSS. Do it in two parts for efficiency: longwords first
# for most of it, then the remaining 0 to 3 bytes.
seth r2, #shigh(__bss_start)
add3 r2, r2, #low(__bss_start); R2 = start of BSS
seth r3, #shigh(_end)
add3 r3, r3, #low(_end) ; R3 = end of BSS + 1
sub r3, r2 ; R3 = BSS size in bytes
mv r4, r3
srli r4, #2 ; R4 = BSS size in longwords (rounded down)
ldi r1, #0 ; clear R1 for longword store
addi r2, #-4 ; account for pre-inc store
beqz r4, .Lendloop1 ; any more to go?
.Lloop1:
st r1, @+r2 ; yep, zero out another longword
addi r4, #-1 ; decrement count
bnez r4, .Lloop1 ; go do some more
.Lendloop1:
and3 r4, r3, #3 ; get no. of remaining BSS bytes to clear
addi r2, #4 ; account for pre-inc store
beqz r4, .Lendloop2 ; any more to go?
.Lloop2:
stb r1, @r2 ; yep, zero out another byte
addi r2, #1 ; bump address
addi r4, #-1 ; decrement count
bnez r4, .Lloop2 ; go do some more
.Lendloop2:
# Run code in the .init section.
# This will queue the .fini section to be run with atexit.
bl __init
# Call main, then exit.
bl main
bl exit
# If that fails just loop.
.Lexit:
bra .Lexit
|
stsp/newlib-ia16
| 1,291
|
libgloss/ia16/dos-msmmabort.S
|
/*
* Copyright (c) 2018--2019 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* Implementation of abort () for MS-DOS and the small or medium memory
model. This implementation tries to work properly even if %ss is wrong. */
#include "call-cvt.h"
.arch i8086, jumps
.code16
TEXT_ (dos_msmmabort.S.LIBGLOSS)
.global abort
abort:
pushfw
cli
pushw %ds
movw %cs:__ia16_near_data_segment, %ds
popw abort_stack-8
popw abort_stack-2
movw %sp, abort_stack-4
movw %ss, abort_stack-6
movw %ds, %sp
movw %sp, %ss
movw $abort_stack-8, %sp
pushw %es
pushw %cs
pushw %di
pushw %si
pushw %bp
pushw %dx
pushw %cx
pushw %bx
pushw %ax
cld
sti
CALL_ (__ia16_abort_impl)
.bss
.skip 128
abort_stack:
|
stsp/newlib-ia16
| 4,670
|
libgloss/ia16/dos-timesr.S
|
/*
* Implementation of _times_r for DOS which should be relatively fast, if a
* tad hacky.
*
* To avoid having to deal with discontinuities in the system timer --- due
* to midnight crossover, daylight saving time, and what not --- I arrange
* to install our own timer tick ISR (int $0x1c) which increments its own
* separate counters. The ISR is placed in the data segment (!) to make it
* easier to access its own data, unless our program is a DPMI-mode program.
*
* Each int 0x1c call corresponds to (24 * 60 * 60) / 0x1800b0 == 1080 / 19663
* seconds of elapsed time, so it should increment the number of clock_t
* "ticks" by _CLOCKS_PER_SEC_ * 1080 / 19663. The code maintains the
* fractional portion of the "tick" count in a separate halfword.
*
* I also use the DOS 2+ InDOS flag to get a (crude) indication of whether
* the CPU is running "system" code or "user" code at each point in time.
*/
#include <machine/time.h>
#include "call-cvt.h"
.arch i8086,jumps
.code16
.att_syntax prefix
#APP /* need this to expand _CLOCKS_PER_SEC_ properly */
#ifndef _CLOCKS_PER_SEC_
#define _CLOCKS_PER_SEC_ 1000
#endif
TEXT_ (dos_timesr.S.LIBGLOSS)
.section .text, "ax"
.Lctor_timesr:
#ifndef __IA16_FEATURE_DOSX
pushw %es
movb $0x34, %ah
int $0x21
movw %bx, .Lp_indos
movw %es, .Lp_indos+2
movw $0x351c, %ax
int $0x21
movw %bx, .Lp_orig_int_0x1c
movw %es, .Lp_orig_int_0x1c+2
movw $0x251c, %ax
movw $.Lour_int_0x1c, %dx
int $0x21
popw %es
RET_ (0)
#else
pushw %es
pushw %di
pushw %ds
popw %es
xorw %cx, %cx
pushw %cx
pushw %cx
subw $0x32-4, %sp
movw %sp, %di
movb $0x34, 0x1d(%di)
mov $0x0300, %ax
movw $0x0021, %bx
int $0x31
movw 0x10(%di), %ax
movw %ax, .Lp_indos
movw 0x22(%di), %bx
addw $0x32, %sp
popw %di
popw %es
movw $0x0002, %ax
int $0x31
movw %ax, .Lp_indos+2
movw $0x0204, %ax
movb $0x1c, %bl
int $0x31
/*
* FIXME: this currently assumes that the original int $0x1c vector
* offset fits into 16 bits.
*/
movw %dx, .Lp_orig_int_0x1c
movw %cx, .Lp_orig_int_0x1c+2
incw %ax
movw $.Lour_int_0x1c, %dx
movw %cs, %cx
callw *__dosx_dpmi16_shim
RET_ (0)
#endif
.Ldtor_timesr:
#ifndef __IA16_FEATURE_DOSX
pushw %es
/*
* If the program (or some other program) had also added its own
* hook for int $0x1c, then do nothing. Otherwise, undo our hook.
*/
movw $0x351c, %ax
int $0x21
cmp $.Lour_int_0x1c, %bx
jnz 0f
movw %es, %ax
movw %ds, %dx
cmpw %ax, %dx
jnz 0f
pushw %ds
ldsw .Lp_orig_int_0x1c, %dx
movw $0x251c, %ax
int $0x21
popw %ds
0: popw %es
RET_ (0)
#else
movw $0x0204, %ax
mov $0x1c, %bl
int $0x31
cmp $.Lour_int_0x1c, %dx
jnz 0f
movw %ds, %dx
cmpw %dx, %cx
jnz 0f
movw .Lp_orig_int_0x1c, %dx
movw .Lp_orig_int_0x1c+2, %cx
incw %ax
int $0x31
0: RET_ (0)
#endif
.global _times_r
_times_r:
ENTER_BX_(4)
MOV_ARG2W_BX_(%bx)
#ifndef __IA16_FEATURE_DOSX
movw %es, %cx
/* Fill ->tms_utime. */
lesw .Luser_counter+2, %dx
movw %dx, (%bx)
movw %es, 2(%bx)
/* Fill ->tms_stime. */
lesw .Lsystem_counter+2, %ax
movw %ax, 4(%bx)
movw %es, 6(%bx)
movw %cx, %es
#else
cli
/* Fill ->tms_utime. */
movw .Luser_counter+2, %dx
movw .Luser_counter+4, %cx
movw %dx, (%bx)
movw %cx, 2(%bx)
/* Fill ->tms_stime. */
movw .Lsystem_counter+2, %ax
movw .Lsystem_counter+4, %cx
movw %ax, 4(%bx)
movw %cx, 6(%bx)
sti
#endif
/* Zero ->tms_cutime and ->tms_cstime for now... */
xorw %cx, %cx
movw %cx, 8(%bx)
movw %cx, 10(%bx)
movw %cx, 12(%bx)
movw %cx, 14(%bx)
/* Add up ->tms_utime and ->tms_stime for the return value. */
addw %dx, %ax
movw 6(%bx), %dx
adcw 2(%bx), %dx
RET_(4)
.section .data, "aw"
.Luser_counter:
.hword -19663, 0, 0
.Lsystem_counter:
.hword -19663, 0, 0
#ifdef __IA16_FEATURE_DOSX
.section .text, "ax"
#endif
.Lour_int_0x1c:
pushw %ax
pushw %ax
pushfw
pushw %ds
pushw %es
pushw %ax
pushw %bx
#ifndef __IA16_FEATURE_DOSX
movw %cs, %bx
movw %bx, %ds
#else
movw %cs:__ia16_near_data_segment, %ds
#endif
movw %sp, %bx
movw .Lp_orig_int_0x1c, %ax
movw %ax, %ss:10(%bx)
movw .Lp_orig_int_0x1c+2, %ax
movw %ax, %ss:12(%bx)
lesw .Lp_indos, %bx
cmpb $0, %es:(%bx)
movw $.Luser_counter, %bx
jnz 2f
0: addw $(_CLOCKS_PER_SEC_ * 1080 % 19663), (%bx)
jnc 1f
subw $19663, (%bx) /* this sets the carry flag */
1: adcw $(_CLOCKS_PER_SEC_ * 1080 / 19663), 2(%bx)
adcw $(_CLOCKS_PER_SEC_ * 1080 / 19663) >> 16, 4(%bx)
popw %bx
popw %ax
popw %es
popw %ds
popfw
lretw
2: movw $.Lsystem_counter, %bx
jmp 0b
.balign 2
.section .ctors.65535
.balign 2
TEXT_PTR_ (.Lctor_timesr)
.section .dtors.65535
.balign 2
TEXT_PTR_ (.Ldtor_timesr)
.lcomm .Lp_orig_int_0x1c, 4
.lcomm .Lp_indos, 4
|
stsp/newlib-ia16
| 8,952
|
libgloss/ia16/dos-models-crt0.S
|
/*
* Startup code for
* * a "tiny" model MS-DOS .com file with combined text and data segment,
* * a "small" model MS-DOS .exe file with one text segment and one separate
* data segment, or
* * a "medium" model MS-DOS .exe file with multiple text segments and one
* data segment.
*/
#if !defined TINY && !defined SMALL && !defined MEDIUM
# error "no memory model defined -- please use -DTINY, -DSMALL or -DMEDIUM"
#endif
#if defined TINY && defined DOSX
# error "tiny model in DOS extender mode not supported"
#endif
#if !defined TINY && defined TSR
# error "non-tiny model TSR not supported"
#endif
#ifdef DOSX
.arch i286
/*
* Assume MS-DOS 3 or above if running under a DOS extender. The CauseWay
* DOS extender will not even start this code, if it finds itself running
* under MS-DOS < 3.01.
*/
# define DOS3P
#else
.arch i8086
#endif
.code16
#include "call-cvt.h"
.global _start
.section .startupA, "ax"
_start:
#ifdef TSR
.section .startupB, "ax"
jmp __stext_nokeep_load
#endif
.section .startupC, "ax"
# Get the MS-DOS version number & see if it is 2 or above.
#ifndef DOS3P
movb $0x30, %ah
int $0x21
subb $2, %al
cbtw
# Set bp to zero iff the MS-DOS version is 2.x. DOS 3+ gives us the
# program's name in the environment segment, but DOS 2.x does not.
xchgw %ax, %bp
# At this point, the flags should contain the result of comparing the
# DOS major version number with 2. dos-mtv1.S & dos-mxv1.S make use
# of this.
#endif
.section .startupD, "ax"
# For a .com file, resize the program's memory control block to
# cover only the near code and data segments. Abort on any failure.
#
# .exe files that are meant to fail properly under MS-DOS 1.x will
# also need to do this, but this is handled by dos-mxv1.S.
#
# TODO: for non-TSRs, maybe allow the MCB to be less than 64 KiB
# under certain conditions --- e.g. if it is enough for BSS and
# stack and perhaps a user-specified heap space.
#ifdef TINY
# ifdef TSR
movw $__entry_stack_end_minimum, %ax
cmpw %ax, %sp
jb .Lno_room
xchgw %ax, %sp
# endif
movb $0x4a, %ah
movw $__msdos_initial_alloc_paras, %bx
int $0x21
jnc .Lmcb_ok
.Lno_room:
movw $.Lno_room_msg, %dx
.global __msdos_crt_bail
__msdos_crt_bail:
movb $9, %ah
int $0x21
movb $-1, %al
jmp .Lexit
.pushsection .msdos_init_rodata, "a"
.Lno_room_msg:
.ascii "No room$"
.balign 2
.popsection
.Lmcb_ok:
#endif
#ifndef TINY
pushw %ss
popw %es
#endif
#ifdef TSR
# If this is a TSR, copy the transient code & data after .startupD
# from their load address (LMA) to their runtime address (VMA).
movw $__edata_nokeep_load-2, %si
movw $__edata_nokeep-2, %di
movw $__lnokeep_to_copy2, %cx
std
rep movsw
# We are still running our startup code at the LMA. The subsequent
# code has been copied to the VMA; jump there. 0xe9 is a near
# relative `jmp'.
.byte 0xe9
.word __text_nokeep_leap
# (This label is used by the linker script.)
.global __stext_nokeep_to_copy
__stext_nokeep_to_copy:
# OK, we are now running at the VMA. Switch to the transient stack.
movw $__stack_end_nokeep, %sp
#endif
# Clear the BSS area(s).
xorw %ax, %ax
#ifndef TSR
movw $__sbss, %di
movw $__lbss, %cx
cld
rep stosw
#else
movw $__sbss_keep, %di
movw $__lbss_keep2, %cx
cld
rep stosw
movw $__sbss_nokeep, %di
movw $__lbss_nokeep2, %cx
rep stosw
#endif
#ifdef DOSX
# Make %ss an expand-down descriptor, and limit it. Use the area
# just after BSS (which will be the heap/stack area) to temporarily
# hold %ss's descriptor entry.
movw $0x000b, %ax
movw %ss, %bx
# ifndef TINY
movw %bx, %es
# endif
movw $__ebss, %di
int $0x31
jc .Lcont_dosx
# ifdef TINY
movw $0x2c-1, (%di)
orb $0x04, 5(%di)
andb $0x30, 6(%di)
# else
movw $__sdata-1, %ss:(%di)
orb $0x04, %ss:5(%di)
andb $0x30, %ss:6(%di)
# endif
movw $0x000c, %ax
int $0x31
# ifdef TINY
pushw %ss
popw %ds
# endif
.Lcont_dosx:
#endif
#ifndef TINY
movw %ds, %bx
#endif
.section .startupE, "ax"
# Handle case where environment segment is null --- this may happen
# for certain versions of MS-DOS & clones if program is started as
# first process (SHELL= or command.com)
xorw %di, %di
xorw %ax, %ax
movw 0x2c(%di), %cx
jcxz .Lnull_env
# Find length of environment + progname
movw %cx, %es
.Lfind_env_end:
movw $-1, %cx
repne scasb
incw %cx
incw %cx
jne .Lfind_env_end
#ifndef DOS3P
testw %bp, %bp
jz .Lno_argv0
#endif
scasw
decw %cx
repne scasb
.Lno_argv0:
# Copy environment + progname
pushw %es
popw %ds
pushw %ss
popw %es
incw %di
andw $-2, %di
subw %di, %sp
movw %di, %cx
movw %sp, %di
xorw %si, %si
rep movsb
# Push pointers to environment + progname
#ifdef TINY
pushw %es
popw %ds
#endif
.byte 0x3d # .. eat up next two instructions in normal
.Lnull_env: # : case (non-null environment segment)
push %ax # :
push %ax # .:
movw %sp, %di
pushw %ax # envp ends with null pointer
.Lpush_env_pointers:
pushw %di
movw $-1, %cx
repne scasb
incw %cx
incw %cx
jne .Lpush_env_pointers
popw %cx # don't include the final empty string
incw %di # advance di to progname (if there is a
incw %di # progname)
#ifndef DOS3P
testw %bp, %bp
#endif
movw %sp, %bp # bp is envp
pushw %ax # argv[argc] = NULL
#ifndef DOS3P
jnz .Largv0
movw %sp, %di # if no progname, use the null byte in the
# null pointer we just pushed as argv[0]
.Largv0:
#endif
pushw %di # argv[0] will be first after reversal
movw %sp, %dx # dx points to last item of argv
# Parse command tail and push argument pointers
movw $0x81, %si
#ifdef TINY
movw %si, %di
#else
movw $.Largv, %di
movw %bx, %ds
#endif
xchgw %ax, %cx
incw %cx # initialize argc in cx to 1 (from ax = 0)
.Lspace:
movw %di, %bx
lodsb
cmpb $' ', %al
je .Lspace
cmpb $9, %al
je .Lspace
cmpb $'\"', %al
je .Linside
cmpb $13, %al
je .Lfinish
.Loutside_check_backslash:
cmpb $'\\', %al
je .Loutside_backslash
.Loutside_other:
stosb
.Loutside:
lodsb
cmpb $' ', %al
je .Lend_argument
cmpb $9, %al
je .Lend_argument
cmpb $'\"', %al
je .Loutside_quote
cmpb $13, %al
jne .Loutside_check_backslash
.Largument_finish:
movb $0, %al
stosb
pushw %bx
incw %cx
.Lfinish:
#ifndef TINY
pushw %ss
popw %ds
#endif
movw %sp, %si
movw %sp, %di
movw %dx, %bx
movw %cx, %dx
shrw $1, %cx
jcxz .Lno_reverse
.Ldo_reverse:
lodsw
xchgw (%bx), %ax
stosw
decw %bx
decw %bx
loop .Ldo_reverse
.Lno_reverse:
#ifndef __IA16_CALLCVT_REGPARMCALL
movw %sp, %ax
pushw %bp # envp
pushw %ax # argv
pushw %dx # argc
#else
pushw %dx
#endif
.section .startupF, "ax"
#ifdef __IA16_CALLCVT_REGPARMCALL
popw %ax # argc
movw %sp, %dx # argv
movw %bp, %cx # envp
#endif
CALL_ (main)
#if defined __IA16_CALLCVT_CDECL
addw $6, %sp
#elif defined __IA16_CALLCVT_STDCALL
# We do not know whether main (...) pops no arguments, two
# arguments (argc, argv), or three arguments (argc, argv, envp). So
# pop nothing here; it should be safe to call exit (.) with extra
# stuff on the stack.
#endif
#ifndef __IA16_CALLCVT_REGPARMCALL
pushw %ax
#endif
CALL_ (exit)
.Linside_backslash_other:
#ifdef TINY
movb $'\\', (%di)
#else
movb $'\\', %es:(%di)
#endif
incw %di
.Linside_other:
stosb
.Linside:
lodsb
cmpb $'\"', %al
je .Lend_argument
cmpb $13, %al
je .Largument_finish
cmpb $'\\', %al
jne .Linside_other
.Linside_backslash:
lodsb
cmpb $'\"', %al
je .Linside_backslash_quote
cmpb $13, %al
je .Lbackslash_finish
cmpb $'\\', %al
jne .Linside_backslash_other
.Linside_backslash_backslash:
movb $'\\', %al
stosb
jmp .Linside_backslash
.Loutside_backslash_backslash:
movb $'\\', %al
stosb
.Loutside_backslash:
lodsb
cmpb $' ', %al
je .Loutside_backslash_space
cmpb $9, %al
je .Loutside_backslash_space
cmpb $'\"', %al
je .Loutside_backslash_quote
cmpb $13, %al
je .Lbackslash_finish
cmpb $'\\', %al
je .Loutside_backslash_backslash
.Loutside_backslash_other:
#ifdef TINY
movb $'\\', (%di)
#else
movb $'\\', %es:(%di)
#endif
incw %di
jmp .Loutside_other
.Loutside_backslash_space:
movb $'\\', %al
stosb
.Lend_argument:
movb $0, %al
stosb
pushw %bx
incw %cx
jmp .Lspace
.Loutside_quote:
mov $0, %al
stosb
pushw %bx
incw %cx
movw %di, %bx
jmp .Linside
.Lbackslash_finish:
movb $'\\', %al
stosb
jmp .Largument_finish
.Linside_backslash_quote:
movb $'\"', %al
jmp .Linside_other
.Loutside_backslash_quote:
movb $'\"', %al
jmp .Loutside_other
.section .exitA, "ax"
.global _exit
_exit:
#ifdef __IA16_CALLCVT_REGPARMCALL
xchgw %ax, %si
#endif
.section .exitB, "ax"
#ifndef __IA16_CALLCVT_REGPARMCALL
popw %bx
# ifdef MEDIUM
popw %bx
# endif
popw %ax
#else
xchgw %ax, %si
#endif
.global __msdos_crt_exit
__msdos_crt_exit:
.Lexit:
movb $0x4c, %ah
int $0x21
#ifndef TINY
# For non-tiny memory models, we need to copy the command line
# arguments out to the data segment, rather than modify them in
# place in DOS's PSP --- since the PSP is outside the data segment.
.lcomm .Largv, 128
#endif
|
stsp/newlib-ia16
| 1,308
|
libgloss/ia16/dos-mti1.S
|
/*
* Copyright (c) 2019--2021 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* Implementation of -mhandle-non-i286 for the tiny memory model. This works
* in conjunction with libck186.a.
*/
.arch i8086, nojumps
.code16
.section .msdos_init.handle_non_i286, "ax"
/*
* Do a quick check that we are indeed dealing with a 286+. On
* pre-286's, `pushw %sp' decrements %sp before storing its value,
* while on 286+, `pushw %sp' stores the old value of %sp first.
* (See Hamarsoft's 86BUGS, distributed with RBIL.)
*/
pushw %sp
popw %ax
subw %sp, %ax
movw $1f, %dx
jnz __msdos_crt_bail
.section .msdos_init_rodata, "a"
1: .ascii "No 286+$"
.globl __msdos_handle_non_i286
.set __msdos_handle_non_i286, 1
|
stsp/newlib-ia16
| 1,616
|
libgloss/ia16/dx-dpmi16.S
|
/*
* Copyright (c) 2023 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <sys/syslimits.h>
#include "call-cvt.h"
.arch i386
.code16
/*
* For programs that use a DOS extender, check whether we can (or should)
* clear the high halves of certain 32-bit registers when calling certain
* DPMI functions. This is necessary if we are running 16-bit code but as
* a 32-bit DPMI application --- which may happen if the program is compiled
* in "dual mode" (-mdosx32).
*/
#define MIN_TB_SZ (2 * PATH_MAX)
TEXT_ (dx_dpmi16.S.LIBGLOSS)
.Lctor_dpmi16:
movw $0x0400, %ax
int $0x31
cmpb $2, %cl
jz .done
movw $.Ldpmi16_386, __dosx_dpmi16_shim
.done:
RET_ (0)
.Ldpmi16_286:
int $0x31
RET_ (0)
.Ldpmi16_386:
pushl %edx
popw %dx
movzwl %dx, %edx
pushl %edi
popw %di
movzwl %di, %edi
int $0x31
pushw %di
popl %edi
pushw %dx
popl %edx
RET_ (0)
.section .data, "aw"
.balign 2
.global __dosx_dpmi16_shim
__dosx_dpmi16_shim:
TEXT_PTR_ (.Ldpmi16_286)
.section .ctors.65535
.balign 2
TEXT_PTR_ (.Lctor_dpmi16)
|
stsp/newlib-ia16
| 1,400
|
libgloss/ia16/dos-mxi1.S
|
/*
* Copyright (c) 2019--2021 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* Implementation of -mhandle-non-i286 for memory models other than the tiny
* model. This works in conjunction with libck186.a.
*/
.arch i8086, nojumps
.code16
.section .msdos_init.handle_non_i286, "ax"
/*
* Do a quick check that we are indeed dealing with a 286+. On
* pre-286's, `pushw %sp' decrements %sp before storing its value,
* while on 286+, `pushw %sp' stores the old value of %sp first.
* (See Hamarsoft's 86BUGS, distributed with RBIL.)
*/
pushw %sp
popw %ax
subw %sp, %ax
jz 0f
movw $1f, %dx
movb $9, %ah
pushw %ss
popw %ds
int $0x21
movb $-1, %al
jmp __msdos_crt_exit
0:
.section .msdos_init_rodata, "a"
1: .ascii "No 286+$"
.globl __msdos_handle_non_i286
.set __msdos_handle_non_i286, 1
|
stsp/newlib-ia16
| 1,230
|
libgloss/ia16/dos-near-data-segment.S
|
/*
* Copyright (c) 2019--2023 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "call-cvt.h"
.arch i8086, jumps
.code16
.text
.balign 2
.global __ia16_near_data_segment
__ia16_near_data_segment:
#ifndef __IA16_FEATURE_DOSX
SEG_RELOC_ (., 9f)
#endif
.hword 0
#ifdef __IA16_FEATURE_DOSX
.Lctor_near_data_segment:
/* Patch the text segment the hard way... */
movw $0x000a, %ax
movw %cs, %bx
int $0x31
jc 8f
movw %ax, %ds
movw %ss, __ia16_near_data_segment
xchgw %ax, %bx
pushw %ss
popw %ds
movw $0x0001, %ax
int $0x31
8:
ret
.section .ctors.65535
.balign 2
.hword .Lctor_near_data_segment
#endif
.section .data, "aw"
9:
|
stsp/newlib-ia16
| 1,837
|
libgloss/ia16/dos-dbcs-weaks.S
|
/*
* Copyright (c) 2021--2022 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "call-cvt.h"
.arch i8086, jumps
.code16
.section .msdos_init.dbcs, "ax"
/*
* At this point %bp should contain 0 iff we are running under MS-DOS
* 2.x.
*
* According to Ralf Brown's Interrupt List, int 0x21 with %ax =
* 0x6600 returns with CF set on error under DOS 2.x, but on DOS 3+
* indicates an error by setting %al = 0xff.
*/
testw %bp, %bp
jnz 0f
incb .Ldos2
0:
TEXT_ (dos_dbcs_weaks.S.LIBGLOSS)
/*
* Return a far pointer to the currently active double-byte character set
* (DBCS) lead byte table. If there is no lead byte table or the table is
* empty, return 0:0.
*
* The routine name _dos_get_dbcs_lead_table () comes from Open Watcom's
* library internal interfaces.
*/
.weak _dos_get_dbcs_lead_table
_dos_get_dbcs_lead_table:
pushw %bp
pushw %si
pushw %di
pushw %ds
pushw %es
movw $0x6300, %ax
movw $-1, %si
testb .Ldos2, %ah
jnz 18f
int $0x21
11:
incw %si
jz 19f
decw %si
testb %al, %al
jnz 19f
cmpb %al, (%si)
jz 19f
xchgw %ax, %si
movw %ds, %dx
12:
popw %es
popw %ds
popw %di
popw %si
popw %bp
RET_ (0)
18:
stc
int $0x21
sbbb %al, %al
jmp 11b
19:
xorw %ax, %ax
cwtd
jmp 12b
.lcomm .Ldos2, 1
|
stsp/newlib-ia16
| 3,126
|
libgloss/ia16/dos-uname-impl.S
|
/* dos-uname-impl.S internal implementation bits for uname
*
* Copyright (c) 2021 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "call-cvt.h"
#include "hw.h"
.arch i8086,jumps
.code16
.att_syntax prefix
TEXT_ (ia16_get_hw_cpu.S.LIBGLOSS)
.global __ia16_get_hw_cpu
__ia16_get_hw_cpu:
#if defined __IA16_FEATURE_PROTECTED_MODE
/*
* If we are already running under DPMI, then the CPU is obviously
* a 286 or above.
*/
#else
xorw %ax, %ax
/*
* Detect an NEC V20 or V30. The opcode 0xd6 is `setalc'/`salc' on
* Intel CPUs, but an alias of `xlat' on NEC (according to 86bugs.lst
* in Ralf Brown's Interrupt List).
*/
pushw %ax
movw %sp, %bx
stc
.byte 0xd6
popw %bx /* %bx := 0, used below */
cmpb $-1, %al
jnz .v20
/*
* Try to tell between an 8086/186 & a 286+: `pushw %sp' on 286+
* stores the %sp value before decrementing %sp, while on 8086 & 186
* it does the opposite.
*/
pushw %sp
popw %ax
cmpw %ax, %sp
jz .i286
# if ! defined _M_IX86 || _M_IX86 - 0 < 100
/*
* Try to tell between an 8086 & a 186, while avoiding the use of
* invalid instructions. Use the fact that a word write at offset
* 0xffff in a segment wraps around on an 8086 but not on a 186
* (www.rcollins.org/ddj/Nov96/Nov96.html). We frob a byte that is
* just above our current stack top.
*/
movw %ss, %ax
movw %sp, %dx
decw %dx
movb $4, %cl
shrw %cl, %dx
addw %dx, %ax
movw %ds, %ax
pushfw
cli
movw -1(%bx), %dx /* %bx = 0 from above */
decb (%bx)
movw -1(%bx), %ax
popfw
pushw %ss
popw %ds
cmpw %dx, %ax
jz .i186
movb $HW_I86, %al
.byte 0x3d
.i186:
# endif
movb $HW_I186, %al
.byte 0x3d
.v20:
movb $HW_V20, %al
.byte 0x3d
.i286:
#endif
movb $HW_I286, %al
cbtw
RET_ (0)
.section .text
.global __msdos_get_kern_ver_str
__msdos_get_kern_ver_str:
pushw %es
pushw %si
pushw %di
xchgw %ax, %di
movw %dx, %cx
jcxz .error
decw %cx
jcxz .error
/*
* Call int 0x21, %ax = 0x33ff, with different values of %dx, to
* test if this syscall is actually supported.
*/
movw $0x33ff, %ax
cwtd
clc
int $0x21
jc .error
testw %dx, %dx
jnz .ok
movw $0x33ff, %ax
movw %ax, %dx
clc
int $0x21
jc .error
testw %dx, %dx
jnz .error
.ok:
pushw %ss
popw %es
movw %dx, %ds
xchgw %ax, %si
.copy:
lodsb
stosb
testb %al, %al
loopnz .copy
/*
* Make sure the output string is 0-terminated. At the same time
* set %ax := 0 for the return value.
*/
xorw %ax, %ax
stosb
pushw %ss
popw %ds
.done:
popw %di
popw %si
popw %es
RET_ (0)
.error:
movw $-1, %ax
jmp .done
|
stsp/newlib-ia16
| 2,046
|
libgloss/ia16/dx-tb.S
|
/*
* Copyright (c) 2022 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <sys/syslimits.h>
#include "call-cvt.h"
.arch i386
.code16
/*
* For programs that use a DOS extender, set up a "transfer buffer" in base
* memory for routines that need it, to allow them to communicate with real
* or V86 mode interrupt handlers. If we have a transfer buffer set up by
* the CauseWay DOS extender, then use it.
*
* This transfer buffer is guaranteed to be at least 2 * PATH_MAX bytes in
* size.
*/
#define MIN_TB_SZ (2 * PATH_MAX)
TEXT_ (dx_tb.S.LIBGLOSS)
.Lctor_dosx_tb:
movw $0xff25, %ax
xorw %bx, %bx
stc
int $0x31
jc 5f
testw %bx, %bx
jz 5f
cmpl $0xfff0, %ecx /* CauseWay APIs work, assume i386 */
ja 0f
movw $0xfff0, %cx
0:
cmpw $(MIN_TB_SZ), %cx
jb 5f
movw %bx, __dosx_tb_rm_seg
movw %dx, __dosx_tb_pm_sel
movw %cx, __dosx_tb_sz
RET_ (0)
5:
movw $0x0100, %ax
movw $(MIN_TB_SZ + 15) >> 4, %bx
int $0x31
jc 9f
movw %ax, __dosx_tb_rm_seg
movw %dx, __dosx_tb_pm_sel
incb __dosx_tb_to_free
RET_ (0)
9:
CALL_ (abort)
.Ldtor_dosx_tb:
testb $1, __dosx_tb_to_free
jz 9f
movw __dosx_tb_pm_sel, %dx
movw $0x0101, %ax
int $0x31
9:
RET_ (0)
.section .data, "wa"
.global __dosx_tb_sz
__dosx_tb_sz:
.hword MIN_TB_SZ
.section .ctors.65535
.balign 2
TEXT_PTR_ (.Lctor_dosx_tb)
.section .dtors.65535
.balign 2
TEXT_PTR_ (.Ldtor_dosx_tb)
.comm __dosx_tb_rm_seg, 2
.comm __dosx_tb_pm_sel, 2
.lcomm __dosx_tb_to_free, 1
|
stsp/newlib-ia16
| 1,359
|
libgloss/ia16/dos-mxi0.S
|
/*
* Copyright (c) 2019--2021 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* Implementation of -mhandle-non-i186 for memory models other than the tiny
* model. This works in conjunction with libck086.a.
*/
.arch i8086, nojumps
.code16
.section .msdos_init.handle_non_i186, "ax"
/*
* Do a quick check that we are indeed dealing with a 186+.
*
* 0x6a is `pushw' on 186+, and as alias for 0x7a (`jpe') on the
* 8086 (www.os2museum.com/wp/undocumented-8086-opcodes/).
*/
movw %sp, %ax
.byte 0x6a, 0x00
subw %sp, %ax
jnz 0f
movw $1f, %dx
movb $9, %ah
pushw %ss
popw %ds
int $0x21
movb $-1, %al
jmp __msdos_crt_exit
0:
popw %ax
.section .msdos_init_rodata, "a"
1: .ascii "No 186+$"
.globl __msdos_handle_non_i186
.set __msdos_handle_non_i186, 1
|
stsp/newlib-ia16
| 1,268
|
libgloss/ia16/dos-mti0.S
|
/*
* Copyright (c) 2019--2021 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* Implementation of -mhandle-non-i186 for the tiny memory model. This works
* in conjunction with libck086.a.
*/
.arch i8086, nojumps
.code16
.section .msdos_init.handle_non_i186, "ax"
/*
* Do a quick check that we are indeed dealing with a 186+.
*
* 0x6a is `pushw' on 186+, and as alias for 0x7a (`jpe') on the
* 8086 (www.os2museum.com/wp/undocumented-8086-opcodes/).
*/
movw %sp, %ax
.byte 0x6a, 0x00
subw %sp, %ax
movw $1f, %dx
jz __msdos_crt_bail
popw %ax
.section .msdos_init_rodata, "a"
1: .ascii "No 186+$"
.globl __msdos_handle_non_i186
.set __msdos_handle_non_i186, 1
|
stsp/newlib-ia16
| 1,201
|
libgloss/ia16/dos-mtabort.S
|
/*
* Copyright (c) 2018--2019 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* Implementation of abort () for MS-DOS and the tiny memory model. This
implementation tries to work properly even if %ss is wrong. */
.arch i8086, jumps
.code16
.text
.global abort
abort:
pushfw
cli
popw %cs:abort_stack-2
movw %sp, %cs:abort_stack-4
movw %ss, %cs:abort_stack-6
movw %cs, %sp
movw %sp, %ss
movw $abort_stack-6, %sp
pushw %ds
pushw %es
pushw %cs
pushw %di
pushw %si
pushw %bp
pushw %dx
pushw %cx
pushw %bx
pushw %ax
pushw %ss
popw %ds
cld
sti
call __ia16_abort_impl
.bss
.skip 128
abort_stack:
|
stsp/newlib-ia16
| 1,171
|
libgloss/ia16/dos-mtv1.S
|
/*
* Copyright (c) 2019 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* Implementation of -mmsdos-handle-v1 for the tiny memory model. This works
* in conjunction with libdosv1.a.
*/
.arch i8086, jumps
.code16
.section .msdos_init, "ax"
/*
* Exit immediately if the MS-DOS version is less than 2. At
* this point the flags should contain the result of comparing the
* DOS major version number with 2.
*/
jnb 0f
movw $1f, %dx
movb $9, %ah
int $0x21
ret
0:
.section .msdos_init_rodata, "a"
1: .ascii "Bad DOS$"
.globl __msdos_handle_v1
.set __msdos_handle_v1, 2
|
stsp/newlib-ia16
| 1,120
|
libgloss/ia16/dos-getpid.S
|
/*
* Copyright (c) 2022 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "call-cvt.h"
.arch i8086,jumps
.code16
.att_syntax prefix
/*
* Get the current process identifier. For MS-DOS, use the Program Segment
* Prefix (PSP) segment as the PID, unless the system supports an actual
* `getpid' syscall, e.g. European MS-DOS 4.0.
*
* Note that pid_t may be a 32-bit type.
*/
TEXT_ (dos_getpid.S.LIBGLOSS)
.global getpid
getpid:
movb $0x87, %ah
stc
int $0x21
jnc .eur_dos
movw _psp, %ax
.eur_dos:
xorw %dx, %dx
RET_ (0)
|
stsp/newlib-ia16
| 1,281
|
libgloss/ia16/dx-abort.S
|
/*
* Copyright (c) 2019--2023 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* Implementation of abort () for MS-DOS and either the tiny or small memory
model. This implementation tries to work properly even if %ss is wrong,
and even when running under DPMI. */
.arch i8086, jumps
.code16
.text
.global abort
abort:
pushfw
cli
pushw %ds
movw %cs:__ia16_near_data_segment, %ds
popw abort_stack-8
popw abort_stack-2
movw %sp, abort_stack-4
movw %ss, abort_stack-6
movw %ds, %sp
movw %sp, %ss
movw $abort_stack-8, %sp
pushw %es
pushw %cs
pushw %di
pushw %si
pushw %bp
pushw %dx
pushw %cx
pushw %bx
pushw %ax
cld
sti
call __ia16_abort_impl
.bss
.skip 128
abort_stack:
|
stsp/newlib-ia16
| 1,598
|
libgloss/ia16/dos-mxv1.S
|
/*
* Copyright (c) 2019 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* Implementation of -mmsdos-handle-v1 for the memory models other than the
* tiny model. This works in conjunction with libdosv1.a.
*/
.arch i8086, jumps
.code16
.section .msdos_init, "ax"
/*
* At this point the flags should contain the result of comparing the
* DOS major version number with 2.
*
* If the MS-DOS is too old (< 2), return to the `int $0x20' command
* at the PSP start --- we cannot just say `int $0x20' here, as %cs
* is wrong.
*/
jnb 0f
movb $9, %ah
cwtd
pushw %es
pushw %dx
movw $1f, %dx
pushw %ss
popw %ds
int $0x21
lretw
0:
/*
* If -mmsdos-handle-v1 is on, then the .exe header will be set to
* allocate the largest possible memory block to our program (see
* dos-mx.ld.in). Shrink the memory block.
*/
movb $0x4a, %ah
movw $__msdos_initial_alloc_paras, %bx
int $0x21
.section .msdos_init_rodata, "a"
1: .ascii "Bad DOS$"
.globl __msdos_handle_v1
.set __msdos_handle_v1, 2
|
stsp/newlib-ia16
| 1,248
|
libgloss/ia16/dos-dbcs.S
|
/*
* Copyright (c) 2021 TK Chia
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "call-cvt.h"
.arch i8086, jumps
.code16
TEXT_ (dos_dbcs.S.LIBGLOSS)
/*
* Given a character C and a lead byte table pointer, say whether C is a
* DBCS lead byte.
*/
.global __msdos_dbcs_lead_byte_p
__msdos_dbcs_lead_byte_p:
ENTER_BX_ (6)
MOV_ARG2W_BX_ (%dx)
MOV_ARG4W_BX_ (%cx)
MOV_ARG0B_BX_ (%al)
movw %dx, %bx
orw %cx, %bx
jnz 20f
xchgw %ax, %dx
RET_ (6)
20:
pushw %es
pushw %si
movw %dx, %si
movw %cx, %es
xchgw %ax, %cx
21:
lodsw %es:(%si)
testb %al, %al
jz 29f
cmpb %al, %cl
jb 21b
cmpb %ah, %cl
ja 21b
movb $1, %al
29:
cbtw
popw %si
popw %es
RET_ (6)
|
stsp/newlib-ia16
| 13,997
|
libgloss/mt/startup-16-002.S
|
/*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
*
*/
.section .startup, "a", @progbits
.global __boot_start
__boot_start:
_INTERRUPT_VECTOR_TABLE:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; The illegal instruction trap is not implemented.
_RESERVED1_IVEC:
jmp _RESERVED1_IVEC ; Vector for illegal instruction
or r0,r0,r0
jmp _OVFIVEC ; Vector for overflow exception
or r0,r0,r0
_RESERVED2_IVEC:
jmp _RESERVED2_IVEC
or r0,r0,r0
_RESERVED3_IVEC:
jmp _RESERVED3_IVEC
or r0,r0,r0
_RESERVED4_IVEC:
jmp _RESERVED4_IVEC
or r0,r0,r0
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
; Statically initialized data must be copied from ROM to RAM.
; This is done in the C run-time start-up code (crt0.o).
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x00031C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0 ; SYS_call is handled by simulator here...
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
; Handler for BREAK instruction. This handler triggers the simulator
; to send a SIGTRAP signal to gdb by writing to the I/O register at
; address $40005, setting bit #0 (0x1).
;
; The above address has been changed to 0x000304 and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
ldw r10, sp, #$0
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
; The documentation is lacking in the specification of the Overflow
; Exception generation. The address of the instruction causing the
; overflow is placed into R15 and the overflow exception interrupt
; is triggered. So, to continue execution, return to the address
; of the next instruction (i.e., R15 + one instruction).
_OVFIVEC:
addi r15, r15, #$4
or r0, r0, r0
reti r15
or r0, r0, r0
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
.section .internal_io, "a", @nobits
.fill 256 ; Fill the first page.
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
;.org 0xfff100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_REG
_DEV8_INTERRUPT_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_REG
_DEV9_INTERRUPT_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_REG
_DEV10_INTERRUPT_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_REG
_DEV11_INTERRUPT_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_REG
_DEV12_INTERRUPT_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_REG
_DEV13_INTERRUPT_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_REG
_DEV14_INTERRUPT_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_REG
_DEV15_INTERRUPT_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_REG
_DEV16_INTERRUPT_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_REG
_DEV17_INTERRUPT_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_REG
_DEV18_INTERRUPT_REG:
.word 0x00000000
; 128 bytes minus ten registers (four bytes per register)
.fill (128 - 19 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
; 128 bytes minus one register (four bytes per register)
.fill (128 - 1 * 4)
;.org 0xfff200
; MorphoSys Decoder Registers
.global _MS_DEC_CIRC_BUFF_SEL_REG
_MS_DEC_CIRC_BUFF_SEL_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERM_REG
_MS_DEC_CUSTOM_PERM_REG:
.word 0x00000000
.global _MS_DEC_CTXT_BASE_REG
_MS_DEC_CTXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TBL_REG
_MS_DEC_LOOKUP_TBL_REG:
.word 0x00000000
.global _MS_CIRC_BUFF0_END_REG
_MS_CIRC_BUFF0_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF0_SIZE_REG
_MS_CIRC_BUFF0_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK0_END_REG
_MS_DATA_BLK0_END_REG:
.word 0x00000000
.global _MS_DATA_BLK0_SIZE_REG
_MS_DATA_BLK0_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF1_END_REG
_MS_CIRC_BUFF1_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF1_SIZE_REG
_MS_CIRC_BUFF1_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK1_END_REG
_MS_DATA_BLK1_END_REG:
.word 0x00000000
.global _MS_DATA_BLK1_SIZE_REG
_MS_DATA_BLK1_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF2_END_REG
_MS_CIRC_BUFF2_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF2_SIZE_REG
_MS_CIRC_BUFF2_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK2_END_REG
_MS_DATA_BLK2_END_REG:
.word 0x00000000
.global _MS_DATA_BLK2_SIZE_REG
_MS_DATA_BLK2_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF3_END_REG
_MS_CIRC_BUFF3_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF3_SIZE_REG
_MS_CIRC_BUFF3_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK3_END_REG
_MS_DATA_BLK3_END_REG:
.word 0x00000000
.global _MS_DATA_BLK3_SIZE_REG
_MS_DATA_BLK3_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF4_END_REG
_MS_CIRC_BUFF4_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF4_SIZE_REG
_MS_CIRC_BUFF4_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK4_END_REG
_MS_DATA_BLK4_END_REG:
.word 0x00000000
.global _MS_DATA_BLK4_SIZE_REG
_MS_DATA_BLK4_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF5_END_REG
_MS_CIRC_BUFF5_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF5_SIZE_REG
_MS_CIRC_BUFF5_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK5_END_REG
_MS_DATA_BLK5_END_REG:
.word 0x00000000
.global _MS_DATA_BLK5_SIZE_REG
_MS_DATA_BLK5_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF6_END_REG
_MS_CIRC_BUFF6_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF6_SIZE_REG
_MS_CIRC_BUFF6_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK6_END_REG
_MS_DATA_BLK6_END_REG:
.word 0x00000000
.global _MS_DATA_BLK6_SIZE_REG
_MS_DATA_BLK6_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF7_END_REG
_MS_CIRC_BUFF7_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF7_SIZE_REG
_MS_CIRC_BUFF7_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK7_END_REG
_MS_DATA_BLK7_END_REG:
.word 0x00000000
.global _MS_DATA_BLK7_SIZE_REG
_MS_DATA_BLK7_SIZE_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC0_REG
_MS_DEC_AUTO_INC0_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC1_REG
_MS_DEC_AUTO_INC1_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC2_REG
_MS_DEC_AUTO_INC2_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC3_REG
_MS_DEC_AUTO_INC3_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC4_REG
_MS_DEC_AUTO_INC4_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC5_REG
_MS_DEC_AUTO_INC5_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC6_REG
_MS_DEC_AUTO_INC6_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC7_REG
_MS_DEC_AUTO_INC7_REG:
.word 0x00000000
; 256 bytes minus forty-five registers (four bytes per register)
.fill (256 - 45 * 4)
;.org 0xfff300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
; There are five reserved registers.
.fill (5 * 4)
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
;.org 0xfff400
; Sequence Generator Registers
.global _SEQ_GEN_CTRL_REG
_SEQ_GEN_CTRL_REG:
.word 0x00000000
.global _SEQ_GEN_MASK_REGS
_SEQ_GEN_MASK_REGS:
; The mask registers consume two pages (less one control register).
; 512 bytes minus one register (four bytes per register).
.fill (256 + 256 - 1 * 4)
;.org 0xfff600
; Timer Registers
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER3_VAL_REG
_TIMER3_VAL_REG:
.word 0x00000000
; 256 bytes minus four registers (four bytes per register)
.fill (256 - 4 * 4)
;.org 0xfff700
; Output Line Control Registers
.global _OUTPUT0_CTRL
_OUTPUT0_CTRL:
.word 0x00000000
.global _OUTPUT1_CTRL
_OUTPUT1_CTRL:
.word 0x00000000
.global _OUTPUT2_CTRL
_OUTPUT2_CTRL:
.word 0x00000000
.global _OUTPUT3_CTRL
_OUTPUT3_CTRL:
.word 0x00000000
.global _OUTPUT4_CTRL
_OUTPUT4_CTRL:
.word 0x00000000
.global _OUTPUT5_CTRL
_OUTPUT5_CTRL:
.word 0x00000000
.global _OUTPUT6_CTRL
_OUTPUT6_CTRL:
.word 0x00000000
.global _OUTPUT7_CTRL
_OUTPUT7_CTRL:
.word 0x00000000
.global _OUTPUT8_CTRL
_OUTPUT8_CTRL:
.word 0x00000000
.global _OUTPUT9_CTRL
_OUTPUT9_CTRL:
.word 0x00000000
.global _OUTPUT10_CTRL
_OUTPUT10_CTRL:
.word 0x00000000
;; 128 bytes minus eleven registers (four bytes per register)
;.fill (128 - 11 * 4)
.global _INPUT0_CTRL
_INPUT0_CTRL:
.word 0x00000000
;; 128 bytes minus one register (four bytes per register)
;.fill (128 - 1 * 4)
; 256 bytes minus twelve registers (four bytes per register)
.fill (256 - 12 * 4)
;.org 0xfff800
; IQ Buffer Registers
.global _IQ_BUFF_CTRL_REG
_IQ_BUFF_CTRL_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER1_REG
_IQ_BUFF_PARAMETER1_REG:
.word 0x00000000
.global _IQ_BUFF_DATA_SIZE1_REG
_IQ_BUFF_DATA_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE1_REG
_IQ_BUFF_TRANSFER_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_ADDR1_REG
_IQ_BUFF_FB_ADDR1_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER2_REG
_IQ_BUFF_PARAMETER2_REG:
.word 0x00000000
.global _IQ_BUFF_DATA_SIZE2_REG
_IQ_BUFF_DATA_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE2_REG
_IQ_BUFF_TRANSFER_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_ADDR2_REG
_IQ_BUFF_FB_ADDR2_REG:
.word 0x00000000
; 256 bytes minus nine registers (four bytes per register)
.fill (256 - 9 * 4)
;.org 0xfff900
; Reserved memory-mapped space.
.fill (0x1000 - 0x900)
|
stsp/newlib-ia16
| 1,289
|
libgloss/mt/crt0.S
|
# Startup Code for the Morpho mt
# Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.section .text
.global _start
_start:
;; Initialise the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the data space
ldui r9, #%hi16(_edata)
addui r9, r9, #%lo16(_edata)
ldui r10, #%hi16(_end)
addui r10, r10, #%lo16(_end)
addi r5, r0, #0
.L0:
stw r5, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .L0
or r0, r0, r0 ; nop
;; Call global and static constructors
ldui r10, #%hi16(_init)
addui r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Setup destructors to be called from exit.
;; (Just in case main never returns....)
ldui r10, #%hi16(atexit)
addui r10, r10, #%lo16(atexit)
ldui r1, #%hi16(_fini)
addui r1, r1, #%lo16(_fini)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Initialise argc, argv and envp to empty
addi r1, r0, #0
addi r2, r0, #0
addi r3, r0, #0
;; Call main
ldui r10, #%hi16(main)
addui r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Jump to exit
ldui r10, #%hi16(exit)
addui r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
|
stsp/newlib-ia16
| 9,014
|
libgloss/mt/startup-64-001.S
|
/*
* $Header$
*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
*
* 26Sep01 (DJK) The memory map is changed and the device interrupts are
* now memory-mapped.
*
* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
* space is now reserved for memory-mapped I/O devices.
* (There is over 2K unused, reserved space in this area.)
*
* 27Jul02 (DJK) Fixed the address for the interrupt mask register. Old
* documentation stated the port address as 0x140, but
* the implementation uses 0x13c.
*
* 30Jul02 (DJK) Added support for printf. This only supports output to
* stderr and stdout. Using the message box interface,
* a (newly defined) message or series of messages is
* passed to the controller to output bytes as text to
* the debug console. These messages are constructed in
* the interrupt handler for the SI instruction.
* With this implementation, the user is unable to
* utilize the message box interface in applications as
* specialized interrupt handlers for the external
* interrupts are necessary.
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
*
*/
.section .startup, "a", @progbits
.global __boot_start
_INTERRUPT_VECTOR_TABLE:
__boot_start:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
.org 0x100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
; 60 bytes minus eight registers (four bytes per register)
.fill (60 - 8 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
; 256 bytes minus sixteen registers (four bytes per register)
.fill (256 - 16 * 4)
.org 0x200
; MorphoSys Decoder Registers
.global _MS_DEC_AUTO_INCREMENT_REG
_MS_DEC_AUTO_INCREMENT_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERMUTATION_REG
_MS_DEC_CUSTOM_PERMUTATION_REG:
.word 0x00000000
.global _MS_DEC_CONTEXT_BASE_REG
_MS_DEC_CONTEXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TABLE_BASE_REG
_MS_DEC_LOOKUP_TABLE_BASE_REG:
.word 0x00000000
.global _MS_CIRCULAR_BUFFER_END_REG
_MS_CIRCULAR_BUFFER_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRCULAR_BUFFER_SIZE_REG
_MS_CIRCULAR_BUFFER_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLOCK_END_REG
_MS_DATA_BLOCK_END_REG:
.word 0x00000000
.global _MS_DATA_BLOCK_SIZE_REG
_MS_DATA_BLOCK_SIZE_REG:
.word 0x00000000
; 256 bytes minus nine registers (four bytes per register)
.fill (256 - 9 * 4)
.org 0x300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED0_REG
_DEBUG_HW_RESERVED0_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED1_REG
_DEBUG_HW_RESERVED1_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED2_REG
_DEBUG_HW_RESERVED2_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED3_REG
_DEBUG_HW_RESERVED3_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED4_REG
_DEBUG_HW_RESERVED4_REG:
.word 0x00000000
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
.org 0x400
; Sequence Generator Registers
_SEQ_GEN_REGS:
.fill 256
.org 0x500
_RESERVED_SEQ_GEN_REGS:
.fill 256
.org 0x600
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER0_CTRL_REG
_TIMER0_CTRL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER1_CTRL_REG
_TIMER1_CTRL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER2_CTRL_REG
_TIMER2_CTRL_REG:
.word 0x00000000
; 256 bytes minus six registers (four bytes per register)
.fill (256 - 6 * 4)
.org 0x700
.global _OUTPUT0_CONTROL
_OUTPUT0_CONTROL:
.word 0x00000000
.global _OUTPUT1_CONTROL
_OUTPUT1_CONTROL:
.word 0x00000000
.global _OUTPUT2_CONTROL
_OUTPUT2_CONTROL:
.word 0x00000000
.global _OUTPUT3_CONTROL
_OUTPUT3_CONTROL:
.word 0x00000000
.global _OUTPUT4_CONTROL
_OUTPUT4_CONTROL:
.word 0x00000000
.global _OUTPUT5_CONTROL
_OUTPUT5_CONTROL:
.word 0x00000000
.global _OUTPUT6_CONTROL
_OUTPUT6_CONTROL:
.word 0x00000000
.global _OUTPUT7_CONTROL
_OUTPUT7_CONTROL:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
.org 0x800
; Reserved memory-mapped space.
.fill (0x1000 - 0x800)
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
; for devices zero through seven.
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed, a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x31C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
;
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
; SYS_call is handled by simulator here...
or r0, r0, r0
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
ldw r10, sp, #$0
subi r15, r15, #$4 ; Backup to address of break
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
|
stsp/newlib-ia16
| 17,327
|
libgloss/mt/startup-ms2.S
|
/*
*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
* 28Apr05 (DJK) Added support for the overflow vector.
*
* XXXXXXX (DJK) Modified for the MS2 target
*
* 09Jan04 (DJK) Modified internal I/O port definitions for the
* MS1-16-003.
*
* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
* space is now reserved for memory-mapped I/O devices.
* (There is over 2K unused, reserved space in this area.)
*
* 26Sep01 (DJK) The memory map is changed and the device interrupts are
* now memory-mapped.
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
*
*/
.section .startup, "a", @progbits
.global __boot_start
__boot_start:
_INTERRUPT_VECTOR_TABLE:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0, r0, r0
jmp _BRKIVEC ; Vector for Break instruction
or r0, r0, r0
; The illegal instruction trap is not implemented.
_RESERVED1_IVEC:
jmp _RESERVED1_IVEC
or r0, r0, r0
jmp _OVFIVEC
or r0, r0, r0
_RESERVED2_IVEC:
jmp _RESERVED2_IVEC
or r0, r0, r0
_RESERVED3_IVEC:
jmp _RESERVED3_IVEC
or r0, r0, r0
_RESERVED4_IVEC:
jmp _RESERVED4_IVEC
or r0, r0, r0
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
; Statically initialized data must be copied from ROM to RAM.
; This is done in the C run-time start-up code (crt0.o).
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x00031C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
; SYS_call is handled by simulator here...
or r0, r0, r0
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
ldw r10, sp, #$0
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
.global _OVFIVEC
_OVFIVEC:
addi r15, r15, #$4
or r0, r0, r0
or r0, r0, r0 ; added 06Sep05
reti r15
or r0, r0, r0
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
.section .internal_io, "a", @nobits
.fill 256 ; Fill the first page.
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
;.org 0xfffff100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_REG
_DEV8_INTERRUPT_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_REG
_DEV9_INTERRUPT_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_REG
_DEV10_INTERRUPT_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_REG
_DEV11_INTERRUPT_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_REG
_DEV12_INTERRUPT_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_REG
_DEV13_INTERRUPT_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_REG
_DEV14_INTERRUPT_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_REG
_DEV15_INTERRUPT_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_REG
_DEV16_INTERRUPT_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_REG
_DEV17_INTERRUPT_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_REG
_DEV18_INTERRUPT_REG:
.word 0x00000000
; 128 bytes minus nineteen registers (four bytes per register)
.fill (128 - 19 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
.global _INTERRUPT_PENDING_REG
_INTERRUPT_PENDING_REG:
.word 0x00000000
; 16 bytes minus two registers (four bytes per register)
.fill (16 - 2 * 4)
.global _DEV0_INTERRUPT_LEVEL_REG
_DEV0_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_LEVEL_REG
_DEV1_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_LEVEL_REG
_DEV2_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_LEVEL_REG
_DEV3_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_LEVEL_REG
_DEV4_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_LEVEL_REG
_DEV5_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_LEVEL_REG
_DEV6_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_LEVEL_REG
_DEV7_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_LEVEL_REG
_DEV8_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_LEVEL_REG
_DEV9_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_LEVEL_REG
_DEV10_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_LEVEL_REG
_DEV11_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_LEVEL_REG
_DEV12_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_LEVEL_REG
_DEV13_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_LEVEL_REG
_DEV14_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_LEVEL_REG
_DEV15_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_LEVEL_REG
_DEV16_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_LEVEL_REG
_DEV17_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_LEVEL_REG
_DEV18_INTERRUPT_LEVEL_REG:
.word 0x00000000
; 128 bytes minus twenty-three registers (four bytes per register)
.fill (128 - 23 * 4)
;.org 0xfffff200
; MorphoSys Decoder Registers
.global _MS_DEC_CIRC_BUFF_SEL_REG
_MS_DEC_CIRC_BUFF_SEL_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERM_REG
_MS_DEC_CUSTOM_PERM_REG:
.word 0x00000000
.global _MS_DEC_CTXT_BASE_REG
_MS_DEC_CTXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TBL_REG
_MS_DEC_LOOKUP_TBL_REG:
.word 0x00000000
.global _MS_CIRC_BUFF0_I_REG
_MS_CIRC_BUFF0_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF0_P_REG
_MS_CIRC_BUFF0_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF0_B_REG
_MS_DATA_BUFF0_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF0_S_REG
_MS_DATA_BUFF0_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF1_I_REG
_MS_CIRC_BUFF1_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF1_P_REG
_MS_CIRC_BUFF1_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF1_B_REG
_MS_DATA_BUFF1_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF1_S_REG
_MS_DATA_BUFF1_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF2_I_REG
_MS_CIRC_BUFF2_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF2_P_REG
_MS_CIRC_BUFF2_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF2_B_REG
_MS_DATA_BUFF2_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF2_S_REG
_MS_DATA_BUFF2_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF3_I_REG
_MS_CIRC_BUFF3_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF3_P_REG
_MS_CIRC_BUFF3_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF3_B_REG
_MS_DATA_BUFF3_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF3_S_REG
_MS_DATA_BUFF3_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF4_I_REG
_MS_CIRC_BUFF4_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF4_P_REG
_MS_CIRC_BUFF4_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF4_B_REG
_MS_DATA_BUFF4_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF4_S_REG
_MS_DATA_BUFF4_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF5_I_REG
_MS_CIRC_BUFF5_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF5_P_REG
_MS_CIRC_BUFF5_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF5_B_REG
_MS_DATA_BUFF5_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF5_S_REG
_MS_DATA_BUFF5_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF6_I_REG
_MS_CIRC_BUFF6_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF6_P_REG
_MS_CIRC_BUFF6_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF6_B_REG
_MS_DATA_BUFF6_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF6_S_REG
_MS_DATA_BUFF6_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF7_I_REG
_MS_CIRC_BUFF7_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF7_P_REG
_MS_CIRC_BUFF7_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF7_B_REG
_MS_DATA_BUFF7_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF7_S_REG
_MS_DATA_BUFF7_S_REG:
.word 0x00000000
.global _MS_OMEGA_PERM1_REG
_MS_OMEGA_PERM1_REG:
.word 0x00000000
.global _MS_WRITE_FB_ADDR_REG
_MS_WRITE_FB_ADDR_REG:
.word 0x00000000
.global _MS_OMEGA_PERM2_REG
_MS_OMEGA_PERM2_REG:
.word 0x00000000
; 256 bytes minus forty registers (four bytes per register)
.fill (256 - 40 * 4)
;.org 0xfffff300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
.global _DEBUG_CRITICAL_REG
_DEBUG_OWNERSHIP_REG:
.word 0x00000000
.global _DEBUG_KERNEL_ID_REG
_DEBUG_KERNEL_ID_REG:
.word 0x00000000
.global _DEBUG_IRQ_STATUS_REG
_DEBUG_IRQ_STATUS_REG:
.word 0x00000000
; There are two reserved registers.
.fill (2 * 4)
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 128 bytes minus eight registers (four bytes per register)
.fill (128 - 8 * 4)
.global _EXTENDED_GP0_REG
_EXTENDED_GP0_REG:
.word 0x00000000
.global _EXTENDED_GP1_REG
_EXTENDED_GP1_REG:
.word 0x00000000
.global _EXTENDED_GP2_REG
_EXTENDED_GP2_REG:
.word 0x00000000
.global _EXTENDED_GP3_REG
_EXTENDED_GP3_REG:
.word 0x00000000
.global _EXTENDED_GP4_REG
_EXTENDED_GP4_REG:
.word 0x00000000
.global _EXTENDED_GP5_REG
_EXTENDED_GP5_REG:
.word 0x00000000
.global _EXTENDED_GP6_REG
_EXTENDED_GP6_REG:
.word 0x00000000
.global _EXTENDED_GP7_REG
_EXTENDED_GP7_REG:
.word 0x00000000
.global _MEM_CTRL_EN_NC_MEM_REG
_MEM_CTRL_EN_NC_MEM_REG:
.word 0x00000000
.global _MEM_CTRL_BASE0_ADDR_REG
_MEM_CTRL_BASE0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK0_ADDR_REG
_MEM_CTRL_MASK0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE1_ADDR_REG
_MEM_CTRL_BASE1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK1_ADDR_REG
_MEM_CTRL_MASK1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE2_ADDR_REG
_MEM_CTRL_BASE2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK2_ADDR_REG
_MEM_CTRL_MASK2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE3_ADDR_REG
_MEM_CTRL_BASE3_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK3_ADDR_REG
_MEM_CTRL_MASK3_ADDR_REG:
.word 0x00000000
; 128 bytes minus seventeen registers (four bytes per register)
.fill (128 - 17 * 4)
; Reserved memory-map space
.fill (256 + 256)
;.org 0xfffff600
; Timer Registers
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER3_VAL_REG
_TIMER3_VAL_REG:
.word 0x00000000
; 256 bytes minus four registers (four bytes per register)
.fill (256 - 4 * 4)
;.org 0xfffff700
; Output Line Control Registers
.global _OUTPUT0_CTRL
_OUTPUT0_CTRL:
.word 0x00000000
.global _OUTPUT1_CTRL
_OUTPUT1_CTRL:
.word 0x00000000
.global _OUTPUT2_CTRL
_OUTPUT2_CTRL:
.word 0x00000000
.global _OUTPUT3_CTRL
_OUTPUT3_CTRL:
.word 0x00000000
.global _OUTPUT4_CTRL
_OUTPUT4_CTRL:
.word 0x00000000
.global _OUTPUT5_CTRL
_OUTPUT5_CTRL:
.word 0x00000000
.global _OUTPUT6_CTRL
_OUTPUT6_CTRL:
.word 0x00000000
; 128 bytes minus seven registers (four bytes per register)
.fill (128 - 7 * 4)
.global _INPUT0_CTRL
_INPUT0_CTRL:
.word 0x00000000
; 128 bytes minus one register (four bytes per register)
.fill (128 - 1 * 4)
;.org 0xfffff800
; IQ Buffer Registers
.global _IQ_BUFF_CTRL_REG
_IQ_BUFF_CTRL_REG:
.word 0x00000000
.global _IQ_BUFF_STATUS_REG
_IQ_BUFF_STATUS_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER1_REG
_IQ_BUFF_PARAMETER1_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE1_REG
_IQ_BUFF_TRANSFER_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE1_REG
_IQ_BUFF_FB_BASE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE1_REG
_IQ_BUFF_FB_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER2_REG
_IQ_BUFF_PARAMETER2_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE2_REG
_IQ_BUFF_TRANSFER_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE2_REG
_IQ_BUFF_FB_BASE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE2_REG
_IQ_BUFF_FB_SIZE2_REG:
.word 0x00000000
; 256 bytes minus ten registers (four bytes per register)
.fill (256 - 10 * 4)
;.org 0xfffff900
; DMA Controller
.global _DMA_CTRL_REG
_DMA_CTRL_REG:
.word 0x00000000
.global _DMA_STATUS_REG
_DMA_STATUS_REG:
.word 0x00000000
.global _DMA_CH0_EADDR_REG
_DMA_CH0_EADDR_REG:
.word 0x00000000
.global _DMA_CH0_IADDR_REG
_DMA_CH0_IADDR_REG:
.word 0x00000000
.global _DMA_CH0_SIZE_REG
_DMA_CH0_SIZE_REG:
.word 0x00000000
.global _DMA_CH1_EADDR_REG
_DMA_CH1_EADDR_REG:
.word 0x00000000
.global _DMA_CH1_IADDR_REG
_DMA_CH1_IADDR_REG:
.word 0x00000000
.global _DMA_CH1_SIZE_REG
_DMA_CH1_SIZE_REG:
.word 0x00000000
.global _DMA_CH2_EADDR_REG
_DMA_CH2_EADDR_REG:
.word 0x00000000
.global _DMA_CH2_IADDR_REG
_DMA_CH2_IADDR_REG:
.word 0x00000000
.global _DMA_CH2_SIZE_REG
_DMA_CH2_SIZE_REG:
.word 0x00000000
.global _DMA_CH3_EADDR_REG
_DMA_CH3_EADDR_REG:
.word 0x00000000
.global _DMA_CH3_IADDR_REG
_DMA_CH3_IADDR_REG:
.word 0x00000000
.global _DMA_CH3_SIZE_REG
_DMA_CH3_SIZE_REG:
.word 0x00000000
; 256 bytes minus fourteen registers (four bytes per register)
.fill (256 - 14 * 4)
;.org 0xfffffa00
; Sequence Generator
.global _SEQ_GEN_CTRL_STATUS_REG
_SEQ_GEN_CTRL_STATUS_REG:
.word 0x00000000
.global _SEQ_GEN_MASK_REGS
_SEQ_GEN_MASK_REGS:
.fill (302 * 4)
.global _SEQ_GEN_SHIFT_REG
_SEQ_GEN_SHIFT_REG:
.word 0x00000000
; 256 bytes minus seven registers (four bytes per register)
.fill (256 - 48 * 4)
; Reserved memory-map space
.fill (0x1000 - 0xf00)
|
stsp/newlib-ia16
| 2,903
|
libgloss/mt/crt0-16-002.S
|
; crt0_2.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
; Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
;
; The authors hereby grant permission to use, copy, modify, distribute,
; and license this software and its documentation for any purpose, provided
; that existing copyright notices are retained in all copies and that this
; notice is included verbatim in any distributions. No written agreement,
; license, or royalty fee is required for any of the authorized uses.
; Modifications to this software may be copyrighted by their authors
; and need not follow the licensing terms described here, provided that
; the new terms are clearly indicated on the first page of each file where
; they apply.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
|
stsp/newlib-ia16
| 2,798
|
libgloss/mt/crt0-ms2.S
|
; crt0.s - Startup code for the ms2. This code initializes the C
; run-time model.
;
;
; Copyright 2001, 2002, 2003, 2004 Morpho Technologies
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Copy data from ROM to SRAM (another on-chip memory)
ldui r9, #%hi16(_sram_data_start)
ori r9, r9, #%lo16(_sram_data_start)
ldui r10, #%hi16(_sram_data_end)
ori r10, r10, #%lo16(_sram_data_end)
ldui r11, #%hi16(_sram_data_vma)
brle r10, r9, .Lnext4
ori r11, r11, #%lo16(_sram_data_vma)
.Lcpy3:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy3
addi r11, r11, #$4
.Lnext4:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
or r0, r0, r0 ; nop, added 06Sep05
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
or r0, r0, r0 ; nop, added 06Sep05
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
or r0, r0, r0 ; nop, added 06Sep05
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
|
stsp/newlib-ia16
| 17,392
|
libgloss/mt/startup-16-003.S
|
/*
* $Header$
*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
* 09Jan04 (DJK) Modified internal I/O port definitions for the
* MS1-16-003.
*
* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
* space is now reserved for memory-mapped I/O devices.
* (There is over 2K unused, reserved space in this area.)
*
* 26Sep01 (DJK) The memory map is changed and the device interrupts are
* now memory-mapped.
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
*
*/
.section .startup, "a", @progbits
.global __boot_start
__boot_start:
_INTERRUPT_VECTOR_TABLE:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; The illegal instruction trap is not implemented.
;jmp _ILLIVEC ; Vector for illegal instruction
or r0,r0,r0
or r0,r0,r0
_RESERVED1_IVEC:
jmp _RESERVED1_IVEC
or r0,r0,r0
_RESERVED2_IVEC:
jmp _RESERVED2_IVEC
or r0,r0,r0
_RESERVED3_IVEC:
jmp _RESERVED3_IVEC
or r0,r0,r0
_RESERVED4_IVEC:
jmp _RESERVED4_IVEC
or r0,r0,r0
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
; Statically initialized data must be copied from ROM to RAM.
; This is done in the C run-time start-up code (crt0.o).
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x00031C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
; SYS_call is handled by simulator here...
or r0, r0, r0
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
ldw r10, sp, #$0
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
.if 0
; Handler for illegal instruction.
.global _ILLIVEC
_ILLIVEC:
reti r15
or r0, r0, r0
.endif
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
.section .internal_io, "a", @nobits
.fill 256 ; Fill the first page.
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
;.org 0xfffff100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_REG
_DEV8_INTERRUPT_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_REG
_DEV9_INTERRUPT_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_REG
_DEV10_INTERRUPT_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_REG
_DEV11_INTERRUPT_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_REG
_DEV12_INTERRUPT_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_REG
_DEV13_INTERRUPT_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_REG
_DEV14_INTERRUPT_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_REG
_DEV15_INTERRUPT_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_REG
_DEV16_INTERRUPT_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_REG
_DEV17_INTERRUPT_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_REG
_DEV18_INTERRUPT_REG:
.word 0x00000000
; 128 bytes minus nineteen registers (four bytes per register)
.fill (128 - 19 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
.global _INTERRUPT_PENDING_REG
_INTERRUPT_PENDING_REG:
.word 0x00000000
; 16 bytes minus two registers (four bytes per register)
.fill (16 - 2 * 4)
.global _DEV0_INTERRUPT_LEVEL_REG
_DEV0_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_LEVEL_REG
_DEV1_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_LEVEL_REG
_DEV2_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_LEVEL_REG
_DEV3_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_LEVEL_REG
_DEV4_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_LEVEL_REG
_DEV5_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_LEVEL_REG
_DEV6_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_LEVEL_REG
_DEV7_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_LEVEL_REG
_DEV8_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_LEVEL_REG
_DEV9_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_LEVEL_REG
_DEV10_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_LEVEL_REG
_DEV11_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_LEVEL_REG
_DEV12_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_LEVEL_REG
_DEV13_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_LEVEL_REG
_DEV14_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_LEVEL_REG
_DEV15_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_LEVEL_REG
_DEV16_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_LEVEL_REG
_DEV17_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_LEVEL_REG
_DEV18_INTERRUPT_LEVEL_REG:
.word 0x00000000
; 128 bytes minus twenty-three registers (four bytes per register)
.fill (128 - 23 * 4)
;.org 0xfffff200
; MorphoSys Decoder Registers
.global _MS_DEC_CIRC_BUFF_SEL_REG
_MS_DEC_CIRC_BUFF_SEL_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERM_REG
_MS_DEC_CUSTOM_PERM_REG:
.word 0x00000000
.global _MS_DEC_CTXT_BASE_REG
_MS_DEC_CTXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TBL_REG
_MS_DEC_LOOKUP_TBL_REG:
.word 0x00000000
.global _MS_CIRC_BUFF0_I_REG
_MS_CIRC_BUFF0_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF0_P_REG
_MS_CIRC_BUFF0_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF0_B_REG
_MS_DATA_BUFF0_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF0_S_REG
_MS_DATA_BUFF0_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF1_I_REG
_MS_CIRC_BUFF1_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF1_P_REG
_MS_CIRC_BUFF1_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF1_B_REG
_MS_DATA_BUFF1_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF1_S_REG
_MS_DATA_BUFF1_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF2_I_REG
_MS_CIRC_BUFF2_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF2_P_REG
_MS_CIRC_BUFF2_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF2_B_REG
_MS_DATA_BUFF2_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF2_S_REG
_MS_DATA_BUFF2_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF3_I_REG
_MS_CIRC_BUFF3_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF3_P_REG
_MS_CIRC_BUFF3_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF3_B_REG
_MS_DATA_BUFF3_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF3_S_REG
_MS_DATA_BUFF3_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF4_I_REG
_MS_CIRC_BUFF4_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF4_P_REG
_MS_CIRC_BUFF4_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF4_B_REG
_MS_DATA_BUFF4_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF4_S_REG
_MS_DATA_BUFF4_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF5_I_REG
_MS_CIRC_BUFF5_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF5_P_REG
_MS_CIRC_BUFF5_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF5_B_REG
_MS_DATA_BUFF5_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF5_S_REG
_MS_DATA_BUFF5_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF6_I_REG
_MS_CIRC_BUFF6_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF6_P_REG
_MS_CIRC_BUFF6_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF6_B_REG
_MS_DATA_BUFF6_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF6_S_REG
_MS_DATA_BUFF6_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF7_I_REG
_MS_CIRC_BUFF7_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF7_P_REG
_MS_CIRC_BUFF7_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF7_B_REG
_MS_DATA_BUFF7_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF7_S_REG
_MS_DATA_BUFF7_S_REG:
.word 0x00000000
.global _MS_OMEGA_PERM1_REG
_MS_OMEGA_PERM1_REG:
.word 0x00000000
.global _MS_WRITE_FB_ADDR_REG
_MS_WRITE_FB_ADDR_REG:
.word 0x00000000
.global _MS_OMEGA_PERM2_REG
_MS_OMEGA_PERM2_REG:
.word 0x00000000
; 256 bytes minus forty registers (four bytes per register)
.fill (256 - 40 * 4)
;.org 0xfffff300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
.global _DEBUG_CRITICAL_REG
_DEBUG_OWNERSHIP_REG:
.word 0x00000000
.global _DEBUG_KERNEL_ID_REG
_DEBUG_KERNEL_ID_REG:
.word 0x00000000
.global _DEBUG_IRQ_STATUS_REG
_DEBUG_IRQ_STATUS_REG:
.word 0x00000000
; There are two reserved registers.
.fill (2 * 4)
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 128 bytes minus eight registers (four bytes per register)
.fill (128 - 8 * 4)
.global _EXTENDED_GP0_REG
_EXTENDED_GP0_REG:
.word 0x00000000
.global _EXTENDED_GP1_REG
_EXTENDED_GP1_REG:
.word 0x00000000
.global _EXTENDED_GP2_REG
_EXTENDED_GP2_REG:
.word 0x00000000
.global _EXTENDED_GP3_REG
_EXTENDED_GP3_REG:
.word 0x00000000
.global _EXTENDED_GP4_REG
_EXTENDED_GP4_REG:
.word 0x00000000
.global _EXTENDED_GP5_REG
_EXTENDED_GP5_REG:
.word 0x00000000
.global _EXTENDED_GP6_REG
_EXTENDED_GP6_REG:
.word 0x00000000
.global _EXTENDED_GP7_REG
_EXTENDED_GP7_REG:
.word 0x00000000
.global _MEM_CTRL_EN_NC_MEM_REG
_MEM_CTRL_EN_NC_MEM_REG:
.word 0x00000000
.global _MEM_CTRL_BASE0_ADDR_REG
_MEM_CTRL_BASE0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK0_ADDR_REG
_MEM_CTRL_MASK0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE1_ADDR_REG
_MEM_CTRL_BASE1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK1_ADDR_REG
_MEM_CTRL_MASK1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE2_ADDR_REG
_MEM_CTRL_BASE2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK2_ADDR_REG
_MEM_CTRL_MASK2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE3_ADDR_REG
_MEM_CTRL_BASE3_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK3_ADDR_REG
_MEM_CTRL_MASK3_ADDR_REG:
.word 0x00000000
; 128 bytes minus seventeen registers (four bytes per register)
.fill (128 - 17 * 4)
; Reserved memory-map space
.fill (256 + 256)
;.org 0xfffff600
; Timer Registers
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER3_VAL_REG
_TIMER3_VAL_REG:
.word 0x00000000
; 256 bytes minus four registers (four bytes per register)
.fill (256 - 4 * 4)
;.org 0xfffff700
; Output Line Control Registers
.global _OUTPUT0_CTRL
_OUTPUT0_CTRL:
.word 0x00000000
.global _OUTPUT1_CTRL
_OUTPUT1_CTRL:
.word 0x00000000
.global _OUTPUT2_CTRL
_OUTPUT2_CTRL:
.word 0x00000000
.global _OUTPUT3_CTRL
_OUTPUT3_CTRL:
.word 0x00000000
.global _OUTPUT4_CTRL
_OUTPUT4_CTRL:
.word 0x00000000
.global _OUTPUT5_CTRL
_OUTPUT5_CTRL:
.word 0x00000000
.global _OUTPUT6_CTRL
_OUTPUT6_CTRL:
.word 0x00000000
; 128 bytes minus seven registers (four bytes per register)
.fill (128 - 7 * 4)
.global _INPUT0_CTRL
_INPUT0_CTRL:
.word 0x00000000
; 128 bytes minus one register (four bytes per register)
.fill (128 - 1 * 4)
;.org 0xfffff800
; IQ Buffer Registers
.global _IQ_BUFF_CTRL_REG
_IQ_BUFF_CTRL_REG:
.word 0x00000000
.global _IQ_BUFF_STATUS_REG
_IQ_BUFF_STATUS_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER1_REG
_IQ_BUFF_PARAMETER1_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE1_REG
_IQ_BUFF_TRANSFER_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE1_REG
_IQ_BUFF_FB_BASE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE1_REG
_IQ_BUFF_FB_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER2_REG
_IQ_BUFF_PARAMETER2_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE2_REG
_IQ_BUFF_TRANSFER_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE2_REG
_IQ_BUFF_FB_BASE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE2_REG
_IQ_BUFF_FB_SIZE2_REG:
.word 0x00000000
; 256 bytes minus ten registers (four bytes per register)
.fill (256 - 10 * 4)
;.org 0xfffff900
; DMA Controller
.global _DMA_CTRL_REG
_DMA_CTRL_REG:
.word 0x00000000
.global _DMA_STATUS_REG
_DMA_STATUS_REG:
.word 0x00000000
.global _DMA_CH0_EADDR_REG
_DMA_CH0_EADDR_REG:
.word 0x00000000
.global _DMA_CH0_IADDR_REG
_DMA_CH0_IADDR_REG:
.word 0x00000000
.global _DMA_CH0_SIZE_REG
_DMA_CH0_SIZE_REG:
.word 0x00000000
.global _DMA_CH1_EADDR_REG
_DMA_CH1_EADDR_REG:
.word 0x00000000
.global _DMA_CH1_IADDR_REG
_DMA_CH1_IADDR_REG:
.word 0x00000000
.global _DMA_CH1_SIZE_REG
_DMA_CH1_SIZE_REG:
.word 0x00000000
.global _DMA_CH2_EADDR_REG
_DMA_CH2_EADDR_REG:
.word 0x00000000
.global _DMA_CH2_IADDR_REG
_DMA_CH2_IADDR_REG:
.word 0x00000000
.global _DMA_CH2_SIZE_REG
_DMA_CH2_SIZE_REG:
.word 0x00000000
.global _DMA_CH3_EADDR_REG
_DMA_CH3_EADDR_REG:
.word 0x00000000
.global _DMA_CH3_IADDR_REG
_DMA_CH3_IADDR_REG:
.word 0x00000000
.global _DMA_CH3_SIZE_REG
_DMA_CH3_SIZE_REG:
.word 0x00000000
; 256 bytes minus fourteen registers (four bytes per register)
.fill (256 - 14 * 4)
;.org 0xfffffa00
; Sequence Generator
.global _SEQ_GEN_CTRL_STATUS_REG
_SEQ_GEN_CTRL_STATUS_REG:
.word 0x00000000
.global _SEQ_GEN_MASK_REGS
_SEQ_GEN_MASK_REGS:
.fill (302 * 4)
.global _SEQ_GEN_SHIFT_REG
_SEQ_GEN_SHIFT_REG:
.word 0x00000000
; 256 bytes minus seven registers (four bytes per register)
.fill (256 - 48 * 4)
; Reserved memory-map space
.fill (0x1000 - 0xf00)
|
stsp/newlib-ia16
| 2,903
|
libgloss/mt/crt0-16-003.S
|
; crt0.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
;
; Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
;
; The authors hereby grant permission to use, copy, modify, distribute,
; and license this software and its documentation for any purpose, provided
; that existing copyright notices are retained in all copies and that this
; notice is included verbatim in any distributions. No written agreement,
; license, or royalty fee is required for any of the authorized uses.
; Modifications to this software may be copyrighted by their authors
; and need not follow the licensing terms described here, provided that
; the new terms are clearly indicated on the first page of each file where
; they apply.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
|
stsp/newlib-ia16
| 3,499
|
libgloss/mt/crt0-64-001.S
|
; crt0_2.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
; 12Nov01 (DJK) - The return code from main was not being passed to exit().
; Now it is passed as a parameter in R1.
;
; 10Sep01 (DJK) - The function exit() does not return. However, in the
; the case of device error (if the halt bit does not
; function properly, for instance), then a catch loop
; has been added.
;
;
; Copyright 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.equ HALT_REG, 0x300
.section .text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(__FRAME_BUFFER_START)
brle r10, r9, .Lnext1
ori r11, r11, #%lo16(__FRAME_BUFFER_START)
.Lcpy0:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy0
addi r11, r11, #$4
.Lnext1:
;; Copy data from ROM to External Memory (off-chip memory)
ldui r9, #%hi16(_extdata_start)
ori r9, r9, #%lo16(_extdata_start)
ldui r10, #%hi16(_extdata_end)
ori r10, r10, #%lo16(_extdata_end)
ldui r11, #%hi16(__EXTERNAL_MEMORY_START)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(__EXTERNAL_MEMORY_START)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy2
or r0, r0, r0 ; nop
.Lnext3:
;; Zero the external memory bss section
ldui r9, #%hi16(_extbss_start)
ori r9, r9, #%lo16(_extbss_start)
ldui r10, #%hi16(_extbss_end)
ori r10, r10, #%lo16(_extbss_end)
or r0, r0, r0
brle r10, r9, .Lnext4
or r0, r0, r0
.Lcpy3:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy3
or r0, r0, r0
.Lnext4:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Setup destructors to be called from exit.
;; (Just in case main never returns....)
ldui r10, #%hi16(atexit)
ori r10, r10, #%lo16(atexit)
ldui r1, #%hi16(_fini)
ori r1, r1, #%lo16(_fini)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Initialise argc, argv and envp to empty
addi r1, r0, #0
addi r2, r0, #0
addi r3, r0, #0
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #HALT_REG
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
|
stsp/newlib-ia16
| 2,914
|
libgloss/cris/irqtable.S
|
/* Default interrupt table for CRIS/CRISv32.
Copyright (C) 2007 Axis Communications.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Neither the name of Axis Communications nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
#ifdef __ELF__
.section .startup,"ax"
#else
.text
#endif
#if defined (__ELF__) || defined (IN_CRT0)
; This is included from crt0.S for a.out, as we can't have it as
; a separate object file in a library due to the lack of named
; section support and the required placement at address 3*4.
; We define an interrupt table with references to the symbols
; _.irq_XX where XX are hex numbers 3..ff (lower-case). They
; are satisfied by weak aliases to the _.irq stub function in
; this file. When overridden, the overriding function must be
; in code explicitly linked in, i.e. *not* in a library.
.global __irqtable_at_irq3
__irqtable_at_irq3:
.irpc irqno,3456789abcdef
.weak _.irq_0\irqno
.set _.irq_0\irqno,_.irq
.dword _.irq_0\irqno
.endr
.irpc irqhd,123456789abcdef
.irpc irqld,0123456789abcdef
.weak _.irq_\irqhd\irqld
.set _.irq_\irqhd\irqld,_.irq
.dword _.irq_\irqhd\irqld
.endr
.endr
; No use having a separate file with default _.irq_[0-f][0-f]
; definitions; just provide a single stub with a weak definition
; and make it up to the user to provide a strong definition that
; they force to be linked in (i.e. not in a library or at least
; together with another symbol they know is linked in).
.text
_.irq:
#ifdef __arch_common_v10_v32
; This is just to allow the multilib to compile without
; hackery: the "common" subset doesn't recognize
; interrupt-return insns.
#elif __CRIS_arch_version >= 32
rete
rfe
#else
reti
nop
#endif
#endif /* __ELF__ || IN_CRT0 */
|
stsp/newlib-ia16
| 2,338
|
libgloss/cris/crt0.S
|
/* Generic simplistic start-up-stub for CRIS/CRISv32.
Copyright (C) 1993-2005, 2007 Axis Communications.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Neither the name of Axis Communications nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
#undef cris
#undef L
#ifdef __NO_UNDERSCORES__
#define L(x) x
#else
#define L(x) _ ## x
#endif
; Rudimentary v0..v32-compatible startup stub.
#ifdef __ELF__
.section .startup,"ax"
#endif
.global __start
nop
__start:
move.d 0f,$r9
jump $r9
setf
#ifndef __ELF__
; For a.out, everything read-only and code-wise goes into a
; single section, so we can't separate the interrupt table from
; the startup code if we want to have files in-between.
#define IN_CRT0
#include "irqtable.S"
#else
; The interrupt table (at offset 12, irq #3) is expected here.
; The simplest way to make sure we link it in, is to sacrifice
; some memory and refer to it with a relocation.
.text
.dword __irqtable_at_irq3
#endif /* __ELF__ */
0:
move.d __setup,$r9
jsr $r9
nop
#ifdef __ELF__
jsr L(_init)
nop
move.d L(_fini),$r10
jsr L(atexit)
nop
#endif
jsr L(main)
nop
jsr L(exit)
nop
0:
nop
ba 0b
nop
|
stsp/newlib-ia16
| 1,859
|
libgloss/cris/setup.S
|
/* Support for standalone CRIS/CRISv32 code.
Copyright (C) 2005, 2007 Axis Communications.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Neither the name of Axis Communications nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
.text
.global __setup
__setup:
/* Make sure to save SRP. */
#ifdef __arch_common_v10_v32
/* Can't do anything if we don't know for which arch. This file is
then only a placeholder. Oh, and we can't use the "ret" and "nop"
insns in "common" code. */
move $srp,$r9
jump $r9
setf
#else
/* Code missing:
- Initialize RAM circuits.
- Initialize serial output and input.
- Set stack-pointer. */
ret
nop
#endif
|
stsp/newlib-ia16
| 1,118
|
libgloss/frv/sim-read.S
|
/*
* sim-read.S -- read interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File descriptor.
* gr9 -- Buffer to be read into.
* gr10 -- Length of the buffer.
*
* Output:
* gr8 -- Length read or -1.
* errno -- Set if an error
*/
.globl EXT(_read)
.type EXT(_read),@function
.weak EXT(read)
.text
EXT(_read):
EXT(read):
setlos #SYS_read,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_read),.Lend-EXT(_read)
|
stsp/newlib-ia16
| 1,056
|
libgloss/frv/sim-close.S
|
/*
* sim-close.S -- close interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File descriptor to close.
*
* Output:
* gr8 -- 0 or -1.
* errno -- Set if an error
*/
.globl EXT(_close)
.type EXT(_close),@function
.weak EXT(close)
.text
EXT(_close):
EXT(close):
setlos #SYS_close,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_close),.Lend-EXT(_close)
|
stsp/newlib-ia16
| 1,140
|
libgloss/frv/sim-lseek.S
|
/*
* sim-lseek.S -- write interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File descriptor
* gr9 -- Offset
* gr10 -- Base from which offset should be taken
*
* Output:
* gr8 -- Zero on success, -1 on failure.
* errno -- Set if an error
*/
.globl EXT(_lseek)
.type EXT(_lseek),@function
.weak EXT(lseek)
.text
EXT(_lseek):
EXT(lseek):
setlos #SYS_lseek,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_lseek),.Lend-EXT(_lseek)
|
stsp/newlib-ia16
| 1,071
|
libgloss/frv/sim-unlink.S
|
/*
* sim-unlink.S -- write interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- Filename
*
* Output:
* gr8 -- Zero on success, -1 on failure.
* errno -- Set if an error
*/
.globl EXT(_unlink)
.type EXT(_unlink),@function
.weak EXT(unlink)
.text
EXT(_unlink):
EXT(unlink):
setlos #SYS_unlink,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_unlink),.Lend-EXT(_unlink)
|
stsp/newlib-ia16
| 7,636
|
libgloss/frv/crt0.S
|
/* crt0.S -- startup file for frv.
*
* Copyright (c) 2002, 2003 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
/* statically store .Lcall's address so we can see if we are running
at the location we were linked for or a different location. */
.data
.type EXT(__start_cmp),@object
.size EXT(__start_cmp),4
.p2align 2
EXT(__start_cmp):
.picptr .Lcall
.globl __start
.weak _start
.text
.type __start,@function
__start:
_start:
call .Lcall /* set up _gp in a pic-friendly manor */
.Lcall: movsg lr, gr4
P(sethi) #gprelhi(.Lcall), gr5
setlo #gprello(.Lcall), gr5
P(sub) gr4, gr5, gr16
#if ! __FRV_FDPIC__
sethi #gprelhi(EXT(_stack)), sp /* load up stack pointer */
P(setlo) #gprello(EXT(_stack)), sp
setlos #0, fp /* zero fp to allow unwinders to stop */
P(add) sp, gr16, sp
#define FDPIC(...)
#else
#define FDPIC(...) __VA_ARGS__
/* The assembler will rightfully claim that
#hi/lo(__stacksize) are unsafe for PIC, but since __stacksize
is absolute, and we don't want it to be relocated, we should
be fine. */
sethi #gprelhi(EXT(__end)), gr6
P(sethi) #hi(EXT(__stacksize+7)), gr5
setlo #gprello(EXT(__end)), gr6
P(setlo) #lo(EXT(__stacksize+7)), gr5
add gr6, gr16, gr6
add gr6, gr5, gr5
andi gr5, -8, sp
/* Using GPREL to compute _GLOBAL_OFFSET_TABLE_'s will force
the entire program to relocate as a unit, which is fine for
frv-elf. */
P(sethi) #gprelhi(EXT(_GLOBAL_OFFSET_TABLE_)), gr15
setlo #gprello(EXT(_GLOBAL_OFFSET_TABLE_)), gr15
/* We compute the value in a call-saved register (that happens
to be the PIC register in the EABI, and copy it to gr15 before
every call. */
add gr15, gr16, gr17
#endif
sethi #gprelhi(EXT(__start_cmp)), gr5
setlo #gprello(EXT(__start_cmp)), gr5
ld @(gr5,gr16), gr6
subcc gr4, gr6, gr8, icc0
beq icc0, 0, .Lfixed
P(st) gr4, @(gr5, gr16) /* update so if we restart no need to fixup */
setlos 4, gr11
#if ! __FRV_FDPIC__
/* fixup the .ctors list */
sethi #gprelhi(EXT(__CTOR_LIST__)), gr9
P(sethi) #gprelhi(EXT(__CTOR_END__)), gr10
setlo #gprello(EXT(__CTOR_LIST__)), gr9
P(setlo) #gprello(EXT(__CTOR_END__)), gr10
add gr9, gr16, gr9
P(add) gr10, gr16, gr10
addi gr9, 4, gr9
P(subi) gr10, 4, gr10
call EXT(__frv_fixptrs)
/* fixup the .dtors list */
P(sethi) #gprelhi(EXT(__DTOR_LIST__)), gr9
sethi #gprelhi(EXT(__DTOR_END__)), gr10
P(setlo) #gprello(EXT(__DTOR_LIST__)), gr9
setlo #gprello(EXT(__DTOR_END__)), gr10
P(add) gr9, gr16, gr9
add gr10, gr16, gr10
P(addi) gr9, 4, gr9
subi gr10, 4, gr10
call EXT(__frv_fixptrs)
#endif /* ! __FRV_FDPIC__ */
/* fixup the user .rofixup list */
P(sethi) #gprelhi(EXT(__ROFIXUP_LIST__)), gr9
sethi #gprelhi(EXT(__ROFIXUP_END__)), gr10
P(setlo) #gprello(EXT(__ROFIXUP_LIST__)), gr9
setlo #gprello(EXT(__ROFIXUP_END__)), gr10
P(add) gr9, gr16, gr9
add gr10, gr16, gr10
FDPIC(mov gr17, gr15)
call EXT(__frv_fix_usrptrs)
.Lfixed:
/* HSR flags */
#define HSR_ICE 0x80000000 /* Instruction cache enable */
#define HSR_DCE 0x40000000 /* Data cache enable */
#define HSR_CBM 0x08000000 /* Cache copy back mode */
#define HSR_EIMM 0x04000000 /* Enable Instruction MMU */
#define HSR_EDMM 0x02000000 /* Enable Data MMU */
#define HSR_EMEM 0x00800000 /* Enable MMU miss exception mask */
#define HSR_RME 0x00400000 /* Ram mode enable */
#define HSR_SA 0x00001000 /* Start address */
#define HSR_FRN 0x00000800 /* Number of FPRs */
#define HSR_GRN 0x00000400 /* Number of GPRs */
#define HSR_FRHE 0x00000200 /* FR Higher Enable */
#define HSR_FRLE 0x00000100 /* FR Lower Enable */
#define HSR_GRHE 0x00000080 /* GR Higher Enable */
#define HSR_GRLE 0x00000040 /* GR Lower Enable */
#ifndef HSR_CLEAR
#define HSR_CLEAR 0
#endif
#ifndef HSR_SET
#ifndef FRV_NO_CACHE
#define HSR_SET (HSR_ICE|HSR_DCE|HSR_FRHE|HSR_FRLE|HSR_GRHE|HSR_GRLE)
#else
#define HSR_SET (HSR_FRHE|HSR_FRLE|HSR_GRHE|HSR_GRLE)
#endif
#endif
/* PSR flags */
#define PSR_ICE 0x00010000 /* In circuit emulation mode */
#define PSR_NEM 0x00004000 /* Non-exception mode */
#define PSR_CM 0x00002000 /* Conditional mode */
#define PSR_BE 0x00001000 /* Big endian mode */
#define PSR_EF 0x00000100 /* Enable floating point */
#define PSR_EM 0x00000080 /* Enable media instructions */
#define PSR_S 0x00000004 /* Enable supervisor mode */
#define PSR_PS 0x00000002 /* Previous supervisor mode */
#define PSR_ET 0x00000001 /* Enable interrupts */
#ifndef PSR_CLEAR
#if __FRV_FPR__
#define PSR_CLEAR 0
#else
#define PSR_CLEAR (PSR_EF|PSR_EM)
#endif
#endif
#ifndef PSR_SET
#if __FRV_FPR__
#define PSR_SET (PSR_NEM|PSR_CM|PSR_EF|PSR_EM)
#else
#define PSR_SET (PSR_NEM|PSR_CM)
#endif
#endif
/* Enable floating point */
movsg hsr0, gr4
P(sethi) #hi(HSR_SET), gr5
setlo #lo(HSR_SET), gr5
P(sethi) #hi(~HSR_CLEAR), gr6
setlo #lo(~HSR_CLEAR), gr6
or gr4, gr5, gr4
and gr4, gr6, gr4
movgs gr4, hsr0
movsg psr, gr4
P(sethi) #hi(PSR_SET), gr5
setlo #lo(PSR_SET), gr5
P(sethi) #hi(~PSR_CLEAR), gr6
setlo #lo(~PSR_CLEAR), gr6
or gr4, gr5, gr4
and gr4, gr6, gr4
movgs gr4, psr
/* zero the bss area */
P(sethi) #gprelhi(__bss_start), gr8
sethi #gprelhi(__end), gr4
P(setlo) #gprello(__bss_start), gr8
setlo #gprello(__end), gr4
P(add) gr8, gr16, gr8
add gr4, gr16, gr4
P(setlos) #0, gr9
sub gr4, gr8, gr10
FDPIC(mov gr17, gr15)
call EXT(memset)
P(setlos) #0, gr8 /* zero argc, argv, envp */
setlos #0, gr9
P(setlos) #0, gr10
FDPIC(mov gr17, gr15)
call EXT(main)
FDPIC(mov gr17, gr15)
call EXT(exit)
.Lend:
.size __start,(.Lend-__start)
#if ! __FRV_FDPIC__
/* Routine to adjust pointers
gr8 = difference to adjust by
gr9 = starting address
gr10 = ending address + 4
gr11 = amount to add to the pointer each iteration. */
.globl EXT(__frv_fixptrs)
.type EXT(__frv_fixptrs),@function
EXT(__frv_fixptrs):
P(sub) gr9, gr11, gr9
sub gr10, gr11, gr10
.Lloop2:
cmp gr10, gr9, icc0
bls icc0, 0, .Lret2
ldu @(gr9,gr11), gr5
add gr8, gr5, gr5
P(st) gr5, @(gr9,gr0)
bra .Lloop2
.Lret2: ret
.Lend2:
.size EXT(__frv_fixptrs),.Lend2-EXT(__frv_fixptrs)
#endif /* ! __FRV_FDPIC__ */
/* Routine to adjust statically initialized pointers
Note since these are pointers to pointers, they
need to be adjusted themsevles.
gr8 = difference to adjust by
gr9 = starting address
gr10 = ending address + 4
gr11 = amount to add to the pointer each iteration. */
.globl EXT(__frv_fix_usrptrs)
.type EXT(__frv_fix_usrptrs),@function
EXT(__frv_fix_usrptrs):
P(sub) gr9, gr11, gr9
sub gr10, gr11, gr10
.Lloop3:
cmp gr10, gr9, icc0
bls icc0, 0, .Lret3
ldu @(gr9,gr11), gr5
ld @(gr5, gr8), gr6
cmp gr6, gr0, icc0 /* skip pointers initialized to 0 */
beq icc0, 0, .Lloop3
add gr8, gr6, gr6
P(st) gr6, @(gr5,gr8)
bra .Lloop3
.Lret3: ret
.Lend3:
.size EXT(__frv_fix_usrptrs),.Lend3-EXT(__frv_fix_usrptrs)
.section .data
.global __dso_handle
.weak __dso_handle
__dso_handle:
.long 0
|
stsp/newlib-ia16
| 1,141
|
libgloss/frv/sim-open.S
|
/*
* sim-open.S -- open interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File name to open.
* gr9 -- open mode.
* gr10 -- optionally, the permission bits to set the file to.
*
* Output:
* gr8 -- file descriptor or -1.
* errno -- Set if an error
*/
.globl EXT(_open)
.type EXT(_open),@function
.weak EXT(open)
.text
EXT(_open):
EXT(open):
setlos #SYS_open,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_open),.Lend-EXT(_open)
|
stsp/newlib-ia16
| 1,129
|
libgloss/frv/sim-write.S
|
/*
* sim-write.S -- write interface for frv simulator
*
* Copyright (c) 2002 Red Hat, Inc
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include <frv-asm.h>
#include "syscall.h"
/*
* Input:
* gr8 -- File descriptor.
* gr9 -- String to be printed.
* gr10 -- Length of the string.
*
* Output:
* gr8 -- Length written or -1.
* errno -- Set if an error
*/
.globl EXT(_write)
.type EXT(_write),@function
.weak EXT(write)
.text
EXT(_write):
EXT(write):
setlos #SYS_write,gr7
tira gr0,#0
ret
.Lend:
.size EXT(_write),.Lend-EXT(_write)
|
stsp/newlib-ia16
| 1,587
|
libgloss/v850/crt0.S
|
# NEC V850 startup code
.section .text
.global _start
_start:
#if defined(__v850e__) || defined(__v850e2__) || defined(__v850e2v3__) || defined(__v850e3v5__)
movea 255, r0, r20
mov 65535, r21
mov hilo(_stack), sp
mov hilo(__ep), ep
mov hilo(__gp), gp
mov hilo(__ctbp), r6
ldsr r6, ctbp
#if defined(__v850e2v3__) || defined(__v850e3v5__)
// FPU enable
stsr psw, r6
movhi 1, r0, r7
or r7, r6
ldsr r6, psw
// Initialize the FPSR
movhi 2, r0, r6
ldsr r6, fpsr
#endif
mov hilo(_edata), r6
mov hilo(_end), r7
.L0:
st.w r0, 0[r6]
addi 4, r6, r6
cmp r7, r6
bl .L0
.L1:
jarl ___main, r31
addi -16, sp, sp
mov 0, r6
mov 0, r7
mov 0, r8
jarl _main, r31
mov r10, r6
jarl _exit, r31
# else
movea 255, r0, r20
mov r0, r21
ori 65535, r0, r21
movhi hi(_stack), r0, sp
movea lo(_stack), sp, sp
movhi hi(__ep), r0, ep
movea lo(__ep), ep, ep
movhi hi(__gp), r0, gp
movea lo(__gp), gp, gp
movhi hi(_edata), r0, r6
movea lo(_edata), r6, r6
movhi hi(_end), r0, r7
movea lo(_end), r7, r7
.L0:
st.b r0, 0[r6]
addi 1, r6, r6
cmp r7, r6
bl .L0
.L1:
jarl ___main, r31
addi -16, sp, sp
mov 0, r6
mov 0, r7
mov 0, r8
jarl _main, r31
mov r10, r6
jarl _exit, r31
# endif
.section .stack
_stack: .long 1
.section .data
.global ___dso_handle
.weak ___dso_handle
___dso_handle:
.long 0
|
stsp/newlib-ia16
| 3,149
|
libgloss/pa/op50n-io.S
|
/* op50n-io.S -- low-level I/O routines for the Oki OP50N eval board.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
mon_start .EQU 0xd0000000
where_dp .EQU mon_start+4*4
where_ci .EQU mon_start+14*4
where_co .EQU mon_start+15*4
where_read .EQU mon_start+22*4
where_write .EQU mon_start+23*4
/*
*int c = inbyte(wait);
*/
.space $TEXT$
.align 4
.EXPORT inbyte,CODE,ARGW0=GR,RTNVAL=GR
inbyte
.PROC
.CALLINFO CALLER,FRAME=64,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30)
ldo 64(%r30),%r30
stw %r27,-56(0,%r30) ; save my dp
ldil l%where_dp,%r27 ; load monitors dp
ldw r%where_dp(0,%r27),%r27
ldil l%where_ci,%r1
ldw r%where_ci(0,%r1),%r1
ble 0(0,%r1)
copy %r31,%r2
ldw -56(0,%r30),%r27 ; load my dp
ldw -84(0,%r30),%r2
ldo -64(%r30),%r30
bv %r0(%r2)
nop
.EXIT
.PROCEND
/* int c = outbyte(c);
*/
.EXPORT outbyte,CODE,ARGW0=GR,RTNVAL=GR
outbyte
.PROC
.CALLINFO CALLER,FRAME=64,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30)
ldo 64(%r30),%r30
stw %r27,-56(0,%r30) ; save my dp
ldil l%where_dp,%r27 ; load monitors dp
ldw r%where_dp(0,%r27),%r27
ldil l%where_co,%r1
ldw r%where_co(0,%r1),%r1
ble 0(0,%r1)
copy %r31,%r2
ldw -56(0,%r30),%r27 ; load my dp
ldw -84(0,%r30),%r2
ldo -64(%r30),%r30
bv %r0(%r2)
nop
.EXIT
.PROCEND
#if 0
/* cnt = read(fd, bufp, cnt);
*/
.EXPORT read,CODE,ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RTNVAL=NO
read
.PROC
.CALLINFO FRAME=64,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30)
ldo 64(%r30),%r30
stw %dp,-56(0,%r30) ; save my dp
ldil l%where_dp,%dp ; load monitors dp
ldw r%where_dp(0,%dp), %dp
ldil l%where_read,%r1
ldw r%where_read(0,%r1), %r1
ble 0(0,%r1)
copy %r31,%r2
ldw -56(0,%r30),%dp ; load my dp
ldw -84(0,%r30),%r2
bv %r0(%r2)
ldo -64(%r30),%r30
.EXIT
.PROCEND
/* cnt = write(fd, bufp, cnt);
*/
.EXPORT write,CODE,ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RTNVAL=NO
write
.PROC
.CALLINFO FRAME=64,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(0,%r30)
ldo 64(%r30),%r30
stw %dp,-56(0,%r30) ; save my dp
ldil l%where_dp,%dp ; load monitors dp
ldw r%where_dp(0,%dp), %dp
ldil l%where_write,%r1
ldw r%where_write(0,%r1), %r1
ble 0(0,%r1)
copy %r31,%r2
ldw -56(0,%r30),%dp ; load my dp
ldw -84(0,%r30),%r2
bv %r0(%r2)
ldo -64(%r30),%r30
.EXIT
.PROCEND
#endif
|
stsp/newlib-ia16
| 56,787
|
libgloss/pa/hp-milli.s
|
;
; (c) Copyright 1986 HEWLETT-PACKARD COMPANY
;
; To anyone who acknowledges that this file is provided "AS IS"
; without any express or implied warranty:
; permission to use, copy, modify, and distribute this file
; for any purpose is hereby granted without fee, provided that
; the above copyright notice and this notice appears in all
; copies, and that the name of Hewlett-Packard Company not be
; used in advertising or publicity pertaining to distribution
; of the software without specific, written prior permission.
; Hewlett-Packard Company makes no representations about the
; suitability of this software for any purpose.
;
; Standard Hardware Register Definitions for Use with Assembler
; version A.08.06
; - fr16-31 added at Utah
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; Hardware General Registers
r0: .equ 0
r1: .equ 1
r2: .equ 2
r3: .equ 3
r4: .equ 4
r5: .equ 5
r6: .equ 6
r7: .equ 7
r8: .equ 8
r9: .equ 9
r10: .equ 10
r11: .equ 11
r12: .equ 12
r13: .equ 13
r14: .equ 14
r15: .equ 15
r16: .equ 16
r17: .equ 17
r18: .equ 18
r19: .equ 19
r20: .equ 20
r21: .equ 21
r22: .equ 22
r23: .equ 23
r24: .equ 24
r25: .equ 25
r26: .equ 26
r27: .equ 27
r28: .equ 28
r29: .equ 29
r30: .equ 30
r31: .equ 31
; Hardware Space Registers
sr0: .equ 0
sr1: .equ 1
sr2: .equ 2
sr3: .equ 3
sr4: .equ 4
sr5: .equ 5
sr6: .equ 6
sr7: .equ 7
; Hardware Floating Point Registers
fr0: .equ 0
fr1: .equ 1
fr2: .equ 2
fr3: .equ 3
fr4: .equ 4
fr5: .equ 5
fr6: .equ 6
fr7: .equ 7
fr8: .equ 8
fr9: .equ 9
fr10: .equ 10
fr11: .equ 11
fr12: .equ 12
fr13: .equ 13
fr14: .equ 14
fr15: .equ 15
fr16: .equ 16
fr17: .equ 17
fr18: .equ 18
fr19: .equ 19
fr20: .equ 20
fr21: .equ 21
fr22: .equ 22
fr23: .equ 23
fr24: .equ 24
fr25: .equ 25
fr26: .equ 26
fr27: .equ 27
fr28: .equ 28
fr29: .equ 29
fr30: .equ 30
fr31: .equ 31
; Hardware Control Registers
cr0: .equ 0
rctr: .equ 0 ; Recovery Counter Register
cr8: .equ 8 ; Protection ID 1
pidr1: .equ 8
cr9: .equ 9 ; Protection ID 2
pidr2: .equ 9
cr10: .equ 10
ccr: .equ 10 ; Coprocessor Confiquration Register
cr11: .equ 11
sar: .equ 11 ; Shift Amount Register
cr12: .equ 12
pidr3: .equ 12 ; Protection ID 3
cr13: .equ 13
pidr4: .equ 13 ; Protection ID 4
cr14: .equ 14
iva: .equ 14 ; Interrupt Vector Address
cr15: .equ 15
eiem: .equ 15 ; External Interrupt Enable Mask
cr16: .equ 16
itmr: .equ 16 ; Interval Timer
cr17: .equ 17
pcsq: .equ 17 ; Program Counter Space queue
cr18: .equ 18
pcoq: .equ 18 ; Program Counter Offset queue
cr19: .equ 19
iir: .equ 19 ; Interruption Instruction Register
cr20: .equ 20
isr: .equ 20 ; Interruption Space Register
cr21: .equ 21
ior: .equ 21 ; Interruption Offset Register
cr22: .equ 22
ipsw: .equ 22 ; Interrpution Processor Status Word
cr23: .equ 23
eirr: .equ 23 ; External Interrupt Request
cr24: .equ 24
ppda: .equ 24 ; Physcial Page Directory Address
tr0: .equ 24 ; Temporary register 0
cr25: .equ 25
hta: .equ 25 ; Hash Table Address
tr1: .equ 25 ; Temporary register 1
cr26: .equ 26
tr2: .equ 26 ; Temporary register 2
cr27: .equ 27
tr3: .equ 27 ; Temporary register 3
cr28: .equ 28
tr4: .equ 28 ; Temporary register 4
cr29: .equ 29
tr5: .equ 29 ; Temporary register 5
cr30: .equ 30
tr6: .equ 30 ; Temporary register 6
cr31: .equ 31
tr7: .equ 31 ; Temporary register 7
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; Procedure Call Convention ~
; Register Definitions for Use with Assembler ~
; version A.08.06
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; Software Architecture General Registers
rp: .equ r2 ; return pointer
mrp: .equ r31 ; millicode return pointer
ret0: .equ r28 ; return value
ret1: .equ r29 ; return value (high part of double)
sl: .equ r29 ; static link
sp: .equ r30 ; stack pointer
dp: .equ r27 ; data pointer
arg0: .equ r26 ; argument
arg1: .equ r25 ; argument or high part of double argument
arg2: .equ r24 ; argument
arg3: .equ r23 ; argument or high part of double argument
;_____________________________________________________________________________
; Software Architecture Space Registers
; sr0 ; return link form BLE
sret: .equ sr1 ; return value
sarg: .equ sr1 ; argument
; sr4 ; PC SPACE tracker
; sr5 ; process private data
;_____________________________________________________________________________
; Software Architecture Pseudo Registers
previous_sp: .equ 64 ; old stack pointer (locates previous frame)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; Standard space and subspace definitions. version A.08.06
; These are generally suitable for programs on HP_UX and HPE.
; Statements commented out are used when building such things as operating
; system kernels.
;;;;;;;;;;;;;;;;
.SPACE $TEXT$, SPNUM=0,SORT=8
.subspa $MILLICODE$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=8
.subspa $LIT$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=16
.subspa $CODE$, QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=24
; Additional code subspaces should have ALIGN=8 for an interspace BV
; and should have SORT=24.
;
; For an incomplete executable (program bound to shared libraries),
; sort keys $GLOBAL$ -1 and $GLOBAL$ -2 are reserved for the $DLT$
; and $PLT$ subspaces respectively.
;;;;;;;;;;;;;;;
.SPACE $PRIVATE$, SPNUM=1,PRIVATE,SORT=16
.subspa $GLOBAL$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=40
.import $global$
.subspa $DATA$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=16
.subspa $BSS$, QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82,ZERO
.SPACE $TEXT$
.SUBSPA $MILLICODE$
.align 8
.EXPORT $$remI,millicode
; .IMPORT cerror
$$remI:
.PROC
.CALLINFO millicode
.ENTRY
addit,= 0,arg1,r0
add,>= r0,arg0,ret1
sub r0,ret1,ret1
sub r0,arg1,r1
ds r0,r1,r0
or r0,r0,r1
add ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
ds r1,arg1,r1
addc ret1,ret1,ret1
movb,>=,n r1,ret1,remI300
add,< arg1,r0,r0
add,tr r1,arg1,ret1
sub r1,arg1,ret1
remI300: add,>= arg0,r0,r0
sub r0,ret1,ret1
bv r0(r31)
nop
.EXIT
.PROCEND
bit1: .equ 1
bit30: .equ 30
bit31: .equ 31
len2: .equ 2
len4: .equ 4
$$dyncall:
.proc
.callinfo NO_CALLS
.entry
.export $$dyncall,MILLICODE
bb,>=,n 22,bit30,noshlibs
depi 0,bit31,len2,22
ldw 4(22),19
ldw 0(22),22
noshlibs:
ldsid (22),r1
mtsp r1,sr0
be 0(sr0,r22)
stw rp,-24(sp)
.exit
.procend
temp: .EQU r1
retreg: .EQU ret1 ; r29
.export $$divU,millicode
.import $$divU_3,millicode
.import $$divU_5,millicode
.import $$divU_6,millicode
.import $$divU_7,millicode
.import $$divU_9,millicode
.import $$divU_10,millicode
.import $$divU_12,millicode
.import $$divU_14,millicode
.import $$divU_15,millicode
$$divU:
.proc
.callinfo millicode
.entry
; The subtract is not nullified since it does no harm and can be used
; by the two cases that branch back to "normal".
comib,>= 15,arg1,special_divisor
sub r0,arg1,temp ; clear carry, negate the divisor
ds r0,temp,r0 ; set V-bit to 1
normal:
add arg0,arg0,retreg ; shift msb bit into carry
ds r0,arg1,temp ; 1st divide step, if no carry
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 2nd divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 3rd divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 4th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 5th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 6th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 7th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 8th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 9th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 10th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 11th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 12th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 13th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 14th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 15th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 16th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 17th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 18th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 19th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 20th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 21st divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 22nd divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 23rd divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 24th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 25th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 26th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 27th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 28th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 29th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 30th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 31st divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 32nd divide step,
bv 0(r31)
addc retreg,retreg,retreg ; shift last retreg bit into retreg
;_____________________________________________________________________________
; handle the cases where divisor is a small constant or has high bit on
special_divisor:
comib,> 0,arg1,big_divisor
nop
blr arg1,r0
nop
zero_divisor: ; this label is here to provide external visibility
addit,= 0,arg1,0 ; trap for zero dvr
nop
bv 0(r31) ; divisor == 1
copy arg0,retreg
bv 0(r31) ; divisor == 2
extru arg0,30,31,retreg
b,n $$divU_3 ; divisor == 3
nop
bv 0(r31) ; divisor == 4
extru arg0,29,30,retreg
b,n $$divU_5 ; divisor == 5
nop
b,n $$divU_6 ; divisor == 6
nop
b,n $$divU_7 ; divisor == 7
nop
bv 0(r31) ; divisor == 8
extru arg0,28,29,retreg
b,n $$divU_9 ; divisor == 9
nop
b,n $$divU_10 ; divisor == 10
nop
b normal ; divisor == 11
ds r0,temp,r0 ; set V-bit to 1
b,n $$divU_12 ; divisor == 12
nop
b normal ; divisor == 13
ds r0,temp,r0 ; set V-bit to 1
b,n $$divU_14 ; divisor == 14
nop
b,n $$divU_15 ; divisor == 15
nop
;_____________________________________________________________________________
; Handle the case where the high bit is on in the divisor.
; Compute: if( dividend>=divisor) quotient=1; else quotient=0;
; Note: dividend>==divisor iff dividend-divisor does not borrow
; and not borrow iff carry
big_divisor:
sub arg0,arg1,r0
bv 0(r31)
addc r0,r0,retreg
.exit
.procend
.end
t2: .EQU r1
; x2 .EQU arg0 ; r26
t1: .EQU arg1 ; r25
; x1 .EQU ret1 ; r29
;_____________________________________________________________________________
$$divide_by_constant:
.PROC
.CALLINFO millicode
.entry
.export $$divide_by_constant,millicode
; Provides a "nice" label for the code covered by the unwind descriptor
; for things like gprof.
$$divI_2:
.EXPORT $$divI_2,MILLICODE
COMCLR,>= arg0,0,0
ADDI 1,arg0,arg0
bv 0(r31)
EXTRS arg0,30,31,ret1
$$divI_4:
.EXPORT $$divI_4,MILLICODE
COMCLR,>= arg0,0,0
ADDI 3,arg0,arg0
bv 0(r31)
EXTRS arg0,29,30,ret1
$$divI_8:
.EXPORT $$divI_8,MILLICODE
COMCLR,>= arg0,0,0
ADDI 7,arg0,arg0
bv 0(r31)
EXTRS arg0,28,29,ret1
$$divI_16:
.EXPORT $$divI_16,MILLICODE
COMCLR,>= arg0,0,0
ADDI 15,arg0,arg0
bv 0(r31)
EXTRS arg0,27,28,ret1
$$divI_3:
.EXPORT $$divI_3,MILLICODE
COMB,<,N arg0,0,$neg3
ADDI 1,arg0,arg0
EXTRU arg0,1,2,ret1
SH2ADD arg0,arg0,arg0
B $pos
ADDC ret1,0,ret1
$neg3:
SUBI 1,arg0,arg0
EXTRU arg0,1,2,ret1
SH2ADD arg0,arg0,arg0
B $neg
ADDC ret1,0,ret1
$$divU_3:
.EXPORT $$divU_3,MILLICODE
ADDI 1,arg0,arg0
ADDC 0,0,ret1
SHD ret1,arg0,30,t1
SH2ADD arg0,arg0,arg0
B $pos
ADDC ret1,t1,ret1
$$divI_5:
.EXPORT $$divI_5,MILLICODE
COMB,<,N arg0,0,$neg5
ADDI 3,arg0,t1
SH1ADD arg0,t1,arg0
B $pos
ADDC 0,0,ret1
$neg5:
SUB 0,arg0,arg0
ADDI 1,arg0,arg0
SHD 0,arg0,31,ret1
SH1ADD arg0,arg0,arg0
B $neg
ADDC ret1,0,ret1
$$divU_5:
.EXPORT $$divU_5,MILLICODE
ADDI 1,arg0,arg0
ADDC 0,0,ret1
SHD ret1,arg0,31,t1
SH1ADD arg0,arg0,arg0
B $pos
ADDC t1,ret1,ret1
$$divI_6:
.EXPORT $$divI_6,MILLICODE
COMB,<,N arg0,0,$neg6
EXTRU arg0,30,31,arg0
ADDI 5,arg0,t1
SH2ADD arg0,t1,arg0
B $pos
ADDC 0,0,ret1
$neg6:
SUBI 2,arg0,arg0
EXTRU arg0,30,31,arg0
SHD 0,arg0,30,ret1
SH2ADD arg0,arg0,arg0
B $neg
ADDC ret1,0,ret1
$$divU_6:
.EXPORT $$divU_6,MILLICODE
EXTRU arg0,30,31,arg0
ADDI 1,arg0,arg0
SHD 0,arg0,30,ret1
SH2ADD arg0,arg0,arg0
B $pos
ADDC ret1,0,ret1
$$divU_10:
.EXPORT $$divU_10,MILLICODE
EXTRU arg0,30,31,arg0
ADDI 3,arg0,t1
SH1ADD arg0,t1,arg0
ADDC 0,0,ret1
$pos:
SHD ret1,arg0,28,t1
SHD arg0,0,28,t2
ADD arg0,t2,arg0
ADDC ret1,t1,ret1
$pos_for_17:
SHD ret1,arg0,24,t1
SHD arg0,0,24,t2
ADD arg0,t2,arg0
ADDC ret1,t1,ret1
SHD ret1,arg0,16,t1
SHD arg0,0,16,t2
ADD arg0,t2,arg0
bv 0(r31)
ADDC ret1,t1,ret1
$$divI_10:
.EXPORT $$divI_10,MILLICODE
COMB,< arg0,0,$neg10
COPY 0,ret1
EXTRU arg0,30,31,arg0
ADDIB,TR 1,arg0,$pos
SH1ADD arg0,arg0,arg0
$neg10:
SUBI 2,arg0,arg0
EXTRU arg0,30,31,arg0
SH1ADD arg0,arg0,arg0
$neg:
SHD ret1,arg0,28,t1
SHD arg0,0,28,t2
ADD arg0,t2,arg0
ADDC ret1,t1,ret1
$neg_for_17:
SHD ret1,arg0,24,t1
SHD arg0,0,24,t2
ADD arg0,t2,arg0
ADDC ret1,t1,ret1
SHD ret1,arg0,16,t1
SHD arg0,0,16,t2
ADD arg0,t2,arg0
ADDC ret1,t1,ret1
bv 0(r31)
SUB 0,ret1,ret1
$$divI_12:
.EXPORT $$divI_12,MILLICODE
COMB,< arg0,0,$neg12
COPY 0,ret1
EXTRU arg0,29,30,arg0
ADDIB,TR 1,arg0,$pos
SH2ADD arg0,arg0,arg0
$neg12:
SUBI 4,arg0,arg0
EXTRU arg0,29,30,arg0
B $neg
SH2ADD arg0,arg0,arg0
$$divU_12:
.EXPORT $$divU_12,MILLICODE
EXTRU arg0,29,30,arg0
ADDI 5,arg0,t1
SH2ADD arg0,t1,arg0
B $pos
ADDC 0,0,ret1
$$divI_15:
.EXPORT $$divI_15,MILLICODE
COMB,< arg0,0,$neg15
COPY 0,ret1
ADDIB,TR 1,arg0,$pos+4
SHD ret1,arg0,28,t1
$neg15:
B $neg
SUBI 1,arg0,arg0
$$divU_15:
.EXPORT $$divU_15,MILLICODE
ADDI 1,arg0,arg0
B $pos
ADDC 0,0,ret1
$$divI_17:
.EXPORT $$divI_17,MILLICODE
COMB,<,N arg0,0,$neg17
ADDI 1,arg0,arg0
SHD 0,arg0,28,t1
SHD arg0,0,28,t2
SUB t2,arg0,arg0
B $pos_for_17
SUBB t1,0,ret1
$neg17:
SUBI 1,arg0,arg0
SHD 0,arg0,28,t1
SHD arg0,0,28,t2
SUB t2,arg0,arg0
B $neg_for_17
SUBB t1,0,ret1
$$divU_17:
.EXPORT $$divU_17,MILLICODE
ADDI 1,arg0,arg0
ADDC 0,0,ret1
SHD ret1,arg0,28,t1
$u17:
SHD arg0,0,28,t2
SUB t2,arg0,arg0
B $pos_for_17
SUBB t1,ret1,ret1
$$divI_7:
.EXPORT $$divI_7,MILLICODE
COMB,<,N arg0,0,$neg7
$7:
ADDI 1,arg0,arg0
SHD 0,arg0,29,ret1
SH3ADD arg0,arg0,arg0
ADDC ret1,0,ret1
$pos7:
SHD ret1,arg0,26,t1
SHD arg0,0,26,t2
ADD arg0,t2,arg0
ADDC ret1,t1,ret1
SHD ret1,arg0,20,t1
SHD arg0,0,20,t2
ADD arg0,t2,arg0
ADDC ret1,t1,t1
COPY 0,ret1
SHD,= t1,arg0,24,t1
$1:
ADDB,TR t1,ret1,$2
EXTRU arg0,31,24,arg0
bv,n 0(r31)
$2:
ADDB,TR t1,arg0,$1
EXTRU,= arg0,7,8,t1
$neg7:
SUBI 1,arg0,arg0
$8:
SHD 0,arg0,29,ret1
SH3ADD arg0,arg0,arg0
ADDC ret1,0,ret1
$neg7_shift:
SHD ret1,arg0,26,t1
SHD arg0,0,26,t2
ADD arg0,t2,arg0
ADDC ret1,t1,ret1
SHD ret1,arg0,20,t1
SHD arg0,0,20,t2
ADD arg0,t2,arg0
ADDC ret1,t1,t1
COPY 0,ret1
SHD,= t1,arg0,24,t1
$3:
ADDB,TR t1,ret1,$4
EXTRU arg0,31,24,arg0
bv 0(r31)
SUB 0,ret1,ret1
$4:
ADDB,TR t1,arg0,$3
EXTRU,= arg0,7,8,t1
$$divU_7:
.EXPORT $$divU_7,MILLICODE
ADDI 1,arg0,arg0
ADDC 0,0,ret1
SHD ret1,arg0,29,t1
SH3ADD arg0,arg0,arg0
B $pos7
ADDC t1,ret1,ret1
$$divI_9:
.EXPORT $$divI_9,MILLICODE
COMB,<,N arg0,0,$neg9
ADDI 1,arg0,arg0
SHD 0,arg0,29,t1
SHD arg0,0,29,t2
SUB t2,arg0,arg0
B $pos7
SUBB t1,0,ret1
$neg9:
SUBI 1,arg0,arg0
SHD 0,arg0,29,t1
SHD arg0,0,29,t2
SUB t2,arg0,arg0
B $neg7_shift
SUBB t1,0,ret1
$$divU_9:
.EXPORT $$divU_9,MILLICODE
ADDI 1,arg0,arg0
ADDC 0,0,ret1
SHD ret1,arg0,29,t1
SHD arg0,0,29,t2
SUB t2,arg0,arg0
B $pos7
SUBB t1,ret1,ret1
$$divI_14:
.EXPORT $$divI_14,MILLICODE
COMB,<,N arg0,0,$neg14
$$divU_14:
.EXPORT $$divU_14,MILLICODE
B $7
EXTRU arg0,30,31,arg0
$neg14:
SUBI 2,arg0,arg0
B $8
EXTRU arg0,30,31,arg0
.exit
.PROCEND
.END
rmndr: .EQU ret1 ; r29
.export $$remU,millicode
$$remU:
.proc
.callinfo millicode
.entry
comib,>=,n 0,arg1,special_case
sub r0,arg1,rmndr ; clear carry, negate the divisor
ds r0,rmndr,r0 ; set V-bit to 1
add arg0,arg0,temp ; shift msb bit into carry
ds r0,arg1,rmndr ; 1st divide step, if no carry
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 2nd divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 3rd divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 4th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 5th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 6th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 7th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 8th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 9th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 10th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 11th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 12th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 13th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 14th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 15th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 16th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 17th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 18th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 19th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 20th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 21st divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 22nd divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 23rd divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 24th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 25th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 26th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 27th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 28th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 29th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 30th divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 31st divide step
addc temp,temp,temp ; shift temp with/into carry
ds rmndr,arg1,rmndr ; 32nd divide step,
comiclr,<= 0,rmndr,r0
add rmndr,arg1,rmndr ; correction
; .exit
bv,n 0(r31)
nop
; Putting >= on the last DS and deleting COMICLR does not work!
;_____________________________________________________________________________
special_case:
addit,= 0,arg1,r0 ; trap on div by zero
sub,>>= arg0,arg1,rmndr
copy arg0,rmndr
bv,n 0(r31)
nop
.exit
.procend
.end
; Use bv 0(r31) and bv,n 0(r31) instead.
; #define return bv 0(%mrp)
; #define return_n bv,n 0(%mrp)
.subspa $MILLICODE$
.align 16
$$mulI:
.proc
.callinfo millicode
.entry
.export $$mulI, millicode
combt,<<= %r25,%r26,l4 ; swap args if unsigned %r25>%r26
copy 0,%r29 ; zero out the result
xor %r26,%r25,%r26 ; swap %r26 & %r25 using the
xor %r26,%r25,%r25 ; old xor trick
xor %r26,%r25,%r26
l4: combt,<= 0,%r26,l3 ; if %r26>=0 then proceed like unsigned
zdep %r25,30,8,%r1 ; %r1 = (%r25&0xff)<<1 *********
sub,> 0,%r25,%r1 ; otherwise negate both and
combt,<=,n %r26,%r1,l2 ; swap back if |%r26|<|%r25|
sub 0,%r26,%r25
movb,tr,n %r1,%r26,l2 ; 10th inst.
l0: add %r29,%r1,%r29 ; add in this partial product
l1: zdep %r26,23,24,%r26 ; %r26 <<= 8 ******************
l2: zdep %r25,30,8,%r1 ; %r1 = (%r25&0xff)<<1 *********
l3: blr %r1,0 ; case on these 8 bits ******
extru %r25,23,24,%r25 ; %r25 >>= 8 ******************
;16 insts before this.
; %r26 <<= 8 **************************
x0: comb,<> %r25,0,l2 ! zdep %r26,23,24,%r26 ! bv,n 0(r31) ! nop
x1: comb,<> %r25,0,l1 ! add %r29,%r26,%r29 ! bv,n 0(r31) ! nop
x2: comb,<> %r25,0,l1 ! sh1add %r26,%r29,%r29 ! bv,n 0(r31) ! nop
x3: comb,<> %r25,0,l0 ! sh1add %r26,%r26,%r1 ! bv 0(r31) ! add %r29,%r1,%r29
x4: comb,<> %r25,0,l1 ! sh2add %r26,%r29,%r29 ! bv,n 0(r31) ! nop
x5: comb,<> %r25,0,l0 ! sh2add %r26,%r26,%r1 ! bv 0(r31) ! add %r29,%r1,%r29
x6: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh1add %r1,%r29,%r29 ! bv,n 0(r31)
x7: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r26,%r29,%r29 ! b,n ret_t0
x8: comb,<> %r25,0,l1 ! sh3add %r26,%r29,%r29 ! bv,n 0(r31) ! nop
x9: comb,<> %r25,0,l0 ! sh3add %r26,%r26,%r1 ! bv 0(r31) ! add %r29,%r1,%r29
x10: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh1add %r1,%r29,%r29 ! bv,n 0(r31)
x11: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r26,%r29,%r29 ! b,n ret_t0
x12: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh2add %r1,%r29,%r29 ! bv,n 0(r31)
x13: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r26,%r29,%r29 ! b,n ret_t0
x14: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x15: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh1add %r1,%r1,%r1 ! b,n ret_t0
x16: zdep %r26,27,28,%r1 ! comb,<> %r25,0,l1 ! add %r29,%r1,%r29 ! bv,n 0(r31)
x17: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r26,%r1,%r1 ! b,n ret_t0
x18: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh1add %r1,%r29,%r29 ! bv,n 0(r31)
x19: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh1add %r1,%r26,%r1 ! b,n ret_t0
x20: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh2add %r1,%r29,%r29 ! bv,n 0(r31)
x21: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r26,%r1 ! b,n ret_t0
x22: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x23: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x24: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh3add %r1,%r29,%r29 ! bv,n 0(r31)
x25: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r1,%r1 ! b,n ret_t0
x26: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x27: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r1,%r1,%r1 ! b,n ret_t0
x28: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x29: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x30: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x31: zdep %r26,26,27,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0
x32: zdep %r26,26,27,%r1 ! comb,<> %r25,0,l1 ! add %r29,%r1,%r29 ! bv,n 0(r31)
x33: sh3add %r26,0,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r26,%r1 ! b,n ret_t0
x34: zdep %r26,27,28,%r1 ! add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x35: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh3add %r26,%r1,%r1
x36: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh2add %r1,%r29,%r29 ! bv,n 0(r31)
x37: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r26,%r1 ! b,n ret_t0
x38: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x39: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x40: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh3add %r1,%r29,%r29 ! bv,n 0(r31)
x41: sh2add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh3add %r1,%r26,%r1 ! b,n ret_t0
x42: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x43: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x44: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x45: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! sh2add %r1,%r1,%r1 ! b,n ret_t0
x46: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! add %r1,%r26,%r1
x47: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh1add %r26,%r1,%r1
x48: sh1add %r26,%r26,%r1 ! comb,<> %r25,0,l0 ! zdep %r1,27,28,%r1 ! b,n ret_t0
x49: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r26,%r1,%r1
x50: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x51: sh3add %r26,%r26,%r1 ! sh3add %r26,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x52: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x53: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x54: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x55: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x56: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x57: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x58: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
x59: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t02a0 ! sh1add %r1,%r1,%r1
x60: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x61: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x62: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x63: zdep %r26,25,26,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0
x64: zdep %r26,25,26,%r1 ! comb,<> %r25,0,l1 ! add %r29,%r1,%r29 ! bv,n 0(r31)
x65: sh3add %r26,0,%r1 ! comb,<> %r25,0,l0 ! sh3add %r1,%r26,%r1 ! b,n ret_t0
x66: zdep %r26,26,27,%r1 ! add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x67: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x68: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x69: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x70: zdep %r26,25,26,%r1 ! sh2add %r26,%r1,%r1 ! b e_t0 ! sh1add %r26,%r1,%r1
x71: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_t0 ! sub %r1,%r26,%r1
x72: sh3add %r26,%r26,%r1 ! comb,<> %r25,0,l1 ! sh3add %r1,%r29,%r29 ! bv,n 0(r31)
x73: sh3add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_shift ! add %r29,%r1,%r29
x74: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x75: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x76: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x77: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x78: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
x79: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sub %r1,%r26,%r1
x80: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! add %r29,%r1,%r29
x81: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_shift ! add %r29,%r1,%r29
x82: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x83: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x84: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x85: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x86: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
x87: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_t02a0 ! sh2add %r26,%r1,%r1
x88: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x89: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x90: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x91: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x92: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
x93: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x94: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sh1add %r26,%r1,%r1
x95: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x96: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x97: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x98: zdep %r26,26,27,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh1add %r26,%r1,%r1
x99: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x100: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x101: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x102: zdep %r26,26,27,%r1 ! sh1add %r26,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x103: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t02a0 ! sh2add %r1,%r26,%r1
x104: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x105: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x106: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
x107: sh3add %r26,%r26,%r1 ! sh2add %r26,%r1,%r1 ! b e_t02a0 ! sh3add %r1,%r26,%r1
x108: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x109: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x110: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
x111: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x112: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! zdep %r1,27,28,%r1
x113: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t02a0 ! sh1add %r1,%r1,%r1
x114: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r1,%r1
x115: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1
x116: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh2add %r1,%r26,%r1
x117: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r1,%r1
x118: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0a0 ! sh3add %r1,%r1,%r1
x119: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t02a0 ! sh3add %r1,%r1,%r1
x120: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x121: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x122: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
x123: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x124: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x125: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x126: zdep %r26,25,26,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x127: zdep %r26,24,25,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0
x128: zdep %r26,24,25,%r1 ! comb,<> %r25,0,l1 ! add %r29,%r1,%r29 ! bv,n 0(r31)
x129: zdep %r26,24,25,%r1 ! comb,<> %r25,0,l0 ! add %r1,%r26,%r1 ! b,n ret_t0
x130: zdep %r26,25,26,%r1 ! add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x131: sh3add %r26,0,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x132: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x133: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x134: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
x135: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x136: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x137: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x138: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
x139: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0a0 ! sh2add %r1,%r26,%r1
x140: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh2add %r1,%r1,%r1
x141: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0a0 ! sh1add %r1,%r26,%r1
x142: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_2t0 ! sub %r1,%r26,%r1
x143: zdep %r26,27,28,%r1 ! sh3add %r1,%r1,%r1 ! b e_t0 ! sub %r1,%r26,%r1
x144: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x145: sh3add %r26,%r26,%r1 ! sh3add %r1,0,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x146: sh3add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x147: sh3add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x148: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x149: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x150: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
x151: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r26,%r1
x152: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x153: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x154: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
x155: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x156: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
x157: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_t02a0 ! sh2add %r1,%r1,%r1
x158: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sub %r1,%r26,%r1
x159: zdep %r26,26,27,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sub %r1,%r26,%r1
x160: sh2add %r26,%r26,%r1 ! sh2add %r1,0,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x161: sh3add %r26,0,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x162: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x163: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r26,%r1
x164: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x165: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x166: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
x167: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r26,%r1
x168: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x169: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x170: zdep %r26,26,27,%r1 ! sh1add %r26,%r1,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x171: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r1,%r1
x172: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
x173: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t02a0 ! sh3add %r1,%r1,%r1
x174: zdep %r26,26,27,%r1 ! sh1add %r26,%r1,%r1 ! b e_t04a0 ! sh2add %r1,%r1,%r1
x175: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_5t0 ! sh1add %r1,%r26,%r1
x176: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_8t0 ! add %r1,%r26,%r1
x177: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_8t0a0 ! add %r1,%r26,%r1
x178: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh3add %r1,%r26,%r1
x179: sh2add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0a0 ! sh3add %r1,%r26,%r1
x180: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x181: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x182: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sh1add %r1,%r26,%r1
x183: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0a0 ! sh1add %r1,%r26,%r1
x184: sh2add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_4t0 ! add %r1,%r26,%r1
x185: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x186: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r1,%r1
x187: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t02a0 ! sh2add %r1,%r1,%r1
x188: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_4t0 ! sh1add %r26,%r1,%r1
x189: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r1,%r1
x190: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r1,%r1
x191: zdep %r26,25,26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sub %r1,%r26,%r1
x192: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x193: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x194: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
x195: sh3add %r26,0,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x196: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
x197: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_4t0a0 ! sh1add %r1,%r26,%r1
x198: zdep %r26,25,26,%r1 ! sh1add %r26,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x199: sh3add %r26,0,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1
x200: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x201: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x202: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
x203: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0a0 ! sh2add %r1,%r26,%r1
x204: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r1,%r1
x205: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x206: zdep %r26,25,26,%r1 ! sh2add %r26,%r1,%r1 ! b e_t02a0 ! sh1add %r1,%r1,%r1
x207: sh3add %r26,0,%r1 ! sh1add %r1,%r26,%r1 ! b e_3t0 ! sh2add %r1,%r26,%r1
x208: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_8t0 ! add %r1,%r26,%r1
x209: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_8t0a0 ! add %r1,%r26,%r1
x210: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh2add %r1,%r1,%r1
x211: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh2add %r1,%r1,%r1
x212: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_4t0 ! sh2add %r1,%r26,%r1
x213: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_4t0a0 ! sh2add %r1,%r26,%r1
x214: sh3add %r26,%r26,%r1 ! sh2add %r26,%r1,%r1 ! b e2t04a0 ! sh3add %r1,%r26,%r1
x215: sh2add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_5t0 ! sh1add %r1,%r26,%r1
x216: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x217: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x218: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r26,%r1
x219: sh3add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x220: sh1add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_4t0 ! sh1add %r1,%r26,%r1
x221: sh1add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_4t0a0 ! sh1add %r1,%r26,%r1
x222: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r1,%r1
x223: sh3add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1
x224: sh3add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_8t0 ! add %r1,%r26,%r1
x225: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0 ! sh2add %r1,%r1,%r1
x226: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_t02a0 ! zdep %r1,26,27,%r1
x227: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_t02a0 ! sh2add %r1,%r1,%r1
x228: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0 ! sh1add %r1,%r1,%r1
x229: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_4t0a0 ! sh1add %r1,%r1,%r1
x230: sh3add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_5t0 ! add %r1,%r26,%r1
x231: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_3t0 ! sh2add %r1,%r26,%r1
x232: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_8t0 ! sh2add %r1,%r26,%r1
x233: sh1add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e_8t0a0 ! sh2add %r1,%r26,%r1
x234: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0 ! sh3add %r1,%r1,%r1
x235: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_2t0a0 ! sh3add %r1,%r1,%r1
x236: sh3add %r26,%r26,%r1 ! sh1add %r1,%r26,%r1 ! b e4t08a0 ! sh1add %r1,%r1,%r1
x237: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_3t0 ! sub %r1,%r26,%r1
x238: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e2t04a0 ! sh3add %r1,%r1,%r1
x239: zdep %r26,27,28,%r1 ! sh2add %r1,%r1,%r1 ! b e_t0ma0 ! sh1add %r1,%r1,%r1
x240: sh3add %r26,%r26,%r1 ! add %r1,%r26,%r1 ! b e_8t0 ! sh1add %r1,%r1,%r1
x241: sh3add %r26,%r26,%r1 ! add %r1,%r26,%r1 ! b e_8t0a0 ! sh1add %r1,%r1,%r1
x242: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_2t0 ! sh3add %r1,%r26,%r1
x243: sh3add %r26,%r26,%r1 ! sh3add %r1,%r1,%r1 ! b e_t0 ! sh1add %r1,%r1,%r1
x244: sh2add %r26,%r26,%r1 ! sh1add %r1,%r1,%r1 ! b e_4t0 ! sh2add %r1,%r26,%r1
x245: sh3add %r26,0,%r1 ! sh1add %r1,%r1,%r1 ! b e_5t0 ! sh1add %r1,%r26,%r1
x246: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_2t0 ! sh1add %r1,%r1,%r1
x247: sh2add %r26,%r26,%r1 ! sh3add %r1,%r26,%r1 ! b e_2t0a0 ! sh1add %r1,%r1,%r1
x248: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh3add %r1,%r29,%r29
x249: zdep %r26,26,27,%r1 ! sub %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r26,%r1
x250: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0 ! sh2add %r1,%r1,%r1
x251: sh2add %r26,%r26,%r1 ! sh2add %r1,%r1,%r1 ! b e_2t0a0 ! sh2add %r1,%r1,%r1
x252: zdep %r26,25,26,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh2add %r1,%r29,%r29
x253: zdep %r26,25,26,%r1 ! sub %r1,%r26,%r1 ! b e_t0 ! sh2add %r1,%r26,%r1
x254: zdep %r26,24,25,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29
x255: zdep %r26,23,24,%r1 ! comb,<> %r25,0,l0 ! sub %r1,%r26,%r1 ! b,n ret_t0
;1040 insts before this.
ret_t0: bv 0(r31)
e_t0: add %r29,%r1,%r29
e_shift: comb,<> %r25,0,l2
zdep %r26,23,24,%r26 ; %r26 <<= 8 ***********
bv,n 0(r31)
e_t0ma0: comb,<> %r25,0,l0
sub %r1,%r26,%r1
bv 0(r31)
add %r29,%r1,%r29
e_t0a0: comb,<> %r25,0,l0
add %r1,%r26,%r1
bv 0(r31)
add %r29,%r1,%r29
e_t02a0: comb,<> %r25,0,l0
sh1add %r26,%r1,%r1
bv 0(r31)
add %r29,%r1,%r29
e_t04a0: comb,<> %r25,0,l0
sh2add %r26,%r1,%r1
bv 0(r31)
add %r29,%r1,%r29
e_2t0: comb,<> %r25,0,l1
sh1add %r1,%r29,%r29
bv,n 0(r31)
e_2t0a0: comb,<> %r25,0,l0
sh1add %r1,%r26,%r1
bv 0(r31)
add %r29,%r1,%r29
e2t04a0: sh1add %r26,%r1,%r1
comb,<> %r25,0,l1
sh1add %r1,%r29,%r29
bv,n 0(r31)
e_3t0: comb,<> %r25,0,l0
sh1add %r1,%r1,%r1
bv 0(r31)
add %r29,%r1,%r29
e_4t0: comb,<> %r25,0,l1
sh2add %r1,%r29,%r29
bv,n 0(r31)
e_4t0a0: comb,<> %r25,0,l0
sh2add %r1,%r26,%r1
bv 0(r31)
add %r29,%r1,%r29
e4t08a0: sh1add %r26,%r1,%r1
comb,<> %r25,0,l1
sh2add %r1,%r29,%r29
bv,n 0(r31)
e_5t0: comb,<> %r25,0,l0
sh2add %r1,%r1,%r1
bv 0(r31)
add %r29,%r1,%r29
e_8t0: comb,<> %r25,0,l1
sh3add %r1,%r29,%r29
bv,n 0(r31)
e_8t0a0: comb,<> %r25,0,l0
sh3add %r1,%r26,%r1
bv 0(r31)
add %r29,%r1,%r29
.exit
.procend
.end
.import $$divI_2,millicode
.import $$divI_3,millicode
.import $$divI_4,millicode
.import $$divI_5,millicode
.import $$divI_6,millicode
.import $$divI_7,millicode
.import $$divI_8,millicode
.import $$divI_9,millicode
.import $$divI_10,millicode
.import $$divI_12,millicode
.import $$divI_14,millicode
.import $$divI_15,millicode
.export $$divI,millicode
.export $$divoI,millicode
$$divoI:
.proc
.callinfo millicode
.entry
comib,=,n -1,arg1,negative1 ; when divisor == -1
$$divI:
comib,>>=,n 15,arg1,small_divisor
add,>= 0,arg0,retreg ; move dividend, if retreg < 0,
normal1:
sub 0,retreg,retreg ; make it positive
sub 0,arg1,temp ; clear carry,
; negate the divisor
ds 0,temp,0 ; set V-bit to the comple-
; ment of the divisor sign
add retreg,retreg,retreg ; shift msb bit into carry
ds r0,arg1,temp ; 1st divide step, if no carry
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 2nd divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 3rd divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 4th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 5th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 6th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 7th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 8th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 9th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 10th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 11th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 12th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 13th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 14th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 15th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 16th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 17th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 18th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 19th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 20th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 21st divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 22nd divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 23rd divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 24th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 25th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 26th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 27th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 28th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 29th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 30th divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 31st divide step
addc retreg,retreg,retreg ; shift retreg with/into carry
ds temp,arg1,temp ; 32nd divide step,
addc retreg,retreg,retreg ; shift last retreg bit into retreg
xor,>= arg0,arg1,0 ; get correct sign of quotient
sub 0,retreg,retreg ; based on operand signs
bv,n 0(r31)
nop
;______________________________________________________________________
small_divisor:
blr,n arg1,r0
nop
; table for divisor == 0,1, ... ,15
addit,= 0,arg1,r0 ; trap if divisor == 0
nop
bv 0(r31) ; divisor == 1
copy arg0,retreg
b,n $$divI_2 ; divisor == 2
nop
b,n $$divI_3 ; divisor == 3
nop
b,n $$divI_4 ; divisor == 4
nop
b,n $$divI_5 ; divisor == 5
nop
b,n $$divI_6 ; divisor == 6
nop
b,n $$divI_7 ; divisor == 7
nop
b,n $$divI_8 ; divisor == 8
nop
b,n $$divI_9 ; divisor == 9
nop
b,n $$divI_10 ; divisor == 10
nop
b normal1 ; divisor == 11
add,>= 0,arg0,retreg
b,n $$divI_12 ; divisor == 12
nop
b normal1 ; divisor == 13
add,>= 0,arg0,retreg
b,n $$divI_14 ; divisor == 14
nop
b,n $$divI_15 ; divisor == 15
nop
;______________________________________________________________________
negative1:
sub 0,arg0,retreg ; result is negation of dividend
bv 0(r31)
addo arg0,arg1,r0 ; trap iff dividend==0x80000000 && divisor==-1
.exit
.procend
.subspa $LIT$
___hp_free_copyright:
.export ___hp_free_copyright,data
.align 4
.string "(c) Copyright 1986 HEWLETT-PACKARD COMPANY\x0aTo anyone who acknowledges that this file is provided \"AS IS\"\x0awithout any express or implied warranty:\x0a permission to use, copy, modify, and distribute this file\x0afor any purpose is hereby granted without fee, provided that\x0athe above copyright notice and this notice appears in all\x0acopies, and that the name of Hewlett-Packard Company not be\x0aused in advertising or publicity pertaining to distribution\x0aof the software without specific, written prior permission.\x0aHewlett-Packard Company makes no representations about the\x0asuitability of this software for any purpose.\x0a\x00"
.align 4
.end
|
stsp/newlib-ia16
| 2,774
|
libgloss/pa/crt0.S
|
/* crt0.S -- startup file for hppa.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
.VERSION "1.0"
.COPYRIGHT "crt0.o for the PA"
.DATA
/*
* Set up the standard spaces (sections) These definitions come
* from /lib/pcc_prefix.s.
*/
.TEXT
/*
* stuff we need that's defined elsewhere.
*/
.IMPORT main, CODE
.IMPORT exit, CODE
.IMPORT _bss_start, DATA
.IMPORT _end, DATA
.IMPORT environ, DATA
/*
* start -- set things up so the application will run.
*
*/
.PROC
.CALLINFO SAVE_SP, FRAME=48
.EXPORT $START$,ENTRY
$START$
/* FIXME: this writes to page zero */
;; setup the %30 (stack pointer) with some memory
ldil L%_stack,%r30
ldo R%_stack(%r30),%r30
;; we need to set %r27 (global data pointer) here too
ldil L%$global$,%r27
ldo R%$global$(%r27),%r27 ; same problem as above
/*
* zerobss -- zero out the bss section
*/
; load the start of bss
ldil L%_bss_start,%r4
ldo R%_bss_start(%r4),%r4
; load the end of bss
ldil L%_end,%r5
ldo R%_end(%r5),%r5
L$bssloop
addi -1,%r5,%r5 ; decrement _bss_end
stb %r0,0(0,%r5) ; we do this by bytes for now even
; though it's slower, it's safer
combf,= %r4,%r5, L$bssloop
nop
ldi 1,%ret0
/*
* Call the main routine from the application to get it going.
* main (argc, argv, environ)
* We pass argv as a pointer to NULL.
*/
ldil L%main,%r22
ble R%main(%sr4,%r22)
copy %r31,%r2
/*
* Call exit() from the C library with the return value from main()
*/
copy %r28,%r26
ldil L%exit,%r22
ble R%exit(%sr4,%r22)
copy %r31,%r2
.PROCEND
/*
* _exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run.
*/
.EXPORT _exit, ENTRY
_exit
.PROC
.CALLINFO
.ENTRY
;; This just causes a breakpoint exception
break 0x0,0x0
bv,n (%rp)
nop
.EXIT
.PROCEND
/*
* _sr4export -- support for called functions. (mostly for GDB)
*/
.EXPORT _sr4export, ENTRY
_sr4export:
.PROC
.CALLINFO
.ENTRY
ble 0(%sr4,%r22)
copy %r31,%rp
ldw -24(%sr0,%sp),%rp
ldsid (%sr0,%rp),%r1
mtsp %r1,%sr0
be,n 0(%sr0,%rp)
nop
.EXIT
.PROCEND
|
stsp/newlib-ia16
| 2,822
|
libgloss/pa/setjmp.S
|
/*
* Copyright (c) 1990,1994 The University of Utah and
* the Computer Systems Laboratory (CSL). All rights reserved.
*
* Permission to use, copy, modify and distribute this software is hereby
* granted provided that (1) source code retains these copyright, permission,
* and disclaimer notices, and (2) redistributions including binaries
* reproduce the notices in supporting documentation, and (3) all advertising
* materials mentioning features or use of this software display the following
* acknowledgement: ``This product includes software developed by the
* Computer Systems Laboratory at the University of Utah.''
*
* THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
* IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
* ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* CSL requests users of this software to return to csl-dist@cs.utah.edu any
* improvements that they make and grant CSL redistribution rights.
*
* Utah $Hdr: _setjmp.s 1.9 94/12/16$
*/
.space $TEXT$
.subspa $CODE$
/*
* The PA jmp_buf is 48 words arranged as follows:
*
* 0- 9: sigcontext
* 10-26: callee save GRs (r3-r18) and DP (r27)
* 27: callee save SRs (sr3)
* 28-47: callee save FRs (fr12-fr21)
*/
/*
* int
* setjmp(env)
* jmp_buf env;
*
* This routine does not restore signal state.
*/
.export setjmp,entry
.export _setjmp,entry
.proc
.callinfo
setjmp
_setjmp
.entry
/*
* save sp and rp in sigcontext, skip the rest
*/
stw %r30,8(%r26)
stw %r2,24(%r26)
ldo 40(%r26),%r26
/*
* save dp and the callee saves registers
*/
stwm %r3,4(%r26)
stwm %r4,4(%r26)
stwm %r5,4(%r26)
stwm %r6,4(%r26)
stwm %r7,4(%r26)
stwm %r8,4(%r26)
stwm %r9,4(%r26)
stwm %r10,4(%r26)
stwm %r11,4(%r26)
stwm %r12,4(%r26)
stwm %r13,4(%r26)
stwm %r14,4(%r26)
stwm %r15,4(%r26)
stwm %r16,4(%r26)
stwm %r17,4(%r26)
stwm %r18,4(%r26)
stwm %r27,4(%r26)
mfsp %sr3,%r9
stwm %r9,4(%r26)
bv 0(%r2)
copy %r0,%r28
.exit
.procend
/*
* void
* longjmp(env, val)
* jmp_buf env;
* int val;
*
* This routine does not retore signal state.
* This routine does not override a zero val.
*/
.export longjmp,entry
.export _longjmp,entry
.proc
.callinfo
longjmp
_longjmp
.entry
/*
* restore sp and rp
*/
ldw 8(%r26),%r30
ldw 24(%r26),%r2
ldo 40(%r26),%r26
/*
* restore callee saves registers
*/
ldwm 4(%r26),%r3
ldwm 4(%r26),%r4
ldwm 4(%r26),%r5
ldwm 4(%r26),%r6
ldwm 4(%r26),%r7
ldwm 4(%r26),%r8
ldwm 4(%r26),%r9
ldwm 4(%r26),%r10
ldwm 4(%r26),%r11
ldwm 4(%r26),%r12
ldwm 4(%r26),%r13
ldwm 4(%r26),%r14
ldwm 4(%r26),%r15
ldwm 4(%r26),%r16
ldwm 4(%r26),%r17
ldwm 4(%r26),%r18
ldwm 4(%r26),%r27
ldwm 4(%r26),%r9
mtsp %r9,%sr3
bv 0(%r2)
copy %r25,%r28
.exit
.procend
|
stsp/newlib-ia16
| 1,701
|
libgloss/rs6000/simulator.S
|
/*
* simulator.S -- PowerPC simulator system calls.
*
* Copyright (c) 1995, 2000, 2001 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "ppc-asm.h"
FUNC_START(_exit)
li r0, 1
sc
/*
* Insure that the debugger tells the client that the PC is in _exit,
* not whatever function happens to follow this function.
*/
0: trap
b 0b /* we never should return, but... */
FUNC_END(_exit)
FUNC_START(read)
li r0,3
sc
bnslr+
b FUNC_NAME(_cerror)
FUNC_END(read)
FUNC_START(write)
li r0,4
sc
bnslr+
b FUNC_NAME(_cerror)
FUNC_END(write)
FUNC_START(open)
li r0,5
sc
bnslr+
b FUNC_NAME(_cerror)
FUNC_END(open)
FUNC_START(close)
li r0,6
sc
bnslr+
b FUNC_NAME(_cerror)
FUNC_END(close)
FUNC_START(brk)
li r0,17
sc
bnslr+
b FUNC_NAME(_cerror)
FUNC_END(brk)
FUNC_START(access)
li r0,33
sc
bnslr+
b FUNC_NAME(_cerror)
FUNC_END(access)
FUNC_START(dup)
li r0,41
sc
bnslr+
b FUNC_NAME(_cerror)
FUNC_END(dup)
FUNC_START(gettimeofday)
li r0,116
sc
bns+ 0f
b FUNC_NAME(_cerror)
0: blr
FUNC_END(gettimeofday)
FUNC_START(lseek)
li r0,199
sc
bnslr+
b FUNC_NAME(_cerror)
FUNC_END(lseek)
|
stsp/newlib-ia16
| 1,355
|
libgloss/rs6000/sim-crt0.S
|
/*
* crt0.S -- startup file for PowerPC systems.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "ppc-asm.h"
.file "sim-crt0.S"
.text
.globl _start
.type _start,@function
_start:
lis r0,0
stw r0,0(sp) /* clear back chain */
stwu sp,-64(sp) /* push another stack frame */
/* Let her rip */
bl FUNC_NAME(main)
/* return value from main is argument to exit */
bl FUNC_NAME(exit)
.Lstart:
.size _start,.Lstart-_start
.extern FUNC_NAME(atexit)
.globl FUNC_NAME(__atexit)
.section ".sdata","aw"
.align 2
FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */
.long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */
.section ".fixup","aw"
.align 2
.long FUNC_NAME(__atexit)
|
stsp/newlib-ia16
| 7,072
|
libgloss/rs6000/sol-syscall.S
|
/*
* solaris-syscall.S -- System call stubs for Solaris.
*
* Copyright (c) 1996 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "ppc-asm.h"
.file "solaris-syscall.S"
#define SYS_syscall 0
#define SYS_exit 1
#define SYS_fork 2
#define SYS_read 3
#define SYS_write 4
#define SYS_open 5
#define SYS_close 6
#define SYS_wait 7
#define SYS_creat 8
#define SYS_link 9
#define SYS_unlink 10
#define SYS_exec 11
#define SYS_chdir 12
#define SYS_time 13
#define SYS_mknod 14
#define SYS_chmod 15
#define SYS_chown 16
#define SYS_brk 17
#define SYS_stat 18
#define SYS_lseek 19
#define SYS_getpid 20
#define SYS_mount 21
#define SYS_umount 22
#define SYS_setuid 23
#define SYS_getuid 24
#define SYS_stime 25
#define SYS_ptrace 26
#define SYS_alarm 27
#define SYS_fstat 28
#define SYS_pause 29
#define SYS_utime 30
#define SYS_stty 31
#define SYS_gtty 32
#define SYS_access 33
#define SYS_nice 34
#define SYS_statfs 35
#define SYS_sync 36
#define SYS_kill 37
#define SYS_fstatfs 38
#define SYS_pgrpsys 39
#define SYS_xenix 40
#define SYS_dup 41
#define SYS_pipe 42
#define SYS_times 43
#define SYS_profil 44
#define SYS_plock 45
#define SYS_setgid 46
#define SYS_getgid 47
#define SYS_signal 48
#define SYS_msgsys 49
#define SYS_syssun 50
#define SYS_sysi86 50
#define SYS_sysppc 50
#define SYS_acct 51
#define SYS_shmsys 52
#define SYS_semsys 53
#define SYS_ioctl 54
#define SYS_uadmin 55
#define SYS_utssys 57
#define SYS_fdsync 58
#define SYS_execve 59
#define SYS_umask 60
#define SYS_chroot 61
#define SYS_fcntl 62
#define SYS_ulimit 63
#define SYS_rmdir 79
#define SYS_mkdir 80
#define SYS_getdents 81
#define SYS_sysfs 84
#define SYS_getmsg 85
#define SYS_putmsg 86
#define SYS_poll 87
#define SYS_lstat 88
#define SYS_symlink 89
#define SYS_readlink 90
#define SYS_setgroups 91
#define SYS_getgroups 92
#define SYS_fchmod 93
#define SYS_fchown 94
#define SYS_sigprocmask 95
#define SYS_sigsuspend 96
#define SYS_sigaltstack 97
#define SYS_sigaction 98
#define SYS_sigpending 99
#define SYS_context 100
#define SYS_evsys 101
#define SYS_evtrapret 102
#define SYS_statvfs 103
#define SYS_fstatvfs 104
#define SYS_nfssys 106
#define SYS_waitsys 107
#define SYS_sigsendsys 108
#define SYS_hrtsys 109
#define SYS_acancel 110
#define SYS_async 111
#define SYS_priocntlsys 112
#define SYS_pathconf 113
#define SYS_mincore 114
#define SYS_mmap 115
#define SYS_mprotect 116
#define SYS_munmap 117
#define SYS_fpathconf 118
#define SYS_vfork 119
#define SYS_fchdir 120
#define SYS_readv 121
#define SYS_writev 122
#define SYS_xstat 123
#define SYS_lxstat 124
#define SYS_fxstat 125
#define SYS_xmknod 126
#define SYS_clocal 127
#define SYS_setrlimit 128
#define SYS_getrlimit 129
#define SYS_lchown 130
#define SYS_memcntl 131
#define SYS_getpmsg 132
#define SYS_putpmsg 133
#define SYS_rename 134
#define SYS_uname 135
#define SYS_setegid 136
#define SYS_sysconfig 137
#define SYS_adjtime 138
#define SYS_systeminfo 139
#define SYS_seteuid 141
#define SYS_vtrace 142
#define SYS_fork1 143
#define SYS_sigtimedwait 144
#define SYS_lwp_info 145
#define SYS_yield 146
#define SYS_lwp_sema_wait 147
#define SYS_lwp_sema_post 148
#define SYS_modctl 152
#define SYS_fchroot 153
#define SYS_utimes 154
#define SYS_vhangup 155
#define SYS_gettimeofday 156
#define SYS_getitimer 157
#define SYS_setitimer 158
#define SYS_lwp_create 159
#define SYS_lwp_exit 160
#define SYS_lwp_suspend 161
#define SYS_lwp_continue 162
#define SYS_lwp_kill 163
#define SYS_lwp_self 164
#define SYS_lwp_setprivate 165
#define SYS_lwp_getprivate 166
#define SYS_lwp_wait 167
#define SYS_lwp_mutex_unlock 168
#define SYS_lwp_mutex_lock 169
#define SYS_lwp_cond_wait 170
#define SYS_lwp_cond_signal 171
#define SYS_lwp_cond_broadcast 172
#define SYS_pread 173
#define SYS_pwrite 174
#define SYS_llseek 175
#define SYS_inst_sync 176
#define SYS_kaio 178
#define SYS_tsolsys 184
#define SYS_acl 185
#define SYS_auditsys 186
#define SYS_processor_bind 187
#define SYS_processor_info 188
#define SYS_p_online 189
#define SYS_sigqueue 190
#define SYS_clock_gettime 191
#define SYS_clock_settime 192
#define SYS_clock_getres 193
#define SYS_timer_create 194
#define SYS_timer_delete 195
#define SYS_timer_settime 196
#define SYS_timer_gettime 197
#define SYS_timer_getoverrun 198
#define SYS_nanosleep 199
#define SYS_facl 200
#define SYS_door 201
#define SYS_setreuid 202
#define SYS_setregid 203
#define SYS_install_utrap 204
#define SYS_signotifywait 210
#define SYS_lwp_sigredirect 211
#define SYS_lwp_alarm 212
.text
FUNC_START(_exit)
li r0,SYS_exit
sc
/*
* Insure that the debugger tells the client that the PC is in _exit,
* not whatever function happens to follow this function.
*/
0: trap
b 0b /* we never should return, but... */
FUNC_END(_exit)
#define SYSCALL(syscall,name) \
FUNC_START(name); \
li r0,syscall; \
sc; \
bns+ 0f; \
b FUNC_NAME(_cerror); \
0: blr; \
FUNC_END(name)
SYSCALL(SYS_access,access)
SYSCALL(SYS_alarm,alarm)
SYSCALL(SYS_brk,brk)
SYSCALL(SYS_chdir,chdir)
SYSCALL(SYS_chmod,chomd)
SYSCALL(SYS_chown,chown)
SYSCALL(SYS_close,close)
SYSCALL(SYS_creat,creat)
SYSCALL(SYS_dup,dup)
SYSCALL(SYS_exec,exec)
SYSCALL(SYS_fork,fork)
SYSCALL(SYS_fstat,_fstat)
SYSCALL(SYS_getpid,getpid)
SYSCALL(SYS_ioctl,ioctl)
SYSCALL(SYS_kill,kill)
SYSCALL(SYS_link,link)
SYSCALL(SYS_lseek,lseek)
SYSCALL(SYS_nice,nice)
SYSCALL(SYS_open,open)
SYSCALL(SYS_pause,pause)
SYSCALL(SYS_pipe,pipe)
SYSCALL(SYS_ptrace,ptrace)
SYSCALL(SYS_read,read)
SYSCALL(SYS_signal,signal)
SYSCALL(SYS_stat,_stat)
SYSCALL(SYS_sync,sync)
SYSCALL(SYS_sysppc,sysppc)
SYSCALL(SYS_time,time)
SYSCALL(SYS_times,times)
SYSCALL(SYS_unlink,unlink)
SYSCALL(SYS_wait,wait)
SYSCALL(SYS_write,write)
SYSCALL(SYS_umask,umask)
SYSCALL(SYS_execve,execve)
SYSCALL(SYS_fcntl,fcntl)
SYSCALL(SYS_ulimit,ulimit)
SYSCALL(SYS_mkdir,mkdir)
SYSCALL(SYS_rmdir,rmdir)
SYSCALL(SYS_getdents,getdents)
SYSCALL(SYS_lstat,_lstat)
SYSCALL(SYS_symlink,symlink)
SYSCALL(SYS_readlink,readlink)
SYSCALL(SYS_sigprocmask,sigprocmask)
SYSCALL(SYS_sigsuspend,sigsuspend)
SYSCALL(SYS_sigaction,sigaction)
SYSCALL(SYS_mmap,mmap)
SYSCALL(SYS_mprotect,mprotect)
SYSCALL(SYS_munmap,munmap)
SYSCALL(SYS_fpathconf,fpathconf)
SYSCALL(SYS_vfork,vfork)
SYSCALL(SYS_setrlimit,setrlimit)
SYSCALL(SYS_getrlimit,getrlimit)
SYSCALL(SYS_rename,rename)
SYSCALL(SYS_utimes,utimes)
SYSCALL(SYS_gettimeofday,gettimeofday)
|
stsp/newlib-ia16
| 3,331
|
libgloss/rs6000/crt0.S
|
/*
* crt0.S -- startup file for PowerPC systems.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "ppc-asm.h"
.file "crt0.S"
.section ".got2","aw"
.align 2
.LCTOC1 = .+32768
.extern FUNC_NAME(atexit)
.globl FUNC_NAME(__atexit)
.section ".sdata","aw"
.align 2
FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */
.long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */
.section ".fixup","aw"
.align 2
.long FUNC_NAME(__atexit)
.section ".got2","aw"
.Ltable = .-.LCTOC1
.long .LCTOC1 /* address we think .LCTOC1 is loaded at */
.Lsbss_start = .-.LCTOC1
.long __sbss_start
.Lsbss_end = .-.LCTOC1
.long __sbss_end
.Lbss_start = .-.LCTOC1
.long __bss_start
.Lend = .-.LCTOC1
.long _end
.Lstack = .-.LCTOC1 /* stack address if set by user */
.long __stack
.text
.Lptr:
.long .LCTOC1-.Laddr
.globl _start
.type _start,@function
_start:
bl .Laddr /* get current address */
.Laddr:
mflr r4 /* real address of .Laddr */
lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */
add r5,r5,r4 /* correct to real pointer */
lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */
subf r4,r4,r5 /* calculate difference between where linked and current */
/* clear bss and sbss */
lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */
lwz r7,.Lend(r5) /* calculate end of the BSS */
add r6,r6,r4 /* adjust pointers */
add r7,r7,r4
cmplw 1,r6,r7
bc 4,4,.Ldone1
subf r8,r6,r7 /* number of bytes to zero */
srwi r9,r8,2 /* number of words to zero */
mtctr r9
li r0,0 /* zero to clear memory */
addi r6,r6,-4 /* adjust so we can use stwu */
.Lloop:
stwu r0,4(r6) /* zero bss */
bdnz .Lloop
.Ldone1:
lwz r6,.Lsbss_start(r5) /* calculate beginning of the SBSS */
lwz r7,.Lsbss_end(r5) /* calculate end of the SBSS */
add r6,r6,r4 /* adjust pointers */
add r7,r7,r4
cmplw 1,r6,r7
bc 4,4,.Ldone
subf r8,r6,r7 /* number of bytes to zero */
srwi r9,r8,2 /* number of words to zero */
mtctr r9
li r0,0 /* zero to clear memory */
addi r6,r6,-4 /* adjust so we can use stwu */
.Lloop2:
stwu r0,4(r6) /* zero bss */
bdnz .Lloop2
.Ldone:
lwz r0,.Lstack(r5) /* stack address or 0 */
cmplwi 1,r0,0 /* equal to 0? */
bc 12,6,.Lnostack /* use default stack if == 0 */
mr sp,r0 /* use user defined stack */
.Lnostack:
/* set up initial stack frame */
addi sp,sp,-4 /* make sure we don't overwrite debug mem */
lis r0,0
stw r0,0(sp) /* clear back chain */
stwu sp,-64(sp) /* push another stack frame */
/* Let her rip */
bl FUNC_NAME(main)
/* return value from main is argument to exit */
bl FUNC_NAME(exit)
trap
.Lstart:
.size _start,.Lstart-_start
|
stsp/newlib-ia16
| 5,580
|
libgloss/rs6000/xil-crt0.S
|
/*-----------------------------------------------------------------------------
//
// Copyright (c) 2004, 2009 Xilinx, Inc. All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// 1. Redistributions source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of Xilinx nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//---------------------------------------------------------------------------*/
.file "xil-crt0.S"
.section ".got2","aw"
.align 2
.LCTOC1 = . + 32768
.Lsbss_start = .-.LCTOC1
.long __sbss_start
.Lsbss_end = .-.LCTOC1
.long __sbss_end
.Lbss_start = .-.LCTOC1
.long __bss_start
.Lbss_end = .-.LCTOC1
.long __bss_end
.Lstack = .-.LCTOC1
.long __stack
.Lsda = .-.LCTOC1
.long _SDA_BASE_ /* address of the first small data area */
.Lsda2 = .-.LCTOC1
.long _SDA2_BASE_ /* address of the second small data area */
.text
.globl _start
_start:
bl __cpu_init /* Initialize the CPU first (BSP provides this) */
lis 5,.LCTOC1@h
ori 5,5,.LCTOC1@l
lwz 13,.Lsda(5) /* load r13 with _SDA_BASE_ address */
lwz 2,.Lsda2(5) /* load r2 with _SDA2_BASE_ address */
#ifndef SIMULATOR
/* clear sbss */
lwz 6,.Lsbss_start(5) /* calculate beginning of the SBSS */
lwz 7,.Lsbss_end(5) /* calculate end of the SBSS */
cmplw 1,6,7
bc 4,4,.Lenclsbss /* If no SBSS, no clearing required */
li 0,0 /* zero to clear memory */
subf 8,6,7 /* number of bytes to zero */
srwi. 9,8,2 /* number of words to zero */
beq .Lstbyteloopsbss /* Check if the number of bytes was less than 4 */
mtctr 9
addi 6,6,-4 /* adjust so we can use stwu */
.Lloopsbss:
stwu 0,4(6) /* zero sbss */
bdnz .Lloopsbss
.Lstbyteloopsbss:
andi. 9,8,3 /* Calculate how many trailing bytes we have */
beq 0,.Lenclsbss
mtctr 9
addi 6,6,-1 /* adjust, so we can use stbu */
.Lbyteloopsbss:
stbu 0,1(6)
bdnz .Lbyteloopsbss
.Lenclsbss:
.Lstclbss:
/* clear bss */
lwz 6,.Lbss_start(5) /* calculate beginning of the BSS */
lwz 7,.Lbss_end(5) /* calculate end of the BSS */
cmplw 1,6,7
bc 4,4,.Lenclbss /* If no BSS, no clearing required */
li 0,0 /* zero to clear memory */
subf 8,6,7 /* number of bytes to zero */
srwi. 9,8,2 /* number of words to zero */
beq .Lstbyteloopbss /* Check if the number of bytes was less than 4 */
mtctr 9
addi 6,6,-4 /* adjust so we can use stwu */
.Lloopbss:
stwu 0,4(6) /* zero bss */
bdnz .Lloopbss
.Lstbyteloopbss:
andi. 9,8,3 /* Calculate how many trailing bytes we have */
beq 0,.Lenclbss /* If zero, we are done */
mtctr 9
addi 6,6,-1 /* adjust, so we can use stbu */
.Lbyteloopbss:
stbu 0,1(6)
bdnz .Lbyteloopbss
.Lenclbss:
#endif /* SIMULATOR */
/* set stack pointer */
lwz 1,.Lstack(5) /* stack address */
/* set up initial stack frame */
addi 1,1,-8 /* location of back chain */
lis 0,0
stw 0,0(1) /* set end of back chain */
/* initialize base timer to zero */
mtspr 0x11c,0
mtspr 0x11d,0
#ifdef HAVE_XFPU
/* On the Xilinx PPC405 and PPC440, the MSR
must be explicitly set to mark the prescence
of an FPU */
mfpvr 0
rlwinm 0,0,0,12,15
cmpwi 7,0,8192
mfmsr 0
ori 0,0,8192
beq- 7,fpu_init_done
do_405:
oris 0,0,512
fpu_init_done:
mtmsr 0
#endif
#ifdef PROFILING
/* Setup profiling stuff */
bl _profile_init
#endif /* PROFILING */
/* Call __init */
bl __init
/* Let her rip */
bl main
/* Invoke the language cleanup functions */
bl __fini
#ifdef PROFILING
/* Cleanup profiling stuff */
bl _profile_clean
#endif /* PROFILING */
/* Call __init */
/* All done */
bl exit
/* Trap has been removed for both simulation and hardware */
.globl _exit
_exit:
b _exit
.Lstart:
.size _start,.Lstart-_start
|
stsp/newlib-ia16
| 1,030
|
libgloss/rs6000/mvme-outbyte.S
|
/*
* mvme-outbyte.S -- outbyte function for targets using the ppcbug monitor
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "ppc-asm.h"
.file "mvme-outbyte.S"
.text
FUNC_START(outbyte)
li r10,0x20
sc
blr
FUNC_END(outbyte)
FUNC_START(__outstr)
li r10,0x21
sc
blr
FUNC_END(__outstr)
FUNC_START(__outln)
li r10,0x22
sc
blr
FUNC_END(__outln)
FUNC_START(__pcrlf)
li r10,0x26
sc
blr
FUNC_END(__pcrlf)
|
stsp/newlib-ia16
| 3,363
|
libgloss/m68k/mvme.S
|
/* mvme.S -- board support for m68k
*
* Copyright (c) 1995, 1996 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
.title "mvme.S for m68k-coff"
.align 2
.text
.global SYM (_exit)
.global SYM (outln)
.global SYM (outbyte)
.global SYM (putDebugChar)
.global SYM (inbyte)
.global SYM (getDebugChar)
.global SYM (havebyte)
.global SYM (exceptionHandler)
.set vbr_size, 0x400
.comm SYM (vbr_table), vbr_size
/*
* _exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run.
*/
SYM (_exit):
unlk a6
trap IMM(15)
.word return
.align 2
/*
* inbyte -- get a byte from the serial port
* d0 - contains the byte read in
*/
.align 2
SYM (getDebugChar): /* symbol name used by m68k-stub */
SYM (inbyte):
link a6, IMM(-8)
trap IMM(15)
.word inchr
moveb sp@, d0
extw d0
extl d0
unlk a6
rts
/*
* outbyte -- sends a byte out the serial port
* d0 - contains the byte to be sent
*/
.align 2
SYM (putDebugChar): /* symbol name used by m68k-stub */
SYM (outbyte):
link fp, IMM(-4)
moveb fp@(11), sp@
trap IMM(15)
.word outchr
unlk fp
rts
/*
* outln -- sends a string of bytes out the serial port with a CR/LF
* a0 - contains the address of the string's first byte
* a1 - contains the address of the string's last byte
*/
.align 2
SYM (outln):
link a6, IMM(-8)
moveml a0/a1, sp@
trap IMM(15)
.word outln
unlk a6
rts
/*
* outstr -- sends a string of bytes out the serial port without a CR/LF
* a0 - contains the address of the string's first byte
* a1 - contains the address of the string's last byte
*/
.align 2
SYM (outstr):
link a6, IMM(-8)
moveml a0/a1, sp@
trap IMM(15)
.word outstr
unlk a6
rts
/*
* havebyte -- checks to see if there is a byte in the serial port,
* returns 1 if there is a byte, 0 otherwise.
*/
SYM (havebyte):
trap IMM(15)
.word instat
beqs empty
movel IMM(1), d0
rts
empty:
movel IMM(0), d0
rts
/*
* These constants are for the MVME-135 board's boot monitor. They
* are used with a TRAP 15 call to access the monitor's I/O routines.
* they must be in the word following the trap call.
*/
.set inchr, 0x0
.set instat, 0x1
.set inln, 0x2
.set readstr, 0x3
.set readln, 0x4
.set chkbrk, 0x5
.set outchr, 0x20
.set outstr, 0x21
.set outln, 0x22
.set write, 0x23
.set writeln, 0x24
.set writdln, 0x25
.set pcrlf, 0x26
.set eraseln, 0x27
.set writd, 0x28
.set sndbrk, 0x29
.set tm_ini, 0x40
.set dt_ini, 0x42
.set tm_disp, 0x43
.set tm_rd, 0x44
.set redir, 0x60
.set redir_i, 0x61
.set redir_o, 0x62
.set return, 0x63
.set bindec, 0x64
.set changev, 0x67
.set strcmp, 0x68
.set mulu32, 0x69
.set divu32, 0x6A
.set chk_sum, 0x6B
|
stsp/newlib-ia16
| 1,693
|
libgloss/m68k/simulator.S
|
/*
* simulator.S -- m68k simulator system calls.
*
* Copyright (c) 1995, 2001 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
#define SYSCALL(x) .word 0x4afc, x
#define FUNC_START(x) .globl x; x:
#define FUNC_END(x)
#define FUNC_NAME(x) SYM(x)
FUNC_START(_exit)
SYSCALL(1)
/*
* Insure that the debugger tells the client that the PC is in _exit,
* not whatever function happens to follow this function.
*/
0: nop
jmp 0b /* we never should return, but... */
FUNC_END(_exit)
FUNC_START(read)
SYSCALL(3)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(read)
FUNC_START(write)
SYSCALL(4)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(write)
FUNC_START(open)
SYSCALL(5)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(open)
FUNC_START(close)
SYSCALL(6)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(close)
FUNC_START(brk)
SYSCALL(17)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(brk)
FUNC_START(lseek)
SYSCALL(199)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(lseek)
FUNC_START(fstat)
SYSCALL(28)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(lseek)
FUNC_START(isatty)
SYSCALL(29)
bcs FUNC_NAME(_cerror)
rts
FUNC_END(isatty)
|
stsp/newlib-ia16
| 2,780
|
libgloss/m68k/sim-crt0.S
|
/*
* crt0.S -- startup file for m68k-coff
*
* Copyright (c) 1995, 1996, 1998, 2001 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "asm.h"
.title "crt0.S for m68k-coff"
#define STACKSIZE 0x4000
/*
* Define an empty environment.
*/
.data
.align 2
SYM (environ):
.long 0
.align 2
.text
/*
* These symbols are defined in C code, so they need to always be
* named with SYM because of the difference between object file formats.
*/
/* These are defined in C code. */
.extern SYM (main)
.extern SYM (exit)
.extern SYM (atexit)
.extern SYM(__do_global_dtors)
/*
* These values are set in the linker script, so they must be
* explicitly named here without SYM.
*/
.extern __stack
.extern __bss_start
.extern _end
/*
* set things up so the application will run. This *must* be called start.
*/
.global SYM (start)
SYM (start):
/* See if user supplied their own stack (__stack != 0). If not, then
* default to using the value of %sp as set by the ROM monitor.
*/
movel IMM(__stack), a0
cmpl IMM(0), a0
jbeq 1f
movel a0, sp
1:
/* set up initial stack frame */
link a6, IMM(-8)
/*
* zero out the bss section.
*/
movel IMM(__bss_start), d1
movel IMM(_end), d0
cmpl d0, d1
jbeq 3f
movl d1, a0
subl d1, d0
subql IMM(1), d0
2:
clrb (a0)+
#if !defined(__mcoldfire__) && !defined(__mcf5200__)
dbra d0, 2b
clrw d0
subql IMM(1), d0
jbcc 2b
#else
subql IMM(1), d0
jbpl 2b
#endif
3:
/*
* call the main routine from the application to get it going.
* main (argc, argv, environ)
* we pass argv as a pointer to NULL.
*/
#ifdef ADD_DTORS
/* put __do_global_dtors in the atexit list so the destructors get run */
movel IMM (SYM(__do_global_dtors)),(sp)
PICCALL SYM (atexit)
#endif
movel IMM (__FINI_SECTION__),(sp)
PICCALL SYM (atexit)
PICCALL __INIT_SECTION__
pea 0
PICPEA SYM (environ),a0
pea sp@(4)
pea 0
PICCALL SYM (main)
movel d0, sp@-
/*
* drop down into exit incase the user doesn't. This should drop
* control back to the ROM monitor, if there is one. This calls the
* exit() from the C library so the C++ tables get cleaned up right.
*/
PICCALL SYM (exit)
|
stsp/newlib-ia16
| 14,877
|
libgloss/m68k/mvme135-asm.S
|
/*
* mvme135-asm.S -- assembler routines for the MVME stub.
*
* This code was pulled out of mvme135-stub.c by Ian Taylor so that I
* could handle different register and label prefixes in a sensible
* way.
*/
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
#include "asm.h"
.title "mvme135-asm.S for m68k"
.globl SYM (registers)
.globl SYM (lastFrame)
.globl SYM (superStack)
.globl SYM (exceptionHook)
.globl SYM (_returnFromException)
.globl SYM (stackPtr)
.globl SYM (handle_exception)
.globl SYM (exceptionSize)
.globl SYM (exceptionHandler)
.text
/*
* Create a new exception vector table and populates it. Vectors from the
* boot monitor are spliced in so I/O and the abort button will continue
* to work. We also use the monitor's generalized vector for anything the
* debugger doesn't want.
*/
.global SYM (setup_vectors)
SYM (setup_vectors):
link fp, IMM (-8)
/* copy monitor vector table */
movecl vbr, a0
lea SYM (vbr_table), a1
movel 0x8(a0), d0 /* get generalized vector */
movew IMM (0x3fc), d1 /* load vector count */
loop: /* fill table to gen. vector */
movel d0, (a1,d1)
subqw IMM (4), d1
bne loop
movel 0x10(a0), 0x10(a1) /* breakpoint */
movel 0x24(a0), 0x24(a1) /* trace */
movel 0xbc(a0), 0xbc(a1) /* system call */
/* add stub vectors to table */
movel SYM (_catchException), 0x8(a1) /* vector = 2, Access Fault */
movel SYM (_catchException), 0xc(a1) /* vector = 3, Address Error */
movel SYM (_catchException), 0x10(a1) /* vector = 4, Illegal instruction */
movel SYM (_catchException), 0x14(a1) /* vector = 5, divide by 0 */
movel SYM (_catchException), 0x18(a1) /* vector = 6, chk, chk2 instruction */
movel SYM (_catchException), 0x1c(a1) /* vector = 7, ftrap, trap, trapv ins */
movel SYM (_catchException), 0x20(a1) /* vector = 8, priviledge violation */
movel SYM (_catchException), 0x24(a1) /* vector = 9, trace */
movel SYM (_catchException), 0x28(a1) /* vector = 10, Aline opcode */
movel SYM (_catchException), 0x2c(a1) /* vector = 11, fline opcode */
movel SYM (_catchException), 0x30(a1) /* vector = 12, reserved */
movel SYM (_catchException), 0x34(a1) /* vector = 13, coprocessor protocol violation */
movel SYM (_catchException), 0x38(a1) /* vector = 14, format error */
movel SYM (_catchException), 0x3c(a1) /* vector = 15, unitialized interupt */
/* unassigned, reserved */
movel SYM (_catchException), 0x40(a1) /* vector = 16 */
movel SYM (_catchException), 0x44(a1) /* vector = 17 */
movel SYM (_catchException), 0x48(a1) /* vector = 18 */
movel SYM (_catchException), 0x4c(a1) /* vector = 19 */
movel SYM (_catchException), 0x50(a1) /* vector = 20 */
movel SYM (_catchException), 0x54(a1) /* vector = 21 */
movel SYM (_catchException), 0x58(a1) /* vector = 22 */
movel SYM (_catchException), 0x5c(a1) /* vector = 23 */
movel SYM (_catchException), 0x84(a1) /* vector = 33, breakpoint, trap #1 */
movel SYM (_catchException), 0xa0(a1) /* vector = 40 , trap #8*/
/* floating point traps */
movel SYM (_catchException), 0xc0(a1) /* vector = 48 */
movel SYM (_catchException), 0xc4(a1) /* vector = 49 */
movel SYM (_catchException), 0xc8(a1) /* vector = 50 */
movel SYM (_catchException), 0xcc(a1) /* vector = 51 */
movel SYM (_catchException), 0xd0(a1) /* vector = 52 */
movel SYM (_catchException), 0xd4(a1) /* vector = 53 */
movel SYM (_catchException), 0xd8(a1) /* vector = 54 */
movel SYM (_catchException), 0xdc(a1) /* vector = 55 */
movel SYM (_catchException), 0xe0(a1) /* vector = 56 */
movel SYM (_catchException), 0xe4(a1) /* vector = 57 */
movel SYM (_catchException), 0xe8(a1) /* vector = 58 */
/*** movel &__debug_level7, 0x7c(a1) /* level7 interupt vector */
movecl a1, vbr /* change VBR to new table */
unlk fp
rts
/*
* exceptionHandler -- sets up exception vector table.
* First arg is an integer vector number
* Second arg is the function pointer for the vector
*/
SYM (exceptionHandler):
# link a6, IMM (-8)
#str1: .ascii "Exception Handler Called\n"
# moveal IMM (str1), a0
# moveal IMM (str1+25), a1
# jsr SYM (outln)
# unlk a6
rts
/* this never gets called */
movel fp@(8), d0 /* get vector number */
movel fp@(12), a0 /* get function address */
moveal &SYM (vbr_table), a1 /* FIXME */
addl d0, d0
addl d0, d0
addal d0, a1
movel a0, (a1)
movecl a1, vbr
unlk a6
rts
.globl SYM (return_to_super)
SYM (return_to_super):
movel SYM (registers)+60,sp /* get new stack pointer */
movel SYM (lastFrame),a0 /* get last frame info */
bra return_to_any
.globl SYM (return_to_user)
SYM (return_to_user):
movel SYM (registers)+60,a0 /* get usp */
movel a0,usp /* set usp */
movel SYM (superStack),sp /* get original stack pointer */
return_to_any:
movel SYM (lastFrame),a0 /* get last frame info */
movel a0@+,SYM (lastFrame) /* link in previous frame */
addql IMM (8),a0 /* skip over pc, vector#*/
movew a0@+,d0 /* get # of words in cpu frame */
addw d0,a0 /* point to end of data */
addw d0,a0 /* point to end of data */
movel a0,a1
/* copy the stack frame */
subql IMM (1),d0
copyUserLoop:
movew a1@-,sp@-
dbf d0,copyUserLoop
#ifdef __HAVE_68881__
fmoveml SYM (registers)+168,fpcr/fpsr/fpi
fmovemx SYM (registers)+72,fp0-fp7
cmpl IMM (-1),a0@ /* skip frestore flag set ? */
beq skip_frestore
frestore a0@+
skip_frestore:
#endif
moveml SYM (registers),d0-d7/a0-a6
rte /* pop and go! */
/* this function is called immediately when a level 7 interrupt occurs */
/* if the previous interrupt level was 7 then we're already servicing */
/* this interrupt and an rte is in order to return to the debugger. */
/* For the 68000, the offset for sr is 6 due to the jsr return address */
.text
.globl SYM (_debug_level7)
SYM (_debug_level7):
movew d0,sp@-
#ifdef mc68020
movew sp@(2),d0
#else
movew sp@(6),d0
#endif
andiw IMM (0x700),d0
cmpiw IMM (0x700),d0
beq _already7
movew sp@+,d0
bra SYM (_catchException)
_already7:
movew sp@+,d0
#ifndef mc68020
lea sp@(4),sp /* pull off 68000 return address */
#endif
rte
#ifdef mc68020
/* This function is called when a 68020 exception occurs. It saves
* all the cpu and fpcp regs in the _registers array, creates a frame on a
* linked list of frames which has the cpu and fpcp stack frames needed
* to properly restore the context of these processors, and invokes
* an exception handler (remcom_handler).
*
* stack on entry: stack on exit:
* N bytes of junk exception # MSWord
* Exception Format Word exception # MSWord
* Program counter LSWord
* Program counter MSWord
* Status Register
*
*
*/
.text
.globl SYM (_catchException)
SYM (_catchException):
oriw IMM (0x0700),sr /* Disable interrupts */
moveml d0-d7/a0-a6,SYM (registers) /* save registers */
movel SYM (lastFrame),a0 /* last frame pointer */
#ifdef __HAVE_68881__
/* do an fsave, then remember the address to begin a restore from */
fsave a0@-
fmovemx fp0-fp7, SYM (registers)+72
fmoveml fpcr/fpsr/fpi, SYM (registers)+168
#endif
lea SYM (registers),a5 /* get address of registers */
movew sp@,d1 /* get status register */
movew d1,a5@(66) /* save sr */
movel sp@(2),a4 /* save pc in a4 for later use */
movel a4,a5@(68) /* save pc in _regisers[] */
/* figure out how many bytes in the stack frame */
movew sp@(6),d0 /* get '020 exception format */
movew d0,d2 /* make a copy of format word */
andiw IMM (0xf000),d0 /* mask off format type */
rolw IMM (5),d0 /* rotate into the low byte *2 */
lea SYM (exceptionSize),a1
addw d0,a1 /* index into the table */
movew a1@,d0 /* get number of words in frame */
movew d0,d3 /* save it */
subw d0,a0 /* adjust save pointer */
subw d0,a0 /* adjust save pointer(bytes) */
movel a0,a1 /* copy save pointer */
subql IMM (1),d0 /* predecrement loop counter */
/* copy the frame */
saveFrameLoop:
movew sp@+,a1@+
dbf d0,saveFrameLoop
/* now that the stack has been clenaed,
* save the a7 in use at time of exception
*/
movel sp,SYM (superStack) /* save supervisor sp */
andiw IMM (0x2000),d1 /* were we in supervisor mode ? */
beq userMode
movel a7,a5@(60) /* save a7 */
bra a7saveDone
userMode:
movel usp,a1
movel a1,a5@(60) /* save user stack pointer */
a7saveDone:
/* save size of frame */
movew d3,a0@-
/* compute exception number */
andl IMM (0xfff),d2 /* mask off vector offset */
lsrw IMM (2),d2 /* divide by 4 to get vect num */
movel d2,a0@- /* save it */
/* save pc causing exception */
movel a4,a0@-
/* save old frame link and set the new value*/
movel SYM (lastFrame),a1 /* last frame pointer */
movel a1,a0@- /* save pointer to prev frame */
movel a0,SYM (lastFrame)
movel d2,sp@- /* push exception num */
#ifdef TMP_HACK
movel SYM (exceptionHook),a0 /* get address of handler */
jbsr a0@ /* and call it */
#else
jbsr SYM (remcomHandler)
#endif
clrl sp@ /* replace exception num parm with frame ptr */
jbsr SYM (_returnFromException) /* jbsr, but never returns */
#else /* mc68000 */
/* This function is called when an exception occurs. It translates the
* return address found on the stack into an exception vector # which
* is then handled by either handle_exception or a system handler.
* _catchException provides a front end for both.
*
* stack on entry: stack on exit:
* Program counter MSWord exception # MSWord
* Program counter LSWord exception # MSWord
* Status Register
* Return Address MSWord
* Return Address LSWord
*/
.text
.globl SYM (_catchException)
SYM (_catchException):
oriw IMM (0x0700),sr /* Disable interrupts */
moveml d0-d7/a0-a6,SYM (registers) /* save registers */
movel SYM (lastFrame),a0 /* last frame pointer */
#ifdef __HAVE_68881__
/* do an fsave, then remember the address to begin a restore from */
fsave a0@-
fmovemx fp0-fp7, SYM (registers)+72
fmoveml fpcr/fpsr/fpi, SYM (registers)+168
#endif
lea SYM (registers),a5 /* get address of registers */
movel sp@+,d2 /* pop return address */
addl IMM (1530),d2 /* convert return addr to */
divs IMM (6),d2 /* exception number */
extl d2
moveql IMM (3),d3 /* assume a three word frame */
cmpiw IMM (3),d2 /* bus error or address error ? */
bgt normal /* if >3 then normal error */
movel sp@+,a0@- /* copy error info to frame buff*/
movel sp@+,a0@- /* these are never used */
moveql IMM (7),d3 /* this is a 7 word frame */
normal:
movew sp@+,d1 /* pop status register */
movel sp@+,a4 /* pop program counter */
movew d1,a5@(66) /* save sr */
movel a4,a5@(68) /* save pc in _regisers[] */
movel a4,a0@- /* copy pc to frame buffer */
movew d1,a0@- /* copy sr to frame buffer */
movel sp,SYM (superStack) /* save supervisor sp */
andiw IMM (0x2000),d1 /* were we in supervisor mode ? */
beq userMode
movel a7,a5@(60) /* save a7 */
bra saveDone
userMode:
movel usp,a1 /* save user stack pointer */
movel a1,a5@(60) /* save user stack pointer */
saveDone:
movew d3,a0@- /* push frame size in words */
movel d2,a0@- /* push vector number */
movel a4,a0@- /* push exception pc */
/* save old frame link and set the new value */
movel SYM (lastFrame),a1 /* last frame pointer */
movel a1,a0@- /* save pointer to prev frame */
movel a0,SYM (lastFrame)
movel d2,sp@- /* push exception num */
movel SYM (exceptionHook),a0 /* get address of handler */
jbsr a0@ /* and call it */
clrl sp@ /* replace exception num parm with frame ptr */
jbsr SYM (_returnFromException) /* jbsr, but never returns */
#endif /* m68000 */
/*
* remcomHandler is a front end for handle_exception. It moves the
* stack pointer into an area reserved for debugger use in case the
* breakpoint happened in supervisor mode.
*/
.globl SYM (remcomHandler)
SYM (remcomHandler):
addl IMM (4),sp /* pop off return address */
movel sp@+,d0 /* get the exception number */
movel SYM (stackPtr),sp /* move to remcom stack area */
movel d0,sp@- /* push exception onto stack */
jbsr SYM (handle_exception) /* this never returns */
rts /* return */
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