repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
stsp/newlib-ia16
| 2,442
|
winsup/cygwin/math/ceil.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "ceil.S"
.text
.align 4
.globl __MINGW_USYMBOL(ceil)
.def __MINGW_USYMBOL(ceil); .scl 2; .type 32; .endef
#ifdef __x86_64__
.seh_proc __MINGW_USYMBOL(ceil)
#endif
__MINGW_USYMBOL(ceil):
#if defined(_AMD64_) || defined(__x86_64__)
.seh_endprologue
movd %xmm0, %rax
movq %rax, %rcx
sarq $52, %rcx
andl $2047, %ecx
subl $1023, %ecx
cmpl $51, %ecx
jg .is_intnaninf
/* Is x zero? */
testq %rax, %rax
je .ret_org
/* Is x signed? */
testl %ecx, %ecx
js .signed_val
/* Is x integral? */
movabsq $4503599627370495, %rdx
sarq %cl, %rdx
testq %rax, %rdx
je .ret_org
addsd .huge(%rip), %xmm0
ucomisd .zero(%rip), %xmm0
jbe .doret
testq %rax, %rax
jle .l1
/* inexact ... */
movabsq $4503599627370496, %r8
shrq %cl, %r8
addq %r8, %rax
.l1:
notq %rdx
andq %rdx, %rax
.doret:
movd %rax, %xmm0
ret
.p2align 4,,10
.signed_val:
addsd .huge(%rip), %xmm0
ucomisd .zero(%rip), %xmm0
jbe .doret2
testq %rax, %rax
movabsq $4607182418800017408, %rdx
movabsq $-9223372036854775808, %rax
cmovns %rdx, %rax
.p2align 4,,10
.doret2:
movd %rax, %xmm0
ret
.p2align 4,,10
.is_intnaninf:
/* Is Nan or Inf? */
cmpl $1024, %ecx
je .ret_naninf
.p2align 4,,10
.ret_org:
/* return x. */
rep
ret
.p2align 4,,10
.ret_naninf:
/* return x + x; */
addsd %xmm0, %xmm0
ret
.seh_endproc
/* local data. */
.section .rdata,"dr"
.align 8
.huge:
.long -2013235812
.long 2117592124
.align 8
.zero:
.long 0
.long 0
#elif defined(_ARM_) || defined(__arm__)
vmrs r1, fpscr
bic r0, r1, #0x00c00000
orr r0, r0, #0x00400000 /* Round towards Plus Infinity */
vmsr fpscr, r0
vcvtr.s32.f64 s0, d0
vcvt.f64.s32 d0, s0
vmsr fpscr, r1
bx lr
#elif defined(_X86_) || defined(__i386__)
fldl 4(%esp)
subl $8,%esp
fstcw 4(%esp) /* store fpu control word */
/* We use here %edx although only the low 1 bits are defined.
But none of the operations should care and they are faster
than the 16 bit operations. */
movl $0x0800,%edx /* round towards +oo */
orl 4(%esp),%edx
andl $0xfbff,%edx
movl %edx,(%esp)
fldcw (%esp) /* load modified control word */
frndint /* round */
fldcw 4(%esp) /* restore original control word */
addl $8,%esp
ret
#endif
|
stsp/newlib-ia16
| 1,975
|
winsup/cygwin/math/frexpl.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
/*
* frexpl(long double x, int* expnt) extracts the exponent from x.
* It returns an integer power of two to expnt and the significand
* between 0.5 and 1 to y. Thus x = y * 2**expn.
*/
#ifdef __x86_64__
.align 8
#else
.align 2
#endif
.globl __MINGW_USYMBOL(frexpl)
__MINGW_USYMBOL(frexpl):
#ifdef __x86_64__
pushq %rbp
movq %rsp,%rbp
subq $48,%rsp
pushq %rsi
fldt (%rdx)
movq %rcx,%r9
fld %st(0)
fstpt -12(%rbp)
leaq -4(%rbp),%rcx
movw -4(%rbp),%dx
andl $32767,%edx
jne L25
fldz
fucompp
fnstsw %ax
andb $68,%ah
xorb $64,%ah
jne L21
movl $0,(%r8)
fldz
jmp L24
.align 4,0x90
.align 4,0x90
L21:
fldt -12(%rbp)
fadd %st(0),%st
fstpt -12(%rbp)
decl %edx
movw (%rcx),%si
andl $32767,%esi
jne L22
cmpl $-66,%edx
jg L21
L22:
add %esi,%edx
jmp L19
.align 2,0x90
L25:
fstp %st(0)
L19:
addl $-16382,%edx
movl %edx,(%r8)
movw (%rcx),%ax
andl $-32768,%eax
orl $16382,%eax
movw %ax,(%rcx)
fldt -12(%rbp)
L24:
popq %rsi
movq %r9,%rax
movq $0,8(%r9)
fstpt (%r9)
leave
ret
#else
pushl %ebp
movl %esp,%ebp
subl $24,%esp
pushl %esi
pushl %ebx
fldt 8(%ebp)
movl 20(%ebp),%ebx
fld %st(0)
fstpt -12(%ebp)
leal -4(%ebp),%ecx
movw -4(%ebp),%dx
andl $32767,%edx
jne L25
fldz
fucompp
fnstsw %ax
andb $68,%ah
xorb $64,%ah
jne L21
movl $0,(%ebx)
fldz
jmp L24
.align 2,0x90
.align 2,0x90
L21:
fldt -12(%ebp)
fadd %st(0),%st
fstpt -12(%ebp)
decl %edx
movw (%ecx),%si
andl $32767,%esi
jne L22
cmpl $-66,%edx
jg L21
L22:
addl %esi,%edx
jmp L19
.align 2,0x90
L25:
fstp %st(0)
L19:
addl $-16382,%edx
movl %edx,(%ebx)
movw (%ecx),%ax
andl $-32768,%eax
orl $16382,%eax
movw %ax,(%ecx)
fldt -12(%ebp)
L24:
leal -32(%ebp),%esp
popl %ebx
popl %esi
leave
ret
#endif
|
stsp/newlib-ia16
| 1,082
|
winsup/cygwin/math/nearbyintl.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "nearbyintl.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
.globl __MINGW_USYMBOL(nearbyintl)
.def __MINGW_USYMBOL(nearbyintl); .scl 2; .type 32; .endef
__MINGW_USYMBOL(nearbyintl):
#if defined(_AMD64_) || defined(__x86_64__)
fldt (%rdx)
movq %rcx,%r8
pushq %rax
pushq %rcx
fnstcw (%rsp)
movl (%rsp), %eax
orl $0x20, %eax
movl %eax, 8(%rsp)
fldcw 8(%rsp)
frndint
fclex
fldcw (%rsp)
popq %rcx
popq %rax
movq %r8,%rax
movq $0,8(%r8)
fstpt (%r8)
ret
#elif defined(_ARM_) || defined(__arm__)
vmrs r1, fpscr
vcvtr.s32.f64 s0, d0
vcvt.f64.s32 d0, s0
vmsr fpscr, r1
bx lr
#elif defined(_X86_) || defined(__i386__)
fldt 4(%esp)
pushl %eax
pushl %ecx
fnstcw (%esp)
movl (%esp), %eax
orl $0x20, %eax
movl %eax, 4(%esp)
fldcw 4(%esp)
frndint
fclex
fldcw (%esp)
popl %ecx
popl %eax
ret
#endif
|
stsp/newlib-ia16
| 1,237
|
winsup/cygwin/math/copysignl.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
/*
* Written by J.T. Conklin <jtc@netbsd.org>.
* Changes for long double by Ulrich Drepper <drepper@cygnus.com>
* Public domain.
*/
#include <_mingw_mac.h>
.file "copysignl.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
.globl __MINGW_USYMBOL(copysignl)
.def __MINGW_USYMBOL(copysignl); .scl 2; .type 32; .endef
__MINGW_USYMBOL(copysignl):
#if defined(_AMD64_) || defined(__x86_64__)
movq (%rdx), %rax
movq %rax, (%rcx)
movq 8(%rdx), %rax
movq 8(%r8), %rdx
andq $0x777f, %rax
andq $0x8000, %rdx
orq %rdx, %rax
movq %rax, 8(%rcx)
movq %rcx, %rax
ret
#elif defined(_ARM_) || defined(__arm__)
fcmpzd d1
fmstat
bmi 1f /* jump if d1 is negative */
fcmpzd d0
fmstat
vnegmi.f64 d0, d0 /* negate d0 if it is negative */
bx lr
1: fcmpzd d0
fmstat
vnegpl.f64 d0, d0 /* negate d0 if it is positive */
bx lr
#elif defined(_X86_) || defined(__i386__)
movl 24(%esp),%edx
movl 12(%esp),%eax
andl $0x8000,%edx
andl $0x7fff,%eax
orl %edx,%eax
movl %eax,12(%esp)
fldt 4(%esp)
ret
#endif
|
stsp/newlib-ia16
| 1,940
|
winsup/cygwin/math/exp2l.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "exp2l.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
.globl __MINGW_USYMBOL(exp2l)
.def __MINGW_USYMBOL(exp2l); .scl 2; .type 32; .endef
__MINGW_USYMBOL(exp2l):
#ifdef __x86_64__
fldt (%rdx)
fxam /* Is NaN or +-Inf? */
fstsw %ax
movb $0x45, %dh
andb %ah, %dh
cmpb $0x05, %dh
je 1f /* Is +-Inf, jump. */
fld %st
subq $8, %rsp /* int(x) */
fnstcw 4(%rsp)
movzwl 4(%rsp), %eax
orb $12, %ah
movw %ax, (%rsp)
fldcw (%rsp)
frndint
fldcw 4(%rsp)
addq $8, %rsp
fsubr %st,%st(1) /* fract(x) */
fxch
f2xm1 /* 2^(fract(x)) - 1 */
fld1
faddp /* 2^(fract(x)) */
fscale /* e^x */
fstp %st(1)
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
1: testl $0x200, %eax /* Test sign. */
jz 2f /* If positive, jump. */
fstp %st
fldz /* Set result to 0. */
2: movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
#else
fldt 4(%esp)
/* I added the following ugly construct because exp(+-Inf) resulted
in NaN. The ugliness results from the bright minds at Intel.
For the i686 the code can be written better.
-- drepper@cygnus.com. */
fxam /* Is NaN or +-Inf? */
fstsw %ax
movb $0x45, %dh
andb %ah, %dh
cmpb $0x05, %dh
je 1f /* Is +-Inf, jump. */
fld %st
subl $8, %esp /* int(x) */
fnstcw 4(%esp)
movzwl 4(%esp), %eax
orb $12, %ah
movw %ax, (%esp)
fldcw (%esp)
frndint
fldcw 4(%esp)
addl $8, %esp
fsubr %st,%st(1) /* fract(x) */
fxch
f2xm1 /* 2^(fract(x)) - 1 */
fld1
faddp /* 2^(fract(x)) */
fscale /* e^x */
fstp %st(1)
ret
1: testl $0x200, %eax /* Test sign. */
jz 2f /* If positive, jump. */
fstp %st
fldz /* Set result to 0. */
2: ret
#endif
|
stsp/newlib-ia16
| 1,085
|
winsup/cygwin/math/nearbyint.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "nearbyint.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
.globl __MINGW_USYMBOL(nearbyint)
.def __MINGW_USYMBOL(nearbyint); .scl 2; .type 32; .endef
__MINGW_USYMBOL(nearbyint):
#if defined(_AMD64_) || defined(__x86_64__)
movsd %xmm0,-16(%rsp)
fldl -16(%rsp)
pushq %rax
pushq %rcx
fnstcw (%rsp)
movq (%rsp), %rax
orq $0x20, %rax
movq %rax, 8(%rsp)
fldcw 8(%rsp)
frndint
fclex
fldcw (%rsp)
popq %rcx
popq %rax
fstpl -16(%rsp)
movsd -16(%rsp),%xmm0
ret
#elif defined(_ARM_) || defined(__arm__)
vmrs r1, fpscr
vcvtr.s32.f64 s0, d0
vcvt.f64.s32 d0, s0
vmsr fpscr, r1
bx lr
#elif defined(_X86_) || defined(__i386__)
fldl 4(%esp)
pushl %eax
pushl %ecx
fnstcw (%esp)
movl (%esp), %eax
orl $0x20, %eax
movl %eax, 4(%esp)
fldcw 4(%esp)
frndint
fclex
fldcw (%esp)
popl %ecx
popl %eax
ret
#endif
|
stsp/newlib-ia16
| 1,715
|
winsup/cygwin/math/log1pl.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "log1pl.S"
.text
/* The fyl2xp1 can only be used for values in
-1 + sqrt(2) / 2 <= x <= 1 - sqrt(2) / 2
0.29 is a safe value.
*/
/* Only gcc understands the .tfloat type
The series of .long below represents
limit: .tfloat 0.29
*/
.align 16
limit:
.long 2920577761
.long 2491081031
.long 16381
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
/* Please note: we use a double value here. Since 1.0 has
an exact representation this does not effect the accuracy
but it helps to optimize the code. */
one: .double 1.0
/*
* Use the fyl2xp1 function when the argument is in the range -0.29 to 0.29,
* otherwise fyl2x with the needed extra computation.
*/
.globl __MINGW_USYMBOL(log1pl)
.def __MINGW_USYMBOL(log1pl); .scl 2; .type 32; .endef
__MINGW_USYMBOL(log1pl):
#ifdef __x86_64__
fldln2
fldt (%rdx)
fxam
fnstsw
fld %st
sahf
jc 3f // in case x is NaN or Inf
4:
fabs
fldt limit(%rip)
fcompp
fnstsw
sahf
jnc 2f
faddl one(%rip)
fyl2x
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
2: fyl2xp1
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
3: jp 4b // in case x is Inf
fstp %st(1)
fstp %st(1)
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
#else
fldln2
fldt 4(%esp)
fxam
fnstsw
fld %st
sahf
jc 3f // in case x is NaN or Inf
4:
fabs
fldt limit
fcompp
fnstsw
sahf
jnc 2f
faddl one
fyl2x
ret
2: fyl2xp1
ret
3: jp 4b // in case x is Inf
fstp %st(1)
fstp %st(1)
ret
#endif
|
stsp/newlib-ia16
| 1,557
|
winsup/cygwin/math/internal_logl.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "internal_logl.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
one: .double 1.0
/* It is not important that this constant is precise. It is only
a value which is known to be on the safe side for using the
fyl2xp1 instruction. */
limit: .double 0.29
.globl __MINGW_USYMBOL(__logl_internal)
.def __MINGW_USYMBOL(__logl_internal); .scl 2; .type 32; .endef
__MINGW_USYMBOL(__logl_internal):
#ifdef __x86_64__
fldln2 // log(2)
fldt (%rdx) // x : log(2)
fld %st // x : x : log(2)
fsubl one(%rip) // x-1 : x : log(2)
fld %st // x-1 : x-1 : x : log(2)
fabs // |x-1| : x-1 : x : log(2)
fcompl limit(%rip) // x-1 : x : log(2)
fnstsw // x-1 : x : log(2)
andb $0x45, %ah
jz 2f
fstp %st(1) // x-1 : log(2)
fyl2xp1 // log(x)
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
2: fstp %st(0) // x : log(2)
fyl2x // log(x)
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
#else
fldln2 // log(2)
fldt 4(%esp) // x : log(2)
fld %st // x : x : log(2)
fsubl one // x-1 : x : log(2)
fld %st // x-1 : x-1 : x : log(2)
fabs // |x-1| : x-1 : x : log(2)
fcompl limit // x-1 : x : log(2)
fnstsw // x-1 : x : log(2)
andb $0x45, %ah
jz 2f
fstp %st(1) // x-1 : log(2)
fyl2xp1 // log(x)
ret
2: fstp %st(0) // x : log(2)
fyl2x // log(x)
ret
#endif
|
stsp/newlib-ia16
| 1,088
|
winsup/cygwin/math/nearbyintf.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "nearbyintf.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
.globl __MINGW_USYMBOL(nearbyintf)
.def __MINGW_USYMBOL(nearbyintf); .scl 2; .type 32; .endef
__MINGW_USYMBOL(nearbyintf):
#if defined(_AMD64_) || defined(__x86_64__)
movss %xmm0,-12(%rsp)
flds -12(%rsp)
pushq %rax
pushq %rcx
fnstcw (%rsp)
movq (%rsp), %rax
orq $0x20, %rax
movq %rax, 8(%rsp)
fldcw 8(%rsp)
frndint
fclex
fldcw (%rsp)
popq %rcx
popq %rax
fstps -12(%rsp)
movss -12(%rsp),%xmm0
ret
#elif defined(_ARM_) || defined(__arm__)
vmrs r1, fpscr
vcvt.s32.f32 s0, s0
vcvt.f32.s32 s0, s0
vmsr fpscr, r1
bx lr
#elif defined(_X86_) || defined(__i386__)
flds 4(%esp)
pushl %eax
pushl %ecx
fnstcw (%esp)
movl (%esp), %eax
orl $0x20, %eax
movl %eax, 4(%esp)
fldcw 4(%esp)
frndint
fclex
fldcw (%esp)
popl %ecx
popl %eax
ret
#endif
|
stsp/newlib-ia16
| 1,707
|
winsup/cygwin/math/log2l.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "log2l.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
one: .double 1.0
/* It is not important that this constant is precise. It is only
a value which is known to be on the safe side for using the
fyl2xp1 instruction. */
limit: .double 0.29
.globl __MINGW_USYMBOL(log2l)
.def __MINGW_USYMBOL(log2l); .scl 2; .type 32; .endef
__MINGW_USYMBOL(log2l):
#ifdef __x86_64__
fldl one(%rip)
fldt (%rdx) // x : 1
fxam
fnstsw
fld %st // x : x : 1
sahf
jc 3f // in case x is NaN or Inf
4: fsub %st(2), %st // x-1 : x : 1
fld %st // x-1 : x-1 : x : 1
fabs // |x-1| : x-1 : x : 1
fcompl limit(%rip) // x-1 : x : 1
fnstsw // x-1 : x : 1
andb $0x45, %ah
jz 2f
fstp %st(1) // x-1 : 1
fyl2xp1 // log(x)
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
2: fstp %st(0) // x : 1
fyl2x // log(x)
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
3: jp 4b // in case x is Inf
fstp %st(1)
fstp %st(1)
movq %rcx,%rax
movq $0,8(%rcx)
fstpt (%rcx)
ret
#else
fldl one
fldt 4(%esp) // x : 1
fxam
fnstsw
fld %st // x : x : 1
sahf
jc 3f // in case x is NaN or Inf
4: fsub %st(2), %st // x-1 : x : 1
fld %st // x-1 : x-1 : x : 1
fabs // |x-1| : x-1 : x : 1
fcompl limit // x-1 : x : 1
fnstsw // x-1 : x : 1
andb $0x45, %ah
jz 2f
fstp %st(1) // x-1 : 1
fyl2xp1 // log(x)
ret
2: fstp %st(0) // x : 1
fyl2x // log(x)
ret
3: jp 4b // in case x is Inf
fstp %st(1)
fstp %st(1)
ret
#endif
|
stsp/newlib-ia16
| 1,977
|
winsup/cygwin/math/exp2.S
|
/**
* This file has no copyright assigned and is placed in the Public Domain.
* This file is part of the mingw-w64 runtime package.
* No warranty is given; refer to the file DISCLAIMER.PD within this package.
*/
#include <_mingw_mac.h>
.file "exp2.S"
.text
#ifdef __x86_64__
.align 8
#else
.align 4
#endif
.globl __MINGW_USYMBOL(exp2)
.def __MINGW_USYMBOL(exp2); .scl 2; .type 32; .endef
__MINGW_USYMBOL(exp2):
#ifdef __x86_64__
subq $24, %rsp
movsd %xmm0,(%rsp)
fldl (%rsp)
fxam /* Is NaN or +-Inf? */
fstsw %ax
movb $0x45, %dh
andb %ah, %dh
cmpb $0x05, %dh
je 1f /* Is +-Inf, jump. */
fld %st
subq $8, %rsp /* int(x) */
fnstcw 4(%rsp)
movzwl 4(%rsp), %eax
orb $12, %ah
movw %ax, (%rsp)
fldcw (%rsp)
frndint
fldcw 4(%rsp)
addq $8, %rsp
fsubr %st,%st(1) /* fract(x) */
fxch
f2xm1 /* 2^(fract(x)) - 1 */
fld1
faddp /* 2^(fract(x)) */
fscale /* e^x */
fstp %st(1)
fstpl (%rsp)
movsd (%rsp),%xmm0
addq $24, %rsp
ret
1: testl $0x200, %eax /* Test sign. */
jz 2f /* If positive, jump. */
fstp %st
fldz /* Set result to 0. */
2: fstpl (%rsp)
movsd (%rsp),%xmm0
addq $24,%rsp
ret
#else
fldl 4(%esp)
/* I added the following ugly construct because exp(+-Inf) resulted
in NaN. The ugliness results from the bright minds at Intel.
For the i686 the code can be written better.
-- drepper@cygnus.com. */
fxam /* Is NaN or +-Inf? */
fstsw %ax
movb $0x45, %dh
andb %ah, %dh
cmpb $0x05, %dh
je 1f /* Is +-Inf, jump. */
fld %st
subl $8, %esp /* int(x) */
fnstcw 4(%esp)
movzwl 4(%esp), %eax
orb $12, %ah
movw %ax, (%esp)
fldcw (%esp)
frndint
fldcw 4(%esp)
addl $8, %esp
fsubr %st,%st(1) /* fract(x) */
fxch
f2xm1 /* 2^(fract(x)) - 1 */
fld1
faddp /* 2^(fract(x)) */
fscale /* e^x */
fstp %st(1)
ret
1: testl $0x200, %eax /* Test sign. */
jz 2f /* If positive, jump. */
fstp %st
fldz /* Set result to 0. */
2: ret
#endif
|
stsp/binutils-ia16
| 24,567
|
gold/testsuite/dwp_test_2.s
|
.file "dwp_test_2.cc"
.text
.Ltext0:
.section .text._Z4f13iv,"axG",@progbits,_Z4f13iv,comdat
.weak _Z4f13iv
.type _Z4f13iv, @function
_Z4f13iv:
.LFB0:
.file 1 "dwp_test.h"
.loc 1 70 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 1 70 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE0:
.size _Z4f13iv, .-_Z4f13iv
.text
.align 2
.globl _ZN2C14t1_2Ev
.type _ZN2C14t1_2Ev, @function
_ZN2C14t1_2Ev:
.LFB1:
.file 2 "dwp_test_2.cc"
.loc 2 31 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 32 0
movl $123, %eax
.loc 2 33 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.size _ZN2C14t1_2Ev, .-_ZN2C14t1_2Ev
.align 2
.globl _ZN2C13t1aEv
.type _ZN2C13t1aEv, @function
_ZN2C13t1aEv:
.LFB2:
.loc 2 37 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $8, %rsp
movq %rdi, -8(%rbp)
.loc 2 38 0
movq -8(%rbp), %rax
movq %rax, %rdi
call _ZN2C14t1_2Ev
cmpl $123, %eax
sete %al
.loc 2 39 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE2:
.size _ZN2C13t1aEv, .-_ZN2C13t1aEv
.globl v2
.data
.align 4
.type v2, @object
.size v2, 4
v2:
.long 456
.globl v3
.bss
.align 4
.type v3, @object
.size v3, 4
v3:
.zero 4
.globl v4
.data
.type v4, @object
.size v4, 13
v4:
.string "Hello, world"
.globl v5
.bss
.type v5, @object
.size v5, 13
v5:
.zero 13
.text
.globl _Z3f10v
.type _Z3f10v, @function
_Z3f10v:
.LFB3:
.loc 2 73 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 74 0
movl $135, %eax
.loc 2 75 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE3:
.size _Z3f10v, .-_Z3f10v
.globl _Z4f11bPFivE
.type _Z4f11bPFivE, @function
_Z4f11bPFivE:
.LFB4:
.loc 2 81 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, -8(%rbp)
.loc 2 82 0
movq -8(%rbp), %rax
call *%rax
.loc 2 83 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE4:
.size _Z4f11bPFivE, .-_Z4f11bPFivE
.align 2
.globl _ZN2C32f4Ev
.type _ZN2C32f4Ev, @function
_ZN2C32f4Ev:
.LFB5:
.loc 2 89 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 90 0
movl $_Z3t12v, %eax
.loc 2 91 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE5:
.size _ZN2C32f4Ev, .-_ZN2C32f4Ev
.globl _Z3f13v
.type _Z3f13v, @function
_Z3f13v:
.LFB6:
.loc 2 97 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 98 0
movl $_Z4f13iv, %eax
.loc 2 99 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE6:
.size _Z3f13v, .-_Z3f13v
.section .rodata
.LC0:
.string "test string constant"
.text
.globl _Z3f14v
.type _Z3f14v, @function
_Z3f14v:
.LFB7:
.loc 2 105 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 106 0
movl $.LC0, %eax
.loc 2 107 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE7:
.size _Z3f14v, .-_Z3f14v
.section .rodata
.align 8
.LC1:
.string "t"
.string ""
.string ""
.string "e"
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "w"
.string ""
.string ""
.string "i"
.string ""
.string ""
.string "d"
.string ""
.string ""
.string "e"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string "r"
.string ""
.string ""
.string "i"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "g"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "c"
.string ""
.string ""
.string "o"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string "a"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.text
.globl _Z3f15v
.type _Z3f15v, @function
_Z3f15v:
.LFB8:
.loc 2 113 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 114 0
movl $.LC1, %eax
.loc 2 115 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE8:
.size _Z3f15v, .-_Z3f15v
.globl t17data
.section .rodata
.LC2:
.string "a"
.LC3:
.string "b"
.LC4:
.string "c"
.LC5:
.string "d"
.LC6:
.string "e"
.data
.align 32
.type t17data, @object
.size t17data, 40
t17data:
.quad .LC2
.quad .LC3
.quad .LC4
.quad .LC5
.quad .LC6
.text
.globl _Z3f18i
.type _Z3f18i, @function
_Z3f18i:
.LFB9:
.loc 2 128 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movl %edi, -4(%rbp)
.loc 2 129 0
cmpl $4, -4(%rbp)
ja .L19
movl -4(%rbp), %eax
movq .L25(,%rax,8), %rax
jmp *%rax
.section .rodata
.align 8
.align 4
.L25:
.quad .L20
.quad .L21
.quad .L22
.quad .L23
.quad .L24
.text
.L20:
.loc 2 132 0
movl $.LC2, %eax
jmp .L26
.L21:
.loc 2 134 0
movl $.LC3, %eax
jmp .L26
.L22:
.loc 2 136 0
movl $.LC4, %eax
jmp .L26
.L23:
.loc 2 138 0
movl $.LC5, %eax
jmp .L26
.L24:
.loc 2 140 0
movl $.LC6, %eax
jmp .L26
.L19:
.loc 2 142 0
movl $0, %eax
.L26:
.loc 2 144 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE9:
.size _Z3f18i, .-_Z3f18i
.Letext0:
.section .debug_types.dwo,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0xf3
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x8a
.byte 0xda
.byte 0x59
.byte 0x6e
.byte 0x4d
.byte 0x5c
.byte 0xa
.byte 0x88
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C3"
.byte 0x4
.byte 0x1
.byte 0x2f
.long 0xd6
.uleb128 0x3
.string "member1"
.byte 0x1
.byte 0x36
.long 0xd6
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x32
.string "_ZN2C39testcase1Ev"
.long 0xdd
.byte 0x1
.long 0x65
.long 0x6b
.uleb128 0x5
.long 0xe5
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x33
.string "_ZN2C39testcase2Ev"
.long 0xdd
.byte 0x1
.long 0x8f
.long 0x95
.uleb128 0x5
.long 0xe5
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x1
.byte 0x34
.string "_ZN2C39testcase3Ev"
.long 0xdd
.byte 0x1
.long 0xb9
.long 0xbf
.uleb128 0x5
.long 0xe5
.byte 0
.uleb128 0x6
.string "f4"
.byte 0x1
.byte 0x35
.uleb128 0x3
.long 0xeb
.byte 0x1
.long 0xcf
.uleb128 0x5
.long 0xe5
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.uleb128 0x8
.byte 0x8
.long 0xf1
.uleb128 0x9
.long 0xdd
.byte 0
.section .debug_types,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_2.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x138
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0xe3
.byte 0xad
.byte 0x5
.byte 0x3b
.byte 0x75
.byte 0xeb
.byte 0xfb
.byte 0xc7
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C1"
.byte 0x4
.byte 0x1
.byte 0x19
.long 0x126
.uleb128 0x3
.string "member1"
.byte 0x1
.byte 0x22
.long 0x126
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x1c
.string "_ZN2C19testcase1Ev"
.long 0x12d
.byte 0x1
.long 0x65
.long 0x6b
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0xa
.string "t1a"
.byte 0x1
.byte 0x1d
.uleb128 0x4
.long 0x12d
.byte 0x1
.long 0x80
.long 0x86
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0xa
.string "t1_2"
.byte 0x1
.byte 0x1e
.uleb128 0x5
.long 0x126
.byte 0x1
.long 0x9c
.long 0xa2
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x1f
.string "_ZN2C19testcase2Ev"
.long 0x12d
.byte 0x1
.long 0xc6
.long 0xcc
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x1
.byte 0x20
.string "_ZN2C19testcase3Ev"
.long 0x12d
.byte 0x1
.long 0xf0
.long 0xf6
.uleb128 0x5
.long 0x135
.byte 0
.uleb128 0xb
.string "testcase4"
.byte 0x1
.byte 0x21
.string "_ZN2C19testcase4Ev"
.long 0x12d
.byte 0x1
.long 0x11f
.uleb128 0x5
.long 0x135
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_2.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_info.dwo,"e",@progbits
.Ldebug_info0:
.long 0x329
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0xc
.string "GNU C++ 4.7.x-google 20120720 (prerelease)"
.byte 0x4
.string "dwp_test_2.cc"
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.byte 0xb9
.byte 0xf8
.byte 0xe0
.byte 0x8c
.byte 0x71
.byte 0xab
.byte 0xc
.byte 0xcf
.uleb128 0xd
.string "C1"
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0xb9
.uleb128 0xe
.string "t1a"
.byte 0x1
.byte 0x1d
.uleb128 0x4
.long 0xc0
.byte 0x1
.uleb128 0xe
.string "t1_2"
.byte 0x1
.byte 0x1e
.uleb128 0x5
.long 0xb9
.byte 0x1
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0xf
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.uleb128 0xd
.string "C3"
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0xef
.uleb128 0xe
.string "f4"
.byte 0x1
.byte 0x35
.uleb128 0x3
.long 0xfe
.byte 0x1
.byte 0
.uleb128 0xf
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x9
.long 0xc0
.uleb128 0x8
.byte 0x8
.long 0xf9
.uleb128 0x10
.string "f13i"
.byte 0x1
.byte 0x46
.string "_Z4f13iv"
.uleb128 0
.quad .LFE0-.LFB0
.uleb128 0x1
.byte 0x9c
.uleb128 0x11
.long 0xaa
.byte 0x2
.uleb128 0x1
.quad .LFE1-.LFB1
.uleb128 0x1
.byte 0x9c
.long 0x139
.long 0x147
.uleb128 0x12
.string "this"
.long 0x147
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0xc8
.uleb128 0x14
.long 0x9d
.byte 0x2
.byte 0x24
.uleb128 0x2
.quad .LFE2-.LFB2
.uleb128 0x1
.byte 0x9c
.long 0x166
.long 0x174
.uleb128 0x12
.string "this"
.long 0x147
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x15
.string "f10"
.byte 0x2
.byte 0x48
.string "_Z3f10v"
.long 0xb9
.uleb128 0x3
.quad .LFE3-.LFB3
.uleb128 0x1
.byte 0x9c
.uleb128 0x16
.string "f11b"
.byte 0x2
.byte 0x50
.string "_Z4f11bPFivE"
.long 0xb9
.uleb128 0x4
.quad .LFE4-.LFB4
.uleb128 0x1
.byte 0x9c
.long 0x1c9
.uleb128 0x17
.string "pfn"
.byte 0x2
.byte 0x50
.long 0x1ce
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x9
.long 0xb9
.uleb128 0x8
.byte 0x8
.long 0x1c9
.uleb128 0x18
.long 0xe2
.byte 0x2
.byte 0x58
.uleb128 0x5
.quad .LFE5-.LFB5
.uleb128 0x1
.byte 0x9c
.long 0x1ee
.long 0x1fc
.uleb128 0x12
.string "this"
.long 0x1fc
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0xef
.uleb128 0x19
.uleb128 0x15
.string "f13"
.byte 0x2
.byte 0x60
.string "_Z3f13v"
.long 0x220
.uleb128 0x6
.quad .LFE6-.LFB6
.uleb128 0x1
.byte 0x9c
.uleb128 0x8
.byte 0x8
.long 0x201
.uleb128 0x15
.string "f14"
.byte 0x2
.byte 0x68
.string "_Z3f14v"
.long 0x244
.uleb128 0x7
.quad .LFE7-.LFB7
.uleb128 0x1
.byte 0x9c
.uleb128 0x8
.byte 0x8
.long 0x24a
.uleb128 0x13
.long 0x24f
.uleb128 0x7
.byte 0x1
.byte 0x6
.string "char"
.uleb128 0x15
.string "f15"
.byte 0x2
.byte 0x70
.string "_Z3f15v"
.long 0x275
.uleb128 0x8
.quad .LFE8-.LFB8
.uleb128 0x1
.byte 0x9c
.uleb128 0x8
.byte 0x8
.long 0x27b
.uleb128 0x13
.long 0x280
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "wchar_t"
.uleb128 0x1a
.string "f18"
.byte 0x2
.byte 0x7f
.string "_Z3f18i"
.long 0x244
.uleb128 0x9
.quad .LFE9-.LFB9
.uleb128 0x1
.byte 0x9c
.long 0x2ba
.uleb128 0x17
.string "i"
.byte 0x2
.byte 0x7f
.long 0xb9
.uleb128 0x2
.byte 0x91
.sleb128 -20
.byte 0
.uleb128 0x1b
.string "v2"
.byte 0x2
.byte 0x2b
.long 0xb9
.uleb128 0x2
.byte 0xfb
.uleb128 0xa
.uleb128 0x1b
.string "v3"
.byte 0x2
.byte 0x30
.long 0xb9
.uleb128 0x2
.byte 0xfb
.uleb128 0xb
.uleb128 0x1c
.long 0x24f
.long 0x2e4
.uleb128 0x1d
.long 0x2e4
.byte 0xc
.byte 0
.uleb128 0x7
.byte 0x8
.byte 0x7
.string "sizetype"
.uleb128 0x1b
.string "v4"
.byte 0x2
.byte 0x34
.long 0x2d4
.uleb128 0x2
.byte 0xfb
.uleb128 0xc
.uleb128 0x1b
.string "v5"
.byte 0x2
.byte 0x39
.long 0x2d4
.uleb128 0x2
.byte 0xfb
.uleb128 0xd
.uleb128 0x1c
.long 0x244
.long 0x31a
.uleb128 0x1d
.long 0x2e4
.byte 0x4
.byte 0
.uleb128 0x1b
.string "t17data"
.byte 0x2
.byte 0x77
.long 0x30a
.uleb128 0x2
.byte 0xfb
.uleb128 0xe
.byte 0
.section .debug_info,"",@progbits
.Lskeleton_debug_info0:
.long 0x7e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.uleb128 0x1
.long .Ldebug_ranges0+0
.quad 0
.long .Ldebug_line0
.byte 0xb9
.byte 0xf8
.byte 0xe0
.byte 0x8c
.byte 0x71
.byte 0xab
.byte 0xc
.byte 0xcf
.long .Ldebug_ranges0
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_2.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_abbrev,"",@progbits
.Lskeleton_debug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0
.uleb128 0x55
.uleb128 0x17
.uleb128 0x11
.uleb128 0x1
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2131
.uleb128 0x7
.uleb128 0x2132
.uleb128 0x17
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x41
.byte 0
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.byte 0
.section .debug_abbrev.dwo,"e",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x41
.byte 0x1
.uleb128 0x13
.uleb128 0xb
.uleb128 0x210f
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.uleb128 0x32
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x15
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2131
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xd
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0x69
.uleb128 0x20
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xe
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0xf
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.byte 0
.byte 0
.uleb128 0x10
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x11
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x12
.uleb128 0x5
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x13
.uleb128 0x26
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x14
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x15
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x16
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x17
.uleb128 0x5
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x18
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x19
.uleb128 0x15
.byte 0
.byte 0
.byte 0
.uleb128 0x1a
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x1b
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x1c
.uleb128 0x1
.byte 0x1
.uleb128 0x49
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x1d
.uleb128 0x21
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2f
.uleb128 0xb
.byte 0
.byte 0
.byte 0
.section .debug_gnu_pubnames,"",@progbits
.Ldebug_pubnames0:
.long 0xa3
.value 0x2
.long .Lskeleton_debug_info0
.long 0x32d
.long 0x104
.byte 0x30
.string "f13i"
.long 0x120
.byte 0x30
.string "C1::t1_2"
.long 0x14c
.byte 0x30
.string "C1::t1a"
.long 0x174
.byte 0x30
.string "f10"
.long 0x192
.byte 0x30
.string "f11b"
.long 0x1d4
.byte 0x30
.string "C3::f4"
.long 0x202
.byte 0x30
.string "f13"
.long 0x226
.byte 0x30
.string "f14"
.long 0x257
.byte 0x30
.string "f15"
.long 0x28b
.byte 0x30
.string "f18"
.long 0x2ba
.byte 0x20
.string "v2"
.long 0x2c7
.byte 0x20
.string "v3"
.long 0x2f0
.byte 0x20
.string "v4"
.long 0x2fd
.byte 0x20
.string "v5"
.long 0x31a
.byte 0x20
.string "t17data"
.long 0
.section .debug_gnu_pubtypes,"",@progbits
.Ldebug_pubtypes0:
.long 0x56
.value 0x2
.long .Lskeleton_debug_info0
.long 0x32d
.long 0xb9
.byte 0x90
.string "int"
.long 0xc0
.byte 0x90
.string "bool"
.long 0x8d
.byte 0x10
.string "C1"
.long 0xd2
.byte 0x10
.string "C3"
.long 0x24f
.byte 0x90
.string "char"
.long 0x280
.byte 0x90
.string "wchar_t"
.long 0x2e4
.byte 0x90
.string "sizetype"
.long 0
.section .debug_aranges,"",@progbits
.long 0x3c
.value 0x2
.long .Lskeleton_debug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad .LFB0
.quad .LFE0-.LFB0
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0
.quad .Letext0
.quad .LFB0
.quad .LFE0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_line.dwo,"e",@progbits
.Lskeleton_debug_line0:
.long .LELT0-.LSLT0
.LSLT0:
.value 0x4
.long .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf2
.byte 0xd
.byte 0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0
.byte 0
.byte 0
.byte 0x1
.byte 0
.byte 0
.byte 0x1
.byte 0
.string "dwp_test.h"
.uleb128 0
.uleb128 0
.uleb128 0
.string "dwp_test_2.cc"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.LELTP0:
.LELT0:
.section .debug_str_offsets.dwo,"e",@progbits
.long 0
.long 0xa
.long 0x14
.long 0x1e
.long 0x2a
.long 0x37
.section .debug_str.dwo,"e",@progbits
.LASF0:
.string "testcase1"
.LASF1:
.string "testcase2"
.LASF2:
.string "testcase3"
.LASF3:
.string "_ZN2C32f4Ev"
.LASF4:
.string "_ZN2C13t1aEv"
.LASF5:
.string "_ZN2C14t1_2Ev"
.section .debug_addr,"",@progbits
.Ldebug_addr0:
.quad .LFB0
.quad .LFB1
.quad .LFB2
.quad .LFB3
.quad .LFB4
.quad .LFB5
.quad .LFB6
.quad .LFB7
.quad .LFB8
.quad .LFB9
.quad v2
.quad v3
.quad v4
.quad v5
.quad t17data
.ident "GCC: (Google_crosstoolv16-gcc-4.7.x-grtev3) 4.7.x-google 20120720 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 1,085
|
gold/testsuite/arm_thm_jump8.s
|
# arm_thm_jump8.s
# Test R_ARM_THM_JUMP8 relocations just within the branch range limits.
.syntax unified
.arch armv5te
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
beq.n _backward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
beq.n _forward_target
.size _forward_test, .-_forward_test
.section .text.post,"x"
# Add padding so that target is just in branch range.
.space 8
.global _forward_target
.code 16
.thumb_func
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
stsp/binutils-ia16
| 22,230
|
gold/testsuite/dwp_test_main.s
|
.file "dwp_test_main.cc"
.text
.Ltext0:
.section .rodata
.LC0:
.string "dwp_test_main.cc"
.LC1:
.string "c1.testcase1()"
.LC2:
.string "c1.t1a()"
.LC3:
.string "c1.testcase2()"
.LC4:
.string "c1.testcase3()"
.LC5:
.string "c1.testcase4()"
.LC6:
.string "c2.testcase1()"
.LC7:
.string "c2.testcase2()"
.LC8:
.string "c2.testcase3()"
.LC9:
.string "c2.testcase4()"
.LC10:
.string "c3.testcase1()"
.LC11:
.string "c3.testcase2()"
.LC12:
.string "c3.testcase3()"
.LC13:
.string "t12()"
.LC14:
.string "t13()"
.LC15:
.string "t16()"
.LC16:
.string "t16a()"
.LC17:
.string "t17()"
.LC18:
.string "t18()"
.text
.globl main
.type main, @function
main:
.LFB1:
.file 1 "dwp_test_main.cc"
.loc 1 31 0
.cfi_startproc
.cfi_personality 0x3,__gxx_personality_v0
.cfi_lsda 0x3,.LLSDA1
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $32, %rsp
.LBB2:
.loc 1 36 0
movl $789, v3(%rip)
.LBB3:
.loc 1 37 0
movl $0, -4(%rbp)
jmp .L2
.L3:
.loc 1 38 0
movl -4(%rbp), %eax
cltq
movzbl v4(%rax), %edx
movl -4(%rbp), %eax
cltq
movb %dl, v5(%rax)
.loc 1 37 0 discriminator 2
addl $1, -4(%rbp)
.L2:
.loc 1 37 0 is_stmt 0 discriminator 1
cmpl $12, -4(%rbp)
setle %al
testb %al, %al
jne .L3
.LBE3:
.loc 1 40 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
.LEHB0:
call _ZN2C19testcase1Ev
.loc 1 40 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L4
.loc 1 40 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $40, %edx
movl $.LC0, %esi
movl $.LC1, %edi
call __assert_fail
.L4:
.loc 1 41 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
call _ZN2C13t1aEv
.loc 1 41 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L5
.loc 1 41 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $41, %edx
movl $.LC0, %esi
movl $.LC2, %edi
call __assert_fail
.L5:
.loc 1 42 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
call _ZN2C19testcase2Ev
.loc 1 42 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L6
.loc 1 42 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $42, %edx
movl $.LC0, %esi
movl $.LC3, %edi
call __assert_fail
.L6:
.loc 1 43 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
call _ZN2C19testcase3Ev
.loc 1 43 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L7
.loc 1 43 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $43, %edx
movl $.LC0, %esi
movl $.LC4, %edi
call __assert_fail
.L7:
.loc 1 44 0 is_stmt 1
leaq -16(%rbp), %rax
movq %rax, %rdi
call _ZN2C19testcase4Ev
.loc 1 44 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L8
.loc 1 44 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $44, %edx
movl $.LC0, %esi
movl $.LC5, %edi
call __assert_fail
.L8:
.loc 1 45 0 is_stmt 1
leaq -32(%rbp), %rax
movq %rax, %rdi
call _ZN2C29testcase1Ev
.loc 1 45 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L9
.loc 1 45 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $45, %edx
movl $.LC0, %esi
movl $.LC6, %edi
call __assert_fail
.L9:
.loc 1 46 0 is_stmt 1
leaq -32(%rbp), %rax
movq %rax, %rdi
call _ZN2C29testcase2Ev
.loc 1 46 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L10
.loc 1 46 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $46, %edx
movl $.LC0, %esi
movl $.LC7, %edi
call __assert_fail
.L10:
.loc 1 47 0 is_stmt 1
leaq -32(%rbp), %rax
movq %rax, %rdi
call _ZN2C29testcase3Ev
.loc 1 47 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L11
.loc 1 47 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $47, %edx
movl $.LC0, %esi
movl $.LC8, %edi
call __assert_fail
.L11:
.loc 1 48 0 is_stmt 1
leaq -32(%rbp), %rax
movq %rax, %rdi
call _ZN2C29testcase4Ev
.loc 1 48 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L12
.loc 1 48 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $48, %edx
movl $.LC0, %esi
movl $.LC9, %edi
call __assert_fail
.L12:
.loc 1 49 0 is_stmt 1
movl $c3, %edi
call _ZN2C39testcase1Ev
.loc 1 49 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L13
.loc 1 49 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $49, %edx
movl $.LC0, %esi
movl $.LC10, %edi
call __assert_fail
.L13:
.loc 1 50 0 is_stmt 1
movl $c3, %edi
call _ZN2C39testcase2Ev
.loc 1 50 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L14
.loc 1 50 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $50, %edx
movl $.LC0, %esi
movl $.LC11, %edi
call __assert_fail
.L14:
.loc 1 51 0 is_stmt 1
movl $c3, %edi
call _ZN2C39testcase3Ev
.loc 1 51 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L15
.loc 1 51 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $51, %edx
movl $.LC0, %esi
movl $.LC12, %edi
call __assert_fail
.L15:
.loc 1 52 0 is_stmt 1
call _Z3t12v
.loc 1 52 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L16
.loc 1 52 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $52, %edx
movl $.LC0, %esi
movl $.LC13, %edi
call __assert_fail
.L16:
.loc 1 53 0 is_stmt 1
call _Z3t13v
.loc 1 53 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L17
.loc 1 53 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $53, %edx
movl $.LC0, %esi
movl $.LC14, %edi
call __assert_fail
.L17:
.loc 1 54 0 is_stmt 1
call _Z3t16v
.loc 1 54 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L18
.loc 1 54 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $54, %edx
movl $.LC0, %esi
movl $.LC15, %edi
call __assert_fail
.L18:
.loc 1 55 0 is_stmt 1
call _Z4t16av
.loc 1 55 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L19
.loc 1 55 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $55, %edx
movl $.LC0, %esi
movl $.LC16, %edi
call __assert_fail
.L19:
.loc 1 56 0 is_stmt 1
call _Z3t17v
.loc 1 56 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L20
.loc 1 56 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $56, %edx
movl $.LC0, %esi
movl $.LC17, %edi
call __assert_fail
.L20:
.loc 1 57 0 is_stmt 1
call _Z3t18v
.LEHE0:
.loc 1 57 0 is_stmt 0 discriminator 1
testb %al, %al
jne .L21
.loc 1 57 0 discriminator 2
movl $_ZZ4mainE19__PRETTY_FUNCTION__, %ecx
movl $57, %edx
movl $.LC0, %esi
movl $.LC18, %edi
call __assert_fail
.L21:
.loc 1 58 0 is_stmt 1
movl $0, %eax
jmp .L25
.L24:
movq %rax, %rdi
.LEHB1:
call _Unwind_Resume
.LEHE1:
.L25:
.LBE2:
.loc 1 59 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA1:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE1-.LLSDACSB1
.LLSDACSB1:
.uleb128 .LEHB0-.LFB1
.uleb128 .LEHE0-.LEHB0
.uleb128 .L24-.LFB1
.uleb128 0
.uleb128 .LEHB1-.LFB1
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE1:
.text
.size main, .-main
.section .rodata
.type _ZZ4mainE19__PRETTY_FUNCTION__, @object
.size _ZZ4mainE19__PRETTY_FUNCTION__, 11
_ZZ4mainE19__PRETTY_FUNCTION__:
.string "int main()"
.text
.Letext0:
.file 2 "dwp_test.h"
.section .debug_types.dwo,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0xf7
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x8a
.byte 0xda
.byte 0x59
.byte 0x6e
.byte 0x4d
.byte 0x5c
.byte 0xa
.byte 0x88
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C3"
.byte 0x4
.byte 0x2
.byte 0x2f
.long 0xda
.uleb128 0x3
.uleb128 0x3
.byte 0x2
.byte 0x36
.long 0xda
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x2
.byte 0x32
.string "_ZN2C39testcase1Ev"
.long 0xe1
.byte 0x1
.long 0x5e
.long 0x64
.uleb128 0x5
.long 0xe9
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x2
.byte 0x33
.string "_ZN2C39testcase2Ev"
.long 0xe1
.byte 0x1
.long 0x88
.long 0x8e
.uleb128 0x5
.long 0xe9
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x2
.byte 0x34
.string "_ZN2C39testcase3Ev"
.long 0xe1
.byte 0x1
.long 0xb2
.long 0xb8
.uleb128 0x5
.long 0xe9
.byte 0
.uleb128 0x6
.string "f4"
.byte 0x2
.byte 0x35
.string "_ZN2C32f4Ev"
.long 0xef
.byte 0x1
.long 0xd3
.uleb128 0x5
.long 0xe9
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.uleb128 0x8
.byte 0x8
.long 0xf5
.uleb128 0x9
.long 0xe1
.byte 0
.section .debug_types,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x71
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_main.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.66526f88bcc798ab,comdat
.long 0xf1
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x4b
.byte 0xf9
.byte 0xce
.byte 0xbf
.byte 0xd8
.byte 0xf0
.byte 0x4a
.byte 0xae
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C2"
.byte 0x4
.byte 0x2
.byte 0x25
.long 0xdf
.uleb128 0x3
.uleb128 0x3
.byte 0x2
.byte 0x2c
.long 0xdf
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x2
.byte 0x28
.string "_ZN2C29testcase1Ev"
.long 0xe6
.byte 0x1
.long 0x5e
.long 0x64
.uleb128 0x5
.long 0xee
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x2
.byte 0x29
.string "_ZN2C29testcase2Ev"
.long 0xe6
.byte 0x1
.long 0x88
.long 0x8e
.uleb128 0x5
.long 0xee
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x2
.byte 0x2a
.string "_ZN2C29testcase3Ev"
.long 0xe6
.byte 0x1
.long 0xb2
.long 0xb8
.uleb128 0x5
.long 0xee
.byte 0
.uleb128 0xa
.uleb128 0x4
.byte 0x2
.byte 0x2b
.string "_ZN2C29testcase4Ev"
.long 0xe6
.byte 0x1
.long 0xd8
.uleb128 0x5
.long 0xee
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.66526f88bcc798ab,comdat
.long 0x71
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_main.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x141
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0xe3
.byte 0xad
.byte 0x5
.byte 0x3b
.byte 0x75
.byte 0xeb
.byte 0xfb
.byte 0xc7
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C1"
.byte 0x4
.byte 0x2
.byte 0x19
.long 0x12f
.uleb128 0x3
.uleb128 0x3
.byte 0x2
.byte 0x22
.long 0x12f
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x2
.byte 0x1c
.string "_ZN2C19testcase1Ev"
.long 0x136
.byte 0x1
.long 0x5e
.long 0x64
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0xb
.string "t1a"
.byte 0x2
.byte 0x1d
.string "_ZN2C13t1aEv"
.long 0x136
.byte 0x1
.long 0x85
.long 0x8b
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0xb
.string "t1_2"
.byte 0x2
.byte 0x1e
.string "_ZN2C14t1_2Ev"
.long 0x12f
.byte 0x1
.long 0xae
.long 0xb4
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x2
.byte 0x1f
.string "_ZN2C19testcase2Ev"
.long 0x136
.byte 0x1
.long 0xd8
.long 0xde
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0x4
.uleb128 0x2
.byte 0x2
.byte 0x20
.string "_ZN2C19testcase3Ev"
.long 0x136
.byte 0x1
.long 0x102
.long 0x108
.uleb128 0x5
.long 0x13e
.byte 0
.uleb128 0xa
.uleb128 0x4
.byte 0x2
.byte 0x21
.string "_ZN2C19testcase4Ev"
.long 0x136
.byte 0x1
.long 0x128
.uleb128 0x5
.long 0x13e
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x71
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_main.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_info.dwo,"e",@progbits
.Ldebug_info0:
.long 0x178
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0xc
.string "GNU C++ 4.7.x-google 20120720 (prerelease)"
.byte 0x4
.string "dwp_test_main.cc"
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.byte 0xc8
.byte 0xeb
.byte 0x9a
.byte 0x5c
.byte 0xd9
.byte 0x51
.byte 0xba
.byte 0xe5
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0xd
.string "main"
.byte 0x1
.byte 0x1e
.long 0x90
.uleb128 0
.quad .LFE1-.LFB1
.uleb128 0x1
.byte 0x9c
.long 0x11b
.uleb128 0xe
.uleb128 0x1
.quad .LBE2-.LBB2
.uleb128 0xf
.string "c1"
.byte 0x1
.byte 0x20
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.uleb128 0x2
.byte 0x91
.sleb128 -32
.uleb128 0xf
.string "c2"
.byte 0x1
.byte 0x21
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.uleb128 0x2
.byte 0x91
.sleb128 -48
.uleb128 0x10
.string "__PRETTY_FUNCTION__"
.long 0x13f
.uleb128 0x2
.byte 0xfb
.uleb128 0x2
.uleb128 0xe
.uleb128 0x3
.quad .LBE3-.LBB3
.uleb128 0x11
.string "i"
.byte 0x1
.byte 0x25
.long 0x90
.uleb128 0x2
.byte 0x91
.sleb128 -20
.byte 0
.byte 0
.byte 0
.uleb128 0x12
.long 0x137
.long 0x12b
.uleb128 0x13
.long 0x12b
.byte 0xa
.byte 0
.uleb128 0x7
.byte 0x8
.byte 0x7
.string "sizetype"
.uleb128 0x7
.byte 0x1
.byte 0x6
.string "char"
.uleb128 0x14
.long 0x11b
.uleb128 0x15
.string "c3"
.byte 0x2
.byte 0x39
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x16
.string "v3"
.byte 0x2
.byte 0x3c
.long 0x90
.uleb128 0x12
.long 0x137
.long 0x167
.uleb128 0x17
.byte 0
.uleb128 0x16
.string "v4"
.byte 0x2
.byte 0x3d
.long 0x15c
.uleb128 0x16
.string "v5"
.byte 0x2
.byte 0x3e
.long 0x15c
.byte 0
.section .debug_info,"",@progbits
.Lskeleton_debug_info0:
.long 0x81
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.uleb128 0x1
.quad .Ltext0
.quad .Letext0-.Ltext0
.long .Ldebug_line0
.byte 0xc8
.byte 0xeb
.byte 0x9a
.byte 0x5c
.byte 0xd9
.byte 0x51
.byte 0xba
.byte 0xe5
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_main.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_abbrev,"",@progbits
.Lskeleton_debug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2131
.uleb128 0x7
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x41
.byte 0
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.byte 0
.section .debug_abbrev.dwo,"e",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x41
.byte 0x1
.uleb128 0x13
.uleb128 0xb
.uleb128 0x210f
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.uleb128 0x32
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x15
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2131
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xd
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xe
.uleb128 0xb
.byte 0x1
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xf
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x10
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x11
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x12
.uleb128 0x1
.byte 0x1
.uleb128 0x49
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x13
.uleb128 0x21
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2f
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x14
.uleb128 0x26
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x15
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x16
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x17
.uleb128 0x21
.byte 0
.byte 0
.byte 0
.byte 0
.section .debug_gnu_pubnames,"",@progbits
.Ldebug_pubnames0:
.long 0x18
.value 0x2
.long .Lskeleton_debug_info0
.long 0x17c
.long 0x9f
.byte 0x30
.string "main"
.long 0
.section .debug_gnu_pubtypes,"",@progbits
.Ldebug_pubtypes0:
.long 0x51
.value 0x2
.long .Lskeleton_debug_info0
.long 0x17c
.long 0x90
.byte 0x90
.string "int"
.long 0x97
.byte 0x90
.string "bool"
.long 0
.byte 0x10
.string "C1"
.long 0
.byte 0x10
.string "C2"
.long 0
.byte 0x10
.string "C3"
.long 0x12b
.byte 0x90
.string "sizetype"
.long 0x137
.byte 0x90
.string "char"
.long 0
.section .debug_aranges,"",@progbits
.long 0x2c
.value 0x2
.long .Lskeleton_debug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_line.dwo,"e",@progbits
.Lskeleton_debug_line0:
.long .LELT0-.LSLT0
.LSLT0:
.value 0x4
.long .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf2
.byte 0xd
.byte 0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0
.byte 0
.byte 0
.byte 0x1
.byte 0
.byte 0
.byte 0x1
.byte 0
.string "dwp_test_main.cc"
.uleb128 0
.uleb128 0
.uleb128 0
.string "dwp_test.h"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.LELTP0:
.LELT0:
.section .debug_str_offsets.dwo,"e",@progbits
.long 0
.long 0xa
.long 0x14
.long 0x1e
.long 0x26
.section .debug_str.dwo,"e",@progbits
.LASF0:
.string "testcase1"
.LASF1:
.string "testcase2"
.LASF2:
.string "testcase3"
.LASF3:
.string "member1"
.LASF4:
.string "testcase4"
.section .debug_addr,"",@progbits
.Ldebug_addr0:
.quad .LFB1
.quad .LBB2
.quad _ZZ4mainE19__PRETTY_FUNCTION__
.quad .LBB3
.ident "GCC: (Google_crosstoolv16-gcc-4.7.x-grtev3) 4.7.x-google 20120720 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 8,232
|
gold/testsuite/dwp_test_1b.s
|
.file "dwp_test_1b.cc"
.text
.Ltext0:
.globl c3
.bss
.align 4
.type c3, @object
.size c3, 4
c3:
.zero 4
.text
.globl _Z4t16av
.type _Z4t16av, @function
_Z4t16av:
.LFB1:
.file 1 "dwp_test_1b.cc"
.loc 1 33 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 1 34 0
call _Z3f10v
cmpl $135, %eax
sete %al
.loc 1 35 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.size _Z4t16av, .-_Z4t16av
.Letext0:
.file 2 "dwp_test.h"
.section .debug_types.dwo,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x119
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x8a
.byte 0xda
.byte 0x59
.byte 0x6e
.byte 0x4d
.byte 0x5c
.byte 0xa
.byte 0x88
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C3"
.byte 0x4
.byte 0x2
.byte 0x2f
.long 0xfc
.uleb128 0x3
.string "member1"
.byte 0x2
.byte 0x36
.long 0xfc
.byte 0
.byte 0x1
.uleb128 0x4
.string "testcase1"
.byte 0x2
.byte 0x32
.string "_ZN2C39testcase1Ev"
.long 0x103
.byte 0x1
.long 0x6e
.long 0x74
.uleb128 0x5
.long 0x10b
.byte 0
.uleb128 0x4
.string "testcase2"
.byte 0x2
.byte 0x33
.string "_ZN2C39testcase2Ev"
.long 0x103
.byte 0x1
.long 0xa1
.long 0xa7
.uleb128 0x5
.long 0x10b
.byte 0
.uleb128 0x4
.string "testcase3"
.byte 0x2
.byte 0x34
.string "_ZN2C39testcase3Ev"
.long 0x103
.byte 0x1
.long 0xd4
.long 0xda
.uleb128 0x5
.long 0x10b
.byte 0
.uleb128 0x6
.string "f4"
.byte 0x2
.byte 0x35
.string "_ZN2C32f4Ev"
.long 0x111
.byte 0x1
.long 0xf5
.uleb128 0x5
.long 0x10b
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.uleb128 0x8
.byte 0x8
.long 0x117
.uleb128 0x9
.long 0x103
.byte 0
.section .debug_types,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x6f
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1b.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_info.dwo,"e",@progbits
.Ldebug_info0:
.long 0xcb
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0xa
.string "GNU C++ 4.7.x-google 20120720 (prerelease)"
.byte 0x4
.string "dwp_test_1b.cc"
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.byte 0xf6
.byte 0xef
.byte 0x47
.byte 0xa2
.byte 0x3e
.byte 0xc1
.byte 0x6e
.byte 0xbd
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0xb
.string "t16a"
.byte 0x1
.byte 0x20
.string "_Z4t16av"
.long 0x95
.uleb128 0
.quad .LFE1-.LFB1
.uleb128 0x1
.byte 0x9c
.uleb128 0xc
.string "c3"
.byte 0x1
.byte 0x1d
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x2
.byte 0xfb
.uleb128 0x1
.byte 0
.section .debug_info,"",@progbits
.Lskeleton_debug_info0:
.long 0x7f
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.uleb128 0x1
.quad .Ltext0
.quad .Letext0-.Ltext0
.long .Ldebug_line0
.byte 0xf6
.byte 0xef
.byte 0x47
.byte 0xa2
.byte 0x3e
.byte 0xc1
.byte 0x6e
.byte 0xbd
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1b.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_abbrev,"",@progbits
.Lskeleton_debug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2131
.uleb128 0x7
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x41
.byte 0
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.byte 0
.section .debug_abbrev.dwo,"e",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x41
.byte 0x1
.uleb128 0x13
.uleb128 0xb
.uleb128 0x210f
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.uleb128 0x32
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x15
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2131
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.byte 0
.section .debug_gnu_pubnames,"",@progbits
.Ldebug_pubnames0:
.long 0x20
.value 0x2
.long .Lskeleton_debug_info0
.long 0xcf
.long 0x9d
.byte 0x30
.string "t16a"
.long 0xbd
.byte 0x20
.string "c3"
.long 0
.section .debug_gnu_pubtypes,"",@progbits
.Ldebug_pubtypes0:
.long 0x29
.value 0x2
.long .Lskeleton_debug_info0
.long 0xcf
.long 0x8e
.byte 0x90
.string "int"
.long 0x95
.byte 0x90
.string "bool"
.long 0
.byte 0x10
.string "C3"
.long 0
.section .debug_aranges,"",@progbits
.long 0x2c
.value 0x2
.long .Lskeleton_debug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_line.dwo,"e",@progbits
.Lskeleton_debug_line0:
.long .LELT0-.LSLT0
.LSLT0:
.value 0x4
.long .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf2
.byte 0xd
.byte 0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0
.byte 0
.byte 0
.byte 0x1
.byte 0
.byte 0
.byte 0x1
.byte 0
.string "dwp_test_1b.cc"
.uleb128 0
.uleb128 0
.uleb128 0
.string "dwp_test.h"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.LELTP0:
.LELT0:
.section .debug_addr,"",@progbits
.Ldebug_addr0:
.quad .LFB1
.quad c3
.ident "GCC: (Google_crosstoolv16-gcc-4.7.x-grtev3) 4.7.x-google 20120720 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 1,297
|
gold/testsuite/thumb_bl_out_of_range_local.s
|
# thumb_bl_out_of_range_local.s
# Test THUMB/THUMB-2 bl instructions just out of the branch range limits
# and with local branch targets.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 6
.code 16
.thumb_func
.type .Lbackward_target, %function
.Lbackward_target:
bx lr
.size .Lbackward_target, .-.Lbackward_target
.text
# Use 256-byte alignment so that we know where the stubs start.
.align 8
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
bl .Lbackward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
bl .Lforward_target
.size _forward_test, .-_forward_test
# Switch back to ARM mode so that we can see stubs
.align 2
.code 32
# Align stub table for address matching.
.align 8
.section .text.post,"x"
# Add padding so that target is just out of branch range.
.space 12
.code 16
.thumb_func
.type .Lforward_target, %function
.Lforward_target:
bx lr
.size .Lforward_target, .-.Lforward_target
|
stsp/binutils-ia16
| 1,345
|
gold/testsuite/thumb_blx_in_range.s
|
# thumb_blx_in_range.s
#
# Test THUMB/THUMB-2 blx instructions just within the branch range limits.
# Because bit 1 of the branch target comes from the branch instruction
# address, the branch range from PC (branch instruction address + 4) is
# acutally -((1<<22) + 2) to ((1<<22) - 4) for THUMB and -((1<<24) + 2) to
# ((1<<24) - 4) from THUMB2.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.align 2
.global _backward_target
.code 32
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
nop.n
blx _backward_target
.size _backward_test, .-_backward_test
.align 2
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
blx _forward_target
.size _forward_test, .-_forward_test
.code 32
.section .text.post,"x"
# Add padding so that target is just in branch range.
.space 12
.align 2
.global _forward_target
.code 32
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
stsp/binutils-ia16
| 1,304
|
gold/testsuite/aarch64_relocs.s
|
.text
test_R_AARCH64_MOVW_UABS_G0:
movz x4, :abs_g0:abs_0x1234
movz x4, :abs_g0:abs_0x1234 + 4
test_R_AARCH64_MOVW_UABS_G0_NC:
movz x4, :abs_g0_nc:abs_0x1234
movz x4, :abs_g0_nc:abs_0x1234 + 0x45000
test_R_AARCH64_MOVW_UABS_G1:
movz x4, :abs_g1:abs_0x1234 - 4
movz x4, :abs_g1:abs_0x11000
movz x4, :abs_g1:abs_0x45000 + 0x20010
test_R_AARCH64_MOVW_UABS_G1_NC:
movz x4, :abs_g1_nc:abs_0x1234 - 4
movz x4, :abs_g1_nc:abs_0x11000
movz x4, :abs_g1_nc:abs_0x45000 + 0x100020010
test_R_AARCH64_MOVW_UABS_G2:
movz x4, :abs_g2:abs_0x45000 + 0x20010
movz x4, :abs_g2:abs_0x3600010000 + 0x100020010
test_R_AARCH64_MOVW_UABS_G2_NC:
movz x4, :abs_g2_nc:abs_0x45000 + 0x20010
movz x4, :abs_g2_nc:abs_0x3600010000 + 0x3000100020010
test_R_AARCH64_MOVW_UABS_G3:
movz x4, :abs_g3:abs_0x3600010000 + 0x100020010
movz x4, :abs_g3:abs_0x3600010000 + 0x3000100020010
test_R_AARCH64_MOVW_SABS_G0:
movz x4, :abs_g0_s:abs_0x1234 + 4
movz x4, :abs_g0_s:abs_0x1234 - 0x2345
test_R_AARCH64_MOVW_SABS_G1:
movz x4, :abs_g1_s:abs_0x1234 - 0x2345
movz x4, :abs_g1_s:abs_0x45000 + 0x20010
movz x4, :abs_g1_s:abs_0x45000 - 0x56000
test_R_AARCH64_MOVW_SABS_G2:
movz x4, :abs_g2_s:abs_0x45000 + 0x20010
movz x4, :abs_g2_s:abs_0x3600010000 + 0x100020010
movz x4, :abs_g2_s:abs_0x3600010000 - 0x4400010000
|
stsp/binutils-ia16
| 1,071
|
gold/testsuite/thumb_bl_in_range.s
|
# thumb_bl_in_range.s
# Test THUMB/THUMB-2 bl instructions just within the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
bl _backward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
bl _forward_target
.size _forward_test, .-_forward_test
.section .text.post,"x"
# Add padding so that target is just in branch range.
.space 10
.global _forward_target
.code 16
.thumb_func
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
stsp/binutils-ia16
| 1,301
|
gold/testsuite/thumb_bl_out_of_range.s
|
# thumb_bl_out_of_range.s
# Test THUMB/THUMB-2 bl instructions just out of the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 6
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Use 256-byte alignment so that we know where the stubs start.
.align 8
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
bl _backward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
bl _forward_target
.size _forward_test, .-_forward_test
# switch back to ARM mode so that stubs are disassembled correctly.
.align 2
.code 32
# Align stub table for address matching.
.align 8
.section .text.post,"x"
# Add padding so that target is just out of branch range.
.space 12
.global _forward_target
.code 16
.thumb_func
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
stsp/binutils-ia16
| 1,549
|
gold/testsuite/thumb_blx_out_of_range.s
|
# thumb_blx_out_of_range.s
# Test THUMB/THUMB-2 blx instructions just out of the branch range limits.
.syntax unified
.section .text.pre,"x"
# Add padding so that target is just output of branch range.
.space 4
.global _forward_target
.global _backward_target
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Use 256-byte alignment so that we know where the stubs start.
.align 8
# Define _start so that linker does not complain.
.align 2
.global _start
.code 32
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
bl _backward_target
.size _backward_test, .-_backward_test
.align 2
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
# Bit 1 of the BLX target comes from bit 1 of branch base address,
# which is BLX instruction's address + 4. We intentionally put this
# forward BLX at an address n*4 + 2 so that the branch offset is
# bumped up by 2.
nop.n
bl _forward_target
.size _forward_test, .-_forward_test
# switch back to ARM mode so that stubs are disassembled correctly.
.align 2
.code 32
# Align stub table for address matching.
.align 8
.section .text.post,"x"
# Add padding so that target is just out of branch range.
.space 12
.align 2
.code 32
.global _forward_target
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
stsp/binutils-ia16
| 1,433
|
gold/testsuite/pr20308_gd.S
|
.text
.p2align 4,,15
.globl get_gd
.type get_gd, @function
get_gd:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal gd@tlsgd(,%ebx,1), %eax
call ___tls_get_addr@PLT
addl $8, %esp
popl %ebx
ret
.size get_gd, .-get_gd
.p2align 4,,15
.globl set_gd
.type set_gd, @function
set_gd:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal gd@tlsgd(%ebx), %eax
call ___tls_get_addr@PLT
nop
movl 16(%esp), %edx
movl %edx, (%eax)
addl $8, %esp
popl %ebx
ret
.size set_gd, .-set_gd
.text
.p2align 4,,15
.globl test_gd
.type test_gd, @function
test_gd:
call __x86.get_pc_thunk.cx
addl $_GLOBAL_OFFSET_TABLE_, %ecx
subl $12, %esp
leal gd@tlsgd(%ecx), %eax
call *___tls_get_addr@GOT(%ecx)
movl 16(%esp), %ecx
cmpl %ecx, (%eax)
sete %al
addl $12, %esp
movzbl %al, %eax
ret
.size test_gd, .-test_gd
.section .text.unlikely
.section .text.__x86.get_pc_thunk.bx,"axG",@progbits,__x86.get_pc_thunk.bx,comdat
.globl __x86.get_pc_thunk.bx
.hidden __x86.get_pc_thunk.bx
.type __x86.get_pc_thunk.bx, @function
__x86.get_pc_thunk.bx:
movl (%esp), %ebx
ret
.section .text.__x86.get_pc_thunk.cx,"axG",@progbits,__x86.get_pc_thunk.cx,comdat
.globl __x86.get_pc_thunk.cx
.hidden __x86.get_pc_thunk.cx
.type __x86.get_pc_thunk.cx, @function
__x86.get_pc_thunk.cx:
movl (%esp), %ecx
ret
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 1,074
|
gold/testsuite/gnu_property_b.S
|
#define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEOF_PTRDIFF_T__ == 4
# define ALIGN 2
#endif
.section ".note.gnu.property", "a"
.p2align ALIGN
.long 1f - 0f /* name length */
.long 3f - 2f /* data length */
.long NT_GNU_PROPERTY_TYPE_0 /* note type */
0: .asciz "GNU" /* vendor name */
1:
.p2align ALIGN
2: .long GNU_PROPERTY_NO_COPY_ON_PROTECTED /* pr_type. */
.long 0 /* pr_datasz. */
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_USED
.long 4
.byte 0x01,0x11,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_NEEDED
.long 4
.byte 0x01,0x11,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_FEATURE_1_AND
.long 4
.byte 0x03,0x00,0x00,0x00
.p2align ALIGN
3:
|
stsp/binutils-ia16
| 1,565
|
gold/testsuite/pr20308_ld.S
|
.text
.p2align 4,,15
.globl get_ld
.type get_ld, @function
get_ld:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal ld@tlsldm(%ebx), %eax
call ___tls_get_addr@PLT
leal ld@dtpoff(%eax), %eax
addl $8, %esp
popl %ebx
ret
.size get_ld, .-get_ld
.p2align 4,,15
.globl set_ld
.type set_ld, @function
set_ld:
pushl %ebx
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
subl $8, %esp
leal ld@tlsldm(%ebx), %eax
call ___tls_get_addr@PLT
movl 16(%esp), %edx
leal ld@dtpoff(%eax), %eax
movl %edx, (%eax)
addl $8, %esp
popl %ebx
ret
.size set_ld, .-set_ld
.p2align 4,,15
.globl test_ld
.type test_ld, @function
test_ld:
call __x86.get_pc_thunk.cx
addl $_GLOBAL_OFFSET_TABLE_, %ecx
subl $12, %esp
leal ld@tlsldm(%ecx), %eax
call *___tls_get_addr@GOT(%ecx)
movl 16(%esp), %ecx
leal ld@dtpoff(%eax), %eax
cmpl %ecx, (%eax)
sete %al
addl $12, %esp
movzbl %al, %eax
ret
.size test_ld, .-test_ld
.section .tbss,"awT",@nobits
.align 4
.type ld, @object
.size ld, 4
ld:
.zero 4
.section .text.__x86.get_pc_thunk.bx,"axG",@progbits,__x86.get_pc_thunk.bx,comdat
.globl __x86.get_pc_thunk.bx
.hidden __x86.get_pc_thunk.bx
.type __x86.get_pc_thunk.bx, @function
__x86.get_pc_thunk.bx:
movl (%esp), %ebx
ret
.section .text.__x86.get_pc_thunk.cx,"axG",@progbits,__x86.get_pc_thunk.cx,comdat
.globl __x86.get_pc_thunk.cx
.hidden __x86.get_pc_thunk.cx
.type __x86.get_pc_thunk.cx, @function
__x86.get_pc_thunk.cx:
movl (%esp), %ecx
ret
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 1,083
|
gold/testsuite/arm_thm_jump11.s
|
# arm_thm_jump11.s
# Test R_ARM_THM_JUMP11 relocations just within the branch range limits.
.syntax unified
.arch armv5te
.section .text.pre,"x"
# Add padding so that target is just in branch range.
.space 8
.global _backward_target
.code 16
.thumb_func
.type _backword_target, %function
_backward_target:
bx lr
.size _backward_target, .-_backward_target
.text
# Define _start so that linker does not complain.
.global _start
.code 32
.align 2
.type _start, %function
_start:
bx lr
.size _start, .-_start
.global _backward_test
.code 16
.thumb_func
.type _backward_test, %function
_backward_test:
b.n _backward_target
.size _backward_test, .-_backward_test
.global _forward_test
.code 16
.thumb_func
.type _forward_test, %function
_forward_test:
b.n _forward_target
.size _forward_test, .-_forward_test
.section .text.post,"x"
# Add padding so that target is just in branch range.
.space 8
.global _forward_target
.code 16
.thumb_func
.type _forward_target, %function
_forward_target:
bx lr
.size _forward_target, .-_forward_target
|
stsp/binutils-ia16
| 38,771
|
gold/testsuite/dwp_test_1.s
|
.file "dwp_test_1.cc"
.text
.Ltext0:
.section .text._Z4f13iv,"axG",@progbits,_Z4f13iv,comdat
.weak _Z4f13iv
.type _Z4f13iv, @function
_Z4f13iv:
.LFB0:
.file 1 "dwp_test.h"
.loc 1 70 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 1 70 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE0:
.size _Z4f13iv, .-_Z4f13iv
.text
.align 2
.globl _ZN2C19testcase1Ev
.type _ZN2C19testcase1Ev, @function
_ZN2C19testcase1Ev:
.LFB1:
.file 2 "dwp_test_1.cc"
.loc 2 31 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, -8(%rbp)
.loc 2 32 0
movq -8(%rbp), %rax
movq %rax, %rdi
call _ZN2C14t1_2Ev
cmpl $123, %eax
sete %al
.loc 2 33 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.size _ZN2C19testcase1Ev, .-_ZN2C19testcase1Ev
.align 2
.globl _ZN2C19testcase2Ev
.type _ZN2C19testcase2Ev, @function
_ZN2C19testcase2Ev:
.LFB2:
.loc 2 39 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 40 0
movl v2(%rip), %eax
cmpl $456, %eax
sete %al
.loc 2 41 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE2:
.size _ZN2C19testcase2Ev, .-_ZN2C19testcase2Ev
.align 2
.globl _ZN2C19testcase3Ev
.type _ZN2C19testcase3Ev, @function
_ZN2C19testcase3Ev:
.LFB3:
.loc 2 47 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 48 0
movl v3(%rip), %eax
cmpl $789, %eax
sete %al
.loc 2 49 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE3:
.size _ZN2C19testcase3Ev, .-_ZN2C19testcase3Ev
.align 2
.globl _ZN2C19testcase4Ev
.type _ZN2C19testcase4Ev, @function
_ZN2C19testcase4Ev:
.LFB4:
.loc 2 55 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 56 0
movzbl v4+5(%rip), %eax
cmpb $44, %al
sete %al
.loc 2 57 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE4:
.size _ZN2C19testcase4Ev, .-_ZN2C19testcase4Ev
.align 2
.globl _ZN2C29testcase1Ev
.type _ZN2C29testcase1Ev, @function
_ZN2C29testcase1Ev:
.LFB5:
.loc 2 63 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 64 0
movzbl v5+7(%rip), %eax
cmpb $119, %al
sete %al
.loc 2 65 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE5:
.size _ZN2C29testcase1Ev, .-_ZN2C29testcase1Ev
.globl p6
.data
.align 8
.type p6, @object
.size p6, 8
p6:
.quad v2
.text
.align 2
.globl _ZN2C29testcase2Ev
.type _ZN2C29testcase2Ev, @function
_ZN2C29testcase2Ev:
.LFB6:
.loc 2 73 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 74 0
movq p6(%rip), %rax
movl (%rax), %eax
cmpl $456, %eax
sete %al
.loc 2 75 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE6:
.size _ZN2C29testcase2Ev, .-_ZN2C29testcase2Ev
.globl p7
.data
.align 8
.type p7, @object
.size p7, 8
p7:
.quad v3
.text
.align 2
.globl _ZN2C29testcase3Ev
.type _ZN2C29testcase3Ev, @function
_ZN2C29testcase3Ev:
.LFB7:
.loc 2 83 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 84 0
movq p7(%rip), %rax
movl (%rax), %eax
cmpl $789, %eax
sete %al
.loc 2 85 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE7:
.size _ZN2C29testcase3Ev, .-_ZN2C29testcase3Ev
.globl p8
.data
.align 8
.type p8, @object
.size p8, 8
p8:
.quad v4+6
.text
.align 2
.globl _ZN2C29testcase4Ev
.type _ZN2C29testcase4Ev, @function
_ZN2C29testcase4Ev:
.LFB8:
.loc 2 93 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 94 0
movq p8(%rip), %rax
movzbl (%rax), %eax
cmpb $32, %al
sete %al
.loc 2 95 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE8:
.size _ZN2C29testcase4Ev, .-_ZN2C29testcase4Ev
.globl p9
.data
.align 8
.type p9, @object
.size p9, 8
p9:
.quad v5+8
.text
.align 2
.globl _ZN2C39testcase1Ev
.type _ZN2C39testcase1Ev, @function
_ZN2C39testcase1Ev:
.LFB9:
.loc 2 103 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movq %rdi, -8(%rbp)
.loc 2 104 0
movq p9(%rip), %rax
movzbl (%rax), %eax
cmpb $111, %al
sete %al
.loc 2 105 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE9:
.size _ZN2C39testcase1Ev, .-_ZN2C39testcase1Ev
.globl pfn
.data
.align 8
.type pfn, @object
.size pfn, 8
pfn:
.quad _Z3f10v
.text
.align 2
.globl _ZN2C39testcase2Ev
.type _ZN2C39testcase2Ev, @function
_ZN2C39testcase2Ev:
.LFB10:
.loc 2 113 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, -8(%rbp)
.loc 2 114 0
movq pfn(%rip), %rax
call *%rax
cmpl $135, %eax
sete %al
.loc 2 115 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE10:
.size _ZN2C39testcase2Ev, .-_ZN2C39testcase2Ev
.globl _Z4f11av
.type _Z4f11av, @function
_Z4f11av:
.LFB11:
.loc 2 121 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 122 0
movl $246, %eax
.loc 2 123 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE11:
.size _Z4f11av, .-_Z4f11av
.align 2
.globl _ZN2C39testcase3Ev
.type _ZN2C39testcase3Ev, @function
_ZN2C39testcase3Ev:
.LFB12:
.loc 2 127 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, -8(%rbp)
.loc 2 128 0
movl $_Z4f11av, %edi
call _Z4f11bPFivE
cmpl $246, %eax
sete %al
.loc 2 129 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE12:
.size _ZN2C39testcase3Ev, .-_ZN2C39testcase3Ev
.globl _Z3t12v
.type _Z3t12v, @function
_Z3t12v:
.LFB13:
.loc 2 135 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 136 0
movl $c3, %edi
call _ZN2C32f4Ev
cmpq $_Z3t12v, %rax
sete %al
.loc 2 137 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE13:
.size _Z3t12v, .-_Z3t12v
.globl _Z3t13v
.type _Z3t13v, @function
_Z3t13v:
.LFB14:
.loc 2 143 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 144 0
call _Z3f13v
cmpq $_Z4f13iv, %rax
sete %al
.loc 2 145 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE14:
.size _Z3t13v, .-_Z3t13v
.section .rodata
.LC0:
.string "test string constant"
.text
.globl _Z3t14v
.type _Z3t14v, @function
_Z3t14v:
.LFB15:
.loc 2 151 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
.LBB2:
.loc 2 152 0
movq $.LC0, -8(%rbp)
.loc 2 153 0
call _Z3f14v
movq %rax, -16(%rbp)
.loc 2 154 0
jmp .L31
.L33:
.loc 2 155 0
movq -8(%rbp), %rax
movzbl (%rax), %edx
movq -16(%rbp), %rax
movzbl (%rax), %eax
cmpb %al, %dl
setne %al
addq $1, -8(%rbp)
addq $1, -16(%rbp)
testb %al, %al
je .L31
.loc 2 156 0
movl $0, %eax
jmp .L32
.L31:
.loc 2 154 0 discriminator 1
movq -8(%rbp), %rax
movzbl (%rax), %eax
testb %al, %al
setne %al
testb %al, %al
jne .L33
.loc 2 157 0
movq -16(%rbp), %rax
movzbl (%rax), %eax
testb %al, %al
sete %al
.L32:
.LBE2:
.loc 2 158 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE15:
.size _Z3t14v, .-_Z3t14v
.section .rodata
.align 8
.LC1:
.string "t"
.string ""
.string ""
.string "e"
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "w"
.string ""
.string ""
.string "i"
.string ""
.string ""
.string "d"
.string ""
.string ""
.string "e"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string "r"
.string ""
.string ""
.string "i"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "g"
.string ""
.string ""
.string " "
.string ""
.string ""
.string "c"
.string ""
.string ""
.string "o"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "s"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string "a"
.string ""
.string ""
.string "n"
.string ""
.string ""
.string "t"
.string ""
.string ""
.string ""
.string ""
.string ""
.string ""
.text
.globl _Z3t15v
.type _Z3t15v, @function
_Z3t15v:
.LFB16:
.loc 2 164 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
.LBB3:
.loc 2 165 0
movq $.LC1, -8(%rbp)
.loc 2 166 0
call _Z3f15v
movq %rax, -16(%rbp)
.loc 2 167 0
jmp .L35
.L37:
.loc 2 168 0
movq -8(%rbp), %rax
movl (%rax), %edx
movq -16(%rbp), %rax
movl (%rax), %eax
cmpl %eax, %edx
setne %al
addq $4, -8(%rbp)
addq $4, -16(%rbp)
testb %al, %al
je .L35
.loc 2 169 0
movl $0, %eax
jmp .L36
.L35:
.loc 2 167 0 discriminator 1
movq -8(%rbp), %rax
movl (%rax), %eax
testl %eax, %eax
setne %al
testb %al, %al
jne .L37
.loc 2 170 0
movq -16(%rbp), %rax
movl (%rax), %eax
testl %eax, %eax
sete %al
.L36:
.LBE3:
.loc 2 171 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE16:
.size _Z3t15v, .-_Z3t15v
.globl _Z3t16v
.type _Z3t16v, @function
_Z3t16v:
.LFB17:
.loc 2 177 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.loc 2 178 0
call _Z3f10v
cmpl $135, %eax
sete %al
.loc 2 179 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE17:
.size _Z3t16v, .-_Z3t16v
.globl _Z3t17v
.type _Z3t17v, @function
_Z3t17v:
.LFB18:
.loc 2 185 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
.LBB4:
.loc 2 186 0
movb $97, -1(%rbp)
.LBB5:
.loc 2 187 0
movl $0, -8(%rbp)
jmp .L41
.L45:
.loc 2 189 0
movl -8(%rbp), %eax
cltq
movq t17data(,%rax,8), %rax
movzbl (%rax), %eax
cmpb -1(%rbp), %al
jne .L42
.loc 2 189 0 is_stmt 0 discriminator 1
movl -8(%rbp), %eax
cltq
movq t17data(,%rax,8), %rax
addq $1, %rax
movzbl (%rax), %eax
testb %al, %al
je .L43
.L42:
.loc 2 190 0 is_stmt 1
movl $0, %eax
jmp .L44
.L43:
.loc 2 191 0
addb $1, -1(%rbp)
.loc 2 187 0
addl $1, -8(%rbp)
.L41:
.loc 2 187 0 is_stmt 0 discriminator 1
cmpl $4, -8(%rbp)
setle %al
testb %al, %al
jne .L45
.LBE5:
.loc 2 193 0 is_stmt 1
movl $1, %eax
.L44:
.LBE4:
.loc 2 194 0
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE18:
.size _Z3t17v, .-_Z3t17v
.globl _Z3t18v
.type _Z3t18v, @function
_Z3t18v:
.LFB19:
.loc 2 200 0
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
.LBB6:
.loc 2 201 0
movb $97, -1(%rbp)
.LBB7:
.loc 2 202 0
movl $0, -8(%rbp)
jmp .L47
.L51:
.LBB8:
.loc 2 204 0
movl -8(%rbp), %eax
movl %eax, %edi
call _Z3f18i
movq %rax, -16(%rbp)
.loc 2 205 0
movq -16(%rbp), %rax
movzbl (%rax), %eax
cmpb -1(%rbp), %al
jne .L48
.loc 2 205 0 is_stmt 0 discriminator 1
movq -16(%rbp), %rax
addq $1, %rax
movzbl (%rax), %eax
testb %al, %al
je .L49
.L48:
.loc 2 206 0 is_stmt 1
movl $0, %eax
jmp .L50
.L49:
.loc 2 207 0
addb $1, -1(%rbp)
.LBE8:
.loc 2 202 0
addl $1, -8(%rbp)
.L47:
.loc 2 202 0 is_stmt 0 discriminator 1
cmpl $4, -8(%rbp)
setle %al
testb %al, %al
jne .L51
.LBE7:
.loc 2 209 0 is_stmt 1
movl $1, %eax
.L50:
.LBE6:
.loc 2 210 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE19:
.size _Z3t18v, .-_Z3t18v
.Letext0:
.section .debug_types.dwo,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0xc1
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x8a
.byte 0xda
.byte 0x59
.byte 0x6e
.byte 0x4d
.byte 0x5c
.byte 0xa
.byte 0x88
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C3"
.byte 0x4
.byte 0x1
.byte 0x2f
.long 0xa4
.uleb128 0x3
.uleb128 0x6
.byte 0x1
.byte 0x36
.long 0xa4
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x32
.uleb128 0x2
.long 0xab
.byte 0x1
.long 0x4c
.long 0x52
.uleb128 0x5
.long 0xb3
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x33
.uleb128 0x3
.long 0xab
.byte 0x1
.long 0x64
.long 0x6a
.uleb128 0x5
.long 0xb3
.byte 0
.uleb128 0x4
.uleb128 0x4
.byte 0x1
.byte 0x34
.uleb128 0x5
.long 0xab
.byte 0x1
.long 0x7c
.long 0x82
.uleb128 0x5
.long 0xb3
.byte 0
.uleb128 0x6
.string "f4"
.byte 0x1
.byte 0x35
.string "_ZN2C32f4Ev"
.long 0xb9
.byte 0x1
.long 0x9d
.uleb128 0x5
.long 0xb3
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.uleb128 0x8
.byte 0x8
.long 0xbf
.uleb128 0x9
.long 0xab
.byte 0
.section .debug_types,"G",@progbits,wt.bb2916f0c1bd34b5,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.66526f88bcc798ab,comdat
.long 0xa9
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0x4b
.byte 0xf9
.byte 0xce
.byte 0xbf
.byte 0xd8
.byte 0xf0
.byte 0x4a
.byte 0xae
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C2"
.byte 0x4
.byte 0x1
.byte 0x25
.long 0x97
.uleb128 0x3
.uleb128 0x6
.byte 0x1
.byte 0x2c
.long 0x97
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x28
.uleb128 0x7
.long 0x9e
.byte 0x1
.long 0x4c
.long 0x52
.uleb128 0x5
.long 0xa6
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x29
.uleb128 0x8
.long 0x9e
.byte 0x1
.long 0x64
.long 0x6a
.uleb128 0x5
.long 0xa6
.byte 0
.uleb128 0x4
.uleb128 0x4
.byte 0x1
.byte 0x2a
.uleb128 0x9
.long 0x9e
.byte 0x1
.long 0x7c
.long 0x82
.uleb128 0x5
.long 0xa6
.byte 0
.uleb128 0xa
.uleb128 0xa
.byte 0x1
.byte 0x2b
.uleb128 0xb
.long 0x9e
.byte 0x1
.long 0x90
.uleb128 0x5
.long 0xa6
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.66526f88bcc798ab,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_types.dwo,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0xf9
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0x25
.uleb128 0x1
.byte 0x4
.byte 0xe3
.byte 0xad
.byte 0x5
.byte 0x3b
.byte 0x75
.byte 0xeb
.byte 0xfb
.byte 0xc7
.long .Lskeleton_debug_line0
.uleb128 0x2
.string "C1"
.byte 0x4
.byte 0x1
.byte 0x19
.long 0xe7
.uleb128 0x3
.uleb128 0x6
.byte 0x1
.byte 0x22
.long 0xe7
.byte 0
.byte 0x1
.uleb128 0x4
.uleb128 0
.byte 0x1
.byte 0x1c
.uleb128 0xc
.long 0xee
.byte 0x1
.long 0x4c
.long 0x52
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0xb
.string "t1a"
.byte 0x1
.byte 0x1d
.string "_ZN2C13t1aEv"
.long 0xee
.byte 0x1
.long 0x73
.long 0x79
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0xb
.string "t1_2"
.byte 0x1
.byte 0x1e
.string "_ZN2C14t1_2Ev"
.long 0xe7
.byte 0x1
.long 0x9c
.long 0xa2
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0x4
.uleb128 0x1
.byte 0x1
.byte 0x1f
.uleb128 0xd
.long 0xee
.byte 0x1
.long 0xb4
.long 0xba
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0x4
.uleb128 0x4
.byte 0x1
.byte 0x20
.uleb128 0xe
.long 0xee
.byte 0x1
.long 0xcc
.long 0xd2
.uleb128 0x5
.long 0xf6
.byte 0
.uleb128 0xa
.uleb128 0xa
.byte 0x1
.byte 0x21
.uleb128 0xf
.long 0xee
.byte 0x1
.long 0xe0
.uleb128 0x5
.long 0xf6
.byte 0
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0x8
.byte 0x8
.long 0x25
.byte 0
.section .debug_types,"G",@progbits,wt.c419a9b7a4a2fab5,comdat
.long 0x6e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0
.uleb128 0x2
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_info.dwo,"e",@progbits
.Ldebug_info0:
.long 0x5af
.value 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0xc
.string "GNU C++ 4.7.x-google 20120720 (prerelease)"
.byte 0x4
.string "dwp_test_1.cc"
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.byte 0x27
.byte 0x37
.byte 0xdc
.byte 0x2f
.byte 0x9
.byte 0xc6
.byte 0xf9
.byte 0x52
.uleb128 0xd
.string "C1"
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.long 0xc6
.uleb128 0xe
.uleb128 0
.byte 0x1
.byte 0x1c
.uleb128 0xc
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x1
.byte 0x1
.byte 0x1f
.uleb128 0xd
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x4
.byte 0x1
.byte 0x20
.uleb128 0xe
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0xa
.byte 0x1
.byte 0x21
.uleb128 0xf
.long 0xcd
.byte 0x1
.byte 0
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x7
.byte 0x1
.byte 0x2
.string "bool"
.uleb128 0xf
.byte 0x8
.byte 0xc4
.byte 0x19
.byte 0xa9
.byte 0xb7
.byte 0xa4
.byte 0xa2
.byte 0xfa
.byte 0xb5
.uleb128 0xd
.string "C2"
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.long 0x118
.uleb128 0xe
.uleb128 0
.byte 0x1
.byte 0x28
.uleb128 0x7
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x1
.byte 0x1
.byte 0x29
.uleb128 0x8
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x4
.byte 0x1
.byte 0x2a
.uleb128 0x9
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0xa
.byte 0x1
.byte 0x2b
.uleb128 0xb
.long 0xcd
.byte 0x1
.byte 0
.uleb128 0xf
.byte 0x8
.byte 0x66
.byte 0x52
.byte 0x6f
.byte 0x88
.byte 0xbc
.byte 0xc7
.byte 0x98
.byte 0xab
.uleb128 0xd
.string "C3"
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.long 0x151
.uleb128 0xe
.uleb128 0
.byte 0x1
.byte 0x32
.uleb128 0x2
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x1
.byte 0x1
.byte 0x33
.uleb128 0x3
.long 0xcd
.byte 0x1
.uleb128 0xe
.uleb128 0x4
.byte 0x1
.byte 0x34
.uleb128 0x5
.long 0xcd
.byte 0x1
.byte 0
.uleb128 0xf
.byte 0x8
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x10
.string "f13i"
.byte 0x1
.byte 0x46
.string "_Z4f13iv"
.uleb128 0
.quad .LFE0-.LFB0
.uleb128 0x1
.byte 0x9c
.uleb128 0x11
.long 0x9d
.byte 0x2
.byte 0x1e
.uleb128 0x1
.quad .LFE1-.LFB1
.uleb128 0x1
.byte 0x9c
.long 0x191
.long 0x19b
.uleb128 0x12
.uleb128 0x10
.long 0x19b
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0xd5
.uleb128 0x14
.long 0xa7
.byte 0x2
.byte 0x26
.uleb128 0x2
.quad .LFE2-.LFB2
.uleb128 0x1
.byte 0x9c
.long 0x1ba
.long 0x1c4
.uleb128 0x12
.uleb128 0x10
.long 0x19b
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0xb1
.byte 0x2
.byte 0x2e
.uleb128 0x3
.quad .LFE3-.LFB3
.uleb128 0x1
.byte 0x9c
.long 0x1de
.long 0x1e8
.uleb128 0x12
.uleb128 0x10
.long 0x19b
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0xbb
.byte 0x2
.byte 0x36
.uleb128 0x4
.quad .LFE4-.LFB4
.uleb128 0x1
.byte 0x9c
.long 0x202
.long 0x20c
.uleb128 0x12
.uleb128 0x10
.long 0x19b
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0xef
.byte 0x2
.byte 0x3e
.uleb128 0x5
.quad .LFE5-.LFB5
.uleb128 0x1
.byte 0x9c
.long 0x226
.long 0x230
.uleb128 0x12
.uleb128 0x10
.long 0x230
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0x118
.uleb128 0x14
.long 0xf9
.byte 0x2
.byte 0x48
.uleb128 0x6
.quad .LFE6-.LFB6
.uleb128 0x1
.byte 0x9c
.long 0x24f
.long 0x259
.uleb128 0x12
.uleb128 0x10
.long 0x230
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0x103
.byte 0x2
.byte 0x52
.uleb128 0x7
.quad .LFE7-.LFB7
.uleb128 0x1
.byte 0x9c
.long 0x273
.long 0x27d
.uleb128 0x12
.uleb128 0x10
.long 0x230
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0x10d
.byte 0x2
.byte 0x5c
.uleb128 0x8
.quad .LFE8-.LFB8
.uleb128 0x1
.byte 0x9c
.long 0x297
.long 0x2a1
.uleb128 0x12
.uleb128 0x10
.long 0x230
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x14
.long 0x132
.byte 0x2
.byte 0x66
.uleb128 0x9
.quad .LFE9-.LFB9
.uleb128 0x1
.byte 0x9c
.long 0x2bb
.long 0x2c5
.uleb128 0x12
.uleb128 0x10
.long 0x2c5
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x13
.long 0x151
.uleb128 0x11
.long 0x13c
.byte 0x2
.byte 0x70
.uleb128 0xa
.quad .LFE10-.LFB10
.uleb128 0x1
.byte 0x9c
.long 0x2e4
.long 0x2ee
.uleb128 0x12
.uleb128 0x10
.long 0x2c5
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x15
.string "f11a"
.byte 0x2
.byte 0x78
.string "_Z4f11av"
.long 0xc6
.uleb128 0xb
.quad .LFE11-.LFB11
.uleb128 0x1
.byte 0x9c
.uleb128 0x11
.long 0x146
.byte 0x2
.byte 0x7e
.uleb128 0xc
.quad .LFE12-.LFB12
.uleb128 0x1
.byte 0x9c
.long 0x328
.long 0x332
.uleb128 0x12
.uleb128 0x10
.long 0x2c5
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.uleb128 0x16
.string "t12"
.byte 0x2
.byte 0x86
.string "_Z3t12v"
.long 0xcd
.uleb128 0xd
.quad .LFE13-.LFB13
.uleb128 0x1
.byte 0x9c
.uleb128 0x16
.string "t13"
.byte 0x2
.byte 0x8e
.string "_Z3t13v"
.long 0xcd
.uleb128 0xe
.quad .LFE14-.LFB14
.uleb128 0x1
.byte 0x9c
.uleb128 0x17
.string "t14"
.byte 0x2
.byte 0x96
.string "_Z3t14v"
.long 0xcd
.uleb128 0xf
.quad .LFE15-.LFB15
.uleb128 0x1
.byte 0x9c
.long 0x3b6
.uleb128 0x18
.uleb128 0x10
.quad .LBE2-.LBB2
.uleb128 0x19
.string "s1"
.byte 0x2
.byte 0x98
.long 0x3b6
.uleb128 0x2
.byte 0x91
.sleb128 -24
.uleb128 0x19
.string "s2"
.byte 0x2
.byte 0x99
.long 0x3b6
.uleb128 0x2
.byte 0x91
.sleb128 -32
.byte 0
.byte 0
.uleb128 0x8
.byte 0x8
.long 0x3bc
.uleb128 0x13
.long 0x3c1
.uleb128 0x7
.byte 0x1
.byte 0x6
.string "char"
.uleb128 0x17
.string "t15"
.byte 0x2
.byte 0xa3
.string "_Z3t15v"
.long 0xcd
.uleb128 0x11
.quad .LFE16-.LFB16
.uleb128 0x1
.byte 0x9c
.long 0x411
.uleb128 0x18
.uleb128 0x12
.quad .LBE3-.LBB3
.uleb128 0x19
.string "s1"
.byte 0x2
.byte 0xa5
.long 0x411
.uleb128 0x2
.byte 0x91
.sleb128 -24
.uleb128 0x19
.string "s2"
.byte 0x2
.byte 0xa6
.long 0x411
.uleb128 0x2
.byte 0x91
.sleb128 -32
.byte 0
.byte 0
.uleb128 0x8
.byte 0x8
.long 0x417
.uleb128 0x13
.long 0x41c
.uleb128 0x7
.byte 0x4
.byte 0x5
.string "wchar_t"
.uleb128 0x16
.string "t16"
.byte 0x2
.byte 0xb0
.string "_Z3t16v"
.long 0xcd
.uleb128 0x13
.quad .LFE17-.LFB17
.uleb128 0x1
.byte 0x9c
.uleb128 0x1a
.string "t17"
.byte 0x2
.byte 0xb8
.string "_Z3t17v"
.long 0xcd
.uleb128 0x14
.quad .LFE18-.LFB18
.uleb128 0x1
.byte 0x9c
.long 0x496
.uleb128 0x18
.uleb128 0x15
.quad .LBE4-.LBB4
.uleb128 0x19
.string "c"
.byte 0x2
.byte 0xba
.long 0x3c1
.uleb128 0x2
.byte 0x91
.sleb128 -17
.uleb128 0x18
.uleb128 0x16
.quad .LBE5-.LBB5
.uleb128 0x19
.string "i"
.byte 0x2
.byte 0xbb
.long 0xc6
.uleb128 0x2
.byte 0x91
.sleb128 -24
.byte 0
.byte 0
.byte 0
.uleb128 0x17
.string "t18"
.byte 0x2
.byte 0xc7
.string "_Z3t18v"
.long 0xcd
.uleb128 0x17
.quad .LFE19-.LFB19
.uleb128 0x1
.byte 0x9c
.long 0x4fe
.uleb128 0x18
.uleb128 0x18
.quad .LBE6-.LBB6
.uleb128 0x19
.string "c"
.byte 0x2
.byte 0xc9
.long 0x3c1
.uleb128 0x2
.byte 0x91
.sleb128 -17
.uleb128 0x18
.uleb128 0x19
.quad .LBE7-.LBB7
.uleb128 0x19
.string "i"
.byte 0x2
.byte 0xca
.long 0xc6
.uleb128 0x2
.byte 0x91
.sleb128 -24
.uleb128 0x18
.uleb128 0x1a
.quad .LBE8-.LBB8
.uleb128 0x19
.string "s"
.byte 0x2
.byte 0xcc
.long 0x3b6
.uleb128 0x2
.byte 0x91
.sleb128 -32
.byte 0
.byte 0
.byte 0
.byte 0
.uleb128 0x1b
.string "c3"
.byte 0x1
.byte 0x39
.byte 0xbb
.byte 0x29
.byte 0x16
.byte 0xf0
.byte 0xc1
.byte 0xbd
.byte 0x34
.byte 0xb5
.uleb128 0x1c
.string "v2"
.byte 0x1
.byte 0x3b
.long 0xc6
.uleb128 0x1c
.string "v3"
.byte 0x1
.byte 0x3c
.long 0xc6
.uleb128 0x1d
.long 0x3c1
.long 0x52b
.uleb128 0x1e
.byte 0
.uleb128 0x1c
.string "v4"
.byte 0x1
.byte 0x3d
.long 0x520
.uleb128 0x1c
.string "v5"
.byte 0x1
.byte 0x3e
.long 0x520
.uleb128 0x1d
.long 0x3b6
.long 0x54a
.uleb128 0x1e
.byte 0
.uleb128 0x1c
.string "t17data"
.byte 0x1
.byte 0x53
.long 0x53f
.uleb128 0x1f
.string "p6"
.byte 0x2
.byte 0x45
.long 0x566
.uleb128 0x2
.byte 0xfb
.uleb128 0x1b
.uleb128 0x8
.byte 0x8
.long 0xc6
.uleb128 0x1f
.string "p7"
.byte 0x2
.byte 0x4f
.long 0x566
.uleb128 0x2
.byte 0xfb
.uleb128 0x1c
.uleb128 0x1f
.string "p8"
.byte 0x2
.byte 0x59
.long 0x586
.uleb128 0x2
.byte 0xfb
.uleb128 0x1d
.uleb128 0x8
.byte 0x8
.long 0x3c1
.uleb128 0x1f
.string "p9"
.byte 0x2
.byte 0x63
.long 0x586
.uleb128 0x2
.byte 0xfb
.uleb128 0x1e
.uleb128 0x9
.long 0xc6
.uleb128 0x1f
.string "pfn"
.byte 0x2
.byte 0x6d
.long 0x5ac
.uleb128 0x2
.byte 0xfb
.uleb128 0x1f
.uleb128 0x8
.byte 0x8
.long 0x599
.byte 0
.section .debug_info,"",@progbits
.Lskeleton_debug_info0:
.long 0x7e
.value 0x4
.long .Lskeleton_debug_abbrev0
.byte 0x8
.uleb128 0x1
.long .Ldebug_ranges0+0
.quad 0
.long .Ldebug_line0
.byte 0x27
.byte 0x37
.byte 0xdc
.byte 0x2f
.byte 0x9
.byte 0xc6
.byte 0xf9
.byte 0x52
.long .Ldebug_ranges0
.string "/home/ccoutant/opensource/binutils-git/binutils/gold/testsuite"
.string "dwp_test_1.dwo"
.long .Ldebug_pubnames0
.long .Ldebug_pubtypes0
.long .Ldebug_addr0
.section .debug_abbrev,"",@progbits
.Lskeleton_debug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0
.uleb128 0x55
.uleb128 0x17
.uleb128 0x11
.uleb128 0x1
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2131
.uleb128 0x7
.uleb128 0x2132
.uleb128 0x17
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x41
.byte 0
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2130
.uleb128 0x8
.uleb128 0x2134
.uleb128 0x17
.uleb128 0x2135
.uleb128 0x17
.uleb128 0x2133
.uleb128 0x17
.byte 0
.byte 0
.byte 0
.section .debug_abbrev.dwo,"e",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x41
.byte 0x1
.uleb128 0x13
.uleb128 0xb
.uleb128 0x210f
.uleb128 0x7
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0xd
.byte 0
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x38
.uleb128 0xb
.uleb128 0x32
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x5
.byte 0
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x9
.uleb128 0x15
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xa
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xb
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x64
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xc
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0x8
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0x8
.uleb128 0x2131
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0xd
.uleb128 0x2
.byte 0x1
.uleb128 0x3
.uleb128 0x8
.uleb128 0x69
.uleb128 0x20
.uleb128 0x3c
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0xe
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x32
.uleb128 0xb
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0xf
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.byte 0
.byte 0
.uleb128 0x10
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x11
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x12
.uleb128 0x5
.byte 0
.uleb128 0x3
.uleb128 0x1f02
.uleb128 0x49
.uleb128 0x13
.uleb128 0x34
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x13
.uleb128 0x26
.byte 0
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x14
.uleb128 0x2e
.byte 0x1
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x64
.uleb128 0x13
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x15
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x16
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x17
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2116
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x18
.uleb128 0xb
.byte 0x1
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.byte 0
.byte 0
.uleb128 0x19
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x1a
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x6e
.uleb128 0x8
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1f01
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x1b
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x20
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x1c
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x1d
.uleb128 0x1
.byte 0x1
.uleb128 0x49
.uleb128 0x13
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x1e
.uleb128 0x21
.byte 0
.byte 0
.byte 0
.uleb128 0x1f
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.byte 0
.section .debug_gnu_pubnames,"",@progbits
.Ldebug_pubnames0:
.long 0x15b
.value 0x2
.long .Lskeleton_debug_info0
.long 0x5b3
.long 0x15b
.byte 0x30
.string "f13i"
.long 0x177
.byte 0x30
.string "C1::testcase1"
.long 0x1a0
.byte 0x30
.string "C1::testcase2"
.long 0x1c4
.byte 0x30
.string "C1::testcase3"
.long 0x1e8
.byte 0x30
.string "C1::testcase4"
.long 0x20c
.byte 0x30
.string "C2::testcase1"
.long 0x235
.byte 0x30
.string "C2::testcase2"
.long 0x259
.byte 0x30
.string "C2::testcase3"
.long 0x27d
.byte 0x30
.string "C2::testcase4"
.long 0x2a1
.byte 0x30
.string "C3::testcase1"
.long 0x2ca
.byte 0x30
.string "C3::testcase2"
.long 0x2ee
.byte 0x30
.string "f11a"
.long 0x30e
.byte 0x30
.string "C3::testcase3"
.long 0x332
.byte 0x30
.string "t12"
.long 0x350
.byte 0x30
.string "t13"
.long 0x36e
.byte 0x30
.string "t14"
.long 0x3c9
.byte 0x30
.string "t15"
.long 0x427
.byte 0x30
.string "t16"
.long 0x445
.byte 0x30
.string "t17"
.long 0x496
.byte 0x30
.string "t18"
.long 0x559
.byte 0x20
.string "p6"
.long 0x56c
.byte 0x20
.string "p7"
.long 0x579
.byte 0x20
.string "p8"
.long 0x58c
.byte 0x20
.string "p9"
.long 0x59e
.byte 0x20
.string "pfn"
.long 0
.section .debug_gnu_pubtypes,"",@progbits
.Ldebug_pubtypes0:
.long 0x50
.value 0x2
.long .Lskeleton_debug_info0
.long 0x5b3
.long 0xc6
.byte 0x90
.string "int"
.long 0xcd
.byte 0x90
.string "bool"
.long 0x8d
.byte 0x10
.string "C1"
.long 0xdf
.byte 0x10
.string "C2"
.long 0x122
.byte 0x10
.string "C3"
.long 0x3c1
.byte 0x90
.string "char"
.long 0x41c
.byte 0x90
.string "wchar_t"
.long 0
.section .debug_aranges,"",@progbits
.long 0x3c
.value 0x2
.long .Lskeleton_debug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad .LFB0
.quad .LFE0-.LFB0
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0
.quad .Letext0
.quad .LFB0
.quad .LFE0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_line.dwo,"e",@progbits
.Lskeleton_debug_line0:
.long .LELT0-.LSLT0
.LSLT0:
.value 0x4
.long .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf2
.byte 0xd
.byte 0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0
.byte 0
.byte 0
.byte 0x1
.byte 0
.byte 0
.byte 0x1
.byte 0
.string "dwp_test.h"
.uleb128 0
.uleb128 0
.uleb128 0
.string "dwp_test_1.cc"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.LELTP0:
.LELT0:
.section .debug_str_offsets.dwo,"e",@progbits
.long 0
.long 0xa
.long 0x14
.long 0x27
.long 0x3a
.long 0x44
.long 0x57
.long 0x5f
.long 0x72
.long 0x85
.long 0x98
.long 0xa2
.long 0xb5
.long 0xc8
.long 0xdb
.long 0xee
.long 0x101
.section .debug_str.dwo,"e",@progbits
.LASF0:
.string "testcase1"
.LASF1:
.string "testcase2"
.LASF2:
.string "_ZN2C39testcase1Ev"
.LASF3:
.string "_ZN2C39testcase2Ev"
.LASF4:
.string "testcase3"
.LASF5:
.string "_ZN2C39testcase3Ev"
.LASF6:
.string "member1"
.LASF7:
.string "_ZN2C29testcase1Ev"
.LASF8:
.string "_ZN2C29testcase2Ev"
.LASF9:
.string "_ZN2C29testcase3Ev"
.LASF10:
.string "testcase4"
.LASF11:
.string "_ZN2C29testcase4Ev"
.LASF12:
.string "_ZN2C19testcase1Ev"
.LASF13:
.string "_ZN2C19testcase2Ev"
.LASF14:
.string "_ZN2C19testcase3Ev"
.LASF15:
.string "_ZN2C19testcase4Ev"
.LASF16:
.string "this"
.section .debug_addr,"",@progbits
.Ldebug_addr0:
.quad .LFB0
.quad .LFB1
.quad .LFB2
.quad .LFB3
.quad .LFB4
.quad .LFB5
.quad .LFB6
.quad .LFB7
.quad .LFB8
.quad .LFB9
.quad .LFB10
.quad .LFB11
.quad .LFB12
.quad .LFB13
.quad .LFB14
.quad .LFB15
.quad .LBB2
.quad .LFB16
.quad .LBB3
.quad .LFB17
.quad .LFB18
.quad .LBB4
.quad .LBB5
.quad .LFB19
.quad .LBB6
.quad .LBB7
.quad .LBB8
.quad p6
.quad p7
.quad p8
.quad p9
.quad pfn
.ident "GCC: (Google_crosstoolv16-gcc-4.7.x-grtev3) 4.7.x-google 20120720 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 1,116
|
gold/testsuite/gnu_property_a.S
|
#define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEOF_PTRDIFF_T__ == 4
# define ALIGN 2
#endif
.text
.globl _start
_start:
ret
.section ".note.gnu.property", "a"
.p2align ALIGN
.long 1f - 0f /* name length */
.long 5f - 2f /* data length */
.long NT_GNU_PROPERTY_TYPE_0 /* note type */
0: .asciz "GNU" /* vendor name */
1:
.p2align ALIGN
2: .long GNU_PROPERTY_STACK_SIZE /* pr_type. */
.long 4f - 3f /* pr_datasz. */
3:
.dc.a 0x800 /* Stack size. */
4:
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_USED
.long 4
.byte 0x01,0x10,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_NEEDED
.long 4
.byte 0x01,0x10,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_FEATURE_1_AND
.long 4
.byte 0x01,0x00,0x00,0x00
.p2align ALIGN
5:
|
stsp/binutils-ia16
| 1,642
|
gold/testsuite/retain_1.s
|
.global discard0
.section .bss.discard0,"aw"
.type discard0, %object
discard0:
.zero 2
.global discard1
.section .bss.discard1,"aw"
.type discard1, %object
discard1:
.zero 2
.global discard2
.section .data.discard2,"aw"
.type discard2, %object
discard2:
.word 1
.section .bss.sdiscard0,"aw"
.type sdiscard0, %object
sdiscard0:
.zero 2
.section .bss.sdiscard1,"aw"
.type sdiscard1, %object
sdiscard1:
.zero 2
.section .data.sdiscard2,"aw"
.type sdiscard2, %object
sdiscard2:
.word 1
.section .text.fndiscard0,"ax"
.global fndiscard0
.type fndiscard0, %function
fndiscard0:
.word 0
.global retain0
.section .bss.retain0,"awR"
.type retain0, %object
retain0:
.zero 2
.global retain1
.section .bss.retain1,"awR"
.type retain1, %object
retain1:
.zero 2
.global retain2
.section .data.retain2,"awR"
.type retain2, %object
retain2:
.word 1
.section .bss.sretain0,"awR"
.type sretain0, %object
sretain0:
.zero 2
.section .bss.sretain1,"awR"
.type sretain1, %object
sretain1:
.zero 2
.section .data.sretain2,"aRw"
.type sretain2, %object
sretain2:
.word 1
.section .text.fnretain1,"Rax"
.global fnretain1
.type fnretain1, %function
fnretain1:
.word 0
.section .text.fndiscard2,"ax"
.global fndiscard2
.type fndiscard2, %function
fndiscard2:
.word 0
.section .bss.lsretain0,"awR"
.type lsretain0.2, %object
lsretain0.2:
.zero 2
.section .bss.lsretain1,"aRw"
.type lsretain1.1, %object
lsretain1.1:
.zero 2
.section .data.lsretain2,"aRw"
.type lsretain2.0, %object
lsretain2.0:
.word 1
.section .text._start,"ax"
.global _start
.type _start, %function
_start:
.word 0
|
stsp/binutils-ia16
| 1,244
|
gold/testsuite/gnu_property_c.S
|
#define NT_GNU_PROPERTY_TYPE_0 5
#define GNU_PROPERTY_STACK_SIZE 1
#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
#define GNU_PROPERTY_X86_ISA_1_USED 0xc0010002
#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0008002
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#if __SIZEOF_PTRDIFF_T__ == 8
# define ALIGN 3
#elif __SIZEOF_PTRDIFF_T__ == 4
# define ALIGN 2
#endif
.section ".note.gnu.property", "a"
.p2align ALIGN
.long 1f - 0f /* name length */
.long 5f - 2f /* data length */
.long NT_GNU_PROPERTY_TYPE_0 /* note type */
0: .asciz "GNU" /* vendor name */
1:
.p2align ALIGN
2: .long GNU_PROPERTY_STACK_SIZE /* pr_type. */
.long 4f - 3f /* pr_datasz. */
3:
.dc.a 0x111100 /* Stack size. */
4:
.p2align ALIGN
.long GNU_PROPERTY_NO_COPY_ON_PROTECTED /* pr_type. */
.long 0 /* pr_datasz. */
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_USED
.long 4
.byte 0x11,0x10,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_ISA_1_NEEDED
.long 4
.byte 0x11,0x10,0x00,0x00
.p2align ALIGN
.long GNU_PROPERTY_X86_FEATURE_1_AND
.long 4
.byte 0x01,0x00,0x00,0x00
.p2align ALIGN
5:
|
stsp/binutils-ia16
| 1,568
|
sim/bfin/linux-fixed-code.s
|
/* Linux fixed code userspace ABI
Copyright (C) 2005-2022 Free Software Foundation, Inc.
Contributed by Analog Devices, Inc.
This file is part of simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* For more info, see this page:
http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:fixed-code */
.text
.align 16
_sigreturn_stub:
P0 = 173;
EXCPT 0;
0: JUMP.S 0b;
.align 16
_atomic_xchg32:
R0 = [P0];
[P0] = R1;
rts;
.align 16
_atomic_cas32:
R0 = [P0];
CC = R0 == R1;
IF !CC JUMP 1f;
[P0] = R2;
1:
rts;
.align 16
_atomic_add32:
R1 = [P0];
R0 = R1 + R0;
[P0] = R0;
rts;
.align 16
_atomic_sub32:
R1 = [P0];
R0 = R1 - R0;
[P0] = R0;
rts;
.align 16
_atomic_ior32:
R1 = [P0];
R0 = R1 | R0;
[P0] = R0;
rts;
.align 16
_atomic_and32:
R1 = [P0];
R0 = R1 & R0;
[P0] = R0;
rts;
.align 16
_atomic_xor32:
R1 = [P0];
R0 = R1 ^ R0;
[P0] = R0;
rts;
.align 16
_safe_user_instruction:
NOP; NOP; NOP; NOP;
EXCPT 0x4;
|
stsp/binutils-ia16
| 1,029
|
sim/testsuite/sh/fsrra.s
|
# sh testcase for fsrra
# mach: sh
# as(sh): -defsym sim_cpu=0
# xerror: test hasn't been run in a long time
.include "testutils.inc"
start
fsrra_single:
set_grs_a5a5
set_fprs_a5a5
# 1/sqrt(0.0) = +infinity.
fldi0 fr0
fsrra fr0
assert_fpreg_x 0x7f800000, fr0
# 1/sqrt(1.0) = 1.0.
fldi1 fr0
fsrra fr0
assert_fpreg_i 1, fr0
# 1/sqrt(4.0) = 1/2.0
fldi1 fr0
# Double it.
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
fsrra fr0
fldi1 fr2
# Double it.
fadd fr2, fr2
fldi1 fr1
# Divide
fdiv fr2, fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
# Double-check (pun intended)
fadd fr0, fr0
assert_fpreg_i 1, fr0
fadd fr1, fr1
assert_fpreg_i 1, fr1
# And make sure the rest of the regs are un-affected.
assert_fpreg_i 2, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
test_grs_a5a5
pass
exit 0
|
stsp/binutils-ia16
| 3,058
|
sim/testsuite/sh/pshai.s
|
# sh testcase for psha <imm>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
psha_imm: ! shift arithmetic, immediate operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x1, a0
psha #0, a0
assert_sreg 0x1, a0
psha #-0, a0
assert_sreg 0x1, a0
psha #1, a0
assert_sreg 0x2, a0
psha #-1, a0
assert_sreg 0x1, a0
psha #2, a0
assert_sreg 0x4, a0
psha #-2, a0
assert_sreg 0x1, a0
psha #3, a0
assert_sreg 0x8, a0
psha #-3, a0
assert_sreg 0x1, a0
psha #4, a0
assert_sreg 0x10, a0
psha #-4, a0
assert_sreg 0x1, a0
psha #5, a0
assert_sreg 0x20, a0
psha #-5, a0
assert_sreg 0x1, a0
psha #6, a0
assert_sreg 0x40, a0
psha #-6, a0
assert_sreg 0x1, a0
psha #7, a0
assert_sreg 0x80, a0
psha #-7, a0
assert_sreg 0x1, a0
psha #8, a0
assert_sreg 0x100, a0
psha #-8, a0
assert_sreg 0x1, a0
psha #9, a0
assert_sreg 0x200, a0
psha #-9, a0
assert_sreg 0x1, a0
psha #10, a0
assert_sreg 0x400, a0
psha #-10, a0
assert_sreg 0x1, a0
psha #11, a0
assert_sreg 0x800, a0
psha #-11, a0
assert_sreg 0x1, a0
psha #12, a0
assert_sreg 0x1000, a0
psha #-12, a0
assert_sreg 0x1, a0
psha #13, a0
assert_sreg 0x2000, a0
psha #-13, a0
assert_sreg 0x1, a0
psha #14, a0
assert_sreg 0x4000, a0
psha #-14, a0
assert_sreg 0x1, a0
psha #15, a0
assert_sreg 0x8000, a0
psha #-15, a0
assert_sreg 0x1, a0
psha #16, a0
assert_sreg 0x10000, a0
psha #-16, a0
assert_sreg 0x1, a0
psha #17, a0
assert_sreg 0x20000, a0
psha #-17, a0
assert_sreg 0x1, a0
psha #18, a0
assert_sreg 0x40000, a0
psha #-18, a0
assert_sreg 0x1, a0
psha #19, a0
assert_sreg 0x80000, a0
psha #-19, a0
assert_sreg 0x1, a0
psha #20, a0
assert_sreg 0x100000, a0
psha #-20, a0
assert_sreg 0x1, a0
psha #21, a0
assert_sreg 0x200000, a0
psha #-21, a0
assert_sreg 0x1, a0
psha #22, a0
assert_sreg 0x400000, a0
psha #-22, a0
assert_sreg 0x1, a0
psha #23, a0
assert_sreg 0x800000, a0
psha #-23, a0
assert_sreg 0x1, a0
psha #24, a0
assert_sreg 0x1000000, a0
psha #-24, a0
assert_sreg 0x1, a0
psha #25, a0
assert_sreg 0x2000000, a0
psha #-25, a0
assert_sreg 0x1, a0
psha #26, a0
assert_sreg 0x4000000, a0
psha #-26, a0
assert_sreg 0x1, a0
psha #27, a0
assert_sreg 0x8000000, a0
psha #-27, a0
assert_sreg 0x1, a0
psha #28, a0
assert_sreg 0x10000000, a0
psha #-28, a0
assert_sreg 0x1, a0
psha #29, a0
assert_sreg 0x20000000, a0
psha #-29, a0
assert_sreg 0x1, a0
psha #30, a0
assert_sreg 0x40000000, a0
psha #-30, a0
assert_sreg 0x1, a0
psha #31, a0
assert_sreg 0x80000000, a0
psha #-31, a0
assert_sreg 0xffffffff, a0
psha #32, a0
assert_sreg 0x00000000, a0
# I don't grok what should happen here...
# psha #-32, a0
# assert_sreg 0x0, a0
test_grs_a5a5
assert_sreg2 0xa5a5a5a5, a1
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
stsp/binutils-ia16
| 1,167
|
sim/testsuite/sh/fadd.s
|
# sh testcase for fadd
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fadd_freg_freg_b0:
set_grs_a5a5
set_fprs_a5a5
bank0
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 2 fr1
fldi0 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 1 fr1
fldi1 fr0
fldi0 fr1
fadd fr0, fr1
assert_fpreg_i 1 fr1
test_grs_a5a5
assert_fpreg_i 1 fr0
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fadd_dreg_dreg_b0:
set_grs_a5a5
set_fprs_a5a5
double_prec
fldi1 fr0
fldi1 fr2
flds fr0, fpul
fcnvsd fpul, dr0
flds fr2, fpul
fcnvsd fpul, dr2
fadd dr0, dr2
fcnvds dr2, fpul
fsts fpul, fr0
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_dpreg_i 2, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 2,259
|
sim/testsuite/sh/bset.s
|
# sh testcase for bset
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0
_y: .long 0x55555555
start
bset_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bset.b #0, @(3, r1)
assertmem _x, 0x1
bset.b #1, @(3, r1)
assertmem _x, 0x3
bset.b #2, @(3, r1)
assertmem _x, 0x7
bset.b #3, @(3, r1)
assertmem _x, 0xf
bset.b #4, @(3, r1)
assertmem _x, 0x1f
bset.b #5, @(3, r1)
assertmem _x, 0x3f
bset.b #6, @(3, r1)
assertmem _x, 0x7f
bset.b #7, @(3, r1)
assertmem _x, 0xff
bset.b #0, @(2, r1)
assertmem _x, 0x1ff
bset.b #1, @(2, r1)
assertmem _x, 0x3ff
bset.b #2, @(2, r1)
assertmem _x, 0x7ff
bset.b #3, @(2, r1)
assertmem _x, 0xfff
bra .L2
nop
.align 2
x: .long _x
y: .long _y
.L2:
bset.b #4, @(2, r1)
assertmem _x, 0x1fff
bset.b #5, @(2, r1)
assertmem _x, 0x3fff
bset.b #6, @(2, r1)
assertmem _x, 0x7fff
bset.b #7, @(2, r1)
assertmem _x, 0xffff
bset.b #0, @(1, r1)
assertmem _x, 0x1ffff
bset.b #1, @(1, r1)
assertmem _x, 0x3ffff
bset.b #2, @(1, r1)
assertmem _x, 0x7ffff
bset.b #3, @(1, r1)
assertmem _x, 0xfffff
bset.b #4, @(1, r1)
assertmem _x, 0x1fffff
bset.b #5, @(1, r1)
assertmem _x, 0x3fffff
bset.b #6, @(1, r1)
assertmem _x, 0x7fffff
bset.b #7, @(1, r1)
assertmem _x, 0xffffff
bset.b #0, @(0, r1)
assertmem _x, 0x1ffffff
bset.b #1, @(0, r1)
assertmem _x, 0x3ffffff
bset.b #2, @(0, r1)
assertmem _x, 0x7ffffff
bset.b #3, @(0, r1)
assertmem _x, 0xfffffff
bset.b #4, @(0, r1)
assertmem _x, 0x1fffffff
bset.b #5, @(0, r1)
assertmem _x, 0x3fffffff
bset.b #6, @(0, r1)
assertmem _x, 0x7fffffff
bset.b #7, @(0, r1)
assertmem _x, 0xffffffff
assertreg _x, r1
bset_imm_reg:
set_greg 0, r1
bset #0, r1
assertreg 0x1, r1
bset #1, r1
assertreg 0x3, r1
bset #2, r1
assertreg 0x7, r1
bset #3, r1
assertreg 0xf, r1
bset #4, r1
assertreg 0x1f, r1
bset #5, r1
assertreg 0x3f, r1
bset #6, r1
assertreg 0x7f, r1
bset #7, r1
assertreg 0xff, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 1,807
|
sim/testsuite/sh/pdec.s
|
# sh testcase for pdec
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pdecx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pdec x0, y0
assert_sreg 0xa5a40000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pdecy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pdec y0, x0
assert_sreg 0xa5a40000, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dct_pdecx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_dcfalse
dct pdec x0, y0
assert_sreg 0xa5a5a5a5, y0
set_dctrue
dct pdec x0, y0
assert_sreg 0xa5a40000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dcf_pdecy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_dctrue
dcf pdec y0, x0
assert_sreg 0xa5a5a5a5, x0
set_dcfalse
dcf pdec y0, x0
assert_sreg 0xa5a40000, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
stsp/binutils-ia16
| 1,557
|
sim/testsuite/sh/fdiv.s
|
# sh testcase for fdiv
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fdiv_single:
# Single test
set_grs_a5a5
set_fprs_a5a5
single_prec
# 1.0 / 0.0 should be INF
# (and not crash the sim).
fldi0 fr0
fldi1 fr1
fdiv fr0, fr1
assert_fpreg_x 0x7f800000, fr1
# 0.0 / 1.0 == 0.0.
fldi0 fr0
fldi1 fr1
fdiv fr1, fr0
assert_fpreg_x 0, fr0
# 2.0 / 1.0 == 2.0.
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fdiv fr1, fr2
assert_fpreg_i 2, fr2
# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fdiv fr2, fr1
# fr1 should contain 0.5.
fadd fr1, fr1
assert_fpreg_i 1, fr1
test_grs_a5a5
assert_fpreg_i 2, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fdiv_double:
# Double test
set_grs_a5a5
set_fprs_a5a5
# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
fldi1 fr1
fldi1 fr2
# This add must be in single precision. The rest must be in double.
fadd fr2, fr2
double_prec
_s2d fr1, dr0
_s2d fr2, dr2
fdiv dr2, dr0
# dr0 should contain 0.5.
# double it, expect 1.0.
fadd dr0, dr0
assert_dpreg_i 1, dr0
assert_dpreg_i 2, dr2
test_grs_a5a5
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,589
|
sim/testsuite/sh/bld.s
|
# sh testcase for bld
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
bld_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bld.b #0, @(0, r1)
bf8k mfail
bld.b #1, @(0, r1)
bt8k mfail
bld.b #2, @(0, r1)
bf8k mfail
bld.b #3, @(0, r1)
bt8k mfail
bld.b #4, @(0, r1)
bt8k mfail
bld.b #5, @(0, r1)
bf8k mfail
bld.b #6, @(0, r1)
bt8k mfail
bld.b #7, @(0, r1)
bf8k mfail
bld.b #0, @(1, r1)
bf8k mfail
bld.b #1, @(1, r1)
bt8k mfail
bld.b #2, @(1, r1)
bf8k mfail
bld.b #3, @(1, r1)
bt8k mfail
bld.b #4, @(1, r1)
bt8k mfail
bld.b #5, @(1, r1)
bf8k mfail
bld.b #6, @(1, r1)
bt8k mfail
bld.b #7, @(1, r1)
bf8k mfail
bld.b #0, @(2, r1)
bf8k mfail
bld.b #1, @(2, r1)
bt8k mfail
bld.b #2, @(2, r1)
bf8k mfail
bld.b #3, @(2, r1)
bt8k mfail
bld.b #4, @(2, r1)
bt8k mfail
bld.b #5, @(2, r1)
bf8k mfail
bld.b #6, @(2, r1)
bt8k mfail
bld.b #7, @(2, r1)
bf8k mfail
bld.b #0, @(3, r1)
bf8k mfail
bld.b #1, @(3, r1)
bt8k mfail
bld.b #2, @(3, r1)
bf8k mfail
bld.b #3, @(3, r1)
bt8k mfail
bld.b #4, @(3, r1)
bt8k mfail
bld.b #5, @(3, r1)
bf8k mfail
bld.b #6, @(3, r1)
bt8k mfail
bld.b #7, @(3, r1)
bf8k mfail
assertreg _x, r1
bld_imm_reg:
set_greg 0xa5a5a5a5, r1
bld #0, r1
bf8k mfail
bld #1, r1
bt8k mfail
bld #2, r1
bf8k mfail
bld #3, r1
bt8k mfail
bld #4, r1
bt8k mfail
bld #5, r1
bf8k mfail
bld #6, r1
bt8k mfail
bld #7, r1
bf8k mfail
test_grs_a5a5
pass
exit 0
.align 2
x: .long _x
y: .long _y
|
stsp/binutils-ia16
| 1,730
|
sim/testsuite/sh/fsca.s
|
# sh testcase for fsca
# mach: sh
# as(sh): -defsym sim_cpu=0
# xerror: test hasn't been run in a long time
.include "testutils.inc"
start
fsca:
set_grs_a5a5
set_fprs_a5a5
# Start with angle zero
mov.l zero, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
mov.l plus_90, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 1, fr2
assert_fpreg_i 0, fr3
mov.l plus_180, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i -1, fr3
mov.l plus_270, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i -1, fr2
assert_fpreg_i 0, fr3
mov.l plus_360, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
mov.l minus_90, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i -1, fr2
assert_fpreg_i 0, fr3
mov.l minus_180, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i -1, fr3
mov.l minus_270, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 1, fr2
assert_fpreg_i 0, fr3
mov.l minus_360, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
assertreg0 0xffff0000
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
test_fpr_a5a5 fr0
test_fpr_a5a5 fr1
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
.align 2
zero: .long 0
one_bitty: .long 1
plus_90: .long 0x04000
plus_180: .long 0x08000
plus_270: .long 0x0c000
plus_360: .long 0x10000
minus_90: .long 0xffffc000
minus_180: .long 0xffff8000
minus_270: .long 0xffff4000
minus_360: .long 0xffff0000
minus_1_bitty: .long 0xffffffff
|
stsp/binutils-ia16
| 1,326
|
sim/testsuite/sh/fmac.s
|
# sh testcase for fmac
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fmac_:
set_grs_a5a5
set_fprs_a5a5
# 0.0 * x + y = y.
fldi0 fr0
fldi1 fr1
fldi1 fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
fcmp/eq fr0, fr2
bt .L0
fail
.L0:
# x * y + 0.0 = x * y.
fldi1 fr0
fldi1 fr1
fldi0 fr2
# double it.
fadd fr1, fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
fadd fr0, fr0
fcmp/eq fr0, fr2
bt .L1
fail
.L1:
# x * 0.0 + y = y.
fldi1 fr0
fldi0 fr1
fldi1 fr2
fadd fr2, fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
# double fr0.
fadd fr0, fr0
fcmp/eq fr0, fr2
bt .L2
fail
.L2:
# x * 0.0 + 0.0 = 0.0
fldi1 fr0
fadd fr0, fr0
fldi0 fr1
fldi0 fr2
fmac fr0, fr1, fr2
# check result.
fldi0 fr0
fcmp/eq fr0, fr2
bt .L3
fail
.L3:
# 0.0 * x + 0.0 = 0.0.
fldi0 fr0
fldi1 fr1
# double it.
fadd fr1, fr1
fldi0 fr2
fmac fr0, fr1, fr2
# check result.
fldi0 fr0
fcmp/eq fr0, fr2
bt .L4
fail
.L4:
test_grs_a5a5
assert_fpreg_i 0, fr0
assert_fpreg_i 2, fr1
assert_fpreg_i 0, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,593
|
sim/testsuite/sh/ldrc.s
|
# sh testcase for ldrc, strc
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
setrc_imm:
set_grs_a5a5
# Test setrc
#
ldrs lstart
ldre lend
setrc #0xff
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xff, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc re, r0 ! re unchanged
assertreg0 lend
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
setrc_reg:
set_grs_a5a5
# Test setrc
#
ldrs lstart
ldre lend
set_greg 0xfff, r0
setrc r0
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xfff, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc re, r0 ! re unchanged
assertreg0 lend
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
bra ldrc_imm
.global lstart
.align 2
lstart: nop
nop
nop
nop
.global lend
.align 2
lend: nop
nop
nop
nop
ldrc_imm:
set_grs_a5a5
# Test ldrc
setrc #0x0 ! zero rc
ldrc #0xa5
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xa5, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc re, r0
assertreg0 lend+1 ! bit 0 set in re
# fix up re for next test
dt r0 ! Ugh! No DEC insn!
ldc r0, re
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
ldrc_reg:
set_grs_a5a5
# Test ldrc
setrc #0x0 ! zero rc
set_greg 0xa5a, r0
ldrc r0
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xa5a, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc re, r0
assertreg0 lend+1 ! bit 0 set in re
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
|
stsp/binutils-ia16
| 2,717
|
sim/testsuite/sh/movua.s
|
# sh testcase for movua
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movua_1:
set_grs_a5a5
mov.l srcp, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x03020100
.else
assertreg0 0x00010203
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x04030201
.else
assertreg0 0x01020304
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x05040302
.else
assertreg0 0x02030405
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x06050403
.else
assertreg0 0x03040506
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x07060504
.else
assertreg0 0x04050607
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x08070605
.else
assertreg0 0x05060708
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x09080706
.else
assertreg0 0x06070809
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0a090807
.else
assertreg0 0x0708090a
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0b0a0908
.else
assertreg0 0x08090a0b
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0c0b0a09
.else
assertreg0 0x090a0b0c
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0d0c0b0a
.else
assertreg0 0x0a0b0c0d
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0e0d0c0b
.else
assertreg0 0x0b0c0d0e
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0f0e0d0c
.else
assertreg0 0x0c0d0e0f
.endif
assertreg src+12, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
bra movua_4:
nop
.align 0
src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
.align 2
srcp: .long src
movua_4:
set_grs_a5a5
mov.l srcp2, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x03020100
.else
assertreg0 0x00010203
.endif
assertreg src+4, r1
mov.l srcp2, r1
add #1, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x04030201
.else
assertreg0 0x01020304
.endif
assertreg src+5, r1
mov.l srcp2, r1
add #2, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x05040302
.else
assertreg0 0x02030405
.endif
assertreg src+6, r1
mov.l srcp2, r1
add #3, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x06050403
.else
assertreg0 0x03040506
.endif
assertreg src+7, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
srcp2: .long src
|
stsp/binutils-ia16
| 1,665
|
sim/testsuite/sh/fmul.s
|
# sh testcase for fmul
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
.endm
start
fmul_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 * 0.0 = 0.0.
init
fmul fr0, fr0
assert_fpreg_i 0, fr0
# 0.0 * 1.0 = 0.0.
init
fmul fr1, fr0
assert_fpreg_i 0, fr0
# 1.0 * 0.0 = 0.0.
init
fmul fr0, fr1
assert_fpreg_i 0, fr1
# 1.0 * 1.0 = 1.0.
init
fmul fr1, fr1
assert_fpreg_i 1, fr1
# 2.0 * 1.0 = 2.0.
init
fmul fr2, fr1
assert_fpreg_i 2, fr1
test_grs_a5a5
assert_fpreg_i 0, fr0
assert_fpreg_i 2, fr1
assert_fpreg_i 2, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
.macro dinit
fldi0 fr0
fldi1 fr2
fldi1 fr4
single_prec
fadd fr4, fr4
double_prec
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
.endm
fmul_double:
double_prec
# 0.0 * 0.0 = 0.0.
dinit
fmul dr0, dr0
assert_dpreg_i 0, dr0
# 0.0 * 1.0 = 0.0.
dinit
fmul dr2, dr0
assert_dpreg_i 0, dr0
# 1.0 * 0.0 = 0.0.
dinit
fmul dr0, dr2
assert_dpreg_i 0, dr2
# 1.0 * 1.0 = 1.0.
dinit
fmul dr2, dr2
assert_dpreg_i 1, dr2
# 2.0 * 1.0 = 2.0.
dinit
fmul dr4, dr2
assert_dpreg_i 2, dr2
test_grs_a5a5
assert_dpreg_i 0, dr0
assert_dpreg_i 2, dr2
assert_dpreg_i 2, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 2,619
|
sim/testsuite/sh/mulr.s
|
# sh testcase for mulr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
mulr_1: ! multiply by one
set_grs_a5a5
mov #1, r0
mulr r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_2: ! multiply by two
set_grs_a5a5
mov #2, r0
mov #12, r1
mulr r0, r1
assertreg0 2
assertreg 24, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_3: ! multiply five by five
set_grs_a5a5
mov #5, r0
mov #5, r1
mulr r0, r1
assertreg0 5
assertreg 25, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_4: ! multiply 127 by 127
set_grs_a5a5
mov #127, r0
mov #127, r1
mulr r0, r1
assertreg0 127
assertreg 0x3f01, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_5: ! multiply -1 by -1
set_grs_a5a5
mov #-1, r0
mov #-1, r1
mulr r0, r1
assertreg0 -1
assertreg 1, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_6: ! multiply 46340 by 46340
set_grs_a5a5
movi20 #46340, r0
movi20 #46340, r1
mulr r0, r1
assertreg0 46340
assertreg 0x7ffea810, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_7: ! multiply 7ffff by 7ffff (overflow)
set_grs_a5a5
movi20 #0x7ffff, r0
movi20 #0x7ffff, r1
mulr r0, r1
assertreg0 0x7ffff
assertreg 0xfff00001, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 2,500
|
sim/testsuite/sh/pushpop.s
|
# sh testcase for push/pop (mov,movml,movmu...) insns.
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movml_1:
set_greg 0, r0
set_greg 1, r1
set_greg 2, r2
set_greg 3, r3
set_greg 4, r4
set_greg 5, r5
set_greg 6, r6
set_greg 7, r7
set_greg 8, r8
set_greg 9, r9
set_greg 10, r10
set_greg 11, r11
set_greg 12, r12
set_greg 13, r13
set_greg 14, r14
set_sreg 15, pr
movml.l r15,@-r15
assertmem stackt-4, 15
assertmem stackt-8, 14
assertmem stackt-12, 13
assertmem stackt-16, 12
assertmem stackt-20, 11
assertmem stackt-24, 10
assertmem stackt-28, 9
assertmem stackt-32, 8
assertmem stackt-36, 7
assertmem stackt-40, 6
assertmem stackt-44, 5
assertmem stackt-48, 4
assertmem stackt-52, 3
assertmem stackt-56, 2
assertmem stackt-60, 1
assertmem stackt-64, 0
assertreg0 0
assertreg 1, r1
assertreg 2, r2
assertreg 3, r3
assertreg 4, r4
assertreg 5, r5
assertreg 6, r6
assertreg 7, r7
assertreg 8, r8
assertreg 9, r9
assertreg 10, r10
assertreg 11, r11
assertreg 12, r12
assertreg 13, r13
assertreg 14, r14
mov r15, r0
assertreg0 stackt-64
movml_2:
set_grs_a5a5
movml.l @r15+, r15
assert_sreg 15, pr
assertreg0 0
assertreg 1, r1
assertreg 2, r2
assertreg 3, r3
assertreg 4, r4
assertreg 5, r5
assertreg 6, r6
assertreg 7, r7
assertreg 8, r8
assertreg 9, r9
assertreg 10, r10
assertreg 11, r11
assertreg 12, r12
assertreg 13, r13
assertreg 14, r14
mov r15, r0
assertreg0 stackt
movmu_1:
set_grs_a5a5
add #1,r14
add #2,r13
add #3,r12
set_sreg 0xa5a5,pr
movmu.l r12,@-r15
assert_sreg 0xa5a5,pr
assertreg 0xa5a5a5a6, r14
assertreg 0xa5a5a5a7, r13
assertreg 0xa5a5a5a8, r12
test_gr_a5a5 r11
test_gr_a5a5 r10
test_gr_a5a5 r9
test_gr_a5a5 r8
test_gr_a5a5 r7
test_gr_a5a5 r6
test_gr_a5a5 r5
test_gr_a5a5 r4
test_gr_a5a5 r3
test_gr_a5a5 r2
test_gr_a5a5 r1
test_gr_a5a5 r0
mov r15, r0
assertreg stackt-16, r0
assertmem stackt-4, 0xa5a5
assertmem stackt-8, 0xa5a5a5a6
assertmem stackt-12, 0xa5a5a5a7
assertmem stackt-16, 0xa5a5a5a8
movmu_2:
set_grs_a5a5
movmu.l @r15+,r12
assert_sreg 0xa5a5, pr
assertreg 0xa5a5a5a6, r14
assertreg 0xa5a5a5a7, r13
assertreg 0xa5a5a5a8, r12
test_gr_a5a5 r11
test_gr_a5a5 r10
test_gr_a5a5 r9
test_gr_a5a5 r8
test_gr_a5a5 r7
test_gr_a5a5 r6
test_gr_a5a5 r5
test_gr_a5a5 r4
test_gr_a5a5 r3
test_gr_a5a5 r2
test_gr_a5a5 r1
test_gr_a5a5 r0
mov r15, r0
assertreg stackt, r0
pass
exit 0
|
stsp/binutils-ia16
| 2,256
|
sim/testsuite/sh/bst.s
|
# sh testcase for bst
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0
_y: .long 0x55555555
start
bst_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bst.b #0, @(3, r1)
assertmem _x, 0x1
bst.b #1, @(3, r1)
assertmem _x, 0x3
bst.b #2, @(3, r1)
assertmem _x, 0x7
bst.b #3, @(3, r1)
assertmem _x, 0xf
bst.b #4, @(3, r1)
assertmem _x, 0x1f
bst.b #5, @(3, r1)
assertmem _x, 0x3f
bst.b #6, @(3, r1)
assertmem _x, 0x7f
bst.b #7, @(3, r1)
assertmem _x, 0xff
bst.b #0, @(2, r1)
assertmem _x, 0x1ff
bst.b #1, @(2, r1)
assertmem _x, 0x3ff
bst.b #2, @(2, r1)
assertmem _x, 0x7ff
bst.b #3, @(2, r1)
assertmem _x, 0xfff
bra .L2
nop
.align 2
x: .long _x
y: .long _y
.L2:
bst.b #4, @(2, r1)
assertmem _x, 0x1fff
bst.b #5, @(2, r1)
assertmem _x, 0x3fff
bst.b #6, @(2, r1)
assertmem _x, 0x7fff
bst.b #7, @(2, r1)
assertmem _x, 0xffff
bst.b #0, @(1, r1)
assertmem _x, 0x1ffff
bst.b #1, @(1, r1)
assertmem _x, 0x3ffff
bst.b #2, @(1, r1)
assertmem _x, 0x7ffff
bst.b #3, @(1, r1)
assertmem _x, 0xfffff
bst.b #4, @(1, r1)
assertmem _x, 0x1fffff
bst.b #5, @(1, r1)
assertmem _x, 0x3fffff
bst.b #6, @(1, r1)
assertmem _x, 0x7fffff
bst.b #7, @(1, r1)
assertmem _x, 0xffffff
bst.b #0, @(0, r1)
assertmem _x, 0x1ffffff
bst.b #1, @(0, r1)
assertmem _x, 0x3ffffff
bst.b #2, @(0, r1)
assertmem _x, 0x7ffffff
bst.b #3, @(0, r1)
assertmem _x, 0xfffffff
bst.b #4, @(0, r1)
assertmem _x, 0x1fffffff
bst.b #5, @(0, r1)
assertmem _x, 0x3fffffff
bst.b #6, @(0, r1)
assertmem _x, 0x7fffffff
bst.b #7, @(0, r1)
assertmem _x, 0xffffffff
assertreg _x, r1
bst_imm_reg:
set_greg 0, r1
bst #0, r1
assertreg 0x1, r1
bst #1, r1
assertreg 0x3, r1
bst #2, r1
assertreg 0x7, r1
bst #3, r1
assertreg 0xf, r1
bst #4, r1
assertreg 0x1f, r1
bst #5, r1
assertreg 0x3f, r1
bst #6, r1
assertreg 0x7f, r1
bst #7, r1
assertreg 0xff, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 1,142
|
sim/testsuite/sh/movi.s
|
# sh testcase for all mov <#imm> instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
mov_i_reg: # Test <imm8>
set_grs_a5a5
mov #-0x55, r1
assertreg 0xffffffab, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
movi20_reg: # Test <imm20>
set_grs_a5a5
movi20 #-0x55555,r1
assertreg 0xfffaaaab, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
movi20s_reg: # Test <imm20> << 8
set_grs_a5a5
movi20s #-0x5555500,r1
assertreg 0xfaaaab00, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 4,383
|
sim/testsuite/sh/pshar.s
|
# sh testcase for psha <reg>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
psha_reg: ! shift arithmetic, register operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x1, x0
set_sreg 0x0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x10000, y0
psha x0, y0, x0
assert_sreg 0x2, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x20000, y0
psha x0, y0, x0
assert_sreg 0x4, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x30000, y0
psha x0, y0, x0
assert_sreg 0x8, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x40000, y0
psha x0, y0, x0
assert_sreg 0x10, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x50000, y0
psha x0, y0, x0
assert_sreg 0x20, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x60000, y0
psha x0, y0, x0
assert_sreg 0x40, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x70000, y0
psha x0, y0, x0
assert_sreg 0x80, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x80000, y0
psha x0, y0, x0
assert_sreg 0x100, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x90000, y0
psha x0, y0, x0
assert_sreg 0x200, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xa0000, y0
psha x0, y0, x0
assert_sreg 0x400, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xb0000, y0
psha x0, y0, x0
assert_sreg 0x800, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xc0000, y0
psha x0, y0, x0
assert_sreg 0x1000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xd0000, y0
psha x0, y0, x0
assert_sreg 0x2000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xe0000, y0
psha x0, y0, x0
assert_sreg 0x4000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xf0000, y0
psha x0, y0, x0
assert_sreg 0x8000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x100000, y0
psha x0, y0, x0
assert_sreg 0x10000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x110000, y0
psha x0, y0, x0
assert_sreg 0x20000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x120000, y0
psha x0, y0, x0
assert_sreg 0x40000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x130000, y0
psha x0, y0, x0
assert_sreg 0x80000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x140000, y0
psha x0, y0, x0
assert_sreg 0x100000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x150000, y0
psha x0, y0, x0
assert_sreg 0x200000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x160000, y0
psha x0, y0, x0
assert_sreg 0x400000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x170000, y0
psha x0, y0, x0
assert_sreg 0x800000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x180000, y0
psha x0, y0, x0
assert_sreg 0x1000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x190000, y0
psha x0, y0, x0
assert_sreg 0x2000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1a0000, y0
psha x0, y0, x0
assert_sreg 0x4000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1b0000, y0
psha x0, y0, x0
assert_sreg 0x8000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1c0000, y0
psha x0, y0, x0
assert_sreg 0x10000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1d0000, y0
psha x0, y0, x0
assert_sreg 0x20000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1e0000, y0
psha x0, y0, x0
assert_sreg 0x40000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1f0000, y0
psha x0, y0, x0
assert_sreg 0x80000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0xffffffff, x0
set_sreg 0x200000, y0
psha x0, y0, x0
assert_sreg 0x00000000, x0
# I don't grok what should happen here...
# pneg y0, y0
# psha x0, y0, x0
# assert_sreg 0x0, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
stsp/binutils-ia16
| 4,699
|
sim/testsuite/sh/fmov.s
|
# sh testcase for all fmov instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fldi1 fr3
.endm
start
fmov1: # Test fr -> fr.
set_grs_a5a5
set_fprs_a5a5
init
single_prec
sz_32
fmov fr0, fr1
# Ensure fr0 and fr1 are now equal.
fcmp/eq fr0, fr1
bt fmov2
fail
fmov2: # Test dr -> dr.
init
double_prec
sz_64
fmov dr0, dr2
# Ensure dr0 and dr2 are now equal.
fcmp/eq dr0, dr2
bt fmov3
fail
fmov3: # Test dr -> xd and xd -> dr.
init
sz_64
fmov dr0, xd0
# Ensure dr0 and xd0 are now equal.
fmov xd0, dr2
fcmp/eq dr0, dr2
bt fmov4
fail
fmov4: # Test xd -> xd.
init
sz_64
double_prec
fmov dr0, xd0
fmov xd0, xd2
fmov xd2, dr2
# Ensure dr0 and dr2 are now equal.
fcmp/eq dr0, dr2
bt .L0
fail
# FIXME: test fmov.s fr -> @gr, fmov dr -> @gr
# FIXME: test fmov.s @gr -> fr, fmov @gr -> dr
# FIXME: test fmov.s @gr+ -> fr, fmov @gr+ -> dr
# FIXME: test fmov.s fr -> @-gr, fmov dr -> @-gr
# FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr
# FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr)
.L0:
test_grs_a5a5
sz_32
single_prec
assert_fpreg_i 0, fr0
assert_fpreg_i 1, fr1
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fmov5: # Test fr -> @rn and @rn -> fr.
init
sz_32
single_prec
# FIXME! Use a reserved memory location!
mov #40, r0
shll8 r0
fmov fr0, @r0
fmov @r0, fr1
fcmp/eq fr0, fr1
bt fmov6
fail
fmov6: # Test dr -> @rn and @rn -> dr.
init
sz_64
double_prec
mov #40, r0
shll8 r0
fmov dr0, @r0
fmov @r0, dr2
fcmp/eq dr0, dr2
bt fmov7
fail
fmov7: # Test xd -> @rn and @rn -> xd.
init
sz_64
double_prec
mov #40, r0
shll8 r0
fmov dr0, xd0
fmov xd0, @r0
fmov @r0, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt fmov8
fail
fmov8: # Test fr -> @-rn.
init
sz_32
single_prec
mov #40, r0
shll8 r0
# Preserve.
mov r0, r1
fmov fr0, @-r0
fmov @r0, fr2
fcmp/eq fr0, fr2
bt f8b
fail
f8b: # check pre-dec.
add #4, r0
cmp/eq r0, r1
bt fmov9
fail
fmov9: # Test dr -> @-rn.
init
sz_64
double_prec
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, @-r0
fmov @r0, dr2
fcmp/eq dr0, dr2
bt f9b
fail
f9b: # check pre-dec.
add #8, r0
cmp/eq r0, r1
bt fmov10
fail
fmov10: # Test xd -> @-rn.
init
sz_64
double_prec
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, xd0
fmov xd0, @-r0
fmov @r0, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt f10b
fail
f10b: # check pre-dec.
add #8, r0
cmp/eq r0, r1
bt fmov11
fail
fmov11: # Test @rn+ -> fr.
init
sz_32
single_prec
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov fr0, @r0
fmov @r0+, fr2
fcmp/eq fr0, fr2
bt f11b
fail
f11b: # check post-inc.
add #4, r1
cmp/eq r0, r1
bt fmov12
fail
fmov12: # Test @rn+ -> dr.
init
sz_64
double_prec
mov #40, r0
shll8 r0
# preserve r0.
mov r0, r1
fmov dr0, @r0
fmov @r0+, dr2
fcmp/eq dr0, dr2
bt f12b
fail
f12b: # check post-inc.
add #8, r1
cmp/eq r0, r1
bt fmov13
fail
fmov13: # Test @rn -> xd.
init
sz_64
double_prec
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, xd0
fmov xd0, @r0
fmov @r0+, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt f13b
fail
f13b:
add #8, r1
cmp/eq r0, r1
bt fmov14
fail
fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr.
init
sz_32
single_prec
mov #40, r0
shll8 r0
mov #0, r1
fmov fr0, @(r0, r1)
fmov @(r0, r1), fr1
fcmp/eq fr0, fr1
bt fmov15
fail
fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr.
init
sz_64
double_prec
mov #40, r0
shll8 r0
mov #0, r1
fmov dr0, @(r0, r1)
fmov @(r0, r1), dr2
fcmp/eq dr0, dr2
bt fmov16
fail
fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd.
init
sz_64
double_prec
mov #40, r0
shll8 r0
mov #0, r1
fmov dr0, xd0
fmov xd0, @(r0, r1)
fmov @(r0, r1), xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt .L1
fail
.L1:
assertreg0 0x2800
assertreg 0, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
sz_32
single_prec
assert_fpreg_i 0, fr0
assert_fpreg_i 1, fr1
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,911
|
sim/testsuite/sh/mov.s
|
# sh testcase for all mov.[bwl] instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.align 2
_lsrc: .long 0x55555555
_wsrc: .long 0x55550000
_bsrc: .long 0x55000000
.align 2
_ldst: .long 0
_wdst: .long 0
_bdst: .long 0
start
movb_disp12_reg: # Test 8-bit @(disp12,gr) -> gr
set_grs_a5a5
mov.l bsrc, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.b @(444,r1), r2
assertreg _bsrc-444, r1
assertreg 0x55, r2
movb_reg_disp12: # Test 8-bit gr -> @(disp12,gr)
set_grs_a5a5
mov.l bdst, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.b r2, @(444,r1)
assertreg _bdst-444, r1
assertmem _bdst, 0xa5000000
movw_disp12_reg: # Test 16-bit @(disp12,gr) -> gr
set_grs_a5a5
mov.l wsrc, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.w @(444,r1), r2
assertreg _wsrc-444, r1
assertreg 0x5555, r2
movw_reg_disp12: # Test 16-bit gr -> @(disp12,gr)
set_grs_a5a5
mov.l wdst, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.w r2, @(444,r1)
assertreg _wdst-444, r1
assertmem _wdst, 0xa5a50000
movl_disp12_reg: # Test 32-bit @(disp12,gr) -> gr
set_grs_a5a5
mov.l lsrc, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.l @(444,r1), r2
assertreg _lsrc-444, r1
assertreg 0x55555555, r2
movl_reg_disp12: # Test 32-bit gr -> @(disp12,gr)
set_grs_a5a5
mov.l ldst, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.l r2, @(444,r1)
assertreg _ldst-444, r1
assertmem _ldst, 0xa5a5a5a5
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
lsrc: .long _lsrc
wsrc: .long _wsrc
bsrc: .long _bsrc
ldst: .long _ldst
wdst: .long _wdst
bdst: .long _bdst
|
stsp/binutils-ia16
| 2,169
|
sim/testsuite/sh/float.s
|
# sh testcase for float
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
float_pos:
set_grs_a5a5
set_fprs_a5a5
single_prec
mov #3, r0
lds r0, fpul
float fpul, fr2
# Check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fcmp/eq fr1, fr2
bt float_neg
fail
float_neg:
mov #3, r0
neg r0, r0
lds r0, fpul
float fpul, fr2
# Check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fneg fr1
fcmp/eq fr1, fr2
bt .L0
fail
.L0:
assertreg0 -3
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
assert_fpreg_i 1, fr0
assert_fpreg_i -3, fr1
assert_fpreg_i -3, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
double_pos:
set_grs_a5a5
set_fprs_a5a5
double_prec
mov #3, r0
lds r0, fpul
float fpul, dr4
# check the result.
fldi1 fr0
fldi1 fr1
single_prec
fadd fr0, fr1
fadd fr0, fr1
double_prec
_s2d fr1, dr2
fcmp/eq dr2, dr4
bt double_neg
fail
double_neg:
double_prec
mov #3, r0
neg r0, r0
lds r0, fpul
float fpul, dr4
# check the result.
fldi1 fr0
fldi1 fr1
single_prec
fadd fr0, fr1
fadd fr0, fr1
fneg fr1
double_prec
_s2d fr1, dr2
fcmp/eq dr2, dr4
bt .L2
fail
.L2:
assertreg0 -3
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
single_prec
assert_fpreg_i 1, fr0
assert_fpreg_i -3, fr1
double_prec
assert_dpreg_i -3, dr2
assert_dpreg_i -3, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,896
|
sim/testsuite/sh/pshli.s
|
# sh testcase for pshl <imm>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pshl_imm: ! shift logical, immediate operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x10000, a0
pshl #0, a0
assert_sreg 0x10000, a0
pshl #-0, a0
assert_sreg 0x10000, a0
pshl #1, a0
assert_sreg 0x20000, a0
pshl #-1, a0
assert_sreg 0x10000, a0
pshl #2, a0
assert_sreg 0x40000, a0
pshl #-2, a0
assert_sreg 0x10000, a0
pshl #3, a0
assert_sreg 0x80000, a0
pshl #-3, a0
assert_sreg 0x10000, a0
pshl #4, a0
assert_sreg 0x100000, a0
pshl #-4, a0
assert_sreg 0x10000, a0
pshl #5, a0
assert_sreg 0x200000, a0
pshl #-5, a0
assert_sreg 0x10000, a0
pshl #6, a0
assert_sreg 0x400000, a0
pshl #-6, a0
assert_sreg 0x10000, a0
pshl #7, a0
assert_sreg 0x800000, a0
pshl #-7, a0
assert_sreg 0x10000, a0
pshl #8, a0
assert_sreg 0x1000000, a0
pshl #-8, a0
assert_sreg 0x10000, a0
pshl #9, a0
assert_sreg 0x2000000, a0
pshl #-9, a0
assert_sreg 0x10000, a0
pshl #10, a0
assert_sreg 0x4000000, a0
pshl #-10, a0
assert_sreg 0x10000, a0
pshl #11, a0
assert_sreg 0x8000000, a0
pshl #-11, a0
assert_sreg 0x10000, a0
pshl #12, a0
assert_sreg 0x10000000, a0
pshl #-12, a0
assert_sreg 0x10000, a0
pshl #13, a0
assert_sreg 0x20000000, a0
pshl #-13, a0
assert_sreg 0x10000, a0
pshl #14, a0
assert_sreg 0x40000000, a0
pshl #-14, a0
assert_sreg 0x10000, a0
pshl #15, a0
assert_sreg 0x80000000, a0
pshl #-15, a0
assert_sreg 0x10000, a0
pshl #16, a0
assert_sreg 0x00000000, a0
pshl #-16, a0
assert_sreg 0x0, a0
test_grs_a5a5
assert_sreg2 0xa5a5a5a5, a1
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
stsp/binutils-ia16
| 1,647
|
sim/testsuite/sh/bxor.s
|
# sh testcase for bxor
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bxor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bxor.b #0, @(3, r1)
bt8k mfail
bxor.b #1, @(3, r1)
bt8k mfail
bxor.b #2, @(3, r1)
bf8k mfail
bxor.b #3, @(3, r1)
bf8k mfail
bxor.b #4, @(3, r1)
bf8k mfail
bxor.b #5, @(3, r1)
bt8k mfail
bxor.b #6, @(3, r1)
bt8k mfail
bxor.b #7, @(3, r1)
bf8k mfail
bxor.b #0, @(2, r1)
bt8k mfail
bxor.b #1, @(2, r1)
bt8k mfail
bxor.b #2, @(2, r1)
bf8k mfail
bxor.b #3, @(2, r1)
bf8k mfail
bra .L2
nop
.align 2
x: .long _x
.L2:
bxor.b #4, @(2, r1)
bf8k mfail
bxor.b #5, @(2, r1)
bt8k mfail
bxor.b #6, @(2, r1)
bt8k mfail
bxor.b #7, @(2, r1)
bf8k mfail
bxor.b #0, @(1, r1)
bt8k mfail
bxor.b #1, @(1, r1)
bt8k mfail
bxor.b #2, @(1, r1)
bf8k mfail
bxor.b #3, @(1, r1)
bf8k mfail
bxor.b #4, @(1, r1)
bf8k mfail
bxor.b #5, @(1, r1)
bt8k mfail
bxor.b #6, @(1, r1)
bt8k mfail
bxor.b #7, @(1, r1)
bf8k mfail
bxor.b #0, @(0, r1)
bt8k mfail
bxor.b #1, @(0, r1)
bt8k mfail
bxor.b #2, @(0, r1)
bf8k mfail
bxor.b #3, @(0, r1)
bf8k mfail
bxor.b #4, @(0, r1)
bf8k mfail
bxor.b #5, @(0, r1)
bt8k mfail
bxor.b #6, @(0, r1)
bt8k mfail
bxor.b #7, @(0, r1)
bf8k mfail
assertreg _x, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 1,643
|
sim/testsuite/sh/fcmpgt.s
|
# sh testcase for fcmpgt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpgt_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf .L0
fail
.L0:
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bt .L1
fail
.L1:
# 1.0 > 0.0.
fldi1 fr0
fldi0 fr1
fcmp/gt fr0, fr1
bf .L2
fail
.L2:
# 2.0 > 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 1, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fcmpgt_double:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
double_prec
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L10
fail
.L10:
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bt .L11
fail
.L11:
# 1.0 > 0.0.
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L12
fail
.L12:
# 2.0 > 1.0.
fldi1 fr0
single_prec
fadd fr0, fr0
double_prec
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 1, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,325
|
sim/testsuite/sh/and.s
|
# sh testcase for and
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
and_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
and r1, r2
test_gr0_a5a5
assertreg 0xa5a5a5a5 r1
assertreg 0xa0a0a0a0 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
bra and_imm_reg
nop
.align 2
i: .long 0xa5a5a5a5
j: .long 0xaaaaaaaa
and_imm_reg:
set_grs_a5a5
and #0xff, r0
assertreg 0xa5, r0
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
and_b_imm_ind:
set_grs_a5a5
mov.l x, r0
and.b #0x55, @(r0, GBR)
mov.l @r0, r0
assertreg 0xa5a5a505, r0
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
.align 2
x: .long _x
y: .long _y
|
stsp/binutils-ia16
| 1,619
|
sim/testsuite/sh/fcmpeq.s
|
# sh testcase for fcmpeq
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpeq_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 == 1.0.
fldi1 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# 0.0 != 1.0.
fldi0 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf .L1
fail
.L1:
# 1.0 != 0.0.
fldi1 fr0
fldi0 fr1
fcmp/eq fr0, fr1
bf .L2
fail
.L2:
# 2.0 != 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 1, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fcmpeq_double:
# 1.0 == 1.0
set_grs_a5a5
set_fprs_a5a5
double_prec
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# 0.0 != 1.0
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L11
fail
.L11:
# 1.0 != 0.0
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L12
fail
.L12:
# 2.0 != 1.0
fldi1 fr0
single_prec
fadd fr0, fr0
double_prec
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 1, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,585
|
sim/testsuite/sh/fneg.s
|
# sh testcase for fneg
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fneg_single:
set_grs_a5a5
set_fprs_a5a5
# neg(0.0) = 0.0.
fldi0 fr0
fldi0 fr1
fneg fr0
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# neg(1.0) = fsub(0,1)
fldi1 fr0
fneg fr0
fldi0 fr1
fldi1 fr2
fsub fr2, fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# neg(neg(1.0)) = 1.0.
fldi1 fr0
fldi1 fr1
fneg fr0
fneg fr0
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
test_grs_a5a5
assert_fpreg_i 1, fr0
assert_fpreg_i 1, fr1
assert_fpreg_i 1, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fneg_double:
set_grs_a5a5
set_fprs_a5a5
double_prec
# neg(0.0) = 0.0.
fldi0 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fneg dr0
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# neg(1.0) = fsub(0,1)
fldi1 fr0
_s2d fr0, dr0
fneg dr0
fldi0 fr2
fldi1 fr3
single_prec
fsub fr3, fr2
double_prec
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L11
fail
.L11:
# neg(neg(1.0)) = 1.0.
fldi1 fr0
_s2d fr0, dr0
fldi1 fr2
_s2d fr2, dr2
fneg dr2
fneg dr2
fcmp/eq dr0, dr2
bt .L12
fail
.L12:
test_grs_a5a5
assert_dpreg_i 1, dr0
assert_dpreg_i 1, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,484
|
sim/testsuite/sh/bldnot.s
|
# sh testcase for bldnot
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
bldnot_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bldnot.b #0, @(0, r1)
bt8k mfail
bldnot.b #1, @(0, r1)
bf8k mfail
bldnot.b #2, @(0, r1)
bt8k mfail
bldnot.b #3, @(0, r1)
bf8k mfail
bldnot.b #4, @(0, r1)
bf8k mfail
bldnot.b #5, @(0, r1)
bt8k mfail
bldnot.b #6, @(0, r1)
bf8k mfail
bldnot.b #7, @(0, r1)
bt8k mfail
bldnot.b #0, @(1, r1)
bt8k mfail
bldnot.b #1, @(1, r1)
bf8k mfail
bldnot.b #2, @(1, r1)
bt8k mfail
bldnot.b #3, @(1, r1)
bf8k mfail
bldnot.b #4, @(1, r1)
bf8k mfail
bldnot.b #5, @(1, r1)
bt8k mfail
bldnot.b #6, @(1, r1)
bf8k mfail
bldnot.b #7, @(1, r1)
bt8k mfail
bldnot.b #0, @(2, r1)
bt8k mfail
bldnot.b #1, @(2, r1)
bf8k mfail
bldnot.b #2, @(2, r1)
bt8k mfail
bldnot.b #3, @(2, r1)
bf8k mfail
bldnot.b #4, @(2, r1)
bf8k mfail
bldnot.b #5, @(2, r1)
bt8k mfail
bldnot.b #6, @(2, r1)
bf8k mfail
bldnot.b #7, @(2, r1)
bt8k mfail
bldnot.b #0, @(3, r1)
bt8k mfail
bldnot.b #1, @(3, r1)
bf8k mfail
bldnot.b #2, @(3, r1)
bt8k mfail
bldnot.b #3, @(3, r1)
bf8k mfail
bldnot.b #4, @(3, r1)
bf8k mfail
bldnot.b #5, @(3, r1)
bt8k mfail
bldnot.b #6, @(3, r1)
bf8k mfail
bldnot.b #7, @(3, r1)
bt8k mfail
assertreg _x, r1
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
.align 2
x: .long _x
y: .long _y
|
stsp/binutils-ia16
| 1,715
|
sim/testsuite/sh/fsqrt.s
|
# sh testcase for fsqrt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsqrt_single:
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
fldi0 fr0
fsqrt fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# sqrt(1.0) = 1.0.
fldi1 fr0
fsqrt fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# sqrt(4.0) = 2.0
fldi1 fr0
# Double it.
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
fsqrt fr0
fldi1 fr1
# Double it.
fadd fr1, fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 2, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fsqrt_double:
double_prec
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
fldi0 fr0
_s2d fr0, dr0
fsqrt dr0
fldi0 fr2
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# sqrt(1.0) = 1.0.
fldi1 fr0
_s2d fr0, dr0
fsqrt dr0
fldi1 fr2
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L11
fail
.L11:
# sqrt(4.0) = 2.0.
fldi1 fr0
# Double it.
single_prec
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
double_prec
_s2d fr0, dr0
fsqrt dr0
fldi1 fr2
# Double it.
single_prec
fadd fr2, fr2
double_prec
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L12
fail
.L12:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 2, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 2,985
|
sim/testsuite/sh/pswap.s
|
# sh testcase for pswap
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pswapx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, x0
pswap x0, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pswapy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, y0
pswap y0, x0
assert_sreg 0x7777a5a5, x0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, y0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pswapa:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, a0
pcopy a0, a1
pswap a1, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, a0
assert_sreg2 0xa5a57777, a1
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pswapm:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, a0
pcopy a0, m1
pswap m1, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, a0
assert_sreg2 0xa5a57777, m1
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
dct_pswapx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, x0
set_dcfalse
dct pswap x0, y0
assert_sreg 0xa5a5a5a5, y0
set_dctrue
dct pswap x0, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dcf_pswapy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, x0
set_dctrue
dcf pswap x0, y0
assert_sreg 0xa5a5a5a5, y0
set_dcfalse
dcf pswap x0, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
stsp/binutils-ia16
| 1,609
|
sim/testsuite/sh/fabs.s
|
# sh testcase for fabs
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fabs_freg_b0:
single_prec
bank0
set_grs_a5a5
set_fprs_a5a5
# fabs(0.0) = 0.0.
fldi0 fr0
fabs fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# fabs(1.0) = 1.0.
fldi1 fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L3
fail
.L3:
test_grs_a5a5
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fabs_dreg_b0:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
double_prec
# fabs(0.0) = 0.0.
fldi0 fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 0 dr0
# fabs(1.0) = 1.0.
fldi1 fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
fldi1 fr2
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L4
fail
.L4:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
fldi1 fr2
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L5
fail
.L5:
test_grs_a5a5
assert_dpreg_i 1 dr0
assert_dpreg_i 1 dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 2,323
|
sim/testsuite/sh/ftrc.s
|
# sh testcase for ftrc
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
ftrc_single:
set_grs_a5a5
set_fprs_a5a5
# ftrc(0.0) = 0.
fldi0 fr0
ftrc fr0, fpul
# check results.
mov #0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L0
fail
.L0:
# ftrc(1.5) = 1.
fldi1 fr0
fldi1 fr1
fldi1 fr2
# double it.
fadd fr2, fr2
# form the fraction.
fdiv fr2, fr1
fadd fr1, fr0
# now we've got 1.5 in fr0.
ftrc fr0, fpul
# check results.
mov #1, r0
sts fpul, r1
cmp/eq r0, r1
bt .L1
fail
.L1:
# ftrc(-1.5) = -1.
fldi1 fr0
fneg fr0
fldi1 fr1
fldi1 fr2
# double it.
fadd fr2, fr2
# form the fraction.
fdiv fr2, fr1
fneg fr1
# -1 + -0.5 = -1.5.
fadd fr1, fr0
# now we've got 1.5 in fr0.
ftrc fr0, fpul
# check results.
mov #1, r0
neg r0, r0
sts fpul, r1
cmp/eq r0, r1
bt ftrc_double
fail
ftrc_double:
double_prec
# ftrc(0.0) = 0.
fldi0 fr0
_s2d fr0, dr0
ftrc dr0, fpul
# check results.
mov #0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L10
fail
.L10:
# ftrc(1.5) = 1.
fldi1 fr0
fldi1 fr2
fldi1 fr4
# double it.
single_prec
fadd fr4, fr4
# form 0.5.
fdiv fr4, fr2
fadd fr2, fr0
double_prec
# now we've got 1.5 in fr0, so do some single->double
# conversions and perform the ftrc.
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
ftrc dr0, fpul
# check results.
mov #1, r0
sts fpul, r1
cmp/eq r0, r1
bt .L11
fail
.L11:
# ftrc(-1.5) = -1.
fldi1 fr0
fneg fr0
fldi1 fr2
fldi1 fr4
single_prec
# double it.
fadd fr4, fr4
# form the fraction.
fdiv fr4, fr2
fneg fr2
# -1 + -0.5 = -1.5.
fadd fr2, fr0
double_prec
# now we've got 1.5 in fr0, so do some single->double
# conversions and perform the ftrc.
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
ftrc dr0, fpul
# check results.
mov #1, r0
neg r0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L12
fail
.L12:
assertreg0 -1
assertreg -1, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
assert_dpreg_i 2, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,911
|
sim/testsuite/sh/fsub.s
|
# sh testcase for fsub
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsub_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 - 0.0 = 0.0.
fldi0 fr0
fldi0 fr1
fsub fr0, fr1
fldi0 fr2
fcmp/eq fr1, fr2
bt .L0
fail
.L0:
# 1.0 - 0.0 = 1.0.
fldi0 fr0
fldi1 fr1
fsub fr0, fr1
fldi1 fr2
fcmp/eq fr1, fr2
bt .L1
fail
.L1:
# 1.0 - 1.0 = 0.0.
fldi1 fr0
fldi1 fr1
fsub fr0, fr1
fldi0 fr2
fcmp/eq fr1, fr2
bt .L2
fail
.L2:
# 0.0 - 1.0 = -1.0.
fldi1 fr0
fldi0 fr1
fsub fr0, fr1
fldi1 fr2
fneg fr2
fcmp/eq fr1, fr2
bt .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 1, fr0
assert_fpreg_i -1, fr1
assert_fpreg_i -1, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fsub_double:
set_grs_a5a5
set_fprs_a5a5
double_prec
# 0.0 - 0.0 = 0.0.
fldi0 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi0 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L10
fail
.L10:
# 1.0 - 0.0 = 1.0.
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi1 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L11
fail
.L11:
# 1.0 - 1.0 = 0.0.
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi0 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L12
fail
.L12:
# 0.0 - 1.0 = -1.0.
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi1 fr4
single_prec
fneg fr4
double_prec
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 1, dr0
assert_dpreg_i -1, dr2
assert_dpreg_i -1, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
stsp/binutils-ia16
| 1,433
|
sim/testsuite/sh/prnd.s
|
# sh testcase for prnd
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
# FIXME: opcode table ambiguity in ignored bits 4-7.
.include "testutils.inc"
start
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
# prnd(0xa5a5a5a5) = 0xa5a60000
prnd x0, x0
prnd y0, y0
assert_sreg 0xa5a60000, x0
assert_sreg 0xa5a60000, y0
# prnd(1) = 1
mov #1, r0
shll16 r0
lds r0, x0
pcopy x0, y0
prnd x0, x0
prnd y0, y0
assert_sreg 0x10000, x0
assert_sreg 0x10000, y0
# prnd(1.4999999) = 1
mov #1, r0
shll8 r0
or #0x7f, r0
shll8 r0
or #0xff, r0
lds r0, x0
pcopy x0, y0
prnd x0, x0
prnd y0, y0
assert_sreg 0x10000, x0
assert_sreg 0x10000, y0
# prnd(1.5) = 2
mov #1, r0
shll8 r0
or #0x80, r0
shll8 r0
lds r0, x0
pcopy x0, y0
prnd x0, x0
prnd y0, y0
assert_sreg 0x20000, x0
assert_sreg 0x20000, y0
# dct prnd
set_dcfalse
dct prnd x0, x1
dct prnd y0, y1
assert_sreg2 0xa5a5a5a5, x1
assert_sreg2 0xa5a5a5a5, y1
set_dctrue
dct prnd x0, x1
dct prnd y0, y1
assert_sreg2 0x20000, x1
assert_sreg2 0x20000, y1
# dcf prnd
set_dctrue
dcf prnd x0, m0
dcf prnd y0, m1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
set_dcfalse
dcf prnd x0, m0
dcf prnd y0, m1
assert_sreg2 0x20000, m0
assert_sreg2 0x20000, m1
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
pass
exit 0
|
stsp/binutils-ia16
| 1,247
|
sim/testsuite/sh/add.s
|
# sh testcase for add
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 1
_y: .long 1
start
add_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
add r1, r2
test_gr0_a5a5
assertreg 2 r1
assertreg 4 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
add_reg_reg_indirect:
set_grs_a5a5
mov.l x, r1
mov.l y, r2
mov.l @r1, r1
mov.l @r2, r2
add r1, r2
test_gr0_a5a5
assertreg 1 r1
assertreg 2 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
add_imm_reg:
set_grs_a5a5
add #0x16, r1
test_gr0_a5a5
assertreg 0xa5a5a5bb r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
.align 2
x: .long _x
y: .long _y
i: .long 2
j: .long 2
|
stsp/binutils-ia16
| 2,387
|
sim/testsuite/sh/bclr.s
|
# sh testcase for bclr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xffffffff
_y: .long 0x55555555
start
bclr_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bclr.b #0, @(3, r1)
assertmem _x, 0xfffffffe
bclr.b #1, @(3, r1)
assertmem _x, 0xfffffffc
bclr.b #2, @(3, r1)
assertmem _x, 0xfffffff8
bclr.b #3, @(3, r1)
assertmem _x, 0xfffffff0
bclr.b #4, @(3, r1)
assertmem _x, 0xffffffe0
bclr.b #5, @(3, r1)
assertmem _x, 0xffffffc0
bclr.b #6, @(3, r1)
assertmem _x, 0xffffff80
bclr.b #7, @(3, r1)
assertmem _x, 0xffffff00
bclr.b #0, @(2, r1)
assertmem _x, 0xfffffe00
bclr.b #1, @(2, r1)
assertmem _x, 0xfffffc00
bclr.b #2, @(2, r1)
assertmem _x, 0xfffff800
bclr.b #3, @(2, r1)
assertmem _x, 0xfffff000
bra .L2
nop
.align 2
x: .long _x
y: .long _y
.L2:
bclr.b #4, @(2, r1)
assertmem _x, 0xffffe000
bclr.b #5, @(2, r1)
assertmem _x, 0xffffc000
bclr.b #6, @(2, r1)
assertmem _x, 0xffff8000
bclr.b #7, @(2, r1)
assertmem _x, 0xffff0000
bclr.b #0, @(1, r1)
assertmem _x, 0xfffe0000
bclr.b #1, @(1, r1)
assertmem _x, 0xfffc0000
bclr.b #2, @(1, r1)
assertmem _x, 0xfff80000
bclr.b #3, @(1, r1)
assertmem _x, 0xfff00000
bclr.b #4, @(1, r1)
assertmem _x, 0xffe00000
bclr.b #5, @(1, r1)
assertmem _x, 0xffc00000
bclr.b #6, @(1, r1)
assertmem _x, 0xff800000
bclr.b #7, @(1, r1)
assertmem _x, 0xff000000
bclr.b #0, @(0, r1)
assertmem _x, 0xfe000000
bclr.b #1, @(0, r1)
assertmem _x, 0xfc000000
bclr.b #2, @(0, r1)
assertmem _x, 0xf8000000
bclr.b #3, @(0, r1)
assertmem _x, 0xf0000000
bclr.b #4, @(0, r1)
assertmem _x, 0xe0000000
bclr.b #5, @(0, r1)
assertmem _x, 0xc0000000
bclr.b #6, @(0, r1)
assertmem _x, 0x80000000
bclr.b #7, @(0, r1)
assertmem _x, 0x00000000
assertreg _x, r1
bclr_imm_reg:
set_greg 0xff, r1
bclr #0, r1
assertreg 0xfe, r1
bclr #1, r1
assertreg 0xfc, r1
bclr #2, r1
assertreg 0xf8, r1
bclr #3, r1
assertreg 0xf0, r1
bclr #4, r1
assertreg 0xe0, r1
bclr #5, r1
assertreg 0xc0, r1
bclr #6, r1
assertreg 0x80, r1
bclr #7, r1
assertreg 0x00, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 1,638
|
sim/testsuite/sh/bandor.s
|
# sh testcase for band, bor
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bandor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
band.b #0, @(3, r1)
bf8k mfail
bor.b #1, @(3, r1)
bf8k mfail
band.b #2, @(3, r1)
bf8k mfail
bor.b #3, @(3, r1)
bf8k mfail
bor.b #4, @(3, r1)
bf8k mfail
band.b #5, @(3, r1)
bf8k mfail
bor.b #6, @(3, r1)
bf8k mfail
band.b #7, @(3, r1)
bf8k mfail
band.b #0, @(2, r1)
bf8k mfail
bor.b #1, @(2, r1)
bf8k mfail
band.b #2, @(2, r1)
bf8k mfail
bor.b #3, @(2, r1)
bf8k mfail
bra .L2
nop
.align 2
x: .long _x
.L2:
bor.b #4, @(2, r1)
bf8k mfail
band.b #5, @(2, r1)
bf8k mfail
bor.b #6, @(2, r1)
bf8k mfail
band.b #7, @(2, r1)
bf8k mfail
band.b #0, @(1, r1)
bf8k mfail
bor.b #1, @(1, r1)
bf8k mfail
band.b #2, @(1, r1)
bf8k mfail
bor.b #3, @(1, r1)
bf8k mfail
bor.b #4, @(1, r1)
bf8k mfail
band.b #5, @(1, r1)
bf8k mfail
bor.b #6, @(1, r1)
bf8k mfail
band.b #7, @(1, r1)
bf8k mfail
band.b #0, @(0, r1)
bf8k mfail
bor.b #1, @(0, r1)
bf8k mfail
band.b #2, @(0, r1)
bf8k mfail
bor.b #3, @(0, r1)
bf8k mfail
bor.b #4, @(0, r1)
bf8k mfail
band.b #5, @(0, r1)
bf8k mfail
bor.b #6, @(0, r1)
bf8k mfail
band.b #7, @(0, r1)
bf8k mfail
assertreg _x, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 1,805
|
sim/testsuite/sh/pinc.s
|
# sh testcase for pinc
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pincx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pinc x0, y0
assert_sreg 0xa5a60000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pincy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pinc y0, x0
assert_sreg 0xa5a60000, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dct_pincx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_dcfalse
dct pinc x0, y0
assert_sreg 0xa5a5a5a5, y0
set_dctrue
dct pinc x0, y0
assert_sreg 0xa5a60000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dcf_pincy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_dctrue
dcf pinc y0, x0
assert_sreg 0xa5a5a5a5, x0
set_dcfalse
dcf pinc y0, x0
assert_sreg 0xa5a60000, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
stsp/binutils-ia16
| 3,257
|
sim/testsuite/sh/div.s
|
# sh testcase for divs and divu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
divs_1: ! divide by one
set_grs_a5a5
mov #1, r0
divs r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_2: ! divide by two
set_grs_a5a5
mov #2, r0
divs r0, r1
assertreg0 2
assertreg 0xd2d2d2d3, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_3: ! divide by three
set_grs_a5a5
mov #3, r0
divs r0, r1
assertreg0 3
assertreg 0xe1e1e1e2, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_0: ! divide by zero
set_grs_a5a5
mov #0, r0
divs r0, r1
assertreg0 0
assertreg 0x7fffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_o: ! divide signed overflow
set_grs_a5a5
mov #16, r0
movi20 #0x8000, r1
shad r0, r1 ! r1 == 0x80000000
mov #-1, r0
divs r0, r1
assertreg0 -1
assertreg 0x7fffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_1: ! divide by one, unsigned
set_grs_a5a5
mov #1, r0
divu r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_2: ! divide by two, unsigned
set_grs_a5a5
mov #2, r0
divu r0, r1
assertreg0 2
assertreg 0x52d2d2d2, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_3: ! divide by three, unsigned
set_grs_a5a5
mov #3, r0
divu r0, r1
assertreg0 3
assertreg 0x37373737, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_0: ! divide by zero, unsigned
set_grs_a5a5
mov #0, r0
divu r0, r1
assertreg0 0
assertreg 0xffffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 2,568
|
sim/testsuite/sh/pshlr.s
|
# sh testcase for pshl <reg>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pshl_reg: ! shift arithmetic, register operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x10000, x0
set_sreg 0x0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x10000, y0
pshl x0, y0, x0
assert_sreg 0x20000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x20000, y0
pshl x0, y0, x0
assert_sreg 0x40000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x30000, y0
pshl x0, y0, x0
assert_sreg 0x80000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x40000, y0
pshl x0, y0, x0
assert_sreg 0x100000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x50000, y0
pshl x0, y0, x0
assert_sreg 0x200000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x60000, y0
pshl x0, y0, x0
assert_sreg 0x400000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x70000, y0
pshl x0, y0, x0
assert_sreg 0x800000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x80000, y0
pshl x0, y0, x0
assert_sreg 0x1000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x90000, y0
pshl x0, y0, x0
assert_sreg 0x2000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xa0000, y0
pshl x0, y0, x0
assert_sreg 0x4000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xb0000, y0
pshl x0, y0, x0
assert_sreg 0x8000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xc0000, y0
pshl x0, y0, x0
assert_sreg 0x10000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xd0000, y0
pshl x0, y0, x0
assert_sreg 0x20000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xe0000, y0
pshl x0, y0, x0
assert_sreg 0x40000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xf0000, y0
pshl x0, y0, x0
assert_sreg 0x80000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x100000, y0
pshl x0, y0, x0
assert_sreg 0x00000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x0, x0
test_grs_a5a5
assert_sreg2 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
stsp/binutils-ia16
| 6,051
|
sim/testsuite/sh/loop.s
|
# sh testcase for loop control
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
loop1:
set_grs_a5a5
ldrs Loop1_start0+8
ldre Loop1_start0+4
setrc #5
Loop1_start0:
add #1, r1 ! Before loop
# Loop should execute one instruction five times.
Loop1_begin:
add #1, r1 ! Within loop
Loop1_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
assertreg 0xa5a5a5a5+8, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop2:
set_grs_a5a5
ldrs Loop2_start0+6
ldre Loop2_start0+4
setrc #5
Loop2_start0:
add #1, r1 ! Before loop
# Loop should execute two instructions five times.
Loop2_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop2_end:
add #3, r1 ! After loop
# r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before)
assertreg 0xa5a5a5a5+14, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop3:
set_grs_a5a5
ldrs Loop3_start0+4
ldre Loop3_start0+4
setrc #5
Loop3_start0:
add #1, r1 ! Before loop
# Loop should execute three instructions five times.
Loop3_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop3_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
assertreg 0xa5a5a5a5+18, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop4:
set_grs_a5a5
ldrs Loop4_begin
ldre Loop4_last3+4
setrc #5
add #1, r1 ! Before loop
# Loop should execute four instructions five times.
Loop4_begin:
Loop4_last3:
add #1, r1 ! Within loop
Loop4_last2:
add #1, r1 ! Within loop
Loop4_last1:
add #1, r1 ! Within loop
Loop4_last:
add #1, r1 ! Within loop
Loop4_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before)
assertreg 0xa5a5a5a5+23, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop5:
set_grs_a5a5
ldrs Loop5_begin
ldre Loop5_last3+4
setrc #5
add #1, r1 ! Before loop
# Loop should execute five instructions five times.
Loop5_begin:
add #1, r1 ! Within loop
Loop5_last3:
add #1, r1 ! Within loop
Loop5_last2:
add #1, r1 ! Within loop
Loop5_last1:
add #1, r1 ! Within loop
Loop5_last:
add #1, r1 ! Within loop
Loop5_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before)
assertreg 0xa5a5a5a5+28, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loopn:
set_grs_a5a5
ldrs Loopn_begin
ldre Loopn_last3+4
setrc #5
add #1, r1 ! Before loop
# Loop should execute n instructions five times.
Loopn_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loopn_last3:
add #1, r1 ! Within loop
Loopn_last2:
add #1, r1 ! Within loop
Loopn_last1:
add #1, r1 ! Within loop
Loopn_last:
add #1, r1 ! Within loop
Loopn_end:
add #3, r1 ! After loop
# r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before)
assertreg 0xa5a5a5a5+64, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop1e:
set_grs_a5a5
ldrs Loop1e_begin
ldre Loop1e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute one instruction five times.
Loop1e_begin:
Loop1e_last:
add #1, r1 ! Within loop
Loop1e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
assertreg 0xa5a5a5a5+8, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop2e:
set_grs_a5a5
ldrs Loop2e_begin
ldre Loop2e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute two instructions five times.
Loop2e_begin:
add #1, r1 ! Within loop
Loop2e_last:
add #1, r1 ! Within loop
Loop2e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before)
assertreg 0xa5a5a5a5+13, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop3e:
set_grs_a5a5
ldrs Loop3e_begin
ldre Loop3e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute three instructions five times.
Loop3e_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop3e_last:
add #1, r1 ! Within loop
Loop3e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
assertreg 0xa5a5a5a5+18, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop4e:
set_grs_a5a5
ldrs Loop4e_begin
ldre Loop4e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute four instructions five times.
Loop4e_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop4e_last:
add #1, r1 ! Within loop
Loop4e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before)
assertreg 0xa5a5a5a5+23, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop5e:
set_grs_a5a5
ldrs Loop5e_begin
ldre Loop5e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute five instructions five times.
Loop5e_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop5e_last:
add #1, r1 ! Within loop
Loop5e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before)
assertreg 0xa5a5a5a5+28, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop_n_e:
set_grs_a5a5
ldrs Loop_n_e_begin
ldre Loop_n_e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute n instructions five times.
Loop_n_e_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop_n_e_last:
add #1, r1 ! Within loop
Loop_n_e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before)
assertreg 0xa5a5a5a5+48, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
|
stsp/binutils-ia16
| 4,107
|
sim/testsuite/sh/resbank.s
|
# sh testcase for ldbank stbank resbank
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.macro SEND reg bankno regno
set_greg ((\bankno << 7) + (\regno << 2)), \reg
.endm
start
stbank_1:
set_grs_a5a5
mov #0, r0
SEND r1, 0, 0
stbank r0, @r1
mov #1, r0
SEND r1, 0, 1
stbank r0, @r1
mov #2, r0
SEND r1, 0, 2
stbank r0, @r1
mov #3, r0
SEND r1, 0, 3
stbank r0, @r1
mov #4, r0
SEND r1, 0, 4
stbank r0, @r1
mov #5, r0
SEND r1, 0, 5
stbank r0, @r1
mov #6, r0
SEND r1, 0, 6
stbank r0, @r1
mov #7, r0
SEND r1, 0, 7
stbank r0, @r1
mov #8, r0
SEND r1, 0, 8
stbank r0, @r1
mov #9, r0
SEND r1, 0, 9
stbank r0, @r1
mov #10, r0
SEND r1, 0, 10
stbank r0, @r1
mov #11, r0
SEND r1, 0, 11
stbank r0, @r1
mov #12, r0
SEND r1, 0, 12
stbank r0, @r1
mov #13, r0
SEND r1, 0, 13
stbank r0, @r1
mov #14, r0
SEND r1, 0, 14
stbank r0, @r1
mov #15, r0
SEND r1, 0, 15
stbank r0, @r1
mov #16, r0
SEND r1, 0, 16
stbank r0, @r1
mov #17, r0
SEND r1, 0, 17
stbank r0, @r1
mov #18, r0
SEND r1, 0, 18
stbank r0, @r1
mov #19, r0
SEND r1, 0, 19
stbank r0, @r1
assertreg0 19
assertreg 19 << 2, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
ldbank_1:
set_grs_a5a5
SEND r1, 0, 0
ldbank @r1, r0
assertreg0 0
SEND r1, 0, 1
ldbank @r1, r0
assertreg0 1
SEND r1, 0, 2
ldbank @r1, r0
assertreg0 2
SEND r1, 0, 3
ldbank @r1, r0
assertreg0 3
SEND r1, 0, 4
ldbank @r1, r0
assertreg0 4
SEND r1, 0, 5
ldbank @r1, r0
assertreg0 5
SEND r1, 0, 6
ldbank @r1, r0
assertreg0 6
SEND r1, 0, 7
ldbank @r1, r0
assertreg0 7
SEND r1, 0, 8
ldbank @r1, r0
assertreg0 8
SEND r1, 0, 9
ldbank @r1, r0
assertreg0 9
SEND r1, 0, 10
ldbank @r1, r0
assertreg0 10
SEND r1, 0, 11
ldbank @r1, r0
assertreg0 11
SEND r1, 0, 12
ldbank @r1, r0
assertreg0 12
SEND r1, 0, 13
ldbank @r1, r0
assertreg0 13
SEND r1, 0, 14
ldbank @r1, r0
assertreg0 14
SEND r1, 0, 15
ldbank @r1, r0
assertreg0 15
SEND r1, 0, 16
ldbank @r1, r0
assertreg0 16
SEND r1, 0, 17
ldbank @r1, r0
assertreg0 17
SEND r1, 0, 18
ldbank @r1, r0
assertreg0 18
SEND r1, 0, 19
ldbank @r1, r0
assertreg0 19
assertreg (19 << 2), r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
resbank_1:
set_grs_a5a5
mov #1, r0
trapa #13 ! magic trap, sets ibnr
resbank
assertreg0 0
assertreg 1, r1
assertreg 2, r2
assertreg 3, r3
assertreg 4, r4
assertreg 5, r5
assertreg 6, r6
assertreg 7, r7
assertreg 8, r8
assertreg 9, r9
assertreg 10, r10
assertreg 11, r11
assertreg 12, r12
assertreg 13, r13
assertreg 14, r14
assert_sreg 15, mach
assert_sreg 17, pr
assert_creg 18, gbr
assert_sreg 19, macl
resbank_2:
set_grs_a5a5
movi20 #555, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
set_sr_bit (1 << 14) ! set BO
resbank
assert_sreg 555, macl
assert_sreg 554, mach
assert_creg 553, gbr
assert_sreg 552, pr
assertreg 551, r14
assertreg 550, r13
assertreg 549, r12
assertreg 548, r11
assertreg 547, r10
assertreg 546, r9
assertreg 545, r8
assertreg 544, r7
assertreg 543, r6
assertreg 542, r5
assertreg 541, r4
assertreg 540, r3
assertreg 539, r2
assertreg 538, r1
assertreg0 537
mov r15, r0
assertreg0 stackt
pass
exit 0
|
stsp/binutils-ia16
| 32,830
|
sim/testsuite/sh/movxy.s
|
# sh testcase for movxy
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
src1: .word 1
src2: .word 2
src3: .word 3
src4: .word 4
src5: .word 5
src6: .word 6
src7: .word 7
src8: .word 8
src9: .word 9
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
dst1: .word 0
dst2: .word 0
dst3: .word 0
dst4: .word 0
dst5: .word 0
dst6: .word 0
dst7: .word 0
dst8: .word 0
dst9: .word 0
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
start
movxw_nopy:
set_grs_a5a5
# load up pointers
mov.l srcp1, r4
mov.l dstp1, r5
# perform moves
movx.w @r4, x0
pcopy x0, a0
movx.w a0, @r5
# verify pointers unchanged
mov.l srcp1, r0
cmp/eq r0, r4
bt .L0
fail
.L0:
mov.l dstp1, r1
cmp/eq r1, r5
bt .L1
fail
.L1:
# verify copied values
mov.w @r0, r0
mov.w @r1, r1
cmp/eq r0, r1
bt .L2
fail
.L2:
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
movyw_nopx:
set_grs_a5a5
# load up pointers
mov.l srcp2, r6
mov.l dstp2, r7
# perform moves
movy.w @r6, y0
pcopy y0, a0
movy.w a0, @r7
# verify pointers unchanged
mov.l srcp2, r2
cmp/eq r2, r6
bt .L3
fail
.L3:
mov.l dstp2, r3
cmp/eq r3, r7
bt .L4
fail
.L4:
# verify copied values
mov.w @r2, r2
mov.w @r3, r3
cmp/eq r2, r3
bt .L5
fail
.L5:
test_gr_a5a5 r0
test_gr_a5a5 r1
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
movxw_movyw:
set_grs_a5a5
# load up pointers
mov.l srcp3, r4
mov.l dstp3, r5
mov.l srcp4, r6
mov.l dstp4, r7
# perform moves
movx.w @r4, x1 movy.w @r6, y1
pcopy x1, a0
pcopy y1, a1
movx.w a0, @r5 movy.w a1, @r7
# verify pointers unchanged
mov.l srcp3, r0
cmp/eq r0, r4
bt .L6
fail
.L6:
mov.l dstp3, r1
cmp/eq r1, r5
bt .L7
fail
.L7:
mov.l srcp4, r2
cmp/eq r2, r6
bt .L8
fail
.L8:
mov.l dstp4, r3
cmp/eq r3, r7
bt .L9
fail
.L9:
# verify copied values
mov.w @r0, r0
mov.w @r1, r1
cmp/eq r0, r1
bt .L10
fail
.L10:
mov.w @r2, r2
mov.w @r3, r3
cmp/eq r2, r3
bt .L11
fail
.L11:
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
bra movxw_movyw_new
nop
.align 2
srcp1: .long src1
srcp2: .long src2
srcp3: .long src3
srcp4: .long src4
srcp5: .long src5
srcp6: .long src6
srcp7: .long src7
srcp8: .long src8
srcp9: .long src9
dstp1: .long dst1
dstp2: .long dst2
dstp3: .long dst3
dstp4: .long dst4
dstp5: .long dst5
dstp6: .long dst6
dstp7: .long dst7
dstp8: .long dst8
dstp9: .long dst9
movxw_movyw_new:
set_grs_a5a5
# load up pointers
mov.l srcp5b, r0
mov.l dstp5b, r1
mov.l srcp6b, r2
mov.l dstp6b, r3
# perform moves
movx.w @r0, x1
movy.w @r2, y1
movx.w x1, @r1
movy.w y1, @r3
# verify pointers unchanged
mov.l srcp5b, r4
cmp/eq r0, r4
bt .L12
fail
.L12:
mov.l dstp5b, r5
cmp/eq r1, r5
bt .L13
fail
.L13:
mov.l srcp6b, r6
cmp/eq r2, r6
bt .L14
fail
.L14:
mov.l dstp6b, r7
cmp/eq r3, r7
bt .L15
fail
.L15:
# verify copied values
mov.w @r0, r0
mov.w @r1, r1
cmp/eq r0, r1
bt .L16
fail
.L16:
mov.w @r2, r2
mov.w @r3, r3
cmp/eq r2, r3
bt .L17
fail
.L17:
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mov.l srcp1b, r0
mov.l dstp1b, r1
mov.l srcp2b, r2
mov.l dstp2b, r3
mov.l srcp1b, r4
mov.l dstp1b, r5
mov.l srcp2b, r6
mov.l dstp2b, r7
mov #4, r8
mov #4, r9
bra .L18
nop
.align 2
srcp1b: .long src1
srcp2b: .long src2
srcp3b: .long src3
srcp4b: .long src4
srcp5b: .long src5
srcp6b: .long src6
srcp7b: .long src7
srcp8b: .long src8
srcp9b: .long src9
dstp1b: .long dst1
dstp2b: .long dst2
dstp3b: .long dst3
dstp4b: .long dst4
dstp5b: .long dst5
dstp6b: .long dst6
dstp7b: .long dst7
dstp8b: .long dst8
dstp9b: .long dst9
.L18:
# movx.w @Ax{}, Dx | nopy
movxwaxdx_nopy:
movx.w @r4,x0 ! .word 0xf004
movx.w @r4,x1 ! .word 0xf084
movx.w @r5,x0 ! .word 0xf204
movx.w @r5,x1 ! .word 0xf284
movx.w @r4+,x0 ! .word 0xf008
movx.w @r4+,x1 ! .word 0xf088
movx.w @r5+,x0 ! .word 0xf208
movx.w @r5+,x1 ! .word 0xf288
movx.w @r4+r8,x0 ! .word 0xf00c
movx.w @r4+r8,x1 ! .word 0xf08c
movx.w @r5+r8,x0 ! .word 0xf20c
movx.w @r5+r8,x1 ! .word 0xf28c
# movx.w Da, @Ax{} | nopy
movxwdaax_nopy:
movx.w a0,@r4 ! .word 0xf024
movx.w a1,@r4 ! .word 0xf0a4
movx.w a0,@r5 ! .word 0xf224
movx.w a1,@r5 ! .word 0xf2a4
movx.w a0,@r4+ ! .word 0xf028
movx.w a1,@r4+ ! .word 0xf0a8
movx.w a0,@r5+ ! .word 0xf228
movx.w a1,@r5+ ! .word 0xf2a8
movx.w a0,@r4+r8 ! .word 0xf02c
movx.w a1,@r4+r8 ! .word 0xf0ac
movx.w a0,@r5+r8 ! .word 0xf22c
movx.w a1,@r5+r8 ! .word 0xf2ac
# movy.w @Ay{}, Dy | nopx
movywaydy_nopx:
movy.w @r6,y0 ! .word 0xf001
movy.w @r6,y1 ! .word 0xf041
movy.w @r7,y0 ! .word 0xf101
movy.w @r7,y1 ! .word 0xf141
movy.w @r6+,y0 ! .word 0xf002
movy.w @r6+,y1 ! .word 0xf042
movy.w @r7+,y0 ! .word 0xf102
movy.w @r7+,y1 ! .word 0xf142
movy.w @r6+r9,y0 ! .word 0xf003
movy.w @r6+r9,y1 ! .word 0xf043
movy.w @r7+r9,y0 ! .word 0xf103
movy.w @r7+r9,y1 ! .word 0xf143
# movy.w Da, @Ay{} | nopx
movywdaay_nopx:
movy.w a0,@r6 ! .word 0xf011
movy.w a1,@r6 ! .word 0xf051
movy.w a0,@r7 ! .word 0xf111
movy.w a1,@r7 ! .word 0xf151
movy.w a0,@r6+ ! .word 0xf012
movy.w a1,@r6+ ! .word 0xf052
movy.w a0,@r7+ ! .word 0xf112
movy.w a1,@r7+ ! .word 0xf152
movy.w a0,@r6+r9 ! .word 0xf013
movy.w a1,@r6+r9 ! .word 0xf053
movy.w a0,@r7+r9 ! .word 0xf113
movy.w a1,@r7+r9 ! .word 0xf153
# movx {} || movy {}
movx_movy:
movx.w @r4,x0 movy.w @r6,y0 ! .word 0xf005
movx.w @r4,x0 movy.w @r6,y1 ! .word 0xf045
movx.w @r4,x1 movy.w @r6,y0 ! .word 0xf085
movx.w @r4,x1 movy.w @r6,y1 ! .word 0xf0c5
movx.w @r4,x0 movy.w @r7,y0 ! .word 0xf105
movx.w @r4,x0 movy.w @r7,y1 ! .word 0xf145
movx.w @r4,x1 movy.w @r7,y0 ! .word 0xf185
movx.w @r4,x1 movy.w @r7,y1 ! .word 0xf1c5
movx.w @r5,x0 movy.w @r6,y0 ! .word 0xf205
movx.w @r5,x0 movy.w @r6,y1 ! .word 0xf245
movx.w @r5,x1 movy.w @r6,y0 ! .word 0xf285
movx.w @r5,x1 movy.w @r6,y1 ! .word 0xf2c5
movx.w @r5,x0 movy.w @r7,y0 ! .word 0xf305
movx.w @r5,x0 movy.w @r7,y1 ! .word 0xf345
movx.w @r5,x1 movy.w @r7,y0 ! .word 0xf385
movx.w @r5,x1 movy.w @r7,y1 ! .word 0xf3c5
movx.w @r4,x0 movy.w @r6+,y0 ! .word 0xf006
movx.w @r4,x0 movy.w @r6+,y1 ! .word 0xf046
movx.w @r4,x1 movy.w @r6+,y0 ! .word 0xf086
movx.w @r4,x1 movy.w @r6+,y1 ! .word 0xf0c6
movx.w @r4,x0 movy.w @r7+,y0 ! .word 0xf106
movx.w @r4,x0 movy.w @r7+,y1 ! .word 0xf146
movx.w @r4,x1 movy.w @r7+,y0 ! .word 0xf186
movx.w @r4,x1 movy.w @r7+,y1 ! .word 0xf1c6
movx.w @r5,x0 movy.w @r6+,y0 ! .word 0xf206
movx.w @r5,x0 movy.w @r6+,y1 ! .word 0xf246
movx.w @r5,x1 movy.w @r6+,y0 ! .word 0xf286
movx.w @r5,x1 movy.w @r6+,y1 ! .word 0xf2c6
movx.w @r5,x0 movy.w @r7+,y0 ! .word 0xf306
movx.w @r5,x0 movy.w @r7+,y1 ! .word 0xf346
movx.w @r5,x1 movy.w @r7+,y0 ! .word 0xf386
movx.w @r5,x1 movy.w @r7+,y1 ! .word 0xf3c6
movx.w @r4,x0 movy.w @r6+r9,y0 ! .word 0xf007
movx.w @r4,x0 movy.w @r6+r9,y1 ! .word 0xf047
movx.w @r4,x1 movy.w @r6+r9,y0 ! .word 0xf087
movx.w @r4,x1 movy.w @r6+r9,y1 ! .word 0xf0c7
movx.w @r4,x0 movy.w @r7+r9,y0 ! .word 0xf107
movx.w @r4,x0 movy.w @r7+r9,y1 ! .word 0xf147
movx.w @r4,x1 movy.w @r7+r9,y0 ! .word 0xf187
movx.w @r4,x1 movy.w @r7+r9,y1 ! .word 0xf1c7
movx.w @r5,x0 movy.w @r6+r9,y0 ! .word 0xf207
movx.w @r5,x0 movy.w @r6+r9,y1 ! .word 0xf247
movx.w @r5,x1 movy.w @r6+r9,y0 ! .word 0xf287
movx.w @r5,x1 movy.w @r6+r9,y1 ! .word 0xf2c7
movx.w @r5,x0 movy.w @r7+r9,y0 ! .word 0xf307
movx.w @r5,x0 movy.w @r7+r9,y1 ! .word 0xf347
movx.w @r5,x1 movy.w @r7+r9,y0 ! .word 0xf387
movx.w @r5,x1 movy.w @r7+r9,y1 ! .word 0xf3c7
movx.w @r4+,x0 movy.w @r6,y0 ! .word 0xf009
movx.w @r4+,x0 movy.w @r6,y1 ! .word 0xf049
movx.w @r4+,x1 movy.w @r6,y0 ! .word 0xf089
movx.w @r4+,x1 movy.w @r6,y1 ! .word 0xf0c9
movx.w @r4+,x0 movy.w @r7,y0 ! .word 0xf109
movx.w @r4+,x0 movy.w @r7,y1 ! .word 0xf149
movx.w @r4+,x1 movy.w @r7,y0 ! .word 0xf189
movx.w @r4+,x1 movy.w @r7,y1 ! .word 0xf1c9
movx.w @r5+,x0 movy.w @r6,y0 ! .word 0xf209
movx.w @r5+,x0 movy.w @r6,y1 ! .word 0xf249
movx.w @r5+,x1 movy.w @r6,y0 ! .word 0xf289
movx.w @r5+,x1 movy.w @r6,y1 ! .word 0xf2c9
movx.w @r5+,x0 movy.w @r7,y0 ! .word 0xf309
movx.w @r5+,x0 movy.w @r7,y1 ! .word 0xf349
movx.w @r5+,x1 movy.w @r7,y0 ! .word 0xf389
movx.w @r5+,x1 movy.w @r7,y1 ! .word 0xf3c9
movx.w @r4+,x0 movy.w @r6+,y0 ! .word 0xf00a
movx.w @r4+,x0 movy.w @r6+,y1 ! .word 0xf04a
movx.w @r4+,x1 movy.w @r6+,y0 ! .word 0xf08a
movx.w @r4+,x1 movy.w @r6+,y1 ! .word 0xf0ca
movx.w @r4+,x0 movy.w @r7+,y0 ! .word 0xf10a
movx.w @r4+,x0 movy.w @r7+,y1 ! .word 0xf14a
movx.w @r4+,x1 movy.w @r7+,y0 ! .word 0xf18a
movx.w @r4+,x1 movy.w @r7+,y1 ! .word 0xf1ca
movx.w @r5+,x0 movy.w @r6+,y0 ! .word 0xf20a
movx.w @r5+,x0 movy.w @r6+,y1 ! .word 0xf24a
movx.w @r5+,x1 movy.w @r6+,y0 ! .word 0xf28a
movx.w @r5+,x1 movy.w @r6+,y1 ! .word 0xf2ca
movx.w @r5+,x0 movy.w @r7+,y0 ! .word 0xf30a
movx.w @r5+,x0 movy.w @r7+,y1 ! .word 0xf34a
movx.w @r5+,x1 movy.w @r7+,y0 ! .word 0xf38a
movx.w @r5+,x1 movy.w @r7+,y1 ! .word 0xf3ca
movx.w @r4+,x0 movy.w @r6+r9,y0 ! .word 0xf00b
movx.w @r4+,x0 movy.w @r6+r9,y1 ! .word 0xf04b
movx.w @r4+,x1 movy.w @r6+r9,y0 ! .word 0xf08b
movx.w @r4+,x1 movy.w @r6+r9,y1 ! .word 0xf0cb
movx.w @r4+,x0 movy.w @r7+r9,y0 ! .word 0xf10b
movx.w @r4+,x0 movy.w @r7+r9,y1 ! .word 0xf14b
movx.w @r4+,x1 movy.w @r7+r9,y0 ! .word 0xf18b
movx.w @r4+,x1 movy.w @r7+r9,y1 ! .word 0xf1cb
movx.w @r5+,x0 movy.w @r6+r9,y0 ! .word 0xf20b
movx.w @r5+,x0 movy.w @r6+r9,y1 ! .word 0xf24b
movx.w @r5+,x1 movy.w @r6+r9,y0 ! .word 0xf28b
movx.w @r5+,x1 movy.w @r6+r9,y1 ! .word 0xf2cb
movx.w @r5+,x0 movy.w @r7+r9,y0 ! .word 0xf30b
movx.w @r5+,x0 movy.w @r7+r9,y1 ! .word 0xf34b
movx.w @r5+,x1 movy.w @r7+r9,y0 ! .word 0xf38b
movx.w @r5+,x1 movy.w @r7+r9,y1 ! .word 0xf3cb
movx.w @r4+r8,x0 movy.w @r6,y0 ! .word 0xf00d
movx.w @r4+r8,x0 movy.w @r6,y1 ! .word 0xf04d
movx.w @r4+r8,x1 movy.w @r6,y0 ! .word 0xf08d
movx.w @r4+r8,x1 movy.w @r6,y1 ! .word 0xf0cd
movx.w @r4+r8,x0 movy.w @r7,y0 ! .word 0xf10d
movx.w @r4+r8,x0 movy.w @r7,y1 ! .word 0xf14d
movx.w @r4+r8,x1 movy.w @r7,y0 ! .word 0xf18d
movx.w @r4+r8,x1 movy.w @r7,y1 ! .word 0xf1cd
movx.w @r5+r8,x0 movy.w @r6,y0 ! .word 0xf20d
movx.w @r5+r8,x0 movy.w @r6,y1 ! .word 0xf24d
movx.w @r5+r8,x1 movy.w @r6,y0 ! .word 0xf28d
movx.w @r5+r8,x1 movy.w @r6,y1 ! .word 0xf2cd
movx.w @r5+r8,x0 movy.w @r7,y0 ! .word 0xf30d
movx.w @r5+r8,x0 movy.w @r7,y1 ! .word 0xf34d
movx.w @r5+r8,x1 movy.w @r7,y0 ! .word 0xf38d
movx.w @r5+r8,x1 movy.w @r7,y1 ! .word 0xf3cd
movx.w @r4+r8,x0 movy.w @r6+,y0 ! .word 0xf00e
movx.w @r4+r8,x0 movy.w @r6+,y1 ! .word 0xf04e
movx.w @r4+r8,x1 movy.w @r6+,y0 ! .word 0xf08e
movx.w @r4+r8,x1 movy.w @r6+,y1 ! .word 0xf0ce
movx.w @r4+r8,x0 movy.w @r7+,y0 ! .word 0xf10e
movx.w @r4+r8,x0 movy.w @r7+,y1 ! .word 0xf14e
movx.w @r4+r8,x1 movy.w @r7+,y0 ! .word 0xf18e
movx.w @r4+r8,x1 movy.w @r7+,y1 ! .word 0xf1ce
movx.w @r5+r8,x0 movy.w @r6+,y0 ! .word 0xf20e
movx.w @r5+r8,x0 movy.w @r6+,y1 ! .word 0xf24e
movx.w @r5+r8,x1 movy.w @r6+,y0 ! .word 0xf28e
movx.w @r5+r8,x1 movy.w @r6+,y1 ! .word 0xf2ce
movx.w @r5+r8,x0 movy.w @r7+,y0 ! .word 0xf30e
movx.w @r5+r8,x0 movy.w @r7+,y1 ! .word 0xf34e
movx.w @r5+r8,x1 movy.w @r7+,y0 ! .word 0xf38e
movx.w @r5+r8,x1 movy.w @r7+,y1 ! .word 0xf3ce
movx.w @r4+r8,x0 movy.w @r6+r9,y0 ! .word 0xf00f
movx.w @r4+r8,x0 movy.w @r6+r9,y1 ! .word 0xf04f
movx.w @r4+r8,x1 movy.w @r6+r9,y0 ! .word 0xf08f
movx.w @r4+r8,x1 movy.w @r6+r9,y1 ! .word 0xf0cf
movx.w @r4+r8,x0 movy.w @r7+r9,y0 ! .word 0xf10f
movx.w @r4+r8,x0 movy.w @r7+r9,y1 ! .word 0xf14f
movx.w @r4+r8,x1 movy.w @r7+r9,y0 ! .word 0xf18f
movx.w @r4+r8,x1 movy.w @r7+r9,y1 ! .word 0xf1cf
movx.w @r5+r8,x0 movy.w @r6+r9,y0 ! .word 0xf20f
movx.w @r5+r8,x0 movy.w @r6+r9,y1 ! .word 0xf24f
movx.w @r5+r8,x1 movy.w @r6+r9,y0 ! .word 0xf28f
movx.w @r5+r8,x1 movy.w @r6+r9,y1 ! .word 0xf2cf
movx.w @r5+r8,x0 movy.w @r7+r9,y0 ! .word 0xf30f
movx.w @r5+r8,x0 movy.w @r7+r9,y1 ! .word 0xf34f
movx.w @r5+r8,x1 movy.w @r7+r9,y0 ! .word 0xf38f
movx.w @r5+r8,x1 movy.w @r7+r9,y1 ! .word 0xf3cf
movx.w @r4,x0 movy.w a0,@r6 ! .word 0xf015
movx.w @r4,x0 movy.w a1,@r6 ! .word 0xf055
movx.w @r4,x1 movy.w a0,@r6 ! .word 0xf095
movx.w @r4,x1 movy.w a1,@r6 ! .word 0xf0d5
movx.w @r4,x0 movy.w a0,@r7 ! .word 0xf115
movx.w @r4,x0 movy.w a1,@r7 ! .word 0xf155
movx.w @r4,x1 movy.w a0,@r7 ! .word 0xf195
movx.w @r4,x1 movy.w a1,@r7 ! .word 0xf1d5
movx.w @r5,x0 movy.w a0,@r6 ! .word 0xf215
movx.w @r5,x0 movy.w a1,@r6 ! .word 0xf255
movx.w @r5,x1 movy.w a0,@r6 ! .word 0xf295
movx.w @r5,x1 movy.w a1,@r6 ! .word 0xf2d5
movx.w @r5,x0 movy.w a0,@r7 ! .word 0xf315
movx.w @r5,x0 movy.w a1,@r7 ! .word 0xf355
movx.w @r5,x1 movy.w a0,@r7 ! .word 0xf395
movx.w @r5,x1 movy.w a1,@r7 ! .word 0xf3d5
movx.w @r4,x0 movy.w a0,@r6+ ! .word 0xf016
movx.w @r4,x0 movy.w a1,@r6+ ! .word 0xf056
movx.w @r4,x1 movy.w a0,@r6+ ! .word 0xf096
movx.w @r4,x1 movy.w a1,@r6+ ! .word 0xf0d6
movx.w @r4,x0 movy.w a0,@r7+ ! .word 0xf116
movx.w @r4,x0 movy.w a1,@r7+ ! .word 0xf156
movx.w @r4,x1 movy.w a0,@r7+ ! .word 0xf196
movx.w @r4,x1 movy.w a1,@r7+ ! .word 0xf1d6
movx.w @r5,x0 movy.w a0,@r6+ ! .word 0xf216
movx.w @r5,x0 movy.w a1,@r6+ ! .word 0xf256
movx.w @r5,x1 movy.w a0,@r6+ ! .word 0xf296
movx.w @r5,x1 movy.w a1,@r6+ ! .word 0xf2d6
movx.w @r5,x0 movy.w a0,@r7+ ! .word 0xf316
movx.w @r5,x0 movy.w a1,@r7+ ! .word 0xf356
movx.w @r5,x1 movy.w a0,@r7+ ! .word 0xf396
movx.w @r5,x1 movy.w a1,@r7+ ! .word 0xf3d6
movx.w @r4,x0 movy.w a0,@r6+r9 ! .word 0xf017
movx.w @r4,x0 movy.w a1,@r6+r9 ! .word 0xf057
movx.w @r4,x1 movy.w a0,@r6+r9 ! .word 0xf097
movx.w @r4,x1 movy.w a1,@r6+r9 ! .word 0xf0d7
movx.w @r4,x0 movy.w a0,@r7+r9 ! .word 0xf117
movx.w @r4,x0 movy.w a1,@r7+r9 ! .word 0xf157
movx.w @r4,x1 movy.w a0,@r7+r9 ! .word 0xf197
movx.w @r4,x1 movy.w a1,@r7+r9 ! .word 0xf1d7
movx.w @r5,x0 movy.w a0,@r6+r9 ! .word 0xf217
movx.w @r5,x0 movy.w a1,@r6+r9 ! .word 0xf257
movx.w @r5,x1 movy.w a0,@r6+r9 ! .word 0xf297
movx.w @r5,x1 movy.w a1,@r6+r9 ! .word 0xf2d7
movx.w @r5,x0 movy.w a0,@r7+r9 ! .word 0xf317
movx.w @r5,x0 movy.w a1,@r7+r9 ! .word 0xf357
movx.w @r5,x1 movy.w a0,@r7+r9 ! .word 0xf397
movx.w @r5,x1 movy.w a1,@r7+r9 ! .word 0xf3d7
movx.w @r4+,x0 movy.w a0,@r6 ! .word 0xf019
movx.w @r4+,x0 movy.w a1,@r6 ! .word 0xf059
movx.w @r4+,x1 movy.w a0,@r6 ! .word 0xf099
movx.w @r4+,x1 movy.w a1,@r6 ! .word 0xf0d9
movx.w @r4+,x0 movy.w a0,@r7 ! .word 0xf119
movx.w @r4+,x0 movy.w a1,@r7 ! .word 0xf159
movx.w @r4+,x1 movy.w a0,@r7 ! .word 0xf199
movx.w @r4+,x1 movy.w a1,@r7 ! .word 0xf1d9
movx.w @r5+,x0 movy.w a0,@r6 ! .word 0xf219
movx.w @r5+,x0 movy.w a1,@r6 ! .word 0xf259
movx.w @r5+,x1 movy.w a0,@r6 ! .word 0xf299
movx.w @r5+,x1 movy.w a1,@r6 ! .word 0xf2d9
movx.w @r5+,x0 movy.w a0,@r7 ! .word 0xf319
movx.w @r5+,x0 movy.w a1,@r7 ! .word 0xf359
movx.w @r5+,x1 movy.w a0,@r7 ! .word 0xf399
movx.w @r5+,x1 movy.w a1,@r7 ! .word 0xf3d9
movx.w @r4+,x0 movy.w a0,@r6+ ! .word 0xf01a
movx.w @r4+,x0 movy.w a1,@r6+ ! .word 0xf05a
movx.w @r4+,x1 movy.w a0,@r6+ ! .word 0xf09a
movx.w @r4+,x1 movy.w a1,@r6+ ! .word 0xf0da
movx.w @r4+,x0 movy.w a0,@r7+ ! .word 0xf11a
movx.w @r4+,x0 movy.w a1,@r7+ ! .word 0xf15a
movx.w @r4+,x1 movy.w a0,@r7+ ! .word 0xf19a
movx.w @r4+,x1 movy.w a1,@r7+ ! .word 0xf1da
movx.w @r5+,x0 movy.w a0,@r6+ ! .word 0xf21a
movx.w @r5+,x0 movy.w a1,@r6+ ! .word 0xf25a
movx.w @r5+,x1 movy.w a0,@r6+ ! .word 0xf29a
movx.w @r5+,x1 movy.w a1,@r6+ ! .word 0xf2da
movx.w @r5+,x0 movy.w a0,@r7+ ! .word 0xf31a
movx.w @r5+,x0 movy.w a1,@r7+ ! .word 0xf35a
movx.w @r5+,x1 movy.w a0,@r7+ ! .word 0xf39a
movx.w @r5+,x1 movy.w a1,@r7+ ! .word 0xf3da
movx.w @r4+,x0 movy.w a0,@r6+r9 ! .word 0xf01b
movx.w @r4+,x0 movy.w a1,@r6+r9 ! .word 0xf05b
movx.w @r4+,x1 movy.w a0,@r6+r9 ! .word 0xf09b
movx.w @r4+,x1 movy.w a1,@r6+r9 ! .word 0xf0db
movx.w @r4+,x0 movy.w a0,@r7+r9 ! .word 0xf11b
movx.w @r4+,x0 movy.w a1,@r7+r9 ! .word 0xf15b
movx.w @r4+,x1 movy.w a0,@r7+r9 ! .word 0xf19b
movx.w @r4+,x1 movy.w a1,@r7+r9 ! .word 0xf1db
movx.w @r5+,x0 movy.w a0,@r6+r9 ! .word 0xf21b
movx.w @r5+,x0 movy.w a1,@r6+r9 ! .word 0xf25b
movx.w @r5+,x1 movy.w a0,@r6+r9 ! .word 0xf29b
movx.w @r5+,x1 movy.w a1,@r6+r9 ! .word 0xf2db
movx.w @r5+,x0 movy.w a0,@r7+r9 ! .word 0xf31b
movx.w @r5+,x0 movy.w a1,@r7+r9 ! .word 0xf35b
movx.w @r5+,x1 movy.w a0,@r7+r9 ! .word 0xf39b
movx.w @r5+,x1 movy.w a1,@r7+r9 ! .word 0xf3db
movx.w @r4+r8,x0 movy.w a0,@r6 ! .word 0xf01d
movx.w @r4+r8,x0 movy.w a1,@r6 ! .word 0xf05d
movx.w @r4+r8,x1 movy.w a0,@r6 ! .word 0xf09d
movx.w @r4+r8,x1 movy.w a1,@r6 ! .word 0xf0dd
movx.w @r4+r8,x0 movy.w a0,@r7 ! .word 0xf11d
movx.w @r4+r8,x0 movy.w a1,@r7 ! .word 0xf15d
movx.w @r4+r8,x1 movy.w a0,@r7 ! .word 0xf19d
movx.w @r4+r8,x1 movy.w a1,@r7 ! .word 0xf1dd
movx.w @r5+r8,x0 movy.w a0,@r6 ! .word 0xf21d
movx.w @r5+r8,x0 movy.w a1,@r6 ! .word 0xf25d
movx.w @r5+r8,x1 movy.w a0,@r6 ! .word 0xf29d
movx.w @r5+r8,x1 movy.w a1,@r6 ! .word 0xf2dd
movx.w @r5+r8,x0 movy.w a0,@r7 ! .word 0xf31d
movx.w @r5+r8,x0 movy.w a1,@r7 ! .word 0xf35d
movx.w @r5+r8,x1 movy.w a0,@r7 ! .word 0xf39d
movx.w @r5+r8,x1 movy.w a1,@r7 ! .word 0xf3dd
movx.w @r4+r8,x0 movy.w a0,@r6+ ! .word 0xf01e
movx.w @r4+r8,x0 movy.w a1,@r6+ ! .word 0xf05e
movx.w @r4+r8,x1 movy.w a0,@r6+ ! .word 0xf09e
movx.w @r4+r8,x1 movy.w a1,@r6+ ! .word 0xf0de
movx.w @r4+r8,x0 movy.w a0,@r7+ ! .word 0xf11e
movx.w @r4+r8,x0 movy.w a1,@r7+ ! .word 0xf15e
movx.w @r4+r8,x1 movy.w a0,@r7+ ! .word 0xf19e
movx.w @r4+r8,x1 movy.w a1,@r7+ ! .word 0xf1de
movx.w @r5+r8,x0 movy.w a0,@r6+ ! .word 0xf21e
movx.w @r5+r8,x0 movy.w a1,@r6+ ! .word 0xf25e
movx.w @r5+r8,x1 movy.w a0,@r6+ ! .word 0xf29e
movx.w @r5+r8,x1 movy.w a1,@r6+ ! .word 0xf2de
movx.w @r5+r8,x0 movy.w a0,@r7+ ! .word 0xf31e
movx.w @r5+r8,x0 movy.w a1,@r7+ ! .word 0xf35e
movx.w @r5+r8,x1 movy.w a0,@r7+ ! .word 0xf39e
movx.w @r5+r8,x1 movy.w a1,@r7+ ! .word 0xf3de
movx.w @r4+r8,x0 movy.w a0,@r6+r9 ! .word 0xf01f
movx.w @r4+r8,x0 movy.w a1,@r6+r9 ! .word 0xf05f
movx.w @r4+r8,x1 movy.w a0,@r6+r9 ! .word 0xf09f
movx.w @r4+r8,x1 movy.w a1,@r6+r9 ! .word 0xf0df
movx.w @r4+r8,x0 movy.w a0,@r7+r9 ! .word 0xf11f
movx.w @r4+r8,x0 movy.w a1,@r7+r9 ! .word 0xf15f
movx.w @r4+r8,x1 movy.w a0,@r7+r9 ! .word 0xf19f
movx.w @r4+r8,x1 movy.w a1,@r7+r9 ! .word 0xf1df
movx.w @r5+r8,x0 movy.w a0,@r6+r9 ! .word 0xf21f
movx.w @r5+r8,x0 movy.w a1,@r6+r9 ! .word 0xf25f
movx.w @r5+r8,x1 movy.w a0,@r6+r9 ! .word 0xf29f
movx.w @r5+r8,x1 movy.w a1,@r6+r9 ! .word 0xf2df
movx.w @r5+r8,x0 movy.w a0,@r7+r9 ! .word 0xf31f
movx.w @r5+r8,x0 movy.w a1,@r7+r9 ! .word 0xf35f
movx.w @r5+r8,x1 movy.w a0,@r7+r9 ! .word 0xf39f
movx.w @r5+r8,x1 movy.w a1,@r7+r9 ! .word 0xf3df
movx.w a0,@r4 movy.w @r6,y0 ! .word 0xf025
movx.w a0,@r4 movy.w @r6,y1 ! .word 0xf065
movx.w a1,@r4 movy.w @r6,y0 ! .word 0xf0a5
movx.w a1,@r4 movy.w @r6,y1 ! .word 0xf0e5
movx.w a0,@r4 movy.w @r7,y0 ! .word 0xf125
movx.w a0,@r4 movy.w @r7,y1 ! .word 0xf165
movx.w a1,@r4 movy.w @r7,y0 ! .word 0xf1a5
movx.w a1,@r4 movy.w @r7,y1 ! .word 0xf1e5
movx.w a0,@r5 movy.w @r6,y0 ! .word 0xf225
movx.w a0,@r5 movy.w @r6,y1 ! .word 0xf265
movx.w a1,@r5 movy.w @r6,y0 ! .word 0xf2a5
movx.w a1,@r5 movy.w @r6,y1 ! .word 0xf2e5
movx.w a0,@r5 movy.w @r7,y0 ! .word 0xf325
movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf365
movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf3a5
movx.w a1,@r5 movy.w @r7,y1 ! .word 0xf3e5
movx.w a0,@r4 movy.w @r6+,y0 ! .word 0xf026
movx.w a0,@r4 movy.w @r6+,y1 ! .word 0xf066
movx.w a1,@r4 movy.w @r6+,y0 ! .word 0xf0a6
movx.w a1,@r4 movy.w @r6+,y1 ! .word 0xf0e6
movx.w a0,@r4 movy.w @r7+,y0 ! .word 0xf126
movx.w a0,@r4 movy.w @r7+,y1 ! .word 0xf166
movx.w a1,@r4 movy.w @r7+,y0 ! .word 0xf1a6
movx.w a1,@r4 movy.w @r7+,y1 ! .word 0xf1e6
movx.w a0,@r5 movy.w @r6+,y0 ! .word 0xf226
movx.w a0,@r5 movy.w @r6+,y1 ! .word 0xf266
movx.w a1,@r5 movy.w @r6+,y0 ! .word 0xf2a6
movx.w a1,@r5 movy.w @r6+,y1 ! .word 0xf2e6
movx.w a0,@r5 movy.w @r7+,y0 ! .word 0xf326
movx.w a0,@r5 movy.w @r7+,y1 ! .word 0xf366
movx.w a1,@r5 movy.w @r7+,y0 ! .word 0xf3a6
movx.w a1,@r5 movy.w @r7+,y1 ! .word 0xf3e6
movx.w a0,@r4 movy.w @r6+r9,y0 ! .word 0xf027
movx.w a0,@r4 movy.w @r6+r9,y1 ! .word 0xf067
movx.w a1,@r4 movy.w @r6+r9,y0 ! .word 0xf0a7
movx.w a1,@r4 movy.w @r6+r9,y1 ! .word 0xf0e7
movx.w a0,@r4 movy.w @r7+r9,y0 ! .word 0xf127
movx.w a0,@r4 movy.w @r7+r9,y1 ! .word 0xf167
movx.w a1,@r4 movy.w @r7+r9,y0 ! .word 0xf1a7
movx.w a1,@r4 movy.w @r7+r9,y1 ! .word 0xf1e7
movx.w a0,@r5 movy.w @r6+r9,y0 ! .word 0xf227
movx.w a0,@r5 movy.w @r6+r9,y1 ! .word 0xf267
movx.w a1,@r5 movy.w @r6+r9,y0 ! .word 0xf2a7
movx.w a1,@r5 movy.w @r6+r9,y1 ! .word 0xf2e7
movx.w a0,@r5 movy.w @r7+r9,y0 ! .word 0xf327
movx.w a0,@r5 movy.w @r7+r9,y1 ! .word 0xf367
movx.w a1,@r5 movy.w @r7+r9,y0 ! .word 0xf3a7
movx.w a1,@r5 movy.w @r7+r9,y1 ! .word 0xf3e7
movx.w a0,@r4+ movy.w @r6,y0 ! .word 0xf029
movx.w a0,@r4+ movy.w @r6,y1 ! .word 0xf069
movx.w a1,@r4+ movy.w @r6,y0 ! .word 0xf0a9
movx.w a1,@r4+ movy.w @r6,y1 ! .word 0xf0e9
movx.w a0,@r4+ movy.w @r7,y0 ! .word 0xf129
movx.w a0,@r4+ movy.w @r7,y1 ! .word 0xf169
movx.w a1,@r4+ movy.w @r7,y0 ! .word 0xf1a9
movx.w a1,@r4+ movy.w @r7,y1 ! .word 0xf1e9
movx.w a0,@r5+ movy.w @r6,y0 ! .word 0xf229
movx.w a0,@r5+ movy.w @r6,y1 ! .word 0xf269
movx.w a1,@r5+ movy.w @r6,y0 ! .word 0xf2a9
movx.w a1,@r5+ movy.w @r6,y1 ! .word 0xf2e9
movx.w a0,@r5+ movy.w @r7,y0 ! .word 0xf329
movx.w a0,@r5+ movy.w @r7,y1 ! .word 0xf369
movx.w a1,@r5+ movy.w @r7,y0 ! .word 0xf3a9
movx.w a1,@r5+ movy.w @r7,y1 ! .word 0xf3e9
movx.w a0,@r4+ movy.w @r6+,y0 ! .word 0xf02a
movx.w a0,@r4+ movy.w @r6+,y1 ! .word 0xf06a
movx.w a1,@r4+ movy.w @r6+,y0 ! .word 0xf0aa
movx.w a1,@r4+ movy.w @r6+,y1 ! .word 0xf0ea
movx.w a0,@r4+ movy.w @r7+,y0 ! .word 0xf12a
movx.w a0,@r4+ movy.w @r7+,y1 ! .word 0xf16a
movx.w a1,@r4+ movy.w @r7+,y0 ! .word 0xf1aa
movx.w a1,@r4+ movy.w @r7+,y1 ! .word 0xf1ea
movx.w a0,@r5+ movy.w @r6+,y0 ! .word 0xf22a
movx.w a0,@r5+ movy.w @r6+,y1 ! .word 0xf26a
movx.w a1,@r5+ movy.w @r6+,y0 ! .word 0xf2aa
movx.w a1,@r5+ movy.w @r6+,y1 ! .word 0xf2ea
movx.w a0,@r5+ movy.w @r7+,y0 ! .word 0xf32a
movx.w a0,@r5+ movy.w @r7+,y1 ! .word 0xf36a
movx.w a1,@r5+ movy.w @r7+,y0 ! .word 0xf3aa
movx.w a1,@r5+ movy.w @r7+,y1 ! .word 0xf3ea
movx.w a0,@r4+ movy.w @r6+r9,y0 ! .word 0xf02b
movx.w a0,@r4+ movy.w @r6+r9,y1 ! .word 0xf06b
movx.w a1,@r4+ movy.w @r6+r9,y0 ! .word 0xf0ab
movx.w a1,@r4+ movy.w @r6+r9,y1 ! .word 0xf0eb
movx.w a0,@r4+ movy.w @r7+r9,y0 ! .word 0xf12b
movx.w a0,@r4+ movy.w @r7+r9,y1 ! .word 0xf16b
movx.w a1,@r4+ movy.w @r7+r9,y0 ! .word 0xf1ab
movx.w a1,@r4+ movy.w @r7+r9,y1 ! .word 0xf1eb
movx.w a0,@r5+ movy.w @r6+r9,y0 ! .word 0xf22b
movx.w a0,@r5+ movy.w @r6+r9,y1 ! .word 0xf26b
movx.w a1,@r5+ movy.w @r6+r9,y0 ! .word 0xf2ab
movx.w a1,@r5+ movy.w @r6+r9,y1 ! .word 0xf2eb
movx.w a0,@r5+ movy.w @r7+r9,y0 ! .word 0xf32b
movx.w a0,@r5+ movy.w @r7+r9,y1 ! .word 0xf36b
movx.w a1,@r5+ movy.w @r7+r9,y0 ! .word 0xf3ab
movx.w a1,@r5+ movy.w @r7+r9,y1 ! .word 0xf3eb
movx.w a0,@r4+r8 movy.w @r6,y0 ! .word 0xf02d
movx.w a0,@r4+r8 movy.w @r6,y1 ! .word 0xf06d
movx.w a1,@r4+r8 movy.w @r6,y0 ! .word 0xf0ad
movx.w a1,@r4+r8 movy.w @r6,y1 ! .word 0xf0ed
movx.w a0,@r4+r8 movy.w @r7,y0 ! .word 0xf12d
movx.w a0,@r4+r8 movy.w @r7,y1 ! .word 0xf16d
movx.w a1,@r4+r8 movy.w @r7,y0 ! .word 0xf1ad
movx.w a1,@r4+r8 movy.w @r7,y1 ! .word 0xf1ed
movx.w a0,@r5+r8 movy.w @r6,y0 ! .word 0xf22d
movx.w a0,@r5+r8 movy.w @r6,y1 ! .word 0xf26d
movx.w a1,@r5+r8 movy.w @r6,y0 ! .word 0xf2ad
movx.w a1,@r5+r8 movy.w @r6,y1 ! .word 0xf2ed
movx.w a0,@r5+r8 movy.w @r7,y0 ! .word 0xf32d
movx.w a0,@r5+r8 movy.w @r7,y1 ! .word 0xf36d
movx.w a1,@r5+r8 movy.w @r7,y0 ! .word 0xf3ad
movx.w a1,@r5+r8 movy.w @r7,y1 ! .word 0xf3ed
movx.w a0,@r4+r8 movy.w @r6+,y0 ! .word 0xf02e
movx.w a0,@r4+r8 movy.w @r6+,y1 ! .word 0xf06e
movx.w a1,@r4+r8 movy.w @r6+,y0 ! .word 0xf0ae
movx.w a1,@r4+r8 movy.w @r6+,y1 ! .word 0xf0ee
movx.w a0,@r4+r8 movy.w @r7+,y0 ! .word 0xf12e
movx.w a0,@r4+r8 movy.w @r7+,y1 ! .word 0xf16e
movx.w a1,@r4+r8 movy.w @r7+,y0 ! .word 0xf1ae
movx.w a1,@r4+r8 movy.w @r7+,y1 ! .word 0xf1ee
movx.w a0,@r5+r8 movy.w @r6+,y0 ! .word 0xf22e
movx.w a0,@r5+r8 movy.w @r6+,y1 ! .word 0xf26e
movx.w a1,@r5+r8 movy.w @r6+,y0 ! .word 0xf2ae
movx.w a1,@r5+r8 movy.w @r6+,y1 ! .word 0xf2ee
movx.w a0,@r5+r8 movy.w @r7+,y0 ! .word 0xf32e
movx.w a0,@r5+r8 movy.w @r7+,y1 ! .word 0xf36e
movx.w a1,@r5+r8 movy.w @r7+,y0 ! .word 0xf3ae
movx.w a1,@r5+r8 movy.w @r7+,y1 ! .word 0xf3ee
movx.w a0,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf02f
movx.w a0,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf06f
movx.w a1,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf0af
movx.w a1,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf0ef
movx.w a0,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf12f
movx.w a0,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf16f
movx.w a1,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf1af
movx.w a1,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf1ef
movx.w a0,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf22f
movx.w a0,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf26f
movx.w a1,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf2af
movx.w a1,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf2ef
movx.w a0,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf32f
movx.w a0,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf36f
movx.w a1,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf3af
movx.w a1,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf3ef
movxwaxydxy:
movx.w @r4,x0 !
movx.w @r4,y0 !
movx.w @r4,x1 !
movx.w @r4,y1 !
movx.w @r0,x0 !
movx.w @r0,y0 !
movx.w @r0,x1 !
movx.w @r0,y1 !
movx.w @r5,x0 !
movx.w @r5,y0 !
movx.w @r5,x1 !
movx.w @r5,y1 !
movx.w @r1,x0 !
movx.w @r1,y0 !
movx.w @r1,x1 !
movx.w @r1,y1 !
movx.w @r4+,x0 !
movx.w @r4+,y0 !
movx.w @r4+,x1 !
movx.w @r4+,y1 !
movx.w @r0+,x0 !
movx.w @r0+,y0 !
movx.w @r0+,x1 !
movx.w @r0+,y1 !
movx.w @r5+,x0 !
movx.w @r5+,y0 !
movx.w @r5+,x1 !
movx.w @r5+,y1 !
movx.w @r1+,x0 !
movx.w @r1+,y0 !
movx.w @r1+,x1 !
movx.w @r1+,y1 !
movx.w @r4+r8,x0 !
movx.w @r4+r8,y0 !
movx.w @r4+r8,x1 !
movx.w @r4+r8,y1 !
movx.w @r0+r8,x0 !
movx.w @r0+r8,y0 !
movx.w @r0+r8,x1 !
movx.w @r0+r8,y1 !
movx.w @r5+r8,x0 !
movx.w @r5+r8,y0 !
movx.w @r5+r8,x1 !
movx.w @r5+r8,y1 !
movx.w @r1+r8,x0 !
movx.w @r1+r8,y0 !
movx.w @r1+r8,x1 !
movx.w @r1+r8,y1 !
movxwdaxaxy: !
movx.w a0,@r4 !
movx.w x0,@r4 !
movx.w a1,@r4 !
movx.w x1,@r4 !
movx.w a0,@r0 !
movx.w x0,@r0 !
movx.w a1,@r0 !
movx.w x1,@r0 !
movx.w a0,@r5 !
movx.w x0,@r5 !
movx.w a1,@r5 !
movx.w x1,@r5 !
movx.w a0,@r1 !
movx.w x0,@r1 !
movx.w a1,@r1 !
movx.w x1,@r1 !
movx.w a0,@r4+ !
movx.w x0,@r4+ !
movx.w a1,@r4+ !
movx.w x1,@r4+ !
movx.w a0,@r0+ !
movx.w x0,@r0+ !
movx.w a1,@r0+ !
movx.w x1,@r0+ !
movx.w a0,@r5+ !
movx.w x0,@r5+ !
movx.w a1,@r5+ !
movx.w x1,@r5+ !
movx.w a0,@r1+ !
movx.w x0,@r1+ !
movx.w a1,@r1+ !
movx.w x1,@r1+ !
movx.w a0,@r4+r8 !
movx.w x0,@r4+r8 !
movx.w a1,@r4+r8 !
movx.w x1,@r4+r8 !
movx.w a0,@r0+r8 !
movx.w x0,@r0+r8 !
movx.w a1,@r0+r8 !
movx.w x1,@r0+r8 !
movx.w a0,@r5+r8 !
movx.w x0,@r5+r8 !
movx.w a1,@r5+r8 !
movx.w x1,@r5+r8 !
movx.w a0,@r1+r8 !
movx.w x0,@r1+r8 !
movx.w a1,@r1+r8 !
movx.w x1,@r1+r8 !
movywayxdyx: !
movy.w @r6,y0 !
movy.w @r6,y1 !
movy.w @r6,x0 !
movy.w @r6,x1 !
movy.w @r7,y0 !
movy.w @r7,y1 !
movy.w @r7,x0 !
movy.w @r7,x1 !
movy.w @r2,y0 !
movy.w @r2,y1 !
movy.w @r2,x0 !
movy.w @r2,x1 !
movy.w @r3,y0 !
movy.w @r3,y1 !
movy.w @r3,x0 !
movy.w @r3,x1 !
movy.w @r6+,y0 !
movy.w @r6+,y1 !
movy.w @r6+,x0 !
movy.w @r6+,x1 !
movy.w @r7+,y0 !
movy.w @r7+,y1 !
movy.w @r7+,x0 !
movy.w @r7+,x1 !
movy.w @r2+,y0 !
movy.w @r2+,y1 !
movy.w @r2+,x0 !
movy.w @r2+,x1 !
movy.w @r3+,y0 !
movy.w @r3+,y1 !
movy.w @r3+,x0 !
movy.w @r3+,x1 !
movy.w @r6+r9,y0 !
movy.w @r6+r9,y1 !
movy.w @r6+r9,x0 !
movy.w @r6+r9,x1 !
movy.w @r7+r9,y0 !
movy.w @r7+r9,y1 !
movy.w @r7+r9,x0 !
movy.w @r7+r9,x1 !
movy.w @r2+r9,y0 !
movy.w @r2+r9,y1 !
movy.w @r2+r9,x0 !
movy.w @r2+r9,x1 !
movy.w @r3+r9,y0 !
movy.w @r3+r9,y1 !
movy.w @r3+r9,x0 !
movy.w @r3+r9,x1 !
movywdayayx:
movy.w a0,@r6
movy.w a1,@r6
movy.w y0,@r6
movy.w y1,@r6
movy.w a0,@r7
movy.w a1,@r7
movy.w y0,@r7
movy.w y1,@r7
movy.w a0,@r2
movy.w a1,@r2
movy.w y0,@r2
movy.w y1,@r2
movy.w a0,@r3
movy.w a1,@r3
movy.w y0,@r3
movy.w y1,@r3
movy.w a0,@r6+
movy.w a1,@r6+
movy.w y0,@r6+
movy.w y1,@r6+
movy.w a0,@r7+
movy.w a1,@r7+
movy.w y0,@r7+
movy.w y1,@r7+
movy.w a0,@r2+
movy.w a1,@r2+
movy.w y0,@r2+
movy.w y1,@r2+
movy.w a0,@r3+
movy.w a1,@r3+
movy.w y0,@r3+
movy.w y1,@r3+
movy.w a0,@r6+r9
movy.w a1,@r6+r9
movy.w y0,@r6+r9
movy.w y1,@r6+r9
movy.w a0,@r7+r9
movy.w a1,@r7+r9
movy.w y0,@r7+r9
movy.w y1,@r7+r9
movy.w a0,@r2+r9
movy.w a1,@r2+r9
movy.w y0,@r2+r9
movy.w y1,@r2+r9
movy.w a0,@r3+r9
movy.w a1,@r3+r9
movy.w y0,@r3+r9
movy.w y1,@r3+r9
mov r4, r0
mov r4, r1
mov r4, r2
mov r4, r3
mov r4, r5
mov r4, r6
mov r5, r7
movxlaxydxy:
movx.l @r4,x0
movx.l @r4,y0
movx.l @r4,x1
movx.l @r4,y1
movx.l @r0,x0
movx.l @r0,y0
movx.l @r0,x1
movx.l @r0,y1
movx.l @r5,x0
movx.l @r5,y0
movx.l @r5,x1
movx.l @r5,y1
movx.l @r1,x0
movx.l @r1,y0
movx.l @r1,x1
movx.l @r1,y1
movx.l @r4+,x0
movx.l @r4+,y0
movx.l @r4+,x1
movx.l @r4+,y1
movx.l @r0+,x0
movx.l @r0+,y0
movx.l @r0+,x1
movx.l @r0+,y1
movx.l @r5+,x0
movx.l @r5+,y0
movx.l @r5+,x1
movx.l @r5+,y1
movx.l @r1+,x0
movx.l @r1+,y0
movx.l @r1+,x1
movx.l @r1+,y1
movx.l @r4+r8,x0
movx.l @r4+r8,y0
movx.l @r4+r8,x1
movx.l @r4+r8,y1
movx.l @r0+r8,x0
movx.l @r0+r8,y0
movx.l @r0+r8,x1
movx.l @r0+r8,y1
movx.l @r5+r8,x0
movx.l @r5+r8,y0
movx.l @r5+r8,x1
movx.l @r5+r8,y1
movx.l @r1+r8,x0
movx.l @r1+r8,y0
movx.l @r1+r8,x1
movx.l @r1+r8,y1
movxldaxaxy:
movx.l a0,@r4
movx.l x0,@r4
movx.l a1,@r4
movx.l x1,@r4
movx.l a0,@r0
movx.l x0,@r0
movx.l a1,@r0
movx.l x1,@r0
movx.l a0,@r5
movx.l x0,@r5
movx.l a1,@r5
movx.l x1,@r5
movx.l a0,@r1
movx.l x0,@r1
movx.l a1,@r1
movx.l x1,@r1
movx.l a0,@r4+
movx.l x0,@r4+
movx.l a1,@r4+
movx.l x1,@r4+
movx.l a0,@r0+
movx.l x0,@r0+
movx.l a1,@r0+
movx.l x1,@r0+
movx.l a0,@r5+
movx.l x0,@r5+
movx.l a1,@r5+
movx.l x1,@r5+
movx.l a0,@r1+
movx.l x0,@r1+
movx.l a1,@r1+
movx.l x1,@r1+
movx.l a0,@r4+r8
movx.l x0,@r4+r8
movx.l a1,@r4+r8
movx.l x1,@r4+r8
movx.l a0,@r0+r8
movx.l x0,@r0+r8
movx.l a1,@r0+r8
movx.l x1,@r0+r8
movx.l a0,@r5+r8
movx.l x0,@r5+r8
movx.l a1,@r5+r8
movx.l x1,@r5+r8
movx.l a0,@r1+r8
movx.l x0,@r1+r8
movx.l a1,@r1+r8
movx.l x1,@r1+r8
movylayxdyx:
movy.l @r6,y0
movy.l @r6,y1
movy.l @r6,x0
movy.l @r6,x1
movy.l @r7,y0
movy.l @r7,y1
movy.l @r7,x0
movy.l @r7,x1
movy.l @r2,y0
movy.l @r2,y1
movy.l @r2,x0
movy.l @r2,x1
movy.l @r3,y0
movy.l @r3,y1
movy.l @r3,x0
movy.l @r3,x1
movy.l @r6+,y0
movy.l @r6+,y1
movy.l @r6+,x0
movy.l @r6+,x1
movy.l @r7+,y0
movy.l @r7+,y1
movy.l @r7+,x0
movy.l @r7+,x1
movy.l @r2+,y0
movy.l @r2+,y1
movy.l @r2+,x0
movy.l @r2+,x1
movy.l @r3+,y0
movy.l @r3+,y1
movy.l @r3+,x0
movy.l @r3+,x1
movy.l @r6+r9,y0
movy.l @r6+r9,y1
movy.l @r6+r9,x0
movy.l @r6+r9,x1
movy.l @r7+r9,y0
movy.l @r7+r9,y1
movy.l @r7+r9,x0
movy.l @r7+r9,x1
movy.l @r2+r9,y0
movy.l @r2+r9,y1
movy.l @r2+r9,x0
movy.l @r2+r9,x1
movy.l @r3+r9,y0
movy.l @r3+r9,y1
movy.l @r3+r9,x0
movy.l @r3+r9,x1
movyldayayx:
movy.l a0,@r6
movy.l a1,@r6
movy.l y0,@r6
movy.l y1,@r6
movy.l a0,@r7
movy.l a1,@r7
movy.l y0,@r7
movy.l y1,@r7
movy.l a0,@r2
movy.l a1,@r2
movy.l y0,@r2
movy.l y1,@r2
movy.l a0,@r3
movy.l a1,@r3
movy.l y0,@r3
movy.l y1,@r3
movy.l a0,@r6+
movy.l a1,@r6+
movy.l y0,@r6+
movy.l y1,@r6+
movy.l a0,@r7+
movy.l a1,@r7+
movy.l y0,@r7+
movy.l y1,@r7+
movy.l a0,@r2+
movy.l a1,@r2+
movy.l y0,@r2+
movy.l y1,@r2+
movy.l a0,@r3+
movy.l a1,@r3+
movy.l y0,@r3+
movy.l y1,@r3+
movy.l a0,@r6+r9
movy.l a1,@r6+r9
movy.l y0,@r6+r9
movy.l y1,@r6+r9
movy.l a0,@r7+r9
movy.l a1,@r7+r9
movy.l y0,@r7+r9
movy.l y1,@r7+r9
movy.l a0,@r2+r9
movy.l a1,@r2+r9
movy.l y0,@r2+r9
movy.l y1,@r2+r9
movy.l a0,@r3+r9
movy.l a1,@r3+r9
movy.l y0,@r3+r9
movy.l y1,@r3+r9
pass
exit 0
|
stsp/binutils-ia16
| 4,646
|
sim/testsuite/sh/pdmsb.s
|
# sh testcase for pdmsb
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x0, x0
L0: pdmsb x0, x1
# assert_sreg 31<<16, x1
set_sreg 0x1, x0
L1: pdmsb x0, x1
assert_sreg 30<<16, x1
set_sreg 0x3, x0
L2: pdmsb x0, x1
assert_sreg 29<<16, x1
set_sreg 0x7, x0
L3: pdmsb x0, x1
assert_sreg 28<<16, x1
set_sreg 0xf, x0
L4: pdmsb x0, x1
assert_sreg 27<<16, x1
set_sreg 0x1f, x0
L5: pdmsb x0, x1
assert_sreg 26<<16, x1
set_sreg 0x3f, x0
L6: pdmsb x0, x1
assert_sreg 25<<16, x1
set_sreg 0x7f, x0
L7: pdmsb x0, x1
assert_sreg 24<<16, x1
set_sreg 0xff, x0
L8: pdmsb x0, x1
assert_sreg 23<<16, x1
set_sreg 0x1ff, x0
L9: pdmsb x0, x1
assert_sreg 22<<16, x1
set_sreg 0x3ff, x0
L10: pdmsb x0, x1
assert_sreg 21<<16, x1
set_sreg 0x7ff, x0
L11: pdmsb x0, x1
assert_sreg 20<<16, x1
set_sreg 0xfff, x0
L12: pdmsb x0, x1
assert_sreg 19<<16, x1
set_sreg 0x1fff, x0
L13: pdmsb x0, x1
assert_sreg 18<<16, x1
set_sreg 0x3fff, x0
L14: pdmsb x0, x1
assert_sreg 17<<16, x1
set_sreg 0x7fff, x0
L15: pdmsb x0, x1
assert_sreg 16<<16, x1
set_sreg 0xffff, x0
L16: pdmsb x0, x1
assert_sreg 15<<16, x1
set_sreg 0x1ffff, x0
L17: pdmsb x0, x1
assert_sreg 14<<16, x1
set_sreg 0x3ffff, x0
L18: pdmsb x0, x1
assert_sreg 13<<16, x1
set_sreg 0x7ffff, x0
L19: pdmsb x0, x1
assert_sreg 12<<16, x1
set_sreg 0xfffff, x0
L20: pdmsb x0, x1
assert_sreg 11<<16, x1
set_sreg 0x1fffff, x0
L21: pdmsb x0, x1
assert_sreg 10<<16, x1
set_sreg 0x3fffff, x0
L22: pdmsb x0, x1
assert_sreg 9<<16, x1
set_sreg 0x7fffff, x0
L23: pdmsb x0, x1
assert_sreg 8<<16, x1
set_sreg 0xffffff, x0
L24: pdmsb x0, x1
assert_sreg 7<<16, x1
set_sreg 0x1ffffff, x0
L25: pdmsb x0, x1
assert_sreg 6<<16, x1
set_sreg 0x3ffffff, x0
L26: pdmsb x0, x1
assert_sreg 5<<16, x1
set_sreg 0x7ffffff, x0
L27: pdmsb x0, x1
assert_sreg 4<<16, x1
set_sreg 0xfffffff, x0
L28: pdmsb x0, x1
assert_sreg 3<<16, x1
set_sreg 0x1fffffff, x0
L29: pdmsb x0, x1
assert_sreg 2<<16, x1
set_sreg 0x3fffffff, x0
L30: pdmsb x0, x1
assert_sreg 1<<16, x1
set_sreg 0x7fffffff, x0
L31: pdmsb x0, x1
assert_sreg 0<<16, x1
set_sreg 0xffffffff, x0
L32: pdmsb x0, x1
# assert_sreg 31<<16, x1
set_sreg 0xfffffffe, x0
L33: pdmsb x0, x1
assert_sreg 30<<16, x1
set_sreg 0xfffffffc, x0
L34: pdmsb x0, x1
assert_sreg 29<<16, x1
set_sreg 0xfffffff8, x0
L35: pdmsb x0, x1
assert_sreg 28<<16, x1
set_sreg 0xfffffff0, x0
L36: pdmsb x0, x1
assert_sreg 27<<16, x1
set_sreg 0xffffffe0, x0
L37: pdmsb x0, x1
assert_sreg 26<<16, x1
set_sreg 0xffffffc0, x0
L38: pdmsb x0, x1
assert_sreg 25<<16, x1
set_sreg 0xffffff80, x0
L39: pdmsb x0, x1
assert_sreg 24<<16, x1
set_sreg 0xffffff00, x0
L40: pdmsb x0, x1
assert_sreg 23<<16, x1
set_sreg 0xfffffe00, x0
L41: pdmsb x0, x1
assert_sreg 22<<16, x1
set_sreg 0xfffffc00, x0
L42: pdmsb x0, x1
assert_sreg 21<<16, x1
set_sreg 0xfffff800, x0
L43: pdmsb x0, x1
assert_sreg 20<<16, x1
set_sreg 0xfffff000, x0
L44: pdmsb x0, x1
assert_sreg 19<<16, x1
set_sreg 0xffffe000, x0
L45: pdmsb x0, x1
assert_sreg 18<<16, x1
set_sreg 0xffffc000, x0
L46: pdmsb x0, x1
assert_sreg 17<<16, x1
set_sreg 0xffff8000, x0
L47: pdmsb x0, x1
assert_sreg 16<<16, x1
set_sreg 0xffff0000, x0
L48: pdmsb x0, x1
assert_sreg 15<<16, x1
set_sreg 0xfffe0000, x0
L49: pdmsb x0, x1
assert_sreg 14<<16, x1
set_sreg 0xfffc0000, x0
L50: pdmsb x0, x1
assert_sreg 13<<16, x1
set_sreg 0xfff80000, x0
L51: pdmsb x0, x1
assert_sreg 12<<16, x1
set_sreg 0xfff00000, x0
L52: pdmsb x0, x1
assert_sreg 11<<16, x1
set_sreg 0xffe00000, x0
L53: pdmsb x0, x1
assert_sreg 10<<16, x1
set_sreg 0xffc00000, x0
L54: pdmsb x0, x1
assert_sreg 9<<16, x1
set_sreg 0xff800000, x0
L55: pdmsb x0, x1
assert_sreg 8<<16, x1
set_sreg 0xff000000, x0
L56: pdmsb x0, x1
assert_sreg 7<<16, x1
set_sreg 0xfe000000, x0
L57: pdmsb x0, x1
assert_sreg 6<<16, x1
set_sreg 0xfc000000, x0
L58: pdmsb x0, x1
assert_sreg 5<<16, x1
set_sreg 0xf8000000, x0
L59: pdmsb x0, x1
assert_sreg 4<<16, x1
set_sreg 0xf0000000, x0
L60: pdmsb x0, x1
assert_sreg 3<<16, x1
set_sreg 0xe0000000, x0
L61: pdmsb x0, x1
assert_sreg 2<<16, x1
set_sreg 0xc0000000, x0
L62: pdmsb x0, x1
assert_sreg 1<<16, x1
set_sreg 0x80000000, x0
L63: pdmsb x0, x1
assert_sreg 0<<16, x1
set_sreg 0x00000000, x0
L64: pdmsb x0, x1
# assert_sreg 31<<16, x1
test_grs_a5a5
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
stsp/binutils-ia16
| 1,740
|
sim/testsuite/sh/bandornot.s
|
# sh testcase for bandnot, bornot
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bandor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bandnot.b #0, @(3, r1)
bt8k mfail
bornot.b #1, @(3, r1)
bf8k mfail
bandnot.b #2, @(3, r1)
bt8k mfail
bornot.b #3, @(3, r1)
bf8k mfail
bornot.b #4, @(3, r1)
bf8k mfail
bandnot.b #5, @(3, r1)
bt8k mfail
bornot.b #6, @(3, r1)
bf8k mfail
bandnot.b #7, @(3, r1)
bt8k mfail
bandnot.b #0, @(2, r1)
bt8k mfail
bornot.b #1, @(2, r1)
bf8k mfail
bandnot.b #2, @(2, r1)
bt8k mfail
bornot.b #3, @(2, r1)
bf8k mfail
bra .L2
nop
.align 2
x: .long _x
.L2:
bornot.b #4, @(2, r1)
bf8k mfail
bandnot.b #5, @(2, r1)
bt8k mfail
bornot.b #6, @(2, r1)
bf8k mfail
bandnot.b #7, @(2, r1)
bt8k mfail
bandnot.b #0, @(1, r1)
bt8k mfail
bornot.b #1, @(1, r1)
bf8k mfail
bandnot.b #2, @(1, r1)
bt8k mfail
bornot.b #3, @(1, r1)
bf8k mfail
bornot.b #4, @(1, r1)
bf8k mfail
bandnot.b #5, @(1, r1)
bt8k mfail
bornot.b #6, @(1, r1)
bf8k mfail
bandnot.b #7, @(1, r1)
bt8k mfail
bandnot.b #0, @(0, r1)
bt8k mfail
bornot.b #1, @(0, r1)
bf8k mfail
bandnot.b #2, @(0, r1)
bt8k mfail
bornot.b #3, @(0, r1)
bf8k mfail
bornot.b #4, @(0, r1)
bf8k mfail
bandnot.b #5, @(0, r1)
bt8k mfail
bornot.b #6, @(0, r1)
bf8k mfail
bandnot.b #7, @(0, r1)
bt8k mfail
assertreg _x, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 1,318
|
sim/testsuite/sh/shll.s
|
# sh testcase for shll
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shll:
set_grs_a5a5
mov #1, r1
shll r1
assertreg 2, r1
shll r1
assertreg 4, r1
shll r1
assertreg 8, r1
shll r1
assertreg 16, r1
shll r1
assertreg 32, r1
shll r1
assertreg 64, r1
shll r1
assertreg 0x80, r1
shll r1
assertreg 0x100, r1
shll r1
assertreg 0x200, r1
shll r1
assertreg 0x400, r1
shll r1
assertreg 0x800, r1
shll r1
assertreg 0x1000, r1
shll r1
assertreg 0x2000, r1
shll r1
assertreg 0x4000, r1
shll r1
assertreg 0x8000, r1
shll r1
assertreg 0x10000, r1
shll r1
assertreg 0x20000, r1
shll r1
assertreg 0x40000, r1
shll r1
assertreg 0x80000, r1
shll r1
assertreg 0x100000, r1
shll r1
assertreg 0x200000, r1
shll r1
assertreg 0x400000, r1
shll r1
assertreg 0x800000, r1
shll r1
assertreg 0x1000000, r1
shll r1
assertreg 0x2000000, r1
shll r1
assertreg 0x4000000, r1
shll r1
assertreg 0x8000000, r1
shll r1
assertreg 0x10000000, r1
shll r1
assertreg 0x20000000, r1
shll r1
assertreg 0x40000000, r1
shll r1
assertreg 0x80000000, r1
shll r1
assertreg 0, r1
shll r1
assertreg 0, r1
# another:
mov #1, r1
shll r1
shll r1
shll r1
assertreg 8, r1
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
|
stsp/binutils-ia16
| 2,333
|
sim/testsuite/sh/fipr.s
|
# sh testcase for fipr $fvm, $fvn
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
initv0:
set_grs_a5a5
set_fprs_a5a5
# Load 1 into fr0.
fldi1 fr0
# Load 2 into fr1.
fldi1 fr1
fadd fr1, fr1
# Load 4 into fr2.
fldi1 fr2
fadd fr2, fr2
fadd fr2, fr2
# Load 8 into fr3.
fmov fr2, fr3
fadd fr2, fr3
initv8:
fldi1 fr8
fldi0 fr9
fldi1 fr10
fldi0 fr11
fipr fv0, fv8
test1:
# Result will be in fr11.
assert_fpreg_i 1, fr0
assert_fpreg_i 2, fr1
assert_fpreg_i 4, fr2
assert_fpreg_i 8, fr3
assert_fpreg_x 0xa5a5a5a5, fr4
assert_fpreg_x 0xa5a5a5a5, fr5
assert_fpreg_x 0xa5a5a5a5, fr6
assert_fpreg_x 0xa5a5a5a5, fr7
assert_fpreg_i 1, fr8
assert_fpreg_i 0, fr9
assert_fpreg_i 1, fr10
assert_fpreg_i 5, fr11
assert_fpreg_x 0xa5a5a5a5, fr12
assert_fpreg_x 0xa5a5a5a5, fr13
assert_fpreg_x 0xa5a5a5a5, fr14
assert_fpreg_x 0xa5a5a5a5, fr15
test_grs_a5a5
test_infp:
# Test positive infinity
fldi0 fr11
mov.l infp, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be plus infinity
assert_fpreg_x 0x7f800000, fr11
test_infm:
# Test negitive infinity
fldi0 fr11
mov.l infm, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be plus infinity
assert_fpreg_x 0xff800000, fr11
test_qnanp:
# Test positive qnan
fldi0 fr11
mov.l qnanp, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be plus qnan (or greater)
flds fr11, fpul
sts fpul, r1
cmp/ge r0, r1
bt .L0
fail
.L0:
test_snanp:
# Test positive snan
fldi0 fr11
mov.l snanp, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be plus snan (or greater)
flds fr11, fpul
sts fpul, r1
cmp/ge r0, r1
bt .L1
fail
.L1:
.if 0
# Handling of nan and inf not implemented yet.
test_qnanm:
# Test negantive qnan
fldi0 fr11
mov.l qnanm, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be minus qnan (or less)
flds fr11, fpul
sts fpul, r1
cmp/ge r1, r0
bt .L2
fail
.L2:
test_snanm:
# Test negative snan
fldi0 fr11
mov.l snanm, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be minus snan (or less)
flds fr11, fpul
sts fpul, r1
cmp/ge r1, r0
bt .L3
fail
.L3:
.endif
pass
exit 0
.align 2
qnanp: .long 0x7f800001
qnanm: .long 0xff800001
snanp: .long 0x7fc00000
snanm: .long 0xffc00000
infp: .long 0x7f800000
infm: .long 0xff800000
|
stsp/binutils-ia16
| 1,361
|
sim/testsuite/sh/clip.s
|
# sh testcase for clips, clipu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
clips_b:
set_grs_a5a5
clips.b r1
test_gr0_a5a5
assertreg 0xffffff80 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
clipu_b:
set_grs_a5a5
clipu.b r1
test_gr0_a5a5
assertreg 0xff r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
clips_w:
set_grs_a5a5
clips.w r1
test_gr0_a5a5
assertreg 0xffff8000 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
clipu_w:
set_grs_a5a5
clipu.w r1
test_gr0_a5a5
assertreg 0xffff r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
stsp/binutils-ia16
| 3,329
|
sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s
|
//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_sft_2_1/c_ptr2op_pr_sft_2_1.dsp
// Spec Reference: ptr2op preg = preg << 2 (>>2, >> 1)
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0xf0921203;
imm32 p2, 0xbe041305;
imm32 p3, 0xd0d61407;
imm32 p4, 0xa00a1089;
imm32 p5, 0x400a300b;
imm32 sp, 0xe07c180d;
imm32 fp, 0x206e109f;
P1 = P1 << 2;
P2 = P1 >> 2;
P3 = P1 << 2;
P4 = P1 >> 1;
P5 = P1 >> 2;
SP = P1 << 2;
FP = P1 >> 1;
CHECKREG p1, 0xC248480C;
CHECKREG p2, 0x30921203;
CHECKREG p3, 0x09212030;
CHECKREG p4, 0x61242406;
CHECKREG p5, 0x30921203;
CHECKREG sp, 0x09212030;
CHECKREG fp, 0x61242406;
imm32 p1, 0x50021003;
imm32 p2, 0x26041005;
imm32 p3, 0x60761007;
imm32 p4, 0x20081009;
imm32 p5, 0xf00a900b;
imm32 sp, 0xb00c1a0d;
imm32 fp, 0x200e10bf;
P1 = P2;
P2 = P2;
P3 = P2;
P4 = P2;
P5 = P2;
SP = P2;
FP = P2;
CHECKREG p1, 0x26041005;
CHECKREG p2, 0x26041005;
CHECKREG p3, 0x26041005;
CHECKREG p4, 0x26041005;
CHECKREG p5, 0x26041005;
CHECKREG sp, 0x26041005;
CHECKREG fp, 0x26041005;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p3, 0x20061007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 sp, 0x200c100d;
imm32 fp, 0x200e100f;
P1 = P3 << 2;
P2 = P3 >> 1;
P3 = P3 >> 2;
P4 = P3 << 2;
P5 = P3 << 2;
SP = P3 >> 1;
FP = P3 << 2;
CHECKREG p1, 0x8018401C;
CHECKREG p2, 0x10030803;
CHECKREG p3, 0x08018401;
CHECKREG p4, 0x20061004;
CHECKREG p5, 0x20061004;
CHECKREG sp, 0x0400C200;
CHECKREG fp, 0x20061004;
imm32 p1, 0xa0021003;
imm32 p2, 0x2c041005;
imm32 p3, 0x40b61007;
imm32 p4, 0x250d1009;
imm32 p5, 0x260ae00b;
imm32 sp, 0x700c110d;
imm32 fp, 0x900e104f;
P1 = P4 >> 1;
P2 = P4 << 2;
P3 = P4 << 2;
P4 = P4 >> 2;
P5 = P4 << 2;
SP = P4 >> 2;
FP = P4 << 2;
CHECKREG p1, 0x12868804;
CHECKREG p2, 0x94344024;
CHECKREG p3, 0x94344024;
CHECKREG p4, 0x09434402;
CHECKREG p5, 0x250D1008;
CHECKREG sp, 0x0250D100;
CHECKREG fp, 0x250D1008;
imm32 p1, 0x10021003;
imm32 p2, 0x22041005;
imm32 p3, 0x20361007;
imm32 p4, 0x20041009;
imm32 p5, 0x200aa00b;
imm32 sp, 0x200c1b0d;
imm32 fp, 0x200e10cf;
P1 = P5 << 2;
P2 = P5 >> 2;
P3 = P5 << 2;
P4 = P5 << 2;
P5 = P5 >> 1;
SP = P5 >> 2;
FP = P5 << 2;
CHECKREG p1, 0x802A802C;
CHECKREG p2, 0x0802A802;
CHECKREG p3, 0x802A802C;
CHECKREG p4, 0x802A802C;
CHECKREG p5, 0x10055005;
CHECKREG sp, 0x04015401;
CHECKREG fp, 0x40154014;
imm32 p1, 0x50021003;
imm32 p2, 0x62041005;
imm32 p3, 0x70e61007;
imm32 p4, 0x290f1009;
imm32 p5, 0x700ab00b;
imm32 sp, 0x2a0c1d0d;
imm32 fp, 0xb00e1e0f;
P1 = SP << 2;
P2 = SP << 2;
P3 = SP >> 2;
P4 = SP << 2;
P5 = SP >> 2;
SP = SP >> 1;
FP = SP >> 2;
CHECKREG p1, 0xA8307434;
CHECKREG p2, 0xA8307434;
CHECKREG p3, 0x0A830743;
CHECKREG p4, 0xA8307434;
CHECKREG p5, 0x0A830743;
CHECKREG sp, 0x15060E86;
CHECKREG fp, 0x054183A1;
imm32 p1, 0x32002003;
imm32 p2, 0x24004005;
imm32 p3, 0x20506007;
imm32 p4, 0x20068009;
imm32 p5, 0x200ae00b;
imm32 sp, 0x200c1f0d;
imm32 fp, 0x200e10bf;
P1 = FP >> 2;
P2 = FP >> 1;
P3 = FP << 2;
P4 = FP >> 2;
P5 = FP << 2;
SP = FP >> 2;
FP = FP << 2;
CHECKREG p1, 0x0803842F;
CHECKREG p2, 0x1007085F;
CHECKREG p3, 0x803842FC;
CHECKREG p4, 0x0803842F;
CHECKREG p5, 0x803842FC;
CHECKREG sp, 0x0803842F;
CHECKREG fp, 0x803842FC;
pass
|
stsp/binutils-ia16
| 6,520
|
sim/testsuite/bfin/c_dspldst_ld_drlo_ipp.s
|
//Original:/testcases/core/c_dspldst_ld_drlo_ipp/c_dspldst_ld_drlo_ipp.dsp
// Spec Reference: c_dspldst ld_drlo_i++/--
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load Lower half of Dregs
R0.L = W [ I0 ++ ];
R1.L = W [ I1 ++ ];
R2.L = W [ I2 ++ ];
R3.L = W [ I3 ++ ];
R4.L = W [ I0 ++ ];
R5.L = W [ I1 ++ ];
R6.L = W [ I2 ++ ];
R7.L = W [ I3 ++ ];
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
CHECKREG r3, 0x00006263;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00002021;
CHECKREG r6, 0x00004041;
CHECKREG r7, 0x00006061;
R1.L = W [ I0 ++ ];
R2.L = W [ I1 ++ ];
R3.L = W [ I2 ++ ];
R4.L = W [ I3 ++ ];
R5.L = W [ I0 ++ ];
R6.L = W [ I1 ++ ];
R7.L = W [ I2 ++ ];
R0.L = W [ I3 ++ ];
CHECKREG r0, 0x00006465;
CHECKREG r1, 0x00000607;
CHECKREG r2, 0x00002627;
CHECKREG r3, 0x00004647;
CHECKREG r4, 0x00006667;
CHECKREG r5, 0x00000405;
CHECKREG r6, 0x00002425;
CHECKREG r7, 0x00004445;
R2.L = W [ I0 ++ ];
R3.L = W [ I1 ++ ];
R4.L = W [ I2 ++ ];
R5.L = W [ I3 ++ ];
R6.L = W [ I0 ++ ];
R7.L = W [ I1 ++ ];
R0.L = W [ I2 ++ ];
R1.L = W [ I3 ++ ];
CHECKREG r0, 0x00004849;
CHECKREG r1, 0x00006869;
CHECKREG r2, 0x00000A0B;
CHECKREG r3, 0x00002A2B;
CHECKREG r4, 0x00004A4B;
CHECKREG r5, 0x00006A6B;
CHECKREG r6, 0x00000809;
CHECKREG r7, 0x00002829;
R3.L = W [ I0 ++ ];
R4.L = W [ I1 ++ ];
R5.L = W [ I2 ++ ];
R6.L = W [ I3 ++ ];
R7.L = W [ I0 ++ ];
R0.L = W [ I1 ++ ];
R1.L = W [ I2 ++ ];
R2.L = W [ I3 ++ ];
CHECKREG r0, 0x00002C2D;
CHECKREG r1, 0x00004C4D;
CHECKREG r2, 0x00006C6D;
CHECKREG r3, 0x00000E0F;
CHECKREG r4, 0x00002E2F;
CHECKREG r5, 0x00004E4F;
CHECKREG r6, 0x00006E6F;
CHECKREG r7, 0x00000C0D;
// reverse to minus mninus i--
// Load Lower half of Dregs
R0.L = W [ I0 -- ];
R1.L = W [ I1 -- ];
R2.L = W [ I2 -- ];
R3.L = W [ I3 -- ];
R4.L = W [ I0 -- ];
R5.L = W [ I1 -- ];
R6.L = W [ I2 -- ];
R7.L = W [ I3 -- ];
CHECKREG r0, 0x00001213;
CHECKREG r1, 0x00003233;
CHECKREG r2, 0x00005253;
CHECKREG r3, 0x00007273;
CHECKREG r4, 0x00000C0D;
CHECKREG r5, 0x00002C2D;
CHECKREG r6, 0x00004C4D;
CHECKREG r7, 0x00006C6D;
R1.L = W [ I0 -- ];
R2.L = W [ I1 -- ];
R3.L = W [ I2 -- ];
R4.L = W [ I3 -- ];
R5.L = W [ I0 -- ];
R6.L = W [ I1 -- ];
R7.L = W [ I2 -- ];
R0.L = W [ I3 -- ];
CHECKREG r0, 0x00006869;
CHECKREG r1, 0x00000E0F;
CHECKREG r2, 0x00002E2F;
CHECKREG r3, 0x00004E4F;
CHECKREG r4, 0x00006E6F;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00002829;
CHECKREG r7, 0x00004849;
R2.L = W [ I0 -- ];
R3.L = W [ I1 -- ];
R4.L = W [ I2 -- ];
R5.L = W [ I3 -- ];
R6.L = W [ I0 -- ];
R7.L = W [ I1 -- ];
R0.L = W [ I2 -- ];
R1.L = W [ I3 -- ];
CHECKREG r0, 0x00004445;
CHECKREG r1, 0x00006465;
CHECKREG r2, 0x00000A0B;
CHECKREG r3, 0x00002A2B;
CHECKREG r4, 0x00004A4B;
CHECKREG r5, 0x00006A6B;
CHECKREG r6, 0x00000405;
CHECKREG r7, 0x00002425;
R3.L = W [ I0 -- ];
R4.L = W [ I1 -- ];
R5.L = W [ I2 -- ];
R6.L = W [ I3 -- ];
R7.L = W [ I0 -- ];
R0.L = W [ I1 -- ];
R1.L = W [ I2 -- ];
R2.L = W [ I3 -- ];
CHECKREG r0, 0x00002021;
CHECKREG r1, 0x00004041;
CHECKREG r2, 0x00006061;
CHECKREG r3, 0x00000607;
CHECKREG r4, 0x00002627;
CHECKREG r5, 0x00004647;
CHECKREG r6, 0x00006667;
CHECKREG r7, 0x00000001;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xBC0DBE26
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 5,720
|
sim/testsuite/bfin/c_mmr_timer.S
|
//Original:/proj/frio/dv/testcases/core/c_mmr_timer/c_mmr_timer.dsp
// Spec Reference: mmr timer
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we set the processor operating modes, initialize registers
// etc.)
//
BOOT:
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP; // and frame pointer
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// TCNTL: 4 bits, rw=1 = 0xFFE03000
LD32(p0, 0xFFE03000);
LD32(r0, 0x0000000D);
[ P0 ] = R0;
CSYNC; // without this it read out zero
R1 = [ P0 ];
// TPERIOD: 32 bits, rw=1 = 0xFFE03004
LD32(p0, 0xFFE03004);
LD32(r0, 0x11112222);
[ P0 ] = R0;
CSYNC; // without this it read out zero
R2 = [ P0 ];
// TSCALE: 8 bits, rw=1 = 0xFFE03008
LD32(p0, 0xFFE03008);
LD32(r0, 0x00000050);
[ P0 ] = R0;
CSYNC; // without this it read out zero
R3 = [ P0 ];
// TCOUNT: 32 bits, rw=1 = 0xFFE0300C
LD32(p0, 0xFFE0300C);
LD32(r0, 0x00000100);
[ P0 ] = R0;
CSYNC; // without this it read out zero
R4 = [ P0 ];
CHECKREG(r1, 0x0000000D);
CHECKREG(r2, 0x11112222);
CHECKREG(r3, 0x00000050);
CHECKREG(r4, 0x00000100);
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
//.data 0xFFE03000
//.dd 0x00000000
|
stsp/binutils-ia16
| 6,093
|
sim/testsuite/bfin/c_dsp32mac_pair_a1_u.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_u/c_dsp32mac_pair_a1_u.dsp
// Spec Reference: dsp32mac pair a1 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
imm32 r3, 0x00890007;
imm32 r4, 0xefb89569;
imm32 r5, 0x1235890b;
imm32 r6, 0x000c089d;
imm32 r7, 0x678e0089;
R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (FU);
P1 = A1.w;
R1 = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L (FU);
P2 = A1.w;
R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (FU);
P3 = A1.w;
R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (FU);
P4 = A1.w;
CHECKREG r0, 0x93545ABD;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0xA8945679;
CHECKREG r3, 0x08B4E563;
CHECKREG r4, 0xEFB89569;
CHECKREG r5, 0x0D514922;
CHECKREG r6, 0x000C089D;
CHECKREG r7, 0x5A4E0EEB;
CHECKREG p1, 0x5A4E0EEB;
CHECKREG p2, 0x00025D4F;
CHECKREG p3, 0x08B4E563;
CHECKREG p4, 0x0D514922;
imm32 r0, 0x98464abd;
imm32 r1, 0xa1b5f4c7;
imm32 r2, 0xa1146649;
imm32 r3, 0x00010805;
imm32 r4, 0xefbc1599;
imm32 r5, 0x12350100;
imm32 r6, 0x200c001d;
imm32 r7, 0x628e0001;
R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (FU);
P1 = A1.w;
R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (FU);
P2 = A1.w;
R3 = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H (FU);
P3 = A1.w;
R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (FU);
P4 = A1.w;
CHECKREG r0, 0x98464ABD;
CHECKREG r1, 0x0D7355F0;
CHECKREG r2, 0xA1146649;
CHECKREG r3, 0x0D682BDA;
CHECKREG r4, 0xEFBC1599;
CHECKREG r5, 0x9EEA5F8C;
CHECKREG r6, 0x200C001D;
CHECKREG r7, 0x628E0001;
CHECKREG p1, 0x9EEA5F8C;
CHECKREG p2, 0x00006649;
CHECKREG p3, 0x0D682BDA;
CHECKREG p4, 0x0D7355F0;
imm32 r0, 0x713a459d;
imm32 r1, 0xabd6aec7;
imm32 r2, 0x7a145a79;
imm32 r3, 0x08a100a7;
imm32 r4, 0xef9a156a;
imm32 r5, 0x1225a10b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0a61;
R5 = ( A1 += R7.H * R3.L ), A0 = R7.L * R3.L (FU);
P1 = A1.w;
R7 = ( A1 = R2.H * R4.L ), A0 -= R2.H * R4.L (FU);
P2 = A1.w;
R1 = ( A1 -= R0.H * R5.L ), A0 += R0.H * R5.H (FU);
P3 = A1.w;
R5 = ( A1 += R6.H * R1.L ), A0 += R6.L * R1.H (FU);
P4 = A1.w;
CHECKREG r0, 0x713A459D;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x7A145A79;
CHECKREG r3, 0x08A100A7;
CHECKREG r4, 0xEF9A156A;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x0003401D;
CHECKREG r7, 0x0A363048;
CHECKREG p1, 0x0DB6E392;
CHECKREG p2, 0x0A363048;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x00000000;
imm32 r0, 0x773489bd;
imm32 r1, 0x917cfec7;
imm32 r2, 0xa9177679;
imm32 r3, 0xd0910777;
imm32 r4, 0xedb91579;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d077999;
imm32 r7, 0x677e0709;
R1 = ( A1 += R5.H * R3.H ), A0 -= R5.L * R3.L (FU);
P1 = A1.w;
R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L (FU);
P2 = A1.w;
R5 = ( A1 = R7.H * R0.H ), A0 += R7.H * R0.H (FU);
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (FU);
P4 = A1.w;
CHECKREG r0, 0x773489BD;
CHECKREG r1, 0xAB422005;
CHECKREG r2, 0xA9177679;
CHECKREG r3, 0x711DF4EE;
CHECKREG r4, 0xEDB91579;
CHECKREG r5, 0x30309798;
CHECKREG r6, 0x0D077999;
CHECKREG r7, 0x3C497CA7;
CHECKREG p1, 0xAB422005;
CHECKREG p2, 0x711DF4EE;
CHECKREG p3, 0x30309798;
CHECKREG p4, 0x3C497CA7;
imm32 r0, 0x83547abd;
imm32 r1, 0x88bc8ec7;
imm32 r2, 0xa8895679;
imm32 r3, 0x00080007;
imm32 r4, 0xe6b86569;
imm32 r5, 0x1A35860b;
imm32 r6, 0x000c896d;
imm32 r7, 0x67Be0096;
R7 = ( A1 += R1.L * R0.L ) (FU);
P1 = A1.w;
R1 = ( A1 = R2.H * R3.L ) (FU);
P2 = A1.w;
R3 = ( A1 -= R7.L * R4.H ) (FU);
P3 = A1.w;
R5 = ( A1 += R6.H * R5.H ) (FU);
P4 = A1.w;
CHECKREG r0, 0x83547ABD;
CHECKREG r1, 0x00049BBF;
CHECKREG r2, 0xA8895679;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xE6B86569;
CHECKREG r5, 0x00013A7C;
CHECKREG r6, 0x000C896D;
CHECKREG r7, 0x80BDBB92;
CHECKREG p1, 0x80BDBB92;
CHECKREG p2, 0x00049BBF;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x00013A7C;
imm32 r0, 0x9aa64abd;
imm32 r1, 0xa1baf4c7;
imm32 r2, 0xb114a649;
imm32 r3, 0x0b010005;
imm32 r4, 0xefbcdb69;
imm32 r5, 0x123501bb;
imm32 r6, 0x000c0d1b;
imm32 r7, 0x678e0d01;
R5 = ( A1 += R5.L * R0.H ) (M), A0 = R5.L * R0.L (FU);
P1 = A1.w;
R1 = ( A1 = R1.L * R3.H ) (M), A0 = R1.H * R3.L (FU);
P2 = A1.w;
R3 = ( A1 -= R2.L * R6.H ) (M), A0 += R2.H * R6.H (FU);
P3 = A1.w;
R1 = ( A1 += R4.L * R7.H ) (M), A0 += R4.L * R7.H (FU);
P4 = A1.w;
CHECKREG r0, 0x9AA64ABD;
CHECKREG r1, 0xF0BBA999;
CHECKREG r2, 0xB114A649;
CHECKREG r3, 0xFF88B65B;
CHECKREG r4, 0xEFBCDB69;
CHECKREG r5, 0x010CD7BE;
CHECKREG r6, 0x000C0D1B;
CHECKREG r7, 0x678E0D01;
CHECKREG p1, 0x010CD7BE;
CHECKREG p2, 0xFF8481C7;
CHECKREG p3, 0xFF88B65B;
CHECKREG p4, 0xF0BBA999;
imm32 r0, 0xd136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0xdd010007;
imm32 r4, 0xeddc1569;
imm32 r5, 0x122d010b;
imm32 r6, 0x00e3d01d;
imm32 r7, 0x678e0d61;
R5 = A1 , A0 = R1.L * R0.L (FU);
P1 = A1.w;
R7 = A1 , A0 = R2.H * R3.L (FU);
P2 = A1.w;
R1 = A1 , A0 += R4.H * R5.H (FU);
P3 = A1.w;
R5 = A1 , A0 += R6.L * R7.H (FU);
P4 = A1.w;
CHECKREG r0, 0xD136459D;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0xDD010007;
CHECKREG r4, 0xEDDC1569;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00E3D01D;
CHECKREG r7, 0xFFFFFFFF;
CHECKREG p1, 0xF0BBA999;
CHECKREG p2, 0xF0BBA999;
CHECKREG p3, 0xF0BBA999;
CHECKREG p4, 0xF0BBA999;
imm32 r0, 0x125489bd;
imm32 r1, 0x91b5fec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910507;
imm32 r4, 0x34567859;
imm32 r5, 0xd2359105;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ) (M,FU);
P1 = A1.w;
R3 = ( A1 -= R2.H * R1.H ) (M,FU);
P2 = A1.w;
R5 = ( A1 = R7.H * R0.H ) (M,FU);
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ) (M,FU);
P4 = A1.w;
CHECKREG r0, 0x125489BD;
CHECKREG r1, 0xCB6CC99E;
CHECKREG r2, 0xA9145679;
CHECKREG r3, 0x107E992E;
CHECKREG r4, 0x34567859;
CHECKREG r5, 0x076FB0D8;
CHECKREG r6, 0x0D0C0999;
CHECKREG r7, 0x0A1A82E0;
CHECKREG p1, 0xCB6CC99E;
CHECKREG p2, 0x107E992E;
CHECKREG p3, 0x076FB0D8;
CHECKREG p4, 0x0A1A82E0;
pass
|
stsp/binutils-ia16
| 3,994
|
sim/testsuite/bfin/c_pushpopmultiple_dp.s
|
//Original:/testcases/core/c_pushpopmultiple_dp/c_pushpopmultiple_dp.dsp
// Spec Reference: pushpopmultiple dreg preg single group
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
P1 = 0xa1 (X);
P2 = 0xa2 (X);
P3 = 0xa3 (X);
P4 = 0xa4 (X);
P5 = 0xa5 (X);
[ -- SP ] = ( R7:0 );
[ -- SP ] = ( P5:1 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
P2 = 0xb2 (X);
P3 = 0xb3 (X);
P4 = 0xb4 (X);
P5 = 0xb5 (X);
[ -- SP ] = ( R7:1 );
[ -- SP ] = ( P5:2 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
P3 = 0xc3 (X);
P4 = 0xc4 (X);
P5 = 0xc5 (X);
[ -- SP ] = ( R7:2 );
[ -- SP ] = ( P5:3 );
R3 = 0x34;
R4 = 0x35;
R5 = 0x36;
R6 = 0x37;
R7 = 0x38;
P4 = 0xd4 (X);
P5 = 0xd5 (X);
[ -- SP ] = ( R7:3 );
[ -- SP ] = ( P5:4 );
R4 = 0x45 (X);
R5 = 0x46 (X);
R6 = 0x47 (X);
R7 = 0x48 (X);
P5 = 0xe5 (X);
[ -- SP ] = ( R7:4 );
[ -- SP ] = ( P5:5 );
R5 = 0x56 (X);
R6 = 0x57 (X);
R7 = 0x58 (X);
[ -- SP ] = ( R7:5 );
R6 = 0x67 (X);
R7 = 0x68 (X);
[ -- SP ] = ( R7:6 );
R7 = 0x78 (X);
[ -- SP ] = ( R7:7 );
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
P1 = 0;
P2 = 0;
P3 = 0;
P4 = 0;
P5 = 0;
( R7:7 ) = [ SP ++ ];
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000078;
( R7:6 ) = [ SP ++ ];
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000067;
CHECKREG r7, 0x00000068;
( R7:5 ) = [ SP ++ ];
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000056;
CHECKREG r6, 0x00000057;
CHECKREG r7, 0x00000058;
( P5:5 ) = [ SP ++ ];
( R7:4 ) = [ SP ++ ];
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x00000000;
CHECKREG p5, 0x000000e5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000045;
CHECKREG r5, 0x00000046;
CHECKREG r6, 0x00000047;
CHECKREG r7, 0x00000048;
( P5:4 ) = [ SP ++ ];
( R7:3 ) = [ SP ++ ];
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x000000d4;
CHECKREG p5, 0x000000d5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000035;
CHECKREG r5, 0x00000036;
CHECKREG r6, 0x00000037;
CHECKREG r7, 0x00000038;
( P5:3 ) = [ SP ++ ];
( R7:2 ) = [ SP ++ ];
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x000000c3;
CHECKREG p4, 0x000000c4;
CHECKREG p5, 0x000000c5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0x00000024;
CHECKREG r4, 0x00000025;
CHECKREG r5, 0x00000026;
CHECKREG r6, 0x00000027;
CHECKREG r7, 0x00000028;
( P5:2 ) = [ SP ++ ];
( R7:1 ) = [ SP ++ ];
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x000000b2;
CHECKREG p3, 0x000000b3;
CHECKREG p4, 0x000000b4;
CHECKREG p5, 0x000000b5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x00000013;
CHECKREG r3, 0x00000014;
CHECKREG r4, 0x00000015;
CHECKREG r5, 0x00000016;
CHECKREG r6, 0x00000017;
CHECKREG r7, 0x00000018;
( P5:1 ) = [ SP ++ ];
( R7:0 ) = [ SP ++ ];
CHECKREG p1, 0x000000a1;
CHECKREG p2, 0x000000a2;
CHECKREG p3, 0x000000a3;
CHECKREG p4, 0x000000a4;
CHECKREG p5, 0x000000a5;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000003;
CHECKREG r3, 0x00000004;
CHECKREG r4, 0x00000005;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000007;
CHECKREG r7, 0x00000008;
pass
|
stsp/binutils-ia16
| 5,857
|
sim/testsuite/bfin/c_dsp32alu_rh_rnd20_p.s
|
//Original:/testcases/core/c_dsp32alu_rh_rnd20_p/c_dsp32alu_rh_rnd20_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm32 r7, 0x86667a77;
R0.H = R0 + R0 (RND20);
R1.H = R0 + R1 (RND20);
R2.H = R0 + R2 (RND20);
R3.H = R0 + R3 (RND20);
R4.H = R0 + R4 (RND20);
R5.H = R0 + R5 (RND20);
R6.H = R0 + R6 (RND20);
R7.H = R0 + R7 (RND20);
CHECKREG r0, 0xF4AD8911;
CHECKREG r1, 0x01F3AB1D;
CHECKREG r2, 0x02955515;
CHECKREG r3, 0x03B57717;
CHECKREG r4, 0x04B2891B;
CHECKREG r5, 0x05C4AB1D;
CHECKREG r6, 0x068FA515;
CHECKREG r7, 0xF7B17A77;
imm32 r0, 0xa5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xb4445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5b78891b;
imm32 r5, 0x67bbab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0x86667b77;
R0.H = R1 + R0 (RND20);
R1.H = R1 + R1 (RND20);
R2.H = R1 + R2 (RND20);
R3.H = R1 + R3 (RND20);
R4.H = R1 + R4 (RND20);
R5.H = R1 + R5 (RND20);
R6.H = R1 + R6 (RND20);
R7.H = R1 + R7 (RND20);
CHECKREG r0, 0xFCCF8911;
CHECKREG r1, 0x04F1AB1D;
CHECKREG r2, 0xFB935515;
CHECKREG r3, 0x04B67717;
CHECKREG r4, 0x0607891B;
CHECKREG r5, 0x06CBAB1D;
CHECKREG r6, 0x0793B515;
CHECKREG r7, 0xF8B67B77;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x3a445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x567a891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0.H = R2 + R0 (RND20);
R1.H = R2 + R1 (RND20);
R2.H = R2 + R2 (RND20);
R3.H = R2 + R3 (RND20);
R4.H = R2 + R4 (RND20);
R5.H = R2 + R5 (RND20);
R6.H = R2 + R6 (RND20);
R7.H = R2 + R7 (RND20);
CHECKREG r0, 0xFDFB8911;
CHECKREG r1, 0x064DAB1D;
CHECKREG r2, 0x07495515;
CHECKREG r3, 0x04DF7717;
CHECKREG r4, 0x05DC891B;
CHECKREG r5, 0x06EDAB1D;
CHECKREG r6, 0x07B95A15;
CHECKREG r7, 0xF8DB77A7;
imm32 r0, 0xb5678911;
imm32 r1, 0xb789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678ddb1d;
imm32 r6, 0x74445d15;
imm32 r7, 0x866677d7;
R0.H = R3 + R0 (RND20);
R1.H = R3 + R1 (RND20);
R2.H = R3 + R2 (RND20);
R3.H = R3 + R3 (RND20);
R4.H = R3 + R4 (RND20);
R5.H = R3 + R5 (RND20);
R6.H = R3 + R6 (RND20);
R7.H = R3 + R7 (RND20);
CHECKREG r0, 0xFFC48911;
CHECKREG r1, 0xFFE6AB1D;
CHECKREG r2, 0x08425515;
CHECKREG r3, 0x08DB7717;
CHECKREG r4, 0x05F5891B;
CHECKREG r5, 0x0707DB1D;
CHECKREG r6, 0x07D25D15;
CHECKREG r7, 0xF8F477D7;
imm32 r0, 0xd5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0xd6667717;
imm32 r4, 0x5d78891b;
imm32 r5, 0x67d9ab1d;
imm32 r6, 0x744d5515;
imm32 r7, 0x8666dd77;
R0.H = R4 + R0 (RND20);
R1.H = R4 + R1 (RND20);
R2.H = R4 + R2 (RND20);
R3.H = R4 + R3 (RND20);
R4.H = R4 + R4 (RND20);
R5.H = R4 + R5 (RND20);
R6.H = R4 + R6 (RND20);
R7.H = R4 + R7 (RND20);
CHECKREG r0, 0x032E8911;
CHECKREG r1, 0x0850AB1D;
CHECKREG r2, 0x031C5515;
CHECKREG r3, 0x033E7717;
CHECKREG r4, 0x0BAF891B;
CHECKREG r5, 0x0739AB1D;
CHECKREG r6, 0x08005515;
CHECKREG r7, 0xF921DD77;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34d45515;
imm32 r3, 0x46667717;
imm32 r4, 0x567d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445d15;
imm32 r7, 0x866677d7;
R0.H = R5 + R0 (RND20);
R1.H = R5 + R1 (RND20);
R2.H = R5 + R2 (RND20);
R3.H = R5 + R3 (RND20);
R4.H = R5 + R4 (RND20);
R5.H = R5 + R5 (RND20);
R6.H = R5 + R6 (RND20);
R7.H = R5 + R7 (RND20);
CHECKREG r0, 0x04CF8911;
CHECKREG r1, 0x0961AB1D;
CHECKREG r2, 0x09C65515;
CHECKREG r3, 0x0ADF7717;
CHECKREG r4, 0x0BE0891B;
CHECKREG r5, 0x0CF1DB1D;
CHECKREG r6, 0x08135D15;
CHECKREG r7, 0xF93677D7;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x56a8891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm32 r7, 0x86667a77;
R0.H = R6 + R0 (RND20);
R1.H = R6 + R1 (RND20);
R2.H = R6 + R2 (RND20);
R3.H = R6 + R3 (RND20);
R4.H = R6 + R4 (RND20);
R5.H = R6 + R5 (RND20);
R6.H = R6 + R6 (RND20);
R7.H = R6 + R7 (RND20);
CHECKREG r0, 0x019B8911;
CHECKREG r1, 0x09EDAB1D;
CHECKREG r2, 0x0A8F5515;
CHECKREG r3, 0x0BAF7717;
CHECKREG r4, 0x0CAF891B;
CHECKREG r5, 0x0DBDAB1D;
CHECKREG r6, 0x0E89A515;
CHECKREG r7, 0xF94F7A77;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R7 + R0 (RND20);
R1.H = R7 + R1 (RND20);
R2.H = R7 + R2 (RND20);
R3.H = R7 + R3 (RND20);
R4.H = R7 + R4 (RND20);
R5.H = R7 + R5 (RND20);
R6.H = R7 + R6 (RND20);
R7.H = R7 + R7 (RND20);
CHECKREG r0, 0xF9BD8911;
CHECKREG r1, 0xFADFAB1D;
CHECKREG r2, 0xFBAB5515;
CHECKREG r3, 0xFCCD7717;
CHECKREG r4, 0xFDCE891B;
CHECKREG r5, 0xFEDFAB1D;
CHECKREG r6, 0xFFAB5515;
CHECKREG r7, 0xF0CD7777;
imm32 r0, 0xe5678911;
imm32 r1, 0xe789ab1d;
imm32 r2, 0xe4445515;
imm32 r3, 0x4ee67717;
imm32 r4, 0x567e891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444e515;
imm32 r7, 0x86667e77;
R6.H = R2 + R3 (RND20);
R1.H = R4 + R5 (RND20);
R5.H = R7 + R2 (RND20);
R3.H = R0 + R0 (RND20);
R0.H = R3 + R4 (RND20);
R2.H = R5 + R7 (RND20);
R7.H = R6 + R7 (RND20);
R4.H = R1 + R6 (RND20);
CHECKREG r0, 0x05338911;
CHECKREG r1, 0x0BE1AB1D;
CHECKREG r2, 0xF7D15515;
CHECKREG r3, 0xFCAD7717;
CHECKREG r4, 0x00F1891B;
CHECKREG r5, 0xF6ABAB1D;
CHECKREG r6, 0x0333E515;
CHECKREG r7, 0xF89A7E77;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x86667d77;
R3.H = R4 + R0 (RND20);
R1.H = R6 + R3 (RND20);
R4.H = R3 + R2 (RND20);
R6.H = R7 + R1 (RND20);
R2.H = R5 + R4 (RND20);
R7.H = R2 + R7 (RND20);
R0.H = R1 + R6 (RND20);
R5.H = R0 + R5 (RND20);
CHECKREG r0, 0x00068911;
CHECKREG r1, 0x0780AB1D;
CHECKREG r2, 0x06BA5515;
CHECKREG r3, 0x03BE7717;
CHECKREG r4, 0x0410891B;
CHECKREG r5, 0x0679DB1D;
CHECKREG r6, 0xF8DED515;
CHECKREG r7, 0xF8D27D77;
pass
|
stsp/binutils-ia16
| 6,086
|
sim/testsuite/bfin/c_mmr_ppop_illegal_adr.S
|
//Original:/proj/frio/dv/testcases/core/c_mmr_ppop_illegal_adr/c_mmr_ppop_illegal_adr.dsp
// Spec Reference: mmr ppop illegal address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we set the processor operating modes, initialize registers
// etc.)
//
BOOT:
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP; // and frame pointer
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
LD32(r0, 0206037020);
LD32(r1, 0x10070030);
LD32(r2, 0xe2000043);
LD32(r3, 0x30305050);
LD32(r4, 0x0f040860);
LD32(r5, 0x0a0050d0);
LD32(r6, 0x00000000);
LD32(r7, 0x0f060071);
// LD32(sp, 0xFFE02104);
// [--sp] = (r7-r6);
[ -- SP ] = R7;
[ -- SP ] = R6;
.dd 0xffff
R1 += 2;
CHECKREG(r1, 0x10070034);
CHECKREG(r2, 0xE2000046);
CHECKREG(r3, 0x30305054);
CHECKREG(r4, 0x0f040865);
CHECKREG(r5, 0x0a0050d6);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x0f060079);
R7 = [ SP ++ ];
CHECKREG(r7, 0x00000000);
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
R0 = RETX; // error handler:RETX has the address of the same Illegal instr
R1 += 2;
R2 += 3;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
R7 += 8;
R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr)
RETX = R0;
NOP; NOP; NOP; NOP;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.section MEM_DATA_ADDR_1,"aw"
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 3,544
|
sim/testsuite/bfin/c_dsp32mac_dr_a1_is.s
|
//Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp
// Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0069007;
imm32 r4, 0xefbc4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c800d;
imm32 r7, 0xf78e900f;
R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (ISS2);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (ISS2);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (ISS2);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (ISS2);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x80008679;
CHECKREG r3, 0xE8CA9815;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xE3B4A529;
CHECKREG r6, 0x8000800D;
CHECKREG r7, 0xE4C27FD1;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xC5885679;
imm32 r3, 0xC5880000;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.H = ( A1 = R1.L * R0.L ) (ISS2);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (ISS2);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (ISS2);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (ISS2);
R7 = A1.w;
CHECKREG r0, 0x7FFF8ABD;
CHECKREG r1, 0x008F5EEB;
CHECKREG r2, 0x80005679;
CHECKREG r3, 0xECCF6C33;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xE0C07F1F;
CHECKREG r6, 0x8000A00D;
CHECKREG r7, 0xEDAD6477;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.H = A1 , A0 -= R1.L * R0.L (ISS2);
R1 = A1.w;
R2.H = A1 , A0 += R2.H * R3.L (ISS2);
R3 = A1.w;
R4.H = A1 , A0 -= R4.H * R5.H (ISS2);
R5 = A1.w;
R6.H = A1 , A0 = R6.L * R7.H (ISS2);
R7 = A1.w;
CHECKREG r0, 0x8000BABD;
CHECKREG r1, 0xEDAD6477;
CHECKREG r2, 0x8000E679;
CHECKREG r3, 0xEDAD6477;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xEDAD6477;
CHECKREG r6, 0x8000300D;
CHECKREG r7, 0xEDAD6477;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (ISS2);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (ISS2);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (ISS2);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (ISS2);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x7FFF5679;
CHECKREG r3, 0x303725C1;
CHECKREG r4, 0x7FFF4569;
CHECKREG r5, 0x5D60D8AD;
CHECKREG r6, 0x7FFFA00D;
CHECKREG r7, 0x43823355;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x92005ABD;
imm32 r1, 0x09300000;
imm32 r2, 0x56749679;
imm32 r3, 0x30A95000;
imm32 r4, 0xa0009669;
imm32 r5, 0x01000970;
imm32 r6, 0xdf45609D;
imm32 r7, 0x12345679;
R0.H = ( A1 += R1.L * R0.L ) (M,ISS2);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M,ISS2);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M,ISS2);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M,ISS2);
R7 = A1.w;
CHECKREG r0, 0x7FFF5ABD;
CHECKREG r1, 0x43823355;
CHECKREG r2, 0x7FFF9679;
CHECKREG r3, 0x57912D74;
CHECKREG r4, 0x7FFF9669;
CHECKREG r5, 0x5B1B2D74;
CHECKREG r6, 0x8000609D;
CHECKREG r7, 0xFDAC3404;
pass
|
stsp/binutils-ia16
| 2,920
|
sim/testsuite/bfin/c_loopsetup_nested.s
|
//Original:/testcases/core/c_loopsetup_nested/c_loopsetup_nested.dsp
// Spec Reference: loopsetup nested inside
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start1 , end1 ) LC0 = P1;
start1: R0 += 1;
R1 += -2;
LSETUP ( start2 , end2 ) LC1 = P2;
start2: R4 += 4;
end2: R5 += -5;
R3 += 1;
end1: R2 += 3;
R3 += 4;
LSETUP ( start3 , end3 ) LC1 = P3;
start3: R6 += 6;
LSETUP ( start4 , end4 ) LC0 = P4 >> 1;
start4: R0 += 1;
R1 += -2;
end4: R2 += 3;
R3 += 4;
end3: R7 += -7;
R3 += 1;
CHECKREG r0, 0x00000017;
CHECKREG r1, 0xFFFFFFEC;
CHECKREG r2, 0x00000056;
CHECKREG r3, 0x0000004C;
CHECKREG r4, 0x00000070;
CHECKREG r5, 0x00000014;
CHECKREG r6, 0x0000007E;
CHECKREG r7, 0x0000004D;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start5 , end5 ) LC0 = P5;
start5: R4 += 1;
LSETUP ( start6 , end6 ) LC1 = SP >> 1;
start6: R6 += 4;
end6: R7 += -5;
R3 += 6;
end5: R5 += -2;
R3 += 3;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x0000005D;
CHECKREG r4, 0x00000047;
CHECKREG r5, 0x00000042;
CHECKREG r6, 0x000000D0;
CHECKREG r7, 0xFFFFFFE4;
LSETUP ( start7 , end7 ) LC0 = FP;
start7: R4 += 4;
end7: R5 += -5;
R3 += 6;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x0000006B;
CHECKREG r5, 0x00000015;
CHECKREG r6, 0x000000D0;
CHECKREG r7, 0xFFFFFFE4;
P1 = 12;
P2 = 14;
P3 = 16;
P4 = 18;
P5 = 20;
SP = 22;
FP = 24;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start11 , end11 ) LC1 = P1;
start11: R0 += 1;
R1 += -1;
LSETUP ( start15 , end15 ) LC0 = P5;
start15: R4 += 1;
end15: R5 += -1;
R3 += 1;
end11: R2 += 1;
R3 += 1;
LSETUP ( start13 , end13 ) LC1 = P3;
start13: R6 += 1;
LSETUP ( start12 , end12 ) LC0 = P2;
start12: R4 += 1;
end12: R5 += -1;
R3 += 1;
end13: R7 += -1;
R3 += 1;
CHECKREG r0, 0x00000011;
CHECKREG r1, 0x00000004;
CHECKREG r2, 0x0000002C;
CHECKREG r3, 0x0000004E;
CHECKREG r4, 0x00000210;
CHECKREG r5, 0xFFFFFE80;
CHECKREG r6, 0x00000070;
CHECKREG r7, 0x00000060;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start14 , end14 ) LC0 = P4;
start14: R0 += 1;
R1 += -1;
LSETUP ( start16 , end16 ) LC1 = SP;
start16: R6 += 1;
end16: R7 += -1;
R3 += 1;
LSETUP ( start17 , end17 ) LC1 = FP >> 1;
start17: R4 += 1;
end17: R5 += -1;
R3 += 1;
end14: R2 += 1;
R3 += 1;
CHECKREG r0, 0x00000017;
CHECKREG r1, 0xFFFFFFFE;
CHECKREG r2, 0x00000032;
CHECKREG r3, 0x00000055;
CHECKREG r4, 0x00000118;
CHECKREG r5, 0xFFFFFF78;
CHECKREG r6, 0x000001EC;
CHECKREG r7, 0xFFFFFEE4;
pass
|
stsp/binutils-ia16
| 2,875
|
sim/testsuite/bfin/c_dsp32mac_dr_a0_ih.s
|
//Original:/testcases/core/c_dsp32mac_dr_a0_ih/c_dsp32mac_dr_a0_ih.dsp
// Spec Reference: dsp32mac dr a0 ih (integer mutiplication with high word extraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfec7;
imm32 r2, 0xc7fff679;
imm32 r3, 0xd0799007;
imm32 r4, 0xefb79f69;
imm32 r5, 0xcd35700b;
imm32 r6, 0xe00c87fd;
imm32 r7, 0xf78e909f;
A1 = R1.L * R0.L, R0.L = ( A0 -= R1.L * R0.L ) (IH);
R1 = A0.w;
A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IH);
R3 = A0.w;
A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IH);
R5 = A0.w;
A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (IH);
R7 = A0.w;
CHECKREG r0, 0xF354006F;
CHECKREG r1, 0x006EF115;
CHECKREG r2, 0xC7FF187F;
CHECKREG r3, 0x187EE7F9;
CHECKREG r4, 0xEFB71BBA;
CHECKREG r5, 0x1BBA13DC;
CHECKREG r6, 0xE00C1FB0;
CHECKREG r7, 0x1FAF9D32;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0xc5548abd;
imm32 r1, 0x9b5cfec7;
imm32 r2, 0xa9b55679;
imm32 r3, 0xb09b5007;
imm32 r4, 0xcfb9b5c9;
imm32 r5, 0x52359b5c;
imm32 r6, 0xe50c5098;
imm32 r7, 0x675e7509;
R0.L = ( A0 = R1.L * R0.L ) (IH);
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H ) (IH);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.L ) (IH);
R5 = A0.w;
R6.L = ( A0 -= R6.H * R7.H ) (IH);
R7 = A0.w;
CHECKREG r0, 0xC554008F;
CHECKREG r1, 0x008F5EEB;
CHECKREG r2, 0xA9B5E5BE;
CHECKREG r3, 0xE5BDEA2E;
CHECKREG r4, 0xCFB912FB;
CHECKREG r5, 0x12FAA97C;
CHECKREG r6, 0xE50C1DDD;
CHECKREG r7, 0x1DDCBB14;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x4b54babd;
imm32 r1, 0x12346ec7;
imm32 r2, 0xa4bbe679;
imm32 r3, 0x8abdb707;
imm32 r4, 0x9f4b7b69;
imm32 r5, 0xa234877b;
imm32 r6, 0xb00c4887;
imm32 r7, 0xc78ea4b8;
R0.L = ( A0 = R1.L * R0.L ) (IH);
R1 = A0.w;
R2.L = ( A0 -= R2.H * R3.L ) (IH);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.H ) (IH);
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H ) (IH);
R7 = A0.w;
CHECKREG r0, 0x4B54E207;
CHECKREG r1, 0xE2075EEB;
CHECKREG r2, 0xA4BBC803;
CHECKREG r3, 0xC80330CE;
CHECKREG r4, 0x9F4B236F;
CHECKREG r5, 0x236ED13C;
CHECKREG r6, 0xB00C1371;
CHECKREG r7, 0x1370FD1E;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x1a545abd;
imm32 r1, 0x42fcfec7;
imm32 r2, 0xc53f5679;
imm32 r3, 0x9c64f007;
imm32 r4, 0xafc7ec69;
imm32 r5, 0xd23c891b;
imm32 r6, 0xc00cc602;
imm32 r7, 0x678edc7e;
A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IH);
R3 = A0.w;
A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (IH);
R7 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (IH);
R5 = A0.w;
A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IH);
R1 = A0.w;
CHECKREG r0, 0x1A54EEED;
CHECKREG r1, 0xEEED15DF;
CHECKREG r2, 0xC53F1302;
CHECKREG r3, 0x13020C09;
CHECKREG r4, 0xAFC7EEE5;
CHECKREG r5, 0xEEE57293;
CHECKREG r6, 0xC00CFD3D;
CHECKREG r7, 0xFD3CE337;
pass
|
stsp/binutils-ia16
| 5,429
|
sim/testsuite/bfin/c_dsp32alu_rmm.s
|
//Original:/testcases/core/c_dsp32alu_rmm/c_dsp32alu_rmm.dsp
// Spec Reference: dsp32alu dreg = -/- ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = R0 -|- R0;
R1 = R0 -|- R1;
R2 = R0 -|- R2;
R3 = R0 -|- R3;
R4 = R0 -|- R4;
R5 = R0 -|- R5;
R6 = R0 -|- R6;
R7 = R0 -|- R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xD87754E3;
CHECKREG r2, 0xCBBCAAEB;
CHECKREG r3, 0xB99A88E9;
CHECKREG r4, 0xAA9976E5;
CHECKREG r5, 0x987754E3;
CHECKREG r6, 0x8BBCAAEB;
CHECKREG r7, 0x799A8889;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = R1 -|- R0;
R1 = R1 -|- R1;
R2 = R1 -|- R2;
R3 = R1 -|- R3;
R4 = R1 -|- R4;
R5 = R1 -|- R5;
R6 = R1 -|- R6;
R7 = R1 -|- R7;
CHECKREG r0, 0x12222202;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x4BBCAADB;
CHECKREG r3, 0x399A88D9;
CHECKREG r4, 0x277866D7;
CHECKREG r5, 0x155644D5;
CHECKREG r6, 0x033422D3;
CHECKREG r7, 0xF1120001;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = R2 -|- R0;
R1 = R2 -|- R1;
R2 = R2 -|- R2;
R3 = R2 -|- R3;
R4 = R2 -|- R4;
R5 = R2 -|- R5;
R6 = R2 -|- R6;
R7 = R2 -|- R7;
CHECKREG r0, 0x01DDCBAA;
CHECKREG r1, 0xE0BBA988;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x9B9A8889;
CHECKREG r4, 0xBA997655;
CHECKREG r5, 0x99775433;
CHECKREG r6, 0xB8BCAAAB;
CHECKREG r7, 0x979A8889;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
R0 = R3 -|- R0;
R1 = R3 -|- R1;
R2 = R3 -|- R2;
R3 = R3 -|- R3;
R4 = R3 -|- R4;
R5 = R3 -|- R5;
R6 = R3 -|- R6;
R7 = R3 -|- R7;
CHECKREG r0, 0x30FFEDFC;
CHECKREG r1, 0x1EDDCBFA;
CHECKREG r2, 0x12222202;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x456789AB;
CHECKREG r5, 0x6689ABCD;
CHECKREG r6, 0x47445555;
CHECKREG r7, 0x68667777;
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0 = R4 -|- R0;
R1 = R4 -|- R1;
R2 = R4 -|- R2;
R3 = R4 -|- R3;
R4 = R4 -|- R4;
R5 = R4 -|- R5;
R6 = R4 -|- R6;
R7 = R4 -|- R7;
CHECKREG r0, 0x43410C4A;
CHECKREG r1, 0x211FEA38;
CHECKREG r2, 0x44234030;
CHECKREG r3, 0x22123E1E;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x557644A5;
CHECKREG r6, 0x3364227B;
CHECKREG r7, 0x11520061;
imm32 r0, 0x456b89ab;
imm32 r1, 0x69764bcd;
imm32 r2, 0x49736564;
imm32 r3, 0x61278394;
imm32 r4, 0x98876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x12346fff;
R0 = R5 -|- R0;
R1 = R5 -|- R1;
R2 = R5 -|- R2;
R3 = R5 -|- R3;
R4 = R5 -|- R4;
R5 = R5 -|- R5;
R6 = R5 -|- R6;
R7 = R5 -|- R7;
CHECKREG r0, 0x653F8210;
CHECKREG r1, 0x4134BFEE;
CHECKREG r2, 0x6137A657;
CHECKREG r3, 0x49838827;
CHECKREG r4, 0x1223A782;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x3334E223;
CHECKREG r7, 0xEDCC9001;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R0 = R6 -|- R0;
R1 = R6 -|- R1;
R2 = R6 -|- R2;
R3 = R6 -|- R3;
R4 = R6 -|- R4;
R5 = R6 -|- R5;
R6 = R6 -|- R6;
R7 = R6 -|- R7;
CHECKREG r0, 0xBECB572B;
CHECKREG r1, 0x9CC94509;
CHECKREG r2, 0x00ED2981;
CHECKREG r3, 0x9DCC295F;
CHECKREG r4, 0xF1FE3A3D;
CHECKREG r5, 0xBECB056B;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xEDCCA981;
imm32 r0, 0x476789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x23456755;
imm32 r3, 0x56789007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R0 = R7 -|- R0;
R1 = R7 -|- R1;
R2 = R7 -|- R2;
R3 = R7 -|- R3;
R4 = R7 -|- R4;
R5 = R7 -|- R5;
R6 = R7 -|- R6;
R7 = R7 -|- R7;
CHECKREG r0, 0x6466A64C;
CHECKREG r1, 0x4454842A;
CHECKREG r2, 0x8888C8A2;
CHECKREG r3, 0x55559FF0;
CHECKREG r4, 0x3333785E;
CHECKREG r5, 0x0123243C;
CHECKREG r6, 0x2222127A;
CHECKREG r7, 0x00000000;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R4 = R4 -|- R7 (S);
R5 = R5 -|- R5 (CO);
R2 = R6 -|- R3 (SCO);
R6 = R0 -|- R4 (S);
R0 = R1 -|- R6 (S);
R2 = R2 -|- R1 (CO);
R1 = R3 -|- R0 (CO);
R7 = R7 -|- R4 (SCO);
CHECKREG r0, 0x2202123C;
CHECKREG r1, 0x553B4464;
CHECKREG r2, 0x51FF1897;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x0000001A;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x45673991;
CHECKREG r7, 0x56651234;
imm32 r0, 0x476789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x23456755;
imm32 r3, 0x56789007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R3 = R4 -|- R0 (S);
R5 = R5 -|- R1 (SCO);
R2 = R2 -|- R2 (S);
R7 = R7 -|- R3 (CO);
R4 = R3 -|- R4 (CO);
R0 = R1 -|- R5 (S);
R1 = R0 -|- R6 (SCO);
R6 = R6 -|- R7 (SCO);
CHECKREG r0, 0x078B2BCD;
CHECKREG r1, 0x0E507DE0;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x31332DEE;
CHECKREG r4, 0x7655B899;
CHECKREG r5, 0x5FEE8000;
CHECKREG r6, 0xA2E387A2;
CHECKREG r7, 0x02097A9A;
pass
|
stsp/binutils-ia16
| 4,478
|
sim/testsuite/bfin/c_dsp32shift_signbits_r.s
|
//Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp
// Spec Reference: dsp32shift signbits dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x88880000;
imm32 r1, 0x34560001;
imm32 r2, 0x08000002;
imm32 r3, 0x08000003;
imm32 r4, 0x08000004;
imm32 r5, 0x08000005;
imm32 r6, 0x08000006;
imm32 r7, 0x08000007;
R7.L = SIGNBITS R0;
R1.L = SIGNBITS R0;
R2.L = SIGNBITS R0;
R3.L = SIGNBITS R0;
R4.L = SIGNBITS R0;
R5.L = SIGNBITS R0;
R6.L = SIGNBITS R0;
R0.L = SIGNBITS R0;
CHECKREG r0, 0x88880000;
CHECKREG r1, 0x34560000;
CHECKREG r2, 0x08000000;
CHECKREG r3, 0x08000000;
CHECKREG r4, 0x08000000;
CHECKREG r5, 0x08000000;
CHECKREG r6, 0x08000000;
CHECKREG r7, 0x08000000;
imm32 r0, 0x9999001E;
imm32 r1, 0x0000001E;
imm32 r2, 0x0000001E;
imm32 r3, 0x0000001E;
imm32 r4, 0x0000001E;
imm32 r5, 0x0000001E;
imm32 r6, 0x0000001E;
imm32 r7, 0x0000001E;
R0.L = SIGNBITS R1;
R7.L = SIGNBITS R1;
R2.L = SIGNBITS R1;
R3.L = SIGNBITS R1;
R4.L = SIGNBITS R1;
R5.L = SIGNBITS R1;
R6.L = SIGNBITS R1;
R1.L = SIGNBITS R1;
CHECKREG r0, 0x9999001A;
CHECKREG r1, 0x0000001A;
CHECKREG r2, 0x0000001A;
CHECKREG r3, 0x0000001A;
CHECKREG r4, 0x0000001A;
CHECKREG r5, 0x0000001A;
CHECKREG r6, 0x0000001A;
CHECKREG r7, 0x0000001A;
imm32 r0, 0x0aaae001;
imm32 r1, 0x0000e001;
imm32 r2, 0xaaaa000f;
imm32 r3, 0x0a00e003;
imm32 r4, 0x00a0e004;
imm32 r5, 0x00a0e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0b00e007;
R0.L = SIGNBITS R2;
R1.L = SIGNBITS R2;
R7.L = SIGNBITS R2;
R3.L = SIGNBITS R2;
R4.L = SIGNBITS R2;
R5.L = SIGNBITS R2;
R6.L = SIGNBITS R2;
R2.L = SIGNBITS R2;
CHECKREG r0, 0x0AAA0000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xAAAA0000;
CHECKREG r3, 0x0A000000;
CHECKREG r4, 0x00A00000;
CHECKREG r5, 0x00A00000;
CHECKREG r6, 0x0A000000;
CHECKREG r7, 0x0B000000;
imm32 r0, 0x0b00f001;
imm32 r1, 0x0a00f001;
imm32 r2, 0x0b00f002;
imm32 r3, 0xbbbb0010;
imm32 r4, 0x0b00f004;
imm32 r5, 0x0b00f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x00b0f007;
R0.L = SIGNBITS R3;
R1.L = SIGNBITS R3;
R2.L = SIGNBITS R3;
R7.L = SIGNBITS R3;
R4.L = SIGNBITS R3;
R5.L = SIGNBITS R3;
R6.L = SIGNBITS R3;
R3.L = SIGNBITS R3;
CHECKREG r0, 0x0B000000;
CHECKREG r1, 0x0A000000;
CHECKREG r2, 0x0B000000;
CHECKREG r3, 0xBBBB0000;
CHECKREG r4, 0x0B000000;
CHECKREG r5, 0x0B000000;
CHECKREG r6, 0x0B000000;
CHECKREG r7, 0x00B00000;
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0xcccc0000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = SIGNBITS R4;
R1.L = SIGNBITS R4;
R2.L = SIGNBITS R4;
R3.L = SIGNBITS R4;
R7.L = SIGNBITS R4;
R5.L = SIGNBITS R4;
R6.L = SIGNBITS R4;
R4.L = SIGNBITS R4;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020001;
CHECKREG r3, 0x00030001;
CHECKREG r4, 0xCCCC0001;
CHECKREG r5, 0x00050001;
CHECKREG r6, 0x00060001;
CHECKREG r7, 0x00070001;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xdddd0000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = SIGNBITS R5;
R1.L = SIGNBITS R5;
R2.L = SIGNBITS R5;
R3.L = SIGNBITS R5;
R4.L = SIGNBITS R5;
R7.L = SIGNBITS R5;
R6.L = SIGNBITS R5;
R5.L = SIGNBITS R5;
CHECKREG r0, 0xA0010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0xA0020001;
CHECKREG r3, 0xA0030001;
CHECKREG r4, 0xA0040001;
CHECKREG r5, 0xDDDD0001;
CHECKREG r6, 0xA0060001;
CHECKREG r7, 0xA0070001;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xeeee0000;
imm32 r7, 0xb0070000;
R0.L = SIGNBITS R6;
R1.L = SIGNBITS R6;
R2.L = SIGNBITS R6;
R3.L = SIGNBITS R6;
R4.L = SIGNBITS R6;
R5.L = SIGNBITS R6;
R7.L = SIGNBITS R6;
R6.L = SIGNBITS R6;
CHECKREG r0, 0xB0010002;
CHECKREG r1, 0xB0010002;
CHECKREG r2, 0xB0020002;
CHECKREG r3, 0xB0030002;
CHECKREG r4, 0xB0040002;
CHECKREG r5, 0xB0050002;
CHECKREG r6, 0xEEEE0002;
CHECKREG r7, 0xB0070002;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xffff0000;
R0.L = SIGNBITS R7;
R1.L = SIGNBITS R7;
R2.L = SIGNBITS R7;
R3.L = SIGNBITS R7;
R4.L = SIGNBITS R7;
R5.L = SIGNBITS R7;
R6.L = SIGNBITS R7;
R7.L = SIGNBITS R7;
CHECKREG r0, 0xD001000F;
CHECKREG r1, 0xD001000F;
CHECKREG r2, 0xD002000F;
CHECKREG r3, 0xD003000F;
CHECKREG r4, 0xD004000F;
CHECKREG r5, 0xD005000F;
CHECKREG r6, 0xD006000F;
CHECKREG r7, 0xFFFF000F;
pass
|
stsp/binutils-ia16
| 7,121
|
sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_j_mv_pop/c_seq_ex1_raise_j_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
RAISE 2; // RTN
JUMP.S LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
RAISE 6; // RTI
JUMP.S LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
RAISE 8; // RTI
JUMP.S LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 1,476
|
sim/testsuite/bfin/hwloop-bits.S
|
# Blackfin testcase for HW Loops and user->super transitions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
.macro check_hwloop_regs lc:req, lt:req, lb:req
R0 = LC0;
CC = R0 == \lc;
IF !CC JUMP fail;
R0 = LT0;
CC = R0 == \lt;
IF !CC JUMP fail;
R0 = LB0;
CC = R0 == \lb;
IF !CC JUMP fail;
R0 = LC1;
CC = R0 == \lc;
IF !CC JUMP fail;
R0 = LT1;
CC = R0 == \lt;
IF !CC JUMP fail;
R0 = LB1;
CC = R0 == \lb;
IF !CC JUMP fail;
.endm
start
imm32 P0, EVT3;
loadsym R0, exception;
[P0] = R0;
imm32 P0, EVT2;
loadsym R0, nmi;
[P0] = R0;
loadsym R0, usermode;
RETI = R0;
# Set the LC/LB/LT up with LSB set
# - Hardware clears LT LSB, but LB remains until we lower
imm32 R6, 0xaaaa5555
R4 = R6;
BITCLR (R4, 0);
imm32 R7, 0xaa55aa55
R5 = R7;
BITCLR (R5, 0);
LC0 = R6;
LT0 = R6;
LB0 = R7;
LC1 = R6;
LT1 = R6;
LB1 = R7;
# Sanity check
check_hwloop_regs R6, R4, R7
RTI;
usermode:
# Make sure LSB has been cleared in LB
check_hwloop_regs R6, R4, R5
# Clear LSB in all LC/LT/LB
LC0 = R4;
LT0 = R4;
LB0 = R5;
LC1 = R4;
LT1 = R4;
LB1 = R5;
# Now move back up to supervisor
EXCPT 4;
exception:
# Make sure LSB is set in LB
check_hwloop_regs R4, R4, R7
# Clear the LSB and move up another supervisor level
LC0 = R4;
LT0 = R4;
LB0 = R5;
LC1 = R4;
LT1 = R4;
LB1 = R5;
RAISE 2;
nmi:
# Make sure LSB stayed clear
check_hwloop_regs R4, R4, R5
dbg_pass
fail:
dbg_fail
|
stsp/binutils-ia16
| 1,417
|
sim/testsuite/bfin/m15.s
|
// Test extraction from accumulators:
// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR with SCALE
# mach: bfin
.include "testutils.inc"
start
// load r0=0x0ffffff0
// load r1=0x7ffffff0
// load r2=0x0fffffff
// load r3=0x80100000
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// extract
// 0x000ffffff0 -> 0x1ffffffe0
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R7 = A1, R6 = A0 (S2RND);
DBGA ( R7.L , 0xffe0 );
DBGA ( R7.H , 0x1fff );
DBGA ( R6.L , 0xffe0 );
DBGA ( R6.H , 0x1fff );
// extract (saturate)
// 0x007ffffff0 -> 0x7ffffffff
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R7 = A1, R6 = A0 (S2RND);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0x7fff );
// extract (saturate negative)
// 0xff0ffffff0 -> 0x80000000
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
A1.x = R4.L;
A0.x = R4.L;
R7 = A1, R6 = A0 (S2RND);
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x8000 );
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
// extract int
// 0x000ffffff0 -> 0x1ffffffe0
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R7 = A1, R6 = A0 (ISS2);
DBGA ( R7.L , 0xffe0 );
DBGA ( R7.H , 0x1fff );
DBGA ( R6.L , 0xffe0 );
DBGA ( R6.H , 0x1fff );
pass
.data
data0:
.dw 0xfff0
.dw 0x0fff
.dw 0xfff0
.dw 0x7fff
.dw 0xffff
.dw 0x0fff
.dw 0x0000
.dw 0x8010
.dw 0x00ff
.dw 0x0000
|
stsp/binutils-ia16
| 8,907
|
sim/testsuite/bfin/se_cc_kill.S
|
//Original:/proj/frio/dv/testcases/seq/se_cc_kill/se_cc_kill.dsp
// Description:
// Verify CC kill under the following condition:
//
// (1) CC = AZ killed in WB
// (2) CC = AN killed in WB
// (3) CC = AC killed in WB
// (4) CC = AV0 killed in WB
// (5) CC = AV1 killed in WB
// (6) CC = AQ killed in WB
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
// ----------------------------------------------------------------
// Include Files
// ----------------------------------------------------------------
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
// ----------------------------------------------------------------
// Defines
// ----------------------------------------------------------------
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_1 //
#endif
// ----------------------------------------------------------------
// Reset ISR
// - set the processor operating modes
// - initialize registers
// - etc ...
// ----------------------------------------------------------------
RST_ISR:
// Initialize data registers
//INIT_R_REGS(0);
R7 = 0;
R6 = 0;
R5 = 0;
R4 = 0;
R3 = 0;
R2 = 0;
R1 = 0;
R0 = 0;
// Initialize pointer registers
INIT_P_REGS(0);
// Initialize address registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the address of the checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Inhibit events during MMR writes
CLI R1;
// Setup user stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup kernel stack
LD32_LABEL(sp, KSTACK);
// Setup frame pointer
FP = SP;
// Setup event vector table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Set the EVT_OVERRIDE MMR
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
// Disable L1 data cache
WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0);
// Mask interrupts (*)
R1 = -1;
// Wait for MMR writes to finish
CSYNC;
// Re-enable events
STI R1;
// Reset loop counters to deterministic values
R0 = 0 (Z);
LT0 = R0;
LB0 = R0;
LC0 = R0;
LT1 = R0;
LB1 = R0;
LC1 = R0;
// Reset other internal regs
ASTAT = R0;
SYSCFG = R0;
RETS = R0;
// Setup the test to run in USER mode
LD32_LABEL(r0, USER_CODE);
RETI = R0;
// Setup the test to run in SUPERVISOR mode
// Comment the following line for a USER mode test
JUMP.S SUPERVISOR_CODE;
RTI;
SUPERVISOR_CODE:
// Load IVG15 general handler (Int15) with MAIN_CODE
LD32_LABEL(p1, MAIN_CODE);
LD32(p0, EVT15);
CLI R1;
[ P0 ] = P1;
CSYNC;
STI R1;
// Take Int15 which branch to MAIN_CODE after RTI
RAISE 15;
RTI;
USER_CODE:
// Setup the stack pointer and the frame pointer
LD32_LABEL(sp, USTACK);
FP = SP;
JUMP.S MAIN_CODE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// ISR Table
// ----------------------------------------------------------------
// ----------------------------------------------------------------
// EMU ISR
// ----------------------------------------------------------------
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// NMI ISR
// ----------------------------------------------------------------
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// EXC ISR
// ----------------------------------------------------------------
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// HWE ISR
// ----------------------------------------------------------------
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// TMR ISR
// ----------------------------------------------------------------
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV7 ISR
// ----------------------------------------------------------------
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV8 ISR
// ----------------------------------------------------------------
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV9 ISR
// ----------------------------------------------------------------
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV10 ISR
// ----------------------------------------------------------------
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV11 ISR
// ----------------------------------------------------------------
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV12 ISR
// ----------------------------------------------------------------
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV13 ISR
// ----------------------------------------------------------------
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV14 ISR
// ----------------------------------------------------------------
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV15 ISR
// ----------------------------------------------------------------
IGV15_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// Main Code
// ----------------------------------------------------------------
MAIN_CODE:
// Enable interrupts in SUPERVISOR mode
// Comment the following line for a USER mode test
[ -- SP ] = RETI;
// Start of the program code
// Verify CC kill under the following condition:
// (1) CC = AZ killed in WB
CC = R2 < R3;
EXCPT 3;
CC = AZ;
// (2) CC = AN killed in WB
CC = R2 == R3;
EXCPT 3;
CC = AN;
// (3) CC = AC killed in WB
CC = R2 < R3;
EXCPT 3;
CC = AC0;
// (4) CC = AV0 killed in WB
CC = R2 == R3;
EXCPT 3;
CC = AV0;
// (5) CC = AV1 killed in WB
CC = R2 == R3;
EXCPT 3;
CC = AV1;
// (6) CC = AQ killed in WB
CC = R2 == R3;
EXCPT 3;
CC = AQ;
END:
dbg_pass;
// ----------------------------------------------------------------
// Data Segment
// - define kernel and user stacks
// ----------------------------------------------------------------
.data
DATA:
.space (STACKSIZE);
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 9,385
|
sim/testsuite/bfin/se_cof.S
|
//Original:/proj/frio/dv/testcases/seq/se_cof/se_cof.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
NOP;
//lz(p0) = 0x0004;
//h(p0) = 0xffe0;
LD32(p0, DMEM_CONTROL);
CSYNC;
R0 = [ P0 ]; // MMR load will Stall
JUMP.S lab1; // Branch in EX1
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
lab1:
[ -- SP ] = ( R7:3 );
IF !CC JUMP 2; // Mispredicted branch;
NOP;
JUMP.S lab2; // Branch in EX1
NOP;
NOP;
NOP;
NOP;
lab2:
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_3 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 2,651
|
sim/testsuite/bfin/c_ccflag_a0a1.S
|
//Original:/testcases/core/c_ccflag_a0a1/c_ccflag_a0a1.dsp
// Spec Reference: ccflag a0-a1 (==, <, <=)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x12345778;
imm32 r1, 0x12345678;
imm32 r2, 0x056789ab;
imm32 r3, 0x80231345;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, _UNSET;
ASTAT = R7;
R4 = ASTAT;
A0 = R0;
A1 = R0;
// positive a0 EQUAL to a1
CC = A0 == A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ);
CHECKREG r6, (_AC0|_AC0_COPY|_AZ);
CC = A0 <= A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CC = A0 <= A1;
R7 = ASTAT;
CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ);
CHECKREG r6, (_AC0|_AC0_COPY|_AZ);
CHECKREG r7, (_AC0|_CC|_AC0_COPY|_AZ);
// positive a0 GREATER than to positive a1
A1 = R1;
CC = A0 == A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CC = A0 <= A1;
R7 = ASTAT;
CHECKREG r5, (_AC0|_AC0_COPY); // carry
CHECKREG r6, (_AC0|_AC0_COPY);
CHECKREG r7, (_AC0|_AC0_COPY);
// positive a0 LESS than to positive a1
A1 = R2;
CC = A0 == A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CC = A0 <= A1;
R7 = ASTAT;
CHECKREG r5, (_AC0|_AC0_COPY);
CHECKREG r6, (_AC0|_AC0_COPY);
CHECKREG r7, (_AC0|_AC0_COPY);
// positive a0 GREATER than to neg a1
A1 = R3;
CC = A0 == A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CC = A0 <= A1;
R7 = ASTAT;
CHECKREG r5, _UNSET;
CHECKREG r6, _UNSET;
CHECKREG r7, _UNSET;
// negative a0 and positive a1
imm32 r0, -1;
imm32 r1, 2;
imm32 r2, -3;
imm32 r3, -4;
A0 = R0;
A1 = R1;
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
CC = A0 == A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CC = A0 <= A1;
R7 = ASTAT;
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0|_AC0_COPY|_AN);
CHECKREG r6, (_AC0|_AC0_COPY|_CC|_AN);
CHECKREG r7, (_AC0|_AC0_COPY|_CC|_AN);
// negative a0 LESS than neg a1
A0 = R3;
A1 = R4;
CC = A0 == A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CC = A0 <= A1;
R7 = ASTAT;
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0|_AC0_COPY|_AN);
CHECKREG r6, (_AC0|_AC0_COPY|_CC|_AN);
CHECKREG r7, (_AC0|_AC0_COPY|_CC|_AN);
// negative a0 GREATER neg a1
A0 = R0;
A1 = R3;
CC = A0 == A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CC = A0 <= A1;
R7 = ASTAT;
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0|_AC0_COPY);
CHECKREG r6, (_AC0|_AC0_COPY);
CHECKREG r7, (_AC0|_AC0_COPY);
// negative a0 EQUAL neg imm3
A0 = R3;
A1 = R3;
CC = A0 == A1;
R5 = ASTAT;
CC = A0 < A1;
R6 = ASTAT;
CC = A0 <= A1;
R7 = ASTAT;
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0|_CC|_AC0_COPY|_AZ);
CHECKREG r6, (_AC0|_AC0_COPY|_AZ);
CHECKREG r7, (_AC0|_CC|_AC0_COPY|_AZ);
pass
|
stsp/binutils-ia16
| 17,730
|
sim/testsuite/bfin/se_loop_kill_dcr_01.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr_01/se_loop_kill_dcr_01.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x1 (Z);
P1 = 0x2 (Z);
P2 = 0x3 (Z);
P3 = 0x4 (Z);
P4 = 0x5 (Z);
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (with Kill WB)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in WB
LSETUP ( L0T , L0T ) LC0 = P0;
EXCPT 0x5;
L0T:R0 += 5;
// Kill Valid Dcr in EX3
LSETUP ( L1T , L1B ) LC0 = P0;
EXCPT 0x5;
L1T:R0 += 5;
L1B:R1 += 4;
// Kill Valid Dcr in EX2
LSETUP ( L2T , L2B ) LC0 = P0;
EXCPT 0x5;
L2T:R0 += 5;
R1 += 4;
L2B:R2 += 3;
// Kill Valid Dcr in EX1
LSETUP ( L3T , L3B ) LC0 = P0;
EXCPT 0x5;
L3T:R0 += 5;
R1 += 4;
R2 += 3;
L3B:R3 += 2;
// Kill Valid Dcr in AC
LSETUP ( L4T , L4B ) LC0 = P0;
EXCPT 0x5;
L4T:R0 += 5;
R1 += 4;
R2 += 3;
R3 += 2;
L4B:R4 += 1;
// Kill Valid Dcr in WB, EX3
LSETUP ( L5T , L5T ) LC0 = P1;
EXCPT 0x5;
L5T:R1 += 5;
// Kill Valid Dcr in EX3, EX2
LSETUP ( L6T , L6T ) LC0 = P1;
EXCPT 0x5;
NOP;
L6T:R2 += 5;
// Kill Valid Dcr in EX2, EX1
LSETUP ( L7T , L7T ) LC0 = P1;
EXCPT 0x5;
NOP;
NOP;
L7T:R3 += 5;
// Kill Valid Dcr in EX1, AC
LSETUP ( L8T , L8T ) LC0 = P1;
EXCPT 0x5;
NOP;
NOP;
NOP;
L8T:R4 += 5;
// Kill Valid Dcr in WB, EX3, EX2
LSETUP ( L9T , L9T ) LC0 = P2;
EXCPT 0x5;
L9T:R5 += 5;
// Kill Valid Dcr in EX3, EX2, EX1
LSETUP ( LAT , LAT ) LC0 = P2;
EXCPT 0x5;
NOP;
LAT:
R6 += 6;
// Kill Valid Dcr in EX2, EX1, AC
LSETUP ( LBT , LBT ) LC0 = P2;
EXCPT 0x5;
NOP;
NOP;
LBT:
R5 += 5;
// Kill Valid Dcr in WB, EX3, EX2, EX1
LSETUP ( LCT , LCT ) LC0 = P3;
EXCPT 0x5;
LCT:
R7 += 7;
// Kill Valid Dcr in EX3, EX2, EX1, AC
LSETUP ( LDT , LDT ) LC0 = P3;
EXCPT 0x5;
NOP;
LDT:
R0 += 7;
// Kill Valid Dcr in WB, EX3, EX2, EX1, AC
LSETUP ( LET , LET ) LC0 = P4;
EXCPT 0x5;
LET:
R1 += 1;
// Kill Valid Dcr in WB, EX2
LSETUP ( LFT , LFB ) LC0 = P1;
LFT:
EXCPT 0x5;
LFB:
R1 += 2;
// Kill Valid Dcr in WB, EX1
LSETUP ( LGT , LGB ) LC0 = P1;
LGT:
R2 += 3;
EXCPT 0x5;
LGB:
R1 += 2;
// Kill Valid Dcr in WB, AC
LSETUP ( LHT , LHB ) LC0 = P1;
LHT:
R2 += 3;
R3 += 4;
EXCPT 0x5;
LHB:
R1 += 2;
// Kill Valid Dcr in EX3, EX1
LSETUP ( LIT , LIB ) LC0 = P1;
EXCPT 0x5;
LIT:
R2 += 1;
LIB:
R1 += 2;
// Kill Valid Dcr in EX3, AC
LSETUP ( LJT , LJB ) LC0 = P1;
LJT:
EXCPT 0x5;
R2 += 1;
LJB:
R1 += 2;
// Kill Valid Dcr in EX2, AC
LSETUP ( LKT , LKB ) LC0 = P1;
EXCPT 0x5;
NOP;
LKT:
R2 += 1;
LKB:
R1 += 2;
// Kill Valid Dcr in WB, EX2, AC
LSETUP ( LLT , LLB ) LC0 = P2;
LLT:
EXCPT 0x5;
LLB:
R2 += 2;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (with Kill WB)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in WB
LSETUP ( M0T , M0T ) LC1 = P0;
EXCPT 0x5;
M0T:R0 += 5;
// Kill Valid Dcr in EX3
LSETUP ( M1T , M1B ) LC1 = P0;
EXCPT 0x5;
M1T:R0 += 5;
M1B:R1 += 4;
// Kill Valid Dcr in EX2
LSETUP ( M2T , M2B ) LC1 = P0;
EXCPT 0x5;
M2T:R0 += 5;
R1 += 4;
M2B:R2 += 3;
// Kill Valid Dcr in EX1
LSETUP ( M3T , M3B ) LC1 = P0;
EXCPT 0x5;
M3T:R0 += 5;
R1 += 4;
R2 += 3;
M3B:R3 += 2;
// Kill Valid Dcr in AC
LSETUP ( M4T , M4B ) LC1 = P0;
EXCPT 0x5;
M4T:R0 += 5;
R1 += 4;
R2 += 3;
R3 += 2;
M4B:R4 += 1;
// Kill Valid Dcr in WB, EX3
LSETUP ( M5T , M5T ) LC1 = P1;
EXCPT 0x5;
M5T:R1 += 5;
// Kill Valid Dcr in EX3, EX2
LSETUP ( M6T , M6T ) LC1 = P1;
EXCPT 0x5;
NOP;
M6T:R2 += 5;
// Kill Valid Dcr in EX2, EX1
LSETUP ( M7T , M7T ) LC1 = P1;
EXCPT 0x5;
NOP;
NOP;
M7T:R3 += 5;
// Kill Valid Dcr in EX1, AC
LSETUP ( M8T , M8T ) LC1 = P1;
EXCPT 0x5;
NOP;
NOP;
NOP;
M8T:R4 += 5;
// Kill Valid Dcr in WB, EX3, EX2
LSETUP ( M9T , M9T ) LC1 = P2;
EXCPT 0x5;
M9T:R5 += 5;
// Kill Valid Dcr in EX3, EX2, EX1
LSETUP ( MAT , MAT ) LC1 = P2;
EXCPT 0x5;
NOP;
MAT:
R6 += 6;
// Kill Valid Dcr in EX2, EX1, AC
LSETUP ( MBT , MBT ) LC1 = P2;
EXCPT 0x5;
NOP;
NOP;
MBT:
R5 += 5;
// Kill Valid Dcr in WB, EX3, EX2, EX1
LSETUP ( MCT , MCT ) LC1 = P3;
EXCPT 0x5;
MCT:
R7 += 7;
// Kill Valid Dcr in EX3, EX2, EX1, AC
LSETUP ( MDT , MDT ) LC1 = P3;
EXCPT 0x5;
NOP;
MDT:
R0 += 7;
// Kill Valid Dcr in WB, EX3, EX2, EX1, AC
LSETUP ( MET , MET ) LC1 = P4;
EXCPT 0x5;
MET:
R1 += 1;
// Kill Valid Dcr in WB, EX2
LSETUP ( MFT , MFB ) LC1 = P1;
MFT:
EXCPT 0x5;
MFB:
R1 += 2;
// Kill Valid Dcr in WB, EX1
LSETUP ( MGT , MGB ) LC1 = P1;
MGT:
R2 += 3;
EXCPT 0x5;
MGB:
R1 += 2;
// Kill Valid Dcr in WB, AC
LSETUP ( MHT , MHB ) LC1 = P1;
MHT:
R2 += 3;
R3 += 4;
EXCPT 0x5;
MHB:
R1 += 2;
// Kill Valid Dcr in EX3, EX1
LSETUP ( MIT , MIB ) LC1 = P1;
EXCPT 0x5;
MIT:
R2 += 1;
MIB:
R1 += 2;
// Kill Valid Dcr in EX3, AC
LSETUP ( MJT , MJB ) LC1 = P1;
MJT:
EXCPT 0x5;
R2 += 1;
MJB:
R1 += 2;
// Kill Valid Dcr in EX2, AC
LSETUP ( MKT , MKB ) LC1 = P1;
EXCPT 0x5;
NOP;
MKT:
R2 += 1;
MKB:
R1 += 2;
// Kill Valid Dcr in WB, EX2, AC
LSETUP ( MLT , MLB ) LC1 = P2;
MLT:
EXCPT 0x5;
MLB:
R2 += 2;
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (with Kill EX3)
/////////////////////////////////////////////////////////////////////////////
R0 = 1;
CC = R0;
// Kill %Valid Dcr in EX3
LSETUP ( N1T , N1T ) LC0 = P0;
IF CC JUMP 2;
N1T:R0 += 5;
// Kill Valid Dcr in EX2
LSETUP ( N2T , N2B ) LC0 = P0;
IF CC JUMP 2;
N2T:R0 += 5;
N2B:R2 += 3;
// Kill Valid Dcr in EX1
LSETUP ( N3T , N3B ) LC0 = P0;
IF CC JUMP 2;
N3T:R0 += 5;
R2 += 3;
N3B:R3 += 2;
// Kill Valid Dcr in AC
LSETUP ( N4T , N4B ) LC0 = P0;
IF CC JUMP 2;
N4T:R0 += 5;
R2 += 3;
R3 += 2;
N4B:R4 += 1;
// Kill Valid Dcr in EX3, EX2
LSETUP ( N6T , N6T ) LC0 = P1;
IF CC JUMP 2;
N6T:R2 += 5;
// Kill Valid Dcr in EX2, EX1
LSETUP ( N7T , N7T ) LC0 = P1;
IF CC JUMP 2;
NOP;
N7T:R3 += 5;
// Kill Valid Dcr in EX1, AC
LSETUP ( N8T , N8T ) LC0 = P1;
IF CC JUMP 2;
NOP;
NOP;
N8T:R4 += 5;
// Kill Valid Dcr in EX3, EX2, EX1
LSETUP ( NAT , NAT ) LC0 = P2;
IF CC JUMP 2;
NAT:
R6 += 6;
// Kill Valid Dcr in EX2, EX1, AC
LSETUP ( NBT , NBT ) LC0 = P2;
IF CC JUMP 2;
NOP;
NBT:
R5 += 5;
// Kill Valid Dcr in EX3, EX2, EX1, AC
LSETUP ( NDT , NDT ) LC0 = P3;
IF CC JUMP 2;
NDT:
R0 += 7;
// Kill Valid Dcr in EX3, EX1
LSETUP ( NIT , NIB ) LC0 = P1;
NIT:
IF CC JUMP 2;
NIB:
R1 += 2;
// Kill Valid Dcr in EX3, AC
LSETUP ( NJT , NJB ) LC0 = P1;
NJT:
R2 += 1;
IF CC JUMP 2;
NJB:
R1 += 2;
// Kill Valid Dcr in EX2, AC
LSETUP ( NKT , NKB ) LC0 = P1;
IF CC JUMP 2;
NKT:
R2 += 1;
NKB:
R1 += 2;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (with Kill EX3)
/////////////////////////////////////////////////////////////////////////////
// Kill %Valid Dcr in EX3
LSETUP ( O1T , O1T ) LC1 = P0;
IF CC JUMP 2;
O1T:R0 += 5;
// Kill Valid Dcr in EX2
LSETUP ( O2T , O2B ) LC1 = P0;
IF CC JUMP 2;
O2T:R0 += 5;
O2B:R2 += 3;
// Kill Valid Dcr in EX1
LSETUP ( O3T , O3B ) LC1 = P0;
IF CC JUMP 2;
O3T:R0 += 5;
R2 += 3;
O3B:R3 += 2;
// Kill Valid Dcr in AC
LSETUP ( O4T , O4B ) LC1 = P0;
IF CC JUMP 2;
O4T:R0 += 5;
R2 += 3;
R3 += 2;
O4B:R4 += 1;
// Kill Valid Dcr in EX3, EX2
LSETUP ( O6T , O6T ) LC1 = P1;
IF CC JUMP 2;
O6T:R2 += 5;
// Kill Valid Dcr in EX2, EX1
LSETUP ( O7T , O7T ) LC1 = P1;
IF CC JUMP 2;
NOP;
O7T:R3 += 5;
// Kill Valid Dcr in EX1, AC
LSETUP ( O8T , O8T ) LC1 = P1;
IF CC JUMP 2;
NOP;
NOP;
O8T:R4 += 5;
// Kill Valid Dcr in EX3, EX2, EX1
LSETUP ( OAT , OAT ) LC1 = P2;
IF CC JUMP 2;
OAT:
R6 += 6;
// Kill Valid Dcr in EX2, EX1, AC
LSETUP ( OBT , OBT ) LC1 = P2;
IF CC JUMP 2;
NOP;
OBT:
R5 += 5;
// Kill Valid Dcr in EX3, EX2, EX1, AC
LSETUP ( ODT , ODT ) LC1 = P3;
IF CC JUMP 2;
ODT:
R0 += 7;
// Kill Valid Dcr in EX3, EX1
LSETUP ( OIT , OIB ) LC1 = P1;
OIT:
IF CC JUMP 2;
OIB:
R1 += 2;
// Kill Valid Dcr in EX3, AC
LSETUP ( OJT , OJB ) LC1 = P1;
OJT:
R2 += 1;
IF CC JUMP 2;
OJB:
R1 += 2;
// Kill Valid Dcr in EX2, AC
LSETUP ( OKT , OKB ) LC1 = P1;
IF CC JUMP 2;
OKT:
R2 += 1;
OKB:
R1 += 2;
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (with Kill AC)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in AC
LSETUP ( P4T , P4T ) LC0 = P0;
JUMP.S 2;
P4T:R0 += 5;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (with Kill AC)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in AC
LSETUP ( Q4T , Q4T ) LC1 = P0;
JUMP.S 2;
Q4T:R0 += 5;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 6,378
|
sim/testsuite/bfin/c_interr_disable.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
// CHECK_INIT(p5, 0x00BFFFFC);
// CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
//.code 0x200
START :
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
CLI R1; // stop interrupt
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
WR_MMR(TPERIOD, 0x00000050, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000000, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000050);
// RD_MMR(TCOUNT, p0, r3);
// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
RD_MMR(TPERIOD, p0, r4);
CHECKREG(r4, 0x00000050);
// RD_MMR(TCNTL, p0, r5);
// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TPERIOD, 0x00000015, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000002, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1)
CSYNC;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label4;
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label5: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label6;
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
label4: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
JUMP.S label5;
R5.L = 0x2222; // Will be killed
R5.H = 0x2222; // Will be killed
NOP;
NOP;
NOP;
NOP;
label6: R3.H = 0x7999;
R3.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// With auto reload
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000015);
// RD_MMR(TCNTL , p0, r3);
// CHECKREG(r3, 0x0000000F);
CHECKREG(r7, 0x00000000); // no interrupt being serviced
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
STI R1;
NOP;
CHECKREG(r7, 0x00000001); // interrupt being serviced
// WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
// csync;
NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_DATA_ADDR_1,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
stsp/binutils-ia16
| 10,526
|
sim/testsuite/bfin/c_dsp32shift_ahalf_lp_s.s
|
//Original:/testcases/core/c_dsp32shift_ahalf_lp_s/c_dsp32shift_ahalf_lp_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = ASHIFT R0.L BY R0.L (S);
R1.L = ASHIFT R1.L BY R0.L (S);
R2.L = ASHIFT R2.L BY R0.L (S);
R3.L = ASHIFT R3.L BY R0.L (S);
R4.L = ASHIFT R4.L BY R0.L (S);
R5.L = ASHIFT R5.L BY R0.L (S);
R6.L = ASHIFT R6.L BY R0.L (S);
R7.L = ASHIFT R7.L BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = ASHIFT R0.L BY R1.L (S);
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L (S);
R3.L = ASHIFT R3.L BY R1.L (S);
R4.L = ASHIFT R4.L BY R1.L (S);
R5.L = ASHIFT R5.L BY R1.L (S);
R6.L = ASHIFT R6.L BY R1.L (S);
R7.L = ASHIFT R7.L BY R1.L (S);
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000004;
CHECKREG r3, 0x00000006;
CHECKREG r4, 0x00000008;
CHECKREG r5, 0x0000000a;
CHECKREG r6, 0x0000000c;
CHECKREG r7, 0x0000000e;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000000f;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = ASHIFT R0.L BY R2.L (S);
R1.L = ASHIFT R1.L BY R2.L (S);
//rl2 = ashift (rl2 by rl2) s;
R3.L = ASHIFT R3.L BY R2.L (S);
R4.L = ASHIFT R4.L BY R2.L (S);
R5.L = ASHIFT R5.L BY R2.L (S);
R6.L = ASHIFT R6.L BY R2.L (S);
R7.L = ASHIFT R7.L BY R2.L (S);
CHECKREG r0, 0x00007fff;
CHECKREG r1, 0x00007fff;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x00007fff;
CHECKREG r4, 0x00007fff;
CHECKREG r5, 0x00007fff;
CHECKREG r6, 0x00007fff;
CHECKREG r7, 0x00007fff;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000010;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = ASHIFT R0.L BY R3.L (S);
R1.L = ASHIFT R1.L BY R3.L (S);
R2.L = ASHIFT R2.L BY R3.L (S);
//rl3 = ashift (rl3 by rl3) s;
R4.L = ASHIFT R4.L BY R3.L (S);
R5.L = ASHIFT R5.L BY R3.L (S);
R6.L = ASHIFT R6.L BY R3.L (S);
R7.L = ASHIFT R7.L BY R3.L (S);
CHECKREG r0, 0x00007fff;
CHECKREG r1, 0x00007fff;
CHECKREG r2, 0x00007fff;
//CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00007fff;
CHECKREG r5, 0x00007fff;
CHECKREG r6, 0x00007fff;
CHECKREG r7, 0x00007fff;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R0.L (S);
R1.L = ASHIFT R1.H BY R0.L (S);
R2.L = ASHIFT R2.H BY R0.L (S);
R3.L = ASHIFT R3.H BY R0.L (S);
R4.L = ASHIFT R4.H BY R0.L (S);
R5.L = ASHIFT R5.H BY R0.L (S);
R6.L = ASHIFT R6.H BY R0.L (S);
R7.L = ASHIFT R7.H BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00010000;
imm32 r1, 0x00010001;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R1.L (S);
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L (S);
R3.L = ASHIFT R3.H BY R1.L (S);
R4.L = ASHIFT R4.H BY R1.L (S);
R5.L = ASHIFT R5.H BY R1.L (S);
R6.L = ASHIFT R6.H BY R1.L (S);
R7.L = ASHIFT R7.H BY R1.L (S);
CHECKREG r0, 0x00010002;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020004;
CHECKREG r3, 0x00030006;
CHECKREG r4, 0x00040008;
CHECKREG r5, 0x0005000a;
CHECKREG r6, 0x0006000c;
CHECKREG r7, 0x0007000e;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x0002000f;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R2.L (S);
R1.L = ASHIFT R1.H BY R2.L (S);
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L (S);
R4.L = ASHIFT R4.H BY R2.L (S);
R5.L = ASHIFT R5.H BY R2.L (S);
R6.L = ASHIFT R6.H BY R2.L (S);
R7.L = ASHIFT R7.H BY R2.L (S);
CHECKREG r0, 0x00017fff;
CHECKREG r1, 0x00017fff;
CHECKREG r2, 0x0002000f;
CHECKREG r3, 0x00037fff;
CHECKREG r4, 0x00047fff;
CHECKREG r5, 0x00057fff;
CHECKREG r6, 0x00067fff;
CHECKREG r7, 0x00077fff;
imm32 r0, 0x00010001;
imm32 r1, 0x00010001;
imm32 r2, 0x00020002;
imm32 r3, 0x00030010;
imm32 r4, 0x00040004;
imm32 r5, 0x00050005;
imm32 r6, 0x00060006;
imm32 r7, 0x00070007;
R0.L = ASHIFT R0.H BY R3.L (S);
R1.L = ASHIFT R1.H BY R3.L (S);
R2.L = ASHIFT R2.H BY R3.L (S);
//rl3 = ashift (rh3 by rl3) s;
R4.L = ASHIFT R4.H BY R3.L (S);
R5.L = ASHIFT R5.H BY R3.L (S);
R6.L = ASHIFT R6.H BY R3.L (S);
R7.L = ASHIFT R7.H BY R3.L (S);
CHECKREG r0, 0x00017fff;
CHECKREG r1, 0x00017fff;
CHECKREG r2, 0x00027fff;
CHECKREG r3, 0x00030010;
CHECKREG r4, 0x00047fff;
CHECKREG r5, 0x00057fff;
CHECKREG r6, 0x00067fff;
CHECKREG r7, 0x00077fff;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R0.L (S);
R1.H = ASHIFT R1.L BY R0.L (S);
R2.H = ASHIFT R2.L BY R0.L (S);
R3.H = ASHIFT R3.L BY R0.L (S);
R4.H = ASHIFT R4.L BY R0.L (S);
R5.H = ASHIFT R5.L BY R0.L (S);
R6.H = ASHIFT R6.L BY R0.L (S);
R7.H = ASHIFT R7.L BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R1.L (S);
R1.H = ASHIFT R1.L BY R1.L (S);
R2.H = ASHIFT R2.L BY R1.L (S);
R3.H = ASHIFT R3.L BY R1.L (S);
R4.H = ASHIFT R4.L BY R1.L (S);
R5.H = ASHIFT R5.L BY R1.L (S);
R6.H = ASHIFT R6.L BY R1.L (S);
R7.H = ASHIFT R7.L BY R1.L (S);
CHECKREG r0, 0x00020001;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00040002;
CHECKREG r3, 0x00060003;
CHECKREG r4, 0x00080004;
CHECKREG r5, 0x000a0005;
CHECKREG r6, 0x000c0006;
CHECKREG r7, 0x000e0007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000000f;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R2.L (S);
R1.H = ASHIFT R1.L BY R2.L (S);
//rh2 = ashift (rl2 by rl2) s;
R3.H = ASHIFT R3.L BY R2.L (S);
R4.H = ASHIFT R4.L BY R2.L (S);
R5.H = ASHIFT R5.L BY R2.L (S);
R6.H = ASHIFT R6.L BY R2.L (S);
R7.H = ASHIFT R7.L BY R2.L (S);
CHECKREG r0, 0x7fff0001;
CHECKREG r1, 0x7fff0001;
//ECKREG(r2, 0x7fff000f);
CHECKREG r3, 0x7fff0003;
CHECKREG r4, 0x7fff0004;
CHECKREG r5, 0x7fff0005;
CHECKREG r6, 0x7fff0006;
CHECKREG r7, 0x7fff0007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000010;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R3.L (S);
R1.H = ASHIFT R1.L BY R3.L (S);
R2.H = ASHIFT R2.L BY R3.L (S);
R3.H = ASHIFT R3.L BY R3.L (S);
R4.H = ASHIFT R4.L BY R3.L (S);
R5.H = ASHIFT R5.L BY R3.L (S);
R6.H = ASHIFT R6.L BY R3.L (S);
R7.H = ASHIFT R7.L BY R3.L (S);
CHECKREG r0, 0x7fff0001;
CHECKREG r1, 0x7fff0001;
CHECKREG r2, 0x7fff0002;
CHECKREG r3, 0x7fff0010;
CHECKREG r4, 0x7fff0004;
CHECKREG r5, 0x7fff0005;
CHECKREG r6, 0x7fff0006;
CHECKREG r7, 0x7fff0007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R0.L (S);
R1.H = ASHIFT R1.H BY R0.L (S);
R2.H = ASHIFT R2.H BY R0.L (S);
R3.H = ASHIFT R3.H BY R0.L (S);
R4.H = ASHIFT R4.H BY R0.L (S);
R5.H = ASHIFT R5.H BY R0.L (S);
R6.H = ASHIFT R6.H BY R0.L (S);
R7.H = ASHIFT R7.H BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;
imm32 r0, 0x00010000;
imm32 r1, 0x00010001;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R1.L (S);
R1.H = ASHIFT R1.H BY R1.L (S);
R2.H = ASHIFT R2.H BY R1.L (S);
R3.H = ASHIFT R3.H BY R1.L (S);
R4.H = ASHIFT R4.H BY R1.L (S);
R5.H = ASHIFT R5.H BY R1.L (S);
R6.H = ASHIFT R6.H BY R1.L (S);
R7.H = ASHIFT R7.H BY R1.L (S);
CHECKREG r0, 0x00020000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00040000;
CHECKREG r3, 0x00060000;
CHECKREG r4, 0x00080000;
CHECKREG r5, 0x000a0000;
CHECKREG r6, 0x000c0000;
CHECKREG r7, 0x000e0000;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x0002000f;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R2.L (S);
R1.L = ASHIFT R1.H BY R2.L (S);
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L (S);
R4.L = ASHIFT R4.H BY R2.L (S);
R5.L = ASHIFT R5.H BY R2.L (S);
R6.L = ASHIFT R6.H BY R2.L (S);
R7.L = ASHIFT R7.H BY R2.L (S);
CHECKREG r0, 0x00017fff;
CHECKREG r1, 0x00017fff;
//CHECKREG r2, 0x00027fff;
CHECKREG r3, 0x00037fff;
CHECKREG r4, 0x00047fff;
CHECKREG r5, 0x00057fff;
CHECKREG r6, 0x00067fff;
CHECKREG r7, 0x00077fff;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030010;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R3.L (S);
R1.H = ASHIFT R1.H BY R3.L (S);
R2.H = ASHIFT R2.H BY R3.L (S);
R3.H = ASHIFT R3.H BY R3.L (S);
R4.H = ASHIFT R4.H BY R3.L (S);
R5.H = ASHIFT R5.H BY R3.L (S);
R6.H = ASHIFT R6.H BY R3.L (S);
R7.H = ASHIFT R7.H BY R3.L (S);
CHECKREG r0, 0x7fff0000;
CHECKREG r1, 0x7fff0000;
CHECKREG r2, 0x7fff0000;
CHECKREG r3, 0x7fff0010;
CHECKREG r4, 0x7fff0000;
CHECKREG r5, 0x7fff0000;
CHECKREG r6, 0x7fff0000;
CHECKREG r7, 0x7fff0000;
pass
|
stsp/binutils-ia16
| 7,027
|
sim/testsuite/bfin/c_ldst_ld_p_p_mm.s
|
//Original:testcases/core/c_ldst_ld_p_p_mm/c_ldst_ld_p_p_mm.dsp
// Spec Reference: c_ldst ld p [p--]
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x18;
loadsym p2, DATA_ADDR_2, 0x18;
loadsym i1, DATA_ADDR_3, 0x18;
loadsym p4, DATA_ADDR_4, 0x18;
loadsym p5, DATA_ADDR_5, 0x18;
loadsym fp, DATA_ADDR_6, 0x18;
loadsym i3, DATA_ADDR_7, 0x18;
P3 = I1; SP = I3;
P2 = [ P1 -- ];
P3 = [ P1 -- ];
P4 = [ P1 -- ];
P5 = [ P1 -- ];
SP = [ P1 -- ];
FP = [ P1 -- ];
CHECKREG p2, 0x18191A1B;
CHECKREG p3, 0x14151617;
CHECKREG p4, 0x10111213;
CHECKREG p5, 0x0C0D0E0F;
CHECKREG sp, 0x08090A0B;
CHECKREG fp, 0x04050607;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p2, DATA_ADDR_2, 0x18;
P3 = I1; SP = I3;
P1 = [ P2 -- ];
P3 = [ P2 -- ];
P4 = [ P2 -- ];
P5 = [ P2 -- ];
SP = [ P2 -- ];
FP = [ P2 -- ];
CHECKREG p1, 0x38393A3B;
CHECKREG p3, 0x34353637;
CHECKREG p4, 0x30313233;
CHECKREG p5, 0x2C2D2E2F;
CHECKREG sp, 0x28292A2B;
CHECKREG fp, 0x24252627;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i1, DATA_ADDR_3, 0x18;
P3 = I1; SP = I3;
P1 = [ P3 -- ];
P2 = [ P3 -- ];
P4 = [ P3 -- ];
P5 = [ P3 -- ];
SP = [ P3 -- ];
FP = [ P3 -- ];
CHECKREG p1, 0x58595A5B;
CHECKREG p2, 0x54555657;
CHECKREG p4, 0x50515253;
CHECKREG p5, 0x4C4D4E4F;
CHECKREG sp, 0x48494A4B;
CHECKREG fp, 0x44454647;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p4, DATA_ADDR_4, 0x18;
P3 = I1; SP = I3;
P1 = [ P4 -- ];
P2 = [ P4 -- ];
P3 = [ P4 -- ];
P5 = [ P4 -- ];
SP = [ P4 -- ];
FP = [ P4 -- ];
CHECKREG p1, 0x78797A7B;
CHECKREG p2, 0x74757677;
CHECKREG p3, 0x70717273;
CHECKREG p5, 0x6C6D6E6F;
CHECKREG sp, 0x68696A6B;
CHECKREG fp, 0x64656667;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_5, 0x18;
P3 = I1; SP = I3;
P1 = [ P5 -- ];
P2 = [ P5 -- ];
P3 = [ P5 -- ];
P4 = [ P5 -- ];
SP = [ P5 -- ];
FP = [ P5 -- ];
CHECKREG p1, 0x98999A9B;
CHECKREG p2, 0x94959697;
CHECKREG p3, 0x90919293;
CHECKREG p4, 0x8C8D8E8F;
CHECKREG sp, 0x88898A8B;
CHECKREG fp, 0x84858687;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i3, DATA_ADDR_6, 0x18;
P3 = I1; SP = I3;
P1 = [ SP -- ];
P2 = [ SP -- ];
P3 = [ SP -- ];
P4 = [ SP -- ];
P5 = [ SP -- ];
FP = [ SP -- ];
CHECKREG p1, 0x18191A1B;
CHECKREG p2, 0x14151617;
CHECKREG p3, 0x10111213;
CHECKREG p4, 0x0C0D0E0F;
CHECKREG p5, 0x08090A0B;
CHECKREG fp, 0x04050607;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_7, 0x18;
P3 = I1; SP = I3;
P1 = [ FP -- ];
P2 = [ FP -- ];
P3 = [ FP -- ];
P4 = [ FP -- ];
P5 = [ FP -- ];
SP = [ FP -- ];
CHECKREG p1, 0x98999A9B;
CHECKREG p2, 0x94959697;
CHECKREG p3, 0x90919293;
CHECKREG p4, 0x8C8D8E8F;
CHECKREG p5, 0x88898A8B;
CHECKREG sp, 0x84858687;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x78910213
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x8A8B8C8D
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 2,415
|
sim/testsuite/bfin/c_compi2opp_pr_eq_i7_n.s
|
//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_n/c_compi2opp_pr_eq_i7_n.dsp
// Spec Reference: compi2opp pregs = imm7 negative
# mach: bfin
.include "testutils.inc"
start
R0 = -0;
P1 = -1;
P2 = -2;
P3 = -3;
P4 = -4;
P5 = -5;
SP = -6;
FP = -7;
CHECKREG r0, -0;
CHECKREG p1, -1;
CHECKREG p2, -2;
CHECKREG p3, -3;
CHECKREG p4, -4;
CHECKREG p5, -5;
CHECKREG sp, -6;
CHECKREG fp, -7;
R0 = -8;
P1 = -9;
P2 = -10;
P3 = -11;
P4 = -12;
P5 = -13;
SP = -14;
FP = -15;
CHECKREG r0, -8;
CHECKREG p1, -9;
CHECKREG p2, -10;
CHECKREG p3, -11;
CHECKREG p4, -12;
CHECKREG p5, -13;
CHECKREG sp, -14;
CHECKREG fp, -15;
R0 = -16;
P1 = -17;
P2 = -18;
P3 = -19;
P4 = -20;
P5 = -21;
SP = -22;
FP = -23;
CHECKREG r0, -16;
CHECKREG p1, -17;
CHECKREG p2, -18;
CHECKREG p3, -19;
CHECKREG p4, -20;
CHECKREG p5, -21;
CHECKREG sp, -22;
CHECKREG fp, -23;
R0 = -24;
P1 = -25;
P2 = -26;
P3 = -27;
P4 = -28;
P5 = -29;
SP = -30;
FP = -31;
CHECKREG r0, -24;
CHECKREG p1, -25;
CHECKREG p2, -26;
CHECKREG p3, -27;
CHECKREG p4, -28;
CHECKREG p5, -29;
CHECKREG sp, -30;
CHECKREG fp, -31;
R0 = -32;
P1 = -33;
P2 = -34;
P3 = -35;
P4 = -36;
P5 = -37;
SP = -38;
FP = -39;
CHECKREG r0, -32;
CHECKREG p1, -33;
CHECKREG p2, -34;
CHECKREG p3, -35;
CHECKREG p4, -36;
CHECKREG p5, -37;
CHECKREG sp, -38;
CHECKREG fp, -39;
R0 = -40;
P1 = -41;
P2 = -42;
P3 = -43;
P4 = -44;
P5 = -45;
SP = -46;
FP = -47;
CHECKREG r0, -40;
CHECKREG p1, -41;
CHECKREG p2, -42;
CHECKREG p3, -43;
CHECKREG p4, -44;
CHECKREG p5, -45;
CHECKREG sp, -46;
CHECKREG fp, -47;
R0 = -48;
P1 = -49;
P2 = -50;
P3 = -51;
P4 = -52;
P5 = -53;
SP = -54;
FP = -55;
CHECKREG r0, -48;
CHECKREG p1, -49;
CHECKREG p2, -50;
CHECKREG p3, -51;
CHECKREG p4, -52;
CHECKREG p5, -53;
CHECKREG sp, -54;
CHECKREG fp, -55;
R0 = -56;
P1 = -57;
P2 = -58;
P3 = -59;
P4 = -60;
P5 = -61;
SP = -62;
FP = -63;
CHECKREG r0, -56;
CHECKREG p1, -57;
CHECKREG p2, -58;
CHECKREG p3, -59;
CHECKREG p4, -60;
CHECKREG p5, -61;
CHECKREG sp, -62;
CHECKREG fp, -63;
R0 = -64;
P1 = -64;
P2 = -64;
P3 = -64;
P4 = -64;
P5 = -64;
SP = -64;
FP = -64;
CHECKREG r0, -64;
CHECKREG p1, -64;
CHECKREG p2, -64;
CHECKREG p3, -64;
CHECKREG p4, -64;
CHECKREG p5, -64;
CHECKREG sp, -64;
CHECKREG fp, -64;
pass
|
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