repo_id
stringlengths 5
115
| size
int64 590
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| file_path
stringlengths 4
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stringlengths 590
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stsp/binutils-ia16
| 7,100
|
sim/testsuite/bfin/random_0028.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x44004010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0x851fa4fc;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x00000000;
imm32 R2, 0x80000000;
imm32 R5, 0x139d77b4;
R5.H = (A1 += R2.L * R0.L) (M, S2RND);
checkreg R5, 0x7fff77b4;
checkreg A1.w, 0x851fa4fc;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x44004010 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x48000600 | _VS | _V | _AV1S | _CC | _V_COPY);
dmm32 A1.w, 0xc5ee7420;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x45f17fff;
imm32 R2, 0x00000000;
imm32 R4, 0xffffffff;
R1 = (A1 -= R2.L * R4.H) (M, S2RND);
checkreg R1, 0x7fffffff;
checkreg A1.w, 0xc5ee7420;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x48000600 | _VS | _V | _AV1S | _CC | _V_COPY);
dmm32 ASTAT, (0x48500a10 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 A1.w, 0x965cddab;
dmm32 A1.x, 0x00000063;
imm32 R1, 0x1d4cc3e7;
imm32 R3, 0xe7ce9d8e;
imm32 R6, 0x3cc80b2f;
R6.H = (A1 -= R3.L * R1.L) (M, S2RND);
checkreg R6, 0x7fff0b2f;
checkreg A1.w, 0xe1b28889;
checkreg A1.x, 0x00000063;
checkreg ASTAT, (0x48500a10 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x44308410 | _VS | _AV0S | _CC | _AN);
dmm32 A1.w, 0x92315df7;
dmm32 A1.x, 0x0000007e;
imm32 R1, 0x9e4b24e0;
imm32 R4, 0xe3da8000;
imm32 R7, 0x00ba086c;
R1.H = (A1 -= R7.L * R4.H) (M, S2RND);
checkreg R1, 0x7fff24e0;
checkreg A1.w, 0x8ab26dff;
checkreg A1.x, 0x0000007e;
checkreg ASTAT, (0x44308410 | _VS | _V | _AV0S | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x10a00090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x8ed084bf;
dmm32 A1.x, 0xffffffbe;
imm32 R0, 0x8000ffff;
imm32 R3, 0xbb4e34ef;
imm32 R5, 0x7af8492d;
R5 = (A1 += R3.L * R0.L) (M, S2RND);
checkreg R5, 0x80000000;
checkreg A1.w, 0xc3bf4fd0;
checkreg A1.x, 0xffffffbe;
checkreg ASTAT, (0x10a00090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x10f04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AN | _AZ);
dmm32 A1.w, 0x81becdd8;
dmm32 A1.x, 0x00000058;
imm32 R2, 0x14946201;
imm32 R4, 0x1a162edd;
R2.H = (A1 -= R2.L * R4.L) (M, S2RND);
checkreg R2, 0x7fff6201;
checkreg A1.w, 0x6fce04fb;
checkreg A1.x, 0x00000058;
checkreg ASTAT, (0x10f04e10 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AN | _AZ);
dmm32 ASTAT, (0x20f04c80 | _VS | _AV0S | _AN);
dmm32 A1.w, 0xe9cc0041;
dmm32 A1.x, 0x00000079;
imm32 R1, 0x0f62a5a2;
imm32 R3, 0x4e8e9bdd;
imm32 R7, 0x6630d991;
R1 = (A1 -= R3.L * R7.H) (M, S2RND);
checkreg R1, 0x7fffffff;
checkreg A1.w, 0x11c4b8d1;
checkreg A1.x, 0x0000007a;
checkreg ASTAT, (0x20f04c80 | _VS | _V | _AV0S | _V_COPY | _AN);
dmm32 ASTAT, (0x20104e00 | _VS | _AC1 | _AC0 | _AQ | _AN);
dmm32 A1.w, 0xadeb5c67;
dmm32 A1.x, 0xffffffa6;
imm32 R1, 0x07911840;
imm32 R7, 0x01070000;
R7 = (A1 += R1.L * R7.H) (M, S2RND);
checkreg R7, 0x80000000;
checkreg A1.w, 0xae044627;
checkreg A1.x, 0xffffffa6;
checkreg ASTAT, (0x20104e00 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x08e04010 | _VS | _AV0S);
dmm32 A1.w, 0xff80f384;
dmm32 A1.x, 0x00000003;
imm32 R1, 0x00000000;
imm32 R2, 0x8000387c;
imm32 R3, 0x1e547fff;
R2.H = (A1 -= R1.L * R3.L) (M, S2RND);
checkreg R2, 0x7fff387c;
checkreg A1.w, 0xff80f384;
checkreg A1.x, 0x00000003;
checkreg ASTAT, (0x08e04010 | _VS | _V | _AV0S | _V_COPY);
dmm32 ASTAT, (0x0cf08280 | _VS | _AV1S | _AC1 | _CC | _AN);
dmm32 A1.w, 0x80000000;
dmm32 A1.x, 0xffffff80;
imm32 R2, 0xecc35cac;
imm32 R4, 0x00007fff;
imm32 R7, 0x80000000;
R7 = (A1 -= R4.L * R2.L) (M, S2RND);
checkreg R7, 0x80000000;
checkreg A1.w, 0x51aa5cac;
checkreg A1.x, 0xffffff80;
checkreg ASTAT, (0x0cf08280 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x40c08090 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0xfcbe6525;
dmm32 A1.x, 0x00000039;
imm32 R0, 0x0003f3c0;
imm32 R2, 0xfffffffc;
imm32 R6, 0xffff0000;
R0.H = (A1 -= R2.L * R6.H) (M, S2RND);
checkreg R0, 0x7ffff3c0;
checkreg A1.w, 0xfcc26521;
checkreg A1.x, 0x00000039;
checkreg ASTAT, (0x40c08090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x00704c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY);
dmm32 A1.w, 0xdfbb3c19;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x50407788;
imm32 R4, 0x50407788;
imm32 R6, 0x0d3f0c0a;
R6.H = (A1 -= R4.L * R0.L) (M, S2RND);
checkreg R6, 0x7fff0c0a;
checkreg A1.w, 0xa7eb83d9;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x00704c10 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY);
dmm32 ASTAT, (0x3c50c610 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
dmm32 A1.w, 0xbc7ca70b;
dmm32 A1.x, 0xffffff80;
imm32 R1, 0x76b3a772;
imm32 R2, 0x5cc87864;
imm32 R5, 0x33169c34;
R1 = (A1 += R2.L * R5.H) (M, S2RND);
checkreg R1, 0x80000000;
checkreg A1.w, 0xd482eba3;
checkreg A1.x, 0xffffff80;
checkreg ASTAT, (0x3c50c610 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x50008480 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A1.w, 0xd843bd0f;
dmm32 A1.x, 0x00000027;
imm32 R0, 0xc5d36b7c;
imm32 R7, 0x7fff8000;
R0.H = (A1 += R0.L * R7.L) (M, S2RND);
checkreg R0, 0x7fff6b7c;
checkreg A1.w, 0x0e01bd0f;
checkreg A1.x, 0x00000028;
checkreg ASTAT, (0x50008480 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _V_COPY | _AN);
dmm32 A1.w, 0xcf30f0be;
dmm32 A1.x, 0xffffffad;
imm32 R0, 0x6d8f3470;
imm32 R4, 0x4174b386;
imm32 R6, 0x0793b3dd;
R0.H = (A1 -= R4.L * R6.H) (M, S2RND);
checkreg R0, 0x80003470;
checkreg A1.w, 0xd17430cc;
checkreg A1.x, 0xffffffad;
checkreg ASTAT, (0x50208610 | _VS | _V | _AV1S | _AV0S | _V_COPY | _AN);
dmm32 ASTAT, (0x60700c10 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0xc867b111;
dmm32 A1.x, 0xffffff90;
imm32 R4, 0x580f445e;
imm32 R5, 0x1fb2e64b;
imm32 R6, 0xb6bc814b;
R6.H = (A1 += R5.L * R4.L) (M, S2RND);
checkreg R6, 0x8000814b;
checkreg A1.w, 0xc18a2c9b;
checkreg A1.x, 0xffffff90;
checkreg ASTAT, (0x60700c10 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x4070c080 | _AV0S | _CC);
dmm32 A1.w, 0xe1239b9f;
dmm32 A1.x, 0xffffffcd;
imm32 R4, 0xe4d2beb4;
imm32 R5, 0x1c919600;
imm32 R6, 0x18356124;
R5.H = (A1 -= R4.L * R6.L) (M, S2RND);
checkreg R5, 0x80009600;
checkreg A1.w, 0xf9ea964f;
checkreg A1.x, 0xffffffcd;
checkreg ASTAT, (0x4070c080 | _VS | _V | _AV0S | _CC | _V_COPY);
dmm32 ASTAT, (0x50608210 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0xe8c00d5a;
dmm32 A1.x, 0xffffffbe;
imm32 R1, 0x2baf99f2;
imm32 R4, 0x03e69887;
imm32 R7, 0x07f45a0f;
R1 = (A1 -= R7.L * R4.H) (M, S2RND);
checkreg R1, 0x80000000;
checkreg A1.w, 0xe760f6e0;
checkreg A1.x, 0xffffffbe;
checkreg ASTAT, (0x50608210 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
pass
|
stsp/binutils-ia16
| 5,343
|
sim/testsuite/bfin/c_ldst_st_p_d.s
|
//Original:/testcases/core/c_ldst_st_p_d/c_ldst_st_p_d.dsp
// Spec Reference: c_ldst st_p_d
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
[ P5 ] = R0;
[ P1 ] = R1;
[ P2 ] = R2;
[ P4 ] = R4;
[ FP ] = R5;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x1B342618;
CHECKREG r1, 0x2C453729;
CHECKREG r3, 0x4E67594B;
CHECKREG r4, 0x0A231507;
CHECKREG r5, 0x5F786A5C;
CHECKREG r7, 0x719A8C7E;
imm32 r0, 0x1a231507;
imm32 r1, 0x12342618;
imm32 r2, 0x2c353729;
imm32 r3, 0x3d54483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f78665c;
imm32 r6, 0x60897b7d;
imm32 r7, 0x719a8c78;
[ P5 ] = R1;
[ P1 ] = R2;
[ P2 ] = R3;
[ P4 ] = R5;
[ FP ] = R6;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x2C353729;
CHECKREG r1, 0x3D54483A;
CHECKREG r3, 0x5F78665C;
CHECKREG r4, 0x12342618;
CHECKREG r5, 0x60897B7D;
CHECKREG r7, 0x719A8C78;
imm32 r0, 0x2a231507;
imm32 r1, 0x12342618;
imm32 r2, 0x2c253729;
imm32 r3, 0x3d52483a;
imm32 r4, 0x4e67294b;
imm32 r5, 0x5f78625c;
imm32 r6, 0x60897b2d;
imm32 r7, 0x719a8c72;
[ P5 ] = R2;
[ P1 ] = R3;
[ P2 ] = R4;
[ P4 ] = R6;
[ FP ] = R7;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x3D52483A;
CHECKREG r1, 0x4E67294B;
CHECKREG r3, 0x60897B2D;
CHECKREG r4, 0x2C253729;
CHECKREG r5, 0x719A8C72;
CHECKREG r7, 0x719A8C72;
imm32 r0, 0x3a231507;
imm32 r1, 0x13342618;
imm32 r2, 0x2c353729;
imm32 r3, 0x3d53483a;
imm32 r4, 0x4e67394b;
imm32 r5, 0x5f78635c;
imm32 r6, 0x60897b3d;
imm32 r7, 0x719a8c73;
[ P5 ] = R3;
[ P1 ] = R4;
[ P2 ] = R5;
[ P4 ] = R7;
[ FP ] = R0;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x4E67394B;
CHECKREG r1, 0x5F78635C;
CHECKREG r3, 0x719A8C73;
CHECKREG r4, 0x3D53483A;
CHECKREG r5, 0x3A231507;
CHECKREG r7, 0x719A8C73;
imm32 r0, 0x4a231507;
imm32 r1, 0x14342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d54483a;
imm32 r4, 0x4e67494b;
imm32 r5, 0x5f78645c;
imm32 r6, 0x60897b4d;
imm32 r7, 0x719a8c74;
[ P5 ] = R4;
[ P1 ] = R5;
[ P2 ] = R6;
[ P4 ] = R0;
[ FP ] = R1;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x5F78645C;
CHECKREG r1, 0x60897B4D;
CHECKREG r3, 0x4A231507;
CHECKREG r4, 0x4E67494B;
CHECKREG r5, 0x14342618;
CHECKREG r7, 0x719A8C74;
imm32 r0, 0x5a231507;
imm32 r1, 0x15342618;
imm32 r2, 0x2c553729;
imm32 r3, 0x3d55483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f78655c;
imm32 r6, 0x60897b5d;
imm32 r7, 0x719a8c75;
[ P5 ] = R5;
[ P1 ] = R6;
[ P2 ] = R7;
[ P4 ] = R1;
[ FP ] = R2;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x60897B5D;
CHECKREG r1, 0x719A8C75;
CHECKREG r3, 0x15342618;
CHECKREG r4, 0x5F78655C;
CHECKREG r5, 0x2C553729;
CHECKREG r7, 0x719A8C75;
imm32 r0, 0x6a231507;
imm32 r1, 0x16342618;
imm32 r2, 0x2c653729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67694b;
imm32 r5, 0x5f78665c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c76;
[ P5 ] = R6;
[ P1 ] = R7;
[ P2 ] = R0;
[ P4 ] = R2;
[ FP ] = R3;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x719A8C76;
CHECKREG r1, 0x6A231507;
CHECKREG r3, 0x2C653729;
CHECKREG r4, 0x60897B6D;
CHECKREG r5, 0x3D56483A;
CHECKREG r7, 0x719A8C76;
imm32 r0, 0x7a231507;
imm32 r1, 0x17342618;
imm32 r2, 0x2c753729;
imm32 r3, 0x3d57483a;
imm32 r4, 0x4e67794b;
imm32 r5, 0x5f78675c;
imm32 r6, 0x60897b7d;
imm32 r7, 0x719a8c77;
[ P5 ] = R7;
[ P1 ] = R0;
[ P2 ] = R1;
[ P4 ] = R3;
[ FP ] = R4;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x7A231507;
CHECKREG r1, 0x17342618;
CHECKREG r3, 0x3D57483A;
CHECKREG r4, 0x719A8C77;
CHECKREG r5, 0x4E67794B;
CHECKREG r7, 0x719A8C77;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 1,066
|
sim/testsuite/bfin/c_brcc_brf_bp.s
|
//Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp
// Spec Reference: brcc brf bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
IF !CC JUMP good1 (BP); // branch on false (should branch)
CC = ! CC; // set cc=1
R1 = 1; // if go here, error
good1: IF !CC JUMP good2 (BP); // branch on false (should branch)
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; //
IF !CC JUMP bad2 (BP); // branch on false (should not branch)
CC = ! CC;
IF !CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF !CC JUMP end; // branch on true (should branch)
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 6,094
|
sim/testsuite/bfin/c_dsp32mult_dr_i.s
|
//Original:/testcases/core/c_dsp32mult_dr_i/c_dsp32mult_dr_i.dsp
// Spec Reference: dsp32mult single dr i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IS);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IS);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IS);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IS);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IS);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IS);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IS);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IS);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x80007FFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x7FFF8000;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0x8923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1824b735;
imm32 r3, 0x99860037;
imm32 r4, 0x8098cd39;
imm32 r5, 0xb0a98f3b;
imm32 r6, 0xa00c083d;
imm32 r7, 0x12467083;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IS);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IS);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IS);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IS);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IS);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IS);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IS);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IS);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x80007FFF;
CHECKREG r7, 0x80008000;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IS);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IS);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IS);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IS);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IS);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IS);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IS);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IS);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x80008000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xe0060066;
imm32 r4, 0x9eab9d69;
imm32 r5, 0x10ecef6b;
imm32 r6, 0x800ee06d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IS);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IS);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IS);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IS);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IS);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IS);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IS);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IS);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x80008000;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0x7FFF7FFF;
// mix order
imm32 r0, 0xac23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13c46705;
imm32 r3, 0xf0060007;
imm32 r4, 0x9faccd09;
imm32 r5, 0x10fcdfdb;
imm32 r6, 0x000fc00d;
imm32 r7, 0x1246ff0f;
R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IS);
R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IS);
R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IS);
R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IS);
R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IS);
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IS);
R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IS);
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IS);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x80008000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x80007FFF;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R5.H * R0.H, R0.L = R5.H * R0.L (IS);
R1.H = R6.H * R1.L, R1.L = R6.L * R1.L (IS);
R2.H = R7.H * R2.H, R2.L = R7.H * R2.H (IS);
R3.H = R0.L * R3.H, R3.L = R0.H * R3.L (IS);
R4.H = R1.H * R4.H, R4.L = R1.L * R4.L (IS);
R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IS);
R6.H = R3.H * R6.H, R6.L = R3.L * R6.L (IS);
R7.H = R4.L * R7.H, R7.L = R4.H * R7.H (IS);
CHECKREG r0, 0x80007FFF;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x80007FFF;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0x80008000;
imm32 r0, 0xfb235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13f46705;
imm32 r3, 0x000f0007;
imm32 r4, 0x90abfd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IS);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IS);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IS);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IS);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IS);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IS);
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IS);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x80007FFF;
imm32 r0, 0xab2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13246d05;
imm32 r3, 0x000600d7;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c500d;
imm32 r7, 0x1246760f;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IS);
R6.H = R6.H * R3.L, R6.L = R6.H * R3.H (IS);
R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IS);
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IS);
R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IS);
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IS);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IS);
R7.H = R4.H * R1.L, R7.L = R4.H * R1.H (IS);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x0A140048;
CHECKREG r7, 0x80007FFF;
pass
|
stsp/binutils-ia16
| 9,517
|
sim/testsuite/bfin/c_dsp32shift_pack.s
|
//Original:/testcases/core/c_dsp32shift_pack/c_dsp32shift_pack.dsp
// Spec Reference: dsp32shift pack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01230000;
imm32 r1, 0x02345678;
imm32 r2, 0x03456789;
imm32 r3, 0x0456789a;
imm32 r4, 0x056789ab;
imm32 r5, 0x06789abc;
imm32 r6, 0x0789abcd;
imm32 r7, 0x089abcde;
R1 = PACK( R0.L , R0.L );
R2 = PACK( R1.L , R0.H );
R3 = PACK( R2.H , R0.L );
R4 = PACK( R3.H , R0.H );
R5 = PACK( R4.L , R0.L );
R6 = PACK( R5.L , R0.H );
R7 = PACK( R6.H , R0.L );
R0 = PACK( R7.H , R0.H );
CHECKREG r1, 0x00000000;
CHECKREG r0, 0x00000123;
CHECKREG r2, 0x00000123;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000123;
CHECKREG r5, 0x01230000;
CHECKREG r6, 0x00000123;
CHECKREG r7, 0x00000000;
imm32 r0, 0x11230001;
imm32 r1, 0x12345678;
imm32 r2, 0x1bcdef12;
imm32 r3, 0x1456789a;
imm32 r4, 0x1cdef012;
imm32 r5, 0x1456789a;
imm32 r6, 0x1789abcd;
imm32 r7, 0x189abcde;
R2 = PACK( R0.L , R1.L );
R3 = PACK( R1.L , R1.H );
R4 = PACK( R2.H , R1.L );
R5 = PACK( R3.H , R1.H );
R6 = PACK( R4.L , R1.L );
R7 = PACK( R5.L , R1.H );
R0 = PACK( R6.H , R1.L );
R1 = PACK( R7.H , R1.H );
CHECKREG r0, 0x56785678;
CHECKREG r1, 0x12341234;
CHECKREG r2, 0x00015678;
CHECKREG r3, 0x56781234;
CHECKREG r4, 0x00015678;
CHECKREG r5, 0x56781234;
CHECKREG r6, 0x56785678;
CHECKREG r7, 0x12341234;
imm32 r0, 0x20230002;
imm32 r1, 0x21345678;
imm32 r2, 0x22456789;
imm32 r3, 0x2356789a;
imm32 r4, 0x246789ab;
imm32 r5, 0x25789abc;
imm32 r6, 0x2689abcd;
imm32 r7, 0x279abcde;
R3 = PACK( R0.L , R2.L );
R4 = PACK( R1.L , R2.H );
R5 = PACK( R2.H , R2.L );
R6 = PACK( R3.H , R2.H );
R7 = PACK( R4.L , R2.L );
R0 = PACK( R5.L , R2.H );
R1 = PACK( R6.H , R2.L );
R2 = PACK( R7.H , R2.H );
CHECKREG r0, 0x67892245;
CHECKREG r1, 0x00026789;
CHECKREG r2, 0x22452245;
CHECKREG r3, 0x00026789;
CHECKREG r4, 0x56782245;
CHECKREG r5, 0x22456789;
CHECKREG r6, 0x00022245;
CHECKREG r7, 0x22456789;
imm32 r0, 0x31230003;
imm32 r1, 0x31345678;
imm32 r2, 0x31456789;
imm32 r3, 0x3156789a;
imm32 r4, 0x316789ab;
imm32 r5, 0x31789abc;
imm32 r6, 0x3189abcd;
imm32 r7, 0x311abcde;
R4 = PACK( R0.L , R3.L );
R5 = PACK( R1.L , R3.H );
R6 = PACK( R2.H , R3.L );
R7 = PACK( R3.H , R3.H );
R0 = PACK( R4.L , R3.L );
R1 = PACK( R5.L , R3.H );
R2 = PACK( R6.H , R3.L );
R3 = PACK( R7.H , R3.H );
CHECKREG r0, 0x789A789A;
CHECKREG r1, 0x31563156;
CHECKREG r2, 0x3145789A;
CHECKREG r3, 0x31563156;
CHECKREG r4, 0x0003789A;
CHECKREG r5, 0x56783156;
CHECKREG r6, 0x3145789A;
CHECKREG r7, 0x31563156;
imm32 r0, 0x41230004;
imm32 r1, 0x42345678;
imm32 r2, 0x43456789;
imm32 r3, 0x4456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x46789abc;
imm32 r6, 0x4789abcd;
imm32 r7, 0x489abcde;
R0 = PACK( R0.L , R4.L );
R1 = PACK( R1.L , R4.H );
R2 = PACK( R2.H , R4.L );
R3 = PACK( R3.H , R4.H );
R4 = PACK( R4.L , R4.L );
R5 = PACK( R5.L , R4.H );
R6 = PACK( R6.H , R4.L );
R7 = PACK( R7.H , R4.H );
CHECKREG r0, 0x000489AB;
CHECKREG r1, 0x56784567;
CHECKREG r2, 0x434589AB;
CHECKREG r3, 0x44564567;
CHECKREG r4, 0x89AB89AB;
CHECKREG r5, 0x9ABC89AB;
CHECKREG r6, 0x478989AB;
CHECKREG r7, 0x489A89AB;
imm32 r0, 0x51230005;
imm32 r1, 0x52345678;
imm32 r2, 0x53456789;
imm32 r3, 0x5456789a;
imm32 r4, 0x556789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x5789abcd;
imm32 r7, 0x589abcde;
R6 = PACK( R0.L , R5.L );
R7 = PACK( R1.L , R5.H );
R0 = PACK( R2.H , R5.L );
R1 = PACK( R3.H , R5.H );
R2 = PACK( R4.L , R5.L );
R3 = PACK( R5.L , R5.H );
R4 = PACK( R6.H , R5.L );
R5 = PACK( R7.H , R5.H );
CHECKREG r0, 0x53459ABC;
CHECKREG r1, 0x54565678;
CHECKREG r2, 0x89AB9ABC;
CHECKREG r3, 0x9ABC5678;
CHECKREG r4, 0x00059ABC;
CHECKREG r5, 0x56785678;
CHECKREG r6, 0x00059ABC;
CHECKREG r7, 0x56785678;
imm32 r0, 0x61230006;
imm32 r1, 0x62345678;
imm32 r2, 0x63456789;
imm32 r3, 0x6456789a;
imm32 r4, 0x656789ab;
imm32 r5, 0x66789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x689abcde;
R7 = PACK( R0.L , R6.L );
R0 = PACK( R1.L , R6.H );
R1 = PACK( R2.H , R6.L );
R2 = PACK( R3.H , R6.H );
R3 = PACK( R4.L , R6.L );
R4 = PACK( R5.L , R6.H );
R5 = PACK( R6.H , R6.L );
R6 = PACK( R7.H , R6.H );
CHECKREG r0, 0x56786789;
CHECKREG r1, 0x6345ABCD;
CHECKREG r2, 0x64566789;
CHECKREG r3, 0x89ABABCD;
CHECKREG r4, 0x9ABC6789;
CHECKREG r5, 0x6789ABCD;
CHECKREG r6, 0x00066789;
CHECKREG r7, 0x0006ABCD;
imm32 r0, 0x71230007;
imm32 r1, 0x72345678;
imm32 r2, 0x73456789;
imm32 r3, 0x7456789a;
imm32 r4, 0x756789ab;
imm32 r5, 0x76789abc;
imm32 r6, 0x7789abcd;
imm32 r7, 0x789abcde;
R0 = PACK( R0.L , R7.L );
R1 = PACK( R1.L , R7.H );
R2 = PACK( R2.H , R7.L );
R3 = PACK( R3.H , R7.H );
R4 = PACK( R4.L , R7.L );
R5 = PACK( R5.L , R7.H );
R6 = PACK( R6.H , R7.L );
R7 = PACK( R7.H , R7.H );
CHECKREG r0, 0x0007BCDE;
CHECKREG r1, 0x5678789A;
CHECKREG r2, 0x7345BCDE;
CHECKREG r3, 0x7456789A;
CHECKREG r4, 0x89ABBCDE;
CHECKREG r5, 0x9ABC789A;
CHECKREG r6, 0x7789BCDE;
CHECKREG r7, 0x789A789A;
imm32 r0, 0x81230008;
imm32 r1, 0x82345678;
imm32 r2, 0x83456789;
imm32 r3, 0x8456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x8789abcd;
imm32 r7, 0x889abcde;
R0 = PACK( R0.L , R0.L );
R1 = PACK( R1.L , R0.H );
R2 = PACK( R2.H , R0.L );
R3 = PACK( R3.H , R0.H );
R4 = PACK( R4.L , R0.L );
R5 = PACK( R5.L , R0.H );
R6 = PACK( R6.H , R0.L );
R7 = PACK( R7.H , R0.H );
CHECKREG r0, 0x00080008;
CHECKREG r1, 0x56780008;
CHECKREG r2, 0x83450008;
CHECKREG r3, 0x84560008;
CHECKREG r4, 0x89AB0008;
CHECKREG r5, 0x9ABC0008;
CHECKREG r6, 0x87890008;
CHECKREG r7, 0x889A0008;
imm32 r0, 0x91230009;
imm32 r1, 0x92345678;
imm32 r2, 0x93456789;
imm32 r3, 0x9456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0x9789abcd;
imm32 r7, 0x989abcde;
R0 = PACK( R0.L , R1.L );
R1 = PACK( R1.L , R1.H );
R2 = PACK( R2.H , R1.L );
R3 = PACK( R3.H , R1.H );
R4 = PACK( R4.L , R1.L );
R5 = PACK( R5.L , R1.H );
R6 = PACK( R6.H , R1.L );
R7 = PACK( R7.H , R1.H );
CHECKREG r0, 0x00095678;
CHECKREG r1, 0x56789234;
CHECKREG r2, 0x93459234;
CHECKREG r3, 0x94565678;
CHECKREG r4, 0x89AB9234;
CHECKREG r5, 0x9ABC5678;
CHECKREG r6, 0x97899234;
CHECKREG r7, 0x989A5678;
imm32 r0, 0xa123000a;
imm32 r1, 0xa2345678;
imm32 r2, 0xa3456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xa56789ab;
imm32 r5, 0xa6789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xa89abcde;
R0 = PACK( R0.L , R2.L );
R1 = PACK( R1.L , R2.H );
R2 = PACK( R2.H , R2.L );
R3 = PACK( R3.H , R2.H );
R4 = PACK( R4.L , R2.L );
R5 = PACK( R5.L , R2.H );
R6 = PACK( R6.H , R2.L );
R7 = PACK( R7.H , R2.H );
CHECKREG r0, 0x000A6789;
CHECKREG r1, 0x5678A345;
CHECKREG r2, 0xA3456789;
CHECKREG r3, 0xA456A345;
CHECKREG r4, 0x89AB6789;
CHECKREG r5, 0x9ABCA345;
CHECKREG r6, 0xA7896789;
CHECKREG r7, 0xA89AA345;
imm32 r0, 0xb123000b;
imm32 r1, 0xb2345678;
imm32 r2, 0xb3456789;
imm32 r3, 0xb456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xb6789abc;
imm32 r6, 0xb789abcd;
imm32 r7, 0xb89abcde;
R0 = PACK( R0.L , R3.L );
R1 = PACK( R1.L , R3.H );
R2 = PACK( R2.H , R3.L );
R3 = PACK( R3.H , R3.H );
R4 = PACK( R4.L , R3.L );
R5 = PACK( R5.L , R3.H );
R6 = PACK( R6.H , R3.L );
R7 = PACK( R7.H , R3.H );
CHECKREG r0, 0x000B789A;
CHECKREG r1, 0x5678B456;
CHECKREG r2, 0xB345789A;
CHECKREG r3, 0xB456B456;
CHECKREG r4, 0x89ABB456;
CHECKREG r5, 0x9ABCB456;
CHECKREG r6, 0xB789B456;
CHECKREG r7, 0xB89AB456;
imm32 r0, 0xc123000c;
imm32 r1, 0xc2345678;
imm32 r2, 0xc3456789;
imm32 r3, 0xc456789a;
imm32 r4, 0xc56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xc789abcd;
imm32 r7, 0xc89abcde;
R0 = PACK( R0.L , R4.L );
R1 = PACK( R1.L , R4.H );
R2 = PACK( R2.H , R4.L );
R3 = PACK( R3.H , R4.H );
R4 = PACK( R4.L , R4.L );
R5 = PACK( R5.L , R4.H );
R6 = PACK( R6.H , R4.L );
R7 = PACK( R7.H , R4.H );
CHECKREG r0, 0x000C89AB;
CHECKREG r1, 0x5678C567;
CHECKREG r2, 0xC34589AB;
CHECKREG r3, 0xC456C567;
CHECKREG r4, 0x89AB89AB;
CHECKREG r5, 0x9ABC89AB;
CHECKREG r6, 0xC78989AB;
CHECKREG r7, 0xC89A89AB;
imm32 r0, 0xd123000d;
imm32 r1, 0xd2345678;
imm32 r2, 0xd3456789;
imm32 r3, 0xd456789a;
imm32 r4, 0xd56789ab;
imm32 r5, 0xd6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xd89abcde;
R0 = PACK( R0.L , R5.L );
R1 = PACK( R1.L , R5.H );
R2 = PACK( R2.H , R5.L );
R3 = PACK( R3.H , R5.H );
R4 = PACK( R4.L , R5.L );
R5 = PACK( R5.L , R5.H );
R6 = PACK( R6.H , R5.L );
R7 = PACK( R7.H , R5.H );
CHECKREG r0, 0x000D9ABC;
CHECKREG r1, 0x5678D678;
CHECKREG r2, 0xD3459ABC;
CHECKREG r3, 0xD456D678;
CHECKREG r4, 0x89AB9ABC;
CHECKREG r5, 0x9ABCD678;
CHECKREG r6, 0xD789D678;
CHECKREG r7, 0xD89A9ABC;
imm32 r0, 0xe123000e;
imm32 r1, 0xe2345678;
imm32 r2, 0xe3456789;
imm32 r3, 0xe456789a;
imm32 r4, 0xe56789ab;
imm32 r5, 0xe6789abc;
imm32 r6, 0xe789abcd;
imm32 r7, 0xe89abcde;
R0 = PACK( R0.L , R6.L );
R1 = PACK( R1.L , R6.H );
R2 = PACK( R2.H , R6.L );
R3 = PACK( R3.H , R6.H );
R4 = PACK( R4.L , R6.L );
R5 = PACK( R5.L , R6.H );
R6 = PACK( R6.H , R6.L );
R7 = PACK( R7.H , R6.H );
CHECKREG r0, 0x000EABCD;
CHECKREG r1, 0x5678E789;
CHECKREG r2, 0xE345ABCD;
CHECKREG r3, 0xE456E789;
CHECKREG r4, 0x89ABABCD;
CHECKREG r5, 0x9ABCE789;
CHECKREG r6, 0xE789ABCD;
CHECKREG r7, 0xE89AE789;
imm32 r0, 0xf123000f;
imm32 r1, 0xf2345678;
imm32 r2, 0xf3456789;
imm32 r3, 0xf456789a;
imm32 r4, 0xf56789ab;
imm32 r5, 0xf6789abc;
imm32 r6, 0xf789abcd;
imm32 r7, 0xf89abcde;
R0 = PACK( R0.L , R7.L );
R1 = PACK( R1.L , R7.H );
R2 = PACK( R2.H , R7.L );
R3 = PACK( R3.H , R7.H );
R4 = PACK( R4.L , R7.L );
R5 = PACK( R5.L , R7.H );
R6 = PACK( R6.H , R7.L );
R7 = PACK( R7.H , R7.H );
CHECKREG r0, 0x000FBCDE;
CHECKREG r1, 0x5678F89A;
CHECKREG r2, 0xF345BCDE;
CHECKREG r3, 0xF456F89A;
CHECKREG r4, 0x89ABBCDE;
CHECKREG r5, 0x9ABCF89A;
CHECKREG r6, 0xF789BCDE;
CHECKREG r7, 0xF89AF89A;
pass
|
stsp/binutils-ia16
| 2,085
|
sim/testsuite/bfin/s5.s
|
// Test r4 = ROT (r2 by r3);
# mach: bfin
.include "testutils.inc"
start
R0.L = 0x0001;
R0.H = 0x8000;
// rot
// left by 1
// 8000 0001 -> 0000 0002 cc=1
R7 = 0;
CC = R7;
R1 = 1;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// right by -1
// 8000 0001 -> 4000 0000 cc=1
R7 = 0;
CC = R7;
R1.L = 0xffff; // check alternate mechanism for immediates
R1.H = 0xffff;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x4000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// right by largest positive magnitude of 31
// 8000 0001 -> a000 0000 cc=0
R7 = 0;
CC = R7;
R1 = 31;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0xa000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by largest positive magnitude of 31 with cc=1
// 8000 0001 cc=1 -> a000 0000 cc=0
R7 = 1;
CC = R7;
R1 = 31;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0xe000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by largest negative magnitude of -31
// 8000 0001 -> 0000 0005 cc=0
R7 = 0;
CC = R7;
R1 = -31;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0005 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by largest negative magnitude of -31 with cc=1
// 8000 0001 cc=1 -> 0000 0007 cc=0
R7 = 1;
CC = R7;
R1 = -31;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0007 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// left by 7
// 8000 0001 cc=1 -> 0000 00e0 cc=0
R7 = 1;
CC = R7;
R1 = 7;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x00e0 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot by zero
// 8000 0001 -> 8000 0000
R7 = 1;
CC = R7;
R1 = 0;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0001 );
DBGA ( R6.H , 0x8000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot by 0b1100 0001 is the same as by 1 (mask 6 bits)
// 8000 0001 -> 0000 0002 cc=1
R7 = 0;
CC = R7;
R1 = 0xc1 (X);
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
pass
|
stsp/binutils-ia16
| 1,219
|
sim/testsuite/bfin/s10.s
|
// Shifter test program.
// Test instructions
// RL0 = SIGNBITS R1;
// RL0 = SIGNBITS RL1;
// RL0 = SIGNBITS RH1;
# mach: bfin
.include "testutils.inc"
start
// on 32-b word
R1.L = 0xffff;
R1.H = 0x7fff;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0000 );
R1.L = 0xffff;
R1.H = 0x30ff;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0001 );
R1.L = 0xff0f;
R1.H = 0x10ff;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0002 );
R1.L = 0xff0f;
R1.H = 0xe0ff;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0002 );
R1.L = 0x0001;
R1.H = 0x0000;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0001e );
R1.L = 0xfffe;
R1.H = 0xffff;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0001e );
R1.L = 0xffff; // return largest norm for -1
R1.H = 0xffff;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x0001f );
R1.L = 0; // return largest norm for zero
R1.H = 0;
R0.L = SIGNBITS R1;
DBGA ( R0.L , 0x001f );
// on 16-b word
R1.L = 0x7fff;
R1.H = 0xffff;
R0.L = SIGNBITS R1.L;
DBGA ( R0.L , 0x0000 );
R1.L = 0x0fff;
R1.H = 0x0001;
R0.L = SIGNBITS R1.H;
DBGA ( R0.L , 0x000e );
R1.L = 0x0fff;
R1.H = 0xffff;
R0.L = SIGNBITS R1.H;
DBGA ( R0.L , 0x000f );
R1.L = 0x0fff;
R1.H = 0xfffe;
R0.L = SIGNBITS R1.H;
DBGA ( R0.L , 0x000e );
pass
|
stsp/binutils-ia16
| 8,862
|
sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp_s.s
|
//Original:/testcases/core/c_dsp32shiftim_ahalf_rp_s/c_dsp32shiftim_ahalf_rp_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00010001;
imm32 r2, 0x00010002;
imm32 r3, 0x00010003;
imm32 r4, 0x00010004;
imm32 r5, 0x00010005;
imm32 r6, 0x00010006;
imm32 r7, 0x00010007;
R0.L = R0.L >>> 1;
R1.L = R1.L >>> 1;
R2.L = R2.L >>> 1;
R3.L = R3.L >>> 1;
R4.L = R4.L >>> 1;
R5.L = R5.L >>> 1;
R6.L = R6.L >>> 1;
R7.L = R7.L >>> 1;
CHECKREG r0, 0x0000FFFF;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00010001;
CHECKREG r3, 0x00010001;
CHECKREG r4, 0x00010002;
CHECKREG r5, 0x00010002;
CHECKREG r6, 0x00010003;
CHECKREG r7, 0x00010003;
imm32 r0, 0x00201001;
R1.L = -1;
imm32 r2, 0x00202002;
imm32 r3, 0x00203003;
imm32 r4, 0x00204004;
imm32 r5, 0x00205005;
imm32 r6, 0x00206006;
imm32 r7, 0x00207007;
R7.L = R0.L >>> 5;
R0.L = R1.L >>> 5;
R1.L = R2.L >>> 5;
R2.L = R3.L >>> 5;
R3.L = R4.L >>> 5;
R4.L = R5.L >>> 5;
R5.L = R6.L >>> 5;
R6.L = R7.L >>> 5;
CHECKREG r0, 0x0020FFFF;
CHECKREG r1, 0x00010100;
CHECKREG r2, 0x00200180;
CHECKREG r3, 0x00200200;
CHECKREG r4, 0x00200280;
CHECKREG r5, 0x00200300;
CHECKREG r6, 0x00200004;
CHECKREG r7, 0x00200080;
imm32 r0, 0x03001001;
imm32 r1, 0x03001001;
R2.L = -15;
imm32 r3, 0x03003003;
imm32 r4, 0x03004004;
imm32 r5, 0x03005005;
imm32 r6, 0x03006006;
imm32 r7, 0x03007007;
R6.L = R0.L >>> 2;
R7.L = R1.L >>> 2;
R0.L = R2.L >>> 2;
R1.L = R3.L >>> 2;
R2.L = R4.L >>> 2;
R3.L = R5.L >>> 2;
R4.L = R6.L >>> 2;
R5.L = R7.L >>> 2;
CHECKREG r0, 0x0300FFFC;
CHECKREG r1, 0x03000C00;
CHECKREG r2, 0x00201001;
CHECKREG r3, 0x03001401;
CHECKREG r4, 0x03000100;
CHECKREG r5, 0x03000100;
CHECKREG r6, 0x03000400;
CHECKREG r7, 0x03000400;
imm32 r0, 0x40001001;
imm32 r1, 0x40001001;
imm32 r2, 0x40002002;
R3.L = -16;
imm32 r4, 0x40004004;
imm32 r5, 0x40005005;
imm32 r6, 0x40006006;
imm32 r7, 0x40007007;
R5.L = R0.L >>> 13;
R6.L = R1.L >>> 13;
R7.L = R2.L >>> 13;
R0.L = R3.L >>> 13;
R1.L = R4.L >>> 13;
R2.L = R5.L >>> 13;
R3.L = R6.L >>> 13;
R4.L = R7.L >>> 13;
CHECKREG r0, 0x4000FFFF;
CHECKREG r1, 0x40000002;
CHECKREG r2, 0x40000000;
CHECKREG r3, 0x03000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x40000000;
CHECKREG r6, 0x40000000;
CHECKREG r7, 0x40000001;
// d_lo = ashift (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x50000000;
imm32 r1, 0x50010000;
imm32 r2, 0x50020000;
imm32 r3, 0x50030000;
imm32 r4, 0x50040000;
imm32 r5, 0x50050000;
imm32 r6, 0x50060000;
imm32 r7, 0x50070000;
R3.L = R0.H >>> 10;
R4.L = R1.H >>> 10;
R5.L = R2.H >>> 10;
R6.L = R3.H >>> 10;
R7.L = R4.H >>> 10;
R0.L = R5.H >>> 10;
R1.L = R6.H >>> 10;
R2.L = R7.H >>> 10;
CHECKREG r0, 0x50000014;
CHECKREG r1, 0x50010014;
CHECKREG r2, 0x50020014;
CHECKREG r3, 0x50030014;
CHECKREG r4, 0x50040014;
CHECKREG r5, 0x50050014;
CHECKREG r6, 0x50060014;
CHECKREG r7, 0x50070014;
imm32 r0, 0x10016000;
R1.L = -1;
imm32 r2, 0x20026000;
imm32 r3, 0x30036000;
imm32 r4, 0x40046000;
imm32 r5, 0x50056000;
imm32 r6, 0x60060000;
imm32 r7, 0x70076000;
R0.L = R0.H >>> 11;
R1.L = R1.H >>> 11;
R2.L = R2.H >>> 11;
R3.L = R3.H >>> 11;
R4.L = R4.H >>> 11;
R5.L = R5.H >>> 11;
R6.L = R6.H >>> 11;
R7.L = R7.H >>> 11;
CHECKREG r0, 0x10010002;
CHECKREG r1, 0x5001000A;
CHECKREG r2, 0x20020004;
CHECKREG r3, 0x30030006;
CHECKREG r4, 0x40040008;
CHECKREG r5, 0x5005000A;
CHECKREG r6, 0x6006000C;
CHECKREG r7, 0x7007000E;
imm32 r0, 0x10010700;
imm32 r1, 0x10010700;
R2.L = -15;
imm32 r3, 0x30030700;
imm32 r4, 0x40040000;
imm32 r5, 0x50050700;
imm32 r6, 0x60060000;
imm32 r7, 0x70070700;
R0.L = R0.H >>> 15;
R1.L = R1.H >>> 15;
R2.L = R2.H >>> 15;
R3.L = R3.H >>> 15;
R4.L = R4.H >>> 15;
R5.L = R5.H >>> 15;
R6.L = R6.H >>> 15;
R7.L = R7.H >>> 15;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020000;
CHECKREG r3, 0x30030000;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
imm32 r0, 0x18010001;
imm32 r1, 0x18010001;
imm32 r2, 0x28020002;
R3.L = -16;
imm32 r4, 0x48040004;
imm32 r5, 0x58050005;
imm32 r6, 0x68060006;
imm32 r7, 0x78070007;
R0.L = R0.H >>> 13;
R1.L = R1.H >>> 13;
R2.L = R2.H >>> 13;
R3.L = R3.H >>> 13;
R4.L = R4.H >>> 13;
R5.L = R5.H >>> 13;
R6.L = R6.H >>> 13;
R7.L = R7.H >>> 13;
CHECKREG r0, 0x18010000;
CHECKREG r1, 0x18010000;
CHECKREG r2, 0x28020001;
CHECKREG r3, 0x30030001;
CHECKREG r4, 0x48040002;
CHECKREG r5, 0x58050002;
CHECKREG r6, 0x68060003;
CHECKREG r7, 0x78070003;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x09000091;
imm32 r1, 0x09000091;
imm32 r2, 0x09000092;
imm32 r3, 0x09000093;
imm32 r4, 0x09000090;
imm32 r5, 0x09000095;
imm32 r6, 0x09000096;
imm32 r7, 0x09000097;
R0.H = R0.L >>> 14;
R1.H = R1.L >>> 14;
R2.H = R2.L >>> 14;
R3.H = R3.L >>> 14;
R4.H = R4.L >>> 14;
R5.H = R5.L >>> 14;
R6.H = R6.L >>> 14;
R7.H = R7.L >>> 14;
CHECKREG r0, 0x00000091;
CHECKREG r1, 0x00000091;
CHECKREG r2, 0x00000092;
CHECKREG r3, 0x00000093;
CHECKREG r4, 0x00000090;
CHECKREG r5, 0x00000095;
CHECKREG r6, 0x00000096;
CHECKREG r7, 0x00000097;
imm32 r0, 0xa0000001;
imm32 r1, 0xa0000001;
imm32 r2, 0xa0000002;
imm32 r3, 0xa0000003;
imm32 r4, 0xa0000004;
R5.L = -1;
imm32 r6, 0xa0000006;
imm32 r7, 0xa0000007;
R0.H = R0.L >>> 15;
R1.H = R1.L >>> 15;
R2.H = R2.L >>> 15;
R3.H = R3.L >>> 15;
R4.H = R4.L >>> 15;
R5.H = R5.L >>> 15;
R6.H = R6.L >>> 15;
R7.H = R7.L >>> 15;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
imm32 r0, 0xb0001001;
imm32 r1, 0xb0001001;
imm32 r1, 0xb0002002;
imm32 r3, 0xb0003003;
imm32 r4, 0xb0004004;
imm32 r5, 0xb0005005;
R6.L = -15;
imm32 r7, 0xb0007007;
R0.H = R0.L >>> 6;
R1.H = R1.L >>> 6;
R2.H = R2.L >>> 6;
R3.H = R3.L >>> 6;
R4.H = R4.L >>> 6;
R5.H = R5.L >>> 6;
R6.H = R6.L >>> 6;
R7.H = R7.L >>> 6;
CHECKREG r0, 0x00401001;
CHECKREG r1, 0x00802002;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00C03003;
CHECKREG r4, 0x01004004;
CHECKREG r5, 0x01405005;
CHECKREG r6, 0xFFFFFFF1;
CHECKREG r7, 0x01C07007;
imm32 r0, 0x0c001c01;
imm32 r1, 0x0c002c01;
imm32 r2, 0x0c002c02;
imm32 r3, 0x0c003c03;
imm32 r4, 0x0c004c04;
imm32 r5, 0x0c005c05;
imm32 r6, 0x0c006c06;
R7.L = -16;
R0.H = R0.L >>> 7;
R1.H = R1.L >>> 7;
R2.H = R2.L >>> 7;
R3.H = R3.L >>> 7;
R4.H = R4.L >>> 7;
R5.H = R5.L >>> 7;
R6.H = R6.L >>> 7;
R7.H = R7.L >>> 7;
CHECKREG r0, 0x00381C01;
CHECKREG r1, 0x00582C01;
CHECKREG r2, 0x00582C02;
CHECKREG r3, 0x00783C03;
CHECKREG r4, 0x00984C04;
CHECKREG r5, 0x00B85C05;
CHECKREG r6, 0x00D86C06;
CHECKREG r7, 0xFFFFFFF0;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x0d01d000;
imm32 r1, 0x0d01d000;
imm32 r2, 0x0d02d000;
imm32 r3, 0x0d03d000;
R4.L = -1;
imm32 r5, 0x0d05d000;
imm32 r6, 0x0d06d000;
imm32 r7, 0x0d07d000;
R0.H = R0.H >>> 4;
R1.H = R1.H >>> 4;
R2.H = R2.H >>> 4;
R3.H = R3.H >>> 4;
R4.H = R4.H >>> 4;
R5.H = R5.H >>> 4;
R6.H = R6.H >>> 4;
R7.H = R6.H >>> 4;
CHECKREG r0, 0x00D0D000;
CHECKREG r1, 0x00D0D000;
CHECKREG r2, 0x00D0D000;
CHECKREG r3, 0x00D0D000;
CHECKREG r4, 0x0009FFFF;
CHECKREG r5, 0x00D0D000;
CHECKREG r6, 0x00D0D000;
CHECKREG r7, 0x000DD000;
imm32 r0, 0x1e010000;
imm32 r1, 0x1e010000;
imm32 r2, 0x2e020000;
imm32 r3, 0x3e030000;
imm32 r4, 0x4e040000;
R5.L = -1;
imm32 r6, 0x6e060000;
imm32 r7, 0x7e070000;
R7.H = R0.H >>> 15;
R6.H = R1.H >>> 15;
R0.H = R2.H >>> 15;
R1.H = R3.H >>> 15;
R2.H = R4.H >>> 15;
R3.H = R5.H >>> 15;
R4.H = R6.H >>> 15;
R5.H = R7.H >>> 15;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x0000FFFF;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x1f010000;
imm32 r1, 0x1f010000;
imm32 r2, 0x2f020000;
imm32 r3, 0x3f030000;
imm32 r4, 0x4f040000;
imm32 r5, 0x5f050000;
R6.L = -15;
imm32 r7, 0x70070000;
R6.H = R0.H >>> 6;
R7.H = R1.H >>> 6;
R5.H = R2.H >>> 6;
R0.H = R3.H >>> 6;
R1.H = R4.H >>> 6;
R2.H = R5.H >>> 6;
R3.H = R6.H >>> 6;
R4.H = R7.H >>> 6;
CHECKREG r0, 0x00FC0000;
CHECKREG r1, 0x013C0000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00010000;
CHECKREG r4, 0x00010000;
CHECKREG r5, 0x00BC0000;
CHECKREG r6, 0x007CFFF1;
CHECKREG r7, 0x007C0000;
imm32 r0, 0x11010a00;
imm32 r1, 0x11010b00;
imm32 r2, 0x21020d00;
imm32 r2, 0x31030c00;
imm32 r4, 0x41040d00;
imm32 r5, 0x51050e00;
imm32 r6, 0x610600f0;
R7.L = -16;
R5.H = R0.H >>> 7;
R6.H = R1.H >>> 7;
R7.H = R2.H >>> 7;
R2.H = R3.H >>> 7;
R3.H = R4.H >>> 7;
R4.H = R5.H >>> 7;
R0.H = R6.H >>> 7;
R1.H = R7.H >>> 7;
CHECKREG r0, 0x00000A00;
CHECKREG r1, 0x00000B00;
CHECKREG r2, 0x00000C00;
CHECKREG r3, 0x00820000;
CHECKREG r4, 0x00000D00;
CHECKREG r5, 0x00220E00;
CHECKREG r6, 0x002200F0;
CHECKREG r7, 0x0062FFF0;
pass
|
stsp/binutils-ia16
| 2,761
|
sim/testsuite/bfin/c_dsp32mac_dr_a0_iu.s
|
//Original:/testcases/core/c_dsp32mac_dr_a0_iu/c_dsp32mac_dr_a0_iu.dsp
// Spec Reference: dsp32mac dr a0 iu (unsigned int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x83545abd;
imm32 r1, 0x78bcfec7;
imm32 r2, 0xc7948679;
imm32 r3, 0xd0799007;
imm32 r4, 0xefb79569;
imm32 r5, 0xcd35700b;
imm32 r6, 0xe00c877d;
imm32 r7, 0xf78e9097;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L );
R3 = A0.w;
A1 = R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H );
R5 = A0.w;
A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0x8354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xC794315B;
CHECKREG r3, 0x315B6A18;
CHECKREG r4, 0xEFB72AE5;
CHECKREG r5, 0x2AE51252;
CHECKREG r6, 0xE00C32D9;
CHECKREG r7, 0x32D896FE;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0xc5548abd;
imm32 r1, 0x7b5cfec7;
imm32 r2, 0xa1b55679;
imm32 r3, 0xb00b5007;
imm32 r4, 0xcfbcb5c9;
imm32 r5, 0x5235cb5c;
imm32 r6, 0xe50c50b8;
imm32 r7, 0x675e750b;
R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H );
R3 = A0.w;
R4.L = ( A0 -= R4.H * R5.L );
R5 = A0.w;
R6.L = ( A0 = R6.H * R7.H );
R7 = A0.w;
CHECKREG r0, 0xC554011F;
CHECKREG r1, 0x011EBDD6;
CHECKREG r2, 0xA1B5CB1B;
CHECKREG r3, 0xCB1A8C3C;
CHECKREG r4, 0xCFBCB741;
CHECKREG r5, 0xB741151C;
CHECKREG r6, 0xE50CEA3C;
CHECKREG r7, 0xEA3BDCD0;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x4b54babd;
imm32 r1, 0xbabcdec7;
imm32 r2, 0xa4bbe679;
imm32 r3, 0x8abdb007;
imm32 r4, 0x9f4b7b69;
imm32 r5, 0xa23487bb;
imm32 r6, 0xb00c488b;
imm32 r7, 0xc78ea4b8;
R0.L = ( A0 -= R1.L * R0.L );
R1 = A0.w;
R2.L = ( A0 = R2.H * R3.L );
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.H );
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0x4B54D842;
CHECKREG r1, 0xD841BEFA;
CHECKREG r2, 0xA4BB3906;
CHECKREG r3, 0x3906223A;
CHECKREG r4, 0x9F4B46DE;
CHECKREG r5, 0x46DDA278;
CHECKREG r6, 0xB00C26E0;
CHECKREG r7, 0x26E036AC;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x1a545abd;
imm32 r1, 0x52fcfec7;
imm32 r2, 0xc13f5679;
imm32 r3, 0x9c04f007;
imm32 r4, 0xafccec69;
imm32 r5, 0xd23c5e1b;
imm32 r6, 0xc00cc6e2;
imm32 r7, 0x678edc7e;
A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L );
R3 = A0.w;
A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L );
R7 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H );
R5 = A0.w;
A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H );
R1 = A0.w;
CHECKREG r0, 0x1A544DFA;
CHECKREG r1, 0x4DFA5880;
CHECKREG r2, 0xC13F2602;
CHECKREG r3, 0x26025482;
CHECKREG r4, 0xAFCC1CAD;
CHECKREG r5, 0x1CAD17A0;
CHECKREG r6, 0xC00C4F71;
CHECKREG r7, 0x4F70B886;
pass
|
stsp/binutils-ia16
| 2,682
|
sim/testsuite/bfin/c_dsp32shift_vmaxvmax.s
|
//Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp
// Spec Reference: dsp32shift vmax / vmax
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x11002001;
imm32 r1, 0x12001001;
imm32 r2, 0x11301302;
imm32 r3, 0x43001003;
imm32 r4, 0x11601604;
imm32 r5, 0x71001705;
imm32 r6, 0x81008006;
imm32 r7, 0x1900b007;
A0 = R3;
R1 = VIT_MAX( R1 , R0 ) (ASL);
R2 = VIT_MAX( R2 , R1 ) (ASL);
R3 = VIT_MAX( R3 , R2 ) (ASL);
R4 = VIT_MAX( R4 , R3 ) (ASL);
R5 = VIT_MAX( R5 , R4 ) (ASL);
R6 = VIT_MAX( R6 , R5 ) (ASL);
R7 = VIT_MAX( R7 , R6 ) (ASL);
R0 = VIT_MAX( R0 , R7 ) (ASL);
CHECKREG r0, 0x20018100;
CHECKREG r1, 0x12002001;
CHECKREG r2, 0x13022001;
CHECKREG r3, 0x43002001;
CHECKREG r4, 0x16044300;
CHECKREG r5, 0x71004300;
CHECKREG r6, 0x81007100;
CHECKREG r7, 0x19008100;
imm32 r0, 0x11002001;
imm32 r1, 0xd2001001;
imm32 r2, 0x14301302;
imm32 r3, 0x43001003;
imm32 r4, 0x11f01604;
imm32 r5, 0xb1001705;
imm32 r6, 0xd1008006;
imm32 r7, 0x39056707;
R1 = VIT_MAX( R1 , R3 ) (ASL);
R2 = VIT_MAX( R2 , R4 ) (ASL);
R3 = VIT_MAX( R3 , R6 ) (ASL);
R4 = VIT_MAX( R4 , R5 ) (ASL);
R5 = VIT_MAX( R5 , R7 ) (ASL);
R6 = VIT_MAX( R6 , R0 ) (ASL);
R7 = VIT_MAX( R7 , R1 ) (ASL);
R0 = VIT_MAX( R0 , R2 ) (ASL);
CHECKREG r0, 0x20011604;
CHECKREG r1, 0x10014300;
CHECKREG r2, 0x14301604;
CHECKREG r3, 0x4300D100;
CHECKREG r4, 0x16041705;
CHECKREG r5, 0x17056707;
CHECKREG r6, 0xD1002001;
CHECKREG r7, 0x67074300;
imm32 r0, 0xa1011001;
imm32 r1, 0x1b002001;
imm32 r2, 0x81c01302;
imm32 r3, 0x910d1403;
imm32 r4, 0x2100e504;
imm32 r5, 0x31007f65;
imm32 r6, 0x41007006;
imm32 r7, 0x15001801;
R1 = VIT_MAX( R1 , R0 ) (ASR);
R2 = VIT_MAX( R2 , R1 ) (ASR);
R3 = VIT_MAX( R3 , R2 ) (ASR);
R4 = VIT_MAX( R4 , R3 ) (ASR);
R5 = VIT_MAX( R5 , R4 ) (ASR);
R6 = VIT_MAX( R6 , R5 ) (ASR);
R7 = VIT_MAX( R7 , R6 ) (ASR);
R0 = VIT_MAX( R0 , R7 ) (ASR);
CHECKREG r0, 0x1001910D;
CHECKREG r1, 0x20011001;
CHECKREG r2, 0x81C02001;
CHECKREG r3, 0x910D81C0;
CHECKREG r4, 0x2100910D;
CHECKREG r5, 0x7F65910D;
CHECKREG r6, 0x7006910D;
CHECKREG r7, 0x1801910D;
imm32 r0, 0xe1011001;
imm32 r1, 0x4b002001;
imm32 r2, 0x8fc01302;
imm32 r3, 0x910d1403;
imm32 r4, 0xb100e504;
imm32 r5, 0x41007f65;
imm32 r6, 0xaf007006;
imm32 r7, 0x16001801;
R0 = VIT_MAX( R4 , R0 ) (ASR);
R1 = VIT_MAX( R5 , R1 ) (ASR);
R2 = VIT_MAX( R6 , R2 ) (ASR);
R3 = VIT_MAX( R7 , R3 ) (ASR);
R4 = VIT_MAX( R0 , R4 ) (ASR);
R5 = VIT_MAX( R1 , R5 ) (ASR);
R6 = VIT_MAX( R2 , R6 ) (ASR);
R7 = VIT_MAX( R3 , R7 ) (ASR);
CHECKREG r0, 0xE5041001;
CHECKREG r1, 0x7F654B00;
CHECKREG r2, 0xAF008FC0;
CHECKREG r3, 0x1801910D;
CHECKREG r4, 0x1001E504;
CHECKREG r5, 0x7F657F65;
CHECKREG r6, 0xAF00AF00;
CHECKREG r7, 0x910D1801;
pass
|
stsp/binutils-ia16
| 1,384
|
sim/testsuite/bfin/issue139.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
ASTAT = R0;
R0.L = 0x33;
R0.H = 0x55;
R1.L = 0x66;
R1.H = 0x77;
R7 = R1 +|+ R0, R6 = R1 -|- R0 (SCO , ASR);
_DBG R7;
CHECKREG R7, 0x0066004c;
CHECKREG R6, 0x00190011;
R7 = ASTAT
CHECKREG R7, 0;
//-----------------------
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
R0.L = 0x33;
R0.H = 0x55;
R1.L = 0x66;
R1.H = 0x77;
R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASR);
R7 = ASTAT;
CHECKREG R7, 0;
//-----------------------
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
R0.L = 0x33;
R0.H = 0x55;
R1.L = 0x66;
R1.H = 0x77;
R5 = R1 +|+ R0, R4 = R1 -|- R0 (CO , ASR);
R7 = ASTAT;
CHECKREG R7, 0;
//-----------------------
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
R0.L = 0x33;
R0.H = 0x55;
R1.L = 0x66;
R1.H = 0x77;
R3 = R1 +|+ R0, R2 = R1 -|- R0 (ASL);
CHECKREG R3, 0x01980132;
CHECKREG R2, 0x00440066;
R7 = ASTAT;
CHECKREG R7, 0;
//-----------------------
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
R0.L = 0x33;
R0.H = 0x55;
R1.L = 0x7fff;
R1.H = 0x77;
R3 = R1 +|+ R0, R2 = R1 -|- R0 (S , ASL);
CHECKREG R3, 0x01987fff;
CHECKREG R2, 0x00447fff;
R7 = ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY);
pass
|
stsp/binutils-ia16
| 4,138
|
sim/testsuite/bfin/c_dsp32mac_dr_a1_u.s
|
//Original:/testcases/core/c_dsp32mac_dr_a1_u/c_dsp32mac_dr_a1_u.dsp
// Spec Reference: dsp32mac dr_a1 u (unsigned fraction & unsigned int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbabcfec7;
imm32 r2, 0xc1a48679;
imm32 r3, 0xd00a9007;
imm32 r4, 0xefbca569;
imm32 r5, 0xcd355a0b;
imm32 r6, 0xe00c80ad;
imm32 r7, 0xf78e900a;
R0.H = ( A1 = R6.L * R7.L ), A0 += R6.L * R7.L (FU);
R1 = A1.w;
R2.H = ( A1 = R3.L * R4.H ), A0 = R3.H * R4.L (FU);
R3 = A1.w;
R4.H = ( A1 += R2.H * R5.L ), A0 = R2.H * R5.H (FU);
R5 = A1.w;
R6.H = ( A1 += R0.H * R1.H ), A0 += R0.L * R1.H (FU);
R7 = A1.w;
CHECKREG r0, 0x48665ABD;
CHECKREG r1, 0x486656C2;
CHECKREG r2, 0x86E08679;
CHECKREG r3, 0x86E04E24;
CHECKREG r4, 0xB651A569;
CHECKREG r5, 0xB650D9C4;
CHECKREG r6, 0xCACA80AD;
CHECKREG r7, 0xCACA6268;
imm32 r0, 0x03545abd;
imm32 r1, 0x1abcfec7;
imm32 r2, 0xc2a48679;
imm32 r3, 0x300a9007;
imm32 r4, 0x54bca569;
imm32 r5, 0x6d355a0b;
imm32 r6, 0x700c80ad;
imm32 r7, 0x878e900a;
R0.H = ( A1 -= R6.L * R7.L ), A0 += R6.L * R7.L (FU);
R1 = A1.w;
R2.H = ( A1 -= R3.L * R4.H ), A0 = R3.H * R4.L (FU);
R3 = A1.w;
R4.H = ( A1 += R2.H * R5.L ), A0 -= R2.H * R5.H (FU);
R5 = A1.w;
R6.H = ( A1 -= R0.H * R1.H ), A0 += R0.L * R1.H (FU);
R7 = A1.w;
CHECKREG r0, 0x82645ABD;
CHECKREG r1, 0x82640BA6;
CHECKREG r2, 0x52B88679;
CHECKREG r3, 0x52B7FA82;
CHECKREG r4, 0x6FD0A569;
CHECKREG r5, 0x6FD0386A;
CHECKREG r6, 0x2D6780AD;
CHECKREG r7, 0x2D66815A;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0xb3548abd;
imm32 r1, 0x7bbcfec7;
imm32 r2, 0xa1b45679;
imm32 r3, 0xb00b9007;
imm32 r4, 0xcfbcb569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00cabbd;
imm32 r7, 0x678e700b;
R0.H = ( A1 = R1.L * R0.L ) (FU);
R1 = A1.w;
R2.H = ( A1 = R2.L * R6.H ) (FU);
R3 = A1.w;
R4.H = ( A1 += R3.H * R5.L ) (FU);
R5 = A1.w;
R6.H = ( A1 = R4.H * R7.H ) (FU);
R7 = A1.w;
CHECKREG r0, 0x8A138ABD;
CHECKREG r1, 0x8A135EEB;
CHECKREG r2, 0x4BAE5679;
CHECKREG r3, 0x4BADEDAC;
CHECKREG r4, 0x8473B569;
CHECKREG r5, 0x8472EE1B;
CHECKREG r6, 0x3594ABBD;
CHECKREG r7, 0x3593BCCA;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0xc354babd;
imm32 r1, 0x6cbcdec7;
imm32 r2, 0x71c4e679;
imm32 r3, 0x800c7007;
imm32 r4, 0x9fbcc569;
imm32 r5, 0xa2359c0b;
imm32 r6, 0xb00c30cd;
imm32 r7, 0xc78ea00c;
R0.H = A1 , A0 = R1.L * R0.L (FU);
R1 = A1.w;
R2.H = A1 , A0 = R2.H * R3.L (FU);
R3 = A1.w;
R4.H = A1 , A0 = R4.H * R5.H (FU);
R5 = A1.w;
R6.H = A1 , A0 = R6.L * R7.H (FU);
R7 = A1.w;
CHECKREG r0, 0x3594BABD;
CHECKREG r1, 0x3593BCCA;
CHECKREG r2, 0x3594E679;
CHECKREG r3, 0x3593BCCA;
CHECKREG r4, 0x3594C569;
CHECKREG r5, 0x3593BCCA;
CHECKREG r6, 0x359430CD;
CHECKREG r7, 0x3593BCCA;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xd3545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71d45679;
imm32 r3, 0x900d0007;
imm32 r4, 0xafbcd569;
imm32 r5, 0xd2359d0b;
imm32 r6, 0xc00ca0dd;
imm32 r7, 0x678ed00d;
R0.H = ( A1 = R1.L * R2.L ) (M), A0 += R1.L * R2.L (FU);
R1 = A1.w;
R2.H = ( A1 = R3.L * R4.H ) (M), A0 = R3.H * R4.L (FU);
R3 = A1.w;
R4.H = ( A1 = R5.H * R6.L ) (M), A0 += R5.H * R6.H (FU);
R5 = A1.w;
R6.H = ( A1 += R7.H * R0.H ) (M), A0 += R7.L * R0.H (FU);
R7 = A1.w;
CHECKREG r0, 0xFF965ABD;
CHECKREG r1, 0xFF96460F;
CHECKREG r2, 0x00055679;
CHECKREG r3, 0x0004CE24;
CHECKREG r4, 0xE33AD569;
CHECKREG r5, 0xE33997C1;
CHECKREG r6, 0x4A9DA0DD;
CHECKREG r7, 0x4A9CB6F5;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0xe3545abd;
imm32 r1, 0xaebcfec7;
imm32 r2, 0xc1e45679;
imm32 r3, 0x1c0e0007;
imm32 r4, 0xe1cce569;
imm32 r5, 0x921c0e0b;
imm32 r6, 0x790190ed;
imm32 r7, 0x679e900e;
R0.H = ( A1 = R1.L * R0.L ) (M,FU);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M,FU);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ) (M,FU);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M,FU);
R7 = A1.w;
CHECKREG r0, 0xFF915ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x090B5679;
CHECKREG r3, 0x090B0589;
CHECKREG r4, 0x0763E569;
CHECKREG r5, 0x0762E14D;
CHECKREG r6, 0x30FA90ED;
CHECKREG r7, 0x30FA159E;
pass
|
stsp/binutils-ia16
| 7,129
|
sim/testsuite/bfin/c_ldstpmod_st_dr_hi.s
|
//Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp
// Spec Reference: c_ldstpmod store dreg hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;
imm32 r2, 0x800d7002;
imm32 r3, 0x900c8003;
imm32 r4, 0xa00b9004;
imm32 r5, 0xb00aa005;
imm32 r6, 0xc009b006;
imm32 r7, 0xd008c007;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x02;
loadsym i1, DATA_ADDR_3, 0x04;
loadsym p4, DATA_ADDR_4, 0x06;
loadsym p5, DATA_ADDR_5, 0x08;
loadsym fp, DATA_ADDR_6, 0x0a;
loadsym i3, DATA_ADDR_7, 0x0c;
P3 = I1; SP = I3;
W [ P1 ] = R1.H;
W [ P2 ] = R2.H;
W [ P3 ] = R3.H;
W [ P4 ] = R4.H;
W [ P5 ] = R5.H;
W [ SP ] = R6.H;
W [ FP ] = R0.H;
R6.H = W [ P1 ];
R5.H = W [ P2 ];
R4.H = W [ P3 ];
R3.H = W [ P4 ];
R2.H = W [ P5 ];
R0.H = W [ SP ];
R1.H = W [ FP ];
CHECKREG r0, 0xC0095000;
CHECKREG r1, 0x600F6001;
CHECKREG r2, 0xB00A7002;
CHECKREG r3, 0xA00B8003;
CHECKREG r4, 0x900C9004;
CHECKREG r5, 0x800DA005;
CHECKREG r6, 0x700EB006;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x0c;
loadsym p2, DATA_ADDR_2, 0x0a;
loadsym i1, DATA_ADDR_3, 0x08;
loadsym p4, DATA_ADDR_4, 0x06;
loadsym p5, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x02;
loadsym i3, DATA_ADDR_7, 0x00;
P3 = I1; SP = I3;
W [ P1 ] = R2.H;
W [ P2 ] = R3.H;
W [ P3 ] = R4.H;
W [ P4 ] = R5.H;
W [ P5 ] = R6.H;
W [ SP ] = R7.H;
W [ FP ] = R1.H;
R1.L = W [ P1 ];
R2.L = W [ P2 ];
R3.L = W [ P3 ];
R4.L = W [ P4 ];
R5.L = W [ P5 ];
R6.L = W [ SP ];
R0.L = W [ FP ];
CHECKREG r0, 0x105F204E;
CHECKREG r1, 0x204E3003;
CHECKREG r2, 0x3003402C;
CHECKREG r3, 0x402C501B;
CHECKREG r4, 0x501B600A;
CHECKREG r5, 0x600A7019;
CHECKREG r6, 0x7019D028;
// initial values
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x12345675;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x10;
loadsym p2, DATA_ADDR_2, 0x02;
loadsym i1, DATA_ADDR_3, 0x00;
loadsym p4, DATA_ADDR_4, 0x08;
loadsym p5, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x06;
loadsym i3, DATA_ADDR_7, 0x02;
P3 = I1; SP = I3;
W [ P1 ] = R5.H;
W [ P2 ] = R6.H;
W [ P3 ] = R7.H;
W [ P4 ] = R0.H;
W [ P5 ] = R1.H;
W [ SP ] = R2.H;
W [ FP ] = R3.H;
R5.H = W [ P1 ];
R4.H = W [ P2 ];
R3.H = W [ P3 ];
R2.H = W [ P4 ];
R1.H = W [ P5 ];
R0.H = W [ SP ];
R6.H = W [ FP ];
CHECKREG r0, 0x30BD50B0;
CHECKREG r1, 0x20BE60B1;
CHECKREG r2, 0x10BF70B2;
CHECKREG r3, 0x80B880B3;
CHECKREG r4, 0x70B990B4;
CHECKREG r5, 0x12345675;
CHECKREG r6, 0x40BCB0B6;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 5,914
|
sim/testsuite/bfin/c_dsp32alu_rh_m.s
|
//Original:/testcases/core/c_dsp32alu_rh_m/c_dsp32alu_rh_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x89678911;
imm32 r1, 0x2189ab1d;
imm32 r2, 0x34145515;
imm32 r3, 0x46617717;
imm32 r4, 0x5678191b;
imm32 r5, 0x6789a11d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667771;
R0.H = R0.L - R0.L (NS);
R1.H = R0.L - R1.H (NS);
R2.H = R0.H - R2.L (NS);
R3.H = R0.H - R3.H (NS);
R4.H = R0.L - R4.L (NS);
R5.H = R0.L - R5.H (NS);
R6.H = R0.H - R6.L (NS);
R7.H = R0.H - R7.H (NS);
CHECKREG r4, 0x6FF6191B;
CHECKREG r5, 0x2188A11D;
CHECKREG r6, 0xAAEB5515;
CHECKREG r7, 0x799A7771;
CHECKREG r4, 0x6FF6191B;
CHECKREG r5, 0x2188A11D;
CHECKREG r6, 0xAAEB5515;
CHECKREG r7, 0x799A7771;
imm32 r0, 0x25678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x38445515;
imm32 r3, 0x468a7717;
imm32 r4, 0x5678e91b;
imm32 r5, 0x6789af1d;
imm32 r6, 0x744455f5;
imm32 r7, 0x8666777f;
R0.H = R1.L - R0.L (NS);
R1.H = R1.L - R1.H (NS);
R2.H = R1.H - R2.L (NS);
R3.H = R1.H - R3.H (NS);
R4.H = R1.L - R4.L (NS);
R5.H = R1.L - R5.H (NS);
R6.H = R1.H - R6.L (NS);
R7.H = R1.H - R7.H (NS);
CHECKREG r4, 0xC202E91B;
CHECKREG r5, 0x4394AF1D;
CHECKREG r6, 0x2D9F55F5;
CHECKREG r7, 0xFD2E777F;
CHECKREG r4, 0xC202E91B;
CHECKREG r5, 0x4394AF1D;
CHECKREG r6, 0x2D9F55F5;
CHECKREG r7, 0xFD2E777F;
imm32 r0, 0x78678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34885515;
imm32 r3, 0x466aa717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789aa1d;
imm32 r6, 0x74445aa5;
imm32 r7, 0x866677a7;
R0.H = R2.L - R0.L (NS);
R1.H = R2.L - R1.H (NS);
R2.H = R2.H - R2.L (NS);
R3.H = R2.H - R3.H (NS);
R4.H = R2.L - R4.L (NS);
R5.H = R2.L - R5.H (NS);
R6.H = R2.H - R6.L (NS);
R7.H = R2.H - R7.H (NS);
CHECKREG r4, 0xCBFA891B;
CHECKREG r5, 0xED8CAA1D;
CHECKREG r6, 0x84CE5AA5;
CHECKREG r7, 0x590D77A7;
CHECKREG r4, 0xCBFA891B;
CHECKREG r5, 0xED8CAA1D;
CHECKREG r6, 0x84CE5AA5;
CHECKREG r7, 0x590D77A7;
imm32 r0, 0xb5678911;
imm32 r1, 0xb789ab1d;
imm32 r2, 0x3b445515;
imm32 r3, 0x46b67717;
imm32 r4, 0x567b891b;
imm32 r5, 0x6789bb1d;
imm32 r6, 0x74445b15;
imm32 r7, 0x866677b7;
R0.H = R3.L - R0.L (NS);
R1.H = R3.L - R1.H (NS);
R2.H = R3.H - R2.L (NS);
R3.H = R3.H - R3.H (NS);
R4.H = R3.L - R4.L (NS);
R5.H = R3.L - R5.H (NS);
R6.H = R3.H - R6.L (NS);
R7.H = R3.H - R7.H (NS);
CHECKREG r4, 0xEDFC891B;
CHECKREG r5, 0x0F8EBB1D;
CHECKREG r6, 0xA4EB5B15;
CHECKREG r7, 0x799A77B7;
CHECKREG r4, 0xEDFC891B;
CHECKREG r5, 0x0F8EBB1D;
CHECKREG r6, 0xA4EB5B15;
CHECKREG r7, 0x799A77B7;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R4.L - R0.L (NS);
R1.H = R4.L - R1.H (NS);
R2.H = R4.H - R2.L (NS);
R3.H = R4.H - R3.H (NS);
R4.H = R4.L - R4.L (NS);
R5.H = R4.L - R5.H (NS);
R6.H = R4.H - R6.L (NS);
R7.H = R4.H - R7.H (NS);
CHECKREG r4, 0x0000891B;
CHECKREG r5, 0x2192AB1D;
CHECKREG r6, 0xAAEB5515;
CHECKREG r7, 0x799A7777;
CHECKREG r4, 0x0000891B;
CHECKREG r5, 0x2192AB1D;
CHECKREG r6, 0xAAEB5515;
CHECKREG r7, 0x799A7777;
imm32 r0, 0xcc678911;
imm32 r1, 0xc789ab1d;
imm32 r2, 0x3c445515;
imm32 r3, 0x46c67717;
imm32 r4, 0x567c891b;
imm32 r5, 0x6789cb1d;
imm32 r6, 0x74445c15;
imm32 r7, 0x866677c7;
R0.H = R5.L - R0.L (NS);
R1.H = R5.L - R1.H (NS);
R2.H = R5.H - R2.L (NS);
R3.H = R5.H - R3.H (NS);
R4.H = R5.L - R4.L (NS);
R5.H = R5.L - R5.H (NS);
R6.H = R5.H - R6.L (NS);
R7.H = R5.H - R7.H (NS);
CHECKREG r4, 0x4202891B;
CHECKREG r5, 0x6394CB1D;
CHECKREG r6, 0x077F5C15;
CHECKREG r7, 0xDD2E77C7;
CHECKREG r4, 0x4202891B;
CHECKREG r5, 0x6394CB1D;
CHECKREG r6, 0x077F5C15;
CHECKREG r7, 0xDD2E77C7;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R6.L - R0.L (NS);
R1.H = R6.L - R1.H (NS);
R2.H = R6.H - R2.L (NS);
R3.H = R6.H - R3.H (NS);
R4.H = R6.L - R4.L (NS);
R5.H = R6.L - R5.H (NS);
R6.H = R6.H - R6.L (NS);
R7.H = R6.H - R7.H (NS);
CHECKREG r4, 0xCBFA891B;
CHECKREG r5, 0xED8CAB1D;
CHECKREG r6, 0x1F2F5515;
CHECKREG r7, 0x98C97777;
CHECKREG r4, 0xCBFA891B;
CHECKREG r5, 0xED8CAB1D;
CHECKREG r6, 0x1F2F5515;
CHECKREG r7, 0x98C97777;
imm32 r0, 0xd5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667e17;
imm32 r4, 0x56e8891b;
imm32 r5, 0x678eab1d;
imm32 r6, 0x7444e515;
imm32 r7, 0x86667e77;
R0.H = R7.L - R0.L (NS);
R1.H = R7.L - R1.H (NS);
R2.H = R7.H - R2.L (NS);
R3.H = R7.H - R3.H (NS);
R4.H = R7.L - R4.L (NS);
R5.H = R7.L - R5.H (NS);
R6.H = R7.H - R6.L (NS);
R7.H = R7.H - R7.H (NS);
CHECKREG r4, 0xF55C891B;
CHECKREG r5, 0x16E9AB1D;
CHECKREG r6, 0xA151E515;
CHECKREG r7, 0x00007E77;
CHECKREG r4, 0xF55C891B;
CHECKREG r5, 0x16E9AB1D;
CHECKREG r6, 0xA151E515;
CHECKREG r7, 0x00007E77;
imm32 r0, 0xff678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34ff5515;
imm32 r3, 0x4666f717;
imm32 r4, 0x567f891b;
imm32 r5, 0x6789fb1d;
imm32 r6, 0x74445f15;
imm32 r7, 0x866677f7;
R6.H = R2.L - R3.L (S);
R1.H = R4.L - R5.H (S);
R5.H = R7.H - R2.L (S);
R3.H = R0.H - R0.H (S);
R0.H = R3.L - R4.L (S);
R2.H = R5.L - R7.H (S);
R7.H = R6.H - R7.L (S);
R4.H = R1.H - R6.H (S);
CHECKREG r4, 0x8000891B;
CHECKREG r5, 0x8000FB1D;
CHECKREG r6, 0x5DFE5F15;
CHECKREG r7, 0xE60777F7;
CHECKREG r4, 0x8000891B;
CHECKREG r5, 0x8000FB1D;
CHECKREG r6, 0x5DFE5F15;
CHECKREG r7, 0xE60777F7;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R3.H = R4.L - R0.L (S);
R1.H = R6.L - R3.H (S);
R4.H = R3.H - R2.L (S);
R6.H = R7.H - R1.H (S);
R2.H = R5.L - R4.L (S);
R7.H = R2.L - R7.H (S);
R0.H = R1.H - R6.L (S);
R5.H = R0.H - R5.H (S);
CHECKREG r4, 0xAAF5891B;
CHECKREG r5, 0x986DAB1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x7FFF7777;
CHECKREG r4, 0xAAF5891B;
CHECKREG r5, 0x986DAB1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x7FFF7777;
pass
|
stsp/binutils-ia16
| 9,487
|
sim/testsuite/bfin/se_loop_ppm_int.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_int/se_loop_ppm_int.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Sync it!
CSYNC;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
P0 = 0x5 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
CSYNC;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
l3s:[ -- SP ] = ( R7:5 );
R6 += 2;
R7 += 3;
NOP;
CSYNC;
NOP;
NOP;
NOP;
l3e:R5 += 1;
NOP;
LSETUP ( m0s , m0s ) LC1 = P0;
CSYNC;
m0s:[ -- SP ] = ( R7:5 );
LSETUP ( m3s , m3e ) LC1 = P0;
m3s:[ -- SP ] = ( R7:5 );
R6 += 2;
R7 += 3;
NOP;
CSYNC;
NOP;
NOP;
NOP;
m3e:R5 += 1;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 7,454
|
sim/testsuite/bfin/c_dsp32mac_pair_a1a0_u.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_u/c_dsp32mac_pair_a1a0_u.dsp
// Spec Reference: dsp32mac pair a1a0 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (FU);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (FU);
FP = A1.w;
CHECKREG r0, 0x00049ABC;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0x549454CC;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x55A3F173;
CHECKREG r5, 0x07CFA619;
CHECKREG r6, 0x5A4E0EEB;
CHECKREG r7, 0x5A4E0EEB;
CHECKREG p1, 0x5A4E0EEB;
CHECKREG p2, 0x5A4E0EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0x00049ABC;
CHECKREG p5, 0x00000000;
CHECKREG sp, 0x549454CC;
CHECKREG fp, 0x07CFA619;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 -= R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 -= R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (FU);
P2 = A0.w;
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (FU);
P5 = A1.w;
SP = A0.w;
R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x089013D8;
CHECKREG r1, 0x6C5ACAC6;
CHECKREG r2, 0x088458C2;
CHECKREG r3, 0x6C4F0FB0;
CHECKREG r4, 0x0E2DB488;
CHECKREG r5, 0x9996A1D3;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x9996A1D3;
CHECKREG p2, 0x00032564;
CHECKREG p3, 0x99964B8A;
CHECKREG p4, 0x00032564;
CHECKREG p5, 0x6C4F0FB0;
CHECKREG sp, 0x088458C2;
CHECKREG fp, 0x089013D8;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (FU);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 -= R6.L * R7.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x1A2AB610;
CHECKREG r1, 0x24F02BB4;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x0BE761C4;
CHECKREG r5, 0x24F2761C;
CHECKREG r6, 0x0003178C;
CHECKREG r7, 0x9B11C378;
CHECKREG p1, 0x9B14DB04;
CHECKREG p2, 0x2B2D030B;
CHECKREG p3, 0x9B11C378;
CHECKREG p5, 0x24F02BB4;
CHECKREG p4, 0x0003178C;
CHECKREG sp, 0x1A2AB610;
CHECKREG fp, 0x0BE761C4;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 -= R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (FU);
P5 = A1.w;
SP = A0.w;
R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x0003F74D;
CHECKREG r1, 0xD0349621;
CHECKREG r2, 0x63278394;
CHECKREG r3, 0x46B1FE11;
CHECKREG r4, 0x6328BB2E;
CHECKREG r5, 0x46B0C677;
CHECKREG r6, 0x6CB2D756;
CHECKREG r7, 0x4BBE7457;
CHECKREG p1, 0xD0349621;
CHECKREG p2, 0x0003F74D;
CHECKREG p3, 0x46B1FE11;
CHECKREG p4, 0x63278394;
CHECKREG p5, 0x46B0C677;
CHECKREG sp, 0x6328BB2E;
CHECKREG fp, 0x6CB2D756;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (FU);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 -= R6.L * R5.L ) (M), R4 = ( A0 -= R6.L * R5.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x00049ABC;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0x46897C84;
CHECKREG r3, 0x316C7D3D;
CHECKREG r4, 0x4579DFDD;
CHECKREG r5, 0x299CD724;
CHECKREG r6, 0x5A4E0EEB;
CHECKREG r7, 0x4B4F8342;
CHECKREG p1, 0x4B4F8342;
CHECKREG p2, 0x5A4E0EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0x00049ABC;
CHECKREG p5, 0x316C7D3D;
CHECKREG sp, 0x46897C84;
CHECKREG fp, 0x4579DFDD;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = A1, R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R1 = A1, R0 = ( A0 -= R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R3 = A1, R2 = ( A0 += R4.H * R5.H ) (FU);
P5 = A1.w;
SP = A0.w;
R1 = A1, R0 = ( A0 -= R6.L * R7.H ) (FU);
FP = A1.w;
CHECKREG r0, 0x5304CE59;
CHECKREG r1, 0x299CD724;
CHECKREG r2, 0x5310896F;
CHECKREG r3, 0x299CD724;
CHECKREG r4, 0x47763CEB;
CHECKREG r5, 0x299CD724;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x299CD724;
CHECKREG p2, 0x47763CEB;
CHECKREG p3, 0x299CD724;
CHECKREG p4, 0x47731787;
CHECKREG p5, 0x299CD724;
CHECKREG sp, 0x5310896F;
CHECKREG fp, 0x299CD724;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R7 = A1, R6 = ( A0 = R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 -= R4.H * R5.H ) (FU);
P5 = A1.w;
SP = A0.w;
R5 = A1, R4 = ( A0 += R6.L * R7.H ) (FU);
FP = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x2706223A;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x01B8DC2C;
CHECKREG r5, 0x2706223A;
CHECKREG r6, 0x0003178C;
CHECKREG r7, 0x12B9E762;
CHECKREG p1, 0x12B9E762;
CHECKREG p2, 0x2B2D030B;
CHECKREG p3, 0x12B9E762;
CHECKREG p4, 0x0003178C;
CHECKREG p5, 0x2706223A;
CHECKREG sp, 0x00000000;
CHECKREG fp, 0x2706223A;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (FU);
P5 = A0.w;
SP = A1.w;
R7 = A1, R6 = ( A0 += R4.L * R6.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x01B4E4DF;
CHECKREG r1, 0x2706223A;
CHECKREG r2, 0x169AF688;
CHECKREG r3, 0xF2C00278;
CHECKREG r4, 0x174BDCA0;
CHECKREG r5, 0x00B0E618;
CHECKREG r6, 0x228A5420;
CHECKREG r7, 0x00B0E618;
CHECKREG p1, 0x2706223A;
CHECKREG p2, 0x01B4E4DF;
CHECKREG p3, 0xF2C00278;
CHECKREG p4, 0x169AF688;
CHECKREG p5, 0x174BDCA0;
CHECKREG sp, 0x00B0E618;
CHECKREG fp, 0x228A5420;
pass
|
stsp/binutils-ia16
| 7,512
|
sim/testsuite/bfin/c_dsp32mac_pair_a1a0_is.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_is/c_dsp32mac_pair_a1a0_is.dsp
// Spec Reference: dsp32mac pair a1a0 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R4.L * R0.L ), R6 = ( A0 = R4.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R3.L * R1.L ), R0 = ( A0 = R3.H * R1.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R2.L ), R2 = ( A0 += R7.H * R2.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R5.L * R6.L ), R4 = ( A0 += R5.L * R6.H ) (ISS2);
FP = A1.w;
CHECKREG r0, 0xFFFEB854;
CHECKREG r1, 0xFFFFEEE2;
CHECKREG r2, 0xCECAD1AC;
CHECKREG r3, 0xB509D374;
CHECKREG r4, 0x8A4CA32E;
CHECKREG r5, 0x1EC2C250;
CHECKREG r6, 0x47E3910A;
CHECKREG r7, 0x47E3910A;
CHECKREG p1, 0x23F1C885;
CHECKREG p2, 0x23F1C885;
CHECKREG p3, 0xFFFFF771;
CHECKREG p4, 0xFFFF5C2A;
CHECKREG p5, 0xDA84E9BA;
CHECKREG sp, 0xE76568D6;
CHECKREG fp, 0x0F616128;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = ( A1 += R4.L * R0.H ), R4 = ( A0 = R4.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A0.w;
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R5.H ), R2 = ( A0 += R7.H * R5.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R1 = ( A1 += R6.L * R1.H ), R0 = ( A0 += R6.L * R1.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0x0ADC2224;
CHECKREG r1, 0x00001AE2;
CHECKREG r2, 0x0ADC2224;
CHECKREG r3, 0x00001AE2;
CHECKREG r4, 0x0C80510A;
CHECKREG r5, 0x0D712F1C;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x06B8978E;
CHECKREG p2, 0xFFFE2564;
CHECKREG p3, 0x00005649;
CHECKREG p4, 0xFFFE2564;
CHECKREG p5, 0x00000D71;
CHECKREG sp, 0x056E1112;
CHECKREG fp, 0x056E1112;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R7 = ( A1 = R6.H * R3.L ), R6 = ( A0 = R6.H * R3.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R2.H * R7.L ), R4 = ( A0 += R2.L * R7.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0x12E88AAA;
CHECKREG r1, 0xE779EB80;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x12E88AAA;
CHECKREG r5, 0xE79F0610;
CHECKREG r6, 0x0000002A;
CHECKREG r7, 0x0000002A;
CHECKREG p1, 0xE91D1DAF;
CHECKREG p2, 0xE590030B;
CHECKREG p3, 0x00000015;
CHECKREG p5, 0xF3BCF5C0;
CHECKREG p4, 0x00000015;
CHECKREG sp, 0x09744555;
CHECKREG fp, 0x09744555;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0xF897461A;
CHECKREG r2, 0xD0654810;
CHECKREG r3, 0x05083598;
CHECKREG r4, 0xD05F99EC;
CHECKREG r5, 0xFFFA51DC;
CHECKREG r6, 0xC5F8000C;
CHECKREG r7, 0xFB1F80C4;
CHECKREG p1, 0xFC4BA30D;
CHECKREG p2, 0xFFFCF74D;
CHECKREG p3, 0x02841ACC;
CHECKREG p4, 0xE832A408;
CHECKREG p5, 0xFFFD28EE;
CHECKREG sp, 0xE82FCCF6;
CHECKREG fp, 0xE2FC0006;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0xFFFB3578;
CHECKREG r1, 0x0004BA9E;
CHECKREG r2, 0x00B650E8;
CHECKREG r3, 0xB2D59E54;
CHECKREG r4, 0x04F4C384;
CHECKREG r5, 0xD21436B8;
CHECKREG r6, 0xFF221DD6;
CHECKREG r7, 0xFA419E9A;
CHECKREG p1, 0xFD20CF4D;
CHECKREG p2, 0xFF910EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0xFFFD9ABC;
CHECKREG p5, 0xD96ACF2A;
CHECKREG sp, 0x005B2874;
CHECKREG fp, 0x027A61C2;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = A1, R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R1 = A1, R0 = ( A0 = R4.H * R3.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R3 = A1, R2 = ( A0 += R2.H * R5.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R1 = A1, R0 = ( A0 += R6.L * R7.H ) (ISS2);
FP = A1.w;
CHECKREG r0, 0x22252FC0;
CHECKREG r1, 0xD21436B8;
CHECKREG r2, 0x220DB994;
CHECKREG r3, 0xD21436B8;
CHECKREG r4, 0xF97279D6;
CHECKREG r5, 0xD21436B8;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xE90A1B5C;
CHECKREG p2, 0xFCB93CEB;
CHECKREG p3, 0xE90A1B5C;
CHECKREG p4, 0xFFFFDF3A;
CHECKREG p5, 0xE90A1B5C;
CHECKREG sp, 0x1106DCCA;
CHECKREG fp, 0xE90A1B5C;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R7 = A1, R6 = ( A0 = R2.H * R3.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R5 = A1, R4 = ( A0 += R6.L * R7.H ) (ISS2);
FP = A1.w;
CHECKREG r0, 0x25E6F698;
CHECKREG r1, 0xDBFA4500;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x042A6938;
CHECKREG r5, 0xDBFA4500;
CHECKREG r6, 0x00062F18;
CHECKREG r7, 0xA44E5734;
CHECKREG p1, 0xD2272B9A;
CHECKREG p2, 0xE590030B;
CHECKREG p3, 0xD2272B9A;
CHECKREG p4, 0x0003178C;
CHECKREG p5, 0xEDFD2280;
CHECKREG sp, 0x12F37B4C;
CHECKREG fp, 0xEDFD2280;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = A1, R0 = ( A0 = R5.L * R3.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (ISS2);
P5 = A0.w;
SP = A1.w;
R7 = A1, R6 = ( A0 += R4.L * R6.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0xDBFA4500;
CHECKREG r2, 0xD124C800;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xD11F19DC;
CHECKREG r5, 0x7FFFFFFF;
CHECKREG r6, 0xD3C1DE7C;
CHECKREG r7, 0x7FFFFFFF;
CHECKREG p1, 0xEDFD2280;
CHECKREG p2, 0xFFFCF74D;
CHECKREG p3, 0xB54F3988;
CHECKREG p4, 0xE8926400;
CHECKREG p5, 0xE88F8CEE;
CHECKREG sp, 0x67DB28EE;
CHECKREG fp, 0xE9E0EF3E;
pass
|
stsp/binutils-ia16
| 5,800
|
sim/testsuite/bfin/c_dsp32mult_dr.s
|
//Original:/testcases/core/c_dsp32mult_dr/c_dsp32mult_dr.dsp
// Spec Reference: dsp32mult single dr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L;
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H;
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L;
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H;
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L;
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H;
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L;
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H;
CHECKREG r0, 0x39FA39FA;
CHECKREG r1, 0x24C2CEF5;
CHECKREG r2, 0xE9C910A6;
CHECKREG r3, 0x12CA0A8E;
CHECKREG r4, 0x39FA39FA;
CHECKREG r5, 0x369EB722;
CHECKREG r6, 0x369EB722;
CHECKREG r7, 0x33735B96;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L;
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H;
R6.H = R3.L * R2.H, R6.L = R3.L * R2.L;
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H;
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L;
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H;
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L;
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H;
CHECKREG r0, 0xFF31FF31;
CHECKREG r1, 0x00B500B5;
CHECKREG r2, 0xF51DF51D;
CHECKREG r3, 0x09860986;
CHECKREG r4, 0xF51DF51D;
CHECKREG r5, 0x3FAEEF41;
CHECKREG r6, 0xF8DB1B2D;
CHECKREG r7, 0x29CE29CE;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L;
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H;
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L;
R3.H = R5.H * R5.L, R3.L = R5.H * R5.H;
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L;
R5.H = R4.H * R5.L, R5.L = R4.L * R5.H;
R6.H = R5.H * R4.L, R6.L = R5.H * R4.L;
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H;
CHECKREG r0, 0x33491B2A;
CHECKREG r1, 0x0E7AF852;
CHECKREG r2, 0xF852F852;
CHECKREG r3, 0xFDD5022C;
CHECKREG r4, 0x33491B2A;
CHECKREG r5, 0xF955038A;
CHECKREG r6, 0xFE96FE96;
CHECKREG r7, 0xFFD10059;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L;
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H;
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L;
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H;
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L;
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H;
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L;
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H;
CHECKREG r0, 0x7FE82A4A;
CHECKREG r1, 0xEDBCF57F;
CHECKREG r2, 0xEDBCF57F;
CHECKREG r3, 0x029C029C;
CHECKREG r4, 0x12400609;
CHECKREG r5, 0x029B029B;
CHECKREG r6, 0x7FE82A4A;
CHECKREG r7, 0x1243060A;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0.H = R0.L * R7.H (M), R0.L = R0.H * R7.L;
R1.H = R1.H * R6.H, R1.L = R1.H * R6.H;
R2.H = R2.H * R5.L, R2.L = R2.L * R5.L;
R3.H = R3.H * R4.L (M), R3.L = R3.H * R4.L;
R4.H = R4.L * R3.L, R4.L = R4.L * R3.H;
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L;
R6.H = R6.L * R1.H, R6.L = R6.L * R1.L;
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H;
CHECKREG r0, 0xF99C0A92;
CHECKREG r1, 0xFFFBFFFB;
CHECKREG r2, 0xFB31E621;
CHECKREG r3, 0x0005FFFE;
CHECKREG r4, 0x0001FFFE;
CHECKREG r5, 0xFCA1FCA1;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x0182FF16;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R0.H = R7.H * R0.H, R0.L = R7.L * R0.L;
R1.H = R6.H * R1.L (M), R1.L = R6.H * R1.L;
R2.H = R5.H * R2.H, R2.L = R5.L * R2.L;
R3.H = R4.L * R3.H, R3.L = R4.H * R3.L;
R4.H = R3.H * R4.H, R4.L = R3.L * R4.L;
R5.H = R2.H * R5.L (M), R5.L = R2.H * R5.L;
R6.H = R1.L * R6.L, R6.L = R1.L * R6.H;
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H;
CHECKREG r0, 0xF19A4F2D;
CHECKREG r1, 0x00040008;
CHECKREG r2, 0x028DEDD5;
CHECKREG r3, 0xFFF9FFFA;
CHECKREG r4, 0x00060005;
CHECKREG r5, 0x0255FF8F;
CHECKREG r6, 0x00010000;
CHECKREG r7, 0x0B4EFDF2;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H;
R3.H = R1.H * R7.H (M), R3.L = R1.L * R7.L;
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H;
R1.H = R3.H * R1.L, R1.L = R3.L * R1.H;
R4.H = R4.L * R2.L, R4.L = R4.L * R2.H;
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L;
R6.H = R6.H * R4.L (M), R6.L = R6.L * R4.H;
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H;
CHECKREG r0, 0x0005FFA9;
CHECKREG r1, 0xFD80E154;
CHECKREG r2, 0x005F0008;
CHECKREG r3, 0xFC0E4707;
CHECKREG r4, 0xFFF9FFAB;
CHECKREG r5, 0x00B70940;
CHECKREG r6, 0x000C0000;
CHECKREG r7, 0x0819001A;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H;
R6.H = R6.H * R3.L (M), R6.L = R6.L * R3.H;
R0.H = R7.L * R4.H, R0.L = R7.H * R4.H;
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L;
R2.H = R1.H * R6.L (M), R2.L = R1.L * R6.H;
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L;
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H;
R7.H = R4.L * R1.L, R7.L = R4.L * R1.H;
CHECKREG r0, 0xF3ECFE08;
CHECKREG r1, 0xFFBE0044;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x0000FFFF;
CHECKREG r4, 0xF234FD56;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xFFFF0001;
pass
|
stsp/binutils-ia16
| 3,646
|
sim/testsuite/bfin/c_dsp32shift_amix.s
|
//Original:/testcases/core/c_dsp32shift_amix/c_dsp32shift_amix.dsp
// Spec Reference: dsp32shift ashift mix
# mach: bfin
.include "testutils.inc"
start
// Ashift (Arithmetic ) retain the sign bit (0-->0, 1-->1)
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// Ashift : positive data, count (+)=left (half reg)
imm32 r0, 0x00010001;
imm32 r1, 1;
imm32 r2, 0x00020002;
imm32 r3, 2;
R4.H = ASHIFT R0.H BY R1.L;
R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
R5.H = ASHIFT R2.H BY R3.L;
R5.L = ASHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
CHECKREG r4, 0x00020002;
CHECKREG r5, 0x00080008;
CHECKREG r6, 0x00020002;
CHECKREG r7, 0x00080008;
// Ashift : (full reg)
imm32 r1, 3;
imm32 r3, 4;
R6 = ASHIFT R0 BY R1.L; /* r6 = 0x00080010 */
R7 = ASHIFT R2 BY R3.L;
CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
CHECKREG r7, 0x00200020;
A0 = 0;
A0.L = R0.L;
A0.H = R0.H;
A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00080008 */
R5 = A0.w; /* r5 = 0x00080008 */
CHECKREG r5, 0x00080008;
imm32 r4, 0x30000003;
imm32 r1, 1;
R5 = ASHIFT R4 BY R1.L; /* r5 = 0x60000006 */
CHECKREG r5, 0x60000006;
imm32 r1, 2;
R5 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
CHECKREG r5, 0xc000000c;
// Ashift : count (-)=right (half reg)
imm32 r0, 0x10001000;
imm32 r1, -1;
imm32 r2, 0x10001000;
imm32 r3, -2;
R4.H = ASHIFT R0.H BY R1.L;
R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x08000800 */
R5.H = ASHIFT R2.H BY R3.L;
R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x04000400 */
R6 = ASHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */
R7 = ASHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */
CHECKREG r4, 0x08000800;
CHECKREG r5, 0x04000400;
CHECKREG r6, 0x08000800;
CHECKREG r7, 0x04000400;
// Ashift : (full reg)
imm32 r1, -3;
imm32 r3, -4;
R6 = ASHIFT R0 BY R1.L; /* r6 = 0x02000200 */
R7 = ASHIFT R2 BY R3.L; /* r7 = 0x01000100 */
CHECKREG r6, 0x02000200;
CHECKREG r7, 0x01000100;
// NEGATIVE
// Ashift : NEGATIVE data, count (+)=left (half reg)
imm32 r0, 0xc00f800f;
imm32 r1, 1;
imm32 r2, 0xe00fe00f;
imm32 r3, 2;
R4.H = ASHIFT R0.H BY R1.L;
R4.L = ASHIFT R0.L BY R1.L (S); /* r4 = 0x801e801e */
R5.H = ASHIFT R2.H BY R3.L;
R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x803c803c */
CHECKREG r4, 0x801e8000;
CHECKREG r5, 0x803c803c;
imm32 r0, 0xc80fe00f;
imm32 r2, 0xe40fe00f;
imm32 r1, 4;
imm32 r3, 5;
R6 = ASHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
R7 = ASHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
CHECKREG r6, 0x80fe00f0;
CHECKREG r7, 0x81fc01e0;
imm32 r0, 0xf80fe00f;
imm32 r2, 0xfc0fe00f;
R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80fe00f0 */
R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x81fc01e0 */
CHECKREG r6, 0x80fe00f0;
CHECKREG r7, 0x81fc01e0;
imm32 r0, 0xc80fe00f;
imm32 r2, 0xe40fe00f;
R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80000000 zero bubble tru MSB */
R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x80000000 */
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok
imm32 r0, 0x80f080f0;
imm32 r1, -1;
imm32 r2, 0x80f080f0;
imm32 r3, -2;
R4.H = ASHIFT R0.H BY R1.L;
R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0xc078c078 */
R5.H = ASHIFT R2.H BY R3.L;
R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0xe03ce03c */
CHECKREG r4, 0xc078c078;
CHECKREG r5, 0xe03ce03c;
R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0xc078c078 */
R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0xe03ce03c */
CHECKREG r6, 0xc078c078;
CHECKREG r7, 0xe03ce03c;
// Ashift : (full reg)
imm32 r1, -3;
imm32 r3, -4;
R6 = ASHIFT R0 BY R1.L; /* r6 = 0xf01e101e */
R7 = ASHIFT R2 BY R3.L; /* r7 = 0xf80f080f */
CHECKREG r6, 0xf01e101e;
CHECKREG r7, 0xf80f080f;
pass
|
stsp/binutils-ia16
| 2,474
|
sim/testsuite/bfin/c_logi2op_bitset.s
|
//Original:/testcases/core/c_logi2op_bitset/c_logi2op_bitset.dsp
// Spec Reference: Logi2op
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// bit set
BITSET( R0 , 0 ); /* r0 = 0x00000001 */
BITSET( R1 , 1 ); /* r1 = 0x00000002 */
BITSET( R2 , 2 ); /* r2 = 0x00000004 */
BITSET( R3 , 3 ); /* r3 = 0x00000008 */
BITSET( R4 , 4 ); /* r4 = 0x00000010 */
BITSET( R5 , 5 ); /* r5 = 0x00000020 */
BITSET( R6 , 6 ); /* r6 = 0x00000040 */
BITSET( R7 , 7 ); /* r7 = 0x00000080 */
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000004;
CHECKREG r3, 0x00000008;
CHECKREG r4, 0x00000010;
CHECKREG r5, 0x00000020;
CHECKREG r6, 0x00000040;
CHECKREG r7, 0x00000080;
// bit set
BITSET( R0 , 8 ); /* r0 = 0x00000100 */
BITSET( R1 , 9 ); /* r1 = 0x00000200 */
BITSET( R2 , 10 ); /* r2 = 0x00000400 */
BITSET( R3 , 11 ); /* r3 = 0x00000800 */
BITSET( R4 , 12 ); /* r4 = 0x00001000 */
BITSET( R5 , 13 ); /* r5 = 0x00002000 */
BITSET( R6 , 14 ); /* r6 = 0x00004000 */
BITSET( R7 , 15 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x00000101;
CHECKREG r1, 0x00000202;
CHECKREG r2, 0x00000404;
CHECKREG r3, 0x00000808;
CHECKREG r4, 0x00001010;
CHECKREG r5, 0x00002020;
CHECKREG r6, 0x00004040;
CHECKREG r7, 0x00008080;
// bit set
BITSET( R0 , 16 ); /* r0 = 0x00000100 */
BITSET( R1 , 17 ); /* r1 = 0x00000200 */
BITSET( R2 , 18 ); /* r2 = 0x00000400 */
BITSET( R3 , 19 ); /* r3 = 0x00000800 */
BITSET( R4 , 20 ); /* r4 = 0x00001000 */
BITSET( R5 , 21 ); /* r5 = 0x00002000 */
BITSET( R6 , 22 ); /* r6 = 0x00004000 */
BITSET( R7 , 23 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x00010101;
CHECKREG r1, 0x00020202;
CHECKREG r2, 0x00040404;
CHECKREG r3, 0x00080808;
CHECKREG r4, 0x00101010;
CHECKREG r5, 0x00202020;
CHECKREG r6, 0x00404040;
CHECKREG r7, 0x00808080;
// bit set
BITSET( R0 , 24 ); /* r0 = 0x00000100 */
BITSET( R1 , 25 ); /* r1 = 0x00000200 */
BITSET( R2 , 26 ); /* r2 = 0x00000400 */
BITSET( R3 , 27 ); /* r3 = 0x00000800 */
BITSET( R4 , 28 ); /* r4 = 0x00001000 */
BITSET( R5 , 29 ); /* r5 = 0x00002000 */
BITSET( R6 , 30 ); /* r6 = 0x00004000 */
BITSET( R7 , 31 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x01010101;
CHECKREG r1, 0x02020202;
CHECKREG r2, 0x04040404;
CHECKREG r3, 0x08080808;
CHECKREG r4, 0x10101010;
CHECKREG r5, 0x20202020;
CHECKREG r6, 0x40404040;
CHECKREG r7, 0x80808080;
pass
|
stsp/binutils-ia16
| 2,559
|
sim/testsuite/bfin/random_0010.S
|
# Test logical left shift (vector) insns with larger shift values
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN);
imm32 R5, 0xb0b40000;
imm32 R6, 0xf43a5d3c;
R6 = R5 << 0x19 (V, S);
checkreg R6, 0xff610000;
checkreg ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ);
dmm32 ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN);
imm32 R2, 0xff2abd08;
imm32 R5, 0xf610ffff;
R2 = R5 << 0x11 (V, S);
checkreg R2, 0xffffffff;
checkreg ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN);
dmm32 ASTAT, (0x6cd0c680 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x760ecf8e;
imm32 R1, 0x3f5c8af5;
R0 = R1 << 0x17 (V, S);
checkreg R0, 0x001fffc5;
checkreg ASTAT, (0x6cd0c680 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC);
imm32 R4, 0x520cb3d4;
imm32 R6, 0x67141e28;
R6 = R4 << 0x14 (V, S);
checkreg R6, 0x0005fffb;
checkreg ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AN);
dmm32 ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN);
imm32 R3, 0x40407f7e;
imm32 R4, 0xc081e040;
R3 = R4 << 0x1a (V, S);
checkreg R3, 0xff02ff81;
checkreg ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN);
dmm32 ASTAT, (0x04f00490 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY);
imm32 R5, 0x63654235;
imm32 R7, 0x00008000;
R5 = R7 << 0x18 (V, S);
checkreg R5, 0x0000ff80;
checkreg ASTAT, (0x04f00490 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ);
dmm32 ASTAT, (0x3830ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AN);
imm32 R1, 0x40000000;
imm32 R2, 0x7fffffff;
R1 = R2 << 0x16 (V, S);
checkreg R1, 0x001fffff;
checkreg ASTAT, (0x3830ca90 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN);
dmm32 ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ);
imm32 R2, 0xfffe0000;
imm32 R3, 0xd9d90000;
R2 = R3 << 0x19 (V, S);
checkreg R2, 0xffb30000;
checkreg ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ);
dmm32 ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AZ);
imm32 R0, 0x32590000;
imm32 R2, 0x708bb53f;
R0 = R2 << 0x1c (V, S);
checkreg R0, 0x0708fb53;
checkreg ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN);
dmm32 ASTAT, (0x4cc00080 | _VS | _V | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
imm32 R3, 0x3563cfa3;
imm32 R7, 0x027e2255;
R7 = R3 << 0x1f (V, S);
checkreg R7, 0x1ab1e7d1;
checkreg ASTAT, (0x4cc00080 | _VS | _AC1 | _AQ | _AC0_COPY | _AN);
pass
|
stsp/binutils-ia16
| 6,516
|
sim/testsuite/bfin/c_seq_ac_raise_mv.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv/c_seq_ac_raise_mv.dsp
// Spec Reference: sequencer stage AC (raise + regmv)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0xa01 (X);
R1 = 0xb02 (X);
R2 = 0xc03 (X);
R3 = 0xd04 (X);
R4 = 0xe05 (X);
R5 = 0xf06 (X);
R6 = 0x107 (X);
R7 = 0x208 (X);
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
RAISE 2; // RTN
P1 = R7;
R0 = P1;
// [--sp] = (r7-r0);
RAISE 5; // RTI
P2 = R6;
R1 = P2;
// [--sp] = (r7-r1);
RAISE 6; // RTI
P3 = R5;
R2 = P3;
[ -- SP ] = ( R7:2 );
// POP
RAISE 7; // RTI
P4 = R4;
R3 = P4;
// (r7-r2) = [sp++];
CHECKREG(r0, 0x00000208);
CHECKREG(r1, 0x00000107);
CHECKREG(r2, 0x00000F06);
CHECKREG(r3, 0x00000E05);
CHECKREG(r4, 0x00000E05);
CHECKREG(r5, 0x00000F06);
CHECKREG(r6, 0x00000107);
CHECKREG(r7, 0x00000208);
R0 = 0xa41 (X);
R1 = 0xb52 (X);
R2 = 0xc63 (X);
R3 = 0xd74 (X);
R4 = 0xe85 (X);
R5 = 0xf96 (X);
R6 = 0x1a7 (X);
R7 = 0x2b8 (X);
RAISE 8; // RTI
P1 = R0;
R6 = P1;
// (r7-r1) = [sp++];
CHECKREG(r0, 0x00000A41);
CHECKREG(r1, 0x00000B52);
CHECKREG(r2, 0x00000C63);
CHECKREG(r3, 0x00000D74);
CHECKREG(r4, 0x00000E85);
CHECKREG(r5, 0x00000F96);
CHECKREG(r6, 0x00000A41);
CHECKREG(r7, 0x000002B8);
RAISE 9; // RTI
P2 = R1;
R7 = P2;
// (r7-r0) = [sp++];
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
CHECKREG(r4, 0x00000E85);
CHECKREG(r5, 0x00000F96);
CHECKREG(r6, 0x00000A41);
CHECKREG(r7, 0x00000B52);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I0 += 2;
RTI;
THANDLE: // Timer Handler 6
I1 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I2 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I3 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 1,045
|
sim/testsuite/bfin/stk.s
|
# mach: bfin
.include "testutils.inc"
start
// load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
R0 = 1;
R1 = 2;
R2 = 3;
R3 = -7;
R4 = 4;
R5 = 5;
R6 = 6;
R7 = 7;
loadsym P0, a;
_DBG P0;
SP = P0;
FP = P0;
P1 = [ P0 ++ ];
P2 = [ P0 ++ ];
P0 += 4;
P4 = [ P0 ++ ];
P5 = [ P0 ++ ];
[ -- SP ] = ( R7:0, P5:0 );
_DBG SP;
_DBG FP;
R0 = R0 ^ R0;
R1 = R1 ^ R1;
R2 = R2 ^ R2;
R4 = R4 ^ R4;
R5 = R5 ^ R5;
R6 = R6 ^ R6;
R7 = R7 ^ R7;
( R7:0, P5:0 ) = [ SP ++ ];
DBGA ( R0.L , 1 );
DBGA ( R2.L , 3 );
DBGA ( R7.L , 7 );
R0 = SP;
loadsym R1, a;
CC = R0 == R1;
IF !CC JUMP abrt;
R0 = FP;
CC = R0 == R1;
CC = R0 == R1;
IF !CC JUMP abrt;
pass
abrt:
fail
.data
_gptab:
.dw 0x200
.dw 0x000
.dw 0x300
.dw 0x400
.dw 0x500
.dw 0x600
.space (0x100)
a:
.dw 1
.dw 2
.dw 3
.dw 4
.dw 5
.dw 6
.dw 7
.dw 8
.dw 9
.dw 0xa
|
stsp/binutils-ia16
| 2,063
|
sim/testsuite/bfin/c_compi2opp_pr_add_i7_p.s
|
//Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_p/c_compi2opp_pr_add_i7_p.dsp
// Spec Reference: compi2opp pregs += imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
imm32 fp, 0x00000000;
P1 += 1;
P2 += 2;
P3 += 3;
P4 += 4;
P5 += 5;
FP += 7;
CHECKREG p1, 0x00000001;
CHECKREG p2, 0x00000002;
CHECKREG p3, 0x00000003;
CHECKREG p4, 0x00000004;
CHECKREG p5, 0x00000005;
CHECKREG fp, 0x00000007;
P1 += 9;
P2 += 10;
P3 += 11;
P4 += 12;
P5 += 13;
FP += 15;
CHECKREG p1, 0x0000000A;
CHECKREG p2, 0x0000000C;
CHECKREG p3, 0x0000000E;
CHECKREG p4, 0x00000010;
CHECKREG p5, 0x00000012;
CHECKREG fp, 0x00000016;
P1 += 17;
P2 += 18;
P3 += 19;
P4 += 20;
P5 += 21;
FP += 23;
CHECKREG p1, 0x0000001B;
CHECKREG p2, 0x0000001E;
CHECKREG p3, 0x00000021;
CHECKREG p4, 0x00000024;
CHECKREG p5, 0x00000027;
CHECKREG fp, 0x0000002D;
P1 += 25;
P2 += 26;
P3 += 27;
P4 += 28;
P5 += 29;
FP += 31;
CHECKREG p1, 0x00000034;
CHECKREG p2, 0x00000038;
CHECKREG p3, 0x0000003C;
CHECKREG p4, 0x00000040;
CHECKREG p5, 0x00000044;
CHECKREG fp, 0x0000004C;
P1 += 33;
P2 += 34;
P3 += 35;
P4 += 36;
P5 += 37;
FP += 39;
CHECKREG p1, 0x00000055;
CHECKREG p2, 0x0000005A;
CHECKREG p3, 0x0000005F;
CHECKREG p4, 0x00000064;
CHECKREG p5, 0x00000069;
CHECKREG fp, 0x00000073;
P1 += 41;
P2 += 42;
P3 += 43;
P4 += 44;
P5 += 45;
FP += 47;
CHECKREG p1, 0x0000007E;
CHECKREG p2, 0x00000084;
CHECKREG p3, 0x0000008A;
CHECKREG p4, 0x00000090;
CHECKREG p5, 0x00000096;
CHECKREG fp, 0x000000A2;
P1 += 49;
P2 += 50;
P3 += 51;
P4 += 52;
P5 += 53;
FP += 55;
CHECKREG p1, 0x000000AF;
CHECKREG p2, 0x000000B6;
CHECKREG p3, 0x000000BD;
CHECKREG p4, 0x000000C4;
CHECKREG p5, 0x000000CB;
CHECKREG fp, 0x000000D9;
P1 += 57;
P2 += 58;
P3 += 59;
P4 += 60;
P5 += 61;
FP += 63;
CHECKREG p1, 0x000000E8;
CHECKREG p2, 0x000000F0;
CHECKREG p3, 0x000000F8;
CHECKREG p4, 0x00000100;
CHECKREG p5, 0x00000108;
CHECKREG fp, 0x00000118;
pass
|
stsp/binutils-ia16
| 5,034
|
sim/testsuite/bfin/c_ldst_st_p_d_h.s
|
//Original:/testcases/core/c_ldst_st_p_d_h/c_ldst_st_p_d_h.dsp
// Spec Reference: c_ldst st_p d h
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
W [ P5 ] = R0;
W [ P1 ] = R1;
W [ P2 ] = R2;
W [ P4 ] = R4;
W [ FP ] = R5;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20212618;
CHECKREG r1, 0x40413729;
CHECKREG r3, 0x8081594B;
CHECKREG r4, 0x00011507;
CHECKREG r5, 0xA0A16A5C;
CHECKREG r7, 0x719A8C7E;
imm32 r0, 0x1a231507;
imm32 r1, 0x11342618;
imm32 r2, 0x2c153729;
imm32 r3, 0x3d51483a;
imm32 r4, 0x4e67194b;
imm32 r5, 0x5f78615c;
imm32 r6, 0x60897b1d;
imm32 r7, 0x719a8c71;
W [ P5 ] = R1;
W [ P1 ] = R2;
W [ P2 ] = R3;
W [ P4 ] = R5;
W [ FP ] = R6;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20213729;
CHECKREG r1, 0x4041483A;
CHECKREG r3, 0x8081615C;
CHECKREG r4, 0x00012618;
CHECKREG r5, 0xA0A17B1D;
CHECKREG r6, 0x60897b1d;
imm32 r0, 0x2a231507;
imm32 r1, 0x12342618;
imm32 r2, 0x2c253729;
imm32 r3, 0x3d52483a;
imm32 r4, 0x4e67294b;
imm32 r5, 0x5f78625c;
imm32 r6, 0x60897b2d;
imm32 r7, 0x719a8c72;
W [ P5 ] = R2;
W [ P1 ] = R3;
W [ P2 ] = R4;
W [ P4 ] = R6;
W [ FP ] = R7;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x2021483A;
CHECKREG r1, 0x4041294B;
CHECKREG r3, 0x80817B2D;
CHECKREG r4, 0x00013729;
CHECKREG r5, 0xA0A18C72;
CHECKREG r7, 0x719A8C72;
imm32 r0, 0x3a231507;
imm32 r1, 0x13342618;
imm32 r2, 0x2c353729;
imm32 r3, 0x3d53483a;
imm32 r4, 0x4e67394b;
imm32 r5, 0x5f78635c;
imm32 r6, 0x60897b3d;
imm32 r7, 0x719a8c73;
W [ P5 ] = R3;
W [ P1 ] = R4;
W [ P2 ] = R5;
W [ P4 ] = R7;
W [ FP ] = R0;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x2021394B;
CHECKREG r1, 0x4041635C;
CHECKREG r3, 0x80818C73;
CHECKREG r4, 0x0001483A;
CHECKREG r5, 0xA0A11507;
CHECKREG r7, 0x719A8C73;
imm32 r0, 0x4a231507;
imm32 r1, 0x14342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d54483a;
imm32 r4, 0x4e67494b;
imm32 r5, 0x5f78645c;
imm32 r6, 0x60897b4d;
imm32 r7, 0x719a8c74;
W [ P5 ] = R4;
W [ P1 ] = R5;
W [ P2 ] = R6;
W [ P4 ] = R0;
W [ FP ] = R1;
W [ P5 ] = R5;
W [ P1 ] = R6;
W [ P2 ] = R7;
W [ P4 ] = R1;
W [ FP ] = R2;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20217B4D;
CHECKREG r1, 0x40418C74;
CHECKREG r3, 0x80812618;
CHECKREG r4, 0x0001645C;
CHECKREG r5, 0xA0A13729;
CHECKREG r7, 0x719A8C74;
imm32 r0, 0x5a231507;
imm32 r1, 0x15342618;
imm32 r2, 0x2c553729;
imm32 r3, 0x3d55483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f78655c;
imm32 r6, 0x60897b5d;
imm32 r7, 0x719a8c75;
W [ P5 ] = R6;
W [ P1 ] = R7;
W [ P2 ] = R0;
W [ P4 ] = R2;
W [ FP ] = R3;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20218C75;
CHECKREG r1, 0x40411507;
CHECKREG r3, 0x80813729;
CHECKREG r4, 0x00017B5D;
CHECKREG r5, 0xA0A1483A;
CHECKREG r7, 0x719A8C75;
imm32 r0, 0x6a231507;
imm32 r1, 0x16342618;
imm32 r2, 0x2c653729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67694b;
imm32 r5, 0x5f78665c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c76;
W [ P5 ] = R7;
W [ P1 ] = R0;
W [ P2 ] = R1;
W [ P4 ] = R3;
W [ FP ] = R4;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20211507;
CHECKREG r1, 0x40412618;
CHECKREG r3, 0x8081483A;
CHECKREG r4, 0x00018C76;
CHECKREG r5, 0xA0A1694B;
CHECKREG r7, 0x719A8C76;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 1,856
|
sim/testsuite/bfin/byteop2p.s
|
# Blackfin testcase for BYTEOP2P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop2p i0:req, resRL:req, resRH:req, resTL:req, resTH:req, resRLr:req, resRHr:req, resTLr:req, resTHr:req
dmm32 I0, \i0
R6 = BYTEOP2P (R1:0, R3:2) (rndl);
check_it \resRL
R6 = BYTEOP2P (R1:0, R3:2) (rndh);
check_it \resRH
R6 = BYTEOP2P (R1:0, R3:2) (tl);
check_it \resTL
R6 = BYTEOP2P (R1:0, R3:2) (th);
check_it \resTH
R6 = BYTEOP2P (R1:0, R3:2) (rndl, r);
check_it \resRLr
R6 = BYTEOP2P (R1:0, R3:2) (rndh, r);
check_it \resRHr
R6 = BYTEOP2P (R1:0, R3:2) (tl, r);
check_it \resTLr
R6 = BYTEOP2P (R1:0, R3:2) (th, r);
check_it \resTHr
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop2p 0, 0x00060008, 0x06000800, 0x00060008, 0x06000800, 0x00600080, 0x60008000, 0x00600080, 0x60008000
test_byteop2p 1, 0x00470007, 0x47000700, 0x00460007, 0x46000700, 0x00300070, 0x30007000, 0x00300070, 0x30007000
test_byteop2p 2, 0x00800006, 0x80000600, 0x00800006, 0x80000600, 0x00080060, 0x08006000, 0x00080060, 0x08006000
test_byteop2p 3, 0x00700047, 0x70004700, 0x00700046, 0x70004600, 0x00070030, 0x07003000, 0x00070030, 0x07003000
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop2p 0, 0x00f900f7, 0xf900f700, 0x00f900f7, 0xf900f700, 0x009f007f, 0x9f007f00, 0x009f007f, 0x9f007f00
test_byteop2p 1, 0x00b800f8, 0xb800f800, 0x00b800f8, 0xb800f800, 0x00cf008f, 0xcf008f00, 0x00ce008f, 0xce008f00
test_byteop2p 2, 0x007f00f9, 0x7f00f900, 0x007f00f9, 0x7f00f900, 0x00f7009f, 0xf7009f00, 0x00f7009f, 0xf7009f00
test_byteop2p 3, 0x008f00b8, 0x8f00b800, 0x008f00b8, 0x8f00b800, 0x00f800cf, 0xf800cf00, 0x00f800ce, 0xf800ce00
pass
|
stsp/binutils-ia16
| 11,033
|
sim/testsuite/bfin/c_ldstiifp_st_dreg.s
|
//Original:testcases/core/c_ldstiifp_st_dreg/c_ldstiifp_st_dreg.dsp
// Spec Reference: c_ldstiifp store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x00;
loadsym i1, DATA_ADDR_3, 0x00;
loadsym p4, DATA_ADDR_4, 0x00;
loadsym p5, DATA_ADDR_1, 0x00;
loadsym i3, DATA_ADDR_3, 0x00;
loadsym fp, DATA_ADDR_1, 0xC8;
P3 = I1; SP = I3;
[ FP + -4 ] = R0;
[ FP + -8 ] = R1;
[ FP + -12 ] = R2;
[ FP + -16 ] = R3;
[ FP + -20 ] = R4;
[ FP + -24 ] = R5;
[ FP + -28 ] = R6;
[ FP + -32 ] = R7;
R6 = [ FP + -4 ];
R5 = [ FP + -8 ];
R4 = [ FP + -12 ];
R3 = [ FP + -16 ];
R2 = [ FP + -20 ];
R7 = [ FP + -24 ];
R0 = [ FP + -28 ];
R1 = [ FP + -32 ];
CHECKREG r0, 0x7019B0A6;
CHECKREG r1, 0xD028C0A7;
CHECKREG r2, 0x501B90A4;
CHECKREG r3, 0x402C80A3;
CHECKREG r4, 0x300370A2;
CHECKREG r5, 0x204E60A1;
CHECKREG r6, 0x105F50A0;
CHECKREG r7, 0x600AA0A5;
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
[ FP + -36 ] = R0;
[ FP + -40 ] = R1;
[ FP + -44 ] = R2;
[ FP + -48 ] = R3;
[ FP + -52 ] = R4;
[ FP + -56 ] = R5;
[ FP + -60 ] = R6;
[ FP + -64 ] = R7;
R3 = [ FP + -36 ];
R4 = [ FP + -40 ];
R0 = [ FP + -44 ];
R1 = [ FP + -48 ];
R2 = [ FP + -52 ];
R5 = [ FP + -56 ];
R6 = [ FP + -60 ];
R7 = [ FP + -64 ];
CHECKREG r0, 0x30BD70B2;
CHECKREG r1, 0x40BC80B3;
CHECKREG r2, 0x55BB90B4;
CHECKREG r3, 0x10BF50B0;
CHECKREG r4, 0x20BE60B1;
CHECKREG r5, 0x60BAA0B5;
CHECKREG r6, 0x70B9B0B6;
CHECKREG r7, 0x80B8C0B7;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
[ FP + -68 ] = R0;
[ FP + -72 ] = R1;
[ FP + -76 ] = R2;
[ FP + -80 ] = R3;
[ FP + -84 ] = R4;
[ FP + -88 ] = R5;
[ FP + -92 ] = R6;
[ FP + -96 ] = R7;
R6 = [ FP + -68 ];
R5 = [ FP + -72 ];
R4 = [ FP + -76 ];
R3 = [ FP + -80 ];
R2 = [ FP + -84 ];
R0 = [ FP + -88 ];
R7 = [ FP + -92 ];
R1 = [ FP + -96 ];
CHECKREG r0, 0x60CAA0C5;
CHECKREG r1, 0xD0C8C0C7;
CHECKREG r2, 0x50CB90C4;
CHECKREG r3, 0x40CC80C3;
CHECKREG r4, 0x30C370C2;
CHECKREG r5, 0x20CE60C1;
CHECKREG r6, 0x10CF50C0;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
[ FP + -100 ] = R0;
[ FP + -104 ] = R1;
[ FP + -108 ] = R2;
[ FP + -112 ] = R3;
[ FP + -116 ] = R4;
[ FP + -120 ] = R5;
[ FP + -124 ] = R6;
[ FP + -128 ] = R7;
R3 = [ FP + -100 ];
R4 = [ FP + -104 ];
R0 = [ FP + -108 ];
R1 = [ FP + -112 ];
R2 = [ FP + -116 ];
R5 = [ FP + -120 ];
R6 = [ FP + -124 ];
R7 = [ FP + -128 ];
CHECKREG r0, 0x80DD70D2;
CHECKREG r1, 0x90DC80D3;
CHECKREG r2, 0xA0DB90D4;
CHECKREG r3, 0x60DF50D0;
CHECKREG r4, 0x70DE60D1;
CHECKREG r5, 0xB0DAA0D5;
CHECKREG r6, 0xC0D9B0D6;
CHECKREG r7, 0xD0D8C0D7;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 4,334
|
sim/testsuite/bfin/c_interr_loopsetup_stld.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_loopsetup_stld/c_interr_loopsetup_stld.dsp
// Spec Reference: interrupt loopsetup_ldst
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
A0 = 0; // reset accumulators
A1 = 0;
P1 = 3;
P2 = 4;
LD32(r0, 0x00200005);
LD32(r1, 0x00300010);
LD32(r2, 0x00500012);
LD32(r3, 0x00600024);
LD32(r4, 0x00700016);
LD32(r5, 0x00900028);
LD32(r6, 0x0a000030);
LD32(r7, 0x00b00044);
loadsym I0, DATA0;
loadsym I1, DATA1;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
LSETUP ( start1 , end1 ) LC0 = P1;
start1: R0 += 1;
R1 += 2;
A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ]; // dsp32mac dual
// a1 += h*h, a0 += l*l (r0,r1) ; r0 = [i0++]; r1 = [i1++]; // dsp32mac
R2 = ( R2 + R5 ) << 1; // alu2op
DIVQ ( R5 , R3 );
R1 <<= R5;
R1 >>>= R1;
R6 = ~ R0;
//MY_GEN_INT(10, 1)
DIVQ ( R5 , R2 );
R0 = R3.B (X);
DIVS ( R7 , R0 );
end1: R2 += 3;
R3 = ( A0 += A1 );
CHECKREG(r0, 0x00000024);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x0670098D);
CHECKREG(r3, 0x000015EC);
CHECKREG(r4, 0x00700016);
CHECKREG(r5, 0x0B240A39);
CHECKREG(r6, 0xFFF2FFFC);
CHECKREG(r7, 0x05800220);
A0 = 0;
A1 = 0;
LSETUP ( start2 , end2 ) LC0 = P2;
start2: R4 += 4;
//a1 += h*h, a0 += l*l (r0,r1), r0 = [i0--], r1 = [i1--];
A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I0 -- ]; R1 = [ I1 -- ];
R1 <<= R5;
R6 = R7.B (Z);
R2 = - R6;
R3 = R4.L (Z);
DIVS ( R1 , R1 );
R6 = - R0;
R0 >>= R0;
DIVS ( R4 , R7 );
//MY_GEN_INT(13, 1)
R1 = R2.L (Z);
end2: R5 += -5;
R6 = ( A0 += A1 );
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x0000FFE0);
CHECKREG(r2, 0xFFFFFFE0);
CHECKREG(r3, 0x000000EC);
CHECKREG(r4, 0x070001D8);
CHECKREG(r5, 0x0B240A25);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x05800220);
LD32(r0, 0x01200805);
LD32(r1, 0x02300710);
LD32(r2, 0x03500612);
LD32(r3, 0x04600524);
LD32(r4, 0x05700416);
LD32(r5, 0x06900328);
LD32(r6, 0x0a700230);
LD32(r7, 0x08b00044);
loadsym I2, DATA0;
loadsym I3, DATA1;
[ I2 ++ ] = R0;
[ I3 ++ ] = R1;
LSETUP ( start3 , end3 ) LC0 = P1;
start3:
[ I2 ++ ] = R2;
[ I3 ++ ] = R3;
R2 += 1;
end3:
R3 += 1;
A0 = 0;
A1 = 0;
LSETUP ( start4 , end4 ) LC0 = P2;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
start4:
// a1 += h*h, a0 += l*l (r0,r1), r0 = [i2--], r1 = [i3--];
A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I2 -- ]; R1 = [ I3 -- ];
R4 = R4 + R0; // comp3op
R5 = R7.L (Z);
R4 >>>= R5;
R0 = R7.B (X);
DIVQ ( R6 , R6 );
//MY_GEN_INT(7, 1)
end4: R5 = R5 + R1;
R6 = ( A0 += A1 );
R7 = ( A0 += A1 );
CHECKREG(r0, 0x00000044);
CHECKREG(r1, 0x04600524);
CHECKREG(r2, 0x03500615);
CHECKREG(r3, 0x04600527);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x04600568);
CHECKREG(r6, 0x007C3498);
CHECKREG(r7, 0x00812098);
pass; // End the test
//
// Data Segment
//
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
.dd 0x001d0003
.dd 0x00010004
.dd 0x00010005
.dd 0x02100006
.dd 0x02200007
.dd 0x02300008
.dd 0x02200009
.dd 0x0250000a
.dd 0x0260000b
.dd 0x0270000c
.dd 0x0280000d
.dd 0x0290000e
.dd 0x2100000f
.dd 0x22000010
.dd 0x22000011
.dd 0x24000012
.dd 0x25000013
.dd 0x26000014
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
.dd 0x00b00104
.dd 0x00a00105
.dd 0x00900106
.dd 0x00800107
.dd 0x00100108
.dd 0x00200109
.dd 0x0030010a
.dd 0x0040010b
.dd 0x0050011c
.dd 0x0060010d
.dd 0x0070010e
.dd 0x0080010f
.dd 0x00900110
.dd 0x01000111
.dd 0x02000112
.dd 0x03000113
.dd 0x04000114
.dd 0x05000115
.dd 0x03f00100
.dd 0x03e00101
.dd 0x03d00102
.dd 0x03c00103
.dd 0x03b00104
.dd 0x03a00105
.dd 0x03900106
.dd 0x03800107
.dd 0x03100108
.dd 0x03200109
.dd 0x0330010a
.dd 0x0330010b
.dd 0x0350011c
.dd 0x0360010d
.dd 0x0370010e
.dd 0x0380010f
.dd 0x03900110
.dd 0x31000111
.dd 0x32000112
.dd 0x33000113
.dd 0x34000114
|
stsp/binutils-ia16
| 2,256
|
sim/testsuite/bfin/c_ccmv_cc_dr_dr.s
|
//Original:/testcases/core/c_ccmv_cc_dr_dr/c_ccmv_cc_dr_dr.dsp
// Spec Reference: ccmv cc dreg = dreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa08d2301;
imm32 r1, 0xd0021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x60b61507;
imm32 r4, 0x50487609;
imm32 r5, 0x3005900b;
imm32 r6, 0x2a0c660d;
imm32 r7, 0xd90e108f;
IF CC R0 = R0;
IF CC R1 = R3;
IF CC R2 = R5;
IF CC R3 = R2;
CC = ! CC;
IF CC R4 = R6;
IF CC R5 = R1;
IF CC R6 = R7;
CC = ! CC;
IF CC R7 = R4;
CHECKREG r0, 0xA08D2301;
CHECKREG r1, 0xD0021053;
CHECKREG r2, 0x2F041405;
CHECKREG r3, 0x60B61507;
CHECKREG r4, 0x2A0C660D;
CHECKREG r5, 0xD0021053;
CHECKREG r6, 0xD90E108F;
CHECKREG r7, 0xD90E108F;
imm32 r0, 0x308d2301;
imm32 r1, 0xd4023053;
imm32 r2, 0x2f041405;
imm32 r3, 0x60f61507;
imm32 r4, 0xd0487f09;
imm32 r5, 0x300b900b;
imm32 r6, 0x2a0cd60d;
imm32 r7, 0xd90e189f;
IF CC R4 = R3;
IF CC R5 = R7;
IF CC R6 = R1;
IF CC R7 = R2;
CC = ! CC;
IF CC R0 = R6;
IF CC R1 = R5;
IF CC R2 = R4;
CC = ! CC;
IF CC R3 = R0;
CHECKREG r0, 0x2A0CD60D;
CHECKREG r1, 0x300B900B;
CHECKREG r2, 0xD0487F09;
CHECKREG r3, 0x60F61507;
CHECKREG r4, 0xD0487F09;
CHECKREG r5, 0x300B900B;
CHECKREG r6, 0x2A0CD60D;
CHECKREG r7, 0xD90E189F;
imm32 r0, 0x708d2301;
imm32 r1, 0xd8021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x65b61507;
imm32 r4, 0x59487609;
imm32 r5, 0x3005900b;
imm32 r6, 0x2abc660d;
imm32 r7, 0xd90e108f;
IF CC R0 = R2;
IF CC R1 = R3;
CC = ! CC;
IF CC R2 = R5;
IF CC R3 = R7;
CC = ! CC;
IF CC R4 = R1;
IF CC R5 = R4;
IF CC R6 = R7;
IF CC R7 = R6;
CHECKREG r0, 0x708D2301;
CHECKREG r1, 0xD8021053;
CHECKREG r2, 0x3005900B;
CHECKREG r3, 0xD90E108F;
CHECKREG r4, 0x59487609;
CHECKREG r5, 0x3005900B;
CHECKREG r6, 0x2ABC660D;
CHECKREG r7, 0xD90E108F;
imm32 r0, 0xc08d2301;
imm32 r1, 0xdb021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x64b61507;
imm32 r4, 0x50487609;
imm32 r5, 0x30f5900b;
imm32 r6, 0x2a4c660d;
imm32 r7, 0x895e108f;
IF CC R4 = R3;
IF CC R5 = R7;
CC = ! CC;
IF CC R6 = R2;
IF CC R7 = R6;
CC = ! CC;
IF CC R0 = R1;
IF CC R1 = R2;
IF CC R2 = R0;
IF CC R3 = R4;
CHECKREG r0, 0xC08D2301;
CHECKREG r1, 0xDB021053;
CHECKREG r2, 0x2F041405;
CHECKREG r3, 0x64B61507;
CHECKREG r4, 0x50487609;
CHECKREG r5, 0x30F5900B;
CHECKREG r6, 0x2F041405;
CHECKREG r7, 0x2F041405;
pass
|
stsp/binutils-ia16
| 77,422
|
sim/testsuite/bfin/divq.s
|
# Blackfin testcase for divide instructions
# mach: bfin
.include "testutils.inc"
start
/*
* Evaluate given a signed integer dividend and signed interger divisor
* input is:
* r0 = dividend, or numerator
* r1 = divisor, or denominator
* output is:
* r0 = quotient (16-bits)
*/
.macro divide num:req, den:req
imm32 r0 \num
r1 = \den (Z);
r0 <<= 1; /* Left shift dividend by 1 needed for integer division */
p0 = 15; /* Evaluate the quotient to 16 bits. */
/* Initialize AQ status bit and dividend for the DIVQ loop. */
divs (r0, r1);
/* Evaluate DIVQ p0=15 times. */
lsetup (1f, 1f) lc0=p0;
1:
divq (r0, r1);
/* Sign extend the 16-bit quotient to 32bits. */
r0 = r0.l (x);
imm32 r1, (\num / \den);
CC = r0 == r1
if CC jump 2f;
fail
2:
.endm
/* test a bunch of values, making sure not to :
* - exceed a signed 16-bit divisor
* - exceed a signed 16-bit answer
*/
divide 0x00000001, 0x0001 /* expect 0x0001 */
divide 0x00000001, 0x0002 /* expect 0x0000 */
divide 0x00000001, 0x0003 /* expect 0x0000 */
divide 0x00000001, 0x0004 /* expect 0x0000 */
divide 0x00000001, 0x0007 /* expect 0x0000 */
divide 0x00000001, 0x0008 /* expect 0x0000 */
divide 0x00000001, 0x000f /* expect 0x0000 */
divide 0x00000001, 0x0010 /* expect 0x0000 */
divide 0x00000001, 0x001f /* expect 0x0000 */
divide 0x00000001, 0x0020 /* expect 0x0000 */
divide 0x00000001, 0x003f /* expect 0x0000 */
divide 0x00000001, 0x0040 /* expect 0x0000 */
divide 0x00000001, 0x007f /* expect 0x0000 */
divide 0x00000001, 0x0080 /* expect 0x0000 */
divide 0x00000001, 0x00ff /* expect 0x0000 */
divide 0x00000001, 0x0100 /* expect 0x0000 */
divide 0x00000001, 0x01ff /* expect 0x0000 */
divide 0x00000001, 0x0200 /* expect 0x0000 */
divide 0x00000001, 0x03ff /* expect 0x0000 */
divide 0x00000001, 0x0400 /* expect 0x0000 */
divide 0x00000001, 0x07ff /* expect 0x0000 */
divide 0x00000001, 0x0800 /* expect 0x0000 */
divide 0x00000001, 0x0fff /* expect 0x0000 */
divide 0x00000001, 0x1000 /* expect 0x0000 */
divide 0x00000001, 0x1fff /* expect 0x0000 */
divide 0x00000001, 0x2000 /* expect 0x0000 */
divide 0x00000001, 0x3fff /* expect 0x0000 */
divide 0x00000001, 0x4000 /* expect 0x0000 */
divide 0x00000001, 0x7fff /* expect 0x0000 */
divide 0x00000002, 0x0001 /* expect 0x0002 */
divide 0x00000002, 0x0002 /* expect 0x0001 */
divide 0x00000002, 0x0003 /* expect 0x0000 */
divide 0x00000002, 0x0004 /* expect 0x0000 */
divide 0x00000002, 0x0007 /* expect 0x0000 */
divide 0x00000002, 0x0008 /* expect 0x0000 */
divide 0x00000002, 0x000f /* expect 0x0000 */
divide 0x00000002, 0x0010 /* expect 0x0000 */
divide 0x00000002, 0x001f /* expect 0x0000 */
divide 0x00000002, 0x0020 /* expect 0x0000 */
divide 0x00000002, 0x003f /* expect 0x0000 */
divide 0x00000002, 0x0040 /* expect 0x0000 */
divide 0x00000002, 0x007f /* expect 0x0000 */
divide 0x00000002, 0x0080 /* expect 0x0000 */
divide 0x00000002, 0x00ff /* expect 0x0000 */
divide 0x00000002, 0x0100 /* expect 0x0000 */
divide 0x00000002, 0x01ff /* expect 0x0000 */
divide 0x00000002, 0x0200 /* expect 0x0000 */
divide 0x00000002, 0x03ff /* expect 0x0000 */
divide 0x00000002, 0x0400 /* expect 0x0000 */
divide 0x00000002, 0x07ff /* expect 0x0000 */
divide 0x00000002, 0x0800 /* expect 0x0000 */
divide 0x00000002, 0x0fff /* expect 0x0000 */
divide 0x00000002, 0x1000 /* expect 0x0000 */
divide 0x00000002, 0x1fff /* expect 0x0000 */
divide 0x00000002, 0x2000 /* expect 0x0000 */
divide 0x00000002, 0x3fff /* expect 0x0000 */
divide 0x00000002, 0x4000 /* expect 0x0000 */
divide 0x00000002, 0x7fff /* expect 0x0000 */
divide 0x00000003, 0x0001 /* expect 0x0003 */
divide 0x00000003, 0x0002 /* expect 0x0001 */
divide 0x00000003, 0x0003 /* expect 0x0001 */
divide 0x00000003, 0x0004 /* expect 0x0000 */
divide 0x00000003, 0x0007 /* expect 0x0000 */
divide 0x00000003, 0x0008 /* expect 0x0000 */
divide 0x00000003, 0x000f /* expect 0x0000 */
divide 0x00000003, 0x0010 /* expect 0x0000 */
divide 0x00000003, 0x001f /* expect 0x0000 */
divide 0x00000003, 0x0020 /* expect 0x0000 */
divide 0x00000003, 0x003f /* expect 0x0000 */
divide 0x00000003, 0x0040 /* expect 0x0000 */
divide 0x00000003, 0x007f /* expect 0x0000 */
divide 0x00000003, 0x0080 /* expect 0x0000 */
divide 0x00000003, 0x00ff /* expect 0x0000 */
divide 0x00000003, 0x0100 /* expect 0x0000 */
divide 0x00000003, 0x01ff /* expect 0x0000 */
divide 0x00000003, 0x0200 /* expect 0x0000 */
divide 0x00000003, 0x03ff /* expect 0x0000 */
divide 0x00000003, 0x0400 /* expect 0x0000 */
divide 0x00000003, 0x07ff /* expect 0x0000 */
divide 0x00000003, 0x0800 /* expect 0x0000 */
divide 0x00000003, 0x0fff /* expect 0x0000 */
divide 0x00000003, 0x1000 /* expect 0x0000 */
divide 0x00000003, 0x1fff /* expect 0x0000 */
divide 0x00000003, 0x2000 /* expect 0x0000 */
divide 0x00000003, 0x3fff /* expect 0x0000 */
divide 0x00000003, 0x4000 /* expect 0x0000 */
divide 0x00000003, 0x7fff /* expect 0x0000 */
divide 0x00000004, 0x0001 /* expect 0x0004 */
divide 0x00000004, 0x0002 /* expect 0x0002 */
divide 0x00000004, 0x0003 /* expect 0x0001 */
divide 0x00000004, 0x0004 /* expect 0x0001 */
divide 0x00000004, 0x0007 /* expect 0x0000 */
divide 0x00000004, 0x0008 /* expect 0x0000 */
divide 0x00000004, 0x000f /* expect 0x0000 */
divide 0x00000004, 0x0010 /* expect 0x0000 */
divide 0x00000004, 0x001f /* expect 0x0000 */
divide 0x00000004, 0x0020 /* expect 0x0000 */
divide 0x00000004, 0x003f /* expect 0x0000 */
divide 0x00000004, 0x0040 /* expect 0x0000 */
divide 0x00000004, 0x007f /* expect 0x0000 */
divide 0x00000004, 0x0080 /* expect 0x0000 */
divide 0x00000004, 0x00ff /* expect 0x0000 */
divide 0x00000004, 0x0100 /* expect 0x0000 */
divide 0x00000004, 0x01ff /* expect 0x0000 */
divide 0x00000004, 0x0200 /* expect 0x0000 */
divide 0x00000004, 0x03ff /* expect 0x0000 */
divide 0x00000004, 0x0400 /* expect 0x0000 */
divide 0x00000004, 0x07ff /* expect 0x0000 */
divide 0x00000004, 0x0800 /* expect 0x0000 */
divide 0x00000004, 0x0fff /* expect 0x0000 */
divide 0x00000004, 0x1000 /* expect 0x0000 */
divide 0x00000004, 0x1fff /* expect 0x0000 */
divide 0x00000004, 0x2000 /* expect 0x0000 */
divide 0x00000004, 0x3fff /* expect 0x0000 */
divide 0x00000004, 0x4000 /* expect 0x0000 */
divide 0x00000004, 0x7fff /* expect 0x0000 */
divide 0x00000007, 0x0001 /* expect 0x0007 */
divide 0x00000007, 0x0002 /* expect 0x0003 */
divide 0x00000007, 0x0003 /* expect 0x0002 */
divide 0x00000007, 0x0004 /* expect 0x0001 */
divide 0x00000007, 0x0007 /* expect 0x0001 */
divide 0x00000007, 0x0008 /* expect 0x0000 */
divide 0x00000007, 0x000f /* expect 0x0000 */
divide 0x00000007, 0x0010 /* expect 0x0000 */
divide 0x00000007, 0x001f /* expect 0x0000 */
divide 0x00000007, 0x0020 /* expect 0x0000 */
divide 0x00000007, 0x003f /* expect 0x0000 */
divide 0x00000007, 0x0040 /* expect 0x0000 */
divide 0x00000007, 0x007f /* expect 0x0000 */
divide 0x00000007, 0x0080 /* expect 0x0000 */
divide 0x00000007, 0x00ff /* expect 0x0000 */
divide 0x00000007, 0x0100 /* expect 0x0000 */
divide 0x00000007, 0x01ff /* expect 0x0000 */
divide 0x00000007, 0x0200 /* expect 0x0000 */
divide 0x00000007, 0x03ff /* expect 0x0000 */
divide 0x00000007, 0x0400 /* expect 0x0000 */
divide 0x00000007, 0x07ff /* expect 0x0000 */
divide 0x00000007, 0x0800 /* expect 0x0000 */
divide 0x00000007, 0x0fff /* expect 0x0000 */
divide 0x00000007, 0x1000 /* expect 0x0000 */
divide 0x00000007, 0x1fff /* expect 0x0000 */
divide 0x00000007, 0x2000 /* expect 0x0000 */
divide 0x00000007, 0x3fff /* expect 0x0000 */
divide 0x00000007, 0x4000 /* expect 0x0000 */
divide 0x00000007, 0x7fff /* expect 0x0000 */
divide 0x00000008, 0x0001 /* expect 0x0008 */
divide 0x00000008, 0x0002 /* expect 0x0004 */
divide 0x00000008, 0x0003 /* expect 0x0002 */
divide 0x00000008, 0x0004 /* expect 0x0002 */
divide 0x00000008, 0x0007 /* expect 0x0001 */
divide 0x00000008, 0x0008 /* expect 0x0001 */
divide 0x00000008, 0x000f /* expect 0x0000 */
divide 0x00000008, 0x0010 /* expect 0x0000 */
divide 0x00000008, 0x001f /* expect 0x0000 */
divide 0x00000008, 0x0020 /* expect 0x0000 */
divide 0x00000008, 0x003f /* expect 0x0000 */
divide 0x00000008, 0x0040 /* expect 0x0000 */
divide 0x00000008, 0x007f /* expect 0x0000 */
divide 0x00000008, 0x0080 /* expect 0x0000 */
divide 0x00000008, 0x00ff /* expect 0x0000 */
divide 0x00000008, 0x0100 /* expect 0x0000 */
divide 0x00000008, 0x01ff /* expect 0x0000 */
divide 0x00000008, 0x0200 /* expect 0x0000 */
divide 0x00000008, 0x03ff /* expect 0x0000 */
divide 0x00000008, 0x0400 /* expect 0x0000 */
divide 0x00000008, 0x07ff /* expect 0x0000 */
divide 0x00000008, 0x0800 /* expect 0x0000 */
divide 0x00000008, 0x0fff /* expect 0x0000 */
divide 0x00000008, 0x1000 /* expect 0x0000 */
divide 0x00000008, 0x1fff /* expect 0x0000 */
divide 0x00000008, 0x2000 /* expect 0x0000 */
divide 0x00000008, 0x3fff /* expect 0x0000 */
divide 0x00000008, 0x4000 /* expect 0x0000 */
divide 0x00000008, 0x7fff /* expect 0x0000 */
divide 0x0000000f, 0x0001 /* expect 0x000f */
divide 0x0000000f, 0x0002 /* expect 0x0007 */
divide 0x0000000f, 0x0003 /* expect 0x0005 */
divide 0x0000000f, 0x0004 /* expect 0x0003 */
divide 0x0000000f, 0x0007 /* expect 0x0002 */
divide 0x0000000f, 0x0008 /* expect 0x0001 */
divide 0x0000000f, 0x000f /* expect 0x0001 */
divide 0x0000000f, 0x0010 /* expect 0x0000 */
divide 0x0000000f, 0x001f /* expect 0x0000 */
divide 0x0000000f, 0x0020 /* expect 0x0000 */
divide 0x0000000f, 0x003f /* expect 0x0000 */
divide 0x0000000f, 0x0040 /* expect 0x0000 */
divide 0x0000000f, 0x007f /* expect 0x0000 */
divide 0x0000000f, 0x0080 /* expect 0x0000 */
divide 0x0000000f, 0x00ff /* expect 0x0000 */
divide 0x0000000f, 0x0100 /* expect 0x0000 */
divide 0x0000000f, 0x01ff /* expect 0x0000 */
divide 0x0000000f, 0x0200 /* expect 0x0000 */
divide 0x0000000f, 0x03ff /* expect 0x0000 */
divide 0x0000000f, 0x0400 /* expect 0x0000 */
divide 0x0000000f, 0x07ff /* expect 0x0000 */
divide 0x0000000f, 0x0800 /* expect 0x0000 */
divide 0x0000000f, 0x0fff /* expect 0x0000 */
divide 0x0000000f, 0x1000 /* expect 0x0000 */
divide 0x0000000f, 0x1fff /* expect 0x0000 */
divide 0x0000000f, 0x2000 /* expect 0x0000 */
divide 0x0000000f, 0x3fff /* expect 0x0000 */
divide 0x0000000f, 0x4000 /* expect 0x0000 */
divide 0x0000000f, 0x7fff /* expect 0x0000 */
divide 0x00000010, 0x0001 /* expect 0x0010 */
divide 0x00000010, 0x0002 /* expect 0x0008 */
divide 0x00000010, 0x0003 /* expect 0x0005 */
divide 0x00000010, 0x0004 /* expect 0x0004 */
divide 0x00000010, 0x0007 /* expect 0x0002 */
divide 0x00000010, 0x0008 /* expect 0x0002 */
divide 0x00000010, 0x000f /* expect 0x0001 */
divide 0x00000010, 0x0010 /* expect 0x0001 */
divide 0x00000010, 0x001f /* expect 0x0000 */
divide 0x00000010, 0x0020 /* expect 0x0000 */
divide 0x00000010, 0x003f /* expect 0x0000 */
divide 0x00000010, 0x0040 /* expect 0x0000 */
divide 0x00000010, 0x007f /* expect 0x0000 */
divide 0x00000010, 0x0080 /* expect 0x0000 */
divide 0x00000010, 0x00ff /* expect 0x0000 */
divide 0x00000010, 0x0100 /* expect 0x0000 */
divide 0x00000010, 0x01ff /* expect 0x0000 */
divide 0x00000010, 0x0200 /* expect 0x0000 */
divide 0x00000010, 0x03ff /* expect 0x0000 */
divide 0x00000010, 0x0400 /* expect 0x0000 */
divide 0x00000010, 0x07ff /* expect 0x0000 */
divide 0x00000010, 0x0800 /* expect 0x0000 */
divide 0x00000010, 0x0fff /* expect 0x0000 */
divide 0x00000010, 0x1000 /* expect 0x0000 */
divide 0x00000010, 0x1fff /* expect 0x0000 */
divide 0x00000010, 0x2000 /* expect 0x0000 */
divide 0x00000010, 0x3fff /* expect 0x0000 */
divide 0x00000010, 0x4000 /* expect 0x0000 */
divide 0x00000010, 0x7fff /* expect 0x0000 */
divide 0x0000001f, 0x0001 /* expect 0x001f */
divide 0x0000001f, 0x0002 /* expect 0x000f */
divide 0x0000001f, 0x0003 /* expect 0x000a */
divide 0x0000001f, 0x0004 /* expect 0x0007 */
divide 0x0000001f, 0x0007 /* expect 0x0004 */
divide 0x0000001f, 0x0008 /* expect 0x0003 */
divide 0x0000001f, 0x000f /* expect 0x0002 */
divide 0x0000001f, 0x0010 /* expect 0x0001 */
divide 0x0000001f, 0x001f /* expect 0x0001 */
divide 0x0000001f, 0x0020 /* expect 0x0000 */
divide 0x0000001f, 0x003f /* expect 0x0000 */
divide 0x0000001f, 0x0040 /* expect 0x0000 */
divide 0x0000001f, 0x007f /* expect 0x0000 */
divide 0x0000001f, 0x0080 /* expect 0x0000 */
divide 0x0000001f, 0x00ff /* expect 0x0000 */
divide 0x0000001f, 0x0100 /* expect 0x0000 */
divide 0x0000001f, 0x01ff /* expect 0x0000 */
divide 0x0000001f, 0x0200 /* expect 0x0000 */
divide 0x0000001f, 0x03ff /* expect 0x0000 */
divide 0x0000001f, 0x0400 /* expect 0x0000 */
divide 0x0000001f, 0x07ff /* expect 0x0000 */
divide 0x0000001f, 0x0800 /* expect 0x0000 */
divide 0x0000001f, 0x0fff /* expect 0x0000 */
divide 0x0000001f, 0x1000 /* expect 0x0000 */
divide 0x0000001f, 0x1fff /* expect 0x0000 */
divide 0x0000001f, 0x2000 /* expect 0x0000 */
divide 0x0000001f, 0x3fff /* expect 0x0000 */
divide 0x0000001f, 0x4000 /* expect 0x0000 */
divide 0x0000001f, 0x7fff /* expect 0x0000 */
divide 0x00000020, 0x0001 /* expect 0x0020 */
divide 0x00000020, 0x0002 /* expect 0x0010 */
divide 0x00000020, 0x0003 /* expect 0x000a */
divide 0x00000020, 0x0004 /* expect 0x0008 */
divide 0x00000020, 0x0007 /* expect 0x0004 */
divide 0x00000020, 0x0008 /* expect 0x0004 */
divide 0x00000020, 0x000f /* expect 0x0002 */
divide 0x00000020, 0x0010 /* expect 0x0002 */
divide 0x00000020, 0x001f /* expect 0x0001 */
divide 0x00000020, 0x0020 /* expect 0x0001 */
divide 0x00000020, 0x003f /* expect 0x0000 */
divide 0x00000020, 0x0040 /* expect 0x0000 */
divide 0x00000020, 0x007f /* expect 0x0000 */
divide 0x00000020, 0x0080 /* expect 0x0000 */
divide 0x00000020, 0x00ff /* expect 0x0000 */
divide 0x00000020, 0x0100 /* expect 0x0000 */
divide 0x00000020, 0x01ff /* expect 0x0000 */
divide 0x00000020, 0x0200 /* expect 0x0000 */
divide 0x00000020, 0x03ff /* expect 0x0000 */
divide 0x00000020, 0x0400 /* expect 0x0000 */
divide 0x00000020, 0x07ff /* expect 0x0000 */
divide 0x00000020, 0x0800 /* expect 0x0000 */
divide 0x00000020, 0x0fff /* expect 0x0000 */
divide 0x00000020, 0x1000 /* expect 0x0000 */
divide 0x00000020, 0x1fff /* expect 0x0000 */
divide 0x00000020, 0x2000 /* expect 0x0000 */
divide 0x00000020, 0x3fff /* expect 0x0000 */
divide 0x00000020, 0x4000 /* expect 0x0000 */
divide 0x00000020, 0x7fff /* expect 0x0000 */
divide 0x0000003f, 0x0001 /* expect 0x003f */
divide 0x0000003f, 0x0002 /* expect 0x001f */
divide 0x0000003f, 0x0003 /* expect 0x0015 */
divide 0x0000003f, 0x0004 /* expect 0x000f */
divide 0x0000003f, 0x0007 /* expect 0x0009 */
divide 0x0000003f, 0x0008 /* expect 0x0007 */
divide 0x0000003f, 0x000f /* expect 0x0004 */
divide 0x0000003f, 0x0010 /* expect 0x0003 */
divide 0x0000003f, 0x001f /* expect 0x0002 */
divide 0x0000003f, 0x0020 /* expect 0x0001 */
divide 0x0000003f, 0x003f /* expect 0x0001 */
divide 0x0000003f, 0x0040 /* expect 0x0000 */
divide 0x0000003f, 0x007f /* expect 0x0000 */
divide 0x0000003f, 0x0080 /* expect 0x0000 */
divide 0x0000003f, 0x00ff /* expect 0x0000 */
divide 0x0000003f, 0x0100 /* expect 0x0000 */
divide 0x0000003f, 0x01ff /* expect 0x0000 */
divide 0x0000003f, 0x0200 /* expect 0x0000 */
divide 0x0000003f, 0x03ff /* expect 0x0000 */
divide 0x0000003f, 0x0400 /* expect 0x0000 */
divide 0x0000003f, 0x07ff /* expect 0x0000 */
divide 0x0000003f, 0x0800 /* expect 0x0000 */
divide 0x0000003f, 0x0fff /* expect 0x0000 */
divide 0x0000003f, 0x1000 /* expect 0x0000 */
divide 0x0000003f, 0x1fff /* expect 0x0000 */
divide 0x0000003f, 0x2000 /* expect 0x0000 */
divide 0x0000003f, 0x3fff /* expect 0x0000 */
divide 0x0000003f, 0x4000 /* expect 0x0000 */
divide 0x0000003f, 0x7fff /* expect 0x0000 */
divide 0x00000040, 0x0001 /* expect 0x0040 */
divide 0x00000040, 0x0002 /* expect 0x0020 */
divide 0x00000040, 0x0003 /* expect 0x0015 */
divide 0x00000040, 0x0004 /* expect 0x0010 */
divide 0x00000040, 0x0007 /* expect 0x0009 */
divide 0x00000040, 0x0008 /* expect 0x0008 */
divide 0x00000040, 0x000f /* expect 0x0004 */
divide 0x00000040, 0x0010 /* expect 0x0004 */
divide 0x00000040, 0x001f /* expect 0x0002 */
divide 0x00000040, 0x0020 /* expect 0x0002 */
divide 0x00000040, 0x003f /* expect 0x0001 */
divide 0x00000040, 0x0040 /* expect 0x0001 */
divide 0x00000040, 0x007f /* expect 0x0000 */
divide 0x00000040, 0x0080 /* expect 0x0000 */
divide 0x00000040, 0x00ff /* expect 0x0000 */
divide 0x00000040, 0x0100 /* expect 0x0000 */
divide 0x00000040, 0x01ff /* expect 0x0000 */
divide 0x00000040, 0x0200 /* expect 0x0000 */
divide 0x00000040, 0x03ff /* expect 0x0000 */
divide 0x00000040, 0x0400 /* expect 0x0000 */
divide 0x00000040, 0x07ff /* expect 0x0000 */
divide 0x00000040, 0x0800 /* expect 0x0000 */
divide 0x00000040, 0x0fff /* expect 0x0000 */
divide 0x00000040, 0x1000 /* expect 0x0000 */
divide 0x00000040, 0x1fff /* expect 0x0000 */
divide 0x00000040, 0x2000 /* expect 0x0000 */
divide 0x00000040, 0x3fff /* expect 0x0000 */
divide 0x00000040, 0x4000 /* expect 0x0000 */
divide 0x00000040, 0x7fff /* expect 0x0000 */
divide 0x0000007f, 0x0001 /* expect 0x007f */
divide 0x0000007f, 0x0002 /* expect 0x003f */
divide 0x0000007f, 0x0003 /* expect 0x002a */
divide 0x0000007f, 0x0004 /* expect 0x001f */
divide 0x0000007f, 0x0007 /* expect 0x0012 */
divide 0x0000007f, 0x0008 /* expect 0x000f */
divide 0x0000007f, 0x000f /* expect 0x0008 */
divide 0x0000007f, 0x0010 /* expect 0x0007 */
divide 0x0000007f, 0x001f /* expect 0x0004 */
divide 0x0000007f, 0x0020 /* expect 0x0003 */
divide 0x0000007f, 0x003f /* expect 0x0002 */
divide 0x0000007f, 0x0040 /* expect 0x0001 */
divide 0x0000007f, 0x007f /* expect 0x0001 */
divide 0x0000007f, 0x0080 /* expect 0x0000 */
divide 0x0000007f, 0x00ff /* expect 0x0000 */
divide 0x0000007f, 0x0100 /* expect 0x0000 */
divide 0x0000007f, 0x01ff /* expect 0x0000 */
divide 0x0000007f, 0x0200 /* expect 0x0000 */
divide 0x0000007f, 0x03ff /* expect 0x0000 */
divide 0x0000007f, 0x0400 /* expect 0x0000 */
divide 0x0000007f, 0x07ff /* expect 0x0000 */
divide 0x0000007f, 0x0800 /* expect 0x0000 */
divide 0x0000007f, 0x0fff /* expect 0x0000 */
divide 0x0000007f, 0x1000 /* expect 0x0000 */
divide 0x0000007f, 0x1fff /* expect 0x0000 */
divide 0x0000007f, 0x2000 /* expect 0x0000 */
divide 0x0000007f, 0x3fff /* expect 0x0000 */
divide 0x0000007f, 0x4000 /* expect 0x0000 */
divide 0x0000007f, 0x7fff /* expect 0x0000 */
divide 0x00000080, 0x0001 /* expect 0x0080 */
divide 0x00000080, 0x0002 /* expect 0x0040 */
divide 0x00000080, 0x0003 /* expect 0x002a */
divide 0x00000080, 0x0004 /* expect 0x0020 */
divide 0x00000080, 0x0007 /* expect 0x0012 */
divide 0x00000080, 0x0008 /* expect 0x0010 */
divide 0x00000080, 0x000f /* expect 0x0008 */
divide 0x00000080, 0x0010 /* expect 0x0008 */
divide 0x00000080, 0x001f /* expect 0x0004 */
divide 0x00000080, 0x0020 /* expect 0x0004 */
divide 0x00000080, 0x003f /* expect 0x0002 */
divide 0x00000080, 0x0040 /* expect 0x0002 */
divide 0x00000080, 0x007f /* expect 0x0001 */
divide 0x00000080, 0x0080 /* expect 0x0001 */
divide 0x00000080, 0x00ff /* expect 0x0000 */
divide 0x00000080, 0x0100 /* expect 0x0000 */
divide 0x00000080, 0x01ff /* expect 0x0000 */
divide 0x00000080, 0x0200 /* expect 0x0000 */
divide 0x00000080, 0x03ff /* expect 0x0000 */
divide 0x00000080, 0x0400 /* expect 0x0000 */
divide 0x00000080, 0x07ff /* expect 0x0000 */
divide 0x00000080, 0x0800 /* expect 0x0000 */
divide 0x00000080, 0x0fff /* expect 0x0000 */
divide 0x00000080, 0x1000 /* expect 0x0000 */
divide 0x00000080, 0x1fff /* expect 0x0000 */
divide 0x00000080, 0x2000 /* expect 0x0000 */
divide 0x00000080, 0x3fff /* expect 0x0000 */
divide 0x00000080, 0x4000 /* expect 0x0000 */
divide 0x00000080, 0x7fff /* expect 0x0000 */
divide 0x000000ff, 0x0001 /* expect 0x00ff */
divide 0x000000ff, 0x0002 /* expect 0x007f */
divide 0x000000ff, 0x0003 /* expect 0x0055 */
divide 0x000000ff, 0x0004 /* expect 0x003f */
divide 0x000000ff, 0x0007 /* expect 0x0024 */
divide 0x000000ff, 0x0008 /* expect 0x001f */
divide 0x000000ff, 0x000f /* expect 0x0011 */
divide 0x000000ff, 0x0010 /* expect 0x000f */
divide 0x000000ff, 0x001f /* expect 0x0008 */
divide 0x000000ff, 0x0020 /* expect 0x0007 */
divide 0x000000ff, 0x003f /* expect 0x0004 */
divide 0x000000ff, 0x0040 /* expect 0x0003 */
divide 0x000000ff, 0x007f /* expect 0x0002 */
divide 0x000000ff, 0x0080 /* expect 0x0001 */
divide 0x000000ff, 0x00ff /* expect 0x0001 */
divide 0x000000ff, 0x0100 /* expect 0x0000 */
divide 0x000000ff, 0x01ff /* expect 0x0000 */
divide 0x000000ff, 0x0200 /* expect 0x0000 */
divide 0x000000ff, 0x03ff /* expect 0x0000 */
divide 0x000000ff, 0x0400 /* expect 0x0000 */
divide 0x000000ff, 0x07ff /* expect 0x0000 */
divide 0x000000ff, 0x0800 /* expect 0x0000 */
divide 0x000000ff, 0x0fff /* expect 0x0000 */
divide 0x000000ff, 0x1000 /* expect 0x0000 */
divide 0x000000ff, 0x1fff /* expect 0x0000 */
divide 0x000000ff, 0x2000 /* expect 0x0000 */
divide 0x000000ff, 0x3fff /* expect 0x0000 */
divide 0x000000ff, 0x4000 /* expect 0x0000 */
divide 0x000000ff, 0x7fff /* expect 0x0000 */
divide 0x00000100, 0x0001 /* expect 0x0100 */
divide 0x00000100, 0x0002 /* expect 0x0080 */
divide 0x00000100, 0x0003 /* expect 0x0055 */
divide 0x00000100, 0x0004 /* expect 0x0040 */
divide 0x00000100, 0x0007 /* expect 0x0024 */
divide 0x00000100, 0x0008 /* expect 0x0020 */
divide 0x00000100, 0x000f /* expect 0x0011 */
divide 0x00000100, 0x0010 /* expect 0x0010 */
divide 0x00000100, 0x001f /* expect 0x0008 */
divide 0x00000100, 0x0020 /* expect 0x0008 */
divide 0x00000100, 0x003f /* expect 0x0004 */
divide 0x00000100, 0x0040 /* expect 0x0004 */
divide 0x00000100, 0x007f /* expect 0x0002 */
divide 0x00000100, 0x0080 /* expect 0x0002 */
divide 0x00000100, 0x00ff /* expect 0x0001 */
divide 0x00000100, 0x0100 /* expect 0x0001 */
divide 0x00000100, 0x01ff /* expect 0x0000 */
divide 0x00000100, 0x0200 /* expect 0x0000 */
divide 0x00000100, 0x03ff /* expect 0x0000 */
divide 0x00000100, 0x0400 /* expect 0x0000 */
divide 0x00000100, 0x07ff /* expect 0x0000 */
divide 0x00000100, 0x0800 /* expect 0x0000 */
divide 0x00000100, 0x0fff /* expect 0x0000 */
divide 0x00000100, 0x1000 /* expect 0x0000 */
divide 0x00000100, 0x1fff /* expect 0x0000 */
divide 0x00000100, 0x2000 /* expect 0x0000 */
divide 0x00000100, 0x3fff /* expect 0x0000 */
divide 0x00000100, 0x4000 /* expect 0x0000 */
divide 0x00000100, 0x7fff /* expect 0x0000 */
divide 0x000001ff, 0x0001 /* expect 0x01ff */
divide 0x000001ff, 0x0002 /* expect 0x00ff */
divide 0x000001ff, 0x0003 /* expect 0x00aa */
divide 0x000001ff, 0x0004 /* expect 0x007f */
divide 0x000001ff, 0x0007 /* expect 0x0049 */
divide 0x000001ff, 0x0008 /* expect 0x003f */
divide 0x000001ff, 0x000f /* expect 0x0022 */
divide 0x000001ff, 0x0010 /* expect 0x001f */
divide 0x000001ff, 0x001f /* expect 0x0010 */
divide 0x000001ff, 0x0020 /* expect 0x000f */
divide 0x000001ff, 0x003f /* expect 0x0008 */
divide 0x000001ff, 0x0040 /* expect 0x0007 */
divide 0x000001ff, 0x007f /* expect 0x0004 */
divide 0x000001ff, 0x0080 /* expect 0x0003 */
divide 0x000001ff, 0x00ff /* expect 0x0002 */
divide 0x000001ff, 0x0100 /* expect 0x0001 */
divide 0x000001ff, 0x01ff /* expect 0x0001 */
divide 0x000001ff, 0x0200 /* expect 0x0000 */
divide 0x000001ff, 0x03ff /* expect 0x0000 */
divide 0x000001ff, 0x0400 /* expect 0x0000 */
divide 0x000001ff, 0x07ff /* expect 0x0000 */
divide 0x000001ff, 0x0800 /* expect 0x0000 */
divide 0x000001ff, 0x0fff /* expect 0x0000 */
divide 0x000001ff, 0x1000 /* expect 0x0000 */
divide 0x000001ff, 0x1fff /* expect 0x0000 */
divide 0x000001ff, 0x2000 /* expect 0x0000 */
divide 0x000001ff, 0x3fff /* expect 0x0000 */
divide 0x000001ff, 0x4000 /* expect 0x0000 */
divide 0x000001ff, 0x7fff /* expect 0x0000 */
divide 0x00000200, 0x0001 /* expect 0x0200 */
divide 0x00000200, 0x0002 /* expect 0x0100 */
divide 0x00000200, 0x0003 /* expect 0x00aa */
divide 0x00000200, 0x0004 /* expect 0x0080 */
divide 0x00000200, 0x0007 /* expect 0x0049 */
divide 0x00000200, 0x0008 /* expect 0x0040 */
divide 0x00000200, 0x000f /* expect 0x0022 */
divide 0x00000200, 0x0010 /* expect 0x0020 */
divide 0x00000200, 0x001f /* expect 0x0010 */
divide 0x00000200, 0x0020 /* expect 0x0010 */
divide 0x00000200, 0x003f /* expect 0x0008 */
divide 0x00000200, 0x0040 /* expect 0x0008 */
divide 0x00000200, 0x007f /* expect 0x0004 */
divide 0x00000200, 0x0080 /* expect 0x0004 */
divide 0x00000200, 0x00ff /* expect 0x0002 */
divide 0x00000200, 0x0100 /* expect 0x0002 */
divide 0x00000200, 0x01ff /* expect 0x0001 */
divide 0x00000200, 0x0200 /* expect 0x0001 */
divide 0x00000200, 0x03ff /* expect 0x0000 */
divide 0x00000200, 0x0400 /* expect 0x0000 */
divide 0x00000200, 0x07ff /* expect 0x0000 */
divide 0x00000200, 0x0800 /* expect 0x0000 */
divide 0x00000200, 0x0fff /* expect 0x0000 */
divide 0x00000200, 0x1000 /* expect 0x0000 */
divide 0x00000200, 0x1fff /* expect 0x0000 */
divide 0x00000200, 0x2000 /* expect 0x0000 */
divide 0x00000200, 0x3fff /* expect 0x0000 */
divide 0x00000200, 0x4000 /* expect 0x0000 */
divide 0x00000200, 0x7fff /* expect 0x0000 */
divide 0x000003ff, 0x0001 /* expect 0x03ff */
divide 0x000003ff, 0x0002 /* expect 0x01ff */
divide 0x000003ff, 0x0003 /* expect 0x0155 */
divide 0x000003ff, 0x0004 /* expect 0x00ff */
divide 0x000003ff, 0x0007 /* expect 0x0092 */
divide 0x000003ff, 0x0008 /* expect 0x007f */
divide 0x000003ff, 0x000f /* expect 0x0044 */
divide 0x000003ff, 0x0010 /* expect 0x003f */
divide 0x000003ff, 0x001f /* expect 0x0021 */
divide 0x000003ff, 0x0020 /* expect 0x001f */
divide 0x000003ff, 0x003f /* expect 0x0010 */
divide 0x000003ff, 0x0040 /* expect 0x000f */
divide 0x000003ff, 0x007f /* expect 0x0008 */
divide 0x000003ff, 0x0080 /* expect 0x0007 */
divide 0x000003ff, 0x00ff /* expect 0x0004 */
divide 0x000003ff, 0x0100 /* expect 0x0003 */
divide 0x000003ff, 0x01ff /* expect 0x0002 */
divide 0x000003ff, 0x0200 /* expect 0x0001 */
divide 0x000003ff, 0x03ff /* expect 0x0001 */
divide 0x000003ff, 0x0400 /* expect 0x0000 */
divide 0x000003ff, 0x07ff /* expect 0x0000 */
divide 0x000003ff, 0x0800 /* expect 0x0000 */
divide 0x000003ff, 0x0fff /* expect 0x0000 */
divide 0x000003ff, 0x1000 /* expect 0x0000 */
divide 0x000003ff, 0x1fff /* expect 0x0000 */
divide 0x000003ff, 0x2000 /* expect 0x0000 */
divide 0x000003ff, 0x3fff /* expect 0x0000 */
divide 0x000003ff, 0x4000 /* expect 0x0000 */
divide 0x000003ff, 0x7fff /* expect 0x0000 */
divide 0x00000400, 0x0001 /* expect 0x0400 */
divide 0x00000400, 0x0002 /* expect 0x0200 */
divide 0x00000400, 0x0003 /* expect 0x0155 */
divide 0x00000400, 0x0004 /* expect 0x0100 */
divide 0x00000400, 0x0007 /* expect 0x0092 */
divide 0x00000400, 0x0008 /* expect 0x0080 */
divide 0x00000400, 0x000f /* expect 0x0044 */
divide 0x00000400, 0x0010 /* expect 0x0040 */
divide 0x00000400, 0x001f /* expect 0x0021 */
divide 0x00000400, 0x0020 /* expect 0x0020 */
divide 0x00000400, 0x003f /* expect 0x0010 */
divide 0x00000400, 0x0040 /* expect 0x0010 */
divide 0x00000400, 0x007f /* expect 0x0008 */
divide 0x00000400, 0x0080 /* expect 0x0008 */
divide 0x00000400, 0x00ff /* expect 0x0004 */
divide 0x00000400, 0x0100 /* expect 0x0004 */
divide 0x00000400, 0x01ff /* expect 0x0002 */
divide 0x00000400, 0x0200 /* expect 0x0002 */
divide 0x00000400, 0x03ff /* expect 0x0001 */
divide 0x00000400, 0x0400 /* expect 0x0001 */
divide 0x00000400, 0x07ff /* expect 0x0000 */
divide 0x00000400, 0x0800 /* expect 0x0000 */
divide 0x00000400, 0x0fff /* expect 0x0000 */
divide 0x00000400, 0x1000 /* expect 0x0000 */
divide 0x00000400, 0x1fff /* expect 0x0000 */
divide 0x00000400, 0x2000 /* expect 0x0000 */
divide 0x00000400, 0x3fff /* expect 0x0000 */
divide 0x00000400, 0x4000 /* expect 0x0000 */
divide 0x00000400, 0x7fff /* expect 0x0000 */
divide 0x000007ff, 0x0001 /* expect 0x07ff */
divide 0x000007ff, 0x0002 /* expect 0x03ff */
divide 0x000007ff, 0x0003 /* expect 0x02aa */
divide 0x000007ff, 0x0004 /* expect 0x01ff */
divide 0x000007ff, 0x0007 /* expect 0x0124 */
divide 0x000007ff, 0x0008 /* expect 0x00ff */
divide 0x000007ff, 0x000f /* expect 0x0088 */
divide 0x000007ff, 0x0010 /* expect 0x007f */
divide 0x000007ff, 0x001f /* expect 0x0042 */
divide 0x000007ff, 0x0020 /* expect 0x003f */
divide 0x000007ff, 0x003f /* expect 0x0020 */
divide 0x000007ff, 0x0040 /* expect 0x001f */
divide 0x000007ff, 0x007f /* expect 0x0010 */
divide 0x000007ff, 0x0080 /* expect 0x000f */
divide 0x000007ff, 0x00ff /* expect 0x0008 */
divide 0x000007ff, 0x0100 /* expect 0x0007 */
divide 0x000007ff, 0x01ff /* expect 0x0004 */
divide 0x000007ff, 0x0200 /* expect 0x0003 */
divide 0x000007ff, 0x03ff /* expect 0x0002 */
divide 0x000007ff, 0x0400 /* expect 0x0001 */
divide 0x000007ff, 0x07ff /* expect 0x0001 */
divide 0x000007ff, 0x0800 /* expect 0x0000 */
divide 0x000007ff, 0x0fff /* expect 0x0000 */
divide 0x000007ff, 0x1000 /* expect 0x0000 */
divide 0x000007ff, 0x1fff /* expect 0x0000 */
divide 0x000007ff, 0x2000 /* expect 0x0000 */
divide 0x000007ff, 0x3fff /* expect 0x0000 */
divide 0x000007ff, 0x4000 /* expect 0x0000 */
divide 0x000007ff, 0x7fff /* expect 0x0000 */
divide 0x00000800, 0x0001 /* expect 0x0800 */
divide 0x00000800, 0x0002 /* expect 0x0400 */
divide 0x00000800, 0x0003 /* expect 0x02aa */
divide 0x00000800, 0x0004 /* expect 0x0200 */
divide 0x00000800, 0x0007 /* expect 0x0124 */
divide 0x00000800, 0x0008 /* expect 0x0100 */
divide 0x00000800, 0x000f /* expect 0x0088 */
divide 0x00000800, 0x0010 /* expect 0x0080 */
divide 0x00000800, 0x001f /* expect 0x0042 */
divide 0x00000800, 0x0020 /* expect 0x0040 */
divide 0x00000800, 0x003f /* expect 0x0020 */
divide 0x00000800, 0x0040 /* expect 0x0020 */
divide 0x00000800, 0x007f /* expect 0x0010 */
divide 0x00000800, 0x0080 /* expect 0x0010 */
divide 0x00000800, 0x00ff /* expect 0x0008 */
divide 0x00000800, 0x0100 /* expect 0x0008 */
divide 0x00000800, 0x01ff /* expect 0x0004 */
divide 0x00000800, 0x0200 /* expect 0x0004 */
divide 0x00000800, 0x03ff /* expect 0x0002 */
divide 0x00000800, 0x0400 /* expect 0x0002 */
divide 0x00000800, 0x07ff /* expect 0x0001 */
divide 0x00000800, 0x0800 /* expect 0x0001 */
divide 0x00000800, 0x0fff /* expect 0x0000 */
divide 0x00000800, 0x1000 /* expect 0x0000 */
divide 0x00000800, 0x1fff /* expect 0x0000 */
divide 0x00000800, 0x2000 /* expect 0x0000 */
divide 0x00000800, 0x3fff /* expect 0x0000 */
divide 0x00000800, 0x4000 /* expect 0x0000 */
divide 0x00000800, 0x7fff /* expect 0x0000 */
divide 0x00000fff, 0x0001 /* expect 0x0fff */
divide 0x00000fff, 0x0002 /* expect 0x07ff */
divide 0x00000fff, 0x0003 /* expect 0x0555 */
divide 0x00000fff, 0x0004 /* expect 0x03ff */
divide 0x00000fff, 0x0007 /* expect 0x0249 */
divide 0x00000fff, 0x0008 /* expect 0x01ff */
divide 0x00000fff, 0x000f /* expect 0x0111 */
divide 0x00000fff, 0x0010 /* expect 0x00ff */
divide 0x00000fff, 0x001f /* expect 0x0084 */
divide 0x00000fff, 0x0020 /* expect 0x007f */
divide 0x00000fff, 0x003f /* expect 0x0041 */
divide 0x00000fff, 0x0040 /* expect 0x003f */
divide 0x00000fff, 0x007f /* expect 0x0020 */
divide 0x00000fff, 0x0080 /* expect 0x001f */
divide 0x00000fff, 0x00ff /* expect 0x0010 */
divide 0x00000fff, 0x0100 /* expect 0x000f */
divide 0x00000fff, 0x01ff /* expect 0x0008 */
divide 0x00000fff, 0x0200 /* expect 0x0007 */
divide 0x00000fff, 0x03ff /* expect 0x0004 */
divide 0x00000fff, 0x0400 /* expect 0x0003 */
divide 0x00000fff, 0x07ff /* expect 0x0002 */
divide 0x00000fff, 0x0800 /* expect 0x0001 */
divide 0x00000fff, 0x0fff /* expect 0x0001 */
divide 0x00000fff, 0x1000 /* expect 0x0000 */
divide 0x00000fff, 0x1fff /* expect 0x0000 */
divide 0x00000fff, 0x2000 /* expect 0x0000 */
divide 0x00000fff, 0x3fff /* expect 0x0000 */
divide 0x00000fff, 0x4000 /* expect 0x0000 */
divide 0x00000fff, 0x7fff /* expect 0x0000 */
divide 0x00001000, 0x0001 /* expect 0x1000 */
divide 0x00001000, 0x0002 /* expect 0x0800 */
divide 0x00001000, 0x0003 /* expect 0x0555 */
divide 0x00001000, 0x0004 /* expect 0x0400 */
divide 0x00001000, 0x0007 /* expect 0x0249 */
divide 0x00001000, 0x0008 /* expect 0x0200 */
divide 0x00001000, 0x000f /* expect 0x0111 */
divide 0x00001000, 0x0010 /* expect 0x0100 */
divide 0x00001000, 0x001f /* expect 0x0084 */
divide 0x00001000, 0x0020 /* expect 0x0080 */
divide 0x00001000, 0x003f /* expect 0x0041 */
divide 0x00001000, 0x0040 /* expect 0x0040 */
divide 0x00001000, 0x007f /* expect 0x0020 */
divide 0x00001000, 0x0080 /* expect 0x0020 */
divide 0x00001000, 0x00ff /* expect 0x0010 */
divide 0x00001000, 0x0100 /* expect 0x0010 */
divide 0x00001000, 0x01ff /* expect 0x0008 */
divide 0x00001000, 0x0200 /* expect 0x0008 */
divide 0x00001000, 0x03ff /* expect 0x0004 */
divide 0x00001000, 0x0400 /* expect 0x0004 */
divide 0x00001000, 0x07ff /* expect 0x0002 */
divide 0x00001000, 0x0800 /* expect 0x0002 */
divide 0x00001000, 0x0fff /* expect 0x0001 */
divide 0x00001000, 0x1000 /* expect 0x0001 */
divide 0x00001000, 0x1fff /* expect 0x0000 */
divide 0x00001000, 0x2000 /* expect 0x0000 */
divide 0x00001000, 0x3fff /* expect 0x0000 */
divide 0x00001000, 0x4000 /* expect 0x0000 */
divide 0x00001000, 0x7fff /* expect 0x0000 */
divide 0x00001fff, 0x0001 /* expect 0x1fff */
divide 0x00001fff, 0x0002 /* expect 0x0fff */
divide 0x00001fff, 0x0003 /* expect 0x0aaa */
divide 0x00001fff, 0x0004 /* expect 0x07ff */
divide 0x00001fff, 0x0007 /* expect 0x0492 */
divide 0x00001fff, 0x0008 /* expect 0x03ff */
divide 0x00001fff, 0x000f /* expect 0x0222 */
divide 0x00001fff, 0x0010 /* expect 0x01ff */
divide 0x00001fff, 0x001f /* expect 0x0108 */
divide 0x00001fff, 0x0020 /* expect 0x00ff */
divide 0x00001fff, 0x003f /* expect 0x0082 */
divide 0x00001fff, 0x0040 /* expect 0x007f */
divide 0x00001fff, 0x007f /* expect 0x0040 */
divide 0x00001fff, 0x0080 /* expect 0x003f */
divide 0x00001fff, 0x00ff /* expect 0x0020 */
divide 0x00001fff, 0x0100 /* expect 0x001f */
divide 0x00001fff, 0x01ff /* expect 0x0010 */
divide 0x00001fff, 0x0200 /* expect 0x000f */
divide 0x00001fff, 0x03ff /* expect 0x0008 */
divide 0x00001fff, 0x0400 /* expect 0x0007 */
divide 0x00001fff, 0x07ff /* expect 0x0004 */
divide 0x00001fff, 0x0800 /* expect 0x0003 */
divide 0x00001fff, 0x0fff /* expect 0x0002 */
divide 0x00001fff, 0x1000 /* expect 0x0001 */
divide 0x00001fff, 0x1fff /* expect 0x0001 */
divide 0x00001fff, 0x2000 /* expect 0x0000 */
divide 0x00001fff, 0x3fff /* expect 0x0000 */
divide 0x00001fff, 0x4000 /* expect 0x0000 */
divide 0x00001fff, 0x7fff /* expect 0x0000 */
divide 0x00002000, 0x0001 /* expect 0x2000 */
divide 0x00002000, 0x0002 /* expect 0x1000 */
divide 0x00002000, 0x0003 /* expect 0x0aaa */
divide 0x00002000, 0x0004 /* expect 0x0800 */
divide 0x00002000, 0x0007 /* expect 0x0492 */
divide 0x00002000, 0x0008 /* expect 0x0400 */
divide 0x00002000, 0x000f /* expect 0x0222 */
divide 0x00002000, 0x0010 /* expect 0x0200 */
divide 0x00002000, 0x001f /* expect 0x0108 */
divide 0x00002000, 0x0020 /* expect 0x0100 */
divide 0x00002000, 0x003f /* expect 0x0082 */
divide 0x00002000, 0x0040 /* expect 0x0080 */
divide 0x00002000, 0x007f /* expect 0x0040 */
divide 0x00002000, 0x0080 /* expect 0x0040 */
divide 0x00002000, 0x00ff /* expect 0x0020 */
divide 0x00002000, 0x0100 /* expect 0x0020 */
divide 0x00002000, 0x01ff /* expect 0x0010 */
divide 0x00002000, 0x0200 /* expect 0x0010 */
divide 0x00002000, 0x03ff /* expect 0x0008 */
divide 0x00002000, 0x0400 /* expect 0x0008 */
divide 0x00002000, 0x07ff /* expect 0x0004 */
divide 0x00002000, 0x0800 /* expect 0x0004 */
divide 0x00002000, 0x0fff /* expect 0x0002 */
divide 0x00002000, 0x1000 /* expect 0x0002 */
divide 0x00002000, 0x1fff /* expect 0x0001 */
divide 0x00002000, 0x2000 /* expect 0x0001 */
divide 0x00002000, 0x3fff /* expect 0x0000 */
divide 0x00002000, 0x4000 /* expect 0x0000 */
divide 0x00002000, 0x7fff /* expect 0x0000 */
divide 0x00003fff, 0x0001 /* expect 0x3fff */
divide 0x00003fff, 0x0002 /* expect 0x1fff */
divide 0x00003fff, 0x0003 /* expect 0x1555 */
divide 0x00003fff, 0x0004 /* expect 0x0fff */
divide 0x00003fff, 0x0007 /* expect 0x0924 */
divide 0x00003fff, 0x0008 /* expect 0x07ff */
divide 0x00003fff, 0x000f /* expect 0x0444 */
divide 0x00003fff, 0x0010 /* expect 0x03ff */
divide 0x00003fff, 0x001f /* expect 0x0210 */
divide 0x00003fff, 0x0020 /* expect 0x01ff */
divide 0x00003fff, 0x003f /* expect 0x0104 */
divide 0x00003fff, 0x0040 /* expect 0x00ff */
divide 0x00003fff, 0x007f /* expect 0x0081 */
divide 0x00003fff, 0x0080 /* expect 0x007f */
divide 0x00003fff, 0x00ff /* expect 0x0040 */
divide 0x00003fff, 0x0100 /* expect 0x003f */
divide 0x00003fff, 0x01ff /* expect 0x0020 */
divide 0x00003fff, 0x0200 /* expect 0x001f */
divide 0x00003fff, 0x03ff /* expect 0x0010 */
divide 0x00003fff, 0x0400 /* expect 0x000f */
divide 0x00003fff, 0x07ff /* expect 0x0008 */
divide 0x00003fff, 0x0800 /* expect 0x0007 */
divide 0x00003fff, 0x0fff /* expect 0x0004 */
divide 0x00003fff, 0x1000 /* expect 0x0003 */
divide 0x00003fff, 0x1fff /* expect 0x0002 */
divide 0x00003fff, 0x2000 /* expect 0x0001 */
divide 0x00003fff, 0x3fff /* expect 0x0001 */
divide 0x00003fff, 0x4000 /* expect 0x0000 */
divide 0x00003fff, 0x7fff /* expect 0x0000 */
divide 0x00004000, 0x0001 /* expect 0x4000 */
divide 0x00004000, 0x0002 /* expect 0x2000 */
divide 0x00004000, 0x0003 /* expect 0x1555 */
divide 0x00004000, 0x0004 /* expect 0x1000 */
divide 0x00004000, 0x0007 /* expect 0x0924 */
divide 0x00004000, 0x0008 /* expect 0x0800 */
divide 0x00004000, 0x000f /* expect 0x0444 */
divide 0x00004000, 0x0010 /* expect 0x0400 */
divide 0x00004000, 0x001f /* expect 0x0210 */
divide 0x00004000, 0x0020 /* expect 0x0200 */
divide 0x00004000, 0x003f /* expect 0x0104 */
divide 0x00004000, 0x0040 /* expect 0x0100 */
divide 0x00004000, 0x007f /* expect 0x0081 */
divide 0x00004000, 0x0080 /* expect 0x0080 */
divide 0x00004000, 0x00ff /* expect 0x0040 */
divide 0x00004000, 0x0100 /* expect 0x0040 */
divide 0x00004000, 0x01ff /* expect 0x0020 */
divide 0x00004000, 0x0200 /* expect 0x0020 */
divide 0x00004000, 0x03ff /* expect 0x0010 */
divide 0x00004000, 0x0400 /* expect 0x0010 */
divide 0x00004000, 0x07ff /* expect 0x0008 */
divide 0x00004000, 0x0800 /* expect 0x0008 */
divide 0x00004000, 0x0fff /* expect 0x0004 */
divide 0x00004000, 0x1000 /* expect 0x0004 */
divide 0x00004000, 0x1fff /* expect 0x0002 */
divide 0x00004000, 0x2000 /* expect 0x0002 */
divide 0x00004000, 0x3fff /* expect 0x0001 */
divide 0x00004000, 0x4000 /* expect 0x0001 */
divide 0x00004000, 0x7fff /* expect 0x0000 */
divide 0x00007fff, 0x0001 /* expect 0x7fff */
divide 0x00007fff, 0x0002 /* expect 0x3fff */
divide 0x00007fff, 0x0003 /* expect 0x2aaa */
divide 0x00007fff, 0x0004 /* expect 0x1fff */
divide 0x00007fff, 0x0007 /* expect 0x1249 */
divide 0x00007fff, 0x0008 /* expect 0x0fff */
divide 0x00007fff, 0x000f /* expect 0x0888 */
divide 0x00007fff, 0x0010 /* expect 0x07ff */
divide 0x00007fff, 0x001f /* expect 0x0421 */
divide 0x00007fff, 0x0020 /* expect 0x03ff */
divide 0x00007fff, 0x003f /* expect 0x0208 */
divide 0x00007fff, 0x0040 /* expect 0x01ff */
divide 0x00007fff, 0x007f /* expect 0x0102 */
divide 0x00007fff, 0x0080 /* expect 0x00ff */
divide 0x00007fff, 0x00ff /* expect 0x0080 */
divide 0x00007fff, 0x0100 /* expect 0x007f */
divide 0x00007fff, 0x01ff /* expect 0x0040 */
divide 0x00007fff, 0x0200 /* expect 0x003f */
divide 0x00007fff, 0x03ff /* expect 0x0020 */
divide 0x00007fff, 0x0400 /* expect 0x001f */
divide 0x00007fff, 0x07ff /* expect 0x0010 */
divide 0x00007fff, 0x0800 /* expect 0x000f */
divide 0x00007fff, 0x0fff /* expect 0x0008 */
divide 0x00007fff, 0x1000 /* expect 0x0007 */
divide 0x00007fff, 0x1fff /* expect 0x0004 */
divide 0x00007fff, 0x2000 /* expect 0x0003 */
divide 0x00007fff, 0x3fff /* expect 0x0002 */
divide 0x00007fff, 0x4000 /* expect 0x0001 */
divide 0x00007fff, 0x7fff /* expect 0x0001 */
divide 0x00008000, 0x0002 /* expect 0x4000 */
divide 0x00008000, 0x0003 /* expect 0x2aaa */
divide 0x00008000, 0x0004 /* expect 0x2000 */
divide 0x00008000, 0x0007 /* expect 0x1249 */
divide 0x00008000, 0x0008 /* expect 0x1000 */
divide 0x00008000, 0x000f /* expect 0x0888 */
divide 0x00008000, 0x0010 /* expect 0x0800 */
divide 0x00008000, 0x001f /* expect 0x0421 */
divide 0x00008000, 0x0020 /* expect 0x0400 */
divide 0x00008000, 0x003f /* expect 0x0208 */
divide 0x00008000, 0x0040 /* expect 0x0200 */
divide 0x00008000, 0x007f /* expect 0x0102 */
divide 0x00008000, 0x0080 /* expect 0x0100 */
divide 0x00008000, 0x00ff /* expect 0x0080 */
divide 0x00008000, 0x0100 /* expect 0x0080 */
divide 0x00008000, 0x01ff /* expect 0x0040 */
divide 0x00008000, 0x0200 /* expect 0x0040 */
divide 0x00008000, 0x03ff /* expect 0x0020 */
divide 0x00008000, 0x0400 /* expect 0x0020 */
divide 0x00008000, 0x07ff /* expect 0x0010 */
divide 0x00008000, 0x0800 /* expect 0x0010 */
divide 0x00008000, 0x0fff /* expect 0x0008 */
divide 0x00008000, 0x1000 /* expect 0x0008 */
divide 0x00008000, 0x1fff /* expect 0x0004 */
divide 0x00008000, 0x2000 /* expect 0x0004 */
divide 0x00008000, 0x3fff /* expect 0x0002 */
divide 0x00008000, 0x4000 /* expect 0x0002 */
divide 0x00008000, 0x7fff /* expect 0x0001 */
divide 0x0000ffff, 0x0002 /* expect 0x7fff */
divide 0x0000ffff, 0x0003 /* expect 0x5555 */
divide 0x0000ffff, 0x0004 /* expect 0x3fff */
divide 0x0000ffff, 0x0007 /* expect 0x2492 */
divide 0x0000ffff, 0x0008 /* expect 0x1fff */
divide 0x0000ffff, 0x000f /* expect 0x1111 */
divide 0x0000ffff, 0x0010 /* expect 0x0fff */
divide 0x0000ffff, 0x001f /* expect 0x0842 */
divide 0x0000ffff, 0x0020 /* expect 0x07ff */
divide 0x0000ffff, 0x003f /* expect 0x0410 */
divide 0x0000ffff, 0x0040 /* expect 0x03ff */
divide 0x0000ffff, 0x007f /* expect 0x0204 */
divide 0x0000ffff, 0x0080 /* expect 0x01ff */
divide 0x0000ffff, 0x00ff /* expect 0x0101 */
divide 0x0000ffff, 0x0100 /* expect 0x00ff */
divide 0x0000ffff, 0x01ff /* expect 0x0080 */
divide 0x0000ffff, 0x0200 /* expect 0x007f */
divide 0x0000ffff, 0x03ff /* expect 0x0040 */
divide 0x0000ffff, 0x0400 /* expect 0x003f */
divide 0x0000ffff, 0x07ff /* expect 0x0020 */
divide 0x0000ffff, 0x0800 /* expect 0x001f */
divide 0x0000ffff, 0x0fff /* expect 0x0010 */
divide 0x0000ffff, 0x1000 /* expect 0x000f */
divide 0x0000ffff, 0x1fff /* expect 0x0008 */
divide 0x0000ffff, 0x2000 /* expect 0x0007 */
divide 0x0000ffff, 0x3fff /* expect 0x0004 */
divide 0x0000ffff, 0x4000 /* expect 0x0003 */
divide 0x0000ffff, 0x7fff /* expect 0x0002 */
divide 0x00010000, 0x0003 /* expect 0x5555 */
divide 0x00010000, 0x0004 /* expect 0x4000 */
divide 0x00010000, 0x0007 /* expect 0x2492 */
divide 0x00010000, 0x0008 /* expect 0x2000 */
divide 0x00010000, 0x000f /* expect 0x1111 */
divide 0x00010000, 0x0010 /* expect 0x1000 */
divide 0x00010000, 0x001f /* expect 0x0842 */
divide 0x00010000, 0x0020 /* expect 0x0800 */
divide 0x00010000, 0x003f /* expect 0x0410 */
divide 0x00010000, 0x0040 /* expect 0x0400 */
divide 0x00010000, 0x007f /* expect 0x0204 */
divide 0x00010000, 0x0080 /* expect 0x0200 */
divide 0x00010000, 0x00ff /* expect 0x0101 */
divide 0x00010000, 0x0100 /* expect 0x0100 */
divide 0x00010000, 0x01ff /* expect 0x0080 */
divide 0x00010000, 0x0200 /* expect 0x0080 */
divide 0x00010000, 0x03ff /* expect 0x0040 */
divide 0x00010000, 0x0400 /* expect 0x0040 */
divide 0x00010000, 0x07ff /* expect 0x0020 */
divide 0x00010000, 0x0800 /* expect 0x0020 */
divide 0x00010000, 0x0fff /* expect 0x0010 */
divide 0x00010000, 0x1000 /* expect 0x0010 */
divide 0x00010000, 0x1fff /* expect 0x0008 */
divide 0x00010000, 0x2000 /* expect 0x0008 */
divide 0x00010000, 0x3fff /* expect 0x0004 */
divide 0x00010000, 0x4000 /* expect 0x0004 */
divide 0x00010000, 0x7fff /* expect 0x0002 */
divide 0x0001ffff, 0x0004 /* expect 0x7fff */
divide 0x0001ffff, 0x0007 /* expect 0x4924 */
divide 0x0001ffff, 0x0008 /* expect 0x3fff */
divide 0x0001ffff, 0x000f /* expect 0x2222 */
divide 0x0001ffff, 0x0010 /* expect 0x1fff */
divide 0x0001ffff, 0x001f /* expect 0x1084 */
divide 0x0001ffff, 0x0020 /* expect 0x0fff */
divide 0x0001ffff, 0x003f /* expect 0x0820 */
divide 0x0001ffff, 0x0040 /* expect 0x07ff */
divide 0x0001ffff, 0x007f /* expect 0x0408 */
divide 0x0001ffff, 0x0080 /* expect 0x03ff */
divide 0x0001ffff, 0x00ff /* expect 0x0202 */
divide 0x0001ffff, 0x0100 /* expect 0x01ff */
divide 0x0001ffff, 0x01ff /* expect 0x0100 */
divide 0x0001ffff, 0x0200 /* expect 0x00ff */
divide 0x0001ffff, 0x03ff /* expect 0x0080 */
divide 0x0001ffff, 0x0400 /* expect 0x007f */
divide 0x0001ffff, 0x07ff /* expect 0x0040 */
divide 0x0001ffff, 0x0800 /* expect 0x003f */
divide 0x0001ffff, 0x0fff /* expect 0x0020 */
divide 0x0001ffff, 0x1000 /* expect 0x001f */
divide 0x0001ffff, 0x1fff /* expect 0x0010 */
divide 0x0001ffff, 0x2000 /* expect 0x000f */
divide 0x0001ffff, 0x3fff /* expect 0x0008 */
divide 0x0001ffff, 0x4000 /* expect 0x0007 */
divide 0x0001ffff, 0x7fff /* expect 0x0004 */
divide 0x00020000, 0x0007 /* expect 0x4924 */
divide 0x00020000, 0x0008 /* expect 0x4000 */
divide 0x00020000, 0x000f /* expect 0x2222 */
divide 0x00020000, 0x0010 /* expect 0x2000 */
divide 0x00020000, 0x001f /* expect 0x1084 */
divide 0x00020000, 0x0020 /* expect 0x1000 */
divide 0x00020000, 0x003f /* expect 0x0820 */
divide 0x00020000, 0x0040 /* expect 0x0800 */
divide 0x00020000, 0x007f /* expect 0x0408 */
divide 0x00020000, 0x0080 /* expect 0x0400 */
divide 0x00020000, 0x00ff /* expect 0x0202 */
divide 0x00020000, 0x0100 /* expect 0x0200 */
divide 0x00020000, 0x01ff /* expect 0x0100 */
divide 0x00020000, 0x0200 /* expect 0x0100 */
divide 0x00020000, 0x03ff /* expect 0x0080 */
divide 0x00020000, 0x0400 /* expect 0x0080 */
divide 0x00020000, 0x07ff /* expect 0x0040 */
divide 0x00020000, 0x0800 /* expect 0x0040 */
divide 0x00020000, 0x0fff /* expect 0x0020 */
divide 0x00020000, 0x1000 /* expect 0x0020 */
divide 0x00020000, 0x1fff /* expect 0x0010 */
divide 0x00020000, 0x2000 /* expect 0x0010 */
divide 0x00020000, 0x3fff /* expect 0x0008 */
divide 0x00020000, 0x4000 /* expect 0x0008 */
divide 0x00020000, 0x7fff /* expect 0x0004 */
divide 0x0003ffff, 0x0008 /* expect 0x7fff */
divide 0x0003ffff, 0x000f /* expect 0x4444 */
divide 0x0003ffff, 0x0010 /* expect 0x3fff */
divide 0x0003ffff, 0x001f /* expect 0x2108 */
divide 0x0003ffff, 0x0020 /* expect 0x1fff */
divide 0x0003ffff, 0x003f /* expect 0x1041 */
divide 0x0003ffff, 0x0040 /* expect 0x0fff */
divide 0x0003ffff, 0x007f /* expect 0x0810 */
divide 0x0003ffff, 0x0080 /* expect 0x07ff */
divide 0x0003ffff, 0x00ff /* expect 0x0404 */
divide 0x0003ffff, 0x0100 /* expect 0x03ff */
divide 0x0003ffff, 0x01ff /* expect 0x0201 */
divide 0x0003ffff, 0x0200 /* expect 0x01ff */
divide 0x0003ffff, 0x03ff /* expect 0x0100 */
divide 0x0003ffff, 0x0400 /* expect 0x00ff */
divide 0x0003ffff, 0x07ff /* expect 0x0080 */
divide 0x0003ffff, 0x0800 /* expect 0x007f */
divide 0x0003ffff, 0x0fff /* expect 0x0040 */
divide 0x0003ffff, 0x1000 /* expect 0x003f */
divide 0x0003ffff, 0x1fff /* expect 0x0020 */
divide 0x0003ffff, 0x2000 /* expect 0x001f */
divide 0x0003ffff, 0x3fff /* expect 0x0010 */
divide 0x0003ffff, 0x4000 /* expect 0x000f */
divide 0x0003ffff, 0x7fff /* expect 0x0008 */
divide 0x00040000, 0x000f /* expect 0x4444 */
divide 0x00040000, 0x0010 /* expect 0x4000 */
divide 0x00040000, 0x001f /* expect 0x2108 */
divide 0x00040000, 0x0020 /* expect 0x2000 */
divide 0x00040000, 0x003f /* expect 0x1041 */
divide 0x00040000, 0x0040 /* expect 0x1000 */
divide 0x00040000, 0x007f /* expect 0x0810 */
divide 0x00040000, 0x0080 /* expect 0x0800 */
divide 0x00040000, 0x00ff /* expect 0x0404 */
divide 0x00040000, 0x0100 /* expect 0x0400 */
divide 0x00040000, 0x01ff /* expect 0x0201 */
divide 0x00040000, 0x0200 /* expect 0x0200 */
divide 0x00040000, 0x03ff /* expect 0x0100 */
divide 0x00040000, 0x0400 /* expect 0x0100 */
divide 0x00040000, 0x07ff /* expect 0x0080 */
divide 0x00040000, 0x0800 /* expect 0x0080 */
divide 0x00040000, 0x0fff /* expect 0x0040 */
divide 0x00040000, 0x1000 /* expect 0x0040 */
divide 0x00040000, 0x1fff /* expect 0x0020 */
divide 0x00040000, 0x2000 /* expect 0x0020 */
divide 0x00040000, 0x3fff /* expect 0x0010 */
divide 0x00040000, 0x4000 /* expect 0x0010 */
divide 0x00040000, 0x7fff /* expect 0x0008 */
divide 0x0007ffff, 0x0010 /* expect 0x7fff */
divide 0x0007ffff, 0x001f /* expect 0x4210 */
divide 0x0007ffff, 0x0020 /* expect 0x3fff */
divide 0x0007ffff, 0x003f /* expect 0x2082 */
divide 0x0007ffff, 0x0040 /* expect 0x1fff */
divide 0x0007ffff, 0x007f /* expect 0x1020 */
divide 0x0007ffff, 0x0080 /* expect 0x0fff */
divide 0x0007ffff, 0x00ff /* expect 0x0808 */
divide 0x0007ffff, 0x0100 /* expect 0x07ff */
divide 0x0007ffff, 0x01ff /* expect 0x0402 */
divide 0x0007ffff, 0x0200 /* expect 0x03ff */
divide 0x0007ffff, 0x03ff /* expect 0x0200 */
divide 0x0007ffff, 0x0400 /* expect 0x01ff */
divide 0x0007ffff, 0x07ff /* expect 0x0100 */
divide 0x0007ffff, 0x0800 /* expect 0x00ff */
divide 0x0007ffff, 0x0fff /* expect 0x0080 */
divide 0x0007ffff, 0x1000 /* expect 0x007f */
divide 0x0007ffff, 0x1fff /* expect 0x0040 */
divide 0x0007ffff, 0x2000 /* expect 0x003f */
divide 0x0007ffff, 0x3fff /* expect 0x0020 */
divide 0x0007ffff, 0x4000 /* expect 0x001f */
divide 0x0007ffff, 0x7fff /* expect 0x0010 */
divide 0x00080000, 0x001f /* expect 0x4210 */
divide 0x00080000, 0x0020 /* expect 0x4000 */
divide 0x00080000, 0x003f /* expect 0x2082 */
divide 0x00080000, 0x0040 /* expect 0x2000 */
divide 0x00080000, 0x007f /* expect 0x1020 */
divide 0x00080000, 0x0080 /* expect 0x1000 */
divide 0x00080000, 0x00ff /* expect 0x0808 */
divide 0x00080000, 0x0100 /* expect 0x0800 */
divide 0x00080000, 0x01ff /* expect 0x0402 */
divide 0x00080000, 0x0200 /* expect 0x0400 */
divide 0x00080000, 0x03ff /* expect 0x0200 */
divide 0x00080000, 0x0400 /* expect 0x0200 */
divide 0x00080000, 0x07ff /* expect 0x0100 */
divide 0x00080000, 0x0800 /* expect 0x0100 */
divide 0x00080000, 0x0fff /* expect 0x0080 */
divide 0x00080000, 0x1000 /* expect 0x0080 */
divide 0x00080000, 0x1fff /* expect 0x0040 */
divide 0x00080000, 0x2000 /* expect 0x0040 */
divide 0x00080000, 0x3fff /* expect 0x0020 */
divide 0x00080000, 0x4000 /* expect 0x0020 */
divide 0x00080000, 0x7fff /* expect 0x0010 */
divide 0x000fffff, 0x0020 /* expect 0x7fff */
divide 0x000fffff, 0x003f /* expect 0x4104 */
divide 0x000fffff, 0x0040 /* expect 0x3fff */
divide 0x000fffff, 0x007f /* expect 0x2040 */
divide 0x000fffff, 0x0080 /* expect 0x1fff */
divide 0x000fffff, 0x00ff /* expect 0x1010 */
divide 0x000fffff, 0x0100 /* expect 0x0fff */
divide 0x000fffff, 0x01ff /* expect 0x0804 */
divide 0x000fffff, 0x0200 /* expect 0x07ff */
divide 0x000fffff, 0x03ff /* expect 0x0401 */
divide 0x000fffff, 0x0400 /* expect 0x03ff */
divide 0x000fffff, 0x07ff /* expect 0x0200 */
divide 0x000fffff, 0x0800 /* expect 0x01ff */
divide 0x000fffff, 0x0fff /* expect 0x0100 */
divide 0x000fffff, 0x1000 /* expect 0x00ff */
divide 0x000fffff, 0x1fff /* expect 0x0080 */
divide 0x000fffff, 0x2000 /* expect 0x007f */
divide 0x000fffff, 0x3fff /* expect 0x0040 */
divide 0x000fffff, 0x4000 /* expect 0x003f */
divide 0x000fffff, 0x7fff /* expect 0x0020 */
divide 0x00100000, 0x003f /* expect 0x4104 */
divide 0x00100000, 0x0040 /* expect 0x4000 */
divide 0x00100000, 0x007f /* expect 0x2040 */
divide 0x00100000, 0x0080 /* expect 0x2000 */
divide 0x00100000, 0x00ff /* expect 0x1010 */
divide 0x00100000, 0x0100 /* expect 0x1000 */
divide 0x00100000, 0x01ff /* expect 0x0804 */
divide 0x00100000, 0x0200 /* expect 0x0800 */
divide 0x00100000, 0x03ff /* expect 0x0401 */
divide 0x00100000, 0x0400 /* expect 0x0400 */
divide 0x00100000, 0x07ff /* expect 0x0200 */
divide 0x00100000, 0x0800 /* expect 0x0200 */
divide 0x00100000, 0x0fff /* expect 0x0100 */
divide 0x00100000, 0x1000 /* expect 0x0100 */
divide 0x00100000, 0x1fff /* expect 0x0080 */
divide 0x00100000, 0x2000 /* expect 0x0080 */
divide 0x00100000, 0x3fff /* expect 0x0040 */
divide 0x00100000, 0x4000 /* expect 0x0040 */
divide 0x00100000, 0x7fff /* expect 0x0020 */
divide 0x001fffff, 0x0040 /* expect 0x7fff */
divide 0x001fffff, 0x007f /* expect 0x4081 */
divide 0x001fffff, 0x0080 /* expect 0x3fff */
divide 0x001fffff, 0x00ff /* expect 0x2020 */
divide 0x001fffff, 0x0100 /* expect 0x1fff */
divide 0x001fffff, 0x01ff /* expect 0x1008 */
divide 0x001fffff, 0x0200 /* expect 0x0fff */
divide 0x001fffff, 0x03ff /* expect 0x0802 */
divide 0x001fffff, 0x0400 /* expect 0x07ff */
divide 0x001fffff, 0x07ff /* expect 0x0400 */
divide 0x001fffff, 0x0800 /* expect 0x03ff */
divide 0x001fffff, 0x0fff /* expect 0x0200 */
divide 0x001fffff, 0x1000 /* expect 0x01ff */
divide 0x001fffff, 0x1fff /* expect 0x0100 */
divide 0x001fffff, 0x2000 /* expect 0x00ff */
divide 0x001fffff, 0x3fff /* expect 0x0080 */
divide 0x001fffff, 0x4000 /* expect 0x007f */
divide 0x001fffff, 0x7fff /* expect 0x0040 */
divide 0x00200000, 0x007f /* expect 0x4081 */
divide 0x00200000, 0x0080 /* expect 0x4000 */
divide 0x00200000, 0x00ff /* expect 0x2020 */
divide 0x00200000, 0x0100 /* expect 0x2000 */
divide 0x00200000, 0x01ff /* expect 0x1008 */
divide 0x00200000, 0x0200 /* expect 0x1000 */
divide 0x00200000, 0x03ff /* expect 0x0802 */
divide 0x00200000, 0x0400 /* expect 0x0800 */
divide 0x00200000, 0x07ff /* expect 0x0400 */
divide 0x00200000, 0x0800 /* expect 0x0400 */
divide 0x00200000, 0x0fff /* expect 0x0200 */
divide 0x00200000, 0x1000 /* expect 0x0200 */
divide 0x00200000, 0x1fff /* expect 0x0100 */
divide 0x00200000, 0x2000 /* expect 0x0100 */
divide 0x00200000, 0x3fff /* expect 0x0080 */
divide 0x00200000, 0x4000 /* expect 0x0080 */
divide 0x00200000, 0x7fff /* expect 0x0040 */
divide 0x003fffff, 0x0080 /* expect 0x7fff */
divide 0x003fffff, 0x00ff /* expect 0x4040 */
divide 0x003fffff, 0x0100 /* expect 0x3fff */
divide 0x003fffff, 0x01ff /* expect 0x2010 */
divide 0x003fffff, 0x0200 /* expect 0x1fff */
divide 0x003fffff, 0x03ff /* expect 0x1004 */
divide 0x003fffff, 0x0400 /* expect 0x0fff */
divide 0x003fffff, 0x07ff /* expect 0x0801 */
divide 0x003fffff, 0x0800 /* expect 0x07ff */
divide 0x003fffff, 0x0fff /* expect 0x0400 */
divide 0x003fffff, 0x1000 /* expect 0x03ff */
divide 0x003fffff, 0x1fff /* expect 0x0200 */
divide 0x003fffff, 0x2000 /* expect 0x01ff */
divide 0x003fffff, 0x3fff /* expect 0x0100 */
divide 0x003fffff, 0x4000 /* expect 0x00ff */
divide 0x003fffff, 0x7fff /* expect 0x0080 */
divide 0x00400000, 0x00ff /* expect 0x4040 */
divide 0x00400000, 0x0100 /* expect 0x4000 */
divide 0x00400000, 0x01ff /* expect 0x2010 */
divide 0x00400000, 0x0200 /* expect 0x2000 */
divide 0x00400000, 0x03ff /* expect 0x1004 */
divide 0x00400000, 0x0400 /* expect 0x1000 */
divide 0x00400000, 0x07ff /* expect 0x0801 */
divide 0x00400000, 0x0800 /* expect 0x0800 */
divide 0x00400000, 0x0fff /* expect 0x0400 */
divide 0x00400000, 0x1000 /* expect 0x0400 */
divide 0x00400000, 0x1fff /* expect 0x0200 */
divide 0x00400000, 0x2000 /* expect 0x0200 */
divide 0x00400000, 0x3fff /* expect 0x0100 */
divide 0x00400000, 0x4000 /* expect 0x0100 */
divide 0x00400000, 0x7fff /* expect 0x0080 */
divide 0x007fffff, 0x0100 /* expect 0x7fff */
divide 0x007fffff, 0x01ff /* expect 0x4020 */
divide 0x007fffff, 0x0200 /* expect 0x3fff */
divide 0x007fffff, 0x03ff /* expect 0x2008 */
divide 0x007fffff, 0x0400 /* expect 0x1fff */
divide 0x007fffff, 0x07ff /* expect 0x1002 */
divide 0x007fffff, 0x0800 /* expect 0x0fff */
divide 0x007fffff, 0x0fff /* expect 0x0800 */
divide 0x007fffff, 0x1000 /* expect 0x07ff */
divide 0x007fffff, 0x1fff /* expect 0x0400 */
divide 0x007fffff, 0x2000 /* expect 0x03ff */
divide 0x007fffff, 0x3fff /* expect 0x0200 */
divide 0x007fffff, 0x4000 /* expect 0x01ff */
divide 0x007fffff, 0x7fff /* expect 0x0100 */
divide 0x00800000, 0x01ff /* expect 0x4020 */
divide 0x00800000, 0x0200 /* expect 0x4000 */
divide 0x00800000, 0x03ff /* expect 0x2008 */
divide 0x00800000, 0x0400 /* expect 0x2000 */
divide 0x00800000, 0x07ff /* expect 0x1002 */
divide 0x00800000, 0x0800 /* expect 0x1000 */
divide 0x00800000, 0x0fff /* expect 0x0800 */
divide 0x00800000, 0x1000 /* expect 0x0800 */
divide 0x00800000, 0x1fff /* expect 0x0400 */
divide 0x00800000, 0x2000 /* expect 0x0400 */
divide 0x00800000, 0x3fff /* expect 0x0200 */
divide 0x00800000, 0x4000 /* expect 0x0200 */
divide 0x00800000, 0x7fff /* expect 0x0100 */
divide 0x00ffffff, 0x0200 /* expect 0x7fff */
divide 0x00ffffff, 0x03ff /* expect 0x4010 */
divide 0x00ffffff, 0x0400 /* expect 0x3fff */
divide 0x00ffffff, 0x07ff /* expect 0x2004 */
divide 0x00ffffff, 0x0800 /* expect 0x1fff */
divide 0x00ffffff, 0x0fff /* expect 0x1001 */
divide 0x00ffffff, 0x1000 /* expect 0x0fff */
divide 0x00ffffff, 0x1fff /* expect 0x0800 */
divide 0x00ffffff, 0x2000 /* expect 0x07ff */
divide 0x00ffffff, 0x3fff /* expect 0x0400 */
divide 0x00ffffff, 0x4000 /* expect 0x03ff */
divide 0x00ffffff, 0x7fff /* expect 0x0200 */
divide 0x01000000, 0x03ff /* expect 0x4010 */
divide 0x01000000, 0x0400 /* expect 0x4000 */
divide 0x01000000, 0x07ff /* expect 0x2004 */
divide 0x01000000, 0x0800 /* expect 0x2000 */
divide 0x01000000, 0x0fff /* expect 0x1001 */
divide 0x01000000, 0x1000 /* expect 0x1000 */
divide 0x01000000, 0x1fff /* expect 0x0800 */
divide 0x01000000, 0x2000 /* expect 0x0800 */
divide 0x01000000, 0x3fff /* expect 0x0400 */
divide 0x01000000, 0x4000 /* expect 0x0400 */
divide 0x01000000, 0x7fff /* expect 0x0200 */
divide 0x01ffffff, 0x0400 /* expect 0x7fff */
divide 0x01ffffff, 0x07ff /* expect 0x4008 */
divide 0x01ffffff, 0x0800 /* expect 0x3fff */
divide 0x01ffffff, 0x0fff /* expect 0x2002 */
divide 0x01ffffff, 0x1000 /* expect 0x1fff */
divide 0x01ffffff, 0x1fff /* expect 0x1000 */
divide 0x01ffffff, 0x2000 /* expect 0x0fff */
divide 0x01ffffff, 0x3fff /* expect 0x0800 */
divide 0x01ffffff, 0x4000 /* expect 0x07ff */
divide 0x01ffffff, 0x7fff /* expect 0x0400 */
divide 0x02000000, 0x07ff /* expect 0x4008 */
divide 0x02000000, 0x0800 /* expect 0x4000 */
divide 0x02000000, 0x0fff /* expect 0x2002 */
divide 0x02000000, 0x1000 /* expect 0x2000 */
divide 0x02000000, 0x1fff /* expect 0x1000 */
divide 0x02000000, 0x2000 /* expect 0x1000 */
divide 0x02000000, 0x3fff /* expect 0x0800 */
divide 0x02000000, 0x4000 /* expect 0x0800 */
divide 0x02000000, 0x7fff /* expect 0x0400 */
divide 0x03ffffff, 0x0800 /* expect 0x7fff */
divide 0x03ffffff, 0x0fff /* expect 0x4004 */
divide 0x03ffffff, 0x1000 /* expect 0x3fff */
divide 0x03ffffff, 0x1fff /* expect 0x2001 */
divide 0x03ffffff, 0x2000 /* expect 0x1fff */
divide 0x03ffffff, 0x3fff /* expect 0x1000 */
divide 0x03ffffff, 0x4000 /* expect 0x0fff */
divide 0x03ffffff, 0x7fff /* expect 0x0800 */
divide 0x04000000, 0x0fff /* expect 0x4004 */
divide 0x04000000, 0x1000 /* expect 0x4000 */
divide 0x04000000, 0x1fff /* expect 0x2001 */
divide 0x04000000, 0x2000 /* expect 0x2000 */
divide 0x04000000, 0x3fff /* expect 0x1000 */
divide 0x04000000, 0x4000 /* expect 0x1000 */
divide 0x04000000, 0x7fff /* expect 0x0800 */
divide 0x07ffffff, 0x1000 /* expect 0x7fff */
divide 0x07ffffff, 0x1fff /* expect 0x4002 */
divide 0x07ffffff, 0x2000 /* expect 0x3fff */
divide 0x07ffffff, 0x3fff /* expect 0x2000 */
divide 0x07ffffff, 0x4000 /* expect 0x1fff */
divide 0x07ffffff, 0x7fff /* expect 0x1000 */
divide 0x08000000, 0x1fff /* expect 0x4002 */
divide 0x08000000, 0x2000 /* expect 0x4000 */
divide 0x08000000, 0x3fff /* expect 0x2000 */
divide 0x08000000, 0x4000 /* expect 0x2000 */
divide 0x08000000, 0x7fff /* expect 0x1000 */
divide 0x0fffffff, 0x2000 /* expect 0x7fff */
divide 0x0fffffff, 0x3fff /* expect 0x4001 */
divide 0x0fffffff, 0x4000 /* expect 0x3fff */
divide 0x0fffffff, 0x7fff /* expect 0x2000 */
divide 0x10000000, 0x3fff /* expect 0x4001 */
divide 0x10000000, 0x4000 /* expect 0x4000 */
divide 0x10000000, 0x7fff /* expect 0x2000 */
divide 0x1fffffff, 0x4000 /* expect 0x7fff */
divide 0x1fffffff, 0x7fff /* expect 0x4000 */
divide 0x20000000, 0x7fff /* expect 0x4000 */
pass
|
stsp/binutils-ia16
| 6,030
|
sim/testsuite/bfin/c_dsp32mult_dr_t.s
|
//Original:/testcases/core/c_dsp32mult_dr_t/c_dsp32mult_dr_t.dsp
// Spec Reference: dsp32mult single dr t
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (T);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (T);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (T);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (T);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (T);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (T);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (T);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (T);
CHECKREG r0, 0x39F939F9;
CHECKREG r1, 0x24C1D139;
CHECKREG r2, 0xEAD010A5;
CHECKREG r3, 0x11180A8D;
CHECKREG r4, 0x39F939F9;
CHECKREG r5, 0x369DBA7F;
CHECKREG r6, 0x369DBA7F;
CHECKREG r7, 0x33735352;
imm32 r0, 0x9923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1324b735;
imm32 r3, 0x99060037;
imm32 r4, 0x809bcd39;
imm32 r5, 0xb0a99f3b;
imm32 r6, 0xa00c093d;
imm32 r7, 0x12467093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (T);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (T);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (T);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (T);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (T);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (T);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (T);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (T);
CHECKREG r0, 0xFF41FF41;
CHECKREG r1, 0x00990099;
CHECKREG r2, 0xF51DF51D;
CHECKREG r3, 0x08C208C2;
CHECKREG r4, 0xF51DF51D;
CHECKREG r5, 0x3A8FF099;
CHECKREG r6, 0xFFE00008;
CHECKREG r7, 0xFFD3FFD3;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (T);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (T);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (T);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (T);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (T);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (T);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (T);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (T);
CHECKREG r0, 0x33491B29;
CHECKREG r1, 0x0E7AF851;
CHECKREG r2, 0xF851F851;
CHECKREG r3, 0x022A022B;
CHECKREG r4, 0x33491B29;
CHECKREG r5, 0xF954FC77;
CHECKREG r6, 0xFF3FFE95;
CHECKREG r7, 0x002F0059;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xe0060066;
imm32 r4, 0x9eab9d69;
imm32 r5, 0x10ecef6b;
imm32 r6, 0x800ee06d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (T);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (T);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (T);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (T);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (T);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (T);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (T);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (T);
CHECKREG r0, 0x7FE407C9;
CHECKREG r1, 0xEDBBFB7E;
CHECKREG r2, 0xEDBBFB7E;
CHECKREG r3, 0x029B029B;
CHECKREG r4, 0x123E011C;
CHECKREG r5, 0x029A029A;
CHECKREG r6, 0x7FE407C9;
CHECKREG r7, 0x1242011C;
// mix order
imm32 r0, 0xac23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x90accd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x1246fc0f;
R0.H = R5.L * R7.L, R0.L = R5.H * R7.H (T);
R1.H = R7.L * R6.L, R1.L = R7.L * R6.H (T);
R2.H = R6.H * R5.H, R2.L = R6.H * R5.L (T);
R3.H = R0.L * R4.L, R3.L = R0.L * R4.L (T);
R4.H = R1.L * R5.H, R4.L = R1.L * R5.L (T);
R5.H = R3.H * R4.L, R5.L = R3.H * R4.L (T);
R6.H = R2.L * R5.L, R6.L = R2.L * R5.L (T);
R7.H = R4.H * R0.L, R7.L = R4.H * R0.H (T);
CHECKREG r0, 0x00FD0261;
CHECKREG r1, 0x01F8FFFF;
CHECKREG r2, 0x0001FFFC;
CHECKREG r3, 0xFF0DFF0D;
CHECKREG r4, 0xFFFF0000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R4.H = R7.H * R0.H, R4.L = R7.H * R0.L (T);
R5.H = R6.H * R1.H, R5.L = R6.L * R1.L (T);
R6.H = R5.H * R2.H, R6.L = R5.H * R2.L (T);
R7.H = R4.H * R3.H, R7.L = R4.H * R3.L (T);
R0.H = R3.H * R4.H, R0.L = R3.H * R4.L (T);
R2.H = R2.H * R5.H, R2.L = R2.H * R5.L (T);
R1.H = R1.H * R6.H, R1.L = R1.H * R6.L (T);
R3.H = R0.L * R7.H, R3.L = R0.H * R7.H (T);
CHECKREG r0, 0xFFEB0015;
CHECKREG r1, 0xFFFF0001;
CHECKREG r2, 0x0001FDBF;
CHECKREG r3, 0xFFFF0000;
CHECKREG r4, 0xF3E20CE9;
CHECKREG r5, 0xFFFB0846;
CHECKREG r6, 0x0001FFFB;
CHECKREG r7, 0xFFEB048A;
imm32 r0, 0xfb235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13f46705;
imm32 r3, 0x000f0007;
imm32 r4, 0x90abfd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (T);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (T);
R0.H = R2.L * R0.L, R0.L = R2.L * R0.H (T);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (T);
R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (T);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (T);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (T);
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (T);
CHECKREG r0, 0x0005FFFF;
CHECKREG r1, 0xE5340299;
CHECKREG r2, 0x00AA0008;
CHECKREG r3, 0xF91BD5BD;
CHECKREG r4, 0xFFFFFFFC;
CHECKREG r5, 0x00DEFA7E;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFB2D001F;
imm32 r0, 0xab2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13246d05;
imm32 r3, 0x000600d7;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c500d;
imm32 r7, 0x1246760f;
R5.H = R5.L * R2.L, R5.L = R5.L * R2.H (T);
R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (T);
R1.H = R7.L * R4.L, R1.L = R7.L * R4.H (T);
R0.H = R1.L * R5.H, R0.L = R1.L * R5.L (T);
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (T);
R4.H = R2.L * R7.H, R4.L = R2.H * R7.L (T);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (T);
R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (T);
CHECKREG r0, 0x0B0B01F1;
CHECKREG r1, 0xD0FE9933;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00030012;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0xF23FFD95;
CHECKREG r6, 0x00000003;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 2,888
|
sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_sn.s
|
//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0xd90e108f;
imm32 p1, 0x1401101f;
imm32 p2, 0x3204108e;
imm32 p3, 0xd93f1084;
imm32 p4, 0xeb04106f;
imm32 p5, 0xa90e5089;
ASTAT = R0;
CC = R1; // cc2dreg
R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac
I0 = P1; // regmv
IF CC R1 = R3; // ccmov
CC = ! CC; // cc2dreg
R4.H = R1.L + R0.L (S); // dsp32alu
M0 = P2; // regmv
IF CC R3 = R2; // ccmov
CC = R0 < R1; // ccflag
R4.L = R5.L << 1; // dsp32shiftimm
I0 += M0; // dagmodim
R2 = R0 + R2; // comp3op dr plus dr
IF CC R4 = R5; // ccmov
CC = R2 == R3; // ccflag
R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult
R5 = R0 + R2; // comp3op dr plus dr
BITCLR( R6 , 1 );
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac
IF !CC JUMP LABEL1; // branch on
CC = ! CC; // cc2dreg
P1.L = 0x3000; // ldimmhalf
A0 += A1 (W32); // dsp32alu a0 + a1
IF !CC JUMP LABEL2 (BP); // branch
LABEL1:
R6 = R6 + R2;
JUMP.S END;
LABEL2:
R7 = R5 - R7;
CC = R0 < R1; // ccflag
P2 = A0.w;
IF CC JUMP END (BP); // branch
P3 = A1.w;
R5 = R5 + R7;
END:
CHECKREG r0, 0xA08D2311;
CHECKREG r1, 0x07300007;
CHECKREG r2, 0xA08E3868;
CHECKREG r3, 0x07300007;
CHECKREG r4, 0x609950AA;
CHECKREG r5, 0x411B5B79;
CHECKREG r6, 0x056C9760;
CHECKREG r7, 0x4116F22D;
CHECKREG p1, 0x14013000;
CHECKREG p2, 0x033352A4;
CHECKREG p3, 0xD93F1084;
imm32 r0, 0x408d2711;
imm32 r1, 0x15124040;
imm32 r2, 0x62661557;
imm32 r3, 0x073b0007;
imm32 r4, 0x01f49088;
imm32 r5, 0x6e2959aa;
imm32 r6, 0xa0b506cc;
imm32 r7, 0x00000002;
CC = R1; // cc2dreg
P1 = -15; // compi2opp_pr_eq_i7
R2 = ROT R2 BY 1; // dsp32shiftim_rot
CC = ! CC; // cc2dreg
R3 >>= R7; // alu2op sft
R4 = ROT R0 BY -3; // dsp32shiftim_rot
CC = R0 < R1; // ccflag
R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair
R5 = R0 + R2; // comp3op dr plus dr
R6 = ROT R4 BY 5; // dsp32shiftim_rot
CC = R2 == R3; // ccflag
P2 = R1; // regmv
R4.H = R1.L + R3.H (S); // dsp32alu
I0 = P1; // regmv
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
I0 += 2;
P3 = I0;
R3.L = R5.L << 1; // dsp32shiftimm
R7 = ROT R6 BY R7.L; // dsp32shiftim_rot
CHECKREG r0, 0x408D2711;
CHECKREG r1, 0x2ACFF368;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xFFFD4E22;
CHECKREG r4, 0x403DA4E2;
CHECKREG r5, 0x408D2711;
CHECKREG r6, 0x15BD33A8;
CHECKREG r7, 0x56F4CEA2;
CHECKREG p1, 0xFFFFFFF1;
CHECKREG p2, 0x15124040;
CHECKREG p3, 0xFFFFFFF3;
pass
|
stsp/binutils-ia16
| 3,312
|
sim/testsuite/bfin/random_0009.S
|
# Verify ASTAT bits are set correctly during dsp mac insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x16ba2677;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x80007fff;
A0 -= R4.H * R4.H (W32);
checkreg A0.w, 0x96ba2678;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3c30c800 | _VS | _AV0S | _AC1 | _CC);
dmm32 A0.w, 0xf170d0c7;
dmm32 A0.x, 0xffffffff;
imm32 R2, 0x80008000;
A0 -= R2.H * R2.L (W32);
checkreg A0.w, 0x80000000;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x3c30c800 | _VS | _AV0S | _AV0 | _AC1 | _CC);
dmm32 ASTAT, (0x6c200880 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AN);
dmm32 A0.x, 0x560a1c52;
dmm32 A0.x, 0xffffffbb;
imm32 R5, 0x8000ffff;
A0 = R5.H * R5.H (W32);
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x6c200880 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _AN);
dmm32 ASTAT, (0x58908a90 | _VS | _AC1 | _AC0 | _AQ);
dmm32 A0.w, 0x00c5a4e0;
dmm32 A0.x, 0x00000000;
imm32 R0, 0xffffb33a;
imm32 R2, 0xffffb33a;
imm32 R3, 0xb33a4cc6;
R2 = (A0 -= R0.L * R3.H) (FU);
checkreg R2, 0x00000000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x58908a90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY);
dmm32 ASTAT, (0x2cc00c90 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x00a38000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x2aa2ffff;
imm32 R1, 0xff5c711e;
imm32 R4, 0x2913dc90;
R0 = (A0 -= R4.L * R1.L) (IU);
checkreg R0, 0x00000000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x2cc00c90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x3880c280 | _VS | _AC1 | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x139ad315;
imm32 R6, 0x7fff0000;
R4.L = (A0 -= R6.H * R6.H) (FU);
checkreg R4, 0x139a0000;
checkreg ASTAT, (0x3880c280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AZ);
dmm32 ASTAT, (0x48408290 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x6b426a69;
dmm32 A0.x, 0xffffffba;
imm32 R0, 0x24038000;
imm32 R2, 0xf62c7780;
imm32 R3, 0x5a64f8e8;
R2.L = (A0 -= R3.L * R0.L) (IH);
checkreg R2, 0xf62c8000;
checkreg A0.w, 0x80000000;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x48408290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x7c00c210 | _VS | _AC1 | _AN);
dmm32 A1.w, 0x730173e9;
dmm32 A1.x, 0xffffffae;
imm32 R4, 0x8000ffff;
imm32 R5, 0x738559e8;
R5.H = (A1 -= R4.L * R5.L) (M, IH);
checkreg R5, 0x800059e8;
checkreg A1.w, 0x80000000;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x7c00c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY | _AN);
dmm32 ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AZ);
dmm32 A0.w, 0x033a05f0;
dmm32 A0.x, 0x00000000;
imm32 R3, 0x5992dd5a;
imm32 R4, 0x098a889e;
imm32 R6, 0x8000de08;
R6.L = (A0 -= R4.L * R3.H) (TFU);
checkreg R6, 0x80000000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AZ);
pass
|
stsp/binutils-ia16
| 1,531
|
sim/testsuite/bfin/c_dagmodim_lz_inc_dec.s
|
//Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp
// Spec Reference: dagmodim L=0, I incremented & decremented (by M)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x10001000;
imm32 i1, 0x02001100;
imm32 i2, 0x00301010;
imm32 i3, 0x00041001;
imm32 m0, 0x00000005;
imm32 m1, 0x00000006;
imm32 m2, 0x00000007;
imm32 m3, 0x00000008;
I0 += M0;
I1 += M1;
I2 += M2;
I3 += M3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += M1;
I1 += M2;
I2 += M3;
I3 += M0;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x10001005;
CHECKREG r1, 0x02001106;
CHECKREG r2, 0x00301017;
CHECKREG r3, 0x00041009;
CHECKREG r4, 0x1000100B;
CHECKREG r5, 0x0200110D;
CHECKREG r6, 0x0030101F;
CHECKREG r7, 0x0004100E;
I0 -= M2;
I1 -= M3;
I2 -= M0;
I3 -= M1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= M3;
I1 -= M2;
I2 -= M1;
I3 -= M0;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x10001004;
CHECKREG r1, 0x02001105;
CHECKREG r2, 0x0030101A;
CHECKREG r3, 0x00041008;
CHECKREG r4, 0x10000FFC;
CHECKREG r5, 0x020010FE;
CHECKREG r6, 0x00301014;
CHECKREG r7, 0x00041003;
I0 += M3 (BREV);
I1 += M0 (BREV);
I2 += M1 (BREV);
I3 += M2 (BREV);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += M2 (BREV);
I1 += M3 (BREV);
I2 += M0 (BREV);
I3 += M1 (BREV);
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x10000FF2;
CHECKREG r1, 0x020010F8;
CHECKREG r2, 0x00301011;
CHECKREG r3, 0x00041005;
CHECKREG r4, 0x10000FF4;
CHECKREG r5, 0x020010F4;
CHECKREG r6, 0x00301014;
CHECKREG r7, 0x00041000;
pass
|
stsp/binutils-ia16
| 9,982
|
sim/testsuite/bfin/se_loop_nest_ppm_1.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_1/se_loop_nest_ppm_1.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x4 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
LSETUP ( l0s , l0s ) LC1 = P1;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l1s , l1e ) LC0 = P0;
LSETUP ( l1s , l1e ) LC1 = P1;
l1s:R5 += 1;
l1e:[ -- SP ] = ( R7:5 );
LSETUP ( l2s , l2e ) LC0 = P0;
LSETUP ( l2s , l2e ) LC1 = P1;
l2s:R5 += 1;
R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
LSETUP ( l3s , l3e ) LC1 = P1;
l3s:R5 += 1;
R6 += 2;
R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LSETUP ( l4s , l4e ) LC0 = P0;
LSETUP ( l4s , l4e ) LC1 = P1;
l4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LSETUP ( l5s , l5e ) LC0 = P0;
LSETUP ( l5s , l5e ) LC1 = P1;
l5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
l5e:[ -- SP ] = ( R7:4 );
LSETUP ( l6s , l6e ) LC1 = P0;
LSETUP ( l6s , l6e ) LC1 = P1;
l6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 2,414
|
sim/testsuite/bfin/c_dsp32alu_alhwx.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_alhwx/c_dsp32alu_alhwx.dsp
// Spec Reference: dsp32alu alhwx
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
A1 = A0 = 0;
imm32 r0, 0xa5678911;
imm32 r1, 0xaa89ab1d;
imm32 r2, 0xd4b45515;
imm32 r3, 0xf66e7717;
imm32 r4, 0xe567f91b;
imm32 r5, 0x6789ae1d;
imm32 r6, 0xb4445515;
imm32 r7, 0x8666a7d7;
A0.L = R0.L;
A0.H = R0.H;
A0.x = R1.L;
R7 = A0.w;
R6 = A0.x;
R5.L = A0.x;
A1.L = R4.L;
A1.H = R4.H;
A1.x = R3.L;
R0 = A1.w;
R1 = A1.x;
R2.L = A1.x;
CHECKREG r0, 0xE567F91B;
CHECKREG r1, 0x00000017;
CHECKREG r2, 0xD4B40017;
CHECKREG r3, 0xF66E7717;
CHECKREG r4, 0xE567F91B;
CHECKREG r5, 0x6789001D;
CHECKREG r6, 0x0000001D;
CHECKREG r7, 0xA5678911;
imm32 r0, 0xe5678911;
imm32 r1, 0xaa89ab1d;
imm32 r2, 0xdfb45515;
imm32 r3, 0xf66e7717;
imm32 r4, 0xe5d7f91b;
imm32 r5, 0x67e9ae1d;
imm32 r6, 0xb4445515;
imm32 r7, 0x866aa7b7;
A0.L = R1.L;
A0.H = R1.H;
A0.x = R2.L;
R5 = A0.w;
R7 = A0.x;
R6.L = A0.x;
A1.L = R3.L;
A1.H = R3.H;
A1.x = R4.L;
R1 = A1.w;
R2 = A1.x;
R0.L = A1.x;
CHECKREG r0, 0xE567001B;
CHECKREG r1, 0xF66E7717;
CHECKREG r2, 0x0000001B;
CHECKREG r3, 0xF66E7717;
CHECKREG r4, 0xE5D7F91B;
CHECKREG r5, 0xAA89AB1D;
CHECKREG r6, 0xB4440015;
CHECKREG r7, 0x00000015;
imm32 r0, 0x35678911;
imm32 r1, 0xa489ab1d;
imm32 r2, 0xd4545515;
imm32 r3, 0xf6667717;
imm32 r4, 0x9567f91b;
imm32 r5, 0x6a89ae1d;
imm32 r6, 0xb4445515;
imm32 r7, 0x8666a7d7;
A0.L = R3.L;
A0.H = R3.H;
A0.x = R4.L;
R0 = A0.w;
R1 = A0.x;
R2.L = A0.x;
A1.L = R5.L;
A1.H = R6.H;
A1.x = R7.L;
R7 = A1.w;
R5 = A1.x;
R5.L = A1.x;
CHECKREG r0, 0xF6667717;
CHECKREG r1, 0x0000001B;
CHECKREG r2, 0xD454001B;
CHECKREG r3, 0xF6667717;
CHECKREG r4, 0x9567F91B;
CHECKREG r5, 0xffffffD7;
CHECKREG r6, 0xB4445515;
CHECKREG r7, 0xB444AE1D;
imm32 r0, 0xd5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0xd3b45515;
imm32 r3, 0xf66e7717;
imm32 r4, 0xe5d7f91b;
imm32 r5, 0x67e9ae1d;
imm32 r6, 0xb4445515;
imm32 r7, 0x889aa7b7;
A0.L = R4.L;
A0.H = R5.H;
A0.x = R6.L;
R1 = A0.w;
R2 = A0.x;
R3.L = A0.x;
A1.L = R0.L;
A1.H = R0.H;
A1.x = R7.L;
R4 = A1.w;
R5 = A1.x;
R6.L = A1.x;
CHECKREG r0, 0xD5678911;
CHECKREG r1, 0x67E9F91B;
CHECKREG r2, 0x00000015;
CHECKREG r3, 0xF66E0015;
CHECKREG r4, 0xD5678911;
CHECKREG r5, 0xffffffB7;
CHECKREG r6, 0xB444ffB7;
CHECKREG r7, 0x889AA7B7;
pass
|
stsp/binutils-ia16
| 1,135
|
sim/testsuite/bfin/cec-syscfg-ssstep.S
|
# Blackfin testcase for hardware single stepping
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set up exception handler
imm32 P4, EVT3;
loadsym R1, _evx;
[P4] = R1;
# Enable single stepping
R0 = 1;
SYSCFG = R0;
# Lower to the code we want to single step through
R1 = 1;
imm32 R5, 0xffff
R6 = 0;
R7 = 0;
loadsym R1, _usr;
RETI = R1;
RTI;
_usr:
# Single step and set a new bit every time
BITSET (R7, 0);
BITSET (R7, 1);
BITSET (R7, 2);
BITSET (R7, 3);
BITSET (R7, 4);
BITSET (R7, 5);
BITSET (R7, 6);
BITSET (R7, 7);
BITSET (R7, 8);
BITSET (R7, 9);
BITSET (R7, 10);
BITSET (R7, 11);
BITSET (R7, 12);
BITSET (R7, 13);
BITSET (R7, 14);
BITSET (R7, 15);
JUMP fail_lvl;
_evx:
# Make sure exception reason is single step
R3 = SEQSTAT;
R4 = 0x3f;
R3 = R3 & R4;
R4 = 0x10;
CC = R3 == R4;
IF !CC JUMP fail_lvl;
# Set a new bit in R6 every single step to match R7
CC = R1;
R6 = ROT R6 BY 1;
CC = R6 == R7;
IF !CC JUMP fail_lvl;
# Do it through each bit
CC = R5 == R6;
IF CC JUMP pass_lvl;
RTX;
pass_lvl:
dbg_pass;
fail_lvl:
dbg_fail;
|
stsp/binutils-ia16
| 5,429
|
sim/testsuite/bfin/c_dsp32alu_rpm.s
|
//Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp
// Spec Reference: dsp32alu dreg = +/- ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x65678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34845515;
imm32 r3, 0x46697717;
imm32 r4, 0x5567191b;
imm32 r5, 0x6789a31d;
imm32 r6, 0x74445545;
imm32 r7, 0x86667779;
R0 = R0 +|- R0;
R1 = R0 +|- R1;
R2 = R0 +|- R2;
R3 = R0 +|- R3;
R4 = R0 +|- R4;
R5 = R0 +|- R5;
R6 = R0 +|- R6;
R7 = R0 +|- R7;
CHECKREG r0, 0xCACE0000;
CHECKREG r1, 0xF25754E3;
CHECKREG r2, 0xFF52AAEB;
CHECKREG r3, 0x113788E9;
CHECKREG r4, 0x2035E6E5;
CHECKREG r5, 0x32575CE3;
CHECKREG r6, 0x3F12AABB;
CHECKREG r7, 0x51348887;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = R1 +|- R0;
R1 = R1 +|- R1;
R2 = R1 +|- R2;
R3 = R1 +|- R3;
R4 = R1 +|- R4;
R5 = R1 +|- R5;
R6 = R1 +|- R6;
R7 = R1 +|- R7;
CHECKREG r0, 0x3CF02202;
CHECKREG r1, 0x4F120000;
CHECKREG r2, 0x0356AADB;
CHECKREG r3, 0x157888D9;
CHECKREG r4, 0x279A66D7;
CHECKREG r5, 0x39BC44D5;
CHECKREG r6, 0x4BDE22D3;
CHECKREG r7, 0x5E000001;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = R2 +|- R0;
R1 = R2 +|- R1;
R2 = R2 +|- R2;
R3 = R2 +|- R3;
R4 = R2 +|- R4;
R5 = R2 +|- R5;
R6 = R2 +|- R6;
R7 = R2 +|- R7;
CHECKREG r0, 0x84ABCBAA;
CHECKREG r1, 0xA5CDA988;
CHECKREG r2, 0x86880000;
CHECKREG r3, 0xEAEE8889;
CHECKREG r4, 0xCBEF7655;
CHECKREG r5, 0xED115433;
CHECKREG r6, 0xCDCCAAAB;
CHECKREG r7, 0xEEEE8889;
imm32 r0, 0xa567892b;
imm32 r1, 0xaa89ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6a67727;
imm32 r0, 0x9a67892b;
imm32 r1, 0xa7a9ab2d;
imm32 r2, 0xb44a5525;
imm32 r3, 0xc666a727;
R0 = R3 +|- R0;
R1 = R3 +|- R1;
R2 = R3 +|- R2;
R3 = R3 +|- R3;
R4 = R3 +|- R4;
R5 = R3 +|- R5;
R6 = R3 +|- R6;
R7 = R3 +|- R7;
CHECKREG r0, 0x60CD1DFC;
CHECKREG r1, 0x6E0FFBFA;
CHECKREG r2, 0x7AB05202;
CHECKREG r3, 0x8CCC0000;
CHECKREG r4, 0x58BB89AB;
CHECKREG r5, 0x79DDABCD;
CHECKREG r6, 0x5A985555;
CHECKREG r7, 0x7BBA7777;
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0 = R4 +|- R0;
R1 = R4 +|- R1;
R2 = R4 +|- R2;
R3 = R4 +|- R3;
R4 = R4 +|- R4;
R5 = R4 +|- R5;
R6 = R4 +|- R6;
R7 = R4 +|- R7;
CHECKREG r0, 0xCDAF0C4A;
CHECKREG r1, 0xEFD1EA38;
CHECKREG r2, 0xCCCD4030;
CHECKREG r3, 0xEEDE3E1E;
CHECKREG r4, 0x10F00000;
CHECKREG r5, 0xBB7A44A5;
CHECKREG r6, 0xDD8C227B;
CHECKREG r7, 0xFF9E0061;
imm32 r0, 0x456b89ab;
imm32 r1, 0x69764bcd;
imm32 r2, 0x49736564;
imm32 r3, 0x61278394;
imm32 r4, 0x98876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x12346fff;
R0 = R5 +|- R0;
R1 = R5 +|- R1;
R2 = R5 +|- R2;
R3 = R5 +|- R3;
R4 = R5 +|- R4;
R5 = R5 +|- R5;
R6 = R5 +|- R6;
R7 = R5 +|- R7;
CHECKREG r0, 0xF0158210;
CHECKREG r1, 0x1420BFEE;
CHECKREG r2, 0xF41DA657;
CHECKREG r3, 0x0BD18827;
CHECKREG r4, 0x4331A782;
CHECKREG r5, 0x55540000;
CHECKREG r6, 0x2220E223;
CHECKREG r7, 0x67889001;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R0 = R6 +|- R0;
R1 = R6 +|- R1;
R2 = R6 +|- R2;
R3 = R6 +|- R3;
R4 = R6 +|- R4;
R5 = R6 +|- R5;
R6 = R6 +|- R6;
R7 = R6 +|- R7;
CHECKREG r0, 0x4999572B;
CHECKREG r1, 0x6B9B4509;
CHECKREG r2, 0x07772981;
CHECKREG r3, 0x6A98295F;
CHECKREG r4, 0x16663A3D;
CHECKREG r5, 0x4999056B;
CHECKREG r6, 0x08640000;
CHECKREG r7, 0x1A98A981;
imm32 r0, 0xb76789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x2b456755;
imm32 r3, 0x56789007;
imm32 r4, 0x78bab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcdbff7;
R0 = R7 +|- R0;
R1 = R7 +|- R1;
R2 = R7 +|- R2;
R3 = R7 +|- R3;
R4 = R7 +|- R4;
R5 = R7 +|- R5;
R6 = R7 +|- R6;
R7 = R7 +|- R7;
CHECKREG r0, 0x6334364C;
CHECKREG r1, 0x1346142A;
CHECKREG r2, 0xD71258A2;
CHECKREG r3, 0x02452FF0;
CHECKREG r4, 0x2487085E;
CHECKREG r5, 0x5677B43C;
CHECKREG r6, 0x3578A27A;
CHECKREG r7, 0x579A0000;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R4 = R4 +|- R7 (S);
R5 = R5 +|- R5 (CO);
R2 = R6 +|- R3 (SCO);
R6 = R0 +|- R4 (S);
R0 = R1 +|- R6 (S);
R2 = R2 +|- R1 (CO);
R1 = R3 +|- R0 (CO);
R7 = R7 +|- R4 (SCO);
CHECKREG r0, 0x7FFF123C;
CHECKREG r1, 0x553BE665;
CHECKREG r2, 0x1ECBE769;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x2468001A;
CHECKREG r5, 0x00008ACE;
CHECKREG r6, 0x69CF3991;
CHECKREG r7, 0x5665369C;
imm32 r0, 0xb76789ab;
imm32 r1, 0x6b79abcd;
imm32 r2, 0x2b456755;
imm32 r3, 0x56b89007;
imm32 r4, 0x78bab799;
imm32 r5, 0xaaab0bbb;
imm32 r6, 0x89abbd7d;
imm32 r7, 0xabcd2bf7;
R3 = R4 +|- R0 (S);
R5 = R5 +|- R1 (SCO);
R2 = R2 +|- R2 (S);
R7 = R7 +|- R3 (CO);
R4 = R3 +|- R4 (CO);
R0 = R1 +|- R5 (S);
R1 = R0 +|- R6 (SCO);
R6 = R6 +|- R7 (SCO);
CHECKREG r0, 0x7FFF95A9;
CHECKREG r1, 0xD82C09AA;
CHECKREG r2, 0x568A0000;
CHECKREG r3, 0x30212DEE;
CHECKREG r4, 0x7655A8DB;
CHECKREG r5, 0x5FEE1624;
CHECKREG r6, 0xE18F87B4;
CHECKREG r7, 0xFE09DBEE;
pass
|
stsp/binutils-ia16
| 4,737
|
sim/testsuite/bfin/c_dspldst_st_dr_ippm.s
|
//Original:/testcases/core/c_dspldst_st_dr_ippm/c_dspldst_st_dr_ippm.dsp
// Spec Reference: c_dspldst st_dr_ippm
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
M0 = 4 (X);
M1 = 0x4 (X);
M2 = 0x4 (X);
M3 = 0x4 (X);
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
[ I0 ++ M0 ] = R0;
[ I1 ++ M1 ] = R1;
[ I2 ++ M2 ] = R2;
[ I3 ++ M3 ] = R3;
[ I0 ++ M1 ] = R1;
[ I1 ++ M2 ] = R2;
[ I2 ++ M3 ] = R3;
[ I3 ++ M0 ] = R4;
[ I0 ++ M2 ] = R3;
[ I1 ++ M3 ] = R4;
[ I2 ++ M0 ] = R5;
[ I3 ++ M1 ] = R6;
[ I0 ++ M3 ] = R4;
[ I1 ++ M0 ] = R5;
[ I2 ++ M1 ] = R6;
[ I3 ++ M2 ] = R7;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ M0 ];
R1 = [ I1 ++ M1 ];
R2 = [ I2 ++ M2 ];
R3 = [ I3 ++ M3 ];
R4 = [ I0 ++ M1 ];
R5 = [ I1 ++ M2 ];
R6 = [ I2 ++ M3 ];
R7 = [ I3 ++ M0 ];
CHECKREG r0, 0x0A234507;
CHECKREG r1, 0x1B345618;
CHECKREG r2, 0x2C456729;
CHECKREG r3, 0x3D56783A;
CHECKREG r4, 0x1B345618;
CHECKREG r5, 0x2C456729;
CHECKREG r6, 0x3D56783A;
CHECKREG r7, 0x4E67894B;
R0 = [ I0 ++ M2 ];
R1 = [ I1 ++ M3 ];
R2 = [ I2 ++ M0 ];
R3 = [ I3 ++ M1 ];
R4 = [ I0 ++ M3 ];
R5 = [ I1 ++ M0 ];
R6 = [ I2 ++ M1 ];
R7 = [ I3 ++ M2 ];
CHECKREG r0, 0x3D56783A;
CHECKREG r1, 0x4E67894B;
CHECKREG r2, 0x5F789A5C;
CHECKREG r3, 0x6089AB6D;
CHECKREG r4, 0x4E67894B;
CHECKREG r5, 0x5F789A5C;
CHECKREG r6, 0x6089AB6D;
CHECKREG r7, 0x719ABC7E;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 1,426
|
sim/testsuite/bfin/c_br_preg_stall_ac.s
|
//Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
/* This test likes to assume the current [SP] is valid */
SP += -12;
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
.ifndef BFIN_HOST;
imm32 p3, 0x00000013;
.endif
imm32 p4, 0x00000014;
P1 = 4;
P2 = 6;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
R0 = CC;
IF CC R1 = R0;
[ SP ] = P2;
P2 = [ SP ];
JUMP ( PC + P2 ); //brf LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1'
CC = ! CC;
LABEL2:
JUMP ( PC + P1 ); //brf LABEL3;
JUMP ( PC + P2 ); //BAD1; // UJUMP killed
LABEL3:
JUMP ( PC + P1 ); //brf LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
|
stsp/binutils-ia16
| 1,313
|
sim/testsuite/bfin/c_dsp32alu_a0a1s.s
|
//Original:/testcases/core/c_dsp32alu_a0a1s/c_dsp32alu_a0a1s.dsp
// Spec Reference: dsp32alu a0a1s
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
imm32 r0, 0x15678911;
imm32 r1, 0xa789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0xf6667717;
imm32 r4, 0xe567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xb4445515;
imm32 r7, 0x86667777;
// A0 & A1 types
A0 = R0;
A1 = R1;
R6 = A0.w;
R7 = A1.w;
A0 = 0;
A1 = 0;
R0 = A0.w;
R1 = A1.w;
A0 = R2;
A1 = R3;
A0 = A0 (S);
A1 = A1 (S);
R4 = A0.w;
R5 = A1.w;
A0 = A1;
R2 = A0.w;
A0 = R3;
A1 = A0;
R3 = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xF6667717;
CHECKREG r3, 0xF6667717;
CHECKREG r4, 0xD4445515;
CHECKREG r5, 0xF6667717;
CHECKREG r6, 0x15678911;
CHECKREG r7, 0xA789AB1D;
A1 = A0 = 0;
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
imm32 r0, 0xa1567891;
imm32 r1, 0xba789abd;
imm32 r2, 0xcd412355;
imm32 r3, 0xdf646777;
imm32 r4, 0xe567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xb4445515;
imm32 r7, 0xf666aeb7;
A0 = R4;
A1 = R5;
R0 = A0.w;
R1 = A1.w;
A0 = R6;
A1 = R7;
R2 = A0.w;
R3 = A1.w;
CHECKREG r0, 0xE567891B;
CHECKREG r1, 0x6789AB1D;
CHECKREG r2, 0xB4445515;
CHECKREG r3, 0xF666AEB7;
CHECKREG r4, 0xE567891B;
CHECKREG r5, 0x6789AB1D;
CHECKREG r6, 0xB4445515;
CHECKREG r7, 0xF666AEB7;
pass
|
stsp/binutils-ia16
| 1,555
|
sim/testsuite/bfin/x1.s
|
# mach: bfin
.include "testutils.inc"
start
// 0.5
imm32 r0, 0x40004000;
imm32 r1, 0x40004000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x40004000;
checkreg r3, 0;
imm32 r1, 0x10001000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x28002800;
checkreg r3, 0x18001800;
R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR);
checkreg r0, 0x20002000;
checkreg r1, 0x08000800;
R0 = 1;
R0 <<= 15;
R1 = R0 << 16;
R0 = R0 | R1;
R1 = R0;
checkreg r0, 0x80008000;
checkreg r1, 0x80008000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x80008000;
checkreg r3, 0x0;
R4 = 0;
R2 = R2 +|+ R4, R3 = R2 -|- R4 (S , ASR);
checkreg r2, 0xc000c000;
checkreg r3, 0xc000c000;
R2 = R2 +|+ R3, R3 = R2 -|- R3 (S , ASR);
checkreg r2, 0xc000c000;
checkreg r3, 0x0;
R4 = R2 +|+ R2, R5 = R2 -|- R2 (ASL);
checkreg r4, 0x0
checkreg r5, 0x0
R2 = R2 +|+ R2, R3 = R2 -|- R2 (S , ASL);
checkreg r2, 0x80008000;
checkreg r3, 0x0;
imm32 r0, 0x50004000;
imm32 r1, 0x40005000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
checkreg r2, 0x7fff7fff;
checkreg r3, 0x2000e000;
R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL);
checkreg r4, 0x20002000
checkreg r5, 0x2000e000
imm32 r0, 0x30001000;
imm32 r1, 0x10003000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
checkreg r2, 0x7fff7fff;
checkreg r3, 0x4000c000;
R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL);
checkreg r4, 0x80008000
checkreg r5, 0x4000c000
imm32 r0, 0x20001fff;
imm32 r1, 0x1fff2000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
checkreg r2, 0x7ffe7ffe;
checkreg r3, 0x0002fffe;
pass
|
stsp/binutils-ia16
| 5,485
|
sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S
|
//Original:/proj/frio/dv/testcases/core/c_progctrl_raise_rt_i_n/c_progctrl_raise_rt_i_n.dsp
// Spec Reference: progctrl raise rti rtn
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CHECK_INIT(p5, 0xe0000000);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
RAISE 2; // RTN
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
RAISE 15; // RTI
CHECKREG(r0, 0x0000000B);
CHECKREG(r1, 0x0000000C);
CHECKREG(r2, 0x0000000D);
CHECKREG(r3, 0x0000000E);
CHECKREG(r4, 0x00000007);
CHECKREG(r5, 0x00000008);
CHECKREG(r6, 0x00000009);
CHECKREG(r7, 0x0000000A);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
CHECKREG(r0, 0x00000002);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000005);
CHECKREG(r3, 0x00000006);
CHECKREG(r4, 0x00000007);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 2,844
|
sim/testsuite/bfin/conv_enc_gen.s
|
# mach: bfin
// GENERIC CONVOLUTIONAL ENCODER
// This a generic rate 1/n convolutional encoder. It computes n output
// bits for each input bit, based on n generic polynomials.
// It uses the set of BXOR_CC instructions to compute bit XOR
// reduction from a state masked by a polynomial. For an alternate
// solution based on assembling several partial words, as in
// the BDT benchmark, see file conv_enc.c. The solution presented
// here is slower than conv_enc.c, but more generic.
//
// Forward Shift Register
// -----------------------
// This solution implements the XOR function by shifting the state
// left by one, applying a mask to the state, and reducing
// the result with a bit XOR reduction function.
// ----- XOR------------> G0
// | | | |
// +------------------------------+
// | b0 b1 b2 b3 b14 b15 | <- in
// +------------------------------+
// | | | | |
// ----- XOR------------> G1
// Instruction BXOR computes the bit G0 or G1 and stores it into CC
// and also into a destination reg half. Here, we take CC and rotate it
// into an output register.
// However, one can also store the output bit directly by storing
// the register half where this bit is placed. This would result
// in an output structure similar to the one in the original function
// Convolutional_Encode(), where an entire half word holds a bit.
// The resulting execution speed would be roughly twice as fast,
// since there is no need to rotate output bit via CC.
.include "testutils.inc"
start
loadsym P0, input;
loadsym P1, output;
R1 = 0; R2 = 0;R3 = 0;
R2.L = 0;
R2.H = 0xa01d; // polynom 0
R3.L = 0;
R3.H = 0x12f4; // polynom 1
// load and CurrentState to upper half of A0
A1 = A0 = 0;
R0 = 0x0000;
A0.w = R0;
A0 = A0 << 16;
// l-loop counter is in P4
P4 = 2(Z);
// **** START l-LOOP *****
l$0:
// insert 16 bits of input into lower half of A0
// and advance input pointer
R0 = W [ P0 ++ ] (Z);
A0.L = R0.L;
P5 = 2 (Z);
LSETUP ( m$0 , m$0end ) LC0 = P5; // **** BEGIN m-LOOP *****
m$0:
P5 = 8 (Z);
LSETUP ( i$1 , i$1end ) LC1 = P5; // **** BEGIN i-LOOP *****
i$1:
R4.L = CC = BXORSHIFT( A0 , R2 ); // polynom0 -> CC
R1 = ROT R1 BY 1; // CC -> R1
R4.L = CC = BXOR( A0 , R3 ); // polynom1 -> CC
i$1end:
R1 = ROT R1 BY 1; // CC -> R1
// store 16 bits of outdata RL1
m$0end:
W [ P1 ++ ] = R1;
P4 += -1;
CC = P4 == 0;
IF !CC JUMP l$0; // **** END l-LOOP *****
// Check results
loadsym I2, output;
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x8c62 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x262e );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5b4d );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x834f );
pass
.data
input:
.dw 0x999f
.dw 0x1999
output:
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
|
stsp/binutils-ia16
| 10,384
|
sim/testsuite/bfin/c_dsp32shift_ahalf_rp_s.s
|
//Original:/testcases/core/c_dsp32shift_ahalf_rp_s/c_dsp32shift_ahalf_rp_s.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
//rl0 = ashift (rl0 by rl0);
R1.L = ASHIFT R1.L BY R0.L (S);
R2.L = ASHIFT R2.L BY R0.L (S);
R3.L = ASHIFT R3.L BY R0.L (S);
R4.L = ASHIFT R4.L BY R0.L (S);
R5.L = ASHIFT R5.L BY R0.L (S);
R6.L = ASHIFT R6.L BY R0.L (S);
R7.L = ASHIFT R7.L BY R0.L (S);
//CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000003;
CHECKREG r7, 0x00000003;
imm32 r0, 0x00001001;
R1.L = -1;
imm32 r2, 0x00002002;
imm32 r3, 0x00003003;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
imm32 r6, 0x00006006;
imm32 r7, 0x00007007;
R0.L = ASHIFT R0.L BY R1.L (S);
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L (S);
R3.L = ASHIFT R3.L BY R1.L (S);
R4.L = ASHIFT R4.L BY R1.L (S);
R5.L = ASHIFT R5.L BY R1.L (S);
R6.L = ASHIFT R6.L BY R1.L (S);
R7.L = ASHIFT R7.L BY R1.L (S);
CHECKREG r0, 0x00000800;
//CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00001001;
CHECKREG r3, 0x00001801;
CHECKREG r4, 0x00002002;
CHECKREG r5, 0x00002802;
CHECKREG r6, 0x00003003;
CHECKREG r7, 0x00003803;
imm32 r0, 0x00001001;
imm32 r1, 0x00001001;
R2.L = -15;
imm32 r3, 0x00003003;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
imm32 r6, 0x00006006;
imm32 r7, 0x00007007;
R0.L = ASHIFT R0.L BY R2.L (S);
R1.L = ASHIFT R1.L BY R2.L (S);
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L (S);
R4.L = ASHIFT R4.L BY R2.L (S);
R5.L = ASHIFT R5.L BY R2.L (S);
R6.L = ASHIFT R6.L BY R2.L (S);
R7.L = ASHIFT R7.L BY R2.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
//CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x00001001;
imm32 r1, 0x00001001;
imm32 r2, 0x00002002;
R3.L = -16;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
imm32 r6, 0x00006006;
imm32 r7, 0x00007007;
R0.L = ASHIFT R0.L BY R3.L (S);
R1.L = ASHIFT R1.L BY R3.L (S);
R2.L = ASHIFT R2.L BY R3.L (S);
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L (S);
R5.L = ASHIFT R5.L BY R3.L (S);
R6.L = ASHIFT R6.L BY R3.L (S);
R7.L = ASHIFT R7.L BY R3.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
//CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R0.L (S);
R1.L = ASHIFT R1.H BY R0.L (S);
R2.L = ASHIFT R2.H BY R0.L (S);
R3.L = ASHIFT R3.H BY R0.L (S);
R4.L = ASHIFT R4.H BY R0.L (S);
R5.L = ASHIFT R5.H BY R0.L (S);
R6.L = ASHIFT R6.H BY R0.L (S);
R7.L = ASHIFT R7.H BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x10010000;
R1.L = -1;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.L = ASHIFT R0.H BY R1.L (S);
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L (S);
R3.L = ASHIFT R3.H BY R1.L (S);
R4.L = ASHIFT R4.H BY R1.L (S);
R5.L = ASHIFT R5.H BY R1.L (S);
R6.L = ASHIFT R6.H BY R1.L (S);
R7.L = ASHIFT R7.H BY R1.L (S);
CHECKREG r0, 0x10010800;
//CHECKREG r1, 0x00010001;
CHECKREG r2, 0x20021001;
CHECKREG r3, 0x30031801;
CHECKREG r4, 0x40042002;
CHECKREG r5, 0x50052802;
CHECKREG r6, 0x60063003;
CHECKREG r7, 0x70073803;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
R2.L = -15;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.L = ASHIFT R0.H BY R2.L (S);
R1.L = ASHIFT R1.H BY R2.L (S);
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L (S);
R4.L = ASHIFT R4.H BY R2.L (S);
R5.L = ASHIFT R5.H BY R2.L (S);
R6.L = ASHIFT R6.H BY R2.L (S);
R7.L = ASHIFT R7.H BY R2.L (S);
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
//CHECKREG r2, 0x2002000f;
CHECKREG r3, 0x30030000;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
imm32 r0, 0x10010001;
imm32 r1, 0x10010001;
imm32 r2, 0x20020002;
R3.L = -16;
imm32 r4, 0x40040004;
imm32 r5, 0x50050005;
imm32 r6, 0x60060006;
imm32 r7, 0x70070007;
R0.L = ASHIFT R0.H BY R3.L (S);
R1.L = ASHIFT R1.H BY R3.L (S);
R2.L = ASHIFT R2.H BY R3.L (S);
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L (S);
R5.L = ASHIFT R5.H BY R3.L (S);
R6.L = ASHIFT R6.H BY R3.L (S);
R7.L = ASHIFT R7.H BY R3.L (S);
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020000;
//CHECKREG r3, 0x30030010;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
// d_hi = ashift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000000;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R4.L (S);
R1.H = ASHIFT R1.L BY R4.L (S);
R2.H = ASHIFT R2.L BY R4.L (S);
R3.H = ASHIFT R3.L BY R4.L (S);
//rh4 = ashift (rl4 by rl4);
R5.H = ASHIFT R5.L BY R4.L (S);
R6.H = ASHIFT R6.L BY R4.L (S);
R7.H = ASHIFT R7.L BY R4.L (S);
CHECKREG r0, 0x00010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
//CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
R5.L = -1;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R5.L (S);
R1.H = ASHIFT R1.L BY R5.L (S);
R2.H = ASHIFT R2.L BY R5.L (S);
R3.H = ASHIFT R3.L BY R5.L (S);
R4.H = ASHIFT R4.L BY R5.L (S);
//rh5 = ashift (rl5 by rl5);
R6.H = ASHIFT R6.L BY R5.L (S);
R7.H = ASHIFT R7.L BY R5.L (S);
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00010002;
CHECKREG r3, 0x00010003;
CHECKREG r4, 0x00020004;
//CHECKREG r5, 0x00020005;
CHECKREG r6, 0x00030006;
CHECKREG r7, 0x00030007;
imm32 r0, 0x00001001;
imm32 r1, 0x00001001;
imm32 r1, 0x00002002;
imm32 r3, 0x00003003;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
R6.L = -15;
imm32 r7, 0x00007007;
R0.H = ASHIFT R0.L BY R6.L (S);
R1.H = ASHIFT R1.L BY R6.L (S);
R2.H = ASHIFT R2.L BY R6.L (S);
R3.H = ASHIFT R3.L BY R6.L (S);
R4.H = ASHIFT R4.L BY R6.L (S);
R5.H = ASHIFT R5.L BY R6.L (S);
//rh6 = ashift (rl6 by rl6);
R7.H = ASHIFT R7.L BY R6.L;
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00002002;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00003003;
CHECKREG r4, 0x00004004;
CHECKREG r5, 0x00005005;
//CHECKREG r6, 0x00006006;
CHECKREG r7, 0x00007007;
imm32 r0, 0x00001001;
imm32 r1, 0x00002001;
imm32 r2, 0x00002002;
imm32 r3, 0x00003003;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
imm32 r6, 0x00006006;
R7.L = -16;
R0.H = ASHIFT R0.L BY R7.L (S);
R1.H = ASHIFT R1.L BY R7.L (S);
R2.H = ASHIFT R2.L BY R7.L (S);
R3.H = ASHIFT R3.L BY R7.L (S);
R4.H = ASHIFT R4.L BY R7.L (S);
R5.H = ASHIFT R5.L BY R7.L (S);
R6.H = ASHIFT R6.L BY R7.L (S);
R7.H = ASHIFT R7.L BY R7.L (S);
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00002001;
CHECKREG r2, 0x00002002;
CHECKREG r3, 0x00003003;
CHECKREG r4, 0x00004004;
CHECKREG r5, 0x00005005;
CHECKREG r6, 0x00006006;
//CHECKREG r7, 0x00007007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
R4.L = -1;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R4.L (S);
R1.H = ASHIFT R1.H BY R4.L (S);
R2.H = ASHIFT R2.H BY R4.L (S);
R3.H = ASHIFT R3.H BY R4.L (S);
//rh4 = ashift (rh4 by rl4);
R5.H = ASHIFT R5.H BY R4.L (S);
R6.H = ASHIFT R6.H BY R4.L (S);
R7.H = ASHIFT R7.H BY R4.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00010000;
CHECKREG r3, 0x00010000;
//CHECKREG r4, 0x00020000;
CHECKREG r5, 0x00020000;
CHECKREG r6, 0x00030000;
CHECKREG r7, 0x00030000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
R5.L = -1;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.H = ASHIFT R0.H BY R5.L (S);
R1.H = ASHIFT R1.H BY R5.L (S);
R2.H = ASHIFT R2.H BY R5.L (S);
R3.H = ASHIFT R3.H BY R5.L (S);
R4.H = ASHIFT R4.H BY R5.L (S);
//rh5 = ashift (rh5 by rl5);
R6.H = ASHIFT R6.H BY R5.L (S);
R7.H = ASHIFT R7.H BY R5.L (S);
CHECKREG r0, 0x08000000;
CHECKREG r1, 0x08000000;
CHECKREG r2, 0x10010000;
CHECKREG r3, 0x18010000;
CHECKREG r4, 0x20020000;
//CHECKREG r5, 0x28020000;
CHECKREG r6, 0x30030000;
CHECKREG r7, 0x38030000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
R6.L = -15;
imm32 r7, 0x70070000;
R0.L = ASHIFT R0.H BY R6.L (S);
R1.L = ASHIFT R1.H BY R6.L (S);
R2.L = ASHIFT R2.H BY R6.L (S);
R3.L = ASHIFT R3.H BY R6.L (S);
R4.L = ASHIFT R4.H BY R6.L (S);
R5.L = ASHIFT R5.H BY R6.L (S);
//rl6 = ashift (rh6 by rl6);
R7.L = ASHIFT R7.H BY R6.L;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020000;
CHECKREG r3, 0x30030000;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
//CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r2, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
R7.L = -16;
R0.H = ASHIFT R0.H BY R7.L (S);
R1.H = ASHIFT R1.H BY R7.L (S);
R2.H = ASHIFT R2.H BY R7.L (S);
R3.H = ASHIFT R3.H BY R7.L (S);
R4.H = ASHIFT R4.H BY R7.L (S);
R5.H = ASHIFT R5.H BY R7.L (S);
R6.H = ASHIFT R6.H BY R7.L (S);
//rh7 = ashift (rh7 by rl7);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
//CHECKREG r7, -16;
pass
|
stsp/binutils-ia16
| 8,465
|
sim/testsuite/bfin/c_mmr_loop.S
|
//Original:/proj/frio/dv/testcases/core/c_mmr_loop/c_mmr_loop.dsp
// Spec Reference: mmr loop (interr control) no exception
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we set the processor operating modes, initialize registers
// etc.)
//
BOOT:
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP; // and frame pointer
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// EVTx
// wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000
LD32(p0, 0xFFE02000);
LD32(r0, 0x00000000);
[ P0 ] = R0;
// wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004
LD32(p0, 0xFFE02004);
LD32(r0, 0x00000000);
[ P0 ] = R0;
// wrt-rd EVT2 = 0xFFE02008
LD32(p0, 0xFFE02008);
LD32(r0, 0xE1DE5D1C);
[ P0 ] = R0;
// wrt-rd EVT3 = 0xFFE0200C
LD32(p0, 0xFFE0200C);
LD32(r0, 0x9CC20332);
[ P0 ] = R0;
// wrt-rd EVT4 = 0xFFE02010
LD32(p0, 0xFFE02010);
LD32(r0, 0x00000000); // not implemented
[ P0 ] = R0;
// wrt-rd EVT5 = 0xFFE02014
LD32(p0, 0xFFE02014);
LD32(r0, 0x55552345);
[ P0 ] = R0;
// wrt-rd EVT6 = 0xFFE02018
LD32(p0, 0xFFE02018);
LD32(r0, 0x66663456);
[ P0 ] = R0;
// wrt-rd EVT7 = 0xFFE0201C
LD32(p0, 0xFFE0201C);
LD32(r0, 0x77774567);
[ P0 ] = R0;
// wrt-rd EVT8 = 0xFFE02020
LD32(p0, 0xFFE02020);
LD32(r0, 0x88885678);
[ P0 ] = R0;
// wrt-rd EVT9 = 0xFFE02024
LD32(p0, 0xFFE02024);
LD32(r0, 0x99996789);
[ P0 ] = R0;
// wrt-rd EVT10 = 0xFFE02028
LD32(p0, 0xFFE02028);
LD32(r0, 0xaaaa1234);
[ P0 ] = R0;
// wrt-rd EVT11 = 0xFFE0202C
LD32(p0, 0xFFE0202C);
LD32(r0, 0xBBBBABC6);
[ P0 ] = R0;
// wrt-rd EVT12 = 0xFFE02030
LD32(p0, 0xFFE02030);
LD32(r0, 0xCCCCABC6);
[ P0 ] = R0;
// wrt-rd EVT13 = 0xFFE02034
LD32(p0, 0xFFE02034);
LD32(r0, 0xDDDDABC6);
[ P0 ] = R0;
// wrt-rd EVT14 = 0xFFE02038
LD32(p0, 0xFFE02038);
LD32(r0, 0xEEEEABC6);
[ P0 ] = R0;
// wrt-rd EVT15 = 0xFFE0203C
LD32(p0, 0xFFE0203C);
LD32(r0, 0xFFFFABC6);
[ P0 ] = R0;
// wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100
LD32(p0, 0xFFE02100);
LD32(r0, 0x000001ff);
[ P0 ] = R0;
// wrt-rd IMASK: 16 bits = 0xFFE02104
LD32(p0, 0xFFE02104);
LD32(r0, 0x00000fe0);
[ P0 ] = R0;
// wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108
LD32(p0, 0xFFE02108);
LD32(r0, 0x00000000);
//[p0] = r0;
RAISE 12;
RAISE 13;
// wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C
LD32(p0, 0xFFE0210C);
LD32(r0, 0x00000000);
//[p0] = r0;
CSYNC;
//*** read ops
P1.L = DATA0;
P1.H = DATA0;
LD32(p0, 0xFFE02000);
P2 = 16;
LSETUP ( start1 , end1 ) LC0 = P2;
start1:
R0 = [ P0 ++ ];
end1: [ P1 ++ ] = R0;
//nop;
P1.L = DATA0;
P1.H = DATA0;
R0 = [ P1 ++ ];
R1 = [ P1 ++ ];
R2 = [ P1 ++ ];
R3 = [ P1 ++ ];
R4 = [ P1 ++ ];
R5 = [ P1 ++ ];
R6 = [ P1 ++ ];
R7 = [ P1 ++ ];
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0xE1DE5D1C);
CHECKREG(r3, 0x9CC20332);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x55552345);
CHECKREG(r6, 0x66663456);
CHECKREG(r7, 0x77774567);
R0 = [ P1 ++ ];
R1 = [ P1 ++ ];
R2 = [ P1 ++ ];
R3 = [ P1 ++ ];
R4 = [ P1 ++ ];
R5 = [ P1 ++ ];
R6 = [ P1 ++ ];
R7 = [ P1 ++ ];
CHECKREG(r0, 0x88885678);
CHECKREG(r1, 0x99996789);
CHECKREG(r2, 0xAAAA1234);
CHECKREG(r3, 0xBBBBABC6);
CHECKREG(r4, 0xCCCCABC6);
CHECKREG(r5, 0xDDDDABC6);
CHECKREG(r6, 0xEEEEABC6);
CHECKREG(r7, 0xFFFFABC6);
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
R7 = 0x00006789 (X);
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.section MEM_DATA_ADDR_1,"aw"
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 1,233
|
sim/testsuite/bfin/c_dsp32shiftim_lhh.s
|
//Original:/testcases/core/c_dsp32shiftim_lhh/c_dsp32shiftim_lhh.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: lshift / lshift
imm32 r0, 0x01230abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0 = R0 << 0 (V);
R1 = R1 << 3 (V);
R2 = R2 << 5 (V);
R3 = R3 << 8 (V);
R4 = R4 << 9 (V);
R5 = R5 << 15 (V);
R6 = R6 << 7 (V);
R7 = R7 << 13 (V);
CHECKREG r0, 0x01230ABC;
CHECKREG r1, 0x91A0B3C0;
CHECKREG r2, 0x68A0F120;
CHECKREG r3, 0x56009A00;
CHECKREG r4, 0xCE005600;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xC480E680;
CHECKREG r7, 0x4000C000;
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7 = R0 >> 11 (V);
R0 = R1 >> 8 (V);
R1 = R2 >> 14 (V);
R2 = R3 >> 15 (V);
R3 = R4 >> 10 (V);
R4 = R5 >> 2 (V);
R5 = R6 >> 9 (V);
R6 = R7 >> 6 (V);
CHECKREG r0, 0x00120056;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00110022;
CHECKREG r4, 0x159E26AF;
CHECKREG r5, 0x00330055;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 1,159
|
sim/testsuite/bfin/m6.s
|
// Test result extraction of mac instructions.
// Test basic edge values
// SIGNED INTEGER mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000001
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// integer extraction with no saturation
// 0x1 * 0x1 = 0x0000000001 -> 0x1
A1 = A0 = 0;
R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IS);
DBGA ( R5.L , 0x1 );
DBGA ( R5.H , 0x1 );
// integer extraction with positive saturation
// 0x7fff * 0x7f -> 0x7fff
A1 = A0 = 0;
R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IS);
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
// integer extraction with negative saturation
// 0x8000 * 0x7f -> 0x8000
A1 = A0 = 0;
R5.H = (A1 += R1.H * R3.L), R5.L = (A0 += R1.H * R3.L) (IS);
DBGA ( R5.L , 0x8000 );
DBGA ( R5.H , 0x8000 );
pass
.data;
data0:
.dw 0x0001
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
stsp/binutils-ia16
| 4,973
|
sim/testsuite/bfin/dbg_tr_tbuf0.S
|
//Original:/proj/frio/dv/testcases/debug/dbg_tr_tbuf0/dbg_tr_tbuf0.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfcheck.inc)
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
// This test embeds .text offsets, so pad our test so it lines up.
.space 0x64
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
CHECK_INIT(p5, 0x00BFFFFC);
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
LD32_LABEL(r7, DUMMY);
RETI = r7;
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
START :
WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer
WR_MMR(TBUFCTL, 0x0000000b, p0, r0); // Turn ON trace Buffer
// TBUFPWR = 1
// TBUFEN = 1
// TBUFOVF = 0
// CMPLP = 01
NOP;
NOP;
NOP;
NOP;
NOP;
R6 = 0;
R7 = 10;
JMP:
JUMP.S LABEL0;
NOP;
NOP;
LABEL0:
P1 = 0x0006;
JUMP (PC+P1);
LABEL1:
LD32(R3, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
LABEL2:
CC = R7 == R6;
IF CC JUMP END;
R6 += 1;
JUMP LABEL2;
LABEL3:
NOP;
LABEL4:
LD32(R4, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
END:
R0 = 1;
NOP;
NOP;
NOP;
CHECKREG(r3, 0x00000000);
CHECKREG(r4, 0x00000000);
// Read the contents of the Trace Buffer
RD_MMR(TBUFSTAT, p0, r0);
CHECKREG(r0, 0x00000004);
// Read last entry of the Trace Buffer
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x00000256);
RD_MMR(TBUF, p0, r2);
CHECKREG(r2, 0x00000246);
RD_MMR(TBUFSTAT, p0, r0);
CHECKREG(r0, 0x00000003);
// Read last entry of the Trace Buffer
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x00000245);
RD_MMR(TBUF, p0, r2);
CHECKREG(r2, 0x0000024a);
RD_MMR(TBUFSTAT, p0, r0);
CHECKREG(r0, 0x00000002);
// Read last entry of the Trace Buffer
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x00000240);
RD_MMR(TBUF, p0, r2);
CHECKREG(r2, 0x0000023a);
RD_MMR(TBUFSTAT, p0, r0);
CHECKREG(r0, 0x00000001);
// Read last entry of the Trace Buffer
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x00000238);
RD_MMR(TBUF, p0, r2);
CHECKREG(r2, 0x00000232);
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
|
stsp/binutils-ia16
| 11,110
|
sim/testsuite/bfin/se_loop_kill_01.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_kill_01/se_loop_kill_01.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE 0x00000500
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
P2 = 0x0200 (Z);
P2.H = 0x00F0;
[ -- SP ] = P0;
[ -- SP ] = P0;
SSYNC;
LD32_LABEL(r0, l0t);
LD32_LABEL(r1, l0b);
[ -- SP ] = R0;
[ -- SP ] = R1;
SSYNC;
LB0 = [sp++];
EXCPT 0x5; // Will kill mv2lc in EX3
LC0 = P0;
LT0 = [sp++];
l0t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l0b:R2 += 2;
LD32_LABEL(r0, l2t);
LD32_LABEL(r1, l2b);
LT0 = r0;
LB0 = r1;
EXCPT 0x5; // Will kill mv2lc in EX3 when stalled
LC0 = [ SP ++ ];
l2t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l2b:R2 += 2;
LD32_LABEL(r0, l1t);
LD32_LABEL(r1, l1b);
LT1 = r0;
LB1 = r1;
EXCPT 0x5; // Will kill mv2lc in EX3 when stalled
LC1 = [ SP ++ ];
l1t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l1b:R2 += 2;
LD32_LABEL(r0, l3t);
LD32_LABEL(r1, l3b);
LT1 = r0;
LB1 = r1;
EXCPT 0x5; // Will kill mv2lc in EX3
NOP;
LC1 = P0;
l3t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l3b:R2 += 2;
EXCPT 0x6; // Will kill Lsetup in EX2
NOP;
NOP;
LSETUP ( l1e , l1e ) LC0 = P1;
l1e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX2
NOP;
NOP;
LSETUP ( m1e , m1e ) LC1 = P1;
m1e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX1
NOP;
NOP;
NOP;
LSETUP ( l2e , l2e ) LC0 = P1;
l2e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX1
NOP;
NOP;
NOP;
LSETUP ( m2e , m2e ) LC1 = P1;
m2e:R7 += 1;
NOP;
NOP;
NOP;
EXCPT 0x6; // Will kill Lsetup in EX2 when stalled
R0 = [ P2 ++ ];
LSETUP ( l3e , l3e ) LC0 = P1;
l3e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX2 when stalled
R0 = [ P2 ++ ];
LSETUP ( m3e , m3e ) LC1 = P1;
m3e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX1 when stalled
R0 = [ P2 ++ ];
NOP;
LSETUP ( l4e , l4e ) LC0 = P1;
l4e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX1 when stalled
R0 = [ P2 ++ ];
NOP;
LSETUP ( m4e , m4e ) LC1 = P1;
m4e:R7 += 1;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_0x00F00200,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.section MEM_0x00F00210,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 10,753
|
sim/testsuite/bfin/lmu_excpt_illaddr.S
|
//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp
// Description: LMU illegal address exceptions
// Illegal core MMR: addr[19:16] != 0
// Illegal core MMR: Illegal peripheral
// Illegal core MMR: Illegal addr in peripheral
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef SR_BASE
#define SR_BASE 0xFF800000 // must match value used for sram_baddr inputs
#endif
#ifndef A_SRAM_BASE
#define A_SRAM_BASE SR_BASE
#endif
#ifndef B_SRAM_BASE
#define B_SRAM_BASE SR_BASE + 0x100000
#endif
#ifndef I_SRAM_BASE
#define I_SRAM_BASE SR_BASE + 0x200000
#endif
#ifndef SCRATCH_SRAM_BASE
#define SCRATCH_SRAM_BASE SR_BASE + 0x300000
#endif
#ifndef A_SRAM_SIZE
#define A_SRAM_SIZE 0x4000
#endif
#ifndef B_SRAM_SIZE
#define B_SRAM_SIZE 0x4000
#endif
#ifndef I_SRAM_SIZE
#define I_SRAM_SIZE 0x4000
#endif
#ifndef SCRATCH_SRAM_SIZE
#define SCRATCH_SRAM_SIZE 0x1000
#endif
CHECK_INIT(p5, 0xE0000000);
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
WR_MMR_LABEL(EVT15, int15, p0, r1);
WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
// Set up CPLB
WR_MMR(DCPLB_ADDR1, SR_BASE, p0, r0); // SRAM segment: Non-cacheable
WR_MMR(DCPLB_DATA1, ( CPLB_VALID | CPLB_L1SRAM | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
WR_MMR(DCPLB_ADDR2, 0xE0000000, p0, r0); // CHECKREG segment: Non-cacheable
WR_MMR(DCPLB_DATA2, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); // MMRs: Non-cacheable
WR_MMR(DCPLB_DATA15, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
WR_MMR(DMEM_CONTROL, (DMC_AB_SRAM | ENDCPLB | ENDM), p0, r0);
CSYNC;
// Write fault addr MMR to known state
WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6);
NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
// But first raise interrupt 15 so we will run in supervisor mode.
RAISE 15;
NOP;
RTI;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
int15:
NOP;NOP;NOP;NOP;NOP;
//-------------------------------------------------------
// First do stores
//-------------------------------------------------------
//
// illegal core MMR: addr[19] !=0
LD32(p1, 0xFFE80000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X01: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE80000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: addr[18] !=0
LD32(p1, 0xFFE40000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X02: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE40000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: addr[17] !=0
LD32(p1, 0xFFE20000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X03: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE20000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: addr[16] !=0
LD32(p1, 0xFFE10000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X04: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE10000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal periperal (addr[15:12] > 8)
LD32(p1, 0xFFE09000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X10: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE09000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X10, r0); // RETX should be value of X10 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 00
LD32(p1, 0xFFE00408);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X20: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE00408); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X20, r0); // RETX should be value of X20 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 01
LD32(p1, 0xFFE01408);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X21: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE01408); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 02
LD32(p1, 0xFFE02114);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X22: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE02114); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X22, r0); // RETX should be value of X22 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 03
LD32(p1, 0xFFE03010);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X23: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE03010); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 04
LD32(p1, 0xFFE04008);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X24: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE04008); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X24, r0); // RETX should be value of X24 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 05
LD32(p1, 0xFFE05010);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X25: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE05010); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X25, r0); // RETX should be value of X25 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 06
LD32(p1, 0xFFE06104);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X26: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE06104); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X26, r0); // RETX should be value of X26 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 07
LD32(p1, 0xFFE07204);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X27: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE07204); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X27, r0); // RETX should be value of X27 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 08
LD32(p1, 0xFFE08108);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X28: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE08108); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X28, r0); // RETX should be value of X28 (HARDCODED ADDR!!)
//-------------------------------------------------------
User:
dbg_pass;
//-------------------------------------------------------
handler:
R5 = SEQSTAT; // Get exception cause
// read and check fail addr (addr_which_causes_exception)
// should not be set for alignment exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r6);
R7 = RETX; // get address of excepting instruction
// align the offending address
P1 = P2;
RTX;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
|
stsp/binutils-ia16
| 2,077
|
sim/testsuite/bfin/PN_generator.s
|
# mach: bfin
// GENERIC PN SEQUENCE GENERATOR
// Linear Feedback Shift Register
// -------------------------------
// This solution implements an LFSR by applying an XOR reduction
// function to the 40 bit accumulator, XORing the contents of the
// CC bit, shifting by one the accumulator, and inserting the
// resulting bit on the open bit slot.
// CC --> ----- XOR--------------------------
// | | | | | |
// | | | | | |
// +------------------------------+ v
// | b0 b1 b2 b3 b38 b39 | in <-- by one
// +------------------------------+
// after:
// +------------------------------+
// | b1 b2 b3 b38 b39 in |
// +------------------------------+
// The program shown here is a PN sequence generator, and hence
// does not take any input other than the initial state. However,
// in order to accept an input, one simply needs to rotate the
// input sequence via CC prior to applying the XOR reduction.
.include "testutils.inc"
start
loadsym P1, output;
init_r_regs 0;
ASTAT = R0;
// load Polynomial into A1
A1 = A0 = 0;
R0.L = 0x1cd4;
R0.H = 0xab18;
A1.w = R0;
R0.L = 0x008d;
A1.x = R0.L;
// load InitState into A0
R0.L = 0x0001;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0.L;
P4 = 4;
LSETUP ( l$0 , l$0end ) LC0 = P4;
l$0: // **** START l-LOOP *****
P4 = 32;
LSETUP ( m$1 , m$1 ) LC1 = P4; // **** START m-LOOP *****
m$1:
A0 = BXORSHIFT( A0 , A1, CC );
// store 16 bits of outdata RL1
R1 = A0.w;
l$0end:
[ P1 ++ ] = R1;
// Check results
loadsym I2, output;
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5adf );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2fc9 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0xbd91 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5520 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x80d5 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x7fef );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x34d1 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x915c );
pass
.data;
output:
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
|
stsp/binutils-ia16
| 5,717
|
sim/testsuite/bfin/se_excpt_ifprotviol.S
|
//Original:/proj/frio/dv/testcases/seq/se_excpt_ifprotviol/se_excpt_ifprotviol.dsp
// Description: EXCPT instruction and IF Prot Viol priority
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x100 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
RETI = r0; // prevent Xs later on
RETX = r0;
RETN = r0;
RETE = r0;
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the user stack pointer
FP = SP;
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
// [--sp] = RETI; // enable interrupts in supervisor mode
R0 = 0;
R1 = -1;
EXCPT 2; // the RAISE should not prevent the EXCPT from being taken
RAISE 15;
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
CHECKREG(r5, 2); // check the flag
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction
CC = r7 == r6;
IF CC JUMP EXCPT2;
R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervisor Resource
CC = r7 == r6;
IF CC JUMP IFPROTVIOL;
JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop
EXCPT2:
R5 = 1; // Set a Flag
JUMP.S OUT;
IFPROTVIOL:
R7 = RETX; // Fix up return address
R7 += 2; // skip offending 16 bit instruction
RETX = r7; // and put back in RETX
R5 <<= 1; // Alter Global Flag
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 4,211
|
sim/testsuite/bfin/c_dsp32shiftim_a0alr.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp
// Spec Reference: dsp32shift a0 ashift, lshift, rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x11140000;
imm32 r1, 0x012C003E;
imm32 r2, 0x81359E24;
imm32 r3, 0x81459E24;
imm32 r4, 0xD159E268;
imm32 r5, 0x51626AF2;
imm32 r6, 0x9176AF36;
imm32 r7, 0xE18BFF86;
R0.L = 0;
A0 = 0;
A0.L = R1.L;
A0.H = R1.H;
A0 = A0 << 0; /* a0 = 0x00000000 */
R1 = A0.w; /* r5 = 0x00000000 */
CHECKREG r1, 0x012C003E;
R1.L = 1;
A0.L = R2.L;
A0.H = R2.H;
A0 = A0 << 1; /* a0 = 0x00000000 */
R2 = A0.w; /* r5 = 0x00000000 */
CHECKREG r2, 0x026B3C48;
R2.L = 15;
A0.L = R3.L;
A0.H = R3.H;
A0 = A0 << 15; /* a0 = 0x00000000 */
R3 = A0.w; /* r5 = 0x00000000 */
CHECKREG r3, 0xCF120000;
R3.L = 31;
A0.L = R4.L;
A0.H = R4.H;
A0 = A0 << 31; /* a0 = 0x00000000 */
R4 = A0.w; /* r5 = 0x00000000 */
CHECKREG r4, 0x00000000;
R4.L = -1;
A0.L = R5.L;
A0.H = R5.H;
A0 = A0 >>> 1; /* a0 = 0x00000000 */
R5 = A0.w; /* r5 = 0x00000000 */
CHECKREG r5, 0x28B13579;
R5.L = -16;
A0 = 0;
A0.L = R6.L;
A0.H = R6.H;
A0 = A0 >>> 16; /* a0 = 0x00000000 */
R6 = A0.w; /* r5 = 0x00000000 */
CHECKREG r6, 0x00009176;
R6.L = -31;
A0.L = R7.L;
A0.H = R7.H;
A0 = A0 >>> 31; /* a0 = 0x00000000 */
R0 = A0.w; /* r5 = 0x00000000 */
CHECKREG r0, 0x00000001;
R7.L = -32;
A0.L = R0.L;
A0.H = R0.H;
.dw 0xC683 // .dw 0xC683 // A0 = A0 >>> 32;
.dw 0x0100
R7 = A0.w; /* r5 = 0x00000000 */
CHECKREG r7, 0x00000000;
imm32 r0, 0x12340000;
imm32 r1, 0x028C003E;
imm32 r2, 0x82159E24;
imm32 r3, 0x82159E24;
imm32 r4, 0xD259E268;
imm32 r5, 0x52E26AF2;
imm32 r6, 0x9226AF36;
imm32 r7, 0xE26BFF86;
R0.L = 0;
A0 = 0;
A0.L = R1.L;
A0.H = R1.H;
A0 = A0 << 0; /* a0 = 0x00000000 */
R1 = A0.w; /* r5 = 0x00000000 */
CHECKREG r1, 0x028C003E;
R1.L = 1;
A0.L = R2.L;
A0.H = R2.H;
A0 = A0 << 3; /* a0 = 0x00000000 */
R2 = A0.w; /* r5 = 0x00000000 */
CHECKREG r2, 0x10ACF120;
R2.L = 15;
A0.L = R3.L;
A0.H = R3.H;
A0 = A0 << 15; /* a0 = 0x00000000 */
R3 = A0.w; /* r5 = 0x00000000 */
CHECKREG r3, 0xCF120000;
R3.L = 31;
A0.L = R4.L;
A0.H = R4.H;
A0 = A0 << 31; /* a0 = 0x00000000 */
R4 = A0.w; /* r5 = 0x00000000 */
CHECKREG r4, 0x00000000;
R4.L = -1;
A0.L = R5.L;
A0.H = R5.H;
A0 = A0 >> 1; /* a0 = 0x00000000 */
R5 = A0.w; /* r5 = 0x00000000 */
CHECKREG r5, 0x29713579;
R5.L = -16;
A0 = 0;
A0.L = R6.L;
A0.H = R6.H;
A0 = A0 >> 16; /* a0 = 0x00000000 */
R6 = A0.w; /* r5 = 0x00000000 */
CHECKREG r6, 0x00009226;
R6.L = -31;
A0.L = R7.L;
A0.H = R7.H;
A0 = A0 >> 31; /* a0 = 0x00000000 */
R7 = A0.w; /* r5 = 0x00000000 */
CHECKREG r7, 0x00000001;
R7.L = -32;
A0.L = R0.L;
A0.H = R0.H;
.dw 0xC683
.dw 0x4100 // A0 = A0 >> 32;
R0 = A0.w; /* r5 = 0x00000000 */
CHECKREG r0, 0x00000000;
imm32 r0, 0x13340000;
imm32 r1, 0x038C003E;
imm32 r2, 0x83159E24;
imm32 r3, 0x83159E24;
imm32 r4, 0xD359E268;
imm32 r5, 0x53E26AF2;
imm32 r6, 0x9326AF36;
imm32 r7, 0xE36BFF86;
R0.L = 0;
A0 = 0;
A0.L = R1.L;
A0.H = R1.H;
A0 = ROT A0 BY 0; /* a0 = 0x00000000 */
R1 = A0.w; /* r5 = 0x00000000 */
CHECKREG r1, 0x038C003E;
R1.L = 1;
A0.L = R2.L;
A0.H = R2.H;
A0 = ROT A0 BY 1; /* a0 = 0x00000000 */
R2 = A0.w; /* r5 = 0x00000000 */
CHECKREG r2, 0x062B3C48;
R2.L = 15;
A0.L = R3.L;
A0.H = R3.H;
A0 = ROT A0 BY 15; /* a0 = 0x00000000 */
R3 = A0.w; /* r5 = 0x00000000 */
CHECKREG r3, 0xCF120060;
R3.L = 31;
A0.L = R4.L;
A0.H = R4.H;
A0 = ROT A0 BY 31; /* a0 = 0x00000000 */
R4 = A0.w; /* r5 = 0x00000000 */
CHECKREG r4, 0x62B4D678;
R4.L = -1;
A0.L = R5.L;
A0.H = R5.H;
A0 = ROT A0 BY -1; /* a0 = 0x00000000 */
R5 = A0.w; /* r5 = 0x00000000 */
CHECKREG r5, 0x29F13579;
R5.L = -16;
A0.L = R6.L;
A0.H = R6.H;
A0 = ROT A0 BY -16; /* a0 = 0x00000000 */
R6 = A0.w; /* r5 = 0x00000000 */
CHECKREG r6, 0x6C9A9326;
R6.L = -31;
A0.L = R7.L;
A0.H = R7.H;
A0 = ROT A0 BY -31; /* a0 = 0x00000000 */
R7 = A0.w; /* r5 = 0x00000000 */
CHECKREG r7, 0xAFFE1ABD;
R7.L = -32;
A0.L = R0.L;
A0.H = R0.H;
A0 = ROT A0 BY -32; /* a0 = 0x00000000 */
R0 = A0.w; /* r5 = 0x00000000 */
CHECKREG r0, 0x6800018D;
pass
|
stsp/binutils-ia16
| 1,470
|
sim/testsuite/bfin/c_ldimmhalf_l_dr.s
|
//Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp
// Spec Reference: ldimmhalf l dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.L = 0x0001;
R1.L = 0x0003;
R2.L = 0x0005;
R3.L = 0x0007;
R4.L = 0x0009;
R5.L = 0x000b;
R6.L = 0x000d;
R7.L = 0x000f;
CHECKREG r0, 0xffff0001;
CHECKREG r1, 0xffff0003;
CHECKREG r2, 0xffff0005;
CHECKREG r3, 0xffff0007;
CHECKREG r4, 0xffff0009;
CHECKREG r5, 0xffff000b;
CHECKREG r6, 0xffff000d;
CHECKREG r7, 0xffff000f;
R0.L = 0x0010;
R1.L = 0x0030;
R2.L = 0x0050;
R3.L = 0x0070;
R4.L = 0x0090;
R5.L = 0x00b0;
R6.L = 0x00d0;
R7.L = 0x00f0;
CHECKREG r0, 0xffff0010;
CHECKREG r1, 0xffff0030;
CHECKREG r2, 0xffff0050;
CHECKREG r3, 0xffff0070;
CHECKREG r4, 0xffff0090;
CHECKREG r5, 0xffff00b0;
CHECKREG r6, 0xffff00d0;
CHECKREG r7, 0xffff00f0;
R0.L = 0x0100;
R1.L = 0x0300;
R2.L = 0x0500;
R3.L = 0x0700;
R4.L = 0x0900;
R5.L = 0x0b00;
R6.L = 0x0d00;
R7.L = 0x0f00;
CHECKREG r0, 0xffff0100;
CHECKREG r1, 0xffff0300;
CHECKREG r2, 0xffff0500;
CHECKREG r3, 0xffff0700;
CHECKREG r4, 0xffff0900;
CHECKREG r5, 0xffff0b00;
CHECKREG r6, 0xffff0d00;
CHECKREG r7, 0xffff0f00;
R0.L = 0x1000;
R1.L = 0x3000;
R2.L = 0x5000;
R3.L = 0x7000;
R4.L = 0x9000;
R5.L = 0xb000;
R6.L = 0xd000;
R7.L = 0xf000;
CHECKREG r0, 0xffff1000;
CHECKREG r1, 0xffff3000;
CHECKREG r2, 0xffff5000;
CHECKREG r3, 0xffff7000;
CHECKREG r4, 0xffff9000;
CHECKREG r5, 0xffffb000;
CHECKREG r6, 0xffffd000;
CHECKREG r7, 0xfffff000;
pass
|
stsp/binutils-ia16
| 4,386
|
sim/testsuite/bfin/a10.s
|
// ALU test program.
// Test dual 16 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0002;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0002 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger
R0.L = 0x0000;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// one operand larger, one smaller.
R0.L = 0x000a;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x000a );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x8001;
R0.H = 0xffff;
R1.L = 0x8000;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x8001 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x8000;
R0.H = 0xffff;
R1.L = 0x8000;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// MIN
// second operand is smaller
R0.L = 0x0001;
R0.H = 0x0004;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller
R0.L = 0xffff;
R0.H = 0x8001;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x8001 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// one of each
R0.L = 0xffff;
R0.H = 0x0034;
R1.L = 0x0999;
R1.H = 0x0010;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x0010 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x0999;
R1.H = 0x0010;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x0010 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// ABS
R0.L = 0x0001;
R0.H = 0x8001;
R7 = ABS R0 (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x7fff );
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0001;
R0.H = 0x8000;
R7 = ABS R0 (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0xffff;
R7 = ABS R0 (V);
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0001 );
CC = VS; R6 = CC; DBGA ( R6.L, 0x1 );
CC = AZ; R6 = CC; DBGA ( R6.L, 0x1 );
pass
|
stsp/binutils-ia16
| 4,000
|
sim/testsuite/bfin/c_dsp32mult_pair_m_is.s
|
//Original:/testcases/core/c_dsp32mult_pair_m_is/c_dsp32mult_pair_m_is.dsp
// Spec Reference: dsp32mult pair MUNOP is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm32 r7, 0xd246712f;
R0 = R0.L * R0.L (ISS2);
R2 = R0.L * R1.H (ISS2);
R4 = R1.H * R1.H (ISS2);
R6 = R0.L * R0.L (ISS2);
CHECKREG r0, 0x39F9C2B2;
CHECKREG r1, 0x9F7A5127;
CHECKREG r2, 0x2E3AADA8;
CHECKREG r3, 0x00069027;
CHECKREG r4, 0x48C98C48;
CHECKREG r5, 0x10ACEF2B;
CHECKREG r6, 0x1D5C8788;
CHECKREG r7, 0xD246712F;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R0 = R2.L * R2.L (ISS2);
R2 = R2.L * R3.H (ISS2);
R4 = R3.H * R2.H (ISS2);
R6 = R2.L * R3.L (ISS2);
CHECKREG r0, 0x2965A1F2;
CHECKREG r1, 0x6FBA5137;
CHECKREG r2, 0x3FAE367C;
CHECKREG r3, 0x90060037;
CHECKREG r4, 0xC84ABC28;
CHECKREG r5, 0xB0ACEF3B;
CHECKREG r6, 0x00176948;
CHECKREG r7, 0x12467003;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x43246755;
imm32 r3, 0x05060055;
imm32 r4, 0x906bc509;
imm32 r5, 0x10a7ef5b;
imm32 r6, 0xb00c805d;
imm32 r7, 0x1246795f;
R0 = R4.L * R4.L (ISS2);
R2 = R4.L * R5.H (ISS2);
R4 = R5.H * R5.H (ISS2);
R6 = R4.L * R5.L (ISS2);
CHECKREG r0, 0x1B29B4A2;
CHECKREG r1, 0xC4BA5157;
CHECKREG r2, 0xF85431BE;
CHECKREG r3, 0x05060055;
CHECKREG r4, 0x022A99E2;
CHECKREG r5, 0x10A7EF5B;
CHECKREG r6, 0x0D4762AC;
CHECKREG r7, 0x1246795F;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
R0 = R6.L * R6.L (ISS2);
R2 = R6.L * R7.H (ISS2);
R4 = R7.H * R7.H (ISS2);
R6 = R6.L * R7.L (ISS2);
CHECKREG r0, 0x31781CD2;
CHECKREG r1, 0xEFBA5166;
CHECKREG r2, 0xF4A3CF9C;
CHECKREG r3, 0xF0060066;
CHECKREG r4, 0x029BD648;
CHECKREG r5, 0x10ACEF6B;
CHECKREG r6, 0xBA1A5E86;
CHECKREG r7, 0x1246706F;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0 = R0.L * R7.L (ISS2);
R2 = R1.L * R6.H (ISS2);
R4 = R3.H * R4.H (ISS2);
R6 = R4.L * R3.L (ISS2);
CHECKREG r0, 0x0B26E1B6;
CHECKREG r1, 0xCFBA5127;
CHECKREG r2, 0x00079BA8;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0xFFFAC804;
CHECKREG r5, 0x10ACDFDB;
CHECKREG r6, 0xFFFCF038;
CHECKREG r7, 0x1246F00F;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R1 = R7.H * R0.H (ISS2);
R3 = R6.H * R1.H (ISS2);
R5 = R5.H * R2.L (ISS2);
R7 = R4.L * R3.H (ISS2);
CHECKREG r0, 0xAB235A75;
CHECKREG r1, 0xF3E28324;
CHECKREG r2, 0x13246905;
CHECKREG r3, 0xFFFEDD30;
CHECKREG r4, 0x90ABCD09;
CHECKREG r5, 0x0DADBEB8;
CHECKREG r6, 0x000C0D0D;
CHECKREG r7, 0x0000CBDC;
imm32 r0, 0x9b235675;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946705;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c009d;
imm32 r7, 0x12467009;
R1 = R6.H * R4.L (ISS2);
R3 = R5.L * R3.H (ISS2);
R5 = R3.H * R1.L (ISS2);
R7 = R1.H * R2.H (ISS2);
CHECKREG r0, 0x9B235675;
CHECKREG r1, 0xFFF6B8D8;
CHECKREG r2, 0x13946705;
CHECKREG r3, 0xFFFE7166;
CHECKREG r4, 0x90AB9D09;
CHECKREG r5, 0x00011CA0;
CHECKREG r6, 0x000C009D;
CHECKREG r7, 0xFFFE7870;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R4.L * R0.H (ISS2);
R3 = R6.H * R1.H (ISS2);
R5 = R1.L * R2.L (ISS2);
R7 = R4.H * R2.L (ISS2);
CHECKREG r0, 0xEB235675;
CHECKREG r1, 0x03175676;
CHECKREG r2, 0x13E46705;
CHECKREG r3, 0x00004A28;
CHECKREG r4, 0x90ABED09;
CHECKREG r5, 0x4596549C;
CHECKREG r6, 0x000C00ED;
CHECKREG r7, 0xA66540AE;
pass
|
stsp/binutils-ia16
| 7,235
|
sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex1_brcc_mv_pop/c_seq_ex1_brcc_mv_pop.dsp
// Spec Reference: sequencer stage ex1 ( brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
R0 = 0;
ASTAT = R0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
// RAISE 2; // RTN
IF !CC JUMP LABEL1 (BP);
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
// RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
// RAISE 6; // RTI
IF !CC JUMP LABEL2 (BP);
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
// RAISE 7; // RTI
IF CC JUMP LABEL4; // SHOULD NOT EXECUTE
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
LABEL4:
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// RAISE 8; // RTI
IF !CC JUMP LABEL3 (BP);
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
// RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 9,418
|
sim/testsuite/bfin/c_ldstidxl_ld_dreg.s
|
//Original:testcases/core/c_ldstidxl_ld_dreg/c_ldstidxl_ld_dreg.dsp
// Spec Reference: c_ldstidxl load dreg (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
// initial values
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0xA0;
loadsym p4, DATA_ADDR_2, 0x70;
loadsym p5, DATA_ADDR_1, 0x70;
loadsym fp, DATA_ADDR_2, 0x70;
R0 = [ P1 + 156 ];
R1 = [ P1 + 84 ];
R2 = [ P1 + 48 ];
R3 = [ P1 + 12 ];
R4 = [ P1 + 36 ];
R5 = [ P1 + 20 ];
R6 = [ P1 + 128 ];
R7 = [ P1 + 156 ];
CHECKREG r0, 0x08090A0B;
CHECKREG r1, 0x22232425;
CHECKREG r2, 0x82838485;
CHECKREG r3, 0x0C0D0E0F;
CHECKREG r4, 0x55667788;
CHECKREG r5, 0x14151617;
CHECKREG r6, 0x66676869;
CHECKREG r7, 0x08090A0B;
R0 = [ P2 + -120 ];
R1 = [ P2 + -112 ];
R2 = [ P2 + -36 ];
R3 = [ P2 + -24 ];
R4 = [ P2 + -44 ];
R5 = [ P2 + -8 ];
R6 = [ P2 + -52 ];
R7 = [ P2 + -148 ];
CHECKREG r0, 0xD3D4D5D6;
CHECKREG r1, 0xDBDCDDDE;
CHECKREG r2, 0xA455565A;
CHECKREG r3, 0xA667686A;
CHECKREG r4, 0x96E899EA;
CHECKREG r5, 0x4C4D4E4F;
CHECKREG r6, 0x94E899EA;
CHECKREG r7, 0x4C4D4E4F;
R0 = [ P4 + 44 ];
R1 = [ P4 + -40 ];
R2 = [ P4 + 36 ];
R3 = [ P4 + -32 ];
R4 = [ P4 + 28 ];
R5 = [ P4 + 24 ];
R6 = [ P4 + -20 ];
R7 = [ P4 + 108 ];
CHECKREG r0, 0x50515253;
CHECKREG r1, 0x94E899EA;
CHECKREG r2, 0x48494A4B;
CHECKREG r3, 0x96E899EA;
CHECKREG r4, 0x40414243;
CHECKREG r5, 0xA667686A;
CHECKREG r6, 0x99E899EA;
CHECKREG r7, 0x96E899EA;
R0 = [ P5 + -16 ];
R1 = [ P5 + 12 ];
R2 = [ P5 + -8 ];
R3 = [ P5 + 4 ];
R4 = [ P5 + 0 ];
R5 = [ P5 + -4 ];
R6 = [ P5 + 8 ];
R7 = [ P5 + -108 ];
CHECKREG r0, 0x34353637;
CHECKREG r1, 0x62636465;
CHECKREG r2, 0x42434445;
CHECKREG r3, 0x54555657;
CHECKREG r4, 0x50515253;
CHECKREG r5, 0x46474849;
CHECKREG r6, 0x58596061;
CHECKREG r7, 0x04050607;
R0 = [ FP + 92 ];
R1 = [ FP + -16 ];
R2 = [ FP + 40 ];
R3 = [ FP + -64 ];
R4 = [ FP + 28 ];
R5 = [ FP + -32 ];
R6 = [ FP + 36 ];
R7 = [ FP + -96 ];
CHECKREG r0, 0x92E899EA;
CHECKREG r1, 0x91E899EA;
CHECKREG r2, 0x4C4D4E4F;
CHECKREG r3, 0xDBDCDDDE;
CHECKREG r4, 0x40414243;
CHECKREG r5, 0x96E899EA;
CHECKREG r6, 0x48494A4B;
CHECKREG r7, 0x50515253;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
DATA_ADDR_2:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 1,181
|
sim/testsuite/bfin/algnbug2.s
|
# mach: bfin
.include "testutils.inc"
start
M0 = 1 (X);
loadsym I0, blocka;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
pass
.data;
.align 8
blocka:
.dw 0xfeff
.dw 0xfcfd
.dw 0xfafb
.dw 0xf8f9
|
stsp/binutils-ia16
| 9,699
|
sim/testsuite/bfin/c_dsp32shift_rot_mix.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp
// Spec Reference: dsp32shift rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x83456789;
imm32 r3, 0x9456789a;
imm32 r4, 0xa56789ab;
imm32 r5, 0xb6789abc;
imm32 r6, 0xc789abcd;
imm32 r7, 0xd89abcde;
R1 = ROT R0 BY R0.L;
R2 = ROT R1 BY R0.L;
R3 = ROT R2 BY R0.L;
R4 = ROT R3 BY R0.L;
R5 = ROT R4 BY R0.L;
R6 = ROT R5 BY R0.L;
R7 = ROT R6 BY R0.L;
R0 = ROT R7 BY R0.L;
CHECKREG r0, 0x01230000;
CHECKREG r1, 0x01230000;
CHECKREG r2, 0x01230000;
CHECKREG r3, 0x01230000;
CHECKREG r4, 0x01230000;
CHECKREG r5, 0x01230000;
CHECKREG r6, 0x01230000;
CHECKREG r7, 0x01230000;
A0 = 0;
A0.L = R0.L;
A0.H = R0.H;
A0 = ROT A0 BY R1.L;
R6 = A0.w;
imm32 r4, 0x30003000;
imm32 r1, 5;
R7 = ROT R4 BY R1.L;
CHECKREG r6, 0x01230000;
CHECKREG r7, 0x00060003;
imm32 r0, 0x11230001;
imm32 r1, 0xc2345678;
imm32 r2, 0xd3456789;
imm32 r3, 0xb456789a;
imm32 r4, 0x056789ab;
imm32 r5, 0x36789abc;
imm32 r6, 0x1789abcd;
imm32 r7, 0x189abcde;
R1.L = 5;
R2 = ROT R0 BY R1.L;
R3 = ROT R1 BY R1.L;
R4 = ROT R2 BY R1.L;
R5 = ROT R3 BY R1.L;
R6 = ROT R4 BY R1.L;
R7 = ROT R5 BY R1.L;
R0 = ROT R6 BY R1.L;
R1 = ROT R7 BY R1.L;
CHECKREG r0, 0x00108908;
CHECKREG r1, 0x005613A0;
CHECKREG r2, 0x24600021;
CHECKREG r3, 0x468000AC;
CHECKREG r4, 0x8C000422;
CHECKREG r5, 0xD0001584;
CHECKREG r6, 0x80008448;
CHECKREG r7, 0x0002B09D;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x8456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0xc789abcd;
imm32 r7, 0x789abcde;
R2 = 15;
R3 = ROT R0 BY R2.L;
R4 = ROT R1 BY R2.L;
R5 = ROT R2 BY R2.L;
R6 = ROT R3 BY R2.L;
R7 = ROT R4 BY R2.L;
R0 = ROT R5 BY R2.L;
R1 = ROT R6 BY R2.L;
R2 = ROT R7 BY R2.L;
CHECKREG r0, 0xC0000001;
CHECKREG r1, 0x10006009;
CHECKREG r2, 0x45678891;
CHECKREG r3, 0x80010048;
CHECKREG r4, 0x2B3C448D;
CHECKREG r5, 0x00078000;
CHECKREG r6, 0x80242000;
CHECKREG r7, 0x22468ACF;
imm32 r0, 0x21230003;
imm32 r1, 0x22345678;
imm32 r2, 0x23456789;
imm32 r3, 0x2456789a;
imm32 r4, 0x256789ab;
imm32 r5, 0x26789abc;
imm32 r6, 0x2789abcd;
imm32 r7, 0x289abcde;
R3.L = 24;
R4 = ROT R0 BY R3.L;
R5 = ROT R1 BY R3.L;
R6 = ROT R2 BY R3.L;
R7 = ROT R3 BY R3.L;
R0 = ROT R4 BY R3.L;
R1 = ROT R5 BY R3.L;
R2 = ROT R6 BY R3.L;
R3 = ROT R7 BY R3.L;
CHECKREG r0, 0x8001C848;
CHECKREG r1, 0x2BBC088D;
CHECKREG r2, 0xB34488D1;
CHECKREG r3, 0x000C4915;
CHECKREG r4, 0x03909180;
CHECKREG r5, 0x78111A2B;
CHECKREG r6, 0x8911A2B3;
CHECKREG r7, 0x18922B00;
imm32 r0, 0x01230004;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -1;
R0 = ROT R0 BY R4.L;
R1 = ROT R1 BY R4.L;
R2 = ROT R2 BY R4.L;
R3 = ROT R3 BY R4.L;
R4 = ROT R4 BY R4.L;
R5 = ROT R5 BY R4.L;
R6 = ROT R6 BY R4.L;
R7 = ROT R7 BY R4.L;
CHECKREG r0, 0x80918002;
CHECKREG r1, 0x091A2B3C;
CHECKREG r2, 0x11A2B3C4;
CHECKREG r3, 0x9A2B3C4D;
CHECKREG r4, 0x22B3FFFF;
CHECKREG r5, 0xAB3C4D5E;
CHECKREG r6, 0x33C4D5E6;
CHECKREG r7, 0xBC4D5E6F;
imm32 r0, 0x01230005;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -6;
R6 = ROT R0 BY R5.L;
R7 = ROT R1 BY R5.L;
R0 = ROT R2 BY R5.L;
R1 = ROT R3 BY R5.L;
R2 = ROT R4 BY R5.L;
R3 = ROT R5 BY R5.L;
R4 = ROT R6 BY R5.L;
R5 = ROT R7 BY R5.L;
CHECKREG r0, 0x4C8D159E;
CHECKREG r1, 0xD0D159E2;
CHECKREG r2, 0x59159E26;
CHECKREG r3, 0xD559E3FF;
CHECKREG r4, 0x04A01230;
CHECKREG r5, 0xCB012345;
CHECKREG r6, 0x28048C00;
CHECKREG r7, 0xC048D159;
imm32 r0, 0x01230006;
imm32 r1, 0x82345678;
imm32 r2, 0x73456789;
imm32 r3, 0x3456789a;
imm32 r4, 0xd56789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0xc789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R7 = ROT R0 BY R6.L;
R0 = ROT R1 BY R6.L;
R1 = ROT R2 BY R6.L;
R2 = ROT R3 BY R6.L;
R3 = ROT R4 BY R6.L;
R4 = ROT R5 BY R6.L;
R5 = ROT R6 BY R6.L;
R6 = ROT R7 BY R6.L;
CHECKREG r0, 0x59E10468;
CHECKREG r1, 0x9E26E68A;
CHECKREG r2, 0xE26A68AC;
CHECKREG r3, 0x26AFAACF;
CHECKREG r4, 0x6AF0ACF1;
CHECKREG r5, 0xFFC58F13;
CHECKREG r6, 0x091A0030;
CHECKREG r7, 0x00180246;
imm32 r0, 0x01230007;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -27;
R0 = ROT R0 BY R7.L;
R1 = ROT R1 BY R7.L;
R2 = ROT R2 BY R7.L;
R3 = ROT R3 BY R7.L;
R4 = ROT R4 BY R7.L;
R5 = ROT R5 BY R7.L;
R6 = ROT R6 BY R7.L;
R7 = ROT R7 BY R7.L;
CHECKREG r0, 0x48C001C0;
CHECKREG r1, 0x8D159E02;
CHECKREG r2, 0xD159E244;
CHECKREG r3, 0x159E2686;
CHECKREG r4, 0x59E26AE8;
CHECKREG r5, 0x9E26AF2A;
CHECKREG r6, 0xE26AF36C;
CHECKREG r7, 0x26BFF96F;
imm32 r0, 0x01230008;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0.L = 7;
//r0 = rot (r0 by rl0);
R1 = ROT R1 BY R0.L;
R2 = ROT R2 BY R0.L;
R3 = ROT R3 BY R0.L;
R4 = ROT R4 BY R0.L;
R5 = ROT R5 BY R0.L;
R6 = ROT R6 BY R0.L;
R7 = ROT R7 BY R0.L;
CHECKREG r0, 0x01230007;
CHECKREG r1, 0x1A2B3C04;
CHECKREG r2, 0xA2B3C4C8;
CHECKREG r3, 0x2B3C4D4D;
CHECKREG r4, 0xB3C4D591;
CHECKREG r5, 0x3C4D5E15;
CHECKREG r6, 0xC4D5E6D9;
CHECKREG r7, 0x4D5E6F5E;
imm32 r0, 0x01230009;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 16;
R0 = ROT R0 BY R1.L;
//r1 = rot (r1 by rl1);
R2 = ROT R2 BY R1.L;
R3 = ROT R3 BY R1.L;
R4 = ROT R4 BY R1.L;
R5 = ROT R5 BY R1.L;
R6 = ROT R6 BY R1.L;
R7 = ROT R7 BY R1.L;
CHECKREG r0, 0x00090091;
CHECKREG r1, 0x12340010;
CHECKREG r2, 0x678991A2;
CHECKREG r3, 0x789A9A2B;
CHECKREG r4, 0x89AB22B3;
CHECKREG r5, 0x9ABCAB3C;
CHECKREG r6, 0xABCD33C4;
CHECKREG r7, 0xBCDEBC4D;
imm32 r0, 0x0123000a;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 = ROT R0 BY R2.L;
R1 = ROT R1 BY R2.L;
//r2 = rot (r2 by rl2);
R3 = ROT R3 BY R2.L;
R4 = ROT R4 BY R2.L;
R5 = ROT R5 BY R2.L;
R6 = ROT R6 BY R2.L;
R7 = ROT R7 BY R2.L;
CHECKREG r0, 0x0048C002;
CHECKREG r1, 0x448D159E;
CHECKREG r2, 0x2345001F;
CHECKREG r3, 0x0D159E26;
CHECKREG r4, 0xD159E26A;
CHECKREG r5, 0x559E26AF;
CHECKREG r6, 0x99E26AF3;
CHECKREG r7, 0x1E26AF37;
imm32 r0, 0x0123000b;
imm32 r1, 0x92345678;
imm32 r2, 0x93456789;
imm32 r3, 0xc456789a;
imm32 r4, 0xa56789ab;
imm32 r5, 0xb6789abc;
imm32 r6, 0xe789abcd;
imm32 r7, 0xf89abcde;
R3.L = 33;
R0 = ROT R0 BY R3.L;
R1 = ROT R1 BY R3.L;
R2 = ROT R2 BY R3.L;
//r3 = rot (r3 by rl3);
R4 = ROT R4 BY R3.L;
R5 = ROT R5 BY R3.L;
R6 = ROT R6 BY R3.L;
R7 = ROT R7 BY R3.L;
CHECKREG r0, 0x048C002E;
CHECKREG r1, 0x48D159E1;
CHECKREG r2, 0x4D159E25;
CHECKREG r3, 0xC4560021;
CHECKREG r4, 0x959E26AD;
CHECKREG r5, 0xD9E26AF1;
CHECKREG r6, 0x9E26AF35;
CHECKREG r7, 0xE26AF37B;
imm32 r0, 0x0123000c;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -2;
R0 = ROT R0 BY R4.L;
R1 = ROT R1 BY R4.L;
R2 = ROT R2 BY R4.L;
R3 = ROT R3 BY R4.L;
//r4 = rot (r4 by rl4);
R5 = ROT R5 BY R4.L;
R6 = ROT R6 BY R4.L;
R7 = ROT R7 BY R4.L;
CHECKREG r0, 0x4048C003;
CHECKREG r1, 0x048D159E;
CHECKREG r2, 0x88D159E2;
CHECKREG r3, 0x0D159E26;
CHECKREG r4, 0x4567FFFE;
CHECKREG r5, 0x559E26AF;
CHECKREG r6, 0x99E26AF3;
CHECKREG r7, 0x1E26AF37;
imm32 r0, 0x0123000d;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -14;
R0 = ROT R0 BY R5.L;
R1 = ROT R1 BY R5.L;
R2 = ROT R2 BY R5.L;
R3 = ROT R3 BY R5.L;
R4 = ROT R4 BY R5.L;
//r5 = rot (r5 by rl5);
R6 = ROT R6 BY R5.L;
R7 = ROT R7 BY R5.L;
CHECKREG r0, 0x006C048C;
CHECKREG r1, 0xB3C048D1;
CHECKREG r2, 0x3C488D15;
CHECKREG r3, 0xC4D4D159;
CHECKREG r4, 0x4D5D159E;
CHECKREG r5, 0x5678FFF2;
CHECKREG r6, 0x5E699E26;
CHECKREG r7, 0xE6F5E26A;
imm32 r0, 0x0123000e;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -16;
R0 = ROT R0 BY R6.L;
R1 = ROT R1 BY R6.L;
R2 = ROT R2 BY R6.L;
R3 = ROT R3 BY R6.L;
R4 = ROT R4 BY R6.L;
R5 = ROT R5 BY R6.L;
//r6 = rot (r6 by rl6);
R7 = ROT R7 BY R6.L;
CHECKREG r0, 0x001D0123;
CHECKREG r1, 0xACF01234;
CHECKREG r2, 0xCF122345;
CHECKREG r3, 0xF1343456;
CHECKREG r4, 0x13564567;
CHECKREG r5, 0x35795678;
CHECKREG r6, 0x6789FFF0;
CHECKREG r7, 0x79BD789A;
imm32 r0, 0x0123000f;
imm32 r1, 0x12345678;
imm32 r2, 0x83456789;
imm32 r3, 0x3456789a;
imm32 r4, 0xd56789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x9789abcd;
imm32 r7, 0x789abcde;
R7.L = -32;
R0 = ROT R0 BY R7.L;
R1 = ROT R1 BY R7.L;
R2 = ROT R2 BY R7.L;
R3 = ROT R3 BY R7.L;
R4 = ROT R4 BY R7.L;
R5 = ROT R5 BY R7.L;
R6 = ROT R6 BY R7.L;
R7 = ROT R7 BY R7.L;
CHECKREG r0, 0x0246001f;
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x068ACF12;
CHECKREG r3, 0x68ACF135;
CHECKREG r4, 0xAACF1356;
CHECKREG r5, 0xACF13579;
CHECKREG r6, 0x2F13579A;
CHECKREG r7, 0xF135FFC1;
pass
|
stsp/binutils-ia16
| 6,161
|
sim/testsuite/bfin/c_dsp32mult_dr_tu.s
|
//Original:/testcases/core/c_dsp32mult_dr_tu/c_dsp32mult_dr_tu.dsp
// Spec Reference: dsp32mult single dr tu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (TFU);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (TFU);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (TFU);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (TFU);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (TFU);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (TFU);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (TFU);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (TFU);
CHECKREG r0, 0x1CFC1CFC;
CHECKREG r1, 0x0930114A;
CHECKREG r2, 0x01F5010A;
CHECKREG r3, 0x012A0054;
CHECKREG r4, 0x1CFC1CFC;
CHECKREG r5, 0x1B4E3364;
CHECKREG r6, 0x1B4E3364;
CHECKREG r7, 0x19B95B1D;
imm32 r0, 0x9923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1324b735;
imm32 r3, 0x99060037;
imm32 r4, 0x809bcd39;
imm32 r5, 0xb0a99f3b;
imm32 r6, 0xa00c093d;
imm32 r7, 0x12467093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (TFU);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (TFU);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (TFU);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (TFU);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (TFU);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (TFU);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (TFU);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (TFU);
CHECKREG r0, 0x00700070;
CHECKREG r1, 0x00420042;
CHECKREG r2, 0x0DB20DB2;
CHECKREG r3, 0x082F082F;
CHECKREG r4, 0x0DB20DB2;
CHECKREG r5, 0x6D820B70;
CHECKREG r6, 0x00270004;
CHECKREG r7, 0x00200020;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (TFU);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (TFU);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (TFU);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (TFU);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (TFU);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (TFU);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (TFU);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (TFU);
CHECKREG r0, 0x6F5897A6;
CHECKREG r1, 0x87430CD4;
CHECKREG r2, 0x0CD40CD4;
CHECKREG r3, 0xDFCB0115;
CHECKREG r4, 0x6F5897A6;
CHECKREG r5, 0x681A8DC9;
CHECKREG r6, 0x53FD3DAA;
CHECKREG r7, 0x39A82A55;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xe0060066;
imm32 r4, 0x9eab9d69;
imm32 r5, 0x10ecef6b;
imm32 r6, 0x800ee06d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (TFU);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (TFU);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (TFU);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (TFU);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (TFU);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (TFU);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (TFU);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (TFU);
CHECKREG r0, 0x400EC4BE;
CHECKREG r1, 0x09231005;
CHECKREG r2, 0x09231005;
CHECKREG r3, 0x014D014D;
CHECKREG r4, 0x01240383;
CHECKREG r5, 0x00140014;
CHECKREG r6, 0x400EC4BE;
CHECKREG r7, 0x04920E0B;
// mix order
imm32 r0, 0xac23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x90accd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x1246fc0f;
R2.H = R0.L * R7.L, R2.L = R0.H * R7.H (TFU);
R5.H = R1.L * R6.L, R5.L = R1.L * R6.H (TFU);
R6.H = R2.H * R5.L, R6.L = R2.H * R5.L (TFU);
R7.H = R3.L * R4.L, R7.L = R3.L * R4.L (TFU);
R0.H = R4.L * R3.L, R0.L = R4.L * R3.L (TFU);
R1.H = R5.H * R2.L, R1.L = R5.H * R2.L (TFU);
R3.H = R6.L * R1.L, R3.L = R6.L * R1.L (TFU);
R4.H = R7.H * R0.L, R4.L = R7.H * R0.H (TFU);
CHECKREG r0, 0x00050005;
CHECKREG r1, 0x02EB02EB;
CHECKREG r2, 0xA3E40C49;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x3CE10003;
CHECKREG r6, 0x00010001;
CHECKREG r7, 0x00050005;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (TFU);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (TFU);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (TFU);
R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (TFU);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (TFU);
R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (TFU);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (TFU);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (TFU);
CHECKREG r0, 0x0C370674;
CHECKREG r1, 0x00090423;
CHECKREG r2, 0x0E6606D6;
CHECKREG r3, 0x0078758E;
CHECKREG r4, 0x00430060;
CHECKREG r5, 0x00F00D60;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x007500DF;
imm32 r0, 0xfb235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13f46705;
imm32 r3, 0x000f0007;
imm32 r4, 0x90abfd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (TFU);
R3.H = R2.H * R7.H, R3.L = R2.H * R7.L (TFU);
R0.H = R1.L * R0.L, R0.L = R1.H * R0.H (TFU);
R1.H = R3.L * R0.L, R1.L = R3.H * R0.H (TFU);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (TFU);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (TFU);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (TFU);
R7.H = R7.L * R6.L, R7.L = R7.H * R6.H (TFU);
CHECKREG r0, 0x1B68CBC7;
CHECKREG r1, 0x001D0000;
CHECKREG r2, 0x00550004;
CHECKREG r3, 0x00060025;
CHECKREG r4, 0x00030030;
CHECKREG r5, 0x00050002;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0xab2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13246d05;
imm32 r3, 0x000600d7;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c500d;
imm32 r7, 0x1246760f;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (TFU);
R6.H = R6.H * R3.L, R6.L = R6.H * R3.L (TFU);
R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (TFU);
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (TFU);
R2.H = R1.L * R6.L, R2.L = R1.H * R6.H (TFU);
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (TFU);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.L (TFU);
R7.H = R4.H * R1.L, R7.L = R4.H * R1.L (TFU);
CHECKREG r0, 0x08442F1A;
CHECKREG r1, 0x03102C21;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00270027;
CHECKREG r4, 0x662411EE;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x119B119B;
pass
|
stsp/binutils-ia16
| 8,752
|
sim/testsuite/bfin/c_dsp32shiftim_lhalf_lp.s
|
//Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY imm5)
// RLx by imm5
imm32 r0, 0x00100a00;
imm32 r1, 0x00100a01;
imm32 r2, 0x00100a02;
imm32 r3, 0x00100a03;
imm32 r4, 0x00100a04;
imm32 r5, 0x00100a05;
imm32 r6, 0x00100a06;
imm32 r7, 0x00100a07;
R7.L = R0.L << 0;
R0.L = R1.L << 1;
R1.L = R2.L << 2;
R2.L = R3.L << 3;
R3.L = R4.L << 4;
R4.L = R5.L << 5;
R5.L = R6.L << 6;
R6.L = R7.L << 7;
CHECKREG r1, 0x00102808;
CHECKREG r0, 0x00101402;
CHECKREG r2, 0x00105018;
CHECKREG r3, 0x0010A040;
CHECKREG r4, 0x001040A0;
CHECKREG r5, 0x00108180;
CHECKREG r6, 0x00100000;
CHECKREG r7, 0x00100A00;
imm32 r0, 0x00200018;
imm32 r1, 0x00200019;
imm32 r2, 0x0020001a;
imm32 r3, 0x0020001b;
imm32 r4, 0x0020001c;
imm32 r5, 0x0020001d;
imm32 r6, 0x0020001e;
imm32 r7, 0x0020001f;
R2.L = R0.L << 8;
R3.L = R1.L << 9;
R4.L = R2.L << 10;
R5.L = R3.L << 11;
R6.L = R4.L << 12;
R7.L = R5.L << 13;
R0.L = R6.L << 14;
R1.L = R7.L << 15;
CHECKREG r0, 0x00200000;
CHECKREG r1, 0x00200000;
CHECKREG r2, 0x00201800;
CHECKREG r3, 0x00203200;
CHECKREG r4, 0x00200000;
CHECKREG r5, 0x00200000;
CHECKREG r6, 0x00200000;
CHECKREG r7, 0x00200000;
imm32 r0, 0x05002001;
imm32 r1, 0x05002001;
imm32 r2, 0x0500000f;
imm32 r3, 0x05002003;
imm32 r4, 0x05002004;
imm32 r5, 0x05002005;
imm32 r6, 0x05002006;
imm32 r7, 0x05002007;
R3.L = R0.L << 0;
R4.L = R1.L << 1;
R5.L = R2.L << 2;
R6.L = R3.L << 3;
R7.L = R4.L << 4;
R0.L = R5.L << 5;
R1.L = R6.L << 6;
R2.L = R7.L << 7;
CHECKREG r0, 0x05000780;
CHECKREG r1, 0x05000200;
CHECKREG r2, 0x05001000;
CHECKREG r3, 0x05002001;
CHECKREG r4, 0x05004002;
CHECKREG r5, 0x0500003C;
CHECKREG r6, 0x05000008;
CHECKREG r7, 0x05000020;
imm32 r0, 0x03000031;
imm32 r1, 0x03000031;
imm32 r2, 0x03000032;
imm32 r3, 0x03000030;
imm32 r4, 0x03000034;
imm32 r5, 0x03000035;
imm32 r6, 0x03000036;
imm32 r7, 0x03000037;
R4.L = R0.L << 8;
R5.L = R1.L << 9;
R6.L = R2.L << 10;
R7.L = R3.L << 11;
R0.L = R4.L << 12;
R1.L = R5.L << 13;
R2.L = R6.L << 14;
R3.L = R7.L << 15;
CHECKREG r0, 0x03000000;
CHECKREG r1, 0x03000000;
CHECKREG r2, 0x03000000;
CHECKREG r3, 0x03000000;
CHECKREG r4, 0x03003100;
CHECKREG r5, 0x03006200;
CHECKREG r6, 0x0300C800;
CHECKREG r7, 0x03008000;
// RHx by RLx
imm32 r0, 0x03000000;
imm32 r1, 0x03000000;
imm32 r2, 0x03000000;
imm32 r3, 0x03000000;
imm32 r4, 0x03003100;
imm32 r5, 0x03006200;
imm32 r6, 0x0300C800;
imm32 r7, 0x03008000;
R5.L = R0.H << 0;
R6.L = R1.H << 1;
R7.L = R2.H << 2;
R0.L = R3.H << 3;
R1.L = R4.H << 4;
R2.L = R5.H << 5;
R3.L = R6.H << 6;
R4.L = R7.H << 7;
CHECKREG r0, 0x03001800;
CHECKREG r1, 0x03003000;
CHECKREG r2, 0x03006000;
CHECKREG r3, 0x0300C000;
CHECKREG r4, 0x03008000;
CHECKREG r5, 0x03000300;
CHECKREG r6, 0x03000600;
CHECKREG r7, 0x03000C00;
imm32 r0, 0x05018000;
imm32 r1, 0x05018001;
imm32 r2, 0x05028000;
imm32 r3, 0x05038000;
imm32 r4, 0x05048000;
imm32 r5, 0x05058000;
imm32 r6, 0x05068000;
imm32 r7, 0x05078000;
R6.L = R0.H << 8;
R7.L = R1.H << 9;
R0.L = R2.H << 10;
R1.L = R3.H << 11;
R2.L = R4.H << 12;
R3.L = R5.H << 13;
R4.L = R6.H << 14;
R5.L = R7.H << 15;
CHECKREG r0, 0x05010800;
CHECKREG r1, 0x05011800;
CHECKREG r2, 0x05024000;
CHECKREG r3, 0x0503A000;
CHECKREG r4, 0x05048000;
CHECKREG r5, 0x05058000;
CHECKREG r6, 0x05060100;
CHECKREG r7, 0x05070200;
imm32 r0, 0x60019000;
imm32 r1, 0x60019000;
imm32 r2, 0x6002900f;
imm32 r3, 0x60039000;
imm32 r4, 0x60049000;
imm32 r5, 0x60059000;
imm32 r6, 0x60069000;
imm32 r7, 0x60079000;
R7.L = R0.H << 0;
R0.L = R1.H << 1;
R1.L = R2.H << 2;
R2.L = R3.H << 3;
R3.L = R4.H << 4;
R4.L = R5.H << 5;
R5.L = R6.H << 6;
R6.L = R7.H << 7;
CHECKREG r0, 0x6001C002;
CHECKREG r1, 0x60018008;
CHECKREG r2, 0x60020018;
CHECKREG r3, 0x60030040;
CHECKREG r4, 0x600400A0;
CHECKREG r5, 0x60050180;
CHECKREG r6, 0x60060380;
CHECKREG r7, 0x60076001;
imm32 r0, 0x70010001;
imm32 r1, 0x70010001;
imm32 r2, 0x70020002;
imm32 r3, 0x77030010;
imm32 r4, 0x70040004;
imm32 r5, 0x70050005;
imm32 r6, 0x70060006;
imm32 r7, 0x70070007;
R0.L = R0.H << 8;
R1.L = R1.H << 9;
R2.L = R2.H << 10;
R3.L = R3.H << 11;
R4.L = R4.H << 12;
R5.L = R5.H << 13;
R6.L = R6.H << 14;
R7.L = R7.H << 15;
CHECKREG r0, 0x70010100;
CHECKREG r1, 0x70010200;
CHECKREG r2, 0x70020800;
CHECKREG r3, 0x77031800;
CHECKREG r4, 0x70044000;
CHECKREG r5, 0x7005A000;
CHECKREG r6, 0x70068000;
CHECKREG r7, 0x70078000;
// d_hi = lshft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0xa8000000;
imm32 r1, 0xa8000001;
imm32 r2, 0xa8000002;
imm32 r3, 0xa8000003;
imm32 r4, 0xa8000004;
imm32 r5, 0xa8000005;
imm32 r6, 0xa8000006;
imm32 r7, 0xa8000007;
R0.H = R0.L << 0;
R1.H = R1.L << 1;
R2.H = R2.L << 2;
R3.H = R3.L << 3;
R4.H = R4.L << 4;
R5.H = R5.L << 5;
R6.H = R6.L << 6;
R7.H = R7.L << 7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00080002;
CHECKREG r3, 0x00180003;
CHECKREG r4, 0x00400004;
CHECKREG r5, 0x00A00005;
CHECKREG r6, 0x01800006;
CHECKREG r7, 0x03800007;
imm32 r0, 0xf0090001;
imm32 r1, 0xf0090001;
imm32 r2, 0xf0090002;
imm32 r3, 0xf0090003;
imm32 r4, 0xf0090004;
imm32 r5, 0xf0090005;
imm32 r6, 0xf0000006;
imm32 r7, 0xf0000007;
R1.H = R0.L << 8;
R2.H = R1.L << 9;
R3.H = R2.L << 10;
R4.H = R3.L << 11;
R5.H = R4.L << 12;
R6.H = R5.L << 13;
R7.H = R6.L << 14;
R0.H = R7.L << 15;
CHECKREG r1, 0x01000001;
CHECKREG r2, 0x02000002;
CHECKREG r3, 0x08000003;
CHECKREG r4, 0x18000004;
CHECKREG r5, 0x40000005;
CHECKREG r6, 0xA0000006;
CHECKREG r7, 0x80000007;
CHECKREG r0, 0x80000001;
imm32 r0, 0x07000001;
imm32 r1, 0x07000001;
imm32 r2, 0x0700000f;
imm32 r3, 0x07000003;
imm32 r4, 0x07000004;
imm32 r5, 0x07000005;
imm32 r6, 0x07000006;
imm32 r7, 0x07000007;
R3.H = R0.L << 0;
R4.H = R1.L << 1;
R5.H = R2.L << 2;
R6.H = R3.L << 3;
R7.H = R4.L << 4;
R0.H = R5.L << 5;
R1.H = R6.L << 6;
R2.H = R7.L << 7;
CHECKREG r0, 0x00A00001;
CHECKREG r1, 0x01800001;
CHECKREG r2, 0x0380000F;
CHECKREG r3, 0x00010003;
CHECKREG r4, 0x00020004;
CHECKREG r5, 0x003C0005;
CHECKREG r6, 0x00180006;
CHECKREG r7, 0x00400007;
imm32 r0, 0x00000501;
imm32 r1, 0x00000501;
imm32 r2, 0x00000502;
imm32 r3, 0x00000510;
imm32 r4, 0x00000504;
imm32 r5, 0x00000505;
imm32 r6, 0x00000506;
imm32 r7, 0x00000507;
R4.H = R0.L << 8;
R5.H = R1.L << 9;
R6.H = R2.L << 10;
R7.H = R3.L << 11;
R0.H = R4.L << 12;
R1.H = R5.L << 13;
R2.H = R6.L << 14;
R3.H = R7.L << 15;
CHECKREG r0, 0x40000501;
CHECKREG r1, 0xA0000501;
CHECKREG r2, 0x80000502;
CHECKREG r3, 0x80000510;
CHECKREG r4, 0x01000504;
CHECKREG r5, 0x02000505;
CHECKREG r6, 0x08000506;
CHECKREG r7, 0x80000507;
imm32 r0, 0x00a00800;
imm32 r1, 0x00a10800;
imm32 r2, 0x00a20800;
imm32 r3, 0x00a30800;
imm32 r4, 0x00a40800;
imm32 r5, 0x00a50800;
imm32 r6, 0x00a60800;
imm32 r7, 0x00a70800;
R5.H = R0.H << 0;
R6.H = R1.H << 1;
R7.H = R2.H << 2;
R0.H = R3.H << 3;
R1.H = R4.H << 4;
R2.H = R5.H << 5;
R3.H = R6.H << 6;
R4.H = R7.H << 7;
CHECKREG r0, 0x05180800;
CHECKREG r1, 0x0A400800;
CHECKREG r2, 0x14000800;
CHECKREG r3, 0x50800800;
CHECKREG r4, 0x44000800;
CHECKREG r5, 0x00A00800;
CHECKREG r6, 0x01420800;
CHECKREG r7, 0x02880800;
imm32 r0, 0x0c010000;
imm32 r1, 0x0c010001;
imm32 r2, 0x0c020000;
imm32 r3, 0x0c030000;
imm32 r4, 0x0c040000;
imm32 r5, 0x0c050000;
imm32 r6, 0x0c060000;
imm32 r7, 0x0c070000;
R6.H = R0.H << 8;
R7.H = R1.H << 9;
R0.H = R2.H << 10;
R1.H = R3.H << 11;
R2.H = R4.H << 12;
R3.H = R5.H << 13;
R4.H = R6.H << 14;
R5.H = R7.H << 15;
CHECKREG r0, 0x08000000;
CHECKREG r1, 0x18000001;
CHECKREG r2, 0x40000000;
CHECKREG r3, 0xA0000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x01000000;
CHECKREG r7, 0x02000000;
imm32 r0, 0x00b10000;
imm32 r1, 0x00b10000;
imm32 r2, 0x00b2000f;
imm32 r3, 0x00b30000;
imm32 r4, 0x00b40000;
imm32 r5, 0x00b50000;
imm32 r6, 0x00b60000;
imm32 r7, 0x00b70000;
R7.L = R0.H << 0;
R0.L = R1.H << 1;
R1.L = R2.H << 2;
R2.L = R3.H << 3;
R3.L = R4.H << 4;
R4.L = R5.H << 5;
R5.L = R6.H << 6;
R6.L = R7.H << 7;
CHECKREG r0, 0x00B10162;
CHECKREG r1, 0x00B102C8;
CHECKREG r2, 0x00B20598;
CHECKREG r3, 0x00B30B40;
CHECKREG r4, 0x00B416A0;
CHECKREG r5, 0x00B52D80;
CHECKREG r6, 0x00B65B80;
CHECKREG r7, 0x00B700B1;
imm32 r0, 0x0a010700;
imm32 r1, 0x0a010700;
imm32 r2, 0x0a020700;
imm32 r3, 0x0a030710;
imm32 r4, 0x0a040700;
imm32 r5, 0x0a050700;
imm32 r6, 0x0a060700;
imm32 r7, 0x0a070700;
R0.H = R0.H << 8;
R1.H = R1.H << 9;
R2.H = R2.H << 10;
R3.H = R3.H << 11;
R4.H = R4.H << 12;
R5.H = R5.H << 13;
R6.H = R6.H << 14;
R7.H = R7.H << 15;
CHECKREG r0, 0x01000700;
CHECKREG r1, 0x02000700;
CHECKREG r2, 0x08000700;
CHECKREG r3, 0x18000710;
CHECKREG r4, 0x40000700;
CHECKREG r5, 0xA0000700;
CHECKREG r6, 0x80000700;
CHECKREG r7, 0x80000700;
pass
|
stsp/binutils-ia16
| 1,064
|
sim/testsuite/bfin/c_brcc_bp3.s
|
//Original:/testcases/core/c_brcc_bp3/c_brcc_bp3.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2; // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 2,822
|
sim/testsuite/bfin/c_dsp32mac_dr_a0_t.s
|
//Original:/testcases/core/c_dsp32mac_dr_a0_t/c_dsp32mac_dr_a0_t.dsp
// Spec Reference: dsp32mac dr a0 t (truncation)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0069007;
imm32 r4, 0xefbc4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c800d;
imm32 r7, 0xf78e900f;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (T);
R1 = A0.w;
A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (T);
R3 = A0.w;
A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (T);
R5 = A0.w;
A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (T);
R7 = A0.w;
CHECKREG r0, 0xA354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xC12436FD;
CHECKREG r3, 0x36FD0FF8;
CHECKREG r4, 0xEFBC3D71;
CHECKREG r5, 0x3D716BD0;
CHECKREG r6, 0xE00C45E2;
CHECKREG r7, 0x45E2903C;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0xb0069007;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.L = ( A0 = R1.L * R0.L ) (T);
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H ) (T);
R3 = A0.w;
R4.L = ( A0 -= R4.H * R5.L ) (T);
R5 = A0.w;
R6.L = ( A0 = R6.H * R7.H ) (T);
R7 = A0.w;
CHECKREG r0, 0x6354011E;
CHECKREG r1, 0x011EBDD6;
CHECKREG r2, 0xA124CB17;
CHECKREG r3, 0xCB172B82;
CHECKREG r4, 0xCFBCB2F9;
CHECKREG r5, 0xB2F9515A;
CHECKREG r6, 0xE00CE626;
CHECKREG r7, 0xE6263550;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.L = ( A0 -= R1.L * R0.L ) (T);
R1 = A0.w;
R2.L = ( A0 = R2.H * R3.L ) (T);
R3 = A0.w;
R4.L = ( A0 -= R4.H * R5.H ) (T);
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H ) (T);
R7 = A0.w;
CHECKREG r0, 0x5354D42C;
CHECKREG r1, 0xD42C177A;
CHECKREG r2, 0x71246305;
CHECKREG r3, 0x6305AFF8;
CHECKREG r4, 0x9FBC1C7B;
CHECKREG r5, 0x1C7B9C20;
CHECKREG r6, 0xB00C074B;
CHECKREG r7, 0x074B208C;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
A1 = R1.L * R0.L (M), R0.L = ( A0 += R1.L * R0.L ) (T);
R1 = A0.w;
A1 += R2.L * R3.H (M), R2.L = ( A0 -= R2.H * R3.L ) (T);
R3 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (T);
R5 = A0.w;
A1 -= R6.H * R7.H (M), R6.L = ( A0 += R6.L * R7.H ) (T);
R7 = A0.w;
CHECKREG r0, 0x3354066D;
CHECKREG r1, 0x066D3E62;
CHECKREG r2, 0x71240667;
CHECKREG r3, 0x06670E6A;
CHECKREG r4, 0xAFBC1CB7;
CHECKREG r5, 0x1CB733D8;
CHECKREG r6, 0xC00CCF17;
CHECKREG r7, 0xCF173844;
pass
|
stsp/binutils-ia16
| 94,871
|
sim/testsuite/bfin/lmu_cplb_multiple0.S
|
//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple0/lmu_cplb_multiple0.dsp
// Description: Multiple CPLB Hit exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
// Test LMU/CPLB exceptions
// Basic outline:
// Set exception handler
// program CPLB Entries
// Enable CPLB in DMEM_CNTL
// perform access
// verify exception occurred
CHECK_INIT(p5, 0xEFFFFFFC);
//-------------------------
// Zero the CPLB Address and Data regs.
LD32(p0, DCPLB_ADDR0);
R0 = 0;
[ P0 ++ ] = R0; // 0
[ P0 ++ ] = R0; // 1
[ P0 ++ ] = R0; // 2
[ P0 ++ ] = R0; // 3
[ P0 ++ ] = R0; // 4
[ P0 ++ ] = R0; // 5
[ P0 ++ ] = R0; // 6
[ P0 ++ ] = R0; // 7
[ P0 ++ ] = R0; // 8
[ P0 ++ ] = R0; // 9
[ P0 ++ ] = R0; // 10
[ P0 ++ ] = R0; // 11
[ P0 ++ ] = R0; // 12
[ P0 ++ ] = R0; // 13
[ P0 ++ ] = R0; // 14
[ P0 ++ ] = R0; // 15
LD32(p0, DCPLB_DATA0);
[ P0 ++ ] = R0; // 0
[ P0 ++ ] = R0; // 1
[ P0 ++ ] = R0; // 2
[ P0 ++ ] = R0; // 3
[ P0 ++ ] = R0; // 4
[ P0 ++ ] = R0; // 5
[ P0 ++ ] = R0; // 6
[ P0 ++ ] = R0; // 7
[ P0 ++ ] = R0; // 8
[ P0 ++ ] = R0; // 9
[ P0 ++ ] = R0; // 10
[ P0 ++ ] = R0; // 11
[ P0 ++ ] = R0; // 12
[ P0 ++ ] = R0; // 13
[ P0 ++ ] = R0; // 14
[ P0 ++ ] = R0; // 15
// Now set the CPLB entries we will need
// Data area for the desired error
WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0);
// MMR space
WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0);
WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0);
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
WR_MMR_LABEL(EVT15, int_15, p0, r1);
WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
CSYNC;
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
// But first raise interrupt 15 so we can do one test
// in supervisor mode.
RAISE 15;
NOP;
RTI;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
handler:
// generic protection exception handler
// Inputs:
// p2: addr of CPLB entry to be modified ( current test)
//
// Outputs:
// r4: SEQSTAT
// r5: DCPLB_FAULT_ADDR
// r6: DCPLB_STATUS
// r7: RETX (instruction addr where exception occurred)
R4 = SEQSTAT; // Get exception cause
R4 <<= 24; // Clear HWERRCAUSE + SFTRESET
R4 >>= 24;
// read data addr which caused exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r5);
RD_MMR(DCPLB_STATUS, p0, r6);
R7 = RETX; // get address of excepting instruction
// disable the offending CPLB entries
R2 = 0;
[ P2 ] = R2;
CSYNC;
// return from exception and re-execute offending instruction
RTX;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
int_15:
// Interrupt 15 handler - test will run in supervisor mode
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x41C6 (Z);
LD32(p2, DCPLB_DATA1);
X0_1: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1));
CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x167E (Z);
LD32(p2, DCPLB_DATA2);
X0_2: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2));
CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2781 (Z);
LD32(p2, DCPLB_DATA3);
X0_3: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3));
CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x446B (Z);
LD32(p2, DCPLB_DATA4);
X0_4: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4));
CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x794B (Z);
LD32(p2, DCPLB_DATA5);
X0_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5));
CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x15FB (Z);
LD32(p2, DCPLB_DATA6);
X0_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6));
CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x59E2 (Z);
LD32(p2, DCPLB_DATA7);
X0_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7));
CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1CFB (Z);
LD32(p2, DCPLB_DATA8);
X0_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8));
CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3F54 (Z);
LD32(p2, DCPLB_DATA9);
X0_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9));
CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0FF6 (Z);
LD32(p2, DCPLB_DATA10);
X0_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10));
CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0ABD (Z);
LD32(p2, DCPLB_DATA11);
X0_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11));
CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x31DF (Z);
LD32(p2, DCPLB_DATA12);
X0_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12));
CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x237C (Z);
LD32(p2, DCPLB_DATA13);
X0_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13));
CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2F1C (Z);
LD32(p2, DCPLB_DATA14);
X0_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14));
CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7DE1 (Z);
LD32(p2, DCPLB_DATA2);
X1_2: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2));
CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4487 (Z);
LD32(p2, DCPLB_DATA3);
X1_3: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3));
CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6201 (Z);
LD32(p2, DCPLB_DATA4);
X1_4: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4));
CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x52BF (Z);
LD32(p2, DCPLB_DATA5);
X1_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5));
CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6231 (Z);
LD32(p2, DCPLB_DATA6);
X1_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6));
CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63DE (Z);
LD32(p2, DCPLB_DATA7);
X1_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7));
CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6956 (Z);
LD32(p2, DCPLB_DATA8);
X1_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8));
CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1372 (Z);
LD32(p2, DCPLB_DATA9);
X1_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9));
CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x500F (Z);
LD32(p2, DCPLB_DATA10);
X1_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10));
CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2847 (Z);
LD32(p2, DCPLB_DATA11);
X1_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11));
CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2C67 (Z);
LD32(p2, DCPLB_DATA12);
X1_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12));
CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7566 (Z);
LD32(p2, DCPLB_DATA13);
X1_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13));
CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4287 (Z);
LD32(p2, DCPLB_DATA14);
X1_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14));
CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3359 (Z);
LD32(p2, DCPLB_DATA3);
X2_3: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3));
CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4DAA (Z);
LD32(p2, DCPLB_DATA4);
X2_4: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4));
CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6488 (Z);
LD32(p2, DCPLB_DATA5);
X2_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5));
CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x773C (Z);
LD32(p2, DCPLB_DATA6);
X2_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6));
CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6F59 (Z);
LD32(p2, DCPLB_DATA7);
X2_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7));
CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6EEA (Z);
LD32(p2, DCPLB_DATA8);
X2_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8));
CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5656 (Z);
LD32(p2, DCPLB_DATA9);
X2_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9));
CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6113 (Z);
LD32(p2, DCPLB_DATA10);
X2_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10));
CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4A7B (Z);
LD32(p2, DCPLB_DATA11);
X2_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11));
CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x31D2 (Z);
LD32(p2, DCPLB_DATA12);
X2_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12));
CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2D85 (Z);
LD32(p2, DCPLB_DATA13);
X2_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13));
CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x19A1 (Z);
LD32(p2, DCPLB_DATA14);
X2_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14));
CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x69D8 (Z);
LD32(p2, DCPLB_DATA4);
X3_4: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4));
CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x353C (Z);
LD32(p2, DCPLB_DATA5);
X3_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5));
CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3B54 (Z);
LD32(p2, DCPLB_DATA6);
X3_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6));
CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7D55 (Z);
LD32(p2, DCPLB_DATA7);
X3_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7));
CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x102F (Z);
LD32(p2, DCPLB_DATA8);
X3_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8));
CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1B37 (Z);
LD32(p2, DCPLB_DATA9);
X3_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9));
CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7AAE (Z);
LD32(p2, DCPLB_DATA10);
X3_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10));
CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5E65 (Z);
LD32(p2, DCPLB_DATA11);
X3_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11));
CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x345B (Z);
LD32(p2, DCPLB_DATA12);
X3_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12));
CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63DA (Z);
LD32(p2, DCPLB_DATA13);
X3_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13));
CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6102 (Z);
LD32(p2, DCPLB_DATA14);
X3_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14));
CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7A79 (Z);
LD32(p2, DCPLB_DATA5);
X4_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5));
CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0398 (Z);
LD32(p2, DCPLB_DATA6);
X4_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6));
CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x28CC (Z);
LD32(p2, DCPLB_DATA7);
X4_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7));
CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x60E3 (Z);
LD32(p2, DCPLB_DATA8);
X4_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8));
CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1F1A (Z);
LD32(p2, DCPLB_DATA9);
X4_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9));
CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4B76 (Z);
LD32(p2, DCPLB_DATA10);
X4_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10));
CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x058E (Z);
LD32(p2, DCPLB_DATA11);
X4_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11));
CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7A5F (Z);
LD32(p2, DCPLB_DATA12);
X4_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12));
CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x28D9 (Z);
LD32(p2, DCPLB_DATA13);
X4_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13));
CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0799 (Z);
LD32(p2, DCPLB_DATA14);
X4_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14));
CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x388F (Z);
LD32(p2, DCPLB_DATA6);
X5_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6));
CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x751F (Z);
LD32(p2, DCPLB_DATA7);
X5_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7));
CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x493F (Z);
LD32(p2, DCPLB_DATA8);
X5_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8));
CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0F36 (Z);
LD32(p2, DCPLB_DATA9);
X5_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9));
CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x48EE (Z);
LD32(p2, DCPLB_DATA10);
X5_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10));
CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2043 (Z);
LD32(p2, DCPLB_DATA11);
X5_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11));
CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3F78 (Z);
LD32(p2, DCPLB_DATA12);
X5_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12));
CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1E4D (Z);
LD32(p2, DCPLB_DATA13);
X5_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13));
CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3D0D (Z);
LD32(p2, DCPLB_DATA14);
X5_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14));
CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x33FA (Z);
LD32(p2, DCPLB_DATA7);
X6_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7));
CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6FBE (Z);
LD32(p2, DCPLB_DATA8);
X6_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8));
CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x36A6 (Z);
LD32(p2, DCPLB_DATA9);
X6_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9));
CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2DDA (Z);
LD32(p2, DCPLB_DATA10);
X6_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10));
CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x30E4 (Z);
LD32(p2, DCPLB_DATA11);
X6_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11));
CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0586 (Z);
LD32(p2, DCPLB_DATA12);
X6_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12));
CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x148E (Z);
LD32(p2, DCPLB_DATA13);
X6_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13));
CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x42DC (Z);
LD32(p2, DCPLB_DATA14);
X6_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14));
CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5929 (Z);
LD32(p2, DCPLB_DATA8);
X7_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8));
CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0C6D (Z);
LD32(p2, DCPLB_DATA9);
X7_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9));
CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x334E (Z);
LD32(p2, DCPLB_DATA10);
X7_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10));
CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x62FF (Z);
LD32(p2, DCPLB_DATA11);
X7_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11));
CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1F56 (Z);
LD32(p2, DCPLB_DATA12);
X7_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12));
CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2BE1 (Z);
LD32(p2, DCPLB_DATA13);
X7_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13));
CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1D70 (Z);
LD32(p2, DCPLB_DATA14);
X7_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14));
CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2620 (Z);
LD32(p2, DCPLB_DATA9);
X8_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9));
CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x26FB (Z);
LD32(p2, DCPLB_DATA10);
X8_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10));
CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x718F (Z);
LD32(p2, DCPLB_DATA11);
X8_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11));
CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x04B1 (Z);
LD32(p2, DCPLB_DATA12);
X8_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12));
CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5358 (Z);
LD32(p2, DCPLB_DATA13);
X8_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13));
CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3305 (Z);
LD32(p2, DCPLB_DATA14);
X8_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14));
CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5690 (Z);
LD32(p2, DCPLB_DATA10);
X9_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10));
CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5DC5 (Z);
LD32(p2, DCPLB_DATA11);
X9_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11));
CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7809 (Z);
LD32(p2, DCPLB_DATA12);
X9_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12));
CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1DDC (Z);
LD32(p2, DCPLB_DATA13);
X9_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13));
CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6B53 (Z);
LD32(p2, DCPLB_DATA14);
X9_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14));
CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7BCD (Z);
LD32(p2, DCPLB_DATA11);
X10_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11));
CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63AA (Z);
LD32(p2, DCPLB_DATA12);
X10_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12));
CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x373B (Z);
LD32(p2, DCPLB_DATA13);
X10_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13));
CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5648 (Z);
LD32(p2, DCPLB_DATA14);
X10_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14));
CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6799 (Z);
LD32(p2, DCPLB_DATA12);
X11_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12));
CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1452 (Z);
LD32(p2, DCPLB_DATA13);
X11_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13));
CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x23D3 (Z);
LD32(p2, DCPLB_DATA14);
X11_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14));
CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1152 (Z);
LD32(p2, DCPLB_DATA13);
X12_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA12, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13));
CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6E9D (Z);
LD32(p2, DCPLB_DATA14);
X12_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA12, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14));
CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6006 (Z);
LD32(p2, DCPLB_DATA14);
X13_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA13, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14));
CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
User:
NOP;
dbg_pass;
|
stsp/binutils-ia16
| 4,307
|
sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s
|
//Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp
// Spec Reference: dagmodik l not zero & i+m < b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000100e;
imm32 b1, 0x0000110c;
imm32 b2, 0x0000101a;
imm32 b3, 0x00001008;
imm32 l0, 0x000000a1;
imm32 l1, 0x000000b2;
imm32 l2, 0x000000c3;
imm32 l3, 0x000000d4;
imm32 m0, 0x00000005;
imm32 m1, 0x00000004;
imm32 m2, 0x00000003;
imm32 m3, 0x00000002;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x00001102;
CHECKREG r2, 0x00001012;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001104;
CHECKREG r6, 0x00001014;
CHECKREG r7, 0x00001005;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x000010A3;
CHECKREG r1, 0x000011B4;
CHECKREG r2, 0x000010D5;
CHECKREG r3, 0x000010D7;
CHECKREG r4, 0x000010A1;
CHECKREG r5, 0x000011B2;
CHECKREG r6, 0x000010D3;
CHECKREG r7, 0x000010D5;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x000010A5;
CHECKREG r1, 0x000011B6;
CHECKREG r2, 0x000010D7;
CHECKREG r3, 0x000010D9;
CHECKREG r4, 0x000010A9;
CHECKREG r5, 0x000011BA;
CHECKREG r6, 0x000010DB;
CHECKREG r7, 0x00001009;
I0 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG r0, 0x000010A1;
CHECKREG r1, 0x000011B2;
CHECKREG r2, 0x000010D3;
CHECKREG r3, 0x000010D5;
CHECKREG r4, 0x000010A9;
CHECKREG r5, 0x000011BA;
CHECKREG r6, 0x000010DB;
CHECKREG r7, 0x00001009;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x000010A1;
CHECKREG r1, 0x000011B2;
CHECKREG r2, 0x000010D3;
CHECKREG r3, 0x000010D5;
CHECKREG r4, 0x00001099;
CHECKREG r5, 0x000011AA;
CHECKREG r6, 0x000010CB;
CHECKREG r7, 0x000010CD;
// i+m = b+l
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000100e;
imm32 b1, 0x0000110c;
imm32 b2, 0x0000101a;
imm32 b3, 0x00001008;
imm32 l0, 0x00000011;
imm32 l1, 0x00000012;
imm32 l2, 0x00000013;
imm32 l3, 0x00000014;
imm32 m0, 0x00000002;
imm32 m1, 0x00000003;
imm32 m2, 0x00000004;
imm32 m3, 0x00000005;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x00001102;
CHECKREG r2, 0x00001012;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001104;
CHECKREG r6, 0x00001014;
CHECKREG r7, 0x00001005;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001013;
CHECKREG r1, 0x00001114;
CHECKREG r2, 0x00001025;
CHECKREG r3, 0x00001017;
CHECKREG r4, 0x00001011;
CHECKREG r5, 0x00001112;
CHECKREG r6, 0x00001023;
CHECKREG r7, 0x00001015;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001015;
CHECKREG r1, 0x00001116;
CHECKREG r2, 0x00001027;
CHECKREG r3, 0x00001019;
CHECKREG r4, 0x00001019;
CHECKREG r5, 0x0000111A;
CHECKREG r6, 0x0000102B;
CHECKREG r7, 0x00001009;
I0 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG r0, 0x00001011;
CHECKREG r1, 0x00001112;
CHECKREG r2, 0x00001023;
CHECKREG r3, 0x00001015;
CHECKREG r4, 0x00001019;
CHECKREG r5, 0x0000111A;
CHECKREG r6, 0x0000102B;
CHECKREG r7, 0x00001009;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001011;
CHECKREG r1, 0x00001112;
CHECKREG r2, 0x00001023;
CHECKREG r3, 0x00001015;
CHECKREG r4, 0x0000101A;
CHECKREG r5, 0x0000111C;
CHECKREG r6, 0x0000101B;
CHECKREG r7, 0x0000100D;
pass
|
stsp/binutils-ia16
| 3,441
|
sim/testsuite/bfin/disalnexcpt_implicit.S
|
# Blackfin testcase for insns that implicitly have DISALGNEXCPT behavior
# when used in parallel insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
LINK 0x100;
# Set up I0/I1/I2/I3 to be unaligned by 0/1/2/3 bytes
init_l_regs 0
init_m_regs 0
R0 = SP;
BITCLR (R0, 0);
BITCLR (R0, 1);
I0 = R0;
B0 = R0;
R1 = 1;
R1 = R0 + R1;
I1 = R1;
B1 = R1;
R2 = 2;
R2 = R0 + R2;
I2 = R2;
B2 = R2;
R3 = 3;
R3 = R0 + R3;
I3 = R3;
B3 = R3;
#define EXP_VAL 0x12345678
#define EXP(r, n) CHECKREG (r, EXP_VAL); r = 0; I##n = B##n
imm32 R5, EXP_VAL;
imm32 R6, 0x9abcdef0;
imm32 R7, 0x0a1b2c3e;
[SP] = R5;
[SP - 4] = R6;
[SP + 4] = R7;
#define BYTEPACK(n) \
R7 = BYTEPACK (R0, R1) || R4 = [I##n]; EXP (R4, n); \
R6 = BYTEPACK (R0, R1) || R5 = [I##n ++ M##n]; EXP (R5, n); \
R5 = BYTEPACK (R0, R1) || R6 = [I##n++]; EXP (R6, n); \
R4 = BYTEPACK (R0, R1) || R7 = [I##n--]; EXP (R7, n);
BYTEPACK(0)
BYTEPACK(1)
BYTEPACK(2)
BYTEPACK(3)
#define BYTEUNPACK(n) \
(R7, R5) = BYTEUNPACK R1:0 || R4 = [I##n]; EXP (R4, n); \
(R6, R7) = BYTEUNPACK R3:2 || R5 = [I##n ++ M##n]; EXP (R5, n); \
(R5, R4) = BYTEUNPACK R1:0 || R6 = [I##n++]; EXP (R6, n); \
(R4, R6) = BYTEUNPACK R3:2 || R7 = [I##n--]; EXP (R7, n);
BYTEUNPACK(0)
BYTEUNPACK(1)
BYTEUNPACK(2)
BYTEUNPACK(3)
#define SAA(n) \
SAA (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \
SAA (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \
SAA (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \
SAA (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n);
SAA(0)
SAA(1)
SAA(2)
SAA(3)
#define BYTEOP1P(n) \
R7 = BYTEOP1P (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \
R6 = BYTEOP1P (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \
R5 = BYTEOP1P (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \
R4 = BYTEOP1P (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n);
BYTEOP1P(0)
BYTEOP1P(1)
BYTEOP1P(2)
BYTEOP1P(3)
#define BYTEOP2P(n) \
R7 = BYTEOP2P (R1:0, R3:2) (TL) || R4 = [I##n]; EXP (R4, n); \
R6 = BYTEOP2P (R1:0, R3:2) (TH) || R5 = [I##n ++ M##n]; EXP (R5, n); \
R5 = BYTEOP2P (R1:0, R3:2) (RNDL) || R6 = [I##n++]; EXP (R6, n); \
R4 = BYTEOP2P (R1:0, R3:2) (RNDH) || R7 = [I##n--]; EXP (R7, n);
BYTEOP2P(0)
BYTEOP2P(1)
BYTEOP2P(2)
BYTEOP2P(3)
#define BYTEOP3P(n) \
R7 = BYTEOP3P (R1:0, R3:2) (LO) || R4 = [I##n]; EXP (R4, n); \
R6 = BYTEOP3P (R1:0, R3:2) (HI) || R5 = [I##n ++ M##n]; EXP (R5, n); \
R5 = BYTEOP3P (R1:0, R3:2) (LO) || R6 = [I##n++]; EXP (R6, n); \
R4 = BYTEOP3P (R1:0, R3:2) (HI) || R7 = [I##n--]; EXP (R7, n);
BYTEOP3P(0)
BYTEOP3P(1)
BYTEOP3P(2)
BYTEOP3P(3)
#define BYTEOP16P(n) \
(R7, R6) = BYTEOP16P (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \
(R6, R4) = BYTEOP16P (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \
(R5, R7) = BYTEOP16P (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \
(R4, R6) = BYTEOP16P (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n);
BYTEOP16P(0)
BYTEOP16P(1)
BYTEOP16P(2)
BYTEOP16P(3)
#define BYTEOP16M(n) \
(R7, R5) = BYTEOP16M (R1:0, R3:2) || R4 = [I##n]; EXP (R4, n); \
(R6, R7) = BYTEOP16M (R1:0, R3:2) || R5 = [I##n ++ M##n]; EXP (R5, n); \
(R5, R4) = BYTEOP16M (R1:0, R3:2) || R6 = [I##n++]; EXP (R6, n); \
(R4, R5) = BYTEOP16M (R1:0, R3:2) || R7 = [I##n--]; EXP (R7, n);
BYTEOP16M(0)
BYTEOP16M(1)
BYTEOP16M(2)
BYTEOP16M(3)
pass
|
stsp/binutils-ia16
| 2,019
|
sim/testsuite/bfin/c_ldst_st_p_p.s
|
//Original:/testcases/core/c_ldst_st_p_p/c_ldst_st_p_p.dsp
// Spec Reference: c_ldst st_p_p
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
// initial values p-p
imm32 p5, 0x0a231507;
imm32 p1, 0x1b342618;
imm32 p2, 0x2c453729;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
[ P4 ] = P1;
[ FP ] = P2;
R5 = [ P4 ];
R6 = [ FP ];
CHECKREG r5, 0x1B342618;
CHECKREG r6, 0x2C453729;
[ P4 ] = P2;
[ FP ] = R3;
R5 = [ P4 ];
R6 = [ FP ];
CHECKREG r5, 0x2C453729;
CHECKREG r6, 0x3D56483A;
[ P4 ] = R3;
[ FP ] = P5;
R5 = [ P4 ];
R6 = [ FP ];
CHECKREG r5, 0x3D56483A;
CHECKREG r6, 0x0A231507;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 3,104
|
sim/testsuite/bfin/c_dspldst_st_dr_i.s
|
//Original:/testcases/core/c_dspldst_st_dr_i/c_dspldst_st_dr_i.dsp
// Spec Reference: c_dspldst st_dr_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
[ I0 ] = R0;
[ I1 ] = R1;
[ I2 ] = R2;
[ I3 ] = R3;
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r4, 0x0a234507;
CHECKREG r5, 0x1b345618;
CHECKREG r6, 0x2c456729;
CHECKREG r7, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
[ I0 ] = R1;
[ I1 ] = R2;
[ I2 ] = R3;
[ I3 ] = R4;
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r4, 0x1b345618;
CHECKREG r5, 0x2c456729;
CHECKREG r6, 0x3d56783a;
CHECKREG r7, 0x4e67894b;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
[ I0 ] = R2;
[ I1 ] = R3;
[ I2 ] = R4;
[ I3 ] = R5;
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r4, 0x2c456729;
CHECKREG r5, 0x3d56783a;
CHECKREG r6, 0x4e67894b;
CHECKREG r7, 0x5f789a5c;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
[ I0 ] = R3;
[ I1 ] = R4;
[ I2 ] = R5;
[ I3 ] = R6;
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r4, 0x3d56783a;
CHECKREG r5, 0x4e67894b;
CHECKREG r6, 0x5f789a5c;
CHECKREG r7, 0x6089ab6d;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
[ I0 ] = R4;
[ I1 ] = R5;
[ I2 ] = R6;
[ I3 ] = R7;
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I2 ];
R3 = [ I3 ];
CHECKREG r0, 0x4e67894b;
CHECKREG r1, 0x5f789a5c;
CHECKREG r2, 0x6089ab6d;
CHECKREG r3, 0x719abc7e;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 8,707
|
sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn_s.s
|
//Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = R0.L >>> 10;
R1.L = R1.L >>> 10;
R2.L = R2.L >>> 10;
R3.L = R3.L >>> 10;
R4.L = R4.L >>> 10;
R5.L = R5.L >>> 10;
R6.L = R6.L >>> 10;
R7.L = R7.L >>> 10;
CHECKREG r0, 0x0000FFFF;
CHECKREG r1, 0x0000FFE0;
CHECKREG r2, 0x0000FFE0;
CHECKREG r3, 0x0000FFE0;
CHECKREG r4, 0x0000FFE0;
CHECKREG r5, 0x0000FFE0;
CHECKREG r6, 0x0000FFE0;
CHECKREG r7, 0x0000FFE0;
imm32 r0, 0x02008020;
imm32 r0, 0x02008021;
imm32 r2, 0x02008022;
imm32 r3, 0x02008023;
imm32 r4, 0x02008024;
imm32 r5, 0x02008025;
imm32 r6, 0x02008026;
imm32 r7, 0x02008027;
R0.L = R0.L >>> 11;
R1.L = R1.L >>> 11;
R2.L = R2.L >>> 11;
R3.L = R3.L >>> 11;
R4.L = R4.L >>> 11;
R5.L = R5.L >>> 11;
R6.L = R6.L >>> 11;
R7.L = R7.L >>> 11;
CHECKREG r0, 0x0200FFF0;
CHECKREG r1, 0x0000FFFF;
CHECKREG r2, 0x0200FFF0;
CHECKREG r3, 0x0200FFF0;
CHECKREG r4, 0x0200FFF0;
CHECKREG r5, 0x0200FFF0;
CHECKREG r6, 0x0200FFF0;
CHECKREG r7, 0x0200FFF0;
imm32 r0, 0x00308001;
imm32 r1, 0x00308001;
R2.L = -15;
imm32 r3, 0x00308003;
imm32 r4, 0x00308004;
imm32 r5, 0x00308005;
imm32 r6, 0x00308006;
imm32 r7, 0x00308007;
R0.L = R0.L >>> 12;
R1.L = R1.L >>> 12;
R2.L = R2.L >>> 12;
R3.L = R3.L >>> 12;
R4.L = R4.L >>> 12;
R5.L = R5.L >>> 12;
R6.L = R6.L >>> 12;
R7.L = R7.L >>> 12;
CHECKREG r0, 0x0030FFF8;
CHECKREG r1, 0x0030FFF8;
CHECKREG r2, 0x0200FFFF;
CHECKREG r3, 0x0030FFF8;
CHECKREG r4, 0x0030FFF8;
CHECKREG r5, 0x0030FFF8;
CHECKREG r6, 0x0030FFF8;
CHECKREG r7, 0x0030FFF8;
imm32 r0, 0x00008401;
imm32 r1, 0x00008401;
imm32 r2, 0x00008402;
R3.L = -16;
imm32 r4, 0x00008404;
imm32 r5, 0x00008405;
imm32 r6, 0x00008406;
imm32 r7, 0x00008407;
R0.L = R0.L >>> 3;
R1.L = R1.L >>> 3;
R2.L = R2.L >>> 3;
R3.L = R3.L >>> 3;
R4.L = R4.L >>> 3;
R5.L = R5.L >>> 3;
R6.L = R6.L >>> 3;
R7.L = R7.L >>> 3;
CHECKREG r0, 0x0000F080;
CHECKREG r1, 0x0000F080;
CHECKREG r2, 0x0000F080;
CHECKREG r3, 0x0030FFFE;
CHECKREG r4, 0x0000F080;
CHECKREG r5, 0x0000F080;
CHECKREG r6, 0x0000F080;
CHECKREG r7, 0x0000F080;
// d_lo = ashift (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x05000500;
imm32 r1, 0x85010500;
imm32 r2, 0x85020500;
imm32 r3, 0x85030500;
imm32 r4, 0x85040500;
imm32 r5, 0x85050500;
imm32 r6, 0x85060500;
imm32 r7, 0x85070500;
R0.L = R0.H >>> 10;
R1.L = R1.H >>> 10;
R2.L = R2.H >>> 10;
R3.L = R3.H >>> 10;
R4.L = R4.H >>> 10;
R5.L = R5.H >>> 10;
R6.L = R6.H >>> 10;
R7.L = R7.H >>> 10;
CHECKREG r0, 0x05000001;
CHECKREG r1, 0x8501FFE1;
CHECKREG r2, 0x8502FFE1;
CHECKREG r3, 0x8503FFE1;
CHECKREG r4, 0x8504FFE1;
CHECKREG r5, 0x8505FFE1;
CHECKREG r6, 0x8506FFE1;
CHECKREG r7, 0x8507FFE1;
imm32 r0, 0x80610000;
R1.L = -1;
imm32 r2, 0x80620000;
imm32 r3, 0x80630000;
imm32 r4, 0x80640000;
imm32 r5, 0x80650000;
imm32 r6, 0x80660000;
imm32 r7, 0x80670000;
R0.L = R0.H >>> 11;
R1.L = R1.H >>> 11;
R2.L = R2.H >>> 11;
R3.L = R3.H >>> 11;
R4.L = R4.H >>> 11;
R5.L = R5.H >>> 11;
R6.L = R6.H >>> 11;
R7.L = R7.H >>> 11;
CHECKREG r0, 0x8061FFF0;
CHECKREG r1, 0x8501FFF0;
CHECKREG r2, 0x8062FFF0;
CHECKREG r3, 0x8063FFF0;
CHECKREG r4, 0x8064FFF0;
CHECKREG r5, 0x8065FFF0;
CHECKREG r6, 0x8066FFF0;
CHECKREG r7, 0x8067FFF0;
imm32 r0, 0xa0010070;
imm32 r1, 0xa0010070;
R2.L = -15;
imm32 r3, 0xa0030070;
imm32 r4, 0xa0040070;
imm32 r5, 0xa0050070;
imm32 r6, 0xa0060070;
imm32 r7, 0xa0070070;
R0.L = R0.H >>> 12;
R1.L = R1.H >>> 12;
R2.L = R2.H >>> 12;
R3.L = R3.H >>> 12;
R4.L = R4.H >>> 12;
R5.L = R5.H >>> 12;
R6.L = R6.H >>> 12;
R7.L = R7.H >>> 12;
CHECKREG r0, 0xA001FFFA;
CHECKREG r1, 0xA001FFFA;
CHECKREG r2, 0x8062FFF8;
CHECKREG r3, 0xA003FFFA;
CHECKREG r4, 0xA004FFFA;
CHECKREG r5, 0xA005FFFA;
CHECKREG r6, 0xA006FFFA;
CHECKREG r7, 0xA007FFFA;
imm32 r0, 0xb8010001;
imm32 r1, 0xb8010001;
imm32 r2, 0xb8020002;
R3.L = -16;
imm32 r4, 0xb8040004;
imm32 r5, 0xb8050005;
imm32 r6, 0xb8060006;
imm32 r7, 0xb8070007;
R0.L = R0.H >>> 13;
R1.L = R1.H >>> 13;
R2.L = R2.H >>> 13;
R3.L = R3.H >>> 13;
R4.L = R4.H >>> 13;
R5.L = R5.H >>> 13;
R6.L = R6.H >>> 13;
R7.L = R7.H >>> 13;
CHECKREG r0, 0xB801FFFD;
CHECKREG r1, 0xB801FFFD;
CHECKREG r2, 0xB802FFFD;
CHECKREG r3, 0xA003FFFD;
CHECKREG r4, 0xB804FFFD;
CHECKREG r5, 0xB805FFFD;
CHECKREG r6, 0xB806FFFD;
CHECKREG r7, 0xB807FFFD;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00009001;
imm32 r1, 0x00009001;
imm32 r2, 0x00009002;
imm32 r3, 0x00009003;
imm32 r4, 0x00009000;
imm32 r5, 0x00009005;
imm32 r6, 0x00009006;
imm32 r7, 0x00009007;
R0.H = R0.L >>> 14;
R1.H = R1.L >>> 14;
R2.H = R2.L >>> 14;
R3.H = R3.L >>> 14;
R4.H = R4.L >>> 14;
R5.H = R5.L >>> 14;
R6.H = R6.L >>> 14;
R7.H = R7.L >>> 14;
CHECKREG r0, 0xFFFE9001;
CHECKREG r1, 0xFFFE9001;
CHECKREG r2, 0xFFFE9002;
CHECKREG r3, 0xFFFE9003;
CHECKREG r4, 0xFFFE9000;
CHECKREG r5, 0xFFFE9005;
CHECKREG r6, 0xFFFE9006;
CHECKREG r7, 0xFFFE9007;
imm32 r0, 0xa0008001;
imm32 r1, 0xa0008001;
imm32 r2, 0xa0008002;
imm32 r3, 0xa0008003;
imm32 r4, 0xa0008004;
R5.L = -1;
imm32 r6, 0xa0008006;
imm32 r7, 0xa0008007;
R0.H = R0.L >>> 5;
R1.H = R1.L >>> 5;
R2.H = R2.L >>> 5;
R3.H = R3.L >>> 5;
R4.H = R4.L >>> 5;
R5.H = R5.L >>> 5;
R6.H = R6.L >>> 5;
R7.H = R7.L >>> 5;
CHECKREG r0, 0xFC008001;
CHECKREG r1, 0xFC008001;
CHECKREG r2, 0xFC008002;
CHECKREG r3, 0xFC008003;
CHECKREG r4, 0xFC008004;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFC008006;
CHECKREG r7, 0xFC008007;
imm32 r0, 0x00009b01;
imm32 r1, 0x00009b01;
imm32 r2, 0x00009b02;
imm32 r3, 0x00009b03;
imm32 r4, 0x00009b04;
imm32 r5, 0x00009b05;
R6.L = -15;
imm32 r7, 0x00009007;
R0.H = R0.L >>> 6;
R1.H = R1.L >>> 6;
R2.H = R2.L >>> 6;
R3.H = R3.L >>> 6;
R4.H = R4.L >>> 6;
R5.H = R5.L >>> 6;
R6.H = R6.L >>> 6;
R7.H = R7.L >>> 6;
CHECKREG r0, 0xFE6C9B01;
CHECKREG r1, 0xFE6C9B01;
CHECKREG r2, 0xFE6C9B02;
CHECKREG r3, 0xFE6C9B03;
CHECKREG r4, 0xFE6C9B04;
CHECKREG r5, 0xFE6C9B05;
CHECKREG r6, 0xFFFFFFF1;
CHECKREG r7, 0xFE409007;
imm32 r0, 0x0000a0c1;
imm32 r1, 0x0000a0c1;
imm32 r2, 0x0000a0c2;
imm32 r3, 0x0000a0c3;
imm32 r4, 0x0000a0c4;
imm32 r5, 0x0000a0c5;
imm32 r6, 0x0000a0c6;
R7.L = -16;
R0.H = R0.L >>> 7;
R1.H = R1.L >>> 7;
R2.H = R2.L >>> 7;
R3.H = R3.L >>> 7;
R4.H = R4.L >>> 7;
R5.H = R5.L >>> 7;
R6.H = R6.L >>> 7;
R7.H = R7.L >>> 7;
CHECKREG r0, 0xFF41A0C1;
CHECKREG r1, 0xFF41A0C1;
CHECKREG r2, 0xFF41A0C2;
CHECKREG r3, 0xFF41A0C3;
CHECKREG r4, 0xFF41A0C4;
CHECKREG r5, 0xFF41A0C5;
CHECKREG r6, 0xFF41A0C6;
CHECKREG r7, 0xFFFFFFF0;
imm32 r0, 0x80010d00;
imm32 r1, 0x80010d00;
imm32 r2, 0x80020d00;
imm32 r3, 0x80030d00;
R4.L = -1;
imm32 r5, 0x80050d00;
imm32 r6, 0x80060d00;
imm32 r7, 0x80070d00;
R0.H = R0.H >>> 14;
R1.H = R1.H >>> 14;
R2.H = R2.H >>> 14;
R3.H = R3.H >>> 14;
R4.H = R4.H >>> 14;
R5.H = R5.H >>> 14;
R6.H = R6.H >>> 14;
R7.H = R7.H >>> 14;
CHECKREG r0, 0xFFFE0D00;
CHECKREG r1, 0xFFFE0D00;
CHECKREG r2, 0xFFFE0D00;
CHECKREG r3, 0xFFFE0D00;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFE0D00;
CHECKREG r6, 0xFFFE0D00;
CHECKREG r7, 0xFFFE0D00;
imm32 r0, 0x8d010000;
imm32 r1, 0x8d010000;
imm32 r2, 0x8d020000;
imm32 r3, 0x8d030000;
imm32 r4, 0x8d040000;
R5.L = -1;
imm32 r6, 0x8d060000;
imm32 r7, 0x8d070000;
R0.H = R0.H >>> 15;
R1.H = R1.H >>> 15;
R2.H = R2.H >>> 15;
R3.H = R3.H >>> 15;
R4.H = R4.H >>> 15;
R5.H = R5.H >>> 15;
R6.H = R6.H >>> 15;
R7.H = R7.H >>> 15;
CHECKREG r0, 0xFFFF0000;
CHECKREG r1, 0xFFFF0000;
CHECKREG r2, 0xFFFF0000;
CHECKREG r3, 0xFFFF0000;
CHECKREG r4, 0xFFFF0000;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFF0000;
CHECKREG r7, 0xFFFF0000;
imm32 r0, 0xde010000;
imm32 r1, 0xde010000;
imm32 r2, 0xde020000;
imm32 r3, 0xde030000;
imm32 r4, 0xde040000;
imm32 r5, 0xde050000;
R6.L = -15;
imm32 r7, 0xd0070000;
R0.L = R0.H >>> 10;
R1.L = R1.H >>> 10;
R2.L = R2.H >>> 10;
R3.L = R3.H >>> 10;
R4.L = R4.H >>> 10;
R5.L = R5.H >>> 10;
R6.L = R6.H >>> 10;
R7.L = R7.H >>> 10;
CHECKREG r0, 0xDE01FFF7;
CHECKREG r1, 0xDE01FFF7;
CHECKREG r2, 0xDE02FFF7;
CHECKREG r3, 0xDE03FFF7;
CHECKREG r4, 0xDE04FFF7;
CHECKREG r5, 0xDE05FFF7;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xD007FFF4;
imm32 r0, 0x9f010c00;
imm32 r1, 0xaf010c00;
imm32 r2, 0xbf020c00;
imm32 r3, 0xcf030c00;
imm32 r4, 0xdf040c00;
imm32 r5, 0xef050c00;
imm32 r6, 0xff060c00;
R7.L = -16;
R0.H = R0.H >>> 5;
R1.H = R1.H >>> 5;
R2.H = R2.H >>> 5;
R3.H = R3.H >>> 5;
R4.H = R4.H >>> 5;
R5.H = R5.H >>> 5;
R6.H = R6.H >>> 5;
R7.H = R7.H >>> 5;
CHECKREG r0, 0xFCF80C00;
CHECKREG r1, 0xFD780C00;
CHECKREG r2, 0xFDF80C00;
CHECKREG r3, 0xFE780C00;
CHECKREG r4, 0xFEF80C00;
CHECKREG r5, 0xFF780C00;
CHECKREG r6, 0xFFF80C00;
CHECKREG r7, 0xFE80FFF0;
pass
|
stsp/binutils-ia16
| 4,000
|
sim/testsuite/bfin/c_dsp32alu_mix.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_mix/c_dsp32alu_mix.dsp
// Spec Reference: dsp32alu mix
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// ALU operations include parallel addition, subtraction, MAX, MIN, ABS on 16-bit
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r2, 0x44445555;
imm32 r3, 0x66667777;
imm32 r4, 0x88889999;
imm32 r5, 0xaaaabbbb;
imm32 r6, 0xccccdddd;
imm32 r7, 0xeeeeffff;
imm32 r0, 0x456789ab;
imm32 r1, 0x6789abcd;
// Use only single ALU (ALU0 only), with saturation (S)
R2 = R1 + R0 (NS); /* 0xACF13578 */
R3 = R2 + R0 (NS); /* 0xACF13578 */
CHECKREG r2, 0xACF13578;
CHECKREG r3, 0xF258BF23;
R2 = R1 + R0 (S); /* 0x7FFFFFFF */
R3 = R1 - R0 (NS); /* 0x22222222 */
R4.L = R1.L + R0.L (NS); /* 0x88883578 */
R5.L = R1.L + R0.H (NS); /* 0xAAAAF134 */
R6.L = R1.H + R0.L (NS); /* 0xCCCCF134 */
R7.L = R1.H + R0.H (NS); /* 0xEEEEACF0 */
CHECKREG r2, 0x7FFFFFFF;
CHECKREG r3, 0x22222222;
CHECKREG r4, 0x88883578;
CHECKREG r5, 0xAAAAF134;
CHECKREG r6, 0xCCCCF134;
CHECKREG r7, 0xEEEEACF0;
R4.H = R1.L + R0.L (S); /* 0x80003578 */
R5.H = R1.L + R0.H (S); /* 0xF134F134 */
R6.H = R1.H + R0.L (S); /* 0xF134F134 */
CHECKREG r4, 0x80003578;
CHECKREG r5, 0xF134F134;
CHECKREG r6, 0xF134F134;
R4.H = R1.L + R0.L (S); /* 0x80003578 */
R5.H = R1.L + R0.H (S); /* 0xF134F134 */
R6.H = R1.H + R0.L (S); /* 0xF134F134 */
CHECKREG r4, 0x80003578; /* 0x */
CHECKREG r5, 0xF134F134; /* 0x */
CHECKREG r6, 0xF134F134; /* 0x */
R4.H = R1.L + R0.L (S); /* 0x80003578 */
R5.H = R1.L + R0.H (S); /* 0xF134F134 */
R6.H = R1.H + R0.L (S); /* 0xF134F134 */
R7.H = R1.H + R0.H (S); /* 0x7FFFACF0 */
CHECKREG r4, 0x80003578; /* 0x */
CHECKREG r5, 0xF134F134; /* 0x */
CHECKREG r6, 0xF134F134; /* 0x */
CHECKREG r7, 0x7FFFACF0; /* 0x */
// Dual
R2 = R0 +|+ R1 (SCO); /* 0x80007FFF */
R3 = R0 +|- R1 (S); /* 0x7FFFDDDE */
R4 = R0 -|+ R1 (SCO); /* 0x8000DDDE)*/
R5 = R0 -|- R1 (SCO); /* 0xDDDEDDDE */
CHECKREG r2, 0x80007FFF;
CHECKREG r3, 0x7FFFDDDE;
CHECKREG r4, 0x8000DDDE;
CHECKREG r5, 0xDDDEDDDE;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (SCO); /* 0x */
CHECKREG r2, 0x7FFF8000;
R4 = R0 +|- R1 , R5 = R0 -|+ R1 (CO); /* 0x */
R6 = R0 + R1, R7 = R0 - R1 (S); /* 0x */
CHECKREG r2, 0x7FFF8000;
CHECKREG r3, 0xDDDEDDDE;
CHECKREG r4, 0xACF0DDDE;
CHECKREG r5, 0x3578DDDE;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0xDDDDDDDE;
// Max min abs types
R3 = MAX ( R0 , R1 ); /* 0x6789ABCD */
R4 = MIN ( R0 , R1 ); /* 0x456789AB */
R5 = ABS R0; /* 0x456789AB */
CHECKREG r3, 0x6789ABCD;
CHECKREG r4, 0x456789AB;
CHECKREG r5, 0x456789AB;
R3 = MAX ( R0 , R1 ) (V); /* 0x6789ABCD */
R4 = MIN ( R0 , R1 ) (V); /* 0x456789AB */
R5 = ABS R0 (V); /* 0x45677655 */
CHECKREG r3, 0x6789ABCD;
CHECKREG r4, 0x456789AB;
CHECKREG r5, 0x45677655;
// RND types
R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L;
R3.L = R0 + R1 (RND12); /* 0x */
R4.H = R0 - R1 (RND12); /* 0x */
R5.L = R0 + R1 (RND20); /* 0x */
R6.H = R0 - R1 (RND20); /* 0x */
R7.H = R1 (RND); /* 0x */
CHECKREG r2, 0xBBBCBBBC;
CHECKREG r3, 0x67897FFF;
CHECKREG r4, 0x800089AB;
CHECKREG r5, 0x45670ACF;
CHECKREG r6, 0xFDDEFFFF;
CHECKREG r7, 0x678ADDDE;
R7 = - R0 (V); /* 0x */
CHECKREG r7, 0xBA997655;
// A0 & A1 types
A0 = 0;
A1 = 0;
A0.L = R0.L;
A0.H = R0.H;
A0 = A1;
A0.x = R0.L;
A1.x = R0.L;
R2.L = A0.x; /* 0x */
R3.L = A1.x; /* 0x */
R4 = ( A0 += A1 ); /* 0x */
R5.L = ( A0 += A1 ); /* 0x */
R5.H = ( A0 += A1 ); /* 0x */
CHECKREG r2, 0xBBBCffAB; /* 0x */
CHECKREG r3, 0x6789ffAB; /* 0x */
CHECKREG r4, 0x80000000; /* 0x */
CHECKREG r5, 0x80008000; /* 0x */
A0 += A1;
A0 -= A1;
R6 = A1.L + A1.H, R7 = A0.L + A0.H; /* 0x */
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 1,668
|
sim/testsuite/bfin/c_loopsetup_topbotcntr.s
|
//Original:/proj/frio/dv/testcases/core/c_loopsetup_topbotcntr/c_loopsetup_topbotcntr.dsp
// Spec Reference: loopsetup top bot counter
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x08;
loadsym R6, start1;
loadsym R7, end1;
LT0 = R6;
LB0 = R7;
LC0 = R5;
//start immmediately
start1: R0 += 1;
R1 += -2;
end1: R2 += 3;
R3 += 4;
CHECKREG r0, 0x00000008;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000038;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000040;
CHECKREG r5, 0x00000008;
//CHECKREG r6, 0x00000090;
//CHECKREG r7, 0x00000094;
R0 = 0x05;
R1 = 0x10;
R2 = 0x10;
R3 = 0x10;
R4 = 0x20;
R5 = 0x20;
R6 = 0x30;
R7 = 0x30;
loadsym R1, start2;
R0 = R1;
loadsym R1, end2;
LT1 = R0;
LB1 = R1;
LC1 = R2;
start2: R4 += 1;
R5 += 2;
end2: R6 += -3;
R7 += 4;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000030;
CHECKREG r5, 0x00000040;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000034;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
loadsym R1, start3
r0 = r1;
loadsym r1, end3;
LT0 = R0;
LB0 = R1;
LC0 = R2;
loadsym r3, start4;
loadsym r4, end4;
LT1 = R3;
LB1 = R4;
LC1 = R5;
R0 = 0x10;
R1 = 0x15;
R2 = 0x20;
R3 = 0x26;
R4 = 0x30;
R5 = 0x40 (X);
start3: R0 += 1;
R1 += -2;
start4: R2 += 3;
R3 += 4;
end4: R6 += 5;
end3: R7 += -6;
CHECKREG r0, 0x00000030;
CHECKREG r1, 0xFFFFFFD5;
CHECKREG r2, 0x0000016D;
CHECKREG r3, 0x000001E2;
CHECKREG r4, 0x00000030;
CHECKREG r5, 0x00000040;
CHECKREG r6, 0x0000028B;
CHECKREG r7, 0xFFFFFFB0;
pass
|
stsp/binutils-ia16
| 4,072
|
sim/testsuite/bfin/c_alu2op_log_r_sft.s
|
//Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp
// Spec Reference: alu2op logical right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0.L = 1;
R1 >>= R0;
R2 >>= R0;
R3 >>= R0;
R4 >>= R0;
R5 >>= R0;
R6 >>= R0;
R7 >>= R0;
R4 >>= R0;
R0 >>= R0;
CHECKREG r1, 0x091A2B3C;
CHECKREG r2, 0x11A2B3C4;
CHECKREG r3, 0x1A2B3C4D;
CHECKREG r4, 0x2159E26A;
CHECKREG r5, 0x4B3C4D5E;
CHECKREG r6, 0x53C4D5E6;
CHECKREG r7, 0x5C4D5E6F;
CHECKREG r0, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
R0 >>= R1;
R2 >>= R1;
R3 >>= R1;
R4 >>= R1;
R5 >>= R1;
R6 >>= R1;
R7 >>= R1;
R1 >>= R1;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 >>= R2;
R1 >>= R2;
R3 >>= R2;
R4 >>= R2;
R5 >>= R2;
R6 >>= R2;
R7 >>= R2;
R2 >>= R2;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
R0 >>= R3;
R1 >>= R3;
R2 >>= R3;
R4 >>= R3;
R5 >>= R3;
R6 >>= R3;
R7 >>= R3;
R3 >>= R3;
CHECKREG r0, 0x00;
CHECKREG r1, 0x0;
CHECKREG r2, 0x0;
CHECKREG r3, 0x0;
CHECKREG r4, 0x0;
CHECKREG r5, 0x0;
CHECKREG r6, 0x0;
CHECKREG r7, 0x0;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
R1 >>= R4;
R2 >>= R4;
R3 >>= R4;
R0 >>= R4;
R5 >>= R4;
R6 >>= R4;
R7 >>= R4;
R4 >>= R4;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00002468;
CHECKREG r2, 0x0000468A;
CHECKREG r3, 0x000068AC;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00012CF1;
CHECKREG r6, 0x00014F13;
CHECKREG r7, 0x00017135;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
R0 >>= R5;
R1 >>= R5;
R2 >>= R5;
R3 >>= R5;
R4 >>= R5;
R6 >>= R5;
R7 >>= R5;
R5 >>= R5;
CHECKREG r0, 0x000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x0000;
CHECKREG r3, 0x0000;
CHECKREG r4, 0x0000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x0000;
CHECKREG r7, 0x0000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
R0 >>= R6;
R1 >>= R6;
R2 >>= R6;
R3 >>= R6;
R4 >>= R6;
R5 >>= R6;
R7 >>= R6;
R6 >>= R6;
CHECKREG r0, 0x00000051;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x000000B1;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000095;
CHECKREG r5, 0x00000086;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000078;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
R0 >>= R7;
R1 >>= R7;
R2 >>= R7;
R3 >>= R7;
R4 >>= R7;
R5 >>= R7;
R6 >>= R7;
R7 >>= R7;
CHECKREG r0, 0x00;
CHECKREG r1, 0x00;
CHECKREG r2, 0x00;
CHECKREG r3, 0x00;
CHECKREG r4, 0x00;
CHECKREG r5, 0x00;
CHECKREG r6, 0x00;
CHECKREG r7, 0x00;
pass
|
stsp/binutils-ia16
| 9,855
|
sim/testsuite/bfin/lmu_excpt_prot1.S
|
//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot1/lmu_excpt_prot1.dsp
// Description: LMU protection exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
// Test LMU/CPLB exceptions
// Basic outline:
// Set exception handler
// program CPLB Entries
// Enable CPLB in DMEM_CNTL
// perform access
// verify exception occurred
CHECK_INIT(p5, 0xEFFFFFFC);
A0 = 0;
//-------------------------
// Zero the CPLB Address and Data regs.
LD32(p0, DCPLB_ADDR0);
R0 = 0;
[ P0 ++ ] = R0; // 0
[ P0 ++ ] = R0; // 1
[ P0 ++ ] = R0; // 2
[ P0 ++ ] = R0; // 3
[ P0 ++ ] = R0; // 4
[ P0 ++ ] = R0; // 5
[ P0 ++ ] = R0; // 6
[ P0 ++ ] = R0; // 7
[ P0 ++ ] = R0; // 8
[ P0 ++ ] = R0; // 9
[ P0 ++ ] = R0; // 10
[ P0 ++ ] = R0; // 11
[ P0 ++ ] = R0; // 12
[ P0 ++ ] = R0; // 13
[ P0 ++ ] = R0; // 14
[ P0 ++ ] = R0; // 15
LD32(p0, DCPLB_DATA0);
[ P0 ++ ] = R0; // 0
[ P0 ++ ] = R0; // 1
[ P0 ++ ] = R0; // 2
[ P0 ++ ] = R0; // 3
[ P0 ++ ] = R0; // 4
[ P0 ++ ] = R0; // 5
[ P0 ++ ] = R0; // 6
[ P0 ++ ] = R0; // 7
[ P0 ++ ] = R0; // 8
[ P0 ++ ] = R0; // 9
[ P0 ++ ] = R0; // 10
[ P0 ++ ] = R0; // 11
[ P0 ++ ] = R0; // 12
[ P0 ++ ] = R0; // 13
[ P0 ++ ] = R0; // 14
[ P0 ++ ] = R0; // 15
// Now set the CPLB entries we will need
// Data area for the desired error
WR_MMR(DCPLB_ADDR0, 0x800, p0, r0);
WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0);
WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE, p0, r0);
WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0);
WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0);
WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0);
WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0);
WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0);
WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0);
// CHECKREG segment
WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0);
WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_WT|CPLB_L1_CACHABLE|CPLB_SUPV_WR|CPLB_USER_RW, p0, r0);
// MMR space
WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0);
WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0);
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
WR_MMR_LABEL(EVT15, int_15, p0, r1);
WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
// enable CPLB
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC
// Address for slot 0 accesses
// LD32(p4, 0xEFFFFFF8);
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
// But first raise interrupt 15 so we can do one test
// in supervisor mode.
RAISE 15;
NOP;
RTI;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
int_15:
// Interrupt 15 handler - needed to try supervisor access with exceptions enabled
//-------------------------------------------------------
// Protection violation - Illegal Supervisor Write Access
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
LD32(i1, 0x800);
LD32(r1, 0xDEADBEEF);
LD32(p2, DCPLB_DATA0);
LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR);
LD32(p3, DCPLB_DATA1);
LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR);
X0: //[p1] = r1; // Exception should occur here
A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1
// Now check that handler read correct values
CHECKREG(r4,0x23); // supv and EXCPT_PROT
CHECKREG(r5, 0x800);
CHECKREG(r6, (FAULT_SUPV|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB0));
CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!)
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RTI;
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
User:
NOP;NOP;NOP;NOP;NOP;
//-------------------------------------------------------
// Protection violation - Illegal User Write Access
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
LD32(i1, 0x1000);
LD32(r1, 0xDEADBEEF);
// values to fix up current test
LD32(p2, DCPLB_DATA1);
LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
// values for next test
LD32(p3, DCPLB_DATA2);
LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE);
X1: //[p1] = r1; // Exception should occur here
A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1
// Now check that handler read correct values
CHECKREG(r4,0x23); // supv and EXCPT_PROT
CHECKREG(r5, 0x1000);
CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB1));
CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!)
//-------------------------------------------------------
// Protection violation - Illegal User Read Access
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
LD32(i1, 0x2000);
LD32(r1, 0xDEADBEEF);
LD32(p2, DCPLB_DATA2);
LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RO|CPLB_SUPV_WR);
LD32(p3, DCPLB_DATA3);
LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
X2: //[p1] = r1; // Exception should occur here
A0 = 0 || NOP || R0 = [ I1 ]; // test access with DAG1
// Now check that handler read correct values
CHECKREG(r4,0x23); // supv and EXCPT_PROT
CHECKREG(r5, 0x2000);
CHECKREG(r6, (FAULT_USER|FAULT_READ|FAULT_DAG1 | FAULT_CPLB2));
CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!)
//-------------------------------------------------------
// Protection violation - Illegal Dirty Page Access
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
LD32(i1, 0x3000);
LD32(r1, 0xDEADBEEF);
LD32(p2, DCPLB_DATA3);
LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
LD32(p3, DCPLB_DATA4);
LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DA0ACC|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_SUPV_WR);
X3: //[p1] = r1; // Exception should occur here
A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1
// Now check that handler read correct values
CHECKREG(r4,0x23); // supv and EXCPT_PROT
CHECKREG(r5, 0x3000);
CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB3));
CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!)
//-------------------------------------------------------
// Protection violation - Illegal DAG1 Access
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
LD32(i1, 0x4000);
LD32(r1, 0xDEADBEEF);
LD32(p2, DCPLB_DATA4);
LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
LD32(p3, DCPLB_DATA5);
LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
X4: //[p1] = r1; // Exception should occur here
A0 = 0 || NOP || [ I1 ] = R1; // test access with DAG1
// Now check that handler read correct values
CHECKREG(r4,0x23); // supv and EXCPT_PROT
CHECKREG(r5, 0x4000);
CHECKREG(r6, (FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB4));
CHECKREG_SYM(r7, X4, r0); // RETX should be value of X4 (HARDCODED ADDR!!)
//-------------------------------------------------------
// L1Miss not implemented yet - skip for now....
// //-------------------------------------------------------
// // Protection violation - L1 Miss
// r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0;
//
// LD32(p1, 0x6000);
// LD32(r1, 0xDEADBEEF);
//
// LD32(p2, DCPLB_DATA6);
// LD32(r2, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_L1_CACHABLE|CPLB_USER_RW|CPLB_SUPV_WR);
//
// LD32(p3, DCPLB_DATA7);
// LD32(r3, PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_USER_RW|CPLB_SUPV_WR);
//
//
//X6: //[p1] = r1; // Exception should occur here
// r0 = [p1];
//
//
// // Now check that handler read correct values
// CHECKREG(r4,0x23); // supv and EXCPT_PROT
// CHECKREG(r5, 0x6000);
// // CHECKREG(r6, FAULT_USER|FAULT_WRITE|FAULT_DAG1 | FAULT_CPLB6);
// CHECKREG_SYM(r7, X6, r0); // RETX should be value of X6 (HARDCODED ADDR!!)
//-------------------------------------------------------
dbg_pass;
handler:
// generic protection exception handler
// Inputs:
// p2: addr of CPLB entry to be modified ( current test)
// r2: new data for CPLB entry
//
// p3: addr of CPLB entry to be modified ( next test)
// r3: new data for CPLB entry
//
// Outputs:
// r4: SEQSTAT
// r5: DCPLB_FAULT_ADDR
// r6: DCPLB_STATUS
// r7: RETX (instruction addr where exception occurred)
R4 = SEQSTAT; // Get exception cause
// read data addr which caused exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r5);
RD_MMR(DCPLB_STATUS, p0, r6);
// Reset status regs
WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r0);
WR_MMR(DCPLB_STATUS, 0, p0, r0);
R7 = RETX; // get address of excepting instruction
// modify CPLB to allow access. Main pgm passes in addr and data
[ P2 ] = R2;
// Set up for next test
[ P3 ] = R3;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC;
// return from exception and re-execute offending instruction
RTX;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
.section MEM_0x800,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.section MEM_0x1000,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.section MEM_0x2000,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.section MEM_0x3000,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.section MEM_0x4000,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.section MEM_0x5000,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
// Need a cache miss to test CPLB_L1REF
//.data 0x6000
// .dd 0x00000000
// .dd 0x00000000
// .dd 0x00000000
// .dd 0x00000000
.section MEM_0x7000,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
stsp/binutils-ia16
| 6,136
|
sim/testsuite/bfin/c_dsp32alu_rh_rnd12_p.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_p/c_dsp32alu_rh_rnd12_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x45678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xf4445515;
imm32 r3, 0x46667717;
imm32 r4, 0xe678891b;
imm32 r5, 0x6f89ab1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x8666b777;
R0.H = R0 + R0 (RND12);
R1.H = R0 + R1 (RND12);
R2.H = R0 + R2 (RND12);
R3.H = R0 + R3 (RND12);
R4.H = R0 + R4 (RND12);
R5.H = R0 + R5 (RND12);
R6.H = R0 + R6 (RND12);
R7.H = R0 + R7 (RND12);
CHECKREG r0, 0x7FFF8911;
CHECKREG r1, 0x7fffAB1D;
CHECKREG r2, 0x7fff5515;
CHECKREG r3, 0x7fff7717;
CHECKREG r4, 0x7fff891B;
CHECKREG r5, 0x7fffAB1D;
CHECKREG r6, 0x7fffD515;
CHECKREG r7, 0x6664B777;
imm32 r0, 0xd5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xa4445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5b78891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74e45515;
imm32 r7, 0x86a6b777;
R0.H = R1 + R0 (RND12);
R1.H = R1 + R1 (RND12);
R2.H = R1 + R2 (RND12);
R3.H = R1 + R3 (RND12);
R4.H = R1 + R4 (RND12);
R5.H = R1 + R5 (RND12);
R6.H = R1 + R6 (RND12);
R7.H = R1 + R7 (RND12);
CHECKREG r0, 0xcf138911;
CHECKREG r1, 0x7FFFAB1D;
CHECKREG r2, 0x7fff5515;
CHECKREG r3, 0x7fff7717;
CHECKREG r4, 0x7fff891B;
CHECKREG r5, 0x7fffAB1D;
CHECKREG r6, 0x7fff5515;
CHECKREG r7, 0x6A66B777;
imm32 r0, 0xa5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xb4445515;
imm32 r3, 0x46667717;
imm32 r4, 0xd678891b;
imm32 r5, 0x6e89ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86967777;
R0.H = R2 + R0 (RND12);
R1.H = R2 + R1 (RND12);
R2.H = R2 + R2 (RND12);
R3.H = R2 + R3 (RND12);
R4.H = R2 + R4 (RND12);
R5.H = R2 + R5 (RND12);
R6.H = R2 + R6 (RND12);
R7.H = R2 + R7 (RND12);
CHECKREG r4, 0x8000891B;
CHECKREG r5, 0x8000AB1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x80007777;
CHECKREG r4, 0x8000891B;
CHECKREG r5, 0x8000AB1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x80007777;
imm32 r0, 0x35678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0xeab9ab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x866e777f;
R0.H = R3 + R0 (RND12);
R1.H = R3 + R1 (RND12);
R2.H = R3 + R2 (RND12);
R3.H = R3 + R3 (RND12);
R4.H = R3 + R4 (RND12);
R5.H = R3 + R5 (RND12);
R6.H = R3 + R6 (RND12);
R7.H = R3 + R7 (RND12);
CHECKREG r0, 0x7FFF8911;
CHECKREG r1, 0x7FFFAB1D;
CHECKREG r2, 0x7FFF5515;
CHECKREG r3, 0x7FFF7717;
CHECKREG r4, 0x7fff891B;
CHECKREG r5, 0x7fffAB1D;
CHECKREG r6, 0x7fff5515;
CHECKREG r7, 0x66df777F;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0xd6667717;
imm32 r4, 0x5675891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xa4465515;
imm32 r7, 0x8b66e777;
R0.H = R4 + R0 (RND12);
R1.H = R4 + R1 (RND12);
R2.H = R4 + R2 (RND12);
R3.H = R4 + R3 (RND12);
R4.H = R4 + R4 (RND12);
R5.H = R4 + R5 (RND12);
R6.H = R4 + R6 (RND12);
R7.H = R4 + R7 (RND12);
CHECKREG r0, 0x7FFF8911;
CHECKREG r1, 0x7FFFAB1D;
CHECKREG r2, 0x7FFF5515;
CHECKREG r3, 0x7FFF7717;
CHECKREG r4, 0x7FFF891B;
CHECKREG r5, 0x7fffAB1D;
CHECKREG r6, 0x7fff5515;
CHECKREG r7, 0x7fffE777;
imm32 r0, 0x35678111;
imm32 r1, 0x2789a21d;
imm32 r2, 0x3e445535;
imm32 r3, 0x46667757;
imm32 r4, 0xe6f8891b;
imm32 r5, 0x6789db7d;
imm32 r6, 0xf44a5595;
imm32 r7, 0x866b7770;
R0.H = R5 + R0 (RND12);
R1.H = R5 + R1 (RND12);
R2.H = R5 + R2 (RND12);
R3.H = R5 + R3 (RND12);
R4.H = R5 + R4 (RND12);
R5.H = R5 + R5 (RND12);
R6.H = R5 + R6 (RND12);
R7.H = R5 + R7 (RND12);
CHECKREG r0, 0x7FFF8111;
CHECKREG r1, 0x7FFFA21D;
CHECKREG r2, 0x7fff5535;
CHECKREG r3, 0x7FFF7757;
CHECKREG r4, 0x7FFF891B;
CHECKREG r5, 0x7FFFDB7D;
CHECKREG r6, 0x7fff5595;
CHECKREG r7, 0x66b57770;
imm32 r0, 0xb5678911;
imm32 r1, 0xc789ab1d;
imm32 r2, 0x3ab45515;
imm32 r3, 0x466b7717;
imm32 r4, 0x4678e91b;
imm32 r5, 0x6789af1d;
imm32 r6, 0xf4445515;
imm32 r7, 0x86e6f777;
R0.H = R6 + R0 (RND12);
R1.H = R6 + R1 (RND12);
R2.H = R6 + R2 (RND12);
R3.H = R6 + R3 (RND12);
R4.H = R6 + R4 (RND12);
R5.H = R6 + R5 (RND12);
R6.H = R6 + R6 (RND12);
R7.H = R6 + R7 (RND12);
CHECKREG r0, 0x80008911;
CHECKREG r1, 0x8000AB1D;
CHECKREG r2, 0x7fff5515;
CHECKREG r3, 0x7FFF7717;
CHECKREG r4, 0x7FFFE91B;
CHECKREG r5, 0x7FFFAF1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x8000F777;
imm32 r0, 0xab678021;
imm32 r1, 0x2c89a33d;
imm32 r2, 0x34d45575;
imm32 r3, 0x466e7797;
imm32 r4, 0x567f89fb;
imm32 r5, 0x6789abdd;
imm32 r6, 0x744e5515;
imm32 r7, 0x8666ab87;
R0.H = R7 + R0 (RND12);
R1.H = R7 + R1 (RND12);
R2.H = R7 + R2 (RND12);
R3.H = R7 + R3 (RND12);
R4.H = R7 + R4 (RND12);
R5.H = R7 + R5 (RND12);
R6.H = R7 + R6 (RND12);
R7.H = R7 + R7 (RND12);
CHECKREG r0, 0x80008021;
CHECKREG r1, 0x8000A33D;
CHECKREG r2, 0x80005575;
CHECKREG r3, 0x80007797;
CHECKREG r4, 0x800089FB;
CHECKREG r5, 0x8000ABDD;
CHECKREG r6, 0xab505515;
CHECKREG r7, 0x8000AB87;
imm32 r0, 0x15678901;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445535;
imm32 r3, 0x46667747;
imm32 r4, 0x56788915;
imm32 r5, 0x6789ab6d;
imm32 r6, 0x74445518;
imm32 r7, 0x86667797;
R6.H = R2 + R3 (RND12);
R1.H = R4 + R5 (RND12);
R5.H = R7 + R2 (RND12);
R3.H = R0 + R0 (RND12);
R0.H = R3 + R4 (RND12);
R2.H = R5 + R7 (RND12);
R7.H = R6 + R7 (RND12);
R4.H = R1 + R6 (RND12);
CHECKREG r0, 0x7fff8901;
CHECKREG r1, 0x7FFFAB2D;
CHECKREG r2, 0x80005535;
CHECKREG r3, 0x7FFF7747;
CHECKREG r4, 0x7fff8915;
CHECKREG r5, 0x8000AB6D;
CHECKREG r6, 0x7FFF5518;
CHECKREG r7, 0x665D7797;
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545565;
imm32 r3, 0x4d6677b7;
imm32 r4, 0x567889db;
imm32 r5, 0x67beab1d;
imm32 r6, 0x7b445595;
imm32 r7, 0x86d6e707;
R3.H = R4 + R0 (RND12);
R1.H = R6 + R3 (RND12);
R4.H = R3 + R2 (RND12);
R6.H = R7 + R1 (RND12);
R2.H = R5 + R4 (RND12);
R7.H = R2 + R7 (RND12);
R0.H = R1 + R6 (RND12);
R5.H = R0 + R5 (RND12);
CHECKREG r0, 0x7fff8911;
CHECKREG r1, 0x7fffAB1D;
CHECKREG r2, 0x7FFF5565;
CHECKREG r3, 0x7FFF77B7;
CHECKREG r4, 0x7fff89DB;
CHECKREG r5, 0x7FFFAB1D;
CHECKREG r6, 0x6d695595;
CHECKREG r7, 0x6D64E707;
pass
|
stsp/binutils-ia16
| 1,849
|
sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s
|
//Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp
// Spec Reference: compi2opd dregs = imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
R4 = 4;
R5 = 5;
R6 = 6;
R7 = 7;
CHECKREG r0, 0;
CHECKREG r1, 1;
CHECKREG r2, 2;
CHECKREG r3, 3;
CHECKREG r4, 4;
CHECKREG r5, 5;
CHECKREG r6, 6;
CHECKREG r7, 7;
R0 = 8;
R1 = 9;
R2 = 10;
R3 = 11;
R4 = 12;
R5 = 13;
R6 = 14;
R7 = 15;
CHECKREG r0, 8;
CHECKREG r1, 9;
CHECKREG r2, 10;
CHECKREG r3, 11;
CHECKREG r4, 12;
CHECKREG r5, 13;
CHECKREG r6, 14;
CHECKREG r7, 15;
R0 = 16;
R1 = 17;
R2 = 18;
R3 = 19;
R4 = 20;
R5 = 21;
R6 = 22;
R7 = 23;
CHECKREG r0, 16;
CHECKREG r1, 17;
CHECKREG r2, 18;
CHECKREG r3, 19;
CHECKREG r4, 20;
CHECKREG r5, 21;
CHECKREG r6, 22;
CHECKREG r7, 23;
R0 = 24;
R1 = 25;
R2 = 26;
R3 = 27;
R4 = 28;
R5 = 29;
R6 = 30;
R7 = 31;
CHECKREG r0, 24;
CHECKREG r1, 25;
CHECKREG r2, 26;
CHECKREG r3, 27;
CHECKREG r4, 28;
CHECKREG r5, 29;
CHECKREG r6, 30;
CHECKREG r7, 31;
R0 = 32;
R1 = 33;
R2 = 34;
R3 = 35;
R4 = 36;
R5 = 37;
R6 = 38;
R7 = 39;
CHECKREG r0, 32;
CHECKREG r1, 33;
CHECKREG r2, 34;
CHECKREG r3, 35;
CHECKREG r4, 36;
CHECKREG r5, 37;
CHECKREG r6, 38;
CHECKREG r7, 39;
R0 = 40;
R1 = 41;
R2 = 42;
R3 = 43;
R4 = 44;
R5 = 45;
R6 = 46;
R7 = 47;
CHECKREG r0, 40;
CHECKREG r1, 41;
CHECKREG r2, 42;
CHECKREG r3, 43;
CHECKREG r4, 44;
CHECKREG r5, 45;
CHECKREG r6, 46;
CHECKREG r7, 47;
R0 = 48;
R1 = 49;
R2 = 50;
R3 = 51;
R4 = 52;
R5 = 53;
R6 = 54;
R7 = 55;
CHECKREG r0, 48;
CHECKREG r1, 49;
CHECKREG r2, 50;
CHECKREG r3, 51;
CHECKREG r4, 52;
CHECKREG r5, 53;
CHECKREG r6, 54;
CHECKREG r7, 55;
R0 = 56;
R1 = 57;
R2 = 58;
R3 = 59;
R4 = 60;
R5 = 61;
R6 = 62;
R7 = 63;
CHECKREG r0, 56;
CHECKREG r1, 57;
CHECKREG r2, 58;
CHECKREG r3, 59;
CHECKREG r4, 60;
CHECKREG r5, 61;
CHECKREG r6, 62;
CHECKREG r7, 63;
pass
|
stsp/binutils-ia16
| 3,831
|
sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s
|
//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_shadd_1_2/c_ptr2op_pr_shadd_1_2.dsp
// Spec Reference: ptr2op shadd preg, pregs, 1 (2)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// check p-reg to p-reg move
imm32 p1, 0xf0921203;
imm32 p2, 0xbe041305;
imm32 p3, 0xd0d61407;
imm32 p4, 0xa00a1089;
imm32 p5, 0x400a300b;
imm32 sp, 0xe07c180d;
imm32 fp, 0x206e109f;
P1 = ( P1 + P1 ) << 2;
P2 = ( P2 + P1 ) << 2;
P3 = ( P3 + P1 ) << 2;
P4 = ( P4 + P1 ) << 1;
P5 = ( P5 + P1 ) << 2;
SP = ( SP + P1 ) << 2;
FP = ( FP + P1 ) << 1;
CHECKREG p1, 0x84909018;
CHECKREG p2, 0x0A528C74;
CHECKREG p3, 0x559A907C;
CHECKREG p4, 0x49354142;
CHECKREG p5, 0x126B008C;
CHECKREG sp, 0x9432A094;
CHECKREG fp, 0x49FD416E;
imm32 p1, 0x50021003;
imm32 p2, 0x26041005;
imm32 p3, 0x60761007;
imm32 p4, 0x20081009;
imm32 p5, 0xf00a900b;
imm32 sp, 0xb00c1a0d;
imm32 fp, 0x200e10bf;
P1 = ( P1 + P2 ) << 1;
P2 = ( P2 + P2 ) << 2;
P3 = ( P3 + P2 ) << 1;
P4 = ( P4 + P2 ) << 2;
P5 = ( P5 + P2 ) << 2;
SP = ( SP + P2 ) << 1;
FP = ( FP + P2 ) << 2;
CHECKREG p1, 0xEC0C4010;
CHECKREG p2, 0x30208028;
CHECKREG p3, 0x212D205E;
CHECKREG p4, 0x40A240C4;
CHECKREG p5, 0x80AC40CC;
CHECKREG sp, 0xC059346A;
CHECKREG fp, 0x40BA439C;
imm32 p1, 0x30026003;
imm32 p2, 0x40051005;
imm32 p3, 0x20e65057;
imm32 p4, 0x2d081089;
imm32 p5, 0xf00ab07b;
imm32 sp, 0x200c1b0d;
imm32 fp, 0x200e100f;
P1 = ( P1 + P3 ) << 2;
P2 = ( P2 + P3 ) << 1;
P3 = ( P3 + P3 ) << 2;
P4 = ( P4 + P3 ) << 2;
P5 = ( P5 + P3 ) << 2;
SP = ( SP + P3 ) << 1;
FP = ( FP + P3 ) << 2;
CHECKREG p1, 0x43A2C168;
CHECKREG p2, 0xC1D6C0B8;
CHECKREG p3, 0x073282B8;
CHECKREG p4, 0xD0EA4D04;
CHECKREG p5, 0xDCF4CCCC;
CHECKREG sp, 0x4E7D3B8A;
CHECKREG fp, 0x9D024B1C;
imm32 p1, 0xa0021003;
imm32 p2, 0x2c041005;
imm32 p3, 0x40b61007;
imm32 p4, 0x250d1009;
imm32 p5, 0x260ae00b;
imm32 sp, 0x700c110d;
imm32 fp, 0x900e104f;
P1 = ( P1 + P4 ) << 1;
P2 = ( P2 + P4 ) << 2;
P3 = ( P3 + P4 ) << 2;
P4 = ( P4 + P4 ) << 2;
P5 = ( P5 + P4 ) << 1;
SP = ( SP + P4 ) << 2;
FP = ( FP + P4 ) << 2;
CHECKREG p1, 0x8A1E4018;
CHECKREG p2, 0x44448038;
CHECKREG p3, 0x970C8040;
CHECKREG p4, 0x28688048;
CHECKREG p5, 0x9CE6C0A6;
CHECKREG sp, 0x61D24554;
CHECKREG fp, 0xE1DA425C;
imm32 p1, 0xae021003;
imm32 p2, 0x22041705;
imm32 p3, 0x20361487;
imm32 p4, 0x90743009;
imm32 p5, 0xa60aa00b;
imm32 sp, 0xb00c1b0d;
imm32 fp, 0x200e10cf;
P1 = ( P1 + P5 ) << 2;
P2 = ( P2 + P5 ) << 2;
P3 = ( P3 + P5 ) << 2;
P4 = ( P4 + P5 ) << 2;
P5 = ( P5 + P5 ) << 1;
SP = ( SP + P5 ) << 2;
FP = ( FP + P5 ) << 2;
CHECKREG p1, 0x5032C038;
CHECKREG p2, 0x203ADC40;
CHECKREG p3, 0x1902D248;
CHECKREG p4, 0xD9FB4050;
CHECKREG p5, 0x982A802C;
CHECKREG sp, 0x20DA6CE4;
CHECKREG fp, 0xE0E243EC;
imm32 p1, 0x50021003;
imm32 p2, 0x62041005;
imm32 p3, 0x70e61007;
imm32 p4, 0x290f1009;
imm32 p5, 0x700ab00b;
imm32 sp, 0x2a0c1d0d;
imm32 fp, 0xb00e1e0f;
P1 = ( P1 + SP ) << 2;
P2 = ( P2 + SP ) << 1;
P3 = ( P3 + SP ) << 2;
P4 = ( P4 + SP ) << 2;
P5 = ( P5 + SP ) << 2;
SP = ( SP + SP ) << 1;
FP = ( FP + SP ) << 2;
CHECKREG p1, 0xE838B440;
CHECKREG p2, 0x18205A24;
CHECKREG p3, 0x6BC8B450;
CHECKREG p4, 0x4C6CB458;
CHECKREG p5, 0x685B3460;
CHECKREG sp, 0xA8307434;
CHECKREG fp, 0x60FA490C;
imm32 p1, 0x32002003;
imm32 p2, 0x24004005;
imm32 p3, 0xe0506007;
imm32 p4, 0xd0068009;
imm32 p5, 0x230ae00b;
imm32 sp, 0x205c1f0d;
imm32 fp, 0x200e10bf;
P1 = ( P1 + FP ) << 2;
P2 = ( P2 + FP ) << 1;
P3 = ( P3 + FP ) << 2;
P4 = ( P4 + FP ) << 2;
P5 = ( P5 + FP ) << 2;
SP = ( SP + FP ) << 2;
FP = ( FP + FP ) << 2;
CHECKREG p1, 0x4838C308;
CHECKREG p2, 0x881CA188;
CHECKREG p3, 0x0179C318;
CHECKREG p4, 0xC0524320;
CHECKREG p5, 0x0C63C328;
CHECKREG sp, 0x01A8BF30;
CHECKREG fp, 0x007085F8;
pass
|
stsp/binutils-ia16
| 1,202
|
sim/testsuite/bfin/m17.s
|
// Test various moves to single register
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7fffffff
// load r1=0x00ffffff
// load r2=0xf0000000
// load r3=0x0000007f
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
// extract only to high register
R5 = 0;
R4 = 0;
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R5 = A1;
DBGA ( R4.L , 0x0000 );
DBGA ( R4.H , 0x0000 );
DBGA ( R5.L , 0xffff );
DBGA ( R5.H , 0x7fff );
// extract only to low register
R5 = 0;
R4 = 0;
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R4 = A0;
DBGA ( R4.L , 0xffff );
DBGA ( R4.H , 0x7fff );
DBGA ( R5.L , 0x0000 );
DBGA ( R5.H , 0x0000 );
// extract only to high reg
R5 = 0;
R4 = 0;
A1 = A0 = 0;
R5 = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H;
DBGA ( R4.L , 0x0000 );
DBGA ( R4.H , 0x0000 );
DBGA ( R5.L , 0x0002 );
DBGA ( R5.H , 0x7ffe );
// extract only to low reg
R5 = 0;
R4 = 0;
A1 = A0 = 0;
A1 += R0.H * R0.H, R4 = ( A0 += R0.H * R0.H );
DBGA ( R4.L , 0x0002 );
DBGA ( R4.H , 0x7ffe );
DBGA ( R5.L , 0x0000 );
DBGA ( R5.H , 0x0000 );
pass
.data
data0:
.dw 0xffff
.dw 0x7fff
.dw 0xffff
.dw 0x00ff
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
|
stsp/binutils-ia16
| 3,363
|
sim/testsuite/bfin/c_dsp32shift_lmix.s
|
//Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp
// Spec Reference: dsp32shift lshift: mix
# mach: bfin
.include "testutils.inc"
start
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// lshift : positive data, count (+)=left (half reg)
imm32 r0, 0x00010001;
imm32 r1, 1;
imm32 r2, 0x00020002;
imm32 r3, 2;
R4.H = LSHIFT R0.H BY R1.L;
R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
R5.H = LSHIFT R2.H BY R3.L;
R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
CHECKREG r4, 0x00020002;
CHECKREG r5, 0x00080008;
CHECKREG r6, 0x00020002;
CHECKREG r7, 0x00080008;
// lshift : (full reg)
imm32 r1, 3;
imm32 r3, 4;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */
R7 = LSHIFT R2 BY R3.L;
CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
CHECKREG r7, 0x00200020;
A0 = 0;
A0.L = R0.L;
A0.H = R0.H;
A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */
R5 = A0.w; /* r5 = 0x00080008 */
CHECKREG r5, 0x00080008;
imm32 r4, 0x30000003;
imm32 r1, 1;
R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 */
imm32 r1, 2;
R7 = LSHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
CHECKREG r6, 0x60000006;
CHECKREG r7, 0xc000000c;
// lshift : count (-)=right (half reg)
imm32 r0, 0x10001000;
imm32 r1, -1;
imm32 r2, 0x10001000;
imm32 r3, -2;
R4.H = LSHIFT R0.H BY R1.L;
R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x08000800 */
R5.H = LSHIFT R2.H BY R3.L;
R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x04000400 */
R6 = LSHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */
R7 = LSHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */
CHECKREG r4, 0x08000800;
CHECKREG r5, 0x04000400;
CHECKREG r6, 0x08000800;
CHECKREG r7, 0x04000400;
// lshift : (full reg)
imm32 r1, -3;
imm32 r3, -4;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x02000200 */
R7 = LSHIFT R2 BY R3.L; /* r7 = 0x01000100 */
CHECKREG r6, 0x02000200;
CHECKREG r7, 0x01000100;
// NEGATIVE
// lshift : NEGATIVE data, count (+)=left (half reg)
imm32 r0, 0xc00f800f;
imm32 r1, 1;
imm32 r2, 0xe00fe00f;
imm32 r3, 2;
R4.H = LSHIFT R0.H BY R1.L;
R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x801e001e */
R5.H = LSHIFT R2.H BY R3.L;
R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x803c803c */
CHECKREG r4, 0x801e001e;
CHECKREG r5, 0x803c803c;
imm32 r0, 0xc80fe00f;
imm32 r2, 0xe40fe00f;
imm32 r1, 4;
imm32 r3, 5;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
CHECKREG r6, 0x80fe00f0;
CHECKREG r7, 0x81fc01e0;
imm32 r0, 0xf80fe00f;
imm32 r2, 0xfc0fe00f;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
CHECKREG r6, 0x80fe00f0;
CHECKREG r7, 0x81fc01e0;
// lshift : NEGATIVE data, count (-)=right (half reg) Working ok
imm32 r0, 0x80f080f0;
imm32 r1, -1;
imm32 r2, 0x80f080f0;
imm32 r3, -2;
R4.H = LSHIFT R0.H BY R1.L;
R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x40784078 */
R5.H = LSHIFT R2.H BY R3.L;
R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x203c203c */
CHECKREG r4, 0x40784078;
CHECKREG r5, 0x203c203c;
R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x40784078 */
R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x203c203c */
CHECKREG r6, 0x40784078;
CHECKREG r7, 0x203c203c;
// lshift : (full reg)
imm32 r1, -3;
imm32 r3, -4;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x101e101e */
R7 = LSHIFT R2 BY R3.L; /* r7 = 0x080f080f */
CHECKREG r6, 0x101e101e;
CHECKREG r7, 0x080f080f;
pass
|
stsp/binutils-ia16
| 3,444
|
sim/testsuite/bfin/cec-multi-pending.S
|
# Blackfin testcase for multiple pending IVGs vs masked state
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym;
[P5 + 4 * \lvl\()] = R1;
.endm
.macro check_cec mmr:req, valid:req
imm32 P3, \mmr;
R0 = [P3];
R1 = ~0x1f;
R0 = R0 & R1;
imm32 R1, \valid;
CC = R1 == R0;
IF CC JUMP 1f;
dbg_fail
1:
.endm
.macro delay cnt:req
imm32 P2, \cnt
LSETUP (1f, 1f) LC1 = P2;
1: mnop;
.endm
start
# First mark all EVTs as fails (they shouldn't be activated)
imm32 P5, EVT0;
P1 = P5;
loadsym R1, fail_lvl
imm32 P2, 16
LSETUP (1f, 1f) LC0 = P2;
1: [P1++] = R1;
# Lower ourselves to EVT15
set_evt 15, evt15;
R7 = 0 (x);
BITSET (R7, 15);
sti R7;
loadsym R1, wait;
RETI = R1;
RAISE 15;
RTI;
wait:
jump wait;
evt15:
# We shouldn't come back here
set_evt 15, fail_lvl;
# Activate interrupt nesting early
[--SP] = RETI;
# Raise some higher levels, but they should be masked and so
# they should never be activated ...
RAISE 6;
RAISE 5;
RAISE 9;
RAISE 12;
# Only IVG15 should be pending
check_cec IPEND, (1<<15);
# But all should be latched
check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<12);
# Delay a little in case a higher level wrongly activates
delay 30
# If we're still here, things are still good. So let's
# transition up *slightly*, but not to the highest latched.
set_evt 12, evt12;
cli R7;
BITSET (R7, 12);
sti R7;
# Let CEC raise us to IVG12
delay 30
# CEC should have been faster than this ...
dbg_fail
evt12:
# We shouldn't come back here
set_evt 12, fail_lvl;
# Raise some higher levels, but they should be masked and so
# they should never be activated ...
RAISE 11;
# Both IVG15 and IVG12 should be pending
check_cec IPEND, (1<<15) | (1<<12);
# But all should be latched
check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<11);
# Activate interrupt nesting a little later
[--SP] = RETI;
# Still here, so unmask a higher IVG again to move up
set_evt 9, evt9;
cli R7;
BITSET (R7, 9);
sti R7;
delay 30
# CEC should have been faster than this ...
dbg_fail
evt9:
# We shouldn't come back here
set_evt 9, fail_lvl;
# IVG9 should also be pending now
check_cec IPEND, (1<<15) | (1<<12) | (1<<9);
# But all should be latched
check_cec ILAT, (1<<5) | (1<<6) | (1<<11);
# Unmask the next level, but IPEND[4] is set, so we should stay here
set_evt 6, evt6;
cli R7;
BITSET (R7, 6);
sti R7;
# Delay a little in case a higher level wrongly activates
delay 30
# Good, now unmask things globally
[--SP] = RETI;
delay 30
# CEC should have been faster than this ...
dbg_fail
evt6:
# We shouldn't come back here
set_evt 6, fail_lvl;
# IVG6 should also be pending now
check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6);
# But all should be latched
check_cec ILAT, (1<<5) | (1<<11);
# Activate interrupt nesting a little later
[--SP] = RETI;
# Unmask the next level, but do it via IMASK
set_evt 5, evt5;
imm32 P2, IMASK;
R7 = [P2];
BITSET (R7, 5);
[P2] = R7;
delay 30
# CEC should have been faster than this ...
dbg_fail
evt5:
# We shouldn't come back here
set_evt 5, fail_lvl;
# IVG5 should also be pending now
check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6) | (1<<5);
# But all should be latched
check_cec ILAT, (1<<11);
# All good!
dbg_pass;
fail_lvl:
dbg_fail;
|
stsp/binutils-ia16
| 1,403
|
sim/testsuite/bfin/m7.s
|
// Test result extraction of mac instructions.
// Test basic edge values
// UNSIGNED FRACTIONAL mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000001
// load r1=0x80007fff
// load r2=0xf000ffff
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// extraction with no saturation (truncate)
// 0x8000 * 0x7fff = 0x003fff8000 -> 0x3fff
A1 = A0 = 0;
R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (TFU);
DBGA ( R5.L , 0x3fff );
DBGA ( R5.H , 0x3fff );
// extraction with no saturation (round)
// 0x8000 * 0x7fff = 0x003fff8000 -> 0x4000
A1 = A0 = 0;
R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (FU);
DBGA ( R5.L , 0x4000 );
DBGA ( R5.H , 0x4000 );
// extraction with no saturation
// 0xffff * 0xffff = 0x00fffe0001 -> 0xfffe
A1 = A0 = 0;
R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU);
DBGA ( R5.L , 0xfffe );
DBGA ( R5.H , 0xfffe );
// extraction with saturation
//0x7ffffe0001 -> 0xffff
A1 = A0 = 0;
A1.x = R3.L;
A0.x = R3.L;
R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU);
DBGA ( R5.L , 0xffff );
DBGA ( R5.H , 0xffff );
pass
.data
data0:
.dw 0x0001
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0xffff
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
stsp/binutils-ia16
| 9,487
|
sim/testsuite/bfin/c_ldstii_ld_dr_xh.s
|
//Original:testcases/core/c_ldstii_ld_dr_xh/c_ldstii_ld_dr_xh.dsp
// Spec Reference: c_ldstii load dreg xh
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x04;
loadsym i1, DATA_ADDR_3, 0x04;
loadsym p4, DATA_ADDR_1, 0x00;
loadsym p5, DATA_ADDR_2, 0x00;
loadsym fp, DATA_ADDR_3, 0x00;
loadsym i3, DATA_ADDR_4, 0x00;
P3 = I1; SP = I3;
R0 = W [ P1 + 0 ] (X);
R1 = W [ P1 + 4 ] (X);
R2 = W [ P1 + 8 ] (X);
R3 = W [ P1 + 12 ] (X);
R4 = W [ P1 + 16 ] (X);
R5 = W [ P1 + 20 ] (X);
R6 = W [ P1 + 24 ] (X);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00000607;
CHECKREG r2, 0x00000A0B;
CHECKREG r3, 0x00000E0F;
CHECKREG r4, 0x00001213;
CHECKREG r5, 0x00001617;
CHECKREG r6, 0x00001A1B;
R0 = W [ P2 + 28 ] (X);
R1 = W [ P2 + 32 ] (X);
R2 = W [ P2 + 36 ] (X);
R3 = W [ P2 + 40 ] (X);
R4 = W [ P2 + 44 ] (X);
R5 = W [ P2 + 48 ] (X);
R6 = W [ P2 + 52 ] (X);
CHECKREG r0, 0xFFFF9394;
CHECKREG r1, 0xFFFF9798;
CHECKREG r2, 0xFFFFA2A3;
CHECKREG r3, 0xFFFFA7A8;
CHECKREG r4, 0xFFFFB1B2;
CHECKREG r5, 0xFFFFB5B6;
CHECKREG r6, 0xFFFFB9C0;
R0 = W [ P3 + 56 ] (X);
R1 = W [ P3 + 60 ] (X);
R2 = W [ P3 + 64 ] (X);
R3 = W [ P3 + 60 ] (X);
R4 = W [ P3 + 56 ] (X);
R5 = W [ P3 + 52 ] (X);
R6 = W [ P3 + 48 ] (X);
CHECKREG r0, 0xFFFF99EA;
CHECKREG r1, 0xFFFF99EA;
CHECKREG r2, 0xFFFF99EA;
CHECKREG r3, 0xFFFF99EA;
CHECKREG r4, 0xFFFF99EA;
CHECKREG r5, 0xFFFFE5E6;
CHECKREG r6, 0xFFFFE1E2;
R0 = W [ P4 + 44 ] (X);
R1 = W [ P4 + 40 ] (X);
R2 = W [ P4 + 36 ] (X);
R3 = W [ P4 + 32 ] (X);
R4 = W [ P4 + 28 ] (X);
R5 = W [ P4 + 24 ] (X);
R6 = W [ P4 + 20 ] (X);
CHECKREG r0, 0x00007677;
CHECKREG r1, 0x00007273;
CHECKREG r2, 0x00007788;
CHECKREG r3, 0x00003344;
CHECKREG r4, 0x00001E1F;
CHECKREG r5, 0x00001A1B;
CHECKREG r6, 0x00001617;
R0 = W [ P5 + 16 ] (X);
R1 = W [ P5 + 12 ] (X);
R2 = W [ P5 + 8 ] (X);
R3 = W [ P5 + 4 ] (X);
R4 = W [ P5 + 0 ] (X);
R5 = W [ P5 + 4 ] (X);
R6 = W [ P5 + 8 ] (X);
CHECKREG r0, 0x00003233;
CHECKREG r1, 0x00002E2F;
CHECKREG r2, 0x00002A2B;
CHECKREG r3, 0x00002627;
CHECKREG r4, 0x00002223;
CHECKREG r5, 0x00002627;
CHECKREG r6, 0x00002A2B;
R0 = W [ FP + 12 ] (X);
R1 = W [ FP + 16 ] (X);
R2 = W [ FP + 20 ] (X);
R3 = W [ FP + 24 ] (X);
R4 = W [ FP + 28 ] (X);
R5 = W [ FP + 32 ] (X);
R6 = W [ FP + 36 ] (X);
CHECKREG r0, 0x00004E4F;
CHECKREG r1, 0x00005253;
CHECKREG r2, 0x00005657;
CHECKREG r3, 0x00005A5B;
CHECKREG r4, 0xFFFFC7C8;
CHECKREG r5, 0xFFFFCBCD;
CHECKREG r6, 0xFFFFD1D2;
R0 = W [ SP + 40 ] (X);
R1 = W [ SP + 44 ] (X);
R2 = W [ SP + 48 ] (X);
R3 = W [ SP + 52 ] (X);
R4 = W [ SP + 56 ] (X);
R5 = W [ SP + 60 ] (X);
R6 = W [ SP + 64 ] (X);
CHECKREG r0, 0xFFFFF9FA;
CHECKREG r1, 0xFFFFFDFE;
CHECKREG r2, 0x00000102;
CHECKREG r3, 0x00000506;
CHECKREG r4, 0x0000090A;
CHECKREG r5, 0xFFFFAD0E;
CHECKREG r6, 0xFFFFAD01;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 2,885
|
sim/testsuite/bfin/c_loopsetup_nested_top.s
|
//Original:/testcases/core/c_loopsetup_nested_top/c_loopsetup_nested_top.dsp
// Spec Reference: loopsetup nested top
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start1 , end1 ) LC0 = P1;
start1: R0 += 1;
R1 += -2;
LSETUP ( start2 , end2 ) LC1 = P2;
start2: R4 += 4;
end2: R5 += -5;
R3 += 1;
end1: R2 += 3;
R3 += 4;
LSETUP ( start3 , end3 ) LC1 = P3;
LSETUP ( start3 , end4 ) LC0 = P4;
start3: R6 += 6;
R0 += 1;
R1 += -2;
end4: R2 += 3;
R3 += 4;
end3: R7 += -7;
R3 += 1;
CHECKREG r0, 0x00000012;
CHECKREG r1, 0xFFFFFFF6;
CHECKREG r2, 0x00000047;
CHECKREG r3, 0x0000004C;
CHECKREG r4, 0x00000070;
CHECKREG r5, 0x00000014;
CHECKREG r6, 0x0000009C;
CHECKREG r7, 0x0000004D;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start5 , end5 ) LC0 = P5;
LSETUP ( start5 , end6 ) LC1 = SP >> 1;
start5: R4 += 1;
R6 += 4;
end6: R7 += -5;
R3 += 6;
end5: R5 += -2;
R3 += 3;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x0000005D;
CHECKREG r4, 0x0000004A;
CHECKREG r5, 0x00000042;
CHECKREG r6, 0x00000088;
CHECKREG r7, 0x0000003E;
LSETUP ( start7 , end7 ) LC0 = FP;
start7: R4 += 4;
end7: R5 += -5;
R3 += 6;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x0000006E;
CHECKREG r5, 0x00000015;
CHECKREG r6, 0x00000088;
CHECKREG r7, 0x0000003E;
P1 = 8;
P2 = 10;
P3 = 12;
P4 = 14;
P5 = 16;
SP = 18;
FP = 20;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start11 , end11 ) LC1 = P1 >> 1;
LSETUP ( start11 , end15 ) LC0 = P5;
start11: R0 += 1;
R1 += -1;
R4 += 1;
end15: R5 += -1;
R3 += 1;
end11: R2 += 1;
R3 += 1;
LSETUP ( start12 , end12 ) LC1 = P3 >> 1;
LSETUP ( start12 , end13 ) LC0 = P2 >> 1;
start12: R6 += 1;
R4 += 1;
end13: R5 += -1;
R3 += 1;
end12: R7 += -1;
R3 += 1;
CHECKREG r0, 0x00000018;
CHECKREG r1, 0xFFFFFFFD;
CHECKREG r2, 0x00000024;
CHECKREG r3, 0x0000003C;
CHECKREG r4, 0x0000005D;
CHECKREG r5, 0x00000033;
CHECKREG r6, 0x0000006A;
CHECKREG r7, 0x0000006A;
R0 = 0x04;
R1 = 0x06;
R2 = 0x08;
R3 = 0x10;
R4 = 0x12;
R5 = 0x14;
R6 = 0x16;
R7 = 0x18;
LSETUP ( start14 , end14 ) LC0 = P4;
LSETUP ( start14 , end16 ) LC1 = SP >> 1;
start14: R0 += 1;
R1 += -1;
R6 += 1;
end16: R7 += -1;
R3 += 1;
LSETUP ( start17 , end17 ) LC1 = FP >> 1;
start17: R4 += 1;
end17: R5 += -1;
R3 += 1;
end14: R2 += 1;
R3 += 1;
CHECKREG r0, 0x0000001A;
CHECKREG r1, 0xFFFFFFF0;
CHECKREG r2, 0x00000016;
CHECKREG r3, 0x0000002D;
CHECKREG r4, 0x0000009E;
CHECKREG r5, 0xFFFFFF88;
CHECKREG r6, 0x0000002C;
CHECKREG r7, 0x00000002;
pass
|
stsp/binutils-ia16
| 7,994
|
sim/testsuite/bfin/c_comp3op_dr_xor_dr.s
|
//Original:/testcases/core/c_comp3op_dr_xor_dr/c_comp3op_dr_xor_dr.dsp
// Spec Reference: comp3op dregs xor dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 ^ R0;
R1 = R0 ^ R1;
R2 = R0 ^ R2;
R3 = R0 ^ R3;
R4 = R0 ^ R4;
R5 = R0 ^ R5;
R6 = R0 ^ R6;
R7 = R0 ^ R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x89ABCDEF;
CHECKREG r2, 0x56789ABC;
CHECKREG r3, 0xDEF01234;
CHECKREG r4, 0x23456899;
CHECKREG r5, 0x78912345;
CHECKREG r6, 0x98765432;
CHECKREG r7, 0x12345678;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 ^ R0;
R1 = R1 ^ R1;
R2 = R1 ^ R2;
R3 = R1 ^ R3;
R4 = R1 ^ R4;
R5 = R1 ^ R5;
R6 = R1 ^ R6;
R7 = R1 ^ R7;
CHECKREG r0, 0x88880888;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x56781ABC;
CHECKREG r3, 0xDEF01234;
CHECKREG r4, 0x23451899;
CHECKREG r5, 0x78911345;
CHECKREG r6, 0x98761432;
CHECKREG r7, 0x12341678;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 ^ R0;
R1 = R2 ^ R1;
R2 = R2 ^ R2;
R3 = R2 ^ R3;
R4 = R2 ^ R4;
R5 = R2 ^ R5;
R6 = R2 ^ R6;
R7 = R2 ^ R7;
CHECKREG r0, 0x575BDF0B;
CHECKREG r1, 0xDFD35703;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xDEF01224;
CHECKREG r4, 0x23456829;
CHECKREG r5, 0x78912325;
CHECKREG r6, 0x98765422;
CHECKREG r7, 0x12345628;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 ^ R0;
R1 = R3 ^ R1;
R2 = R3 ^ R2;
R3 = R3 ^ R3;
R4 = R3 ^ R4;
R5 = R3 ^ R5;
R6 = R3 ^ R6;
R7 = R3 ^ R7;
CHECKREG r0, 0xDFD35750;
CHECKREG r1, 0x575BDFD0;
CHECKREG r2, 0x88888880;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x23456893;
CHECKREG r5, 0x78912343;
CHECKREG r6, 0x98765433;
CHECKREG r7, 0x12345673;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 ^ R0;
R1 = R4 ^ R1;
R2 = R4 ^ R2;
R3 = R4 ^ R3;
R4 = R4 ^ R4;
R5 = R4 ^ R5;
R6 = R4 ^ R6;
R7 = R4 ^ R7;
CHECKREG r0, 0x02662DFE;
CHECKREG r1, 0x0AEEA576;
CHECKREG r2, 0x053DF225;
CHECKREG r3, 0x0DB57AAD;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x48912345;
CHECKREG r6, 0x48765432;
CHECKREG r7, 0x42345678;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 ^ R0;
R1 = R5 ^ R1;
R2 = R5 ^ R2;
R3 = R5 ^ R3;
R4 = R5 ^ R4;
R5 = R5 ^ R5;
R6 = R5 ^ R6;
R7 = R5 ^ R7;
CHECKREG r0, 0x70B26622;
CHECKREG r1, 0xF03AEEAA;
CHECKREG r2, 0x20E9B9F9;
CHECKREG r3, 0xA0613171;
CHECKREG r4, 0x50D44BDC;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x95765432;
CHECKREG r7, 0x15345678;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 ^ R0;
R1 = R6 ^ R1;
R2 = R6 ^ R2;
R3 = R6 ^ R3;
R4 = R6 ^ R4;
R5 = R6 ^ R5;
R6 = R6 ^ R6;
R7 = R6 ^ R7;
CHECKREG r0, 0x99501155;
CHECKREG r1, 0x11D099DD;
CHECKREG r2, 0xCE00CE8E;
CHECKREG r3, 0x46804606;
CHECKREG r4, 0xBB303CAB;
CHECKREG r5, 0xE0E07777;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x12365678;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 ^ R0;
R1 = R7 ^ R1;
R2 = R7 ^ R2;
R3 = R7 ^ R3;
R4 = R7 ^ R4;
R5 = R7 ^ R5;
R6 = R7 ^ R6;
R7 = R7 ^ R7;
CHECKREG r0, 0x1317231F;
CHECKREG r1, 0x9B9F2B97;
CHECKREG r2, 0x444C2CC4;
CHECKREG r3, 0xCCC4244C;
CHECKREG r4, 0x31712EE1;
CHECKREG r5, 0x6AA5253D;
CHECKREG r6, 0x8A42224A;
CHECKREG r7, 0x00000000;
imm32 r0, 0x11234567;
imm32 r1, 0x81abcdef;
imm32 r2, 0x56189abc;
imm32 r3, 0xdef11234;
imm32 r4, 0x23451899;
imm32 r5, 0x78912145;
imm32 r6, 0x98765412;
imm32 r7, 0x12345671;
R0 = R1 ^ R0;
R1 = R2 ^ R0;
R2 = R3 ^ R0;
R3 = R4 ^ R0;
R4 = R5 ^ R0;
R5 = R6 ^ R0;
R6 = R7 ^ R0;
R7 = R0 ^ R0;
CHECKREG r0, 0x90888888;
CHECKREG r1, 0xC6901234;
CHECKREG r2, 0x4E799ABC;
CHECKREG r3, 0xB3CD9011;
CHECKREG r4, 0xE819A9CD;
CHECKREG r5, 0x08FEDC9A;
CHECKREG r6, 0x82BCDEF9;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01231567;
imm32 r1, 0x29ab1def;
imm32 r2, 0x52781abc;
imm32 r3, 0xde201234;
imm32 r4, 0x23421899;
imm32 r5, 0x78912345;
imm32 r6, 0x98761232;
imm32 r7, 0x12341628;
R0 = R2 ^ R1;
R1 = R3 ^ R1;
R2 = R4 ^ R1;
R3 = R5 ^ R1;
R4 = R6 ^ R1;
R5 = R7 ^ R1;
R6 = R0 ^ R1;
R7 = R1 ^ R1;
CHECKREG r0, 0x7BD30753;
CHECKREG r1, 0xF78B0FDB;
CHECKREG r2, 0xD4C91742;
CHECKREG r3, 0x8F1A2C9E;
CHECKREG r4, 0x6FFD1DE9;
CHECKREG r5, 0xE5BF19F3;
CHECKREG r6, 0x8C580888;
CHECKREG r7, 0x00000000;
imm32 r0, 0x03234527;
imm32 r1, 0x893bcd2f;
imm32 r2, 0x56739a2c;
imm32 r3, 0x3ef03224;
imm32 r4, 0x23456329;
imm32 r5, 0x78312335;
imm32 r6, 0x98735423;
imm32 r7, 0x12343628;
R0 = R4 ^ R2;
R1 = R5 ^ R2;
R2 = R6 ^ R2;
R3 = R7 ^ R2;
R4 = R0 ^ R2;
R5 = R1 ^ R2;
R6 = R2 ^ R2;
R7 = R3 ^ R2;
CHECKREG r0, 0x7536F905;
CHECKREG r1, 0x2E42B919;
CHECKREG r2, 0xCE00CE0F;
CHECKREG r3, 0xDC34F827;
CHECKREG r4, 0xBB36370A;
CHECKREG r5, 0xE0427716;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x12343628;
imm32 r0, 0x04234563;
imm32 r1, 0x894bcde3;
imm32 r2, 0x56749ab3;
imm32 r3, 0x4ef04233;
imm32 r4, 0x24456493;
imm32 r5, 0x78412344;
imm32 r6, 0x98745434;
imm32 r7, 0x12344673;
R0 = R5 ^ R3;
R1 = R6 ^ R3;
R2 = R7 ^ R3;
R3 = R0 ^ R3;
R4 = R1 ^ R3;
R5 = R2 ^ R3;
R6 = R3 ^ R3;
R7 = R4 ^ R3;
CHECKREG r0, 0x36B16177;
CHECKREG r1, 0xD6841607;
CHECKREG r2, 0x5CC40440;
CHECKREG r3, 0x78412344;
CHECKREG r4, 0xAEC53543;
CHECKREG r5, 0x24852704;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xD6841607;
imm32 r0, 0x41235567;
imm32 r1, 0x49abc5ef;
imm32 r2, 0x46789a5c;
imm32 r3, 0x4ef01235;
imm32 r4, 0x53456899;
imm32 r5, 0x45912345;
imm32 r6, 0x48565432;
imm32 r7, 0x42355678;
R0 = R6 ^ R4;
R1 = R7 ^ R4;
R2 = R0 ^ R4;
R3 = R1 ^ R4;
R4 = R2 ^ R4;
R5 = R3 ^ R4;
R6 = R4 ^ R4;
R7 = R5 ^ R4;
CHECKREG r0, 0x1B133CAB;
CHECKREG r1, 0x11703EE1;
CHECKREG r2, 0x48565432;
CHECKREG r3, 0x42355678;
CHECKREG r4, 0x1B133CAB;
CHECKREG r5, 0x59266AD3;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x42355678;
imm32 r0, 0x05264567;
imm32 r1, 0x85ab6def;
imm32 r2, 0x657896bc;
imm32 r3, 0xd6f01264;
imm32 r4, 0x25656896;
imm32 r5, 0x75962345;
imm32 r6, 0x95766432;
imm32 r7, 0x15345678;
R0 = R7 ^ R5;
R1 = R0 ^ R5;
R2 = R1 ^ R5;
R3 = R2 ^ R5;
R4 = R3 ^ R5;
R5 = R4 ^ R5;
R6 = R5 ^ R5;
R7 = R6 ^ R5;
CHECKREG r0, 0x60A2753D;
CHECKREG r1, 0x15345678;
CHECKREG r2, 0x60A2753D;
CHECKREG r3, 0x15345678;
CHECKREG r4, 0x60A2753D;
CHECKREG r5, 0x15345678;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x15345678;
imm32 r0, 0x01764567;
imm32 r1, 0x89a7cdef;
imm32 r2, 0x56767abc;
imm32 r3, 0xdef61734;
imm32 r4, 0x73466879;
imm32 r5, 0x77962347;
imm32 r6, 0x98765432;
imm32 r7, 0x12375678;
R0 = R7 ^ R6;
R1 = R0 ^ R6;
R2 = R1 ^ R6;
R3 = R2 ^ R6;
R4 = R3 ^ R6;
R5 = R4 ^ R6;
R6 = R5 ^ R6;
R7 = R6 ^ R6;
CHECKREG r0, 0x8A41024A;
CHECKREG r1, 0x12375678;
CHECKREG r2, 0x8A41024A;
CHECKREG r3, 0x12375678;
CHECKREG r4, 0x8A41024A;
CHECKREG r5, 0x12375678;
CHECKREG r6, 0x8A41024A;
CHECKREG r7, 0x00000000;
imm32 r0, 0x81238567;
imm32 r1, 0x88ab78ef;
imm32 r2, 0x56887a8c;
imm32 r3, 0x8ef87238;
imm32 r4, 0x28458899;
imm32 r5, 0x78817845;
imm32 r6, 0x98787482;
imm32 r7, 0x12348678;
R0 = R1 ^ R7;
R1 = R2 ^ R7;
R2 = R3 ^ R7;
R3 = R4 ^ R7;
R4 = R5 ^ R7;
R5 = R6 ^ R7;
R6 = R7 ^ R7;
R7 = R0 ^ R7;
CHECKREG r0, 0x9A9FFE97;
CHECKREG r1, 0x44BCFCF4;
CHECKREG r2, 0x9CCCF440;
CHECKREG r3, 0x3A710EE1;
CHECKREG r4, 0x6AB5FE3D;
CHECKREG r5, 0x8A4CF2FA;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x88AB78EF;
pass
|
stsp/binutils-ia16
| 5,431
|
sim/testsuite/bfin/c_dsp32alu_rpp.s
|
//Original:/testcases/core/c_dsp32alu_rpp/c_dsp32alu_rpp.dsp
// Spec Reference: dsp32alu dreg = +/+ ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = R0 +|+ R0;
R1 = R0 +|+ R1;
R2 = R0 +|+ R2;
R3 = R0 +|+ R3;
R4 = R0 +|+ R4;
R5 = R0 +|+ R5;
R6 = R0 +|+ R6;
R7 = R0 +|+ R7;
CHECKREG r0, 0x2ACE1222;
CHECKREG r1, 0x5257BD3F;
CHECKREG r2, 0x5F126737;
CHECKREG r3, 0x71348939;
CHECKREG r4, 0x80359B3D;
CHECKREG r5, 0x9257BD3F;
CHECKREG r6, 0x9F126737;
CHECKREG r7, 0xB1348999;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = R1 +|+ R0;
R1 = R1 +|+ R1;
R2 = R1 +|+ R2;
R3 = R1 +|+ R3;
R4 = R1 +|+ R4;
R5 = R1 +|+ R5;
R6 = R1 +|+ R6;
R7 = R1 +|+ R7;
CHECKREG r0, 0x3CF03458;
CHECKREG r1, 0x4F12565A;
CHECKREG r2, 0x0356AB7F;
CHECKREG r3, 0x1578CD81;
CHECKREG r4, 0x279AEF83;
CHECKREG r5, 0x39BC1185;
CHECKREG r6, 0x4BDE3387;
CHECKREG r7, 0x5E005659;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = R2 +|+ R0;
R1 = R2 +|+ R1;
R2 = R2 +|+ R2;
R3 = R2 +|+ R3;
R4 = R2 +|+ R4;
R5 = R2 +|+ R5;
R6 = R2 +|+ R6;
R7 = R2 +|+ R7;
CHECKREG r0, 0x84ABDF00;
CHECKREG r1, 0xA5CD0122;
CHECKREG r2, 0x8688AAAA;
CHECKREG r3, 0xEAEE2221;
CHECKREG r4, 0xCBEF3455;
CHECKREG r5, 0xED115677;
CHECKREG r6, 0xCDCCFFFF;
CHECKREG r7, 0xEEEE2221;
imm32 r0, 0xd567892b;
imm32 r1, 0xad89ab2d;
imm32 r2, 0xb4d45525;
imm32 r3, 0xc66d7727;
imm32 r0, 0x9567d92b;
imm32 r1, 0xa789ad2d;
imm32 r2, 0xb44455d5;
imm32 r3, 0xc666772d;
R0 = R3 +|+ R0;
R1 = R3 +|+ R1;
R2 = R3 +|+ R2;
R3 = R3 +|+ R3;
R4 = R3 +|+ R4;
R5 = R3 +|+ R5;
R6 = R3 +|+ R6;
R7 = R3 +|+ R7;
CHECKREG r0, 0x5BCD5058;
CHECKREG r1, 0x6DEF245A;
CHECKREG r2, 0x7AAACD02;
CHECKREG r3, 0x8CCCEE5A;
CHECKREG r4, 0x58BB22AF;
CHECKREG r5, 0x79DD44D1;
CHECKREG r6, 0x5A98EE59;
CHECKREG r7, 0x7BBA107B;
imm32 r0, 0x4577891b;
imm32 r1, 0x6779ab2d;
imm32 r2, 0x44755535;
imm32 r3, 0x66765747;
imm32 r4, 0x88779565;
imm32 r5, 0xaa7abb5b;
imm32 r6, 0xcc97dd85;
imm32 r7, 0xeeae7f9f;
R0 = R4 +|+ R0;
R1 = R4 +|+ R1;
R2 = R4 +|+ R2;
R3 = R4 +|+ R3;
R4 = R4 +|+ R4;
R5 = R4 +|+ R5;
R6 = R4 +|+ R6;
R7 = R4 +|+ R7;
CHECKREG r0, 0xCDEE1E80;
CHECKREG r1, 0xEFF04092;
CHECKREG r2, 0xCCECEA9A;
CHECKREG r3, 0xEEEDECAC;
CHECKREG r4, 0x10EE2ACA;
CHECKREG r5, 0xBB68E625;
CHECKREG r6, 0xDD85084F;
CHECKREG r7, 0xFF9CAA69;
imm32 r0, 0x456b89ab;
imm32 r1, 0x69764bcd;
imm32 r2, 0x49736564;
imm32 r3, 0x61278394;
imm32 r4, 0x98876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x12346fff;
R0 = R5 +|+ R0;
R1 = R5 +|+ R1;
R2 = R5 +|+ R2;
R3 = R5 +|+ R3;
R4 = R5 +|+ R4;
R5 = R5 +|+ R5;
R6 = R5 +|+ R6;
R7 = R5 +|+ R7;
CHECKREG r0, 0xF0159566;
CHECKREG r1, 0x14205788;
CHECKREG r2, 0xF41D711F;
CHECKREG r3, 0x0BD18F4F;
CHECKREG r4, 0x43316FF4;
CHECKREG r5, 0x55541776;
CHECKREG r6, 0x22203553;
CHECKREG r7, 0x67888775;
imm32 r0, 0xaa6739ab;
imm32 r1, 0x67dd4bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x6b66bb77;
imm32 r4, 0x12345699;
imm32 r5, 0x45b78b6b;
imm32 r6, 0x043b90d6;
imm32 r7, 0x12b4bb7f;
R0 = R6 +|+ R0;
R1 = R6 +|+ R1;
R2 = R6 +|+ R2;
R3 = R6 +|+ R3;
R4 = R6 +|+ R4;
R5 = R6 +|+ R5;
R6 = R6 +|+ R6;
R7 = R6 +|+ R7;
CHECKREG r0, 0xAEA2CA81;
CHECKREG r1, 0x6C18DCA3;
CHECKREG r2, 0x0780F82B;
CHECKREG r3, 0x6FA14C4D;
CHECKREG r4, 0x166FE76F;
CHECKREG r5, 0x49F21C41;
CHECKREG r6, 0x087621AC;
CHECKREG r7, 0x1B2ADD2B;
imm32 r0, 0x976789ab;
imm32 r1, 0x6979abcd;
imm32 r2, 0x23956755;
imm32 r3, 0x56799007;
imm32 r4, 0x789a9799;
imm32 r5, 0xaaaa09bb;
imm32 r6, 0x89ab1d9d;
imm32 r7, 0xabcd2ff9;
R0 = R7 +|+ R0;
R1 = R7 +|+ R1;
R2 = R7 +|+ R2;
R3 = R7 +|+ R3;
R4 = R7 +|+ R4;
R5 = R7 +|+ R5;
R6 = R7 +|+ R6;
R7 = R7 +|+ R7;
CHECKREG r0, 0x4334B9A4;
CHECKREG r1, 0x1546DBC6;
CHECKREG r2, 0xCF62974E;
CHECKREG r3, 0x0246C000;
CHECKREG r4, 0x2467C792;
CHECKREG r5, 0x567739B4;
CHECKREG r6, 0x35784D96;
CHECKREG r7, 0x579A5FF2;
imm32 r0, 0x856739ab;
imm32 r1, 0x87694bcd;
imm32 r2, 0x08856755;
imm32 r3, 0x66686777;
imm32 r4, 0x12385699;
imm32 r5, 0x4567886b;
imm32 r6, 0x04329086;
imm32 r7, 0x12345678;
R4 = R4 +|+ R7 (S);
R5 = R5 +|+ R5 (CO);
R2 = R6 +|+ R3 (SCO);
R6 = R0 +|+ R4 (S);
R0 = R1 +|+ R6 (S);
R2 = R2 +|+ R1 (CO);
R1 = R3 +|+ R0 (CO);
R7 = R7 +|+ R4 (SCO);
CHECKREG r0, 0x80007FFF;
CHECKREG r1, 0xE776E668;
CHECKREG r2, 0xB6677F66;
CHECKREG r3, 0x66686777;
CHECKREG r4, 0x246C7FFF;
CHECKREG r5, 0x10D68ACE;
CHECKREG r6, 0xA9D37FFF;
CHECKREG r7, 0x7FFF36A0;
imm32 r0, 0x476789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x23456755;
imm32 r3, 0x56789007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R3 = R4 +|+ R0 (S);
R5 = R5 +|+ R1 (SCO);
R2 = R2 +|+ R2 (S);
R7 = R7 +|+ R3 (CO);
R4 = R3 +|+ R4 (CO);
R0 = R1 +|+ R5 (S);
R1 = R0 +|+ R6 (SCO);
R6 = R6 +|+ R7 (SCO);
CHECKREG r0, 0x1F01BDF0;
CHECKREG r1, 0xDB6DA8AC;
CHECKREG r2, 0x468A7FFF;
CHECKREG r3, 0x7FFF8000;
CHECKREG r4, 0x3799F899;
CHECKREG r5, 0xB7881223;
CHECKREG r6, 0x49498000;
CHECKREG r7, 0xAFF72BCC;
pass
|
stsp/binutils-ia16
| 4,778
|
sim/testsuite/bfin/c_dsp32shift_align8.s
|
//Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp
// Spec Reference: dsp32shift align8
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x08000807;
R1 = ALIGN8 ( R1 , R0 );
R2 = ALIGN8 ( R2 , R0 );
R3 = ALIGN8 ( R3 , R0 );
R4 = ALIGN8 ( R4 , R0 );
R5 = ALIGN8 ( R5 , R0 );
R6 = ALIGN8 ( R6 , R0 );
R7 = ALIGN8 ( R7 , R0 );
R0 = ALIGN8 ( R0 , R0 );
CHECKREG r0, 0x01000000;
CHECKREG r1, 0x01000000;
CHECKREG r2, 0x02000000;
CHECKREG r3, 0x03000000;
CHECKREG r4, 0x04000000;
CHECKREG r5, 0x05000000;
CHECKREG r6, 0x66000000;
CHECKREG r7, 0x07000000;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000002;
imm32 r2, 0x09400002;
imm32 r3, 0x09100003;
imm32 r4, 0x09020004;
imm32 r5, 0x09003005;
imm32 r6, 0x09000406;
imm32 r7, 0x09000057;
R0 = ALIGN8 ( R0 , R1 );
R2 = ALIGN8 ( R2 , R1 );
R3 = ALIGN8 ( R3 , R1 );
R4 = ALIGN8 ( R4 , R1 );
R5 = ALIGN8 ( R5 , R1 );
R6 = ALIGN8 ( R6 , R1 );
R7 = ALIGN8 ( R7 , R1 );
R1 = ALIGN8 ( R1 , R1 );
CHECKREG r0, 0x01090000;
CHECKREG r1, 0x02090000;
CHECKREG r2, 0x02090000;
CHECKREG r3, 0x03090000;
CHECKREG r4, 0x04090000;
CHECKREG r5, 0x05090000;
CHECKREG r6, 0x06090000;
CHECKREG r7, 0x57090000;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a400010;
imm32 r4, 0x0a05e004;
imm32 r5, 0x0a006005;
imm32 r6, 0x0a00e706;
imm32 r7, 0x0a00e087;
R0 = ALIGN8 ( R0 , R2 );
R1 = ALIGN8 ( R1 , R2 );
R3 = ALIGN8 ( R3 , R2 );
R4 = ALIGN8 ( R4 , R2 );
R5 = ALIGN8 ( R5 , R2 );
R6 = ALIGN8 ( R6 , R2 );
R7 = ALIGN8 ( R7 , R2 );
R2 = ALIGN8 ( R2 , R2 );
CHECKREG r0, 0x010A0000;
CHECKREG r1, 0x010A0000;
CHECKREG r2, 0x0F0A0000;
CHECKREG r3, 0x100A0000;
CHECKREG r4, 0x040A0000;
CHECKREG r5, 0x050A0000;
CHECKREG r6, 0x060A0000;
CHECKREG r7, 0x870A0000;
imm32 r0, 0x2b00f001;
imm32 r1, 0x0300f001;
imm32 r2, 0x0b40f002;
imm32 r3, 0x0b050010;
imm32 r4, 0x0b006004;
imm32 r5, 0x0b00f705;
imm32 r6, 0x0b00f086;
imm32 r7, 0x0b00f009;
R0 = ALIGN8 ( R0 , R3 );
R1 = ALIGN8 ( R1 , R3 );
R2 = ALIGN8 ( R2 , R3 );
R4 = ALIGN8 ( R4 , R3 );
R5 = ALIGN8 ( R5 , R3 );
R6 = ALIGN8 ( R6 , R3 );
R7 = ALIGN8 ( R7 , R3 );
R3 = ALIGN8 ( R3 , R3 );
CHECKREG r0, 0x010B0500;
CHECKREG r1, 0x010B0500;
CHECKREG r2, 0x020B0500;
CHECKREG r3, 0x100B0500;
CHECKREG r4, 0x040B0500;
CHECKREG r5, 0x050B0500;
CHECKREG r6, 0x860B0500;
CHECKREG r7, 0x090B0500;
imm32 r0, 0x4c0000c0;
imm32 r1, 0x050100c0;
imm32 r2, 0x0c6200c0;
imm32 r3, 0x0c0700c0;
imm32 r4, 0x0c04800c;
imm32 r5, 0x0c0509c0;
imm32 r6, 0x0c060000;
imm32 r7, 0x0c0700ca;
R0 = ALIGN8 ( R0 , R4 );
R1 = ALIGN8 ( R1 , R4 );
R2 = ALIGN8 ( R2 , R4 );
R3 = ALIGN8 ( R3 , R4 );
R5 = ALIGN8 ( R5 , R4 );
R6 = ALIGN8 ( R6 , R4 );
R7 = ALIGN8 ( R7 , R4 );
R4 = ALIGN8 ( R4 , R4 );
CHECKREG r0, 0xC00C0480;
CHECKREG r1, 0xC00C0480;
CHECKREG r2, 0xC00C0480;
CHECKREG r3, 0xC00C0480;
CHECKREG r4, 0x0C0C0480;
CHECKREG r5, 0xC00C0480;
CHECKREG r6, 0x000C0480;
CHECKREG r7, 0xCA0C0480;
imm32 r0, 0xa00100d0;
imm32 r1, 0xa00100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa0050007;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R0 = ALIGN8 ( R0 , R5 );
R1 = ALIGN8 ( R1 , R5 );
R2 = ALIGN8 ( R2 , R5 );
R3 = ALIGN8 ( R3 , R5 );
R4 = ALIGN8 ( R4 , R5 );
R6 = ALIGN8 ( R6 , R5 );
R7 = ALIGN8 ( R7 , R5 );
R5 = ALIGN8 ( R5 , R5 );
CHECKREG r0, 0xD0A00500;
CHECKREG r1, 0xD1A00500;
CHECKREG r2, 0xD0A00500;
CHECKREG r3, 0xD0A00500;
CHECKREG r4, 0xD0A00500;
CHECKREG r5, 0x07A00500;
CHECKREG r6, 0xD0A00500;
CHECKREG r7, 0xD0A00500;
imm32 r0, 0xb2010000;
imm32 r1, 0xb0310000;
imm32 r2, 0xb042000f;
imm32 r3, 0xbf030000;
imm32 r4, 0xba040000;
imm32 r5, 0xbb050000;
imm32 r6, 0xbc060009;
imm32 r7, 0xb0e70000;
R0 = ALIGN8 ( R0 , R6 );
R1 = ALIGN8 ( R1 , R6 );
R2 = ALIGN8 ( R2 , R6 );
R3 = ALIGN8 ( R3 , R6 );
R4 = ALIGN8 ( R4 , R6 );
R5 = ALIGN8 ( R5 , R6 );
R6 = ALIGN8 ( R6 , R6 );
R7 = ALIGN8 ( R7 , R6 );
CHECKREG r0, 0x00BC0600;
CHECKREG r1, 0x00BC0600;
CHECKREG r2, 0x0FBC0600;
CHECKREG r3, 0x00BC0600;
CHECKREG r4, 0x00BC0600;
CHECKREG r5, 0x00BC0600;
CHECKREG r6, 0x09BC0600;
CHECKREG r7, 0x0009BC06;
imm32 r0, 0xd23100e0;
imm32 r1, 0xd04500e0;
imm32 r2, 0xde32f0e0;
imm32 r3, 0xd90300e0;
imm32 r4, 0xd07400e0;
imm32 r5, 0xdef500e0;
imm32 r6, 0xd06600e0;
imm32 r7, 0xd0080023;
R1 = ALIGN8 ( R0 , R7 );
R2 = ALIGN8 ( R1 , R7 );
R3 = ALIGN8 ( R2 , R7 );
R4 = ALIGN8 ( R3 , R7 );
R5 = ALIGN8 ( R4 , R7 );
R6 = ALIGN8 ( R5 , R7 );
R7 = ALIGN8 ( R6 , R7 );
R0 = ALIGN8 ( R7 , R7 );
CHECKREG r0, 0x0000D008;
CHECKREG r1, 0xE0D00800;
CHECKREG r2, 0x00D00800;
CHECKREG r3, 0x00D00800;
CHECKREG r4, 0x00D00800;
CHECKREG r5, 0x00D00800;
CHECKREG r6, 0x00D00800;
CHECKREG r7, 0x00D00800;
pass
|
stsp/binutils-ia16
| 1,189
|
sim/testsuite/bfin/se_ssync.S
|
//Original:/proj/frio/dv/testcases/seq/se_ssync/se_ssync.dsp
// Description: Test SSYNC by writing a bunch of MMRs and verifying read
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10 // change for how much stack you need
#endif
LD32(p0, EVT5);
LD32(r0, 0x55555555);
LD32(p1, EVT6);
LD32(r1, 0xAAAAAAAA);
LD32(p2, EVT7);
LD32(r2, 0xBABEFACE);
LD32(p3, EVT8);
LD32(r3, 0xCFCFCFCF);
LD32(p4, EVT9);
LD32(r4, 0xDEADBEEF);
LD32(p5, EVT10);
LD32(r5, 0xBAD1BAD1);
[ P0 ] = R0; // write the MMRS
[ P1 ] = R1;
[ P2 ] = R2;
[ P3 ] = R3;
[ P4 ] = R4;
[ P5 ] = R5;
SSYNC; // wait for it
R7 = [ P5 ]; // read back MMRs
R6 = [ P4 ]; // should be updated
R5 = [ P3 ];
R4 = [ P2 ];
R3 = [ P1 ];
R2 = [ P0 ];
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
CHECKREG(r2, 0x55555555);
CHECKREG(r3, 0xAAAAAAAA);
CHECKREG(r4, 0xBABEFACE);
CHECKREG(r5, 0xCFCFCFCF);
CHECKREG(r6, 0xDEADBEEF);
CHECKREG(r7, 0xBAD1BAD1);
dbg_pass;
|
stsp/binutils-ia16
| 6,180
|
sim/testsuite/bfin/c_ldst_ld_d_p_mm_xh.s
|
//Original:testcases/core/c_ldst_ld_d_p_mm_xh/c_ldst_ld_d_p_mm_xh.dsp
// Spec Reference: c_ldst ld d [p++/--] h b xh xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x08;
loadsym p1, DATA_ADDR_2, 0x08;
loadsym p2, DATA_ADDR_3, 0x08;
loadsym i1, DATA_ADDR_4, 0x08;
loadsym p4, DATA_ADDR_5, 0x08;
loadsym fp, DATA_ADDR_6, 0x08;
loadsym i3, DATA_ADDR_7, 0x08;
P3 = I1; SP = I3;
R4 = W [ P5 -- ] (X);
R5 = W [ P1 -- ] (X);
R6 = W [ P2 -- ] (X);
R7 = W [ P3 -- ] (X);
R0 = W [ P4 -- ] (X);
R1 = W [ FP -- ] (X);
R2 = W [ SP -- ] (X);
CHECKREG r0, 0xFFFF8A8B;
CHECKREG r1, 0x00000A0B;
CHECKREG r2, 0xFFFF8A8B;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00002A2B;
CHECKREG r6, 0x00004A4B;
CHECKREG r7, 0x00006A6B;
R5 = W [ P5 -- ] (X);
R6 = W [ P1 -- ] (X);
R7 = W [ P2 -- ] (X);
R0 = W [ P3 -- ] (X);
R1 = W [ P4 -- ] (X);
R2 = W [ FP -- ] (X);
R3 = W [ SP -- ] (X);
CHECKREG r0, 0x00006465;
CHECKREG r1, 0xFFFF8485;
CHECKREG r2, 0x00000405;
CHECKREG r3, 0xFFFF8485;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000405;
CHECKREG r6, 0x00002425;
CHECKREG r7, 0x00004445;
R6 = W [ P5 -- ] (X);
R7 = W [ P1 -- ] (X);
R0 = W [ P2 -- ] (X);
R1 = W [ P3 -- ] (X);
R2 = W [ P4 -- ] (X);
R3 = W [ FP -- ] (X);
R4 = W [ SP -- ] (X);
CHECKREG r0, 0x00004647;
CHECKREG r1, 0x00006667;
CHECKREG r2, 0xFFFF8687;
CHECKREG r3, 0x00000607;
CHECKREG r4, 0xFFFF8687;
CHECKREG r5, 0x00000405;
CHECKREG r6, 0x00000607;
CHECKREG r7, 0x00002627;
R7 = W [ P5 -- ] (X);
R0 = W [ P1 -- ] (X);
R1 = W [ P2 -- ] (X);
R2 = W [ P3 -- ] (X);
R3 = W [ P4 -- ] (X);
R4 = W [ FP -- ] (X);
R5 = W [ SP -- ] (X);
CHECKREG r0, 0x00002021;
CHECKREG r1, 0x00004041;
CHECKREG r2, 0x00006061;
CHECKREG r3, 0xFFFF8081;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0xFFFF8081;
CHECKREG r6, 0x00000607;
CHECKREG r7, 0x00000001;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 6,857
|
sim/testsuite/bfin/c_dsp32mac_a1a0_m.s
|
//Original:/testcases/core/c_dsp32mac_a1a0_m/c_dsp32mac_a1a0_m.dsp
// Spec Reference: dsp32mac a1 a0 m MNOP
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1
imm32 r0, 0x123c5678;
imm32 r1, 0x2345c789;
imm32 r2, 0x34567c9a;
imm32 r3, 0x456789c2;
imm32 r4, 0xc678912c;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1c34567;
imm32 r7, 0xc12c4567;
A0 = 0;
A1 = 0;
A1 = R0.L * R1.L (M);
R0 = A0.w;
R1 = A1.w;
A0 += R2.H * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 += R4.L * R5.H;
R4 = A0.w;
R5 = A1.w;
A0 += R6.L * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x43658E38;
CHECKREG r2, 0x1C607934;
CHECKREG r3, 0x43658E38;
CHECKREG r4, 0x1C607934;
CHECKREG r5, 0xE56C0F50;
CHECKREG r6, 0xFA4FA29C;
CHECKREG r7, 0xE56C0F50;
imm32 r0, 0xd2345678;
imm32 r1, 0x2d456789;
imm32 r2, 0x34d6789a;
imm32 r3, 0x456d8912;
imm32 r4, 0x5678d123;
imm32 r5, 0x67891d34;
imm32 r6, 0xa12345d7;
imm32 r7, 0xc123456d;
A0 += R6.H * R7.L;
R6 = A0.w;
R7 = A1.w;
A1 += R4.L * R5.H;
R4 = A0.w;
R5 = A1.w;
A0 += R2.L * R3.L;
R2 = A0.w;
R3 = A1.w;
A1 += R0.H * R1.L;
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x56CD8212;
CHECKREG r1, 0x9A78E46E;
CHECKREG r2, 0x56CD8212;
CHECKREG r3, 0xBF8410C6;
CHECKREG r4, 0xC6DBB86A;
CHECKREG r5, 0xBF8410C6;
CHECKREG r6, 0xC6DBB86A;
CHECKREG r7, 0xE56C0F50;
// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is
// signed, the other input is unsigned
imm32 r0, 0x12345678;
imm32 r1, 0x33456789;
imm32 r2, 0x5556789a;
imm32 r3, 0x75678912;
imm32 r4, 0x86789123;
imm32 r5, 0xa7891234;
imm32 r6, 0xc1234567;
imm32 r7, 0xf1234567;
A1 += R0.L * R1.L (M), A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.L (M), A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 += R4.L * R5.L (M), A0 = R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 = R6.L * R7.L (M), A0 = R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x45F11C70;
CHECKREG r1, 0xBD7172A6;
CHECKREG r2, 0xB48EEC5C;
CHECKREG r3, 0x4092E4D4;
CHECKREG r4, 0xEEB780C0;
CHECKREG r5, 0x38B0D5F0;
CHECKREG r6, 0x074CB592;
CHECKREG r7, 0x12D0AF71;
imm32 r0, 0x12245618;
imm32 r1, 0x23256719;
imm32 r2, 0x3426781a;
imm32 r3, 0x45278912;
imm32 r4, 0x56289113;
imm32 r5, 0x67291214;
imm32 r6, 0xa1234517;
imm32 r7, 0xc1234517;
A1 += R0.L * R1.H (M), A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 += R2.L * R3.H (M), A0 = R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 += R4.L * R5.H (M), A0 = R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.L * R7.H (M), A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x455820B0;
CHECKREG r1, 0x1EA268E9;
CHECKREG r2, 0x40E29BEC;
CHECKREG r3, 0x3F13B6DF;
CHECKREG r4, 0x0C2B1640;
CHECKREG r5, 0x126097EA;
CHECKREG r6, 0x3AC1EBD2;
CHECKREG r7, 0x4680610F;
imm32 r0, 0x15245648;
imm32 r1, 0x25256749;
imm32 r2, 0x3526784a;
imm32 r3, 0x45278942;
imm32 r4, 0x55389143;
imm32 r5, 0x65391244;
imm32 r6, 0xa5334547;
imm32 r7, 0xc5334547;
A1 = R0.H * R1.H (M), A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 += R2.H * R3.H (M), A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 = R4.H * R5.H (M), A0 = R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 = R6.H * R7.H (M), A0 = R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x459F2510;
CHECKREG r1, 0x03114234;
CHECKREG r2, 0x869BAF9C;
CHECKREG r3, 0x116C98FE;
CHECKREG r4, 0x0C2925C0;
CHECKREG r5, 0x21B21178;
CHECKREG r6, 0x29B65052;
CHECKREG r7, 0xBA0E2829;
imm32 r0, 0x13245628;
imm32 r1, 0x23256729;
imm32 r2, 0x3326782a;
imm32 r3, 0x43278922;
imm32 r4, 0x56389123;
imm32 r5, 0x67391224;
imm32 r6, 0xa1334527;
imm32 r7, 0xc1334527;
A1 = R0.H * R1.L (M), A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 += R2.H * R3.L (M), A0 = R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 = R4.H * R5.L (M), A0 = R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.H * R7.L (M), A0 = R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x456FC8D0;
CHECKREG r1, 0x07B68CC4;
CHECKREG r2, 0x3F0A98CC;
CHECKREG r3, 0x231CADD0;
CHECKREG r4, 0x0C381FC0;
CHECKREG r5, 0x061C0FE0;
CHECKREG r6, 0x2E832052;
CHECKREG r7, 0xEC805DA5;
// test the MNOP default (signed fraction : left ) rounding U=0 I=0 T=0 w32=1
imm32 r0, 0x123c5678;
imm32 r1, 0x2345c789;
imm32 r2, 0x34567c9a;
imm32 r3, 0x456789c2;
imm32 r4, 0xc678912c;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1c34567;
imm32 r7, 0xc12c4567;
A0 = 0;
A1 = 0;
A1 += R0.L * R1.L (M);
R0 = A0.w;
R1 = A1.w;
A0 += R2.H * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 = R4.L * R5.H (M);
R4 = A0.w;
R5 = A1.w;
A0 += R6.L * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x43658E38;
CHECKREG r2, 0x1C607934;
CHECKREG r3, 0x43658E38;
CHECKREG r4, 0x1C607934;
CHECKREG r5, 0xD103408C;
CHECKREG r6, 0xFA4FA29C;
CHECKREG r7, 0xD103408C;
imm32 r0, 0xd2345678;
imm32 r1, 0x2d456789;
imm32 r2, 0x34d6789a;
imm32 r3, 0x456d8912;
imm32 r4, 0x5678d123;
imm32 r5, 0x67891d34;
imm32 r6, 0xa12345d7;
imm32 r7, 0xc123456d;
A0 = R6.H * R7.L;
R6 = A0.w;
R7 = A1.w;
A1 = R4.L * R5.H (M);
R4 = A0.w;
R5 = A1.w;
A0 = R2.L * R3.L;
R2 = A0.w;
R3 = A1.w;
A1 += R0.H * R1.L (M);
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x8FF1C9A8;
CHECKREG r1, 0xDA866A8F;
CHECKREG r2, 0x8FF1C9A8;
CHECKREG r3, 0xED0C00BB;
CHECKREG r4, 0xCC8C15CE;
CHECKREG r5, 0xED0C00BB;
CHECKREG r6, 0xCC8C15CE;
CHECKREG r7, 0xD103408C;
imm32 r0, 0x123c5678;
imm32 r1, 0x2345c789;
imm32 r2, 0x34567c9a;
imm32 r3, 0x456789c2;
imm32 r4, 0xc678912c;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1c34567;
imm32 r7, 0xc12c4567;
A0 = 0;
A1 = 0;
A1 -= R0.L * R1.L (M);
R0 = A0.w;
R1 = A1.w;
A0 -= R2.H * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.L * R5.H (M);
R4 = A0.w;
R5 = A1.w;
A0 -= R6.L * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xBC9A71C8;
CHECKREG r2, 0xE39F86CC;
CHECKREG r3, 0xBC9A71C8;
CHECKREG r4, 0xE39F86CC;
CHECKREG r5, 0xEB97313C;
CHECKREG r6, 0x05B05D64;
CHECKREG r7, 0xEB97313C;
imm32 r0, 0xd2345678;
imm32 r1, 0x2d456789;
imm32 r2, 0x34d6789a;
imm32 r3, 0x456d8912;
imm32 r4, 0x5678d123;
imm32 r5, 0x67891d34;
imm32 r6, 0xa12345d7;
imm32 r7, 0xc123456d;
A0 -= R6.H * R7.L;
R6 = A0.w;
R7 = A1.w;
A1 -= R4.L * R5.H (M);
R4 = A0.w;
R5 = A1.w;
A0 -= R2.L * R3.L;
R2 = A0.w;
R3 = A1.w;
A1 -= R0.H * R1.L (M);
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0xA9327DEE;
CHECKREG r1, 0x1110C6AD;
CHECKREG r2, 0xA9327DEE;
CHECKREG r3, 0xFE8B3081;
CHECKREG r4, 0x39244796;
CHECKREG r5, 0xFE8B3081;
CHECKREG r6, 0x39244796;
CHECKREG r7, 0xEB97313C;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
.dd 0x00b00104
.dd 0x00a00105
|
stsp/binutils-ia16
| 5,477
|
sim/testsuite/bfin/c_dsp32mult_dr_mix.s
|
//Original:/testcases/core/c_dsp32mult_dr_mix/c_dsp32mult_dr_mix.dsp
// Spec Reference: dsp32mult single dr (mix) u i t is tu ih
# mach: bfin
.include "testutils.inc"
start
// test the default (signed fraction) rounding U=0 I=0 T=0
imm32 r0, 0xab235615;
imm32 r1, 0xcfba5117;
imm32 r2, 0x13246715;
imm32 r3, 0x00060017;
imm32 r4, 0x90abcd19;
imm32 r5, 0x10acef1b;
imm32 r6, 0x000c001d;
imm32 r7, 0x1246701f;
R2.H = R1.L * R0.L, R2.L = R1.L * R0.L;
R3.L = R1.L * R0.H (ISS2);
R4.H = R1.H * R0.L;
R5.H = R1.L * R0.H (M), R5.L = R1.H * R0.H;
R6.H = R1.H * R0.L, R6.L = R1.L * R0.L;
R7.H = R1.H * R0.H (M), R7.L = R1.H * R0.H;
CHECKREG r2, 0x36893689;
CHECKREG r3, 0x00068000;
CHECKREG r4, 0xDF89CD19;
CHECKREG r5, 0x36352001;
CHECKREG r6, 0xDF893689;
CHECKREG r7, 0xDFBB2001;
// test the signed integer U=0 I=1
imm32 r0, 0x8b235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3246725;
imm32 r3, 0x00060027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c002d;
imm32 r7, 0xd246702f;
R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (TFU);
R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (IS);
R4.H = R1.L * R0.L, R4.L = R1.H * R0.L (ISS2);
R5.H = R1.L * R0.L, R5.L = R1.H * R0.H (IS);
R6.H = R1.L * R0.H, R6.L = R1.L * R0.L (IS);
R7.H = R1.L * R0.H, R7.L = R1.L * R0.H (IH);
CHECKREG r0, 0x8B235625;
CHECKREG r1, 0x9FBA5127;
CHECKREG r2, 0x1B4E1B4E;
CHECKREG r3, 0x7FFF8000;
CHECKREG r4, 0x7FFF8000;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x80007FFF;
CHECKREG r7, 0xDAF4DAF4;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R0.H = R3.L * R2.H, R0.L = R3.H * R2.L (IS);
R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (ISS2);
R4.H = R3.H * R2.L, R4.L = R3.L * R2.L (IS);
R5.H = R3.H * R2.L, R5.L = R3.L * R2.H (IS);
R6.H = R3.H * R2.L, R6.L = R3.H * R2.L (IH);
R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (IS);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x1324B735;
CHECKREG r3, 0x90060037;
CHECKREG r4, 0x7FFF8000;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x1FD71FD7;
CHECKREG r7, 0x7FFF8000;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R0.H = R5.H * R4.H, R0.L = R5.L * R4.L (IS);
R1.H = R5.H * R4.H, R1.L = R5.L * R4.H (ISS2);
R2.H = R5.H * R4.H, R2.L = R5.H * R4.L (IS);
R3.H = R5.H * R4.H, R3.L = R5.H * R4.H (IS);
R4.H = R6.H * R7.L, R4.L = R6.H * R7.L (IH);
R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (IS);
CHECKREG r0, 0x80007FFF;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0xDCE8DCE8;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0xB00C005D;
CHECKREG r7, 0x1246705F;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
// test the unsigned U=1
R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (FU);
R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (ISS2);
R4.H = R7.L * R6.L, R4.L = R7.H * R6.L (FU);
R5.H = R3.L * R2.L (M), R5.L = R3.H * R2.H (FU);
R6.H = R5.L * R4.H, R6.L = R5.L * R4.L (TFU);
R7.H = R5.L * R4.H, R7.L = R5.L * R4.H (FU);
CHECKREG r0, 0xBB235666;
CHECKREG r1, 0xEFBA5166;
CHECKREG r2, 0x1B791B79;
CHECKREG r3, 0x7FFF8000;
CHECKREG r4, 0x4D7C0C98;
CHECKREG r5, 0xF2440DBC;
CHECKREG r6, 0x042800AC;
CHECKREG r7, 0x04280428;
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0.H = R5.L * R4.H, R0.L = R5.H * R4.L (FU);
R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (IU);
R2.H = R7.H * R6.L, R2.L = R7.L * R6.L (TFU);
R3.H = R5.H * R4.L, R3.L = R5.L * R4.H (FU);
R6.H = R1.H * R0.L, R6.L = R1.H * R0.L (IH);
R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (FU);
CHECKREG r0, 0x7E810D5A;
CHECKREG r1, 0x85FC72D8;
CHECKREG r2, 0x0000000C;
CHECKREG r3, 0x0D5A7E81;
CHECKREG r4, 0x90ABCD09;
CHECKREG r5, 0x10ACDFDB;
CHECKREG r6, 0xF9A3F9A3;
CHECKREG r7, 0x00010000;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R2.H = R1.H * R0.H, R2.L = R1.L * R0.L (TFU);
R3.H = R1.H * R0.L, R3.L = R1.L * R0.H (FU);
R4.H = R6.H * R7.H, R4.L = R6.H * R7.L (ISS2);
R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (FU);
CHECKREG r0, 0xAB235A75;
CHECKREG r1, 0xCFBA5127;
CHECKREG r2, 0x8ADD1CAC;
CHECKREG r3, 0x49663640;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x00EE0001;
CHECKREG r6, 0x000C0D0D;
CHECKREG r7, 0x1246700F;
// test the ROUNDING only on signed fraction T=1
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246700f;
R2.H = R1.L * R0.L (M), R2.L = R1.L * R0.H (IS);
R3.H = R1.H * R0.L (M), R3.L = R1.H * R0.H (FU);
R0.H = R3.L * R2.L (M), R0.L = R3.H * R2.H (T);
R1.H = R5.L * R4.H (M), R1.L = R5.L * R4.L (S2RND);
R4.H = R7.H * R6.H (M), R4.L = R7.L * R6.L (IU);
R5.H = R7.L * R6.H (M), R5.L = R7.H * R6.L (TFU);
R6.H = R5.H * R4.L (M), R6.L = R5.L * R4.H (ISS2);
R7.H = R3.L * R2.H (M), R7.L = R3.L * R2.L (IH);
CHECKREG r0, 0xC56FEFB2;
CHECKREG r1, 0xEDC10CDB;
CHECKREG r2, 0x7FFF8000;
CHECKREG r3, 0xEFB28ADE;
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x7FFF0000;
CHECKREG r7, 0xC56F3A91;
pass
|
stsp/binutils-ia16
| 10,799
|
sim/testsuite/bfin/se_loop_lr.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_lr/se_loop_lr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
LD32_LABEL(r0, l1e);
LSETUP ( l1e , l1e ) LC0 = P1;
l1s:LT0 = R0;
l1e:[ -- SP ] = R7;
LD32_LABEL(r0, ls1);
LSETUP ( l2s , l2e ) LC0 = P0;
l2s:LB0 = R0;
ls1:R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LD32_LABEL(r0, ls2);
LD32_LABEL(r1, ls3);
LSETUP ( l3s , l3e ) LC0 = P0;
l3s:LT0 = R0;
ls2:LB0 = R1;
ls3:R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LD32_LABEL(r0, ls4);
LD32_LABEL(r1, ls5);
LSETUP ( l4s , l4e ) LC0 = P0;
l4s:LT0 = R0;
LB0 = r1;
ls4:R7 += 3;
ls5:R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LD32_LABEL(r0, ls6);
LD32_LABEL(r1, ls7);
LSETUP ( l5s , l5e ) LC0 = P0;
l5s:LB0 = R1;
LT0 = r0;
ls6:R7 += 3;
R4 += 4;
R5 += 3;
ls7:R6 += 3;
l5e:[ -- SP ] = ( R7:4 );
LD32_LABEL(r0, ls8);
LD32_LABEL(r1, ls9);
LSETUP ( l6s , l6e ) LC0 = P0;
l6s:R5 += 1;
LB0 = r1;
LT0 = r0;
ls8:R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
ls9:R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
LD32_LABEL(r0, m1e);
LSETUP ( m1e , m1e ) LC1 = P1;
m1s:LT0 = R0;
m1e:[ -- SP ] = R7;
LD32_LABEL(r0, ms1);
LSETUP ( m2s , m2e ) LC1 = P0;
m2s:LB0 = R0;
ms1:R6 += 2;
m2e:[ -- SP ] = ( R7:5 );
LD32_LABEL(r0, ms2);
LD32_LABEL(r1, ms3);
LSETUP ( m3s , m3e ) LC1 = P0;
m3s:LT0 = R0;
ms2:LB0 = R1;
ms3:R7 += 3;
m3e:[ -- SP ] = ( R7:5 );
LD32_LABEL(r0, ms4);
LD32_LABEL(r1, ms5);
LSETUP ( m4s , m4e ) LC1 = P0;
m4s:LT0 = R0;
LB0 = r1;
ms4:R7 += 3;
ms5:R4 += 4;
m4e:[ -- SP ] = ( R7:4 );
LD32_LABEL(r0, ms6);
LD32_LABEL(r1, ms7);
LSETUP ( m5s , m5e ) LC1 = P0;
m5s:LB0 = R1;
LT0 = r0;
ms6:R7 += 3;
R4 += 4;
R5 += 3;
ms7:R6 += 3;
m5e:[ -- SP ] = ( R7:4 );
LD32_LABEL(r0, ms8);
LD32_LABEL(r1, ms9);
LSETUP ( m6s , m6e ) LC1 = P0;
m6s:R5 += 1;
LB0 = r1;
LT0 = r0;
ms8:R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
ms9:R7 += 5;
m6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 21,914
|
sim/testsuite/bfin/c_dsp32mac_a1a0_iuw32.s
|
//Original:/testcases/core/c_dsp32mac_a1a0_iuw32/c_dsp32mac_a1a0_iuw32.dsp
// Spec Reference: dsp32mac a1 a0 iuw32 MNOP
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the (signed integer: no ) I=1
imm32 r0, 0x22345628;
imm32 r1, 0x23456729;
imm32 r2, 0x3456782a;
imm32 r3, 0x45678922;
imm32 r4, 0x56789123;
imm32 r5, 0x67891224;
imm32 r6, 0xa1234527;
imm32 r7, 0xc1234567;
A1 = R0.L * R7.L, A0 = R0.L * R7.L (IS);
R0 = A0.w;
R7 = A1.w;
A1 = R6.L * R1.L, A0 += R6.L * R1.H (IS);
R6 = A0.w;
R1 = A1.w;
A1 += R2.L * R3.L, A0 = R2.H * R3.L (IS);
R2 = A0.w;
R3 = A1.w;
A1 += R5.L * R4.L, A0 += R5.H * R4.H (IS);
R5 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x175B7218;
CHECKREG r1, 0x1BDDC43F;
CHECKREG r2, 0xE7B2F96C;
CHECKREG r3, 0xE41233D3;
CHECKREG r4, 0xDC3712BF;
CHECKREG r5, 0x0AAB87A4;
CHECKREG r6, 0x20E26A9B;
CHECKREG r7, 0x175B7218;
imm32 r0, 0x13335678;
imm32 r1, 0x23436789;
imm32 r2, 0x3353789a;
imm32 r3, 0xa3638912;
imm32 r4, 0x53739123;
imm32 r5, 0x63831234;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234567;
A1 = R2.L * R7.H, A0 += R2.L * R7.L (IS);
R2 = A0.w;
R7 = A1.w;
A1 = R6.L * R1.H, A0 += R6.L * R1.H (IS);
R6 = A0.w;
R1 = A1.w;
A1 += R0.L * R5.H, A0 = R0.H * R5.L (IS);
R0 = A0.w;
R5 = A1.w;
A1 += R4.L * R3.H, A0 = R4.H * R3.H (IS);
R4 = A0.w;
R3 = A1.w;
CHECKREG r0, 0x015D7C5C;
CHECKREG r1, 0x098F3EF5;
CHECKREG r2, 0x2B5D8F9A;
CHECKREG r3, 0x53474FE6;
CHECKREG r4, 0xE1CF7E79;
CHECKREG r5, 0x2B2BE65D;
CHECKREG r6, 0x34ECCE8F;
CHECKREG r7, 0xE262970E;
imm32 r0, 0x14345678;
imm32 r1, 0x24456789;
imm32 r2, 0x3456789a;
imm32 r3, 0x44678912;
imm32 r4, 0x54789123;
imm32 r5, 0x67891244;
imm32 r6, 0xa1234547;
imm32 r7, 0xc1234547;
A1 += R4.H * R0.L, A0 = R4.L * R0.L (IS);
R4 = A0.w;
R0 = A1.w;
A1 = R3.H * R1.L, A0 += R3.L * R1.H (IS);
R3 = A0.w;
R1 = A1.w;
A1 = R2.H * R6.L, A0 = R2.H * R6.L (IS);
R2 = A0.w;
R6 = A1.w;
A1 += R7.H * R5.L, A0 += R7.H * R5.H (IS);
R7 = A0.w;
R5 = A1.w;
CHECKREG r0, 0x6FCF3826;
CHECKREG r1, 0x1BAA0C1F;
CHECKREG r2, 0x0E29B1DA;
CHECKREG r3, 0xC9B44442;
CHECKREG r4, 0xDA8DCA68;
CHECKREG r5, 0x09AD7526;
CHECKREG r6, 0x0E29B1DA;
CHECKREG r7, 0xF4BD2295;
imm32 r0, 0x15345678;
imm32 r1, 0x23556789;
imm32 r2, 0x3455789a;
imm32 r3, 0x45675912;
imm32 r4, 0x56789523;
imm32 r5, 0x67891234;
imm32 r6, 0xa1234557;
imm32 r7, 0xc1234565;
A1 += R0.H * R1.H, A0 = R0.L * R1.L (IS);
R0 = A0.w;
R1 = A1.w;
A1 = R5.H * R6.H, A0 = R5.L * R6.H (IS);
R5 = A0.w;
R6 = A1.w;
A1 = R4.H * R3.H, A0 += R4.H * R3.L (IS);
R4 = A0.w;
R3 = A1.w;
A1 = R2.H * R7.H, A0 = R2.H * R7.H (IS);
R2 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x22F88E38;
CHECKREG r1, 0x0C9A9B6A;
CHECKREG r2, 0xF3263C9F;
CHECKREG r3, 0x17712248;
CHECKREG r4, 0x1756FD8C;
CHECKREG r5, 0xF941311C;
CHECKREG r6, 0xD9A250BB;
CHECKREG r7, 0xF3263C9F;
// test the (unsigned or integer :no ) U=1
imm32 r0, 0x62345678;
imm32 r1, 0x26456789;
imm32 r2, 0x3466789a;
imm32 r3, 0x45668912;
imm32 r4, 0x56786123;
imm32 r5, 0x67891634;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234566;
A1 = R0.L * R2.L, A0 = R0.L * R2.L (FU);
R0 = A0.w;
R2 = A1.w;
A1 = R1.L * R3.L, A0 += R1.L * R3.H (FU);
R1 = A0.w;
R3 = A1.w;
A1 += R4.L * R6.L, A0 = R4.H * R6.L (FU);
R4 = A0.w;
R6 = A1.w;
A1 += R5.L * R7.L, A0 += R5.H * R7.H (FU);
R5 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x28BC4430;
CHECKREG r1, 0x44CD71C6;
CHECKREG r2, 0x28BC4430;
CHECKREG r3, 0x376F98A2;
CHECKREG r4, 0x17712248;
CHECKREG r5, 0x658D9303;
CHECKREG r6, 0x51C51CB7;
CHECKREG r7, 0x57C9F96F;
imm32 r0, 0x12345678;
imm32 r1, 0x73456789;
imm32 r2, 0x8456789a;
imm32 r3, 0x49998912;
imm32 r4, 0x56782123;
imm32 r5, 0x67891234;
imm32 r6, 0xa1234577;
imm32 r7, 0xc1234567;
A1 = R2.L * R3.H, A0 = R2.L * R3.L (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R0.L * R1.H, A0 = R0.L * R1.H (FU);
R0 = A0.w;
R1 = A1.w;
A1 += R4.L * R5.H, A0 = R4.H * R5.L (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R7.L * R6.H, A0 += R7.H * R6.H (FU);
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x26EF3658;
CHECKREG r1, 0x26EF3658;
CHECKREG r2, 0x4092E4D4;
CHECKREG r3, 0x22ABFE0A;
CHECKREG r4, 0x06260060;
CHECKREG r5, 0x34560713;
CHECKREG r6, 0x7FB76B29;
CHECKREG r7, 0x2BAF4415;
imm32 r0, 0x1234567a;
imm32 r1, 0x2345678a;
imm32 r2, 0x3456a89a;
imm32 r3, 0x4a678912;
imm32 r4, 0xa6789123;
imm32 r5, 0xc7891234;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234567;
A1 = R5.H * R4.L, A0 = R5.L * R4.L (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R3.H * R2.L, A0 = R3.L * R2.H (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R1.H * R0.L, A0 = R1.H * R0.L (FU);
R0 = A0.w;
R1 = A1.w;
A1 = R7.H * R6.L, A0 = R7.H * R6.H (FU);
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x0BE9FCE2;
CHECKREG r1, 0x0BE9FCE2;
CHECKREG r2, 0x1C05B40C;
CHECKREG r3, 0x310059F6;
CHECKREG r4, 0x0A51F11C;
CHECKREG r5, 0x711FE0BB;
CHECKREG r6, 0x79916AC9;
CHECKREG r7, 0x345C2415;
imm32 r0, 0xb2345678;
imm32 r1, 0x2b456789;
imm32 r2, 0x34b6789a;
imm32 r3, 0xc56b8912;
imm32 r4, 0x5c78b123;
imm32 r5, 0x67c91b34;
imm32 r6, 0xa12345b7;
imm32 r7, 0xc123456b;
A1 = R6.H * R7.H, A0 = R6.L * R7.L (FU);
R6 = A0.w;
R7 = A1.w;
A1 = R5.H * R4.H, A0 = R5.L * R4.H (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R2.H * R3.H, A0 = R2.H * R3.L (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R0.H * R1.H, A0 = R0.H * R1.H (FU);
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x1E1EC404;
CHECKREG r1, 0x1E1EC404;
CHECKREG r2, 0x1C391ACC;
CHECKREG r3, 0x28A61612;
CHECKREG r4, 0x09D37060;
CHECKREG r5, 0x257CE238;
CHECKREG r6, 0x12E7767D;
CHECKREG r7, 0x79916AC9;
// Test w32
imm32 r0, 0x123df178;
imm32 r1, 0x2245e189;
imm32 r2, 0x3256719a;
imm32 r3, 0x42678112;
imm32 r4, 0xa2789123;
imm32 r5, 0x62891134;
imm32 r6, 0xa2b34167;
imm32 r7, 0xc22d4167;
A1 = R0.L * R4.L, A0 += R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.L * R5.L, A0 += R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.L * R6.L, A0 += R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.L * R4.L, A0 += R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x2AB4BAD4;
CHECKREG r1, 0x13410376;
CHECKREG r2, 0x2CF930AA;
CHECKREG r3, 0x33802490;
CHECKREG r4, 0x091C5540;
CHECKREG r5, 0xFBE7D1A8;
CHECKREG r6, 0x3A0B9DEC;
CHECKREG r7, 0xC22D4167;
imm32 r0, 0x553df344;
imm32 r1, 0x2525e349;
imm32 r2, 0x3252734a;
imm32 r3, 0x42658342;
imm32 r4, 0xa5789343;
imm32 r5, 0x63591344;
imm32 r6, 0xa3b54347;
imm32 r7, 0xc32d4347;
A1 += R0.L * R4.H, A0 = R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 += R1.L * R5.H, A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.L * R6.H, A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 += R3.L * R4.H, A0 = R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x0AD16D98;
CHECKREG r1, 0xE9B67EC2;
CHECKREG r2, 0x1A72D57C;
CHECKREG r3, 0x0965C3AC;
CHECKREG r4, 0x970BD9DE;
CHECKREG r5, 0xFBD48BC2;
CHECKREG r6, 0xA8B3CE66;
CHECKREG r7, 0xC32D4347;
imm32 r0, 0x163df678;
imm32 r1, 0x2625e689;
imm32 r2, 0x3652769a;
imm32 r3, 0x46628612;
imm32 r4, 0xa6789623;
imm32 r5, 0x63691634;
imm32 r6, 0xa3634367;
imm32 r7, 0xc3264667;
A1 += R0.H * R4.L, A0 = R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.H * R5.L, A0 += R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.L, A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 += R3.H * R4.L, A0 += R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x07E204D0;
CHECKREG r1, 0xF41B1732;
CHECKREG r2, 0x1C9AA1FC;
CHECKREG r3, 0xD8C785D8;
CHECKREG r4, 0x5DCEA034;
CHECKREG r5, 0x069DDB08;
CHECKREG r6, 0x23387D04;
CHECKREG r7, 0xC3264667;
imm32 r0, 0x123df378;
imm32 r1, 0x2225e389;
imm32 r2, 0x3252739a;
imm32 r3, 0x42628312;
imm32 r4, 0xa3789323;
imm32 r5, 0x63891334;
imm32 r6, 0xa3b34367;
imm32 r7, 0xc32d4367;
A1 += R0.H * R4.H, A0 = R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.H * R5.H, A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.H, A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R4.H, A0 = R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x0AA862D0;
CHECKREG r1, 0xE9DD7EA2;
CHECKREG r2, 0x1A7F69FC;
CHECKREG r3, 0x29CFB5BC;
CHECKREG r4, 0x29CFB5BC;
CHECKREG r5, 0x1A8D299A;
CHECKREG r6, 0xF643F446;
CHECKREG r7, 0xC32D4367;
imm32 r0, 0x123df678;
imm32 r1, 0x2345e789;
imm32 r2, 0x34567b9a;
imm32 r3, 0x45678c12;
imm32 r4, 0xa6789123;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1b34567;
imm32 r7, 0xc12d4567;
A1 = R0.H * R4.L, A0 = R0.H * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.H * R5.L, A0 = R1.H * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.H * R6.H, A0 = R2.L * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R4.H, A0 = R3.L * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF03416AE;
CHECKREG r1, 0x1DE7F7DA;
CHECKREG r2, 0x430479EC;
CHECKREG r3, 0x0E4EA750;
CHECKREG r4, 0xF76F51D8;
CHECKREG r5, 0x05040808;
CHECKREG r6, 0xD9715C44;
CHECKREG r7, 0xC12D4567;
// MNOP & w32
imm32 r0, 0x623df17a;
imm32 r1, 0x7245e18b;
imm32 r2, 0x8256719a;
imm32 r3, 0x92678112;
imm32 r4, 0xa2789123;
imm32 r5, 0xb2891134;
imm32 r6, 0xc2b34167;
imm32 r7, 0xd22d4167;
A0 += R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A0 += R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A0 = R3.H * R7.H (W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x1AE2E2AC;
CHECKREG r1, 0x126EB2C6;
CHECKREG r2, 0xD2393FFA;
CHECKREG r3, 0x273C7436;
CHECKREG r4, 0xF76F51D8;
CHECKREG r5, 0xF76F51D8;
CHECKREG r6, 0xF76F51D8;
CHECKREG r7, 0xF76F51D8;
imm32 r0, 0xa23df17a;
imm32 r1, 0x7b45e18b;
imm32 r2, 0x82c6719a;
imm32 r3, 0x126d8112;
imm32 r4, 0xc278e123;
imm32 r5, 0xb2491f34;
imm32 r6, 0x89b54167;
imm32 r7, 0xd25d6767;
A1 += R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R7.H (W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x273C7436;
CHECKREG r1, 0x273C7436;
CHECKREG r2, 0x273C7436;
CHECKREG r3, 0x273C7436;
CHECKREG r4, 0xFAEFCD34;
CHECKREG r5, 0x127DED46;
CHECKREG r6, 0xD281B49A;
CHECKREG r7, 0xF96E3732;
// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is
// signed, the other input is unsigned
imm32 r0, 0x22345628;
imm32 r1, 0x23456729;
imm32 r2, 0x3456782a;
imm32 r3, 0x45678922;
imm32 r4, 0x56789123;
imm32 r5, 0x67891224;
imm32 r6, 0xa1234527;
imm32 r7, 0xc1234567;
A1 += R0.L * R7.L (M), A0 = R0.L * R7.L (IS);
R0 = A0.w;
R7 = A1.w;
A1 = R6.L * R1.L (M), A0 += R6.L * R1.H (IS);
R6 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.L (M), A0 = R2.H * R3.L (IS);
R2 = A0.w;
R3 = A1.w;
A1 += R5.L * R4.L (M), A0 += R5.H * R4.H (IS);
R5 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x175B7218;
CHECKREG r1, 0x1BDDC43F;
CHECKREG r2, 0xE7B2F96C;
CHECKREG r3, 0x405E6F94;
CHECKREG r4, 0x4AA74E80;
CHECKREG r5, 0x0AAB87A4;
CHECKREG r6, 0x20E26A9B;
CHECKREG r7, 0x10C9A94A;
imm32 r0, 0x13335678;
imm32 r1, 0x23436789;
imm32 r2, 0x3353789a;
imm32 r3, 0xa3638912;
imm32 r4, 0x53739123;
imm32 r5, 0x63831234;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234567;
A1 += R2.L * R7.H (M), A0 = R2.L * R7.L (IS);
R2 = A0.w;
R7 = A1.w;
A1 = R6.L * R1.H (M), A0 = R6.L * R1.H (IS);
R6 = A0.w;
R1 = A1.w;
A1 += R0.L * R5.H (M), A0 = R0.H * R5.L (IS);
R0 = A0.w;
R5 = A1.w;
A1 = R4.L * R3.H (M), A0 += R4.H * R3.H (IS);
R4 = A0.w;
R3 = A1.w;
CHECKREG r0, 0x015D7C5C;
CHECKREG r1, 0x098F3EF5;
CHECKREG r2, 0x20B207F6;
CHECKREG r3, 0xB93E6989;
CHECKREG r4, 0xE32CFAD5;
CHECKREG r5, 0x2B2BE65D;
CHECKREG r6, 0x098F3EF5;
CHECKREG r7, 0xA5A3E58E;
imm32 r0, 0x14345678;
imm32 r1, 0x24456789;
imm32 r2, 0x3456789a;
imm32 r3, 0x44678912;
imm32 r4, 0x54789123;
imm32 r5, 0x67891244;
imm32 r6, 0xa1234547;
imm32 r7, 0xc1234547;
A1 = R4.H * R0.L (M), A0 = R4.L * R0.L (IS);
R4 = A0.w;
R0 = A1.w;
A1 = R3.H * R1.L (M), A0 = R3.L * R1.H (IS);
R3 = A0.w;
R1 = A1.w;
A1 = R2.H * R6.L (M), A0 = R2.H * R6.L (IS);
R2 = A0.w;
R6 = A1.w;
A1 = R7.H * R5.L (M), A0 = R7.H * R5.H (IS);
R7 = A0.w;
R5 = A1.w;
CHECKREG r0, 0x1C87E840;
CHECKREG r1, 0x1BAA0C1F;
CHECKREG r2, 0x0E29B1DA;
CHECKREG r3, 0xEF2679DA;
CHECKREG r4, 0xDA8DCA68;
CHECKREG r5, 0xFB83C34C;
CHECKREG r6, 0x0E29B1DA;
CHECKREG r7, 0xE69370BB;
imm32 r0, 0x15345678;
imm32 r1, 0x23556789;
imm32 r2, 0x3455789a;
imm32 r3, 0x45675912;
imm32 r4, 0x56789523;
imm32 r5, 0x67891234;
imm32 r6, 0xa1234557;
imm32 r7, 0xc1234565;
A1 = R0.H * R1.H (M), A0 = R0.L * R1.L (IS);
R0 = A0.w;
R1 = A1.w;
A1 = R5.H * R6.H (M), A0 = R5.L * R6.H (IS);
R5 = A0.w;
R6 = A1.w;
A1 += R4.H * R3.H (M), A0 = R4.H * R3.L (IS);
R4 = A0.w;
R3 = A1.w;
A1 += R2.H * R7.H (M), A0 = R2.H * R7.H (IS);
R2 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x22F88E38;
CHECKREG r1, 0x02ED2644;
CHECKREG r2, 0xF3263C9F;
CHECKREG r3, 0x589C7303;
CHECKREG r4, 0x1E15CC70;
CHECKREG r5, 0xF941311C;
CHECKREG r6, 0x412B50BB;
CHECKREG r7, 0x8017AFA2;
// test the (unsigned or integer :no ) U=1
imm32 r0, 0x62345678;
imm32 r1, 0x26456789;
imm32 r2, 0x3466789a;
imm32 r3, 0x45668912;
imm32 r4, 0x56786123;
imm32 r5, 0x67891634;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234566;
A1 = R0.L * R2.L (M), A0 = R0.L * R2.L (FU);
R0 = A0.w;
R2 = A1.w;
A1 += R1.L * R3.L (M), A0 = R1.L * R3.H (FU);
R1 = A0.w;
R3 = A1.w;
A1 = R4.L * R6.L (M), A0 = R4.H * R6.L (FU);
R4 = A0.w;
R6 = A1.w;
A1 += R5.L * R7.L (M), A0 = R5.H * R7.H (FU);
R5 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x28BC4430;
CHECKREG r1, 0x1C112D96;
CHECKREG r2, 0x28BC4430;
CHECKREG r3, 0x602BDCD2;
CHECKREG r4, 0x17712248;
CHECKREG r5, 0x4E1C70BB;
CHECKREG r6, 0x1A558415;
CHECKREG r7, 0x205A60CD;
imm32 r0, 0x12345678;
imm32 r1, 0x73456789;
imm32 r2, 0x8456789a;
imm32 r3, 0x49998912;
imm32 r4, 0x56782123;
imm32 r5, 0x67891234;
imm32 r6, 0xa1234577;
imm32 r7, 0xc1234567;
A1 = R2.L * R3.H (M), A0 = R2.L * R3.L (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R0.L * R1.H (M), A0 = R0.L * R1.H (FU);
R0 = A0.w;
R1 = A1.w;
A1 = R4.L * R5.H (M), A0 = R4.H * R5.L (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R7.L * R6.H (M), A0 = R7.H * R6.H (FU);
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x26EF3658;
CHECKREG r1, 0x26EF3658;
CHECKREG r2, 0x4092E4D4;
CHECKREG r3, 0x22ABFE0A;
CHECKREG r4, 0x06260060;
CHECKREG r5, 0x0D66D0BB;
CHECKREG r6, 0x79916AC9;
CHECKREG r7, 0x2BAF4415;
imm32 r0, 0x1234567a;
imm32 r1, 0x2345678a;
imm32 r2, 0x3456a89a;
imm32 r3, 0x4a678912;
imm32 r4, 0xa6789123;
imm32 r5, 0xc7891234;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234567;
A1 = R5.H * R4.L (M), A0 += R5.L * R4.L (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R3.H * R2.L (M), A0 = R3.L * R2.H (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R1.H * R0.L (M), A0 += R1.H * R0.L (FU);
R0 = A0.w;
R1 = A1.w;
A1 = R7.H * R6.L (M), A0 = R7.H * R6.H (FU);
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x27EFB0EE;
CHECKREG r1, 0x0BE9FCE2;
CHECKREG r2, 0x1C05B40C;
CHECKREG r3, 0x310059F6;
CHECKREG r4, 0x83E35BE5;
CHECKREG r5, 0xDFFCE0BB;
CHECKREG r6, 0x79916AC9;
CHECKREG r7, 0xEEF52415;
imm32 r0, 0xb2345678;
imm32 r1, 0x2b456789;
imm32 r2, 0x34b6789a;
imm32 r3, 0xc56b8912;
imm32 r4, 0x5c78b123;
imm32 r5, 0x67c91b34;
imm32 r6, 0xa12345b7;
imm32 r7, 0xc123456b;
A1 += R6.H * R7.H (M), A0 = R6.L * R7.L (FU);
R6 = A0.w;
R7 = A1.w;
A1 += R5.H * R4.H (M), A0 = R5.L * R4.H (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R2.H * R3.H (M), A0 += R2.H * R3.L (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R0.H * R1.H (M), A0 += R0.H * R1.H (FU);
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x442B4F30;
CHECKREG r1, 0xF2D9C404;
CHECKREG r2, 0x260C8B2C;
CHECKREG r3, 0x28A61612;
CHECKREG r4, 0x09D37060;
CHECKREG r5, 0xCCE07116;
CHECKREG r6, 0x12E7767D;
CHECKREG r7, 0xA7638EDE;
// Test w32
imm32 r0, 0x123df178;
imm32 r1, 0x2245e189;
imm32 r2, 0x3256719a;
imm32 r3, 0x42678112;
imm32 r4, 0xa2789123;
imm32 r5, 0x62891134;
imm32 r6, 0xa2b34167;
imm32 r7, 0xc22d4167;
A1 = R0.L * R7.L (M), A0 = R0.L * R7.L (W32);
R0 = A0.w;
R7 = A1.w;
A1 += R1.L * R5.L (M), A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.L * R6.L (M), A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 += R3.L * R4.L (M), A0 = R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF8933E90;
CHECKREG r1, 0xE88C48A2;
CHECKREG r2, 0x19B82D34;
CHECKREG r3, 0xCF7A9C90;
CHECKREG r4, 0xD50FA66C;
CHECKREG r5, 0xFA3D881C;
CHECKREG r6, 0x1D05CEF6;
CHECKREG r7, 0xFC499F48;
imm32 r0, 0x553df344;
imm32 r1, 0x2525e349;
imm32 r2, 0x3252734a;
imm32 r3, 0x42658342;
imm32 r4, 0xa5789343;
imm32 r5, 0x63591344;
imm32 r6, 0xa3b54347;
imm32 r7, 0xc32d4347;
A1 = R0.L * R7.H (M), A0 = R0.L * R7.L (W32);
R0 = A0.w;
R7 = A1.w;
A1 = R1.L * R5.H (M), A0 += R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.L * R6.H (M), A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.L * R4.H (M), A0 += R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF94E87B8;
CHECKREG r1, 0xE305067A;
CHECKREG r2, 0x1A72D57C;
CHECKREG r3, 0xEB7D462C;
CHECKREG r4, 0xAF5F10F0;
CHECKREG r5, 0xF4DB3F61;
CHECKREG r6, 0x49B9A152;
CHECKREG r7, 0xF64A8EF4;
imm32 r0, 0x163df678;
imm32 r1, 0x2625e689;
imm32 r2, 0x3652769a;
imm32 r3, 0x46628612;
imm32 r4, 0xa6789623;
imm32 r5, 0x63691634;
imm32 r6, 0xa3634367;
imm32 r7, 0xc3264667;
A1 = R0.H * R7.L (M), A0 = R0.L * R7.L (W32);
R0 = A0.w;
R7 = A1.w;
A1 = R1.H * R5.L (M), A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.L (M), A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R4.L (M), A0 = R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xFAC1F490;
CHECKREG r1, 0xEC391262;
CHECKREG r2, 0x1C9AA1FC;
CHECKREG r3, 0xCEC513E0;
CHECKREG r4, 0x29470B66;
CHECKREG r5, 0x034EED84;
CHECKREG r6, 0x119C3E82;
CHECKREG r7, 0x061DA08B;
imm32 r0, 0x123df378;
imm32 r1, 0x2225e389;
imm32 r2, 0x3252739a;
imm32 r3, 0x42628312;
imm32 r4, 0xa3789323;
imm32 r5, 0x63891334;
imm32 r6, 0xa3b34367;
imm32 r7, 0xc32d4367;
A1 = R0.H * R7.H (M), A0 = R0.L * R7.L (W32);
R0 = A0.w;
R7 = A1.w;
A1 = R1.H * R5.H (M), A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.H (M), A0 += R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 += R3.H * R4.H (M), A0 += R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF966BA90;
CHECKREG r1, 0xE9DD7EA2;
CHECKREG r2, 0x045CE89E;
CHECKREG r3, 0xD45FF07E;
CHECKREG r4, 0x57D77E13;
CHECKREG r5, 0x0D4694CD;
CHECKREG r6, 0x2D73FA23;
CHECKREG r7, 0x0DE7ABB9;
imm32 r0, 0x123df678;
imm32 r1, 0x2345e789;
imm32 r2, 0x34567b9a;
imm32 r3, 0x45678c12;
imm32 r4, 0xa6789123;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1b34567;
imm32 r7, 0xc12d4567;
A1 = R0.H * R4.L (M), A0 = R0.H * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.H * R5.L (M), A0 = R1.H * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.H * R6.H (M), A0 = R2.L * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R4.H (M), A0 = R3.L * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF03416AE;
CHECKREG r1, 0x1DE7F7DA;
CHECKREG r2, 0x430479EC;
CHECKREG r3, 0xF6A29C3C;
CHECKREG r4, 0x02CD9C01;
CHECKREG r5, 0x02820404;
CHECKREG r6, 0x210EAE22;
CHECKREG r7, 0xC12D4567;
// MNOP & w32
imm32 r0, 0x623df17a;
imm32 r1, 0x7245e18b;
imm32 r2, 0x8256719a;
imm32 r3, 0x92678112;
imm32 r4, 0xa2789123;
imm32 r5, 0xb2891134;
imm32 r6, 0xc2b34167;
imm32 r7, 0xd22d4167;
A0 = R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A0 += R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A0 += R3.H * R7.H (W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x0C943B5C;
CHECKREG r1, 0x1F02EE22;
CHECKREG r2, 0xBFCA8D34;
CHECKREG r3, 0xE707016A;
CHECKREG r4, 0x02CD9C01;
CHECKREG r5, 0x02CD9C01;
CHECKREG r6, 0x02CD9C01;
CHECKREG r7, 0x02CD9C01;
imm32 r0, 0xa23df17a;
imm32 r1, 0x7b45e18b;
imm32 r2, 0x82c6719a;
imm32 r3, 0x126d8112;
imm32 r4, 0xc278e123;
imm32 r5, 0xb2491f34;
imm32 r6, 0x89b54167;
imm32 r7, 0xd25d6767;
A1 += R0.L * R4.L (M,W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.L * R5.H (M,W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.L (M,W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R7.H (M,W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0xE707016A;
CHECKREG r1, 0xE707016A;
CHECKREG r2, 0xE707016A;
CHECKREG r3, 0xE707016A;
CHECKREG r4, 0xF607D9AF;
CHECKREG r5, 0xEAC9F6A3;
CHECKREG r6, 0xCACBDA4D;
CHECKREG r7, 0x0F241B99;
imm32 r0, 0x123df678;
imm32 r1, 0x2345e789;
imm32 r2, 0x34567b9a;
imm32 r3, 0x45678c12;
imm32 r4, 0xa6789123;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1b34567;
imm32 r7, 0xc12d4567;
A1 -= R0.H * R4.L (M), A0 += R0.H * R4.L (IS);
R0 = A0.w;
R4 = A1.w;
A1 -= R1.H * R5.L (M), A0 -= R1.H * R5.H (FU);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.H (M), A0 -= R2.L * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 -= R3.H * R4.H (M), A0 -= R3.L * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xDF210CC1;
CHECKREG r1, 0xD02D10D4;
CHECKREG r2, 0x8D2896E8;
CHECKREG r3, 0x9181B214;
CHECKREG r4, 0x220C8AE5;
CHECKREG r5, 0x024B0C3E;
CHECKREG r6, 0x2359BA60;
CHECKREG r7, 0xC12D4567;
imm32 r0, 0x123df678;
imm32 r1, 0x2345e789;
imm32 r2, 0x34567b9a;
imm32 r3, 0x45678c12;
imm32 r4, 0xa6789123;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1b34567;
imm32 r7, 0xc12d4567;
A1 -= R0.H * R4.L (M), A0 = R0.H * R4.L (IS);
R0 = A0.w;
R4 = A1.w;
A1 -= R1.H * R5.L (M), A0 = R1.H * R5.H (FU);
R1 = A0.w;
R5 = A1.w;
A1 -= R2.H * R6.H (M), A0 = R2.L * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 -= R3.H * R4.H (M), A0 = R3.L * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF81A0B57;
CHECKREG r1, 0x0EF3FBED;
CHECKREG r2, 0x430479EC;
CHECKREG r3, 0xEA874D74;
CHECKREG r4, 0xEDB77A95;
CHECKREG r5, 0x15337B8A;
CHECKREG r6, 0xF424CD68;
CHECKREG r7, 0xC12D4567;
// MNOP & w32
imm32 r0, 0x623df17a;
imm32 r1, 0x7245e18b;
imm32 r2, 0x8256719a;
imm32 r3, 0x92678112;
imm32 r4, 0xa2789123;
imm32 r5, 0xb2891134;
imm32 r6, 0xc2b34167;
imm32 r7, 0xd22d4167;
A0 -= R0.L * R4.L (IS);
R0 = A0.w;
R4 = A1.w;
A0 -= R1.L * R5.H (FU);
R1 = A0.w;
R5 = A1.w;
A0 -= R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A0 -= R3.H * R7.H (W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0xE43D2FC6;
CHECKREG r1, 0x46F1D663;
CHECKREG r2, 0x8727492F;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xEDB77A95;
CHECKREG r5, 0xEDB77A95;
CHECKREG r6, 0xEDB77A95;
CHECKREG r7, 0xEDB77A95;
imm32 r0, 0xa23df17a;
imm32 r1, 0x7b45e18b;
imm32 r2, 0x82c6719a;
imm32 r3, 0x126d8112;
imm32 r4, 0xc278e123;
imm32 r5, 0xb2491f34;
imm32 r6, 0x89b54167;
imm32 r7, 0xd25d6767;
A1 -= R0.L * R4.L (M,IS);
R0 = A0.w;
R4 = A1.w;
A1 -= R1.L * R5.H (M,FU);
R1 = A0.w;
R5 = A1.w;
A1 -= R2.H * R6.L (M,W32);
R2 = A0.w;
R6 = A1.w;
A1 -= R3.H * R7.H (M,FU);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xFA7D3CE7;
CHECKREG r5, 0x0FB34644;
CHECKREG r6, 0x2FB1629A;
CHECKREG r7, 0x208D4701;
pass
|
stsp/binutils-ia16
| 5,401
|
sim/testsuite/bfin/c_ccflag_dr_dr.s
|
//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr/c_ccflag_dr_dr.dsp
// Spec Reference: ccflags dr-dr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00110022;
imm32 r1, 0x00110022;
imm32 r2, 0x00330044;
imm32 r3, 0x00550066;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, 0x00000000;
ASTAT = R7;
R4 = ASTAT;
// positive dreg-1 EQUAL to positive dreg-2
CC = R0 == R1;
R5 = ASTAT;
CC = R0 < R1;
R6 = ASTAT;
CC = R0 <= R1;
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001025;
CHECKREG r6, 0x00001005;
CHECKREG r7, 0x00001025;
CC = R0 < R1;
R4 = ASTAT;
CC = R0 <= R1 (IU);
R5 = ASTAT;
CHECKREG r4, 0x00001005;
CHECKREG r5, 0x00001025;
// positive dreg-1 GREATER than positive dreg-2
CC = R3 == R2;
R5 = ASTAT;
CC = R3 < R2;
R6 = ASTAT;
CC = R3 <= R2;
R7 = ASTAT;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
CC = R3 < R2 (IU);
R4 = ASTAT;
CC = R3 <= R2 (IU);
R5 = ASTAT;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001004;
// positive dreg-1 LESS than positive dreg-2
CC = R2 == R3;
R5 = ASTAT;
CC = R2 < R3;
R6 = ASTAT;
CC = R2 <= R3;
R7 = ASTAT;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
CC = R2 < R3;
R4 = ASTAT;
CC = R2 <= R3;
R5 = ASTAT;
CHECKREG r4, 0x00000022;
CHECKREG r5, 0x00000022;
imm32 r0, 0x01230123;
imm32 r1, 0x81230123;
imm32 r2, 0x04560456;
imm32 r3, 0x87890789;
// operate on negative number
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
// positive dreg-1 GREATER than negative dreg-2
CC = R0 == R1;
R5 = ASTAT;
CC = R0 < R1;
R6 = ASTAT;
CC = R0 <= R1;
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// negative dreg-1 LESS than POSITIVE dreg-2 small
CC = R3 == R2;
R5 = ASTAT;
CC = R3 < R2;
R6 = ASTAT;
CC = R3 <= R2;
R7 = ASTAT;
CHECKREG r5, 0x00001006;
CHECKREG r6, 0x00001026;
CHECKREG r7, 0x00001026;
// negative dreg-1 GREATER than negative dreg-2
CC = R1 == R3;
R5 = ASTAT;
CC = R1 < R3;
R6 = ASTAT;
CC = R1 <= R3;
R7 = ASTAT;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
// negative dreg-1 LESS than negative dreg-2
CC = R3 == R1;
R5 = ASTAT;
CC = R3 < R1;
R6 = ASTAT;
CC = R3 <= R1;
R7 = ASTAT;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
imm32 r0, 0x80230123;
imm32 r1, 0x00230123;
imm32 r2, 0x80560056;
imm32 r3, 0x00890089;
// operate on negative number
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
// negative dreg-1 LESS than POSITIVE dreg-2
CC = R2 == R3;
R5 = ASTAT;
CC = R2 < R3;
R6 = ASTAT;
CC = R2 <= R3;
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001006; // overflow and carry but not negative
CHECKREG r6, 0x00001026; // cc overflow, carry and negative
CHECKREG r7, 0x00001026;
imm32 r4, 0x44444444;
imm32 r5, 0x55555555;
imm32 r6, 0x66666666;
imm32 r7, 0x77777777;
imm32 r0, 0x00000000;
imm32 r1, 0x11111111;
imm32 r2, 0x22222222;
imm32 r3, 0x33333333;
ASTAT = R0;
R3 = ASTAT;
NOP;
CHECKREG r3, 0x00000000;
// positive dreg-1 EQUAL to positive dreg-2
CC = R4 == R5;
R0 = ASTAT;
CC = R4 < R5;
R1 = ASTAT;
CC = R4 <= R5;
R2 = ASTAT;
CC = R4 < R5;
R3 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CC = R4 <= R5;
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00000022;
// positive dreg-1 GREATER than positive dreg-2
CC = R7 == R6;
R0 = ASTAT;
CC = R7 < R6;
R1 = ASTAT;
CC = R7 <= R6;
R2 = ASTAT;
CC = R7 < R6;
R3 = ASTAT;
CHECKREG r0, 0x00001004;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
CC = R7 <= R6 (IU);
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00001004;
// positive dreg-1 LESS than positive dreg-2
CC = R6 == R7;
R0 = ASTAT;
CC = R6 < R7;
R1 = ASTAT;
CC = R6 <= R7;
R2 = ASTAT;
CC = R6 < R7;
R3 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CC = R6 <= R7;
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00000022;
imm32 r4, 0x01230123;
imm32 r5, 0x81230123;
imm32 r6, 0x04560456;
imm32 r7, 0x87890789;
// operate on negative number
R0 = 0;
ASTAT = R0;
R3 = ASTAT;
CHECKREG r3, 0x00000000;
// positive dreg-1 GREATER than negative dreg-2
CC = R4 == R5;
R1 = ASTAT;
CC = R4 < R5;
R2 = ASTAT;
CC = R4 <= R5;
R3 = ASTAT;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
// negative dreg-1 LESS than POSITIVE dreg-2 small
CC = R7 == R6;
R0 = ASTAT;
CC = R7 < R6;
R1 = ASTAT;
CC = R7 <= R6;
R2 = ASTAT;
CHECKREG r0, 0x00001006;
CHECKREG r1, 0x00001026;
CHECKREG r2, 0x00001026;
// negative dreg-1 GREATER than negative dreg-2
CC = R5 == R7;
R0 = ASTAT;
CC = R5 < R7;
R1 = ASTAT;
CC = R5 <= R7;
R2 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
// negative dreg-1 LESS than negative dreg-2
CC = R7 == R5;
R1 = ASTAT;
CC = R7 < R5;
R2 = ASTAT;
CC = R7 <= R5;
R3 = ASTAT;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
imm32 r4, 0x80230123;
imm32 r5, 0x00230123;
imm32 r6, 0x80560056;
imm32 r7, 0x00890089;
// operate on negative number
R3 = 0;
ASTAT = R3;
R0 = ASTAT;
// negative dreg-1 LESS than POSITIVE dreg-2
CC = R6 == R7;
R1 = ASTAT;
CC = R6 < R7;
R2 = ASTAT;
CC = R6 <= R7;
R3 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001006; // overflow and carry but not negative
CHECKREG r2, 0x00001026; // cc overflow, carry and negative
CHECKREG r3, 0x00001026;
pass;
|
stsp/binutils-ia16
| 2,330
|
sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_s1.s
|
//Original:/testcases/core/c_cc_regmvlogi_mvbrsft_s1/c_cc_regmvlogi_mvbrsft_s1.dsp
// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
A0 = 0;
A1 = 0;
imm32 r0, 0x00000020; // cc=1
imm32 r1, 0x00000000; // cc=0
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0x00000002;
ASTAT = R0; // cc=1 REGMV
R5 = R0 + R2; // comp3op dr plus dr
IF CC R1 = R3; // ccmov
ASTAT = R1; // cc=0 REGMV
R4 >>= R7; // alu2op sft
IF CC R3 = R2; // ccmv
CC = R0 < R1; // ccflag
R3.H = R1.L + R3.H (S); // dsp32alu
IF CC R4 = R5; // ccmv
CC = ! BITTST( R0 , 4 ); // cc = 0
R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
IF CC R4 = R5; // ccmv
CC = BITTST ( R1 , 4 ); // cc = 0
R3.L = R5.L << 1; // dsp32shiftim
IF !CC JUMP LABEL1; // branch
CC = ! CC;
R1 = ( A1 = R7.L * R4.L ), R0 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair
IF !CC JUMP LABEL2 (BP); // branch
LABEL1:
R2 = R0 + R2;
JUMP.S END;
LABEL2:
R7 = R5 - R3;
CC = R0 < R1; // ccflag
R5 = R0 + R2; // comp3op dr plus dr
IF CC JUMP END (BP); // branch on
R4 = R5 + R7;
END:
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x0398000C;
CHECKREG r2, 0x62B61577;
CHECKREG r3, 0x07372AEE;
CHECKREG r4, 0x62B61577;
CHECKREG r5, 0x62B61577;
CHECKREG r6, 0xFC680013;
CHECKREG r7, 0x00000002;
imm32 r0, 0x00000020;
imm32 r1, 0x00000000;
imm32 r2, 0x62661557;
imm32 r3, 0x073b0007;
imm32 r4, 0x01f49088;
imm32 r5, 0x6e2959aa;
imm32 r6, 0xa0b506cc;
imm32 r7, 0x00000002;
ASTAT = R0; // cc=1 REGMV
R4.H = R1.L + R0.L (S); // dsp32alu
R2 = ROT R2 BY 1; // dsp32shiftim_rot
ASTAT = R1; // cc=0 REGMV
A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac
R3 = ROT R3 BY 1; // dsp32shiftim_rot
CC = ! BITTST( R0 , 4 ); // cc = 0
R4.L = R5.L << 1; // dsp32shiftimm
R6 = ROT R4 BY 5; // dsp32shiftim_rot
CC = BITTST ( R1 , 4 ); // cc = 0
R7 = R0 + R2; // comp3op dr plus dr
IF CC R4 = R5; // ccmov
A0 += A1 (W32); // dsp32alu a0 + a1
CC = BITTST ( R0 , 4 ); // cc = 1
R5 = ROT R6 BY R7.L;
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x026B943C;
CHECKREG r1, 0x00025592;
CHECKREG r2, 0xC4CC2AAF;
CHECKREG r3, 0x0E76000E;
CHECKREG r4, 0x0020B354;
CHECKREG r5, 0x35480105;
CHECKREG r6, 0x04166A90;
CHECKREG r7, 0xC4CC2ACF;
pass
|
stsp/binutils-ia16
| 5,457
|
sim/testsuite/bfin/c_ldst_ld_p_p_pp.s
|
//Original:/testcases/core/c_ldst_ld_p_p_pp/c_ldst_ld_p_p_pp.dsp
// Spec Reference: c_ldst ld p [p++]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
P2 = [ P1 ++ ];
P1 += 4;
P4 = [ P1 ++ ];
P5 = [ P1 ++ ];
P1 += 4;
FP = [ P1 ++ ];
CHECKREG p2, 0x78910213;
CHECKREG p4, 0x08090A0B;
CHECKREG p5, 0x0C0D0E0F;
CHECKREG fp, 0x14151617;
loadsym p2, DATA_ADDR_2;
P1 = [ P2 ++ ];
P2 += 4;
P4 = [ P2 ++ ];
P5 = [ P2 ++ ];
P2 += 4;
FP = [ P2 ++ ];
CHECKREG p1, 0x20212223;
CHECKREG p4, 0x28292A2B;
CHECKREG p5, 0x2C2D2E2F;
CHECKREG fp, 0x34353637;
loadsym p4, DATA_ADDR_4;
P1 = [ P4 ++ ];
P2 = [ P4 ++ ];
P4 += 4;
P5 = [ P4 ++ ];
P4 += 4;
FP = [ P4 ++ ];
CHECKREG p1, 0x60616263;
CHECKREG p2, 0x64656667;
CHECKREG p5, 0x6C6D6E6F;
CHECKREG fp, 0x74757677;
loadsym p5, DATA_ADDR_5;
P1 = [ P5 ++ ];
P2 = [ P5 ++ ];
P5 += 4;
P4 = [ P5 ++ ];
P5 += 4;
FP = [ P5 ++ ];
CHECKREG p1, 0x8A8B8C8D;
CHECKREG p2, 0x84858687;
CHECKREG p4, 0x8C8D8E8F;
CHECKREG fp, 0x94959697;
loadsym fp, DATA_ADDR_7;
P1 = [ FP ++ ];
P2 = [ FP ++ ];
FP += 4;
P4 = [ FP ++ ];
P5 = [ FP ++ ];
CHECKREG p1, 0x80818283;
CHECKREG p2, 0x84858687;
CHECKREG p4, 0x8C8D8E8F;
CHECKREG p5, 0x90919293;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x78910213
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x8A8B8C8D
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 1,750
|
sim/testsuite/bfin/a21.s
|
// Test ALU RND RND12 RND20
# mach: bfin
.include "testutils.inc"
start
// positive saturation
R0 = 0xffffffff;
A0.w = R0;
A1.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// neg saturation
R0 = 0;
A0.w = R0;
A1.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x8000 ); DBGA ( R3.L , 0x0000 );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// positive saturation
R0 = 0xfffffff0;
A0.w = R0;
A1.w = R0;
R0 = 0x01;
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// no sat
R0 = 0xfffffff0;
A0.w = R0;
A1.w = R0;
R0 = 0x01;
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (NS);
DBGA ( R3.H , 0xffff ); DBGA ( R3.L , 0xffe0 );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// add and sub +1 -1
R0 = 0x00000001;
A0.w = R0;
R0 = 0xffffffff;
A1.w = R0;
R0 = 0;
A0.x = R0;
R0 = 0xff (X);
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (NS);
DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2
// should get the same with saturation
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2
// add and sub -1 +1 but with reverse order of A0 A1
R0 = 0x00000001;
A0.w = R0;
R0 = 0xffffffff;
A1.w = R0;
R0 = 0;
A0.x = R0;
R0 = 0xff (X);
A1.x = R0;
R3 = A0 + A1, R4 = A0 - A1 (NS);
DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0002 );
pass
|
stsp/binutils-ia16
| 6,888
|
sim/testsuite/bfin/random_0019.S
|
# Test a few (W32) corner cases
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV0S | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x70da33ff;
dmm32 A1.x, 0x0000000f;
imm32 R0, 0x5e29f819;
imm32 R1, 0x3f59520b;
A1 += R0.L * R1.L (M, W32);
checkreg A1.w, 0x7fffffff;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV1 | _AV0S | _CC | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x18300c10 | _VS | _AV1S | _AN);
dmm32 A0.w, 0x1096b1c1;
dmm32 A0.x, 0xfffffff1;
imm32 R6, 0x3a0178ee;
imm32 R7, 0x17c95e45;
A0 -= R6.L * R7.L (W32);
checkreg A0.w, 0x80000000;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x18300c10 | _VS | _AV1S | _AV0S | _AV0 | _AN);
dmm32 ASTAT, (0x68508800 | _VS | _AV1S | _AV0S | _CC | _AZ);
dmm32 A0.w, 0x30c8f917;
dmm32 A0.x, 0xffffffc8;
imm32 R3, 0x7ad1091c;
imm32 R4, 0x80002874;
A0 -= R3.L * R4.L (W32);
checkreg A0.w, 0x80000000;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x68508800 | _VS | _AV1S | _AV0S | _AV0 | _CC | _AZ);
dmm32 ASTAT, (0x58708e90 | _VS | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x13de4c3d;
dmm32 A0.x, 0xffffffa5;
imm32 R0, 0xf70f956f;
imm32 R2, 0xf837e08c;
A0 -= R0.L * R2.H (W32);
checkreg A0.w, 0x80000000;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x58708e90 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x70800280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x80140410;
dmm32 A0.x, 0x00000000;
imm32 R1, 0x028b09a4;
imm32 R4, 0x00007ffc;
A0 += R4.L * R1.H (W32);
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x70800280 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x0060c610 | _VS | _AC1 | _AC0 | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x1794b937;
dmm32 A1.x, 0xfffffff5;
imm32 R6, 0x008e1c0d;
A1 -= R6.L * R6.L (W32);
checkreg A1.w, 0x80000000;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x0060c610 | _VS | _AV1S | _AV1 | _AC1 | _AC0 | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x2c600410 | _VS | _AV0S | _AC1 | _CC | _AN);
dmm32 A1.w, 0x2d03ef79;
dmm32 A1.x, 0x00000079;
imm32 R5, 0x15d1b500;
imm32 R6, 0xf7962b39;
A1 += R6.L * R5.H (W32);
checkreg A1.w, 0x7fffffff;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x2c600410 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _CC | _AN);
dmm32 ASTAT, (0x5cf04e10 | _VS | _AV0S | _AC1 | _CC | _AC0_COPY);
dmm32 A0.w, 0x4d50b3f0;
dmm32 A0.x, 0xfffffffc;
imm32 R4, 0x6671002a;
imm32 R7, 0x00288000;
A0 += R4.L * R7.L (W32);
checkreg A0.w, 0x80000000;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x5cf04e10 | _VS | _AV0S | _AV0 | _AC1 | _CC | _AC0_COPY);
dmm32 ASTAT, (0x28908000 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AN);
dmm32 A1.w, 0xc94e99f1;
dmm32 A1.x, 0x00000021;
imm32 R4, 0x7fff52b7;
imm32 R7, 0x3ebb26c6;
A1 += R7.L * R4.L (M, W32);
checkreg A1.w, 0x7fffffff;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x28908000 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x34708a00 | _VS | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0xf61f316d;
dmm32 A1.x, 0x00000061;
imm32 R1, 0x86f0ffff;
imm32 R3, 0x791048c5;
A1 += R1.L * R3.L (M, W32);
checkreg A1.w, 0x7fffffff;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x34708a00 | _VS | _AV1S | _AV1 | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x5020c280 | _VS | _V | _AC1 | _AC0 | _V_COPY);
dmm32 A1.w, 0x8700591f;
dmm32 A1.x, 0x00000007;
imm32 R2, 0x145b00b1;
imm32 R3, 0x7fffffff;
A1 -= R3.L * R2.H (M, W32);
checkreg A1.w, 0x7fffffff;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x5020c280 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _V_COPY);
dmm32 ASTAT, (0x00000290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 A0.w, 0xfe84e1ec;
dmm32 A0.x, 0xffffffff;
imm32 R1, 0x07e73e7b;
imm32 R3, 0x00033e7b;
A0 -= R3.L * R1.H (W32);
checkreg A0.w, 0xfaa965f2;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x00000290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x78204a80 | _VS | _AV1S | _CC | _AN);
dmm32 A0.w, 0xca398210;
dmm32 A0.x, 0xffffffff;
imm32 R3, 0xffff0000;
imm32 R7, 0x00000000;
A0 += R7.L * R3.L (W32);
checkreg ASTAT, (0x78204a80 | _VS | _AV1S | _CC | _AN);
dmm32 ASTAT, (0x04208890 | _VS | _AC1 | _AC0_COPY);
dmm32 A0.w, 0x224cbaee;
dmm32 A0.x, 0x00000000;
imm32 R3, 0x3db86584;
imm32 R6, 0xdb505ed8;
A0 -= R6.L * R3.H (W32);
checkreg A0.w, 0xf491746e;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x04208890 | _VS | _AC1 | _AC0_COPY);
dmm32 ASTAT, (0x3c908600 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x03f7c0ec;
dmm32 A0.x, 0x00000000;
imm32 R1, 0x1c25c7b4;
imm32 R5, 0x3f7da612;
A0 -= R5.L * R1.L (W32);
checkreg A0.w, 0xdc6a3b9c;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x3c908600 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x7cb08680 | _VS | _AQ | _CC | _AN);
dmm32 A0.w, 0xdc7c243c;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0xe2ccef4c;
imm32 R5, 0x7fff8000;
A0 += R5.L * R0.L (W32);
checkreg A0.w, 0xed30243c;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x7cb08680 | _VS | _AQ | _CC | _AN);
dmm32 ASTAT, (0x78f00080 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AN);
dmm32 A0.w, 0x39180f38;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x01308ac1;
imm32 R6, 0x7ffff8fd;
A0 = R6.L * R4.H (W32);
checkreg A0.w, 0xffef58e0;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x78f00080 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x7050c090 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x010909b0;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x80000000;
imm32 R6, 0x6ad06150;
A1 = R6.L * R0.H (W32);
checkreg A1.w, 0x9eb00000;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x7050c090 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x68c04c10 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AN);
dmm32 A0.w, 0x43687862;
dmm32 A0.x, 0x00000000;
imm32 R2, 0xff278000;
imm32 R4, 0x0000436a;
A0 += R2.L * R4.L (W32);
checkreg A0.w, 0xfffe7862;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x68c04c10 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x74a00200 | _AV1 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x64c15e6b;
dmm32 A1.x, 0xffffff87;
imm32 R4, 0x30b3e20d;
imm32 R7, 0x4a562069;
A1 = R4.L * R7.H (M, W32);
checkreg A1.w, 0xf74db25e;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x74a00200 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x70f08410 | _AV0 | _AC1 | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x5f011b0d;
dmm32 A0.x, 0xffffff86;
imm32 R3, 0x21f93a90;
imm32 R4, 0x1c82d429;
A0 = R3.H * R4.L (W32);
checkreg A0.w, 0xf45d49c2;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x70f08410 | _AC1 | _AC0_COPY | _AN | _AZ);
pass
|
stsp/binutils-ia16
| 4,030
|
sim/testsuite/bfin/c_regmv_pr_dep_stall.s
|
//Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_stall/c_regmv_pr_dep_stall.dsp
// Spec Reference: regmv pr-dependency stall
# mach: bfin
.include "testutils.inc"
start
INIT_M_REGS 0;
// R-reg to P-reg to R reg: stall
imm32 r0, 0x00001110;
imm32 r1, 0x00213330;
imm32 r2, 0x04015550;
imm32 r3, 0x06607770;
imm32 r4, 0x08810990;
imm32 r5, 0x01a1b0b0;
imm32 r6, 0x01c1dd00;
imm32 r7, 0x01e1fff0;
P1 = R1;
R0 = P1;
P2 = R2;
R1 = P2;
P3 = R3;
R2 = P3;
P4 = R4;
R3 = P4;
P5 = R5;
R4 = P5;
SP = R6;
R5 = P2;
FP = R7;
R6 = P3;
CHECKREG r0, 0x00213330;
CHECKREG r1, 0x04015550;
CHECKREG r2, 0x06607770;
CHECKREG r3, 0x08810990;
CHECKREG r4, 0x01A1B0B0;
CHECKREG r5, 0x04015550;
CHECKREG r6, 0x06607770;
CHECKREG r7, 0x01E1FFF0;
// R-reg to P-reg to I,M reg: stall
imm32 r0, 0x10001111;
imm32 r1, 0x11213331;
imm32 r2, 0x14115551;
imm32 r3, 0x16617771;
imm32 r4, 0x18811991;
imm32 r5, 0x11a1b1b1;
imm32 r6, 0x11c1dd11;
imm32 r7, 0x11e1fff1;
P1 = R0;
I0 = P1;
P2 = R1;
I1 = P2;
P3 = R2;
I2 = P3;
P4 = R3;
I3 = P4;
P5 = R4;
M0 = P5;
SP = R5;
M1 = SP;
FP = R6;
M2 = FP;
R0 = I3;
R1 = I2;
R2 = I1;
R3 = I0;
R4 = M3;
R5 = M2;
R6 = M1;
R7 = M0;
CHECKREG r0, 0x16617771;
CHECKREG r1, 0x14115551;
CHECKREG r2, 0x11213331;
CHECKREG r3, 0x10001111;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x11C1DD11;
CHECKREG r6, 0x11A1B1B1;
CHECKREG r7, 0x18811991;
CHECKREG p1, 0x10001111;
CHECKREG p2, 0x11213331;
CHECKREG p3, 0x14115551;
CHECKREG p4, 0x16617771;
CHECKREG p5, 0x18811991;
CHECKREG sp, 0x11A1B1B1;
CHECKREG fp, 0x11C1DD11;
imm32 r0, 0x20001112;
imm32 r1, 0x21213332;
imm32 r2, 0x24115552;
imm32 r3, 0x26617772;
imm32 r4, 0x28811992;
imm32 r5, 0x21a1b1b2;
imm32 r6, 0x21c1dd12;
imm32 r7, 0x21e1fff2;
P1 = R3;
I3 = P1;
P2 = R4;
I0 = P2;
P3 = R5;
I1 = P3;
P4 = R6;
I2 = P4;
P5 = R7;
M1 = P5;
SP = R0;
M2 = SP;
FP = R1;
M3 = FP;
R0 = I3;
R1 = I2;
R2 = I1;
R3 = I0;
R4 = M3;
R5 = M2;
R6 = M1;
R7 = M0;
CHECKREG r0, 0x26617772;
CHECKREG r1, 0x21C1DD12;
CHECKREG r2, 0x21A1B1B2;
CHECKREG r3, 0x28811992;
CHECKREG r4, 0x21213332;
CHECKREG r5, 0x20001112;
CHECKREG r6, 0x21E1FFF2;
CHECKREG r7, 0x18811991;
CHECKREG p1, 0x26617772;
CHECKREG p2, 0x28811992;
CHECKREG p3, 0x21A1B1B2;
CHECKREG p4, 0x21C1DD12;
CHECKREG p5, 0x21E1FFF2;
CHECKREG sp, 0x20001112;
CHECKREG fp, 0x21213332;
// R-reg to P-reg to L,B reg: stall
imm32 r0, 0x30001113;
imm32 r1, 0x31213333;
imm32 r2, 0x34115553;
imm32 r3, 0x36617773;
imm32 r4, 0x38811993;
imm32 r5, 0x31a1b1b3;
imm32 r6, 0x31c1dd13;
imm32 r7, 0x31e1fff3;
P1 = R4;
L0 = P1;
P2 = R5;
L1 = P2;
P3 = R6;
L2 = P3;
P4 = R7;
L3 = P4;
P5 = R0;
B0 = P5;
SP = R1;
B1 = SP;
FP = R2;
B2 = FP;
R0 = L3;
R1 = L2;
R2 = L1;
R3 = L0;
R4 = B3;
R5 = B2;
R6 = B1;
R7 = B0;
CHECKREG r0, 0x31E1FFF3;
CHECKREG r1, 0x31C1DD13;
CHECKREG r2, 0x31A1B1B3;
CHECKREG r3, 0x38811993;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x34115553;
CHECKREG r6, 0x31213333;
CHECKREG r7, 0x30001113;
CHECKREG p1, 0x38811993;
CHECKREG p2, 0x31A1B1B3;
CHECKREG p3, 0x31C1DD13;
CHECKREG p4, 0x31E1FFF3;
CHECKREG p5, 0x30001113;
CHECKREG sp, 0x31213333;
CHECKREG fp, 0x34115553;
imm32 r0, 0x40001114;
imm32 r1, 0x44213334;
imm32 r2, 0x44415554;
imm32 r3, 0x46647774;
imm32 r4, 0x48814994;
imm32 r5, 0x41a1b4b4;
imm32 r6, 0x41c1dd44;
imm32 r7, 0x41e1fff4;
P1 = R5;
L2 = P1;
P2 = R6;
L3 = P2;
P3 = R7;
L0 = P3;
P4 = R0;
L1 = P4;
P5 = R1;
B2 = P5;
SP = R2;
B3 = SP;
FP = R3;
B0 = FP;
R0 = L3;
R1 = L2;
R2 = L1;
R3 = L0;
R4 = B3;
R5 = B2;
R6 = B1;
R7 = B0;
CHECKREG r0, 0x41C1DD44;
CHECKREG r1, 0x41A1B4B4;
CHECKREG r2, 0x40001114;
CHECKREG r3, 0x41E1FFF4;
CHECKREG r4, 0x44415554;
CHECKREG r5, 0x44213334;
CHECKREG r6, 0x31213333;
CHECKREG r7, 0x46647774;
CHECKREG p1, 0x41A1B4B4;
CHECKREG p2, 0x41C1DD44;
CHECKREG p3, 0x41E1FFF4;
CHECKREG p4, 0x40001114;
CHECKREG p5, 0x44213334;
CHECKREG sp, 0x44415554;
CHECKREG fp, 0x46647774;
pass
|
stsp/binutils-ia16
| 6,034
|
sim/testsuite/bfin/c_dsp32alu_minmin.s
|
//Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp
// Spec Reference: dsp32alu dregs = min / min ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x2a445345;
imm32 r3, 0x46657717;
imm32 r4, 0xd567e91b;
imm32 r5, 0x6789af1d;
imm32 r6, 0x74445d85;
imm32 r7, 0x8666a779;
R0 = MIN ( R0 , R0 ) (V);
R1 = MIN ( R0 , R1 ) (V);
R2 = MIN ( R0 , R2 ) (V);
R3 = MIN ( R0 , R3 ) (V);
R4 = MIN ( R0 , R4 ) (V);
R5 = MIN ( R0 , R5 ) (V);
R6 = MIN ( R0 , R6 ) (V);
R7 = MIN ( R0 , R7 ) (V);
CHECKREG r0, 0x25678911;
CHECKREG r1, 0x23898911;
CHECKREG r2, 0x25678911;
CHECKREG r3, 0x25678911;
CHECKREG r4, 0xD5678911;
CHECKREG r5, 0x25678911;
CHECKREG r6, 0x25678911;
CHECKREG r7, 0x86668911;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = MIN ( R1 , R0 ) (V);
R1 = MIN ( R1 , R1 ) (V);
R2 = MIN ( R1 , R2 ) (V);
R3 = MIN ( R1 , R3 ) (V);
R4 = MIN ( R1 , R4 ) (V);
R5 = MIN ( R1 , R5 ) (V);
R6 = MIN ( R1 , R6 ) (V);
R7 = MIN ( R1 , R7 ) (V);
CHECKREG r0, 0x9567892B;
CHECKREG r1, 0xA789AB2D;
CHECKREG r2, 0xA789AB2D;
CHECKREG r3, 0xA789AB2D;
CHECKREG r4, 0xA7899929;
CHECKREG r5, 0xA789AB2D;
CHECKREG r6, 0xA789AB2D;
CHECKREG r7, 0xA789AB2D;
imm32 r0, 0x416789ab;
imm32 r1, 0x5289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0xa466a777;
imm32 r4, 0x45678dab;
imm32 r5, 0xf689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = MIN ( R2 , R0 ) (V);
R1 = MIN ( R2 , R1 ) (V);
R2 = MIN ( R2 , R2 ) (V);
R3 = MIN ( R2 , R3 ) (V);
R4 = MIN ( R2 , R4 ) (V);
R5 = MIN ( R2 , R5 ) (V);
R6 = MIN ( R2 , R6 ) (V);
R7 = MIN ( R2 , R7 ) (V);
CHECKREG r0, 0x416789AB;
CHECKREG r1, 0x4344ABCD;
CHECKREG r2, 0x43445555;
CHECKREG r3, 0xA466A777;
CHECKREG r4, 0x43448DAB;
CHECKREG r5, 0xF689ABCD;
CHECKREG r6, 0x43445555;
CHECKREG r7, 0x43445555;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
R0 = MIN ( R3 , R0 ) (V);
R1 = MIN ( R3 , R1 ) (V);
R2 = MIN ( R3 , R2 ) (V);
R3 = MIN ( R3 , R3 ) (V);
R4 = MIN ( R3 , R4 ) (V);
R5 = MIN ( R3 , R5 ) (V);
R6 = MIN ( R3 , R6 ) (V);
R7 = MIN ( R3 , R7 ) (V);
CHECKREG r0, 0x9567892B;
CHECKREG r1, 0xA789AB2D;
CHECKREG r2, 0xB4445525;
CHECKREG r3, 0xC6667727;
CHECKREG r4, 0xC6668DAB;
CHECKREG r5, 0xC666ABCD;
CHECKREG r6, 0xC6665555;
CHECKREG r7, 0xC6665555;
imm32 r0, 0x5537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x74555535;
imm32 r3, 0x86665747;
imm32 r4, 0x98789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0 = MIN ( R4 , R0 ) (V);
R1 = MIN ( R4 , R1 ) (V);
R2 = MIN ( R4 , R2 ) (V);
R3 = MIN ( R4 , R3 ) (V);
R4 = MIN ( R4 , R4 ) (V);
R5 = MIN ( R4 , R5 ) (V);
R6 = MIN ( R4 , R6 ) (V);
R7 = MIN ( R4 , R7 ) (V);
CHECKREG r0, 0x9878891B;
CHECKREG r1, 0x98789565;
CHECKREG r2, 0x98789565;
CHECKREG r3, 0x86669565;
CHECKREG r4, 0x98789565;
CHECKREG r5, 0x98789565;
CHECKREG r6, 0x98789565;
CHECKREG r7, 0x98789565;
imm32 r0, 0x256b89ab;
imm32 r1, 0x64764bcd;
imm32 r2, 0x49736564;
imm32 r3, 0x61278394;
imm32 r4, 0x98876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x43346fff;
R0 = MIN ( R5 , R0 ) (V);
R1 = MIN ( R5 , R1 ) (V);
R2 = MIN ( R5 , R2 ) (V);
R3 = MIN ( R5 , R3 ) (V);
R4 = MIN ( R5 , R4 ) (V);
R5 = MIN ( R5 , R5 ) (V);
R6 = MIN ( R5 , R6 ) (V);
R7 = MIN ( R5 , R7 ) (V);
CHECKREG r0, 0xAAAA89AB;
CHECKREG r1, 0xAAAA0BBB;
CHECKREG r2, 0xAAAA0BBB;
CHECKREG r3, 0xAAAA8394;
CHECKREG r4, 0x98870BBB;
CHECKREG r5, 0xAAAA0BBB;
CHECKREG r6, 0xAAAA0BBB;
CHECKREG r7, 0xAAAA0BBB;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R0 = MIN ( R6 , R0 ) (V);
R1 = MIN ( R6 , R1 ) (V);
R2 = MIN ( R6 , R2 ) (V);
R3 = MIN ( R6 , R3 ) (V);
R4 = MIN ( R6 , R4 ) (V);
R5 = MIN ( R6 , R5 ) (V);
R6 = MIN ( R6 , R6 ) (V);
R7 = MIN ( R6 , R7 ) (V);
CHECKREG r0, 0x043290D6;
CHECKREG r1, 0x043290D6;
CHECKREG r2, 0x034590D6;
CHECKREG r3, 0x043290D6;
CHECKREG r4, 0x043290D6;
CHECKREG r5, 0x04328B6B;
CHECKREG r6, 0x043290D6;
CHECKREG r7, 0x043290D6;
imm32 r0, 0x976789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x8345a755;
imm32 r3, 0x5678b007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R0 = MIN ( R7 , R0 ) (V);
R1 = MIN ( R7 , R1 ) (V);
R2 = MIN ( R7 , R2 ) (V);
R3 = MIN ( R7 , R3 ) (V);
R4 = MIN ( R7 , R4 ) (V);
R5 = MIN ( R7 , R5 ) (V);
R6 = MIN ( R7 , R6 ) (V);
R7 = MIN ( R7 , R7 ) (V);
CHECKREG r0, 0x976789AB;
CHECKREG r1, 0xABCDABCD;
CHECKREG r2, 0x8345A755;
CHECKREG r3, 0xABCDB007;
CHECKREG r4, 0xABCDB799;
CHECKREG r5, 0xAAAA0BBB;
CHECKREG r6, 0x89AB1D7D;
CHECKREG r7, 0xABCD2FF7;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R4 = MIN ( R4 , R7 ) (V);
R5 = MIN ( R5 , R5 ) (V);
R2 = MIN ( R6 , R3 ) (V);
R6 = MIN ( R0 , R4 ) (V);
R0 = MIN ( R1 , R6 ) (V);
R2 = MIN ( R2 , R1 ) (V);
R1 = MIN ( R3 , R0 ) (V);
R7 = MIN ( R7 , R4 ) (V);
CHECKREG r0, 0x123439AB;
CHECKREG r1, 0x123439AB;
CHECKREG r2, 0x043290D6;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x1234567F;
CHECKREG r5, 0x45678B6B;
CHECKREG r6, 0x123439AB;
CHECKREG r7, 0x1234567F;
imm32 r0, 0xa76789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0xb3456755;
imm32 r3, 0x5678d007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R3 = MIN ( R4 , R0 ) (V);
R5 = MIN ( R5 , R1 ) (V);
R2 = MIN ( R2 , R2 ) (V);
R7 = MIN ( R7 , R3 ) (V);
R4 = MIN ( R3 , R4 ) (V);
R0 = MIN ( R1 , R5 ) (V);
R1 = MIN ( R0 , R6 ) (V);
R6 = MIN ( R6 , R7 ) (V);
CHECKREG r0, 0xAAAAABCD;
CHECKREG r1, 0x89ABABCD;
CHECKREG r2, 0xB3456755;
CHECKREG r3, 0xA76789AB;
CHECKREG r4, 0xA76789AB;
CHECKREG r5, 0xAAAAABCD;
CHECKREG r6, 0x89AB89AB;
CHECKREG r7, 0xA76789AB;
pass
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