repo_id
stringlengths 5
115
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int64 590
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| file_path
stringlengths 4
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stringlengths 590
5.01M
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|---|---|---|---|
stsp/binutils-ia16
| 1,441
|
sim/testsuite/h8300/adds.s
|
# Hitachi H8 testcase 'adds'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# adds #1, erd ; 0 b 0 xerd
# adds #2, erd ; 0 b 8 xerd
# adds #4, erd ; 0 b 9 xerd
#
start
.if (sim_cpu) ; 32 bit only
adds_1:
set_grs_a5a5
set_ccr_zero
adds #1, er0
test_cc_clear ; adds should not affect any condition codes
test_h_gr32 0xa5a5a5a6 er0 ; result of adds #1
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
adds_2:
set_grs_a5a5
set_ccr_zero
adds #2, er0
test_cc_clear ; adds should not affect any condition codes
test_h_gr32 0xa5a5a5a7 er0 ; result of adds #2
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
adds_4:
set_grs_a5a5
set_ccr_zero
adds #4, er0
test_cc_clear ; adds should not affect any condition codes
test_h_gr32 0xa5a5a5a9 er0 ; result of adds #4
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
.endif
exit 0
|
stsp/binutils-ia16
| 48,429
|
sim/testsuite/h8300/movl.s
|
# Hitachi H8 testcase 'mov.l'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 4
long_dst_dec:
.long 0
long_src:
.long 0x77777777
long_dst:
.long 0
.text
;;
;; Move long from immediate source
;;
.if (sim_cpu == h8sx)
mov_l_imm3_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:3, erd
mov.l #0x3:3, er0 ; Immediate 3-bit operand
;;; .word 0x0fb8
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x3 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_imm16_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, erd
mov.l #0x1234, er0 ; Immediate 16-bit operand
;;; .word 0x7a08
;;; .word 0x1234
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x1234 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
mov_l_imm32_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, erd
mov.l #0x12345678, er0 ; Immediate 32-bit operand
;;; .word 0x7a00
;;; .long 0x12345678
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x12345678 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mov_l_imm8_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @erd
mov.l #long_dst, er1
mov.l #0xa5:8, @er1 ; Register indirect operand
;;; .word 0x010d
;;; .word 0x01a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext1
fail
.Lnext1:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_postinc: ; post-increment from imm8 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @erd+
mov.l #long_dst, er1
mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands.
;;; .word 0x010d
;;; .word 0x81a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst+4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext2
fail
.Lnext2:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @erd-
mov.l #long_dst, er1
mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands.
;;; .word 0x010d
;;; .word 0xa1a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext3
fail
.Lnext3:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @+erd
mov.l #long_dst-4, er1
mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands
;;; .word 0x010d
;;; .word 0x91a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext4
fail
.Lnext4:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @-erd
mov.l #long_dst+4, er1
mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands
;;; .word 0x010d
;;; .word 0xb1a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext5
fail
.Lnext5:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @(dd:2, erd)
mov.l #long_dst-12, er1
mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand
;;; .word 0x010d
;;; .word 0x31a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-12, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext6
fail
.Lnext6:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @(dd:16, erd)
mov.l #long_dst-4, er1
mov.l #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x010d
;;; .word 0x6f90
;;; .word 0x0004
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext7
fail
.Lnext7:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @(dd:32, erd)
mov.l #long_dst-8, er1
mov.l #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x010d
;;; .word 0xc9a5
;;; .long 8
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-8, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext8
fail
.Lnext8:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @aa:16
mov.l #0xa5:8, @long_dst:16 ; 16-bit address-direct operand
;;; .word 0x010d
;;; .word 0x40a5
;;; .word @long_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext9
fail
.Lnext9:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm8_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:8, @aa:32
mov.l #0xa5:8, @long_dst:32 ; 32-bit address-direct operand
;;; .word 0x010d
;;; .word 0x48a5
;;; .long @long_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xa5, @long_dst
beq .Lnext10
fail
.Lnext10:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @erd
mov.l #long_dst, er1
mov.l #0xdead:16, @er1 ; Register indirect operand
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0x0100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext11
fail
.Lnext11:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_postinc: ; post-increment from imm16 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @erd+
mov.l #long_dst, er1
mov.l #0xdead:16, @er1+ ; Imm16, register post-incr operands.
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0x8100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst+4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext12
fail
.Lnext12:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_postdec: ; post-decrement from imm16 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @erd-
mov.l #long_dst, er1
mov.l #0xdead:16, @er1- ; Imm16, register post-decr operands.
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0xa100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext13
fail
.Lnext13:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @+erd
mov.l #long_dst-4, er1
mov.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0x9100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext14
fail
.Lnext14:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @-erd
mov.l #long_dst+4, er1
mov.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0xb100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext15
fail
.Lnext15:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @(dd:2, erd)
mov.l #long_dst-12, er1
mov.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0x3100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-12, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext16
fail
.Lnext16:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @(dd:16, erd)
mov.l #long_dst-4, er1
mov.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0xc100
;;; .word 0x0004
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext17
fail
.Lnext17:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @(dd:32, erd)
mov.l #long_dst-8, er1
mov.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0xc900
;;; .long 8
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-8, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext18
fail
.Lnext18:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @aa:16
mov.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0x4000
;;; .word @long_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext19
fail
.Lnext19:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm16_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:16, @aa:32
mov.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand
;;; .word 0x7a7c
;;; .word 0xdead
;;; .word 0x4800
;;; .long @long_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xdead, @long_dst
beq .Lnext20
fail
.Lnext20:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @erd
mov.l #long_dst, er1
mov.l #0xcafedead:32, @er1 ; Register indirect operand
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0x0100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext21
fail
.Lnext21:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_postinc: ; post-increment from imm32 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @erd+
mov.l #long_dst, er1
mov.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands.
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0x8100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst+4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext22
fail
.Lnext22:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_postdec: ; post-decrement from imm32 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @erd-
mov.l #long_dst, er1
mov.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands.
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0xa100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext23
fail
.Lnext23:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @+erd
mov.l #long_dst-4, er1
mov.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0x9100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext24
fail
.Lnext24:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @-erd
mov.l #long_dst+4, er1
mov.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0xb100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext25
fail
.Lnext25:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @(dd:2, erd)
mov.l #long_dst-12, er1
mov.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0x3100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-12, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext26
fail
.Lnext26:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @(dd:16, erd)
mov.l #long_dst-4, er1
mov.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0xc100
;;; .word 0x0004
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext27
fail
.Lnext27:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @(dd:32, erd)
mov.l #long_dst-8, er1
mov.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0xc900
;;; .long 8
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-8, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext28
fail
.Lnext28:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @aa:16
mov.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0x4000
;;; .word @long_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext29
fail
.Lnext29:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_imm32_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l #xx:32, @aa:32
mov.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand
;;; .word 0x7a74
;;; .long 0xcafedead
;;; .word 0x4800
;;; .long @long_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0xcafedead, @long_dst
beq .Lnext30
fail
.Lnext30:
mov.l #0, @long_dst ; zero it again for the next use.
.endif
;;
;; Move long from register source
;;
mov_l_reg32_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, erd
mov.l #0x12345678, er1
mov.l er1, er0 ; Register 32-bit operand
;;; .word 0x0f90
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x12345678 er0
test_h_gr32 0x12345678 er1 ; mov src unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_reg32_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @erd
mov.l #long_dst, er1
mov.l er0, @er1 ; Register indirect operand
;;; .word 0x0100
;;; .word 0x6990
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.l #0, er0
mov.l @long_dst, er0
cmp.l er2, er0
beq .Lnext44
fail
.Lnext44:
mov.l #0, er0
mov.l er0, @long_dst ; zero it again for the next use.
.if (sim_cpu == h8sx)
mov_l_reg32_to_postinc: ; post-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @erd+
mov.l #long_dst, er1
mov.l er0, @er1+ ; Register post-incr operand
;;; .word 0x0103
;;; .word 0x6d90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst+4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l er2, @long_dst
beq .Lnext49
fail
.Lnext49:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_reg32_to_postdec: ; post-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @erd-
mov.l #long_dst, er1
mov.l er0, @er1- ; Register post-decr operand
;;; .word 0x0101
;;; .word 0x6d90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l er2, @long_dst
beq .Lnext50
fail
.Lnext50:
;; special case same register
mov.l #long_dst, er0
mov.l er0, er1
subs #4, er1
mov.l er0, @er0-
mov.l @long_dst, er0
cmp.l er0, er1
beq .Lnext54
fail
.Lnext54:
mov.l #0, @long_dst ; zero it again for the next use.
mov_l_reg32_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @+erd
mov.l #long_dst-4, er1
mov.l er0, @+er1 ; Register pre-incr operand
;;; .word 0x0102
;;; .word 0x6d90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l er2, @long_dst
beq .Lnext51
fail
.Lnext51:
mov.l #0, @long_dst ; zero it again for the next use.
.endif ; h8sx
mov_l_reg32_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @-erd
mov.l #long_dst+4, er1
mov.l er0, @-er1 ; Register pre-decr operand
;;; .word 0x0100
;;; .word 0x6d90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.l #0, er0
mov.l @long_dst, er0
cmp.l er2, er0
beq .Lnext48
fail
.Lnext48:
;; Special case in same register
;; CCR confirmation omitted
mov.l #long_dst+4, er1
mov.l er1, er0
subs #4, er1
mov.l er0, @-er0
mov.l @long_dst, er0
cmp.l er1, er0
beq .Lnext47
fail
.Lnext47:
mov.l #0, er0
mov.l er0, @long_dst ; zero it again for the next use.
.if (sim_cpu == h8sx)
mov_l_reg32_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @(dd:2, erd)
mov.l #long_dst-12, er1
mov.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand
;;; .word 0x0103
;;; .word 0x6990
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-12, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l er2, @long_dst
beq .Lnext52
fail
.Lnext52:
mov.l #0, @long_dst ; zero it again for the next use.
.endif ; h8sx
mov_l_reg32_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @(dd:16, erd)
mov.l #long_dst-4, er1
mov.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x0100
;;; .word 0x6f90
;;; .word 0x0004
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 long_dst-4, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.l #0, er0
mov.l @long_dst, er0
cmp.l er2, er0
beq .Lnext45
fail
.Lnext45:
mov.l #0, er0
mov.l er0, @long_dst ; zero it again for the next use.
mov_l_reg32_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @(dd:32, erd)
mov.l #long_dst-8, er1
mov.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x7890
;;; .word 0x6ba0
;;; .long 8
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 long_dst-8, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.l #0, er0
mov.l @long_dst, er0
cmp.l er2, er0
beq .Lnext46
fail
.Lnext46:
mov.l #0, er0
mov.l er0, @long_dst ; zero it again for the next use.
mov_l_reg32_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @aa:16
mov.l er0, @long_dst:16 ; 16-bit address-direct operand
;;; .word 0x0100
;;; .word 0x6b80
;;; .word @long_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.l #0, er0
mov.l @long_dst, er0
cmp.l er0, er1
beq .Lnext41
fail
.Lnext41:
mov.l #0, er0
mov.l er0, @long_dst ; zero it again for the next use.
mov_l_reg32_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l ers, @aa:32
mov.l er0, @long_dst:32 ; 32-bit address-direct operand
;;; .word 0x0100
;;; .word 0x6ba0
;;; .long @long_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.l #0, er0
mov.l @long_dst, er0
cmp.l er0, er1
beq .Lnext42
fail
.Lnext42:
mov.l #0, er0
mov.l er0, @long_dst ; zero it again for the next use.
;;
;; Move long to register destination.
;;
mov_l_indirect_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @ers, erd
mov.l #long_src, er1
mov.l @er1, er0 ; Register indirect operand
;;; .word 0x0100
;;; .word 0x6910
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0
test_h_gr32 long_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_postinc_to_reg32: ; post-increment from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @ers+, erd
mov.l #long_src, er1
mov.l @er1+, er0 ; Register post-incr operand
;;; .word 0x0100
;;; .word 0x6d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0
test_h_gr32 long_src+4, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mov_l_postdec_to_reg32: ; post-decrement from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @ers-, erd
mov.l #long_src, er1
mov.l @er1-, er0 ; Register post-decr operand
;;; .word 0x0102
;;; .word 0x6d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0
test_h_gr32 long_src-4, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_preinc_to_reg32: ; pre-increment from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @+ers, erd
mov.l #long_src-4, er1
mov.l @+er1, er0 ; Register pre-incr operand
;;; .word 0x0101
;;; .word 0x6d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0
test_h_gr32 long_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_predec_to_reg32: ; pre-decrement from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @-ers, erd
mov.l #long_src+4, er1
mov.l @-er1, er0 ; Register pre-decr operand
;;; .word 0x0103
;;; .word 0x6d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0
test_h_gr32 long_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_disp2_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @(dd:2, ers), erd
mov.l #long_src-4, er1
mov.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand
;;; .word 0x0101
;;; .word 0x6910
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777
test_h_gr32 long_src-4, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
mov_l_disp16_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @(dd:16, ers), erd
mov.l #long_src+0x1234, er1
mov.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand
;;; .word 0x0100
;;; .word 0x6f10
;;; .word -0x1234
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777
test_h_gr32 long_src+0x1234, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_disp32_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @(dd:32, ers), erd
mov.l #long_src+65536, er1
mov.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand
;;; .word 0x7890
;;; .word 0x6b20
;;; .long -65536
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777
test_h_gr32 long_src+65536, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_abs16_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @aa:16, erd
mov.l @long_src:16, er0 ; 16-bit address-direct operand
;;; .word 0x0100
;;; .word 0x6b00
;;; .word @long_src
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_l_abs32_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @aa:32, erd
mov.l @long_src:32, er0 ; 32-bit address-direct operand
;;; .word 0x0100
;;; .word 0x6b20
;;; .long @long_src
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x77777777 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
;;
;; Move long from memory to memory
;;
mov_l_indirect_to_indirect: ; reg indirect, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @ers, @erd
mov.l #long_src, er1
mov.l #long_dst, er0
mov.l @er1, @er0
;;; .word 0x0108
;;; .word 0x0100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst er0
test_h_gr32 long_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext56
fail
.Lnext56:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext57
fail
.Lnext57: ; OK, pass on.
mov_l_postinc_to_postinc: ; reg post-increment, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @ers+, @erd+
mov.l #long_src, er1
mov.l #long_dst, er0
mov.l @er1+, @er0+
;;; .word 0x0108
;;; .word 0x8180
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst+4 er0
test_h_gr32 long_src+4 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext65
fail
.Lnext65:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext66
fail
.Lnext66: ; OK, pass on.
;; special case same register
mov.l #long_src, er0
mov.l @er0+, @er0+ ; copying long_src to long_dst
test_h_gr32 long_src+8 er0
cmp.b @long_src, @long_dst
beq .Lnext67
fail
.Lnext67:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext68
fail
.Lnext68:
mov_l_postdec_to_postdec: ; reg post-decrement, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @ers-, @erd-
mov.l #long_src, er1
mov.l #long_dst, er0
mov.l @er1-, @er0-
;;; .word 0x0108
;;; .word 0xa1a0
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst-4 er0
test_h_gr32 long_src-4 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext75
fail
.Lnext75:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext76
fail
.Lnext76: ; OK, pass on.
;; special case same register
mov.l #long_src, er0
mov.l @er0-, @er0- ; copying long_src to long_dst_dec
test_h_gr32 long_src-8 er0
cmp.l @long_src, @long_dst_dec
beq .Lnext77
fail
.Lnext77:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst_dec
cmp.l @long_src, @long_dst_dec
bne .Lnext78
fail
.Lnext78:
mov_l_preinc_to_preinc: ; reg pre-increment, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @+ers, @+erd
mov.l #long_src-4, er1
mov.l #long_dst-4, er0
mov.l @+er1, @+er0
;;; .word 0x0108
;;; .word 0x9190
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst er0
test_h_gr32 long_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext85
fail
.Lnext85:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext86
fail
.Lnext86: ; OK, pass on.
;; special case same register
mov.l #long_src-4, er0
mov.l @+er0, @+er0 ; copying long_src to long_dst
test_h_gr32 long_src+4 er0
cmp.b @long_src, @long_dst
beq .Lnext87
fail
.Lnext87:
;; Now clear the destination location, and verify that.
mov.b #0, @long_dst
cmp.b @long_src, @long_dst
bne .Lnext88
fail
.Lnext88:
mov_l_predec_to_predec: ; reg pre-decrement, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @-ers, @-erd
mov.l #long_src+4, er1
mov.l #long_dst+4, er0
mov.l @-er1, @-er0
;;; .word 0x0108
;;; .word 0xb1b0
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst er0
test_h_gr32 long_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext95
fail
.Lnext95:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext96
fail
.Lnext96: ; OK, pass on.
;; special case same register
mov.l #long_src+4, er0
mov.l @-er0, @-er0 ; copying long_src to long_dst_dec
test_h_gr32 long_src-4 er0
cmp.l @long_src, @long_dst_dec
beq .Lnext97
fail
.Lnext97:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst_dec
cmp.l @long_src, @long_dst_dec
bne .Lnext98
fail
.Lnext98:
mov_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @(dd:2, ers), @(dd:2, erd)
mov.l #long_src-4, er1
mov.l #long_dst-8, er0
mov.l @(4:2, er1), @(8:2, er0)
;;; .word 0x0108
;;; .word 0x1120
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst-8 er0
test_h_gr32 long_src-4 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext105
fail
.Lnext105:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext106
fail
.Lnext106: ; OK, pass on.
mov_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @(dd:16, ers), @(dd:16, erd)
mov.l #long_src-1, er1
mov.l #long_dst-2, er0
mov.l @(1:16, er1), @(2:16, er0)
;;; .word 0x0108
;;; .word 0xc1c0
;;; .word 0x0001
;;; .word 0x0002
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst-2 er0
test_h_gr32 long_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext115
fail
.Lnext115:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext116
fail
.Lnext116: ; OK, pass on.
mov_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @(dd:32, ers), @(dd:32, erd)
mov.l #long_src-1, er1
mov.l #long_dst-2, er0
mov.l @(1:32, er1), @(2:32, er0)
;;; .word 0x0108
;;; .word 0xc9c8
;;; .long 1
;;; .long 2
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst-2 er0
test_h_gr32 long_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext125
fail
.Lnext125:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext126
fail
.Lnext126: ; OK, pass on.
mov_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @aa:16, @aa:16
mov.l @long_src:16, @long_dst:16
;;; .word 0x0108
;;; .word 0x4040
;;; .word @long_src
;;; .word @long_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure *NO* general registers are changed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext135
fail
.Lnext135:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext136
fail
.Lnext136: ; OK, pass on.
mov_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.l @aa:32, @aa:32
mov.l @long_src:32, @long_dst:32
;;; .word 0x0108
;;; .word 0x4848
;;; .long @long_src
;;; .long @long_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure *NO* general registers are changed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l @long_src, @long_dst
beq .Lnext145
fail
.Lnext145:
;; Now clear the destination location, and verify that.
mov.l #0, @long_dst
cmp.l @long_src, @long_dst
bne .Lnext146
fail
.Lnext146: ; OK, pass on.
.endif
pass
exit 0
|
stsp/binutils-ia16
| 1,514
|
sim/testsuite/h8300/andw.s
|
# Hitachi H8 testcase 'and.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
and_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.w #xx:16,Rd
and.w #0xaaaa, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
and_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.w Rs,Rd
mov.w #0xaaaa, r1
and.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0
|
stsp/binutils-ia16
| 2,570
|
sim/testsuite/h8300/cmpw.s
|
# Hitachi H8 testcase 'cmp.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
cmp_w_imm3: ;
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w #xx:3,Rd ; Immediate 3-bit operand
mov.w #5, r0
cmp.w #5, r0
beq eq3
fail
eq3:
cmp.w #6, r0
blt lt3
fail
lt3:
cmp.w #4, r0
bgt gt3
fail
gt3:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a50005 er0 ; er0 unchanged
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; non-zero means h8300h, s, or sx
cmp_w_imm16: ; cmp.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w #xx:16,Rd
cmp.w #0xa5a5, r0 ; Immediate 16-bit operand
beq eqi
fail
eqi: cmp.w #0xa5a6, r0
blt lti
fail
lti: cmp.w #0xa5a4, r0
bgt gti
fail
gti:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a5 r0 ; r0 unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp_w_imm16_less_than_zero: ; Test for less-than-zero immediate
set_grs_a5a5
;; cmp.w #xx:16, Rd, where #xx < 0 (ie. #xx > 0x7fff).
sub.w r0, r0
cmp.w #0x8001, r0
bls ltz
fail
ltz: test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
cmp_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w Rs,Rd
mov.w #0xa5a5, r1
cmp.w r1, r0 ; Register operand
beq eqr
fail
eqr: mov.w #0xa5a6, r1
cmp.w r1, r0
blt ltr
fail
ltr: mov.w #0xa5a4, r1
cmp.w r1, r0
bgt gtr
fail
gtr:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a5 r0 ; r0 unchanged.
test_h_gr16 0xa5a4 r1 ; r1 unchanged.
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0
|
stsp/binutils-ia16
| 1,514
|
sim/testsuite/h8300/xorw.s
|
# Hitachi H8 testcase 'xor.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
xor_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.w #xx:16,Rd
xor.w #0xffff, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
xor_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.w Rs,Rd
mov.w #0xffff, r1
xor.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
test_h_gr16 0xffff r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0
|
stsp/binutils-ia16
| 8,117
|
sim/testsuite/h8300/stack.s
|
# Hitachi H8 testcase 'ldc'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 4
stack:
.if (sim_cpu == h8300)
.fill 128, 2, 0
.else
.fill 128, 4, 0
.endif
stacktop:
.text
push_w:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
.if (sim_cpu == h8300)
mov.w #stacktop, r7
.else
mov.l #stacktop, er7
.endif
push.w r0 ; a5a5 is negative
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
push.w r1
push.w r2
push.w r3
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
mov @stacktop-2, r0
test_gr_a5a5 0
mov @stacktop-4, r0
test_gr_a5a5 0
mov @stacktop-6, r0
test_gr_a5a5 0
mov @stacktop-8, r0
test_gr_a5a5 0
mov.w #1, r1
mov.w #2, r2
mov.w #3, r3
mov.w #4, r4
push.w r1 ; #1 is non-negative, non-zero
test_cc_clear
push.w r2
push.w r3
push.w r4
test_h_gr16 1 r1
test_h_gr16 2 r2
test_h_gr16 3 r3
test_h_gr16 4 r4
mov @stacktop-10, r0
test_h_gr16 1 r0
mov @stacktop-12, r0
test_h_gr16 2 r0
mov @stacktop-14, r0
test_h_gr16 3 r0
mov @stacktop-16, r0
test_h_gr16 4 r0
.if (sim_cpu == h8300)
test_h_gr16 4 r0
test_h_gr16 1 r1
test_h_gr16 2 r2
test_h_gr16 3 r3
test_h_gr16 4 r4
;;; test_h_gr16 stacktop-16 r7 ; FIXME
.else
test_h_gr32 0xa5a50004 er0
test_h_gr32 0xa5a50001 er1
test_h_gr32 0xa5a50002 er2
test_h_gr32 0xa5a50003 er3
test_h_gr32 0xa5a50004 er4
test_h_gr32 stacktop-16 er7
.endif
test_gr_a5a5 5
test_gr_a5a5 6
pop_w:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
.if (sim_cpu == h8300)
mov.w #stacktop-16, r7
.else
mov.l #stacktop-16, er7
.endif
pop.w r4
pop.w r3
pop.w r2
pop.w r1 ; Should set all flags zero
test_cc_clear
test_h_gr16 1 r1
test_h_gr16 2 r2
test_h_gr16 3 r3
test_h_gr16 4 r4
pop.w r4
pop.w r3
pop.w r2
pop.w r1 ; a5a5 is negative
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
.if (sim_cpu == h8300)
;;; test_h_gr16 stacktop r7 ; FIXME
.else
test_h_gr32 stacktop er7
.endif
.if (sim_cpu) ; non-zero means not h8300
push_l:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #stacktop, er7
push.l er0 ; a5a5 is negative
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
push.l er1
push.l er2
push.l er3
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
mov @stacktop-4, er0
test_gr_a5a5 0
mov @stacktop-8, er0
test_gr_a5a5 0
mov @stacktop-12, er0
test_gr_a5a5 0
mov @stacktop-16, er0
test_gr_a5a5 0
mov #1, er1
mov #2, er2
mov #3, er3
mov #4, er4
push.l er1 ; #1 is non-negative, non-zero
test_cc_clear
push.l er2
push.l er3
push.l er4
test_h_gr32 1 er1
test_h_gr32 2 er2
test_h_gr32 3 er3
test_h_gr32 4 er4
mov @stacktop-20, er0
test_h_gr32 1 er0
mov @stacktop-24, er0
test_h_gr32 2 er0
mov @stacktop-28, er0
test_h_gr32 3 er0
mov @stacktop-32, er0
test_h_gr32 4 er0
test_h_gr32 4 er0
test_h_gr32 1 er1
test_h_gr32 2 er2
test_h_gr32 3 er3
test_h_gr32 4 er4
test_gr_a5a5 5
test_gr_a5a5 6
test_h_gr32 stacktop-32 er7
pop_l:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov.l #stacktop-32, er7
pop.l er4
pop.l er3
pop.l er2
pop.l er1 ; Should set all flags zero
test_cc_clear
test_h_gr32 1 er1
test_h_gr32 2 er2
test_h_gr32 3 er3
test_h_gr32 4 er4
pop.l er4
pop.l er3
pop.l er2
pop.l er1 ; a5a5 is negative
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_h_gr32 stacktop er7
.endif
;; Jump over subroutine
jmp _bsr
bsr_jsr_func:
test_ccr 0 ; call should not affect ccr
mov.w #0, r0
mov.w #1, r1
mov.w #2, r2
mov.w #3, r3
mov.w #4, r4
mov.w #5, r5
mov.w #6, r6
rts
_bsr: set_grs_a5a5
.if (sim_cpu == h8300)
mov.w #stacktop, r7
.else
mov.l #stacktop, er7
.endif
set_ccr_zero
bsr bsr_jsr_func
test_h_gr16 0 r0
test_h_gr16 1 r1
test_h_gr16 2 r2
test_h_gr16 3 r3
test_h_gr16 4 r4
test_h_gr16 5 r5
test_h_gr16 6 r6
.if (sim_cpu == h8300)
;;; test_h_gr16 stacktop, r7 ; FIXME
.else
test_h_gr32 stacktop, er7
.endif
_jsr: set_grs_a5a5
.if (sim_cpu == h8300)
mov.w #stacktop, r7
.else
mov.l #stacktop, er7
.endif
set_ccr_zero
jsr bsr_jsr_func
test_h_gr16 0 r0
test_h_gr16 1 r1
test_h_gr16 2 r2
test_h_gr16 3 r3
test_h_gr16 4 r4
test_h_gr16 5 r5
test_h_gr16 6 r6
.if (sim_cpu == h8300)
;;; test_h_gr16 stacktop, r7 ; FIXME
.else
test_h_gr32 stacktop, er7
.endif
.if (sim_cpu) ; not zero ie. not h8300
_trapa:
set_grs_a5a5
mov.l #trap_handler, er7 ; trap vector
mov.l er7, @0x2c
mov.l #stacktop, er7
set_ccr_zero
trapa #3
test_cc_clear ; ccr should be restored by rte
test_h_gr16 0x10 r0
test_h_gr16 0x11 r1
test_h_gr16 0x12 r2
test_h_gr16 0x13 r3
test_h_gr16 0x14 r4
test_h_gr16 0x15 r5
test_h_gr16 0x16 r6
test_h_gr32 stacktop er7
.endif
.if (sim_cpu == h8sx)
_rtsl: ; Test rts/l insn.
set_grs_a5a5
mov #0,r0l
mov #1,r1l
mov #2,r2l
mov #3,r3l
mov #4,r4l
mov #5,r5l
mov #6,r6l
mov #stacktop, er7
jsr rtsl1_func
test_h_gr32 0xa5a5a500 er0
test_h_gr32 0xa5a5a501 er1
test_h_gr32 0xa5a5a502 er2
test_h_gr32 0xa5a5a503 er3
test_h_gr32 0xa5a5a504 er4
test_h_gr32 0xa5a5a505 er5
test_h_gr32 0xa5a5a506 er6
test_h_gr32 stacktop er7
jsr rtsl2_func
test_h_gr32 0xa5a5a500 er0
test_h_gr32 0xa5a5a501 er1
test_h_gr32 0xa5a5a502 er2
test_h_gr32 0xa5a5a503 er3
test_h_gr32 0xa5a5a504 er4
test_h_gr32 0xa5a5a505 er5
test_h_gr32 0xa5a5a506 er6
test_h_gr32 stacktop er7
jsr rtsl3_func
test_h_gr32 0xa5a5a500 er0
test_h_gr32 0xa5a5a501 er1
test_h_gr32 0xa5a5a502 er2
test_h_gr32 0xa5a5a503 er3
test_h_gr32 0xa5a5a504 er4
test_h_gr32 0xa5a5a505 er5
test_h_gr32 0xa5a5a506 er6
test_h_gr32 stacktop er7
jsr rtsl4_func
test_h_gr32 0xa5a5a500 er0
test_h_gr32 0xa5a5a501 er1
test_h_gr32 0xa5a5a502 er2
test_h_gr32 0xa5a5a503 er3
test_h_gr32 0xa5a5a504 er4
test_h_gr32 0xa5a5a505 er5
test_h_gr32 0xa5a5a506 er6
test_h_gr32 stacktop er7
.endif ; h8sx
pass
exit 0
;; Handler for a software exception (trap).
trap_handler:
;; Test the 'i' interrupt mask flag.
stc ccr, r0l
test_h_gr8 0x80, r0l
;; Change the registers (so we know we've been here)
mov.w #0x10, r0
mov.w #0x11, r1
mov.w #0x12, r2
mov.w #0x13, r3
mov.w #0x14, r4
mov.w #0x15, r5
mov.w #0x16, r6
;; Change the ccr (which will be restored by RTE)
orc #0xff, ccr
rte
.if (sim_cpu == h8sx)
;; Functions for testing rts/l
rtsl1_func: ; Save and restore R0
push.l er0
;; Now modify it, and verify the modification.
mov #0xfeedface, er0
test_h_gr32 0xfeedface, er0
;; Then use rts/l to restore them and return.
rts/l er0
rtsl2_func: ; Save and restore R5 and R6
push.l er5
push.l er6
;; Now modify them, and verify the modification.
mov #0xdeadbeef, er5
mov #0xfeedface, er6
test_h_gr32 0xdeadbeef, er5
test_h_gr32 0xfeedface, er6
;; Then use rts/l to restore them and return.
rts/l (er5-er6)
rtsl3_func: ; Save and restore R4, R5, and R6
push.l er4
push.l er5
push.l er6
;; Now modify them, and verify the modification.
mov #0xdeafcafe, er4
mov #0xdeadbeef, er5
mov #0xfeedface, er6
test_h_gr32 0xdeafcafe, er4
test_h_gr32 0xdeadbeef, er5
test_h_gr32 0xfeedface, er6
;; Then use rts/l to restore them and return.
rts/l (er4-er6)
rtsl4_func: ; Save and restore R0 - R3
push.l er0
push.l er1
push.l er2
push.l er3
;; Now modify them, and verify the modification.
mov #0xdadacafe, er0
mov #0xfeedbeef, er1
mov #0xdeadface, er2
mov #0xf00dd00d, er3
test_h_gr32 0xdadacafe, er0
test_h_gr32 0xfeedbeef, er1
test_h_gr32 0xdeadface, er2
test_h_gr32 0xf00dd00d, er3
;; Then use rts/l to restore them and return.
rts/l (er0-er3)
.endif ; h8sx
|
stsp/binutils-ia16
| 2,015
|
sim/testsuite/h8300/brabc.s
|
# Hitachi H8 testcase 'bra/bc'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src: .byte 0xa5
start
.if (sim_cpu == h8sx)
brabc_ind_disp8:
set_grs_a5a5
mov #byte_src, er1
set_ccr_zero
;; bra/bc xx:3, @erd, disp8
bra/bc #1, @er1, .Lpass1:8
;;; .word 0x7c10
;;; .word 0x4110
fail
.Lpass1:
bra/bc #2, @er1, .Lfail1:8
;;; .word 0x7c10
;;; .word 0x4202
bra .Lpass2
.Lfail1:
fail
.Lpass2:
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 byte_src er1
test_h_gr32 0xa5a5a5a5 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
brabc_abs8_disp16:
set_grs_a5a5
mov.b #0xa5, @0x20:32
set_ccr_zero
;; bra/bc xx:3, @aa:8, disp16
bra/bc #1, @0x20:8, .Lpass3:16
fail
.Lpass3:
bra/bc #2, @0x20:8, Lfail:16
test_cc_clear
test_grs_a5a5
brabc_abs16_disp16:
set_grs_a5a5
set_ccr_zero
;; bra/bc xx:3, @aa:16, disp16
bra/bc #1, @byte_src:16, .Lpass5:16
fail
.Lpass5:
bra/bc #2, @byte_src:16, Lfail:16
test_cc_clear
test_grs_a5a5
brabs_ind_disp8:
set_grs_a5a5
mov #byte_src, er1
set_ccr_zero
;; bra/bs xx:3, @erd, disp8
bra/bs #2, @er1, .Lpass7:8
;;; .word 0x7c10
;;; .word 0x4a10
fail
.Lpass7:
bra/bs #1, @er1, .Lfail3:8
;;; .word 0x7c10
;;; .word 0x4902
bra .Lpass8
.Lfail3:
fail
.Lpass8:
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 byte_src er1
test_h_gr32 0xa5a5a5a5 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
brabs_abs32_disp16:
set_grs_a5a5
set_ccr_zero
;; bra/bs xx:3, @aa:32, disp16
bra/bs #2, @byte_src:32, .Lpass9:16
fail
.Lpass9:
bra/bs #1, @byte_src:32, Lfail:16
test_cc_clear
test_grs_a5a5
.endif
pass
exit 0
Lfail: fail
|
stsp/binutils-ia16
| 1,997
|
sim/testsuite/h8300/subw.s
|
# Hitachi H8 testcase 'sub.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
sub_w_imm3: ; sub.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w #xx:3,Rd ; Immediate 3-bit operand
sub.w #7:3, r0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7
test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; non-zero means h8300h, s, or sx
sub_w_imm16: ; sub.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w #xx:16,Rd
sub.w #0x111, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
sub.w.reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w Rs,Rd
mov.w #0x111, r1
sub.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
test_h_gr16 0x0111 r1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
test_h_gr32 0xa5a50111 er1
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0
|
stsp/binutils-ia16
| 1,727
|
sim/testsuite/h8300/xorl.s
|
# Hitachi H8 testcase 'xor.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
xor_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l #xx:16,Rd
xor.l #0xffff:16, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
xor_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l #xx:32,Rd
xor.l #0xffffffff, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
xor_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l Rs,Rd
mov.l #0xffffffff, er1
xor.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff
test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0
|
stsp/binutils-ia16
| 1,726
|
sim/testsuite/h8300/andl.s
|
# Hitachi H8 testcase 'and.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
and_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l #xx:16,Rd
and.l #0xaaaa:16, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
and_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l #xx:32,Rd
and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
and_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l Rs,Rd
mov.l #0xaaaaaaaa, er1
and.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa
test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0
|
stsp/binutils-ia16
| 2,599
|
sim/testsuite/h8300/dec.s
|
# Hitachi H8 testcase 'dec.b, dec.w, dec.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
dec_b:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.b Rd
dec.b r0h ; Decrement 8-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa4a5 r0 ; dec result: a4|a5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; non-zero means h8300h, s, or sx
dec_w_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.w #1, Rd
dec.w #1, r0 ; Decrement 16-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a4 r0 ; dec result: a5|a4
test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
dec_w_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.w #2, Rd
dec.w #2, r0 ; Decrement 16-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a3 r0 ; dec result: a5|a3
test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
dec_l_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.l #1, eRd
dec.l #1, er0 ; Decrement 32-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
dec_l_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.l #2, eRd
dec.l #2, er0 ; Decrement 32-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0
|
stsp/binutils-ia16
| 38,858
|
sim/testsuite/h8300/rotr.s
|
# Hitachi H8 testcase 'rotr'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
rotr_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.b r0l ; shift right arithmetic by one
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010
.if (sim_cpu)
test_h_gr32 0xa5a5a5d2 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotr_b_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotr.b @er0 ; shift right arithmetic by one, indirect
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbind1
fail
.Lbind1:
mov.b #0xa5, @byte_dest
rotr_b_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotr.b @er0+ ; shift right arithmetic by one, postinc
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbpostinc1
fail
.Lbpostinc1:
mov.b #0xa5, @byte_dest
rotr_b_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotr.b @er0- ; shift right arithmetic by one, postdec
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbpostdec1
fail
.Lbpostdec1:
mov.b #0xa5, @byte_dest
rotr_b_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
rotr.b @+er0 ; shift right arithmetic by one, preinc
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbpreinc1
fail
.Lbpreinc1:
mov.b #0xa5, @byte_dest
rotr_b_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
rotr.b @-er0 ; shift right arithmetic by one, predec
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbpredec1
fail
.Lbpredec1:
mov.b #0xa5, @byte_dest
rotr_b_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
rotr.b @(2:2, er0) ; shift right arithmetic by one, disp2
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbdisp21
fail
.Lbdisp21:
mov.b #0xa5, @byte_dest
rotr_b_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
rotr.b @(44:16, er0) ; shift right arithmetic by one, disp16
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbdisp161
fail
.Lbdisp161:
mov.b #0xa5, @byte_dest
rotr_b_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
rotr.b @(666:32, er0) ; shift right arithmetic by one, disp32
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbdisp321
fail
.Lbdisp321:
mov.b #0xa5, @byte_dest
rotr_b_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.b @byte_dest:16 ; shift right arithmetic by one, abs16
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbabs161
fail
.Lbabs161:
mov.b #0xa5, @byte_dest
rotr_b_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.b @byte_dest:32 ; shift right arithmetic by one, abs32
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbabs321
fail
.Lbabs321:
mov.b #0xa5, @byte_dest
.endif
rotr_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.b #2, r0l ; shift right arithmetic by two
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa569 r0 ; 1010 0101 -> 0110 1001
.if (sim_cpu)
test_h_gr32 0xa5a5a569 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotr_b_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotr.b #2, @er0 ; shift right arithmetic by two, indirect
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbind2
fail
.Lbind2:
mov.b #0xa5, @byte_dest
rotr_b_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotr.b #2, @er0+ ; shift right arithmetic by two, postinc
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbpostinc2
fail
.Lbpostinc2:
mov.b #0xa5, @byte_dest
rotr_b_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotr.b #2, @er0- ; shift right arithmetic by two, postdec
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbpostdec2
fail
.Lbpostdec2:
mov.b #0xa5, @byte_dest
rotr_b_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
rotr.b #2, @+er0 ; shift right arithmetic by two, preinc
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbpreinc2
fail
.Lbpreinc2:
mov.b #0xa5, @byte_dest
rotr_b_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
rotr.b #2, @-er0 ; shift right arithmetic by two, predec
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbpredec2
fail
.Lbpredec2:
mov.b #0xa5, @byte_dest
rotr_b_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
rotr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbdisp22
fail
.Lbdisp22:
mov.b #0xa5, @byte_dest
rotr_b_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
rotr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbdisp162
fail
.Lbdisp162:
mov.b #0xa5, @byte_dest
rotr_b_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
rotr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbdisp322
fail
.Lbdisp322:
mov.b #0xa5, @byte_dest
rotr_b_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbabs162
fail
.Lbabs162:
mov.b #0xa5, @byte_dest
rotr_b_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0110 1001
cmp.b #0x69, @byte_dest
beq .Lbabs322
fail
.Lbabs322:
mov.b #0xa5, @byte_dest
.endif
.if (sim_cpu) ; Not available in h8300 mode
rotr_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.w r0 ; shift right arithmetic by one
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
test_h_gr32 0xa5a5d2d2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotr_w_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotr.w @er0 ; shift right arithmetic by one, indirect
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwind1
fail
.Lwind1:
mov.w #0xa5a5, @word_dest
rotr_w_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotr.w @er0+ ; shift right arithmetic by one, postinc
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwpostinc1
fail
.Lwpostinc1:
mov.w #0xa5a5, @word_dest
rotr_w_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotr.w @er0- ; shift right arithmetic by one, postdec
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwpostdec1
fail
.Lwpostdec1:
mov.w #0xa5a5, @word_dest
rotr_w_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
rotr.w @+er0 ; shift right arithmetic by one, preinc
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwpreinc1
fail
.Lwpreinc1:
mov.w #0xa5a5, @word_dest
rotr_w_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
rotr.w @-er0 ; shift right arithmetic by one, predec
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwpredec1
fail
.Lwpredec1:
mov.w #0xa5a5, @word_dest
rotr_w_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
rotr.w @(4:2, er0) ; shift right arithmetic by one, disp2
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwdisp21
fail
.Lwdisp21:
mov.w #0xa5a5, @word_dest
rotr_w_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
rotr.w @(44:16, er0) ; shift right arithmetic by one, disp16
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwdisp161
fail
.Lwdisp161:
mov.w #0xa5a5, @word_dest
rotr_w_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
rotr.w @(666:32, er0) ; shift right arithmetic by one, disp32
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwdisp321
fail
.Lwdisp321:
mov.w #0xa5a5, @word_dest
rotr_w_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.w @word_dest:16 ; shift right arithmetic by one, abs16
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwabs161
fail
.Lwabs161:
mov.w #0xa5a5, @word_dest
rotr_w_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.w @word_dest:32 ; shift right arithmetic by one, abs32
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwabs321
fail
.Lwabs321:
mov.w #0xa5a5, @word_dest
.endif
rotr_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.w #2, r0 ; shift right arithmetic by two
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x6969 r0 ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
test_h_gr32 0xa5a56969 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotr_w_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotr.w #2, @er0 ; shift right arithmetic by two, indirect
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwind2
fail
.Lwind2:
mov.w #0xa5a5, @word_dest
rotr_w_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotr.w #2, @er0+ ; shift right arithmetic by two, postinc
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwpostinc2
fail
.Lwpostinc2:
mov.w #0xa5a5, @word_dest
rotr_w_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotr.w #2, @er0- ; shift right arithmetic by two, postdec
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwpostdec2
fail
.Lwpostdec2:
mov.w #0xa5a5, @word_dest
rotr_w_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
rotr.w #2, @+er0 ; shift right arithmetic by two, preinc
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwpreinc2
fail
.Lwpreinc2:
mov.w #0xa5a5, @word_dest
rotr_w_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
rotr.w #2, @-er0 ; shift right arithmetic by two, predec
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwpredec2
fail
.Lwpredec2:
mov.w #0xa5a5, @word_dest
rotr_w_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
rotr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwdisp22
fail
.Lwdisp22:
mov.w #0xa5a5, @word_dest
rotr_w_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
rotr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwdisp162
fail
.Lwdisp162:
mov.w #0xa5a5, @word_dest
rotr_w_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
rotr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwdisp322
fail
.Lwdisp322:
mov.w #0xa5a5, @word_dest
rotr_w_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwabs162
fail
.Lwabs162:
mov.w #0xa5a5, @word_dest
rotr_w_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0110 1001 0110 1001
cmp.w #0x6969, @word_dest
beq .Lwabs322
fail
.Lwabs322:
mov.w #0xa5a5, @word_dest
.endif
rotr_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.l er0 ; shift right arithmetic by one, register
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1101 0010 1101 0010 1101 0010 1101 0010
test_h_gr32 0xd2d2d2d2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotr_l_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotr.l @er0 ; shift right arithmetic by one, indirect
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llind1
fail
.Llind1:
mov #0xa5a5a5a5, @long_dest
rotr_l_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotr.l @er0+ ; shift right arithmetic by one, postinc
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llpostinc1
fail
.Llpostinc1:
mov #0xa5a5a5a5, @long_dest
rotr_l_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotr.l @er0- ; shift right arithmetic by one, postdec
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llpostdec1
fail
.Llpostdec1:
mov #0xa5a5a5a5, @long_dest
rotr_l_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
rotr.l @+er0 ; shift right arithmetic by one, preinc
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llpreinc1
fail
.Llpreinc1:
mov #0xa5a5a5a5, @long_dest
rotr_l_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
rotr.l @-er0 ; shift right arithmetic by one, predec
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llpredec1
fail
.Llpredec1:
mov #0xa5a5a5a5, @long_dest
rotr_l_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
rotr.l @(8:2, er0) ; shift right arithmetic by one, disp2
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Lldisp21
fail
.Lldisp21:
mov #0xa5a5a5a5, @long_dest
rotr_l_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
rotr.l @(44:16, er0) ; shift right arithmetic by one, disp16
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Lldisp161
fail
.Lldisp161:
mov #0xa5a5a5a5, @long_dest
rotr_l_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
rotr.l @(666:32, er0) ; shift right arithmetic by one, disp32
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Lldisp321
fail
.Lldisp321:
mov #0xa5a5a5a5, @long_dest
rotr_l_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.l @long_dest:16 ; shift right arithmetic by one, abs16
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llabs161
fail
.Llabs161:
mov #0xa5a5a5a5, @long_dest
rotr_l_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.l @long_dest:32 ; shift right arithmetic by one, abs32
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llabs321
fail
.Llabs321:
mov #0xa5a5a5a5, @long_dest
.endif
rotr_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.l #2, er0 ; shift right arithmetic by two, register
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0110 1001 0110 1001 0110 1001 0110 1001
test_h_gr32 0x69696969 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotr_l_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotr.l #2, @er0 ; shift right arithmetic by two, indirect
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Llind2
fail
.Llind2:
mov #0xa5a5a5a5, @long_dest
rotr_l_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotr.l #2, @er0+ ; shift right arithmetic by two, postinc
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Llpostinc2
fail
.Llpostinc2:
mov #0xa5a5a5a5, @long_dest
rotr_l_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotr.l #2, @er0- ; shift right arithmetic by two, postdec
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Llpostdec2
fail
.Llpostdec2:
mov #0xa5a5a5a5, @long_dest
rotr_l_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
rotr.l #2, @+er0 ; shift right arithmetic by two, preinc
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Llpreinc2
fail
.Llpreinc2:
mov #0xa5a5a5a5, @long_dest
rotr_l_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
rotr.l #2, @-er0 ; shift right arithmetic by two, predec
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Llpredec2
fail
.Llpredec2:
mov #0xa5a5a5a5, @long_dest
rotr_l_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
rotr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Lldisp22
fail
.Lldisp22:
mov #0xa5a5a5a5, @long_dest
rotr_l_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
rotr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Lldisp162
fail
.Lldisp162:
mov #0xa5a5a5a5, @long_dest
rotr_l_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
rotr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Lldisp322
fail
.Lldisp322:
mov #0xa5a5a5a5, @long_dest
rotr_l_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Llabs162
fail
.Llabs162:
mov #0xa5a5a5a5, @long_dest
rotr_l_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x69696969, @long_dest
beq .Llabs322
fail
.Llabs322:
mov #0xa5a5a5a5, @long_dest
.endif
.endif
pass
exit 0
|
stsp/binutils-ia16
| 2,209
|
sim/testsuite/h8300/movmd.s
|
# Hitachi H8 testcase 'movmd'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src:
.byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
byte_dst:
.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
.align 2
word_src:
.word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
word_dst:
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
.align 4
long_src:
.long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
long_dst:
.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
start
.if (sim_cpu == h8sx)
movmd_b:#
# Byte block transfer
#
set_grs_a5a5
mov #byte_src, er5
mov #byte_dst, er6
mov #10, r4
set_ccr_zero
;; movmd.b
movmd.b
;;; .word 0x7b94
test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50000 er4
test_h_gr32 byte_src+10 er5
test_h_gr32 byte_dst+10 er6
test_gr_a5a5 7
#
# Now make sure exactly 10 bytes were transferred.
memcmp byte_src byte_dst 10
cmp.b #0, @byte_dst+10
beq .L0
fail
.L0:
movmd_w:#
# Word block transfer
#
set_grs_a5a5
mov #word_src, er5
mov #word_dst, er6
mov #10, r4
set_ccr_zero
;; movmd.w
movmd.w
;;; .word 0x7ba4
test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50000 er4
test_h_gr32 word_src+20 er5
test_h_gr32 word_dst+20 er6
test_gr_a5a5 7
#
# Now make sure exactly 20 bytes were transferred.
memcmp word_src word_dst 20
cmp.w #0, @word_dst+20
beq .L1
fail
.L1:
movmd_l:#
# Long block transfer
#
set_grs_a5a5
mov #long_src, er5
mov #long_dst, er6
mov #10, r4
set_ccr_zero
;; movmd.b
movmd.l
;;; .word 0x7bb4
test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50000 er4
test_h_gr32 long_src+40 er5
test_h_gr32 long_dst+40 er6
test_gr_a5a5 7
#
# Now make sure exactly 40 bytes were transferred.
memcmp long_src long_dst 40
cmp.l #0, @long_dst+40
beq .L2
fail
.L2:
.endif
pass
exit 0
|
stsp/binutils-ia16
| 87,156
|
sim/testsuite/h8300/shlr.s
|
# Hitachi H8 testcase 'shlr'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
shlr_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b r0l ; shift right logical by one
;;; .word 0x1108
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010
.if (sim_cpu)
test_h_gr32 0xa5a5a552 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shlr_b_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b @er0 ; shift right logical by one, indirect
;;; .word 0x7d00
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbind1
fail
.Lbind1:
mov.b #0xa5, @byte_dest
shlr_b_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b @er0+ ; shift right logical by one, postinc
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbpostinc1
fail
.Lbpostinc1:
mov.b #0xa5, @byte_dest
shlr_b_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b @er0- ; shift right logical by one, postdec
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbpostdec1
fail
.Lbpostdec1:
mov.b #0xa5, @byte_dest
shlr_b_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
shlr.b @+er0 ; shift right logical by one, preinc
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbpreinc1
fail
.Lbpreinc1:
mov.b #0xa5, @byte_dest
shlr_b_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
shlr.b @-er0 ; shift right logical by one, predec
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbpredec1
fail
.Lbpredec1:
mov.b #0xa5, @byte_dest
shlr_b_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
shlr.b @(2:2, er0) ; shift right logical by one, disp2
;;; .word 0x0176
;;; .word 0x6808
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbdisp21
fail
.Lbdisp21:
mov.b #0xa5, @byte_dest
shlr_b_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
shlr.b @(44:16, er0) ; shift right logical by one, disp16
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 44
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbdisp161
fail
.Lbdisp161:
mov.b #0xa5, @byte_dest
shlr_b_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
shlr.b @(666:32, er0) ; shift right logical by one, disp32
;;; .word 0x7884
;;; .word 0x6a28
;;; .long 666
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbdisp321
fail
.Lbdisp321:
mov.b #0xa5, @byte_dest
shlr_b_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b @byte_dest:16 ; shift right logical by one, abs16
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbabs161
fail
.Lbabs161:
mov.b #0xa5, @byte_dest
shlr_b_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b @byte_dest:32 ; shift right logical by one, abs32
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x1100
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbabs321
fail
.Lbabs321:
mov.b #0xa5, @byte_dest
.endif
shlr_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b #2, r0l ; shift right logical by two
;;; .word 0x1148
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa529 r0 ; 1010 0101 -> 0010 1001
.if (sim_cpu)
test_h_gr32 0xa5a5a529 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shlr_b_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b #2, @er0 ; shift right logical by two, indirect
;;; .word 0x7d00
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbind2
fail
.Lbind2:
mov.b #0xa5, @byte_dest
shlr_b_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b #2, @er0+ ; shift right logical by two, postinc
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbpostinc2
fail
.Lbpostinc2:
mov.b #0xa5, @byte_dest
shlr_b_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b #2, @er0- ; shift right logical by two, postdec
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbpostdec2
fail
.Lbpostdec2:
mov.b #0xa5, @byte_dest
shlr_b_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
shlr.b #2, @+er0 ; shift right logical by two, preinc
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbpreinc2
fail
.Lbpreinc2:
mov.b #0xa5, @byte_dest
shlr_b_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
shlr.b #2, @-er0 ; shift right logical by two, predec
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbpredec2
fail
.Lbpredec2:
mov.b #0xa5, @byte_dest
shlr_b_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
shlr.b #2, @(2:2, er0) ; shift right logical by two, disp2
;;; .word 0x0176
;;; .word 0x6808
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbdisp22
fail
.Lbdisp22:
mov.b #0xa5, @byte_dest
shlr_b_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
shlr.b #2, @(44:16, er0) ; shift right logical by two, disp16
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 44
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbdisp162
fail
.Lbdisp162:
mov.b #0xa5, @byte_dest
shlr_b_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
shlr.b #2, @(666:32, er0) ; shift right logical by two, disp32
;;; .word 0x7884
;;; .word 0x6a28
;;; .long 666
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbdisp322
fail
.Lbdisp322:
mov.b #0xa5, @byte_dest
shlr_b_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b #2, @byte_dest:16 ; shift right logical by two, abs16
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbabs162
fail
.Lbabs162:
mov.b #0xa5, @byte_dest
shlr_b_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b #2, @byte_dest:32 ; shift right logical by two, abs32
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x1140
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0010 1001
cmp.b #0x29, @byte_dest
beq .Lbabs322
fail
.Lbabs322:
mov.b #0xa5, @byte_dest
shlr_b_reg8_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b #4, r0l ; shift right logical by four
;;; .word 0x11a8
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa50a r0 ; 1010 0101 -> 0000 1010
test_h_gr32 0xa5a5a50a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #5, r0h
shlr.b r0h, r0l ; shift right logical by register value
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x0505 r0 ; 1010 0101 -> 0000 0101
test_h_gr32 0xa5a50505 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_b_ind_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b #4, @er0 ; shift right logical by four, indirect
;;; .word 0x7d00
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbind4
fail
.Lbind4:
mov.b #0xa5, @byte_dest
shlr_b_postinc_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b #4, @er0+ ; shift right logical by four, postinc
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbpostinc4
fail
.Lbpostinc4:
mov.b #0xa5, @byte_dest
shlr_b_postdec_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shlr.b #4, @er0- ; shift right logical by four, postdec
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbpostdec4
fail
.Lbpostdec4:
mov.b #0xa5, @byte_dest
shlr_b_preinc_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
shlr.b #4, @+er0 ; shift right logical by four, preinc
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbpreinc4
fail
.Lbpreinc4:
mov.b #0xa5, @byte_dest
shlr_b_predec_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
shlr.b #4, @-er0 ; shift right logical by four, predec
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbpredec4
fail
.Lbpredec4:
mov.b #0xa5, @byte_dest
shlr_b_disp2_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
shlr.b #4, @(2:2, er0) ; shift right logical by four, disp2
;;; .word 0x0176
;;; .word 0x6808
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbdisp24
fail
.Lbdisp24:
mov.b #0xa5, @byte_dest
shlr_b_disp16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
shlr.b #4, @(44:16, er0) ; shift right logical by four, disp16
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 44
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbdisp164
fail
.Lbdisp164:
mov.b #0xa5, @byte_dest
shlr_b_disp32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
shlr.b #4, @(666:32, er0) ; shift right logical by four, disp32
;;; .word 0x7884
;;; .word 0x6a28
;;; .long 666
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbdisp324
fail
.Lbdisp324:
mov.b #0xa5, @byte_dest
shlr_b_abs16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b #4, @byte_dest:16 ; shift right logical by four, abs16
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbabs164
fail
.Lbabs164:
mov.b #0xa5, @byte_dest
shlr_b_abs32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.b #4, @byte_dest:32 ; shift right logical by four, abs32
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x11a0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0000 1010
cmp.b #0x0a, @byte_dest
beq .Lbabs324
fail
.Lbabs324:
mov.b #0xa5, @byte_dest
.endif
.if (sim_cpu == h8sx)
shlr_w_imm5_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #15:5, r0 ; shift right logical by 5-bit immediate
;;; .word 0x038f
;;; .word 0x1110
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 -> 0000 0000 0000 0001
test_h_gr32 0xa5a50001 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; Not available in h8300 mode
shlr_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w r0 ; shift right logical by one
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
test_h_gr32 0xa5a552d2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shlr_w_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w @er0 ; shift right logical by one, indirect
;;; .word 0x7d80
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwind1
fail
.Lwind1:
mov.w #0xa5a5, @word_dest
shlr_w_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w @er0+ ; shift right logical by one, postinc
;;; .word 0x0154
;;; .word 0x6d08
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwpostinc1
fail
.Lwpostinc1:
mov.w #0xa5a5, @word_dest
shlr_w_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w @er0- ; shift right logical by one, postdec
;;; .word 0x0156
;;; .word 0x6d08
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwpostdec1
fail
.Lwpostdec1:
mov.w #0xa5a5, @word_dest
shlr_w_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
shlr.w @+er0 ; shift right logical by one, preinc
;;; .word 0x0155
;;; .word 0x6d08
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwpreinc1
fail
.Lwpreinc1:
mov.w #0xa5a5, @word_dest
shlr_w_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
shlr.w @-er0 ; shift right logical by one, predec
;;; .word 0x0157
;;; .word 0x6d08
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwpredec1
fail
.Lwpredec1:
mov.w #0xa5a5, @word_dest
shlr_w_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
shlr.w @(4:2, er0) ; shift right logical by one, disp2
;;; .word 0x0156
;;; .word 0x6908
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwdisp21
fail
.Lwdisp21:
mov.w #0xa5a5, @word_dest
shlr_w_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
shlr.w @(44:16, er0) ; shift right logical by one, disp16
;;; .word 0x0154
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwdisp161
fail
.Lwdisp161:
mov.w #0xa5a5, @word_dest
shlr_w_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
shlr.w @(666:32, er0) ; shift right logical by one, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwdisp321
fail
.Lwdisp321:
mov.w #0xa5a5, @word_dest
shlr_w_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w @word_dest:16 ; shift right logical by one, abs16
;;; .word 0x6b18
;;; .word word_dest
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwabs161
fail
.Lwabs161:
mov.w #0xa5a5, @word_dest
shlr_w_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w @word_dest:32 ; shift right logical by one, abs32
;;; .word 0x6b38
;;; .long word_dest
;;; .word 0x1110
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwabs321
fail
.Lwabs321:
mov.w #0xa5a5, @word_dest
.endif
shlr_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #2, r0 ; shift right logical by two
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x2969 r0 ; 1010 0101 1010 0101 -> 0010 1001 0110 1001
test_h_gr32 0xa5a52969 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shlr_w_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #2, @er0 ; shift right logical by two, indirect
;;; .word 0x7d80
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwind2
fail
.Lwind2:
mov.w #0xa5a5, @word_dest
shlr_w_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #2, @er0+ ; shift right logical by two, postinc
;;; .word 0x0154
;;; .word 0x6d08
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwpostinc2
fail
.Lwpostinc2:
mov.w #0xa5a5, @word_dest
shlr_w_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #2, @er0- ; shift right logical by two, postdec
;;; .word 0x0156
;;; .word 0x6d08
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwpostdec2
fail
.Lwpostdec2:
mov.w #0xa5a5, @word_dest
shlr_w_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
shlr.w #2, @+er0 ; shift right logical by two, preinc
;;; .word 0x0155
;;; .word 0x6d08
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwpreinc2
fail
.Lwpreinc2:
mov.w #0xa5a5, @word_dest
shlr_w_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
shlr.w #2, @-er0 ; shift right logical by two, predec
;;; .word 0x0157
;;; .word 0x6d08
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwpredec2
fail
.Lwpredec2:
mov.w #0xa5a5, @word_dest
shlr_w_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
shlr.w #2, @(4:2, er0) ; shift right logical by two, disp2
;;; .word 0x0156
;;; .word 0x6908
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwdisp22
fail
.Lwdisp22:
mov.w #0xa5a5, @word_dest
shlr_w_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
shlr.w #2, @(44:16, er0) ; shift right logical by two, disp16
;;; .word 0x0154
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwdisp162
fail
.Lwdisp162:
mov.w #0xa5a5, @word_dest
shlr_w_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
shlr.w #2, @(666:32, er0) ; shift right logical by two, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwdisp322
fail
.Lwdisp322:
mov.w #0xa5a5, @word_dest
shlr_w_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #2, @word_dest:16 ; shift right logical by two, abs16
;;; .word 0x6b18
;;; .word word_dest
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwabs162
fail
.Lwabs162:
mov.w #0xa5a5, @word_dest
shlr_w_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #2, @word_dest:32 ; shift right logical by two, abs32
;;; .word 0x6b38
;;; .long word_dest
;;; .word 0x1150
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0010 1001 0110 1001
cmp.w #0x2969, @word_dest
beq .Lwabs322
fail
.Lwabs322:
mov.w #0xa5a5, @word_dest
shlr_w_reg16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #4, r0 ; shift right logical by four
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x0a5a r0 ; 1010 0101 1010 0101 -> 0000 1010 0101 1010
test_h_gr32 0xa5a50a5a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_w_reg16_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #5, r1l
shlr.w r1l, r0 ; shift right logical by register value
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x052d r0 ; 1010 0101 1010 0101 -> 0000 0101 0010 1101
test_h_gr32 0xa5a5052d er0
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_w_ind_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #4, @er0 ; shift right logical by four, indirect
;;; .word 0x7d80
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwind4
fail
.Lwind4:
mov.w #0xa5a5, @word_dest
shlr_w_postinc_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #4, @er0+ ; shift right logical by four, postinc
;;; .word 0x0154
;;; .word 0x6d08
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwpostinc4
fail
.Lwpostinc4:
mov.w #0xa5a5, @word_dest
shlr_w_postdec_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #4, @er0- ; shift right logical by four, postdec
;;; .word 0x0156
;;; .word 0x6d08
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwpostdec4
fail
.Lwpostdec4:
mov.w #0xa5a5, @word_dest
shlr_w_preinc_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
shlr.w #4, @+er0 ; shift right logical by four, preinc
;;; .word 0x0155
;;; .word 0x6d08
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwpreinc4
fail
.Lwpreinc4:
mov.w #0xa5a5, @word_dest
shlr_w_predec_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
shlr.w #4, @-er0 ; shift right logical by four, predec
;;; .word 0x0157
;;; .word 0x6d08
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwpredec4
fail
.Lwpredec4:
mov.w #0xa5a5, @word_dest
shlr_w_disp2_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
shlr.w #4, @(4:2, er0) ; shift right logical by four, disp2
;;; .word 0x0156
;;; .word 0x6908
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwdisp24
fail
.Lwdisp24:
mov.w #0xa5a5, @word_dest
shlr_w_disp16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
shlr.w #4, @(44:16, er0) ; shift right logical by four, disp16
;;; .word 0x0154
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwdisp164
fail
.Lwdisp164:
mov.w #0xa5a5, @word_dest
shlr_w_disp32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
shlr.w #4, @(666:32, er0) ; shift right logical by four, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwdisp324
fail
.Lwdisp324:
mov.w #0xa5a5, @word_dest
shlr_w_abs16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #4, @word_dest:16 ; shift right logical by four, abs16
;;; .word 0x6b18
;;; .word word_dest
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwabs164
fail
.Lwabs164:
mov.w #0xa5a5, @word_dest
shlr_w_abs32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #4, @word_dest:32 ; shift right logical by four, abs32
;;; .word 0x6b38
;;; .long word_dest
;;; .word 0x1120
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 1010 0101 1010
cmp.w #0x0a5a, @word_dest
beq .Lwabs324
fail
.Lwabs324:
mov.w #0xa5a5, @word_dest
shlr_w_reg16_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #8, r0 ; shift right logical by eight
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x00a5 r0 ; 1010 0101 1010 0101 -> 0000 0000 1010 0101
test_h_gr32 0xa5a500a5 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_w_ind_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #8, @er0 ; shift right logical by eight, indirect
;;; .word 0x7d80
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwind8
fail
.Lwind8:
mov.w #0xa5a5, @word_dest
shlr_w_postinc_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #8, @er0+ ; shift right logical by eight, postinc
;;; .word 0x0154
;;; .word 0x6d08
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwpostinc8
fail
.Lwpostinc8:
mov.w #0xa5a5, @word_dest
shlr_w_postdec_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shlr.w #8, @er0- ; shift right logical by eight, postdec
;;; .word 0x0156
;;; .word 0x6d08
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwpostdec8
fail
.Lwpostdec8:
mov.w #0xa5a5, @word_dest
shlr_w_preinc_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
shlr.w #8, @+er0 ; shift right logical by eight, preinc
;;; .word 0x0155
;;; .word 0x6d08
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwpreinc8
fail
.Lwpreinc8:
mov.w #0xa5a5, @word_dest
shlr_w_predec_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
shlr.w #8, @-er0 ; shift right logical by eight, predec
;;; .word 0x0157
;;; .word 0x6d08
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwpredec8
fail
.Lwpredec8:
mov.w #0xa5a5, @word_dest
shlr_w_disp2_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
shlr.w #8, @(4:2, er0) ; shift right logical by eight, disp2
;;; .word 0x0156
;;; .word 0x6908
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwdisp28
fail
.Lwdisp28:
mov.w #0xa5a5, @word_dest
shlr_w_disp16_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
shlr.w #8, @(44:16, er0) ; shift right logical by eight, disp16
;;; .word 0x0154
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwdisp168
fail
.Lwdisp168:
mov.w #0xa5a5, @word_dest
shlr_w_disp32_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
shlr.w #8, @(666:32, er0) ; shift right logical by eight, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwdisp328
fail
.Lwdisp328:
mov.w #0xa5a5, @word_dest
shlr_w_abs16_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #8, @word_dest:16 ; shift right logical by eight, abs16
;;; .word 0x6b18
;;; .word word_dest
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwabs168
fail
.Lwabs168:
mov.w #0xa5a5, @word_dest
shlr_w_abs32_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.w #8, @word_dest:32 ; shift right logical by eight, abs32
;;; .word 0x6b38
;;; .long word_dest
;;; .word 0x1160
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0000 0000 1010 0101
cmp.w #0x00a5, @word_dest
beq .Lwabs328
fail
.Lwabs328:
mov.w #0xa5a5, @word_dest
shlr_l_imm5_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #31:5, er0 ; shift right logical by 5-bit immediate
;;; .word 0x0399
;;; .word 0x1130
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0000 0000 0000 0000 0000 0000 0000 0001
test_h_gr32 0x1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
shlr_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l er0 ; shift right logical by one, register
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0101 0010 1101 0010 1101 0010 1101 0010
test_h_gr32 0x52d2d2d2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shlr_l_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l @er0 ; shift right logical by one, indirect
;;; .word 0x0104
;;; .word 0x6908
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llind1
fail
.Llind1:
mov #0xa5a5a5a5, @long_dest
shlr_l_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l @er0+ ; shift right logical by one, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llpostinc1
fail
.Llpostinc1:
mov #0xa5a5a5a5, @long_dest
shlr_l_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l @er0- ; shift right logical by one, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llpostdec1
fail
.Llpostdec1:
mov #0xa5a5a5a5, @long_dest
shlr_l_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
shlr.l @+er0 ; shift right logical by one, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llpreinc1
fail
.Llpreinc1:
mov #0xa5a5a5a5, @long_dest
shlr_l_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
shlr.l @-er0 ; shift right logical by one, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llpredec1
fail
.Llpredec1:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
shlr.l @(8:2, er0) ; shift right logical by one, disp2
;;; .word 0x0106
;;; .word 0x6908
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Lldisp21
fail
.Lldisp21:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
shlr.l @(44:16, er0) ; shift right logical by one, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Lldisp161
fail
.Lldisp161:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
shlr.l @(666:32, er0) ; shift right logical by one, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Lldisp321
fail
.Lldisp321:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l @long_dest:16 ; shift right logical by one, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llabs161
fail
.Llabs161:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l @long_dest:32 ; shift right logical by one, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x1130
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llabs321
fail
.Llabs321:
mov #0xa5a5a5a5, @long_dest
.endif
shlr_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #2, er0 ; shift right logical by two, register
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0010 1001 0110 1001 0110 1001 0110 1001
test_h_gr32 0x29696969 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shlr_l_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #2, @er0 ; shift right logical by two, indirect
;;; .word 0x0104
;;; .word 0x6908
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Llind2
fail
.Llind2:
mov #0xa5a5a5a5, @long_dest
shlr_l_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #2, @er0+ ; shift right logical by two, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Llpostinc2
fail
.Llpostinc2:
mov #0xa5a5a5a5, @long_dest
shlr_l_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #2, @er0- ; shift right logical by two, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Llpostdec2
fail
.Llpostdec2:
mov #0xa5a5a5a5, @long_dest
shlr_l_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
shlr.l #2, @+er0 ; shift right logical by two, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Llpreinc2
fail
.Llpreinc2:
mov #0xa5a5a5a5, @long_dest
shlr_l_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
shlr.l #2, @-er0 ; shift right logical by two, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Llpredec2
fail
.Llpredec2:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
shlr.l #2, @(8:2, er0) ; shift right logical by two, disp2
;;; .word 0x0106
;;; .word 0x6908
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Lldisp22
fail
.Lldisp22:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
shlr.l #2, @(44:16, er0) ; shift right logical by two, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Lldisp162
fail
.Lldisp162:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
shlr.l #2, @(666:32, er0) ; shift right logical by two, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Lldisp322
fail
.Lldisp322:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #2, @long_dest:16 ; shift right logical by two, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Llabs162
fail
.Llabs162:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #2, @long_dest:32 ; shift right logical by two, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x1170
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0x29696969, @long_dest
beq .Llabs322
fail
.Llabs322:
mov #0xa5a5a5a5, @long_dest
shlr_l_reg32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #4, er0 ; shift right logical by four, register
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0000 1010 0101 1010 0101 1010 0101 1010
test_h_gr32 0x0a5a5a5a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_l_reg32_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #5, r1l
shlr.l r1l, er0 ; shift right logical by value of register
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0000 0101 0010 1101 0010 1101 0010 1101
test_h_gr32 0x052d2d2d er0
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_l_ind_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #4, @er0 ; shift right logical by four, indirect
;;; .word 0x0104
;;; .word 0x6908
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Llind4
fail
.Llind4:
mov #0xa5a5a5a5, @long_dest
shlr_l_postinc_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #4, @er0+ ; shift right logical by four, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Llpostinc4
fail
.Llpostinc4:
mov #0xa5a5a5a5, @long_dest
shlr_l_postdec_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #4, @er0- ; shift right logical by four, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Llpostdec4
fail
.Llpostdec4:
mov #0xa5a5a5a5, @long_dest
shlr_l_preinc_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
shlr.l #4, @+er0 ; shift right logical by four, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Llpreinc4
fail
.Llpreinc4:
mov #0xa5a5a5a5, @long_dest
shlr_l_predec_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
shlr.l #4, @-er0 ; shift right logical by four, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Llpredec4
fail
.Llpredec4:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp2_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
shlr.l #4, @(8:2, er0) ; shift right logical by four, disp2
;;; .word 0x0106
;;; .word 0x6908
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Lldisp24
fail
.Lldisp24:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
shlr.l #4, @(44:16, er0) ; shift right logical by four, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Lldisp164
fail
.Lldisp164:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
shlr.l #4, @(666:32, er0) ; shift right logical by four, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Lldisp324
fail
.Lldisp324:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #4, @long_dest:16 ; shift right logical by four, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Llabs164
fail
.Llabs164:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #4, @long_dest:32 ; shift right logical by four, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x1138
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 1010 0101 1010 0101 1010 0101 1010
cmp.l #0x0a5a5a5a, @long_dest
beq .Llabs324
fail
.Llabs324:
mov #0xa5a5a5a5, @long_dest
shlr_l_reg32_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #8, er0 ; shift right logical by eight, register
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0000 0000 1010 0101 1010 0101 1010 0101
test_h_gr32 0x00a5a5a5 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_l_ind_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #8, @er0 ; shift right logical by eight, indirect
;;; .word 0x0104
;;; .word 0x6908
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Llind8
fail
.Llind8:
mov #0xa5a5a5a5, @long_dest
shlr_l_postinc_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #8, @er0+ ; shift right logical by eight, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Llpostinc8
fail
.Llpostinc8:
mov #0xa5a5a5a5, @long_dest
shlr_l_postdec_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #8, @er0- ; shift right logical by eight, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Llpostdec8
fail
.Llpostdec8:
mov #0xa5a5a5a5, @long_dest
shlr_l_preinc_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
shlr.l #8, @+er0 ; shift right logical by eight, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Llpreinc8
fail
.Llpreinc8:
mov #0xa5a5a5a5, @long_dest
shlr_l_predec_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
shlr.l #8, @-er0 ; shift right logical by eight, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Llpredec8
fail
.Llpredec8:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp2_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
shlr.l #8, @(8:2, er0) ; shift right logical by eight, disp2
;;; .word 0x0106
;;; .word 0x6908
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Lldisp28
fail
.Lldisp28:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp16_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
shlr.l #8, @(44:16, er0) ; shift right logical by eight, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Lldisp168
fail
.Lldisp168:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp32_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
shlr.l #8, @(666:32, er0) ; shift right logical by eight, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Lldisp328
fail
.Lldisp328:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs16_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #8, @long_dest:16 ; shift right logical by eight, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Llabs168
fail
.Llabs168:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs32_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #8, @long_dest:32 ; shift right logical by eight, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x1178
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 1010 0101 1010 0101 1010 0101
cmp.l #0x00a5a5a5, @long_dest
beq .Llabs328
fail
.Llabs328:
mov #0xa5a5a5a5, @long_dest
shlr_l_reg32_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #16, er0 ; shift right logical by sixteen, register
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
test_h_gr32 0x0000a5a5 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shlr_l_ind_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #16, @er0 ; shift right logical by sixteen, indirect
;;; .word 0x0104
;;; .word 0x6908
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Llind16
fail
.Llind16:
mov #0xa5a5a5a5, @long_dest
shlr_l_postinc_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #16, @er0+ ; shift right logical by sixteen, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Llpostinc16
fail
.Llpostinc16:
mov #0xa5a5a5a5, @long_dest
shlr_l_postdec_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shlr.l #16, @er0- ; shift right logical by sixteen, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Llpostdec16
fail
.Llpostdec16:
mov #0xa5a5a5a5, @long_dest
shlr_l_preinc_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
shlr.l #16, @+er0 ; shift right logical by sixteen, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Llpreinc16
fail
.Llpreinc16:
mov #0xa5a5a5a5, @long_dest
shlr_l_predec_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
shlr.l #16, @-er0 ; shift right logical by sixteen, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Llpredec16
fail
.Llpredec16:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp2_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
shlr.l #16, @(8:2, er0) ; shift right logical by 16, dest2
;;; .word 0x0106
;;; .word 0x6908
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Lldisp216
fail
.Lldisp216:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp16_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
shlr.l #16, @(44:16, er0) ; shift right logical by 16, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Lldisp1616
fail
.Lldisp1616:
mov #0xa5a5a5a5, @long_dest
shlr_l_disp32_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
shlr.l #16, @(666:32, er0) ; shift right logical by 16, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Lldisp3216
fail
.Lldisp3216:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs16_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #16, @long_dest:16 ; shift right logical by 16, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Llabs1616
fail
.Llabs1616:
mov #0xa5a5a5a5, @long_dest
shlr_l_abs32_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shlr.l #16, @long_dest:32 ; shift right logical by 16, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x11f8
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0000 0000 0000 0000 1010 0101 1010 0101
cmp.l #0x0000a5a5, @long_dest
beq .Llabs3216
fail
.Llabs3216:
mov #0xa5a5a5a5, @long_dest
.endif
.endif
pass
exit 0
|
stsp/binutils-ia16
| 11,255
|
sim/testsuite/h8300/extw.s
|
# Hitachi H8 testcase 'exts.w, extu.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 2
pos: .word 0xff01
neg: .word 0x0080
.text
exts_w_reg16_p:
set_grs_a5a5
set_ccr_zero
;; exts.w rn16
mov.b #1, r0l
exts.w r0
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 0xa5a50001 er0 ; result of sign extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
exts_w_reg16_n:
set_grs_a5a5
set_ccr_zero
;; exts.w rn16
mov.b #0xff, r0l
exts.w r0
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5ffff er0 ; result of sign extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
extu_w_reg16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w rn16
mov.b #0xff, r0l
extu.w r0
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 0xa5a500ff er0 ; result of zero extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
exts_w_ind_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern
mov.l #pos, er1
exts.w @er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswindp
fail
.Lswindp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_ind_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern
mov.l #neg, er1
exts.w @er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswindn
fail
.Lswindn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_ind_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern
mov.l #neg, er1
extu.w @er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwindn
fail
.Luwindn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_postinc_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern+
mov.l #pos, er1
exts.w @er1+
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpostincp
fail
.Lswpostincp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_postinc_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern+
mov.l #neg, er1
exts.w @er1+
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg+2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpostincn
fail
.Lswpostincn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_postinc_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern+
mov.l #neg, er1
extu.w @er1+
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg+2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpostincn
fail
.Luwpostincn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_postdec_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern-
mov.l #pos, er1
exts.w @er1-
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpostdecp
fail
.Lswpostdecp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_postdec_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern-
mov.l #neg, er1
exts.w @er1-
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg-2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpostdecn
fail
.Lswpostdecn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_postdec_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern-
mov.l #neg, er1
extu.w @er1-
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpostdecn
fail
.Luwpostdecn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_preinc_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @+ern
mov.l #pos-2, er1
exts.w @+er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpreincp
fail
.Lswpreincp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_preinc_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @+ern
mov.l #neg-2, er1
exts.w @+er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpreincn
fail
.Lswpreincn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_preinc_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @+ern
mov.l #neg-2, er1
extu.w @+er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpreincn
fail
.Luwpreincn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_predec_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @-ern
mov.l #pos+2, er1
exts.w @-er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpredecp
fail
.Lswpredecp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_predec_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @-ern
mov.l #neg+2, er1
exts.w @-er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpredecn
fail
.Lswpredecn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_predec_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @-ern
mov.l #neg+2, er1
extu.w @-er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpredecn
fail
.Luwpredecn:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp2_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:2, ern)
mov.l #neg-2, er1
extu.w @(2:2, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp2n
fail
.Luwdisp2n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:16, ern)
mov.l #neg-44, er1
extu.w @(44:16, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-44 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp16n
fail
.Luwdisp16n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp32_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:32, ern)
mov.l #neg+444, er1
extu.w @(-444:32, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg+444 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp32n
fail
.Luwdisp32n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_abs16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @aa:16
extu.w @neg:16
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwabs16n
fail
.Luwabs16n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_abs32_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @aa:32
extu.w @neg:32
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwabs32n
fail
.Luwabs32n:
;; Note: leave the value as 0x0080, like it started out.
.endif
pass
exit 0
|
stsp/binutils-ia16
| 6,997
|
sim/testsuite/h8300/stc.s
|
# Hitachi H8 testcase 'stc'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_dest1:
.byte 0
.byte 0
byte_dest2:
.byte 0
.byte 0
byte_dest3:
.byte 0
.byte 0
byte_dest4:
.byte 0
.byte 0
byte_dest5:
.byte 0
.byte 0
byte_dest6:
.byte 0
.byte 0
byte_dest7:
.byte 0
.byte 0
byte_dest8:
.byte 0
.byte 0
byte_dest9:
.byte 0
.byte 0
byte_dest10:
.byte 0
.byte 0
byte_dest11:
.byte 0
.byte 0
byte_dest12:
.byte 0
.byte 0
start
stc_ccr_reg8:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr ; test value
stc ccr, r0h ; copy test value to r0h
test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l
.if (sim_cpu) ; h/s/sx
test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
stc_exr_reg8:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr ; set exr to 0x87
stc exr, r0l ; retrieve and check exr value
cmp.b #0x87, r0l
beq .L21
fail
.L21:
test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_abs16:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr
stc ccr, @byte_dest1:16 ; abs16 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_abs16:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr
stc exr, @byte_dest2:16 ; abs16 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_abs32:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr
stc ccr, @byte_dest3:32 ; abs32 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_abs32:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr
stc exr, @byte_dest4:32 ; abs32 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_disp16:
set_grs_a5a5
set_ccr_zero
mov #byte_dest5-1, er1
ldc #0xff, ccr
stc ccr, @(1:16,er1) ; disp16 dest (5)
test_h_gr32 byte_dest5-1, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_disp16:
set_grs_a5a5
set_ccr_zero
mov #byte_dest6+1, er1
ldc #0x87, exr
stc exr, @(-1:16,er1) ; disp16 dest (6)
test_h_gr32 byte_dest6+1, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_disp32:
set_grs_a5a5
set_ccr_zero
mov #byte_dest7-1, er1
ldc #0xff, ccr
stc ccr, @(1:32,er1) ; disp32 dest (7)
test_h_gr32 byte_dest7-1, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_disp32:
set_grs_a5a5
set_ccr_zero
mov #byte_dest8+1, er1
ldc #0x87, exr
stc exr, @(-1:32,er1) ; disp16 dest (8)
test_h_gr32 byte_dest8+1, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_predecr:
set_grs_a5a5
set_ccr_zero
mov #byte_dest9+2, er1
ldc #0xff, ccr
stc ccr, @-er1 ; predecr dest (9)
test_h_gr32 byte_dest9 er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_predecr:
set_grs_a5a5
set_ccr_zero
mov #byte_dest10+2, er1
ldc #0x87, exr
stc exr, @-er1 ; predecr dest (10)
test_h_gr32 byte_dest10, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_ind:
set_grs_a5a5
set_ccr_zero
mov #byte_dest11, er1
ldc #0xff, ccr
stc ccr, @er1 ; postinc dest (11)
test_h_gr32 byte_dest11, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_ind:
set_grs_a5a5
set_ccr_zero
mov #byte_dest12, er1
ldc #0x87, exr
stc exr, @er1, exr ; postinc dest (12)
test_h_gr32 byte_dest12, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
stc_sbr_reg:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
stc sbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_vbr_reg:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
stc vbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
check_results:
;; Now check results
mov @byte_dest1, r0h
cmp.b #0xff, r0h
beq .L1
fail
.L1: mov @byte_dest2, r0h
cmp.b #0x87, r0h
beq .L2
fail
.L2: mov @byte_dest3, r0h
cmp.b #0xff, r0h
beq .L3
fail
.L3: mov @byte_dest4, r0h
cmp.b #0x87, r0h
beq .L4
fail
.L4: mov @byte_dest5, r0h
cmp.b #0xff, r0h
beq .L5
fail
.L5: mov @byte_dest6, r0h
cmp.b #0x87, r0h
beq .L6
fail
.L6: mov @byte_dest7, r0h
cmp.b #0xff, r0h
beq .L7
fail
.L7: mov @byte_dest8, r0h
cmp.b #0x87, r0h
beq .L8
fail
.L8: mov @byte_dest9, r0h
cmp.b #0xff, r0h
beq .L9
fail
.L9: mov @byte_dest10, r0h
cmp.b #0x87, r0h
beq .L10
fail
.L10: mov @byte_dest11, r0h
cmp.b #0xff, r0h
beq .L11
fail
.L11: mov @byte_dest12, r0h
cmp.b #0x87, r0h
beq .L12
fail
.L12:
.endif
pass
exit 0
|
stsp/binutils-ia16
| 51,202
|
sim/testsuite/h8300/movb.s
|
# Hitachi H8 testcase 'mov.b'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 4
byte_dst_dec:
.byte 0
byte_src:
.byte 0x77
byte_dst:
.byte 0
.text
;;
;; Move byte from immediate source
;;
.if (sim_cpu == h8sx)
mov_b_imm8_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, rd
mov.b #0x77:8, r0l ; Immediate 3-bit operand
;;; .word 0xf877
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx)
mov_b_imm4_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:4, @aa:16
mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand
;;; .word 0x6adf
;;; .word @byte_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xf, @byte_dst
beq .Lnext21
fail
.Lnext21:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm4_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:4, @aa:32
mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand
;;; .word 0x6aff
;;; .long @byte_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xf, @byte_dst
beq .Lnext22
fail
.Lnext22:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @erd
mov.l #byte_dst, er1
mov.b #0xa5:8, @er1 ; Register indirect operand
;;; .word 0x017d
;;; .word 0x01a5
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext1
fail
.Lnext1:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_postinc: ; post-increment from imm8 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @erd+
mov.l #byte_dst, er1
mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands.
;;; .word 0x017d
;;; .word 0x81a5
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst+1, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext2
fail
.Lnext2:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @erd-
mov.l #byte_dst, er1
mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands.
;;; .word 0x017d
;;; .word 0xa1a5
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst-1, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext3
fail
.Lnext3:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @+erd
mov.l #byte_dst-1, er1
mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands
;;; .word 0x017d
;;; .word 0x91a5
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext4
fail
.Lnext4:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @-erd
mov.l #byte_dst+1, er1
mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands
;;; .word 0x017d
;;; .word 0xb1a5
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext5
fail
.Lnext5:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @(dd:2, erd)
mov.l #byte_dst-3, er1
mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
;;; .word 0x017d
;;; .word 0x31a5
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst-3, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext6
fail
.Lnext6:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @(dd:16, erd)
mov.l #byte_dst-4, er1
mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x017d
;;; .word 0x6f90
;;; .word 0x0004
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext7
fail
.Lnext7:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @(dd:32, erd)
mov.l #byte_dst-8, er1
mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x017d
;;; .word 0xc9a5
;;; .long 8
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst-8, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext8
fail
.Lnext8:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_indexb16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffffff01, er1
set_ccr_zero
;; mov.b #xx:8, @(dd:16, rd.b)
mov.b #0xa5:8, @(byte_dst-1:16, r1.b) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 0xffffff01, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_indexw16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffff0002, er1
set_ccr_zero
;; mov.b #xx:8, @(dd:16, rd.w)
mov.b #0xa5:8, @(byte_dst-2:16, r1.w) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 0xffff0002, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_indexl16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0x00000003, er1
set_ccr_zero
;; mov.b #xx:8, @(dd:16, erd.l)
mov.b #0xa5:8, @(byte_dst-3:16, er1.l) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 0x00000003, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_indexb32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffffff04, er1
set_ccr_zero
;; mov.b #xx:8, @(dd:32, rd.b)
mov.b #0xa5:8, @(byte_dst-4:32, r1.b) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 0xffffff04 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_indexw32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffff0005, er1
set_ccr_zero
;; mov.b #xx:8, @(dd:32, rd.w)
mov.b #0xa5:8, @(byte_dst-5:32, r1.w) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 0xffff0005 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_indexl32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0x00000006, er1
set_ccr_zero
;; mov.b #xx:8, @(dd:32, erd.l)
mov.b #0xa5:8, @(byte_dst-6:32, er1.l) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 0x00000006 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @aa:16
mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand
;;; .word 0x017d
;;; .word 0x40a5
;;; .word @byte_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext9
fail
.Lnext9:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_imm8_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b #xx:8, @aa:32
mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand
;;; .word 0x017d
;;; .word 0x48a5
;;; .long @byte_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b #0xa5, @byte_dst
beq .Lnext10
fail
.Lnext10:
mov.b #0, @byte_dst ; zero it again for the next use.
.endif
;;
;; Move byte from register source
;;
mov_b_reg8_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, erd
mov.b #0x12, r1l
mov.b r1l, r0l ; Register 8-bit operand
;;; .word 0x0c98
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr16 0xa512 r0
test_h_gr16 0xa512 r1 ; mov src unchanged
.if (sim_cpu)
test_h_gr32 0xa5a5a512 er0
test_h_gr32 0xa5a5a512 er1 ; mov src unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_reg8_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @erd
mov.l #byte_dst, er1
mov.b r0l, @er1 ; Register indirect operand
;;; .word 0x6898
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.b @byte_dst, r0l
cmp.b r2l, r0l
beq .Lnext44
fail
.Lnext44:
mov.b #0, r0l
mov.b r0l, @byte_dst ; zero it again for the next use.
.if (sim_cpu == h8sx)
mov_b_reg8_to_postinc: ; post-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @erd+
mov.l #byte_dst, er1
mov.b r0l, @er1+ ; Register post-incr operand
;;; .word 0x0173
;;; .word 0x6c98
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst+1, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b r2l, @byte_dst
beq .Lnext49
fail
.Lnext49:
;; special case same register
mov.l #byte_dst, er0
mov.b r0l, r1l
inc.b r1l
mov.b r0l, @er0+
mov.b @byte_dst, r0l
cmp.b r0l, r1l
beq .Lnext53
fail
.Lnext53:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_postdec: ; post-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @erd-
mov.l #byte_dst, er1
mov.b r0l, @er1- ; Register post-decr operand
;;; .word 0x0171
;;; .word 0x6c98
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst-1, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b r2l, @byte_dst
beq .Lnext50
fail
.Lnext50:
;; special case same register
mov.l #byte_dst, er0
mov.b r0l, r1l
dec.b r1l
mov.b r0l, @er0-
mov.b @byte_dst, r0l
cmp.b r0l, r1l
beq .Lnext54
fail
.Lnext54:
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @+erd
mov.l #byte_dst-1, er1
mov.b r0l, @+er1 ; Register pre-incr operand
;;; .word 0x0172
;;; .word 0x6c98
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b r2l, @byte_dst
beq .Lnext51
fail
.Lnext51:
;; special case same register
mov.l #byte_dst-1, er0
mov.b r0l, r1l
inc.b r1l
mov.b r0l, @+er0
mov.b @byte_dst, r0l
cmp.b r0l, r1l
beq .Lnext55
fail
.Lnext55:
mov.b #0, @byte_dst ; zero it again for the next use.
.endif
mov_b_reg8_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @-erd
mov.l #byte_dst+1, er1
mov.b r0l, @-er1 ; Register pre-decr operand
;;; .word 0x6c98
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.b @byte_dst, r0l
cmp.b r2l, r0l
beq .Lnext48
fail
.Lnext48:
;; Special case in same register
;; CCR confirmation omitted
mov.l #byte_dst+1, er1
mov.l er1, er0
dec.b r1l
mov.b r0l, @-er0
mov.b @byte_dst, r0l
cmp.b r1l, r0l
beq .Lnext47
fail
.Lnext47:
mov.b #0, r0l
mov.b r0l, @byte_dst ; zero it again for the next use.
.if (sim_cpu == h8sx)
mov_b_reg8_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @(dd:2, erd)
mov.l #byte_dst-3, er1
mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand
;;; .word 0x0173
;;; .word 0x6898
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 byte_dst-3, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b r2l, @byte_dst
beq .Lnext52
fail
.Lnext52:
mov.b #0, @byte_dst ; zero it again for the next use.
.endif
mov_b_reg8_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @(dd:16, erd)
mov.l #byte_dst-4, er1
mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x6e98
;;; .word 0x0004
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 byte_dst-4, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.b @byte_dst, r0l
cmp.b r2l, r0l
beq .Lnext45
fail
.Lnext45:
mov.b #0, r0l
mov.b r0l, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @(dd:32, erd)
mov.l #byte_dst-8, er1
mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x7810
;;; .word 0x6aa8
;;; .long 8
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 byte_dst-8, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.b @byte_dst, r0l
cmp.b r2l, r0l
beq .Lnext46
fail
.Lnext46:
mov.b #0, r0l
mov.b r0l, @byte_dst ; zero it again for the next use.
.if (sim_cpu == h8sx)
mov_b_reg8_to_indexb16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffffff01, er1
set_ccr_zero
;; mov.b ers, @(dd:16, rd.b)
mov.b r0l, @(byte_dst-1:16, r1.b) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xffffff01 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_dst, r0l
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_indexw16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffff0002, er1
set_ccr_zero
;; mov.b ers, @(dd:16, rd.w)
mov.b r0l, @(byte_dst-2:16, r1.w) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xffff0002 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_dst, r0l
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_indexl16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0x00000003, er1
set_ccr_zero
;; mov.b ers, @(dd:16, erd.l)
mov.b r0l, @(byte_dst-3:16, er1.l) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x00000003 er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_dst, r0l
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_indexb32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffffff04 er1
set_ccr_zero
;; mov.b ers, @(dd:32, rd.b)
mov.b r0l, @(byte_dst-4:32, r1.b) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xffffff04, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_dst, r0l
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_indexw32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffff0005 er1
set_ccr_zero
;; mov.b ers, @(dd:32, rd.w)
mov.b r0l, @(byte_dst-5:32, r1.w) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xffff0005, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_dst, r0l
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_indexl32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0x00000006 er1
set_ccr_zero
;; mov.b ers, @(dd:32, erd.l)
mov.b r0l, @(byte_dst-6:32, er1.l) ; byte indexed operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0x00000006, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_dst, r0l
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
.endif
.if (sim_cpu == h8sx)
mov_b_reg8_to_abs8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #byte_dst-20, er0
ldc er0, sbr
set_ccr_zero
;; mov.b ers, @aa:8
mov.b r1l, @20:8 ; 8-bit address-direct (sbr-relative) operand
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 byte_dst-20, er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_dst, r1l
bne fail1
mov.b #0, @byte_dst ; zero it again for the next use.
.endif
mov_b_reg8_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @aa:16
mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand
;;; .word 0x6a88
;;; .word @byte_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.b @byte_dst, r0l
cmp.b r0l, r1l
beq .Lnext41
fail
.Lnext41:
mov.b #0, r0l
mov.b r0l, @byte_dst ; zero it again for the next use.
mov_b_reg8_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b ers, @aa:32
mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand
;;; .word 0x6aa8
;;; .long @byte_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.b @byte_dst, r0l
cmp.b r0l, r1l
beq .Lnext42
fail
.Lnext42:
mov.b #0, r0l
mov.b r0l, @byte_dst ; zero it again for the next use.
;;
;; Move byte to register destination.
;;
mov_b_indirect_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @ers, rd
mov.l #byte_src, er1
mov.b @er1, r0l ; Register indirect operand
;;; .word 0x6818
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_h_gr32 byte_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_postinc_to_reg8: ; post-increment from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @ers+, rd
mov.l #byte_src, er1
mov.b @er1+, r0l ; Register post-incr operand
;;; .word 0x6c18
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_h_gr32 byte_src+1, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mov_b_postdec_to_reg8: ; post-decrement from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @ers-, rd
mov.l #byte_src, er1
mov.b @er1-, r0l ; Register post-decr operand
;;; .word 0x0172
;;; .word 0x6c18
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_h_gr32 byte_src-1, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_preinc_to_reg8: ; pre-increment from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @+ers, rd
mov.l #byte_src-1, er1
mov.b @+er1, r0l ; Register pre-incr operand
;;; .word 0x0171
;;; .word 0x6c18
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_h_gr32 byte_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_predec_to_reg8: ; pre-decrement from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @-ers, rd
mov.l #byte_src+1, er1
mov.b @-er1, r0l ; Register pre-decr operand
;;; .word 0x0173
;;; .word 0x6c18
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_h_gr32 byte_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_disp2_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @(dd:2, ers), rd
mov.l #byte_src-1, er1
mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand
;;; .word 0x0171
;;; .word 0x6818
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
test_h_gr32 byte_src-1, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
mov_b_disp16_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @(dd:16, ers), rd
mov.l #byte_src+0x1234, er1
mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand
;;; .word 0x6e18
;;; .word -0x1234
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
test_h_gr32 byte_src+0x1234, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_disp32_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @(dd:32, ers), rd
mov.l #byte_src+65536, er1
mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand
;;; .word 0x7810
;;; .word 0x6a28
;;; .long -65536
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
test_h_gr32 byte_src+65536, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mov_b_indexb16_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffffff01, er1
set_ccr_zero
;; mov.b @(dd:16, rs.b), rd
mov.b @(byte_src-1:16, r1.b), r0l ; indexed byte operand
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77
test_h_gr32 0xffffff01, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_indexw16_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffff0002, er1
set_ccr_zero
;; mov.b @(dd:16, rs.w), rd
mov.b @(byte_src-2:16, r1.w), r0l ; indexed byte operand
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77
test_h_gr32 0xffff0002, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_indexl16_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0x00000003, er1
set_ccr_zero
;; mov.b @(dd:16, ers.l), rd
mov.b @(byte_src-3:16, er1.l), r0l ; indexed byte operand
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77
test_h_gr32 0x00000003, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_indexb32_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffffff04, er1
set_ccr_zero
;; mov.b @(dd:32, rs.b), rd
mov.b @(byte_src-4:32, r1.b), r0l ; indexed byte operand
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
test_h_gr32 0xffffff04 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_indexw32_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffff0005, er1
set_ccr_zero
;; mov.b @(dd:32, rs.w), rd
mov.b @(byte_src-5:32, r1.w), r0l ; indexed byte operand
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
test_h_gr32 0xffff0005 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_indexl32_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0x00000006, er1
set_ccr_zero
;; mov.b @(dd:32, ers.l), rd
mov.b @(byte_src-6:32, er1.l), r0l ; indexed byte operand
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
test_h_gr32 0x00000006 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx)
mov_b_abs8_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #byte_src-255, er1
ldc er1, sbr
set_ccr_zero
;; mov.b @aa:8, rd
mov.b @0xff:8, r0l ; 8-bit (sbr relative) address-direct operand
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_h_gr32 byte_src-255, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
mov_b_abs16_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @aa:16, rd
mov.b @byte_src:16, r0l ; 16-bit address-direct operand
;;; .word 0x6a08
;;; .word @byte_src
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_b_abs32_to_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @aa:32, rd
mov.b @byte_src:32, r0l ; 32-bit address-direct operand
;;; .word 0x6a28
;;; .long @byte_src
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a577 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
;;
;; Move byte from memory to memory
;;
mov_b_indirect_to_indirect: ; reg indirect, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @ers, @erd
mov.l #byte_src, er1
mov.l #byte_dst, er0
mov.b @er1, @er0
;;; .word 0x0178
;;; .word 0x0100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 byte_dst er0
test_h_gr32 byte_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext56
fail
.Lnext56:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext57
fail
.Lnext57: ; OK, pass on.
mov_b_postinc_to_postinc: ; reg post-increment, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @ers+, @erd+
mov.l #byte_src, er1
mov.l #byte_dst, er0
mov.b @er1+, @er0+
;;; .word 0x0178
;;; .word 0x8180
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 byte_dst+1 er0
test_h_gr32 byte_src+1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext65
fail
.Lnext65:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext66
fail
.Lnext66: ; OK, pass on.
;; special case same register
mov.l #byte_src, er0
mov.b @er0+, @er0+ ; copying byte_src to byte_dst
test_h_gr32 byte_src+2 er0
cmp.b @byte_src, @byte_dst
beq .Lnext67
fail
.Lnext67:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext68
fail
.Lnext68:
mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @ers-, @erd-
mov.l #byte_src, er1
mov.l #byte_dst, er0
mov.b @er1-, @er0-
;;; .word 0x0178
;;; .word 0xa1a0
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 byte_dst-1 er0
test_h_gr32 byte_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext75
fail
.Lnext75:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext76
fail
.Lnext76: ; OK, pass on.
;; special case same register
mov.l #byte_src, er0
mov.b @er0-, @er0- ; copying byte_src to byte_dst_dec
test_h_gr32 byte_src-2 er0
cmp.b @byte_src, @byte_dst_dec
beq .Lnext77
fail
.Lnext77:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst_dec
cmp.b @byte_src, @byte_dst_dec
bne .Lnext78
fail
.Lnext78:
mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @+ers, @+erd
mov.l #byte_src-1, er1
mov.l #byte_dst-1, er0
mov.b @+er1, @+er0
;;; .word 0x0178
;;; .word 0x9190
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 byte_dst er0
test_h_gr32 byte_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext85
fail
.Lnext85:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext86
fail
.Lnext86: ; OK, pass on.
;; special case same register
mov.l #byte_src-1, er0
mov.b @+er0, @+er0 ; copying byte_src to byte_dst
test_h_gr32 byte_src+1 er0
cmp.b @byte_src, @byte_dst
beq .Lnext87
fail
.Lnext87:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext88
fail
.Lnext88:
mov_b_predec_to_predec: ; reg pre-decrement, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @-ers, @-erd
mov.l #byte_src+1, er1
mov.l #byte_dst+1, er0
mov.b @-er1, @-er0
;;; .word 0x0178
;;; .word 0xb1b0
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 byte_dst er0
test_h_gr32 byte_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext95
fail
.Lnext95:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext96
fail
.Lnext96: ; OK, pass on.
;; special case same register
mov.l #byte_src+1, er0
mov.b @-er0, @-er0 ; copying byte_src to byte_dst_dec
test_h_gr32 byte_src-1 er0
cmp.b @byte_src, @byte_dst_dec
beq .Lnext97
fail
.Lnext97:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst_dec
cmp.b @byte_src, @byte_dst_dec
bne .Lnext98
fail
.Lnext98:
mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @(dd:2, ers), @(dd:2, erd)
mov.l #byte_src-1, er1
mov.l #byte_dst-2, er0
mov.b @(1:2, er1), @(2:2, er0)
;;; .word 0x0178
;;; .word 0x1120
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 byte_dst-2 er0
test_h_gr32 byte_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext105
fail
.Lnext105:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext106
fail
.Lnext106: ; OK, pass on.
mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @(dd:16, ers), @(dd:16, erd)
mov.l #byte_src-1, er1
mov.l #byte_dst-2, er0
mov.b @(1:16, er1), @(2:16, er0)
;;; .word 0x0178
;;; .word 0xc1c0
;;; .word 0x0001
;;; .word 0x0002
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 byte_dst-2 er0
test_h_gr32 byte_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext115
fail
.Lnext115:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext116
fail
.Lnext116: ; OK, pass on.
mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @(dd:32, ers), @(dd:32, erd)
mov.l #byte_src-1, er1
mov.l #byte_dst-2, er0
mov.b @(1:32, er1), @(2:32, er0)
;;; .word 0x0178
;;; .word 0xc9c8
;;; .long 1
;;; .long 2
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 byte_dst-2 er0
test_h_gr32 byte_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext125
fail
.Lnext125:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext126
fail
.Lnext126: ; OK, pass on.
mov_b_indexb16_to_indexb16: ; reg 16-bit indexed, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffffff01, er1
mov.l #0xffffff02, er0
;; mov.b @(dd:16, rs.b), @(dd:16, rd.b)
set_ccr_zero
mov.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r0.b)
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 0xffffff02 er0
test_h_gr32 0xffffff01 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
bne fail1
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
beq fail1
mov_b_indexw16_to_indewb16: ; reg 16-bit indexed, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffff0003, er1
mov.l #0xffff0004, er0
;; mov.b @(dd:16, rs.w), @(dd:16, rd.w)
set_ccr_zero
mov.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r0.w)
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 0xffff0004 er0
test_h_gr32 0xffff0003 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
bne fail1
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
beq fail1
mov_b_indexl16_to_indexl16: ; reg 16-bit indexed, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0x00000005, er1
mov.l #0x00000006, er0
;; mov.b @(dd:16, ers.l), @(dd:16, erd.l)
set_ccr_zero
mov.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er0.l)
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 0x00000006 er0
test_h_gr32 0x00000005 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
bne fail1
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
beq fail1
mov_b_indexb32_to_indexb32: ; reg 32-bit indexed, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffffff01, er1
mov.l #0xffffff02, er0
set_ccr_zero
;; mov.b @(dd:32, rs.b), @(dd:32, rd.b)
mov.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r0.b)
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 0xffffff02 er0
test_h_gr32 0xffffff01 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
bne fail1
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
beq fail1
mov_b_indexw32_to_indexw32: ; reg 32-bit indexed, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0xffff0003, er1
mov.l #0xffff0004, er0
set_ccr_zero
;; mov.b @(dd:32, rs.w), @(dd:32, rd.w)
mov.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r0.w)
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 0xffff0004 er0
test_h_gr32 0xffff0003 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
bne fail1
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
beq fail1
mov_b_indexl32_to_indexl32: ; reg 32-bit indexed, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov.l #0x00000005, er1
mov.l #0x00000006, er0
set_ccr_zero
;; mov.b @(dd:32, rs.w), @(dd:32, rd.w)
mov.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er0.l)
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 0x00000006 er0
test_h_gr32 0x00000005 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
bne fail1
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
beq fail1
mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @aa:16, @aa:16
mov.b @byte_src:16, @byte_dst:16
;;; .word 0x0178
;;; .word 0x4040
;;; .word @byte_src
;;; .word @byte_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure *NO* general registers are changed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext135
fail
.Lnext135:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext136
fail
.Lnext136: ; OK, pass on.
mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.b @aa:32, @aa:32
mov.b @byte_src:32, @byte_dst:32
;;; .word 0x0178
;;; .word 0x4848
;;; .long @byte_src
;;; .long @byte_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure *NO* general registers are changed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.b @byte_src, @byte_dst
beq .Lnext145
fail
.Lnext145:
;; Now clear the destination location, and verify that.
mov.b #0, @byte_dst
cmp.b @byte_src, @byte_dst
bne .Lnext146
fail
.Lnext146: ; OK, pass on.
.endif
pass
exit 0
fail1:
fail
|
stsp/binutils-ia16
| 4,679
|
sim/testsuite/h8300/bfld.s
|
# Hitachi H8 testcase 'bfld', 'bfst'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src: .byte 0xa5
byte_dst: .byte 0
start
.if (sim_cpu == h8sx)
bfld_imm8_ind:
set_grs_a5a5
mov #byte_src, er2
;; bfld #xx:8, @ers, rd8
set_ccr_zero
bfld #1, @er2, r1l
test_cc_clear
test_h_gr8 1 r1l
set_ccr_zero
bfld #2, @er2, r1l
test_cc_clear
test_h_gr8 0 r1l
set_ccr_zero
bfld #7, @er2, r1l
test_cc_clear
test_h_gr8 5 r1l
set_ccr_zero
bfld #0x10, @er2, r1l
test_cc_clear
test_h_gr8 0 r1l
set_ccr_zero
bfld #0x20, @er2, r1l
test_cc_clear
test_h_gr8 1 r1l
set_ccr_zero
bfld #0xf0, @er2, r1l
test_cc_clear
test_h_gr8 0xa r1l
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 0xa5a5a50a er1
test_h_gr32 byte_src er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
bfld_imm8_abs16:
set_grs_a5a5
;; bfld #xx:8, @aa:16, rd8
set_ccr_zero
bfld #0x80, @byte_src:16, r1l
test_cc_clear
test_h_gr8 1 r1l
set_ccr_zero
bfld #0x40, @byte_src:16, r1l
test_cc_clear
test_h_gr8 0 r1l
set_ccr_zero
bfld #0xe0, @byte_src:16, r1l
test_cc_clear
test_h_gr8 0x5 r1l
set_ccr_zero
bfld #0x3c, @byte_src:16, r1l
test_cc_clear
test_h_gr8 9 r1l
set_ccr_zero
bfld #0xfe, @byte_src:16, r1l
test_cc_clear
test_h_gr8 0x52 r1l
set_ccr_zero
bfld #0, @byte_src:16, r1l
test_cc_clear
test_h_gr8 0 r1l
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 0xa5a5a500 er1
test_h_gr32 0xa5a5a5a5 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
bfst_imm8_ind:
set_grs_a5a5
mov #byte_dst, er2
;; bfst rd8, #xx:8, @ers
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #1, @er2
;;; .word 0x7d20
;;; .word 0xf901
test_cc_clear
cmp.b #1, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #2, @er2
;;; .word 0x7d20
;;; .word 0xf902
test_cc_clear
cmp.b #2, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #7, @er2
;;; .word 0x7d20
;;; .word 0xf907
test_cc_clear
cmp.b #5, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x10, @er2
;;; .word 0x7d20
;;; .word 0xf910
test_cc_clear
cmp.b #0x10, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x20, @er2
;;; .word 0x7d20
;;; .word 0xf920
test_cc_clear
cmp.b #0x20, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0xf0, @er2
;;; .word 0x7d20
;;; .word 0xf9f0
test_cc_clear
cmp.b #0x50, @byte_dst
bne fail1:16
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 0xa5a5a5a5 er1
test_h_gr32 byte_dst er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
bfst_imm8_abs32:
set_grs_a5a5
;; bfst #xx:8, @aa:32, rd8
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x80, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf980
test_cc_clear
cmp.b #0x80, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x40, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf940
test_cc_clear
cmp.b #0x40, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0xe0, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf9e0
test_cc_clear
cmp.b #0xa0, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x3c, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf93c
test_cc_clear
cmp.b #0x14, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0xfe, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf9fe
test_cc_clear
cmp.b #0x4a, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf900
test_cc_clear
cmp.b #0x0, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x38, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf938
test_cc_clear
cmp.b #0x28, @byte_dst
bne fail1:16
;;
;; Now let's do one in which the bits in the destination
;; are appropriately combined with the bits in the source.
;;
mov.b #0xc3, @byte_dst
set_ccr_zero
bfst r1l, #0x3c, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf93c
test_cc_clear
cmp.b #0xd7, @byte_dst
bne fail1:16
test_grs_a5a5
.endif
pass
exit 0
fail1: fail
|
stsp/binutils-ia16
| 5,946
|
sim/testsuite/h8300/div.s
|
# Hitachi H8 testcase 'divs', 'divu', 'divxs', 'divxu'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx)
divs_w_reg_reg:
set_grs_a5a5
;; divs.w rs, rd
mov.w #32, r1
mov.w #-2, r2
set_ccr_zero
divs.w r2, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr16 0xfff0 r1
test_h_gr32 0xa5a5fffe er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
divs_w_imm4_reg:
set_grs_a5a5
;; divs.w xx:4, rd
mov.w #-32, r1
set_ccr_zero
divs.w #2:4, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr16 -16 r1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
divs_l_reg_reg:
set_grs_a5a5
;; divs.l ers, erd
mov.l #320000, er1
mov.l #-2, er2
set_ccr_zero
divs.l er2, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 -160000 er1
test_h_gr32 -2 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
divs_l_imm4_reg:
set_grs_a5a5
;; divs.l xx:4, rd
mov.l #-320000, er1
set_ccr_zero
divs.l #2:4, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 -160000 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
divu_w_reg_reg:
set_grs_a5a5
;; divu.w rs, rd
mov.w #32, r1
mov.w #2, r2
set_ccr_zero
divu.w r2, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr16 16 r1
test_h_gr32 0xa5a50002 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
divu_w_imm4_reg:
set_grs_a5a5
;; divu.w xx:4, rd
mov.w #32, r1
set_ccr_zero
divu.w #2:4, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr16 16 r1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
divu_l_reg_reg:
set_grs_a5a5
;; divu.l ers, erd
mov.l #320000, er1
mov.l #2, er2
set_ccr_zero
divu.l er2, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 160000 er1
test_h_gr32 2 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
divu_l_imm4_reg:
set_grs_a5a5
;; divu.l xx:4, rd
mov.l #320000, er1
set_ccr_zero
divu.l #2:4, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 160000 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; not equal to zero ie. not h8
divxs_b_reg_reg:
set_grs_a5a5
;; divxs.b rs, rd
mov.w #32, r1
mov.b #-2, r2l
set_ccr_zero
divxs.b r2l, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr16 0x00f0 r1
test_h_gr32 0xa5a5a5fe er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
divxs_b_imm4_reg:
set_grs_a5a5
;; divxs.b xx:4, rd
mov.w #-32, r1
set_ccr_zero
divxs.b #2:4, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr16 0x00f0 r1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
divxs_w_reg_reg:
set_grs_a5a5
;; divxs.w ers, erd
mov.l #0x1000, er1
mov.w #-0x1000, r2
set_ccr_zero
divxs.w r2, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 0x0000ffff er1
test_h_gr32 0xa5a5f000 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
divxs_w_imm4_reg:
set_grs_a5a5
;; divxs.w xx:4, rd
mov.l #-4, er1
set_ccr_zero
divxs.w #2:4, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 0x0000fffe er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
.endif ; not h8
divxu_b_reg_reg:
set_grs_a5a5
;; divxu.b rs, rd
mov.w #32, r1
mov.b #2, r2l
set_ccr_zero
divxu.b r2l, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr16 0x0010 r1
test_h_gr16 0xa502 r2
.if (sim_cpu)
test_h_gr32 0xa5a5a502 er2
.endif
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; not h8
.if (sim_cpu == h8sx)
divxu_b_imm4_reg:
set_grs_a5a5
;; divxu.b xx:4, rd
mov.w #32, r1
set_ccr_zero
divxu.b #2:4, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr16 0x0010 r1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
divxu_w_reg_reg:
set_grs_a5a5
;; divxu.w ers, erd
mov.l #0x1000, er1
mov.w #0x1000, r2
set_ccr_zero
divxu.w r2, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 0x00000001 er1
test_h_gr32 0xa5a51000 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
divxu_w_imm4_reg:
set_grs_a5a5
;; divxu.w xx:4, rd
mov.l #0xffff, er1
set_ccr_zero
divxu.w #2:4, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 0x00017fff er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
.endif ; not h8
pass
exit 0
|
stsp/binutils-ia16
| 1,820
|
sim/testsuite/h8300/movsd.s
|
# Hitachi H8 testcase 'movsd'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
src: .byte 'h', 'e', 'l', 'l', 'o', 0
dst1: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
dst2: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
start
.if (sim_cpu == h8sx)
movsd_n:#
# In this test, the transfer will stop after n bytes.
#
set_grs_a5a5
mov #src, er5
mov #dst1, er6
mov #4, r4
set_ccr_zero
;; movsd.b disp:16
movsd.b fail1:16
;;; .word 0x7b84
;;; .word 0x02
bra pass1
fail1: fail
pass1: test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50000 er4
test_h_gr32 src+4 er5
test_h_gr32 dst1+4 er6
test_gr_a5a5 7
#
# Now make sure exactly 4 bytes were transferred.
cmp.b @src, @dst1
bne fail1:16
cmp.b @src+1, @dst1+1
bne fail1:16
cmp.b @src+2, @dst1+2
bne fail1:16
cmp.b @src+3, @dst1+3
bne fail1:16
cmp.b @src+4, @dst1+4
beq fail1:16
movsd_s:#
# In this test, the entire null-terminated string is transferred.
#
set_grs_a5a5
mov #src, er5
mov #dst2, er6
mov #8, r4
set_ccr_zero
;; movsd.b disp:16
movsd.b pass2:16
;;; .word 0x7b84
;;; .word 0x10
fail2: fail
pass2: test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50002 er4
test_h_gr32 src+6 er5
test_h_gr32 dst2+6 er6
test_gr_a5a5 7
#
# Now make sure 5 bytes were transferred, and the 6th is zero.
cmp.b @src, @dst2
bne fail2:16
cmp.b @src+1, @dst2+1
bne fail2:16
cmp.b @src+2, @dst2+2
bne fail2:16
cmp.b @src+3, @dst2+3
bne fail2:16
cmp.b @src+4, @dst2+4
bne fail2:16
cmp.b #0, @dst2+5
bne fail2:16
.endif
pass
exit 0
|
stsp/binutils-ia16
| 22,331
|
sim/testsuite/h8300/addx.s
|
# Hitachi H8 testcase 'addx'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx
# addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx
# addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx
# addx.b rs8, rd8 ; 0 e rs8 rd8
# addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ????
# addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ????
# addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8
# addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8
# addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ????
# addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ????
#
# word ops
# long ops
.data
byte_src: .byte 0x5
byte_dest: .byte 0
.align 2
word_src: .word 0x505
word_dest: .word 0
.align 4
long_src: .long 0x50505
long_dest: .long 0
start
addx_b_imm8_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,Rd ; Addx with carry initially zero.
addx.b #5, r0l ; Immediate 8-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa5aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_imm8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,Rd ; Addx with carry initially one.
set_carry_flag
addx.b #5, r0l ; Immediate 8-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
addx_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,@eRd ; Addx to register indirect
mov #byte_dest, er0
addx.b #5, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #5, @byte_dest
beq .Lb1
fail
.Lb1:
addx_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,@eRd- ; Addx to register post-decrement
mov #byte_dest, er0
addx.b #5, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #10, @byte_dest
beq .Lb2
fail
.Lb2:
.endif
addx_b_reg8_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b Rs,Rd ; addx with carry initially zero
mov.b #5, r0h
addx.b r0h, r0l ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0x05aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b Rs,Rd ; addx with carry initially one
mov.b #5, r0h
set_carry_flag
addx.b r0h, r0l ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
addx_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b rs8,@eRd ; Addx to register indirect
mov #byte_dest, er0
mov.b #5, r1l
addx.b r1l, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #15, @byte_dest
beq .Lb3
fail
.Lb3:
addx_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b rs8,@eRd- ; Addx to register post-decrement
mov #byte_dest, er0
mov.b #5, r1l
addx.b r1l, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #20, @byte_dest
beq .Lb4
fail
.Lb4:
addx_b_rsind_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs,rd8 ; Addx from reg indirect to reg
mov #byte_src, er0
addx.b @er0, r1l
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src er0 ; er0 still contains address
test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_rspostdec_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs-,rd8 ; Addx to register post-decrement
mov #byte_src, er0
addx.b @er0-, r1l
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src-1 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_rsind_rsind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs,rd8 ; Addx from reg indirect to reg
mov #byte_src, er0
mov #byte_dest, er1
addx.b @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_src er0 ; er0 still contains src address
test_h_gr32 byte_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #25, @byte_dest
beq .Lb5
fail
.Lb5:
addx_b_rspostdec_rspostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs-,rd8 ; Addx to register post-decrement
mov #byte_src, er0
mov #byte_dest, er1
addx.b @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one
test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #30, @byte_dest
beq .Lb6
fail
.Lb6:
addx_w_imm16_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,Rd ; Addx with carry initially zero.
addx.w #0x505, r0 ; Immediate 16-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505
test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_imm16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,Rd ; Addx with carry initially one.
set_carry_flag
addx.w #0x505, r0 ; Immediate 16-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1
test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_imm16_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,@eRd ; Addx to register indirect
mov #word_dest, er0
addx.w #0x505, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x505, @word_dest
beq .Lw1
fail
.Lw1:
addx_w_imm16_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,@eRd- ; Addx to register post-decrement
mov #word_dest, er0
addx.w #0x505, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest-2 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0xa0a, @word_dest
beq .Lw2
fail
.Lw2:
addx_w_reg16_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w Rs,Rd ; addx with carry initially zero
mov.w #0x505, e0
addx.w e0, r0 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x0505aaaa er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w Rs,Rd ; addx with carry initially one
mov.w #0x505, e0
set_carry_flag
addx.w e0, r0 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x0505aaab er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_reg16_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w rs8,@eRd ; Addx to register indirect
mov #word_dest, er0
mov.w #0x505, r1
addx.w r1, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest er0 ; er0 still contains address
test_h_gr32 0xa5a50505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0xf0f, @word_dest
beq .Lw3
fail
.Lw3:
addx_w_reg16_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w rs8,@eRd- ; Addx to register post-decrement
mov #word_dest, er0
mov.w #0x505, r1
addx.w r1, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest-2 er0 ; er0 contains address minus one
test_h_gr32 0xa5a50505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1414, @word_dest
beq .Lw4
fail
.Lw4:
addx_w_rsind_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs,rd8 ; Addx from reg indirect to reg
mov #word_src, er0
addx.w @er0, r1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src er0 ; er0 still contains address
test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_rspostdec_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs-,rd8 ; Addx to register post-decrement
mov #word_src, er0
addx.w @er0-, r1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src-2 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs,rd8 ; Addx from reg indirect to reg
mov #word_src, er0
mov #word_dest, er1
addx.w @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_src er0 ; er0 still contains src address
test_h_gr32 word_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1919, @word_dest
beq .Lw5
fail
.Lw5:
addx_w_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs-,rd8 ; Addx to register post-decrement
mov #word_src, er0
mov #word_dest, er1
addx.w @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_src-2 er0 ; er0 contains src address minus one
test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1e1e, @word_dest
beq .Lw6
fail
.Lw6:
addx_l_imm32_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,Rd ; Addx with carry initially zero.
addx.l #0x50505, er0 ; Immediate 32-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0xa5aaaaaa er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_imm32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,Rd ; Addx with carry initially one.
set_carry_flag
addx.l #0x50505, er0 ; Immediate 32-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0xa5aaaaab er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_imm32_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,@eRd ; Addx to register indirect
mov #long_dest, er0
addx.l #0x50505, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x50505, @long_dest
beq .Ll1
fail
.Ll1:
addx_l_imm32_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,@eRd- ; Addx to register post-decrement
mov #long_dest, er0
addx.l #0x50505, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest-4 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0xa0a0a, @long_dest
beq .Ll2
fail
.Ll2:
addx_l_reg32_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l Rs,Rd ; addx with carry initially zero
mov.l #0x50505, er0
addx.l er0, er1 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x50505 er0 ; add load
test_h_gr32 0xa5aaaaaa er1 ; add result:
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l Rs,Rd ; addx with carry initially one
mov.l #0x50505, er0
set_carry_flag
addx.l er0, er1 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x50505 er0 ; add result:
test_h_gr32 0xa5aaaaab er1 ; add result:
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_reg32_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l rs8,@eRd ; Addx to register indirect
mov #long_dest, er0
mov.l #0x50505, er1
addx.l er1, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest er0 ; er0 still contains address
test_h_gr32 0x50505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0xf0f0f, @long_dest
beq .Ll3
fail
.Ll3:
addx_l_reg32_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l rs8,@eRd- ; Addx to register post-decrement
mov #long_dest, er0
mov.l #0x50505, er1
addx.l er1, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest-4 er0 ; er0 contains address minus one
test_h_gr32 0x50505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x141414, @long_dest
beq .Ll4
fail
.Ll4:
addx_l_rsind_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs,rd8 ; Addx from reg indirect to reg
mov #long_src, er0
addx.l @er0, er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src er0 ; er0 still contains address
test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_rspostdec_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs-,rd8 ; Addx to register post-decrement
mov #long_src, er0
addx.l @er0-, er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src-4 er0 ; er0 contains address minus one
test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs,rd8 ; Addx from reg indirect to reg
mov #long_src, er0
mov #long_dest, er1
addx.l @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_src er0 ; er0 still contains src address
test_h_gr32 long_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x191919, @long_dest
beq .Ll5
fail
.Ll5:
addx_l_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs-,rd8 ; Addx to register post-decrement
mov #long_src, er0
mov #long_dest, er1
addx.l @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_src-4 er0 ; er0 contains src address minus one
test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x1e1e1e, @long_dest
beq .Ll6
fail
.Ll6:
.endif
pass
exit 0
|
stsp/binutils-ia16
| 11,981
|
sim/testsuite/h8300/orb.s
|
# Hitachi H8 testcase 'or.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# or.b #xx:8, rd ; c rd xxxxxxxx
# or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx
# or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx
# or.b rs, rd ; 1 4 rs rd
# or.b reg8, @erd ; 7 d rd ???? 1 4 rs ????
# or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs
# or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs
# or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs
# or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs
#
# orc #xx:8, ccr
# orc #xx:8, exr
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
or_b_imm8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.b #xx:8,Rd
or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5af r0 ; or result: a5 | aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
or_b_imm8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd
mov #byte_dest, er0
or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L1
fail
.L1:
or_b_imm8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd+
mov #byte_dest, er0
or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xc055
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L2
fail
.L2:
or_b_imm8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd-
mov #byte_dest, er0
or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L3
fail
.L3:
or_b_imm8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@+eRd
mov #pre_byte, er0
or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xc055
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L4
fail
.L4:
or_b_imm8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@-eRd
mov #post_byte, er0
or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L5
fail
.L5:
.endif
or_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.b Rs,Rd
mov.b #0xaa, r0h
or.b r0h, r0l ; Reg8 src, reg8 dest
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xaaaf r0 ; or result: a5 | aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
or_b_reg8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd ; or reg8 to register indirect
mov #byte_dest, er0
mov #0xaa, r1l
or.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1490
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L6
fail
.L6:
or_b_reg8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment
mov #byte_dest, er0
mov #0x55, r1l
or.b r1l, @er0+ ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x8049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L7
fail
.L7:
;; special case same register
mov.l #byte_dest, er0
mov.b r0l, r1l
mov.b @er0, r1h
or.b r0l, @er0+
inc.b r1l
or.b r1h, r1l
mov.b @byte_dest, r0l
cmp.b r1l, r0l
beq .L27
fail
.L27:
or_b_reg8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement
mov #byte_dest, er0
mov #0xaa, r1l
or.b r1l, @er0- ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xa049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L8
fail
.L8:
;; special case same register
mov.l #byte_dest, er0
mov.b r0l, r1l
mov.b @er0, r1h
or.b r0l, @er0-
dec.b r1l
or.b r1h, r1l
mov.b @byte_dest, r0l
cmp.b r1l, r0l
beq .L28
fail
.L28:
or_b_reg8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment
mov #pre_byte, er0
mov #0x55, r1l
or.b r1l, @+er0 ; reg8 src, reg pre-incr dest
;;; .word 0x0179
;;; .word 0x9049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L9
fail
.L9:
;; special case same register
mov.l #pre_byte, er0
mov.b r0l, r1l
mov.b @byte_dest, r1h
or.b r0l, @+er0
inc.b r1l
or.b r1h, r1l
mov.b @byte_dest, r0l
cmp.b r1l, r0l
beq .L29
fail
.L29:
or_b_reg8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement
mov #post_byte, er0
mov #0xaa, r1l
or.b r1l, @-er0 ; reg8 src, reg pre-decr dest
;;; .word 0x0179
;;; .word 0xb049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L10
fail
.L10:
;; special case same register
mov.l #post_byte, er0
mov.b r0l, r1l
mov.b @byte_dest, r1h
or.b r0l, @-er0
dec.b r1l
or.b r1h, r1l
mov.b @byte_dest, r0l
cmp.b r1l, r0l
beq .L30
fail
.L30:
.endif
orc_imm8_ccr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; orc #xx:8,ccr
test_neg_clear
orc #0x8, ccr ; Immediate 8-bit operand (neg flag)
test_neg_set
test_zero_clear
orc #0x4, ccr ; Immediate 8-bit operand (zero flag)
test_zero_set
test_ovf_clear
orc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
test_ovf_set
test_carry_clear
orc #0x1, ccr ; Immediate 8-bit operand (carry flag)
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
orc_imm8_exr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
ldc #0, exr
stc exr, r0l
test_h_gr8 0, r0l
;; orc #xx:8,exr
orc #0x1, exr
stc exr,r0l
test_h_gr8 1, r0l
orc #0x2, exr
stc exr,r0l
test_h_gr8 3, r0l
orc #0x4, exr
stc exr,r0l
test_h_gr8 7, r0l
orc #0x80, exr
stc exr,r0l
test_h_gr8 0x87, r0l
test_h_gr32 0xa5a5a587 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; not h8300 or h8300h
pass
exit 0
|
stsp/binutils-ia16
| 42,164
|
sim/testsuite/h8300/shar.s
|
# Hitachi H8 testcase 'shar'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
shar_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.b r0l ; shift right arithmetic by one
;;; .word 0x1188
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010
.if (sim_cpu)
test_h_gr32 0xa5a5a5d2 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shar_b_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shar.b @er0 ; shift right arithmetic by one, indirect
;;; .word 0x7d00
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbind1
fail
.Lbind1:
mov.b #0xa5, @byte_dest
shar_b_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shar.b @er0+ ; shift right arithmetic by one, postinc
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbpostinc1
fail
.Lbpostinc1:
mov.b #0xa5, @byte_dest
shar_b_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shar.b @er0- ; shift right arithmetic by one, postdec
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbpostdec1
fail
.Lbpostdec1:
mov.b #0xa5, @byte_dest
shar_b_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
shar.b @+er0 ; shift right arithmetic by one, preinc
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbpreinc1
fail
.Lbpreinc1:
mov.b #0xa5, @byte_dest
shar_b_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
shar.b @-er0 ; shift right arithmetic by one, predec
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbpredec1
fail
.Lbpredec1:
mov.b #0xa5, @byte_dest
shar_b_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
shar.b @(2:2, er0) ; shift right arithmetic by one, disp2
;;; .word 0x0176
;;; .word 0x6808
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbdisp21
fail
.Lbdisp21:
mov.b #0xa5, @byte_dest
shar_b_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
shar.b @(44:16, er0) ; shift right arithmetic by one, disp16
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 44
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbdisp161
fail
.Lbdisp161:
mov.b #0xa5, @byte_dest
shar_b_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
shar.b @(666:32, er0) ; shift right arithmetic by one, disp32
;;; .word 0x7884
;;; .word 0x6a28
;;; .long 666
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbdisp321
fail
.Lbdisp321:
mov.b #0xa5, @byte_dest
shar_b_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.b @byte_dest:16 ; shift right arithmetic by one, abs16
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbabs161
fail
.Lbabs161:
mov.b #0xa5, @byte_dest
shar_b_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.b @byte_dest:32 ; shift right arithmetic by one, abs32
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x1180
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1101 0010
cmp.b #0xd2, @byte_dest
beq .Lbabs321
fail
.Lbabs321:
mov.b #0xa5, @byte_dest
.endif
shar_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.b #2, r0l ; shift right arithmetic by two
;;; .word 0x11c8
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa5e9 r0 ; 1010 0101 -> 1110 1001
.if (sim_cpu)
test_h_gr32 0xa5a5a5e9 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shar_b_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shar.b #2, @er0 ; shift right arithmetic by two, indirect
;;; .word 0x7d00
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbind2
fail
.Lbind2:
mov.b #0xa5, @byte_dest
shar_b_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shar.b #2, @er0+ ; shift right arithmetic by two, postinc
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbpostinc2
fail
.Lbpostinc2:
mov.b #0xa5, @byte_dest
shar_b_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
shar.b #2, @er0- ; shift right arithmetic by two, postdec
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbpostdec2
fail
.Lbpostdec2:
mov.b #0xa5, @byte_dest
shar_b_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
shar.b #2, @+er0 ; shift right arithmetic by two, preinc
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbpreinc2
fail
.Lbpreinc2:
mov.b #0xa5, @byte_dest
shar_b_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
shar.b #2, @-er0 ; shift right arithmetic by two, predec
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbpredec2
fail
.Lbpredec2:
mov.b #0xa5, @byte_dest
shar_b_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
shar.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
;;; .word 0x0176
;;; .word 0x6808
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbdisp22
fail
.Lbdisp22:
mov.b #0xa5, @byte_dest
shar_b_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
shar.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 44
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbdisp162
fail
.Lbdisp162:
mov.b #0xa5, @byte_dest
shar_b_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
shar.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
;;; .word 0x7884
;;; .word 0x6a28
;;; .long 666
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbdisp322
fail
.Lbdisp322:
mov.b #0xa5, @byte_dest
shar_b_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbabs162
fail
.Lbabs162:
mov.b #0xa5, @byte_dest
shar_b_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x11c0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1110 1001
cmp.b #0xe9, @byte_dest
beq .Lbabs322
fail
.Lbabs322:
mov.b #0xa5, @byte_dest
.endif
.if (sim_cpu) ; Not available in h8300 mode
shar_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.w r0 ; shift right arithmetic by one
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
test_h_gr32 0xa5a5d2d2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shar_w_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shar.w @er0 ; shift right arithmetic by one, indirect
;;; .word 0x7d80
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwind1
fail
.Lwind1:
mov.w #0xa5a5, @word_dest
shar_w_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shar.w @er0+ ; shift right arithmetic by one, postinc
;;; .word 0x0154
;;; .word 0x6d08
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwpostinc1
fail
.Lwpostinc1:
mov.w #0xa5a5, @word_dest
shar_w_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shar.w @er0- ; shift right arithmetic by one, postdec
;;; .word 0x0156
;;; .word 0x6d08
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwpostdec1
fail
.Lwpostdec1:
mov.w #0xa5a5, @word_dest
shar_w_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
shar.w @+er0 ; shift right arithmetic by one, preinc
;;; .word 0x0155
;;; .word 0x6d08
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwpreinc1
fail
.Lwpreinc1:
mov.w #0xa5a5, @word_dest
shar_w_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
shar.w @-er0 ; shift right arithmetic by one, predec
;;; .word 0x0157
;;; .word 0x6d08
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwpredec1
fail
.Lwpredec1:
mov.w #0xa5a5, @word_dest
shar_w_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
shar.w @(4:2, er0) ; shift right arithmetic by one, disp2
;;; .word 0x0156
;;; .word 0x6908
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwdisp21
fail
.Lwdisp21:
mov.w #0xa5a5, @word_dest
shar_w_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
shar.w @(44:16, er0) ; shift right arithmetic by one, disp16
;;; .word 0x0154
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwdisp161
fail
.Lwdisp161:
mov.w #0xa5a5, @word_dest
shar_w_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
shar.w @(666:32, er0) ; shift right arithmetic by one, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwdisp321
fail
.Lwdisp321:
mov.w #0xa5a5, @word_dest
shar_w_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.w @word_dest:16 ; shift right arithmetic by one, abs16
;;; .word 0x6b18
;;; .word word_dest
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwabs161
fail
.Lwabs161:
mov.w #0xa5a5, @word_dest
shar_w_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.w @word_dest:32 ; shift right arithmetic by one, abs32
;;; .word 0x6b38
;;; .long word_dest
;;; .word 0x1190
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1101 0010 1101 0010
cmp.w #0xd2d2, @word_dest
beq .Lwabs321
fail
.Lwabs321:
mov.w #0xa5a5, @word_dest
.endif
shar_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.w #2, r0 ; shift right arithmetic by two
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
test_h_gr32 0xa5a5e969 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shar_w_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shar.w #2, @er0 ; shift right arithmetic by two, indirect
;;; .word 0x7d80
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwind2
fail
.Lwind2:
mov.w #0xa5a5, @word_dest
shar_w_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shar.w #2, @er0+ ; shift right arithmetic by two, postinc
;;; .word 0x0154
;;; .word 0x6d08
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwpostinc2
fail
.Lwpostinc2:
mov.w #0xa5a5, @word_dest
shar_w_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
shar.w #2, @er0- ; shift right arithmetic by two, postdec
;;; .word 0x0156
;;; .word 0x6d08
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwpostdec2
fail
.Lwpostdec2:
mov.w #0xa5a5, @word_dest
shar_w_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
shar.w #2, @+er0 ; shift right arithmetic by two, preinc
;;; .word 0x0155
;;; .word 0x6d08
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwpreinc2
fail
.Lwpreinc2:
mov.w #0xa5a5, @word_dest
shar_w_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
shar.w #2, @-er0 ; shift right arithmetic by two, predec
;;; .word 0x0157
;;; .word 0x6d08
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwpredec2
fail
.Lwpredec2:
mov.w #0xa5a5, @word_dest
shar_w_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
shar.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2
;;; .word 0x0156
;;; .word 0x6908
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwdisp22
fail
.Lwdisp22:
mov.w #0xa5a5, @word_dest
shar_w_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
;;; .word 0x0154
;;; .word 0x6f08
;;; .word 44
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwdisp162
fail
.Lwdisp162:
mov.w #0xa5a5, @word_dest
shar_w_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwdisp322
fail
.Lwdisp322:
mov.w #0xa5a5, @word_dest
shar_w_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
;;; .word 0x6b18
;;; .word word_dest
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwabs162
fail
.Lwabs162:
mov.w #0xa5a5, @word_dest
shar_w_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
;;; .word 0x6b38
;;; .long word_dest
;;; .word 0x11d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1110 1001 0110 1001
cmp.w #0xe969, @word_dest
beq .Lwabs322
fail
.Lwabs322:
mov.w #0xa5a5, @word_dest
.endif
shar_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.l er0 ; shift right arithmetic by one, register
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1101 0010 1101 0010 1101 0010 1101 0010
test_h_gr32 0xd2d2d2d2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shar_l_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shar.l @er0 ; shift right arithmetic by one, indirect
;;; .word 0x0104
;;; .word 0x6908
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llind1
fail
.Llind1:
mov #0xa5a5a5a5, @long_dest
shar_l_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shar.l @er0+ ; shift right arithmetic by one, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llpostinc1
fail
.Llpostinc1:
mov #0xa5a5a5a5, @long_dest
shar_l_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shar.l @er0- ; shift right arithmetic by one, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llpostdec1
fail
.Llpostdec1:
mov #0xa5a5a5a5, @long_dest
shar_l_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
shar.l @+er0 ; shift right arithmetic by one, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llpreinc1
fail
.Llpreinc1:
mov #0xa5a5a5a5, @long_dest
shar_l_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
shar.l @-er0 ; shift right arithmetic by one, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llpredec1
fail
.Llpredec1:
mov #0xa5a5a5a5, @long_dest
shar_l_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
shar.l @(8:2, er0) ; shift right arithmetic by one, disp2
;;; .word 0x0106
;;; .word 0x6908
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Lldisp21
fail
.Lldisp21:
mov #0xa5a5a5a5, @long_dest
shar_l_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
shar.l @(44:16, er0) ; shift right arithmetic by one, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Lldisp161
fail
.Lldisp161:
mov #0xa5a5a5a5, @long_dest
shar_l_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
shar.l @(666:32, er0) ; shift right arithmetic by one, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Lldisp321
fail
.Lldisp321:
mov #0xa5a5a5a5, @long_dest
shar_l_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.l @long_dest:16 ; shift right arithmetic by one, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llabs161
fail
.Llabs161:
mov #0xa5a5a5a5, @long_dest
shar_l_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.l @long_dest:32 ; shift right arithmetic by one, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x11b0
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0xd2d2d2d2, @long_dest
beq .Llabs321
fail
.Llabs321:
mov #0xa5a5a5a5, @long_dest
.endif
shar_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.l #2, er0 ; shift right arithmetic by two, register
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1110 1001 0110 1001 0110 1001 0110 1001
test_h_gr32 0xe9696969 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shar_l_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shar.l #2, @er0 ; shift right arithmetic by two, indirect
;;; .word 0x0104
;;; .word 0x6908
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Llind2
fail
.Llind2:
mov #0xa5a5a5a5, @long_dest
shar_l_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shar.l #2, @er0+ ; shift right arithmetic by two, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Llpostinc2
fail
.Llpostinc2:
mov #0xa5a5a5a5, @long_dest
shar_l_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
shar.l #2, @er0- ; shift right arithmetic by two, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Llpostdec2
fail
.Llpostdec2:
mov #0xa5a5a5a5, @long_dest
shar_l_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
shar.l #2, @+er0 ; shift right arithmetic by two, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Llpreinc2
fail
.Llpreinc2:
mov #0xa5a5a5a5, @long_dest
shar_l_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
shar.l #2, @-er0 ; shift right arithmetic by two, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Llpredec2
fail
.Llpredec2:
mov #0xa5a5a5a5, @long_dest
shar_l_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
shar.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2
;;; .word 0x0106
;;; .word 0x6908
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Lldisp22
fail
.Lldisp22:
mov #0xa5a5a5a5, @long_dest
shar_l_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
shar.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Lldisp162
fail
.Lldisp162:
mov #0xa5a5a5a5, @long_dest
shar_l_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
shar.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Lldisp322
fail
.Lldisp322:
mov #0xa5a5a5a5, @long_dest
shar_l_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Llabs162
fail
.Llabs162:
mov #0xa5a5a5a5, @long_dest
shar_l_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shar.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x11f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1110 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xe9696969, @long_dest
beq .Llabs322
fail
.Llabs322:
mov #0xa5a5a5a5, @long_dest
.endif
.endif
pass
exit 0
|
stsp/binutils-ia16
| 8,171
|
sim/testsuite/h8300/shll.s
|
# Hitachi H8 testcase 'shll'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
shll_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.b r0l ; shift left logical by one
;;; .word 0x1008
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
.if (sim_cpu)
test_h_gr32 0xa5a5a54a er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.b #2, r0l ; shift left logical by two
;;; .word 0x1048
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
.if (sim_cpu)
test_h_gr32 0xa5a5a594 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shll_b_reg8_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.b #4, r0l ; shift left logical by four
;;; .word 0x10a8
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000
test_h_gr32 0xa5a5a550 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #5, r0h
shll.b r0h, r0l ; shift left logical by register value
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000
test_h_gr32 0xa5a505a0 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; Not available in h8300 mode
shll_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.w r0 ; shift left logical by one
;;; .word 0x1010
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
test_h_gr32 0xa5a54b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.w #2, r0 ; shift left logical by two
;;; .word 0x1050
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
test_h_gr32 0xa5a59694 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shll_w_reg16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.w #4, r0 ; shift left logical by four
;;; .word 0x1020
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000
test_h_gr32 0xa5a55a50 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_w_reg16_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.w #8, r0 ; shift left logical by eight
;;; .word 0x1060
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000
test_h_gr32 0xa5a5a500 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_w_reg16_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #5, r0h
shll.w r0h, r0 ; shift left logical by register value
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000
test_h_gr32 0xa5a5b4a0 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
shll_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l er0 ; shift left logical by one
;;; .word 1030
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1010
test_h_gr32 0x4b4b4b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l #2, er0 ; shift left logical by two
;;; .word 0x1070
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0100
test_h_gr32 0x96969694 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shll_l_reg32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l #4, er0 ; shift left logical by four
;;; .word 0x1038
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0101 1010 0101 1010 0101 1010 0101 0000
test_h_gr32 0x5a5a5a50 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_l_reg32_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l #8, er0 ; shift left logical by eight
;;; .word 0x1078
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa500 r0
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1010 0101 1010 0101 1010 0101 0000 0000
test_h_gr32 0xa5a5a500 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_l_reg32_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l #16, er0 ; shift left logical by sixteen
;;; .word 0x10f8
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 0101 1010 0101 0000 0000 0000 0000
test_h_gr32 0xa5a50000 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_l_reg32_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #5, r1l
shll.l r1l, er0 ; shift left logical by register value
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1011 0100 1011 0100 1011 0100 1010 0000
test_h_gr32 0xb4b4b4a0 er0
test_h_gr32 0xa5a5a505 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.endif
pass
exit 0
|
stsp/binutils-ia16
| 42,455
|
sim/testsuite/h8300/rotxr.s
|
# Hitachi H8 testcase 'rotxr'
# mach(): h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
rotxr_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.b r0l ; shift right arithmetic by one
;;; .word 0x1308
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa552 r0 ; 1010 0101 -> 0101 0010
.if (sim_cpu)
test_h_gr32 0xa5a5a552 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotxr_b_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotxr.b @er0 ; shift right arithmetic by one, indirect
;;; .word 0x7d00
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbind1
fail
.Lbind1:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotxr.b @er0+ ; shift right arithmetic by one, postinc
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbpostinc1
fail
.Lbpostinc1:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotxr.b @er0- ; shift right arithmetic by one, postdec
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbpostdec1
fail
.Lbpostdec1:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
rotxr.b @+er0 ; shift right arithmetic by one, preinc
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbpreinc1
fail
.Lbpreinc1:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
rotxr.b @-er0 ; shift right arithmetic by one, predec
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbpredec1
fail
.Lbpredec1:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
rotxr.b @(2:2, er0) ; shift right arithmetic by one, disp2
;;; .word 0x0176
;;; .word 0x6808
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbdisp21
fail
.Lbdisp21:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
rotxr.b @(44:16, er0) ; shift right arithmetic by one, disp16
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 44
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbdisp161
fail
.Lbdisp161:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
rotxr.b @(666:32, er0) ; shift right arithmetic by one, disp32
;;; .word 0x7884
;;; .word 0x6a28
;;; .long 666
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbdisp321
fail
.Lbdisp321:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.b @byte_dest:16 ; shift right arithmetic by one, abs16
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbabs161
fail
.Lbabs161:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.b @byte_dest:32 ; shift right arithmetic by one, abs32
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x1300
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 0101 0010
cmp.b #0x52, @byte_dest
beq .Lbabs321
fail
.Lbabs321:
mov #0xa5a5a5a5, @byte_dest
.endif
rotxr_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.b #2, r0l ; shift right arithmetic by two
;;; .word 0x1348
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa5a9 r0 ; 1010 0101 -> 1010 1001
.if (sim_cpu)
test_h_gr32 0xa5a5a5a9 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotxr_b_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotxr.b #2, @er0 ; shift right arithmetic by two, indirect
;;; .word 0x7d00
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbind2
fail
.Lbind2:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotxr.b #2, @er0+ ; shift right arithmetic by two, postinc
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest+1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbpostinc2
fail
.Lbpostinc2:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest, er0
rotxr.b #2, @er0- ; shift right arithmetic by two, postdec
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-1 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbpostdec2
fail
.Lbpostdec2:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-1, er0
rotxr.b #2, @+er0 ; shift right arithmetic by two, preinc
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbpreinc2
fail
.Lbpreinc2:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest+1, er0
rotxr.b #2, @-er0 ; shift right arithmetic by two, predec
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbpredec2
fail
.Lbpredec2:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-2, er0
rotxr.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
;;; .word 0x0176
;;; .word 0x6808
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbdisp22
fail
.Lbdisp22:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-44, er0
rotxr.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 44
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbdisp162
fail
.Lbdisp162:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #byte_dest-666, er0
rotxr.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
;;; .word 0x7884
;;; .word 0x6a28
;;; .long 666
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 byte_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbdisp322
fail
.Lbdisp322:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbabs162
fail
.Lbabs162:
mov #0xa5a5a5a5, @byte_dest
rotxr_b_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x1340
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 -> 1010 1001
cmp.b #0xa9, @byte_dest
beq .Lbabs322
fail
.Lbabs322:
mov #0xa5a5a5a5, @byte_dest
.endif
.if (sim_cpu) ; Not available in h8300 mode
rotxr_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.w r0 ; shift right arithmetic by one
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x52d2 r0 ; 1010 0101 1010 0101 -> 0101 0010 1101 0010
test_h_gr32 0xa5a552d2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotxr_w_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotxr.w @er0 ; shift right arithmetic by one, indirect
;;; .word 0x7d80
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwind1
fail
.Lwind1:
mov #0xa5a5a5a5, @word_dest
rotxr_w_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotxr.w @er0+ ; shift right arithmetic by one, postinc
;;; .word 0x0154
;;; .word 0x6d08
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwpostinc1
fail
.Lwpostinc1:
mov #0xa5a5a5a5, @word_dest
rotxr_w_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotxr.w @er0- ; shift right arithmetic by one, postdec
;;; .word 0x0156
;;; .word 0x6d08
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwpostdec1
fail
.Lwpostdec1:
mov #0xa5a5a5a5, @word_dest
rotxr_w_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
rotxr.w @+er0 ; shift right arithmetic by one, preinc
;;; .word 0x0155
;;; .word 0x6d08
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwpreinc1
fail
.Lwpreinc1:
mov #0xa5a5a5a5, @word_dest
rotxr_w_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
rotxr.w @-er0 ; shift right arithmetic by one, predec
;;; .word 0x0157
;;; .word 0x6d08
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwpredec1
fail
.Lwpredec1:
mov #0xa5a5a5a5, @word_dest
rotxr_w_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
rotxr.w @(4:2, er0) ; shift right arithmetic by one, disp2
;;; .word 0x0156
;;; .word 0xa908
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwdisp21
fail
.Lwdisp21:
mov #0xa5a5a5a5, @word_dest
rotxr_w_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
rotxr.w @(44:16, er0) ; shift right arithmetic by one, disp16
;;; .word 0x0154
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwdisp161
fail
.Lwdisp161:
mov #0xa5a5a5a5, @word_dest
rotxr_w_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
rotxr.w @(666:32, er0) ; shift right arithmetic by one, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwdisp321
fail
.Lwdisp321:
mov #0xa5a5a5a5, @word_dest
rotxr_w_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.w @word_dest:16 ; shift right arithmetic by one, abs16
;;; .word 0x6b18
;;; .word word_dest
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwabs161
fail
.Lwabs161:
mov #0xa5a5a5a5, @word_dest
rotxr_w_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.w @word_dest:32 ; shift right arithmetic by one, abs32
;;; .word 0x6b38
;;; .long word_dest
;;; .word 0x1310
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 0101 0010 1101 0010
cmp.w #0x52d2, @word_dest
beq .Lwabs321
fail
.Lwabs321:
mov #0xa5a5a5a5, @word_dest
.endif
rotxr_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.w #2, r0 ; shift right arithmetic by two
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa969 r0 ; 1010 0101 1010 0101 -> 1010 1001 0110 1001
test_h_gr32 0xa5a5a969 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotxr_w_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotxr.w #2, @er0 ; shift right arithmetic by two, indirect
;;; .word 0x7d80
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwind2
fail
.Lwind2:
mov #0xa5a5a5a5, @word_dest
rotxr_w_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotxr.w #2, @er0+ ; shift right arithmetic by two, postinc
;;; .word 0x0154
;;; .word 0x6d08
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest+2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwpostinc2
fail
.Lwpostinc2:
mov #0xa5a5a5a5, @word_dest
rotxr_w_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest, er0
rotxr.w #2, @er0- ; shift right arithmetic by two, postdec
;;; .word 0x0156
;;; .word 0x6d08
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwpostdec2
fail
.Lwpostdec2:
mov #0xa5a5a5a5, @word_dest
rotxr_w_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-2, er0
rotxr.w #2, @+er0 ; shift right arithmetic by two, preinc
;;; .word 0x0155
;;; .word 0x6d08
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwpreinc2
fail
.Lwpreinc2:
mov #0xa5a5a5a5, @word_dest
rotxr_w_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest+2, er0
rotxr.w #2, @-er0 ; shift right arithmetic by two, predec
;;; .word 0x0157
;;; .word 0x6d08
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwpredec2
fail
.Lwpredec2:
mov #0xa5a5a5a5, @word_dest
rotxr_w_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-4, er0
rotxr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2
;;; .word 0x0156
;;; .word 0xa908
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwdisp22
fail
.Lwdisp22:
mov #0xa5a5a5a5, @word_dest
rotxr_w_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-44, er0
rotxr.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
;;; .word 0x0154
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwdisp162
fail
.Lwdisp162:
mov #0xa5a5a5a5, @word_dest
rotxr_w_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #word_dest-666, er0
rotxr.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 word_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwdisp322
fail
.Lwdisp322:
mov #0xa5a5a5a5, @word_dest
rotxr_w_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
;;; .word 0x6b18
;;; .word word_dest
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwabs162
fail
.Lwabs162:
mov #0xa5a5a5a5, @word_dest
rotxr_w_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
;;; .word 0x6b38
;;; .long word_dest
;;; .word 0x1350
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 -> 1010 1001 0110 1001
cmp.w #0xa969, @word_dest
beq .Lwabs322
fail
.Lwabs322:
mov #0xa5a5a5a5, @word_dest
.endif
rotxr_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.l er0 ; shift right arithmetic by one, register
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0101 0010 1101 0010 1101 0010 1101 0010
test_h_gr32 0x52d2d2d2 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotxr_l_ind_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotxr.l @er0 ; shift right arithmetic by one, indirect
;;; .word 0x0104
;;; .word 0xa908
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llind1
fail
.Llind1:
mov #0xa5a5a5a5, @long_dest
rotxr_l_postinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotxr.l @er0+ ; shift right arithmetic by one, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llpostinc1
fail
.Llpostinc1:
mov #0xa5a5a5a5, @long_dest
rotxr_l_postdec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotxr.l @er0- ; shift right arithmetic by one, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llpostdec1
fail
.Llpostdec1:
mov #0xa5a5a5a5, @long_dest
rotxr_l_preinc_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
rotxr.l @+er0 ; shift right arithmetic by one, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llpreinc1
fail
.Llpreinc1:
mov #0xa5a5a5a5, @long_dest
rotxr_l_predec_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
rotxr.l @-er0 ; shift right arithmetic by one, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llpredec1
fail
.Llpredec1:
mov #0xa5a5a5a5, @long_dest
rotxr_l_disp2_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
rotxr.l @(8:2, er0) ; shift right arithmetic by one, disp2
;;; .word 0x0106
;;; .word 0xa908
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Lldisp21
fail
.Lldisp21:
mov #0xa5a5a5a5, @long_dest
rotxr_l_disp16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
rotxr.l @(44:16, er0) ; shift right arithmetic by one, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Lldisp161
fail
.Lldisp161:
mov #0xa5a5a5a5, @long_dest
rotxr_l_disp32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
rotxr.l @(666:32, er0) ; shift right arithmetic by one, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Lldisp321
fail
.Lldisp321:
mov #0xa5a5a5a5, @long_dest
rotxr_l_abs16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.l @long_dest:16 ; shift right arithmetic by one, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llabs161
fail
.Llabs161:
mov #0xa5a5a5a5, @long_dest
rotxr_l_abs32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.l @long_dest:32 ; shift right arithmetic by one, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x1330
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 0101 0010 1101 0010 1101 0010 1101 0010
cmp.l #0x52d2d2d2, @long_dest
beq .Llabs321
fail
.Llabs321:
mov #0xa5a5a5a5, @long_dest
.endif
rotxr_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.l #2, er0 ; shift right arithmetic by two, register
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1010 1001 0110 1001 0110 1001 0110 1001
test_h_gr32 0xa9696969 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
rotxr_l_ind_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotxr.l #2, @er0 ; shift right arithmetic by two, indirect
;;; .word 0x0104
;;; .word 0xa908
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Llind2
fail
.Llind2:
mov #0xa5a5a5a5, @long_dest
rotxr_l_postinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotxr.l #2, @er0+ ; shift right arithmetic by two, postinc
;;; .word 0x0104
;;; .word 0x6d08
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest+4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Llpostinc2
fail
.Llpostinc2:
mov #0xa5a5a5a5, @long_dest
rotxr_l_postdec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest, er0
rotxr.l #2, @er0- ; shift right arithmetic by two, postdec
;;; .word 0x0106
;;; .word 0x6d08
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-4 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Llpostdec2
fail
.Llpostdec2:
mov #0xa5a5a5a5, @long_dest
rotxr_l_preinc_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-4, er0
rotxr.l #2, @+er0 ; shift right arithmetic by two, preinc
;;; .word 0x0105
;;; .word 0x6d08
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Llpreinc2
fail
.Llpreinc2:
mov #0xa5a5a5a5, @long_dest
rotxr_l_predec_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest+4, er0
rotxr.l #2, @-er0 ; shift right arithmetic by two, predec
;;; .word 0x0107
;;; .word 0x6d08
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Llpredec2
fail
.Llpredec2:
mov #0xa5a5a5a5, @long_dest
rotxr_l_disp2_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-8, er0
rotxr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2
;;; .word 0x0106
;;; .word 0xa908
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Lldisp22
fail
.Lldisp22:
mov #0xa5a5a5a5, @long_dest
rotxr_l_disp16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-44, er0
rotxr.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
;;; .word 0x0104
;;; .word 0x6f08
;;; .word 44
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-44 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Lldisp162
fail
.Lldisp162:
mov #0xa5a5a5a5, @long_dest
rotxr_l_disp32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
mov #long_dest-666, er0
rotxr.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
;;; .word 0x7884
;;; .word 0x6b28
;;; .long 666
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr32 long_dest-666 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Lldisp322
fail
.Lldisp322:
mov #0xa5a5a5a5, @long_dest
rotxr_l_abs16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
;;; .word 0x0104
;;; .word 0x6b08
;;; .word long_dest
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Llabs162
fail
.Llabs162:
mov #0xa5a5a5a5, @long_dest
rotxr_l_abs32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxr.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
;;; .word 0x0104
;;; .word 0x6b28
;;; .long long_dest
;;; .word 0x1370
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 1001 0110 1001 0110 1001 0110 1001
cmp.l #0xa9696969, @long_dest
beq .Llabs322
fail
.Llabs322:
mov #0xa5a5a5a5, @long_dest
.endif
.endif
pass
exit 0
|
stsp/binutils-ia16
| 2,597
|
sim/testsuite/h8300/inc.s
|
# Hitachi H8 testcase 'inc, inc.w, inc.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
inc_b:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.b Rd
inc.b r0h ; Increment 8-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa6a5 r0 ; inc result: a6|a5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; non-zero means h8300h, s, or sx
inc_w_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.w #1, Rd
inc.w #1, r0 ; Increment 16-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a6 r0 ; inc result: a5|a6
test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_w_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.w #2, Rd
inc.w #2, r0 ; Increment 16-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a7 r0 ; inc result: a5|a7
test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_l_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.l #1, eRd
inc.l #1, er0 ; Increment 32-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_l_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.l #2, eRd
inc.l #2, er0 ; Increment 32-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0
|
stsp/binutils-ia16
| 22,700
|
sim/testsuite/h8300/subx.s
|
# Hitachi H8 testcase 'subx'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# subx.b #xx:8, rd8 ; b rd8 xxxxxxxx
# subx.b #xx:8, @erd ; 7 d erd ???? b ???? xxxxxxxx
# subx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? b ???? xxxxxxxx
# subx.b rs8, rd8 ; 1 e rs8 rd8
# subx.b rs8, @erd ; 7 d erd ???? 1 e rs8 ????
# subx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 1 e rs8 ????
# subx.b @ers, rd8 ; 7 c ers ???? 1 e ???? rd8
# subx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 1 e ???? rd8
# subx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 3 ????
# subx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 3 ????
#
# word ops
# long ops
.data
byte_src: .byte 0x5
byte_dest: .byte 0
.align 2
word_src: .word 0x505
word_dest: .word 0
.align 4
long_src: .long 0x50505
long_dest: .long 0
start
subx_b_imm8_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; subx.b #xx:8,Rd ; Subx with carry initially zero.
subx.b #5, r0l ; Immediate 8-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_b_imm8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; subx.b #xx:8,Rd ; Subx with carry initially one.
set_carry_flag
subx.b #4, r0l ; Immediate 8-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa5a0 r0 ; sub result: a5 - (4 + 1)
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - (4 + 1)
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
subx_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b #xx:8,@eRd ; Subx to register indirect
mov #byte_dest, er0
mov.b #0xa5, @er0
set_ccr_zero
subx.b #5, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains subress
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.b #0xa0, @byte_dest
beq .Lb1
fail
.Lb1:
subx_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b #xx:8,@eRd- ; Subx to register post-decrement
mov #byte_dest, er0
mov.b #0xa5, @er0
set_ccr_zero
subx.b #5, @er0-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.b #0xa0, @byte_dest
beq .Lb2
fail
.Lb2:
.endif
subx_b_reg8_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b Rs,Rd ; subx with carry initially zero
mov.b #5, r0h
set_ccr_zero
subx.b r0h, r0l ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0x05a0 r0 ; sub result: a5 - 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b Rs,Rd ; subx with carry initially one
mov.b #4, r0h
set_ccr_zero
set_carry_flag
subx.b r0h, r0l ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0x04a0 r0 ; sub result: a5 - (4 + 1)
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a504a0 er0 ; sub result: a5 - (4 + 1)
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
subx_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b rs8,@eRd ; Subx to register indirect
mov #byte_dest, er0
mov.b #0xa5, @er0
mov.b #5, r1l
set_ccr_zero
subx.b r1l, @er0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains subress
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.b #0xa0, @byte_dest
beq .Lb3
fail
.Lb3:
subx_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b rs8,@eRd- ; Subx to register post-decrement
mov #byte_dest, er0
mov.b #0xa5, @er0
mov.b #5, r1l
set_ccr_zero
subx.b r1l, @er0-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one
test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.b #0xa0, @byte_dest
beq .Lb4
fail
.Lb4:
subx_b_rsind_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b @eRs,rd8 ; Subx from reg indirect to reg
mov #byte_src, er0
set_ccr_zero
subx.b @er0, r1l
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src er0 ; er0 still contains subress
test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_b_rspostdec_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b @eRs-,rd8 ; Subx to register post-decrement
mov #byte_src, er0
set_ccr_zero
subx.b @er0-, r1l
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src-1 er0 ; er0 contains subress minus one
test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_b_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.b @eRs,rd8 ; Subx from reg indirect to reg
mov #byte_src, er0
mov #byte_dest, er1
mov.b #0xa5, @er1
set_ccr_zero
subx.b @er0, @er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src er0 ; er0 still contains src subress
test_h_gr32 byte_dest er1 ; er1 still contains dst subress
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.b #0xa0, @byte_dest
beq .Lb5
fail
.Lb5:
subx_b_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
mov #byte_src, er0
mov #byte_dest, er1
mov.b #0xa5, @er1
set_ccr_zero
;; subx.b @eRs-,@erd- ; Subx post-decrement to post-decrement
subx.b @er0-, @er1-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src-1 er0 ; er0 contains src subress minus one
test_h_gr32 byte_dest-1 er1 ; er1 contains dst subress minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.b #0xa0, @byte_dest
beq .Lb6
fail
.Lb6:
subx_w_imm16_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; subx.w #xx:16,Rd ; Subx with carry initially zero.
subx.w #0x505, r0 ; Immediate 16-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505
test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_w_imm16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; subx.w #xx:16,Rd ; Subx with carry initially one.
set_carry_flag
subx.w #0x504, r0 ; Immediate 16-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + 1
test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + 1
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_w_imm16_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w #xx:16,@eRd ; Subx to register indirect
mov #word_dest, er0
mov.w #0xa5a5, @er0
set_ccr_zero
subx.w #0x505, @er0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_dest er0 ; er0 still contains subress
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.w #0xa0a0, @word_dest
beq .Lw1
fail
.Lw1:
subx_w_imm16_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w #xx:16,@eRd- ; Subx to register post-decrement
mov #word_dest, er0
mov.w #0xa5a5, @er0
set_ccr_zero
subx.w #0x505, @er0-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.w #0xa0a0, @word_dest
beq .Lw2
fail
.Lw2:
subx_w_reg16_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w Rs,Rd ; subx with carry initially zero
mov.w #0x505, e0
set_ccr_zero
subx.w e0, r0 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x0505a0a0 er0 ; sub result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w Rs,Rd ; subx with carry initially one
mov.w #0x504, e0
set_ccr_zero
set_carry_flag
subx.w e0, r0 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x0504a0a0 er0 ; sub result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_w_reg16_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w rs8,@eRd ; Subx to register indirect
mov #word_dest, er0
mov.w #0xa5a5, @er0
mov.w #0x505, r1
set_ccr_zero
subx.w r1, @er0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_dest er0 ; er0 still contains subress
test_h_gr32 0xa5a50505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.w #0xa0a0, @word_dest
beq .Lw3
fail
.Lw3:
subx_w_reg16_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w rs8,@eRd- ; Subx to register post-decrement
mov #word_dest, er0
mov.w #0xa5a5, @er0
mov.w #0x505, r1
set_ccr_zero
subx.w r1, @er0-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one
test_h_gr32 0xa5a50505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.w #0xa0a0, @word_dest
beq .Lw4
fail
.Lw4:
subx_w_rsind_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w @eRs,rd8 ; Subx from reg indirect to reg
mov #word_src, er0
set_ccr_zero
subx.w @er0, r1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src er0 ; er0 still contains subress
test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_w_rspostdec_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w @eRs-,rd8 ; Subx to register post-decrement
mov #word_src, er0
set_ccr_zero
subx.w @er0-, r1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src-2 er0 ; er0 contains subress minus one
test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_w_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w @eRs,rd8 ; Subx from reg indirect to reg
mov #word_src, er0
mov #word_dest, er1
mov.w #0xa5a5, @er1
set_ccr_zero
subx.w @er0, @er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src er0 ; er0 still contains src subress
test_h_gr32 word_dest er1 ; er1 still contains dst subress
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.w #0xa0a0, @word_dest
beq .Lw5
fail
.Lw5:
subx_w_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.w @eRs-,rd8 ; Subx to register post-decrement
mov #word_src, er0
mov #word_dest, er1
mov.w #0xa5a5, @er1
set_ccr_zero
subx.w @er0-, @er1-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src-2 er0 ; er0 contains src subress minus one
test_h_gr32 word_dest-2 er1 ; er1 contains dst subress minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.w #0xa0a0, @word_dest
beq .Lw6
fail
.Lw6:
subx_l_imm32_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; subx.l #xx:32,Rd ; Subx with carry initially zero.
subx.l #0x50505, er0 ; Immediate 32-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0xa5a0a0a0 er0 ; sub result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_l_imm32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; subx.l #xx:32,Rd ; Subx with carry initially one.
set_carry_flag
subx.l #0x50504, er0 ; Immediate 32-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0xa5a0a0a0 er0 ; sub result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_l_imm32_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l #xx:32,@eRd ; Subx to register indirect
mov #long_dest, er0
mov.l #0xa5a5a5a5, @er0
set_ccr_zero
subx.l #0x50505, @er0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_dest er0 ; er0 still contains subress
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.l #0xa5a0a0a0, @long_dest
beq .Ll1
fail
.Ll1:
subx_l_imm32_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l #xx:32,@eRd- ; Subx to register post-decrement
mov #long_dest, er0
mov.l #0xa5a5a5a5, @er0
set_ccr_zero
subx.l #0x50505, @er0-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.l #0xa5a0a0a0, @long_dest
beq .Ll2
fail
.Ll2:
subx_l_reg32_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l Rs,Rd ; subx with carry initially zero
mov.l #0x50505, er0
set_ccr_zero
subx.l er0, er1 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x50505 er0 ; sub load
test_h_gr32 0xa5a0a0a0 er1 ; sub result:
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l Rs,Rd ; subx with carry initially one
mov.l #0x50504, er0
set_ccr_zero
set_carry_flag
subx.l er0, er1 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x50504 er0 ; sub result:
test_h_gr32 0xa5a0a0a0 er1 ; sub result:
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_l_reg32_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l rs8,@eRd ; Subx to register indirect
mov #long_dest, er0
mov.l er1, @er0
mov.l #0x50505, er1
set_ccr_zero
subx.l er1, @er0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_dest er0 ; er0 still contains subress
test_h_gr32 0x50505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.l #0xa5a0a0a0, @long_dest
beq .Ll3
fail
.Ll3:
subx_l_reg32_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l rs8,@eRd- ; Subx to register post-decrement
mov #long_dest, er0
mov.l er1, @er0
mov.l #0x50505, er1
set_ccr_zero
subx.l er1, @er0-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one
test_h_gr32 0x50505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.l #0xa5a0a0a0, @long_dest
beq .Ll4
fail
.Ll4:
subx_l_rsind_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l @eRs,rd8 ; Subx from reg indirect to reg
mov #long_src, er0
set_ccr_zero
subx.l @er0, er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src er0 ; er0 still contains subress
test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_l_rspostdec_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l @eRs-,rd8 ; Subx to register post-decrement
mov #long_src, er0
set_ccr_zero
subx.l @er0-, er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src-4 er0 ; er0 contains subress minus one
test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
subx_l_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l @eRs,rd8 ; Subx from reg indirect to reg
mov #long_src, er0
mov #long_dest, er1
mov.l er2, @er1
set_ccr_zero
subx.l @er0, @er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src er0 ; er0 still contains src subress
test_h_gr32 long_dest er1 ; er1 still contains dst subress
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.l #0xa5a0a0a0, @long_dest
beq .Ll5
fail
.Ll5:
subx_l_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; subx.l @eRs-,rd8 ; Subx to register post-decrement
mov #long_src, er0
mov #long_dest, er1
mov.l er2, @er1
set_ccr_zero
subx.l @er0-, @er1-
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src-4 er0 ; er0 contains src subress minus one
test_h_gr32 long_dest-4 er1 ; er1 contains dst subress minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
cmp.l #0xa5a0a0a0, @long_dest
beq .Ll6
fail
.Ll6:
.endif
pass
exit 0
|
stsp/binutils-ia16
| 41,951
|
sim/testsuite/h8300/movw.s
|
# Hitachi H8 testcase 'mov.w'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 2
word_dst_dec:
.word 0
word_src:
.word 0x7777
word_dst:
.word 0
.text
;;
;; Move word from immediate source
;;
.if (sim_cpu == h8sx)
mov_w_imm3_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:3, rd
mov.w #0x3:3, r0 ; Immediate 3-bit operand
;;; .word 0x0f30
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a50003 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
mov_w_imm16_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, rd
mov.w #0x1234, r0 ; Immediate 16-bit operand
;;; .word 0x7900
;;; .word 0x1234
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a51234 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mov_w_imm4_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:4, @aa:16
mov.w #0xf:4, @word_dst:16 ; 4-bit imm to 16-bit address-direct
;;; .word 0x6bdf
;;; .word @word_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xf, @word_dst
beq .Lnext21
fail
.Lnext21:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm4_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:4, @aa:32
mov.w #0xf:4, @word_dst:32 ; 4-bit imm to 32-bit address-direct
;;; .word 0x6bff
;;; .long @word_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xf, @word_dst
beq .Lnext22
fail
.Lnext22:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @erd
mov.l #word_dst, er1
mov.w #0xa5:8, @er1 ; Register indirect operand
;;; .word 0x015d
;;; .word 0x01a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext1
fail
.Lnext1:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_postinc: ; post-increment from imm8 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @erd+
mov.l #word_dst, er1
mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands.
;;; .word 0x015d
;;; .word 0x81a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst+2, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext2
fail
.Lnext2:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @erd-
mov.l #word_dst, er1
mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands.
;;; .word 0x015d
;;; .word 0xa1a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-2, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext3
fail
.Lnext3:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @+erd
mov.l #word_dst-2, er1
mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands
;;; .word 0x015d
;;; .word 0x91a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext4
fail
.Lnext4:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @-erd
mov.l #word_dst+2, er1
mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands
;;; .word 0x015d
;;; .word 0xb1a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext5
fail
.Lnext5:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @(dd:2, erd)
mov.l #word_dst-6, er1
mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand
;;; .word 0x015d
;;; .word 0x31a5
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-6, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext6
fail
.Lnext6:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @(dd:16, erd)
mov.l #word_dst-4, er1
mov.w #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x015d
;;; .word 0x6f90
;;; .word 0x0004
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext7
fail
.Lnext7:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @(dd:32, erd)
mov.l #word_dst-8, er1
mov.w #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x015d
;;; .word 0xc9a5
;;; .long 8
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-8, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext8
fail
.Lnext8:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @aa:16
mov.w #0xa5:8, @word_dst:16 ; 16-bit address-direct operand
;;; .word 0x015d
;;; .word 0x40a5
;;; .word @word_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext9
fail
.Lnext9:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm8_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:8, @aa:32
mov.w #0xa5:8, @word_dst:32 ; 32-bit address-direct operand
;;; .word 0x015d
;;; .word 0x48a5
;;; .long @word_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xa5, @word_dst
beq .Lnext10
fail
.Lnext10:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @erd
mov.l #word_dst, er1
mov.w #0xdead:16, @er1 ; Register indirect operand
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0x0100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext11
fail
.Lnext11:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_postinc: ; post-increment from imm16 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @erd+
mov.l #word_dst, er1
mov.w #0xdead:16, @er1+ ; Imm16, register post-incr operands.
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0x8100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst+2, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext12
fail
.Lnext12:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_postdec: ; post-decrement from imm16 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @erd-
mov.l #word_dst, er1
mov.w #0xdead:16, @er1- ; Imm16, register post-decr operands.
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0xa100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-2, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext13
fail
.Lnext13:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @+erd
mov.l #word_dst-2, er1
mov.w #0xdead:16, @+er1 ; Imm16, register pre-incr operands
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0x9100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext14
fail
.Lnext14:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @-erd
mov.l #word_dst+2, er1
mov.w #0xdead:16, @-er1 ; Imm16, register pre-decr operands
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0xb100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext15
fail
.Lnext15:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @(dd:2, erd)
mov.l #word_dst-6, er1
mov.w #0xdead:16, @(6:2, er1) ; Imm16, reg plus 2-bit disp. operand
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0x3100
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-6, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext16
fail
.Lnext16:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @(dd:16, erd)
mov.l #word_dst-4, er1
mov.w #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0xc100
;;; .word 0x0004
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext17
fail
.Lnext17:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @(dd:32, erd)
mov.l #word_dst-8, er1
mov.w #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0xc900
;;; .long 8
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-8, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext18
fail
.Lnext18:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @aa:16
mov.w #0xdead:16, @word_dst:16 ; 16-bit address-direct operand
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0x4000
;;; .word @word_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext19
fail
.Lnext19:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_imm16_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w #xx:16, @aa:32
mov.w #0xdead:16, @word_dst:32 ; 32-bit address-direct operand
;;; .word 0x7974
;;; .word 0xdead
;;; .word 0x4800
;;; .long @word_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w #0xdead, @word_dst
beq .Lnext20
fail
.Lnext20:
mov.w #0, @word_dst ; zero it again for the next use.
.endif
;;
;; Move word from register source
;;
mov_w_reg16_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, erd
mov.w #0x1234, r1
mov.w r1, r0 ; Register 16-bit operand
;;; .word 0x0d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr16 0x1234 r0
test_h_gr16 0x1234 r1 ; mov src unchanged
.if (sim_cpu)
test_h_gr32 0xa5a51234 er0
test_h_gr32 0xa5a51234 er1 ; mov src unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_w_reg16_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @erd
mov.l #word_dst, er1
mov.w r0, @er1 ; Register indirect operand
;;; .word 0x6990
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.w #0, r0
mov.w @word_dst, r0
cmp.w r2, r0
beq .Lnext44
fail
.Lnext44:
mov.w #0, r0
mov.w r0, @word_dst ; zero it again for the next use.
.if (sim_cpu == h8sx)
mov_w_reg16_to_postinc: ; post-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @erd+
mov.l #word_dst, er1
mov.w r0, @er1+ ; Register post-incr operand
;;; .word 0x0153
;;; .word 0x6d90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst+2, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w r2, @word_dst
beq .Lnext49
fail
.Lnext49:
;; special case same register
mov.l #word_dst, er0
mov.w r0, r1
inc.w #2,r1
mov.w r0, @er0+
mov.w @word_dst, r0
cmp.w r0, r1
beq .Lnext53
fail
.Lnext53:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_reg16_to_postdec: ; post-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @erd-
mov.l #word_dst, er1
mov.w r0, @er1- ; Register post-decr operand
;;; .word 0x0151
;;; .word 0x6d90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-2, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w r2, @word_dst
beq .Lnext50
fail
.Lnext50:
;; special case same register
mov.l #word_dst, er0
mov.w r0, r1
dec.w #2, r1
mov.w r0, @er0-
mov.w @word_dst, r0
cmp.w r0, r1
beq .Lnext54
fail
.Lnext54:
mov.w #0, @word_dst ; zero it again for the next use.
mov_w_reg16_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @+erd
mov.l #word_dst-2, er1
mov.w r0, @+er1 ; Register pre-incr operand
;;; .word 0x0152
;;; .word 0x6d90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w r2, @word_dst
beq .Lnext51
fail
.Lnext51:
;; special case same register
mov.l #word_dst-2, er0
mov.w r0, r1
inc.w #2, r1
mov.w r0, @+er0
mov.w @word_dst, r0
cmp.w r0, r1
beq .Lnext55
fail
.Lnext55:
mov.w #0, @word_dst ; zero it again for the next use.
.endif
mov_w_reg16_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @-erd
mov.l #word_dst+2, er1
mov.w r0, @-er1 ; Register pre-decr operand
;;; .word 0x6d90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.w #0, r0
mov.w @word_dst, r0
cmp.w r2, r0
beq .Lnext48
fail
.Lnext48:
;; Special case in same register
;; CCR confirmation omitted
mov.l #word_dst+2, er1
mov.l er1, er0
dec.w #2, r1
mov.w r0, @-er0
mov.w @word_dst, r0
cmp.w r1, r0
beq .Lnext47
fail
.Lnext47:
mov.w #0, r0
mov.w r0, @word_dst ; zero it again for the next use.
.if (sim_cpu == h8sx)
mov_w_reg16_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @(dd:2, erd)
mov.l #word_dst-6, er1
mov.w r0, @(6:2, er1) ; Register plus 2-bit disp. operand
;;; .word 0x0153
;;; .word 0x6990
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 word_dst-6, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w r2, @word_dst
beq .Lnext52
fail
.Lnext52:
mov.w #0, @word_dst ; zero it again for the next use.
.endif
mov_w_reg16_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @(dd:16, erd)
mov.l #word_dst-4, er1
mov.w r0, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x6f90
;;; .word 0x0004
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 word_dst-4, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.w #0, r0
mov.w @word_dst, r0
cmp.w r2, r0
beq .Lnext45
fail
.Lnext45:
mov.w #0, r0
mov.w r0, @word_dst ; zero it again for the next use.
mov_w_reg16_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @(dd:32, erd)
mov.l #word_dst-8, er1
mov.w r0, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x7810
;;; .word 0x6ba0
;;; .long 8
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 word_dst-8, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.w #0, r0
mov.w @word_dst, r0
cmp.w r2, r0
beq .Lnext46
fail
.Lnext46:
mov.w #0, r0
mov.w r0, @word_dst ; zero it again for the next use.
mov_w_reg16_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @aa:16
mov.w r0, @word_dst:16 ; 16-bit address-direct operand
;;; .word 0x6b80
;;; .word @word_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.w #0, r0
mov.w @word_dst, r0
cmp.w r0, r1
beq .Lnext41
fail
.Lnext41:
mov.w #0, r0
mov.w r0, @word_dst ; zero it again for the next use.
mov_w_reg16_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w ers, @aa:32
mov.w r0, @word_dst:32 ; 32-bit address-direct operand
;;; .word 0x6ba0
;;; .long @word_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
mov.w #0, r0
mov.w @word_dst, r0
cmp.w r0, r1
beq .Lnext42
fail
.Lnext42:
mov.w #0, r0
mov.w r0, @word_dst ; zero it again for the next use.
;;
;; Move word to register destination.
;;
mov_w_indirect_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @ers, rd
mov.l #word_src, er1
mov.w @er1, r0 ; Register indirect operand
;;; .word 0x6910
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0
test_h_gr32 word_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_w_postinc_to_reg16: ; post-increment from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @ers+, rd
mov.l #word_src, er1
mov.w @er1+, r0 ; Register post-incr operand
;;; .word 0x6d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0
test_h_gr32 word_src+2, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mov_w_postdec_to_reg16: ; post-decrement from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @ers-, rd
mov.l #word_src, er1
mov.w @er1-, r0 ; Register post-decr operand
;;; .word 0x0152
;;; .word 0x6d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0
test_h_gr32 word_src-2, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_w_preinc_to_reg16: ; pre-increment from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @+ers, rd
mov.l #word_src-2, er1
mov.w @+er1, r0 ; Register pre-incr operand
;;; .word 0x0151
;;; .word 0x6d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0
test_h_gr32 word_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_w_predec_to_reg16: ; pre-decrement from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @-ers, rd
mov.l #word_src+2, er1
mov.w @-er1, r0 ; Register pre-decr operand
;;; .word 0x0153
;;; .word 0x6d10
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0
test_h_gr32 word_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_w_disp2_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @(dd:2, ers), rd
mov.l #word_src-2, er1
mov.w @(2:2, er1), r0 ; Register plus 2-bit disp. operand
;;; .word 0x0151
;;; .word 0x6910
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
test_h_gr32 word_src-2, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
mov_w_disp16_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @(dd:16, ers), rd
mov.l #word_src+0x1234, er1
mov.w @(-0x1234:16, er1), r0 ; Register plus 16-bit disp. operand
;;; .word 0x6f10
;;; .word -0x1234
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
test_h_gr32 word_src+0x1234, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_w_disp32_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @(dd:32, ers), rd
mov.l #word_src+65536, er1
mov.w @(-65536:32, er1), r0 ; Register plus 32-bit disp. operand
;;; .word 0x7810
;;; .word 0x6b20
;;; .long -65536
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
test_h_gr32 word_src+65536, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_w_abs16_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @aa:16, rd
mov.w @word_src:16, r0 ; 16-bit address-direct operand
;;; .word 0x6b00
;;; .word @word_src
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mov_w_abs32_to_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @aa:32, rd
mov.w @word_src:32, r0 ; 32-bit address-direct operand
;;; .word 0x6b20
;;; .long @word_src
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a57777 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
;;
;; Move word from memory to memory
;;
mov_w_indirect_to_indirect: ; reg indirect, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @ers, @erd
mov.l #word_src, er1
mov.l #word_dst, er0
mov.w @er1, @er0
;;; .word 0x0158
;;; .word 0x0100
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 word_dst er0
test_h_gr32 word_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext56
fail
.Lnext56:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext57
fail
.Lnext57: ; OK, pass on.
mov_w_postinc_to_postinc: ; reg post-increment, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @ers+, @erd+
mov.l #word_src, er1
mov.l #word_dst, er0
mov.w @er1+, @er0+
;;; .word 0x0158
;;; .word 0x8180
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 word_dst+2 er0
test_h_gr32 word_src+2 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext65
fail
.Lnext65:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext66
fail
.Lnext66: ; OK, pass on.
;; special case same register
mov.l #word_src, er0
mov.w @er0+, @er0+ ; copying word_src to word_dst
test_h_gr32 word_src+4 er0
cmp.w @word_src, @word_dst
beq .Lnext67
fail
.Lnext67:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.b @word_src, @word_dst
bne .Lnext68
fail
.Lnext68:
mov_w_postdec_to_postdec: ; reg post-decrement, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @ers-, @erd-
mov.l #word_src, er1
mov.l #word_dst, er0
mov.w @er1-, @er0-
;;; .word 0x0158
;;; .word 0xa1a0
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 word_dst-2 er0
test_h_gr32 word_src-2 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext75
fail
.Lnext75:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext76
fail
.Lnext76: ; OK, pass on.
;; special case same register
mov.l #word_src, er0
mov.w @er0-, @er0- ; copying word_src to word_dst_dec
test_h_gr32 word_src-4 er0
cmp.w @word_src, @word_dst_dec
beq .Lnext77
fail
.Lnext77:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst_dec
cmp.w @word_src, @word_dst_dec
bne .Lnext78
fail
.Lnext78:
mov_w_preinc_to_preinc: ; reg pre-increment, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @+ers, @+erd
mov.l #word_src-2, er1
mov.l #word_dst-2, er0
mov.w @+er1, @+er0
;;; .word 0x0158
;;; .word 0x9190
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 word_dst er0
test_h_gr32 word_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext85
fail
.Lnext85:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext86
fail
.Lnext86: ; OK, pass on.
;; special case same register
mov.l #word_src-2, er0
mov.w @+er0, @+er0 ; copying word_src to word_dst
test_h_gr32 word_src+2 er0
cmp.w @word_src, @word_dst
beq .Lnext87
fail
.Lnext87:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext88
fail
.Lnext88:
mov_w_predec_to_predec: ; reg pre-decrement, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @-ers, @-erd
mov.l #word_src+2, er1
mov.l #word_dst+2, er0
mov.w @-er1, @-er0
;;; .word 0x0158
;;; .word 0xb1b0
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 word_dst er0
test_h_gr32 word_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext95
fail
.Lnext95:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext96
fail
.Lnext96: ; OK, pass on.
;; special case same register
mov.l #word_src+2, er0
mov.w @-er0, @-er0 ; copying word_src to word_dst_dec
test_h_gr32 word_src-2 er0
cmp.w @word_src, @word_dst_dec
beq .Lnext97
fail
.Lnext97:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst_dec
cmp.w @word_src, @word_dst_dec
bne .Lnext98
fail
.Lnext98:
mov_w_disp2_to_disp2: ; reg 2-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @(dd:2, ers), @(dd:2, erd)
mov.l #word_src-2, er1
mov.l #word_dst-4, er0
mov.w @(2:2, er1), @(4:2, er0)
;;; .word 0x0158
;;; .word 0x1120
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 word_dst-4 er0
test_h_gr32 word_src-2 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext105
fail
.Lnext105:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext106
fail
.Lnext106: ; OK, pass on.
mov_w_disp16_to_disp16: ; reg 16-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @(dd:16, ers), @(dd:16, erd)
mov.l #word_src-1, er1
mov.l #word_dst-2, er0
mov.w @(1:16, er1), @(2:16, er0)
;;; .word 0x0158
;;; .word 0xc1c0
;;; .word 0x0001
;;; .word 0x0002
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 word_dst-2 er0
test_h_gr32 word_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext115
fail
.Lnext115:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext116
fail
.Lnext116: ; OK, pass on.
mov_w_disp32_to_disp32: ; reg 32-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @(dd:32, ers), @(dd:32, erd)
mov.l #word_src-1, er1
mov.l #word_dst-2, er0
mov.w @(1:32, er1), @(2:32, er0)
;;; .word 0x0158
;;; .word 0xc9c8
;;; .long 1
;;; .long 2
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 word_dst-2 er0
test_h_gr32 word_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext125
fail
.Lnext125:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext126
fail
.Lnext126: ; OK, pass on.
mov_w_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @aa:16, @aa:16
mov.w @word_src:16, @word_dst:16
;;; .word 0x0158
;;; .word 0x4040
;;; .word @word_src
;;; .word @word_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure *NO* general registers are changed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext135
fail
.Lnext135:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext136
fail
.Lnext136: ; OK, pass on.
mov_w_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; mov.w @aa:32, @aa:32
mov.w @word_src:32, @word_dst:32
;;; .word 0x0158
;;; .word 0x4848
;;; .long @word_src
;;; .long @word_dst
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_neg_clear
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure *NO* general registers are changed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.w @word_src, @word_dst
beq .Lnext145
fail
.Lnext145:
;; Now clear the destination location, and verify that.
mov.w #0, @word_dst
cmp.w @word_src, @word_dst
bne .Lnext146
fail
.Lnext146: ; OK, pass on.
.endif
pass
exit 0
|
stsp/binutils-ia16
| 7,295
|
sim/testsuite/h8300/mul.s
|
# Hitachi H8 testcase 'muls', 'muls/u', mulu', 'mulu/u', 'mulxs', 'mulxu'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx)
muls_w_reg_reg:
set_grs_a5a5
;; muls.w rs, rd
mov.w #32, r1
mov.w #-2, r2
set_ccr_zero
muls.w r2, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr16 -64 r1
test_h_gr32 0xa5a5fffe er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
muls_w_imm4_reg:
set_grs_a5a5
;; muls.w xx:4, rd
mov.w #-32, r1
set_ccr_zero
muls.w #2:4, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr16 -64 r1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
muls_l_reg_reg:
set_grs_a5a5
;; muls.l ers, erd
mov.l #320000, er1
mov.l #-2, er2
set_ccr_zero
muls.l er2, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 -640000 er1
test_h_gr32 -2 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
muls_l_imm4_reg:
set_grs_a5a5
;; muls.l xx:4, rd
mov.l #-320000, er1
set_ccr_zero
muls.l #2:4, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 -640000 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
muls_u_l_reg_reg:
set_grs_a5a5
;; muls/u.l ers, erd
mov.l #0x10000000, er1
mov.l #-16, er2
set_ccr_zero
muls/u.l er2, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 -1 er1
test_h_gr32 -16 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
muls_u_l_imm4_reg:
set_grs_a5a5
;; muls/u.l xx:4, rd
mov.l #0xffffffff, er1
set_ccr_zero
muls/u.l #2:4, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 -1 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mulu_w_reg_reg:
set_grs_a5a5
;; mulu.w rs, rd
mov.w #32, r1
mov.w #-2, r2
set_ccr_zero
mulu.w r2, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr16 -64 r1
test_h_gr32 0xa5a5fffe er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mulu_w_imm4_reg:
set_grs_a5a5
;; mulu.w xx:4, rd
mov.w #32, r1
set_ccr_zero
mulu.w #-2:4, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr16 0x1c0 r1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mulu_l_reg_reg:
set_grs_a5a5
;; mulu.l ers, erd
mov.l #320000, er1
mov.l #-2, er2
set_ccr_zero
mulu.l er2, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 -640000 er1
test_h_gr32 -2 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mulu_l_imm4_reg:
set_grs_a5a5
;; mulu.l xx:4, rd
mov.l #320000, er1
set_ccr_zero
mulu.l #-2:4, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 0x445c00 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mulu_u_l_reg_reg:
set_grs_a5a5
;; mulu/u.l ers, erd
mov.l #0x10000000, er1
mov.l #16, er2
set_ccr_zero
mulu/u.l er2, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 1 er1
test_h_gr32 16 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mulu_u_l_imm4_reg:
set_grs_a5a5
;; mulu/u.l xx:4, rd
mov.l #0xffffffff, er1
set_ccr_zero
mulu/u.l #2:4, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 0x1 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; not equal to zero ie. not h8
mulxs_b_reg_reg:
set_grs_a5a5
;; mulxs.b rs, rd
mov.b #32, r1l
mov.b #-2, r2l
set_ccr_zero
mulxs.b r2l, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr16 -64 r1
test_h_gr32 0xa5a5a5fe er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mulxs_b_imm4_reg:
set_grs_a5a5
;; mulxs.b xx:4, rd
mov.w #-32, r1
set_ccr_zero
mulxs.b #2:4, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr16 -64 r1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
mulxs_w_reg_reg:
set_grs_a5a5
;; mulxs.w ers, erd
mov.w #0x1000, r1
mov.w #-0x1000, r2
set_ccr_zero
mulxs.w r2, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 0xff000000 er1
test_h_gr32 0xa5a5f000 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mulxs_w_imm4_reg:
set_grs_a5a5
;; mulxs.w xx:4, rd
mov.w #-1, r1
set_ccr_zero
mulxs.w #2:4, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_carry_clear
test_zero_clear
test_ovf_clear
test_gr_a5a5 0
test_h_gr32 -2 er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
.endif ; not h8
mulxu_b_reg_reg:
set_grs_a5a5
;; mulxu.b rs, rd
mov.b #32, r1l
mov.b #-2, r2l
set_ccr_zero
mulxu.b r2l, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr16 0x1fc0 r1
test_h_gr16 0xa5fe r2
.if (sim_cpu)
test_h_gr32 0xa5a5a5fe er2
.endif
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; not h8
.if (sim_cpu == h8sx)
mulxu_b_imm4_reg:
set_grs_a5a5
;; mulxu.b xx:4, rd
mov.b #-32, r1l
set_ccr_zero
mulxu.b #2:4, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr16 0x1c0 r1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
mulxu_w_reg_reg:
set_grs_a5a5
;; mulxu.w ers, erd
mov.w #0x1000, r1
mov.w #-0x1000, r2
set_ccr_zero
mulxu.w r2, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 0x0f000000 er1
test_h_gr32 0xa5a5f000 er2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
mulxu_w_imm4_reg:
set_grs_a5a5
;; mulxu.w xx:4, rd
mov.w #-1, r1
set_ccr_zero
mulxu.w #2:4, er1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0
test_h_gr32 0x1fffe er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; h8sx
.endif ; not h8
pass
exit 0
|
stsp/binutils-ia16
| 41,115
|
sim/testsuite/h8300/addl.s
|
# Hitachi H8 testcase 'add.l'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.l xx:3, erd
# add.l xx:16, erd
# add.l xx:32, erd
# add.l xx:16, @erd
# add.l xx:16, @erd+
# add.l xx:16, @erd-
# add.l xx:16, @+erd
# add.l xx:16, @-erd
# add.l xx:16, @(dd:2, erd)
# add.l xx:16, @(dd:16, erd)
# add.l xx:16, @(dd:32, erd)
# add.l xx:16, @aa:16
# add.l xx:16, @aa:32
# add.l xx:32, @erd+
# add.l xx:32, @erd-
# add.l xx:32, @+erd
# add.l xx:32, @-erd
# add.l xx:32, @(dd:2, erd)
# add.l xx:32, @(dd:16, erd)
# add.l xx:32, @(dd:32, erd)
# add.l xx:32, @aa:16
# add.l xx:32, @aa:32
# add.l ers, erd
# add.l ers, @erd
# add.l ers, @erd+
# add.l ers, @erd-
# add.l ers, @+erd
# add.l ers, @-erd
# add.l ers, @(dd:2, erd)
# add.l ers, @(dd:16, erd)
# add.l ers, @(dd:32, erd)
# add.l ers, @aa:16
# add.l ers, @aa:32
# add.l ers, erd
# add.l @ers, erd
# add.l @ers+, erd
# add.l @ers-, erd
# add.l @+ers, erd
# add.l @-ers, erd
# add.l @(dd:2, ers), erd
# add.l @(dd:16, ers), erd
# add.l @(dd:32, ers), erd
# add.l @aa:16, erd
# add.l @aa:32, erd
# add.l @ers, @erd
# add.l @ers+, @erd+
# add.l @ers-, @erd-
# add.l @+ers, +@erd
# add.l @-ers, @-erd
# add.l @(dd:2, ers), @(dd:2, erd)
# add.l @(dd:16, ers), @(dd:16, erd)
# add.l @(dd:32, ers), @(dd:32, erd)
# add.l @aa:16, @aa:16
# add.l @aa:32, @aa:32
start
.data
.align 4
long_src:
.long 0x12345678
long_dst:
.long 0x87654321
.text
;;
;; Add long from immediate source
;;
.if (sim_cpu == h8sx)
add_l_imm3_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:3, erd
add.l #0x3:3, er0 ; Immediate 16-bit operand
;;; .word 0x0ab8
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5a5a8 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_imm16_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, erd
add.l #0x1234, er0 ; Immediate 16-bit operand
;;; .word 0x7a18
;;; .word 0x1234
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5b7d9 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
add_l_imm32_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, erd
add.l #0x12345678, er0 ; Immediate 32-bit operand
;;; .word 0x7a10
;;; .long 0x12345678
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
add_l_imm16_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @erd
mov.l #long_dst, er1
add.l #0xdead:16, @er1 ; Register indirect operand
;;; .word 0x010e
;;; .word 0x0110
;;; .word 0xdead
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext11
fail
.Lnext11:
mov.l #0x87654321, @long_dst ; Initialize it again for the next use.
add_l_imm16_to_postinc: ; post-increment from imm16 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @erd+
mov.l #long_dst, er1
add.l #0xdead:16, @er1+ ; Imm16, register post-incr operands.
;;; .word 0x010e
;;; .word 0x8110
;;; .word 0xdead
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst+4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext12
fail
.Lnext12:
mov.l #0x87654321, @long_dst ; initialize it again for the next use.
add_l_imm16_to_postdec: ; post-decrement from imm16 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @erd-
mov.l #long_dst, er1
add.l #0xdead:16, @er1- ; Imm16, register post-decr operands.
;;; .word 0x010e
;;; .word 0xa110
;;; .word 0xdead
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext13
fail
.Lnext13:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm16_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @+erd
mov.l #long_dst-4, er1
add.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands
;;; .word 0x010e
;;; .word 0x9110
;;; .word 0xdead
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext14
fail
.Lnext14:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm16_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @-erd
mov.l #long_dst+4, er1
add.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands
;;; .word 0x010e
;;; .word 0xb110
;;; .word 0xdead
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext15
fail
.Lnext15:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm16_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @(dd:2, erd)
mov.l #long_dst-12, er1
add.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand
;;; .word 0x010e
;;; .word 0x3110
;;; .word 0xdead
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-12, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext16
fail
.Lnext16:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm16_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @(dd:16, erd)
mov.l #long_dst-4, er1
add.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x010e
;;; .word 0xc110
;;; .word 0xdead
;;; .word 0x0004
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext17
fail
.Lnext17:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm16_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @(dd:32, erd)
mov.l #long_dst-8, er1
add.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x010e
;;; .word 0xc910
;;; .word 0xdead
;;; .long 8
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-8, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext18
fail
.Lnext18:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm16_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @aa:16
add.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand
;;; .word 0x010e
;;; .word 0x4010
;;; .word 0xdead
;;; .word @long_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext19
fail
.Lnext19:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm16_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:16, @aa:32
add.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand
;;; .word 0x010e
;;; .word 0x4810
;;; .word 0xdead
;;; .long @long_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x876621ce, @long_dst
beq .Lnext20
fail
.Lnext20:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @erd
mov.l #long_dst, er1
add.l #0xcafedead:32, @er1 ; Register indirect operand
;;; .word 0x010e
;;; .word 0x0118
;;; .long 0xcafedead
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext21
fail
.Lnext21:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_postinc: ; post-increment from imm32 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @erd+
mov.l #long_dst, er1
add.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands.
;;; .word 0x010e
;;; .word 0x8118
;;; .long 0xcafedead
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst+4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext22
fail
.Lnext22:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_postdec: ; post-decrement from imm32 to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @erd-
mov.l #long_dst, er1
add.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands.
;;; .word 0x010e
;;; .word 0xa118
;;; .long 0xcafedead
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext23
fail
.Lnext23:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @+erd
mov.l #long_dst-4, er1
add.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands
;;; .word 0x010e
;;; .word 0x9118
;;; .long 0xcafedead
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext24
fail
.Lnext24:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @-erd
mov.l #long_dst+4, er1
add.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands
;;; .word 0x010e
;;; .word 0xb118
;;; .long 0xcafedead
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext25
fail
.Lnext25:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @(dd:2, erd)
mov.l #long_dst-12, er1
add.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand
;;; .word 0x010e
;;; .word 0x3118
;;; .long 0xcafedead
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-12, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext26
fail
.Lnext26:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @(dd:16, erd)
mov.l #long_dst-4, er1
add.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x010e
;;; .word 0xc118
;;; .long 0xcafedead
;;; .word 0x0004
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext27
fail
.Lnext27:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @(dd:32, erd)
mov.l #long_dst-8, er1
add.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x010e
;;; .word 0xc918
;;; .long 0xcafedead
;;; .long 8
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-8, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext28
fail
.Lnext28:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @aa:16
add.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand
;;; .word 0x010e
;;; .word 0x4018
;;; .long 0xcafedead
;;; .word @long_dst
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext29
fail
.Lnext29:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_imm32_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l #xx:32, @aa:32
add.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand
;;; .word 0x010e
;;; .word 0x4818
;;; .long 0xcafedead
;;; .long @long_dst
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x526421ce, @long_dst
beq .Lnext30
fail
.Lnext30:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
.endif
;;
;; Add long from register source
;;
add_l_reg32_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, erd
mov.l #0x12345678, er1
add.l er1, er0 ; Register 32-bit operand
;;; .word 0x0a90
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0 ; add result
test_h_gr32 0x12345678 er1 ; add src unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
add_l_reg32_to_indirect:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @erd
mov.l #long_dst, er1
add.l er0, @er1 ; Register indirect operand
;;; .word 0x0109
;;; .word 0x0110
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext44
fail
.Lnext44:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_postinc: ; post-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @erd+
mov.l #long_dst, er1
add.l er0, @er1+ ; Register post-incr operand
;;; .word 0x0109
;;; .word 0x8110
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst+4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext49
fail
.Lnext49:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_postdec: ; post-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @erd-
mov.l #long_dst, er1
add.l er0, @er1- ; Register post-decr operand
;;; .word 0x0109
;;; .word 0xa110
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-4, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext50
fail
.Lnext50:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_preinc: ; pre-increment from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @+erd
mov.l #long_dst-4, er1
add.l er0, @+er1 ; Register pre-incr operand
;;; .word 0x0109
;;; .word 0x9110
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext51
fail
.Lnext51:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_predec: ; pre-decrement from register to mem
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @-erd
mov.l #long_dst+4, er1
add.l er0, @-er1 ; Register pre-decr operand
;;; .word 0x0109
;;; .word 0xb110
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext48
fail
.Lnext48:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_disp2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @(dd:2, erd)
mov.l #long_dst-12, er1
add.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand
;;; .word 0x0109
;;; .word 0x3110
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_h_gr32 long_dst-12, er1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext52
fail
.Lnext52:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @(dd:16, erd)
mov.l #long_dst-4, er1
add.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand
;;; .word 0x0109
;;; .word 0xc110
;;; .word 0x0004
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_h_gr32 long_dst-4, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext45
fail
.Lnext45:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @(dd:32, erd)
mov.l #long_dst-8, er1
add.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand
;;; .word 0x0109
;;; .word 0xc910
;;; .long 8
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_h_gr32 long_dst-8, er1
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext46
fail
.Lnext46:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @aa:16
add.l er0, @long_dst:16 ; 16-bit address-direct operand
;;; .word 0x0109
;;; .word 0x4110
;;; .word @long_dst
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext41
fail
.Lnext41:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
add_l_reg32_to_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l ers, @aa:32
add.l er0, @long_dst:32 ; 32-bit address-direct operand
;;; .word 0x0109
;;; .word 0x4910
;;; .long @long_dst
;; test ccr ; H=0 N=0 Z=0 V=1 C=1
test_neg_clear
test_zero_clear
test_ovf_set
test_carry_set
test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
test_gr_a5a5 1 ; (first, because on h8/300 we must use one
test_gr_a5a5 2 ; to examine the destination memory).
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x2d0ae8c6, @long_dst
beq .Lnext42
fail
.Lnext42:
mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
;;
;; Add long to register destination.
;;
add_l_indirect_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @ers, Rd
mov.l #long_src, er1
add.l @er1, er0 ; Register indirect operand
;;; .word 0x010a
;;; .word 0x0110
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0
test_h_gr32 long_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_postinc_to_reg32: ; post-increment from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @ers+, erd
mov.l #long_src, er1
add.l @er1+, er0 ; Register post-incr operand
;;; .word 0x010a
;;; .word 0x8110
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0
test_h_gr32 long_src+4, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_postdec_to_reg32: ; post-decrement from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @ers-, erd
mov.l #long_src, er1
add.l @er1-, er0 ; Register post-decr operand
;;; .word 0x010a
;;; .word 0xa110
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0
test_h_gr32 long_src-4, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_preinc_to_reg32: ; pre-increment from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @+ers, erd
mov.l #long_src-4, er1
add.l @+er1, er0 ; Register pre-incr operand
;;; .word 0x010a
;;; .word 0x9110
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0
test_h_gr32 long_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_predec_to_reg32: ; pre-decrement from mem to register
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @-ers, erd
mov.l #long_src+4, er1
add.l @-er1, er0 ; Register pre-decr operand
;;; .word 0x010a
;;; .word 0xb110
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0
test_h_gr32 long_src, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_disp2_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @(dd:2, ers), erd
mov.l #long_src-4, er1
add.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand
;;; .word 0x010a
;;; .word 0x1110
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
test_h_gr32 long_src-4, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_disp16_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @(dd:16, ers), erd
mov.l #long_src+0x1234, er1
add.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand
;;; .word 0x010a
;;; .word 0xc110
;;; .word -0x1234
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
test_h_gr32 long_src+0x1234, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_disp32_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @(dd:32, ers), erd
mov.l #long_src+65536, er1
add.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand
;;; .word 0x010a
;;; .word 0xc910
;;; .long -65536
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
test_h_gr32 long_src+65536, er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_abs16_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @aa:16, erd
add.l @long_src:16, er0 ; 16-bit address-direct operand
;;; .word 0x010a
;;; .word 0x4010
;;; .word @long_src
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
add_l_abs32_to_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @aa:32, erd
add.l @long_src:32, er0 ; 32-bit address-direct operand
;;; .word 0x010a
;;; .word 0x4810
;;; .long @long_src
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xb7d9fc1d er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;;
;; Add long from memory to memory
;;
add_l_indirect_to_indirect: ; reg indirect, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @ers, @erd
mov.l #long_src, er1
mov.l #long_dst, er0
add.l @er1, @er0
;;; .word 0x0104
;;; .word 0x691c
;;; .word 0x0010
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst er0
test_h_gr32 long_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst ; FIXME
beq .Lnext55
fail
.Lnext55:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext56
fail
.Lnext56: ; OK, pass on.
add_l_postinc_to_postinc: ; reg post-increment, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @ers+, @erd+
mov.l #long_src, er1
mov.l #long_dst, er0
add.l @er1+, @er0+
;;; .word 0x0104
;;; .word 0x6d1c
;;; .word 0x8010
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst+4 er0
test_h_gr32 long_src+4 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext65
fail
.Lnext65:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext66
fail
.Lnext66: ; OK, pass on.
add_l_postdec_to_postdec: ; reg post-decrement, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @ers-, @erd-
mov.l #long_src, er1
mov.l #long_dst, er0
add.l @er1-, @er0-
;;; .word 0x0106
;;; .word 0x6d1c
;;; .word 0xa010
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst-4 er0
test_h_gr32 long_src-4 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext75
fail
.Lnext75:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext76
fail
.Lnext76: ; OK, pass on.
add_l_preinc_to_preinc: ; reg pre-increment, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @+ers, @+erd
mov.l #long_src-4, er1
mov.l #long_dst-4, er0
add.l @+er1, @+er0
;;; .word 0x0105
;;; .word 0x6d1c
;;; .word 0x9010
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst er0
test_h_gr32 long_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext85
fail
.Lnext85:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext86
fail
.Lnext86: ; OK, pass on.
add_l_predec_to_predec: ; reg pre-decrement, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @-ers, @-erd
mov.l #long_src+4, er1
mov.l #long_dst+4, er0
add.l @-er1, @-er0
;;; .word 0x0107
;;; .word 0x6d1c
;;; .word 0xb010
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst er0
test_h_gr32 long_src er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext95
fail
.Lnext95:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext96
fail
.Lnext96: ; OK, pass on.
add_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @(dd:2, ers), @(dd:2, erd)
mov.l #long_src-4, er1
mov.l #long_dst-8, er0
add.l @(4:2, er1), @(8:2, er0)
;;; .word 0x0105
;;; .word 0x691c
;;; .word 0x2010
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst-8 er0
test_h_gr32 long_src-4 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext105
fail
.Lnext105:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext106
fail
.Lnext106: ; OK, pass on.
add_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @(dd:16, ers), @(dd:16, erd)
mov.l #long_src-1, er1
mov.l #long_dst-2, er0
add.l @(1:16, er1), @(2:16, er0)
;;; .word 0x0104
;;; .word 0x6f1c
;;; .word 0x0001
;;; .word 0xc010
;;; .word 0x0002
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst-2 er0
test_h_gr32 long_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext115
fail
.Lnext115:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext116
fail
.Lnext116: ; OK, pass on.
add_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @(dd:32, ers), @(dd:32, erd)
mov.l #long_src-1, er1
mov.l #long_dst-2, er0
add.l @(1:32, er1), @(2:32, er0)
;;; .word 0x7894
;;; .word 0x6b2c
;;; .word 0xc9c8
;;; .long 1
;;; .word 0xc810
;;; .long 2
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
;; Verify the affected registers.
test_h_gr32 long_dst-2 er0
test_h_gr32 long_src-1 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext125
fail
.Lnext125:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext126
fail
.Lnext126: ; OK, pass on.
add_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @aa:16, @aa:16
add.l @long_src:16, @long_dst:16
;;; .word 0x0104
;;; .word 0x6b0c
;;; .word @long_src
;;; .word 0x4010
;;; .word @long_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure *NO* general registers are changed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext135
fail
.Lnext135:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext136
fail
.Lnext136: ; OK, pass on.
add_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.l @aa:32, @aa:32
add.l @long_src:32, @long_dst:32
;;; .word 0x0104
;;; .word 0x6b2c
;;; .long @long_src
;;; .word 0x4810
;;; .long @long_dst
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_gr_a5a5 0 ; Make sure *NO* general registers are changed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the move to memory.
cmp.l #0x99999999, @long_dst
beq .Lnext145
fail
.Lnext145:
;; Now clear the destination location, and verify that.
mov.l #0x87654321, @long_dst
cmp.l #0x99999999, @long_dst
bne .Lnext146
fail
.Lnext146: ; OK, pass on.
.endif
pass
exit 0
|
stsp/binutils-ia16
| 5,445
|
sim/testsuite/or1k/mfspr.S
|
/* Tests instructions l.mfspr and l.mtspr.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00000000);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000801);\n
# output: report(0x00002000);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002000);\n
# output: report(0x00000801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00000001);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000800);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00000000);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000801);\n
# output: report(0x00002000);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002000);\n
# output: report(0x00000801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00002801);\n
# output: report(0x00000001);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: report(0x00000800);\n
# output: report(0x00002801);\n
# output: report(0xdeadbeef);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-env.h"
#define MACLO_VAL 0xdeadbeef
/* A macro to carry out a test of l.mfspr.
MACLO (0x2801) is used as the SPR, since it can be read and
cleared using l.macrc and can be set using l.maci. spr_number
and immediate_val_to_or should be chosen to address this
register.
The value placed in the register is entirely arbitrary - we use
0xdeadbeef. */
.macro TEST_MFSPR spr_number, immediate_val_to_or
REPORT_IMMEDIATE_TO_CONSOLE \spr_number
REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or
/* Write MACLO_VAL to MACLO. */
l.macrc r2
LOAD_IMMEDIATE r2, MACLO_VAL
l.maci r2, 1
LOAD_IMMEDIATE r5, \spr_number
l.mfspr r4, r5, \immediate_val_to_or
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
/* A macro to carry out a test of l.mtspr
MACLO (0x2801) is used as the SPR, since it can be read and
cleared using l.macrc and can be set using l.maci. The
arguments spr_number and immediate_val_to_or should be chosen
to address this register.
The value placed in the register is entirely arbitrary - we use
0xdeadbeef. */
.macro TEST_MTSPR spr_number, immediate_val_to_or
REPORT_IMMEDIATE_TO_CONSOLE \spr_number
REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or
/* Clear MACLO */
l.macrc r2
LOAD_IMMEDIATE r4, MACLO_VAL
LOAD_IMMEDIATE r5, \spr_number
l.mtspr r5, r4, \immediate_val_to_or
/* Retrieve MACLO. */
l.macrc r4
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test the l.mfspr instruction with a range of operands. */
/* Move a test value using zero in the register. */
TEST_MFSPR SPR_VR, SPR_MACLO /* 0x0000, 0x2801 */
/* Move a test value using zero as the constant. */
TEST_MFSPR SPR_MACLO, SPR_VR /* 0x2801, 0x0000 */
/* Move a test value using non-zero in both register and constant. */
/* Some of these values will not give the correct result if OR
rather than ADD is used to determine the SPR address. */
TEST_MFSPR SPR_MACLO, SPR_MACLO /* 0x2801, 0x2801 */
TEST_MFSPR SPR_DMMUPR, SPR_ICCR /* 0x0801, 0x2000 */
TEST_MFSPR SPR_ICCR, SPR_DMMUPR /* 0x2000, 0x0801 */
TEST_MFSPR SPR_MACLO, SPR_UPR /* 0x2801, 0x0001 */
TEST_MFSPR SPR_DMMUCR, SPR_MACLO /* 0x0800, 0x2801 */
/* Test the l.mtspr instruction with a range of operands. */
/* Move a test value using zero in the register. */
TEST_MTSPR SPR_VR, SPR_MACLO /* 0x0000, 0x2801 */
/* Move a test value using zero as the constant. */
TEST_MTSPR SPR_MACLO, SPR_VR /* 0x2801, 0x0000 */
/* Move a test value using non-zero in both register and constant. */
/* Some of these values will not give the correct result if or
rather than add is used to determine the SPR address. */
TEST_MTSPR SPR_MACLO, SPR_MACLO /* 0x2801, 0x2801 */
TEST_MTSPR SPR_DMMUPR, SPR_ICCR /* 0x0801, 0x2000 */
TEST_MTSPR SPR_ICCR, SPR_DMMUPR /* 0x2000, 0x0801 */
TEST_MTSPR SPR_MACLO, SPR_UPR /* 0x2801, 0x0001 */
TEST_MTSPR SPR_DMMUCR, SPR_MACLO /* 0x0800, 0x2801 */
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 7,113
|
sim/testsuite/or1k/ext.S
|
/* Tests the l.ext{b,h}{s,z} instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x0000007f);\n
# output: report(0x0000007f);\n
# output: report(0x00000053);\n
# output: report(0x00000053);\n
# output: report(0x0000ff53);\n
# output: report(0x00000053);\n
# output: report(0x00001234);\n
# output: report(0x00000034);\n
# output: report(0x000000ff);\n
# output: report(0xffffffff);\n
# output: report(0x00000080);\n
# output: report(0xffffff80);\n
# output: report(0x0000ff80);\n
# output: report(0xffffff80);\n
# output: report(0x00007f80);\n
# output: report(0xffffff80);\n
# output: report(0x00007fff);\n
# output: report(0xffffffff);\n
# output: report(0x0000007f);\n
# output: report(0x0000007f);\n
# output: report(0x00000053);\n
# output: report(0x00000053);\n
# output: report(0x0000ff53);\n
# output: report(0x00000053);\n
# output: report(0x00001234);\n
# output: report(0x00000034);\n
# output: report(0x000000ff);\n
# output: report(0x000000ff);\n
# output: report(0x00000080);\n
# output: report(0x00000080);\n
# output: report(0x0000ff80);\n
# output: report(0x00000080);\n
# output: report(0x00007f80);\n
# output: report(0x00000080);\n
# output: report(0x00007fff);\n
# output: report(0x000000ff);\n
# output: report(0x00007fff);\n
# output: report(0x00007fff);\n
# output: report(0x00005233);\n
# output: report(0x00005233);\n
# output: report(0xffff2f53);\n
# output: report(0x00002f53);\n
# output: report(0x12345678);\n
# output: report(0x00005678);\n
# output: report(0x0000ffff);\n
# output: report(0xffffffff);\n
# output: report(0x00008000);\n
# output: report(0xffff8000);\n
# output: report(0x0000ff80);\n
# output: report(0xffffff80);\n
# output: report(0x80008000);\n
# output: report(0xffff8000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00007fff);\n
# output: report(0x00007fff);\n
# output: report(0x00005233);\n
# output: report(0x00005233);\n
# output: report(0xffff2f53);\n
# output: report(0x00002f53);\n
# output: report(0x12345678);\n
# output: report(0x00005678);\n
# output: report(0x0000ffff);\n
# output: report(0x0000ffff);\n
# output: report(0x00008000);\n
# output: report(0x00008000);\n
# output: report(0x0000ff80);\n
# output: report(0x0000ff80);\n
# output: report(0x80008000);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x0000ffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x7fff7fff);\n
# output: report(0x7fff7fff);\n
# output: report(0xffff7f7f);\n
# output: report(0xffff7f7f);\n
# output: report(0xffffff7f);\n
# output: report(0xffffff7f);\n
# output: report(0xffff7fff);\n
# output: report(0xffff7fff);\n
# output: report(0x7fff7f7f);\n
# output: report(0x7fff7f7f);\n
# output: report(0x12345678);\n
# output: report(0x12345678);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x7fff7fff);\n
# output: report(0x7fff7fff);\n
# output: report(0xffff7f7f);\n
# output: report(0xffff7f7f);\n
# output: report(0xffffff7f);\n
# output: report(0xffffff7f);\n
# output: report(0xffff7fff);\n
# output: report(0xffff7fff);\n
# output: report(0x7fff7f7f);\n
# output: report(0x7fff7f7f);\n
# output: report(0x12345678);\n
# output: report(0x12345678);\n
# output: exit(0)\n
#include "or1k-asm-test-env.h"
.macro CHECK_EXT insn, val, mask, high_mask
LOAD_IMMEDIATE r4, \val
REPORT_REG_TO_CONSOLE r4
\insn r5, r4
REPORT_REG_TO_CONSOLE r5
LOAD_IMMEDIATE r6, \mask
l.xori r7, r6, -1
l.and r8, r4, r6
l.and r9, r5, r6
l.sfne r8, r9
OR1K_DELAYED_NOP (l.bf ext_fail)
l.and r8, r5, r7
LOAD_IMMEDIATE r7, \high_mask
l.sfne r8, r7
OR1K_DELAYED_NOP (l.bf ext_fail)
.endm
#define CHECK_HIGH3_CLEAR(insn, val) CHECK_EXT insn, val, 0x000000ff, 0
#define CHECK_HIGH3_SET(val) CHECK_EXT l.extbs, val, 0x000000ff, 0xffffff00
#define CHECK_HIGH2_CLEAR(insn, val) CHECK_EXT insn, val, 0x0000ffff, 0
#define CHECK_HIGH2_SET(val) CHECK_EXT l.exths, val, 0x0000ffff, 0xffff0000
.macro CHECK_MOVE insn, val
LOAD_IMMEDIATE r4, \val
REPORT_REG_TO_CONSOLE r4
\insn r5, r4
REPORT_REG_TO_CONSOLE r5
l.sfne r5, r4
OR1K_DELAYED_NOP (l.bf ext_fail)
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.extbs */
CHECK_HIGH3_CLEAR ( l.extbs, 0x7f )
CHECK_HIGH3_CLEAR ( l.extbs, 0x53 )
CHECK_HIGH3_CLEAR ( l.extbs, 0xff53 )
CHECK_HIGH3_CLEAR ( l.extbs, 0x1234 )
CHECK_HIGH3_SET (0xff)
CHECK_HIGH3_SET (0x80)
CHECK_HIGH3_SET (0xff80)
CHECK_HIGH3_SET (0x7f80)
CHECK_HIGH3_SET (0x7fff)
/* Test l.extbz */
CHECK_HIGH3_CLEAR (l.extbz, 0x7f)
CHECK_HIGH3_CLEAR (l.extbz, 0x53)
CHECK_HIGH3_CLEAR (l.extbz, 0xff53)
CHECK_HIGH3_CLEAR (l.extbz, 0x1234)
CHECK_HIGH3_CLEAR (l.extbz, 0xff)
CHECK_HIGH3_CLEAR (l.extbz, 0x80)
CHECK_HIGH3_CLEAR (l.extbz, 0xff80)
CHECK_HIGH3_CLEAR (l.extbz, 0x7f80)
CHECK_HIGH3_CLEAR (l.extbz, 0x7fff)
/* Test l.exths */
CHECK_HIGH2_CLEAR (l.exths, 0x7fff)
CHECK_HIGH2_CLEAR (l.exths, 0x5233)
CHECK_HIGH2_CLEAR (l.exths, 0xffff2f53)
CHECK_HIGH2_CLEAR (l.exths, 0x12345678)
CHECK_HIGH2_SET (0xffff)
CHECK_HIGH2_SET (0x8000)
CHECK_HIGH2_SET (0xff80)
CHECK_HIGH2_SET (0x80008000)
CHECK_HIGH2_SET (0x7fffffff)
/* Test l.exthz */
CHECK_HIGH2_CLEAR (l.exthz, 0x7fff)
CHECK_HIGH2_CLEAR (l.exthz, 0x5233)
CHECK_HIGH2_CLEAR (l.exthz, 0xffff2f53)
CHECK_HIGH2_CLEAR (l.exthz, 0x12345678)
CHECK_HIGH2_CLEAR (l.exthz, 0xffff)
CHECK_HIGH2_CLEAR (l.exthz, 0x8000)
CHECK_HIGH2_CLEAR (l.exthz, 0xff80)
CHECK_HIGH2_CLEAR (l.exthz, 0x80008000)
CHECK_HIGH2_CLEAR (l.exthz, 0x7fffffff)
/* Test l.extws */
CHECK_MOVE l.extws, 0xffffffff
CHECK_MOVE l.extws, 0x7fffffff
CHECK_MOVE l.extws, 0x7fff7fff
CHECK_MOVE l.extws, 0xffff7f7f
CHECK_MOVE l.extws, 0xffffff7f
CHECK_MOVE l.extws, 0xffff7fff
CHECK_MOVE l.extws, 0x7fff7f7f
CHECK_MOVE l.extws, 0x12345678
/* Test l.extwz */
CHECK_MOVE l.extwz, 0xffffffff
CHECK_MOVE l.extwz, 0x7fffffff
CHECK_MOVE l.extwz, 0x7fff7fff
CHECK_MOVE l.extwz, 0xffff7f7f
CHECK_MOVE l.extwz, 0xffffff7f
CHECK_MOVE l.extwz, 0xffff7fff
CHECK_MOVE l.extwz, 0x7fff7f7f
CHECK_MOVE l.extwz, 0x12345678
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
ext_fail:
EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR
|
stsp/binutils-ia16
| 6,227
|
sim/testsuite/or1k/or.S
|
/* Tests instructions l.or, l.ori.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x55555555);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xc4c70f07);\n
# output: report(0xccf7ff7f);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x38f0f83b);\n
# output: report(0xbbffffbb);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000ffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x0000aaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00005555);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00005555);\n
# output: report(0xaaaaffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f83);\n
# output: report(0x4c70ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f07);\n
# output: report(0x4c70ff7f);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000f83b);\n
# output: report(0xb38fffbb);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Always set OVE. We should never trigger an exception, even if
this bit is set. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test the l.or instruction with a range of operands. */
TEST_INST_I32_I32 l.or, 0x00000000, 0x00000000
TEST_INST_I32_I32 l.or, 0xffffffff, 0xffffffff
TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x00000000
TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0xaaaaaaaa
TEST_INST_I32_I32 l.or, 0x55555555, 0x00000000
TEST_INST_I32_I32 l.or, 0x55555555, 0x55555555
TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x55555555
TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xb38f0f83
TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xc4c70f07
TEST_INST_I32_I32 l.or, 0xb38f0f83, 0x38f0f83b
/* Test the l.ori instruction with a range of operands. */
TEST_INST_I32_I16 l.ori, 0x00000000, 0x0000
TEST_INST_I32_I16 l.ori, 0xffffffff, 0xffff
TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x0000
TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0xaaaa
TEST_INST_I32_I16 l.ori, 0x55555555, 0x0000
TEST_INST_I32_I16 l.ori, 0x55555555, 0x5555
TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x5555
TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f83
TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f07
TEST_INST_I32_I16 l.ori, 0xb38f0f83, 0xf83b
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 9,037
|
sim/testsuite/or1k/flag.S
|
/* Tests the set flag (l.sf*) instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
#define INT_MAX 2147483647 /* 0x7fffffff */
#define INT_MAX_MIN1 2147483646 /* 0x7ffffffe */
#define NEG_INT_MAX -2147483648 /* 0x80000000 */
#define NEG_INT_MAX_PL1 -2147483647 /* 0x80000001 */
#define MIN1 -1 /* 0xffffffff */
#define SHRT_MIN (-32768)
#define SHRT_MAX 32767
#define UINT_MAX 4294967295 /* 0xffffffff */
#define UINT_MAX_MIN1 4294967294 /* 0xfffffffe */
#define USHRT_MAX 65535
.macro MOVE_TO_R4_R5_AND_REPORT a, b
LOAD_IMMEDIATE r4, \a
LOAD_IMMEDIATE r5, \b
/* During development, add REPORT_xxx statements here to see the
operands. */
.endm
.macro MOVE_TO_R4_AND_REPORT_I a, b
LOAD_IMMEDIATE r4, \a
/* During development, add REPORT_xxx statements here to see the
operands. */
.endm
.macro SHOULD_BE_SET
OR1K_DELAYED_NOP (l.bnf failed)
.endm
.macro SHOULDNT_BE_SET
OR1K_DELAYED_NOP (l.bf failed)
.endm
.macro SHOULD_BE_LESS_THAN_SIGNED a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
l.sfgts r4, r5
SHOULDNT_BE_SET
l.sfges r4, r5
SHOULDNT_BE_SET
l.sfles r4, r5
SHOULD_BE_SET
l.sflts r4, r5
SHOULD_BE_SET
.endm
.macro SHOULD_BE_GREATER_THAN_SIGNED a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
l.sfgts r4, r5
SHOULD_BE_SET
l.sfges r4, r5
SHOULD_BE_SET
l.sfles r4, r5
SHOULDNT_BE_SET
l.sflts r4, r5
SHOULDNT_BE_SET
.endm
.macro SHOULD_BE_LESS_THAN_UNSIGNED a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
l.sfgtu r4, r5
SHOULDNT_BE_SET
l.sfgeu r4, r5
SHOULDNT_BE_SET
l.sfleu r4, r5
SHOULD_BE_SET
l.sfltu r4, r5
SHOULD_BE_SET
.endm
.macro SHOULD_BE_GREATER_THAN_UNSIGNED a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
l.sfgtu r4, r5
SHOULD_BE_SET
l.sfgeu r4, r5
SHOULD_BE_SET
l.sfleu r4, r5
SHOULDNT_BE_SET
l.sfltu r4, r5
SHOULDNT_BE_SET
.endm
.macro SHOULD_BE_EQUAL a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULD_BE_SET
l.sfne r4, r5
SHOULDNT_BE_SET
/* Signed tests. */
l.sfgts r4, r5
SHOULDNT_BE_SET
l.sfges r4, r5
SHOULD_BE_SET
l.sfles r4, r5
SHOULD_BE_SET
l.sflts r4, r5
SHOULDNT_BE_SET
/* Unsigned tests. */
l.sfgtu r4, r5
SHOULDNT_BE_SET
l.sfgeu r4, r5
SHOULD_BE_SET
l.sfleu r4, r5
SHOULD_BE_SET
l.sfltu r4, r5
SHOULDNT_BE_SET
.endm
.macro SHOULDNT_BE_EQUAL a, b
MOVE_TO_R4_R5_AND_REPORT \a , \b
l.sfeq r4, r5
SHOULDNT_BE_SET
l.sfne r4, r5
SHOULD_BE_SET
.endm
.macro SHOULD_BE_EQUAL_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULD_BE_SET
l.sfnei r4, \b
SHOULDNT_BE_SET
/* Signed tests. */
l.sfgtsi r4, \b
SHOULDNT_BE_SET
l.sfgesi r4, \b
SHOULD_BE_SET
l.sflesi r4, \b
SHOULD_BE_SET
l.sfltsi r4, \b
SHOULDNT_BE_SET
/* Unsigned tests. */
l.sfgtui r4, \b
SHOULDNT_BE_SET
l.sfgeui r4, \b
SHOULD_BE_SET
l.sfleui r4, \b
SHOULD_BE_SET
l.sfltui r4, \b
SHOULDNT_BE_SET
.endm
.macro SHOULDNT_BE_EQUAL_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
.endm
.macro SHOULD_BE_LESS_THAN_SIGNED_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
l.sfgtsi r4, \b
SHOULDNT_BE_SET
l.sfgesi r4, \b
SHOULDNT_BE_SET
l.sflesi r4, \b
SHOULD_BE_SET
l.sfltsi r4, \b
SHOULD_BE_SET
.endm
.macro SHOULD_BE_GREATER_THAN_SIGNED_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
l.sfgtsi r4, \b
SHOULD_BE_SET
l.sfgesi r4, \b
SHOULD_BE_SET
l.sflesi r4, \b
SHOULDNT_BE_SET
l.sfltsi r4, \b
SHOULDNT_BE_SET
.endm
.macro SHOULD_BE_LESS_THAN_UNSIGNED_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
l.sfgtui r4, \b
SHOULDNT_BE_SET
l.sfgeui r4, \b
SHOULDNT_BE_SET
l.sfleui r4, \b
SHOULD_BE_SET
l.sfltui r4, \b
SHOULD_BE_SET
.endm
.macro SHOULD_BE_GREATER_THAN_UNSIGNED_I a, b
MOVE_TO_R4_AND_REPORT_I \a, \b
l.sfeqi r4, \b
SHOULDNT_BE_SET
l.sfnei r4, \b
SHOULD_BE_SET
l.sfgtui r4, \b
SHOULD_BE_SET
l.sfgeui r4, \b
SHOULD_BE_SET
l.sfleui r4, \b
SHOULDNT_BE_SET
l.sfltui r4, \b
SHOULDNT_BE_SET
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Signed tests */
SHOULD_BE_LESS_THAN_SIGNED 0, 1
SHOULD_BE_LESS_THAN_SIGNED MIN1, 0
SHOULD_BE_LESS_THAN_SIGNED INT_MAX_MIN1, INT_MAX
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX_MIN1
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX_MIN1
SHOULD_BE_LESS_THAN_SIGNED -7, -6
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, NEG_INT_MAX_PL1
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, MIN1
SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, 0
SHOULD_BE_GREATER_THAN_SIGNED 1, 0
SHOULD_BE_GREATER_THAN_SIGNED 0, MIN1
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, INT_MAX_MIN1
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX_PL1
SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX_PL1
SHOULD_BE_GREATER_THAN_SIGNED -6, -7
SHOULD_BE_GREATER_THAN_SIGNED NEG_INT_MAX_PL1, NEG_INT_MAX
SHOULD_BE_GREATER_THAN_SIGNED MIN1, NEG_INT_MAX
SHOULD_BE_GREATER_THAN_SIGNED 0, NEG_INT_MAX
/* See the immediate tests below. */
SHOULD_BE_LESS_THAN_SIGNED 0xFFFF7FFF, 0xFFFF8000
/* See the immediate tests below. */
SHOULD_BE_GREATER_THAN_SIGNED 0xFFFF8001, 0xFFFF8000
/* Signed tests, immediate */
SHOULD_BE_LESS_THAN_SIGNED_I 0, 1
SHOULD_BE_LESS_THAN_SIGNED_I -1, 0
SHOULD_BE_LESS_THAN_SIGNED_I -7, -6
SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x7FFF
SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFFFFFF, 0x7FFF
/* 0x8000 gets sign-extended to 0xFFFF8000. */
SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFF7FFF, 0x8000
/* 0x8000 gets sign-extended to 0xFFFF8000. */
SHOULD_BE_GREATER_THAN_SIGNED_I 0xFFFF8001, 0x8000
/* 0x8000 gets sign-extended to 0xFFFF8000. */
SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x8000
/* Unsigned tests */
SHOULD_BE_LESS_THAN_UNSIGNED 0, 1
SHOULD_BE_LESS_THAN_UNSIGNED UINT_MAX_MIN1, UINT_MAX
SHOULD_BE_GREATER_THAN_UNSIGNED 1, 0
SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, UINT_MAX_MIN1
SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, 0
SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000001, 0x80000000
SHOULD_BE_LESS_THAN_UNSIGNED 0x80000000, 0x80000001
SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000000, 0x7fffffff
SHOULD_BE_LESS_THAN_UNSIGNED 0x7fffffff, 0x80000000
SHOULD_BE_GREATER_THAN_UNSIGNED 0x7fffffff, 0x7ffffffe
SHOULD_BE_LESS_THAN_UNSIGNED 0x7ffffffe, 0x7fffffff
SHOULD_BE_LESS_THAN_UNSIGNED 0x2024fae0, 0xfef03220
/* Unsigned tests, immediate */
SHOULD_BE_LESS_THAN_UNSIGNED_I 0, 1
SHOULD_BE_GREATER_THAN_UNSIGNED_I 1, 0
SHOULD_BE_LESS_THAN_UNSIGNED_I SHRT_MAX - 1, SHRT_MAX
SHOULD_BE_GREATER_THAN_UNSIGNED_I SHRT_MAX , SHRT_MAX - 1
/* The sign extension produces unexpected results here. */
/* 0xFFFF gets sign-extended to 0xFFFFFFFF. */
SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFFFFFF - 1, 0xFFFF
/* 0x8000 gets sign-extended to 0xFFFF8000. */
SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFF7FFF, 0x8000
/* Equal tests. */
SHOULD_BE_EQUAL 0, 0
SHOULD_BE_EQUAL UINT_MAX, UINT_MAX
SHOULD_BE_EQUAL MIN1, UINT_MAX
SHOULD_BE_EQUAL INT_MAX, INT_MAX
SHOULD_BE_EQUAL NEG_INT_MAX, NEG_INT_MAX
/* Equal tests, immediate. Test the 16-to-32-bit sign extension. */
SHOULD_BE_EQUAL_I 0, 0
SHOULD_BE_EQUAL_I 0x00007FFF, 0x7FFF
SHOULD_BE_EQUAL_I 0xFFFF8000, 0x8000
SHOULD_BE_EQUAL_I 0xFFFFFFFF, 0xFFFF
/* Non-equal tests. */
SHOULDNT_BE_EQUAL 0, 1
SHOULDNT_BE_EQUAL UINT_MAX, INT_MAX
SHOULDNT_BE_EQUAL UINT_MAX, NEG_INT_MAX
SHOULDNT_BE_EQUAL MIN1, NEG_INT_MAX_PL1
SHOULDNT_BE_EQUAL INT_MAX, NEG_INT_MAX
SHOULDNT_BE_EQUAL NEG_INT_MAX_PL1, UINT_MAX_MIN1
/* Non-equal tests, immediate. Test the 16-to-32-bit sign
extension. */
SHOULDNT_BE_EQUAL_I 0x00008000, 0x8000
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
failed:
EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR
|
stsp/binutils-ia16
| 3,423
|
sim/testsuite/or1k/fpu.S
|
/* Tests some basic fpu instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00007ab7);\n
# output: report(0xffffd8f0);\n
# output: report(0x46f56e00);\n
# output: report(0xc61c4000);\n
# output: report(0x00007ab7);\n
# output: report(0xffffd8f0);\n
# output: \n
# output: report(0xc0490e56);\n
# output: report(0xfffffffd);\n
# output: \n
# output: report(0x4e6b4bbb);\n
# output: \n
# output: report(0xbdc0be40);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: WARNING: ignoring fpu error caught in fast mode.\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Floating point exception. */
.org 0xd00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots. But we don't have those in this test. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw -4(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test lf.itof.s int to float conversion. Setting up:
* r10 31415.0f
* r12 -10000.0f
*/
l.ori r11, r0, 31415
l.ori r13, r0, -10000
l.movhi r15, 0xffff
l.or r13, r13, r15
REPORT_REG_TO_CONSOLE r11
REPORT_REG_TO_CONSOLE r13
lf.itof.s r10, r11
lf.itof.s r12, r13
REPORT_REG_TO_CONSOLE r10
REPORT_REG_TO_CONSOLE r12
/* Test lf.ftoi.s float to int conversion. */
lf.ftoi.s r11, r10
lf.ftoi.s r13, r12
REPORT_REG_TO_CONSOLE r11
REPORT_REG_TO_CONSOLE r13
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.div.s divide 31415 by -1000 to get -pi. Setting up:
* r8 -3.1415f
*/
lf.div.s r8, r10, r12
REPORT_REG_TO_CONSOLE r8
lf.ftoi.s r11, r8
REPORT_REG_TO_CONSOLE r11
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.mul.s multiply -pi x -10000 x 31415. Setting up:
* r6 986902225
*/
lf.mul.s r6, r8, r12
lf.mul.s r6, r6, r10
REPORT_REG_TO_CONSOLE r6
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.rem.s remainder of 986902225 / -pi. */
lf.rem.s r2, r6, r8
REPORT_REG_TO_CONSOLE r2
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.sfge.s set flag if r6 >= r10. */
lf.sfge.s r6, r10
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
/* Test raising an exception by dividing by 0. */
MOVE_FROM_SPR r2, SPR_FPCSR
l.ori r2, r2, 0x1
MOVE_TO_SPR SPR_FPCSR, r2
div0: lf.div.s r2, r8, r0
REPORT_EXCEPTION div0
PRINT_NEWLINE_TO_CONSOLE
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 3,346
|
sim/testsuite/or1k/jump.S
|
/* Tests the jump instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x48000000);\n
# output: report(0x00000005);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x48000000);\n
# output: report(0x00000009);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x44000000);\n
# output: report(0x00000005);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x44000000);\n
# output: report(0x00000009);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
/* Tests a jump instruction using a register destination.
Checks whether the jump succeeds, or whether an exception is triggered
(but not if the right exception was triggered yet).
We manually construct the opcode, to allow us to force R9 into the
destination field, to test exception handling. Usually the assembler
would prevent this.
Do not specify R31 as the register to use for the jump, as it's used
internally. */
.macro TEST_JUMP opcode_value dest_register_number alignment_offset
REPORT_IMMEDIATE_TO_CONSOLE \opcode_value
REPORT_IMMEDIATE_TO_CONSOLE \dest_register_number
REPORT_IMMEDIATE_TO_CONSOLE \alignment_offset
LOAD_IMMEDIATE r\dest_register_number, 51f + \alignment_offset
/* Generate the jump opcode. */
\@1$: OR1K_DELAYED_NOP \
(.word ( \opcode_value | (\dest_register_number << 11) ))
/* If the jump failed, we land here. */
REPORT_IMMEDIATE_TO_CONSOLE 1
OR1K_DELAYED_NOP (l.j 52f)
/* If the jump succeeds, we land here. */
51: REPORT_IMMEDIATE_TO_CONSOLE 0
52: REPORT_EXCEPTION \@1$
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.jalr (jump and link register) */
TEST_JUMP 0x48000000, 5, 0
/* TODO: The sim does not support unaligned memory access yet.
TEST_JUMP 0x48000000, 5, 1
TEST_JUMP 0x48000000, 5, 2
TEST_JUMP 0x48000000, 5, 3
*/
/* Test with link register as the destination. This is not
allowed. */
TEST_JUMP 0x48000000, 9, 0
/* Test l.jr (jump register) */
TEST_JUMP 0x44000000, 5, 0
/* TODO: The sim does not support unaligned memory access yet.
TEST_JUMP 0x44000000, 5, 1
TEST_JUMP 0x44000000, 5, 2
TEST_JUMP 0x44000000, 5, 3
*/
/* Test with link register as the destination. */
TEST_JUMP 0x44000000, 9, 0
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 20,517
|
sim/testsuite/or1k/add.S
|
/* Tests instructions l.add, l.addc, l.addi and l.addic.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0xc0000000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xbfffffff);\n
# output: report(0xbfffffff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xbfffffff);\n
# output: report(0xbfffffff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0xc0000000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0xbfffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xbfffffff);\n
# output: report(0xbfffffff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xbfffffff);\n
# output: report(0xbfffffff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000fffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fff8000);\n
# output: report(0x00007fff);\n
# output: report(0x7fffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80008000);\n
# output: report(0x00008000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000fffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000fffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fff8000);\n
# output: report(0x00007fff);\n
# output: report(0x7fffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fff8000);\n
# output: report(0x00007fff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x0000ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80008000);\n
# output: report(0x00008000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x7fffc000);\n
# output: report(0x00003fff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000fffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x0000ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80007fff);\n
# output: report(0x00008000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Range exception. */
.org 0xb00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots. But we don't have those in this test. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw 0(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.add */
/* Add two small positive numbers */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 1, 2
/* The carry flag should be ignored. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.add, 1, 2
/* Add two small negative numbers, which should set the carry flag
but not the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1, -2
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \
0x3fffffff
/* Add two large positive numbers. Should set the overflow, but
not the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \
0x40000000
/* Add two quite large negative numbers. Should set the carry, but
not the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1073741824, \
-1073741824 /* -1073741824 = 0xC0000000 */
/* Add two large negative numbers. Should set both the overflow
and carry flags. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, \
0xbfffffff
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, \
0x40000000
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xffffffff, \
0xfffffffe
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, \
0xbfffffff
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.addc */
/* Add two small positive numbers */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 1, 2
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1, -2
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \
0x3fffffff
/* Add two quite large positive numbers with a carry in. Should
set the overflow but not the carry flag. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, \
0x3fffffff
/* Add two large positive numbers. Should set the overflow, but
not the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \
0x40000000
/* Add the largest unsigned value to zero with a carry. This
potentially can break a simplistic test for carry that does not
consider the carry flag properly. Do it both ways around. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1, 0
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0, -1
/* Add two quite large negative numbers. Should set the carry, but
not the overflow flag. Here -1073741824 is 0xC0000000. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741824, \
-1073741824
/* Add two quite large negative numbers that would overflow, with a
carry that just avoids the overflow. Should set the carry, but
not the overflow flag. Here -1073741824 is 0xC0000000 and
-1073741825 is 0xBFFFFFFF. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1073741824, \
-1073741825
/* Add two large negative numbers. Should set both the overflow
and carry flags. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741825, \
-1073741825
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception, even when
it is the carry that causes the overflow. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, \
0x40000000
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, \
0x3fffffff
/* Check that a carry alone does not cause a RANGE Exception, even
when it is the carry that causes the overflow. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xffffffff, \
0xfffffffe
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x00000000, \
0xffffffff
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xbfffffff, \
0xbfffffff
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.addi */
/* Add two small positive numbers */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 1, 2
/* Check carry in is ignored. */
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addi, 1, 2
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, \
0xfffe
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fff8000, \
0x7fff
/* Add two large positive numbers. Should set the overflow, but
not the carry flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, \
0x4000
/* Add two quite large negative numbers. Should set the carry, but
not the overflow flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80008000, \
0x8000
/* Add two large negative numbers. Should set both the overflow
and carry flags. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, \
0x8000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, \
0x4000
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, \
0xfffe
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, \
0x8000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.addi */
/* Add two small positive numbers */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 1, 2
/* Add two small negative numbers. Sets the carry flag but not the
overflow flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, \
0xfffe
/* Add two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fff8000, \
0x7fff
/* Add two quite large positive numbers with a carry in. Should
set the overflow but not the carry flag. */
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fff8000, 0x7fff
/* Add two large positive numbers. Should set the overflow, but
not the carry flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, \
0x4000
/* Add the largest unsigned value to zero with a carry. This
potentially can break a simplistic test for carry that does not
consider the carry flag properly. Do it both ways around. */
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0xffffffff, 0x0000
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff
/* Add two quite large negative numbers. Should set the carry, but
not the overflow flag. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80008000, \
0x8000
/* Add two quite large negative numbers that would overflow, with a
carry that just avoids the overflow. This should set the carry,
but not the overflow flag. */
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x80007fff, 0x8000
/* Add two large negative numbers. Should set both the overflow
and carry flags. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, \
0x8000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception, even when
it is the carry that causes the overflow. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, \
0x4000
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fffc000, 0x3fff
/* Check that a carry alone does not cause a RANGE Exception, even
when it is the carry that causes the overflow. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, \
0xfffe
TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, \
0x8000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 9,141
|
sim/testsuite/or1k/basic.S
|
/* Tests some basic CPU instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0xffff0012);\n
# output: report(0x12352af7);\n
# output: report(0x7ffffffe);\n
# output: report(0xffffa5a7);\n
# output: report(0x000fffff);\n
# output: report(0x00002800);\n
# output: report(0x00000009);\n
# output: report(0xdeaddead);\n
# output: report(0xffff0000);\n
# output: report(0x12345678);\n
# output: report(0xabcdf0bd);\n
# output: exit(0)\n
#include "or1k-asm-test-env.h"
#define FIRST_RAM_ADDR 0x00000000
STANDARD_TEST_HEADER
/* Early test begin. */
/* Do this test upfront, as it modifies STACK_POINTER_R1. */
l.addi r1 , r0 , 0x1
l.addi r2 , r1 , 0x2
l.addi r3 , r2 , 0x4
l.addi r4 , r3 , 0x8
l.addi r5 , r4 , 0x10
l.addi r6 , r5 , 0x20
l.addi r7 , r6 , 0x40
l.addi r8 , r7 , 0x80
l.addi r9 , r8 , 0x100
l.addi r10, r9 , 0x200
l.addi r11, r10, 0x400
l.addi r12, r11, 0x800
l.addi r13, r12, 0x1000
l.addi r14, r13, 0x2000
l.addi r15, r14, 0x4000
l.addi r16, r15, 0x8000
l.sub r31, r0 , r1
l.sub r30, r31, r2
l.sub r29, r30, r3
l.sub r28, r29, r4
l.sub r27, r28, r5
l.sub r26, r27, r6
l.sub r25, r26, r7
l.sub r24, r25, r8
l.sub r23, r24, r9
l.sub r22, r23, r10
l.sub r21, r22, r11
l.sub r20, r21, r12
l.sub r19, r20, r13
l.sub r18, r19, r14
l.sub r17, r18, r15
l.sub r16, r17, r16
/* We cannot use REPORT_REG_TO_CONSOLE here, as the stack is not
set up yet. */
MOVE_REG NOP_REPORT_R3, r16
REPORT_TO_CONSOLE /* Should be 0xffff0012 */
/* Early test end. */
STANDARD_TEST_BODY
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Read and write from RAM. */
LOAD_IMMEDIATE r31, FIRST_RAM_ADDR
l.sw 0(r31), r16
l.movhi r3,0x1234
l.ori r3,r3,0x5678
l.sw 4(r31),r3
l.lbz r4,4(r31)
l.add r8,r8,r4
l.sb 11(r31),r4
l.lbz r4,5(r31)
l.add r8,r8,r4
l.sb 10(r31),r4
l.lbz r4,6(r31)
l.add r8,r8,r4
l.sb 9(r31),r4
l.lbz r4,7(r31)
l.add r8,r8,r4
l.sb 8(r31),r4
l.lbs r4,8(r31)
l.add r8,r8,r4
l.sb 7(r31),r4
l.lbs r4,9(r31)
l.add r8,r8,r4
l.sb 6(r31),r4
l.lbs r4,10(r31)
l.add r8,r8,r4
l.sb 5(r31),r4
l.lbs r4,11(r31)
l.add r8,r8,r4
l.sb 4(r31),r4
l.lhz r4,4(r31)
l.add r8,r8,r4
l.sh 10(r31),r4
l.lhz r4,6(r31)
l.add r8,r8,r4
l.sh 8(r31),r4
l.lhs r4,8(r31)
l.add r8,r8,r4
l.sh 6(r31),r4
l.lhs r4,10(r31)
l.add r8,r8,r4
l.sh 4(r31),r4
l.lwz r4,4(r31)
l.add r8,r8,r4
REPORT_REG_TO_CONSOLE r8 /* Should be 0x12352af7 */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test arithmetic operations. */
l.addi r3,r0,1
l.addi r4,r0,2
l.addi r5,r0,-1
l.addi r6,r0,-1
l.addi r8,r0,0
l.sub r7,r5,r3
l.sub r8,r3,r5
l.add r8,r8,r7
l.div r7,r7,r4
l.add r9,r3,r4
l.mul r7,r9,r7
l.divu r7,r7,r4
l.add r8,r8,r7
REPORT_REG_TO_CONSOLE r8 /* Should be 0x7ffffffe */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test logical operations. */
l.addi r3,r0,1
l.addi r4,r0,2
l.addi r5,r0,-1
l.addi r6,r0,-1
l.addi r8,r0,0
l.andi r8,r8,1
l.and r8,r8,r3
l.xori r8,r5,0xa5a5
l.xor r8,r8,r5
l.ori r8,r8,2
l.or r8,r8,r4
REPORT_REG_TO_CONSOLE r8 /* Should be 0xffffa5a7 */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test shifting operations. */
l.addi r3,r0,1
l.addi r4,r0,2
l.addi r5,r0,-1
l.addi r6,r0,-1
l.addi r8,r0,0
l.slli r8,r5,6
l.sll r8,r8,r4
l.srli r8,r8,6
l.srl r8,r8,r4
l.srai r8,r8,2
l.sra r8,r8,r4
REPORT_REG_TO_CONSOLE r8 /* Should be 0x000fffff */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test the CPU flag. */
l.addi r3,r0,1
l.addi r4,r0,-2
l.addi r8,r0,0
l.sfeq r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfeq r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfeqi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfeqi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfne r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfne r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfnei r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfnei r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtu r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtu r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtui r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtui r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgeu r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgeu r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgeui r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgeui r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltu r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltu r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltui r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltui r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfleu r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfleu r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfleui r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfleui r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgts r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgts r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtsi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgtsi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfges r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfges r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgesi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfgesi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sflts r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sflts r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltsi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfltsi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfles r3,r3
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sfles r3,r4
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sflesi r3,1
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
l.sflesi r3,-2
l.mfspr r5,r0,17
l.andi r4,r5,0x200
l.add r8,r8,r4
REPORT_REG_TO_CONSOLE r8 /* Should be 0x00002800 */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
/* Test the jump instructions. */
l.addi r8,r0,0
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.j _T1)
)
_T2: OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.jr r9)
)
_T1: OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.jal _T2)
)
l.sfeqi r0,0
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.bf _T3)
)
_T3: l.sfeqi r0,1
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.bf _T4)
)
l.addi r8,r8,1
_T4: l.sfeqi r0,0
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.bnf _T5)
)
l.addi r8,r8,1
_T5: l.sfeqi r0,1
OR1K_DELAYED (
OR1K_INST (l.addi r8,r8,1),
OR1K_INST (l.bnf _T6)
)
l.addi r8,r8,1
_T6: l.movhi r3,hi (_T7)
l.ori r3,r3,lo (_T7)
l.mtspr r0,r3,32
l.mfspr r5,r0,17
l.mtspr r0,r5,64
l.rfe
l.addi r8,r8,1 /* l.rfe should not have a delay slot */
l.addi r8,r8,1
_T7: REPORT_REG_TO_CONSOLE r8 /* Should be 0x000000009 */
l.lwz r9,0(r31)
l.add r8,r9,r8
l.sw 0(r31),r8
l.lwz r9,0(r31)
l.movhi r3,0x4c69
l.ori r3,r3,0xe5f7
l.add r8,r8,r3
REPORT_REG_TO_CONSOLE r8 /* Should be 0xdeaddead */
/* Test l.movhi, on 32-bit implementations it should not
sign-extend anything. */
l.movhi r3, -1
REPORT_REG_TO_CONSOLE r3
/* Test l.cmov */
LOAD_IMMEDIATE r14, 0x12345678
LOAD_IMMEDIATE r15, 0xABCDF0BD
SET_SPR_SR_FLAGS SPR_SR_F, r6, r7
l.cmov r10, r14, r15
CLEAR_SPR_SR_FLAGS SPR_SR_F, r6, r7
l.cmov r11, r14, r15
REPORT_REG_TO_CONSOLE r10
REPORT_REG_TO_CONSOLE r11
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 8,100
|
sim/testsuite/or1k/load.S
|
/* Tests the load and store instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0xdeadbeef);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0xdeadbeef);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xdeadbeef);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0xdeadbeef);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0x000000de);\n
# output: report(0x000000ad);\n
# output: report(0x000000be);\n
# output: report(0x000000ef);\n
# output: report(0x000000ef);\n
# output: report(0x000000be);\n
# output: report(0x000000ad);\n
# output: report(0x000000de);\n
# output: report(0xffffffde);\n
# output: report(0xffffffad);\n
# output: report(0xffffffbe);\n
# output: report(0xffffffef);\n
# output: report(0xffffffef);\n
# output: report(0xffffffbe);\n
# output: report(0xffffffad);\n
# output: report(0xffffffde);\n
# output: report(0x0000dead);\n
# output: report(0x0000beef);\n
# output: report(0x0000beef);\n
# output: report(0x0000dead);\n
# output: report(0xffffdead);\n
# output: report(0xffffbeef);\n
# output: report(0xffffbeef);\n
# output: report(0xffffdead);\n
# output: report(0xa1a2a3a4);\n
# output: report(0xb4b3b2b1);\n
# output: report(0x81828384);\n
# output: report(0x53545152);\n
# output: report(0xa0b0c0d0);\n
# output: report(0xa1b1c1d1);\n
# output: report(0xa3b3c3d3);\n
# output: report(0xa2b2c2d2);\n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
.macro TEST_LW opcode, label, offset
LOAD_IMMEDIATE r5, \label
\opcode r4, \offset(r5)
REPORT_REG_TO_CONSOLE r4
.endm
STANDARD_TEST_ENVIRONMENT
.section .rodata
.balign 4
50: .word 0xdeadbeef
51: .word 0x00000000
52: .word 0x7fffffff
53: .word 0x80000000
54: .word 0xffffffff
.section .data
.balign 4
buffer1: .word 0x00000000
buffer2: .word 0x00000000
buffer3: .word 0x00000000
buffer4: .word 0x00000000
buffer5:
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test instruction l.lws */
/* Load with zero offset. */
TEST_LW l.lws 50b, 0
TEST_LW l.lws 51b, 0
TEST_LW l.lws 52b, 0
TEST_LW l.lws 53b, 0
TEST_LW l.lws 54b, 0
/* Load with positive offset. */
TEST_LW l.lws 50b, 4
TEST_LW l.lws 50b, 8
TEST_LW l.lws 50b, 12
TEST_LW l.lws 50b, 16
/* Load with negative offset. */
TEST_LW l.lws 54b, -16
TEST_LW l.lws 54b, -12
TEST_LW l.lws 54b, -8
TEST_LW l.lws 54b, -4
/* TODO: add here test cases to cover unaligned memory accesses
with l.lws. */
/* Test instruction l.lwz */
/* Load with zero offset. */
TEST_LW l.lwz 50b, 0
TEST_LW l.lwz 51b, 0
TEST_LW l.lwz 52b, 0
TEST_LW l.lwz 53b, 0
TEST_LW l.lwz 54b, 0
/* Load with positive offset. */
TEST_LW l.lwz 50b, 4
TEST_LW l.lwz 50b, 8
TEST_LW l.lwz 50b, 12
TEST_LW l.lwz 50b, 16
/* Load with negative offset. */
TEST_LW l.lwz 54b, -16
TEST_LW l.lwz 54b, -12
TEST_LW l.lwz 54b, -8
TEST_LW l.lwz 54b, -4
/* TODO: add here test cases to cover unaligned memory accesses
with l.lwz. */
/* Test instruction l.lbz */
/* Read data at label 50, forwards, byte by byte. */
LOAD_IMMEDIATE r5, 50b
l.lbz r4, 0(r5)
REPORT_REG_TO_CONSOLE r4
l.lbz r4, 1(r5)
REPORT_REG_TO_CONSOLE r4
l.lbz r4, 2(r5)
REPORT_REG_TO_CONSOLE r4
l.lbz r4, 3(r5)
REPORT_REG_TO_CONSOLE r4
/* Read data at label 50, backwards, byte by byte. */
LOAD_IMMEDIATE r31, 51b
l.lbz r3, -1(r31)
REPORT_REG_TO_CONSOLE r3
l.lbz r3, -2(r31)
REPORT_REG_TO_CONSOLE r3
l.lbz r3, -3(r31)
REPORT_REG_TO_CONSOLE r3
l.lbz r3, -4(r31)
REPORT_REG_TO_CONSOLE r3
/* Test instruction l.lbs */
/* Read data at label 50, forwards, byte by byte. */
LOAD_IMMEDIATE r5, 50b
l.lbs r4, 0(r5)
REPORT_REG_TO_CONSOLE r4
l.lbs r4, 1(r5)
REPORT_REG_TO_CONSOLE r4
l.lbs r4, 2(r5)
REPORT_REG_TO_CONSOLE r4
l.lbs r4, 3(r5)
REPORT_REG_TO_CONSOLE r4
/* Read data at label 50, backwards, byte by byte. */
LOAD_IMMEDIATE r31, 51b
l.lbs r3, -1(r31)
REPORT_REG_TO_CONSOLE r3
l.lbs r3, -2(r31)
REPORT_REG_TO_CONSOLE r3
l.lbs r3, -3(r31)
REPORT_REG_TO_CONSOLE r3
l.lbs r3, -4(r31)
REPORT_REG_TO_CONSOLE r3
/* Test instruction l.lhz */
/* Read data at label 50, forwards, half-word by half-word. */
LOAD_IMMEDIATE r5, 50b
l.lhz r4, 0(r5)
REPORT_REG_TO_CONSOLE r4
l.lhz r4, 2(r5)
REPORT_REG_TO_CONSOLE r4
/* Read data at label 50, backwards, half-word by half-word. */
LOAD_IMMEDIATE r31, 51b
l.lhz r3, -2(r31)
REPORT_REG_TO_CONSOLE r3
l.lhz r3, -4(r31)
REPORT_REG_TO_CONSOLE r3
/* TODO: add here test cases to cover unaligned memory accesses
with l.lhz. */
/* Test instruction l.lhs */
/* Read data at label 50, forwards, half-word by half-word. */
LOAD_IMMEDIATE r5, 50b
l.lhs r4, 0(r5)
REPORT_REG_TO_CONSOLE r4
l.lhs r4, 2(r5)
REPORT_REG_TO_CONSOLE r4
/* Read data at label 50, backwards, half-word by half-word. */
LOAD_IMMEDIATE r31, 51b
l.lhs r3, -2(r31)
REPORT_REG_TO_CONSOLE r3
l.lhs r3, -4(r31)
REPORT_REG_TO_CONSOLE r3
/* TODO: add here test cases to cover unaligned memory accesses
with l.lhs. */
/* Test instruction l.sb */
/* Write 32-bits forwards, byte-to-byte. */
LOAD_IMMEDIATE r5, buffer1
LOAD_IMMEDIATE r10, 0xA1
LOAD_IMMEDIATE r11, 0xA2
LOAD_IMMEDIATE r12, 0xA3
LOAD_IMMEDIATE r13, 0xA4
l.sb 0(r5), r10
l.sb 1(r5), r11
l.sb 2(r5), r12
l.sb 3(r5), r13
l.lwz r3, 0(r5)
REPORT_REG_TO_CONSOLE r3
/* Write 32-bits backwards, byte-to-byte. */
LOAD_IMMEDIATE r6, buffer2
LOAD_IMMEDIATE r10, 0xB1
LOAD_IMMEDIATE r11, 0xB2
LOAD_IMMEDIATE r12, 0xB3
LOAD_IMMEDIATE r13, 0xB4
l.sb -1(r6), r10
l.sb -2(r6), r11
l.sb -3(r6), r12
l.sb -4(r6), r13
l.lwz r3, 0(r5)
REPORT_REG_TO_CONSOLE r3
/* TODO: add here test cases to cover unaligned memory accesses
with l.sb. */
/* Test instruction l.sh */
/* Write 32-bits forwards, one half-word at a time. */
LOAD_IMMEDIATE r5, buffer1
LOAD_IMMEDIATE r10, 0x8182
LOAD_IMMEDIATE r11, 0x8384
l.sh 0(r5), r10
l.sh 2(r5), r11
l.lwz r3, 0(r5)
REPORT_REG_TO_CONSOLE r3
/* Write 32-bits backwards, one half-word at a time. */
LOAD_IMMEDIATE r6, buffer2
LOAD_IMMEDIATE r10, 0x5152
LOAD_IMMEDIATE r11, 0x5354
l.sh -2(r6), r10
l.sh -4(r6), r11
l.lwz r3, 0(r5)
REPORT_REG_TO_CONSOLE r3
/* TODO: add here test cases to cover unaligned memory accesses
with l.sh. */
/* Test instruction l.sw */
LOAD_IMMEDIATE r5, buffer1
LOAD_IMMEDIATE r6, buffer5
LOAD_IMMEDIATE r10, 0xA0B0C0D0
LOAD_IMMEDIATE r11, 0xA1B1C1D1
LOAD_IMMEDIATE r12, 0xA2B2C2D2
LOAD_IMMEDIATE r13, 0xA3B3C3D3
l.sw 0(r5), r10
l.sw 4(r5), r11
l.sw -4(r6), r12
l.sw -8(r6), r13
TEST_LW l.lwz buffer1, 0
TEST_LW l.lwz buffer2, 0
TEST_LW l.lwz buffer3, 0
TEST_LW l.lwz buffer4, 0
/* TODO: add here test cases to cover unaligned memory accesses
with l.sw. */
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 15,484
|
sim/testsuite/or1k/shift.S
|
/* Tests the shift instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0x671e1f06);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x38f0f830);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0f830000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x80000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0x671e1f06);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00002224);\n
# output: report(0x38f0f830);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00f789f0);\n
# output: report(0x0f830000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0x671e1f06);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x38f0f830);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0f830000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x80000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0x671e1f06);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000024);\n
# output: report(0x38f0f830);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000030);\n
# output: report(0x0f830000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000003f);\n
# output: report(0x80000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0xfb38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0xffffb38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0xffffffff);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000001);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000004);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000010);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000001f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00002224);\n
# output: report(0xfb38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00f789f0);\n
# output: report(0xffffb38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000021);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00002224);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00f789f0);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0xfb38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0xffffb38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0xffffffff);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000001);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000004);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000010);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000001f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000024);\n
# output: report(0xfb38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000030);\n
# output: report(0xffffb38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000003f);\n
# output: report(0xffffffff);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000021);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000024);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000030);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000003f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0x59c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x0b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0000b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000001);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000004);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000010);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000001f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0x59c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00002224);\n
# output: report(0x0b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00f789f0);\n
# output: report(0x0000b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000021);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00002224);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00f789f0);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0x59c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x0b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0000b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000001);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000004);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000010);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000001f);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0x59c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000024);\n
# output: report(0x0b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000030);\n
# output: report(0x0000b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000003f);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000021);\n
# output: report(0x2638783e);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000024);\n
# output: report(0x04c70f07);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000030);\n
# output: report(0x00004c70);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x0000003f);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
.macro TEST_SHIFT opcode, op1, op2
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
REPORT_REG_TO_CONSOLE r5
REPORT_REG_TO_CONSOLE r6
\opcode r4, r5, r6
CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
.macro TEST_SHIFT_I opcode, op1, op2
LOAD_IMMEDIATE r5, \op1
REPORT_REG_TO_CONSOLE r5
REPORT_IMMEDIATE_TO_CONSOLE \op2
\opcode r4, r5, \op2
CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Always set OVE. We should never trigger an exception, even if
this bit is set. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.sll */
/* Shift left by zero. */
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000000
/* Shift left by amounts in the 1-31 range. */
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000001
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000004
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000010
TEST_SHIFT l.sll, 0xb38f0f83, 0x0000001f
/* Shift left by larger amounts - should be masked. */
TEST_SHIFT l.sll, 0xb38f0f83, 0x00000021
TEST_SHIFT l.sll, 0xb38f0f83, 0x00002224
TEST_SHIFT l.sll, 0xb38f0f83, 0x00f789f0
TEST_SHIFT l.sll, 0xb38f0f83, 0xffffffff
/* Test l.slli */
/* Shift left by zero. */
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0000
/* Shift left by amounts in the 1-31 range. */
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0001
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0004
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0010
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x001f
/* Shift left by larger amounts - should be masked. */
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0021
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0024
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0030
TEST_SHIFT_I l.slli, 0xb38f0f83, 0x003f
/* Test l.sra */
/* Shift right by zero. */
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000000
/* Shift right by amounts in the 1-31 range. */
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000001
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000004
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000010
TEST_SHIFT l.sra, 0xb38f0f83, 0x0000001f
TEST_SHIFT l.sra, 0x4c70f07c, 0x00000001
TEST_SHIFT l.sra, 0x4c70f07c, 0x00000004
TEST_SHIFT l.sra, 0x4c70f07c, 0x00000010
TEST_SHIFT l.sra, 0x4c70f07c, 0x0000001f
/* Shift right by larger amounts - should be masked. */
TEST_SHIFT l.sra, 0xb38f0f83, 0x00000021
TEST_SHIFT l.sra, 0xb38f0f83, 0x00002224
TEST_SHIFT l.sra, 0xb38f0f83, 0x00f789f0
TEST_SHIFT l.sra, 0xb38f0f83, 0xffffffff
TEST_SHIFT l.sra, 0x4c70f07c, 0x00000021
TEST_SHIFT l.sra, 0x4c70f07c, 0x00002224
TEST_SHIFT l.sra, 0x4c70f07c, 0x00f789f0
TEST_SHIFT l.sra, 0x4c70f07c, 0xffffffff
/* Test l.srai */
/* Shift right by zero. */
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0000
/* Shift right by amounts in the 1-31 range. */
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0001
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0004
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0010
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x001f
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0001
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0004
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0010
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x001f
/* Shift right by larger amounts - should be masked. */
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0021
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0024
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0030
TEST_SHIFT_I l.srai, 0xb38f0f83, 0x003f
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0021
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0024
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0030
TEST_SHIFT_I l.srai, 0x4c70f07c, 0x003f
/* Test l.srl */
/* Shift right by zero. */
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000000
/* Shift right by amounts in the 1-31 range. */
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000001
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000004
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000010
TEST_SHIFT l.srl, 0xb38f0f83, 0x0000001f
TEST_SHIFT l.srl, 0x4c70f07c, 0x00000001
TEST_SHIFT l.srl, 0x4c70f07c, 0x00000004
TEST_SHIFT l.srl, 0x4c70f07c, 0x00000010
TEST_SHIFT l.srl, 0x4c70f07c, 0x0000001f
/* Shift right by larger amounts - should be masked. */
TEST_SHIFT l.srl, 0xb38f0f83, 0x00000021
TEST_SHIFT l.srl, 0xb38f0f83, 0x00002224
TEST_SHIFT l.srl, 0xb38f0f83, 0x00f789f0
TEST_SHIFT l.srl, 0xb38f0f83, 0xffffffff
TEST_SHIFT l.srl, 0x4c70f07c, 0x00000021
TEST_SHIFT l.srl, 0x4c70f07c, 0x00002224
TEST_SHIFT l.srl, 0x4c70f07c, 0x00f789f0
TEST_SHIFT l.srl, 0x4c70f07c, 0xffffffff
/* Test l.srli */
/* Shift right by zero. */
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0000
/* Shift right by amounts in the 1-31 range. */
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0001
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0004
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0010
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x001f
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0001
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0004
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0010
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x001f
/* Shift right by larger amounts - should be masked. */
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0021
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0024
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0030
TEST_SHIFT_I l.srli, 0xb38f0f83, 0x003f
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0021
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0024
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0030
TEST_SHIFT_I l.srli, 0x4c70f07c, 0x003f
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 27,149
|
sim/testsuite/or1k/mac.S
|
/* Tests the MAC instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x40000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000006);\n
# output: report(0x80000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7ffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000005);\n
# output: report(0xffffffff);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x40000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000006);\n
# output: report(0x80000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7ffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000005);\n
# output: report(0xffffffff);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000006);\n
# output: report(0x7ffffffe);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x7ffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x0000000c);\n
# output: report(0x00000005);\n
# output: report(0xfffffffa);\n
# output: report(0x00000006);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff9);\n
# output: report(0xfffffff9);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x80000000);\n
# output: report(0x80000006);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0xfffffffa);\n
# output: report(0x3fffffff);\n
# output: report(0xfffffffa);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff4);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0xffffffff);\n
# output: report(0x80000002);\n
# output: report(0xffffffff);\n
# output: report(0x80000004);\n
# output: report(0x00000000);\n
# output: report(0x00000004);\n
# output: report(0x7ffffffe);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x80000001);\n
# output: report(0xffffffff);\n
# output: report(0x00000004);\n
# output: report(0xfffffffe);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0xffffffff);\n
# output: report(0xfffffff9);\n
# output: report(0x00000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x0000000c);\n
# output: report(0x00000001);\n
# output: report(0x00000005);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000005);\n
# output: report(0x80000000);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x80000006);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x7fffffff);\n
# output: report(0xffffffff);\n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0x80000000);\n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
.macro TEST_MACRC mac_hi, mac_lo, op1, op2
LOAD_IMMEDIATE r2, \mac_hi
MOVE_TO_SPR SPR_MACHI, r2
LOAD_IMMEDIATE r2, \mac_lo
MOVE_TO_SPR SPR_MACLO, r2
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
l.mac r5, r6
l.macrc r3
REPORT_REG_TO_CONSOLE r3
.endm
.macro TEST_MAC mac_hi, mac_lo, op1, op2
LOAD_IMMEDIATE r2, \mac_hi
MOVE_TO_SPR SPR_MACHI, r2
LOAD_IMMEDIATE r2, \mac_lo
MOVE_TO_SPR SPR_MACLO, r2
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
l.mac r5, r6
MOVE_FROM_SPR r3, SPR_MACHI
REPORT_REG_TO_CONSOLE r3
MOVE_FROM_SPR r3, SPR_MACLO
REPORT_REG_TO_CONSOLE r3
.endm
.macro TEST_MACI mac_hi, mac_lo, op1, op2_immediate
LOAD_IMMEDIATE r2, \mac_hi
MOVE_TO_SPR SPR_MACHI, r2
LOAD_IMMEDIATE r2, \mac_lo
MOVE_TO_SPR SPR_MACLO, r2
LOAD_IMMEDIATE r5, \op1
l.maci r5, \op2_immediate
MOVE_FROM_SPR r3, SPR_MACHI
REPORT_REG_TO_CONSOLE r3
MOVE_FROM_SPR r3, SPR_MACLO
REPORT_REG_TO_CONSOLE r3
.endm
.macro TEST_MSB mac_hi, mac_lo, op1, op2
LOAD_IMMEDIATE r2, \mac_hi
MOVE_TO_SPR SPR_MACHI, r2
LOAD_IMMEDIATE r2, \mac_lo
MOVE_TO_SPR SPR_MACLO, r2
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
l.msb r5, r6
MOVE_FROM_SPR r3, SPR_MACHI
REPORT_REG_TO_CONSOLE r3
MOVE_FROM_SPR r3, SPR_MACLO
REPORT_REG_TO_CONSOLE r3
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test the l.mac instruction. */
/* two small positive numbers */
/* MAC two small positive numbers on a zero total */
TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0x00000003
/* MAC two small positive numbers on a small positive total */
TEST_MAC 0x00000000, 0x00000006, 0x00000002, 0x00000003,
/* MAC two small positive numbers on a moderate positive total */
TEST_MAC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a large positive total */
TEST_MAC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a small negative total */
TEST_MAC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a moderate negative total */
TEST_MAC 0xffffffff, 0x00000000, 0x00000002, 0x00000003
/* MAC two small positive numbers on a large negative total */
TEST_MAC 0x80000000, 0x00000000, 0x00000002, 0x00000003
/* two moderate positive numbers */
/* MAC two moderate positive numbers on a zero total */
TEST_MAC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a small positive total */
TEST_MAC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a moderate positive total */
TEST_MAC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a large positive total */
TEST_MAC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a small negative total */
TEST_MAC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a moderate negative total */
TEST_MAC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a large negative total */
TEST_MAC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
/* two small negative numbers */
/* MAC two small negative numbers on a zero total */
TEST_MAC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd
/* MAC two small negative numbers on a small positive total */
TEST_MAC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
/* MAC two small negative numbers on a small negative total */
TEST_MAC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
/* one small positive and one small negative */
/* MAC one small positive and one small negative number on a zero
total */
TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a small
positive total */
TEST_MAC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a
moderate positive total */
TEST_MAC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a large
positive total */
TEST_MAC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a small
negative total */
TEST_MAC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a
moderate negative total */
TEST_MAC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a large
negative total */
TEST_MAC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd
/* one moderate positive and one moderate negative number */
/* MAC one moderate positive and one moderate negative number on a
zero total */
TEST_MAC 0x00000000, 0x00000000, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
small positive total */
TEST_MAC 0x00000000, 0x00000006, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
moderate positive total */
TEST_MAC 0x00000000, 0x80000000, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
large positive total */
TEST_MAC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
small negative total */
TEST_MAC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
moderate negative total */
TEST_MAC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
large negative total */
TEST_MAC 0x80000000, 0x80000000, 0x00008000, 0xffff0000
/* Test the l.maci instruction. */
/* two small positive numbers */
/* MAC two small positive numbers on a zero total */
TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0x0003
/* MAC two small positive numbers on a small positive total */
TEST_MACI 0x00000000, 0x00000006, 0x00000002, 0x0003
/* MAC two small positive numbers on a moderate positive total */
TEST_MACI 0x00000000, 0xfffffffa, 0x00000002, 0x0003
/* MAC two small positive numbers on a large positive total */
TEST_MACI 0x3fffffff, 0xfffffffa, 0x00000002, 0x0003
/* MAC two small positive numbers on a small negative total */
TEST_MACI 0xffffffff, 0xfffffffa, 0x00000002, 0x0003
/* MAC two small positive numbers on a moderate negative total */
TEST_MACI 0xffffffff, 0x00000000, 0x00000002, 0x0003
/* MAC two small positive numbers on a large negative total */
TEST_MACI 0x80000000, 0x00000000, 0x00000002, 0x0003
/* two moderate positive numbers */
/* MAC two moderate positive numbers on a zero total */
TEST_MACI 0x00000000, 0x00000000, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a small positive total */
TEST_MACI 0x00000000, 0x00000002, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a moderate positive total */
TEST_MACI 0x00000000, 0x80000002, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a large positive total */
TEST_MACI 0x7fffffff, 0x80000001, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a small negative total */
TEST_MACI 0xffffffff, 0xffffffff, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a moderate negative total */
TEST_MACI 0xffffffff, 0x80000002, 0x00010002, 0x7fff
/* MAC two moderate positive numbers on a large negative total */
TEST_MACI 0xfffffffe, 0x80000002, 0x00010002, 0x7fff
/* two small negative numbers */
/* MAC two small negative numbers on a zero total */
TEST_MACI 0x00000000, 0x00000000, 0xfffffffe, 0xfffd
/* MAC two small negative numbers on a small positive total */
TEST_MACI 0x00000000, 0x00000006, 0xfffffffe, 0xfffd
/* MAC two small negative numbers on a small negative total */
TEST_MACI 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffd
/* one small positive and one small negative */
/* MAC one small positive and one small negative number on a zero
total */
TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a small
positive total */
TEST_MACI 0x00000000, 0x0000000c, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a
moderate positive total */
TEST_MACI 0x00000001, 0x00000005, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a large
positive total */
TEST_MACI 0x7fffffff, 0xffffffff, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a small
negative total */
TEST_MACI 0xffffffff, 0xffffffff, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a
moderate negative total */
TEST_MACI 0xffffffff, 0x00000005, 0x00000002, 0xfffd
/* MAC one small positive and one small negative number on a large
negative total */
TEST_MACI 0x80000000, 0x00000006, 0x00000002, 0xfffd
/* one moderate positive and one moderate negative */
/* MAC one moderate positive and one moderate negative number on a
zero total */
TEST_MACI 0x00000000, 0x00000000, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
small positive total */
TEST_MACI 0x00000000, 0x00000006, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
moderate positive total */
TEST_MACI 0x00000000, 0x80000000, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
large positive total */
TEST_MACI 0x7fffffff, 0xffffffff, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
small negative total */
TEST_MACI 0xffffffff, 0xffffffff, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
moderate negative total */
TEST_MACI 0xffffffff, 0x7fffffff, 0x00010000, 0x8000
/* MAC one moderate positive and one moderate negative number on a
large negative total */
TEST_MACI 0x80000000, 0x80000000, 0x00010000, 0x8000
/* Test the l.macrc instruction.
Note that these tests use the same input data as the ones for
l.mac above. The results are the same, but only the low 32-bits
are compared. */
/* two small positive numbers */
/* MAC two small positive numbers on a zero total */
TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0x00000003
/* MAC two small positive numbers on a small positive total */
TEST_MACRC 0x00000000, 0x00000006, 0x00000002, 0x00000003
/* MAC two small positive numbers on a moderate positive total */
TEST_MACRC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a large positive total */
TEST_MACRC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a small negative total */
TEST_MACRC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MAC two small positive numbers on a moderate negative total */
TEST_MACRC 0xffffffff, 0x00000000, 0x00000002, 0x00000003
/* MAC two small positive numbers on a large negative total */
TEST_MACRC 0x80000000, 0x00000000, 0x00000002, 0x00000003
/* two moderate positive numbers */
/* MAC two moderate positive numbers on a zero total */
TEST_MACRC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a small positive total */
TEST_MACRC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a moderate positive total */
TEST_MACRC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a large positive total */
TEST_MACRC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a small negative total */
TEST_MACRC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a moderate negative total */
TEST_MACRC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
/* MAC two moderate positive numbers on a large negative total */
TEST_MACRC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
/* two small negative numbers */
/* MAC two small negative numbers on a zero total */
TEST_MACRC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd
/* MAC two small negative numbers on a small positive total */
TEST_MACRC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
/* MAC two small negative numbers on a small negative total */
TEST_MACRC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
/* one small positive and one small negative number */
/* MAC one small positive and one small negative number on a zero
total */
TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a small
positive total */
TEST_MACRC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a
moderate positive total */
TEST_MACRC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a large
positive total */
TEST_MACRC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a small
negative total */
TEST_MACRC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a
moderate negative total */
TEST_MACRC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd
/* MAC one small positive and one small negative number on a large
negative total */
TEST_MACRC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd
/* one moderate positive and one moderate negative */
/* MAC one moderate positive and one moderate negative number on a
zero total */
TEST_MACRC 0x00000000, 0x00000000, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
small positive total */
TEST_MACRC 0x00000000, 0x00000006, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
moderate positive total */
TEST_MACRC 0x00000000, 0x80000000, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
large positive total */
TEST_MACRC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
small negative total */
TEST_MACRC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
moderate negative total */
TEST_MACRC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000
/* MAC one moderate positive and one moderate negative number on a
large negative total */
TEST_MACRC 0x80000000, 0x80000000, 0x00008000, 0xffff0000
/* Test the l.msb instruction. */
/* MSB two small positive numbers on a zero total */
TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0x00000003
/* MSB two small positive numbers on a small positive total */
TEST_MSB 0x00000000, 0x0000000c, 0x00000002, 0x00000003
/* MSB two small positive numbers on a moderate positive total */
TEST_MSB 0x00000001, 0x00000000, 0x00000002, 0x00000003
/* MSB two small positive numbers on a large positive total */
TEST_MSB 0x40000000, 0x00000000, 0x00000002, 0x00000003
/* MSB two small positive numbers on a small negative total */
TEST_MSB 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
/* MSB two small positive numbers on a moderate negative total */
TEST_MSB 0xffffffff, 0x00000005, 0x00000002, 0x00000003
/* MSB two small positive numbers on a large negative total */
TEST_MSB 0x80000000, 0x00000006, 0x00000002, 0x00000003
/* two moderate positive numbers */
/* MSB two moderate positive numbers on a zero total */
TEST_MSB 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a small positive total */
TEST_MSB 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a moderate positive total */
TEST_MSB 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a large positive total */
TEST_MSB 0x7fffffff, 0x7ffffffd, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a small negative total */
TEST_MSB 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a moderate negative total */
TEST_MSB 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
/* MSB two moderate positive numbers on a large negative total */
TEST_MSB 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
/* two small negative numbers */
/* MSB two small negative numbers on a zero total */
TEST_MSB 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
/* MSB two small negative numbers on a small positive total */
TEST_MSB 0x00000000, 0x0000000c, 0xfffffffe, 0xfffffffd
/* MSB two small negative numbers on a small negative total */
TEST_MSB 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
/* one small positive and one small negative number */
/* MSB one small positive and one small negative number on a zero
total */
TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a small
positive total */
TEST_MSB 0x00000000, 0x00000006, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a
moderate positive total */
TEST_MSB 0x00000000, 0xffffffff, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a large
positive total */
TEST_MSB 0x7fffffff, 0xfffffff9, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a small
negative total */
TEST_MSB 0xffffffff, 0xfffffff9, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a
moderate negative total */
TEST_MSB 0xfffffffe, 0xffffffff, 0x00000002, 0xfffffffd
/* MSB one small positive and one small negative number on a large
negative total */
TEST_MSB 0x80000000, 0x00000000, 0x00000002, 0xfffffffd
/* one moderate positive and one moderate negative number */
/* MSB one moderate positive and one moderate negative number on a
zero total */
TEST_MSB 0x00000000, 0x00000000, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
small positive total */
TEST_MSB 0x00000000, 0x00000006, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
moderate positive total */
TEST_MSB 0x00000000, 0x80000000, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
large positive total */
TEST_MSB 0x7fffffff, 0x7fffffff, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
small negative total */
TEST_MSB 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
moderate negative total */
TEST_MSB 0xfffffffe, 0xffffffff, 0x00008000, 0xffff0000
/* MSB one moderate positive and one moderate negative number on a
large negative total */
TEST_MSB 0x80000000, 0x00000000, 0x00008000, 0xffff0000
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 8,972
|
sim/testsuite/or1k/div.S
|
/* Tests the divide instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x0000000c);\n
# output: report(0x00000003);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000b);\n
# output: report(0x00000003);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0xfffffffd);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff5);\n
# output: report(0xfffffffd);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000003);\n
# output: report(0xfffffffc);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff5);\n
# output: report(0x00000003);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffc);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000b);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000000);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000000);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000003);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000b);\n
# output: report(0x00000003);\n
# output: report(0x00000003);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff5);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000003);\n
# output: report(0x55555551);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff5);\n
# output: report(0x00000003);\n
# output: report(0x55555551);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000b);\n
# output: report(0xfffffffd);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x0000000c);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xfffffff4);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Range exception. */
.org 0xb00
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw 0(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.div */
/* Divide two positive numbers and check rounding. Should set no
flags. */
TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000003 /* 12 / 3 = 4 */
TEST_INST_I32_I32 l.div, 0x0000000b, 0x00000003 /* 11 / 3 = 3 */
/* Divide two negative numbers and check rounding. Should set no
flags. */
TEST_INST_I32_I32 l.div, 0xfffffff4, 0xfffffffd
TEST_INST_I32_I32 l.div, 0xfffffff5, 0xfffffffd
/* Divide a negative number by a positive number and check
rounding. Should set no flags. */
TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000003
TEST_INST_I32_I32 l.div, 0xfffffff5, 0x00000003
/* Divide a positive number by a negative number and check
rounding. Should set no flags. */
TEST_INST_I32_I32 l.div, 0x0000000c, 0xfffffffd
TEST_INST_I32_I32 l.div, 0x0000000b, 0xfffffffd
/* Divide by zero. This will set the overflow flag. */
TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000
TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Divide by zero. This will set the overflow flag and trigger an
exception. */
TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000
TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.divu */
/* Divide two positive numbers and check rounding. Should set no
flags. */
TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000003
TEST_INST_I32_I32 l.divu, 0x0000000b, 0x00000003
/* Divide two numbers that would be negative under 2's complement
and check rounding. Should set no flags. */
TEST_INST_I32_I32 l.divu, 0xfffffff4, 0xfffffffd
TEST_INST_I32_I32 l.divu, 0xfffffff5, 0xfffffffd
/* Divide a number that would be negative under 2's complement by a
number that would be positive under 2's complement and check
rounding. This should set no flags. */
TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000003
TEST_INST_I32_I32 l.divu, 0xfffffff5, 0x00000003
/* Divide a number that would be positive under 2's complement by a
number that would be negative under 2's complement and check
rounding. This should set no flags. */
TEST_INST_I32_I32 l.divu, 0x0000000c, 0xfffffffd
TEST_INST_I32_I32 l.divu, 0x0000000b, 0xfffffffd
/* Divide by zero. This will set the carry flag. */
TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000
TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Divide by zero. This will set the carry flag and trigger an
exception. */
TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000
TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 1,909
|
sim/testsuite/or1k/adrp.S
|
/* Tests the load page address instruction.
Copyright (C) 2019-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00002064);\n
# output: report(0x00012138);\n
# output: report(0x00002000);\n
# output: report(0x00012000);\n
# output: report(0x00002000);\n
# output: report(0x00014000);\n
# output: report(0x00000000);\n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .data
.org 0x10000
.align 4
.type pi, @object
.size pi, 4
pi:
.float 3.14159
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Print out the PC. To compare with that loaded by l.adrp. */
l.jal capture_pc
l.nop
capture_pc:
REPORT_REG_TO_CONSOLE r9
/* Print out our data address to compared with l.adrp offset. */
l.movhi r11, ha(pi)
l.addi r11, r11, lo(pi)
REPORT_REG_TO_CONSOLE r11
/* Test l.adrp with symbols, loads page of symbol to register. */
l.adrp r4, start_tests
REPORT_REG_TO_CONSOLE r4
l.adrp r4, pi
REPORT_REG_TO_CONSOLE r4
/* Test l.adrp with immediate, immediate is the page offset. */
l.adrp r4, 0x0
REPORT_REG_TO_CONSOLE r4
l.adrp r4, 0x12000
REPORT_REG_TO_CONSOLE r4
l.adrp r4, -0x2000
REPORT_REG_TO_CONSOLE r4
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 6,250
|
sim/testsuite/or1k/and.S
|
/* Tests instructions l.and, l.andi.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xc4c70f07);\n
# output: report(0x44400004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x38f0f83b);\n
# output: report(0x30800803);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000ffff);\n
# output: report(0x0000ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x0000aaaa);\n
# output: report(0x0000aaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00005555);\n
# output: report(0x00005555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00005555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f83);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f07);\n
# output: report(0x00000004);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000f83b);\n
# output: report(0x00000803);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Always set OVE. We should never trigger an exception, even if
this bit is set. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test the l.and instruction with a range of operands. */
TEST_INST_I32_I32 l.and, 0x00000000, 0x00000000
TEST_INST_I32_I32 l.and, 0xffffffff, 0xffffffff
TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x00000000
TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0xaaaaaaaa
TEST_INST_I32_I32 l.and, 0x55555555, 0x00000000
TEST_INST_I32_I32 l.and, 0x55555555, 0x55555555
TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x55555555
TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xb38f0f83
TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xc4c70f07
TEST_INST_I32_I32 l.and, 0xb38f0f83, 0x38f0f83b
/* Test the l.andi instruction with a range of operands. */
TEST_INST_I32_I16 l.andi, 0x00000000, 0x0000
TEST_INST_I32_I16 l.andi, 0xffffffff, 0xffff
TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x0000
TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0xaaaa
TEST_INST_I32_I16 l.andi, 0x55555555, 0x0000
TEST_INST_I32_I16 l.andi, 0x55555555, 0x5555
TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x5555
TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f83
TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f07
TEST_INST_I32_I16 l.andi, 0xb38f0f83, 0xf83b
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 2,444
|
sim/testsuite/or1k/fpu64a32-unordered.S
|
/* Tests some basic unordered fpu compare instructions.
Copyright (C) 2019-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x400921f9);\n
# output: report(0xf01b866e);\n
# output: report(0x4005bf09);\n
# output: report(0x95aaf790);\n
# output: report(0x7ff80000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .data
.align 4
.type pi, @object
.size pi, 8
anchor:
pi:
.double 3.14159
.type e, @object
.size e, 8
e:
.double 2.71828
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test unordered double comparisons. Setting up:
* r11 pointer to data
* r12,r13 pi as double
* r14,r15 e as double
* r16,r17 nan as double
*/
l.ori r11, r0, ha(anchor)
l.addi r11, r11, lo(anchor)
l.lwz r12, 0(r11)
l.lwz r13, 4(r11)
l.lwz r14, 8(r11)
l.lwz r15, 12(r11)
/* Make a NaN. */
lf.sub.d r16,r18, r12,r13, r12,r13
lf.div.d r16,r18, r16,r18, r16,r18
/* Output to ensure we loaded it correctly. */
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
REPORT_REG_TO_CONSOLE r14
REPORT_REG_TO_CONSOLE r15
REPORT_REG_TO_CONSOLE r16
REPORT_REG_TO_CONSOLE r18
PRINT_NEWLINE_TO_CONSOLE
lf.sfuge.d r12,r13, r14,r15
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfun.d r12,r13, r14,r15
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfun.d r12,r13, r16,r18
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 2,315
|
sim/testsuite/or1k/fpu-unordered.S
|
/* Tests some basic unordered fpu compare instructions.
Copyright (C) 2019-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x40490fd0);\n
# output: report(0x402df84d);\n
# output: report(0x7fc00000);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .data
.align 4
.type pi, @object
.size pi, 4
anchor:
pi:
.float 3.14159
.type e, @object
.size e, 4
e:
.float 2.71828
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test unordered float comparisons. Setting up:
* r11 pointer to data
* r12 pi as float
* r13 e as float
* r16 nan as float
*/
l.ori r11, r0, ha(anchor)
l.addi r11, r11, lo(anchor)
l.lwz r12, 0(r11)
l.lwz r13, 4(r11)
/* Make a NaN. */
lf.sub.s r16, r13, r13
lf.div.s r16, r16, r16
/* Output to ensure we loaded it correctly. */
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
REPORT_REG_TO_CONSOLE r16
PRINT_NEWLINE_TO_CONSOLE
lf.sfuge.s r12, r13
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfun.s r12, r13
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfun.s r12, r16
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
lf.sfueq.s r12, r12
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 18,041
|
sim/testsuite/or1k/mul.S
|
/* Tests the multiply instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008001);\n
# output: report(0x0000fffe);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00010000);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0002);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0000);\n
# output: report(0x80010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff0000);\n
# output: report(0xfffeffff);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff8000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0x00010000);\n
# output: report(0x7fff0000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0000);\n
# output: report(0x80010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00010002);\n
# output: report(0x00007fff);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00020000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00040000);\n
# output: report(0x00004000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffffe);\n
# output: report(0x0000fffd);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffefffe);\n
# output: report(0x00008001);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffe0000);\n
# output: report(0x0000bfff);\n
# output: report(0x80020000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffdfffe);\n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0x0000fffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00010000);\n
# output: report(0x00008000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffdfffc);\n
# output: report(0x00004000);\n
# output: report(0x7fff0000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00020000);\n
# output: report(0x00004000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xfffffffe);\n
# output: report(0x0000fffd);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffdfffe);\n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0x00000003);\n
# output: report(0x00000006);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008001);\n
# output: report(0x0000fffe);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00010000);\n
# output: report(0x00010000);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffffe);\n
# output: report(0xfffffffd);\n
# output: report(0x00000006);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0002);\n
# output: report(0x7ffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0000);\n
# output: report(0x80010000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff0000);\n
# output: report(0xfffeffff);\n
# output: report(0x00010000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff8000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0x00010000);\n
# output: report(0x7fff0000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000001);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00008000);\n
# output: report(0x00010000);\n
# output: report(0x80000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000002);\n
# output: report(0xfffffffd);\n
# output: report(0xfffffffa);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xffff7fff);\n
# output: report(0xffff0000);\n
# output: report(0x80010000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Range exception. */
.org 0xb00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots, but we are not testing that here. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw 0(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.mul */
/* Multiply two small positive numbers. This should set no flags.
*/
TEST_INST_I32_I32 l.mul, 0x00000002, 0x00000003
/* Multiply two quite large positive numbers. This should set no
flags */
TEST_INST_I32_I32 l.mul, 0x00008001, 0x0000fffe
/* Multiply two slightly too large positive numbers. This should
set the overflow, but not the carry flag . */
TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000
/* Multiply two large positive numbers. This should set the
overflow flags (even though the result is not a negative
number. */
TEST_INST_I32_I32 l.mul, 0x00010000, 0x00010000
/* Multiply two small negative numbers. This will set no flags. */
TEST_INST_I32_I32 l.mul, 0xfffffffe, 0xfffffffd
/* Multiply two quite large negative numbers. This will no flags. */
TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0002
/* Multiply two slightly too large negative numbers. This should
set the overflow flag. */
TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000
/* Multiply two large negative numbers. This should set the
both the carry and overflow flags (even though the result is a
positive number. */
TEST_INST_I32_I32 l.mul, 0xffff0000, 0xfffeffff
/* Multiply one small negative number and one small positive
number. This will set the no flags. */
TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd
/* Multiply one quite large negative number and one quite large
positive number. This will set no flags. */
TEST_INST_I32_I32 l.mul, 0xffff8000, 0x00010000
/* Multiply one slightly too large negative number and one slightly
too large positive number. This should set the overflow flag. */
TEST_INST_I32_I32 l.mul, 0xffff7fff, 0x00010000
/* Multiply the largest negative number by positive unity. This
should set neither carry, nor overflow flag. */
TEST_INST_I32_I32 l.mul, 0x80000000, 0x00000001
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000
/* Check multiply of a negative and positive does not cause a RANGE
Exception. */
TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd
/* Check that negative overflow causes a RANGE exception. */
TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.muli */
/* Multiply two small positive numbers. This should set no flags. */
TEST_INST_I32_I16 l.muli, 0x00000002, 0x0003
/* Multiply two quite large positive numbers. This should set no
flags */
TEST_INST_I32_I16 l.muli, 0x00010002, 0x7fff
/* Multiply two slightly too large positive numbers. This should
set the overflow, but not the carry flag. */
TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000
/* Multiply two large positive numbers. This should set the
overflow flag, even though the result is not a negative number. */
TEST_INST_I32_I16 l.muli, 0x00040000, 0x4000
/* Multiply two small negative numbers. This should set no flags. */
TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd
/* Multiply two quite large negative numbers. This will set no
flags. */
TEST_INST_I32_I16 l.muli, 0xfffefffe, 0x8001
/* Multiply two slightly too large negative numbers. This should
set the overflow flag. */
TEST_INST_I32_I16 l.muli, 0xfffe0000, 0xbfff
/* Multiply two large negative numbers. This should set the
overflow flag, even though the result is a positive number. */
TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000
/* Multiply one small negative number and one small positive
number. This will set no flags. */
TEST_INST_I32_I16 l.muli, 0x00000002, 0xfffd
/* Multiply one quite large negative number and one quite large
positive number. This will set no flags. */
TEST_INST_I32_I16 l.muli, 0x00010000, 0x8000
/* Multiply one slightly too large negative number and one slightly
too large positive number. This will set the overflow flag. */
TEST_INST_I32_I16 l.muli, 0xfffdfffc, 0x4000
/* Multiply the largest negative number by positive unity. Should
set neither carry, nor overflow flag. */
TEST_INST_I32_I16 l.muli, 0x80000000, 0x0001
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000
/* Check that two negatives will not cause a RANGE Exception. */
TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd
/* Check that multiply of larget negative and positive numbers causes
a RANGE exception and overflow. */
TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test l.mulu */
/* Multiply two small positive numbers. This should set no flags. */
TEST_INST_I32_I32 l.mulu, 0x00000002, 0x00000003
/* Multiply two quite large positive numbers. This should set no
flags. */
TEST_INST_I32_I32 l.mulu, 0x00008001, 0x0000fffe
/* Multiply two slightly too large positive numbers. This will set
no flags. */
TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000
/* Multiply two large positive numbers. This will set the overflow
flag. */
TEST_INST_I32_I32 l.mulu, 0x00010000, 0x00010000
/* Multiply two small negative numbers. This will set the
carry flag, but not the overflow flag. */
TEST_INST_I32_I32 l.mulu, 0xfffffffe, 0xfffffffd
/* Multiply two quite large negative numbers. This will set the
carry flag, but not the overflow flag. */
TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0002
/* Multiply two slightly too large negative numbers. This will set
the carry flag, and not the overflow flag */
TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000
/* Multiply two large negative numbers. This will set the both the
carry flag (even though the result is a positive number.) */
TEST_INST_I32_I32 l.mulu, 0xffff0000, 0xfffeffff
/* Multiply one small negative number and one small positive
number. This will set the carry flag, but not the overflow
flag. */
TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd
/* Multiply one quite large negative number and one quite large
positive number. This will set the carry flag, but not the
overflow flag. */
TEST_INST_I32_I32 l.mulu, 0xffff8000, 0x00010000
/* Multiply one slightly too large negative number and one slightly
too large positive number. This will set the carry flag, but
not the overflow flag. */
TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0x00010000
/* Multiply the largest negative number by positive unity. Should
set neither carry, nor overflow flag. */
TEST_INST_I32_I32 l.mulu, 0x80000000, 0x00000001
/* Check that range exceptions are never triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that what would cause an overflow alone in 2's complement
does not cause a RANGE Exception. */
TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000
/* Check that a carry causes a RANGE Exception. */
TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd
/* Check that what would cause an overflow and carry in 2's
complement causes a RANGE Exception. */
TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 4,321
|
sim/testsuite/or1k/fpu64a32.S
|
/* Tests some basic fpu instructions.
Copyright (C) 2019-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x400921f9);\n
# output: report(0xf01b866e);\n
# output: report(0x4005bf09);\n
# output: report(0x95aaf790);\n
# output: report(0x00000000);\n
# output: report(0x00001234);\n
# output: \n
# output: report(0x40b23400);\n
# output: report(0x00000000);\n
# output: report(0x40b23400);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40177081);\n
# output: report(0xc2e33eff);\n
# output: report(0x400921f9);\n
# output: report(0xf01b866e);\n
# output: \n
# output: report(0x40211456);\n
# output: report(0x587dfabf);\n
# output: report(0x400921f9);\n
# output: report(0xf01b866d);\n
# output: \n
# output: report(0x00000001);\n
# output: \n
# output: WARNING: ignoring fpu error caught in fast mode.\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Floating point exception. */
.org 0xd00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots. But we don't have those in this test. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw -4(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .data
.align 4
.type pi, @object
.size pi, 8
anchor:
pi:
.double 3.14159
.type e, @object
.size e, 8
e:
.double 2.71828
.type large, @object
.size large, 8
large:
.long 0
.long 0x1234
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test lf.itof.d int to double conversion. Setting up:
* r11 pointer to data
* r12,r13 pi as double
* r14,r15 e as double
* r16,r17 a long long
*/
l.ori r11, r0, ha(anchor)
l.addi r11, r11, lo(anchor)
l.lwz r12, 0(r11)
l.lwz r13, 4(r11)
l.lwz r14, 8(r11)
l.lwz r15, 12(r11)
l.lwz r16, 16(r11)
l.lwz r18, 20(r11)
/* Output to ensure we loaded it correctly. */
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
REPORT_REG_TO_CONSOLE r14
REPORT_REG_TO_CONSOLE r15
REPORT_REG_TO_CONSOLE r16
REPORT_REG_TO_CONSOLE r18
PRINT_NEWLINE_TO_CONSOLE
/* Convert the big long to a double. */
lf.itof.d r16,r18, r16,r18
REPORT_REG_TO_CONSOLE r16
REPORT_REG_TO_CONSOLE r18
/* Convert the double back to a long, it should match before. */
lf.ftoi.d r16,r18, r16,r18
lf.itof.d r16,r18, r16,r18
REPORT_REG_TO_CONSOLE r16
REPORT_REG_TO_CONSOLE r18
PRINT_NEWLINE_TO_CONSOLE
/* Add and subtract some double values. */
lf.add.d r12,r13, r12,r13, r14,r15
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
lf.sub.d r12,r13, r12,r13, r14,r15
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
PRINT_NEWLINE_TO_CONSOLE
/* Multiply and divide double values. */
lf.mul.d r12,r13, r12,r13, r14,r15
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
lf.div.d r12,r13, r12,r13, r14,r15
REPORT_REG_TO_CONSOLE r12
REPORT_REG_TO_CONSOLE r13
PRINT_NEWLINE_TO_CONSOLE
/* Test lf.sfge.s set flag if r6 >= r10. */
lf.sfge.d r12,r13, r14,r15
MOVE_FROM_SPR r2, SPR_SR
REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
PRINT_NEWLINE_TO_CONSOLE
/* Test raising an exception by dividing by 0. */
MOVE_FROM_SPR r2, SPR_FPCSR
l.ori r2, r2, 0x1
MOVE_TO_SPR SPR_FPCSR, r2
div0: lf.div.d r2,r3, r12,r13, r0,r1
REPORT_EXCEPTION div0
PRINT_NEWLINE_TO_CONSOLE
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 2,631
|
sim/testsuite/or1k/find.S
|
/* Tests the find instructions.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000020);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000002);\n
# output: \n
# output: report(0x00018000);\n
# output: report(0x00000010);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0x0000001f);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x00000020);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x0000001f);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000020);\n
# output: \n
# output: report(0x00018000);\n
# output: report(0x00000011);\n
# output: \n
# output: report(0xc0000000);\n
# output: report(0x00000020);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
.macro TEST_FIND opcode, operand
LOAD_IMMEDIATE r5, \operand
REPORT_REG_TO_CONSOLE r5
\opcode r4, r5
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.ff1 */
TEST_FIND l.ff1, 0x00000001
TEST_FIND l.ff1, 0x80000000
TEST_FIND l.ff1, 0x55555555
TEST_FIND l.ff1, 0xaaaaaaaa
TEST_FIND l.ff1, 0x00018000
TEST_FIND l.ff1, 0xc0000000
TEST_FIND l.ff1, 0x00000000
/* Test l.fl1 */
TEST_FIND l.fl1, 0x00000001
TEST_FIND l.fl1, 0x80000000
TEST_FIND l.fl1, 0x55555555
TEST_FIND l.fl1, 0xaaaaaaaa
TEST_FIND l.fl1, 0x00018000
TEST_FIND l.fl1, 0xc0000000
TEST_FIND l.fl1, 0x00000000
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 6,252
|
sim/testsuite/or1k/xor.S
|
/* Tests instructions l.xor, l.xori.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x55555555);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0xc4c70f07);\n
# output: report(0x88b7ff7b);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x38f0f83b);\n
# output: report(0x8b7ff7b8);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0x0000ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0xaaaaaaaa);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x0000aaaa);\n
# output: report(0x55550000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x55555555);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x55555555);\n
# output: report(0x00005555);\n
# output: report(0x55550000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xaaaaaaaa);\n
# output: report(0x00005555);\n
# output: report(0xaaaaffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f83);\n
# output: report(0x4c70ffff);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x4c70f07c);\n
# output: report(0x00000f07);\n
# output: report(0x4c70ff7b);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000f83b);\n
# output: report(0x4c70f7b8);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Always set OVE. We should never trigger an exception, even if
this bit is set. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Test the l.xor instruction with a range of operands. */
TEST_INST_I32_I32 l.xor, 0x00000000, 0x00000000
TEST_INST_I32_I32 l.xor, 0xffffffff, 0xffffffff
TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x00000000
TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0xaaaaaaaa
TEST_INST_I32_I32 l.xor, 0x55555555, 0x00000000
TEST_INST_I32_I32 l.xor, 0x55555555, 0x55555555
TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x55555555
TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xb38f0f83
TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xc4c70f07
TEST_INST_I32_I32 l.xor, 0xb38f0f83, 0x38f0f83b
/* Test the l.xori instruction with a range of operands. */
TEST_INST_I32_I16 l.xori, 0x00000000, 0x0000
TEST_INST_I32_I16 l.xori, 0xffffffff, 0xffff
TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x0000
TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0xaaaa
TEST_INST_I32_I16 l.xori, 0x55555555, 0x0000
TEST_INST_I32_I16 l.xori, 0x55555555, 0x5555
TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x5555
TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f83
TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f07
TEST_INST_I32_I16 l.xori, 0xb38f0f83, 0xf83b
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 4,656
|
sim/testsuite/or1k/ror.S
|
/* Tests instructions l.ror and l.rori.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x3b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0f83b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x671e1f07);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00002224);\n
# output: report(0x3b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00f789f0);\n
# output: report(0x0f83b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0xffffffff);\n
# output: report(0x671e1f07);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000000);\n
# output: report(0xb38f0f83);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000001);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000004);\n
# output: report(0x3b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000010);\n
# output: report(0x0f83b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000001f);\n
# output: report(0x671e1f07);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000021);\n
# output: report(0xd9c787c1);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000024);\n
# output: report(0x3b38f0f8);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x00000030);\n
# output: report(0x0f83b38f);\n
# output: \n
# output: report(0xb38f0f83);\n
# output: report(0x0000003f);\n
# output: report(0x671e1f07);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-env.h"
.macro TEST_ROR op1, op2, res
/* Note that 'res' is not used here. We could stop using the
.TestResults file and use 'res' here instead. */
LOAD_IMMEDIATE r5, \op1
LOAD_IMMEDIATE r6, \op2
REPORT_REG_TO_CONSOLE r5
REPORT_REG_TO_CONSOLE r6
l.ror r4, r5, r6
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
.macro TEST_RORI op1, op2, res
/* Note that 'res' is not used here. We could stop using the
.TestResults file and use 'res' here instead. */
LOAD_IMMEDIATE r5, \op1
REPORT_REG_TO_CONSOLE r5
REPORT_IMMEDIATE_TO_CONSOLE \op2
l.rori r4, r5, \op2
REPORT_REG_TO_CONSOLE r4
PRINT_NEWLINE_TO_CONSOLE
.endm
STANDARD_TEST_ENVIRONMENT
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test the l.ror instruction. */
/* Rotate by zero */
TEST_ROR 0xb38f0f83, 0x00000000, 0xb38f0f83
/* Rotate by amounts in the 1 - 31 range. */
TEST_ROR 0xb38f0f83, 0x00000001, 0xd9c787c1
TEST_ROR 0xb38f0f83, 0x00000004, 0x3b38f0f8
TEST_ROR 0xb38f0f83, 0x00000010, 0x0f83b38f
TEST_ROR 0xb38f0f83, 0x0000001f, 0x671e1f07
/* Rotate by larger amounts - should be masked. */
TEST_ROR 0xb38f0f83, 0x00000021, 0xd9c787c1
TEST_ROR 0xb38f0f83, 0x00002224, 0x3b38f0f8
TEST_ROR 0xb38f0f83, 0x00f789f0, 0x0f83b38f
TEST_ROR 0xb38f0f83, 0xffffffff, 0x671e1f07
/* Test the l.rori instruction. */
/* Rotate by zero */
TEST_RORI 0xb38f0f83, 0x00000000, 0xb38f0f83
/* Rotate by amounts in the 1 - 31 range. */
TEST_RORI 0xb38f0f83, 0x01, 0xd9c787c1
TEST_RORI 0xb38f0f83, 0x04, 0x3b38f0f8
TEST_RORI 0xb38f0f83, 0x10, 0x0f83b38f
TEST_RORI 0xb38f0f83, 0x1f, 0x671e1f07
/* Rotate by larger amounts (32 - 63) - should be masked. */
TEST_RORI 0xb38f0f83, 0x21, 0xd9c787c1
TEST_RORI 0xb38f0f83, 0x24, 0x3b38f0f8
TEST_RORI 0xb38f0f83, 0x30, 0x0f83b38f
TEST_RORI 0xb38f0f83, 0x3f, 0x671e1f07
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 6,846
|
sim/testsuite/or1k/sub.S
|
/* Tests instruction l.sub.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
# mach: or1k
# output: report(0x00000003);\n
# output: report(0x00000002);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000001);\n
# output: report(0x00000002);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x00000003);\n
# output: report(0x00000002);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xfffffffd);\n
# output: report(0xfffffffe);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0xffffffff);\n
# output: report(0xfffffffe);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffffff);\n
# output: report(0x3fffffff);\n
# output: report(0x40000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x40000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x3fffffff);\n
# output: report(0x40000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x40000000);\n
# output: report(0x3fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x80000000);\n
# output: report(0x7fffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: report(0x3fffffff);\n
# output: report(0x40000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000000);\n
# output: report(0x00000000);\n
# output: \n
# output: report(0x7fffffff);\n
# output: report(0x80000000);\n
# output: report(0xffffffff);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: report(0x00000001);\n
# output: \n
# output: exit(0)\n
#include "or1k-asm-test-helpers.h"
STANDARD_TEST_ENVIRONMENT
.section .exception_vectors
/* Range exception. */
.org 0xb00
/* The handling is a bit dubious at present. We just patch the
instruction with l.nop and restart. This will go wrong in branch
delay slots. But we don't have those in this test. */
l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
PUSH r2
PUSH r3
/* Save the address of the instruction that caused the problem. */
MOVE_FROM_SPR r2, SPR_EPCR_BASE
LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
l.sw 0(r2), r3
POP r3
POP r2
l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
l.rfe
.section .text
start_tests:
PUSH LINK_REGISTER_R9
/* Test l.sub */
/* Subtract two small positive numbers. Sets the carry, but never
the overflow if the result is negative. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000003, \
0x00000002
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000001, \
0x00000002
/* Check carry in is ignored. */
TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.sub, 0x00000003, 0x00000002
/* Subtract two small negative numbers. Sets the carry flag if
the result is negative, but never the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xfffffffd, \
0xfffffffe
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xffffffff, \
0xfffffffe
/* Subtract two quite large positive numbers. Should set neither
the overflow nor the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \
0x3fffffff
/* Subtract two quite large negative numbers. Should set neither
the overflow nor the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, \
0x40000000
/* Subtract two large positive numbers with a negative result.
Should set the carry, but not the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, \
0x40000000
/* Subtract two large negative numbers with a positive result.
Should set neither the carry nor the overflow flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, \
0x3fffffff
/* Subtract a large positive from a large negative number. Should
set overflow but not the carry flag. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, \
0x7fffffff
/* Subtract a large negative from a large positive number. Should
set both the overflow and carry flags. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \
0x80000000
/* Check that range exceptions are triggered. */
SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
/* Check that an overflow alone causes a RANGE Exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, \
0x7fffffff
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, \
0x40000000
/* Check that carry and overflow together cause an exception. */
TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, \
0x80000000
CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
POP LINK_REGISTER_R9
RETURN_TO_LINK_REGISTER_R9
|
stsp/binutils-ia16
| 3,095
|
sim/testsuite/bpf/alu.s
|
# mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; alu.s
;;; Tests for ALU64 BPF instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov %r1, 0
mov %r2, -1
;; add
add %r1, 1
add %r2, -1
add %r1, %r2
fail_ne %r1, -1
;; sub
sub %r1, %r1
fail_ne %r1, 0
sub %r1, 10
sub %r2, %r1
fail_ne %r2, 8
;; mul
mul %r2, %r2 ; r2 = 64
mul %r2, 3 ; r2 = 192
mov %r1, -3
mul %r1, %r2 ; r1 = -576
mul %r2, 0
fail_ne %r1, -576
fail_ne %r2, 0
mul %r1, %r1
mul %r1, %r1
fail_ne %r1, 110075314176
;; div
div %r2, %r1
fail_ne %r2, 0
div %r1, 10000
fail_ne %r1, 11007531
div %r1, %r1
fail_ne %r1, 1
;; div is unsigned
lddw %r1, -8
div %r1, 2
fail_ne %r1, 0x7ffffffffffffffc ; sign bits NOT maintained - large pos.
;; and
lddw %r1, 0xaaaaaaaa55555555
and %r1, 0x55aaaaaa ; we still only have 32-bit imm.
fail_ne %r1, 0x0000000055000000
lddw %r2, 0x5555555a5aaaaaaa
and %r2, %r1
fail_ne %r2, 0x0000000050000000
;; or
or %r2, 0xdeadbeef
fail_ne %r2, 0xffffffffdeadbeef ; 0xdeadbeef gets sign extended
lddw %r1, 0xdead00000000beef
lddw %r2, 0x0000123456780000
or %r1, %r2
fail_ne %r1, 0xdead12345678beef
;; lsh
mov %r1, 0xdeadbeef
lsh %r1, 11
fail_ne %r1, 0xfffffef56df77800 ; because deadbeef gets sign ext.
mov %r2, 21
lsh %r1, %r2
fail_ne %r1, 0xdeadbeef00000000
;; rsh
rsh %r1, 11
fail_ne %r1, 0x001bd5b7dde00000 ; 0xdeadbeef 00000000 >> 0xb
rsh %r1, %r2
fail_ne %r1, 0x00000000deadbeef
;; arsh
arsh %r1, 8
fail_ne %r1, 0x0000000000deadbe
lsh %r1, 40 ; r1 = 0xdead be00 0000 0000
arsh %r1, %r2 ; r1 arsh (r2 == 21)
fail_ne %r1, 0xfffffef56df00000
;; mod
mov %r1, 1025
mod %r1, 16
fail_ne %r1, 1
;; mod is unsigned
mov %r1, 1025
mod %r1, -16 ; mod unsigned -> will treat as large positive
fail_ne %r1, 1025
mov %r1, -25 ; -25 is 0xff..ffe7
mov %r2, 5 ; ... which when unsigned is a large positive
mod %r1, %r2 ; ... which is not evenly divisible by 5
fail_ne %r1, 1
;; xor
mov %r1, 0
xor %r1, %r2
fail_ne %r1, 5
xor %r1, 0x7eadbeef
fail_ne %r1, 0x7eadbeea
xor %r1, %r1
fail_ne %r1, 0
;; neg
neg %r2
fail_ne %r2, -5
mov %r1, -1025
neg %r1
fail_ne %r1, 1025
pass
|
stsp/binutils-ia16
| 3,044
|
sim/testsuite/bpf/jmp.s
|
# mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; jmp.s
;;; Tests for eBPF JMP instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov %r1, 5
mov %r2, 2
mov %r3, 7
mov %r4, -1
;; ja - jump absolute (unconditional)
ja 2f
1: fail
2: ;; jeq - jump eq
jeq %r1, 4, 1b ; no
jeq %r1, %r2, 1b ; no
jeq %r1, 5, 2f ; yes
fail
2: jeq %r1, %r1, 2f ; yes
fail
2: ;; jgt - jump (unsigned) greater-than
jgt %r1, 6, 1b ; no
jgt %r1, -5, 1b ; no - unsigned
jgt %r1, %r4, 1b ; no - unsigned
jgt %r1, 4, 2f ; yes
fail
2: jgt %r1, %r2, 2f ; yes
fail
2: ;; jge - jump (unsigned) greater-than-or-equal-to
jge %r1, 6, 1b ; no
jge %r1, 5, 2f ; yes
fail
2: jge %r1, %r3, 1b ; no
jge %r1, -5, 1b ; no - unsigned
jge %r1, %r2, 2f ; yes
fail
2: ;; jlt - jump (unsigned) less-than
jlt %r1, 5, 1b ; no
jlt %r1, %r2, 1b ; no
jlt %r4, %r1, 1b ; no - unsigned
jlt %r1, 6, 2f ; yes
fail
2:
jlt %r1, %r3, 2f ; yes
fail
2: ;; jle - jump (unsigned) less-than-or-equal-to
jle %r1, 4, 1b ; no
jle %r1, %r2, 1b ; no
jle %r4, %r1, 1b ; no
jle %r1, 5, 2f ; yes
fail
2: jle %r1, %r1, 2f ; yes
fail
2: ;; jset - jump "test" (AND)
jset %r1, 2, 1b ; no (5 & 2 = 0)
jset %r1, %r2, 1b ; no (same)
jset %r1, 4, 2f ; yes (5 & 4 != 0)
fail
2: ;; jne - jump not-equal-to
jne %r1, 5, 1b ; no
jne %r1, %r1, 1b ; no
jne %r1, 6, 2f ; yes
fail
2: jne %r1, %r4, 2f ; yes
fail
2: ;; jsgt - jump (signed) greater-than
jsgt %r1, %r3, 1b ; no
jsgt %r1, %r1, 1b ; no
jsgt %r1, 5, 1b ; no
jsgt %r1, -4, 2f ; yes
fail
2: jsgt %r1, %r4, 2f ; yes
fail
2: ;; jsge - jump (signed) greater-than-or-equal-to
jsge %r1, %r3, 1b ; no
jsge %r1, %r1, 2f ; yes
fail
2: jsge %r1, 7, 1b ; no
jsge %r1, -4, 2f ; yes
fail
2: jsge %r1, %r4, 2f ; yes
fail
2: ;; jslt - jump (signed) less-than
jslt %r1, 5, 1b ; no
jslt %r1, %r2, 1b ; no
jslt %r4, %r1, 2f ; yes
fail
2: jslt %r1, 6, 2f ; yes
fail
2: jslt %r1, %r3, 2f ; yes
fail
2: ;; jsle - jump (signed) less-than-or-equal-to
jsle %r1, 4, 1b ; no
jsle %r1, %r2, 1b ; no
jsle %r4, %r1, 2f ; yes
fail
2: jsle %r1, 5, 2f ; yes
fail
2: jsle %r1, %r3, 2f ; yes
fail
2:
pass
|
stsp/binutils-ia16
| 1,088
|
sim/testsuite/bpf/mov.s
|
# mach: bpf
# output: pass\nexit 0 (0x0)\n
;; mov.s
;; Tests for mov and mov32 instructions
.include "testutils.inc"
.text
.global main
.type main, @function
main:
;; some basic sanity checks
mov32 %r1, 5
fail_ne %r1, 5
mov32 %r2, %r1
fail_ne %r2, 5
mov %r2, %r1
fail_ne %r2, 5
mov %r1, -666
fail_ne %r1, -666
;; should NOT sign extend
mov32 %r1, -1
fail_ne %r1, 0x00000000ffffffff
;; should sign extend
mov %r2, -1
fail_ne %r2, 0xffffffffffffffff
mov %r3, 0x80000000
;; should NOT sign extend
mov32 %r4, %r3
fail_ne %r4, 0x0000000080000000
;; should sign extend
mov %r5, %r3
fail_ne %r5, 0xffffffff80000000
mov32 %r1, -2147483648
mov32 %r1, %r1
fail_ne32 %r1, -2147483648
;; casting shenanigans
mov %r1, %r1
fail_ne %r1, +2147483648
mov32 %r2, -1
mov %r2, %r2
fail_ne %r2, +4294967295
pass
|
stsp/binutils-ia16
| 2,479
|
sim/testsuite/bpf/ldabs.s
|
# mach: bpf
# sim: --skb-data-offset=0x20
# output: pass\nexit 0 (0x0)\n
;;; ldabs.s
;;; Tests for non-generic BPF load instructions in simulator.
;;; These instructions (ld{abs,ind}{b,h,w,dw}) are used to access
;;; kernel socket data from BPF programs for high performance filters.
;;;
;;; Register r6 is an implicit input holding a pointer to a struct sk_buff.
;;; Register r0 is an implicit output, holding the fetched data.
;;;
;;; e.g.
;;; ldabsw means:
;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + imm32))
;;;
;;; ldindw means
;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + src_reg + imm32))
.include "testutils.inc"
.text
.global main
.type main, @function
main:
;; R6 holds a pointer to a struct sk_buff, which we pretend
;; exists at 0x1000
mov %r6, 0x1000
;; We configure skb-data-offset=0x20
;; This specifies offsetof(struct sk_buff, data), where the field 'data'
;; is a pointer a data buffer, in this case at 0x2000
stw [%r6+0x20], 0x2000
;; Write the value 0x7eadbeef into memory at 0x2004
;; i.e. offset 4 within the data buffer pointed to by
;; ((struct sk_buff *)r6)->data
stw [%r6+0x1004], 0xdeadbeef
;; Now load data[4] into r0 using the ldabsw instruction
ldabsw 0x4
;; ...and compare to what we expect
fail_ne32 %r0, 0xdeadbeef
;; Repeat for a half-word (2-bytes)
sth [%r6+0x1008], 0x1234
ldabsh 0x8
fail_ne32 %r0, 0x1234
;; Repeat for a single byte
stb [%r6+0x1010], 0x5a
ldabsb 0x10
fail_ne32 %r0, 0x5a
;; Repeat for a double-word (8-byte)
;; (note: fail_ne macro uses r0, so copy to another r1 to compare)
lddw %r2, 0x1234deadbeef5678
stxdw [%r6+0x1018], %r2
ldabsdw 0x18
mov %r1, %r0
fail_ne %r1, 0x1234deadbeef5678
;; Now, we do the same for the indirect loads
mov %r7, 0x100
stw [%r6+0x1100], 0xfeedbeef
ldindw %r7, 0x0
fail_ne32 %r0, 0xfeedbeef
;; half-word
sth [%r6+0x1104], 0x6789
ldindh %r7, 0x4
fail_ne32 %r0, 0x6789
;; byte
stb [%r6+0x1108], 0x5f
ldindb %r7, 0x8
fail_ne32 %r0, 0x5f
;; double-word
lddw %r2, 0xcafe12345678d00d
stxdw [%r6+0x1110], %r2
ldinddw %r7, 0x10
mov %r1, %r0
fail_ne %r1, 0xcafe12345678d00d
pass
|
stsp/binutils-ia16
| 1,066
|
sim/testsuite/bpf/xadd.s
|
# mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; xadd.s
;;; Tests for BPF atomic exchange-and-add instructions in simulator
;;;
;;; The xadd instructions (XADDW, XADDDW) operate on a memory location
;;; specified in $dst + offset16, atomically adding the value in $src.
;;;
;;; In the simulator, there isn't anything else happening. The atomic
;;; instructions are identical to a non-atomic load/add/store.
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov %r1, 0x1000
mov %r2, 5
;; basic xadd w
stw [%r1+0], 10
xaddw [%r1+0], %r2
ldxw %r3, [%r1+0]
fail_ne %r3, 15
;; basic xadd dw
stdw [%r1+8], 42
xadddw [%r1+8], %r2
ldxdw %r3, [%r1+8]
fail_ne %r3, 47
;; xadd w negative value
mov %r4, -1
xaddw [%r1+0], %r4
ldxw %r3, [%r1+0]
fail_ne %r3, 14
;; xadd dw negative val
xadddw [%r1+8], %r4
ldxdw %r3, [%r1+8]
fail_ne %r3, 46
pass
|
stsp/binutils-ia16
| 1,044
|
sim/testsuite/bpf/endbe.s
|
# mach: bpf
# as: --EB
# ld: --EB
# sim: -E big
# output: pass\nexit 0 (0x0)\n
;;; endbe.s
;;; Tests for BPF endianness-conversion instructions in simulator
;;; running in BIG ENDIAN
;;;
;;; Both 'be' and 'le' ISAs have both endbe and endle instructions.
.include "testutils.inc"
.text
.global main
.type main, @function
main:
lddw %r1, 0x12345678deadbeef
endle %r1, 64
fail_ne %r1, 0xefbeadde78563412
endle %r1, 64
fail_ne %r1, 0x12345678deadbeef
;; `bitsize` < 64 will truncate
endle %r1, 32
fail_ne %r1, 0xefbeadde
endle %r1, 32
fail_ne %r1, 0xdeadbeef
endle %r1, 16
fail_ne %r1, 0xefbe
endle %r1, 16
fail_ne %r1, 0xbeef
;; endbe on be should be noop (except truncate)
lddw %r1, 0x12345678deadbeef
endbe %r1, 64
fail_ne %r1, 0x12345678deadbeef
endbe %r1, 32
fail_ne %r1, 0xdeadbeef
endbe %r1, 16
fail_ne %r1, 0xbeef
pass
|
stsp/binutils-ia16
| 3,048
|
sim/testsuite/bpf/jmp32.s
|
# mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; jmp32.s
;;; Tests for eBPF JMP32 instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov32 %r1, 5
mov32 %r2, 2
mov32 %r3, 7
mov32 %r4, -1
;; ja - jump absolute (unconditional)
ja 2f
1: fail
2: ;; jeq - jump eq
jeq32 %r1, 4, 1b ; no
jeq32 %r1, %r2, 1b ; no
jeq32 %r1, 5, 2f ; yes
fail
2: jeq32 %r1, %r1, 2f ; yes
fail
2: ;; jgt - jump (unsigned) greater-than
jgt32 %r1, 6, 1b ; no
jgt32 %r1, -5, 1b ; no - unsigned
jgt32 %r1, %r4, 1b ; no - unsigned
jgt32 %r1, 4, 2f ; yes
fail
2: jgt32 %r1, %r2, 2f ; yes
fail
2: ;; jge - jump (unsigned) greater-than-or-equal-to
jge32 %r1, 6, 1b ; no
jge32 %r1, 5, 2f ; yes
fail
2: jge32 %r1, %r3, 1b ; no
jge32 %r1, -5, 1b ; no - unsigned
jge32 %r1, %r2, 2f ; yes
fail
2: ;; jlt - jump (unsigned) less-than
jlt32 %r1, 5, 1b ; no
jlt32 %r1, %r2, 1b ; no
jlt32 %r4, %r1, 1b ; no - unsigned
jlt32 %r1, 6, 2f ; yes
fail
2:
jlt32 %r1, %r3, 2f ; yes
fail
2: ;; jle - jump (unsigned) less-than-or-equal-to
jle32 %r1, 4, 1b ; no
jle32 %r1, %r2, 1b ; no
jle32 %r4, %r1, 1b ; no
jle32 %r1, 5, 2f ; yes
fail
2: jle32 %r1, %r1, 2f ; yes
fail
2: ;; jset - jump "test" (AND)
jset32 %r1, 2, 1b ; no (5 & 2 = 0)
jset32 %r1, %r2, 1b ; no (same)
jset32 %r1, 4, 2f ; yes (5 & 4 != 0)
fail
2: ;; jne - jump not-equal-to
jne32 %r1, 5, 1b ; no
jne32 %r1, %r1, 1b ; no
jne32 %r1, 6, 2f ; yes
fail
2: jne32 %r1, %r4, 2f ; yes
fail
2: ;; jsgt - jump (signed) greater-than
jsgt32 %r1, %r3, 1b ; no
jsgt32 %r1, %r1, 1b ; no
jsgt32 %r1, 5, 1b ; no
jsgt32 %r1, -4, 2f ; yes
fail
2: jsgt32 %r1, %r4, 2f ; yes
fail
2: ;; jsge - jump (signed) greater-than-or-equal-to
jsge32 %r1, %r3, 1b ; no
jsge32 %r1, %r1, 2f ; yes
fail
2: jsge32 %r1, 7, 1b ; no
jsge32 %r1, -4, 2f ; yes
fail
2: jsge32 %r1, %r4, 2f ; yes
fail
2: ;; jslt - jump (signed) less-than
jslt32 %r1, 5, 1b ; no
jslt32 %r1, %r2, 1b ; no
jslt32 %r4, %r1, 2f ; yes
fail
2: jslt32 %r1, 6, 2f ; yes
fail
2: jslt32 %r1, %r3, 2f ; yes
fail
2: ;; jsle - jump (signed) less-than-or-equal-to
jsle32 %r1, 4, 1b ; no
jsle32 %r1, %r2, 1b ; no
jsle32 %r4, %r1, 2f ; yes
fail
2: jsle32 %r1, 5, 2f ; yes
fail
2: jsle32 %r1, %r3, 2f ; yes
fail
2:
pass
|
stsp/binutils-ia16
| 1,403
|
sim/testsuite/bpf/mem.s
|
# mach: bpf
# output: pass\nexit 0 (0x0)\n
;;; mem.s
;;; Tests for BPF memory (ldx, stx, ..) instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
lddw %r1, 0x1234deadbeef5678
mov %r2, 0x1000
;; basic store/load check
stxb [%r2+0], %r1
stxh [%r2+2], %r1
stxw [%r2+4], %r1
stxdw [%r2+8], %r1
stb [%r2+16], 0x5a
sth [%r2+18], 0xcafe
stw [%r2+20], 0xbeefface
stdw [%r2+24], 0x7eadbeef
ldxb %r1, [%r2+16]
fail_ne %r1, 0x5a
ldxh %r1, [%r2+18]
fail_ne %r1, 0xffffffffffffcafe
ldxw %r1, [%r2+20]
fail_ne %r1, 0xffffffffbeefface
ldxdw %r1, [%r2+24]
fail_ne %r1, 0x7eadbeef
ldxb %r3, [%r2+0]
fail_ne %r3, 0x78
ldxh %r3, [%r2+2]
fail_ne %r3, 0x5678
ldxw %r3, [%r2+4]
fail_ne %r3, 0xffffffffbeef5678
ldxdw %r3, [%r2+8]
fail_ne %r3, 0x1234deadbeef5678
ldxw %r4, [%r2+10]
fail_ne %r4, 0xffffffffdeadbeef
;; negative offsets
add %r2, 16
ldxh %r5, [%r2+-14]
fail_ne %r5, 0x5678
ldxw %r5, [%r2+-12]
fail_ne %r5, 0xffffffffbeef5678
ldxdw %r5, [%r2+-8]
fail_ne %r5, 0x1234deadbeef5678
pass
|
stsp/binutils-ia16
| 3,084
|
sim/testsuite/bpf/alu32.s
|
# mach: bpf
# output: pass\nexit 0 (0x0)\n
;; alu32.s
;; Tests for ALU(32) BPF instructions in simulator
.include "testutils.inc"
.text
.global main
.type main, @function
main:
mov32 %r1, 10 ; r1 = 10
mov32 %r2, -5 ; r2 = -5
;; add
add32 %r1, 1 ; r1 += 1 (r1 = 11)
add32 %r2, -1 ; r2 += -1 (r2 = -6)
add32 %r1, %r2 ; r1 += r2 (r1 = 11 + -6 = 5)
fail_ne32 %r1, 5
;; sub
sub32 %r1, 5 ; r1 -= 5 (r1 = 0)
sub32 %r1, -5 ; r1 -= -5 (r1 = 5)
sub32 %r1, %r2 ; r1 -= r2 (r1 = 5 - -6 = 11)
fail_ne32 %r1, 11
;; mul
mul32 %r1, 2 ; r1 *= 2 (r1 = 22)
mul32 %r1, -2 ; r1 *= -2 (r1 = -44)
mul32 %r1, %r2 ; r1 *= r2 (r1 = -44 * -6 = 264)
fail_ne32 %r1, 264
;; div
div32 %r1, 6
mov32 %r2, 11
div32 %r1, %r2
fail_ne32 %r1, 4
;; div is unsigned
mov32 %r1, -8 ; 0xfffffff8
div32 %r1, 2
fail_ne32 %r1, 0x7ffffffc ; sign bits are not preserved
;; and (bitwise)
mov32 %r1, 0xb ; r1 = (0xb = 0b1011)
mov32 %r2, 0x5 ; r2 = (0x5 = 0b0101)
and32 %r1, 0xa ; r1 &= (0xa = 0b1010) = (0b1010 = 0xa)
fail_ne32 %r1, 0xa
and32 %r1, %r2 ; r1 &= r2 = 0x0
fail_ne32 %r1, 0x0
;; or (bitwise)
or32 %r1, 0xb
or32 %r1, %r2
fail_ne32 %r1, 0xf
;; lsh (left shift)
lsh32 %r1, 4 ; r1 <<= 4 (r1 = 0xf0)
mov32 %r2, 24 ; r2 = 24
lsh32 %r1, %r2
fail_ne32 %r1, 0xf0000000
;; rsh (right logical shift)
rsh32 %r1, 2
rsh32 %r1, %r2
fail_ne32 %r1, 0x3c ; (0xf000 0000 >> 26)
;; arsh (right arithmetic shift)
arsh32 %r1, 1
or32 %r1, 0x80000000
mov32 %r2, 3
arsh32 %r1, %r2
fail_ne %r1, 0x00000000F0000003
; Note: make sure r1 is NOT sign-extended
; i.e. upper-32 bits should be untouched
;; mod
mov32 %r1, 1025
mod32 %r1, 16
fail_ne32 %r1, 1
;; mod is unsigned
mov32 %r1, 1025
mod32 %r1, -16 ; when unsigned, much larger than 1025
fail_ne32 %r1, 1025
mov32 %r1, -25 ; when unsigned, a large positive which is
mov32 %r2, 5 ; ... not evenly divisible by 5
mod32 %r1, %r2
fail_ne32 %r1, 1
;; xor
xor32 %r1, %r2
fail_ne32 %r1, 4
xor32 %r1, 0xF000000F
fail_ne %r1, 0xF000000B ; Note: check for (bad) sign-extend
xor32 %r1, %r1
fail_ne %r1, 0
;; neg
mov32 %r1, -1
mov32 %r2, 0x7fffffff
neg32 %r1
neg32 %r2
fail_ne32 %r1, 1
fail_ne %r2, 0x80000001 ; Note: check for (bad) sign-extend
neg32 %r2
fail_ne32 %r2, 0x7fffffff
pass
|
stsp/binutils-ia16
| 4,321
|
sim/testsuite/d10v/t-mod-ld-pre.s
|
# mach: all
# output:
# sim: --environment operating
.include "t-macros.i"
start
mvfc r0, PSW || ldi.s r14, #0
ldi.l r2, 0x100 ; MOD_E
ldi.l r3, 0x108 ; MOD_S
test_mod_dec_ld:
mvtc r2, MOD_E || bseti r0, #7
mvtc r3, MOD_S
mvtc r0, PSW ; modulo mode enable
mv r1,r3 ; r1=0x108
ld r4, @r1- || nop ; r1=0x106
ld r4, @r1- || nop ; r1=0x104
ld r4, @r1- || nop ; r1=0x102
ld r4, @r1- || nop ; r1=0x100
ld r4, @r1- || nop ; r1=0x108
ld r4, @r1- || nop ; r1=0x106
cmpeqi r1,#0x106
brf0f _ERR ; branch to error
test_mod_inc_ld:
mvtc r2, MOD_S
mvtc r3, MOD_E
mv r1,r2 ; r1=0x100
ld r4, @r1+ || nop ; r1=0x102
ld r4, @r1+ || nop ; r1=0x104
ld r4, @r1+ || nop ; r1=0x106
ld r4, @r1+ || nop ; r1=0x108
ld r4, @r1+ || nop ; r1=0x100
ld r4, @r1+ || nop ; r1=0x102
cmpeqi r1,#0x102
brf0f _ERR
test_mod_dec_ld2w:
mvtc r2, MOD_E
mvtc r3, MOD_S
mv r1,r3 ; r1=0x108
ld2W r4, @r1- || nop ; r1=0x104
ld2W r4, @r1- || nop ; r1=0x100
ld2W r4, @r1- || nop ; r1=0x108
ld2W r4, @r1- || nop ; r1=0x104
cmpeqi r1,#0x104
brf0f _ERR ; <= branch to error
test_mod_inc_ld2w:
mvtc r2, MOD_S
mvtc r3, MOD_E || BCLRI r0, #7
mv r1,r2 ; r1=0x100
ld2W r4, @r1+ || nop ; r1=0x104
ld2W r4, @r1+ || nop ; r1=0x108
ld2W r4, @r1+ || nop ; r1=0x100
ld2W r4, @r1+ || nop ; r1=0x104
cmpeqi r1,#0x104
brf0f _ERR
test_mod_dec_ld_dis:
mvtc r0, PSW ; modulo mode disable
mvtc r2, MOD_E
mvtc r3, MOD_S
mv r1,r3 ; r1=0x108
ld r4, @r1- || nop ; r1=0x106
ld r4, @r1- || nop ; r1=0x104
ld r4, @r1- || nop ; r1=0x102
ld r4, @r1- || nop ; r1=0x100
ld r4, @r1- || nop ; r1=0xFE
ld r4, @r1- || nop ; r1=0xFC
cmpeqi r1,#0xFC
brf0f _ERR
test_mod_inc_ld_dis:
mvtc r2, MOD_S
mvtc r3, MOD_E
mv r1,r2 ; r1=0x100
ld r4, @r1+ || nop ; r1=0x102
ld r4, @r1+ || nop ; r1=0x104
ld r4, @r1+ || nop ; r1=0x106
ld r4, @r1+ || nop ; r1=0x108
ld r4, @r1+ || nop ; r1=0x10A
ld r4, @r1+ || nop ; r1=0x10C
cmpeqi r1,#0x10C
brf0f _ERR
test_mod_dec_ld2w_dis:
mvtc r2, MOD_E
mvtc r3, MOD_S
mv r1,r3 ; r1=0x108
ld2W r4, @r1- || nop ; r1=0x104
ld2W r4, @r1- || nop ; r1=0x100
ld2W r4, @r1- || nop ; r1=0xFC
ld2W r4, @r1- || nop ; r1=0xF8
cmpeqi r1,#0xF8
brf0f _ERR
test_mod_inc_ld2w_dis:
mvtc r2, MOD_S
mvtc r3, MOD_E
mv r1,r2 ; r1=0x100
ld2W r4, @r1+ || nop ; r1=0x104
ld2W r4, @r1+ || nop ; r1=0x108
ld2W r4, @r1+ || nop ; r1=0x10C
ld2W r4, @r1+ || nop ; r1=0x110
cmpeqi r1,#0x110
brf0f _ERR
_OK:
exit0
_ERR:
exit47
|
stsp/binutils-ia16
| 1,820
|
sim/testsuite/d10v/t-mvtc.s
|
# mach: all
# output:
# sim: --environment operating
# as: -W
.include "t-macros.i"
start
;;; Try out each bit in the PSW
loadpsw2 PSW_SM
checkpsw2 1 PSW_SM
loadpsw2 PSW_01
checkpsw2 2 0 ;; PSW_01
loadpsw2 PSW_EA
checkpsw2 3 PSW_EA
loadpsw2 PSW_DB
checkpsw2 4 PSW_DB
loadpsw2 PSW_DM
checkpsw2 5 0 ;; PSW_DM
loadpsw2 PSW_IE
checkpsw2 6 PSW_IE
loadpsw2 PSW_RP
checkpsw2 7 PSW_RP
loadpsw2 PSW_MD
checkpsw2 8 PSW_MD
loadpsw2 PSW_FX|PSW_ST
checkpsw2 9 PSW_FX|PSW_ST
;; loadpsw2 PSW_ST
;; checkpsw2 10
loadpsw2 PSW_10
checkpsw2 11 0 ;; PSW_10
loadpsw2 PSW_11
checkpsw2 12 0 ;; PSW_11
loadpsw2 PSW_F0
checkpsw2 13 PSW_F0
loadpsw2 PSW_F1
checkpsw2 14 PSW_F1
loadpsw2 PSW_14
checkpsw2 15 0 ;; PSW_14
loadpsw2 PSW_C
checkpsw2 16 PSW_C
;;; Check that bit 0 (LSB) of the MOD_E & MOD_S registers are stuck at ZERO.
ldi r6, #0xdead
mvtc r6, cr10
ldi r6, #0xbeef
mvtc r6, cr11
mvfc r7, cr10
check 17 r7 0xdeac
mvfc r7, cr11
check 18 r7 0xbeee
;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero
psw_ffff:
ldi r6, 0xffff
mvtc r6, psw
mvfc r7, psw
check 18 r7 0xb7cd
bpsw_ffff:
ldi r6, 0xffff
mvtc r6, bpsw
mvfc r7, bpsw
check 18 r7 0xb7cd
dpsw_ffff:
ldi r6, 0xffff
mvtc r6, dpsw
mvfc r7, dpsw
check 18 r7 0xb7cd
;;; Another check. Very similar
psw_dfff:
ldi r6, 0xdfff
mvtc r6, psw
mvfc r7, psw
check 18 r7 0x97cd
bpsw_dfff:
ldi r6, 0xdfff
mvtc r6, bpsw
mvfc r7, bpsw
check 18 r7 0x97cd
dpsw_dfff:
ldi r6, 0xdfff
mvtc r6, dpsw
mvfc r7, dpsw
check 18 r7 0x97cd
;;; And again.
psw_8005:
ldi r6, 0x8005
mvtc r6, psw
mvfc r7, psw
check 18 r7 0x8005
bpsw_8005:
ldi r6, 0x8005
mvtc r6, bpsw
mvfc r7, bpsw
check 18 r7 0x8005
dpsw_8005:
ldi r6, 0x8005
mvtc r6, dpsw
mvfc r7, dpsw
check 18 r7 0x8005
exit0
|
stsp/binutils-ia16
| 1,118
|
sim/testsuite/d10v/t-mac.s
|
# mach: all
# output:
# sim: --environment operating
.include "t-macros.i"
start
;; clear FX
loadpsw2 0x8005
loadacc2 a1 0x7f 0xffff 0xffff
load r8 0xffff
load r9 0x8001
test_macu1:
MACU a1, r9, r8
checkacc2 1 a1 0x80 0x8000 0x7FFE
;; set FX
loadpsw2 0x8085
loadacc2 a1 0x7f 0xffff 0xffff
load r8 0xffff
load r9 0x8001
test_macu2:
MACU a1, r9, r8
checkacc2 2 a1 0x81 0x0000 0xfffd
;; clear FX
ldi r2, #0x8005
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, #0xffff
ldi r9, #0x7FFF
test_macsu1:
MACSU a1, r9, r8
checkacc2 3 a1 0x80 0x7FFE 0x8000
;; set FX
ldi r2, #0x8085
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, #0xffff
ldi r9, #0x7FFF
test_macsu2:
MACSU a1, r9, r8
checkacc2 4 a1 0x80 0xfffd 0x0001
;; clear FX
ldi r2, #0x8005
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, 0xffff
ldi r9, 0x8001
test_macsu3:
MACSU a1, r9, r8
checkacc2 5 a1 0x7F 0x8001 0x7FFE
;; set FX
ldi r2, #0x8085
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, #0xffff
ldi r9, #0x8001
test_macsu4:
MACSU a1, r9, r8
checkacc2 6 a1 0x7f 0x0002 0xFFFD
exit0
|
stsp/binutils-ia16
| 10,168
|
gdb/testsuite/gdb.btrace/i686-tailcall.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2013-2022 Free Software Foundation, Inc.
Contributed by Intel Corp. <markus.t.metzger@intel.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
This file has been generated using:
gcc -S -O2 -dA -g tailcall.c -o i686-tailcall.S */
.file "tailcall.c"
.text
.Ltext0:
.p2align 4,,15
.type bar, @function
bar:
.LFB0:
.file 1 "tailcall.c"
# tailcall.c:22
.loc 1 22 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall.c:24
.loc 1 24 0
movl $42, %eax
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE0:
.size bar, .-bar
.p2align 4,,15
.type foo, @function
foo:
.LFB1:
# tailcall.c:28
.loc 1 28 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall.c:29
.loc 1 29 0
jmp bar
# SUCC: EXIT [100.0%] (ABNORMAL,SIBCALL)
.LVL0:
.cfi_endproc
.LFE1:
.size foo, .-foo
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB2:
# tailcall.c:34
.loc 1 34 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall.c:37
.loc 1 37 0
call foo
.LVL1:
# tailcall.c:38
.loc 1 38 0
addl $1, %eax
.LVL2:
# SUCC: EXIT [100.0%]
# tailcall.c:41
.loc 1 41 0
ret
.cfi_endproc
.LFE2:
.size main, .-main
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0x8f # Length of Compilation Unit Info
.value 0x4 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x4 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF0 # DW_AT_producer: "GNU C 4.8.3 20140911 (Red Hat 4.8.3-7) -mtune=generic -march=i686 -g -O2"
.byte 0x1 # DW_AT_language
.long .LASF1 # DW_AT_name: "tailcall.c"
.long .LASF2 # DW_AT_comp_dir: ""
.long .Ldebug_ranges0+0 # DW_AT_ranges
.long 0 # DW_AT_low_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x25) DW_TAG_subprogram)
.ascii "bar\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (tailcall.c)
.byte 0x15 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x3a # DW_AT_type
.long .LFB0 # DW_AT_low_pc
.long .LFE0-.LFB0 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x3 # (DIE (0x3a) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.uleb128 0x4 # (DIE (0x41) DW_TAG_subprogram)
.ascii "foo\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (tailcall.c)
.byte 0x1b # DW_AT_decl_line
# DW_AT_prototyped
.long 0x3a # DW_AT_type
.long .LFB1 # DW_AT_low_pc
.long .LFE1-.LFB1 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0x64 # DW_AT_sibling
.uleb128 0x5 # (DIE (0x5a) DW_TAG_GNU_call_site)
.long .LVL0 # DW_AT_low_pc
# DW_AT_GNU_tail_call
.long 0x25 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x41
.uleb128 0x6 # (DIE (0x64) DW_TAG_subprogram)
# DW_AT_external
.long .LASF3 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (tailcall.c)
.byte 0x21 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x3a # DW_AT_type
.long .LFB2 # DW_AT_low_pc
.long .LFE2-.LFB2 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x7 # (DIE (0x79) DW_TAG_variable)
.long .LASF4 # DW_AT_name: "answer"
.byte 0x1 # DW_AT_decl_file (tailcall.c)
.byte 0x23 # DW_AT_decl_line
.long 0x3a # DW_AT_type
.long .LLST0 # DW_AT_location
.uleb128 0x8 # (DIE (0x88) DW_TAG_GNU_call_site)
.long .LVL1 # DW_AT_low_pc
.long 0x41 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x64
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x17 # (DW_FORM_sec_offset)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x2115 # (DW_AT_GNU_tail_call)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x6 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x7 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x8 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.long .LVL1 # Location list begin address (*.LLST0)
.long .LVL2 # Location list end address (*.LLST0)
.value 0x3 # Location expression size
.byte 0x70 # DW_OP_breg0
.sleb128 1
.byte 0x9f # DW_OP_stack_value
.long .LVL2 # Location list begin address (*.LLST0)
.long .LFE2 # Location list end address (*.LLST0)
.value 0x1 # Location expression size
.byte 0x50 # DW_OP_reg0
.long 0 # Location list terminator begin (*.LLST0)
.long 0 # Location list terminator end (*.LLST0)
.section .debug_aranges,"",@progbits
.long 0x24 # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x4 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 8 byte boundary
.value 0
.long .Ltext0 # Address
.long .Letext0-.Ltext0 # Length
.long .LFB2 # Address
.long .LFE2-.LFB2 # Length
.long 0
.long 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.long .Ltext0 # Offset 0
.long .Letext0
.long .LFB2 # Offset 0x8
.long .LFE2
.long 0
.long 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF1:
.string "tailcall.c"
.LASF3:
.string "main"
.LASF0:
.string "GNU C 4.8.3 20140911 (Red Hat 4.8.3-7) -mtune=generic -march=i686 -g -O2"
.LASF4:
.string "answer"
.LASF2:
.string ""
.ident "GCC: (GNU) 4.8.3 20140911 (Red Hat 4.8.3-7)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 12,814
|
gdb/testsuite/gdb.btrace/x86_64-tailcall-only.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2016-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
This file has been generated using:
gcc -S -O2 -dA -g tailcall-only.c -o x86_64-tailcall-only.S */
.file "tailcall-only.c"
.text
.Ltext0:
.p2align 4,,15
.type bar_1, @function
bar_1:
.LFB0:
.file 1 "tailcall-only.c"
# tailcall-only.c:22
.loc 1 22 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:24
.loc 1 24 0
movl $42, %eax
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE0:
.size bar_1, .-bar_1
.p2align 4,,15
.type bar, @function
bar:
.LFB1:
# tailcall-only.c:28
.loc 1 28 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:29
.loc 1 29 0
jmp bar_1
# SUCC: EXIT [100.0%] (ABNORMAL,SIBCALL)
.LVL0:
.cfi_endproc
.LFE1:
.size bar, .-bar
.p2align 4,,15
.type foo_1, @function
foo_1:
.LFB2:
# tailcall-only.c:34
.loc 1 34 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:35
.loc 1 35 0
jmp bar
# SUCC: EXIT [100.0%] (ABNORMAL,SIBCALL)
.LVL1:
.cfi_endproc
.LFE2:
.size foo_1, .-foo_1
.p2align 4,,15
.type foo, @function
foo:
.LFB3:
# tailcall-only.c:40
.loc 1 40 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:41
.loc 1 41 0
jmp foo_1
# SUCC: EXIT [100.0%] (ABNORMAL,SIBCALL)
.LVL2:
.cfi_endproc
.LFE3:
.size foo, .-foo
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB4:
# tailcall-only.c:46
.loc 1 46 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:49
.loc 1 49 0
call foo
.LVL3:
# tailcall-only.c:50
.loc 1 50 0
addl $1, %eax
.LVL4:
# SUCC: EXIT [100.0%]
# tailcall-only.c:53
.loc 1 53 0
ret
.cfi_endproc
.LFE4:
.size main, .-main
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0x111 # Length of Compilation Unit Info
.value 0x4 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x8 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF1 # DW_AT_producer: "GNU C 4.8.3 20140911 (Red Hat 4.8.3-9) -mtune=generic -march=x86-64 -g -O2"
.byte 0x1 # DW_AT_language
.long .LASF2 # DW_AT_name: "tailcall-only.c"
.long .LASF3 # DW_AT_comp_dir: ""
.long .Ldebug_ranges0+0 # DW_AT_ranges
.quad 0 # DW_AT_low_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x29) DW_TAG_subprogram)
.long .LASF4 # DW_AT_name: "bar_1"
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x15 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x46 # DW_AT_type
.quad .LFB0 # DW_AT_low_pc
.quad .LFE0-.LFB0 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x3 # (DIE (0x46) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.uleb128 0x4 # (DIE (0x4d) DW_TAG_subprogram)
.ascii "bar\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x1b # DW_AT_decl_line
# DW_AT_prototyped
.long 0x46 # DW_AT_type
.quad .LFB1 # DW_AT_low_pc
.quad .LFE1-.LFB1 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0x7c # DW_AT_sibling
.uleb128 0x5 # (DIE (0x6e) DW_TAG_GNU_call_site)
.quad .LVL0 # DW_AT_low_pc
# DW_AT_GNU_tail_call
.long 0x29 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x4d
.uleb128 0x6 # (DIE (0x7c) DW_TAG_subprogram)
.long .LASF0 # DW_AT_name: "foo_1"
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x21 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x46 # DW_AT_type
.quad .LFB2 # DW_AT_low_pc
.quad .LFE2-.LFB2 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0xab # DW_AT_sibling
.uleb128 0x5 # (DIE (0x9d) DW_TAG_GNU_call_site)
.quad .LVL1 # DW_AT_low_pc
# DW_AT_GNU_tail_call
.long 0x4d # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x7c
.uleb128 0x4 # (DIE (0xab) DW_TAG_subprogram)
.ascii "foo\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x27 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x46 # DW_AT_type
.quad .LFB3 # DW_AT_low_pc
.quad .LFE3-.LFB3 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0xda # DW_AT_sibling
.uleb128 0x5 # (DIE (0xcc) DW_TAG_GNU_call_site)
.quad .LVL2 # DW_AT_low_pc
# DW_AT_GNU_tail_call
.long 0x7c # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0xab
.uleb128 0x7 # (DIE (0xda) DW_TAG_subprogram)
# DW_AT_external
.long .LASF5 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x2d # DW_AT_decl_line
# DW_AT_prototyped
.long 0x46 # DW_AT_type
.quad .LFB4 # DW_AT_low_pc
.quad .LFE4-.LFB4 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x8 # (DIE (0xf7) DW_TAG_variable)
.long .LASF6 # DW_AT_name: "answer"
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x2f # DW_AT_decl_line
.long 0x46 # DW_AT_type
.long .LLST0 # DW_AT_location
.uleb128 0x9 # (DIE (0x106) DW_TAG_GNU_call_site)
.quad .LVL3 # DW_AT_low_pc
.long 0xab # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0xda
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x17 # (DW_FORM_sec_offset)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x7 # (DW_FORM_data8)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x7 # (DW_FORM_data8)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x2115 # (DW_AT_GNU_tail_call)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x6 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x7 # (DW_FORM_data8)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x7 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x7 # (DW_FORM_data8)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x8 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x9 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.quad .LVL3 # Location list begin address (*.LLST0)
.quad .LVL4 # Location list end address (*.LLST0)
.value 0x3 # Location expression size
.byte 0x70 # DW_OP_breg0
.sleb128 1
.byte 0x9f # DW_OP_stack_value
.quad .LVL4 # Location list begin address (*.LLST0)
.quad .LFE4 # Location list end address (*.LLST0)
.value 0x1 # Location expression size
.byte 0x50 # DW_OP_reg0
.quad 0 # Location list terminator begin (*.LLST0)
.quad 0 # Location list terminator end (*.LLST0)
.section .debug_aranges,"",@progbits
.long 0x3c # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x8 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 16 byte boundary
.value 0
.quad .Ltext0 # Address
.quad .Letext0-.Ltext0 # Length
.quad .LFB4 # Address
.quad .LFE4-.LFB4 # Length
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0 # Offset 0
.quad .Letext0
.quad .LFB4 # Offset 0x10
.quad .LFE4
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF4:
.string "bar_1"
.LASF2:
.string "tailcall-only.c"
.LASF1:
.string "GNU C 4.8.3 20140911 (Red Hat 4.8.3-9) -mtune=generic -march=x86-64 -g -O2"
.LASF6:
.string "answer"
.LASF5:
.string "main"
.LASF3:
.string ""
.LASF0:
.string "foo_1"
.ident "GCC: (GNU) 4.8.3 20140911 (Red Hat 4.8.3-9)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 10,176
|
gdb/testsuite/gdb.btrace/x86_64-tailcall.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2013-2022 Free Software Foundation, Inc.
Contributed by Intel Corp. <markus.t.metzger@intel.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
This file has been generated using:
gcc -S -O2 -dA -g tailcall.c -o x86_64-tailcall.S */
.file "tailcall.c"
.text
.Ltext0:
.p2align 4,,15
.type bar, @function
bar:
.LFB0:
.file 1 "tailcall.c"
# tailcall.c:22
.loc 1 22 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall.c:24
.loc 1 24 0
movl $42, %eax
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE0:
.size bar, .-bar
.p2align 4,,15
.type foo, @function
foo:
.LFB1:
# tailcall.c:28
.loc 1 28 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall.c:29
.loc 1 29 0
jmp bar
# SUCC: EXIT [100.0%] (ABNORMAL,SIBCALL)
.LVL0:
.cfi_endproc
.LFE1:
.size foo, .-foo
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB2:
# tailcall.c:34
.loc 1 34 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall.c:37
.loc 1 37 0
call foo
.LVL1:
# tailcall.c:38
.loc 1 38 0
addl $1, %eax
.LVL2:
# SUCC: EXIT [100.0%]
# tailcall.c:41
.loc 1 41 0
ret
.cfi_endproc
.LFE2:
.size main, .-main
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0xb3 # Length of Compilation Unit Info
.value 0x4 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x8 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF0 # DW_AT_producer: "GNU C 4.8.3 20140911 (Red Hat 4.8.3-7) -mtune=generic -march=x86-64 -g -O2"
.byte 0x1 # DW_AT_language
.long .LASF1 # DW_AT_name: "tailcall.c"
.long .LASF2 # DW_AT_comp_dir: ""
.long .Ldebug_ranges0+0 # DW_AT_ranges
.quad 0 # DW_AT_low_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x29) DW_TAG_subprogram)
.ascii "bar\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (tailcall.c)
.byte 0x15 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x46 # DW_AT_type
.quad .LFB0 # DW_AT_low_pc
.quad .LFE0-.LFB0 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x3 # (DIE (0x46) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.uleb128 0x4 # (DIE (0x4d) DW_TAG_subprogram)
.ascii "foo\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (tailcall.c)
.byte 0x1b # DW_AT_decl_line
# DW_AT_prototyped
.long 0x46 # DW_AT_type
.quad .LFB1 # DW_AT_low_pc
.quad .LFE1-.LFB1 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0x7c # DW_AT_sibling
.uleb128 0x5 # (DIE (0x6e) DW_TAG_GNU_call_site)
.quad .LVL0 # DW_AT_low_pc
# DW_AT_GNU_tail_call
.long 0x29 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x4d
.uleb128 0x6 # (DIE (0x7c) DW_TAG_subprogram)
# DW_AT_external
.long .LASF3 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (tailcall.c)
.byte 0x21 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x46 # DW_AT_type
.quad .LFB2 # DW_AT_low_pc
.quad .LFE2-.LFB2 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x7 # (DIE (0x99) DW_TAG_variable)
.long .LASF4 # DW_AT_name: "answer"
.byte 0x1 # DW_AT_decl_file (tailcall.c)
.byte 0x23 # DW_AT_decl_line
.long 0x46 # DW_AT_type
.long .LLST0 # DW_AT_location
.uleb128 0x8 # (DIE (0xa8) DW_TAG_GNU_call_site)
.quad .LVL1 # DW_AT_low_pc
.long 0x4d # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x7c
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x17 # (DW_FORM_sec_offset)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x7 # (DW_FORM_data8)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x7 # (DW_FORM_data8)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x2115 # (DW_AT_GNU_tail_call)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x6 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x7 # (DW_FORM_data8)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x7 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x8 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.quad .LVL1 # Location list begin address (*.LLST0)
.quad .LVL2 # Location list end address (*.LLST0)
.value 0x3 # Location expression size
.byte 0x70 # DW_OP_breg0
.sleb128 1
.byte 0x9f # DW_OP_stack_value
.quad .LVL2 # Location list begin address (*.LLST0)
.quad .LFE2 # Location list end address (*.LLST0)
.value 0x1 # Location expression size
.byte 0x50 # DW_OP_reg0
.quad 0 # Location list terminator begin (*.LLST0)
.quad 0 # Location list terminator end (*.LLST0)
.section .debug_aranges,"",@progbits
.long 0x3c # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x8 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 16 byte boundary
.value 0
.quad .Ltext0 # Address
.quad .Letext0-.Ltext0 # Length
.quad .LFB2 # Address
.quad .LFE2-.LFB2 # Length
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0 # Offset 0
.quad .Letext0
.quad .LFB2 # Offset 0x10
.quad .LFE2
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF3:
.string "main"
.LASF1:
.string "tailcall.c"
.LASF0:
.string "GNU C 4.8.3 20140911 (Red Hat 4.8.3-7) -mtune=generic -march=x86-64 -g -O2"
.LASF4:
.string "answer"
.LASF2:
.string ""
.ident "GCC: (GNU) 4.8.3 20140911 (Red Hat 4.8.3-7)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 12,801
|
gdb/testsuite/gdb.btrace/i686-tailcall-only.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2016-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
This file has been generated using:
gcc -m32 -march=i686 -S -O2 -dA -g tailcall-only.c -o i686-tailcall-only.S
*/
.file "tailcall-only.c"
.text
.Ltext0:
.p2align 4,,15
.type bar_1, @function
bar_1:
.LFB0:
.file 1 "tailcall-only.c"
# tailcall-only.c:22
.loc 1 22 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:24
.loc 1 24 0
movl $42, %eax
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE0:
.size bar_1, .-bar_1
.p2align 4,,15
.type bar, @function
bar:
.LFB1:
# tailcall-only.c:28
.loc 1 28 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:29
.loc 1 29 0
jmp bar_1
# SUCC: EXIT [100.0%] (ABNORMAL,SIBCALL)
.LVL0:
.cfi_endproc
.LFE1:
.size bar, .-bar
.p2align 4,,15
.type foo_1, @function
foo_1:
.LFB2:
# tailcall-only.c:34
.loc 1 34 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:35
.loc 1 35 0
jmp bar
# SUCC: EXIT [100.0%] (ABNORMAL,SIBCALL)
.LVL1:
.cfi_endproc
.LFE2:
.size foo_1, .-foo_1
.p2align 4,,15
.type foo, @function
foo:
.LFB3:
# tailcall-only.c:40
.loc 1 40 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:41
.loc 1 41 0
jmp foo_1
# SUCC: EXIT [100.0%] (ABNORMAL,SIBCALL)
.LVL2:
.cfi_endproc
.LFE3:
.size foo, .-foo
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB4:
# tailcall-only.c:46
.loc 1 46 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (FALLTHRU)
# tailcall-only.c:49
.loc 1 49 0
call foo
.LVL3:
# tailcall-only.c:50
.loc 1 50 0
addl $1, %eax
.LVL4:
# SUCC: EXIT [100.0%]
# tailcall-only.c:53
.loc 1 53 0
ret
.cfi_endproc
.LFE4:
.size main, .-main
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0xd5 # Length of Compilation Unit Info
.value 0x4 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x4 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF1 # DW_AT_producer: "GNU C 4.8.3 20140911 (Red Hat 4.8.3-9) -m32 -march=i686 -g -O2"
.byte 0x1 # DW_AT_language
.long .LASF2 # DW_AT_name: "tailcall-only.c"
.long .LASF3 # DW_AT_comp_dir: ""
.long .Ldebug_ranges0+0 # DW_AT_ranges
.long 0 # DW_AT_low_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x25) DW_TAG_subprogram)
.long .LASF4 # DW_AT_name: "bar_1"
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x15 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x3a # DW_AT_type
.long .LFB0 # DW_AT_low_pc
.long .LFE0-.LFB0 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x3 # (DIE (0x3a) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.uleb128 0x4 # (DIE (0x41) DW_TAG_subprogram)
.ascii "bar\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x1b # DW_AT_decl_line
# DW_AT_prototyped
.long 0x3a # DW_AT_type
.long .LFB1 # DW_AT_low_pc
.long .LFE1-.LFB1 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0x64 # DW_AT_sibling
.uleb128 0x5 # (DIE (0x5a) DW_TAG_GNU_call_site)
.long .LVL0 # DW_AT_low_pc
# DW_AT_GNU_tail_call
.long 0x25 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x41
.uleb128 0x6 # (DIE (0x64) DW_TAG_subprogram)
.long .LASF0 # DW_AT_name: "foo_1"
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x21 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x3a # DW_AT_type
.long .LFB2 # DW_AT_low_pc
.long .LFE2-.LFB2 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0x87 # DW_AT_sibling
.uleb128 0x5 # (DIE (0x7d) DW_TAG_GNU_call_site)
.long .LVL1 # DW_AT_low_pc
# DW_AT_GNU_tail_call
.long 0x41 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x64
.uleb128 0x4 # (DIE (0x87) DW_TAG_subprogram)
.ascii "foo\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x27 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x3a # DW_AT_type
.long .LFB3 # DW_AT_low_pc
.long .LFE3-.LFB3 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0xaa # DW_AT_sibling
.uleb128 0x5 # (DIE (0xa0) DW_TAG_GNU_call_site)
.long .LVL2 # DW_AT_low_pc
# DW_AT_GNU_tail_call
.long 0x64 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x87
.uleb128 0x7 # (DIE (0xaa) DW_TAG_subprogram)
# DW_AT_external
.long .LASF5 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x2d # DW_AT_decl_line
# DW_AT_prototyped
.long 0x3a # DW_AT_type
.long .LFB4 # DW_AT_low_pc
.long .LFE4-.LFB4 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x8 # (DIE (0xbf) DW_TAG_variable)
.long .LASF6 # DW_AT_name: "answer"
.byte 0x1 # DW_AT_decl_file (tailcall-only.c)
.byte 0x2f # DW_AT_decl_line
.long 0x3a # DW_AT_type
.long .LLST0 # DW_AT_location
.uleb128 0x9 # (DIE (0xce) DW_TAG_GNU_call_site)
.long .LVL3 # DW_AT_low_pc
.long 0x87 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0xaa
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x17 # (DW_FORM_sec_offset)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x2115 # (DW_AT_GNU_tail_call)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x6 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x7 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x8 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x9 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.long .LVL3 # Location list begin address (*.LLST0)
.long .LVL4 # Location list end address (*.LLST0)
.value 0x3 # Location expression size
.byte 0x70 # DW_OP_breg0
.sleb128 1
.byte 0x9f # DW_OP_stack_value
.long .LVL4 # Location list begin address (*.LLST0)
.long .LFE4 # Location list end address (*.LLST0)
.value 0x1 # Location expression size
.byte 0x50 # DW_OP_reg0
.long 0 # Location list terminator begin (*.LLST0)
.long 0 # Location list terminator end (*.LLST0)
.section .debug_aranges,"",@progbits
.long 0x24 # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x4 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 8 byte boundary
.value 0
.long .Ltext0 # Address
.long .Letext0-.Ltext0 # Length
.long .LFB4 # Address
.long .LFE4-.LFB4 # Length
.long 0
.long 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.long .Ltext0 # Offset 0
.long .Letext0
.long .LFB4 # Offset 0x8
.long .LFE4
.long 0
.long 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF4:
.string "bar_1"
.LASF2:
.string "tailcall-only.c"
.LASF1:
.string "GNU C 4.8.3 20140911 (Red Hat 4.8.3-9) -m32 -march=i686 -g -O2"
.LASF6:
.string "answer"
.LASF5:
.string "main"
.LASF3:
.string ""
.LASF0:
.string "foo_1"
.ident "GCC: (GNU) 4.8.3 20140911 (Red Hat 4.8.3-9)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 8,990
|
gdb/testsuite/gdb.btrace/x86_64-record_goto.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2013-2022 Free Software Foundation, Inc.
Contributed by Intel Corp. <markus.t.metzger@intel.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
This file has been generated using:
gcc -S -dA -g record_goto.c -o x86_64-record_goto.S */
.file "record_goto.c"
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.section .debug_line,"",@progbits
.Ldebug_line0:
.text
.Ltext0:
.globl fun1
.type fun1, @function
fun1:
.LFB0:
.file 1 "record_goto.c"
# record_goto.c:22
.loc 1 22 0
.cfi_startproc
# basic block 2
pushq %rbp
.cfi_def_cfa_offset 16
movq %rsp, %rbp
.cfi_offset 6, -16
.cfi_def_cfa_register 6
# record_goto.c:23
.loc 1 23 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE0:
.size fun1, .-fun1
.globl fun2
.type fun2, @function
fun2:
.LFB1:
# record_goto.c:27
.loc 1 27 0
.cfi_startproc
# basic block 2
pushq %rbp
.cfi_def_cfa_offset 16
movq %rsp, %rbp
.cfi_offset 6, -16
.cfi_def_cfa_register 6
# record_goto.c:28
.loc 1 28 0
call fun1
# record_goto.c:29
.loc 1 29 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE1:
.size fun2, .-fun2
.globl fun3
.type fun3, @function
fun3:
.LFB2:
# record_goto.c:33
.loc 1 33 0
.cfi_startproc
# basic block 2
pushq %rbp
.cfi_def_cfa_offset 16
movq %rsp, %rbp
.cfi_offset 6, -16
.cfi_def_cfa_register 6
# record_goto.c:34
.loc 1 34 0
call fun1
# record_goto.c:35
.loc 1 35 0
call fun2
# record_goto.c:36
.loc 1 36 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE2:
.size fun3, .-fun3
.globl fun4
.type fun4, @function
fun4:
.LFB3:
# record_goto.c:40
.loc 1 40 0
.cfi_startproc
# basic block 2
pushq %rbp
.cfi_def_cfa_offset 16
movq %rsp, %rbp
.cfi_offset 6, -16
.cfi_def_cfa_register 6
# record_goto.c:41
.loc 1 41 0
call fun1
# record_goto.c:42
.loc 1 42 0
call fun2
# record_goto.c:43
.loc 1 43 0
call fun3
# record_goto.c:44
.loc 1 44 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE3:
.size fun4, .-fun4
.globl main
.type main, @function
main:
.LFB4:
# record_goto.c:48
.loc 1 48 0
.cfi_startproc
# basic block 2
pushq %rbp
.cfi_def_cfa_offset 16
movq %rsp, %rbp
.cfi_offset 6, -16
.cfi_def_cfa_register 6
# record_goto.c:49
.loc 1 49 0
call fun4
# record_goto.c:50
.loc 1 50 0
movl $0, %eax
# record_goto.c:51
.loc 1 51 0
leave
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE4:
.size main, .-main
.Letext0:
.section .debug_info
.long 0xbc # Length of Compilation Unit Info
.value 0x3 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x8 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF4 # DW_AT_producer: "GNU C 4.4.4 20100726 (Red Hat 4.4.4-13)"
.byte 0x1 # DW_AT_language
.long .LASF5 # DW_AT_name: "record_goto.c"
.long .LASF6 # DW_AT_comp_dir: ""
.quad .Ltext0 # DW_AT_low_pc
.quad .Letext0 # DW_AT_high_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x2d) DW_TAG_subprogram)
.byte 0x1 # DW_AT_external
.long .LASF0 # DW_AT_name: "fun1"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x15 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB0 # DW_AT_low_pc
.quad .LFE0 # DW_AT_high_pc
.byte 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
.uleb128 0x2 # (DIE (0x48) DW_TAG_subprogram)
.byte 0x1 # DW_AT_external
.long .LASF1 # DW_AT_name: "fun2"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x1a # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB1 # DW_AT_low_pc
.quad .LFE1 # DW_AT_high_pc
.byte 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
.uleb128 0x2 # (DIE (0x63) DW_TAG_subprogram)
.byte 0x1 # DW_AT_external
.long .LASF2 # DW_AT_name: "fun3"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x20 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB2 # DW_AT_low_pc
.quad .LFE2 # DW_AT_high_pc
.byte 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
.uleb128 0x2 # (DIE (0x7e) DW_TAG_subprogram)
.byte 0x1 # DW_AT_external
.long .LASF3 # DW_AT_name: "fun4"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x27 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB3 # DW_AT_low_pc
.quad .LFE3 # DW_AT_high_pc
.byte 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
.uleb128 0x3 # (DIE (0x99) DW_TAG_subprogram)
.byte 0x1 # DW_AT_external
.long .LASF7 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x2f # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.long 0xb8 # DW_AT_type
.quad .LFB4 # DW_AT_low_pc
.quad .LFE4 # DW_AT_high_pc
.byte 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
.uleb128 0x4 # (DIE (0xb8) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.byte 0x0 # end of children of DIE 0xb
.section .debug_abbrev
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x6 # (DW_FORM_data4)
.byte 0x0
.byte 0x0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x0 # DW_children_no
.uleb128 0x3f # (DW_AT_external)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.byte 0x0
.byte 0x0
.uleb128 0x3 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x0 # DW_children_no
.uleb128 0x3f # (DW_AT_external)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.byte 0x0
.byte 0x0
.uleb128 0x4 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0x0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0x0
.byte 0x0
.byte 0x0
.section .debug_pubnames,"",@progbits
.long 0x3b # Length of Public Names Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.long 0xc0 # Compilation Unit Length
.long 0x2d # DIE offset
.ascii "fun1\0" # external name
.long 0x48 # DIE offset
.ascii "fun2\0" # external name
.long 0x63 # DIE offset
.ascii "fun3\0" # external name
.long 0x7e # DIE offset
.ascii "fun4\0" # external name
.long 0x99 # DIE offset
.ascii "main\0" # external name
.long 0x0
.section .debug_aranges,"",@progbits
.long 0x2c # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x8 # Size of Address
.byte 0x0 # Size of Segment Descriptor
.value 0x0 # Pad to 16 byte boundary
.value 0x0
.quad .Ltext0 # Address
.quad .Letext0-.Ltext0 # Length
.quad 0x0
.quad 0x0
.section .debug_str,"MS",@progbits,1
.LASF3:
.string "fun4"
.LASF5:
.string "record_goto.c"
.LASF4:
.string "GNU C 4.4.4 20100726 (Red Hat 4.4.4-13)"
.LASF7:
.string "main"
.LASF1:
.string "fun2"
.LASF0:
.string "fun1"
.LASF6:
.string ""
.LASF2:
.string "fun3"
.ident "GCC: (GNU) 4.4.4 20100726 (Red Hat 4.4.4-13)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 9,903
|
gdb/testsuite/gdb.btrace/i686-record_goto.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2013-2022 Free Software Foundation, Inc.
Contributed by Intel Corp. <markus.t.metzger@intel.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
This file has been generated using:
gcc -S -dA -g record_goto.c -o i686-record_goto.S */
.file "record_goto.c"
.text
.Ltext0:
.globl fun1
.type fun1, @function
fun1:
.LFB0:
.file 1 "record_goto.c"
# record_goto.c:22
.loc 1 22 0
.cfi_startproc
# BLOCK 2 seq:0
# PRED: ENTRY (FALLTHRU)
pushl %ebp
.cfi_def_cfa_offset 8
.cfi_offset 5, -8
movl %esp, %ebp
.cfi_def_cfa_register 5
# record_goto.c:23
.loc 1 23 0
popl %ebp
.cfi_restore 5
.cfi_def_cfa 4, 4
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE0:
.size fun1, .-fun1
.globl fun2
.type fun2, @function
fun2:
.LFB1:
# record_goto.c:27
.loc 1 27 0
.cfi_startproc
# BLOCK 2 seq:0
# PRED: ENTRY (FALLTHRU)
pushl %ebp
.cfi_def_cfa_offset 8
.cfi_offset 5, -8
movl %esp, %ebp
.cfi_def_cfa_register 5
# record_goto.c:28
.loc 1 28 0
call fun1
# record_goto.c:29
.loc 1 29 0
popl %ebp
.cfi_restore 5
.cfi_def_cfa 4, 4
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE1:
.size fun2, .-fun2
.globl fun3
.type fun3, @function
fun3:
.LFB2:
# record_goto.c:33
.loc 1 33 0
.cfi_startproc
# BLOCK 2 seq:0
# PRED: ENTRY (FALLTHRU)
pushl %ebp
.cfi_def_cfa_offset 8
.cfi_offset 5, -8
movl %esp, %ebp
.cfi_def_cfa_register 5
# record_goto.c:34
.loc 1 34 0
call fun1
# record_goto.c:35
.loc 1 35 0
call fun2
# record_goto.c:36
.loc 1 36 0
popl %ebp
.cfi_restore 5
.cfi_def_cfa 4, 4
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE2:
.size fun3, .-fun3
.globl fun4
.type fun4, @function
fun4:
.LFB3:
# record_goto.c:40
.loc 1 40 0
.cfi_startproc
# BLOCK 2 seq:0
# PRED: ENTRY (FALLTHRU)
pushl %ebp
.cfi_def_cfa_offset 8
.cfi_offset 5, -8
movl %esp, %ebp
.cfi_def_cfa_register 5
# record_goto.c:41
.loc 1 41 0
call fun1
# record_goto.c:42
.loc 1 42 0
call fun2
# record_goto.c:43
.loc 1 43 0
call fun3
# record_goto.c:44
.loc 1 44 0
popl %ebp
.cfi_restore 5
.cfi_def_cfa 4, 4
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE3:
.size fun4, .-fun4
.globl main
.type main, @function
main:
.LFB4:
# record_goto.c:48
.loc 1 48 0
.cfi_startproc
# BLOCK 2 seq:0
# PRED: ENTRY (FALLTHRU)
pushl %ebp
.cfi_def_cfa_offset 8
.cfi_offset 5, -8
movl %esp, %ebp
.cfi_def_cfa_register 5
# record_goto.c:49
.loc 1 49 0
call fun4
# record_goto.c:50
.loc 1 50 0
movl $0, %eax
# record_goto.c:51
.loc 1 51 0
popl %ebp
.cfi_restore 5
.cfi_def_cfa 4, 4
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE4:
.size main, .-main
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0x82 # Length of Compilation Unit Info
.value 0x4 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x4 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF4 # DW_AT_producer: "GNU C 4.8.3 20140911 (Red Hat 4.8.3-7) -mtune=generic -march=i686 -g"
.byte 0x1 # DW_AT_language
.long .LASF5 # DW_AT_name: "record_goto.c"
.long .LASF6 # DW_AT_comp_dir: ""
.long .Ltext0 # DW_AT_low_pc
.long .Letext0-.Ltext0 # DW_AT_high_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x25) DW_TAG_subprogram)
# DW_AT_external
.long .LASF0 # DW_AT_name: "fun1"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x15 # DW_AT_decl_line
# DW_AT_prototyped
.long .LFB0 # DW_AT_low_pc
.long .LFE0-.LFB0 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.uleb128 0x3 # (DIE (0x36) DW_TAG_subprogram)
# DW_AT_external
.long .LASF1 # DW_AT_name: "fun2"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x1a # DW_AT_decl_line
# DW_AT_prototyped
.long .LFB1 # DW_AT_low_pc
.long .LFE1-.LFB1 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_tail_call_sites
.uleb128 0x3 # (DIE (0x47) DW_TAG_subprogram)
# DW_AT_external
.long .LASF2 # DW_AT_name: "fun3"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x20 # DW_AT_decl_line
# DW_AT_prototyped
.long .LFB2 # DW_AT_low_pc
.long .LFE2-.LFB2 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_tail_call_sites
.uleb128 0x3 # (DIE (0x58) DW_TAG_subprogram)
# DW_AT_external
.long .LASF3 # DW_AT_name: "fun4"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x27 # DW_AT_decl_line
# DW_AT_prototyped
.long .LFB3 # DW_AT_low_pc
.long .LFE3-.LFB3 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_tail_call_sites
.uleb128 0x4 # (DIE (0x69) DW_TAG_subprogram)
# DW_AT_external
.long .LASF7 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (record_goto.c)
.byte 0x2f # DW_AT_decl_line
# DW_AT_prototyped
.long 0x7e # DW_AT_type
.long .LFB4 # DW_AT_low_pc
.long .LFE4-.LFB4 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_tail_call_sites
.uleb128 0x5 # (DIE (0x7e) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2116 # (DW_AT_GNU_all_tail_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2116 # (DW_AT_GNU_all_tail_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.byte 0
.section .debug_aranges,"",@progbits
.long 0x1c # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x4 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 8 byte boundary
.value 0
.long .Ltext0 # Address
.long .Letext0-.Ltext0 # Length
.long 0
.long 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF3:
.string "fun4"
.LASF4:
.string "GNU C 4.8.3 20140911 (Red Hat 4.8.3-7) -mtune=generic -march=i686 -g"
.LASF7:
.string "main"
.LASF1:
.string "fun2"
.LASF5:
.string "record_goto.c"
.LASF0:
.string "fun1"
.LASF6:
.string ""
.LASF2:
.string "fun3"
.ident "GCC: (GNU) 4.8.3 20140911 (Red Hat 4.8.3-7)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 10,218
|
gdb/testsuite/gdb.base/disasm-optim.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright (C) 2015-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
This file was created with gcc -O2 -g -S -fverbose-asm -dA disasm-optim.c
and then cleaning up the output. */
.file "disasm-optim.c"
.text
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB1:
.file 1 "disasm-optim.c"
# disasm-optim.c:24
.loc 1 24 0
.cfi_startproc
# disasm-optim.c:25
.loc 1 25 0
movl y(%rip), %eax
.LVL0:
.LBB4:
.LBB5:
.file 2 "disasm-optim.h"
# disasm-optim.h:21
.loc 2 21 0
testl %eax, %eax
js .L6
# disasm-optim.h:25
.loc 2 25 0
leal 10(%rax), %edx
testl %eax, %eax
movl $1, %eax
.LVL1:
cmovne %edx, %eax
.LVL2:
.L3:
.LBE5:
.LBE4:
# disasm-optim.c:25
.loc 1 25 0
movl %eax, x(%rip)
# disasm-optim.c:27
.loc 1 27 0
xorl %eax, %eax
ret
.LVL3:
.L6:
.LBB7:
.LBB6:
# disasm-optim.h:22
.loc 2 22 0
addl %eax, %eax
.LVL4:
jmp .L3
.LBE6:
.LBE7:
.cfi_endproc
.LFE1:
.size main, .-main
.comm y,4,4
.comm x,4,4
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0xb1 # Length of Compilation Unit Info
.value 0x4 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x8 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF0 # DW_AT_producer: "GNU C 4.9.2 20150212 (Red Hat 4.9.2-6) -mtune=generic -march=x86-64 -g -O2"
.byte 0x1 # DW_AT_language
.long .LASF1 # DW_AT_name: "disasm-optim.c"
.long .LASF2 # DW_AT_comp_dir: "/main/disassemble3/gdb/testsuite/gdb.base"
.long .Ldebug_ranges0+0x30 # DW_AT_ranges
.quad 0 # DW_AT_low_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x29) DW_TAG_subprogram)
# DW_AT_external
.ascii "foo\0" # DW_AT_name
.byte 0x2 # DW_AT_decl_file (disasm-optim.h)
.byte 0x13 # DW_AT_decl_line
# DW_AT_prototyped
.long 0x43 # DW_AT_type
.byte 0x3 # DW_AT_inline
.long 0x43 # DW_AT_sibling
.uleb128 0x3 # (DIE (0x39) DW_TAG_formal_parameter)
.ascii "a\0" # DW_AT_name
.byte 0x2 # DW_AT_decl_file (disasm-optim.h)
.byte 0x13 # DW_AT_decl_line
.long 0x43 # DW_AT_type
.byte 0 # end of children of DIE 0x29
.uleb128 0x4 # (DIE (0x43) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.uleb128 0x5 # (DIE (0x4a) DW_TAG_subprogram)
# DW_AT_external
.long .LASF3 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (disasm-optim.c)
.byte 0x17 # DW_AT_decl_line
.long 0x43 # DW_AT_type
.quad .LFB1 # DW_AT_low_pc
.quad .LFE1-.LFB1 # DW_AT_high_pc
.uleb128 0x1 # DW_AT_frame_base
.byte 0x9c # DW_OP_call_frame_cfa
# DW_AT_GNU_all_call_sites
.long 0x89 # DW_AT_sibling
.uleb128 0x6 # (DIE (0x6b) DW_TAG_inlined_subroutine)
.long 0x29 # DW_AT_abstract_origin
.quad .LBB4 # DW_AT_entry_pc
.long .Ldebug_ranges0+0 # DW_AT_ranges
.byte 0x1 # DW_AT_call_file (disasm-optim.c)
.byte 0x19 # DW_AT_call_line
.uleb128 0x7 # (DIE (0x7e) DW_TAG_formal_parameter)
.long 0x39 # DW_AT_abstract_origin
.long .LLST0 # DW_AT_location
.byte 0 # end of children of DIE 0x6b
.byte 0 # end of children of DIE 0x4a
.uleb128 0x8 # (DIE (0x89) DW_TAG_variable)
.ascii "x\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (disasm-optim.c)
.byte 0x14 # DW_AT_decl_line
.long 0x9c # DW_AT_type
# DW_AT_external
.uleb128 0x9 # DW_AT_location
.byte 0x3 # DW_OP_addr
.quad x
.uleb128 0x9 # (DIE (0x9c) DW_TAG_volatile_type)
.long 0x43 # DW_AT_type
.uleb128 0x8 # (DIE (0xa1) DW_TAG_variable)
.ascii "y\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (disasm-optim.c)
.byte 0x14 # DW_AT_decl_line
.long 0x9c # DW_AT_type
# DW_AT_external
.uleb128 0x9 # DW_AT_location
.byte 0x3 # DW_OP_addr
.quad y
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x17 # (DW_FORM_sec_offset)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x20 # (DW_AT_inline)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x5 # (TAG: DW_TAG_formal_parameter)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x7 # (DW_FORM_data8)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x18 # (DW_FORM_exprloc)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x6 # (abbrev code)
.uleb128 0x1d # (TAG: DW_TAG_inlined_subroutine)
.byte 0x1 # DW_children_yes
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x52 # (DW_AT_entry_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x17 # (DW_FORM_sec_offset)
.uleb128 0x58 # (DW_AT_call_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x59 # (DW_AT_call_line)
.uleb128 0xb # (DW_FORM_data1)
.byte 0
.byte 0
.uleb128 0x7 # (abbrev code)
.uleb128 0x5 # (TAG: DW_TAG_formal_parameter)
.byte 0 # DW_children_no
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0x17 # (DW_FORM_sec_offset)
.byte 0
.byte 0
.uleb128 0x8 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0x18 # (DW_FORM_exprloc)
.byte 0
.byte 0
.uleb128 0x9 # (abbrev code)
.uleb128 0x35 # (TAG: DW_TAG_volatile_type)
.byte 0 # DW_children_no
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.quad .LVL0 # Location list begin address (*.LLST0)
.quad .LVL1 # Location list end address (*.LLST0)
.value 0x1 # Location expression size
.byte 0x50 # DW_OP_reg0
.quad .LVL1 # Location list begin address (*.LLST0)
.quad .LVL2 # Location list end address (*.LLST0)
.value 0x3 # Location expression size
.byte 0x71 # DW_OP_breg1
.sleb128 -10
.byte 0x9f # DW_OP_stack_value
.quad .LVL3 # Location list begin address (*.LLST0)
.quad .LVL4 # Location list end address (*.LLST0)
.value 0x1 # Location expression size
.byte 0x50 # DW_OP_reg0
.quad 0 # Location list terminator begin (*.LLST0)
.quad 0 # Location list terminator end (*.LLST0)
.section .debug_aranges,"",@progbits
.long 0x2c # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x8 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 16 byte boundary
.value 0
.quad .LFB1 # Address
.quad .LFE1-.LFB1 # Length
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .LBB4 # Offset 0
.quad .LBE4
.quad .LBB7
.quad .LBE7
.quad 0
.quad 0
.quad .LFB1 # Offset 0x30
.quad .LFE1
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF2:
.string "/main/disassemble3/gdb/testsuite/gdb.base"
.LASF1:
.string "disasm-optim.c"
.LASF3:
.string "main"
.LASF0:
.string "GNU C 4.9.2 20150212 (Red Hat 4.9.2-6) -mtune=generic -march=x86-64 -g -O2"
.ident "GCC: (GNU) 4.9.2 20150212 (Red Hat 4.9.2-6)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 3,229
|
gdb/testsuite/gdb.compile/compile-constvar.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2014-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
// gcc -o gdb.base/compile-constvar.S -dA -S -g gdb.base/compile-constvar.c
.file "compile-constvar.c"
.file 1 "gdb.base/compile-constvar.c"
.section .debug_info,"",@progbits
.Ldebug_info0:
.long .Lend-.Lstart # Length of Compilation Unit Info
.Lstart:
.value 0x4 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x8 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF0 # DW_AT_producer: "GNU C 4.8.2 20131212 (Red Hat 4.8.2-7) -mtune=generic -march=x86-64 -g"
.byte 0x1 # DW_AT_language
.long .LASF1 # DW_AT_name: "gdb.base/compile-constvar.c"
.long .LASF2 # DW_AT_comp_dir: "/home/jkratoch/redhat/gdb-gdbjit/gdb/testsuite"
.uleb128 0x2 # (DIE (0x1d) DW_TAG_variable)
.long .LASF3 # DW_AT_name: "constvar"
.long .Linttype-.Ldebug_info0 # DW_AT_type
# DW_AT_external
.byte 0x3 # DW_AT_const_value
.Linttype:
.uleb128 0x3 # (DIE (0x32) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.byte 0 # end of children of DIE 0xb
.Lend:
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x3f # (DW_AT_external)
.uleb128 0x19 # (DW_FORM_flag_present)
.uleb128 0x1c # (DW_AT_const_value)
.uleb128 0xb # (DW_FORM_data1)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.byte 0
.section .debug_str,"MS",@progbits,1
.LASF1:
.string "gdb.base/compile-constvar.c"
.LASF3:
.string "constvar"
.LASF2:
.string ""
.LASF0:
.string "GNU C 4.8.2 20131212 (Red Hat 4.8.2-7) -mtune=generic -march=x86-64 -g"
.ident "GCC: (GNU) 4.8.2 20131212 (Red Hat 4.8.2-7)"
|
stsp/binutils-ia16
| 67,586
|
gdb/testsuite/gdb.disasm/t03_add.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;arith_1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
add.b #0x12:8,r1h ;8112
add.b #0x12:8,@er1 ;7d108012
add.b #0x12:8,@(0x3:2,er1) ;017768188012
add.b #0x12:8,@er1+ ;01746c188012
add.b #0x12:8,@-er1 ;01776c188012
add.b #0x12:8,@+er1 ;01756c188012
add.b #0x12:8,@er1- ;01766c188012
add.b #0x12:8,@(0x1234:16,er1) ;01746e1812348012
add.b #0x12:8,@(0x12345678:32,er1) ;78146a28123456788012
add.b #0x12:8,@(0x1234:16,r2l.b) ;01756e2812348012
add.b #0x12:8,@(0x1234:16,r2.w) ;01766e2812348012
add.b #0x12:8,@(0x1234:16,er2.l) ;01776e2812348012
add.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a28123456788012
add.b #0x12:8,@(0x12345678:32,r2.w) ;78266a28123456788012
add.b #0x12:8,@(0x12345678:32,er2.l) ;78276a28123456788012
add.b #0x12:8,@0xffffff9a:8 ;7f9a8012
add.b #0x12:8,@0x1234:16 ;6a1812348012
add.b #0x12:8,@0x12345678:32 ;6a38123456788012
add.b r3h,r1h ;0831
add.b r3h,@er1 ;7d100830
add.b r3h,@(0x3:2,er1) ;01793113
add.b r3h,@er1+ ;01798113
add.b r3h,@-er1 ;0179b113
add.b r3h,@+er1 ;01799113
add.b r3h,@er1- ;0179a113
add.b r3h,@(0x1234:16,er1) ;0179c1131234
add.b r3h,@(0x12345678:32,er1) ;0179c91312345678
add.b r3h,@(0x1234:16,r2l.b) ;0179d2131234
add.b r3h,@(0x1234:16,r2.w) ;0179e2131234
add.b r3h,@(0x1234:16,er2.l) ;0179f2131234
add.b r3h,@(0x12345678:32,r2l.b) ;0179da1312345678
add.b r3h,@(0x12345678:32,r2.w) ;0179ea1312345678
add.b r3h,@(0x12345678:32,er2.l) ;0179fa1312345678
add.b r3h,@0xffffff12:8 ;7f120830
add.b r3h,@0x1234:16 ;6a1812340830
add.b r3h,@0x12345678:32 ;6a38123456780830
add.b @er3,r1h ;7c300801
add.b @(0x3:2,er3),r1h ;017a3311
add.b @er3+,r1h ;017a8311
add.b @-er3,r1h ;017ab311
add.b @+er3,r1h ;017a9311
add.b @er3-,r1h ;017aa311
add.b @(0x1234:16,er1),r1h ;017ac1111234
add.b @(0x12345678:32,er1),r1h ;017ac91112345678
add.b @(0x1234:16,r2l.b),r1h ;017ad2111234
add.b @(0x1234:16,r2.w),r1h ;017ae2111234
add.b @(0x1234:16,er2.l),r1h ;017af2111234
add.b @(0x12345678:32,r2l.b),r1h ;017ada1112345678
add.b @(0x12345678:32,r2.w),r1h ;017aea1112345678
add.b @(0x12345678:32,er2.l),r1h ;017afa1112345678
add.b @0xffffff12:8,r1h ;7e120801
add.b @0x1234:16,r1h ;6a1012340801
add.b @0x12345678:32,r1h ;6a30123456780801
add.b @er3,@er1 ;7c350110
add.b @er3,@(3:2,er1) ;7c353110
add.b @er3,@-er1 ;7c35b110
add.b @er3,@er1+ ;7c358110
add.b @er3,@er1- ;7c35a110
add.b @er3,@+er1 ;7c359110
add.b @er3,@(0xffff9abc:16,er1) ;7c35c1109abc
add.b @er3,@(0x9abcdef0:32,er1) ;7c35c9109abcdef0
add.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2109abc
add.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2109abc
add.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2109abc
add.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da109abcdef0
add.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea109abcdef0
add.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa109abcdef0
add.b @er3,@0xffff9abc:16 ;7c3540109abc
add.b @er3,@0x9abcdef0:32 ;7c3548109abcdef0
add.b @-er3,@er1 ;01776c3c0110
add.b @-er3,@(3:2,er1) ;01776c3c3110
add.b @-er3,@-er1 ;01776c3cb110
add.b @-er3,@er1+ ;01776c3c8110
add.b @-er3,@er1- ;01776c3ca110
add.b @-er3,@+er1 ;01776c3c9110
add.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1109abc
add.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9109abcdef0
add.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2109abc
add.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2109abc
add.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2109abc
add.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda109abcdef0
add.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea109abcdef0
add.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa109abcdef0
add.b @-er3,@0xffff9abc:16 ;01776c3c40109abc
add.b @-er3,@0x9abcdef0:32 ;01776c3c48109abcdef0
add.b @er3+,@er1 ;01746c3c0110
add.b @er3+,@(3:2,er1) ;01746c3c3110
add.b @er3+,@-er1 ;01746c3cb110
add.b @er3+,@er1+ ;01746c3c8110
add.b @er3+,@er1- ;01746c3ca110
add.b @er3+,@+er1 ;01746c3c9110
add.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1109abc
add.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9109abcdef0
add.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2109abc
add.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2109abc
add.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2109abc
add.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda109abcdef0
add.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea109abcdef0
add.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa109abcdef0
add.b @er3+,@0xffff9abc:16 ;01746c3c40109abc
add.b @er3+,@0x9abcdef0:32 ;01746c3c48109abcdef0
add.b @er3-,@er1 ;01766c3c0110
add.b @er3-,@(3:2,er1) ;01766c3c3110
add.b @er3-,@-er1 ;01766c3cb110
add.b @er3-,@er1+ ;01766c3c8110
add.b @er3-,@er1- ;01766c3ca110
add.b @er3-,@+er1 ;01766c3c9110
add.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1109abc
add.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9109abcdef0
add.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2109abc
add.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2109abc
add.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2109abc
add.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda109abcdef0
add.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea109abcdef0
add.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa109abcdef0
add.b @er3-,@0xffff9abc:16 ;01766c3c40109abc
add.b @er3-,@0x9abcdef0:32 ;01766c3c48109abcdef0
add.b @+er3,@er1 ;01756c3c0110
add.b @+er3,@(3:2,er1) ;01756c3c3110
add.b @+er3,@-er1 ;01756c3cb110
add.b @+er3,@er1+ ;01756c3c8110
add.b @+er3,@er1- ;01756c3ca110
add.b @+er3,@+er1 ;01756c3c9110
add.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1109abc
add.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9109abcdef0
add.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2109abc
add.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2109abc
add.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2109abc
add.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda109abcdef0
add.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea109abcdef0
add.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa109abcdef0
add.b @+er3,@0xffff9abc:16 ;01756c3c40109abc
add.b @+er3,@0x9abcdef0:32 ;01756c3c48109abcdef0
add.b @(0x1234:16,er3),@er1 ;01746e3c12340110
add.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343110
add.b @(0x1234:16,er3),@-er1 ;01746e3c1234b110
add.b @(0x1234:16,er3),@er1+ ;01746e3c12348110
add.b @(0x1234:16,er3),@er1- ;01746e3c1234a110
add.b @(0x1234:16,er3),@+er1 ;01746e3c12349110
add.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1109abc
add.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9109abcdef0
add.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2109abc
add.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2109abc
add.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2109abc
add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da109abcdef0
add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea109abcdef0
add.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa109abcdef0
add.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440109abc
add.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448109abcdef0
add.b @(0x12345678:32,er3),@er1 ;78346a2c123456780110
add.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783110
add.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b110
add.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788110
add.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a110
add.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789110
add.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1109abc
add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9109abcdef0
add.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2109abc
add.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2109abc
add.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2109abc
add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da109abcdef0
add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea109abcdef0
add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa109abcdef0
add.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840109abc
add.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848109abcdef0
add.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340110
add.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343110
add.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b110
add.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348110
add.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a110
add.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349110
add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1109abc
add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9109abcdef0
add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2109abc
add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2109abc
add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2109abc
add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da109abcdef0
add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea109abcdef0
add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa109abcdef0
add.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440109abc
add.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448109abcdef0
add.b @(0x1234:16,r3.w),@er1 ;01766e3c12340110
add.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343110
add.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b110
add.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348110
add.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a110
add.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349110
add.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1109abc
add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9109abcdef0
add.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2109abc
add.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2109abc
add.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2109abc
add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da109abcdef0
add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea109abcdef0
add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa109abcdef0
add.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440109abc
add.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448109abcdef0
add.b @(0x1234:16,er3.l),@er1 ;01776e3c12340110
add.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343110
add.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b110
add.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348110
add.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a110
add.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349110
add.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1109abc
add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9109abcdef0
add.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2109abc
add.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2109abc
add.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2109abc
add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da109abcdef0
add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea109abcdef0
add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa109abcdef0
add.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440109abc
add.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448109abcdef0
add.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780110
add.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783110
add.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b110
add.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788110
add.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a110
add.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789110
add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1109abc
add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9109abcdef0
add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2109abc
add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2109abc
add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2109abc
add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da109abcdef0
add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea109abcdef0
add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa109abcdef0
add.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840109abc
add.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848109abcdef0
add.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780110
add.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783110
add.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b110
add.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788110
add.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a110
add.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789110
add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1109abc
add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9109abcdef0
add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2109abc
add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2109abc
add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2109abc
add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da109abcdef0
add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea109abcdef0
add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa109abcdef0
add.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840109abc
add.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848109abcdef0
add.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780110
add.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783110
add.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b110
add.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788110
add.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a110
add.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789110
add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1109abc
add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9109abcdef0
add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2109abc
add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2109abc
add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2109abc
add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da109abcdef0
add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea109abcdef0
add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa109abcdef0
add.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840109abc
add.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848109abcdef0
add.b @0x1234:16,@er1 ;6a1512340110
add.b @0x1234:16,@(3:2,er1) ;6a1512343110
add.b @0x1234:16,@-er1 ;6a151234b110
add.b @0x1234:16,@er1+ ;6a1512348110
add.b @0x1234:16,@er1- ;6a151234a110
add.b @0x1234:16,@+er1 ;6a1512349110
add.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1109abc
add.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9109abcdef0
add.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2109abc
add.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2109abc
add.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2109abc
add.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da109abcdef0
add.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea109abcdef0
add.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa109abcdef0
add.b @0x1234:16,@0xffff9abc:16 ;6a15123440109abc
add.b @0x1234:16,@0x9abcdef0:32 ;6a15123448109abcdef0
add.b @0x12345678:32,@er1 ;6a35123456780110
add.b @0x12345678:32,@(3:2,er1) ;6a35123456783110
add.b @0x12345678:32,@-er1 ;6a3512345678b110
add.b @0x12345678:32,@er1+ ;6a35123456788110
add.b @0x12345678:32,@er1- ;6a3512345678a110
add.b @0x12345678:32,@+er1 ;6a35123456789110
add.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1109abc
add.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9109abcdef0
add.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2109abc
add.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2109abc
add.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2109abc
add.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da109abcdef0
add.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea109abcdef0
add.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa109abcdef0
add.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840109abc
add.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848109abcdef0
add.w #0x1234:16,r1 ;79111234
add.w #0x7:3,r2 ;0a72
add.w #0x1234:16,@er1 ;015e01101234
add.w #0x1234:16,@(0x6:2,er1) ;015e31101234
add.w #0x1234:16,@er1+ ;015e81101234
add.w #0x1234:16,@-er1 ;015eb1101234
add.w #0x1234:16,@+er1 ;015e91101234
add.w #0x1234:16,@er1- ;015ea1101234
add.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1109abc1234
add.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9109abcdef01234
add.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2109abc1234
add.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2109abc1234
add.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2109abc1234
add.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda109abcdef01234
add.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea109abcdef01234
add.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa109abcdef01234
add.w #0x1234:16,@0xffff9abc:16 ;015e40109abc1234
add.w #0x1234:16,@0x9abcdef0:32 ;015e48109abcdef01234
add.w #0x7:3,@er1 ;7d900a70
add.w #0x7:3,@0x1234:16 ;6b1812340a70
add.w #0x7:3,@0x12345678:32 ;6b38123456780a70
add.w r3,r1 ;0931
add.w r3,@er1 ;7d900930
add.w r3,@(0x6:2,er1) ;01593113
add.w r3,@er1+ ;01598113
add.w r3,@-er1 ;0159b113
add.w r3,@+er1 ;01599113
add.w r3,@er1- ;0159a113
add.w r3,@(0x1234:16,er1) ;0159c1131234
add.w r3,@(0x12345678:32,er1) ;0159c91312345678
add.w r3,@(0x1234:16,r2l.b) ;0159d2131234
add.w r3,@(0x1234:16,r2.w) ;0159e2131234
add.w r3,@(0x1234:16,er2.l) ;0159f2131234
add.w r3,@(0x12345678:32,r2l.b) ;0159da1312345678
add.w r3,@(0x12345678:32,r2.w) ;0159ea1312345678
add.w r3,@(0x12345678:32,er2.l) ;0159fa1312345678
add.w r3,@0x1234:16 ;6b1812340930
add.w r3,@0x12345678:32 ;6b38123456780930
add.w @er3,r1 ;7cb00901
add.w @(0x6:2,er1),r1 ;015a3111
add.w @er3+,r1 ;015a8311
add.w @-er3,r1 ;015ab311
add.w @+er3,r1 ;015a9311
add.w @er3-,r1 ;015aa311
add.w @(0x1234:16,er1),r1 ;015ac1111234
add.w @(0x12345678:32,er1),r1 ;015ac91112345678
add.w @(0x1234:16,r2l.b),r1 ;015ad2111234
add.w @(0x1234:16,r2.w),r1 ;015ae2111234
add.w @(0x1234:16,er2.l),r1 ;015af2111234
add.w @(0x12345678:32,r2l.b),r1 ;015ada1112345678
add.w @(0x12345678:32,r2.w),r1 ;015aea1112345678
add.w @(0x12345678:32,er2.l),r1 ;015afa1112345678
add.w @0x1234:16,r1 ;6b1012340901
add.w @0x12345678:32,r1 ;6b30123456780901
add.w @er3,@er1 ;7cb50110
add.w @er3,@(6:2,er1) ;7cb53110
add.w @er3,@-er1 ;7cb5b110
add.w @er3,@er1+ ;7cb58110
add.w @er3,@er1- ;7cb5a110
add.w @er3,@+er1 ;7cb59110
add.w @er3,@(0xffff9abc:16,er1) ;7cb5c1109abc
add.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9109abcdef0
add.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2109abc
add.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2109abc
add.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2109abc
add.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da109abcdef0
add.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea109abcdef0
add.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa109abcdef0
add.w @er3,@0xffff9abc:16 ;7cb540109abc
add.w @er3,@0x9abcdef0:32 ;7cb548109abcdef0
add.w @-er3,@er1 ;01576d3c0110
add.w @-er3,@(6:2,er1) ;01576d3c3110
add.w @-er3,@-er1 ;01576d3cb110
add.w @-er3,@er1+ ;01576d3c8110
add.w @-er3,@er1- ;01576d3ca110
add.w @-er3,@+er1 ;01576d3c9110
add.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1109abc
add.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9109abcdef0
add.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2109abc
add.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2109abc
add.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2109abc
add.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda109abcdef0
add.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea109abcdef0
add.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa109abcdef0
add.w @-er3,@0xffff9abc:16 ;01576d3c40109abc
add.w @-er3,@0x9abcdef0:32 ;01576d3c48109abcdef0
add.w @er3+,@er1 ;01546d3c0110
add.w @er3+,@(6:2,er1) ;01546d3c3110
add.w @er3+,@-er1 ;01546d3cb110
add.w @er3+,@er1+ ;01546d3c8110
add.w @er3+,@er1- ;01546d3ca110
add.w @er3+,@+er1 ;01546d3c9110
add.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1109abc
add.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9109abcdef0
add.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2109abc
add.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2109abc
add.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2109abc
add.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda109abcdef0
add.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea109abcdef0
add.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa109abcdef0
add.w @er3+,@0xffff9abc:16 ;01546d3c40109abc
add.w @er3+,@0x9abcdef0:32 ;01546d3c48109abcdef0
add.w @er3-,@er1 ;01566d3c0110
add.w @er3-,@(6:2,er1) ;01566d3c3110
add.w @er3-,@-er1 ;01566d3cb110
add.w @er3-,@er1+ ;01566d3c8110
add.w @er3-,@er1- ;01566d3ca110
add.w @er3-,@+er1 ;01566d3c9110
add.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1109abc
add.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9109abcdef0
add.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2109abc
add.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2109abc
add.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2109abc
add.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda109abcdef0
add.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea109abcdef0
add.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa109abcdef0
add.w @er3-,@0xffff9abc:16 ;01566d3c40109abc
add.w @er3-,@0x9abcdef0:32 ;01566d3c48109abcdef0
add.w @+er3,@er1 ;01556d3c0110
add.w @+er3,@(6:2,er1) ;01556d3c3110
add.w @+er3,@-er1 ;01556d3cb110
add.w @+er3,@er1+ ;01556d3c8110
add.w @+er3,@er1- ;01556d3ca110
add.w @+er3,@+er1 ;01556d3c9110
add.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1109abc
add.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9109abcdef0
add.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2109abc
add.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2109abc
add.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2109abc
add.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda109abcdef0
add.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea109abcdef0
add.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa109abcdef0
add.w @+er3,@0xffff9abc:16 ;01556d3c40109abc
add.w @+er3,@0x9abcdef0:32 ;01556d3c48109abcdef0
add.w @(0x1234:16,er3),@er1 ;01546f3c12340110
add.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343110
add.w @(0x1234:16,er3),@-er1 ;01546f3c1234b110
add.w @(0x1234:16,er3),@er1+ ;01546f3c12348110
add.w @(0x1234:16,er3),@er1- ;01546f3c1234a110
add.w @(0x1234:16,er3),@+er1 ;01546f3c12349110
add.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1109abc
add.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9109abcdef0
add.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2109abc
add.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2109abc
add.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2109abc
add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da109abcdef0
add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea109abcdef0
add.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa109abcdef0
add.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440109abc
add.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448109abcdef0
add.w @(0x12345678:32,er3),@er1 ;78346b2c123456780110
add.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783110
add.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b110
add.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788110
add.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a110
add.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789110
add.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1109abc
add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9109abcdef0
add.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2109abc
add.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2109abc
add.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2109abc
add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da109abcdef0
add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea109abcdef0
add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa109abcdef0
add.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840109abc
add.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848109abcdef0
add.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340110
add.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343110
add.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b110
add.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348110
add.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a110
add.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349110
add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1109abc
add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9109abcdef0
add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2109abc
add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2109abc
add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2109abc
add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da109abcdef0
add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea109abcdef0
add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa109abcdef0
add.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440109abc
add.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448109abcdef0
add.w @(0x1234:16,r3.w),@er1 ;01566f3c12340110
add.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343110
add.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b110
add.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348110
add.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a110
add.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349110
add.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1109abc
add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9109abcdef0
add.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2109abc
add.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2109abc
add.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2109abc
add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da109abcdef0
add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea109abcdef0
add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa109abcdef0
add.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440109abc
add.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448109abcdef0
add.w @(0x1234:16,er3.l),@er1 ;01576f3c12340110
add.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343110
add.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b110
add.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348110
add.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a110
add.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349110
add.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1109abc
add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9109abcdef0
add.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2109abc
add.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2109abc
add.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2109abc
add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da109abcdef0
add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea109abcdef0
add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa109abcdef0
add.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440109abc
add.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448109abcdef0
add.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780110
add.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783110
add.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b110
add.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788110
add.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a110
add.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789110
add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1109abc
add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9109abcdef0
add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2109abc
add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2109abc
add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2109abc
add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da109abcdef0
add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea109abcdef0
add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa109abcdef0
add.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840109abc
add.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848109abcdef0
add.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780110
add.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783110
add.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b110
add.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788110
add.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a110
add.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789110
add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1109abc
add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9109abcdef0
add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2109abc
add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2109abc
add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2109abc
add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da109abcdef0
add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea109abcdef0
add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa109abcdef0
add.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840109abc
add.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848109abcdef0
add.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780110
add.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783110
add.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b110
add.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788110
add.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a110
add.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789110
add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1109abc
add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9109abcdef0
add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2109abc
add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2109abc
add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2109abc
add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da109abcdef0
add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea109abcdef0
add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa109abcdef0
add.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840109abc
add.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848109abcdef0
add.w @0x1234:16,@er1 ;6b1512340110
add.w @0x1234:16,@(6:2,er1) ;6b1512343110
add.w @0x1234:16,@-er1 ;6b151234b110
add.w @0x1234:16,@er1+ ;6b1512348110
add.w @0x1234:16,@er1- ;6b151234a110
add.w @0x1234:16,@+er1 ;6b1512349110
add.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1109abc
add.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9109abcdef0
add.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2109abc
add.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2109abc
add.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2109abc
add.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da109abcdef0
add.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea109abcdef0
add.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa109abcdef0
add.w @0x1234:16,@0xffff9abc:16 ;6b15123440109abc
add.w @0x1234:16,@0x9abcdef0:32 ;6b15123448109abcdef0
add.w @0x12345678:32,@er1 ;6b35123456780110
add.w @0x12345678:32,@(6:2,er1) ;6b35123456783110
add.w @0x12345678:32,@-er1 ;6b3512345678b110
add.w @0x12345678:32,@er1+ ;6b35123456788110
add.w @0x12345678:32,@er1- ;6b3512345678a110
add.w @0x12345678:32,@+er1 ;6b35123456789110
add.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1109abc
add.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9109abcdef0
add.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2109abc
add.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2109abc
add.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2109abc
add.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da109abcdef0
add.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea109abcdef0
add.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa109abcdef0
add.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840109abc
add.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848109abcdef0
add.l #0x12345678:32,er1 ;7a1112345678
add.l #0x1234:16,er1 ;7a191234
add.l #0x7:3,er2 ;0afa
add.l #0x12345678:32,@er1 ;010e011812345678
add.l #0x12345678:32,@(0xc:2,er1) ;010e311812345678
add.l #0x12345678:32,@er1+ ;010e811812345678
add.l #0x12345678:32,@-er1 ;010eb11812345678
add.l #0x12345678:32,@+er1 ;010e911812345678
add.l #0x12345678:32,@er1- ;010ea11812345678
add.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1189abc12345678
add.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9189abcdef012345678
add.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2189abc12345678
add.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2189abc12345678
add.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2189abc12345678
add.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda189abcdef012345678
add.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea189abcdef012345678
add.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa189abcdef012345678
add.l #0x12345678:32,@0xffff9abc:16 ;010e40189abc12345678
add.l #0x12345678:32,@0x9abcdef0:32 ;010e48189abcdef012345678
add.l #0x1234:16,@er1 ;010e01101234
add.l #0x1234:16,@(0xc:2,er1) ;010e31101234
add.l #0x1234:16,@er1+ ;010e81101234
add.l #0x1234:16,@-er1 ;010eb1101234
add.l #0x1234:16,@+er1 ;010e91101234
add.l #0x1234:16,@er1- ;010ea1101234
add.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1109abc1234
add.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9109abcdef01234
add.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2109abc1234
add.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2109abc1234
add.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2109abc1234
add.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda109abcdef01234
add.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea109abcdef01234
add.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa109abcdef01234
add.l #0x1234:16,@0xffff9abc:16 ;010e40109abc1234
add.l #0x1234:16,@0x9abcdef0:32 ;010e48109abcdef01234
add.l er3,er1 ;0ab1
add.l er3,@er1 ;01090113
add.l er3,@(0xc:2,er1) ;01093113
add.l er3,@er1+ ;01098113
add.l er3,@-er1 ;0109b113
add.l er3,@+er1 ;01099113
add.l er3,@er1- ;0109a113
add.l er3,@(0x1234:16,er1) ;0109c1131234
add.l er3,@(0x12345678:32,er1) ;0109c91312345678
add.l er3,@(0x1234:16,r2l.b) ;0109d2131234
add.l er3,@(0x1234:16,r2.w) ;0109e2131234
add.l er3,@(0x1234:16,er2.l) ;0109f2131234
add.l er3,@(0x12345678:32,r2l.b) ;0109da1312345678
add.l er3,@(0x12345678:32,r2.w) ;0109ea1312345678
add.l er3,@(0x12345678:32,er2.l) ;0109fa1312345678
add.l er3,@0x1234:16 ;010940131234
add.l er3,@0x12345678:32 ;0109481312345678
add.l @er3,er1 ;010a0311
add.l @(0xc:2,er3),er1 ;010a3311
add.l @er3+,er1 ;010a8311
add.l @-er3,er1 ;010ab311
add.l @+er3,er1 ;010a9311
add.l @er3-,er1 ;010aa311
add.l @(0x1234:16,er1),er1 ;010ac1111234
add.l @(0x12345678:32,er1),er1 ;010ac91112345678
add.l @(0x1234:16,r2l.b),er1 ;010ad2111234
add.l @(0x1234:16,r2.w),er1 ;010ae2111234
add.l @(0x1234:16,er2.l),er1 ;010af2111234
add.l @(0x12345678:32,r2l.b),er1 ;010ada1112345678
add.l @(0x12345678:32,r2.w),er1 ;010aea1112345678
add.l @(0x12345678:32,er2.l),er1 ;010afa1112345678
add.l @0x1234:16,er1 ;010a40111234
add.l @0x12345678:32,er1 ;010a481112345678
add.l @er3,@er1 ;0104693c0110
add.l @er3,@(0xc:2,er1) ;0104693c3110
add.l @er3,@-er1 ;0104693cb110
add.l @er3,@er1+ ;0104693c8110
add.l @er3,@er1- ;0104693ca110
add.l @er3,@+er1 ;0104693c9110
add.l @er3,@(0xffff9abc:16,er1) ;0104693cc1109abc
add.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9109abcdef0
add.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2109abc
add.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2109abc
add.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2109abc
add.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda109abcdef0
add.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea109abcdef0
add.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa109abcdef0
add.l @er3,@0xffff9abc:16 ;0104693c40109abc
add.l @er3,@0x9abcdef0:32 ;0104693c48109abcdef0
add.l @(0xc:2,er3),@er1 ;0107693c0110
add.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3110
add.l @(0xc:2,er3),@-er1 ;0107693cb110
add.l @(0xc:2,er3),@er1+ ;0107693c8110
add.l @(0xc:2,er3),@er1- ;0107693ca110
add.l @(0xc:2,er3),@+er1 ;0107693c9110
add.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1109abc
add.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9109abcdef0
add.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2109abc
add.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2109abc
add.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2109abc
add.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda109abcdef0
add.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea109abcdef0
add.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa109abcdef0
add.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40109abc
add.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48109abcdef0
add.l @-er3,@er1 ;01076d3c0110
add.l @-er3,@(0xc:2,er1) ;01076d3c3110
add.l @-er3,@-er1 ;01076d3cb110
add.l @-er3,@er1+ ;01076d3c8110
add.l @-er3,@er1- ;01076d3ca110
add.l @-er3,@+er1 ;01076d3c9110
add.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1109abc
add.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9109abcdef0
add.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2109abc
add.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2109abc
add.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2109abc
add.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda109abcdef0
add.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea109abcdef0
add.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa109abcdef0
add.l @-er3,@0xffff9abc:16 ;01076d3c40109abc
add.l @-er3,@0x9abcdef0:32 ;01076d3c48109abcdef0
add.l @er3+,@er1 ;01046d3c0110
add.l @er3+,@(0xc:2,er1) ;01046d3c3110
add.l @er3+,@-er1 ;01046d3cb110
add.l @er3+,@er1+ ;01046d3c8110
add.l @er3+,@er1- ;01046d3ca110
add.l @er3+,@+er1 ;01046d3c9110
add.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1109abc
add.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9109abcdef0
add.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2109abc
add.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2109abc
add.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2109abc
add.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda109abcdef0
add.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea109abcdef0
add.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa109abcdef0
add.l @er3+,@0xffff9abc:16 ;01046d3c40109abc
add.l @er3+,@0x9abcdef0:32 ;01046d3c48109abcdef0
add.l @er3-,@er1 ;01066d3c0110
add.l @er3-,@(0xc:2,er1) ;01066d3c3110
add.l @er3-,@-er1 ;01066d3cb110
add.l @er3-,@er1+ ;01066d3c8110
add.l @er3-,@er1- ;01066d3ca110
add.l @er3-,@+er1 ;01066d3c9110
add.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1109abc
add.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9109abcdef0
add.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2109abc
add.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2109abc
add.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2109abc
add.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda109abcdef0
add.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea109abcdef0
add.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa109abcdef0
add.l @er3-,@0xffff9abc:16 ;01066d3c40109abc
add.l @er3-,@0x9abcdef0:32 ;01066d3c48109abcdef0
add.l @+er3,@er1 ;01056d3c0110
add.l @+er3,@(0xc:2,er1) ;01056d3c3110
add.l @+er3,@-er1 ;01056d3cb110
add.l @+er3,@er1+ ;01056d3c8110
add.l @+er3,@er1- ;01056d3ca110
add.l @+er3,@+er1 ;01056d3c9110
add.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1109abc
add.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9109abcdef0
add.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2109abc
add.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2109abc
add.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2109abc
add.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda109abcdef0
add.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea109abcdef0
add.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa109abcdef0
add.l @+er3,@0xffff9abc:16 ;01056d3c40109abc
add.l @+er3,@0x9abcdef0:32 ;01056d3c48109abcdef0
add.l @(0x1234:16,er3),@er1 ;01046f3c12340110
add.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343110
add.l @(0x1234:16,er3),@-er1 ;01046f3c1234b110
add.l @(0x1234:16,er3),@er1+ ;01046f3c12348110
add.l @(0x1234:16,er3),@er1- ;01046f3c1234a110
add.l @(0x1234:16,er3),@+er1 ;01046f3c12349110
add.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1109abc
add.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9109abcdef0
add.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2109abc
add.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2109abc
add.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2109abc
add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da109abcdef0
add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea109abcdef0
add.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa109abcdef0
add.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440109abc
add.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448109abcdef0
add.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780110
add.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783110
add.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b110
add.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788110
add.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a110
add.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789110
add.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1109abc
add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9109abcdef0
add.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2109abc
add.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2109abc
add.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2109abc
add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da109abcdef0
add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea109abcdef0
add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa109abcdef0
add.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840109abc
add.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848109abcdef0
add.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340110
add.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343110
add.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b110
add.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348110
add.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a110
add.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349110
add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1109abc
add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9109abcdef0
add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2109abc
add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2109abc
add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2109abc
add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da109abcdef0
add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea109abcdef0
add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa109abcdef0
add.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440109abc
add.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448109abcdef0
add.l @(0x1234:16,r3.w),@er1 ;01066f3c12340110
add.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343110
add.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b110
add.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348110
add.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a110
add.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349110
add.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1109abc
add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9109abcdef0
add.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2109abc
add.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2109abc
add.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2109abc
add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da109abcdef0
add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea109abcdef0
add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa109abcdef0
add.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440109abc
add.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448109abcdef0
add.l @(0x1234:16,er3.l),@er1 ;01076f3c12340110
add.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343110
add.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b110
add.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348110
add.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a110
add.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349110
add.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1109abc
add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9109abcdef0
add.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2109abc
add.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2109abc
add.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2109abc
add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da109abcdef0
add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea109abcdef0
add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa109abcdef0
add.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440109abc
add.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448109abcdef0
add.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780110
add.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783110
add.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b110
add.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788110
add.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a110
add.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789110
add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1109abc
add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9109abcdef0
add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2109abc
add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2109abc
add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2109abc
add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da109abcdef0
add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea109abcdef0
add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa109abcdef0
add.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840109abc
add.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848109abcdef0
add.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780110
add.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783110
add.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b110
add.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788110
add.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a110
add.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789110
add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1109abc
add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9109abcdef0
add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2109abc
add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2109abc
add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2109abc
add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da109abcdef0
add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea109abcdef0
add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa109abcdef0
add.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840109abc
add.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848109abcdef0
add.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780110
add.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783110
add.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b110
add.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788110
add.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a110
add.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789110
add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1109abc
add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9109abcdef0
add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2109abc
add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2109abc
add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2109abc
add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da109abcdef0
add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea109abcdef0
add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa109abcdef0
add.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840109abc
add.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848109abcdef0
add.l @0x1234:16,@er1 ;01046b0c12340110
add.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343110
add.l @0x1234:16,@-er1 ;01046b0c1234b110
add.l @0x1234:16,@er1+ ;01046b0c12348110
add.l @0x1234:16,@er1- ;01046b0c1234a110
add.l @0x1234:16,@+er1 ;01046b0c12349110
add.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1109abc
add.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9109abcdef0
add.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2109abc
add.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2109abc
add.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2109abc
add.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da109abcdef0
add.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea109abcdef0
add.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa109abcdef0
add.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440109abc
add.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448109abcdef0
add.l @0x12345678:32,@er1 ;01046b2c123456780110
add.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783110
add.l @0x12345678:32,@-er1 ;01046b2c12345678b110
add.l @0x12345678:32,@er1+ ;01046b2c123456788110
add.l @0x12345678:32,@er1- ;01046b2c12345678a110
add.l @0x12345678:32,@+er1 ;01046b2c123456789110
add.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1109abc
add.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9109abcdef0
add.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2109abc
add.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2109abc
add.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2109abc
add.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da109abcdef0
add.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea109abcdef0
add.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa109abcdef0
add.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840109abc
add.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848109abcdef0
.end
|
stsp/binutils-ia16
| 64,344
|
gdb/testsuite/gdb.disasm/t05_cmp.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;arith_1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
cmp.b @er3,@er1 ;7c350120
cmp.b @er3,@(3:2,er1) ;7c353120
cmp.b @er3,@-er1 ;7c35b120
cmp.b @er3,@er1+ ;7c358120
cmp.b @er3,@er1- ;7c35a120
cmp.b @er3,@+er1 ;7c359120
cmp.b @er3,@(0xffff9abc:16,er1) ;7c35c1209abc
cmp.b @er3,@(0x9abcdef0:32,er1) ;7c35c9209abcdef0
cmp.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2209abc
cmp.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2209abc
cmp.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2209abc
cmp.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da209abcdef0
cmp.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea209abcdef0
cmp.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa209abcdef0
cmp.b @er3,@0xffff9abc:16 ;7c3540209abc
cmp.b @er3,@0x9abcdef0:32 ;7c3548209abcdef0
cmp.b @-er3,@er1 ;01776c3c0120
cmp.b @-er3,@(3:2,er1) ;01776c3c3120
cmp.b @-er3,@-er1 ;01776c3cb120
cmp.b @-er3,@er1+ ;01776c3c8120
cmp.b @-er3,@er1- ;01776c3ca120
cmp.b @-er3,@+er1 ;01776c3c9120
cmp.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1209abc
cmp.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9209abcdef0
cmp.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2209abc
cmp.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2209abc
cmp.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2209abc
cmp.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda209abcdef0
cmp.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea209abcdef0
cmp.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa209abcdef0
cmp.b @-er3,@0xffff9abc:16 ;01776c3c40209abc
cmp.b @-er3,@0x9abcdef0:32 ;01776c3c48209abcdef0
cmp.b @er3+,@er1 ;01746c3c0120
cmp.b @er3+,@(3:2,er1) ;01746c3c3120
cmp.b @er3+,@-er1 ;01746c3cb120
cmp.b @er3+,@er1+ ;01746c3c8120
cmp.b @er3+,@er1- ;01746c3ca120
cmp.b @er3+,@+er1 ;01746c3c9120
cmp.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1209abc
cmp.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9209abcdef0
cmp.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2209abc
cmp.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2209abc
cmp.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2209abc
cmp.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda209abcdef0
cmp.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea209abcdef0
cmp.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa209abcdef0
cmp.b @er3+,@0xffff9abc:16 ;01746c3c40209abc
cmp.b @er3+,@0x9abcdef0:32 ;01746c3c48209abcdef0
cmp.b @er3-,@er1 ;01766c3c0120
cmp.b @er3-,@(3:2,er1) ;01766c3c3120
cmp.b @er3-,@-er1 ;01766c3cb120
cmp.b @er3-,@er1+ ;01766c3c8120
cmp.b @er3-,@er1- ;01766c3ca120
cmp.b @er3-,@+er1 ;01766c3c9120
cmp.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1209abc
cmp.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9209abcdef0
cmp.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2209abc
cmp.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2209abc
cmp.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2209abc
cmp.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda209abcdef0
cmp.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea209abcdef0
cmp.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa209abcdef0
cmp.b @er3-,@0xffff9abc:16 ;01766c3c40209abc
cmp.b @er3-,@0x9abcdef0:32 ;01766c3c48209abcdef0
cmp.b @+er3,@er1 ;01756c3c0120
cmp.b @+er3,@(3:2,er1) ;01756c3c3120
cmp.b @+er3,@-er1 ;01756c3cb120
cmp.b @+er3,@er1+ ;01756c3c8120
cmp.b @+er3,@er1- ;01756c3ca120
cmp.b @+er3,@+er1 ;01756c3c9120
cmp.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1209abc
cmp.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9209abcdef0
cmp.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2209abc
cmp.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2209abc
cmp.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2209abc
cmp.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda209abcdef0
cmp.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea209abcdef0
cmp.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa209abcdef0
cmp.b @+er3,@0xffff9abc:16 ;01756c3c40209abc
cmp.b @+er3,@0x9abcdef0:32 ;01756c3c48209abcdef0
cmp.b @(0x1234:16,er3),@er1 ;01746e3c12340120
cmp.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343120
cmp.b @(0x1234:16,er3),@-er1 ;01746e3c1234b120
cmp.b @(0x1234:16,er3),@er1+ ;01746e3c12348120
cmp.b @(0x1234:16,er3),@er1- ;01746e3c1234a120
cmp.b @(0x1234:16,er3),@+er1 ;01746e3c12349120
cmp.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1209abc
cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9209abcdef0
cmp.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2209abc
cmp.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2209abc
cmp.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2209abc
cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da209abcdef0
cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea209abcdef0
cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa209abcdef0
cmp.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440209abc
cmp.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448209abcdef0
cmp.b @(0x12345678:32,er3),@er1 ;78346a2c123456780120
cmp.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783120
cmp.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b120
cmp.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788120
cmp.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a120
cmp.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789120
cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1209abc
cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9209abcdef0
cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2209abc
cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2209abc
cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2209abc
cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da209abcdef0
cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea209abcdef0
cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa209abcdef0
cmp.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840209abc
cmp.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848209abcdef0
cmp.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340120
cmp.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343120
cmp.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b120
cmp.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348120
cmp.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a120
cmp.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349120
cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1209abc
cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9209abcdef0
cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2209abc
cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2209abc
cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2209abc
cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da209abcdef0
cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea209abcdef0
cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa209abcdef0
cmp.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440209abc
cmp.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448209abcdef0
cmp.b @(0x1234:16,r3.w),@er1 ;01766e3c12340120
cmp.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343120
cmp.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b120
cmp.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348120
cmp.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a120
cmp.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349120
cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1209abc
cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9209abcdef0
cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2209abc
cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2209abc
cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2209abc
cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da209abcdef0
cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea209abcdef0
cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa209abcdef0
cmp.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440209abc
cmp.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448209abcdef0
cmp.b @(0x1234:16,er3.l),@er1 ;01776e3c12340120
cmp.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343120
cmp.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b120
cmp.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348120
cmp.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a120
cmp.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349120
cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1209abc
cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9209abcdef0
cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2209abc
cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2209abc
cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2209abc
cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da209abcdef0
cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea209abcdef0
cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa209abcdef0
cmp.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440209abc
cmp.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448209abcdef0
cmp.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780120
cmp.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783120
cmp.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b120
cmp.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788120
cmp.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a120
cmp.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789120
cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1209abc
cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9209abcdef0
cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2209abc
cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2209abc
cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2209abc
cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da209abcdef0
cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea209abcdef0
cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa209abcdef0
cmp.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840209abc
cmp.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848209abcdef0
cmp.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780120
cmp.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783120
cmp.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b120
cmp.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788120
cmp.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a120
cmp.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789120
cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1209abc
cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9209abcdef0
cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2209abc
cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2209abc
cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2209abc
cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da209abcdef0
cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea209abcdef0
cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa209abcdef0
cmp.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840209abc
cmp.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848209abcdef0
cmp.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780120
cmp.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783120
cmp.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b120
cmp.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788120
cmp.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a120
cmp.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789120
cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1209abc
cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9209abcdef0
cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2209abc
cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2209abc
cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2209abc
cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da209abcdef0
cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea209abcdef0
cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa209abcdef0
cmp.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840209abc
cmp.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848209abcdef0
cmp.b @0x1234:16,@er1 ;6a1512340120
cmp.b @0x1234:16,@(3:2,er1) ;6a1512343120
cmp.b @0x1234:16,@-er1 ;6a151234b120
cmp.b @0x1234:16,@er1+ ;6a1512348120
cmp.b @0x1234:16,@er1- ;6a151234a120
cmp.b @0x1234:16,@+er1 ;6a1512349120
cmp.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1209abc
cmp.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9209abcdef0
cmp.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2209abc
cmp.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2209abc
cmp.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2209abc
cmp.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da209abcdef0
cmp.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea209abcdef0
cmp.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa209abcdef0
cmp.b @0x1234:16,@0xffff9abc:16 ;6a15123440209abc
cmp.b @0x1234:16,@0x9abcdef0:32 ;6a15123448209abcdef0
cmp.b @0x12345678:32,@er1 ;6a35123456780120
cmp.b @0x12345678:32,@(3:2,er1) ;6a35123456783120
cmp.b @0x12345678:32,@-er1 ;6a3512345678b120
cmp.b @0x12345678:32,@er1+ ;6a35123456788120
cmp.b @0x12345678:32,@er1- ;6a3512345678a120
cmp.b @0x12345678:32,@+er1 ;6a35123456789120
cmp.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1209abc
cmp.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9209abcdef0
cmp.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2209abc
cmp.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2209abc
cmp.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2209abc
cmp.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da209abcdef0
cmp.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea209abcdef0
cmp.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa209abcdef0
cmp.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840209abc
cmp.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848209abcdef0
cmp.w #0x1234:16,r1 ;79211234
cmp.w #0x7:3,r2 ;1f72
cmp.w #0x1234:16,@er1 ;015e01201234
cmp.w #0x1234:16,@(0x6:2,er1) ;015e31201234
cmp.w #0x1234:16,@er1+ ;015e81201234
cmp.w #0x1234:16,@-er1 ;015eb1201234
cmp.w #0x1234:16,@+er1 ;015e91201234
cmp.w #0x1234:16,@er1- ;015ea1201234
cmp.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1209abc1234
cmp.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9209abcdef01234
cmp.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2209abc1234
cmp.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2209abc1234
cmp.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2209abc1234
cmp.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda209abcdef01234
cmp.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea209abcdef01234
cmp.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa209abcdef01234
cmp.w #0x1234:16,@0xffff9abc:16 ;015e40209abc1234
cmp.w #0x1234:16,@0x9abcdef0:32 ;015e48209abcdef01234
cmp.w #0x7:3,@er1 ;7d901f70
cmp.w #0x7:3,@0x1234:16 ;6b1812341f70
cmp.w #0x7:3,@0x12345678:32 ;6b38123456781f70
cmp.w r3,r1 ;1d31
cmp.w r3,@er1 ;7d901d30
cmp.w r3,@(0x6:2,er1) ;01593123
cmp.w r3,@er1+ ;01598123
cmp.w r3,@-er1 ;0159b123
cmp.w r3,@+er1 ;01599123
cmp.w r3,@er1- ;0159a123
cmp.w r3,@(0x1234:16,er1) ;0159c1231234
cmp.w r3,@(0x12345678:32,er1) ;0159c92312345678
cmp.w r3,@(0x1234:16,r2l.b) ;0159d2231234
cmp.w r3,@(0x1234:16,r2.w) ;0159e2231234
cmp.w r3,@(0x1234:16,er2.l) ;0159f2231234
cmp.w r3,@(0x12345678:32,r2l.b) ;0159da2312345678
cmp.w r3,@(0x12345678:32,r2.w) ;0159ea2312345678
cmp.w r3,@(0x12345678:32,er2.l) ;0159fa2312345678
cmp.w r3,@0x1234:16 ;6b1812341d30
cmp.w r3,@0x12345678:32 ;6b38123456781d30
cmp.w @er3,r1 ;7cb01d01
cmp.w @(0x6:2,er3),r1 ;015a3321
cmp.w @er3+,r1 ;015a8321
cmp.w @-er3,r1 ;015ab321
cmp.w @+er3,r1 ;015a9321
cmp.w @er3-,r1 ;015aa321
cmp.w @(0x1234:16,er1),r1 ;015ac1211234
cmp.w @(0x12345678:32,er1),r1 ;015ac92112345678
cmp.w @(0x1234:16,r2l.b),r1 ;015ad2211234
cmp.w @(0x1234:16,r2.w),r1 ;015ae2211234
cmp.w @(0x1234:16,er2.l),r1 ;015af2211234
cmp.w @(0x12345678:32,r2l.b),r1 ;015ada2112345678
cmp.w @(0x12345678:32,r2.w),r1 ;015aea2112345678
cmp.w @(0x12345678:32,er2.l),r1 ;015afa2112345678
cmp.w @0x1234:16,r1 ;6b1012341d01
cmp.w @0x12345678:32,r1 ;6b30123456781d01
cmp.w @er3,@er1 ;7cb50120
cmp.w @er3,@(6:2,er1) ;7cb53120
cmp.w @er3,@-er1 ;7cb5b120
cmp.w @er3,@er1+ ;7cb58120
cmp.w @er3,@er1- ;7cb5a120
cmp.w @er3,@+er1 ;7cb59120
cmp.w @er3,@(0xffff9abc:16,er1) ;7cb5c1209abc
cmp.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9209abcdef0
cmp.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2209abc
cmp.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2209abc
cmp.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2209abc
cmp.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da209abcdef0
cmp.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea209abcdef0
cmp.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa209abcdef0
cmp.w @er3,@0xffff9abc:16 ;7cb540209abc
cmp.w @er3,@0x9abcdef0:32 ;7cb548209abcdef0
cmp.w @-er3,@er1 ;01576d3c0120
cmp.w @-er3,@(6:2,er1) ;01576d3c3120
cmp.w @-er3,@-er1 ;01576d3cb120
cmp.w @-er3,@er1+ ;01576d3c8120
cmp.w @-er3,@er1- ;01576d3ca120
cmp.w @-er3,@+er1 ;01576d3c9120
cmp.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1209abc
cmp.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9209abcdef0
cmp.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2209abc
cmp.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2209abc
cmp.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2209abc
cmp.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda209abcdef0
cmp.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea209abcdef0
cmp.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa209abcdef0
cmp.w @-er3,@0xffff9abc:16 ;01576d3c40209abc
cmp.w @-er3,@0x9abcdef0:32 ;01576d3c48209abcdef0
cmp.w @er3+,@er1 ;01546d3c0120
cmp.w @er3+,@(6:2,er1) ;01546d3c3120
cmp.w @er3+,@-er1 ;01546d3cb120
cmp.w @er3+,@er1+ ;01546d3c8120
cmp.w @er3+,@er1- ;01546d3ca120
cmp.w @er3+,@+er1 ;01546d3c9120
cmp.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1209abc
cmp.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9209abcdef0
cmp.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2209abc
cmp.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2209abc
cmp.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2209abc
cmp.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda209abcdef0
cmp.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea209abcdef0
cmp.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa209abcdef0
cmp.w @er3+,@0xffff9abc:16 ;01546d3c40209abc
cmp.w @er3+,@0x9abcdef0:32 ;01546d3c48209abcdef0
cmp.w @er3-,@er1 ;01566d3c0120
cmp.w @er3-,@(6:2,er1) ;01566d3c3120
cmp.w @er3-,@-er1 ;01566d3cb120
cmp.w @er3-,@er1+ ;01566d3c8120
cmp.w @er3-,@er1- ;01566d3ca120
cmp.w @er3-,@+er1 ;01566d3c9120
cmp.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1209abc
cmp.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9209abcdef0
cmp.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2209abc
cmp.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2209abc
cmp.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2209abc
cmp.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda209abcdef0
cmp.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea209abcdef0
cmp.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa209abcdef0
cmp.w @er3-,@0xffff9abc:16 ;01566d3c40209abc
cmp.w @er3-,@0x9abcdef0:32 ;01566d3c48209abcdef0
cmp.w @+er3,@er1 ;01556d3c0120
cmp.w @+er3,@(6:2,er1) ;01556d3c3120
cmp.w @+er3,@-er1 ;01556d3cb120
cmp.w @+er3,@er1+ ;01556d3c8120
cmp.w @+er3,@er1- ;01556d3ca120
cmp.w @+er3,@+er1 ;01556d3c9120
cmp.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1209abc
cmp.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9209abcdef0
cmp.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2209abc
cmp.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2209abc
cmp.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2209abc
cmp.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda209abcdef0
cmp.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea209abcdef0
cmp.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa209abcdef0
cmp.w @+er3,@0xffff9abc:16 ;01556d3c40209abc
cmp.w @+er3,@0x9abcdef0:32 ;01556d3c48209abcdef0
cmp.w @(0x1234:16,er3),@er1 ;01546f3c12340120
cmp.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343120
cmp.w @(0x1234:16,er3),@-er1 ;01546f3c1234b120
cmp.w @(0x1234:16,er3),@er1+ ;01546f3c12348120
cmp.w @(0x1234:16,er3),@er1- ;01546f3c1234a120
cmp.w @(0x1234:16,er3),@+er1 ;01546f3c12349120
cmp.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1209abc
cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9209abcdef0
cmp.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2209abc
cmp.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2209abc
cmp.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2209abc
cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da209abcdef0
cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea209abcdef0
cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa209abcdef0
cmp.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440209abc
cmp.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448209abcdef0
cmp.w @(0x12345678:32,er3),@er1 ;78346b2c123456780120
cmp.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783120
cmp.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b120
cmp.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788120
cmp.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a120
cmp.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789120
cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1209abc
cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9209abcdef0
cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2209abc
cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2209abc
cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2209abc
cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da209abcdef0
cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea209abcdef0
cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa209abcdef0
cmp.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840209abc
cmp.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848209abcdef0
cmp.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340120
cmp.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343120
cmp.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b120
cmp.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348120
cmp.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a120
cmp.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349120
cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1209abc
cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9209abcdef0
cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2209abc
cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2209abc
cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2209abc
cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da209abcdef0
cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea209abcdef0
cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa209abcdef0
cmp.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440209abc
cmp.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448209abcdef0
cmp.w @(0x1234:16,r3.w),@er1 ;01566f3c12340120
cmp.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343120
cmp.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b120
cmp.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348120
cmp.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a120
cmp.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349120
cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1209abc
cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9209abcdef0
cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2209abc
cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2209abc
cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2209abc
cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da209abcdef0
cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea209abcdef0
cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa209abcdef0
cmp.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440209abc
cmp.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448209abcdef0
cmp.w @(0x1234:16,er3.l),@er1 ;01576f3c12340120
cmp.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343120
cmp.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b120
cmp.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348120
cmp.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a120
cmp.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349120
cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1209abc
cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9209abcdef0
cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2209abc
cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2209abc
cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2209abc
cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da209abcdef0
cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea209abcdef0
cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa209abcdef0
cmp.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440209abc
cmp.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448209abcdef0
cmp.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780120
cmp.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783120
cmp.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b120
cmp.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788120
cmp.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a120
cmp.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789120
cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1209abc
cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9209abcdef0
cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2209abc
cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2209abc
cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2209abc
cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da209abcdef0
cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea209abcdef0
cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa209abcdef0
cmp.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840209abc
cmp.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848209abcdef0
cmp.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780120
cmp.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783120
cmp.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b120
cmp.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788120
cmp.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a120
cmp.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789120
cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1209abc
cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9209abcdef0
cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2209abc
cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2209abc
cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2209abc
cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da209abcdef0
cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea209abcdef0
cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa209abcdef0
cmp.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840209abc
cmp.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848209abcdef0
cmp.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780120
cmp.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783120
cmp.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b120
cmp.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788120
cmp.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a120
cmp.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789120
cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1209abc
cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9209abcdef0
cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2209abc
cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2209abc
cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2209abc
cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da209abcdef0
cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea209abcdef0
cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa209abcdef0
cmp.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840209abc
cmp.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848209abcdef0
cmp.w @0x1234:16,@er1 ;6b1512340120
cmp.w @0x1234:16,@(6:2,er1) ;6b1512343120
cmp.w @0x1234:16,@-er1 ;6b151234b120
cmp.w @0x1234:16,@er1+ ;6b1512348120
cmp.w @0x1234:16,@er1- ;6b151234a120
cmp.w @0x1234:16,@+er1 ;6b1512349120
cmp.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1209abc
cmp.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9209abcdef0
cmp.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2209abc
cmp.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2209abc
cmp.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2209abc
cmp.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da209abcdef0
cmp.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea209abcdef0
cmp.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa209abcdef0
cmp.w @0x1234:16,@0xffff9abc:16 ;6b15123440209abc
cmp.w @0x1234:16,@0x9abcdef0:32 ;6b15123448209abcdef0
cmp.w @0x12345678:32,@er1 ;6b35123456780120
cmp.w @0x12345678:32,@(6:2,er1) ;6b35123456783120
cmp.w @0x12345678:32,@-er1 ;6b3512345678b120
cmp.w @0x12345678:32,@er1+ ;6b35123456788120
cmp.w @0x12345678:32,@er1- ;6b3512345678a120
cmp.w @0x12345678:32,@+er1 ;6b35123456789120
cmp.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1209abc
cmp.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9209abcdef0
cmp.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2209abc
cmp.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2209abc
cmp.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2209abc
cmp.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da209abcdef0
cmp.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea209abcdef0
cmp.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa209abcdef0
cmp.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840209abc
cmp.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848209abcdef0
cmp.l #0x12345678:32,er1 ;7a2112345678
cmp.l #0x1234:16,er1 ;7a291234
cmp.l #0x7:3,er2 ;1ffa
cmp.l #0x12345678:32,@er1 ;010e012812345678
cmp.l #0x12345678:32,@(0xc:2,er1) ;010e312812345678
cmp.l #0x12345678:32,@er1+ ;010e812812345678
cmp.l #0x12345678:32,@-er1 ;010eb12812345678
cmp.l #0x12345678:32,@+er1 ;010e912812345678
cmp.l #0x12345678:32,@er1- ;010ea12812345678
cmp.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1289abc12345678
cmp.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9289abcdef012345678
cmp.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2289abc12345678
cmp.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2289abc12345678
cmp.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2289abc12345678
cmp.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda289abcdef012345678
cmp.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea289abcdef012345678
cmp.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa289abcdef012345678
cmp.l #0x12345678:32,@0xffff9abc:16 ;010e40289abc12345678
cmp.l #0x12345678:32,@0x9abcdef0:32 ;010e48289abcdef012345678
cmp.l #0x1234:16,@er1 ;010e01201234
cmp.l #0x1234:16,@(0xc:2,er1) ;010e31201234
cmp.l #0x1234:16,@er1+ ;010e81201234
cmp.l #0x1234:16,@-er1 ;010eb1201234
cmp.l #0x1234:16,@+er1 ;010e91201234
cmp.l #0x1234:16,@er1- ;010ea1201234
cmp.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1209abc1234
cmp.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9209abcdef01234
cmp.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2209abc1234
cmp.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2209abc1234
cmp.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2209abc1234
cmp.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda209abcdef01234
cmp.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea209abcdef01234
cmp.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa209abcdef01234
cmp.l #0x1234:16,@0xffff9abc:16 ;010e40209abc1234
cmp.l #0x1234:16,@0x9abcdef0:32 ;010e48209abcdef01234
cmp.l er3,er1 ;1fb1
cmp.l er3,@er1 ;01090123
cmp.l er3,@(0xc:2,er1) ;01093123
cmp.l er3,@er1+ ;01098123
cmp.l er3,@-er1 ;0109b123
cmp.l er3,@+er1 ;01099123
cmp.l er3,@er1- ;0109a123
cmp.l er3,@(0x1234:16,er1) ;0109c1231234
cmp.l er3,@(0x12345678:32,er1) ;0109c92312345678
cmp.l er3,@(0x1234:16,r2l.b) ;0109d2231234
cmp.l er3,@(0x1234:16,r2.w) ;0109e2231234
cmp.l er3,@(0x1234:16,er2.l) ;0109f2231234
cmp.l er3,@(0x12345678:32,r2l.b) ;0109da2312345678
cmp.l er3,@(0x12345678:32,r2.w) ;0109ea2312345678
cmp.l er3,@(0x12345678:32,er2.l) ;0109fa2312345678
cmp.l er3,@0x1234:16 ;010940231234
cmp.l er3,@0x12345678:32 ;0109482312345678
cmp.l @er3,er1 ;010a0321
cmp.l @(0xc:2,er3),er1 ;010a3321
cmp.l @er3+,er1 ;010a8321
cmp.l @-er3,er1 ;010ab321
cmp.l @+er3,er1 ;010a9321
cmp.l @er3-,er1 ;010aa321
cmp.l @(0x1234:16,er1),er1 ;010ac1211234
cmp.l @(0x12345678:32,er1),er1 ;010ac92112345678
cmp.l @(0x1234:16,r2l.b),er1 ;010ad2211234
cmp.l @(0x1234:16,r2.w),er1 ;010ae2211234
cmp.l @(0x1234:16,er2.l),er1 ;010af2211234
cmp.l @(0x12345678:32,r2l.b),er1 ;010ada2112345678
cmp.l @(0x12345678:32,r2.w),er1 ;010aea2112345678
cmp.l @(0x12345678:32,er2.l),er1 ;010afa2112345678
cmp.l @0x1234:16,er1 ;010a40211234
cmp.l @0x12345678:32,er1 ;010a482112345678
cmp.l @er3,@er1 ;0104693c0120
cmp.l @er3,@(0xc:2,er1) ;0104693c3120
cmp.l @er3,@-er1 ;0104693cb120
cmp.l @er3,@er1+ ;0104693c8120
cmp.l @er3,@er1- ;0104693ca120
cmp.l @er3,@+er1 ;0104693c9120
cmp.l @er3,@(0xffff9abc:16,er1) ;0104693cc1209abc
cmp.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9209abcdef0
cmp.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2209abc
cmp.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2209abc
cmp.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2209abc
cmp.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda209abcdef0
cmp.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea209abcdef0
cmp.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa209abcdef0
cmp.l @er3,@0xffff9abc:16 ;0104693c40209abc
cmp.l @er3,@0x9abcdef0:32 ;0104693c48209abcdef0
cmp.l @(0xc:2,er3),@er1 ;0107693c0120
cmp.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3120
cmp.l @(0xc:2,er3),@-er1 ;0107693cb120
cmp.l @(0xc:2,er3),@er1+ ;0107693c8120
cmp.l @(0xc:2,er3),@er1- ;0107693ca120
cmp.l @(0xc:2,er3),@+er1 ;0107693c9120
cmp.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1209abc
cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9209abcdef0
cmp.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2209abc
cmp.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2209abc
cmp.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2209abc
cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda209abcdef0
cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea209abcdef0
cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa209abcdef0
cmp.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40209abc
cmp.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48209abcdef0
cmp.l @-er3,@er1 ;01076d3c0120
cmp.l @-er3,@(0xc:2,er1) ;01076d3c3120
cmp.l @-er3,@-er1 ;01076d3cb120
cmp.l @-er3,@er1+ ;01076d3c8120
cmp.l @-er3,@er1- ;01076d3ca120
cmp.l @-er3,@+er1 ;01076d3c9120
cmp.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1209abc
cmp.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9209abcdef0
cmp.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2209abc
cmp.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2209abc
cmp.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2209abc
cmp.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda209abcdef0
cmp.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea209abcdef0
cmp.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa209abcdef0
cmp.l @-er3,@0xffff9abc:16 ;01076d3c40209abc
cmp.l @-er3,@0x9abcdef0:32 ;01076d3c48209abcdef0
cmp.l @er3+,@er1 ;01046d3c0120
cmp.l @er3+,@(0xc:2,er1) ;01046d3c3120
cmp.l @er3+,@-er1 ;01046d3cb120
cmp.l @er3+,@er1+ ;01046d3c8120
cmp.l @er3+,@er1- ;01046d3ca120
cmp.l @er3+,@+er1 ;01046d3c9120
cmp.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1209abc
cmp.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9209abcdef0
cmp.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2209abc
cmp.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2209abc
cmp.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2209abc
cmp.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda209abcdef0
cmp.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea209abcdef0
cmp.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa209abcdef0
cmp.l @er3+,@0xffff9abc:16 ;01046d3c40209abc
cmp.l @er3+,@0x9abcdef0:32 ;01046d3c48209abcdef0
cmp.l @er3-,@er1 ;01066d3c0120
cmp.l @er3-,@(0xc:2,er1) ;01066d3c3120
cmp.l @er3-,@-er1 ;01066d3cb120
cmp.l @er3-,@er1+ ;01066d3c8120
cmp.l @er3-,@er1- ;01066d3ca120
cmp.l @er3-,@+er1 ;01066d3c9120
cmp.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1209abc
cmp.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9209abcdef0
cmp.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2209abc
cmp.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2209abc
cmp.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2209abc
cmp.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda209abcdef0
cmp.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea209abcdef0
cmp.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa209abcdef0
cmp.l @er3-,@0xffff9abc:16 ;01066d3c40209abc
cmp.l @er3-,@0x9abcdef0:32 ;01066d3c48209abcdef0
cmp.l @+er3,@er1 ;01056d3c0120
cmp.l @+er3,@(0xc:2,er1) ;01056d3c3120
cmp.l @+er3,@-er1 ;01056d3cb120
cmp.l @+er3,@er1+ ;01056d3c8120
cmp.l @+er3,@er1- ;01056d3ca120
cmp.l @+er3,@+er1 ;01056d3c9120
cmp.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1209abc
cmp.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9209abcdef0
cmp.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2209abc
cmp.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2209abc
cmp.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2209abc
cmp.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda209abcdef0
cmp.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea209abcdef0
cmp.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa209abcdef0
cmp.l @+er3,@0xffff9abc:16 ;01056d3c40209abc
cmp.l @+er3,@0x9abcdef0:32 ;01056d3c48209abcdef0
cmp.l @(0x1234:16,er3),@er1 ;01046f3c12340120
cmp.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343120
cmp.l @(0x1234:16,er3),@-er1 ;01046f3c1234b120
cmp.l @(0x1234:16,er3),@er1+ ;01046f3c12348120
cmp.l @(0x1234:16,er3),@er1- ;01046f3c1234a120
cmp.l @(0x1234:16,er3),@+er1 ;01046f3c12349120
cmp.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1209abc
cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9209abcdef0
cmp.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2209abc
cmp.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2209abc
cmp.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2209abc
cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da209abcdef0
cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea209abcdef0
cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa209abcdef0
cmp.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440209abc
cmp.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448209abcdef0
cmp.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780120
cmp.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783120
cmp.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b120
cmp.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788120
cmp.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a120
cmp.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789120
cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1209abc
cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9209abcdef0
cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2209abc
cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2209abc
cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2209abc
cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da209abcdef0
cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea209abcdef0
cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa209abcdef0
cmp.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840209abc
cmp.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848209abcdef0
cmp.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340120
cmp.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343120
cmp.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b120
cmp.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348120
cmp.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a120
cmp.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349120
cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1209abc
cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9209abcdef0
cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2209abc
cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2209abc
cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2209abc
cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da209abcdef0
cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea209abcdef0
cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa209abcdef0
cmp.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440209abc
cmp.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448209abcdef0
cmp.l @(0x1234:16,r3.w),@er1 ;01066f3c12340120
cmp.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343120
cmp.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b120
cmp.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348120
cmp.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a120
cmp.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349120
cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1209abc
cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9209abcdef0
cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2209abc
cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2209abc
cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2209abc
cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da209abcdef0
cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea209abcdef0
cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa209abcdef0
cmp.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440209abc
cmp.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448209abcdef0
cmp.l @(0x1234:16,er3.l),@er1 ;01076f3c12340120
cmp.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343120
cmp.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b120
cmp.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348120
cmp.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a120
cmp.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349120
cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1209abc
cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9209abcdef0
cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2209abc
cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2209abc
cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2209abc
cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da209abcdef0
cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea209abcdef0
cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa209abcdef0
cmp.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440209abc
cmp.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448209abcdef0
cmp.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780120
cmp.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783120
cmp.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b120
cmp.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788120
cmp.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a120
cmp.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789120
cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1209abc
cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9209abcdef0
cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2209abc
cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2209abc
cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2209abc
cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da209abcdef0
cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea209abcdef0
cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa209abcdef0
cmp.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840209abc
cmp.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848209abcdef0
cmp.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780120
cmp.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783120
cmp.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b120
cmp.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788120
cmp.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a120
cmp.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789120
cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1209abc
cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9209abcdef0
cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2209abc
cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2209abc
cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2209abc
cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da209abcdef0
cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea209abcdef0
cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa209abcdef0
cmp.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840209abc
cmp.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848209abcdef0
cmp.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780120
cmp.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783120
cmp.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b120
cmp.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788120
cmp.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a120
cmp.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789120
cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1209abc
cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9209abcdef0
cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2209abc
cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2209abc
cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2209abc
cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da209abcdef0
cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea209abcdef0
cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa209abcdef0
cmp.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840209abc
cmp.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848209abcdef0
cmp.l @0x1234:16,@er1 ;01046b0c12340120
cmp.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343120
cmp.l @0x1234:16,@-er1 ;01046b0c1234b120
cmp.l @0x1234:16,@er1+ ;01046b0c12348120
cmp.l @0x1234:16,@er1- ;01046b0c1234a120
cmp.l @0x1234:16,@+er1 ;01046b0c12349120
cmp.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1209abc
cmp.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9209abcdef0
cmp.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2209abc
cmp.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2209abc
cmp.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2209abc
cmp.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da209abcdef0
cmp.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea209abcdef0
cmp.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa209abcdef0
cmp.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440209abc
cmp.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448209abcdef0
cmp.l @0x12345678:32,@er1 ;01046b2c123456780120
cmp.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783120
cmp.l @0x12345678:32,@-er1 ;01046b2c12345678b120
cmp.l @0x12345678:32,@er1+ ;01046b2c123456788120
cmp.l @0x12345678:32,@er1- ;01046b2c12345678a120
cmp.l @0x12345678:32,@+er1 ;01046b2c123456789120
cmp.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1209abc
cmp.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9209abcdef0
cmp.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2209abc
cmp.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2209abc
cmp.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2209abc
cmp.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da209abcdef0
cmp.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea209abcdef0
cmp.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa209abcdef0
cmp.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840209abc
cmp.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848209abcdef0
.end
|
stsp/binutils-ia16
| 37,946
|
gdb/testsuite/gdb.disasm/hppa.s
|
.SPACE $PRIVATE$
.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
.SPACE $TEXT$
.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY
.IMPORT $global$,DATA
.IMPORT $$dyncall,MILLICODE
; gcc_compiled.:
.SPACE $TEXT$
.SUBSPA $CODE$
.align 4
.EXPORT integer_memory_tests,CODE
.EXPORT integer_indexing_load,CODE
.EXPORT integer_load_short_memory,CODE
.EXPORT integer_store_short_memory,CODE
.EXPORT immediate_tests,CODE
.EXPORT branch_tests_1,CODE
.EXPORT branch_tests_2,CODE
.EXPORT movb_tests,CODE
.EXPORT movb_nullified_tests,CODE
.EXPORT movib_tests,CODE
.EXPORT movib_nullified_tests,CODE
.EXPORT comb_tests_1,CODE
.EXPORT comb_tests_2,CODE
.EXPORT comb_nullified_tests_1,CODE
.EXPORT comb_nullified_tests_2,CODE
.EXPORT comib_tests_1,CODE
.EXPORT comib_tests_2,CODE
.EXPORT comib_nullified_tests_1,CODE
.EXPORT comib_nullified_tests_2,CODE
.EXPORT addb_tests_1,CODE
.EXPORT addb_tests_2,CODE
.EXPORT addb_nullified_tests_1,CODE
.EXPORT addb_nullified_tests_2,CODE
.EXPORT addib_tests_1,CODE
.EXPORT addib_tests_2,CODE
.EXPORT addib_nullified_tests_1,CODE
.EXPORT addib_nullified_tests_2,CODE
.EXPORT bb_tests,CODE
.EXPORT add_tests,CODE
.EXPORT addl_tests,CODE
.EXPORT addo_tests,CODE
.EXPORT addc_tests,CODE
.EXPORT addco_tests,CODE
.EXPORT sh1add_tests,CODE
.EXPORT sh1addl_tests,CODE
.EXPORT sh1addo_tests,CODE
.EXPORT sh2add_tests,CODE
.EXPORT sh2addl_tests,CODE
.EXPORT sh2addo_tests,CODE
.EXPORT sh3add_tests,CODE
.EXPORT sh3addl_tests,CODE
.EXPORT sh3addo_tests,CODE
.EXPORT sub_tests,CODE
.EXPORT subo_tests,CODE
.EXPORT subb_tests,CODE
.EXPORT subbo_tests,CODE
.EXPORT subt_tests,CODE
.EXPORT subto_tests,CODE
.EXPORT ds_tests,CODE
.EXPORT comclr_tests,CODE
.EXPORT or_tests,CODE
.EXPORT xor_tests,CODE
.EXPORT and_tests,CODE
.EXPORT andcm_tests,CODE
.EXPORT uxor_tests,CODE
.EXPORT uaddcm_tests,CODE
.EXPORT uaddcmt_tests,CODE
.EXPORT dcor_tests,CODE
.EXPORT idcor_tests,CODE
.EXPORT addi_tests,CODE
.EXPORT addio_tests,CODE
.EXPORT addit_tests,CODE
.EXPORT addito_tests,CODE
.EXPORT subi_tests,CODE
.EXPORT subio_tests,CODE
.EXPORT comiclr_tests,CODE
.EXPORT vshd_tests,CODE
.EXPORT shd_tests,CODE
.EXPORT extru_tests,CODE
.EXPORT extrs_tests,CODE
.EXPORT zdep_tests,CODE
.EXPORT dep_tests,CODE
.EXPORT vextru_tests,CODE
.EXPORT vextrs_tests,CODE
.EXPORT zvdep_tests,CODE
.EXPORT vdep_tests,CODE
.EXPORT vdepi_tests,CODE
.EXPORT zvdepi_tests,CODE
.EXPORT depi_tests,CODE
.EXPORT zdepi_tests,CODE
.EXPORT system_control_tests,CODE
.EXPORT probe_tests,CODE
.EXPORT lpa_tests,CODE
.EXPORT purge_tests,CODE
.EXPORT insert_tests,CODE
.EXPORT fpu_misc_tests,CODE
.EXPORT fpu_memory_indexing_tests,CODE
.EXPORT fpu_short_memory_tests,CODE
.EXPORT fcpy_tests,CODE
.EXPORT fabs_tests,CODE
.EXPORT fsqrt_tests,CODE
.EXPORT frnd_tests,CODE
.EXPORT fcnvff_tests,CODE
.EXPORT fcnvxf_tests,CODE
.EXPORT fcnvfx_tests,CODE
.EXPORT fcnvfxt_tests,CODE
.EXPORT fadd_tests,CODE
.EXPORT fsub_tests,CODE
.EXPORT fmpy_tests,CODE
.EXPORT fdiv_tests,CODE
.EXPORT frem_tests,CODE
.EXPORT fcmp_sgl_tests_1,CODE
.EXPORT fcmp_sgl_tests_2,CODE
.EXPORT fcmp_sgl_tests_3,CODE
.EXPORT fcmp_sgl_tests_4,CODE
.EXPORT fcmp_dbl_tests_1,CODE
.EXPORT fcmp_dbl_tests_2,CODE
.EXPORT fcmp_dbl_tests_3,CODE
.EXPORT fcmp_dbl_tests_4,CODE
.EXPORT fcmp_quad_tests_1,CODE
.EXPORT fcmp_quad_tests_2,CODE
.EXPORT fcmp_quad_tests_3,CODE
.EXPORT fcmp_quad_tests_4,CODE
.EXPORT fmpy_addsub_tests,CODE
.EXPORT xmpyu_tests,CODE
.EXPORT special_tests,CODE
.EXPORT sfu_tests,CODE
.EXPORT copr_tests,CODE
.EXPORT copr_indexing_load,CODE
.EXPORT copr_indexing_store,CODE
.EXPORT copr_short_memory,CODE
.EXPORT fmemLRbug_tests_1,CODE
.EXPORT fmemLRbug_tests_2,CODE
.EXPORT fmemLRbug_tests_3,CODE
.EXPORT fmemLRbug_tests_4,CODE
.EXPORT main,CODE
.EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR
main
.PROC
.CALLINFO FRAME=64,NO_CALLS,SAVE_SP
.ENTRY
copy %r4,%r1
copy %r30,%r4
stwm %r1,64(0,%r30)
; First memory reference instructions.
; Should try corner cases for each field extraction.
; Should deal with s == 0 case somehow?!?
integer_memory_tests
ldw 0(0,%r4),%r26
ldh 0(0,%r4),%r26
ldb 0(0,%r4),%r26
stw %r26,0(0,%r4)
sth %r26,0(0,%r4)
stb %r26,0(0,%r4)
; Should make sure pre/post modes are recognized correctly.
ldwm 0(0,%r4),%r26
stwm %r26,0(0,%r4)
integer_indexing_load
ldwx %r5(0,%r4),%r26
ldwx,s %r5(0,%r4),%r26
ldwx,m %r5(0,%r4),%r26
ldwx,sm %r5(0,%r4),%r26
ldhx %r5(0,%r4),%r26
ldhx,s %r5(0,%r4),%r26
ldhx,m %r5(0,%r4),%r26
ldhx,sm %r5(0,%r4),%r26
ldbx %r5(0,%r4),%r26
ldbx,s %r5(0,%r4),%r26
ldbx,m %r5(0,%r4),%r26
ldbx,sm %r5(0,%r4),%r26
ldwax %r5(%r4),%r26
ldwax,s %r5(%r4),%r26
ldwax,m %r5(%r4),%r26
ldwax,sm %r5(%r4),%r26
ldcwx %r5(0,%r4),%r26
ldcwx,s %r5(0,%r4),%r26
ldcwx,m %r5(0,%r4),%r26
ldcwx,sm %r5(0,%r4),%r26
integer_load_short_memory
ldws 0(0,%r4),%r26
ldws,mb 0(0,%r4),%r26
ldws,ma 0(0,%r4),%r26
ldhs 0(0,%r4),%r26
ldhs,mb 0(0,%r4),%r26
ldhs,ma 0(0,%r4),%r26
ldbs 0(0,%r4),%r26
ldbs,mb 0(0,%r4),%r26
ldbs,ma 0(0,%r4),%r26
ldwas 0(%r4),%r26
ldwas,mb 0(%r4),%r26
ldwas,ma 0(%r4),%r26
ldcws 0(0,%r4),%r26
ldcws,mb 0(0,%r4),%r26
ldcws,ma 0(0,%r4),%r26
integer_store_short_memory
stws %r26,0(0,%r4)
stws,mb %r26,0(0,%r4)
stws,ma %r26,0(0,%r4)
sths %r26,0(0,%r4)
sths,mb %r26,0(0,%r4)
sths,ma %r26,0(0,%r4)
stbs %r26,0(0,%r4)
stbs,mb %r26,0(0,%r4)
stbs,ma %r26,0(0,%r4)
stwas %r26,0(%r4)
stwas,mb %r26,0(%r4)
stwas,ma %r26,0(%r4)
stbys %r26,0(0,%r4)
stbys,b %r26,0(0,%r4)
stbys,e %r26,0(0,%r4)
stbys,b,m %r26,0(0,%r4)
stbys,e,m %r26,0(0,%r4)
; Immediate instructions.
immediate_tests
ldo 5(%r26),%r26
ldil L%0xdeadbeef,%r26
addil L%0xdeadbeef,%r5
; Lots of branch instructions.
; blr with %r0 as return pointer should really be just br <target>,
; but the assemblers can't handle it.
branch_tests_1
bl main,%r2
bl,n main,%r2
b main
b,n main
gate main,%r2
gate,n main,%r2
blr %r4,%r2
blr,n %r4,%r2
blr %r4,%r0
blr,n %r4,%r0
branch_tests_2
bv 0(%r2)
bv,n 0(%r2)
be 0x1234(%sr1,%r2)
be,n 0x1234(%sr1,%r2)
ble 0x1234(%sr1,%r2)
ble,n 0x1234(%sr1,%r2)
; GAS can't assemble movb,n or movib,n.
movb_tests
movb %r4,%r26,movb_tests
movb,= %r4,%r26,movb_tests
movb,< %r4,%r26,movb_tests
movb,od %r4,%r26,movb_tests
movb,tr %r4,%r26,movb_tests
movb,<> %r4,%r26,movb_tests
movb,>= %r4,%r26,movb_tests
movb,ev %r4,%r26,movb_tests
movb_nullified_tests
movb,n %r4,%r26,movb_tests
movb,=,n %r4,%r26,movb_tests
movb,<,n %r4,%r26,movb_tests
movb,od,n %r4,%r26,movb_tests
movb,tr,n %r4,%r26,movb_tests
movb,<>,n %r4,%r26,movb_tests
movb,>=,n %r4,%r26,movb_tests
movb,ev,n %r4,%r26,movb_tests
movib_tests
movib 5,%r26,movib_tests
movib,= 5,%r26,movib_tests
movib,< 5,%r26,movib_tests
movib,od 5,%r26,movib_tests
movib,tr 5,%r26,movib_tests
movib,<> 5,%r26,movib_tests
movib,>= 5,%r26,movib_tests
movib,ev 5,%r26,movib_tests
movib_nullified_tests
movib,n 5,%r26,movib_tests
movib,=,n 5,%r26,movib_tests
movib,<,n 5,%r26,movib_tests
movib,od,n 5,%r26,movib_tests
movib,tr,n 5,%r26,movib_tests
movib,<>,n 5,%r26,movib_tests
movib,>=,n 5,%r26,movib_tests
movib,ev,n 5,%r26,movib_tests
comb_tests_1
comb %r0,%r4,comb_tests_1
comb,= %r0,%r4,comb_tests_1
comb,< %r0,%r4,comb_tests_1
comb,<= %r0,%r4,comb_tests_1
comb,<< %r0,%r4,comb_tests_1
comb,<<= %r0,%r4,comb_tests_1
comb,sv %r0,%r4,comb_tests_1
comb,od %r0,%r4,comb_tests_1
comb_tests_2
comb,tr %r0,%r4,comb_tests_2
comb,<> %r0,%r4,comb_tests_2
comb,>= %r0,%r4,comb_tests_2
comb,> %r0,%r4,comb_tests_2
comb,>>= %r0,%r4,comb_tests_2
comb,>> %r0,%r4,comb_tests_2
comb,nsv %r0,%r4,comb_tests_2
comb,ev %r0,%r4,comb_tests_2
comb_nullified_tests_1
comb,n %r0,%r4,comb_tests_1
comb,=,n %r0,%r4,comb_tests_1
comb,<,n %r0,%r4,comb_tests_1
comb,<=,n %r0,%r4,comb_tests_1
comb,<<,n %r0,%r4,comb_tests_1
comb,<<=,n %r0,%r4,comb_tests_1
comb,sv,n %r0,%r4,comb_tests_1
comb,od,n %r0,%r4,comb_tests_1
comb_nullified_tests_2
comb,tr,n %r0,%r4,comb_tests_2
comb,<>,n %r0,%r4,comb_tests_2
comb,>=,n %r0,%r4,comb_tests_2
comb,>,n %r0,%r4,comb_tests_2
comb,>>=,n %r0,%r4,comb_tests_2
comb,>>,n %r0,%r4,comb_tests_2
comb,nsv,n %r0,%r4,comb_tests_2
comb,ev,n %r0,%r4,comb_tests_2
comib_tests_1
comib 0,%r4,comib_tests_1
comib,= 0,%r4,comib_tests_1
comib,< 0,%r4,comib_tests_1
comib,<= 0,%r4,comib_tests_1
comib,<< 0,%r4,comib_tests_1
comib,<<= 0,%r4,comib_tests_1
comib,sv 0,%r4,comib_tests_1
comib,od 0,%r4,comib_tests_1
comib_tests_2
comib,tr 0,%r4,comib_tests_2
comib,<> 0,%r4,comib_tests_2
comib,>= 0,%r4,comib_tests_2
comib,> 0,%r4,comib_tests_2
comib,>>= 0,%r4,comib_tests_2
comib,>> 0,%r4,comib_tests_2
comib,nsv 0,%r4,comib_tests_2
comib,ev 0,%r4,comib_tests_2
comib_nullified_tests_1
comib,n 0,%r4,comib_tests_1
comib,=,n 0,%r4,comib_tests_1
comib,<,n 0,%r4,comib_tests_1
comib,<=,n 0,%r4,comib_tests_1
comib,<<,n 0,%r4,comib_tests_1
comib,<<=,n 0,%r4,comib_tests_1
comib,sv,n 0,%r4,comib_tests_1
comib,od,n 0,%r4,comib_tests_1
comib_nullified_tests_2
comib,tr,n 0,%r4,comib_tests_2
comib,<>,n 0,%r4,comib_tests_2
comib,>=,n 0,%r4,comib_tests_2
comib,>,n 0,%r4,comib_tests_2
comib,>>=,n 0,%r4,comib_tests_2
comib,>>,n 0,%r4,comib_tests_2
comib,nsv,n 0,%r4,comib_tests_2
comib,ev,n 0,%r4,comib_tests_2
addb_tests_1
addb %r1,%r4,addb_tests_1
addb,= %r1,%r4,addb_tests_1
addb,< %r1,%r4,addb_tests_1
addb,<= %r1,%r4,addb_tests_1
addb,nuv %r1,%r4,addb_tests_1
addb,znv %r1,%r4,addb_tests_1
addb,sv %r1,%r4,addb_tests_1
addb,od %r1,%r4,addb_tests_1
addb_tests_2
addb,tr %r1,%r4,addb_tests_2
addb,<> %r1,%r4,addb_tests_2
addb,>= %r1,%r4,addb_tests_2
addb,> %r1,%r4,addb_tests_2
addb,uv %r1,%r4,addb_tests_2
addb,vnz %r1,%r4,addb_tests_2
addb,nsv %r1,%r4,addb_tests_2
addb,ev %r1,%r4,addb_tests_2
addb_nullified_tests_1
addb,n %r1,%r4,addb_tests_1
addb,=,n %r1,%r4,addb_tests_1
addb,<,n %r1,%r4,addb_tests_1
addb,<=,n %r1,%r4,addb_tests_1
addb,nuv,n %r1,%r4,addb_tests_1
addb,znv,n %r1,%r4,addb_tests_1
addb,sv,n %r1,%r4,addb_tests_1
addb,od,n %r1,%r4,addb_tests_1
addb_nullified_tests_2
addb,tr,n %r1,%r4,addb_tests_2
addb,<>,n %r1,%r4,addb_tests_2
addb,>=,n %r1,%r4,addb_tests_2
addb,>,n %r1,%r4,addb_tests_2
addb,uv,n %r1,%r4,addb_tests_2
addb,vnz,n %r1,%r4,addb_tests_2
addb,nsv,n %r1,%r4,addb_tests_2
addb,ev,n %r1,%r4,addb_tests_2
addib_tests_1
addib -1,%r4,addib_tests_1
addib,= -1,%r4,addib_tests_1
addib,< -1,%r4,addib_tests_1
addib,<= -1,%r4,addib_tests_1
addib,nuv -1,%r4,addib_tests_1
addib,znv -1,%r4,addib_tests_1
addib,sv -1,%r4,addib_tests_1
addib,od -1,%r4,addib_tests_1
addib_tests_2
addib,tr -1,%r4,addib_tests_2
addib,<> -1,%r4,addib_tests_2
addib,>= -1,%r4,addib_tests_2
addib,> -1,%r4,addib_tests_2
addib,uv -1,%r4,addib_tests_2
addib,vnz -1,%r4,addib_tests_2
addib,nsv -1,%r4,addib_tests_2
addib,ev -1,%r4,addib_tests_2
addib_nullified_tests_1
addib,n -1,%r4,addib_tests_1
addib,=,n -1,%r4,addib_tests_1
addib,<,n -1,%r4,addib_tests_1
addib,<=,n -1,%r4,addib_tests_1
addib,nuv,n -1,%r4,addib_tests_1
addib,znv,n -1,%r4,addib_tests_1
addib,sv,n -1,%r4,addib_tests_1
addib,od,n -1,%r4,addib_tests_1
addib_nullified_tests_2
addib,tr,n -1,%r4,addib_tests_2
addib,<>,n -1,%r4,addib_tests_2
addib,>=,n -1,%r4,addib_tests_2
addib,>,n -1,%r4,addib_tests_2
addib,uv,n -1,%r4,addib_tests_2
addib,vnz,n -1,%r4,addib_tests_2
addib,nsv,n -1,%r4,addib_tests_2
addib,ev,n -1,%r4,addib_tests_2
; Needs to check lots of stuff (like corner bit cases)
bb_tests
bvb,< %r4,bb_tests
bvb,>= %r4,bb_tests
bvb,<,n %r4,bb_tests
bvb,>=,n %r4,bb_tests
bb,< %r4,5,bb_tests
bb,>= %r4,5,bb_tests
bb,<,n %r4,5,bb_tests
bb,>=,n %r4,5,bb_tests
; Computational instructions
add_tests
add %r4,%r5,%r6
add,= %r4,%r5,%r6
add,< %r4,%r5,%r6
add,<= %r4,%r5,%r6
add,nuv %r4,%r5,%r6
add,znv %r4,%r5,%r6
add,sv %r4,%r5,%r6
add,od %r4,%r5,%r6
add,tr %r4,%r5,%r6
add,<> %r4,%r5,%r6
add,>= %r4,%r5,%r6
add,> %r4,%r5,%r6
add,uv %r4,%r5,%r6
add,vnz %r4,%r5,%r6
add,nsv %r4,%r5,%r6
add,ev %r4,%r5,%r6
addl_tests
addl %r4,%r5,%r6
addl,= %r4,%r5,%r6
addl,< %r4,%r5,%r6
addl,<= %r4,%r5,%r6
addl,nuv %r4,%r5,%r6
addl,znv %r4,%r5,%r6
addl,sv %r4,%r5,%r6
addl,od %r4,%r5,%r6
addl,tr %r4,%r5,%r6
addl,<> %r4,%r5,%r6
addl,>= %r4,%r5,%r6
addl,> %r4,%r5,%r6
addl,uv %r4,%r5,%r6
addl,vnz %r4,%r5,%r6
addl,nsv %r4,%r5,%r6
addl,ev %r4,%r5,%r6
addo_tests
addo %r4,%r5,%r6
addo,= %r4,%r5,%r6
addo,< %r4,%r5,%r6
addo,<= %r4,%r5,%r6
addo,nuv %r4,%r5,%r6
addo,znv %r4,%r5,%r6
addo,sv %r4,%r5,%r6
addo,od %r4,%r5,%r6
addo,tr %r4,%r5,%r6
addo,<> %r4,%r5,%r6
addo,>= %r4,%r5,%r6
addo,> %r4,%r5,%r6
addo,uv %r4,%r5,%r6
addo,vnz %r4,%r5,%r6
addo,nsv %r4,%r5,%r6
addo,ev %r4,%r5,%r6
addc_tests
addc %r4,%r5,%r6
addc,= %r4,%r5,%r6
addc,< %r4,%r5,%r6
addc,<= %r4,%r5,%r6
addc,nuv %r4,%r5,%r6
addc,znv %r4,%r5,%r6
addc,sv %r4,%r5,%r6
addc,od %r4,%r5,%r6
addc,tr %r4,%r5,%r6
addc,<> %r4,%r5,%r6
addc,>= %r4,%r5,%r6
addc,> %r4,%r5,%r6
addc,uv %r4,%r5,%r6
addc,vnz %r4,%r5,%r6
addc,nsv %r4,%r5,%r6
addc,ev %r4,%r5,%r6
addco_tests
addco %r4,%r5,%r6
addco,= %r4,%r5,%r6
addco,< %r4,%r5,%r6
addco,<= %r4,%r5,%r6
addco,nuv %r4,%r5,%r6
addco,znv %r4,%r5,%r6
addco,sv %r4,%r5,%r6
addco,od %r4,%r5,%r6
addco,tr %r4,%r5,%r6
addco,<> %r4,%r5,%r6
addco,>= %r4,%r5,%r6
addco,> %r4,%r5,%r6
addco,uv %r4,%r5,%r6
addco,vnz %r4,%r5,%r6
addco,nsv %r4,%r5,%r6
addco,ev %r4,%r5,%r6
sh1add_tests
sh1add %r4,%r5,%r6
sh1add,= %r4,%r5,%r6
sh1add,< %r4,%r5,%r6
sh1add,<= %r4,%r5,%r6
sh1add,nuv %r4,%r5,%r6
sh1add,znv %r4,%r5,%r6
sh1add,sv %r4,%r5,%r6
sh1add,od %r4,%r5,%r6
sh1add,tr %r4,%r5,%r6
sh1add,<> %r4,%r5,%r6
sh1add,>= %r4,%r5,%r6
sh1add,> %r4,%r5,%r6
sh1add,uv %r4,%r5,%r6
sh1add,vnz %r4,%r5,%r6
sh1add,nsv %r4,%r5,%r6
sh1add,ev %r4,%r5,%r6
sh1addl_tests
sh1addl %r4,%r5,%r6
sh1addl,= %r4,%r5,%r6
sh1addl,< %r4,%r5,%r6
sh1addl,<= %r4,%r5,%r6
sh1addl,nuv %r4,%r5,%r6
sh1addl,znv %r4,%r5,%r6
sh1addl,sv %r4,%r5,%r6
sh1addl,od %r4,%r5,%r6
sh1addl,tr %r4,%r5,%r6
sh1addl,<> %r4,%r5,%r6
sh1addl,>= %r4,%r5,%r6
sh1addl,> %r4,%r5,%r6
sh1addl,uv %r4,%r5,%r6
sh1addl,vnz %r4,%r5,%r6
sh1addl,nsv %r4,%r5,%r6
sh1addl,ev %r4,%r5,%r6
sh1addo_tests
sh1addo %r4,%r5,%r6
sh1addo,= %r4,%r5,%r6
sh1addo,< %r4,%r5,%r6
sh1addo,<= %r4,%r5,%r6
sh1addo,nuv %r4,%r5,%r6
sh1addo,znv %r4,%r5,%r6
sh1addo,sv %r4,%r5,%r6
sh1addo,od %r4,%r5,%r6
sh1addo,tr %r4,%r5,%r6
sh1addo,<> %r4,%r5,%r6
sh1addo,>= %r4,%r5,%r6
sh1addo,> %r4,%r5,%r6
sh1addo,uv %r4,%r5,%r6
sh1addo,vnz %r4,%r5,%r6
sh1addo,nsv %r4,%r5,%r6
sh1addo,ev %r4,%r5,%r6
sh2add_tests
sh2add %r4,%r5,%r6
sh2add,= %r4,%r5,%r6
sh2add,< %r4,%r5,%r6
sh2add,<= %r4,%r5,%r6
sh2add,nuv %r4,%r5,%r6
sh2add,znv %r4,%r5,%r6
sh2add,sv %r4,%r5,%r6
sh2add,od %r4,%r5,%r6
sh2add,tr %r4,%r5,%r6
sh2add,<> %r4,%r5,%r6
sh2add,>= %r4,%r5,%r6
sh2add,> %r4,%r5,%r6
sh2add,uv %r4,%r5,%r6
sh2add,vnz %r4,%r5,%r6
sh2add,nsv %r4,%r5,%r6
sh2add,ev %r4,%r5,%r6
sh2addl_tests
sh2addl %r4,%r5,%r6
sh2addl,= %r4,%r5,%r6
sh2addl,< %r4,%r5,%r6
sh2addl,<= %r4,%r5,%r6
sh2addl,nuv %r4,%r5,%r6
sh2addl,znv %r4,%r5,%r6
sh2addl,sv %r4,%r5,%r6
sh2addl,od %r4,%r5,%r6
sh2addl,tr %r4,%r5,%r6
sh2addl,<> %r4,%r5,%r6
sh2addl,>= %r4,%r5,%r6
sh2addl,> %r4,%r5,%r6
sh2addl,uv %r4,%r5,%r6
sh2addl,vnz %r4,%r5,%r6
sh2addl,nsv %r4,%r5,%r6
sh2addl,ev %r4,%r5,%r6
sh2addo_tests
sh2addo %r4,%r5,%r6
sh2addo,= %r4,%r5,%r6
sh2addo,< %r4,%r5,%r6
sh2addo,<= %r4,%r5,%r6
sh2addo,nuv %r4,%r5,%r6
sh2addo,znv %r4,%r5,%r6
sh2addo,sv %r4,%r5,%r6
sh2addo,od %r4,%r5,%r6
sh2addo,tr %r4,%r5,%r6
sh2addo,<> %r4,%r5,%r6
sh2addo,>= %r4,%r5,%r6
sh2addo,> %r4,%r5,%r6
sh2addo,uv %r4,%r5,%r6
sh2addo,vnz %r4,%r5,%r6
sh2addo,nsv %r4,%r5,%r6
sh2addo,ev %r4,%r5,%r6
sh3add_tests
sh3add %r4,%r5,%r6
sh3add,= %r4,%r5,%r6
sh3add,< %r4,%r5,%r6
sh3add,<= %r4,%r5,%r6
sh3add,nuv %r4,%r5,%r6
sh3add,znv %r4,%r5,%r6
sh3add,sv %r4,%r5,%r6
sh3add,od %r4,%r5,%r6
sh3add,tr %r4,%r5,%r6
sh3add,<> %r4,%r5,%r6
sh3add,>= %r4,%r5,%r6
sh3add,> %r4,%r5,%r6
sh3add,uv %r4,%r5,%r6
sh3add,vnz %r4,%r5,%r6
sh3add,nsv %r4,%r5,%r6
sh3add,ev %r4,%r5,%r6
sh3addl_tests
sh3addl %r4,%r5,%r6
sh3addl,= %r4,%r5,%r6
sh3addl,< %r4,%r5,%r6
sh3addl,<= %r4,%r5,%r6
sh3addl,nuv %r4,%r5,%r6
sh3addl,znv %r4,%r5,%r6
sh3addl,sv %r4,%r5,%r6
sh3addl,od %r4,%r5,%r6
sh3addl,tr %r4,%r5,%r6
sh3addl,<> %r4,%r5,%r6
sh3addl,>= %r4,%r5,%r6
sh3addl,> %r4,%r5,%r6
sh3addl,uv %r4,%r5,%r6
sh3addl,vnz %r4,%r5,%r6
sh3addl,nsv %r4,%r5,%r6
sh3addl,ev %r4,%r5,%r6
sh3addo_tests
sh3addo %r4,%r5,%r6
sh3addo,= %r4,%r5,%r6
sh3addo,< %r4,%r5,%r6
sh3addo,<= %r4,%r5,%r6
sh3addo,nuv %r4,%r5,%r6
sh3addo,znv %r4,%r5,%r6
sh3addo,sv %r4,%r5,%r6
sh3addo,od %r4,%r5,%r6
sh3addo,tr %r4,%r5,%r6
sh3addo,<> %r4,%r5,%r6
sh3addo,>= %r4,%r5,%r6
sh3addo,> %r4,%r5,%r6
sh3addo,uv %r4,%r5,%r6
sh3addo,vnz %r4,%r5,%r6
sh3addo,nsv %r4,%r5,%r6
sh3addo,ev %r4,%r5,%r6
sub_tests
sub %r4,%r5,%r6
sub,= %r4,%r5,%r6
sub,< %r4,%r5,%r6
sub,<= %r4,%r5,%r6
sub,<< %r4,%r5,%r6
sub,<<= %r4,%r5,%r6
sub,sv %r4,%r5,%r6
sub,od %r4,%r5,%r6
sub,tr %r4,%r5,%r6
sub,<> %r4,%r5,%r6
sub,>= %r4,%r5,%r6
sub,> %r4,%r5,%r6
sub,>>= %r4,%r5,%r6
sub,>> %r4,%r5,%r6
sub,nsv %r4,%r5,%r6
sub,ev %r4,%r5,%r6
subo_tests
subo %r4,%r5,%r6
subo,= %r4,%r5,%r6
subo,< %r4,%r5,%r6
subo,<= %r4,%r5,%r6
subo,<< %r4,%r5,%r6
subo,<<= %r4,%r5,%r6
subo,sv %r4,%r5,%r6
subo,od %r4,%r5,%r6
subo,tr %r4,%r5,%r6
subo,<> %r4,%r5,%r6
subo,>= %r4,%r5,%r6
subo,> %r4,%r5,%r6
subo,>>= %r4,%r5,%r6
subo,>> %r4,%r5,%r6
subo,nsv %r4,%r5,%r6
subo,ev %r4,%r5,%r6
subb_tests
subb %r4,%r5,%r6
subb,= %r4,%r5,%r6
subb,< %r4,%r5,%r6
subb,<= %r4,%r5,%r6
subb,<< %r4,%r5,%r6
subb,<<= %r4,%r5,%r6
subb,sv %r4,%r5,%r6
subb,od %r4,%r5,%r6
subb,tr %r4,%r5,%r6
subb,<> %r4,%r5,%r6
subb,>= %r4,%r5,%r6
subb,> %r4,%r5,%r6
subb,>>= %r4,%r5,%r6
subb,>> %r4,%r5,%r6
subb,nsv %r4,%r5,%r6
subb,ev %r4,%r5,%r6
subbo_tests
subbo %r4,%r5,%r6
subbo,= %r4,%r5,%r6
subbo,< %r4,%r5,%r6
subbo,<= %r4,%r5,%r6
subbo,<< %r4,%r5,%r6
subbo,<<= %r4,%r5,%r6
subbo,sv %r4,%r5,%r6
subbo,od %r4,%r5,%r6
subbo,tr %r4,%r5,%r6
subbo,<> %r4,%r5,%r6
subbo,>= %r4,%r5,%r6
subbo,> %r4,%r5,%r6
subbo,>>= %r4,%r5,%r6
subbo,>> %r4,%r5,%r6
subbo,nsv %r4,%r5,%r6
subbo,ev %r4,%r5,%r6
subt_tests
subt %r4,%r5,%r6
subt,= %r4,%r5,%r6
subt,< %r4,%r5,%r6
subt,<= %r4,%r5,%r6
subt,<< %r4,%r5,%r6
subt,<<= %r4,%r5,%r6
subt,sv %r4,%r5,%r6
subt,od %r4,%r5,%r6
subt,tr %r4,%r5,%r6
subt,<> %r4,%r5,%r6
subt,>= %r4,%r5,%r6
subt,> %r4,%r5,%r6
subt,>>= %r4,%r5,%r6
subt,>> %r4,%r5,%r6
subt,nsv %r4,%r5,%r6
subt,ev %r4,%r5,%r6
subto_tests
subto %r4,%r5,%r6
subto,= %r4,%r5,%r6
subto,< %r4,%r5,%r6
subto,<= %r4,%r5,%r6
subto,<< %r4,%r5,%r6
subto,<<= %r4,%r5,%r6
subto,sv %r4,%r5,%r6
subto,od %r4,%r5,%r6
subto,tr %r4,%r5,%r6
subto,<> %r4,%r5,%r6
subto,>= %r4,%r5,%r6
subto,> %r4,%r5,%r6
subto,>>= %r4,%r5,%r6
subto,>> %r4,%r5,%r6
subto,nsv %r4,%r5,%r6
subto,ev %r4,%r5,%r6
ds_tests
ds %r4,%r5,%r6
ds,= %r4,%r5,%r6
ds,< %r4,%r5,%r6
ds,<= %r4,%r5,%r6
ds,<< %r4,%r5,%r6
ds,<<= %r4,%r5,%r6
ds,sv %r4,%r5,%r6
ds,od %r4,%r5,%r6
ds,tr %r4,%r5,%r6
ds,<> %r4,%r5,%r6
ds,>= %r4,%r5,%r6
ds,> %r4,%r5,%r6
ds,>>= %r4,%r5,%r6
ds,>> %r4,%r5,%r6
ds,nsv %r4,%r5,%r6
ds,ev %r4,%r5,%r6
comclr_tests
comclr %r4,%r5,%r6
comclr,= %r4,%r5,%r6
comclr,< %r4,%r5,%r6
comclr,<= %r4,%r5,%r6
comclr,<< %r4,%r5,%r6
comclr,<<= %r4,%r5,%r6
comclr,sv %r4,%r5,%r6
comclr,od %r4,%r5,%r6
comclr,tr %r4,%r5,%r6
comclr,<> %r4,%r5,%r6
comclr,>= %r4,%r5,%r6
comclr,> %r4,%r5,%r6
comclr,>>= %r4,%r5,%r6
comclr,>> %r4,%r5,%r6
comclr,nsv %r4,%r5,%r6
comclr,ev %r4,%r5,%r6
or_tests
or %r4,%r5,%r6
or,= %r4,%r5,%r6
or,< %r4,%r5,%r6
or,<= %r4,%r5,%r6
or,od %r4,%r5,%r6
or,tr %r4,%r5,%r6
or,<> %r4,%r5,%r6
or,>= %r4,%r5,%r6
or,> %r4,%r5,%r6
or,ev %r4,%r5,%r6
xor_tests
xor %r4,%r5,%r6
xor,= %r4,%r5,%r6
xor,< %r4,%r5,%r6
xor,<= %r4,%r5,%r6
xor,od %r4,%r5,%r6
xor,tr %r4,%r5,%r6
xor,<> %r4,%r5,%r6
xor,>= %r4,%r5,%r6
xor,> %r4,%r5,%r6
xor,ev %r4,%r5,%r6
and_tests
and %r4,%r5,%r6
and,= %r4,%r5,%r6
and,< %r4,%r5,%r6
and,<= %r4,%r5,%r6
and,od %r4,%r5,%r6
and,tr %r4,%r5,%r6
and,<> %r4,%r5,%r6
and,>= %r4,%r5,%r6
and,> %r4,%r5,%r6
and,ev %r4,%r5,%r6
andcm_tests
andcm %r4,%r5,%r6
andcm,= %r4,%r5,%r6
andcm,< %r4,%r5,%r6
andcm,<= %r4,%r5,%r6
andcm,od %r4,%r5,%r6
andcm,tr %r4,%r5,%r6
andcm,<> %r4,%r5,%r6
andcm,>= %r4,%r5,%r6
andcm,> %r4,%r5,%r6
andcm,ev %r4,%r5,%r6
uxor_tests
uxor %r4,%r5,%r6
uxor,sbz %r4,%r5,%r6
uxor,shz %r4,%r5,%r6
uxor,sdc %r4,%r5,%r6
uxor,sbc %r4,%r5,%r6
uxor,shc %r4,%r5,%r6
uxor,tr %r4,%r5,%r6
uxor,nbz %r4,%r5,%r6
uxor,nhz %r4,%r5,%r6
uxor,ndc %r4,%r5,%r6
uxor,nbc %r4,%r5,%r6
uxor,nhc %r4,%r5,%r6
uaddcm_tests
uaddcm %r4,%r5,%r6
uaddcm,sbz %r4,%r5,%r6
uaddcm,shz %r4,%r5,%r6
uaddcm,sdc %r4,%r5,%r6
uaddcm,sbc %r4,%r5,%r6
uaddcm,shc %r4,%r5,%r6
uaddcm,tr %r4,%r5,%r6
uaddcm,nbz %r4,%r5,%r6
uaddcm,nhz %r4,%r5,%r6
uaddcm,ndc %r4,%r5,%r6
uaddcm,nbc %r4,%r5,%r6
uaddcm,nhc %r4,%r5,%r6
uaddcmt_tests
uaddcmt %r4,%r5,%r6
uaddcmt,sbz %r4,%r5,%r6
uaddcmt,shz %r4,%r5,%r6
uaddcmt,sdc %r4,%r5,%r6
uaddcmt,sbc %r4,%r5,%r6
uaddcmt,shc %r4,%r5,%r6
uaddcmt,tr %r4,%r5,%r6
uaddcmt,nbz %r4,%r5,%r6
uaddcmt,nhz %r4,%r5,%r6
uaddcmt,ndc %r4,%r5,%r6
uaddcmt,nbc %r4,%r5,%r6
uaddcmt,nhc %r4,%r5,%r6
dcor_tests
dcor %r4,%r5
dcor,sbz %r4,%r5
dcor,shz %r4,%r5
dcor,sdc %r4,%r5
dcor,sbc %r4,%r5
dcor,shc %r4,%r5
dcor,tr %r4,%r5
dcor,nbz %r4,%r5
dcor,nhz %r4,%r5
dcor,ndc %r4,%r5
dcor,nbc %r4,%r5
dcor,nhc %r4,%r5
idcor_tests
idcor %r4,%r5
idcor,sbz %r4,%r5
idcor,shz %r4,%r5
idcor,sdc %r4,%r5
idcor,sbc %r4,%r5
idcor,shc %r4,%r5
idcor,tr %r4,%r5
idcor,nbz %r4,%r5
idcor,nhz %r4,%r5
idcor,ndc %r4,%r5
idcor,nbc %r4,%r5
idcor,nhc %r4,%r5
addi_tests
addi 123,%r5,%r6
addi,= 123,%r5,%r6
addi,< 123,%r5,%r6
addi,<= 123,%r5,%r6
addi,nuv 123,%r5,%r6
addi,znv 123,%r5,%r6
addi,sv 123,%r5,%r6
addi,od 123,%r5,%r6
addi,tr 123,%r5,%r6
addi,<> 123,%r5,%r6
addi,>= 123,%r5,%r6
addi,> 123,%r5,%r6
addi,uv 123,%r5,%r6
addi,vnz 123,%r5,%r6
addi,nsv 123,%r5,%r6
addi,ev 123,%r5,%r6
addio_tests
addio 123,%r5,%r6
addio,= 123,%r5,%r6
addio,< 123,%r5,%r6
addio,<= 123,%r5,%r6
addio,nuv 123,%r5,%r6
addio,znv 123,%r5,%r6
addio,sv 123,%r5,%r6
addio,od 123,%r5,%r6
addio,tr 123,%r5,%r6
addio,<> 123,%r5,%r6
addio,>= 123,%r5,%r6
addio,> 123,%r5,%r6
addio,uv 123,%r5,%r6
addio,vnz 123,%r5,%r6
addio,nsv 123,%r5,%r6
addio,ev 123,%r5,%r6
addit_tests
addit 123,%r5,%r6
addit,= 123,%r5,%r6
addit,< 123,%r5,%r6
addit,<= 123,%r5,%r6
addit,nuv 123,%r5,%r6
addit,znv 123,%r5,%r6
addit,sv 123,%r5,%r6
addit,od 123,%r5,%r6
addit,tr 123,%r5,%r6
addit,<> 123,%r5,%r6
addit,>= 123,%r5,%r6
addit,> 123,%r5,%r6
addit,uv 123,%r5,%r6
addit,vnz 123,%r5,%r6
addit,nsv 123,%r5,%r6
addit,ev 123,%r5,%r6
addito_tests
addito 123,%r5,%r6
addito,= 123,%r5,%r6
addito,< 123,%r5,%r6
addito,<= 123,%r5,%r6
addito,nuv 123,%r5,%r6
addito,znv 123,%r5,%r6
addito,sv 123,%r5,%r6
addito,od 123,%r5,%r6
addito,tr 123,%r5,%r6
addito,<> 123,%r5,%r6
addito,>= 123,%r5,%r6
addito,> 123,%r5,%r6
addito,uv 123,%r5,%r6
addito,vnz 123,%r5,%r6
addito,nsv 123,%r5,%r6
addito,ev 123,%r5,%r6
subi_tests
subi 123,%r5,%r6
subi,= 123,%r5,%r6
subi,< 123,%r5,%r6
subi,<= 123,%r5,%r6
subi,<< 123,%r5,%r6
subi,<<= 123,%r5,%r6
subi,sv 123,%r5,%r6
subi,od 123,%r5,%r6
subi,tr 123,%r5,%r6
subi,<> 123,%r5,%r6
subi,>= 123,%r5,%r6
subi,> 123,%r5,%r6
subi,>>= 123,%r5,%r6
subi,>> 123,%r5,%r6
subi,nsv 123,%r5,%r6
subi,ev 123,%r5,%r6
subio_tests
subio 123,%r5,%r6
subio,= 123,%r5,%r6
subio,< 123,%r5,%r6
subio,<= 123,%r5,%r6
subio,<< 123,%r5,%r6
subio,<<= 123,%r5,%r6
subio,sv 123,%r5,%r6
subio,od 123,%r5,%r6
subio,tr 123,%r5,%r6
subio,<> 123,%r5,%r6
subio,>= 123,%r5,%r6
subio,> 123,%r5,%r6
subio,>>= 123,%r5,%r6
subio,>> 123,%r5,%r6
subio,nsv 123,%r5,%r6
subio,ev 123,%r5,%r6
comiclr_tests
comiclr 123,%r5,%r6
comiclr,= 123,%r5,%r6
comiclr,< 123,%r5,%r6
comiclr,<= 123,%r5,%r6
comiclr,<< 123,%r5,%r6
comiclr,<<= 123,%r5,%r6
comiclr,sv 123,%r5,%r6
comiclr,od 123,%r5,%r6
comiclr,tr 123,%r5,%r6
comiclr,<> 123,%r5,%r6
comiclr,>= 123,%r5,%r6
comiclr,> 123,%r5,%r6
comiclr,>>= 123,%r5,%r6
comiclr,>> 123,%r5,%r6
comiclr,nsv 123,%r5,%r6
comiclr,ev 123,%r5,%r6
vshd_tests
vshd %r4,%r5,%r6
vshd,= %r4,%r5,%r6
vshd,< %r4,%r5,%r6
vshd,od %r4,%r5,%r6
vshd,tr %r4,%r5,%r6
vshd,<> %r4,%r5,%r6
vshd,>= %r4,%r5,%r6
vshd,ev %r4,%r5,%r6
shd_tests
shd %r4,%r5,5,%r6
shd,= %r4,%r5,5,%r6
shd,< %r4,%r5,5,%r6
shd,od %r4,%r5,5,%r6
shd,tr %r4,%r5,5,%r6
shd,<> %r4,%r5,5,%r6
shd,>= %r4,%r5,5,%r6
shd,ev %r4,%r5,5,%r6
extru_tests
extru %r4,5,10,%r6
extru,= %r4,5,10,%r6
extru,< %r4,5,10,%r6
extru,od %r4,5,10,%r6
extru,tr %r4,5,10,%r6
extru,<> %r4,5,10,%r6
extru,>= %r4,5,10,%r6
extru,ev %r4,5,10,%r6
extrs_tests
extrs %r4,5,10,%r6
extrs,= %r4,5,10,%r6
extrs,< %r4,5,10,%r6
extrs,od %r4,5,10,%r6
extrs,tr %r4,5,10,%r6
extrs,<> %r4,5,10,%r6
extrs,>= %r4,5,10,%r6
extrs,ev %r4,5,10,%r6
zdep_tests
zdep %r4,5,10,%r6
zdep,= %r4,5,10,%r6
zdep,< %r4,5,10,%r6
zdep,od %r4,5,10,%r6
zdep,tr %r4,5,10,%r6
zdep,<> %r4,5,10,%r6
zdep,>= %r4,5,10,%r6
zdep,ev %r4,5,10,%r6
dep_tests
dep %r4,5,10,%r6
dep,= %r4,5,10,%r6
dep,< %r4,5,10,%r6
dep,od %r4,5,10,%r6
dep,tr %r4,5,10,%r6
dep,<> %r4,5,10,%r6
dep,>= %r4,5,10,%r6
dep,ev %r4,5,10,%r6
vextru_tests
vextru %r4,5,%r6
vextru,= %r4,5,%r6
vextru,< %r4,5,%r6
vextru,od %r4,5,%r6
vextru,tr %r4,5,%r6
vextru,<> %r4,5,%r6
vextru,>= %r4,5,%r6
vextru,ev %r4,5,%r6
vextrs_tests
vextrs %r4,5,%r6
vextrs,= %r4,5,%r6
vextrs,< %r4,5,%r6
vextrs,od %r4,5,%r6
vextrs,tr %r4,5,%r6
vextrs,<> %r4,5,%r6
vextrs,>= %r4,5,%r6
vextrs,ev %r4,5,%r6
zvdep_tests
zvdep %r4,5,%r6
zvdep,= %r4,5,%r6
zvdep,< %r4,5,%r6
zvdep,od %r4,5,%r6
zvdep,tr %r4,5,%r6
zvdep,<> %r4,5,%r6
zvdep,>= %r4,5,%r6
zvdep,ev %r4,5,%r6
vdep_tests
vdep %r4,5,%r6
vdep,= %r4,5,%r6
vdep,< %r4,5,%r6
vdep,od %r4,5,%r6
vdep,tr %r4,5,%r6
vdep,<> %r4,5,%r6
vdep,>= %r4,5,%r6
vdep,ev %r4,5,%r6
vdepi_tests
vdepi -1,5,%r6
vdepi,= -1,5,%r6
vdepi,< -1,5,%r6
vdepi,od -1,5,%r6
vdepi,tr -1,5,%r6
vdepi,<> -1,5,%r6
vdepi,>= -1,5,%r6
vdepi,ev -1,5,%r6
zvdepi_tests
zvdepi -1,5,%r6
zvdepi,= -1,5,%r6
zvdepi,< -1,5,%r6
zvdepi,od -1,5,%r6
zvdepi,tr -1,5,%r6
zvdepi,<> -1,5,%r6
zvdepi,>= -1,5,%r6
zvdepi,ev -1,5,%r6
depi_tests
depi -1,4,10,%r6
depi,= -1,4,10,%r6
depi,< -1,4,10,%r6
depi,od -1,4,10,%r6
depi,tr -1,4,10,%r6
depi,<> -1,4,10,%r6
depi,>= -1,4,10,%r6
depi,ev -1,4,10,%r6
zdepi_tests
zdepi -1,4,10,%r6
zdepi,= -1,4,10,%r6
zdepi,< -1,4,10,%r6
zdepi,od -1,4,10,%r6
zdepi,tr -1,4,10,%r6
zdepi,<> -1,4,10,%r6
zdepi,>= -1,4,10,%r6
zdepi,ev -1,4,10,%r6
system_control_tests
break 5,12
rfi
rfir
ssm 5,%r4
rsm 5,%r4
mtsm %r4
ldsid (%sr0,%r5),%r4
mtsp %r4,%sr0
mtctl %r4,%cr10
mfsp %sr0,%r4
mfctl %cr10,%r4
sync
syncdma
diag 1234
probe_tests
prober (%sr0,%r5),%r6,%r7
proberi (%sr0,%r5),1,%r7
probew (%sr0,%r5),%r6,%r7
probewi (%sr0,%r5),1,%r7
lpa_tests
lpa %r4(%sr0,%r5),%r6
lpa,m %r4(%sr0,%r5),%r6
lha %r4(%sr0,%r5),%r6
lha,m %r4(%sr0,%r5),%r6
lci %r4(%sr0,%r5),%r6
purge_tests
pdtlb %r4(%sr0,%r5)
pdtlb,m %r4(%sr0,%r5)
pitlb %r4(%sr0,%r5)
pitlb,m %r4(%sr0,%r5)
pdtlbe %r4(%sr0,%r5)
pdtlbe,m %r4(%sr0,%r5)
pitlbe %r4(%sr0,%r5)
pitlbe,m %r4(%sr0,%r5)
pdc %r4(%sr0,%r5)
pdc,m %r4(%sr0,%r5)
fdc %r4(%sr0,%r5)
fdc,m %r4(%sr0,%r5)
fic %r4(%sr0,%r5)
fic,m %r4(%sr0,%r5)
fdce %r4(%sr0,%r5)
fdce,m %r4(%sr0,%r5)
fice %r4(%sr0,%r5)
fice,m %r4(%sr0,%r5)
insert_tests
idtlba %r4,(%sr0,%r5)
iitlba %r4,(%sr0,%r5)
idtlbp %r4,(%sr0,%r5)
iitlbp %r4,(%sr0,%r5)
fpu_misc_tests
ftest
fpu_memory_indexing_tests
fldwx %r4(%sr0,%r5),%fr6
fldwx,s %r4(%sr0,%r5),%fr6
fldwx,m %r4(%sr0,%r5),%fr6
fldwx,sm %r4(%sr0,%r5),%fr6
flddx %r4(%sr0,%r5),%fr6
flddx,s %r4(%sr0,%r5),%fr6
flddx,m %r4(%sr0,%r5),%fr6
flddx,sm %r4(%sr0,%r5),%fr6
fstwx %fr6,%r4(%sr0,%r5)
fstwx,s %fr6,%r4(%sr0,%r5)
fstwx,m %fr6,%r4(%sr0,%r5)
fstwx,sm %fr6,%r4(%sr0,%r5)
fstdx %fr6,%r4(%sr0,%r5)
fstdx,s %fr6,%r4(%sr0,%r5)
fstdx,m %fr6,%r4(%sr0,%r5)
fstdx,sm %fr6,%r4(%sr0,%r5)
fstqx %fr6,%r4(%sr0,%r5)
fstqx,s %fr6,%r4(%sr0,%r5)
fstqx,m %fr6,%r4(%sr0,%r5)
fstqx,sm %fr6,%r4(%sr0,%r5)
fpu_short_memory_tests
fldws 0(%sr0,%r5),%fr6
fldws,mb 0(%sr0,%r5),%fr6
fldws,ma 0(%sr0,%r5),%fr6
fldds 0(%sr0,%r5),%fr6
fldds,mb 0(%sr0,%r5),%fr6
fldds,ma 0(%sr0,%r5),%fr6
fstws %fr6,0(%sr0,%r5)
fstws,mb %fr6,0(%sr0,%r5)
fstws,ma %fr6,0(%sr0,%r5)
fstds %fr6,0(%sr0,%r5)
fstds,mb %fr6,0(%sr0,%r5)
fstds,ma %fr6,0(%sr0,%r5)
fstqs %fr6,0(%sr0,%r5)
fstqs,mb %fr6,0(%sr0,%r5)
fstqs,ma %fr6,0(%sr0,%r5)
fcpy_tests
fcpy,sgl %fr5,%fr10
fcpy,dbl %fr5,%fr10
fcpy,quad %fr5,%fr10
fcpy,sgl %fr20,%fr24
fcpy,dbl %fr20,%fr24
fabs_tests
fabs,sgl %fr5,%fr10
fabs,dbl %fr5,%fr10
fabs,quad %fr5,%fr10
fabs,sgl %fr20,%fr24
fabs,dbl %fr20,%fr24
fsqrt_tests
fsqrt,sgl %fr5,%fr10
fsqrt,dbl %fr5,%fr10
fsqrt,quad %fr5,%fr10
fsqrt,sgl %fr20,%fr24
fsqrt,dbl %fr20,%fr24
frnd_tests
frnd,sgl %fr5,%fr10
frnd,dbl %fr5,%fr10
frnd,quad %fr5,%fr10
frnd,sgl %fr20,%fr24
frnd,dbl %fr20,%fr24
fcnvff_tests
fcnvff,sgl,sgl %fr5,%fr10
fcnvff,sgl,dbl %fr5,%fr10
fcnvff,sgl,quad %fr5,%fr10
fcnvff,dbl,sgl %fr5,%fr10
fcnvff,dbl,dbl %fr5,%fr10
fcnvff,dbl,quad %fr5,%fr10
fcnvff,quad,sgl %fr5,%fr10
fcnvff,quad,dbl %fr5,%fr10
fcnvff,quad,quad %fr5,%fr10
fcnvff,sgl,sgl %fr20,%fr24
fcnvff,sgl,dbl %fr20,%fr24
fcnvff,sgl,quad %fr20,%fr24
fcnvff,dbl,sgl %fr20,%fr24
fcnvff,dbl,dbl %fr20,%fr24
fcnvff,dbl,quad %fr20,%fr24
fcnvff,quad,sgl %fr20,%fr24
fcnvff,quad,dbl %fr20,%fr24
fcnvff,quad,quad %fr20,%fr24
fcnvxf_tests
fcnvxf,sgl,sgl %fr5,%fr10
fcnvxf,sgl,dbl %fr5,%fr10
fcnvxf,sgl,quad %fr5,%fr10
fcnvxf,dbl,sgl %fr5,%fr10
fcnvxf,dbl,dbl %fr5,%fr10
fcnvxf,dbl,quad %fr5,%fr10
fcnvxf,quad,sgl %fr5,%fr10
fcnvxf,quad,dbl %fr5,%fr10
fcnvxf,quad,quad %fr5,%fr10
fcnvxf,sgl,sgl %fr20,%fr24
fcnvxf,sgl,dbl %fr20,%fr24
fcnvxf,sgl,quad %fr20,%fr24
fcnvxf,dbl,sgl %fr20,%fr24
fcnvxf,dbl,dbl %fr20,%fr24
fcnvxf,dbl,quad %fr20,%fr24
fcnvxf,quad,sgl %fr20,%fr24
fcnvxf,quad,dbl %fr20,%fr24
fcnvxf,quad,quad %fr20,%fr24
fcnvfx_tests
fcnvfx,sgl,sgl %fr5,%fr10
fcnvfx,sgl,dbl %fr5,%fr10
fcnvfx,sgl,quad %fr5,%fr10
fcnvfx,dbl,sgl %fr5,%fr10
fcnvfx,dbl,dbl %fr5,%fr10
fcnvfx,dbl,quad %fr5,%fr10
fcnvfx,quad,sgl %fr5,%fr10
fcnvfx,quad,dbl %fr5,%fr10
fcnvfx,quad,quad %fr5,%fr10
fcnvfx,sgl,sgl %fr20,%fr24
fcnvfx,sgl,dbl %fr20,%fr24
fcnvfx,sgl,quad %fr20,%fr24
fcnvfx,dbl,sgl %fr20,%fr24
fcnvfx,dbl,dbl %fr20,%fr24
fcnvfx,dbl,quad %fr20,%fr24
fcnvfx,quad,sgl %fr20,%fr24
fcnvfx,quad,dbl %fr20,%fr24
fcnvfx,quad,quad %fr20,%fr24
fcnvfxt_tests
fcnvfxt,sgl,sgl %fr5,%fr10
fcnvfxt,sgl,dbl %fr5,%fr10
fcnvfxt,sgl,quad %fr5,%fr10
fcnvfxt,dbl,sgl %fr5,%fr10
fcnvfxt,dbl,dbl %fr5,%fr10
fcnvfxt,dbl,quad %fr5,%fr10
fcnvfxt,quad,sgl %fr5,%fr10
fcnvfxt,quad,dbl %fr5,%fr10
fcnvfxt,quad,quad %fr5,%fr10
fcnvfxt,sgl,sgl %fr20,%fr24
fcnvfxt,sgl,dbl %fr20,%fr24
fcnvfxt,sgl,quad %fr20,%fr24
fcnvfxt,dbl,sgl %fr20,%fr24
fcnvfxt,dbl,dbl %fr20,%fr24
fcnvfxt,dbl,quad %fr20,%fr24
fcnvfxt,quad,sgl %fr20,%fr24
fcnvfxt,quad,dbl %fr20,%fr24
fcnvfxt,quad,quad %fr20,%fr24
fadd_tests
fadd,sgl %fr4,%fr8,%fr12
fadd,dbl %fr4,%fr8,%fr12
fadd,quad %fr4,%fr8,%fr12
fadd,sgl %fr20,%fr24,%fr28
fadd,dbl %fr20,%fr24,%fr28
fadd,quad %fr20,%fr24,%fr28
fsub_tests
fsub,sgl %fr4,%fr8,%fr12
fsub,dbl %fr4,%fr8,%fr12
fsub,quad %fr4,%fr8,%fr12
fsub,sgl %fr20,%fr24,%fr28
fsub,dbl %fr20,%fr24,%fr28
fsub,quad %fr20,%fr24,%fr28
fmpy_tests
fmpy,sgl %fr4,%fr8,%fr12
fmpy,dbl %fr4,%fr8,%fr12
fmpy,quad %fr4,%fr8,%fr12
fmpy,sgl %fr20,%fr24,%fr28
fmpy,dbl %fr20,%fr24,%fr28
fmpy,quad %fr20,%fr24,%fr28
fdiv_tests
fdiv,sgl %fr4,%fr8,%fr12
fdiv,dbl %fr4,%fr8,%fr12
fdiv,quad %fr4,%fr8,%fr12
fdiv,sgl %fr20,%fr24,%fr28
fdiv,dbl %fr20,%fr24,%fr28
fdiv,quad %fr20,%fr24,%fr28
frem_tests
frem,sgl %fr4,%fr8,%fr12
frem,dbl %fr4,%fr8,%fr12
frem,quad %fr4,%fr8,%fr12
frem,sgl %fr20,%fr24,%fr28
frem,dbl %fr20,%fr24,%fr28
frem,quad %fr20,%fr24,%fr28
fcmp_sgl_tests_1
fcmp,sgl,false? %fr4,%fr5
fcmp,sgl,false %fr4,%fr5
fcmp,sgl,? %fr4,%fr5
fcmp,sgl,!<=> %fr4,%fr5
fcmp,sgl,= %fr4,%fr5
fcmp,sgl,=T %fr4,%fr5
fcmp,sgl,?= %fr4,%fr5
fcmp,sgl,!<> %fr4,%fr5
fcmp_sgl_tests_2
fcmp,sgl,!?>= %fr4,%fr5
fcmp,sgl,< %fr4,%fr5
fcmp,sgl,?< %fr4,%fr5
fcmp,sgl,!>= %fr4,%fr5
fcmp,sgl,!?> %fr4,%fr5
fcmp,sgl,<= %fr4,%fr5
fcmp,sgl,?<= %fr4,%fr5
fcmp,sgl,!> %fr4,%fr5
fcmp_sgl_tests_3
fcmp,sgl,!?<= %fr4,%fr5
fcmp,sgl,> %fr4,%fr5
fcmp,sgl,?> %fr4,%fr5
fcmp,sgl,!<= %fr4,%fr5
fcmp,sgl,!?< %fr4,%fr5
fcmp,sgl,>= %fr4,%fr5
fcmp,sgl,?>= %fr4,%fr5
fcmp,sgl,!< %fr4,%fr5
fcmp_sgl_tests_4
fcmp,sgl,!?= %fr4,%fr5
fcmp,sgl,<> %fr4,%fr5
fcmp,sgl,!= %fr4,%fr5
fcmp,sgl,!=T %fr4,%fr5
fcmp,sgl,!? %fr4,%fr5
fcmp,sgl,<=> %fr4,%fr5
fcmp,sgl,true? %fr4,%fr5
fcmp,sgl,true %fr4,%fr5
fcmp_dbl_tests_1
fcmp,dbl,false? %fr4,%fr5
fcmp,dbl,false %fr4,%fr5
fcmp,dbl,? %fr4,%fr5
fcmp,dbl,!<=> %fr4,%fr5
fcmp,dbl,= %fr4,%fr5
fcmp,dbl,=T %fr4,%fr5
fcmp,dbl,?= %fr4,%fr5
fcmp,dbl,!<> %fr4,%fr5
fcmp_dbl_tests_2
fcmp,dbl,!?>= %fr4,%fr5
fcmp,dbl,< %fr4,%fr5
fcmp,dbl,?< %fr4,%fr5
fcmp,dbl,!>= %fr4,%fr5
fcmp,dbl,!?> %fr4,%fr5
fcmp,dbl,<= %fr4,%fr5
fcmp,dbl,?<= %fr4,%fr5
fcmp,dbl,!> %fr4,%fr5
fcmp_dbl_tests_3
fcmp,dbl,!?<= %fr4,%fr5
fcmp,dbl,> %fr4,%fr5
fcmp,dbl,?> %fr4,%fr5
fcmp,dbl,!<= %fr4,%fr5
fcmp,dbl,!?< %fr4,%fr5
fcmp,dbl,>= %fr4,%fr5
fcmp,dbl,?>= %fr4,%fr5
fcmp,dbl,!< %fr4,%fr5
fcmp_dbl_tests_4
fcmp,dbl,!?= %fr4,%fr5
fcmp,dbl,<> %fr4,%fr5
fcmp,dbl,!= %fr4,%fr5
fcmp,dbl,!=T %fr4,%fr5
fcmp,dbl,!? %fr4,%fr5
fcmp,dbl,<=> %fr4,%fr5
fcmp,dbl,true? %fr4,%fr5
fcmp,dbl,true %fr4,%fr5
fcmp_quad_tests_1
fcmp,quad,false? %fr4,%fr5
fcmp,quad,false %fr4,%fr5
fcmp,quad,? %fr4,%fr5
fcmp,quad,!<=> %fr4,%fr5
fcmp,quad,= %fr4,%fr5
fcmp,quad,=T %fr4,%fr5
fcmp,quad,?= %fr4,%fr5
fcmp,quad,!<> %fr4,%fr5
fcmp_quad_tests_2
fcmp,quad,!?>= %fr4,%fr5
fcmp,quad,< %fr4,%fr5
fcmp,quad,?< %fr4,%fr5
fcmp,quad,!>= %fr4,%fr5
fcmp,quad,!?> %fr4,%fr5
fcmp,quad,<= %fr4,%fr5
fcmp,quad,?<= %fr4,%fr5
fcmp,quad,!> %fr4,%fr5
fcmp_quad_tests_3
fcmp,quad,!?<= %fr4,%fr5
fcmp,quad,> %fr4,%fr5
fcmp,quad,?> %fr4,%fr5
fcmp,quad,!<= %fr4,%fr5
fcmp,quad,!?< %fr4,%fr5
fcmp,quad,>= %fr4,%fr5
fcmp,quad,?>= %fr4,%fr5
fcmp,quad,!< %fr4,%fr5
fcmp_quad_tests_4
fcmp,quad,!?= %fr4,%fr5
fcmp,quad,<> %fr4,%fr5
fcmp,quad,!= %fr4,%fr5
fcmp,quad,!=T %fr4,%fr5
fcmp,quad,!? %fr4,%fr5
fcmp,quad,<=> %fr4,%fr5
fcmp,quad,true? %fr4,%fr5
fcmp,quad,true %fr4,%fr5
fmpy_addsub_tests
fmpyadd,sgl %fr16,%fr17,%fr18,%fr19,%fr20
fmpyadd,dbl %fr16,%fr17,%fr18,%fr19,%fr20
fmpysub,sgl %fr16,%fr17,%fr18,%fr19,%fr20
fmpysub,dbl %fr16,%fr17,%fr18,%fr19,%fr20
xmpyu_tests
xmpyu %fr4,%fr5,%fr6
special_tests
gfw %r4(%sr0,%r5)
gfw,m %r4(%sr0,%r5)
gfr %r4(%sr0,%r5)
gfr,m %r4(%sr0,%r5)
sfu_tests
spop0,4,5
spop0,4,115
spop0,4,5,n
spop0,4,115,n
spop1,4,5 5
spop1,4,115 5
spop1,4,5,n 5
spop1,4,115,n 5
spop2,4,5 5
spop2,4,115 5
spop2,4,5,n 5
spop2,4,115,n 5
spop3,4,5 5,6
spop3,4,115 5,6
spop3,4,5,n 5,6
spop3,4,115,n 5,6
copr_tests
copr,4,5
copr,4,115
copr,4,5,n
copr,4,115,n
copr_indexing_load
cldwx,4 5(0,4),26
cldwx,4,s 5(0,4),26
cldwx,4,m 5(0,4),26
cldwx,4,sm 5(0,4),26
clddx,4 5(0,4),26
clddx,4,s 5(0,4),26
clddx,4,m 5(0,4),26
clddx,4,sm 5(0,4),26
copr_indexing_store
cstwx,4 26,5(0,4)
cstwx,4,s 26,5(0,4)
cstwx,4,m 26,5(0,4)
cstwx,4,sm 26,5(0,4)
cstdx,4 26,5(0,4)
cstdx,4,s 26,5(0,4)
cstdx,4,m 26,5(0,4)
cstdx,4,sm 26,5(0,4)
copr_short_memory
cldws,4 0(0,4),26
cldws,4,mb 0(0,4),26
cldws,4,ma 0(0,4),26
cldds,4 0(0,4),26
cldds,4,mb 0(0,4),26
cldds,4,ma 0(0,4),26
cstws,4 26,0(0,4)
cstws,4,mb 26,0(0,4)
cstws,4,ma 26,0(0,4)
cstds,4 26,0(0,4)
cstds,4,mb 26,0(0,4)
cstds,4,ma 26,0(0,4)
fmemLRbug_tests_1
fstws %fr6R,0(%r26)
fstws %fr6L,4(%r26)
fstws %fr6,8(%r26)
fstds %fr6R,0(%r26)
fstds %fr6L,4(%r26)
fstds %fr6,8(%r26)
fldws 0(%r26),%fr6R
fldws 4(%r26),%fr6L
fldws 8(%r26),%fr6
fldds 0(%r26),%fr6R
fldds 4(%r26),%fr6L
fldds 8(%r26),%fr6
fmemLRbug_tests_2
fstws %fr6R,0(%sr0,%r26)
fstws %fr6L,4(%sr0,%r26)
fstws %fr6,8(%sr0,%r26)
fstds %fr6R,0(%sr0,%r26)
fstds %fr6L,4(%sr0,%r26)
fstds %fr6,8(%sr0,%r26)
fldws 0(%sr0,%r26),%fr6R
fldws 4(%sr0,%r26),%fr6L
fldws 8(%sr0,%r26),%fr6
fldds 0(%sr0,%r26),%fr6R
fldds 4(%sr0,%r26),%fr6L
fldds 8(%sr0,%r26),%fr6
fmemLRbug_tests_3
fstwx %fr6R,%r25(%r26)
fstwx %fr6L,%r25(%r26)
fstwx %fr6,%r25(%r26)
fstdx %fr6R,%r25(%r26)
fstdx %fr6L,%r25(%r26)
fstdx %fr6,%r25(%r26)
fldwx %r25(%r26),%fr6R
fldwx %r25(%r26),%fr6L
fldwx %r25(%r26),%fr6
flddx %r25(%r26),%fr6R
flddx %r25(%r26),%fr6L
flddx %r25(%r26),%fr6
fmemLRbug_tests_4
fstwx %fr6R,%r25(%sr0,%r26)
fstwx %fr6L,%r25(%sr0,%r26)
fstwx %fr6,%r25(%sr0,%r26)
fstdx %fr6R,%r25(%sr0,%r26)
fstdx %fr6L,%r25(%sr0,%r26)
fstdx %fr6,%r25(%sr0,%r26)
fldwx %r25(%sr0,%r26),%fr6R
fldwx %r25(%sr0,%r26),%fr6L
fldwx %r25(%sr0,%r26),%fr6
flddx %r25(%sr0,%r26),%fr6R
flddx %r25(%sr0,%r26),%fr6L
flddx %r25(%sr0,%r26),%fr6
ldw 0(0,%r4),%r26
ldw 0(0,%r4),%r26
ldo 64(%r4),%r30
ldwm -64(0,%r30),%r4
bv,n 0(%r2)
.EXIT
.PROCEND
|
stsp/binutils-ia16
| 2,899
|
gdb/testsuite/gdb.disasm/mn10200.s
|
.text
.global _main
.global add_tests
.global bCC_tests
.global bCCx_tests
.global bit_tests
.global cmp_tests
.global extend_tests
.global logical_tests
.global mov_tests_1
.global mov_tests_2
.global mov_tests_3
.global mov_tests_4
.global movb_tests
.global movbu_tests
.global movx_tests
.global misc_tests
.global shift_tests
.global sub_tests
_main:
nop
add_tests:
add d1,d2
add d2,a3
add a2,d1
add a3,a2
add 16,d1
add 256,d2
add 131071,d3
add 16,a1
add 256,a2
add 131071,a3
addc d1,d2
addnf 16,a2
bCC_tests:
beq bCC_tests
bne bCC_tests
bgt bCC_tests
bge bCC_tests
ble bCC_tests
blt bCC_tests
bhi bCC_tests
bcc bCC_tests
bls bCC_tests
bcs bCC_tests
bvc bCC_tests
bvs bCC_tests
bnc bCC_tests
bns bCC_tests
bra bCC_tests
bCCx_tests:
beqx bCCx_tests
bnex bCCx_tests
bgtx bCCx_tests
bgex bCCx_tests
blex bCCx_tests
bltx bCCx_tests
bhix bCCx_tests
bccx bCCx_tests
blsx bCCx_tests
bcsx bCCx_tests
bvcx bCCx_tests
bvsx bCCx_tests
bncx bCCx_tests
bnsx bCCx_tests
bit_tests:
btst 64,d1
btst 8192,d2
bset d1,(a2)
bclr d1,(a2)
cmp_tests:
cmp d1,d2
cmp d2,a3
cmp a3,d3
cmp a3,a2
cmp 16,d3
cmp 256,d2
cmp 131071,d1
cmp 256,a2
cmp 131071,a1
extend_tests:
ext d1
extx d2
extxu d3
extxb d2
extxbu d1
logical_tests:
and d1,d2
and 127,d2
and 32767,d3
and 32767,psw
or d1,d2
or 127,d2
or 32767,d3
or 32767,psw
xor d1,d2
xor 32767,d3
not d3
mov_tests_1:
mov d1,a2
mov a2,d1
mov d1,d2
mov a2,a1
mov psw,d3
mov d2,psw
mov mdr,d1
mov d2,mdr
mov (a2),d1
mov (8,a2),d1
mov (256,a2),d1
mov (131071,a2),d1
mov_tests_2:
mov (d1,a1),d2
mov (32768),d1
mov (131071),d1
mov (8,a2),a1
mov (256,a2),a1
mov (131071,a2),a1
mov (d1,a1),a2
mov (32768),a1
mov (131071),a1
mov_tests_3:
mov d1,(a2)
mov d1,(32,a2)
mov d1,(256,a2)
mov d1,(131071,a2)
mov d1,(d2,a2)
mov d1,(128)
mov d1,(131071)
mov a1,(32,a2)
mov a1,(256,a2)
mov a1,(131071,a2)
mov_tests_4:
mov a1,(d2,a2)
mov a1,(128)
mov a1,(131071)
mov 8,d1
mov 256,d1
mov 131071,d1
mov 256,a1
mov 131071,a1
movb_tests:
movb (8,a2),d1
movb (256,a2),d1
movb (131071,a2),d1
movb (d2,a2),d3
movb (131071),d2
movb d1,(a2)
movb d1,(8,a2)
movb d1,(256,a2)
movb d1,(131071,a2)
movb d1,(d2,a2)
movb d1,(256)
movb d1,(131071)
movbu_tests:
movbu (a2),d1
movbu (8,a2),d1
movbu (256,a2),d1
movbu (131071,a2),d1
movbu (d1,a1),d2
movbu (32768),d1
movbu (131071),d1
movx_tests:
movx (8,a2),d1
movx (256,a2),d1
movx (131071,a2),d1
movx d1,(8,a2)
movx d1,(256,a2)
movx d1,(131071,a2)
muldiv_tests:
mul d1,d2
mulu d2,d3
divu d3,d2
misc_tests:
jmp _main
jmp _start
jmp (a2)
jsr _main
jsr _start
jsr (a2)
rts
rti
nop
shift_tests:
asr d2
lsr d3
ror d1
rol d2
sub_tests:
sub d1,d2
sub d2,a3
sub a3,d3
sub a3,a2
sub 32767,d2
sub 131071,d2
sub 32767,a2
sub 131071,a2
subc d1,d2
|
stsp/binutils-ia16
| 5,814
|
gdb/testsuite/gdb.disasm/h8300s.s
|
.h8300s
.section .text
.align 2
.global _main
.global movb_tests
.global movw_tests
.global movl_tests
.global ldm_stm_tests
.global movfpe_movtpe_tests
.global add_sub_addx_subx_tests
.global inc_dec_adds_subs_tests
.global daa_das_tests
.global mul_div_tests
.global cmp_tests
.global neg_tests
.global ext_tests
.global tas_mac_tests
.global logic_operations_tests
.global sha_shl_tests
.global rot_rotx_tests
.global bset_bclr_tests
.global bnot_btst_tests
.global band_bor_bxor_tests
.global bld_bst_tests
.global branch_tests
.global system_control_tests
.global block_data_transfer_tests
_main:
nop
movb_tests:
mov.b r0l,r0h
mov.b #0x12,r1l
mov.b @er0,r1h
mov.b @(0x1234:16,er0),r2l
mov.b @(0x12345678:32,er0),r2h
mov.b @er0+,r3l
mov.b @0x12:8,r3h
mov.b @0x1234:16,r4l
mov.b @0x12345678:32,r4h
movw_tests:
mov.w e0,r0
mov.w #0x1234,r1
mov.w @er0,r2
mov.w @(0x1234:16,er0),r3
mov.w @(0x12345678:32,er0),r4
mov.w @er0+,r5
mov.w @0x1234:16,r6
mov.w @0x12345678:32,r7
movl_tests:
mov.l er0,er1
mov.l #0x12345678,er1
mov.l @er0,er2
mov.l @(0x1234:16,er0),er3
mov.l @(0x12345678:32,er0),er4
mov.l @er0+,er5
mov.l @0x1234:16,er6
mov.l @0x12345678:32,er7
ldm_stm_tests:
ldm.l @sp+,er0-er1
ldm.l @sp+,er0-er2
ldm.l @sp+,er0-er3
stm.l er0-er1,@-sp
stm.l er0-er2,@-sp
stm.l er0-er3,@-sp
movfpe_movtpe_tests:
movfpe @0x1234:16,r2l
movtpe r2l,@0x1234:16
add_sub_addx_subx_tests:
add.b #0x12,r0l
add.b r1l,r1h
add.w #0x1234,r2
add.w r3,r4
add.l #0x12345678,er5
add.l er6,er7
sub.b r1l,r1h
sub.w #0x1234,r2
sub.w r3,r4
sub.l #0x12345678,er5
sub.l er6,er7
addx #0x12,r0l
addx r1l,r1h
subx #0x12,r0l
subx r1l,r1h
inc_dec_adds_subs_tests:
inc.b r0l
inc.w #0x1,r4
inc.w #0x2,r3
inc.l #0x1,er2
inc.l #0x2,er1
dec.b r0l
dec.w #0x1,r4
dec.w #0x2,r3
dec.l #0x1,er2
dec.l #0x2,er1
adds #0x1,er7
adds #0x2,er6
adds #0x4,er5
subs #0x1,er7
subs #0x2,er6
subs #0x4,er5
daa_das_tests:
daa r0l
das r0h
mul_div_tests:
mulxs.b r0l,r1
mulxs.w r2,er3
mulxu.b r0l,e1
mulxu.w e2,er3
divxs.b r0l,r1
divxs.w r2,er3
divxu.b r0l,e1
divxu.w e2,er3
cmp_tests:
cmp.b #0x12,r0l
cmp.b r1l,r1h
cmp.w #0x1234,r2
cmp.w r3,e3
cmp.l #0x12345678,er4
cmp.l er5,er6
neg_tests:
neg.b r0l
neg.w r2
neg.l er3
ext_tests:
exts.w r0
exts.l er1
extu.w r2
extu.l er3
tas_mac_tests:
tas @er0
mac @er1+,@er2+
clrmac
ldmac er4,mach
ldmac er5,macl
stmac mach,er6
stmac macl,er7
logic_operations_tests:
and.b #0x12,r0l
and.b r1l,r2h
and.w #0x1234,r0
and.w r1,r2
and.l #0x12345678,er0
and.l er1,er2
or.b #0x12,r0l
or.b r1l,r2h
or.w #0x1234,r0
or.w r1,r2
or.l #0x12345678,er0
or.l er1,er2
xor.b #0x12,r0l
xor.b r1l,r2h
xor.w #0x1234,r0
xor.w r1,r2
xor.l #0x12345678,er0
xor.l er1,er2
not.b r0l
not.w r1
not.l er2
sha_shl_tests:
shal r0l
shal r1
shal er2
shar r3l
shar r4
shar er5
shll r0l
shll r1
shll er2
shlr r3l
shlr r4
shlr er5
rot_rotx_tests:
rotl r0l
rotl r1
rotl er2
rotr r3l
rotr r4
rotr er5
rotxl r0l
rotxl r1
rotxl er2
rotxr r3l
rotxr r4
rotxr er5
bset_bclr_tests:
bset #0x7,r0l
bset #0x6,@er1
bset #0x5,@0x12:8
bset #0x4,@0x1234:16
bset #0x3,@0x12345678:32
bset r7l,r0h
bset r6l,@er1
bset r5l,@0x12:8
bset r4l,@0x1234:16
bset r3l,@0x12345678:32
bclr #0x7,r0l
bclr #0x6,@er1
bclr #0x5,@0x12:8
bclr #0x4,@0x1234:16
bclr #0x3,@0x12345678:32
bclr r7h,r0h
bclr r6h,@er1
bclr r5h,@0x12:8
bclr r4h,@0x1234:16
bclr r3h,@0x12345678:32
bnot_btst_tests:
bnot #0x7,r0l
bnot #0x6,@er1
bnot #0x5,@0x12:8
bnot #0x4,@0x1234:16
bnot #0x3,@0x12345678:32
bnot r7l,r0h
bnot r6l,@er1
bnot r5l,@0x12:8
bnot r4l,@0x1234:16
bnot r3l,@0x12345678:32
btst #0x7,r0l
btst #0x6,@er1
btst #0x5,@0x12:8
btst #0x4,@0x1234:16
btst #0x3,@0x12345678:32
btst r7h,r0h
btst r6h,@er1
btst r5h,@0x12:8
btst r4h,@0x1234:16
btst r3h,@0x12345678:32
band_bor_bxor_tests:
band #0x7,r0l
band #0x6,@er1
band #0x5,@0x12:8
band #0x4,@0x1234:16
band #0x3,@0x12345678:32
bor #0x7,r0l
bor #0x6,@er1
bor #0x5,@0x12:8
bor #0x4,@0x1234:16
bor #0x3,@0x12345678:32
bxor #0x7,r0l
bxor #0x6,@er1
bxor #0x5,@0x12:8
bxor #0x4,@0x1234:16
bxor #0x3,@0x12345678:32
bld_bst_tests:
bld #0x7,r0l
bld #0x6,@er1
bld #0x5,@0x12:8
bld #0x4,@0x1234:16
bld #0x3,@0x12345678:32
bild #0x7,r0l
bild #0x6,@er1
bild #0x5,@0x12:8
bild #0x4,@0x1234:16
bild #0x3,@0x12345678:32
bst #0x7,r0l
bst #0x6,@er1
bst #0x5,@0x12:8
bst #0x4,@0x1234:16
bst #0x3,@0x12345678:32
bist #0x7,r0l
bist #0x6,@er1
bist #0x5,@0x12:8
bist #0x4,@0x1234:16
bist #0x3,@0x12345678:32
branch_tests:
bra branch_tests
brn branch_tests
bhi branch_tests
bls branch_tests
bcc branch_tests
bcs branch_tests
bne branch_tests
beq branch_tests
bvc branch_tests
bvs branch_tests
bpl branch_tests
bmi branch_tests
bge branch_tests
blt branch_tests
bgt branch_tests
ble branch_tests
jmp @er0
jmp @branch_tests
jmp @@0 (0)
bsr branch_tests:8
bsr branch_tests:16
jsr @er0
jsr @branch_tests
jsr @@0 (0)
rts
system_control_tests:
trapa #0x2
rte
sleep
ldc #0x12,ccr
ldc r3l,ccr
ldc @er0,ccr
ldc @(0x1234:16,er0),ccr
ldc @(0x12345678:32,er0),ccr
ldc @er1+,ccr
ldc @0x1234:16,ccr
ldc @0x12345678:32,ccr
stc ccr,r3l
stc ccr,@er0
stc ccr,@(0x1234:16,er0)
stc ccr,@(0x12345678:32,er0)
stc ccr,@-er1
stc ccr,@0x1234:16
stc ccr,@0x12345678:32
andc #0x12,ccr
orc #0x34,ccr
xorc #0x56,ccr
ldc #0x12,exr
ldc r3l,exr
ldc @er0,exr
ldc @(0x1234:16,er0),exr
ldc @(0x12345678:32,er0),exr
ldc @er1+,exr
ldc @0x1234:16,exr
ldc @0x12345678:32,exr
stc exr,r3l
stc exr,@er0
stc exr,@(0x1234:16,er0)
stc exr,@(0x12345678:32,er0)
stc exr,@-er1
stc exr,@0x1234:16
stc exr,@0x12345678:32
andc #0x12,exr
orc #0x34,exr
xorc #0x56,exr
nop
block_data_transfer_tests:
eepmov.b
eepmov.w
|
stsp/binutils-ia16
| 4,998
|
gdb/testsuite/gdb.disasm/t06_ari2.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;arith_2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
addx.b #0x12:8,r1h ;9112
addx.b #0x12:8,@er1 ;7d109012
addx.b #0x12:8,@er1- ;01766c189012
addx.b r3h,r1h ;0e31
addx.b r3h,@er1 ;7d100e30
addx.b r3h,@er1- ;01766c180e30
addx.b @er3,r1h ;7c300e01
addx.b @er3,@er1 ;0174683d0110
addx.b @er3-,r1h ;01766c300e01
addx.b @er3-,@er1- ;01766c3da110
addx.w #0x1234:16,r1 ;015179111234
addx.w #0x1234:16,@er1 ;7d9179101234
addx.w #0x1234:16,@er1- ;01566d1979101234
addx.w r3,r1 ;01510931
addx.w r3,@er1 ;7d910930
addx.w r3,@er1- ;01566d190930
addx.w @er3,r1 ;7cb10901
addx.w @er3,@er1 ;0154693d0110
addx.w @er3-,r1 ;01566d310901
addx.w @er3-,@er1- ;01566d3da110
addx.l #0x12345678:32,er1 ;01017a1112345678
addx.l #0x12345678:32,@er1 ;010469197a1012345678
addx.l #0x12345678:32,@er1- ;01066d197a1012345678
addx.l er3,er1 ;01010ab1
addx.l er3,@er1 ;010469190ab0
addx.l er3,@er1- ;01066d190ab0
addx.l @er3,er1 ;010469310a81
addx.l @er3,@er1 ;0104693d0110
addx.l @er3-,er1 ;01066d310a81
addx.l @er3-,@er1- ;01066d3da110
subx.b #0x12:8,r1h ;b112
subx.b #0x12:8,@er1 ;7d10b012
subx.b #0x12:8,@er1- ;01766c18b012
subx.b r3h,r1h ;1e31
subx.b r3h,@er1 ;7d101e30
subx.b r3h,@er1- ;01766c181e30
subx.b @er3,r1h ;7c301e01
subx.b @er3,@er1 ;0174683d0130
subx.b @er3-,r1h ;01766c301e01
subx.b @er3-,@er1- ;01766c3da130
subx.w #0x1234:16,r1 ;015179311234
subx.w #0x1234:16,@er1 ;7d9179301234
subx.w #0x1234:16,@er1- ;01566d1979301234
subx.w r3,r1 ;01511931
subx.w r3,@er1 ;7d911930
subx.w r3,@er1- ;01566d191930
subx.w @er3,r1 ;7cb11901
subx.w @er3,@er1 ;0154693d0130
subx.w @er3-,r1 ;01566d311901
subx.w @er3-,@er1- ;01566d3da130
subx.l #0x12345678:32,er1 ;01017a3112345678
subx.l #0x12345678:32,@er1 ;010469197a3012345678
subx.l #0x12345678:32,@er1- ;01066d197a3012345678
subx.l er3,er1 ;01011ab1
subx.l er3,@er1 ;010469191ab0
subx.l er3,@er1- ;01066d191ab0
subx.l @er3,er1 ;010469311a81
subx.l @er3,@er1 ;0104693d0130
subx.l @er3-,er1 ;01066d311a81
subx.l @er3-,@er1- ;01066d3da130
inc.b r1h ;0a01
inc.w #1,r1 ;0b51
inc.w #2,r1 ;0bd1
inc.l #1,er1 ;0b71
inc.l #2,er1 ;0bf1
dec.b r1h ;1a01
dec.w #1,r1 ;1b51
dec.w #2,r1 ;1bd1
dec.l #1,er1 ;1b71
dec.l #2,er1 ;1bf1
adds.l #1,er1 ;0b01
adds.l #2,er1 ;0b81
adds.l #4,er1 ;0b91
subs.l #1,er1 ;1b01
subs.l #2,er1 ;1b81
subs.l #4,er1 ;1b91
daa.b r1h ;0f01
das.b r1h ;1f01
mulxu.b #0xf:4,r1 ;01cc50f1
mulxu.b r3h,r1 ;5031
mulxu.w #0xf:4,er1 ;01cc52f1
mulxu.w r3,er1 ;5231
divxu.b #0xf:4,r1 ;01dc51f1
divxu.b r3h,r1 ;5131
divxu.w #0xf:4,er1 ;01dc53f1
divxu.w r3,er1 ;5331
mulxs.b #0xf:4,r1 ;01c450f1
mulxs.b r3h,r1 ;01c05031
mulxs.w #0xf:4,er1 ;01c452f1
mulxs.w r3,er1 ;01c05231
divxs.b #0xf:4,r1 ;01d451f1
divxs.b r3h,r1 ;01d05131
divxs.w #0xf:4,er1 ;01d453f1
divxs.w r3,er1 ;01d05331
mulu.w #0xf:4,r1 ;01ce50f1
mulu.w r3,r1 ;01ca5031
mulu.l #0xf:4,er1 ;01ce52f1
mulu.l er3,er1 ;01ca5231
mulu/u.l #0xf:4,er1 ;01cf52f1
mulu/u.l er3,er1 ;01cb5231
muls.w #0xf:4,r1 ;01c650f1
muls.w r3,r1 ;01c25031
muls.l #0xf:4,er1 ;01c652f1
muls.l er3,er1 ;01c25231
muls/u.l #0xf:4,er1 ;01c752f1
muls/u.l er3,er1 ;01c35231
divu.w #0xf:4,r1 ;01de51f1
divu.w r3,r1 ;01da5131
divu.l #0xf:4,er1 ;01de53f1
divu.l er3,er1 ;01da5331
divs.w #0xf:4,r1 ;01d651f1
divs.w r3,r1 ;01d25131
divs.l #0xf:4,er1 ;01d653f1
divs.l er3,er1 ;01d25331
.end
|
stsp/binutils-ia16
| 66,800
|
gdb/testsuite/gdb.disasm/t01_mov.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;mov
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
mov.b #0x12:8,r3h ;f312
mov.b #0x12:8,@er3 ;017d0312
mov.b #0x12:8,@(0x1:2,er3) ;017d1312
mov.b #0x12:8,@-er3 ;017db312
mov.b #0x12:8,@er3+ ;017d8312
mov.b #0x12:8,@er3- ;017da312
mov.b #0x12:8,@+er3 ;017d9312
mov.b #0x12:8,@(0x1234:16,er3) ;017dc3121234
mov.b #0x12:8,@(0x12345678:32,er3) ;017dcb1212345678
mov.b #0x12:8,@(0x1234:16,r3l.b) ;017dd3121234
mov.b #0x12:8,@(0x1234:16,r3.w) ;017de3121234
mov.b #0x12:8,@(0x1234:16,er3.l) ;017df3121234
mov.b #0x12:8,@(0x12345678:32,r3l.b) ;017ddb1212345678
mov.b #0x12:8,@(0x12345678:32,r3.w) ;017deb1212345678
mov.b #0x12:8,@(0x12345678:32,er3.l) ;017dfb1212345678
mov.b #0x12:8,@0x1234:16 ;017d40121234
mov.b #0x12:8,@0x12345678:32 ;017d481212345678
mov.b #0x1:4,@0x1234:16 ;6ad11234
mov.b #0x1:4,@0x12345678:32 ;6af112345678
mov.b r3h,r1h ;0c31
mov.b r3h,@er1 ;6893
mov.b r3h,@(0x1:2,er1) ;01716893
mov.b r3h,@-er1 ;6c93
mov.b r3h,@er1+ ;01736c93
mov.b r3h,@er1- ;01716c93
mov.b r3h,@+er1 ;01726c93
mov.b r3h,@(0x1234:16,er1) ;6e931234
mov.b r3h,@(0x12345678:32,er1) ;78106aa312345678
mov.b r3h,@(0x1234:16,r1l.b) ;01716e931234
mov.b r3h,@(0x1234:16,r1.w) ;01726e931234
mov.b r3h,@(0x1234:16,er1.l) ;01736e931234
mov.b r3h,@(0x12345678:32,r1l.b) ;78116aa312345678
mov.b r3h,@(0x12345678:32,r1.w) ;78126aa312345678
mov.b r3h,@(0x12345678:32,er1.l) ;78136aa312345678
mov.b r3h,@0xffffff12:8 ;3312
mov.b r3h,@0x1234:16 ;6a831234
mov.b r3h,@0x12345678:32 ;6aa312345678
mov.b @er3,r1h ;6831
mov.b @(0x1:2,er3),r1h ;01716831
mov.b @er3+,r1h ;6c31
mov.b @-er3,r1h ;01736c31
mov.b @+er3,r1h ;01716c31
mov.b @er3-,r1h ;01726c31
mov.b @(0x1234:16,er3),r1h ;6e311234
mov.b @(0x12345678:32,er3),r1h ;78306a2112345678
mov.b @(0x1234:16,r3l.b),r1h ;01716e311234
mov.b @(0x1234:16,r3.w),r1h ;01726e311234
mov.b @(0x1234:16,er3.l),r1h ;01736e311234
mov.b @(0x12345678:32,r3l.b),r1h ;78316a2112345678
mov.b @(0x12345678:32,r3.w),r1h ;78326a2112345678
mov.b @(0x12345678:32,er3.l),r1h ;78336a2112345678
mov.b @0xffffff12:8,r3h ;2312
mov.b @0x1234:16,r3h ;6a031234
mov.b @0x12345678:32,r3h ;6a2312345678
mov.b @er3,@er1 ;01780301
mov.b @er3,@(0x1:2,er1) ;01780311
mov.b @er3,@er1+ ;01780381
mov.b @er3,@-er1 ;017803b1
mov.b @er3,@+er1 ;01780391
mov.b @er3,@er1- ;017803a1
mov.b @er3,@(0x1234:16,er1) ;017803c11234
mov.b @er3,@(0x12345678:32,er1) ;017803c912345678
mov.b @er3,@(0x1234:16,r1l.b) ;017803d11234
mov.b @er3,@(0x1234:16,r1.w) ;017803e11234
mov.b @er3,@(0x1234:16,er1.l) ;017803f11234
mov.b @er3,@(0x12345678:32,r1l.b) ;017803d912345678
mov.b @er3,@(0x12345678:32,r1.w) ;017803e912345678
mov.b @er3,@(0x12345678:32,er1.l) ;017803f912345678
mov.b @er3,@0x1234:16 ;017803401234
mov.b @er3,@0x12345678:32 ;0178034812345678
mov.b @(0x1:2,er3),@er1 ;01781301
mov.b @(0x1:2,er3),@(0x1:2,er1) ;01781311
mov.b @(0x1:2,er3),@er1+ ;01781381
mov.b @(0x1:2,er3),@-er1 ;017813b1
mov.b @(0x1:2,er3),@+er1 ;01781391
mov.b @(0x1:2,er3),@er1- ;017813a1
mov.b @(0x1:2,er3),@(0x1234:16,er1) ;017813c11234
mov.b @(0x1:2,er3),@(0x12345678:32,er1) ;017813c912345678
mov.b @(0x1:2,er3),@(0x1234:16,r1l.b) ;017813d11234
mov.b @(0x1:2,er3),@(0x1234:16,r1.w) ;017813e11234
mov.b @(0x1:2,er3),@(0x1234:16,er1.l) ;017813f11234
mov.b @(0x1:2,er3),@(0x12345678:32,r1l.b) ;017813d912345678
mov.b @(0x1:2,er3),@(0x12345678:32,r1.w) ;017813e912345678
mov.b @(0x1:2,er3),@(0x12345678:32,er1.l) ;017813f912345678
mov.b @(0x1:2,er3),@0x1234:16 ;017813401234
mov.b @(0x1:2,er3),@0x12345678:32 ;0178134812345678
mov.b @-er3,@er1 ;0178b301
mov.b @-er3,@(0x1:2,er1) ;0178b311
mov.b @-er3,@er1+ ;0178b381
mov.b @-er3,@-er1 ;0178b3b1
mov.b @-er3,@+er1 ;0178b391
mov.b @-er3,@er1- ;0178b3a1
mov.b @-er3,@(0x1234:16,er1) ;0178b3c11234
mov.b @-er3,@(0x12345678:32,er1) ;0178b3c912345678
mov.b @-er3,@(0x1234:16,r1l.b) ;0178b3d11234
mov.b @-er3,@(0x1234:16,r1.w) ;0178b3e11234
mov.b @-er3,@(0x1234:16,er1.l) ;0178b3f11234
mov.b @-er3,@(0x12345678:32,r1l.b) ;0178b3d912345678
mov.b @-er3,@(0x12345678:32,r1.w) ;0178b3e912345678
mov.b @-er3,@(0x12345678:32,er1.l) ;0178b3f912345678
mov.b @-er3,@0x1234:16 ;0178b3401234
mov.b @-er3,@0x12345678:32 ;0178b34812345678
mov.b @er3+,@er1 ;01788301
mov.b @er3+,@(0x1:2,er1) ;01788311
mov.b @er3+,@er1+ ;01788381
mov.b @er3+,@-er1 ;017883b1
mov.b @er3+,@+er1 ;01788391
mov.b @er3+,@er1- ;017883a1
mov.b @er3+,@(0x1234:16,er1) ;017883c11234
mov.b @er3+,@(0x12345678:32,er1) ;017883c912345678
mov.b @er3+,@(0x1234:16,r1l.b) ;017883d11234
mov.b @er3+,@(0x1234:16,r1.w) ;017883e11234
mov.b @er3+,@(0x1234:16,er1.l) ;017883f11234
mov.b @er3+,@(0x12345678:32,r1l.b) ;017883d912345678
mov.b @er3+,@(0x12345678:32,r1.w) ;017883e912345678
mov.b @er3+,@(0x12345678:32,er1.l) ;017883f912345678
mov.b @er3+,@0x1234:16 ;017883401234
mov.b @er3+,@0x12345678:32 ;0178834812345678
mov.b @er3-,@er1 ;0178a301
mov.b @er3-,@(0x1:2,er1) ;0178a311
mov.b @er3-,@er1+ ;0178a381
mov.b @er3-,@-er1 ;0178a3b1
mov.b @er3-,@+er1 ;0178a391
mov.b @er3-,@er1- ;0178a3a1
mov.b @er3-,@(0x1234:16,er1) ;0178a3c11234
mov.b @er3-,@(0x12345678:32,er1) ;0178a3c912345678
mov.b @er3-,@(0x1234:16,r1l.b) ;0178a3d11234
mov.b @er3-,@(0x1234:16,r1.w) ;0178a3e11234
mov.b @er3-,@(0x1234:16,er1.l) ;0178a3f11234
mov.b @er3-,@(0x12345678:32,r1l.b) ;0178a3d912345678
mov.b @er3-,@(0x12345678:32,r1.w) ;0178a3e912345678
mov.b @er3-,@(0x12345678:32,er1.l) ;0178a3f912345678
mov.b @er3-,@0x1234:16 ;0178a3401234
mov.b @er3-,@0x12345678:32 ;0178a34812345678
mov.b @+er3,@er1 ;01789301
mov.b @+er3,@(0x1:2,er1) ;01789311
mov.b @+er3,@er1+ ;01789381
mov.b @+er3,@-er1 ;017893b1
mov.b @+er3,@+er1 ;01789391
mov.b @+er3,@er1- ;017893a1
mov.b @+er3,@(0x1234:16,er1) ;017893c11234
mov.b @+er3,@(0x12345678:32,er1) ;017893c912345678
mov.b @+er3,@(0x1234:16,r1l.b) ;017893d11234
mov.b @+er3,@(0x1234:16,r1.w) ;017893e11234
mov.b @+er3,@(0x1234:16,er1.l) ;017893f11234
mov.b @+er3,@(0x12345678:32,r1l.b) ;017893d912345678
mov.b @+er3,@(0x12345678:32,r1.w) ;017893e912345678
mov.b @+er3,@(0x12345678:32,er1.l) ;017893f912345678
mov.b @+er3,@0x1234:16 ;017893401234
mov.b @+er3,@0x12345678:32 ;0178934812345678
mov.b @(0x1234:16,er3),@er1 ;0178c3011234
mov.b @(0x1234:16,er3),@(0x1:2,er1) ;0178c3111234
mov.b @(0x1234:16,er3),@er1+ ;0178c3811234
mov.b @(0x1234:16,er3),@-er1 ;0178c3b11234
mov.b @(0x1234:16,er3),@+er1 ;0178c3911234
mov.b @(0x1234:16,er3),@er1- ;0178c3a11234
mov.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;0178c3c112349abc
mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;0178c3c912349abcdef0
mov.b @(0x1234:16,er3),@(0xffff9abc:16,r1l.b) ;0178c3d112349abc
mov.b @(0x1234:16,er3),@(0xffff9abc:16,r1.w) ;0178c3e112349abc
mov.b @(0x1234:16,er3),@(0xffff9abc:16,er1.l) ;0178c3f112349abc
mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1l.b) ;0178c3d912349abcdef0
mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1.w) ;0178c3e912349abcdef0
mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1.l) ;0178c3f912349abcdef0
mov.b @(0x1234:16,er3),@0xffff9abc:16 ;0178c34012349abc
mov.b @(0x1234:16,er3),@0x9abcdef0:32 ;0178c34812349abcdef0
mov.b @(0x12345678:32,er3),@er1 ;0178cb0112345678
mov.b @(0x12345678:32,er3),@(0x1:2,er1) ;0178cb1112345678
mov.b @(0x12345678:32,er3),@er1+ ;0178cb8112345678
mov.b @(0x12345678:32,er3),@-er1 ;0178cbb112345678
mov.b @(0x12345678:32,er3),@+er1 ;0178cb9112345678
mov.b @(0x12345678:32,er3),@er1- ;0178cba112345678
mov.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;0178cbc1123456789abc
mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;0178cbc9123456789abcdef0
mov.b @(0x12345678:32,er3),@(0xffff9abc:16,r1l.b) ;0178cbd1123456789abc
mov.b @(0x12345678:32,er3),@(0xffff9abc:16,r1.w) ;0178cbe1123456789abc
mov.b @(0x12345678:32,er3),@(0xffff9abc:16,er1.l) ;0178cbf1123456789abc
mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1l.b) ;0178cbd9123456789abcdef0
mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1.w) ;0178cbe9123456789abcdef0
mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1.l) ;0178cbf9123456789abcdef0
mov.b @(0x12345678:32,er3),@0xffff9abc:16 ;0178cb40123456789abc
mov.b @(0x12345678:32,er3),@0x9abcdef0:32 ;0178cb48123456789abcdef0
mov.b @(0x1234:16,r3l.b),@er1 ;0178d3011234
mov.b @(0x1234:16,r3l.b),@(0x1:2,er1) ;0178d3111234
mov.b @(0x1234:16,r3l.b),@er1+ ;0178d3811234
mov.b @(0x1234:16,r3l.b),@-er1 ;0178d3b11234
mov.b @(0x1234:16,r3l.b),@+er1 ;0178d3911234
mov.b @(0x1234:16,r3l.b),@er1- ;0178d3a11234
mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r1l.b) ;0178d3d112349abc
mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r1.w) ;0178d3e112349abc
mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1.l) ;0178d3f112349abc
mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1l.b) ;0178d3d912349abcdef0
mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1.w) ;0178d3e912349abcdef0
mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1.l) ;0178d3f912349abcdef0
mov.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;0178d34012349abc
mov.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0178d34812349abcdef0
mov.b @(0x1234:16,r3.w),@er1 ;0178e3011234
mov.b @(0x1234:16,r3.w),@(0x1:2,er1) ;0178e3111234
mov.b @(0x1234:16,r3.w),@er1+ ;0178e3811234
mov.b @(0x1234:16,r3.w),@-er1 ;0178e3b11234
mov.b @(0x1234:16,r3.w),@+er1 ;0178e3911234
mov.b @(0x1234:16,r3.w),@er1- ;0178e3a11234
mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0178e3c112349abc
mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0178e3c912349abcdef0
mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0178e3d312349abc
mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0178e3e312349abc
mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0178e3f312349abc
mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0178e3db12349abcdef0
mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0178e3eb12349abcdef0
mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0178e3fb12349abcdef0
mov.b @(0x1234:16,r3.w),@0xffff9abc:16 ;0178e34012349abc
mov.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;0178e34812349abcdef0
mov.b @(0x1234:16,er3.l),@er1 ;0178f3011234
mov.b @(0x1234:16,er3.l),@(0x1:2,er1) ;0178f3111234
mov.b @(0x1234:16,er3.l),@er1+ ;0178f3811234
mov.b @(0x1234:16,er3.l),@-er1 ;0178f3b11234
mov.b @(0x1234:16,er3.l),@+er1 ;0178f3911234
mov.b @(0x1234:16,er3.l),@er1- ;0178f3a11234
mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0178f3c112349abc
mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0178f3c912349abcdef0
mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0178f3d312349abc
mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0178f3e312349abc
mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0178f3f312349abc
mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0178f3db12349abcdef0
mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0178f3eb12349abcdef0
mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0178f3fb12349abcdef0
mov.b @(0x1234:16,er3.l),@0xffff9abc:16 ;0178f34012349abc
mov.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;0178f34812349abcdef0
mov.b @(0x12345678:32,r3l.b),@er1 ;0178db0112345678
mov.b @(0x12345678:32,r3l.b),@(0x1:2,er1) ;0178db1112345678
mov.b @(0x12345678:32,r3l.b),@er1+ ;0178db8112345678
mov.b @(0x12345678:32,r3l.b),@-er1 ;0178dbb112345678
mov.b @(0x12345678:32,r3l.b),@+er1 ;0178db9112345678
mov.b @(0x12345678:32,r3l.b),@er1- ;0178dba112345678
mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0178dbc1123456789abc
mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0178dbc9123456789abcdef0
mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0178dbd3123456789abc
mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0178dbe3123456789abc
mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0178dbf3123456789abc
mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0178dbdb123456789abcdef0
mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0178dbeb123456789abcdef0
mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0178dbfb123456789abcdef0
mov.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0178db40123456789abc
mov.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0178db48123456789abcdef0
mov.b @(0x12345678:32,r3.w),@er1 ;0178eb0112345678
mov.b @(0x12345678:32,r3.w),@(0x1:2,er1) ;0178eb1112345678
mov.b @(0x12345678:32,r3.w),@er1+ ;0178eb8112345678
mov.b @(0x12345678:32,r3.w),@-er1 ;0178ebb112345678
mov.b @(0x12345678:32,r3.w),@+er1 ;0178eb9112345678
mov.b @(0x12345678:32,r3.w),@er1- ;0178eba112345678
mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0178ebc1123456789abc
mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0178ebc9123456789abcdef0
mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0178ebd3123456789abc
mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0178ebe3123456789abc
mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0178ebf3123456789abc
mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0178ebdb123456789abcdef0
mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0178ebeb123456789abcdef0
mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0178ebfb123456789abcdef0
mov.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;0178eb40123456789abc
mov.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0178eb48123456789abcdef0
mov.b @(0x12345678:32,er3.l),@er1 ;0178fb0112345678
mov.b @(0x12345678:32,er3.l),@(0x1:2,er1) ;0178fb1112345678
mov.b @(0x12345678:32,er3.l),@er1+ ;0178fb8112345678
mov.b @(0x12345678:32,er3.l),@-er1 ;0178fbb112345678
mov.b @(0x12345678:32,er3.l),@+er1 ;0178fb9112345678
mov.b @(0x12345678:32,er3.l),@er1- ;0178fba112345678
mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0178fbc1123456789abc
mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0178fbc9123456789abcdef0
mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0178fbd3123456789abc
mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0178fbe3123456789abc
mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0178fbf3123456789abc
mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0178fbdb123456789abcdef0
mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0178fbeb123456789abcdef0
mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0178fbfb123456789abcdef0
mov.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;0178fb40123456789abc
mov.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0178fb48123456789abcdef0
mov.b @0x1234:16,@er1 ;017840011234
mov.b @0x1234:16,@(0x1:2,er1) ;017840111234
mov.b @0x1234:16,@er1+ ;017840811234
mov.b @0x1234:16,@-er1 ;017840b11234
mov.b @0x1234:16,@+er1 ;017840911234
mov.b @0x1234:16,@er1- ;017840a11234
mov.b @0x1234:16,@(0xffff9abc:16,er1) ;017840c112349abc
mov.b @0x1234:16,@(0x9abcdef0:32,er1) ;017840c912349abcdef0
mov.b @0x1234:16,@(0xffff9abc:16,r3l.b) ;017840d312349abc
mov.b @0x1234:16,@(0xffff9abc:16,r3.w) ;017840e312349abc
mov.b @0x1234:16,@(0xffff9abc:16,er3.l) ;017840f312349abc
mov.b @0x1234:16,@(0x9abcdef0:32,r3l.b) ;017840db12349abcdef0
mov.b @0x1234:16,@(0x9abcdef0:32,r3.w) ;017840eb12349abcdef0
mov.b @0x1234:16,@(0x9abcdef0:32,er3.l) ;017840fb12349abcdef0
mov.b @0x1234:16,@0xffff9abc:16 ;0178404012349abc
mov.b @0x1234:16,@0x9abcdef0:32 ;0178404812349abcdef0
mov.b @0x12345678:32,@er1 ;0178480112345678
mov.b @0x12345678:32,@(0x1:2,er1) ;0178481112345678
mov.b @0x12345678:32,@er1+ ;0178488112345678
mov.b @0x12345678:32,@-er1 ;017848b112345678
mov.b @0x12345678:32,@+er1 ;0178489112345678
mov.b @0x12345678:32,@er1- ;017848a112345678
mov.b @0x12345678:32,@(0xffff9abc:16,er1) ;017848c1123456789abc
mov.b @0x12345678:32,@(0x9abcdef0:32,er1) ;017848c9123456789abcdef0
mov.b @0x12345678:32,@(0xffff9abc:16,r3l.b) ;017848d3123456789abc
mov.b @0x12345678:32,@(0xffff9abc:16,r3.w) ;017848e3123456789abc
mov.b @0x12345678:32,@(0xffff9abc:16,er3.l) ;017848f3123456789abc
mov.b @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;017848db123456789abcdef0
mov.b @0x12345678:32,@(0x9abcdef0:32,r3.w) ;017848eb123456789abcdef0
mov.b @0x12345678:32,@(0x9abcdef0:32,er3.l) ;017848fb123456789abcdef0
mov.b @0x12345678:32,@0xffff9abc:16 ;01784840123456789abc
mov.b @0x12345678:32,@0x9abcdef0:32 ;01784848123456789abcdef0
mov.w #0x1234:16,r1 ;79011234
mov.w #0x1:3,r3 ;0f13
mov.w #0x1234:16,@er1 ;797412340100
mov.w #0x1234:16,@(0x2:2,er1) ;797412341100
mov.w #0x1234:16,@er1+ ;797412348100
mov.w #0x1234:16,@-er1 ;79741234b100
mov.w #0x1234:16,@+er1 ;797412349100
mov.w #0x1234:16,@er1- ;79741234a100
mov.w #0x1234:16,@(0x1234:16,er1) ;79741234c1001234
mov.w #0x1234:16,@(0x12345678:32,er1) ;79741234c90012345678
mov.w #0x1234:16,@(0x1234:16,r3l.b) ;79741234d3001234
mov.w #0x1234:16,@(0x1234:16,r3.w) ;79741234e3001234
mov.w #0x1234:16,@(0x1234:16,er3.l) ;79741234f3001234
mov.w #0x1234:16,@(0x12345678:32,r3l.b) ;79741234db0012345678
mov.w #0x1234:16,@(0x12345678:32,r3.w) ;79741234eb0012345678
mov.w #0x1234:16,@(0x12345678:32,er3.l) ;79741234fb0012345678
mov.w #0x1234:16,@0x1234:16 ;7974123440001234
mov.w #0x1234:16,@0x12345678:32 ;79741234480012345678
mov.w #0x12:8,@er1 ;015d0112
mov.w #0x12:8,@(0x2:2,er1) ;015d1112
mov.w #0x12:8,@er1+ ;015d8112
mov.w #0x12:8,@-er1 ;015db112
mov.w #0x12:8,@+er1 ;015d9112
mov.w #0x12:8,@er1- ;015da112
mov.w #0x12:8,@(0x1234:16,er1) ;015dc1121234
mov.w #0x12:8,@(0x12345678:32,er1) ;015dc91212345678
mov.w #0x12:8,@(0x1234:16,r3l.b) ;015dd3121234
mov.w #0x12:8,@(0x1234:16,r3.w) ;015de3121234
mov.w #0x12:8,@(0x1234:16,er3.l) ;015df3121234
mov.w #0x12:8,@(0x12345678:32,r3l.b) ;015ddb1212345678
mov.w #0x12:8,@(0x12345678:32,r3.w) ;015deb1212345678
mov.w #0x12:8,@(0x12345678:32,er3.l) ;015dfb1212345678
mov.w #0x12:8,@0x1234:16 ;015d40121234
mov.w #0x12:8,@0x12345678:32 ;015d481212345678
mov.w #0x1:4,@0x1234:16 ;6bd11234
mov.w #0x1:4,@0x12345678:32 ;6bf112345678
mov.w r2,r1 ;0d21
mov.w r2,@er1 ;6992
mov.w r2,@(0x2:2,er1) ;01516992
mov.w r2,@er1+ ;01536d92
mov.w r2,@-er1 ;6d92
mov.w r2,@+er1 ;01526d92
mov.w r2,@er1- ;01516d92
mov.w r2,@(0x1234:16,er1) ;6f921234
mov.w r2,@(0x12345678:32,er1) ;78106ba212345678
mov.w r2,@(0x1234:16,r3l.b) ;01516fb21234
mov.w r2,@(0x1234:16,r3.w) ;01526fb21234
mov.w r2,@(0x1234:16,er3.l) ;01536fb21234
mov.w r2,@(0x12345678:32,r3l.b) ;78316ba212345678
mov.w r2,@(0x12345678:32,r3.w) ;78326ba212345678
mov.w r2,@(0x12345678:32,er3.l) ;78336ba212345678
mov.w r2,@0x1234:16 ;6b821234
mov.w r2,@0x12345678:32 ;6ba212345678
mov.w @er2,r1 ;6921
mov.w @(0x2:2,er2),r1 ;01516921
mov.w @er2+,r1 ;6d21
mov.w @-er2,r1 ;01536d21
mov.w @+er2,r1 ;01516d21
mov.w @er2-,r1 ;01526d21
mov.w @(0x1234:16,er1),r1 ;6f111234
mov.w @(0x12345678:32,er1),r1 ;78106b2112345678
mov.w @(0x1234:16,r3l.b),r1 ;01516f311234
mov.w @(0x1234:16,r3.w),r1 ;01526f311234
mov.w @(0x1234:16,er3.l),r1 ;01536f311234
mov.w @(0x12345678:32,r3l.b),r1 ;78316b2112345678
mov.w @(0x12345678:32,r3.w),r1 ;78326b2112345678
mov.w @(0x12345678:32,er3.l),r1 ;78336b2112345678
mov.w @0x1234:16,r1 ;6b011234
mov.w @0x12345678:32,r1 ;6b2112345678
mov.w @er2,@er1 ;01580201
mov.w @er2,@(0x2:2,er1) ;01580211
mov.w @er2,@er1+ ;01580281
mov.w @er2,@-er1 ;015802b1
mov.w @er2,@+er1 ;01580291
mov.w @er2,@er1- ;015802a1
mov.w @er2,@(0x1234:16,er1) ;015802c11234
mov.w @er2,@(0x12345678:32,er1) ;015802c912345678
mov.w @er2,@(0x1234:16,r3l.b) ;015802d31234
mov.w @er2,@(0x1234:16,r3.w) ;015802e31234
mov.w @er2,@(0x1234:16,er3.l) ;015802f31234
mov.w @er2,@(0x12345678:32,r3l.b) ;015802db12345678
mov.w @er2,@(0x12345678:32,r3.w) ;015802eb12345678
mov.w @er2,@(0x12345678:32,er3.l) ;015802fb12345678
mov.w @er2,@0x1234:16 ;015802401234
mov.w @er2,@0x12345678:32 ;0158024812345678
mov.w @(0x2:2,er2),@er1 ;01581201
mov.w @(0x2:2,er2),@(0x2:2,er1) ;01581211
mov.w @(0x2:2,er2),@er1+ ;01581281
mov.w @(0x2:2,er2),@-er1 ;015812b1
mov.w @(0x2:2,er2),@+er1 ;01581291
mov.w @(0x2:2,er2),@er1- ;015812a1
mov.w @(0x2:2,er2),@(0x1234:16,er1) ;015812c11234
mov.w @(0x2:2,er2),@(0x12345678:32,er1) ;015812c912345678
mov.w @(0x2:2,er2),@(0x1234:16,r3l.b) ;015812d31234
mov.w @(0x2:2,er2),@(0x1234:16,r3.w) ;015812e31234
mov.w @(0x2:2,er2),@(0x1234:16,er3.l) ;015812f31234
mov.w @(0x2:2,er2),@(0x12345678:32,r3l.b) ;015812db12345678
mov.w @(0x2:2,er2),@(0x12345678:32,r3.w) ;015812eb12345678
mov.w @(0x2:2,er2),@(0x12345678:32,er3.l) ;015812fb12345678
mov.w @(0x2:2,er2),@0x1234:16 ;015812401234
mov.w @(0x2:2,er2),@0x12345678:32 ;0158124812345678
mov.w @-er2,@er1 ;0158b201
mov.w @-er2,@(0x2:2,er1) ;0158b211
mov.w @-er2,@er1+ ;0158b281
mov.w @-er2,@-er1 ;0158b2b1
mov.w @-er2,@+er1 ;0158b291
mov.w @-er2,@er1- ;0158b2a1
mov.w @-er2,@(0x1234:16,er1) ;0158b2c11234
mov.w @-er2,@(0x12345678:32,er1) ;0158b2c912345678
mov.w @-er2,@(0x1234:16,r3l.b) ;0158b2d31234
mov.w @-er2,@(0x1234:16,r3.w) ;0158b2e31234
mov.w @-er2,@(0x1234:16,er3.l) ;0158b2f31234
mov.w @-er2,@(0x12345678:32,r3l.b) ;0158b2db12345678
mov.w @-er2,@(0x12345678:32,r3.w) ;0158b2eb12345678
mov.w @-er2,@(0x12345678:32,er3.l) ;0158b2fb12345678
mov.w @-er2,@0x1234:16 ;0158b2401234
mov.w @-er2,@0x12345678:32 ;0158b24812345678
mov.w @er2+,@er1 ;01588201
mov.w @er2+,@(0x2:2,er1) ;01588211
mov.w @er2+,@er1+ ;01588281
mov.w @er2+,@-er1 ;015882b1
mov.w @er2+,@+er1 ;01588291
mov.w @er2+,@er1- ;015882a1
mov.w @er2+,@(0x1234:16,er1) ;015882c11234
mov.w @er2+,@(0x12345678:32,er1) ;015882c912345678
mov.w @er2+,@(0x1234:16,r3l.b) ;015882d31234
mov.w @er2+,@(0x1234:16,r3.w) ;015882e31234
mov.w @er2+,@(0x1234:16,er3.l) ;015882f31234
mov.w @er2+,@(0x12345678:32,r3l.b) ;015882db12345678
mov.w @er2+,@(0x12345678:32,r3.w) ;015882eb12345678
mov.w @er2+,@(0x12345678:32,er3.l) ;015882fb12345678
mov.w @er2+,@0x1234:16 ;015882401234
mov.w @er2+,@0x12345678:32 ;0158824812345678
mov.w @er2-,@er1 ;0158a201
mov.w @er2-,@(0x2:2,er1) ;0158a211
mov.w @er2-,@er1+ ;0158a281
mov.w @er2-,@-er1 ;0158a2b1
mov.w @er2-,@+er1 ;0158a291
mov.w @er2-,@er1- ;0158a2a1
mov.w @er2-,@(0x1234:16,er1) ;0158a2c11234
mov.w @er2-,@(0x12345678:32,er1) ;0158a2c912345678
mov.w @er2-,@(0x1234:16,r3l.b) ;0158a2d31234
mov.w @er2-,@(0x1234:16,r3.w) ;0158a2e31234
mov.w @er2-,@(0x1234:16,er3.l) ;0158a2f31234
mov.w @er2-,@(0x12345678:32,r3l.b) ;0158a2db12345678
mov.w @er2-,@(0x12345678:32,r3.w) ;0158a2eb12345678
mov.w @er2-,@(0x12345678:32,er3.l) ;0158a2fb12345678
mov.w @er2-,@0x1234:16 ;0158a2401234
mov.w @er2-,@0x12345678:32 ;0158a24812345678
mov.w @+er2,@er1 ;01589201
mov.w @+er2,@(0x2:2,er1) ;01589211
mov.w @+er2,@er1+ ;01589281
mov.w @+er2,@-er1 ;015892b1
mov.w @+er2,@+er1 ;01589291
mov.w @+er2,@er1- ;015892a1
mov.w @+er2,@(0x1234:16,er1) ;015892c11234
mov.w @+er2,@(0x12345678:32,er1) ;015892c912345678
mov.w @+er2,@(0x1234:16,r3l.b) ;015892d31234
mov.w @+er2,@(0x1234:16,r3.w) ;015892e31234
mov.w @+er2,@(0x1234:16,er3.l) ;015892f31234
mov.w @+er2,@(0x12345678:32,r3l.b) ;015892db12345678
mov.w @+er2,@(0x12345678:32,r3.w) ;015892eb12345678
mov.w @+er2,@(0x12345678:32,er3.l) ;015892fb12345678
mov.w @+er2,@0x1234:16 ;015892401234
mov.w @+er2,@0x12345678:32 ;0158924812345678
mov.w @(0x1234:16,er2),@er1 ;0158c2011234
mov.w @(0x1234:16,er2),@(0x2:2,er1) ;0158c2111234
mov.w @(0x1234:16,er2),@er1+ ;0158c2811234
mov.w @(0x1234:16,er2),@-er1 ;0158c2b11234
mov.w @(0x1234:16,er2),@+er1 ;0158c2911234
mov.w @(0x1234:16,er2),@er1- ;0158c2a11234
mov.w @(0x1234:16,er2),@(0xffff9abc:16,er1) ;0158c2c112349abc
mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er1) ;0158c2c912349abcdef0
mov.w @(0x1234:16,er2),@(0xffff9abc:16,r3l.b) ;0158c2d312349abc
mov.w @(0x1234:16,er2),@(0xffff9abc:16,r3.w) ;0158c2e312349abc
mov.w @(0x1234:16,er2),@(0xffff9abc:16,er3.l) ;0158c2f312349abc
mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b) ;0158c2db12349abcdef0
mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3.w) ;0158c2eb12349abcdef0
mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er3.l) ;0158c2fb12349abcdef0
mov.w @(0x1234:16,er2),@0xffff9abc:16 ;0158c24012349abc
mov.w @(0x1234:16,er2),@0x9abcdef0:32 ;0158c24812349abcdef0
mov.w @(0x12345678:32,er2),@er1 ;0158ca0112345678
mov.w @(0x12345678:32,er2),@(0x2:2,er1) ;0158ca1112345678
mov.w @(0x12345678:32,er2),@er1+ ;0158ca8112345678
mov.w @(0x12345678:32,er2),@-er1 ;0158cab112345678
mov.w @(0x12345678:32,er2),@+er1 ;0158ca9112345678
mov.w @(0x12345678:32,er2),@er1- ;0158caa112345678
mov.w @(0x12345678:32,er2),@(0xffff9abc:16,er1) ;0158cac1123456789abc
mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er1) ;0158cac9123456789abcdef0
mov.w @(0x12345678:32,er2),@(0xffff9abc:16,r3l.b) ;0158cad3123456789abc
mov.w @(0x12345678:32,er2),@(0xffff9abc:16,r3.w) ;0158cae3123456789abc
mov.w @(0x12345678:32,er2),@(0xffff9abc:16,er3.l) ;0158caf3123456789abc
mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b) ;0158cadb123456789abcdef0
mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w) ;0158caeb123456789abcdef0
mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l) ;0158cafb123456789abcdef0
mov.w @(0x12345678:32,er2),@0xffff9abc:16 ;0158ca40123456789abc
mov.w @(0x12345678:32,er2),@0x9abcdef0:32 ;0158ca48123456789abcdef0
mov.w @(0x1234:16,r3l.b),@er1 ;0158d3011234
mov.w @(0x1234:16,r3l.b),@(0x2:2,er1) ;0158d3111234
mov.w @(0x1234:16,r3l.b),@er1+ ;0158d3811234
mov.w @(0x1234:16,r3l.b),@-er1 ;0158d3b11234
mov.w @(0x1234:16,r3l.b),@+er1 ;0158d3911234
mov.w @(0x1234:16,r3l.b),@er1- ;0158d3a11234
mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;0158d3c112349abc
mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;0158d3c912349abcdef0
mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r3l.b) ;0158d3d312349abc
mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r3.w) ;0158d3e312349abc
mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er3.l) ;0158d3f312349abc
mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b) ;0158d3db12349abcdef0
mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w) ;0158d3eb12349abcdef0
mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l) ;0158d3fb12349abcdef0
mov.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;0158d34012349abc
mov.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0158d34812349abcdef0
mov.w @(0x1234:16,r3.w),@er1 ;0158e3011234
mov.w @(0x1234:16,r3.w),@(0x2:2,er1) ;0158e3111234
mov.w @(0x1234:16,r3.w),@er1+ ;0158e3811234
mov.w @(0x1234:16,r3.w),@-er1 ;0158e3b11234
mov.w @(0x1234:16,r3.w),@+er1 ;0158e3911234
mov.w @(0x1234:16,r3.w),@er1- ;0158e3a11234
mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0158e3c112349abc
mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0158e3c912349abcdef0
mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0158e3d312349abc
mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0158e3e312349abc
mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0158e3f312349abc
mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0158e3db12349abcdef0
mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0158e3eb12349abcdef0
mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0158e3fb12349abcdef0
mov.w @(0x1234:16,r3.w),@0xffff9abc:16 ;0158e34012349abc
mov.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;0158e34812349abcdef0
mov.w @(0x1234:16,er3.l),@er1 ;0158f3011234
mov.w @(0x1234:16,er3.l),@(0x2:2,er1) ;0158f3111234
mov.w @(0x1234:16,er3.l),@er1+ ;0158f3811234
mov.w @(0x1234:16,er3.l),@-er1 ;0158f3b11234
mov.w @(0x1234:16,er3.l),@+er1 ;0158f3911234
mov.w @(0x1234:16,er3.l),@er1- ;0158f3a11234
mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0158f3c112349abc
mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0158f3c912349abcdef0
mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0158f3d312349abc
mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0158f3e312349abc
mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0158f3f312349abc
mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0158f3db12349abcdef0
mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0158f3eb12349abcdef0
mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0158f3fb12349abcdef0
mov.w @(0x1234:16,er3.l),@0xffff9abc:16 ;0158f34012349abc
mov.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;0158f34812349abcdef0
mov.w @(0x12345678:32,r3l.b),@er1 ;0158db0112345678
mov.w @(0x12345678:32,r3l.b),@(0x2:2,er1) ;0158db1112345678
mov.w @(0x12345678:32,r3l.b),@er1+ ;0158db8112345678
mov.w @(0x12345678:32,r3l.b),@-er1 ;0158dbb112345678
mov.w @(0x12345678:32,r3l.b),@+er1 ;0158db9112345678
mov.w @(0x12345678:32,r3l.b),@er1- ;0158dba112345678
mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0158dbc1123456789abc
mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0158dbc9123456789abcdef0
mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0158dbd3123456789abc
mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0158dbe3123456789abc
mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0158dbf3123456789abc
mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0158dbdb123456789abcdef0
mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0158dbeb123456789abcdef0
mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0158dbfb123456789abcdef0
mov.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0158db40123456789abc
mov.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0158db48123456789abcdef0
mov.w @(0x12345678:32,r3.w),@er1 ;0158eb0112345678
mov.w @(0x12345678:32,r3.w),@(0x2:2,er1) ;0158eb1112345678
mov.w @(0x12345678:32,r3.w),@er1+ ;0158eb8112345678
mov.w @(0x12345678:32,r3.w),@-er1 ;0158ebb112345678
mov.w @(0x12345678:32,r3.w),@+er1 ;0158eb9112345678
mov.w @(0x12345678:32,r3.w),@er1- ;0158eba112345678
mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0158ebc1123456789abc
mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0158ebc9123456789abcdef0
mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0158ebd3123456789abc
mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0158ebe3123456789abc
mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0158ebf3123456789abc
mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0158ebdb123456789abcdef0
mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0158ebeb123456789abcdef0
mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0158ebfb123456789abcdef0
mov.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;0158eb40123456789abc
mov.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0158eb48123456789abcdef0
mov.w @(0x12345678:32,er3.l),@er1 ;0158fb0112345678
mov.w @(0x12345678:32,er3.l),@(0x2:2,er1) ;0158fb1112345678
mov.w @(0x12345678:32,er3.l),@er1+ ;0158fb8112345678
mov.w @(0x12345678:32,er3.l),@-er1 ;0158fbb112345678
mov.w @(0x12345678:32,er3.l),@+er1 ;0158fb9112345678
mov.w @(0x12345678:32,er3.l),@er1- ;0158fba112345678
mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0158fbc1123456789abc
mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0158fbc9123456789abcdef0
mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0158fbd3123456789abc
mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0158fbe3123456789abc
mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0158fbf3123456789abc
mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0158fbdb123456789abcdef0
mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0158fbeb123456789abcdef0
mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0158fbfb123456789abcdef0
mov.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;0158fb40123456789abc
mov.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0158fb48123456789abcdef0
mov.w @0x1234:16,@er1 ;015840011234
mov.w @0x1234:16,@(0x2:2,er1) ;015840111234
mov.w @0x1234:16,@er1+ ;015840811234
mov.w @0x1234:16,@-er1 ;015840b11234
mov.w @0x1234:16,@+er1 ;015840911234
mov.w @0x1234:16,@er1- ;015840a11234
mov.w @0x1234:16,@(0xffff9abc:16,er1) ;015840c112349abc
mov.w @0x1234:16,@(0x9abcdef0:32,er1) ;015840c912349abcdef0
mov.w @0x1234:16,@(0xffff9abc:16,r3l.b) ;015840d312349abc
mov.w @0x1234:16,@(0xffff9abc:16,r3.w) ;015840e312349abc
mov.w @0x1234:16,@(0xffff9abc:16,er3.l) ;015840f312349abc
mov.w @0x1234:16,@(0x9abcdef0:32,r3l.b) ;015840db12349abcdef0
mov.w @0x1234:16,@(0x9abcdef0:32,r3.w) ;015840eb12349abcdef0
mov.w @0x1234:16,@(0x9abcdef0:32,er3.l) ;015840fb12349abcdef0
mov.w @0x1234:16,@0xffff9abc:16 ;0158404012349abc
mov.w @0x1234:16,@0x9abcdef0:32 ;0158404812349abcdef0
mov.w @0x12345678:32,@er1 ;0158480112345678
mov.w @0x12345678:32,@(0x2:2,er1) ;0158481112345678
mov.w @0x12345678:32,@er1+ ;0158488112345678
mov.w @0x12345678:32,@-er1 ;015848b112345678
mov.w @0x12345678:32,@+er1 ;0158489112345678
mov.w @0x12345678:32,@er1- ;015848a112345678
mov.w @0x12345678:32,@(0xffff9abc:16,er1) ;015848c1123456789abc
mov.w @0x12345678:32,@(0x9abcdef0:32,er1) ;015848c9123456789abcdef0
mov.w @0x12345678:32,@(0xffff9abc:16,r3l.b) ;015848d3123456789abc
mov.w @0x12345678:32,@(0xffff9abc:16,r3.w) ;015848e3123456789abc
mov.w @0x12345678:32,@(0xffff9abc:16,er3.l) ;015848f3123456789abc
mov.w @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;015848db123456789abcdef0
mov.w @0x12345678:32,@(0x9abcdef0:32,r3.w) ;015848eb123456789abcdef0
mov.w @0x12345678:32,@(0x9abcdef0:32,er3.l) ;015848fb123456789abcdef0
mov.w @0x12345678:32,@0xffff9abc:16 ;01584840123456789abc
mov.w @0x12345678:32,@0x9abcdef0:32 ;01584848123456789abcdef0
mov.l #0x12345678:32,er1 ;7a0112345678
mov.l #0x1234:16,er1 ;7a091234
mov.l #0x1:3,er3 ;0f9b
mov.l #0x12345678:32,@er1 ;7a74123456780100
mov.l #0x12345678:32,@(0x4:2,er1) ;7a74123456781100
mov.l #0x12345678:32,@-er1 ;7a7412345678b100
mov.l #0x12345678:32,@er1+ ;7a74123456788100
mov.l #0x12345678:32,@er1- ;7a7412345678a100
mov.l #0x12345678:32,@+er1 ;7a74123456789100
mov.l #0x12345678:32,@(0x1234:16,er1) ;7a7412345678c1001234
mov.l #0x12345678:32,@(0x12345678:32,er1) ;7a7412345678c90012345678
mov.l #0x12345678:32,@(0x1234:16,r3l.b) ;7a7412345678d3001234
mov.l #0x12345678:32,@(0x1234:16,r3.w) ;7a7412345678e3001234
mov.l #0x12345678:32,@(0x1234:16,er3.l) ;7a7412345678f3001234
mov.l #0x12345678:32,@(0x12345678:32,r3l.b) ;7a7412345678db0012345678
mov.l #0x12345678:32,@(0x12345678:32,r3.w) ;7a7412345678eb0012345678
mov.l #0x12345678:32,@(0x12345678:32,er3.l) ;7a7412345678fb0012345678
mov.l #0x12345678:32,@0x1234:16 ;7a741234567840001234
mov.l #0x12345678:32,@0x12345678:32 ;7a7412345678480012345678
mov.l #0x1234:16,@er1 ;7a7c12340100
mov.l #0x1234:16,@(0x4:2,er1) ;7a7c12341100
mov.l #0x1234:16,@-er1 ;7a7c1234b100
mov.l #0x1234:16,@er1+ ;7a7c12348100
mov.l #0x1234:16,@er1- ;7a7c1234a100
mov.l #0x1234:16,@+er1 ;7a7c12349100
mov.l #0x1234:16,@(0x1234:16,er1) ;7a7c1234c1001234
mov.l #0x1234:16,@(0x12345678:32,er1) ;7a7c1234c90012345678
mov.l #0x1234:16,@(0x1234:16,r3l.b) ;7a7c1234d3001234
mov.l #0x1234:16,@(0x1234:16,r3.w) ;7a7c1234e3001234
mov.l #0x1234:16,@(0x1234:16,er3.l) ;7a7c1234f3001234
mov.l #0x1234:16,@(0x12345678:32,r3l.b) ;7a7c1234db0012345678
mov.l #0x1234:16,@(0x12345678:32,r3.w) ;7a7c1234eb0012345678
mov.l #0x1234:16,@(0x12345678:32,er3.l) ;7a7c1234fb0012345678
mov.l #0x1234:16,@0x1234:16 ;7a7c123440001234
mov.l #0x1234:16,@0x12345678:32 ;7a7c1234480012345678
mov.l #0x12:8,@er1 ;010d0112
mov.l #0x12:8,@(0x4:2,er1) ;010d1112
mov.l #0x12:8,@-er1 ;010db112
mov.l #0x12:8,@er1+ ;010d8112
mov.l #0x12:8,@er1- ;010da112
mov.l #0x12:8,@+er1 ;010d9112
mov.l #0x12:8,@(0x1234:16,er1) ;010dc1121234
mov.l #0x12:8,@(0x12345678:32,er1) ;010dc91212345678
mov.l #0x12:8,@(0x1234:16,r3l.b) ;010dd3121234
mov.l #0x12:8,@(0x1234:16,r3.w) ;010de3121234
mov.l #0x12:8,@(0x1234:16,er3.l) ;010df3121234
mov.l #0x12:8,@(0x12345678:32,r3l.b) ;010ddb1212345678
mov.l #0x12:8,@(0x12345678:32,r3.w) ;010deb1212345678
mov.l #0x12:8,@(0x12345678:32,er3.l) ;010dfb1212345678
mov.l #0x12:8,@0x1234:16 ;010d40121234
mov.l #0x12:8,@0x12345678:32 ;010d481212345678
mov.l er2,er1 ;0fa1
mov.l er2,@er1 ;01006992
mov.l er2,@(0x4:2,er1) ;01016992
mov.l er2,@-er1 ;01006d92
mov.l er2,@er1+ ;01036d92
mov.l er2,@er1- ;01016d92
mov.l er2,@+er1 ;01026d92
mov.l er2,@(0x1234:16,er1) ;01006f921234
mov.l er2,@(0x12345678:32,er1) ;78906ba212345678
mov.l er2,@(0x1234:16,r3l.b) ;01016fb21234
mov.l er2,@(0x1234:16,r3.w) ;01026fb21234
mov.l er2,@(0x1234:16,er3.l) ;01036fb21234
mov.l er2,@(0x12345678:32,r3l.b) ;78b16ba212345678
mov.l er2,@(0x12345678:32,r3.w) ;78b26ba212345678
mov.l er2,@(0x12345678:32,er3.l) ;78b36ba212345678
mov.l er2,@0x1234:16 ;01006b821234
mov.l er2,@0x12345678:32 ;01006ba212345678
mov.l @er2,er1 ;01006921
mov.l @(0x4:2,er2),er1 ;01016921
mov.l @er2+,er1 ;01006d21
mov.l @-er2,er1 ;01036d21
mov.l @+er2,er1 ;01016d21
mov.l @er2-,er1 ;01026d21
mov.l @(0x1234:16,er1),er1 ;01006f111234
mov.l @(0x12345678:32,er1),er1 ;78906b2112345678
mov.l @(0x1234:16,r3l.b),er1 ;01016f311234
mov.l @(0x1234:16,r3.w),er1 ;01026f311234
mov.l @(0x1234:16,er3.l),er1 ;01036f311234
mov.l @(0x12345678:32,r3l.b),er1 ;78b16b2112345678
mov.l @(0x12345678:32,r3.w),er1 ;78b26b2112345678
mov.l @(0x12345678:32,er3.l),er1 ;78b36b2112345678
mov.l @0x1234:16,er1 ;01006b011234
mov.l @0x12345678:32,er1 ;01006b2112345678
mov.l @er2,@er1 ;01080201
mov.l @er2,@(0x4:2,er1) ;01080211
mov.l @er2,@er1+ ;01080281
mov.l @er2,@-er1 ;010802b1
mov.l @er2,@+er1 ;01080291
mov.l @er2,@er1- ;010802a1
mov.l @er2,@(0x1234:16,er1) ;010802c11234
mov.l @er2,@(0x12345678:32,er1) ;010802c912345678
mov.l @er2,@(0x1234:16,r3l.b) ;010802d31234
mov.l @er2,@(0x1234:16,r3.w) ;010802e31234
mov.l @er2,@(0x1234:16,er3.l) ;010802f31234
mov.l @er2,@(0x12345678:32,r3l.b) ;010802db12345678
mov.l @er2,@(0x12345678:32,r3.w) ;010802eb12345678
mov.l @er2,@(0x12345678:32,er3.l) ;010802fb12345678
mov.l @er2,@0x1234:16 ;010802401234
mov.l @er2,@0x12345678:32 ;0108024812345678
mov.l @(0x4:2,er2),@er1 ;01081201
mov.l @(0x4:2,er2),@(0x4:2,er1) ;01081211
mov.l @(0x4:2,er2),@er1+ ;01081281
mov.l @(0x4:2,er2),@-er1 ;010812b1
mov.l @(0x4:2,er2),@+er1 ;01081291
mov.l @(0x4:2,er2),@er1- ;010812a1
mov.l @(0x4:2,er2),@(0x1234:16,er1) ;010812c11234
mov.l @(0x4:2,er2),@(0x12345678:32,er1) ;010812c912345678
mov.l @(0x4:2,er2),@(0x1234:16,r3l.b) ;010812d31234
mov.l @(0x4:2,er2),@(0x1234:16,r3.w) ;010812e31234
mov.l @(0x4:2,er2),@(0x1234:16,er3.l) ;010812f31234
mov.l @(0x4:2,er2),@(0x12345678:32,r3l.b) ;010812db12345678
mov.l @(0x4:2,er2),@(0x12345678:32,r3.w) ;010812eb12345678
mov.l @(0x4:2,er2),@(0x12345678:32,er3.l) ;010812fb12345678
mov.l @(0x4:2,er2),@0x1234:16 ;010812401234
mov.l @(0x4:2,er2),@0x12345678:32 ;0108124812345678
mov.l @-er2,@er1 ;0108b201
mov.l @-er2,@(0x4:2,er1) ;0108b211
mov.l @-er2,@er1+ ;0108b281
mov.l @-er2,@-er1 ;0108b2b1
mov.l @-er2,@+er1 ;0108b291
mov.l @-er2,@er1- ;0108b2a1
mov.l @-er2,@(0x1234:16,er1) ;0108b2c11234
mov.l @-er2,@(0x12345678:32,er1) ;0108b2c912345678
mov.l @-er2,@(0x1234:16,r3l.b) ;0108b2d31234
mov.l @-er2,@(0x1234:16,r3.w) ;0108b2e31234
mov.l @-er2,@(0x1234:16,er3.l) ;0108b2f31234
mov.l @-er2,@(0x12345678:32,r3l.b) ;0108b2db12345678
mov.l @-er2,@(0x12345678:32,r3.w) ;0108b2eb12345678
mov.l @-er2,@(0x12345678:32,er3.l) ;0108b2fb12345678
mov.l @-er2,@0x1234:16 ;0108b2401234
mov.l @-er2,@0x12345678:32 ;0108b24812345678
mov.l @er2+,@er1 ;01088201
mov.l @er2+,@(0x4:2,er1) ;01088211
mov.l @er2+,@er1+ ;01088281
mov.l @er2+,@-er1 ;010882b1
mov.l @er2+,@+er1 ;01088291
mov.l @er2+,@er1- ;010882a1
mov.l @er2+,@(0x1234:16,er1) ;010882c11234
mov.l @er2+,@(0x12345678:32,er1) ;010882c912345678
mov.l @er2+,@(0x1234:16,r3l.b) ;010882d31234
mov.l @er2+,@(0x1234:16,r3.w) ;010882e31234
mov.l @er2+,@(0x1234:16,er3.l) ;010882f31234
mov.l @er2+,@(0x12345678:32,r3l.b) ;010882db12345678
mov.l @er2+,@(0x12345678:32,r3.w) ;010882eb12345678
mov.l @er2+,@(0x12345678:32,er3.l) ;010882fb12345678
mov.l @er2+,@0x1234:16 ;010882401234
mov.l @er2+,@0x12345678:32 ;0108824812345678
mov.l @er2-,@er1 ;0108a201
mov.l @er2-,@(0x4:2,er1) ;0108a211
mov.l @er2-,@er1+ ;0108a281
mov.l @er2-,@-er1 ;0108a2b1
mov.l @er2-,@+er1 ;0108a291
mov.l @er2-,@er1- ;0108a2a1
mov.l @er2-,@(0x1234:16,er1) ;0108a2c11234
mov.l @er2-,@(0x12345678:32,er1) ;0108a2c912345678
mov.l @er2-,@(0x1234:16,r3l.b) ;0108a2d31234
mov.l @er2-,@(0x1234:16,r3.w) ;0108a2e31234
mov.l @er2-,@(0x1234:16,er3.l) ;0108a2f31234
mov.l @er2-,@(0x12345678:32,r3l.b) ;0108a2db12345678
mov.l @er2-,@(0x12345678:32,r3.w) ;0108a2eb12345678
mov.l @er2-,@(0x12345678:32,er3.l) ;0108a2fb12345678
mov.l @er2-,@0x1234:16 ;0108a2401234
mov.l @er2-,@0x12345678:32 ;0108a24812345678
mov.l @+er2,@er1 ;01089201
mov.l @+er2,@(0x4:2,er1) ;01089211
mov.l @+er2,@er1+ ;01089281
mov.l @+er2,@-er1 ;010892b1
mov.l @+er2,@+er1 ;01089291
mov.l @+er2,@er1- ;010892a1
mov.l @+er2,@(0x1234:16,er1) ;010892c11234
mov.l @+er2,@(0x12345678:32,er1) ;010892c912345678
mov.l @+er2,@(0x1234:16,r3l.b) ;010892d31234
mov.l @+er2,@(0x1234:16,r3.w) ;010892e31234
mov.l @+er2,@(0x1234:16,er3.l) ;010892f31234
mov.l @+er2,@(0x12345678:32,r3l.b) ;010892db12345678
mov.l @+er2,@(0x12345678:32,r3.w) ;010892eb12345678
mov.l @+er2,@(0x12345678:32,er3.l) ;010892fb12345678
mov.l @+er2,@0x1234:16 ;010892401234
mov.l @+er2,@0x12345678:32 ;0108924812345678
mov.l @(0x1234:16,er2),@er1 ;0108c2011234
mov.l @(0x1234:16,er2),@(0x4:2,er1) ;0108c2111234
mov.l @(0x1234:16,er2),@er1+ ;0108c2811234
mov.l @(0x1234:16,er2),@-er1 ;0108c2b11234
mov.l @(0x1234:16,er2),@+er1 ;0108c2911234
mov.l @(0x1234:16,er2),@er1- ;0108c2a11234
mov.l @(0x1234:16,er2),@(0xffff9abc:16,er1) ;0108c2c112349abc
mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er1) ;0108c2c912349abcdef0
mov.l @(0x1234:16,er2),@(0xffff9abc:16,r3l.b) ;0108c2d312349abc
mov.l @(0x1234:16,er2),@(0xffff9abc:16,r3.w) ;0108c2e312349abc
mov.l @(0x1234:16,er2),@(0xffff9abc:16,er3.l) ;0108c2f312349abc
mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b) ;0108c2db12349abcdef0
mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3.w) ;0108c2eb12349abcdef0
mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er3.l) ;0108c2fb12349abcdef0
mov.l @(0x1234:16,er2),@0xffff9abc:16 ;0108c24012349abc
mov.l @(0x1234:16,er2),@0x9abcdef0:32 ;0108c24812349abcdef0
mov.l @(0x12345678:32,er2),@er1 ;0108ca0112345678
mov.l @(0x12345678:32,er2),@(0x4:2,er1) ;0108ca1112345678
mov.l @(0x12345678:32,er2),@er1+ ;0108ca8112345678
mov.l @(0x12345678:32,er2),@-er1 ;0108cab112345678
mov.l @(0x12345678:32,er2),@+er1 ;0108ca9112345678
mov.l @(0x12345678:32,er2),@er1- ;0108caa112345678
mov.l @(0x12345678:32,er2),@(0xffff9abc:16,er1) ;0108cac1123456789abc
mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er1) ;0108cac9123456789abcdef0
mov.l @(0x12345678:32,er2),@(0xffff9abc:16,r3l.b) ;0108cad3123456789abc
mov.l @(0x12345678:32,er2),@(0xffff9abc:16,r3.w) ;0108cae3123456789abc
mov.l @(0x12345678:32,er2),@(0xffff9abc:16,er3.l) ;0108caf3123456789abc
mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b) ;0108cadb123456789abcdef0
mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w) ;0108caeb123456789abcdef0
mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l) ;0108cafb123456789abcdef0
mov.l @(0x12345678:32,er2),@0xffff9abc:16 ;0108ca40123456789abc
mov.l @(0x12345678:32,er2),@0x9abcdef0:32 ;0108ca48123456789abcdef0
mov.l @(0x1234:16,r3l.b),@er1 ;0108d3011234
mov.l @(0x1234:16,r3l.b),@(0x4:2,er1) ;0108d3111234
mov.l @(0x1234:16,r3l.b),@er1+ ;0108d3811234
mov.l @(0x1234:16,r3l.b),@-er1 ;0108d3b11234
mov.l @(0x1234:16,r3l.b),@+er1 ;0108d3911234
mov.l @(0x1234:16,r3l.b),@er1- ;0108d3a11234
mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;0108d3c112349abc
mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;0108d3c912349abcdef0
mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r3l.b) ;0108d3d312349abc
mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r3.w) ;0108d3e312349abc
mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er3.l) ;0108d3f312349abc
mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b) ;0108d3db12349abcdef0
mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w) ;0108d3eb12349abcdef0
mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l) ;0108d3fb12349abcdef0
mov.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;0108d34012349abc
mov.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0108d34812349abcdef0
mov.l @(0x1234:16,r3.w),@er1 ;0108e3011234
mov.l @(0x1234:16,r3.w),@(0x4:2,er1) ;0108e3111234
mov.l @(0x1234:16,r3.w),@er1+ ;0108e3811234
mov.l @(0x1234:16,r3.w),@-er1 ;0108e3b11234
mov.l @(0x1234:16,r3.w),@+er1 ;0108e3911234
mov.l @(0x1234:16,r3.w),@er1- ;0108e3a11234
mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0108e3c112349abc
mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0108e3c912349abcdef0
mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0108e3d312349abc
mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0108e3e312349abc
mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0108e3f312349abc
mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0108e3db12349abcdef0
mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0108e3eb12349abcdef0
mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0108e3fb12349abcdef0
mov.l @(0x1234:16,r3.w),@0xffff9abc:16 ;0108e34012349abc
mov.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;0108e34812349abcdef0
mov.l @(0x1234:16,er3.l),@er1 ;0108f3011234
mov.l @(0x1234:16,er3.l),@(0x4:2,er1) ;0108f3111234
mov.l @(0x1234:16,er3.l),@er1+ ;0108f3811234
mov.l @(0x1234:16,er3.l),@-er1 ;0108f3b11234
mov.l @(0x1234:16,er3.l),@+er1 ;0108f3911234
mov.l @(0x1234:16,er3.l),@er1- ;0108f3a11234
mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0108f3c112349abc
mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0108f3c912349abcdef0
mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0108f3d312349abc
mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0108f3e312349abc
mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0108f3f312349abc
mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0108f3db12349abcdef0
mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0108f3eb12349abcdef0
mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0108f3fb12349abcdef0
mov.l @(0x1234:16,er3.l),@0xffff9abc:16 ;0108f34012349abc
mov.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;0108f34812349abcdef0
mov.l @(0x12345678:32,r3l.b),@er1 ;0108db0112345678
mov.l @(0x12345678:32,r3l.b),@(0x4:2,er1) ;0108db1112345678
mov.l @(0x12345678:32,r3l.b),@er1+ ;0108db8112345678
mov.l @(0x12345678:32,r3l.b),@-er1 ;0108dbb112345678
mov.l @(0x12345678:32,r3l.b),@+er1 ;0108db9112345678
mov.l @(0x12345678:32,r3l.b),@er1- ;0108dba112345678
mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0108dbc1123456789abc
mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0108dbc9123456789abcdef0
mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0108dbd3123456789abc
mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0108dbe3123456789abc
mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0108dbf3123456789abc
mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0108dbdb123456789abcdef0
mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0108dbeb123456789abcdef0
mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0108dbfb123456789abcdef0
mov.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0108db40123456789abc
mov.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0108db48123456789abcdef0
mov.l @(0x12345678:32,r3.w),@er1 ;0108eb0112345678
mov.l @(0x12345678:32,r3.w),@(0x4:2,er1) ;0108eb1112345678
mov.l @(0x12345678:32,r3.w),@er1+ ;0108eb8112345678
mov.l @(0x12345678:32,r3.w),@-er1 ;0108ebb112345678
mov.l @(0x12345678:32,r3.w),@+er1 ;0108eb9112345678
mov.l @(0x12345678:32,r3.w),@er1- ;0108eba112345678
mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0108ebc1123456789abc
mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0108ebc9123456789abcdef0
mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0108ebd3123456789abc
mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0108ebe3123456789abc
mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0108ebf3123456789abc
mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0108ebdb123456789abcdef0
mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0108ebeb123456789abcdef0
mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0108ebfb123456789abcdef0
mov.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;0108eb40123456789abc
mov.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0108eb48123456789abcdef0
mov.l @(0x12345678:32,er3.l),@er1 ;0108fb0112345678
mov.l @(0x12345678:32,er3.l),@(0x4:2,er1) ;0108fb1112345678
mov.l @(0x12345678:32,er3.l),@er1+ ;0108fb8112345678
mov.l @(0x12345678:32,er3.l),@-er1 ;0108fbb112345678
mov.l @(0x12345678:32,er3.l),@+er1 ;0108fb9112345678
mov.l @(0x12345678:32,er3.l),@er1- ;0108fba112345678
mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0108fbc1123456789abc
mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0108fbc9123456789abcdef0
mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0108fbd3123456789abc
mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0108fbe3123456789abc
mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0108fbf3123456789abc
mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0108fbdb123456789abcdef0
mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0108fbeb123456789abcdef0
mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0108fbfb123456789abcdef0
mov.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;0108fb40123456789abc
mov.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0108fb48123456789abcdef0
mov.l @0x1234:16,@er1 ;010840011234
mov.l @0x1234:16,@(0x4:2,er1) ;010840111234
mov.l @0x1234:16,@er1+ ;010840811234
mov.l @0x1234:16,@-er1 ;010840b11234
mov.l @0x1234:16,@+er1 ;010840911234
mov.l @0x1234:16,@er1- ;010840a11234
mov.l @0x1234:16,@(0xffff9abc:16,er1) ;010840c112349abc
mov.l @0x1234:16,@(0x9abcdef0:32,er1) ;010840c912349abcdef0
mov.l @0x1234:16,@(0xffff9abc:16,r3l.b) ;010840d312349abc
mov.l @0x1234:16,@(0xffff9abc:16,r3.w) ;010840e312349abc
mov.l @0x1234:16,@(0xffff9abc:16,er3.l) ;010840f312349abc
mov.l @0x1234:16,@(0x9abcdef0:32,r3l.b) ;010840db12349abcdef0
mov.l @0x1234:16,@(0x9abcdef0:32,r3.w) ;010840eb12349abcdef0
mov.l @0x1234:16,@(0x9abcdef0:32,er3.l) ;010840fb12349abcdef0
mov.l @0x1234:16,@0xffff9abc:16 ;0108404012349abc
mov.l @0x1234:16,@0x9abcdef0:32 ;0108404812349abcdef0
mov.l @0x12345678:32,@er1 ;0108480112345678
mov.l @0x12345678:32,@(0x4:2,er1) ;0108481112345678
mov.l @0x12345678:32,@er1+ ;0108488112345678
mov.l @0x12345678:32,@-er1 ;010848b112345678
mov.l @0x12345678:32,@+er1 ;0108489112345678
mov.l @0x12345678:32,@er1- ;010848a112345678
mov.l @0x12345678:32,@(0xffff9abc:16,er1) ;010848c1123456789abc
mov.l @0x12345678:32,@(0x9abcdef0:32,er1) ;010848c9123456789abcdef0
mov.l @0x12345678:32,@(0xffff9abc:16,r3l.b) ;010848d3123456789abc
mov.l @0x12345678:32,@(0xffff9abc:16,r3.w) ;010848e3123456789abc
mov.l @0x12345678:32,@(0xffff9abc:16,er3.l) ;010848f3123456789abc
mov.l @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;010848db123456789abcdef0
mov.l @0x12345678:32,@(0x9abcdef0:32,r3.w) ;010848eb123456789abcdef0
mov.l @0x12345678:32,@(0x9abcdef0:32,er3.l) ;010848fb123456789abcdef0
mov.l @0x12345678:32,@0xffff9abc:16 ;01084840123456789abc
mov.l @0x12345678:32,@0x9abcdef0:32 ;01084848123456789abcdef0
movtpe.b r2h,@0x1234:16 ;6ac21234
movfpe.b @0x1234:16,r1h ;6a411234
ldm @sp+,(er0-er1) ;01106d71
ldm @sp+,(er1-er2) ;01106d72
ldm @sp+,(er2-er3) ;01106d73
ldm @sp+,(er3-er4) ;01106d74
ldm @sp+,(er4-er5) ;01106d75
ldm @sp+,(er5-er6) ;01106d76
ldm @sp+,(er6-er7) ;01106d77
ldm @sp+,(er0-er2) ;01206d72
ldm @sp+,(er1-er3) ;01206d73
ldm @sp+,(er2-er4) ;01206d74
ldm @sp+,(er3-er5) ;01206d75
ldm @sp+,(er4-er6) ;01206d76
ldm @sp+,(er5-er7) ;01206d77
ldm @sp+,(er0-er3) ;01306d73
ldm @sp+,(er1-er4) ;01306d74
ldm @sp+,(er2-er5) ;01306d75
ldm @sp+,(er3-er6) ;01306d76
ldm @sp+,(er4-er7) ;01306d77
stm (er0-er1),@-sp ;01106df0
stm (er1-er2),@-sp ;01106df1
stm (er2-er3),@-sp ;01106df2
stm (er3-er4),@-sp ;01106df3
stm (er4-er5),@-sp ;01106df4
stm (er5-er6),@-sp ;01106df5
stm (er6-er7),@-sp ;01106df6
stm (er0-er2),@-sp ;01206df0
stm (er1-er3),@-sp ;01206df1
stm (er2-er4),@-sp ;01206df2
stm (er3-er5),@-sp ;01206df3
stm (er4-er6),@-sp ;01206df4
stm (er5-er7),@-sp ;01206df5
stm (er0-er3),@-sp ;01306df0
stm (er1-er4),@-sp ;01306df1
stm (er2-er5),@-sp ;01306df2
stm (er3-er6),@-sp ;01306df3
stm (er4-er7),@-sp ;01306df4
eepmov.b ;7b5c598f
eepmov.w ;7bd4598f
movmd.b ;7b94
movmd.w ;7ba4
movmd.l ;7bb4
movsd.b label ;7b840004
nop ;0000
nop ;0000
label:
.end
|
stsp/binutils-ia16
| 16,021
|
gdb/testsuite/gdb.disasm/t02_mova.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;mova
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
mova/b.c @(0x1234:16,r3l.b),er1 ;7A891234
mova/b.c @(0x1234:16,r3.w),er1 ;7A991234
mova/w.c @(0x1234:16,r3l.b),er1 ;7AA91234
mova/w.c @(0x1234:16,r3.w),er1 ;7AB91234
mova/l.c @(0x1234:16,r3l.b),er1 ;7AC91234
mova/l.c @(0x1234:16,r3.w),er1 ;7AD91234
mova/b.c @(0x12345678:32,r3l.b),er1 ;7A8112345678
mova/b.c @(0x12345678:32,r3.w),er1 ;7A9112345678
mova/w.c @(0x12345678:32,r3l.b),er1 ;7AA112345678
mova/w.c @(0x12345678:32,r3.w),er1 ;7AB112345678
mova/l.c @(0x12345678:32,r3l.b),er1 ;7AC112345678
mova/l.c @(0x12345678:32,r3.w),er1 ;7AD112345678
mova/b.l @(0x1234:16,r3l.b),er1 ;78B87A891234
mova/b.l @(0x1234:16,r3.w),er1 ;78397A991234
mova/w.l @(0x1234:16,r3l.b),er1 ;78B87AA91234
mova/w.l @(0x1234:16,r3.w),er1 ;78397AB91234
mova/l.l @(0x1234:16,r3l.b),er1 ;78B87AC91234
mova/l.l @(0x1234:16,r3.w),er1 ;78397AD91234
mova/b.l @(0x12345678:32,r3l.b),er1 ;78B87A8112345678
mova/b.l @(0x12345678:32,r3.w),er1 ;78397A9112345678
mova/w.l @(0x12345678:32,r3l.b),er1 ;78B87AA112345678
mova/w.l @(0x12345678:32,r3.w),er1 ;78397AB112345678
mova/l.l @(0x12345678:32,r3l.b),er1 ;78B87AC112345678
mova/l.l @(0x12345678:32,r3.w),er1 ;78397AD112345678
mova/b.l @(0x1234:16,@er2.b),er1 ;017F02811234
mova/b.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12811234
mova/b.l @(0x1234:16,@er2+.b),er1 ;017F82811234
mova/b.l @(0x1234:16,@-er2.b),er1 ;017FB2811234
mova/b.l @(0x1234:16,@+er2.b),er1 ;017F92811234
mova/b.l @(0x1234:16,@er2-.b),er1 ;017FA2811234
mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2819ABC1234
mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCA819ABCDEF01234
mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2819ABC1234
mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2819ABC1234
mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2819ABC1234
mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDA819ABCDEF01234
mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEA819ABCDEF01234
mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFA819ABCDEF01234
mova/b.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40819ABC1234
mova/b.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48819ABCDEF01234
mova/b.l @(0x1234:16,@er2.w),er1 ;015F02911234
mova/b.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12911234
mova/b.l @(0x1234:16,@er2+.w),er1 ;015F82911234
mova/b.l @(0x1234:16,@-er2.w),er1 ;015FB2911234
mova/b.l @(0x1234:16,@+er2.w),er1 ;015F92911234
mova/b.l @(0x1234:16,@er2-.w),er1 ;015FA2911234
mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2919ABC1234
mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCA919ABCDEF01234
mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2919ABC1234
mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2919ABC1234
mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2919ABC1234
mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDA919ABCDEF01234
mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEA919ABCDEF01234
mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFA919ABCDEF01234
mova/b.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40919ABC1234
mova/b.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48919ABCDEF01234
mova/w.l @(0x1234:16,@er2.b),er1 ;017F02A11234
mova/w.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12A11234
mova/w.l @(0x1234:16,@er2+.b),er1 ;017F82A11234
mova/w.l @(0x1234:16,@-er2.b),er1 ;017FB2A11234
mova/w.l @(0x1234:16,@+er2.b),er1 ;017F92A11234
mova/w.l @(0x1234:16,@er2-.b),er1 ;017FA2A11234
mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2A19ABC1234
mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAA19ABCDEF01234
mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2A19ABC1234
mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2A19ABC1234
mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2A19ABC1234
mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAA19ABCDEF01234
mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAA19ABCDEF01234
mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAA19ABCDEF01234
mova/w.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40A19ABC1234
mova/w.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48A19ABCDEF01234
mova/w.l @(0x1234:16,@er2.w),er1 ;015F02B11234
mova/w.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12B11234
mova/w.l @(0x1234:16,@er2+.w),er1 ;015F82B11234
mova/w.l @(0x1234:16,@-er2.w),er1 ;015FB2B11234
mova/w.l @(0x1234:16,@+er2.w),er1 ;015F92B11234
mova/w.l @(0x1234:16,@er2-.w),er1 ;015FA2B11234
mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2B19ABC1234
mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAB19ABCDEF01234
mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2B19ABC1234
mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2B19ABC1234
mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2B19ABC1234
mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAB19ABCDEF01234
mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAB19ABCDEF01234
mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAB19ABCDEF01234
mova/w.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40B19ABC1234
mova/w.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48B19ABCDEF01234
mova/l.l @(0x1234:16,@er2.b),er1 ;017F02C11234
mova/l.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12C11234
mova/l.l @(0x1234:16,@er2+.b),er1 ;017F82C11234
mova/l.l @(0x1234:16,@-er2.b),er1 ;017FB2C11234
mova/l.l @(0x1234:16,@+er2.b),er1 ;017F92C11234
mova/l.l @(0x1234:16,@er2-.b),er1 ;017FA2C11234
mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2C19ABC1234
mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAC19ABCDEF01234
mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2C19ABC1234
mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2C19ABC1234
mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2C19ABC1234
mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAC19ABCDEF01234
mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAC19ABCDEF01234
mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAC19ABCDEF01234
mova/l.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40C19ABC1234
mova/l.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48C19ABCDEF01234
mova/l.l @(0x1234:16,@er2.w),er1 ;015F02D11234
mova/l.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12D11234
mova/l.l @(0x1234:16,@er2+.w),er1 ;015F82D11234
mova/l.l @(0x1234:16,@-er2.w),er1 ;015FB2D11234
mova/l.l @(0x1234:16,@+er2.w),er1 ;015F92D11234
mova/l.l @(0x1234:16,@er2-.w),er1 ;015FA2D11234
mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2D19ABC1234
mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAD19ABCDEF01234
mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2D19ABC1234
mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2D19ABC1234
mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2D19ABC1234
mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAD19ABCDEF01234
mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAD19ABCDEF01234
mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAD19ABCDEF01234
mova/l.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40D19ABC1234
mova/l.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48D19ABCDEF01234
mova/b.l @(0x12345678:32,@er2.b),er1 ;017F028912345678
mova/b.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F128912345678
mova/b.l @(0x12345678:32,@er2+.b),er1 ;017F828912345678
mova/b.l @(0x12345678:32,@-er2.b),er1 ;017FB28912345678
mova/b.l @(0x12345678:32,@+er2.b),er1 ;017F928912345678
mova/b.l @(0x12345678:32,@er2-.b),er1 ;017FA28912345678
mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2899ABC12345678
mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCA899ABCDEF012345678
mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2899ABC12345678
mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2899ABC12345678
mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2899ABC12345678
mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDA899ABCDEF012345678
mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEA899ABCDEF012345678
mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFA899ABCDEF012345678
mova/b.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40899ABC12345678
mova/b.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48899ABCDEF012345678
mova/b.l @(0x12345678:32,@er2.w),er1 ;015F029912345678
mova/b.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F129912345678
mova/b.l @(0x12345678:32,@er2+.w),er1 ;015F829912345678
mova/b.l @(0x12345678:32,@-er2.w),er1 ;015FB29912345678
mova/b.l @(0x12345678:32,@+er2.w),er1 ;015F929912345678
mova/b.l @(0x12345678:32,@er2-.w),er1 ;015FA29912345678
mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2999ABC12345678
mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCA999ABCDEF012345678
mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2999ABC12345678
mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2999ABC12345678
mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2999ABC12345678
mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDA999ABCDEF012345678
mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEA999ABCDEF012345678
mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFA999ABCDEF012345678
mova/b.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40999ABC12345678
mova/b.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48999ABCDEF012345678
mova/w.l @(0x12345678:32,@er2.b),er1 ;017F02A912345678
mova/w.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12A912345678
mova/w.l @(0x12345678:32,@er2+.b),er1 ;017F82A912345678
mova/w.l @(0x12345678:32,@-er2.b),er1 ;017FB2A912345678
mova/w.l @(0x12345678:32,@+er2.b),er1 ;017F92A912345678
mova/w.l @(0x12345678:32,@er2-.b),er1 ;017FA2A912345678
mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2A99ABC12345678
mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAA99ABCDEF012345678
mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2A99ABC12345678
mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2A99ABC12345678
mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2A99ABC12345678
mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAA99ABCDEF012345678
mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAA99ABCDEF012345678
mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAA99ABCDEF012345678
mova/w.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40A99ABC12345678
mova/w.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48A99ABCDEF012345678
mova/w.l @(0x12345678:32,@er2.w),er1 ;015F02B912345678
mova/w.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12B912345678
mova/w.l @(0x12345678:32,@er2+.w),er1 ;015F82B912345678
mova/w.l @(0x12345678:32,@-er2.w),er1 ;015FB2B912345678
mova/w.l @(0x12345678:32,@+er2.w),er1 ;015F92B912345678
mova/w.l @(0x12345678:32,@er2-.w),er1 ;015FA2B912345678
mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2B99ABC12345678
mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAB99ABCDEF012345678
mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2B99ABC12345678
mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2B99ABC12345678
mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2B99ABC12345678
mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAB99ABCDEF012345678
mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAB99ABCDEF012345678
mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAB99ABCDEF012345678
mova/w.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40B99ABC12345678
mova/w.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48B99ABCDEF012345678
mova/l.l @(0x12345678:32,@er2.b),er1 ;017F02C912345678
mova/l.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12C912345678
mova/l.l @(0x12345678:32,@er2+.b),er1 ;017F82C912345678
mova/l.l @(0x12345678:32,@-er2.b),er1 ;017FB2C912345678
mova/l.l @(0x12345678:32,@+er2.b),er1 ;017F92C912345678
mova/l.l @(0x12345678:32,@er2-.b),er1 ;017FA2C912345678
mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2C99ABC12345678
mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAC99ABCDEF012345678
mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2C99ABC12345678
mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2C99ABC12345678
mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2C99ABC12345678
mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAC99ABCDEF012345678
mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAC99ABCDEF012345678
mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAC99ABCDEF012345678
mova/l.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40C99ABC12345678
mova/l.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48C99ABCDEF012345678
mova/l.l @(0x12345678:32,@er2.w),er1 ;015F02D912345678
mova/l.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12D912345678
mova/l.l @(0x12345678:32,@er2+.w),er1 ;015F82D912345678
mova/l.l @(0x12345678:32,@-er2.w),er1 ;015FB2D912345678
mova/l.l @(0x12345678:32,@+er2.w),er1 ;015F92D912345678
mova/l.l @(0x12345678:32,@er2-.w),er1 ;015FA2D912345678
mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2D99ABC12345678
mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAD99ABCDEF012345678
mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2D99ABC12345678
mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2D99ABC12345678
mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2D99ABC12345678
mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAD99ABCDEF012345678
mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAD99ABCDEF012345678
mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAD99ABCDEF012345678
mova/l.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40D99ABC12345678
mova/l.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48D99ABCDEF012345678
.end
|
stsp/binutils-ia16
| 67,588
|
gdb/testsuite/gdb.disasm/t04_sub.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;arith_1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
sub.b #0x12:8,@er1 ;7d10a112
sub.b #0x12:8,@(0x3:2,er1) ;01776818a112
sub.b #0x12:8,@er1+ ;01746c18a112
sub.b #0x12:8,@-er1 ;01776c18a112
sub.b #0x12:8,@+er1 ;01756c18a112
sub.b #0x12:8,@er1- ;01766c18a112
sub.b #0x12:8,@(0x1234:16,er1) ;01746e181234a112
sub.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678a112
sub.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234a112
sub.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234a112
sub.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234a112
sub.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678a112
sub.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678a112
sub.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678a112
sub.b #0x12:8,@0xffffff9a:8 ;7f9aa112
sub.b #0x12:8,@0x1234:16 ;6a181234a112
sub.b #0x12:8,@0x12345678:32 ;6a3812345678a112
sub.b r3h,r1h ;1831
sub.b r3h,@er1 ;7d101830
sub.b r3h,@(0x3:2,er1) ;01793133
sub.b r3h,@er1+ ;01798133
sub.b r3h,@-er1 ;0179b133
sub.b r3h,@+er1 ;01799133
sub.b r3h,@er1- ;0179a133
sub.b r3h,@(0x1234:16,er1) ;0179c1331234
sub.b r3h,@(0x12345678:32,er1) ;0179c93312345678
sub.b r3h,@(0x1234:16,r2l.b) ;0179d2331234
sub.b r3h,@(0x1234:16,r2.w) ;0179e2331234
sub.b r3h,@(0x1234:16,er2.l) ;0179f2331234
sub.b r3h,@(0x12345678:32,r2l.b) ;0179da3312345678
sub.b r3h,@(0x12345678:32,r2.w) ;0179ea3312345678
sub.b r3h,@(0x12345678:32,er2.l) ;0179fa3312345678
sub.b r3h,@0xffffff12:8 ;7f121830
sub.b r3h,@0x1234:16 ;6a1812341830
sub.b r3h,@0x12345678:32 ;6a38123456781830
sub.b @er3,r1h ;7c301801
sub.b @(0x3:2,er3),r1h ;017a3331
sub.b @er3+,r1h ;017a8331
sub.b @-er3,r1h ;017ab331
sub.b @+er3,r1h ;017a9331
sub.b @er3-,r1h ;017aa331
sub.b @(0x1234:16,er1),r1h ;017ac1311234
sub.b @(0x12345678:32,er1),r1h ;017ac93112345678
sub.b @(0x1234:16,r2l.b),r1h ;017ad2311234
sub.b @(0x1234:16,r2.w),r1h ;017ae2311234
sub.b @(0x1234:16,er2.l),r1h ;017af2311234
sub.b @(0x12345678:32,r2l.b),r1h ;017ada3112345678
sub.b @(0x12345678:32,r2.w),r1h ;017aea3112345678
sub.b @(0x12345678:32,er2.l),r1h ;017afa3112345678
sub.b @0xffffff12:8,r1h ;7e121801
sub.b @0x1234:16,r1h ;6a1012341801
sub.b @0x12345678:32,r1h ;6a30123456781801
sub.b @er3,@er1 ;7c350130
sub.b @er3,@(3:2,er1) ;7c353130
sub.b @er3,@-er1 ;7c35b130
sub.b @er3,@er1+ ;7c358130
sub.b @er3,@er1- ;7c35a130
sub.b @er3,@+er1 ;7c359130
sub.b @er3,@(0xffff9abc:16,er1) ;7c35c1309abc
sub.b @er3,@(0x9abcdef0:32,er1) ;7c35c9309abcdef0
sub.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2309abc
sub.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2309abc
sub.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2309abc
sub.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da309abcdef0
sub.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea309abcdef0
sub.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa309abcdef0
sub.b @er3,@0xffff9abc:16 ;7c3540309abc
sub.b @er3,@0x9abcdef0:32 ;7c3548309abcdef0
sub.b @-er3,@er1 ;01776c3c0130
sub.b @-er3,@(3:2,er1) ;01776c3c3130
sub.b @-er3,@-er1 ;01776c3cb130
sub.b @-er3,@er1+ ;01776c3c8130
sub.b @-er3,@er1- ;01776c3ca130
sub.b @-er3,@+er1 ;01776c3c9130
sub.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1309abc
sub.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9309abcdef0
sub.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2309abc
sub.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2309abc
sub.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2309abc
sub.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda309abcdef0
sub.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea309abcdef0
sub.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa309abcdef0
sub.b @-er3,@0xffff9abc:16 ;01776c3c40309abc
sub.b @-er3,@0x9abcdef0:32 ;01776c3c48309abcdef0
sub.b @er3+,@er1 ;01746c3c0130
sub.b @er3+,@(3:2,er1) ;01746c3c3130
sub.b @er3+,@-er1 ;01746c3cb130
sub.b @er3+,@er1+ ;01746c3c8130
sub.b @er3+,@er1- ;01746c3ca130
sub.b @er3+,@+er1 ;01746c3c9130
sub.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1309abc
sub.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9309abcdef0
sub.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2309abc
sub.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2309abc
sub.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2309abc
sub.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda309abcdef0
sub.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea309abcdef0
sub.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa309abcdef0
sub.b @er3+,@0xffff9abc:16 ;01746c3c40309abc
sub.b @er3+,@0x9abcdef0:32 ;01746c3c48309abcdef0
sub.b @er3-,@er1 ;01766c3c0130
sub.b @er3-,@(3:2,er1) ;01766c3c3130
sub.b @er3-,@-er1 ;01766c3cb130
sub.b @er3-,@er1+ ;01766c3c8130
sub.b @er3-,@er1- ;01766c3ca130
sub.b @er3-,@+er1 ;01766c3c9130
sub.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1309abc
sub.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9309abcdef0
sub.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2309abc
sub.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2309abc
sub.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2309abc
sub.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda309abcdef0
sub.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea309abcdef0
sub.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa309abcdef0
sub.b @er3-,@0xffff9abc:16 ;01766c3c40309abc
sub.b @er3-,@0x9abcdef0:32 ;01766c3c48309abcdef0
sub.b @+er3,@er1 ;01756c3c0130
sub.b @+er3,@(3:2,er1) ;01756c3c3130
sub.b @+er3,@-er1 ;01756c3cb130
sub.b @+er3,@er1+ ;01756c3c8130
sub.b @+er3,@er1- ;01756c3ca130
sub.b @+er3,@+er1 ;01756c3c9130
sub.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1309abc
sub.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9309abcdef0
sub.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2309abc
sub.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2309abc
sub.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2309abc
sub.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda309abcdef0
sub.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea309abcdef0
sub.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa309abcdef0
sub.b @+er3,@0xffff9abc:16 ;01756c3c40309abc
sub.b @+er3,@0x9abcdef0:32 ;01756c3c48309abcdef0
sub.b @(0x1234:16,er3),@er1 ;01746e3c12340130
sub.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343130
sub.b @(0x1234:16,er3),@-er1 ;01746e3c1234b130
sub.b @(0x1234:16,er3),@er1+ ;01746e3c12348130
sub.b @(0x1234:16,er3),@er1- ;01746e3c1234a130
sub.b @(0x1234:16,er3),@+er1 ;01746e3c12349130
sub.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1309abc
sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9309abcdef0
sub.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2309abc
sub.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2309abc
sub.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2309abc
sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da309abcdef0
sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea309abcdef0
sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa309abcdef0
sub.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440309abc
sub.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448309abcdef0
sub.b @(0x12345678:32,er3),@er1 ;78346a2c123456780130
sub.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783130
sub.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b130
sub.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788130
sub.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a130
sub.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789130
sub.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1309abc
sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9309abcdef0
sub.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2309abc
sub.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2309abc
sub.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2309abc
sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da309abcdef0
sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea309abcdef0
sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa309abcdef0
sub.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840309abc
sub.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848309abcdef0
sub.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340130
sub.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343130
sub.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b130
sub.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348130
sub.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a130
sub.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349130
sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1309abc
sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9309abcdef0
sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2309abc
sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2309abc
sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2309abc
sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da309abcdef0
sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea309abcdef0
sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa309abcdef0
sub.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440309abc
sub.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448309abcdef0
sub.b @(0x1234:16,r3.w),@er1 ;01766e3c12340130
sub.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343130
sub.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b130
sub.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348130
sub.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a130
sub.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349130
sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1309abc
sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9309abcdef0
sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2309abc
sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2309abc
sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2309abc
sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da309abcdef0
sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea309abcdef0
sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa309abcdef0
sub.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440309abc
sub.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448309abcdef0
sub.b @(0x1234:16,er3.l),@er1 ;01776e3c12340130
sub.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343130
sub.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b130
sub.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348130
sub.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a130
sub.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349130
sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1309abc
sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9309abcdef0
sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2309abc
sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2309abc
sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2309abc
sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da309abcdef0
sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea309abcdef0
sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa309abcdef0
sub.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440309abc
sub.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448309abcdef0
sub.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780130
sub.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783130
sub.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b130
sub.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788130
sub.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a130
sub.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789130
sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1309abc
sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9309abcdef0
sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2309abc
sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2309abc
sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2309abc
sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da309abcdef0
sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea309abcdef0
sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa309abcdef0
sub.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840309abc
sub.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848309abcdef0
sub.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780130
sub.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783130
sub.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b130
sub.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788130
sub.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a130
sub.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789130
sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1309abc
sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9309abcdef0
sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2309abc
sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2309abc
sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2309abc
sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da309abcdef0
sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea309abcdef0
sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa309abcdef0
sub.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840309abc
sub.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848309abcdef0
sub.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780130
sub.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783130
sub.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b130
sub.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788130
sub.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a130
sub.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789130
sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1309abc
sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9309abcdef0
sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2309abc
sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2309abc
sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2309abc
sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da309abcdef0
sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea309abcdef0
sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa309abcdef0
sub.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840309abc
sub.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848309abcdef0
sub.b @0x1234:16,@er1 ;6a1512340130
sub.b @0x1234:16,@(3:2,er1) ;6a1512343130
sub.b @0x1234:16,@-er1 ;6a151234b130
sub.b @0x1234:16,@er1+ ;6a1512348130
sub.b @0x1234:16,@er1- ;6a151234a130
sub.b @0x1234:16,@+er1 ;6a1512349130
sub.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1309abc
sub.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9309abcdef0
sub.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2309abc
sub.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2309abc
sub.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2309abc
sub.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da309abcdef0
sub.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea309abcdef0
sub.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa309abcdef0
sub.b @0x1234:16,@0xffff9abc:16 ;6a15123440309abc
sub.b @0x1234:16,@0x9abcdef0:32 ;6a15123448309abcdef0
sub.b @0x12345678:32,@er1 ;6a35123456780130
sub.b @0x12345678:32,@(3:2,er1) ;6a35123456783130
sub.b @0x12345678:32,@-er1 ;6a3512345678b130
sub.b @0x12345678:32,@er1+ ;6a35123456788130
sub.b @0x12345678:32,@er1- ;6a3512345678a130
sub.b @0x12345678:32,@+er1 ;6a35123456789130
sub.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1309abc
sub.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9309abcdef0
sub.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2309abc
sub.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2309abc
sub.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2309abc
sub.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da309abcdef0
sub.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea309abcdef0
sub.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa309abcdef0
sub.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840309abc
sub.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848309abcdef0
sub.w #0x1234:16,r1 ;79311234
sub.w #7:3,r2 ;1a72
sub.w #0x1234:16,@er1 ;015e01301234
sub.w #0x1234:16,@(0x6:2,er1) ;015e31301234
sub.w #0x1234:16,@er1+ ;015e81301234
sub.w #0x1234:16,@-er1 ;015eb1301234
sub.w #0x1234:16,@+er1 ;015e91301234
sub.w #0x1234:16,@er1- ;015ea1301234
sub.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1309abc1234
sub.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9309abcdef01234
sub.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2309abc1234
sub.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2309abc1234
sub.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2309abc1234
sub.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda309abcdef01234
sub.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea309abcdef01234
sub.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa309abcdef01234
sub.w #0x1234:16,@0xffff9abc:16 ;015e40309abc1234
sub.w #0x1234:16,@0x9abcdef0:32 ;015e48309abcdef01234
sub.w #0x7:3,@er1 ;7d901a70
sub.w #0x7:3,@0x1234:16 ;6b1812341a70
sub.w #0x7:3,@0x12345678:32 ;6b38123456781a70
sub.w r3,r1 ;1931
sub.w r3,@er1 ;7d901930
sub.w r3,@(0x6:2,er1) ;01593133
sub.w r3,@er1+ ;01598133
sub.w r3,@-er1 ;0159b133
sub.w r3,@+er1 ;01599133
sub.w r3,@er1- ;0159a133
sub.w r3,@(0x1234:16,er1) ;0159c1331234
sub.w r3,@(0x12345678:32,er1) ;0159c93312345678
sub.w r3,@(0x1234:16,r2l.b) ;0159d2331234
sub.w r3,@(0x1234:16,r2.w) ;0159e2331234
sub.w r3,@(0x1234:16,er2.l) ;0159f2331234
sub.w r3,@(0x12345678:32,r2l.b) ;0159da3312345678
sub.w r3,@(0x12345678:32,r2.w) ;0159ea3312345678
sub.w r3,@(0x12345678:32,er2.l) ;0159fa3312345678
sub.w r3,@0x1234:16 ;6b1812341930
sub.w r3,@0x12345678:32 ;6b38123456781930
sub.w @er3,r1 ;7cb01901
sub.w @(0x6:2,er3),r1 ;015a3331
sub.w @er3+,r1 ;015a8331
sub.w @-er3,r1 ;015ab331
sub.w @+er3,r1 ;015a9331
sub.w @er3-,r1 ;015aa331
sub.w @(0x1234:16,er1),r1 ;015ac1311234
sub.w @(0x12345678:32,er1),r1 ;015ac93112345678
sub.w @(0x1234:16,r2l.b),r1 ;015ad2311234
sub.w @(0x1234:16,r2.w),r1 ;015ae2311234
sub.w @(0x1234:16,er2.l),r1 ;015af2311234
sub.w @(0x12345678:32,r2l.b),r1 ;015ada3112345678
sub.w @(0x12345678:32,r2.w),r1 ;015aea3112345678
sub.w @(0x12345678:32,er2.l),r1 ;015afa3112345678
sub.w @0x1234:16,r1 ;6b1012341901
sub.w @0x12345678:32,r1 ;6b30123456781901
sub.w @er3,@er1 ;7cb50130
sub.w @er3,@(6:2,er1) ;7cb53130
sub.w @er3,@-er1 ;7cb5b130
sub.w @er3,@er1+ ;7cb58130
sub.w @er3,@er1- ;7cb5a130
sub.w @er3,@+er1 ;7cb59130
sub.w @er3,@(0xffff9abc:16,er1) ;7cb5c1309abc
sub.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9309abcdef0
sub.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2309abc
sub.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2309abc
sub.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2309abc
sub.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da309abcdef0
sub.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea309abcdef0
sub.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa309abcdef0
sub.w @er3,@0xffff9abc:16 ;7cb540309abc
sub.w @er3,@0x9abcdef0:32 ;7cb548309abcdef0
sub.w @-er3,@er1 ;01576d3c0130
sub.w @-er3,@(6:2,er1) ;01576d3c3130
sub.w @-er3,@-er1 ;01576d3cb130
sub.w @-er3,@er1+ ;01576d3c8130
sub.w @-er3,@er1- ;01576d3ca130
sub.w @-er3,@+er1 ;01576d3c9130
sub.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1309abc
sub.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9309abcdef0
sub.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2309abc
sub.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2309abc
sub.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2309abc
sub.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda309abcdef0
sub.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea309abcdef0
sub.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa309abcdef0
sub.w @-er3,@0xffff9abc:16 ;01576d3c40309abc
sub.w @-er3,@0x9abcdef0:32 ;01576d3c48309abcdef0
sub.w @er3+,@er1 ;01546d3c0130
sub.w @er3+,@(6:2,er1) ;01546d3c3130
sub.w @er3+,@-er1 ;01546d3cb130
sub.w @er3+,@er1+ ;01546d3c8130
sub.w @er3+,@er1- ;01546d3ca130
sub.w @er3+,@+er1 ;01546d3c9130
sub.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1309abc
sub.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9309abcdef0
sub.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2309abc
sub.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2309abc
sub.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2309abc
sub.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda309abcdef0
sub.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea309abcdef0
sub.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa309abcdef0
sub.w @er3+,@0xffff9abc:16 ;01546d3c40309abc
sub.w @er3+,@0x9abcdef0:32 ;01546d3c48309abcdef0
sub.w @er3-,@er1 ;01566d3c0130
sub.w @er3-,@(6:2,er1) ;01566d3c3130
sub.w @er3-,@-er1 ;01566d3cb130
sub.w @er3-,@er1+ ;01566d3c8130
sub.w @er3-,@er1- ;01566d3ca130
sub.w @er3-,@+er1 ;01566d3c9130
sub.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1309abc
sub.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9309abcdef0
sub.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2309abc
sub.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2309abc
sub.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2309abc
sub.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda309abcdef0
sub.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea309abcdef0
sub.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa309abcdef0
sub.w @er3-,@0xffff9abc:16 ;01566d3c40309abc
sub.w @er3-,@0x9abcdef0:32 ;01566d3c48309abcdef0
sub.w @+er3,@er1 ;01556d3c0130
sub.w @+er3,@(6:2,er1) ;01556d3c3130
sub.w @+er3,@-er1 ;01556d3cb130
sub.w @+er3,@er1+ ;01556d3c8130
sub.w @+er3,@er1- ;01556d3ca130
sub.w @+er3,@+er1 ;01556d3c9130
sub.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1309abc
sub.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9309abcdef0
sub.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2309abc
sub.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2309abc
sub.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2309abc
sub.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda309abcdef0
sub.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea309abcdef0
sub.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa309abcdef0
sub.w @+er3,@0xffff9abc:16 ;01556d3c40309abc
sub.w @+er3,@0x9abcdef0:32 ;01556d3c48309abcdef0
sub.w @(0x1234:16,er3),@er1 ;01546f3c12340130
sub.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343130
sub.w @(0x1234:16,er3),@-er1 ;01546f3c1234b130
sub.w @(0x1234:16,er3),@er1+ ;01546f3c12348130
sub.w @(0x1234:16,er3),@er1- ;01546f3c1234a130
sub.w @(0x1234:16,er3),@+er1 ;01546f3c12349130
sub.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1309abc
sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9309abcdef0
sub.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2309abc
sub.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2309abc
sub.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2309abc
sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da309abcdef0
sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea309abcdef0
sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa309abcdef0
sub.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440309abc
sub.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448309abcdef0
sub.w @(0x12345678:32,er3),@er1 ;78346b2c123456780130
sub.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783130
sub.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b130
sub.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788130
sub.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a130
sub.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789130
sub.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1309abc
sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9309abcdef0
sub.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2309abc
sub.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2309abc
sub.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2309abc
sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da309abcdef0
sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea309abcdef0
sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa309abcdef0
sub.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840309abc
sub.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848309abcdef0
sub.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340130
sub.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343130
sub.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b130
sub.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348130
sub.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a130
sub.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349130
sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1309abc
sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9309abcdef0
sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2309abc
sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2309abc
sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2309abc
sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da309abcdef0
sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea309abcdef0
sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa309abcdef0
sub.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440309abc
sub.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448309abcdef0
sub.w @(0x1234:16,r3.w),@er1 ;01566f3c12340130
sub.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343130
sub.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b130
sub.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348130
sub.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a130
sub.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349130
sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1309abc
sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9309abcdef0
sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2309abc
sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2309abc
sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2309abc
sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da309abcdef0
sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea309abcdef0
sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa309abcdef0
sub.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440309abc
sub.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448309abcdef0
sub.w @(0x1234:16,er3.l),@er1 ;01576f3c12340130
sub.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343130
sub.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b130
sub.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348130
sub.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a130
sub.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349130
sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1309abc
sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9309abcdef0
sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2309abc
sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2309abc
sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2309abc
sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da309abcdef0
sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea309abcdef0
sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa309abcdef0
sub.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440309abc
sub.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448309abcdef0
sub.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780130
sub.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783130
sub.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b130
sub.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788130
sub.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a130
sub.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789130
sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1309abc
sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9309abcdef0
sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2309abc
sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2309abc
sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2309abc
sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da309abcdef0
sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea309abcdef0
sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa309abcdef0
sub.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840309abc
sub.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848309abcdef0
sub.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780130
sub.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783130
sub.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b130
sub.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788130
sub.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a130
sub.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789130
sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1309abc
sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9309abcdef0
sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2309abc
sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2309abc
sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2309abc
sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da309abcdef0
sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea309abcdef0
sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa309abcdef0
sub.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840309abc
sub.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848309abcdef0
sub.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780130
sub.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783130
sub.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b130
sub.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788130
sub.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a130
sub.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789130
sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1309abc
sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9309abcdef0
sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2309abc
sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2309abc
sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2309abc
sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da309abcdef0
sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea309abcdef0
sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa309abcdef0
sub.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840309abc
sub.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848309abcdef0
sub.w @0x1234:16,@er1 ;6b1512340130
sub.w @0x1234:16,@(6:2,er1) ;6b1512343130
sub.w @0x1234:16,@-er1 ;6b151234b130
sub.w @0x1234:16,@er1+ ;6b1512348130
sub.w @0x1234:16,@er1- ;6b151234a130
sub.w @0x1234:16,@+er1 ;6b1512349130
sub.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1309abc
sub.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9309abcdef0
sub.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2309abc
sub.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2309abc
sub.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2309abc
sub.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da309abcdef0
sub.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea309abcdef0
sub.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa309abcdef0
sub.w @0x1234:16,@0xffff9abc:16 ;6b15123440309abc
sub.w @0x1234:16,@0x9abcdef0:32 ;6b15123448309abcdef0
sub.w @0x12345678:32,@er1 ;6b35123456780130
sub.w @0x12345678:32,@(6:2,er1) ;6b35123456783130
sub.w @0x12345678:32,@-er1 ;6b3512345678b130
sub.w @0x12345678:32,@er1+ ;6b35123456788130
sub.w @0x12345678:32,@er1- ;6b3512345678a130
sub.w @0x12345678:32,@+er1 ;6b35123456789130
sub.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1309abc
sub.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9309abcdef0
sub.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2309abc
sub.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2309abc
sub.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2309abc
sub.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da309abcdef0
sub.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea309abcdef0
sub.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa309abcdef0
sub.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840309abc
sub.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848309abcdef0
sub.l #0x12345678:32,er1 ;7a3112345678
sub.l #0x1234:16,er1 ;7a391234
sub.l #0x7:3,er2 ;1afa
sub.l #0x12345678:32,@er1 ;010e013812345678
sub.l #0x12345678:32,@(0xc:2,er1) ;010e313812345678
sub.l #0x12345678:32,@er1+ ;010e813812345678
sub.l #0x12345678:32,@-er1 ;010eb13812345678
sub.l #0x12345678:32,@+er1 ;010e913812345678
sub.l #0x12345678:32,@er1- ;010ea13812345678
sub.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1389abc12345678
sub.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9389abcdef012345678
sub.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2389abc12345678
sub.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2389abc12345678
sub.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2389abc12345678
sub.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda389abcdef012345678
sub.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea389abcdef012345678
sub.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa389abcdef012345678
sub.l #0x12345678:32,@0xffff9abc:16 ;010e40389abc12345678
sub.l #0x12345678:32,@0x9abcdef0:32 ;010e48389abcdef012345678
sub.l #0x1234:16,@er1 ;010e01301234
sub.l #0x1234:16,@(0xc:2,er1) ;010e31301234
sub.l #0x1234:16,@er1+ ;010e81301234
sub.l #0x1234:16,@-er1 ;010eb1301234
sub.l #0x1234:16,@+er1 ;010e91301234
sub.l #0x1234:16,@er1- ;010ea1301234
sub.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1309abc1234
sub.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9309abcdef01234
sub.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2309abc1234
sub.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2309abc1234
sub.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2309abc1234
sub.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda309abcdef01234
sub.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea309abcdef01234
sub.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa309abcdef01234
sub.l #0x1234:16,@0xffff9abc:16 ;010e40309abc1234
sub.l #0x1234:16,@0x9abcdef0:32 ;010e48309abcdef01234
sub.l er3,er1 ;1ab1
sub.l er3,@er1 ;01090133
sub.l er3,@(0xc:2,er1) ;01093133
sub.l er3,@er1+ ;01098133
sub.l er3,@-er1 ;0109b133
sub.l er3,@+er1 ;01099133
sub.l er3,@er1- ;0109a133
sub.l er3,@(0x1234:16,er1) ;0109c1331234
sub.l er3,@(0x12345678:32,er1) ;0109c93312345678
sub.l er3,@(0x1234:16,r2l.b) ;0109d2331234
sub.l er3,@(0x1234:16,r2.w) ;0109e2331234
sub.l er3,@(0x1234:16,er2.l) ;0109f2331234
sub.l er3,@(0x12345678:32,r2l.b) ;0109da3312345678
sub.l er3,@(0x12345678:32,r2.w) ;0109ea3312345678
sub.l er3,@(0x12345678:32,er2.l) ;0109fa3312345678
sub.l er3,@0x1234:16 ;010940331234
sub.l er3,@0x12345678:32 ;0109483312345678
sub.l @er3,er1 ;010a0331
sub.l @(0xc:2,er3),er1 ;010a3331
sub.l @er3+,er1 ;010a8331
sub.l @-er3,er1 ;010ab331
sub.l @+er3,er1 ;010a9331
sub.l @er3-,er1 ;010aa331
sub.l @(0x1234:16,er1),er1 ;010ac1311234
sub.l @(0x12345678:32,er1),er1 ;010ac93112345678
sub.l @(0x1234:16,r2l.b),er1 ;010ad2311234
sub.l @(0x1234:16,r2.w),er1 ;010ae2311234
sub.l @(0x1234:16,er2.l),er1 ;010af2311234
sub.l @(0x12345678:32,r2l.b),er1 ;010ada3112345678
sub.l @(0x12345678:32,r2.w),er1 ;010aea3112345678
sub.l @(0x12345678:32,er2.l),er1 ;010afa3112345678
sub.l @0x1234:16,er1 ;010a40311234
sub.l @0x12345678:32,er1 ;010a483112345678
sub.l @er3,@er1 ;0104693c0130
sub.l @er3,@(0xc:2,er1) ;0104693c3130
sub.l @er3,@-er1 ;0104693cb130
sub.l @er3,@er1+ ;0104693c8130
sub.l @er3,@er1- ;0104693ca130
sub.l @er3,@+er1 ;0104693c9130
sub.l @er3,@(0xffff9abc:16,er1) ;0104693cc1309abc
sub.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9309abcdef0
sub.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2309abc
sub.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2309abc
sub.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2309abc
sub.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda309abcdef0
sub.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea309abcdef0
sub.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa309abcdef0
sub.l @er3,@0xffff9abc:16 ;0104693c40309abc
sub.l @er3,@0x9abcdef0:32 ;0104693c48309abcdef0
sub.l @(0xc:2,er3),@er1 ;0107693c0130
sub.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3130
sub.l @(0xc:2,er3),@-er1 ;0107693cb130
sub.l @(0xc:2,er3),@er1+ ;0107693c8130
sub.l @(0xc:2,er3),@er1- ;0107693ca130
sub.l @(0xc:2,er3),@+er1 ;0107693c9130
sub.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1309abc
sub.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9309abcdef0
sub.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2309abc
sub.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2309abc
sub.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2309abc
sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda309abcdef0
sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea309abcdef0
sub.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa309abcdef0
sub.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40309abc
sub.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48309abcdef0
sub.l @-er3,@er1 ;01076d3c0130
sub.l @-er3,@(0xc:2,er1) ;01076d3c3130
sub.l @-er3,@-er1 ;01076d3cb130
sub.l @-er3,@er1+ ;01076d3c8130
sub.l @-er3,@er1- ;01076d3ca130
sub.l @-er3,@+er1 ;01076d3c9130
sub.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1309abc
sub.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9309abcdef0
sub.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2309abc
sub.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2309abc
sub.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2309abc
sub.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda309abcdef0
sub.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea309abcdef0
sub.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa309abcdef0
sub.l @-er3,@0xffff9abc:16 ;01076d3c40309abc
sub.l @-er3,@0x9abcdef0:32 ;01076d3c48309abcdef0
sub.l @er3+,@er1 ;01046d3c0130
sub.l @er3+,@(0xc:2,er1) ;01046d3c3130
sub.l @er3+,@-er1 ;01046d3cb130
sub.l @er3+,@er1+ ;01046d3c8130
sub.l @er3+,@er1- ;01046d3ca130
sub.l @er3+,@+er1 ;01046d3c9130
sub.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1309abc
sub.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9309abcdef0
sub.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2309abc
sub.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2309abc
sub.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2309abc
sub.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda309abcdef0
sub.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea309abcdef0
sub.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa309abcdef0
sub.l @er3+,@0xffff9abc:16 ;01046d3c40309abc
sub.l @er3+,@0x9abcdef0:32 ;01046d3c48309abcdef0
sub.l @er3-,@er1 ;01066d3c0130
sub.l @er3-,@(0xc:2,er1) ;01066d3c3130
sub.l @er3-,@-er1 ;01066d3cb130
sub.l @er3-,@er1+ ;01066d3c8130
sub.l @er3-,@er1- ;01066d3ca130
sub.l @er3-,@+er1 ;01066d3c9130
sub.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1309abc
sub.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9309abcdef0
sub.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2309abc
sub.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2309abc
sub.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2309abc
sub.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda309abcdef0
sub.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea309abcdef0
sub.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa309abcdef0
sub.l @er3-,@0xffff9abc:16 ;01066d3c40309abc
sub.l @er3-,@0x9abcdef0:32 ;01066d3c48309abcdef0
sub.l @+er3,@er1 ;01056d3c0130
sub.l @+er3,@(0xc:2,er1) ;01056d3c3130
sub.l @+er3,@-er1 ;01056d3cb130
sub.l @+er3,@er1+ ;01056d3c8130
sub.l @+er3,@er1- ;01056d3ca130
sub.l @+er3,@+er1 ;01056d3c9130
sub.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1309abc
sub.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9309abcdef0
sub.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2309abc
sub.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2309abc
sub.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2309abc
sub.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda309abcdef0
sub.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea309abcdef0
sub.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa309abcdef0
sub.l @+er3,@0xffff9abc:16 ;01056d3c40309abc
sub.l @+er3,@0x9abcdef0:32 ;01056d3c48309abcdef0
sub.l @(0x1234:16,er3),@er1 ;01046f3c12340130
sub.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343130
sub.l @(0x1234:16,er3),@-er1 ;01046f3c1234b130
sub.l @(0x1234:16,er3),@er1+ ;01046f3c12348130
sub.l @(0x1234:16,er3),@er1- ;01046f3c1234a130
sub.l @(0x1234:16,er3),@+er1 ;01046f3c12349130
sub.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1309abc
sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9309abcdef0
sub.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2309abc
sub.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2309abc
sub.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2309abc
sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da309abcdef0
sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea309abcdef0
sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa309abcdef0
sub.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440309abc
sub.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448309abcdef0
sub.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780130
sub.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783130
sub.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b130
sub.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788130
sub.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a130
sub.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789130
sub.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1309abc
sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9309abcdef0
sub.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2309abc
sub.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2309abc
sub.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2309abc
sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da309abcdef0
sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea309abcdef0
sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa309abcdef0
sub.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840309abc
sub.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848309abcdef0
sub.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340130
sub.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343130
sub.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b130
sub.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348130
sub.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a130
sub.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349130
sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1309abc
sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9309abcdef0
sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2309abc
sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2309abc
sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2309abc
sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da309abcdef0
sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea309abcdef0
sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa309abcdef0
sub.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440309abc
sub.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448309abcdef0
sub.l @(0x1234:16,r3.w),@er1 ;01066f3c12340130
sub.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343130
sub.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b130
sub.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348130
sub.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a130
sub.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349130
sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1309abc
sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9309abcdef0
sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2309abc
sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2309abc
sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2309abc
sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da309abcdef0
sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea309abcdef0
sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa309abcdef0
sub.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440309abc
sub.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448309abcdef0
sub.l @(0x1234:16,er3.l),@er1 ;01076f3c12340130
sub.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343130
sub.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b130
sub.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348130
sub.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a130
sub.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349130
sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1309abc
sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9309abcdef0
sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2309abc
sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2309abc
sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2309abc
sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da309abcdef0
sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea309abcdef0
sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa309abcdef0
sub.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440309abc
sub.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448309abcdef0
sub.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780130
sub.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783130
sub.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b130
sub.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788130
sub.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a130
sub.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789130
sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1309abc
sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9309abcdef0
sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2309abc
sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2309abc
sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2309abc
sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da309abcdef0
sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea309abcdef0
sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa309abcdef0
sub.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840309abc
sub.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848309abcdef0
sub.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780130
sub.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783130
sub.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b130
sub.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788130
sub.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a130
sub.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789130
sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1309abc
sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9309abcdef0
sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2309abc
sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2309abc
sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2309abc
sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da309abcdef0
sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea309abcdef0
sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa309abcdef0
sub.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840309abc
sub.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848309abcdef0
sub.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780130
sub.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783130
sub.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b130
sub.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788130
sub.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a130
sub.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789130
sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1309abc
sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9309abcdef0
sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2309abc
sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2309abc
sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2309abc
sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da309abcdef0
sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea309abcdef0
sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa309abcdef0
sub.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840309abc
sub.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848309abcdef0
sub.l @0x1234:16,@er1 ;01046b0c12340130
sub.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343130
sub.l @0x1234:16,@-er1 ;01046b0c1234b130
sub.l @0x1234:16,@er1+ ;01046b0c12348130
sub.l @0x1234:16,@er1- ;01046b0c1234a130
sub.l @0x1234:16,@+er1 ;01046b0c12349130
sub.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1309abc
sub.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9309abcdef0
sub.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2309abc
sub.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2309abc
sub.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2309abc
sub.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da309abcdef0
sub.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea309abcdef0
sub.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa309abcdef0
sub.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440309abc
sub.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448309abcdef0
sub.l @0x12345678:32,@er1 ;01046b2c123456780130
sub.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783130
sub.l @0x12345678:32,@-er1 ;01046b2c12345678b130
sub.l @0x12345678:32,@er1+ ;01046b2c123456788130
sub.l @0x12345678:32,@er1- ;01046b2c12345678a130
sub.l @0x12345678:32,@+er1 ;01046b2c123456789130
sub.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1309abc
sub.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9309abcdef0
sub.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2309abc
sub.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2309abc
sub.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2309abc
sub.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da309abcdef0
sub.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea309abcdef0
sub.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa309abcdef0
sub.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840309abc
sub.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848309abcdef0
.end
|
stsp/binutils-ia16
| 5,816
|
gdb/testsuite/gdb.disasm/t13_otr.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;others
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.org 0x12
lab_12:
.org 0x1234
.global _start
_start:
bra 0x12+.+2 ;4012
brn 0x12+.+2 ;4112
bhi 0x12+.+2 ;4212
bls 0x12+.+2 ;4312
bcc 0x12+.+2 ;4412
bcs 0x12+.+2 ;4512
bne 0x12+.+2 ;4612
beq 0x12+.+2 ;4712
bvc 0x12+.+2 ;4812
bvs 0x12+.+2 ;4912
bpl 0x12+.+2 ;4a12
bmi 0x12+.+2 ;4b12
bge 0x12+.+2 ;4c12
blt 0x12+.+2 ;4d12
bgt 0x12+.+2 ;4e12
ble 0x12+.+2 ;4f12
bra 0x1234+.+4 ;58001234
brn 0x1234+.+4 ;58101234
bhi 0x1234+.+4 ;58201234
bls 0x1234+.+4 ;58301234
bcc 0x1234+.+4 ;58401234
bcs 0x1234+.+4 ;58501234
bne 0x1234+.+4 ;58601234
beq 0x1234+.+4 ;58701234
bvc 0x1234+.+4 ;58801234
bvs 0x1234+.+4 ;58901234
bpl 0x1234+.+4 ;58a01234
bmi 0x1234+.+4 ;58b01234
bge 0x1234+.+4 ;58c01234
blt 0x1234+.+4 ;58d01234
bgt 0x1234+.+4 ;58e01234
ble 0x1234+.+4 ;58f01234
bra/s 0x12+.+2 ;4013
nop ;0000
bra/bc #0x7,@er2,0x12+.+4 ;7c204712
bra/bc #0x7,@0xffffff9a:8,0x12+.+4 ;7e9a4712
bra/bc #0x7,@0x1234:16,0x12+.+6 ;6a1012344712
bra/bc #0x7,@0x12345678:32,0x12+.+8 ;6a30123456784712
bra/bc #0x7,@er2,0x1234+.+6 ;7c2058701234
bra/bc #0x7,@0xffffff12:8,0x1234+.+6 ;7e1258701234
bra/bc #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc58701234
bra/bc #0x7,@0x12345678:32,0x1234+.+0xa ;6a301234567858701234
bra/bs #0x7,@er2,0x12+.+4 ;7c204f12
bra/bs #0x7,@0xffffff9a:8,0x12+.+4 ;7e9a4f12
bra/bs #0x7,@0x1234:16,0x12+.+6 ;6a1012344f12
bra/bs #0x7,@0x12345678:32,0x12+.+8 ;6a30123456784f12
bra/bs #0x7,@er2,0x1234+.+6 ;7c2058f01234
bra/bs #0x7,@0xffffff12:8,0x1234+.+6 ;7e1258f01234
bra/bs #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc58f01234
bra/bs #0x7,@0x12345678:32,0x1234+.+0xa ;6a301234567858f01234
bsr/bc #0x7,@er2,0x1234+.+6 ;7c205c701234
bsr/bc #0x7,@0xffffff12:8,0x1234+.+6 ;7e125c701234
bsr/bc #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc5c701234
bsr/bc #0x7,@0x12345678:32,0x1234+.+0xa ;6a30123456785c701234
bsr/bs #0x7,@er2,0x1234+.+6 ;7c205cf01234
bsr/bs #0x7,@0xffffff12:8,0x1234+.+6 ;7e125cf01234
bsr/bs #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc5cf01234
bsr/bs #0x7,@0x12345678:32,0x1234+.+0xa ;6a30123456785cf01234
bra r2l.b ;5925
bra r2.w ;5926
bra er2.l ;5927
bsr 0x12+.+2 ;5512
bsr 0x1234+.+4 ;5c001234
bsr r2l.b ;5d25
bsr r2.w ;5d26
bsr er2.l ;5d27
jmp @er2 ;5920
jmp @0x123456:24 ;5a123456
jmp @0x12345678:32 ;590812345678
jmp @@0x12 ;5b12
jmp @@0x234 ;598d
jsr @er2 ;5d20
jsr @0x123456:24 ;5e123456
jsr @0x12345678:32 ;5d0812345678
jsr @@0x12 ;5f12
jsr @@0x234 ;5d8d
rts ;5470
rts/l er3 ;5403
rts/l er1-er2 ;5412
rts/l er2-er4 ;5424
rts/l er3-er6 ;5436
trapa #0x3 ;5730
rte ;5670
rte/l er3 ;5603
rte/l er1-er2 ;5612
rte/l er2-er4 ;5624
rte/l er3-er6 ;5636
ldc.b #0x12:8,ccr ;0712
ldc.b r3h,ccr ;0303
ldc.w @er3,ccr ;01406930
ldc.w @er3+,ccr ;01406d30
ldc.w @(0x1234:16,er3),ccr ;01406f301234
ldc.w @(0x12345678:32,er3),ccr ;014078306b2012345678
ldc.w @0x1234:16,ccr ;01406b001234
ldc.w @0x12345678:32,ccr ;01406b2012345678
ldc.b #0x12:8,exr ;01410712
ldc.b r3h,exr ;0313
ldc.w @er3,exr ;01416930
ldc.w @er3+,exr ;01416d30
ldc.w @(0x1234:16,er3),exr ;01416f301234
ldc.w @(0x12345678:32,er3),exr ;014178306b2012345678
ldc.w @0x1234:16,exr ;01416b001234
ldc.w @0x12345678:32,exr ;01416b2012345678
stc.b ccr,r1h ;0201
stc.w ccr,@er1 ;01406990
stc.w ccr,@-er1 ;01406d90
stc.w ccr,@(0x1234:16,er1) ;01406f901234
stc.w ccr,@(0x12345678:32,er1) ;014078106ba012345678
stc.w ccr,@0x1234:16 ;01406b801234
stc.w ccr,@0x12345678:32 ;01406ba012345678
stc.b exr,r1h ;0211
stc.w exr,@er1 ;01416990
stc.w exr,@-er1 ;01416d90
stc.w exr,@(0x1234:16,er1) ;01416f901234
stc.w exr,@(0x12345678:32,er1) ;014178106ba012345678
stc.w exr,@0x1234:16 ;01416b801234
stc.w exr,@0x12345678:32 ;01416ba012345678
orc.b #0x12:8,ccr ;0412
orc.b #0x12:8,exr ;01410412
xorc.b #0x12:8,ccr ;0512
xorc.b #0x12:8,exr ;01410512
andc.b #0x12:8,ccr ;0612
andc.b #0x12:8,exr ;01410612
sleep ;0180
nop ;0000
.end
|
stsp/binutils-ia16
| 7,887
|
gdb/testsuite/gdb.disasm/t07_ari3.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;arith_3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
neg.b r1h ;1781
neg.b @er1 ;7d101780
neg.b @(0x3:2,er1) ;017768181780
neg.b @er1+ ;01746c181780
neg.b @-er1 ;01776c181780
neg.b @+er1 ;01756c181780
neg.b @er1- ;01766c181780
neg.b @(0x1234:16,er1) ;01746e1812341780
neg.b @(0x12345678:32,er1) ;78146a28123456781780
neg.b @(0x1234:16,r2l.b) ;01756e2812341780
neg.b @(0x1234:16,r2.w) ;01766e2812341780
neg.b @(0x1234:16,er2.l) ;01776e2812341780
neg.b @(0x12345678:32,r2l.b) ;78256a28123456781780
neg.b @(0x12345678:32,r2.w) ;78266a28123456781780
neg.b @(0x12345678:32,er2.l) ;78276a28123456781780
neg.b @0xffffff12:8 ;7f121780
neg.b @0x1234:16 ;6a1812341780
neg.b @0x12345678:32 ;6a38123456781780
neg.w r1 ;1791
neg.w @er1 ;7d901790
neg.w @(0x6:2,er1) ;015769181790
neg.w @er1+ ;01546d181790
neg.w @-er1 ;01576d181790
neg.w @+er1 ;01556d181790
neg.w @er1- ;01566d181790
neg.w @(0x1234:16,er1) ;01546f1812341790
neg.w @(0x12345678:32,er1) ;78146b28123456781790
neg.w @(0x1234:16,r2l.b) ;01556f2812341790
neg.w @(0x1234:16,r2.w) ;01566f2812341790
neg.w @(0x1234:16,er2.l) ;01576f2812341790
neg.w @(0x12345678:32,r2l.b) ;78256b28123456781790
neg.w @(0x12345678:32,r2.w) ;78266b28123456781790
neg.w @(0x12345678:32,er2.l) ;78276b28123456781790
neg.w @0x1234:16 ;6b1812341790
neg.w @0x12345678:32 ;6b38123456781790
neg.l er1 ;17b1
neg.l @er1 ;0104691817b0
neg.l @(0xc:2,er1) ;0107691817b0
neg.l @er1+ ;01046d1817b0
neg.l @-er1 ;01076d1817b0
neg.l @+er1 ;01056d1817b0
neg.l @er1- ;01066d1817b0
neg.l @(0x1234:16,er1) ;01046f18123417b0
neg.l @(0x12345678:32,er1) ;78946b281234567817b0
neg.l @(0x1234:16,r2l.b) ;01056f28123417b0
neg.l @(0x1234:16,r2.w) ;01066f28123417b0
neg.l @(0x1234:16,er2.l) ;01076f28123417b0
neg.l @(0x12345678:32,r2l.b) ;78a56b281234567817b0
neg.l @(0x12345678:32,r2.w) ;78a66b281234567817b0
neg.l @(0x12345678:32,er2.l) ;78a76b281234567817b0
neg.l @0x1234:16 ;01046b08123417b0
neg.l @0x12345678:32 ;01046b281234567817b0
tas @er1 ;01e07b1c
extu.w r1 ;1751
extu.w @er1 ;7d901750
extu.w @(0x6:2,er1) ;015769181750
extu.w @er1+ ;01546d181750
extu.w @-er1 ;01576d181750
extu.w @+er1 ;01556d181750
extu.w @er1- ;01566d181750
extu.w @(0x1234:16,er1) ;01546f1812341750
extu.w @(0x12345678:32,er1) ;78146b28123456781750
extu.w @(0x1234:16,r2l.b) ;01556f2812341750
extu.w @(0x1234:16,r2.w) ;01566f2812341750
extu.w @(0x1234:16,er2.l) ;01576f2812341750
extu.w @(0x12345678:32,r2l.b) ;78256b28123456781750
extu.w @(0x12345678:32,r2.w) ;78266b28123456781750
extu.w @(0x12345678:32,er2.l) ;78276b28123456781750
extu.w @0x1234:16 ;6b1812341750
extu.w @0x12345678:32 ;6b38123456781750
extu.l er1 ;1771
extu.l @er1 ;010469181770
extu.l @(0xc:2,er1) ;010769181770
extu.l @er1+ ;01046d181770
extu.l @-er1 ;01076d181770
extu.l @+er1 ;01056d181770
extu.l @er1- ;01066d181770
extu.l @(0x1234:16,er1) ;01046f1812341770
extu.l @(0x12345678:32,er1) ;78946b28123456781770
extu.l @(0x1234:16,r2l.b) ;01056f2812341770
extu.l @(0x1234:16,r2.w) ;01066f2812341770
extu.l @(0x1234:16,er2.l) ;01076f2812341770
extu.l @(0x12345678:32,r2l.b) ;78a56b28123456781770
extu.l @(0x12345678:32,r2.w) ;78a66b28123456781770
extu.l @(0x12345678:32,er2.l) ;78a76b28123456781770
extu.l @0x1234:16 ;01046b0812341770
extu.l @0x12345678:32 ;01046b28123456781770
extu.l #2,er1 ;1761
extu.l #2,@er1 ;010469181760
extu.l #2,@(0xc:2,er1) ;010769181760
extu.l #2,@er1+ ;01046d181760
extu.l #2,@-er1 ;01076d181760
extu.l #2,@+er1 ;01056d181760
extu.l #2,@er1- ;01066d181760
extu.l #2,@(0x1234:16,er1) ;01046f1812341760
extu.l #2,@(0x12345678:32,er1) ;78946b28123456781760
extu.l #2,@(0x1234:16,r2l.b) ;01056f2812341760
extu.l #2,@(0x1234:16,r2.w) ;01066f2812341760
extu.l #2,@(0x1234:16,er2.l) ;01076f2812341760
extu.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781760
extu.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781760
extu.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781760
extu.l #2,@0x1234:16 ;01046b0812341760
extu.l #2,@0x12345678:32 ;01046b28123456781760
exts.w r1 ;17d1
exts.w @er1 ;7d9017d0
exts.w @(0x6:2,er1) ;0157691817d0
exts.w @er1+ ;01546d1817d0
exts.w @-er1 ;01576d1817d0
exts.w @+er1 ;01556d1817d0
exts.w @er1- ;01566d1817d0
exts.w @(0x1234:16,er1) ;01546f18123417d0
exts.w @(0x12345678:32,er1) ;78146b281234567817d0
exts.w @(0x1234:16,r2l.b) ;01556f28123417d0
exts.w @(0x1234:16,r2.w) ;01566f28123417d0
exts.w @(0x1234:16,er2.l) ;01576f28123417d0
exts.w @(0x12345678:32,r2l.b) ;78256b281234567817d0
exts.w @(0x12345678:32,r2.w) ;78266b281234567817d0
exts.w @(0x12345678:32,er2.l) ;78276b281234567817d0
exts.w @0x1234:16 ;6b18123417d0
exts.w @0x12345678:32 ;6b381234567817d0
exts.l er1 ;17f1
exts.l @er1 ;0104691817f0
exts.l @(0xc:2,er1) ;0107691817f0
exts.l @er1+ ;01046d1817f0
exts.l @-er1 ;01076d1817f0
exts.l @+er1 ;01056d1817f0
exts.l @er1- ;01066d1817f0
exts.l @(0x1234:16,er1) ;01046f18123417f0
exts.l @(0x12345678:32,er1) ;78946b281234567817f0
exts.l @(0x1234:16,r2l.b) ;01056f28123417f0
exts.l @(0x1234:16,r2.w) ;01066f28123417f0
exts.l @(0x1234:16,er2.l) ;01076f28123417f0
exts.l @(0x12345678:32,r2l.b) ;78a56b281234567817f0
exts.l @(0x12345678:32,r2.w) ;78a66b281234567817f0
exts.l @(0x12345678:32,er2.l) ;78a76b281234567817f0
exts.l @0x1234:16 ;01046b08123417f0
exts.l @0x12345678:32 ;01046b281234567817f0
exts.l #2,er1 ;17e1
exts.l #2,@er1 ;0104691817e0
exts.l #2,@(0xc:2,er1) ;0107691817e0
exts.l #2,@er1+ ;01046d1817e0
exts.l #2,@-er1 ;01076d1817e0
exts.l #2,@+er1 ;01056d1817e0
exts.l #2,@er1- ;01066d1817e0
exts.l #2,@(0x1234:16,er1) ;01046f18123417e0
exts.l #2,@(0x12345678:32,er1) ;78946b281234567817e0
exts.l #2,@(0x1234:16,r2l.b) ;01056f28123417e0
exts.l #2,@(0x1234:16,r2.w) ;01066f28123417e0
exts.l #2,@(0x1234:16,er2.l) ;01076f28123417e0
exts.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567817e0
exts.l #2,@(0x12345678:32,r2.w) ;78a66b281234567817e0
exts.l #2,@(0x12345678:32,er2.l) ;78a76b281234567817e0
exts.l #2,@0x1234:16 ;01046b08123417e0
exts.l #2,@0x12345678:32 ;01046b281234567817e0
.end
|
stsp/binutils-ia16
| 65,202
|
gdb/testsuite/gdb.disasm/t10_and.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;log_1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
and.b #0x12:8,r1h ;e112
and.b #0x12:8,@er1 ;7d10e012
and.b #0x12:8,@(0x3:2,er1) ;01776818e012
and.b #0x12:8,@er1+ ;01746c18e012
and.b #0x12:8,@-er1 ;01776c18e012
and.b #0x12:8,@+er1 ;01756c18e012
and.b #0x12:8,@er1- ;01766c18e012
and.b #0x12:8,@(0x1234:16,er1) ;01746e181234e012
and.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678e012
and.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234e012
and.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234e012
and.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234e012
and.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678e012
and.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678e012
and.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678e012
and.b #0x12:8,@0xffffff12:8 ;7f12e012
and.b #0x12:8,@0x1234:16 ;6a181234e012
and.b #0x12:8,@0x12345678:32 ;6a3812345678e012
and.b r3h,r1h ;1631
and.b r3h,@er1 ;7d101630
and.b r3h,@(0x3:2,er1) ;01793163
and.b r3h,@er1+ ;01798163
and.b r3h,@-er1 ;0179b163
and.b r3h,@+er1 ;01799163
and.b r3h,@er1- ;0179a163
and.b r3h,@(0x1234:16,er1) ;0179c1631234
and.b r3h,@(0x12345678:32,er1) ;0179c96312345678
and.b r3h,@(0x1234:16,r2l.b) ;0179d2631234
and.b r3h,@(0x1234:16,r2.w) ;0179e2631234
and.b r3h,@(0x1234:16,er2.l) ;0179f2631234
and.b r3h,@(0x12345678:32,r2l.b) ;0179da6312345678
and.b r3h,@(0x12345678:32,r2.w) ;0179ea6312345678
and.b r3h,@(0x12345678:32,er2.l) ;0179fa6312345678
and.b r3h,@0xffffff12:8 ;7f121630
and.b r3h,@0x1234:16 ;6a1812341630
and.b r3h,@0x12345678:32 ;6a38123456781630
and.b @er3,r1h ;7c301601
and.b @(0x3:2,er3),r1h ;017a3361
and.b @er3+,r1h ;017a8361
and.b @-er3,r1h ;017ab361
and.b @+er3,r1h ;017a9361
and.b @er3-,r1h ;017aa361
and.b @(0x1234:16,er1),r1h ;017ac1611234
and.b @(0x12345678:32,er1),r1h ;017ac96112345678
and.b @(0x1234:16,r2l.b),r1h ;017ad2611234
and.b @(0x1234:16,r2.w),r1h ;017ae2611234
and.b @(0x1234:16,er2.l),r1h ;017af2611234
and.b @(0x12345678:32,r2l.b),r1h ;017ada6112345678
and.b @(0x12345678:32,r2.w),r1h ;017aea6112345678
and.b @(0x12345678:32,er2.l),r1h ;017afa6112345678
and.b @0xffffff12:8,r1h ;7e121601
and.b @0x1234:16,r1h ;6a1012341601
and.b @0x12345678:32,r1h ;6a30123456781601
and.b @er3,@er1 ;7c350160
and.b @er3,@(3:2,er1) ;7c353160
and.b @er3,@-er1 ;7c35b160
and.b @er3,@er1+ ;7c358160
and.b @er3,@er1- ;7c35a160
and.b @er3,@+er1 ;7c359160
and.b @er3,@(0xffff9abc:16,er1) ;7c35c1609abc
and.b @er3,@(0x9abcdef0:32,er1) ;7c35c9609abcdef0
and.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2609abc
and.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2609abc
and.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2609abc
and.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da609abcdef0
and.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea609abcdef0
and.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa609abcdef0
and.b @er3,@0xffff9abc:16 ;7c3540609abc
and.b @er3,@0x9abcdef0:32 ;7c3548609abcdef0
and.b @-er3,@er1 ;01776c3c0160
and.b @-er3,@(3:2,er1) ;01776c3c3160
and.b @-er3,@-er1 ;01776c3cb160
and.b @-er3,@er1+ ;01776c3c8160
and.b @-er3,@er1- ;01776c3ca160
and.b @-er3,@+er1 ;01776c3c9160
and.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1609abc
and.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9609abcdef0
and.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2609abc
and.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2609abc
and.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2609abc
and.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda609abcdef0
and.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea609abcdef0
and.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa609abcdef0
and.b @-er3,@0xffff9abc:16 ;01776c3c40609abc
and.b @-er3,@0x9abcdef0:32 ;01776c3c48609abcdef0
and.b @er3+,@er1 ;01746c3c0160
and.b @er3+,@(3:2,er1) ;01746c3c3160
and.b @er3+,@-er1 ;01746c3cb160
and.b @er3+,@er1+ ;01746c3c8160
and.b @er3+,@er1- ;01746c3ca160
and.b @er3+,@+er1 ;01746c3c9160
and.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1609abc
and.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9609abcdef0
and.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2609abc
and.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2609abc
and.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2609abc
and.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda609abcdef0
and.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea609abcdef0
and.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa609abcdef0
and.b @er3+,@0xffff9abc:16 ;01746c3c40609abc
and.b @er3+,@0x9abcdef0:32 ;01746c3c48609abcdef0
and.b @er3-,@er1 ;01766c3c0160
and.b @er3-,@(3:2,er1) ;01766c3c3160
and.b @er3-,@-er1 ;01766c3cb160
and.b @er3-,@er1+ ;01766c3c8160
and.b @er3-,@er1- ;01766c3ca160
and.b @er3-,@+er1 ;01766c3c9160
and.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1609abc
and.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9609abcdef0
and.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2609abc
and.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2609abc
and.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2609abc
and.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda609abcdef0
and.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea609abcdef0
and.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa609abcdef0
and.b @er3-,@0xffff9abc:16 ;01766c3c40609abc
and.b @er3-,@0x9abcdef0:32 ;01766c3c48609abcdef0
and.b @+er3,@er1 ;01756c3c0160
and.b @+er3,@(3:2,er1) ;01756c3c3160
and.b @+er3,@-er1 ;01756c3cb160
and.b @+er3,@er1+ ;01756c3c8160
and.b @+er3,@er1- ;01756c3ca160
and.b @+er3,@+er1 ;01756c3c9160
and.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1609abc
and.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9609abcdef0
and.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2609abc
and.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2609abc
and.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2609abc
and.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda609abcdef0
and.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea609abcdef0
and.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa609abcdef0
and.b @+er3,@0xffff9abc:16 ;01756c3c40609abc
and.b @+er3,@0x9abcdef0:32 ;01756c3c48609abcdef0
and.b @(0x1234:16,er3),@er1 ;01746e3c12340160
and.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343160
and.b @(0x1234:16,er3),@-er1 ;01746e3c1234b160
and.b @(0x1234:16,er3),@er1+ ;01746e3c12348160
and.b @(0x1234:16,er3),@er1- ;01746e3c1234a160
and.b @(0x1234:16,er3),@+er1 ;01746e3c12349160
and.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1609abc
and.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9609abcdef0
and.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2609abc
and.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2609abc
and.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2609abc
and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da609abcdef0
and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea609abcdef0
and.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa609abcdef0
and.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440609abc
and.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448609abcdef0
and.b @(0x12345678:32,er3),@er1 ;78346a2c123456780160
and.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783160
and.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b160
and.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788160
and.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a160
and.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789160
and.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1609abc
and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9609abcdef0
and.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2609abc
and.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2609abc
and.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2609abc
and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da609abcdef0
and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea609abcdef0
and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa609abcdef0
and.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840609abc
and.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848609abcdef0
and.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340160
and.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343160
and.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b160
and.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348160
and.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a160
and.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349160
and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1609abc
and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9609abcdef0
and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2609abc
and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2609abc
and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2609abc
and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da609abcdef0
and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea609abcdef0
and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa609abcdef0
and.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440609abc
and.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448609abcdef0
and.b @(0x1234:16,r3.w),@er1 ;01766e3c12340160
and.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343160
and.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b160
and.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348160
and.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a160
and.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349160
and.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1609abc
and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9609abcdef0
and.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2609abc
and.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2609abc
and.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2609abc
and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da609abcdef0
and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea609abcdef0
and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa609abcdef0
and.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440609abc
and.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448609abcdef0
and.b @(0x1234:16,er3.l),@er1 ;01776e3c12340160
and.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343160
and.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b160
and.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348160
and.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a160
and.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349160
and.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1609abc
and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9609abcdef0
and.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2609abc
and.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2609abc
and.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2609abc
and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da609abcdef0
and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea609abcdef0
and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa609abcdef0
and.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440609abc
and.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448609abcdef0
and.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780160
and.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783160
and.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b160
and.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788160
and.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a160
and.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789160
and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1609abc
and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9609abcdef0
and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2609abc
and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2609abc
and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2609abc
and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da609abcdef0
and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea609abcdef0
and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa609abcdef0
and.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840609abc
and.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848609abcdef0
and.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780160
and.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783160
and.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b160
and.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788160
and.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a160
and.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789160
and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1609abc
and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9609abcdef0
and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2609abc
and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2609abc
and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2609abc
and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da609abcdef0
and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea609abcdef0
and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa609abcdef0
and.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840609abc
and.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848609abcdef0
and.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780160
and.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783160
and.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b160
and.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788160
and.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a160
and.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789160
and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1609abc
and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9609abcdef0
and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2609abc
and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2609abc
and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2609abc
and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da609abcdef0
and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea609abcdef0
and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa609abcdef0
and.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840609abc
and.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848609abcdef0
and.b @0x1234:16,@er1 ;6a1512340160
and.b @0x1234:16,@(3:2,er1) ;6a1512343160
and.b @0x1234:16,@-er1 ;6a151234b160
and.b @0x1234:16,@er1+ ;6a1512348160
and.b @0x1234:16,@er1- ;6a151234a160
and.b @0x1234:16,@+er1 ;6a1512349160
and.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1609abc
and.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9609abcdef0
and.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2609abc
and.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2609abc
and.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2609abc
and.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da609abcdef0
and.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea609abcdef0
and.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa609abcdef0
and.b @0x1234:16,@0xffff9abc:16 ;6a15123440609abc
and.b @0x1234:16,@0x9abcdef0:32 ;6a15123448609abcdef0
and.b @0x12345678:32,@er1 ;6a35123456780160
and.b @0x12345678:32,@(3:2,er1) ;6a35123456783160
and.b @0x12345678:32,@-er1 ;6a3512345678b160
and.b @0x12345678:32,@er1+ ;6a35123456788160
and.b @0x12345678:32,@er1- ;6a3512345678a160
and.b @0x12345678:32,@+er1 ;6a35123456789160
and.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1609abc
and.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9609abcdef0
and.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2609abc
and.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2609abc
and.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2609abc
and.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da609abcdef0
and.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea609abcdef0
and.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa609abcdef0
and.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840609abc
and.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848609abcdef0
and.w #0x1234:16,r1 ;79611234
and.w #0x1234:16,@er1 ;015e01601234
and.w #0x1234:16,@(0x6:2,er1) ;015e31601234
and.w #0x1234:16,@er1+ ;015e81601234
and.w #0x1234:16,@-er1 ;015eb1601234
and.w #0x1234:16,@+er1 ;015e91601234
and.w #0x1234:16,@er1- ;015ea1601234
and.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1609abc1234
and.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9609abcdef01234
and.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2609abc1234
and.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2609abc1234
and.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2609abc1234
and.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda609abcdef01234
and.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea609abcdef01234
and.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa609abcdef01234
and.w #0x1234:16,@0xffff9abc:16 ;015e40609abc1234
and.w #0x1234:16,@0x9abcdef0:32 ;015e48609abcdef01234
and.w r3,r1 ;6631
and.w r3,@er1 ;7d906630
and.w r3,@(0x6:2,er1) ;01593163
and.w r3,@er1+ ;01598163
and.w r3,@-er1 ;0159b163
and.w r3,@+er1 ;01599163
and.w r3,@er1- ;0159a163
and.w r3,@(0x1234:16,er1) ;0159c1631234
and.w r3,@(0x12345678:32,er1) ;0159c96312345678
and.w r3,@(0x1234:16,r2l.b) ;0159d2631234
and.w r3,@(0x1234:16,r2.w) ;0159e2631234
and.w r3,@(0x1234:16,er2.l) ;0159f2631234
and.w r3,@(0x12345678:32,r2l.b) ;0159da6312345678
and.w r3,@(0x12345678:32,r2.w) ;0159ea6312345678
and.w r3,@(0x12345678:32,er2.l) ;0159fa6312345678
and.w r3,@0x1234:16 ;6b1812346630
and.w r3,@0x12345678:32 ;6b38123456786630
and.w @er3,r1 ;7cb06601
and.w @(0x6:2,er3),r1 ;015a3361
and.w @er3+,r1 ;015a8361
and.w @-er3,r1 ;015ab361
and.w @+er3,r1 ;015a9361
and.w @er3-,r1 ;015aa361
and.w @(0x1234:16,er1),r1 ;015ac1611234
and.w @(0x12345678:32,er1),r1 ;015ac96112345678
and.w @(0x1234:16,r2l.b),r1 ;015ad2611234
and.w @(0x1234:16,r2.w),r1 ;015ae2611234
and.w @(0x1234:16,er2.l),r1 ;015af2611234
and.w @(0x12345678:32,r2l.b),r1 ;015ada6112345678
and.w @(0x12345678:32,r2.w),r1 ;015aea6112345678
and.w @(0x12345678:32,er2.l),r1 ;015afa6112345678
and.w @0x1234:16,r1 ;6b1012346601
and.w @0x12345678:32,r1 ;6b30123456786601
and.w @er3,@er1 ;7cb50160
and.w @er3,@(6:2,er1) ;7cb53160
and.w @er3,@-er1 ;7cb5b160
and.w @er3,@er1+ ;7cb58160
and.w @er3,@er1- ;7cb5a160
and.w @er3,@+er1 ;7cb59160
and.w @er3,@(0xffff9abc:16,er1) ;7cb5c1609abc
and.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9609abcdef0
and.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2609abc
and.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2609abc
and.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2609abc
and.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da609abcdef0
and.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea609abcdef0
and.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa609abcdef0
and.w @er3,@0xffff9abc:16 ;7cb540609abc
and.w @er3,@0x9abcdef0:32 ;7cb548609abcdef0
and.w @-er3,@er1 ;01576d3c0160
and.w @-er3,@(6:2,er1) ;01576d3c3160
and.w @-er3,@-er1 ;01576d3cb160
and.w @-er3,@er1+ ;01576d3c8160
and.w @-er3,@er1- ;01576d3ca160
and.w @-er3,@+er1 ;01576d3c9160
and.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1609abc
and.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9609abcdef0
and.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2609abc
and.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2609abc
and.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2609abc
and.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda609abcdef0
and.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea609abcdef0
and.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa609abcdef0
and.w @-er3,@0xffff9abc:16 ;01576d3c40609abc
and.w @-er3,@0x9abcdef0:32 ;01576d3c48609abcdef0
and.w @er3+,@er1 ;01546d3c0160
and.w @er3+,@(6:2,er1) ;01546d3c3160
and.w @er3+,@-er1 ;01546d3cb160
and.w @er3+,@er1+ ;01546d3c8160
and.w @er3+,@er1- ;01546d3ca160
and.w @er3+,@+er1 ;01546d3c9160
and.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1609abc
and.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9609abcdef0
and.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2609abc
and.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2609abc
and.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2609abc
and.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda609abcdef0
and.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea609abcdef0
and.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa609abcdef0
and.w @er3+,@0xffff9abc:16 ;01546d3c40609abc
and.w @er3+,@0x9abcdef0:32 ;01546d3c48609abcdef0
and.w @er3-,@er1 ;01566d3c0160
and.w @er3-,@(6:2,er1) ;01566d3c3160
and.w @er3-,@-er1 ;01566d3cb160
and.w @er3-,@er1+ ;01566d3c8160
and.w @er3-,@er1- ;01566d3ca160
and.w @er3-,@+er1 ;01566d3c9160
and.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1609abc
and.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9609abcdef0
and.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2609abc
and.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2609abc
and.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2609abc
and.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda609abcdef0
and.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea609abcdef0
and.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa609abcdef0
and.w @er3-,@0xffff9abc:16 ;01566d3c40609abc
and.w @er3-,@0x9abcdef0:32 ;01566d3c48609abcdef0
and.w @+er3,@er1 ;01556d3c0160
and.w @+er3,@(6:2,er1) ;01556d3c3160
and.w @+er3,@-er1 ;01556d3cb160
and.w @+er3,@er1+ ;01556d3c8160
and.w @+er3,@er1- ;01556d3ca160
and.w @+er3,@+er1 ;01556d3c9160
and.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1609abc
and.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9609abcdef0
and.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2609abc
and.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2609abc
and.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2609abc
and.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda609abcdef0
and.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea609abcdef0
and.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa609abcdef0
and.w @+er3,@0xffff9abc:16 ;01556d3c40609abc
and.w @+er3,@0x9abcdef0:32 ;01556d3c48609abcdef0
and.w @(0x1234:16,er3),@er1 ;01546f3c12340160
and.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343160
and.w @(0x1234:16,er3),@-er1 ;01546f3c1234b160
and.w @(0x1234:16,er3),@er1+ ;01546f3c12348160
and.w @(0x1234:16,er3),@er1- ;01546f3c1234a160
and.w @(0x1234:16,er3),@+er1 ;01546f3c12349160
and.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1609abc
and.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9609abcdef0
and.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2609abc
and.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2609abc
and.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2609abc
and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da609abcdef0
and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea609abcdef0
and.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa609abcdef0
and.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440609abc
and.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448609abcdef0
and.w @(0x12345678:32,er3),@er1 ;78346b2c123456780160
and.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783160
and.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b160
and.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788160
and.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a160
and.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789160
and.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1609abc
and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9609abcdef0
and.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2609abc
and.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2609abc
and.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2609abc
and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da609abcdef0
and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea609abcdef0
and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa609abcdef0
and.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840609abc
and.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848609abcdef0
and.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340160
and.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343160
and.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b160
and.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348160
and.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a160
and.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349160
and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1609abc
and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9609abcdef0
and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2609abc
and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2609abc
and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2609abc
and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da609abcdef0
and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea609abcdef0
and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa609abcdef0
and.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440609abc
and.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448609abcdef0
and.w @(0x1234:16,r3.w),@er1 ;01566f3c12340160
and.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343160
and.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b160
and.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348160
and.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a160
and.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349160
and.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1609abc
and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9609abcdef0
and.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2609abc
and.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2609abc
and.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2609abc
and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da609abcdef0
and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea609abcdef0
and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa609abcdef0
and.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440609abc
and.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448609abcdef0
and.w @(0x1234:16,er3.l),@er1 ;01576f3c12340160
and.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343160
and.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b160
and.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348160
and.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a160
and.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349160
and.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1609abc
and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9609abcdef0
and.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2609abc
and.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2609abc
and.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2609abc
and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da609abcdef0
and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea609abcdef0
and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa609abcdef0
and.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440609abc
and.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448609abcdef0
and.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780160
and.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783160
and.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b160
and.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788160
and.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a160
and.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789160
and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1609abc
and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9609abcdef0
and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2609abc
and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2609abc
and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2609abc
and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da609abcdef0
and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea609abcdef0
and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa609abcdef0
and.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840609abc
and.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848609abcdef0
and.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780160
and.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783160
and.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b160
and.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788160
and.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a160
and.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789160
and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1609abc
and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9609abcdef0
and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2609abc
and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2609abc
and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2609abc
and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da609abcdef0
and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea609abcdef0
and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa609abcdef0
and.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840609abc
and.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848609abcdef0
and.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780160
and.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783160
and.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b160
and.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788160
and.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a160
and.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789160
and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1609abc
and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9609abcdef0
and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2609abc
and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2609abc
and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2609abc
and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da609abcdef0
and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea609abcdef0
and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa609abcdef0
and.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840609abc
and.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848609abcdef0
and.w @0x1234:16,@er1 ;6b1512340160
and.w @0x1234:16,@(6:2,er1) ;6b1512343160
and.w @0x1234:16,@-er1 ;6b151234b160
and.w @0x1234:16,@er1+ ;6b1512348160
and.w @0x1234:16,@er1- ;6b151234a160
and.w @0x1234:16,@+er1 ;6b1512349160
and.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1609abc
and.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9609abcdef0
and.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2609abc
and.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2609abc
and.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2609abc
and.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da609abcdef0
and.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea609abcdef0
and.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa609abcdef0
and.w @0x1234:16,@0xffff9abc:16 ;6b15123440609abc
and.w @0x1234:16,@0x9abcdef0:32 ;6b15123448609abcdef0
and.w @0x12345678:32,@er1 ;6b35123456780160
and.w @0x12345678:32,@(6:2,er1) ;6b35123456783160
and.w @0x12345678:32,@-er1 ;6b3512345678b160
and.w @0x12345678:32,@er1+ ;6b35123456788160
and.w @0x12345678:32,@er1- ;6b3512345678a160
and.w @0x12345678:32,@+er1 ;6b35123456789160
and.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1609abc
and.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9609abcdef0
and.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2609abc
and.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2609abc
and.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2609abc
and.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da609abcdef0
and.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea609abcdef0
and.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa609abcdef0
and.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840609abc
and.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848609abcdef0
and.l #0x12345678:32,er1 ;7a6112345678
and.l #0x1234:16,er1 ;7a691234
and.l #0x12345678:32,@er1 ;010e016812345678
and.l #0x12345678:32,@(0xc:2,er1) ;010e316812345678
and.l #0x12345678:32,@er1+ ;010e816812345678
and.l #0x12345678:32,@-er1 ;010eb16812345678
and.l #0x12345678:32,@+er1 ;010e916812345678
and.l #0x12345678:32,@er1- ;010ea16812345678
and.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1689abc12345678
and.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9689abcdef012345678
and.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2689abc12345678
and.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2689abc12345678
and.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2689abc12345678
and.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda689abcdef012345678
and.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea689abcdef012345678
and.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa689abcdef012345678
and.l #0x12345678:32,@0xffff9abc:16 ;010e40689abc12345678
and.l #0x12345678:32,@0x9abcdef0:32 ;010e48689abcdef012345678
and.l #0x1234:16,@er1 ;010e01601234
and.l #0x1234:16,@(0xc:2,er1) ;010e31601234
and.l #0x1234:16,@er1+ ;010e81601234
and.l #0x1234:16,@-er1 ;010eb1601234
and.l #0x1234:16,@+er1 ;010e91601234
and.l #0x1234:16,@er1- ;010ea1601234
and.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1609abc1234
and.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9609abcdef01234
and.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2609abc1234
and.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2609abc1234
and.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2609abc1234
and.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda609abcdef01234
and.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea609abcdef01234
and.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa609abcdef01234
and.l #0x1234:16,@0xffff9abc:16 ;010e40609abc1234
and.l #0x1234:16,@0x9abcdef0:32 ;010e48609abcdef01234
and.l er3,er1 ;01f06631
and.l er3,@er1 ;01090163
and.l er3,@(0xc:2,er1) ;01093163
and.l er3,@er1+ ;01098163
and.l er3,@-er1 ;0109b163
and.l er3,@+er1 ;01099163
and.l er3,@er1- ;0109a163
and.l er3,@(0x1234:16,er1) ;0109c1631234
and.l er3,@(0x12345678:32,er1) ;0109c96312345678
and.l er3,@(0x1234:16,r2l.b) ;0109d2631234
and.l er3,@(0x1234:16,r2.w) ;0109e2631234
and.l er3,@(0x1234:16,er2.l) ;0109f2631234
and.l er3,@(0x12345678:32,r2l.b) ;0109da6312345678
and.l er3,@(0x12345678:32,r2.w) ;0109ea6312345678
and.l er3,@(0x12345678:32,er2.l) ;0109fa6312345678
and.l er3,@0x1234:16 ;010940631234
and.l er3,@0x12345678:32 ;0109486312345678
and.l @er3,er1 ;010a0361
and.l @(0xc:2,er3),er1 ;010a3361
and.l @er3+,er1 ;010a8361
and.l @-er3,er1 ;010ab361
and.l @+er3,er1 ;010a9361
and.l @er3-,er1 ;010aa361
and.l @(0x1234:16,er1),er1 ;010ac1611234
and.l @(0x12345678:32,er1),er1 ;010ac96112345678
and.l @(0x1234:16,r2l.b),er1 ;010ad2611234
and.l @(0x1234:16,r2.w),er1 ;010ae2611234
and.l @(0x1234:16,er2.l),er1 ;010af2611234
and.l @(0x12345678:32,r2l.b),er1 ;010ada6112345678
and.l @(0x12345678:32,r2.w),er1 ;010aea6112345678
and.l @(0x12345678:32,er2.l),er1 ;010afa6112345678
and.l @0x1234:16,er1 ;010a40611234
and.l @0x12345678:32,er1 ;010a486112345678
and.l @er3,@er1 ;0104693c0160
and.l @er3,@(0xc:2,er1) ;0104693c3160
and.l @er3,@-er1 ;0104693cb160
and.l @er3,@er1+ ;0104693c8160
and.l @er3,@er1- ;0104693ca160
and.l @er3,@+er1 ;0104693c9160
and.l @er3,@(0xffff9abc:16,er1) ;0104693cc1609abc
and.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9609abcdef0
and.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2609abc
and.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2609abc
and.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2609abc
and.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda609abcdef0
and.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea609abcdef0
and.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa609abcdef0
and.l @er3,@0xffff9abc:16 ;0104693c40609abc
and.l @er3,@0x9abcdef0:32 ;0104693c48609abcdef0
and.l @(0xc:2,er3),@er1 ;0107693c0160
and.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3160
and.l @(0xc:2,er3),@-er1 ;0107693cb160
and.l @(0xc:2,er3),@er1+ ;0107693c8160
and.l @(0xc:2,er3),@er1- ;0107693ca160
and.l @(0xc:2,er3),@+er1 ;0107693c9160
and.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1609abc
and.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9609abcdef0
and.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2609abc
and.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2609abc
and.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2609abc
and.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda609abcdef0
and.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea609abcdef0
and.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa609abcdef0
and.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40609abc
and.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48609abcdef0
and.l @-er3,@er1 ;01076d3c0160
and.l @-er3,@(0xc:2,er1) ;01076d3c3160
and.l @-er3,@-er1 ;01076d3cb160
and.l @-er3,@er1+ ;01076d3c8160
and.l @-er3,@er1- ;01076d3ca160
and.l @-er3,@+er1 ;01076d3c9160
and.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1609abc
and.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9609abcdef0
and.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2609abc
and.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2609abc
and.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2609abc
and.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda609abcdef0
and.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea609abcdef0
and.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa609abcdef0
and.l @-er3,@0xffff9abc:16 ;01076d3c40609abc
and.l @-er3,@0x9abcdef0:32 ;01076d3c48609abcdef0
and.l @er3+,@er1 ;01046d3c0160
and.l @er3+,@(0xc:2,er1) ;01046d3c3160
and.l @er3+,@-er1 ;01046d3cb160
and.l @er3+,@er1+ ;01046d3c8160
and.l @er3+,@er1- ;01046d3ca160
and.l @er3+,@+er1 ;01046d3c9160
and.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1609abc
and.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9609abcdef0
and.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2609abc
and.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2609abc
and.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2609abc
and.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda609abcdef0
and.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea609abcdef0
and.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa609abcdef0
and.l @er3+,@0xffff9abc:16 ;01046d3c40609abc
and.l @er3+,@0x9abcdef0:32 ;01046d3c48609abcdef0
and.l @er3-,@er1 ;01066d3c0160
and.l @er3-,@(0xc:2,er1) ;01066d3c3160
and.l @er3-,@-er1 ;01066d3cb160
and.l @er3-,@er1+ ;01066d3c8160
and.l @er3-,@er1- ;01066d3ca160
and.l @er3-,@+er1 ;01066d3c9160
and.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1609abc
and.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9609abcdef0
and.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2609abc
and.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2609abc
and.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2609abc
and.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda609abcdef0
and.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea609abcdef0
and.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa609abcdef0
and.l @er3-,@0xffff9abc:16 ;01066d3c40609abc
and.l @er3-,@0x9abcdef0:32 ;01066d3c48609abcdef0
and.l @+er3,@er1 ;01056d3c0160
and.l @+er3,@(0xc:2,er1) ;01056d3c3160
and.l @+er3,@-er1 ;01056d3cb160
and.l @+er3,@er1+ ;01056d3c8160
and.l @+er3,@er1- ;01056d3ca160
and.l @+er3,@+er1 ;01056d3c9160
and.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1609abc
and.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9609abcdef0
and.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2609abc
and.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2609abc
and.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2609abc
and.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda609abcdef0
and.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea609abcdef0
and.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa609abcdef0
and.l @+er3,@0xffff9abc:16 ;01056d3c40609abc
and.l @+er3,@0x9abcdef0:32 ;01056d3c48609abcdef0
and.l @(0x1234:16,er3),@er1 ;01046f3c12340160
and.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343160
and.l @(0x1234:16,er3),@-er1 ;01046f3c1234b160
and.l @(0x1234:16,er3),@er1+ ;01046f3c12348160
and.l @(0x1234:16,er3),@er1- ;01046f3c1234a160
and.l @(0x1234:16,er3),@+er1 ;01046f3c12349160
and.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1609abc
and.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9609abcdef0
and.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2609abc
and.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2609abc
and.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2609abc
and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da609abcdef0
and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea609abcdef0
and.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa609abcdef0
and.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440609abc
and.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448609abcdef0
and.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780160
and.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783160
and.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b160
and.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788160
and.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a160
and.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789160
and.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1609abc
and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9609abcdef0
and.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2609abc
and.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2609abc
and.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2609abc
and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da609abcdef0
and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea609abcdef0
and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa609abcdef0
and.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840609abc
and.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848609abcdef0
and.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340160
and.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343160
and.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b160
and.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348160
and.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a160
and.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349160
and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1609abc
and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9609abcdef0
and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2609abc
and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2609abc
and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2609abc
and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da609abcdef0
and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea609abcdef0
and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa609abcdef0
and.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440609abc
and.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448609abcdef0
and.l @(0x1234:16,r3.w),@er1 ;01066f3c12340160
and.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343160
and.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b160
and.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348160
and.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a160
and.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349160
and.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1609abc
and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9609abcdef0
and.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2609abc
and.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2609abc
and.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2609abc
and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da609abcdef0
and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea609abcdef0
and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa609abcdef0
and.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440609abc
and.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448609abcdef0
and.l @(0x1234:16,er3.l),@er1 ;01076f3c12340160
and.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343160
and.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b160
and.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348160
and.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a160
and.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349160
and.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1609abc
and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9609abcdef0
and.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2609abc
and.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2609abc
and.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2609abc
and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da609abcdef0
and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea609abcdef0
and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa609abcdef0
and.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440609abc
and.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448609abcdef0
and.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780160
and.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783160
and.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b160
and.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788160
and.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a160
and.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789160
and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1609abc
and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9609abcdef0
and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2609abc
and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2609abc
and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2609abc
and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da609abcdef0
and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea609abcdef0
and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa609abcdef0
and.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840609abc
and.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848609abcdef0
and.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780160
and.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783160
and.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b160
and.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788160
and.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a160
and.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789160
and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1609abc
and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9609abcdef0
and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2609abc
and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2609abc
and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2609abc
and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da609abcdef0
and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea609abcdef0
and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa609abcdef0
and.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840609abc
and.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848609abcdef0
and.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780160
and.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783160
and.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b160
and.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788160
and.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a160
and.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789160
and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1609abc
and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9609abcdef0
and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2609abc
and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2609abc
and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2609abc
and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da609abcdef0
and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea609abcdef0
and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa609abcdef0
and.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840609abc
and.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848609abcdef0
and.l @0x1234:16,@er1 ;01046b0c12340160
and.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343160
and.l @0x1234:16,@-er1 ;01046b0c1234b160
and.l @0x1234:16,@er1+ ;01046b0c12348160
and.l @0x1234:16,@er1- ;01046b0c1234a160
and.l @0x1234:16,@+er1 ;01046b0c12349160
and.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1609abc
and.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9609abcdef0
and.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2609abc
and.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2609abc
and.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2609abc
and.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da609abcdef0
and.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea609abcdef0
and.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa609abcdef0
and.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440609abc
and.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448609abcdef0
and.l @0x12345678:32,@er1 ;01046b2c123456780160
and.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783160
and.l @0x12345678:32,@-er1 ;01046b2c12345678b160
and.l @0x12345678:32,@er1+ ;01046b2c123456788160
and.l @0x12345678:32,@er1- ;01046b2c12345678a160
and.l @0x12345678:32,@+er1 ;01046b2c123456789160
and.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1609abc
and.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9609abcdef0
and.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2609abc
and.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2609abc
and.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2609abc
and.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da609abcdef0
and.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea609abcdef0
and.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa609abcdef0
and.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840609abc
and.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848609abcdef0
.end
|
stsp/binutils-ia16
| 65,197
|
gdb/testsuite/gdb.disasm/t09_xor.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;log_1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
xor.b #0x12:8,r1h ;d112
xor.b #0x12:8,@er1 ;7d10d012
xor.b #0x12:8,@(0x3:2,er1) ;01776818d012
xor.b #0x12:8,@er1+ ;01746c18d012
xor.b #0x12:8,@-er1 ;01776c18d012
xor.b #0x12:8,@+er1 ;01756c18d012
xor.b #0x12:8,@er1- ;01766c18d012
xor.b #0x12:8,@(0x1234:16,er1) ;01746e181234d012
xor.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678d012
xor.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234d012
xor.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234d012
xor.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234d012
xor.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678d012
xor.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678d012
xor.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678d012
xor.b #0x12:8,@0xffffff12:8 ;7f12d012
xor.b #0x12:8,@0x1234:16 ;6a181234d012
xor.b #0x12:8,@0x12345678:32 ;6a3812345678d012
xor.b r3h,r1h ;1531
xor.b r3h,@er1 ;7d101530
xor.b r3h,@(0x3:2,er1) ;01793153
xor.b r3h,@er1+ ;01798153
xor.b r3h,@-er1 ;0179b153
xor.b r3h,@+er1 ;01799153
xor.b r3h,@er1- ;0179a153
xor.b r3h,@(0x1234:16,er1) ;0179c1531234
xor.b r3h,@(0x12345678:32,er1) ;0179c95312345678
xor.b r3h,@(0x1234:16,r2l.b) ;0179d2531234
xor.b r3h,@(0x1234:16,r2.w) ;0179e2531234
xor.b r3h,@(0x1234:16,er2.l) ;0179f2531234
xor.b r3h,@(0x12345678:32,r2l.b) ;0179da5312345678
xor.b r3h,@(0x12345678:32,r2.w) ;0179ea5312345678
xor.b r3h,@(0x12345678:32,er2.l) ;0179fa5312345678
xor.b r3h,@0xffffff12:8 ;7f121530
xor.b r3h,@0x1234:16 ;6a1812341530
xor.b r3h,@0x12345678:32 ;6a38123456781530
xor.b @er3,r1h ;7c301501
xor.b @(0x3:2,er3),r1h ;017a3351
xor.b @er3+,r1h ;017a8351
xor.b @-er3,r1h ;017ab351
xor.b @+er3,r1h ;017a9351
xor.b @er3-,r1h ;017aa351
xor.b @(0x1234:16,er1),r1h ;017ac1511234
xor.b @(0x12345678:32,er1),r1h ;017ac95112345678
xor.b @(0x1234:16,r2l.b),r1h ;017ad2511234
xor.b @(0x1234:16,r2.w),r1h ;017ae2511234
xor.b @(0x1234:16,er2.l),r1h ;017af2511234
xor.b @(0x12345678:32,r2l.b),r1h ;017ada5112345678
xor.b @(0x12345678:32,r2.w),r1h ;017aea5112345678
xor.b @(0x12345678:32,er2.l),r1h ;017afa5112345678
xor.b @0xffffff12:8,r1h ;7e121501
xor.b @0x1234:16,r1h ;6a1012341501
xor.b @0x12345678:32,r1h ;6a30123456781501
xor.b @er3,@er1 ;7c350150
xor.b @er3,@(3:2,er1) ;7c353150
xor.b @er3,@-er1 ;7c35b150
xor.b @er3,@er1+ ;7c358150
xor.b @er3,@er1- ;7c35a150
xor.b @er3,@+er1 ;7c359150
xor.b @er3,@(0xffff9abc:16,er1) ;7c35c1509abc
xor.b @er3,@(0x9abcdef0:32,er1) ;7c35c9509abcdef0
xor.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2509abc
xor.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2509abc
xor.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2509abc
xor.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da509abcdef0
xor.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea509abcdef0
xor.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa509abcdef0
xor.b @er3,@0xffff9abc:16 ;7c3540509abc
xor.b @er3,@0x9abcdef0:32 ;7c3548509abcdef0
xor.b @-er3,@er1 ;01776c3c0150
xor.b @-er3,@(3:2,er1) ;01776c3c3150
xor.b @-er3,@-er1 ;01776c3cb150
xor.b @-er3,@er1+ ;01776c3c8150
xor.b @-er3,@er1- ;01776c3ca150
xor.b @-er3,@+er1 ;01776c3c9150
xor.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1509abc
xor.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9509abcdef0
xor.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2509abc
xor.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2509abc
xor.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2509abc
xor.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda509abcdef0
xor.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea509abcdef0
xor.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa509abcdef0
xor.b @-er3,@0xffff9abc:16 ;01776c3c40509abc
xor.b @-er3,@0x9abcdef0:32 ;01776c3c48509abcdef0
xor.b @er3+,@er1 ;01746c3c0150
xor.b @er3+,@(3:2,er1) ;01746c3c3150
xor.b @er3+,@-er1 ;01746c3cb150
xor.b @er3+,@er1+ ;01746c3c8150
xor.b @er3+,@er1- ;01746c3ca150
xor.b @er3+,@+er1 ;01746c3c9150
xor.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1509abc
xor.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9509abcdef0
xor.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2509abc
xor.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2509abc
xor.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2509abc
xor.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda509abcdef0
xor.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea509abcdef0
xor.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa509abcdef0
xor.b @er3+,@0xffff9abc:16 ;01746c3c40509abc
xor.b @er3+,@0x9abcdef0:32 ;01746c3c48509abcdef0
xor.b @er3-,@er1 ;01766c3c0150
xor.b @er3-,@(3:2,er1) ;01766c3c3150
xor.b @er3-,@-er1 ;01766c3cb150
xor.b @er3-,@er1+ ;01766c3c8150
xor.b @er3-,@er1- ;01766c3ca150
xor.b @er3-,@+er1 ;01766c3c9150
xor.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1509abc
xor.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9509abcdef0
xor.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2509abc
xor.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2509abc
xor.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2509abc
xor.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda509abcdef0
xor.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea509abcdef0
xor.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa509abcdef0
xor.b @er3-,@0xffff9abc:16 ;01766c3c40509abc
xor.b @er3-,@0x9abcdef0:32 ;01766c3c48509abcdef0
xor.b @+er3,@er1 ;01756c3c0150
xor.b @+er3,@(3:2,er1) ;01756c3c3150
xor.b @+er3,@-er1 ;01756c3cb150
xor.b @+er3,@er1+ ;01756c3c8150
xor.b @+er3,@er1- ;01756c3ca150
xor.b @+er3,@+er1 ;01756c3c9150
xor.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1509abc
xor.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9509abcdef0
xor.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2509abc
xor.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2509abc
xor.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2509abc
xor.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda509abcdef0
xor.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea509abcdef0
xor.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa509abcdef0
xor.b @+er3,@0xffff9abc:16 ;01756c3c40509abc
xor.b @+er3,@0x9abcdef0:32 ;01756c3c48509abcdef0
xor.b @(0x1234:16,er3),@er1 ;01746e3c12340150
xor.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343150
xor.b @(0x1234:16,er3),@-er1 ;01746e3c1234b150
xor.b @(0x1234:16,er3),@er1+ ;01746e3c12348150
xor.b @(0x1234:16,er3),@er1- ;01746e3c1234a150
xor.b @(0x1234:16,er3),@+er1 ;01746e3c12349150
xor.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1509abc
xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9509abcdef0
xor.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2509abc
xor.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2509abc
xor.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2509abc
xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da509abcdef0
xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea509abcdef0
xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa509abcdef0
xor.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440509abc
xor.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448509abcdef0
xor.b @(0x12345678:32,er3),@er1 ;78346a2c123456780150
xor.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783150
xor.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b150
xor.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788150
xor.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a150
xor.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789150
xor.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1509abc
xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9509abcdef0
xor.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2509abc
xor.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2509abc
xor.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2509abc
xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da509abcdef0
xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea509abcdef0
xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa509abcdef0
xor.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840509abc
xor.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848509abcdef0
xor.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340150
xor.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343150
xor.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b150
xor.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348150
xor.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a150
xor.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349150
xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1509abc
xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9509abcdef0
xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2509abc
xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2509abc
xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2509abc
xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da509abcdef0
xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea509abcdef0
xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa509abcdef0
xor.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440509abc
xor.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448509abcdef0
xor.b @(0x1234:16,r3.w),@er1 ;01766e3c12340150
xor.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343150
xor.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b150
xor.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348150
xor.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a150
xor.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349150
xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1509abc
xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9509abcdef0
xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2509abc
xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2509abc
xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2509abc
xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da509abcdef0
xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea509abcdef0
xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa509abcdef0
xor.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440509abc
xor.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448509abcdef0
xor.b @(0x1234:16,er3.l),@er1 ;01776e3c12340150
xor.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343150
xor.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b150
xor.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348150
xor.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a150
xor.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349150
xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1509abc
xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9509abcdef0
xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2509abc
xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2509abc
xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2509abc
xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da509abcdef0
xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea509abcdef0
xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa509abcdef0
xor.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440509abc
xor.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448509abcdef0
xor.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780150
xor.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783150
xor.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b150
xor.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788150
xor.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a150
xor.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789150
xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1509abc
xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9509abcdef0
xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2509abc
xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2509abc
xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2509abc
xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da509abcdef0
xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea509abcdef0
xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa509abcdef0
xor.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840509abc
xor.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848509abcdef0
xor.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780150
xor.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783150
xor.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b150
xor.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788150
xor.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a150
xor.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789150
xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1509abc
xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9509abcdef0
xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2509abc
xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2509abc
xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2509abc
xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da509abcdef0
xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea509abcdef0
xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa509abcdef0
xor.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840509abc
xor.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848509abcdef0
xor.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780150
xor.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783150
xor.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b150
xor.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788150
xor.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a150
xor.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789150
xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1509abc
xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9509abcdef0
xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2509abc
xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2509abc
xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2509abc
xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da509abcdef0
xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea509abcdef0
xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa509abcdef0
xor.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840509abc
xor.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848509abcdef0
xor.b @0x1234:16,@er1 ;6a1512340150
xor.b @0x1234:16,@(3:2,er1) ;6a1512343150
xor.b @0x1234:16,@-er1 ;6a151234b150
xor.b @0x1234:16,@er1+ ;6a1512348150
xor.b @0x1234:16,@er1- ;6a151234a150
xor.b @0x1234:16,@+er1 ;6a1512349150
xor.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1509abc
xor.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9509abcdef0
xor.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2509abc
xor.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2509abc
xor.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2509abc
xor.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da509abcdef0
xor.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea509abcdef0
xor.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa509abcdef0
xor.b @0x1234:16,@0xffff9abc:16 ;6a15123440509abc
xor.b @0x1234:16,@0x9abcdef0:32 ;6a15123448509abcdef0
xor.b @0x12345678:32,@er1 ;6a35123456780150
xor.b @0x12345678:32,@(3:2,er1) ;6a35123456783150
xor.b @0x12345678:32,@-er1 ;6a3512345678b150
xor.b @0x12345678:32,@er1+ ;6a35123456788150
xor.b @0x12345678:32,@er1- ;6a3512345678a150
xor.b @0x12345678:32,@+er1 ;6a35123456789150
xor.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1509abc
xor.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9509abcdef0
xor.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2509abc
xor.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2509abc
xor.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2509abc
xor.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da509abcdef0
xor.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea509abcdef0
xor.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa509abcdef0
xor.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840509abc
xor.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848509abcdef0
xor.w #0x1234:16,r1 ;79511234
xor.w #0x1234:16,@er1 ;015e01501234
xor.w #0x1234:16,@(0x6:2,er1) ;015e31501234
xor.w #0x1234:16,@er1+ ;015e81501234
xor.w #0x1234:16,@-er1 ;015eb1501234
xor.w #0x1234:16,@+er1 ;015e91501234
xor.w #0x1234:16,@er1- ;015ea1501234
xor.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1509abc1234
xor.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9509abcdef01234
xor.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2509abc1234
xor.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2509abc1234
xor.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2509abc1234
xor.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda509abcdef01234
xor.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea509abcdef01234
xor.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa509abcdef01234
xor.w #0x1234:16,@0xffff9abc:16 ;015e40509abc1234
xor.w #0x1234:16,@0x9abcdef0:32 ;015e48509abcdef01234
xor.w r3,r1 ;6531
xor.w r3,@er1 ;7d906530
xor.w r3,@(0x6:2,er1) ;01593153
xor.w r3,@-er1 ;0159b153
xor.w r3,@er1+ ;01598153
xor.w r3,@er1- ;0159a153
xor.w r3,@+er1 ;01599153
xor.w r3,@(0x1234:16,er1) ;0159c1531234
xor.w r3,@(0x12345678:32,er1) ;0159c95312345678
xor.w r3,@(0x1234:16,r2l.b) ;0159d2531234
xor.w r3,@(0x1234:16,r2.w) ;0159e2531234
xor.w r3,@(0x1234:16,er2.l) ;0159f2531234
xor.w r3,@(0x12345678:32,r2l.b) ;0159da5312345678
xor.w r3,@(0x12345678:32,r2.w) ;0159ea5312345678
xor.w r3,@(0x12345678:32,er2.l) ;0159fa5312345678
xor.w r3,@0x1234:16 ;6b1812346530
xor.w r3,@0x12345678:32 ;6b38123456786530
xor.w @er3,r1 ;7cb06501
xor.w @(0x6:2,er3),r1 ;015a3351
xor.w @er3+,r1 ;015a8351
xor.w @-er3,r1 ;015ab351
xor.w @+er3,r1 ;015a9351
xor.w @er3-,r1 ;015aa351
xor.w @(0x1234:16,er1),r1 ;015ac1511234
xor.w @(0x12345678:32,er1),r1 ;015ac95112345678
xor.w @(0x1234:16,r2l.b),r1 ;015ad2511234
xor.w @(0x1234:16,r2.w),r1 ;015ae2511234
xor.w @(0x1234:16,er2.l),r1 ;015af2511234
xor.w @(0x12345678:32,r2l.b),r1 ;015ada5112345678
xor.w @(0x12345678:32,r2.w),r1 ;015aea5112345678
xor.w @(0x12345678:32,er2.l),r1 ;015afa5112345678
xor.w @0x1234:16,r1 ;6b1012346501
xor.w @0x12345678:32,r1 ;6b30123456786501
xor.w @er3,@er1 ;7cb50150
xor.w @er3,@(6:2,er1) ;7cb53150
xor.w @er3,@-er1 ;7cb5b150
xor.w @er3,@er1+ ;7cb58150
xor.w @er3,@er1- ;7cb5a150
xor.w @er3,@+er1 ;7cb59150
xor.w @er3,@(0xffff9abc:16,er1) ;7cb5c1509abc
xor.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9509abcdef0
xor.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2509abc
xor.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2509abc
xor.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2509abc
xor.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da509abcdef0
xor.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea509abcdef0
xor.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa509abcdef0
xor.w @er3,@0xffff9abc:16 ;7cb540509abc
xor.w @er3,@0x9abcdef0:32 ;7cb548509abcdef0
xor.w @-er3,@er1 ;01576d3c0150
xor.w @-er3,@(6:2,er1) ;01576d3c3150
xor.w @-er3,@-er1 ;01576d3cb150
xor.w @-er3,@er1+ ;01576d3c8150
xor.w @-er3,@er1- ;01576d3ca150
xor.w @-er3,@+er1 ;01576d3c9150
xor.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1509abc
xor.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9509abcdef0
xor.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2509abc
xor.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2509abc
xor.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2509abc
xor.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda509abcdef0
xor.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea509abcdef0
xor.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa509abcdef0
xor.w @-er3,@0xffff9abc:16 ;01576d3c40509abc
xor.w @-er3,@0x9abcdef0:32 ;01576d3c48509abcdef0
xor.w @er3+,@er1 ;01546d3c0150
xor.w @er3+,@(6:2,er1) ;01546d3c3150
xor.w @er3+,@-er1 ;01546d3cb150
xor.w @er3+,@er1+ ;01546d3c8150
xor.w @er3+,@er1- ;01546d3ca150
xor.w @er3+,@+er1 ;01546d3c9150
xor.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1509abc
xor.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9509abcdef0
xor.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2509abc
xor.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2509abc
xor.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2509abc
xor.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda509abcdef0
xor.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea509abcdef0
xor.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa509abcdef0
xor.w @er3+,@0xffff9abc:16 ;01546d3c40509abc
xor.w @er3+,@0x9abcdef0:32 ;01546d3c48509abcdef0
xor.w @er3-,@er1 ;01566d3c0150
xor.w @er3-,@(6:2,er1) ;01566d3c3150
xor.w @er3-,@-er1 ;01566d3cb150
xor.w @er3-,@er1+ ;01566d3c8150
xor.w @er3-,@er1- ;01566d3ca150
xor.w @er3-,@+er1 ;01566d3c9150
xor.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1509abc
xor.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9509abcdef0
xor.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2509abc
xor.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2509abc
xor.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2509abc
xor.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda509abcdef0
xor.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea509abcdef0
xor.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa509abcdef0
xor.w @er3-,@0xffff9abc:16 ;01566d3c40509abc
xor.w @er3-,@0x9abcdef0:32 ;01566d3c48509abcdef0
xor.w @+er3,@er1 ;01556d3c0150
xor.w @+er3,@(6:2,er1) ;01556d3c3150
xor.w @+er3,@-er1 ;01556d3cb150
xor.w @+er3,@er1+ ;01556d3c8150
xor.w @+er3,@er1- ;01556d3ca150
xor.w @+er3,@+er1 ;01556d3c9150
xor.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1509abc
xor.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9509abcdef0
xor.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2509abc
xor.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2509abc
xor.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2509abc
xor.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda509abcdef0
xor.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea509abcdef0
xor.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa509abcdef0
xor.w @+er3,@0xffff9abc:16 ;01556d3c40509abc
xor.w @+er3,@0x9abcdef0:32 ;01556d3c48509abcdef0
xor.w @(0x1234:16,er3),@er1 ;01546f3c12340150
xor.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343150
xor.w @(0x1234:16,er3),@-er1 ;01546f3c1234b150
xor.w @(0x1234:16,er3),@er1+ ;01546f3c12348150
xor.w @(0x1234:16,er3),@er1- ;01546f3c1234a150
xor.w @(0x1234:16,er3),@+er1 ;01546f3c12349150
xor.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1509abc
xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9509abcdef0
xor.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2509abc
xor.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2509abc
xor.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2509abc
xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da509abcdef0
xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea509abcdef0
xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa509abcdef0
xor.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440509abc
xor.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448509abcdef0
xor.w @(0x12345678:32,er3),@er1 ;78346b2c123456780150
xor.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783150
xor.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b150
xor.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788150
xor.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a150
xor.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789150
xor.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1509abc
xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9509abcdef0
xor.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2509abc
xor.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2509abc
xor.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2509abc
xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da509abcdef0
xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea509abcdef0
xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa509abcdef0
xor.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840509abc
xor.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848509abcdef0
xor.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340150
xor.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343150
xor.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b150
xor.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348150
xor.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a150
xor.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349150
xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1509abc
xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9509abcdef0
xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2509abc
xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2509abc
xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2509abc
xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da509abcdef0
xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea509abcdef0
xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa509abcdef0
xor.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440509abc
xor.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448509abcdef0
xor.w @(0x1234:16,r3.w),@er1 ;01566f3c12340150
xor.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343150
xor.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b150
xor.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348150
xor.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a150
xor.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349150
xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1509abc
xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9509abcdef0
xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2509abc
xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2509abc
xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2509abc
xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da509abcdef0
xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea509abcdef0
xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa509abcdef0
xor.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440509abc
xor.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448509abcdef0
xor.w @(0x1234:16,er3.l),@er1 ;01576f3c12340150
xor.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343150
xor.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b150
xor.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348150
xor.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a150
xor.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349150
xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1509abc
xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9509abcdef0
xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2509abc
xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2509abc
xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2509abc
xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da509abcdef0
xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea509abcdef0
xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa509abcdef0
xor.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440509abc
xor.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448509abcdef0
xor.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780150
xor.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783150
xor.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b150
xor.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788150
xor.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a150
xor.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789150
xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1509abc
xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9509abcdef0
xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2509abc
xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2509abc
xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2509abc
xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da509abcdef0
xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea509abcdef0
xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa509abcdef0
xor.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840509abc
xor.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848509abcdef0
xor.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780150
xor.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783150
xor.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b150
xor.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788150
xor.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a150
xor.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789150
xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1509abc
xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9509abcdef0
xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2509abc
xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2509abc
xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2509abc
xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da509abcdef0
xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea509abcdef0
xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa509abcdef0
xor.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840509abc
xor.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848509abcdef0
xor.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780150
xor.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783150
xor.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b150
xor.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788150
xor.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a150
xor.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789150
xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1509abc
xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9509abcdef0
xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2509abc
xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2509abc
xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2509abc
xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da509abcdef0
xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea509abcdef0
xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa509abcdef0
xor.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840509abc
xor.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848509abcdef0
xor.w @0x1234:16,@er1 ;6b1512340150
xor.w @0x1234:16,@(6:2,er1) ;6b1512343150
xor.w @0x1234:16,@-er1 ;6b151234b150
xor.w @0x1234:16,@er1+ ;6b1512348150
xor.w @0x1234:16,@er1- ;6b151234a150
xor.w @0x1234:16,@+er1 ;6b1512349150
xor.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1509abc
xor.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9509abcdef0
xor.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2509abc
xor.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2509abc
xor.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2509abc
xor.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da509abcdef0
xor.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea509abcdef0
xor.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa509abcdef0
xor.w @0x1234:16,@0xffff9abc:16 ;6b15123440509abc
xor.w @0x1234:16,@0x9abcdef0:32 ;6b15123448509abcdef0
xor.w @0x12345678:32,@er1 ;6b35123456780150
xor.w @0x12345678:32,@(6:2,er1) ;6b35123456783150
xor.w @0x12345678:32,@-er1 ;6b3512345678b150
xor.w @0x12345678:32,@er1+ ;6b35123456788150
xor.w @0x12345678:32,@er1- ;6b3512345678a150
xor.w @0x12345678:32,@+er1 ;6b35123456789150
xor.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1509abc
xor.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9509abcdef0
xor.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2509abc
xor.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2509abc
xor.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2509abc
xor.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da509abcdef0
xor.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea509abcdef0
xor.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa509abcdef0
xor.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840509abc
xor.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848509abcdef0
xor.l #0x12345678:32,er1 ;7a5112345678
xor.l #0x1234:16,er1 ;7a591234
xor.l #0x12345678:32,@er1 ;010e015812345678
xor.l #0x12345678:32,@(0xc:2,er1) ;010e315812345678
xor.l #0x12345678:32,@er1+ ;010e815812345678
xor.l #0x12345678:32,@-er1 ;010eb15812345678
xor.l #0x12345678:32,@+er1 ;010e915812345678
xor.l #0x12345678:32,@er1- ;010ea15812345678
xor.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1589abc12345678
xor.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9589abcdef012345678
xor.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2589abc12345678
xor.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2589abc12345678
xor.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2589abc12345678
xor.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda589abcdef012345678
xor.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea589abcdef012345678
xor.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa589abcdef012345678
xor.l #0x12345678:32,@0xffff9abc:16 ;010e40589abc12345678
xor.l #0x12345678:32,@0x9abcdef0:32 ;010e48589abcdef012345678
xor.l #0x1234:16,@er1 ;010e01501234
xor.l #0x1234:16,@(0xc:2,er1) ;010e31501234
xor.l #0x1234:16,@er1+ ;010e81501234
xor.l #0x1234:16,@-er1 ;010eb1501234
xor.l #0x1234:16,@+er1 ;010e91501234
xor.l #0x1234:16,@er1- ;010ea1501234
xor.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1509abc1234
xor.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9509abcdef01234
xor.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2509abc1234
xor.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2509abc1234
xor.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2509abc1234
xor.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda509abcdef01234
xor.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea509abcdef01234
xor.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa509abcdef01234
xor.l #0x1234:16,@0xffff9abc:16 ;010e40509abc1234
xor.l #0x1234:16,@0x9abcdef0:32 ;010e48509abcdef01234
xor.l er3,er1 ;01f06531
xor.l er3,@er1 ;01090153
xor.l er3,@(0xc:2,er1) ;01093153
xor.l er3,@er1+ ;01098153
xor.l er3,@-er1 ;0109b153
xor.l er3,@+er1 ;01099153
xor.l er3,@er1- ;0109a153
xor.l er3,@(0x1234:16,er1) ;0109c1531234
xor.l er3,@(0x12345678:32,er1) ;0109c95312345678
xor.l er3,@(0x1234:16,r2l.b) ;0109d2531234
xor.l er3,@(0x1234:16,r2.w) ;0109e2531234
xor.l er3,@(0x1234:16,er2.l) ;0109f2531234
xor.l er3,@(0x12345678:32,r2l.b) ;0109da5312345678
xor.l er3,@(0x12345678:32,r2.w) ;0109ea5312345678
xor.l er3,@(0x12345678:32,er2.l) ;0109fa5312345678
xor.l er3,@0x1234:16 ;010940531234
xor.l er3,@0x12345678:32 ;0109485312345678
xor.l @er3,er1 ;010a0351
xor.l @(0xc:2,er3),er1 ;010a3351
xor.l @er3+,er1 ;010a8351
xor.l @-er3,er1 ;010ab351
xor.l @+er3,er1 ;010a9351
xor.l @er3-,er1 ;010aa351
xor.l @(0x1234:16,er1),er1 ;010ac1511234
xor.l @(0x12345678:32,er1),er1 ;010ac95112345678
xor.l @(0x1234:16,r2l.b),er1 ;010ad2511234
xor.l @(0x1234:16,r2.w),er1 ;010ae2511234
xor.l @(0x1234:16,er2.l),er1 ;010af2511234
xor.l @(0x12345678:32,r2l.b),er1 ;010ada5112345678
xor.l @(0x12345678:32,r2.w),er1 ;010aea5112345678
xor.l @(0x12345678:32,er2.l),er1 ;010afa5112345678
xor.l @0x1234:16,er1 ;010a40511234
xor.l @0x12345678:32,er1 ;010a485112345678
xor.l @er3,@er1 ;0104693c0150
xor.l @er3,@(0xc:2,er1) ;0104693c3150
xor.l @er3,@-er1 ;0104693cb150
xor.l @er3,@er1+ ;0104693c8150
xor.l @er3,@er1- ;0104693ca150
xor.l @er3,@+er1 ;0104693c9150
xor.l @er3,@(0xffff9abc:16,er1) ;0104693cc1509abc
xor.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9509abcdef0
xor.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2509abc
xor.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2509abc
xor.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2509abc
xor.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda509abcdef0
xor.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea509abcdef0
xor.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa509abcdef0
xor.l @er3,@0xffff9abc:16 ;0104693c40509abc
xor.l @er3,@0x9abcdef0:32 ;0104693c48509abcdef0
xor.l @(0xc:2,er3),@er1 ;0107693c0150
xor.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3150
xor.l @(0xc:2,er3),@-er1 ;0107693cb150
xor.l @(0xc:2,er3),@er1+ ;0107693c8150
xor.l @(0xc:2,er3),@er1- ;0107693ca150
xor.l @(0xc:2,er3),@+er1 ;0107693c9150
xor.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1509abc
xor.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9509abcdef0
xor.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2509abc
xor.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2509abc
xor.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2509abc
xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda509abcdef0
xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea509abcdef0
xor.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa509abcdef0
xor.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40509abc
xor.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48509abcdef0
xor.l @-er3,@er1 ;01076d3c0150
xor.l @-er3,@(0xc:2,er1) ;01076d3c3150
xor.l @-er3,@-er1 ;01076d3cb150
xor.l @-er3,@er1+ ;01076d3c8150
xor.l @-er3,@er1- ;01076d3ca150
xor.l @-er3,@+er1 ;01076d3c9150
xor.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1509abc
xor.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9509abcdef0
xor.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2509abc
xor.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2509abc
xor.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2509abc
xor.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda509abcdef0
xor.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea509abcdef0
xor.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa509abcdef0
xor.l @-er3,@0xffff9abc:16 ;01076d3c40509abc
xor.l @-er3,@0x9abcdef0:32 ;01076d3c48509abcdef0
xor.l @er3+,@er1 ;01046d3c0150
xor.l @er3+,@(0xc:2,er1) ;01046d3c3150
xor.l @er3+,@-er1 ;01046d3cb150
xor.l @er3+,@er1+ ;01046d3c8150
xor.l @er3+,@er1- ;01046d3ca150
xor.l @er3+,@+er1 ;01046d3c9150
xor.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1509abc
xor.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9509abcdef0
xor.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2509abc
xor.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2509abc
xor.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2509abc
xor.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda509abcdef0
xor.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea509abcdef0
xor.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa509abcdef0
xor.l @er3+,@0xffff9abc:16 ;01046d3c40509abc
xor.l @er3+,@0x9abcdef0:32 ;01046d3c48509abcdef0
xor.l @er3-,@er1 ;01066d3c0150
xor.l @er3-,@(0xc:2,er1) ;01066d3c3150
xor.l @er3-,@-er1 ;01066d3cb150
xor.l @er3-,@er1+ ;01066d3c8150
xor.l @er3-,@er1- ;01066d3ca150
xor.l @er3-,@+er1 ;01066d3c9150
xor.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1509abc
xor.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9509abcdef0
xor.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2509abc
xor.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2509abc
xor.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2509abc
xor.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda509abcdef0
xor.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea509abcdef0
xor.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa509abcdef0
xor.l @er3-,@0xffff9abc:16 ;01066d3c40509abc
xor.l @er3-,@0x9abcdef0:32 ;01066d3c48509abcdef0
xor.l @+er3,@er1 ;01056d3c0150
xor.l @+er3,@(0xc:2,er1) ;01056d3c3150
xor.l @+er3,@-er1 ;01056d3cb150
xor.l @+er3,@er1+ ;01056d3c8150
xor.l @+er3,@er1- ;01056d3ca150
xor.l @+er3,@+er1 ;01056d3c9150
xor.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1509abc
xor.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9509abcdef0
xor.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2509abc
xor.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2509abc
xor.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2509abc
xor.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda509abcdef0
xor.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea509abcdef0
xor.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa509abcdef0
xor.l @+er3,@0xffff9abc:16 ;01056d3c40509abc
xor.l @+er3,@0x9abcdef0:32 ;01056d3c48509abcdef0
xor.l @(0x1234:16,er3),@er1 ;01046f3c12340150
xor.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343150
xor.l @(0x1234:16,er3),@-er1 ;01046f3c1234b150
xor.l @(0x1234:16,er3),@er1+ ;01046f3c12348150
xor.l @(0x1234:16,er3),@er1- ;01046f3c1234a150
xor.l @(0x1234:16,er3),@+er1 ;01046f3c12349150
xor.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1509abc
xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9509abcdef0
xor.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2509abc
xor.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2509abc
xor.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2509abc
xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da509abcdef0
xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea509abcdef0
xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa509abcdef0
xor.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440509abc
xor.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448509abcdef0
xor.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780150
xor.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783150
xor.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b150
xor.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788150
xor.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a150
xor.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789150
xor.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1509abc
xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9509abcdef0
xor.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2509abc
xor.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2509abc
xor.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2509abc
xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da509abcdef0
xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea509abcdef0
xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa509abcdef0
xor.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840509abc
xor.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848509abcdef0
xor.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340150
xor.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343150
xor.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b150
xor.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348150
xor.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a150
xor.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349150
xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1509abc
xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9509abcdef0
xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2509abc
xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2509abc
xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2509abc
xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da509abcdef0
xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea509abcdef0
xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa509abcdef0
xor.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440509abc
xor.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448509abcdef0
xor.l @(0x1234:16,r3.w),@er1 ;01066f3c12340150
xor.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343150
xor.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b150
xor.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348150
xor.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a150
xor.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349150
xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1509abc
xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9509abcdef0
xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2509abc
xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2509abc
xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2509abc
xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da509abcdef0
xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea509abcdef0
xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa509abcdef0
xor.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440509abc
xor.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448509abcdef0
xor.l @(0x1234:16,er3.l),@er1 ;01076f3c12340150
xor.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343150
xor.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b150
xor.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348150
xor.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a150
xor.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349150
xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1509abc
xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9509abcdef0
xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2509abc
xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2509abc
xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2509abc
xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da509abcdef0
xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea509abcdef0
xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa509abcdef0
xor.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440509abc
xor.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448509abcdef0
xor.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780150
xor.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783150
xor.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b150
xor.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788150
xor.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a150
xor.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789150
xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1509abc
xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9509abcdef0
xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2509abc
xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2509abc
xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2509abc
xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da509abcdef0
xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea509abcdef0
xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa509abcdef0
xor.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840509abc
xor.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848509abcdef0
xor.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780150
xor.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783150
xor.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b150
xor.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788150
xor.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a150
xor.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789150
xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1509abc
xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9509abcdef0
xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2509abc
xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2509abc
xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2509abc
xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da509abcdef0
xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea509abcdef0
xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa509abcdef0
xor.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840509abc
xor.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848509abcdef0
xor.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780150
xor.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783150
xor.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b150
xor.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788150
xor.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a150
xor.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789150
xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1509abc
xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9509abcdef0
xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2509abc
xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2509abc
xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2509abc
xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da509abcdef0
xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea509abcdef0
xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa509abcdef0
xor.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840509abc
xor.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848509abcdef0
xor.l @0x1234:16,@er1 ;01046b0c12340150
xor.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343150
xor.l @0x1234:16,@-er1 ;01046b0c1234b150
xor.l @0x1234:16,@er1+ ;01046b0c12348150
xor.l @0x1234:16,@er1- ;01046b0c1234a150
xor.l @0x1234:16,@+er1 ;01046b0c12349150
xor.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1509abc
xor.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9509abcdef0
xor.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2509abc
xor.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2509abc
xor.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2509abc
xor.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da509abcdef0
xor.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea509abcdef0
xor.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa509abcdef0
xor.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440509abc
xor.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448509abcdef0
xor.l @0x12345678:32,@er1 ;01046b2c123456780150
xor.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783150
xor.l @0x12345678:32,@-er1 ;01046b2c12345678b150
xor.l @0x12345678:32,@er1+ ;01046b2c123456788150
xor.l @0x12345678:32,@er1- ;01046b2c12345678a150
xor.l @0x12345678:32,@+er1 ;01046b2c123456789150
xor.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1509abc
xor.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9509abcdef0
xor.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2509abc
xor.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2509abc
xor.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2509abc
xor.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da509abcdef0
xor.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea509abcdef0
xor.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa509abcdef0
xor.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840509abc
xor.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848509abcdef0
.end
|
stsp/binutils-ia16
| 4,045
|
gdb/testsuite/gdb.disasm/mn10300.s
|
.text
.global _main
.global add_tests
.global bCC_tests
.global bit_tests
.global cmp_tests
.global extend_tests
.global extended_tests
.global logical_tests
.global loop_tests
.global mov_tests_1
.global mov_tests_2
.global mov_tests_3
.global mov_tests_4
.global movbu_tests
.global movhu_tests
.global movm_tests
.global muldiv_tests
.global other_tests
.global shift_tests
.global sub_tests
_main:
nop
add_tests:
add d1,d2
add d2,a3
add a3,a2
add a2,d1
add 16,d1
add 256,d2
add 131071,d3
add 16,a1
add 256,a2
add 131071,a3
add 16,sp
add 256,sp
add 131071,sp
addc d1,d2
bCC_tests:
beq bCC_tests
bne bCC_tests
bgt bCC_tests
bge bCC_tests
ble bCC_tests
blt bCC_tests
bhi bCC_tests
bcc bCC_tests
bls bCC_tests
bcs bCC_tests
bvc bCC_tests
bvs bCC_tests
bnc bCC_tests
bns bCC_tests
bra bCC_tests
bit_tests:
btst 64,d1
btst 8192,d2
btst 131071,d3
btst 64,(8,a1)
btst 64,(0x1ffff)
bset d1,(a2)
bset 64,(8,a1)
bset 64,(0x1ffff)
bclr d1,(a2)
bclr 64,(8,a1)
bclr 64,(0x1ffff)
cmp_tests:
cmp d1,d2
cmp d2,a3
cmp a3,d3
cmp a3,a2
cmp 16,d3
cmp 256,d2
cmp 131071,d1
cmp 16,a3
cmp 256,a2
cmp 131071,a1
extend_tests:
ext d1
extb d2
extbu d3
exth d2
exthu d1
extended_tests:
putx d1
getx d2
mulq d1,d2
mulq 16,d2
mulq 256,d3
mulq 131071,d3
mulqu d1,d2
mulqu 16,d2
mulqu 256,d3
mulqu 131071,d3
sat16 d2,d3
sat24 d3,d2
bsch d1,d2
logical_tests:
and d1,d2
and 127,d2
and 32767,d3
and 131071,d3
and 32767,psw
or d1,d2
or 127,d2
or 32767,d3
or 131071,d3
or 32767,psw
xor d1,d2
xor 32767,d3
xor 131071,d3
not d3
loop_tests:
leq
lne
lgt
lge
lle
llt
lhi
lcc
lls
lcs
lra
setlb
mov_tests_1:
mov d1,d2
mov d1,a2
mov a2,d1
mov a2,a1
mov sp,a2
mov a1,sp
mov d2,psw
mov mdr,d1
mov d2,mdr
mov (a2),d1
mov (8,a2),d1
mov (256,a2),d1
mov (131071,a2),d1
mov (8,sp),d1
mov (256,sp),d1
mov psw,d3
mov_tests_2:
mov (131071,sp),d1
mov (d1,a1),d2
mov (32768),d1
mov (131071),d1
mov (a2),a1
mov (8,a2),a1
mov (256,a2),a1
mov (131071,a2),a1
mov (8,sp),a1
mov (256,sp),a1
mov (131071,sp),a1
mov (d1,a1),a2
mov (32768),a1
mov (131071),a1
mov (32,a1),sp
mov_tests_3:
mov d1,(a2)
mov d1,(32,a2)
mov d1,(256,a2)
mov d1,(131071,a2)
mov d1,(32,sp)
mov d1,(32768,sp)
mov d1,(131071,sp)
mov d1,(d2,a2)
mov d1,(128)
mov d1,(131071)
mov a1,(a2)
mov a1,(32,a2)
mov a1,(256,a2)
mov a1,(131071,a2)
mov a1,(32,sp)
mov_tests_4:
mov a1,(32768,sp)
mov a1,(131071,sp)
mov a1,(d2,a2)
mov a1,(128)
mov a1,(131071)
mov sp,(32,a1)
mov 8,d1
mov 256,d1
mov 131071,d1
mov 8,a1
mov 256,a1
mov 131071,a1
movbu_tests:
movbu (a2),d1
movbu (8,a2),d1
movbu (256,a2),d1
movbu (131071,a2),d1
movbu (8,sp),d1
movbu (256,sp),d1
movbu (131071,sp),d1
movbu (d1,a1),d2
movbu (32768),d1
movbu (131071),d1
movbu d1,(a2)
movbu d1,(32,a2)
movbu d1,(256,a2)
movbu d1,(131071,a2)
movbu d1,(32,sp)
movbu d1,(32768,sp)
movbu d1,(131071,sp)
movbu d1,(d2,a2)
movbu d1,(128)
movbu d1,(131071)
movhu_tests:
movhu (a2),d1
movhu (8,a2),d1
movhu (256,a2),d1
movhu (131071,a2),d1
movhu (8,sp),d1
movhu (256,sp),d1
movhu (131071,sp),d1
movhu (d1,a1),d2
movhu (32768),d1
movhu (131071),d1
movhu d1,(a2)
movhu d1,(32,a2)
movhu d1,(256,a2)
movhu d1,(131071,a2)
movhu d1,(32,sp)
movhu d1,(32768,sp)
movhu d1,(131071,sp)
movhu d1,(d2,a2)
movhu d1,(128)
movhu d1,(131071)
movm_tests:
movm (sp),[a2,a3]
movm (sp),[d2,d3,a2,a3,other]
movm [a2,a3],(sp)
movm [d2,d3,a2,a3,other],(sp)
muldiv_tests:
mul d1,d2
mulu d2,d3
div d3,d3
divu d3,d2
other_tests:
clr d2
inc d1
inc a2
inc4 a3
jmp (a2)
jmp _main
jmp _start
call _main,[a2,a3],9
call _start,[a2,a3],32
calls (a2)
calls _main
calls _start
ret [a2,a3],7
retf [a2,a3],5
rets
rti
trap
nop
rtm
shift_tests:
asr d1,d2
asr 4,d2
lsr d2,d3
lsr 4,d3
asl d3,d2
asl 4,d2
asl2 d2
ror d1
rol d2
sub_tests:
sub d1,d2
sub d2,a3
sub a3,d3
sub a3,a2
sub 131071,d2
sub 131071,a1
subc d1,d2
|
stsp/binutils-ia16
| 54,669
|
gdb/testsuite/gdb.disasm/t11_logs.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;log_sft
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
not.b r1h ;1701
not.b @er1 ;7d101700
not.b @(0x3:2,er1) ;017768181700
not.b @er1+ ;01746c181700
not.b @-er1 ;01776c181700
not.b @+er1 ;01756c181700
not.b @er1- ;01766c181700
not.b @(0x1234:16,er1) ;01746e1812341700
not.b @(0x12345678:32,er1) ;78146a28123456781700
not.b @(0x1234:16,r2l.b) ;01756e2812341700
not.b @(0x1234:16,r2.w) ;01766e2812341700
not.b @(0x1234:16,er2.l) ;01776e2812341700
not.b @(0x12345678:32,r2l.b) ;78256a28123456781700
not.b @(0x12345678:32,r2.w) ;78266a28123456781700
not.b @(0x12345678:32,er2.l) ;78276a28123456781700
not.b @0xffffff12:8 ;7f121700
not.b @0x1234:16 ;6a1812341700
not.b @0x12345678:32 ;6a38123456781700
not.w r1 ;1711
not.w @er1 ;7d901710
not.w @(0x6:2,er1) ;015769181710
not.w @er1+ ;01546d181710
not.w @-er1 ;01576d181710
not.w @+er1 ;01556d181710
not.w @er1- ;01566d181710
not.w @(0x1234:16,er1) ;01546f1812341710
not.w @(0x12345678:32,er1) ;78146b28123456781710
not.w @(0x1234:16,r2l.b) ;01556f2812341710
not.w @(0x1234:16,r2.w) ;01566f2812341710
not.w @(0x1234:16,er2.l) ;01576f2812341710
not.w @(0x12345678:32,r2l.b) ;78256b28123456781710
not.w @(0x12345678:32,r2.w) ;78266b28123456781710
not.w @(0x12345678:32,er2.l) ;78276b28123456781710
not.w @0x1234:16 ;6b1812341710
not.w @0x12345678:32 ;6b38123456781710
not.l er1 ;1731
not.l @er1 ;010469181730
not.l @(0xc:2,er1) ;010769181730
not.l @er1+ ;01046d181730
not.l @-er1 ;01076d181730
not.l @+er1 ;01056d181730
not.l @er1- ;01066d181730
not.l @(0x1234:16,er1) ;01046f1812341730
not.l @(0x12345678:32,er1) ;78946b28123456781730
not.l @(0x1234:16,r2l.b) ;01056f2812341730
not.l @(0x1234:16,r2.w) ;01066f2812341730
not.l @(0x1234:16,er2.l) ;01076f2812341730
not.l @(0x12345678:32,r2l.b) ;78a56b28123456781730
not.l @(0x12345678:32,r2.w) ;78a66b28123456781730
not.l @(0x12345678:32,er2.l) ;78a76b28123456781730
not.l @0x1234:16 ;01046b0812341730
not.l @0x12345678:32 ;01046b28123456781730
shll.b r1h ;1001
shll.b @er1 ;7d101000
shll.b @(0x3:2,er1) ;017768181000
shll.b @er1+ ;01746c181000
shll.b @-er1 ;01776c181000
shll.b @+er1 ;01756c181000
shll.b @er1- ;01766c181000
shll.b @(0x1234:16,er1) ;01746e1812341000
shll.b @(0x12345678:32,er1) ;78146a28123456781000
shll.b @(0x1234:16,r2l.b) ;01756e2812341000
shll.b @(0x1234:16,r2.w) ;01766e2812341000
shll.b @(0x1234:16,er2.l) ;01776e2812341000
shll.b @(0x12345678:32,r2l.b) ;78256a28123456781000
shll.b @(0x12345678:32,r2.w) ;78266a28123456781000
shll.b @(0x12345678:32,er2.l) ;78276a28123456781000
shll.b @0xffffff12:8 ;7f121000
shll.b @0x1234:16 ;6a1812341000
shll.b @0x12345678:32 ;6a38123456781000
shll.w r1 ;1011
shll.w @er1 ;7d901010
shll.w @(0x6:2,er1) ;015769181010
shll.w @er1+ ;01546d181010
shll.w @-er1 ;01576d181010
shll.w @+er1 ;01556d181010
shll.w @er1- ;01566d181010
shll.w @(0x1234:16,er1) ;01546f1812341010
shll.w @(0x12345678:32,er1) ;78146b28123456781010
shll.w @(0x1234:16,r2l.b) ;01556f2812341010
shll.w @(0x1234:16,r2.w) ;01566f2812341010
shll.w @(0x1234:16,er2.l) ;01576f2812341010
shll.w @(0x12345678:32,r2l.b) ;78256b28123456781010
shll.w @(0x12345678:32,r2.w) ;78266b28123456781010
shll.w @(0x12345678:32,er2.l) ;78276b28123456781010
shll.w @0x1234:16 ;6b1812341010
shll.w @0x12345678:32 ;6b38123456781010
shll.l er1 ;1031
shll.l @er1 ;010469181030
shll.l @(0xc:2,er1) ;010769181030
shll.l @er1+ ;01046d181030
shll.l @-er1 ;01076d181030
shll.l @+er1 ;01056d181030
shll.l @er1- ;01066d181030
shll.l @(0x1234:16,er1) ;01046f1812341030
shll.l @(0x12345678:32,er1) ;78946b28123456781030
shll.l @(0x1234:16,r2l.b) ;01056f2812341030
shll.l @(0x1234:16,r2.w) ;01066f2812341030
shll.l @(0x1234:16,er2.l) ;01076f2812341030
shll.l @(0x12345678:32,r2l.b) ;78a56b28123456781030
shll.l @(0x12345678:32,r2.w) ;78a66b28123456781030
shll.l @(0x12345678:32,er2.l) ;78a76b28123456781030
shll.l @0x1234:16 ;01046b0812341030
shll.l @0x12345678:32 ;01046b28123456781030
shll.b #2,r1h ;1041
shll.b #2,@er1 ;7d101040
shll.b #2,@(0x3:2,er1) ;017768181040
shll.b #2,@er1+ ;01746c181040
shll.b #2,@-er1 ;01776c181040
shll.b #2,@+er1 ;01756c181040
shll.b #2,@er1- ;01766c181040
shll.b #2,@(0x1234:16,er1) ;01746e1812341040
shll.b #2,@(0x12345678:32,er1) ;78146a28123456781040
shll.b #2,@(0x1234:16,r2l.b) ;01756e2812341040
shll.b #2,@(0x1234:16,r2.w) ;01766e2812341040
shll.b #2,@(0x1234:16,er2.l) ;01776e2812341040
shll.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781040
shll.b #2,@(0x12345678:32,r2.w) ;78266a28123456781040
shll.b #2,@(0x12345678:32,er2.l) ;78276a28123456781040
shll.b #2,@0xffffff12:8 ;7f121040
shll.b #2,@0x1234:16 ;6a1812341040
shll.b #2,@0x12345678:32 ;6a38123456781040
shll.w #2,r1 ;1051
shll.w #2,@er1 ;7d901050
shll.w #2,@(0x6:2,er1) ;015769181050
shll.w #2,@er1+ ;01546d181050
shll.w #2,@-er1 ;01576d181050
shll.w #2,@+er1 ;01556d181050
shll.w #2,@er1- ;01566d181050
shll.w #2,@(0x1234:16,er1) ;01546f1812341050
shll.w #2,@(0x12345678:32,er1) ;78146b28123456781050
shll.w #2,@(0x1234:16,r2l.b) ;01556f2812341050
shll.w #2,@(0x1234:16,r2.w) ;01566f2812341050
shll.w #2,@(0x1234:16,er2.l) ;01576f2812341050
shll.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781050
shll.w #2,@(0x12345678:32,r2.w) ;78266b28123456781050
shll.w #2,@(0x12345678:32,er2.l) ;78276b28123456781050
shll.w #2,@0x1234:16 ;6b1812341050
shll.w #2,@0x12345678:32 ;6b38123456781050
shll.l #2,er1 ;1071
shll.l #2,@er1 ;010469181070
shll.l #2,@(0xc:2,er1) ;010769181070
shll.l #2,@er1+ ;01046d181070
shll.l #2,@-er1 ;01076d181070
shll.l #2,@+er1 ;01056d181070
shll.l #2,@er1- ;01066d181070
shll.l #2,@(0x1234:16,er1) ;01046f1812341070
shll.l #2,@(0x12345678:32,er1) ;78946b28123456781070
shll.l #2,@(0x1234:16,r2l.b) ;01056f2812341070
shll.l #2,@(0x1234:16,r2.w) ;01066f2812341070
shll.l #2,@(0x1234:16,er2.l) ;01076f2812341070
shll.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781070
shll.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781070
shll.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781070
shll.l #2,@0x1234:16 ;01046b0812341070
shll.l #2,@0x12345678:32 ;01046b28123456781070
shll.b #4,r1h ;10a1
shll.b #4,@er1 ;7d1010a0
shll.b #4,@(0x3:2,er1) ;0177681810a0
shll.b #4,@er1+ ;01746c1810a0
shll.b #4,@-er1 ;01776c1810a0
shll.b #4,@+er1 ;01756c1810a0
shll.b #4,@er1- ;01766c1810a0
shll.b #4,@(0x1234:16,er1) ;01746e18123410a0
shll.b #4,@(0x12345678:32,er1) ;78146a281234567810a0
shll.b #4,@(0x1234:16,r2l.b) ;01756e28123410a0
shll.b #4,@(0x1234:16,r2.w) ;01766e28123410a0
shll.b #4,@(0x1234:16,er2.l) ;01776e28123410a0
shll.b #4,@(0x12345678:32,r2l.b) ;78256a281234567810a0
shll.b #4,@(0x12345678:32,r2.w) ;78266a281234567810a0
shll.b #4,@(0x12345678:32,er2.l) ;78276a281234567810a0
shll.b #4,@0xffffff12:8 ;7f1210a0
shll.b #4,@0x1234:16 ;6a18123410a0
shll.b #4,@0x12345678:32 ;6a381234567810a0
shll.w #4,r1 ;1021
shll.w #4,@er1 ;7d901020
shll.w #4,@(0x6:2,er1) ;015769181020
shll.w #4,@er1+ ;01546d181020
shll.w #4,@-er1 ;01576d181020
shll.w #4,@+er1 ;01556d181020
shll.w #4,@er1- ;01566d181020
shll.w #4,@(0x1234:16,er1) ;01546f1812341020
shll.w #4,@(0x12345678:32,er1) ;78146b28123456781020
shll.w #4,@(0x1234:16,r2l.b) ;01556f2812341020
shll.w #4,@(0x1234:16,r2.w) ;01566f2812341020
shll.w #4,@(0x1234:16,er2.l) ;01576f2812341020
shll.w #4,@(0x12345678:32,r2l.b) ;78256b28123456781020
shll.w #4,@(0x12345678:32,r2.w) ;78266b28123456781020
shll.w #4,@(0x12345678:32,er2.l) ;78276b28123456781020
shll.w #4,@0x1234:16 ;6b1812341020
shll.w #4,@0x12345678:32 ;6b38123456781020
shll.l #4,er1 ;1039
shll.l #4,@er1 ;010469181038
shll.l #4,@(0xc:2,er1) ;010769181038
shll.l #4,@er1+ ;01046d181038
shll.l #4,@-er1 ;01076d181038
shll.l #4,@+er1 ;01056d181038
shll.l #4,@er1- ;01066d181038
shll.l #4,@(0x1234:16,er1) ;01046f1812341038
shll.l #4,@(0x12345678:32,er1) ;78946b28123456781038
shll.l #4,@(0x1234:16,r2l.b) ;01056f2812341038
shll.l #4,@(0x1234:16,r2.w) ;01066f2812341038
shll.l #4,@(0x1234:16,er2.l) ;01076f2812341038
shll.l #4,@(0x12345678:32,r2l.b) ;78a56b28123456781038
shll.l #4,@(0x12345678:32,r2.w) ;78a66b28123456781038
shll.l #4,@(0x12345678:32,er2.l) ;78a76b28123456781038
shll.l #4,@0x1234:16 ;01046b0812341038
shll.l #4,@0x12345678:32 ;01046b28123456781038
shll.w #8,r1 ;1061
shll.w #8,@er1 ;7d901060
shll.w #8,@(0x6:2,er1) ;015769181060
shll.w #8,@er1+ ;01546d181060
shll.w #8,@-er1 ;01576d181060
shll.w #8,@+er1 ;01556d181060
shll.w #8,@er1- ;01566d181060
shll.w #8,@(0x1234:16,er1) ;01546f1812341060
shll.w #8,@(0x12345678:32,er1) ;78146b28123456781060
shll.w #8,@(0x1234:16,r2l.b) ;01556f2812341060
shll.w #8,@(0x1234:16,r2.w) ;01566f2812341060
shll.w #8,@(0x1234:16,er2.l) ;01576f2812341060
shll.w #8,@(0x12345678:32,r2l.b) ;78256b28123456781060
shll.w #8,@(0x12345678:32,r2.w) ;78266b28123456781060
shll.w #8,@(0x12345678:32,er2.l) ;78276b28123456781060
shll.w #8,@0x1234:16 ;6b1812341060
shll.w #8,@0x12345678:32 ;6b38123456781060
shll.l #8,er1 ;1079
shll.l #8,@er1 ;010469181078
shll.l #8,@(0xc:2,er1) ;010769181078
shll.l #8,@er1+ ;01046d181078
shll.l #8,@-er1 ;01076d181078
shll.l #8,@+er1 ;01056d181078
shll.l #8,@er1- ;01066d181078
shll.l #8,@(0x1234:16,er1) ;01046f1812341078
shll.l #8,@(0x12345678:32,er1) ;78946b28123456781078
shll.l #8,@(0x1234:16,r2l.b) ;01056f2812341078
shll.l #8,@(0x1234:16,r2.w) ;01066f2812341078
shll.l #8,@(0x1234:16,er2.l) ;01076f2812341078
shll.l #8,@(0x12345678:32,r2l.b) ;78a56b28123456781078
shll.l #8,@(0x12345678:32,r2.w) ;78a66b28123456781078
shll.l #8,@(0x12345678:32,er2.l) ;78a76b28123456781078
shll.l #8,@0x1234:16 ;01046b0812341078
shll.l #8,@0x12345678:32 ;01046b28123456781078
shll.l #16,er1 ;10f9
shll.l #16,@er1 ;0104691810f8
shll.l #16,@(0xc:2,er1) ;0107691810f8
shll.l #16,@er1+ ;01046d1810f8
shll.l #16,@-er1 ;01076d1810f8
shll.l #16,@+er1 ;01056d1810f8
shll.l #16,@er1- ;01066d1810f8
shll.l #16,@(0x1234:16,er1) ;01046f18123410f8
shll.l #16,@(0x12345678:32,er1) ;78946b281234567810f8
shll.l #16,@(0x1234:16,r2l.b) ;01056f28123410f8
shll.l #16,@(0x1234:16,r2.w) ;01066f28123410f8
shll.l #16,@(0x1234:16,er2.l) ;01076f28123410f8
shll.l #16,@(0x12345678:32,r2l.b) ;78a56b281234567810f8
shll.l #16,@(0x12345678:32,r2.w) ;78a66b281234567810f8
shll.l #16,@(0x12345678:32,er2.l) ;78a76b281234567810f8
shll.l #16,@0x1234:16 ;01046b08123410f8
shll.l #16,@0x12345678:32 ;01046b281234567810f8
shll.b #0x7:5,r1h ;03871001
shll.w #0xf:5,r1 ;038f1011
shll.l #0x1f:5,er1 ;039f1031
shll.b r3h,r1h ;78381001
shll.w r3h,r1 ;78381011
shll.l r3h,er1 ;78381031
shlr.b r1h ;1101
shlr.b @er1 ;7d101100
shlr.b @(0x3:2,er1) ;017768181100
shlr.b @er1+ ;01746c181100
shlr.b @-er1 ;01776c181100
shlr.b @+er1 ;01756c181100
shlr.b @er1- ;01766c181100
shlr.b @(0x1234:16,er1) ;01746e1812341100
shlr.b @(0x12345678:32,er1) ;78146a28123456781100
shlr.b @(0x1234:16,r2l.b) ;01756e2812341100
shlr.b @(0x1234:16,r2.w) ;01766e2812341100
shlr.b @(0x1234:16,er2.l) ;01776e2812341100
shlr.b @(0x12345678:32,r2l.b) ;78256a28123456781100
shlr.b @(0x12345678:32,r2.w) ;78266a28123456781100
shlr.b @(0x12345678:32,er2.l) ;78276a28123456781100
shlr.b @0xffffff12:8 ;7f121100
shlr.b @0x1234:16 ;6a1812341100
shlr.b @0x12345678:32 ;6a38123456781100
shlr.w r1 ;1111
shlr.w @er1 ;7d901110
shlr.w @(0x6:2,er1) ;015769181110
shlr.w @er1+ ;01546d181110
shlr.w @-er1 ;01576d181110
shlr.w @+er1 ;01556d181110
shlr.w @er1- ;01566d181110
shlr.w @(0x1234:16,er1) ;01546f1812341110
shlr.w @(0x12345678:32,er1) ;78146b28123456781110
shlr.w @(0x1234:16,r2l.b) ;01556f2812341110
shlr.w @(0x1234:16,r2.w) ;01566f2812341110
shlr.w @(0x1234:16,er2.l) ;01576f2812341110
shlr.w @(0x12345678:32,r2l.b) ;78256b28123456781110
shlr.w @(0x12345678:32,r2.w) ;78266b28123456781110
shlr.w @(0x12345678:32,er2.l) ;78276b28123456781110
shlr.w @0x1234:16 ;6b1812341110
shlr.w @0x12345678:32 ;6b38123456781110
shlr.l er1 ;1131
shlr.l @er1 ;010469181130
shlr.l @(0xc:2,er1) ;010769181130
shlr.l @er1+ ;01046d181130
shlr.l @-er1 ;01076d181130
shlr.l @+er1 ;01056d181130
shlr.l @er1- ;01066d181130
shlr.l @(0x1234:16,er1) ;01046f1812341130
shlr.l @(0x12345678:32,er1) ;78946b28123456781130
shlr.l @(0x1234:16,r2l.b) ;01056f2812341130
shlr.l @(0x1234:16,r2.w) ;01066f2812341130
shlr.l @(0x1234:16,er2.l) ;01076f2812341130
shlr.l @(0x12345678:32,r2l.b) ;78a56b28123456781130
shlr.l @(0x12345678:32,r2.w) ;78a66b28123456781130
shlr.l @(0x12345678:32,er2.l) ;78a76b28123456781130
shlr.l @0x1234:16 ;01046b0812341130
shlr.l @0x12345678:32 ;01046b28123456781130
shlr.b #2,r1h ;1141
shlr.b #2,@er1 ;7d101140
shlr.b #2,@(0x3:2,er1) ;017768181140
shlr.b #2,@er1+ ;01746c181140
shlr.b #2,@-er1 ;01776c181140
shlr.b #2,@+er1 ;01756c181140
shlr.b #2,@er1- ;01766c181140
shlr.b #2,@(0x1234:16,er1) ;01746e1812341140
shlr.b #2,@(0x12345678:32,er1) ;78146a28123456781140
shlr.b #2,@(0x1234:16,r2l.b) ;01756e2812341140
shlr.b #2,@(0x1234:16,r2.w) ;01766e2812341140
shlr.b #2,@(0x1234:16,er2.l) ;01776e2812341140
shlr.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781140
shlr.b #2,@(0x12345678:32,r2.w) ;78266a28123456781140
shlr.b #2,@(0x12345678:32,er2.l) ;78276a28123456781140
shlr.b #2,@0xffffff12:8 ;7f121140
shlr.b #2,@0x1234:16 ;6a1812341140
shlr.b #2,@0x12345678:32 ;6a38123456781140
shlr.w #2,r1 ;1151
shlr.w #2,@er1 ;7d901150
shlr.w #2,@(0x6:2,er1) ;015769181150
shlr.w #2,@er1+ ;01546d181150
shlr.w #2,@-er1 ;01576d181150
shlr.w #2,@+er1 ;01556d181150
shlr.w #2,@er1- ;01566d181150
shlr.w #2,@(0x1234:16,er1) ;01546f1812341150
shlr.w #2,@(0x12345678:32,er1) ;78146b28123456781150
shlr.w #2,@(0x1234:16,r2l.b) ;01556f2812341150
shlr.w #2,@(0x1234:16,r2.w) ;01566f2812341150
shlr.w #2,@(0x1234:16,er2.l) ;01576f2812341150
shlr.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781150
shlr.w #2,@(0x12345678:32,r2.w) ;78266b28123456781150
shlr.w #2,@(0x12345678:32,er2.l) ;78276b28123456781150
shlr.w #2,@0x1234:16 ;6b1812341150
shlr.w #2,@0x12345678:32 ;6b38123456781150
shlr.l #2,er1 ;1171
shlr.l #2,@er1 ;010469181170
shlr.l #2,@(0xc:2,er1) ;010769181170
shlr.l #2,@er1+ ;01046d181170
shlr.l #2,@-er1 ;01076d181170
shlr.l #2,@+er1 ;01056d181170
shlr.l #2,@er1- ;01066d181170
shlr.l #2,@(0x1234:16,er1) ;01046f1812341170
shlr.l #2,@(0x12345678:32,er1) ;78946b28123456781170
shlr.l #2,@(0x1234:16,r2l.b) ;01056f2812341170
shlr.l #2,@(0x1234:16,r2.w) ;01066f2812341170
shlr.l #2,@(0x1234:16,er2.l) ;01076f2812341170
shlr.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781170
shlr.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781170
shlr.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781170
shlr.l #2,@0x1234:16 ;01046b0812341170
shlr.l #2,@0x12345678:32 ;01046b28123456781170
shlr.b #4,r1h ;11a1
shlr.b #4,@er1 ;7d1011a0
shlr.b #4,@(0x3:2,er1) ;0177681811a0
shlr.b #4,@er1+ ;01746c1811a0
shlr.b #4,@-er1 ;01776c1811a0
shlr.b #4,@+er1 ;01756c1811a0
shlr.b #4,@er1- ;01766c1811a0
shlr.b #4,@(0x1234:16,er1) ;01746e18123411a0
shlr.b #4,@(0x12345678:32,er1) ;78146a281234567811a0
shlr.b #4,@(0x1234:16,r2l.b) ;01756e28123411a0
shlr.b #4,@(0x1234:16,r2.w) ;01766e28123411a0
shlr.b #4,@(0x1234:16,er2.l) ;01776e28123411a0
shlr.b #4,@(0x12345678:32,r2l.b) ;78256a281234567811a0
shlr.b #4,@(0x12345678:32,r2.w) ;78266a281234567811a0
shlr.b #4,@(0x12345678:32,er2.l) ;78276a281234567811a0
shlr.b #4,@0xffffff12:8 ;7f1211a0
shlr.b #4,@0x1234:16 ;6a18123411a0
shlr.b #4,@0x12345678:32 ;6a381234567811a0
shlr.w #4,r1 ;1121
shlr.w #4,@er1 ;7d901120
shlr.w #4,@(0x6:2,er1) ;015769181120
shlr.w #4,@er1+ ;01546d181120
shlr.w #4,@-er1 ;01576d181120
shlr.w #4,@+er1 ;01556d181120
shlr.w #4,@er1- ;01566d181120
shlr.w #4,@(0x1234:16,er1) ;01546f1812341120
shlr.w #4,@(0x12345678:32,er1) ;78146b28123456781120
shlr.w #4,@(0x1234:16,r2l.b) ;01556f2812341120
shlr.w #4,@(0x1234:16,r2.w) ;01566f2812341120
shlr.w #4,@(0x1234:16,er2.l) ;01576f2812341120
shlr.w #4,@(0x12345678:32,r2l.b) ;78256b28123456781120
shlr.w #4,@(0x12345678:32,r2.w) ;78266b28123456781120
shlr.w #4,@(0x12345678:32,er2.l) ;78276b28123456781120
shlr.w #4,@0x1234:16 ;6b1812341120
shlr.w #4,@0x12345678:32 ;6b38123456781120
shlr.l #4,er1 ;1139
shlr.l #4,@er1 ;010469181138
shlr.l #4,@(0xc:2,er1) ;010769181138
shlr.l #4,@er1+ ;01046d181138
shlr.l #4,@-er1 ;01076d181138
shlr.l #4,@+er1 ;01056d181138
shlr.l #4,@er1- ;01066d181138
shlr.l #4,@(0x1234:16,er1) ;01046f1812341138
shlr.l #4,@(0x12345678:32,er1) ;78946b28123456781138
shlr.l #4,@(0x1234:16,r2l.b) ;01056f2812341138
shlr.l #4,@(0x1234:16,r2.w) ;01066f2812341138
shlr.l #4,@(0x1234:16,er2.l) ;01076f2812341138
shlr.l #4,@(0x12345678:32,r2l.b) ;78a56b28123456781138
shlr.l #4,@(0x12345678:32,r2.w) ;78a66b28123456781138
shlr.l #4,@(0x12345678:32,er2.l) ;78a76b28123456781138
shlr.l #4,@0x1234:16 ;01046b0812341138
shlr.l #4,@0x12345678:32 ;01046b28123456781138
shlr.w #8,r1 ;1161
shlr.w #8,@er1 ;7d901160
shlr.w #8,@(0x6:2,er1) ;015769181160
shlr.w #8,@er1+ ;01546d181160
shlr.w #8,@-er1 ;01576d181160
shlr.w #8,@+er1 ;01556d181160
shlr.w #8,@er1- ;01566d181160
shlr.w #8,@(0x1234:16,er1) ;01546f1812341160
shlr.w #8,@(0x12345678:32,er1) ;78146b28123456781160
shlr.w #8,@(0x1234:16,r2l.b) ;01556f2812341160
shlr.w #8,@(0x1234:16,r2.w) ;01566f2812341160
shlr.w #8,@(0x1234:16,er2.l) ;01576f2812341160
shlr.w #8,@(0x12345678:32,r2l.b) ;78256b28123456781160
shlr.w #8,@(0x12345678:32,r2.w) ;78266b28123456781160
shlr.w #8,@(0x12345678:32,er2.l) ;78276b28123456781160
shlr.w #8,@0x1234:16 ;6b1812341160
shlr.w #8,@0x12345678:32 ;6b38123456781160
shlr.l #8,er1 ;1179
shlr.l #8,@er1 ;010469181178
shlr.l #8,@(0xc:2,er1) ;010769181178
shlr.l #8,@er1+ ;01046d181178
shlr.l #8,@-er1 ;01076d181178
shlr.l #8,@+er1 ;01056d181178
shlr.l #8,@er1- ;01066d181178
shlr.l #8,@(0x1234:16,er1) ;01046f1812341178
shlr.l #8,@(0x12345678:32,er1) ;78946b28123456781178
shlr.l #8,@(0x1234:16,r2l.b) ;01056f2812341178
shlr.l #8,@(0x1234:16,r2.w) ;01066f2812341178
shlr.l #8,@(0x1234:16,er2.l) ;01076f2812341178
shlr.l #8,@(0x12345678:32,r2l.b) ;78a56b28123456781178
shlr.l #8,@(0x12345678:32,r2.w) ;78a66b28123456781178
shlr.l #8,@(0x12345678:32,er2.l) ;78a76b28123456781178
shlr.l #8,@0x1234:16 ;01046b0812341178
shlr.l #8,@0x12345678:32 ;01046b28123456781178
shlr.l #16,er1 ;11f9
shlr.l #16,@er1 ;0104691811f8
shlr.l #16,@(0xc:2,er1) ;0107691811f8
shlr.l #16,@er1+ ;01046d1811f8
shlr.l #16,@-er1 ;01076d1811f8
shlr.l #16,@+er1 ;01056d1811f8
shlr.l #16,@er1- ;01066d1811f8
shlr.l #16,@(0x1234:16,er1) ;01046f18123411f8
shlr.l #16,@(0x12345678:32,er1) ;78946b281234567811f8
shlr.l #16,@(0x1234:16,r2l.b) ;01056f28123411f8
shlr.l #16,@(0x1234:16,r2.w) ;01066f28123411f8
shlr.l #16,@(0x1234:16,er2.l) ;01076f28123411f8
shlr.l #16,@(0x12345678:32,r2l.b) ;78a56b281234567811f8
shlr.l #16,@(0x12345678:32,r2.w) ;78a66b281234567811f8
shlr.l #16,@(0x12345678:32,er2.l) ;78a76b281234567811f8
shlr.l #16,@0x1234:16 ;01046b08123411f8
shlr.l #16,@0x12345678:32 ;01046b281234567811f8
shlr.b #0x7:5,r1h ;03871101
shlr.w #0xf:5,r1 ;038f1111
shlr.l #0x1f:5,er1 ;039f1131
shlr.b r3h,r1h ;78381101
shlr.w r3h,r1 ;78381111
shlr.l r3h,er1 ;78381131
shal.b r1h ;1081
shal.b @er1 ;7d101080
shal.b @(0x3:2,er1) ;017768181080
shal.b @er1+ ;01746c181080
shal.b @-er1 ;01776c181080
shal.b @+er1 ;01756c181080
shal.b @er1- ;01766c181080
shal.b @(0x1234:16,er1) ;01746e1812341080
shal.b @(0x12345678:32,er1) ;78146a28123456781080
shal.b @(0x1234:16,r2l.b) ;01756e2812341080
shal.b @(0x1234:16,r2.w) ;01766e2812341080
shal.b @(0x1234:16,er2.l) ;01776e2812341080
shal.b @(0x12345678:32,r2l.b) ;78256a28123456781080
shal.b @(0x12345678:32,r2.w) ;78266a28123456781080
shal.b @(0x12345678:32,er2.l) ;78276a28123456781080
shal.b @0xffffff12:8 ;7f121080
shal.b @0x1234:16 ;6a1812341080
shal.b @0x12345678:32 ;6a38123456781080
shal.w r1 ;1091
shal.w @er1 ;7d901090
shal.w @(0x6:2,er1) ;015769181090
shal.w @er1+ ;01546d181090
shal.w @-er1 ;01576d181090
shal.w @+er1 ;01556d181090
shal.w @er1- ;01566d181090
shal.w @(0x1234:16,er1) ;01546f1812341090
shal.w @(0x12345678:32,er1) ;78146b28123456781090
shal.w @(0x1234:16,r2l.b) ;01556f2812341090
shal.w @(0x1234:16,r2.w) ;01566f2812341090
shal.w @(0x1234:16,er2.l) ;01576f2812341090
shal.w @(0x12345678:32,r2l.b) ;78256b28123456781090
shal.w @(0x12345678:32,r2.w) ;78266b28123456781090
shal.w @(0x12345678:32,er2.l) ;78276b28123456781090
shal.w @0x1234:16 ;6b1812341090
shal.w @0x12345678:32 ;6b38123456781090
shal.l er1 ;10b1
shal.l @er1 ;0104691810b0
shal.l @(0xc:2,er1) ;0107691810b0
shal.l @er1+ ;01046d1810b0
shal.l @-er1 ;01076d1810b0
shal.l @+er1 ;01056d1810b0
shal.l @er1- ;01066d1810b0
shal.l @(0x1234:16,er1) ;01046f18123410b0
shal.l @(0x12345678:32,er1) ;78946b281234567810b0
shal.l @(0x1234:16,r2l.b) ;01056f28123410b0
shal.l @(0x1234:16,r2.w) ;01066f28123410b0
shal.l @(0x1234:16,er2.l) ;01076f28123410b0
shal.l @(0x12345678:32,r2l.b) ;78a56b281234567810b0
shal.l @(0x12345678:32,r2.w) ;78a66b281234567810b0
shal.l @(0x12345678:32,er2.l) ;78a76b281234567810b0
shal.l @0x1234:16 ;01046b08123410b0
shal.l @0x12345678:32 ;01046b281234567810b0
shal.b #2,r1h ;10c1
shal.b #2,@er1 ;7d1010c0
shal.b #2,@(0x3:2,er1) ;0177681810c0
shal.b #2,@er1+ ;01746c1810c0
shal.b #2,@-er1 ;01776c1810c0
shal.b #2,@+er1 ;01756c1810c0
shal.b #2,@er1- ;01766c1810c0
shal.b #2,@(0x1234:16,er1) ;01746e18123410c0
shal.b #2,@(0x12345678:32,er1) ;78146a281234567810c0
shal.b #2,@(0x1234:16,r2l.b) ;01756e28123410c0
shal.b #2,@(0x1234:16,r2.w) ;01766e28123410c0
shal.b #2,@(0x1234:16,er2.l) ;01776e28123410c0
shal.b #2,@(0x12345678:32,r2l.b) ;78256a281234567810c0
shal.b #2,@(0x12345678:32,r2.w) ;78266a281234567810c0
shal.b #2,@(0x12345678:32,er2.l) ;78276a281234567810c0
shal.b #2,@0xffffff12:8 ;7f1210c0
shal.b #2,@0x1234:16 ;6a18123410c0
shal.b #2,@0x12345678:32 ;6a381234567810c0
shal.w #2,r1 ;10d1
shal.w #2,@er1 ;7d9010d0
shal.w #2,@(0x6:2,er1) ;0157691810d0
shal.w #2,@er1+ ;01546d1810d0
shal.w #2,@-er1 ;01576d1810d0
shal.w #2,@+er1 ;01556d1810d0
shal.w #2,@er1- ;01566d1810d0
shal.w #2,@(0x1234:16,er1) ;01546f18123410d0
shal.w #2,@(0x12345678:32,er1) ;78146b281234567810d0
shal.w #2,@(0x1234:16,r2l.b) ;01556f28123410d0
shal.w #2,@(0x1234:16,r2.w) ;01566f28123410d0
shal.w #2,@(0x1234:16,er2.l) ;01576f28123410d0
shal.w #2,@(0x12345678:32,r2l.b) ;78256b281234567810d0
shal.w #2,@(0x12345678:32,r2.w) ;78266b281234567810d0
shal.w #2,@(0x12345678:32,er2.l) ;78276b281234567810d0
shal.w #2,@0x1234:16 ;6b18123410d0
shal.w #2,@0x12345678:32 ;6b381234567810d0
shal.l #2,er1 ;10f1
shal.l #2,@er1 ;0104691810f0
shal.l #2,@(0xc:2,er1) ;0107691810f0
shal.l #2,@er1+ ;01046d1810f0
shal.l #2,@-er1 ;01076d1810f0
shal.l #2,@+er1 ;01056d1810f0
shal.l #2,@er1- ;01066d1810f0
shal.l #2,@(0x1234:16,er1) ;01046f18123410f0
shal.l #2,@(0x12345678:32,er1) ;78946b281234567810f0
shal.l #2,@(0x1234:16,r2l.b) ;01056f28123410f0
shal.l #2,@(0x1234:16,r2.w) ;01066f28123410f0
shal.l #2,@(0x1234:16,er2.l) ;01076f28123410f0
shal.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567810f0
shal.l #2,@(0x12345678:32,r2.w) ;78a66b281234567810f0
shal.l #2,@(0x12345678:32,er2.l) ;78a76b281234567810f0
shal.l #2,@0x1234:16 ;01046b08123410f0
shal.l #2,@0x12345678:32 ;01046b281234567810f0
shar.b r1h ;1181
shar.b @er1 ;7d101180
shar.b @(0x3:2,er1) ;017768181180
shar.b @er1+ ;01746c181180
shar.b @-er1 ;01776c181180
shar.b @+er1 ;01756c181180
shar.b @er1- ;01766c181180
shar.b @(0x1234:16,er1) ;01746e1812341180
shar.b @(0x12345678:32,er1) ;78146a28123456781180
shar.b @(0x1234:16,r2l.b) ;01756e2812341180
shar.b @(0x1234:16,r2.w) ;01766e2812341180
shar.b @(0x1234:16,er2.l) ;01776e2812341180
shar.b @(0x12345678:32,r2l.b) ;78256a28123456781180
shar.b @(0x12345678:32,r2.w) ;78266a28123456781180
shar.b @(0x12345678:32,er2.l) ;78276a28123456781180
shar.b @0xffffff12:8 ;7f121180
shar.b @0x1234:16 ;6a1812341180
shar.b @0x12345678:32 ;6a38123456781180
shar.w r1 ;1191
shar.w @er1 ;7d901190
shar.w @(0x6:2,er1) ;015769181190
shar.w @er1+ ;01546d181190
shar.w @-er1 ;01576d181190
shar.w @+er1 ;01556d181190
shar.w @er1- ;01566d181190
shar.w @(0x1234:16,er1) ;01546f1812341190
shar.w @(0x12345678:32,er1) ;78146b28123456781190
shar.w @(0x1234:16,r2l.b) ;01556f2812341190
shar.w @(0x1234:16,r2.w) ;01566f2812341190
shar.w @(0x1234:16,er2.l) ;01576f2812341190
shar.w @(0x12345678:32,r2l.b) ;78256b28123456781190
shar.w @(0x12345678:32,r2.w) ;78266b28123456781190
shar.w @(0x12345678:32,er2.l) ;78276b28123456781190
shar.w @0x1234:16 ;6b1812341190
shar.w @0x12345678:32 ;6b38123456781190
shar.l er1 ;11b1
shar.l @er1 ;0104691811b0
shar.l @(0xc:2,er1) ;0107691811b0
shar.l @er1+ ;01046d1811b0
shar.l @-er1 ;01076d1811b0
shar.l @+er1 ;01056d1811b0
shar.l @er1- ;01066d1811b0
shar.l @(0x1234:16,er1) ;01046f18123411b0
shar.l @(0x12345678:32,er1) ;78946b281234567811b0
shar.l @(0x1234:16,r2l.b) ;01056f28123411b0
shar.l @(0x1234:16,r2.w) ;01066f28123411b0
shar.l @(0x1234:16,er2.l) ;01076f28123411b0
shar.l @(0x12345678:32,r2l.b) ;78a56b281234567811b0
shar.l @(0x12345678:32,r2.w) ;78a66b281234567811b0
shar.l @(0x12345678:32,er2.l) ;78a76b281234567811b0
shar.l @0x1234:16 ;01046b08123411b0
shar.l @0x12345678:32 ;01046b281234567811b0
shar.b #2,r1h ;11c1
shar.b #2,@er1 ;7d1011c0
shar.b #2,@(0x3:2,er1) ;0177681811c0
shar.b #2,@er1+ ;01746c1811c0
shar.b #2,@-er1 ;01776c1811c0
shar.b #2,@+er1 ;01756c1811c0
shar.b #2,@er1- ;01766c1811c0
shar.b #2,@(0x1234:16,er1) ;01746e18123411c0
shar.b #2,@(0x12345678:32,er1) ;78146a281234567811c0
shar.b #2,@(0x1234:16,r2l.b) ;01756e28123411c0
shar.b #2,@(0x1234:16,r2.w) ;01766e28123411c0
shar.b #2,@(0x1234:16,er2.l) ;01776e28123411c0
shar.b #2,@(0x12345678:32,r2l.b) ;78256a281234567811c0
shar.b #2,@(0x12345678:32,r2.w) ;78266a281234567811c0
shar.b #2,@(0x12345678:32,er2.l) ;78276a281234567811c0
shar.b #2,@0xffffff12:8 ;7f1211c0
shar.b #2,@0x1234:16 ;6a18123411c0
shar.b #2,@0x12345678:32 ;6a381234567811c0
shar.w #2,r1 ;11d1
shar.w #2,@er1 ;7d9011d0
shar.w #2,@(0x6:2,er1) ;0157691811d0
shar.w #2,@er1+ ;01546d1811d0
shar.w #2,@-er1 ;01576d1811d0
shar.w #2,@+er1 ;01556d1811d0
shar.w #2,@er1- ;01566d1811d0
shar.w #2,@(0x1234:16,er1) ;01546f18123411d0
shar.w #2,@(0x12345678:32,er1) ;78146b281234567811d0
shar.w #2,@(0x1234:16,r2l.b) ;01556f28123411d0
shar.w #2,@(0x1234:16,r2.w) ;01566f28123411d0
shar.w #2,@(0x1234:16,er2.l) ;01576f28123411d0
shar.w #2,@(0x12345678:32,r2l.b) ;78256b281234567811d0
shar.w #2,@(0x12345678:32,r2.w) ;78266b281234567811d0
shar.w #2,@(0x12345678:32,er2.l) ;78276b281234567811d0
shar.w #2,@0x1234:16 ;6b18123411d0
shar.w #2,@0x12345678:32 ;6b381234567811d0
shar.l #2,er1 ;11f1
shar.l #2,@er1 ;0104691811f0
shar.l #2,@(0xc:2,er1) ;0107691811f0
shar.l #2,@er1+ ;01046d1811f0
shar.l #2,@-er1 ;01076d1811f0
shar.l #2,@+er1 ;01056d1811f0
shar.l #2,@er1- ;01066d1811f0
shar.l #2,@(0x1234:16,er1) ;01046f18123411f0
shar.l #2,@(0x12345678:32,er1) ;78946b281234567811f0
shar.l #2,@(0x1234:16,r2l.b) ;01056f28123411f0
shar.l #2,@(0x1234:16,r2.w) ;01066f28123411f0
shar.l #2,@(0x1234:16,er2.l) ;01076f28123411f0
shar.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567811f0
shar.l #2,@(0x12345678:32,r2.w) ;78a66b281234567811f0
shar.l #2,@(0x12345678:32,er2.l) ;78a76b281234567811f0
shar.l #2,@0x1234:16 ;01046b08123411f0
shar.l #2,@0x12345678:32 ;01046b281234567811f0
rotxl.b r1h ;1201
rotxl.b @er1 ;7d101200
rotxl.b @(0x3:2,er1) ;017768181200
rotxl.b @er1+ ;01746c181200
rotxl.b @-er1 ;01776c181200
rotxl.b @+er1 ;01756c181200
rotxl.b @er1- ;01766c181200
rotxl.b @(0x1234:16,er1) ;01746e1812341200
rotxl.b @(0x12345678:32,er1) ;78146a28123456781200
rotxl.b @(0x1234:16,r2l.b) ;01756e2812341200
rotxl.b @(0x1234:16,r2.w) ;01766e2812341200
rotxl.b @(0x1234:16,er2.l) ;01776e2812341200
rotxl.b @(0x12345678:32,r2l.b) ;78256a28123456781200
rotxl.b @(0x12345678:32,r2.w) ;78266a28123456781200
rotxl.b @(0x12345678:32,er2.l) ;78276a28123456781200
rotxl.b @0xffffff12:8 ;7f121200
rotxl.b @0x1234:16 ;6a1812341200
rotxl.b @0x12345678:32 ;6a38123456781200
rotxl.w r1 ;1211
rotxl.w @er1 ;7d901210
rotxl.w @(0x6:2,er1) ;015769181210
rotxl.w @er1+ ;01546d181210
rotxl.w @-er1 ;01576d181210
rotxl.w @+er1 ;01556d181210
rotxl.w @er1- ;01566d181210
rotxl.w @(0x1234:16,er1) ;01546f1812341210
rotxl.w @(0x12345678:32,er1) ;78146b28123456781210
rotxl.w @(0x1234:16,r2l.b) ;01556f2812341210
rotxl.w @(0x1234:16,r2.w) ;01566f2812341210
rotxl.w @(0x1234:16,er2.l) ;01576f2812341210
rotxl.w @(0x12345678:32,r2l.b) ;78256b28123456781210
rotxl.w @(0x12345678:32,r2.w) ;78266b28123456781210
rotxl.w @(0x12345678:32,er2.l) ;78276b28123456781210
rotxl.w @0x1234:16 ;6b1812341210
rotxl.w @0x12345678:32 ;6b38123456781210
rotxl.l er1 ;1231
rotxl.l @er1 ;010469181230
rotxl.l @(0xc:2,er1) ;010769181230
rotxl.l @er1+ ;01046d181230
rotxl.l @-er1 ;01076d181230
rotxl.l @+er1 ;01056d181230
rotxl.l @er1- ;01066d181230
rotxl.l @(0x1234:16,er1) ;01046f1812341230
rotxl.l @(0x12345678:32,er1) ;78946b28123456781230
rotxl.l @(0x1234:16,r2l.b) ;01056f2812341230
rotxl.l @(0x1234:16,r2.w) ;01066f2812341230
rotxl.l @(0x1234:16,er2.l) ;01076f2812341230
rotxl.l @(0x12345678:32,r2l.b) ;78a56b28123456781230
rotxl.l @(0x12345678:32,r2.w) ;78a66b28123456781230
rotxl.l @(0x12345678:32,er2.l) ;78a76b28123456781230
rotxl.l @0x1234:16 ;01046b0812341230
rotxl.l @0x12345678:32 ;01046b28123456781230
rotxl.b #2,r1h ;1241
rotxl.b #2,@er1 ;7d101240
rotxl.b #2,@(0x3:2,er1) ;017768181240
rotxl.b #2,@er1+ ;01746c181240
rotxl.b #2,@-er1 ;01776c181240
rotxl.b #2,@+er1 ;01756c181240
rotxl.b #2,@er1- ;01766c181240
rotxl.b #2,@(0x1234:16,er1) ;01746e1812341240
rotxl.b #2,@(0x12345678:32,er1) ;78146a28123456781240
rotxl.b #2,@(0x1234:16,r2l.b) ;01756e2812341240
rotxl.b #2,@(0x1234:16,r2.w) ;01766e2812341240
rotxl.b #2,@(0x1234:16,er2.l) ;01776e2812341240
rotxl.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781240
rotxl.b #2,@(0x12345678:32,r2.w) ;78266a28123456781240
rotxl.b #2,@(0x12345678:32,er2.l) ;78276a28123456781240
rotxl.b #2,@0xffffff12:8 ;7f121240
rotxl.b #2,@0x1234:16 ;6a1812341240
rotxl.b #2,@0x12345678:32 ;6a38123456781240
rotxl.w #2,r1 ;1251
rotxl.w #2,@er1 ;7d901250
rotxl.w #2,@(0x6:2,er1) ;015769181250
rotxl.w #2,@er1+ ;01546d181250
rotxl.w #2,@-er1 ;01576d181250
rotxl.w #2,@+er1 ;01556d181250
rotxl.w #2,@er1- ;01566d181250
rotxl.w #2,@(0x1234:16,er1) ;01546f1812341250
rotxl.w #2,@(0x12345678:32,er1) ;78146b28123456781250
rotxl.w #2,@(0x1234:16,r2l.b) ;01556f2812341250
rotxl.w #2,@(0x1234:16,r2.w) ;01566f2812341250
rotxl.w #2,@(0x1234:16,er2.l) ;01576f2812341250
rotxl.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781250
rotxl.w #2,@(0x12345678:32,r2.w) ;78266b28123456781250
rotxl.w #2,@(0x12345678:32,er2.l) ;78276b28123456781250
rotxl.w #2,@0x1234:16 ;6b1812341250
rotxl.w #2,@0x12345678:32 ;6b38123456781250
rotxl.l #2,er1 ;1271
rotxl.l #2,@er1 ;010469181270
rotxl.l #2,@(0xc:2,er1) ;010769181270
rotxl.l #2,@er1+ ;01046d181270
rotxl.l #2,@-er1 ;01076d181270
rotxl.l #2,@+er1 ;01056d181270
rotxl.l #2,@er1- ;01066d181270
rotxl.l #2,@(0x1234:16,er1) ;01046f1812341270
rotxl.l #2,@(0x12345678:32,er1) ;78946b28123456781270
rotxl.l #2,@(0x1234:16,r2l.b) ;01056f2812341270
rotxl.l #2,@(0x1234:16,r2.w) ;01066f2812341270
rotxl.l #2,@(0x1234:16,er2.l) ;01076f2812341270
rotxl.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781270
rotxl.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781270
rotxl.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781270
rotxl.l #2,@0x1234:16 ;01046b0812341270
rotxl.l #2,@0x12345678:32 ;01046b28123456781270
rotxr.b r1h ;1301
rotxr.b @er1 ;7d101300
rotxr.b @(0x3:2,er1) ;017768181300
rotxr.b @er1+ ;01746c181300
rotxr.b @-er1 ;01776c181300
rotxr.b @+er1 ;01756c181300
rotxr.b @er1- ;01766c181300
rotxr.b @(0x1234:16,er1) ;01746e1812341300
rotxr.b @(0x12345678:32,er1) ;78146a28123456781300
rotxr.b @(0x1234:16,r2l.b) ;01756e2812341300
rotxr.b @(0x1234:16,r2.w) ;01766e2812341300
rotxr.b @(0x1234:16,er2.l) ;01776e2812341300
rotxr.b @(0x12345678:32,r2l.b) ;78256a28123456781300
rotxr.b @(0x12345678:32,r2.w) ;78266a28123456781300
rotxr.b @(0x12345678:32,er2.l) ;78276a28123456781300
rotxr.b @0xffffff12:8 ;7f121300
rotxr.b @0x1234:16 ;6a1812341300
rotxr.b @0x12345678:32 ;6a38123456781300
rotxr.w r1 ;1311
rotxr.w @er1 ;7d901310
rotxr.w @(0x6:2,er1) ;015769181310
rotxr.w @er1+ ;01546d181310
rotxr.w @-er1 ;01576d181310
rotxr.w @+er1 ;01556d181310
rotxr.w @er1- ;01566d181310
rotxr.w @(0x1234:16,er1) ;01546f1812341310
rotxr.w @(0x12345678:32,er1) ;78146b28123456781310
rotxr.w @(0x1234:16,r2l.b) ;01556f2812341310
rotxr.w @(0x1234:16,r2.w) ;01566f2812341310
rotxr.w @(0x1234:16,er2.l) ;01576f2812341310
rotxr.w @(0x12345678:32,r2l.b) ;78256b28123456781310
rotxr.w @(0x12345678:32,r2.w) ;78266b28123456781310
rotxr.w @(0x12345678:32,er2.l) ;78276b28123456781310
rotxr.w @0x1234:16 ;6b1812341310
rotxr.w @0x12345678:32 ;6b38123456781310
rotxr.l er1 ;1331
rotxr.l @er1 ;010469181330
rotxr.l @(0xc:2,er1) ;010769181330
rotxr.l @er1+ ;01046d181330
rotxr.l @-er1 ;01076d181330
rotxr.l @+er1 ;01056d181330
rotxr.l @er1- ;01066d181330
rotxr.l @(0x1234:16,er1) ;01046f1812341330
rotxr.l @(0x12345678:32,er1) ;78946b28123456781330
rotxr.l @(0x1234:16,r2l.b) ;01056f2812341330
rotxr.l @(0x1234:16,r2.w) ;01066f2812341330
rotxr.l @(0x1234:16,er2.l) ;01076f2812341330
rotxr.l @(0x12345678:32,r2l.b) ;78a56b28123456781330
rotxr.l @(0x12345678:32,r2.w) ;78a66b28123456781330
rotxr.l @(0x12345678:32,er2.l) ;78a76b28123456781330
rotxr.l @0x1234:16 ;01046b0812341330
rotxr.l @0x12345678:32 ;01046b28123456781330
rotxr.b #2,r1h ;1341
rotxr.b #2,@er1 ;7d101340
rotxr.b #2,@(0x3:2,er1) ;017768181340
rotxr.b #2,@er1+ ;01746c181340
rotxr.b #2,@-er1 ;01776c181340
rotxr.b #2,@+er1 ;01756c181340
rotxr.b #2,@er1- ;01766c181340
rotxr.b #2,@(0x1234:16,er1) ;01746e1812341340
rotxr.b #2,@(0x12345678:32,er1) ;78146a28123456781340
rotxr.b #2,@(0x1234:16,r2l.b) ;01756e2812341340
rotxr.b #2,@(0x1234:16,r2.w) ;01766e2812341340
rotxr.b #2,@(0x1234:16,er2.l) ;01776e2812341340
rotxr.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781340
rotxr.b #2,@(0x12345678:32,r2.w) ;78266a28123456781340
rotxr.b #2,@(0x12345678:32,er2.l) ;78276a28123456781340
rotxr.b #2,@0xffffff12:8 ;7f121340
rotxr.b #2,@0x1234:16 ;6a1812341340
rotxr.b #2,@0x12345678:32 ;6a38123456781340
rotxr.w #2,r1 ;1351
rotxr.w #2,@er1 ;7d901350
rotxr.w #2,@(0x6:2,er1) ;015769181350
rotxr.w #2,@er1+ ;01546d181350
rotxr.w #2,@-er1 ;01576d181350
rotxr.w #2,@+er1 ;01556d181350
rotxr.w #2,@er1- ;01566d181350
rotxr.w #2,@(0x1234:16,er1) ;01546f1812341350
rotxr.w #2,@(0x12345678:32,er1) ;78146b28123456781350
rotxr.w #2,@(0x1234:16,r2l.b) ;01556f2812341350
rotxr.w #2,@(0x1234:16,r2.w) ;01566f2812341350
rotxr.w #2,@(0x1234:16,er2.l) ;01576f2812341350
rotxr.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781350
rotxr.w #2,@(0x12345678:32,r2.w) ;78266b28123456781350
rotxr.w #2,@(0x12345678:32,er2.l) ;78276b28123456781350
rotxr.w #2,@0x1234:16 ;6b1812341350
rotxr.w #2,@0x12345678:32 ;6b38123456781350
rotxr.l #2,er1 ;1371
rotxr.l #2,@er1 ;010469181370
rotxr.l #2,@(0xc:2,er1) ;010769181370
rotxr.l #2,@er1+ ;01046d181370
rotxr.l #2,@-er1 ;01076d181370
rotxr.l #2,@+er1 ;01056d181370
rotxr.l #2,@er1- ;01066d181370
rotxr.l #2,@(0x1234:16,er1) ;01046f1812341370
rotxr.l #2,@(0x12345678:32,er1) ;78946b28123456781370
rotxr.l #2,@(0x1234:16,r2l.b) ;01056f2812341370
rotxr.l #2,@(0x1234:16,r2.w) ;01066f2812341370
rotxr.l #2,@(0x1234:16,er2.l) ;01076f2812341370
rotxr.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781370
rotxr.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781370
rotxr.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781370
rotxr.l #2,@0x1234:16 ;01046b0812341370
rotxr.l #2,@0x12345678:32 ;01046b28123456781370
rotl.b r1h ;1281
rotl.b @er1 ;7d101280
rotl.b @(0x3:2,er1) ;017768181280
rotl.b @er1+ ;01746c181280
rotl.b @-er1 ;01776c181280
rotl.b @+er1 ;01756c181280
rotl.b @er1- ;01766c181280
rotl.b @(0x1234:16,er1) ;01746e1812341280
rotl.b @(0x12345678:32,er1) ;78146a28123456781280
rotl.b @(0x1234:16,r2l.b) ;01756e2812341280
rotl.b @(0x1234:16,r2.w) ;01766e2812341280
rotl.b @(0x1234:16,er2.l) ;01776e2812341280
rotl.b @(0x12345678:32,r2l.b) ;78256a28123456781280
rotl.b @(0x12345678:32,r2.w) ;78266a28123456781280
rotl.b @(0x12345678:32,er2.l) ;78276a28123456781280
rotl.b @0xffffff12:8 ;7f121280
rotl.b @0x1234:16 ;6a1812341280
rotl.b @0x12345678:32 ;6a38123456781280
rotl.w r1 ;1291
rotl.w @er1 ;7d901290
rotl.w @(0x6:2,er1) ;015769181290
rotl.w @-er1 ;01576d181290
rotl.w @er1+ ;01546d181290
rotl.w @er1- ;01566d181290
rotl.w @+er1 ;01556d181290
rotl.w @(0x1234:16,er1) ;01546f1812341290
rotl.w @(0x12345678:32,er1) ;78146b28123456781290
rotl.w @(0x1234:16,r2l.b) ;01556f2812341290
rotl.w @(0x1234:16,r2.w) ;01566f2812341290
rotl.w @(0x1234:16,er2.l) ;01576f2812341290
rotl.w @(0x12345678:32,r2l.b) ;78256b28123456781290
rotl.w @(0x12345678:32,r2.w) ;78266b28123456781290
rotl.w @(0x12345678:32,er2.l) ;78276b28123456781290
rotl.w @0x1234:16 ;6b1812341290
rotl.w @0x12345678:32 ;6b38123456781290
rotl.l er1 ;12b1
rotl.l @er1 ;0104691812b0
rotl.l @(0xc:2,er1) ;0107691812b0
rotl.l @er1+ ;01046d1812b0
rotl.l @-er1 ;01076d1812b0
rotl.l @+er1 ;01056d1812b0
rotl.l @er1- ;01066d1812b0
rotl.l @(0x1234:16,er1) ;01046f18123412b0
rotl.l @(0x12345678:32,er1) ;78946b281234567812b0
rotl.l @(0x1234:16,r2l.b) ;01056f28123412b0
rotl.l @(0x1234:16,r2.w) ;01066f28123412b0
rotl.l @(0x1234:16,er2.l) ;01076f28123412b0
rotl.l @(0x12345678:32,r2l.b) ;78a56b281234567812b0
rotl.l @(0x12345678:32,r2.w) ;78a66b281234567812b0
rotl.l @(0x12345678:32,er2.l) ;78a76b281234567812b0
rotl.l @0x1234:16 ;01046b08123412b0
rotl.l @0x12345678:32 ;01046b281234567812b0
rotl.b #2,r1h ;12c1
rotl.b #2,@er1 ;7d1012c0
rotl.b #2,@(0x3:2,er1) ;0177681812c0
rotl.b #2,@er1+ ;01746c1812c0
rotl.b #2,@-er1 ;01776c1812c0
rotl.b #2,@+er1 ;01756c1812c0
rotl.b #2,@er1- ;01766c1812c0
rotl.b #2,@(0x1234:16,er1) ;01746e18123412c0
rotl.b #2,@(0x12345678:32,er1) ;78146a281234567812c0
rotl.b #2,@(0x1234:16,r2l.b) ;01756e28123412c0
rotl.b #2,@(0x1234:16,r2.w) ;01766e28123412c0
rotl.b #2,@(0x1234:16,er2.l) ;01776e28123412c0
rotl.b #2,@(0x12345678:32,r2l.b) ;78256a281234567812c0
rotl.b #2,@(0x12345678:32,r2.w) ;78266a281234567812c0
rotl.b #2,@(0x12345678:32,er2.l) ;78276a281234567812c0
rotl.b #2,@0xffffff12:8 ;7f1212c0
rotl.b #2,@0x1234:16 ;6a18123412c0
rotl.b #2,@0x12345678:32 ;6a381234567812c0
rotl.w #2,r1 ;12d1
rotl.w #2,@er1 ;7d9012d0
rotl.w #2,@(0x6:2,er1) ;0157691812d0
rotl.w #2,@er1+ ;01546d1812d0
rotl.w #2,@-er1 ;01576d1812d0
rotl.w #2,@+er1 ;01556d1812d0
rotl.w #2,@er1- ;01566d1812d0
rotl.w #2,@(0x1234:16,er1) ;01546f18123412d0
rotl.w #2,@(0x12345678:32,er1) ;78146b281234567812d0
rotl.w #2,@(0x1234:16,r2l.b) ;01556f28123412d0
rotl.w #2,@(0x1234:16,r2.w) ;01566f28123412d0
rotl.w #2,@(0x1234:16,er2.l) ;01576f28123412d0
rotl.w #2,@(0x12345678:32,r2l.b) ;78256b281234567812d0
rotl.w #2,@(0x12345678:32,r2.w) ;78266b281234567812d0
rotl.w #2,@(0x12345678:32,er2.l) ;78276b281234567812d0
rotl.w #2,@0x1234:16 ;6b18123412d0
rotl.w #2,@0x12345678:32 ;6b381234567812d0
rotl.l #2,er1 ;12f1
rotl.l #2,@er1 ;0104691812f0
rotl.l #2,@(0xc:2,er1) ;0107691812f0
rotl.l #2,@er1+ ;01046d1812f0
rotl.l #2,@-er1 ;01076d1812f0
rotl.l #2,@+er1 ;01056d1812f0
rotl.l #2,@er1- ;01066d1812f0
rotl.l #2,@(0x1234:16,er1) ;01046f18123412f0
rotl.l #2,@(0x12345678:32,er1) ;78946b281234567812f0
rotl.l #2,@(0x1234:16,r2l.b) ;01056f28123412f0
rotl.l #2,@(0x1234:16,r2.w) ;01066f28123412f0
rotl.l #2,@(0x1234:16,er2.l) ;01076f28123412f0
rotl.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567812f0
rotl.l #2,@(0x12345678:32,r2.w) ;78a66b281234567812f0
rotl.l #2,@(0x12345678:32,er2.l) ;78a76b281234567812f0
rotl.l #2,@0x1234:16 ;01046b08123412f0
rotl.l #2,@0x12345678:32 ;01046b281234567812f0
rotr.b r1h ;1381
rotr.b @er1 ;7d101380
rotr.b @(0x3:2,er1) ;017768181380
rotr.b @er1+ ;01746c181380
rotr.b @-er1 ;01776c181380
rotr.b @+er1 ;01756c181380
rotr.b @er1- ;01766c181380
rotr.b @(0x1234:16,er1) ;01746e1812341380
rotr.b @(0x12345678:32,er1) ;78146a28123456781380
rotr.b @(0x1234:16,r2l.b) ;01756e2812341380
rotr.b @(0x1234:16,r2.w) ;01766e2812341380
rotr.b @(0x1234:16,er2.l) ;01776e2812341380
rotr.b @(0x12345678:32,r2l.b) ;78256a28123456781380
rotr.b @(0x12345678:32,r2.w) ;78266a28123456781380
rotr.b @(0x12345678:32,er2.l) ;78276a28123456781380
rotr.b @0xffffff12:8 ;7f121380
rotr.b @0x1234:16 ;6a1812341380
rotr.b @0x12345678:32 ;6a38123456781380
rotr.w r1 ;1391
rotr.w @er1 ;7d901390
rotr.w @(0x6:2,er1) ;015769181390
rotr.w @-er1 ;01576d181390
rotr.w @er1+ ;01546d181390
rotr.w @er1- ;01566d181390
rotr.w @+er1 ;01556d181390
rotr.w @(0x1234:16,er1) ;01546f1812341390
rotr.w @(0x12345678:32,er1) ;78146b28123456781390
rotr.w @(0x1234:16,r2l.b) ;01556f2812341390
rotr.w @(0x1234:16,r2.w) ;01566f2812341390
rotr.w @(0x1234:16,er2.l) ;01576f2812341390
rotr.w @(0x12345678:32,r2l.b) ;78256b28123456781390
rotr.w @(0x12345678:32,r2.w) ;78266b28123456781390
rotr.w @(0x12345678:32,er2.l) ;78276b28123456781390
rotr.w @0x1234:16 ;6b1812341390
rotr.w @0x12345678:32 ;6b38123456781390
rotr.l er1 ;13b1
rotr.l @er1 ;0104691813b0
rotr.l @(0xc:2,er1) ;0107691813b0
rotr.l @er1+ ;01046d1813b0
rotr.l @-er1 ;01076d1813b0
rotr.l @+er1 ;01056d1813b0
rotr.l @er1- ;01066d1813b0
rotr.l @(0x1234:16,er1) ;01046f18123413b0
rotr.l @(0x12345678:32,er1) ;78946b281234567813b0
rotr.l @(0x1234:16,r2l.b) ;01056f28123413b0
rotr.l @(0x1234:16,r2.w) ;01066f28123413b0
rotr.l @(0x1234:16,er2.l) ;01076f28123413b0
rotr.l @(0x12345678:32,r2l.b) ;78a56b281234567813b0
rotr.l @(0x12345678:32,r2.w) ;78a66b281234567813b0
rotr.l @(0x12345678:32,er2.l) ;78a76b281234567813b0
rotr.l @0x1234:16 ;01046b08123413b0
rotr.l @0x12345678:32 ;01046b281234567813b0
rotr.b #2,r1h ;13c1
rotr.b #2,@er1 ;7d1013c0
rotr.b #2,@(0x3:2,er1) ;0177681813c0
rotr.b #2,@er1+ ;01746c1813c0
rotr.b #2,@-er1 ;01776c1813c0
rotr.b #2,@+er1 ;01756c1813c0
rotr.b #2,@er1- ;01766c1813c0
rotr.b #2,@(0x1234:16,er1) ;01746e18123413c0
rotr.b #2,@(0x12345678:32,er1) ;78146a281234567813c0
rotr.b #2,@(0x1234:16,r2l.b) ;01756e28123413c0
rotr.b #2,@(0x1234:16,r2.w) ;01766e28123413c0
rotr.b #2,@(0x1234:16,er2.l) ;01776e28123413c0
rotr.b #2,@(0x12345678:32,r2l.b) ;78256a281234567813c0
rotr.b #2,@(0x12345678:32,r2.w) ;78266a281234567813c0
rotr.b #2,@(0x12345678:32,er2.l) ;78276a281234567813c0
rotr.b #2,@0xffffff12:8 ;7f1213c0
rotr.b #2,@0x1234:16 ;6a18123413c0
rotr.b #2,@0x12345678:32 ;6a381234567813c0
rotr.w #2,r1 ;13d1
rotr.w #2,@er1 ;7d9013d0
rotr.w #2,@(0x6:2,er1) ;0157691813d0
rotr.w #2,@er1+ ;01546d1813d0
rotr.w #2,@-er1 ;01576d1813d0
rotr.w #2,@+er1 ;01556d1813d0
rotr.w #2,@er1- ;01566d1813d0
rotr.w #2,@(0x1234:16,er1) ;01546f18123413d0
rotr.w #2,@(0x12345678:32,er1) ;78146b281234567813d0
rotr.w #2,@(0x1234:16,r2l.b) ;01556f28123413d0
rotr.w #2,@(0x1234:16,r2.w) ;01566f28123413d0
rotr.w #2,@(0x1234:16,er2.l) ;01576f28123413d0
rotr.w #2,@(0x12345678:32,r2l.b) ;78256b281234567813d0
rotr.w #2,@(0x12345678:32,r2.w) ;78266b281234567813d0
rotr.w #2,@(0x12345678:32,er2.l) ;78276b281234567813d0
rotr.w #2,@0x1234:16 ;6b18123413d0
rotr.w #2,@0x12345678:32 ;6b381234567813d0
rotr.l #2,er1 ;13f1
rotr.l #2,@er1 ;0104691813f0
rotr.l #2,@(0xc:2,er1) ;0107691813f0
rotr.l #2,@er1+ ;01046d1813f0
rotr.l #2,@-er1 ;01076d1813f0
rotr.l #2,@+er1 ;01056d1813f0
rotr.l #2,@er1- ;01066d1813f0
rotr.l #2,@(0x1234:16,er1) ;01046f18123413f0
rotr.l #2,@(0x12345678:32,er1) ;78946b281234567813f0
rotr.l #2,@(0x1234:16,r2l.b) ;01056f28123413f0
rotr.l #2,@(0x1234:16,r2.w) ;01066f28123413f0
rotr.l #2,@(0x1234:16,er2.l) ;01076f28123413f0
rotr.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567813f0
rotr.l #2,@(0x12345678:32,r2.w) ;78a66b281234567813f0
rotr.l #2,@(0x12345678:32,er2.l) ;78a76b281234567813f0
rotr.l #2,@0x1234:16 ;01046b08123413f0
rotr.l #2,@0x12345678:32 ;01046b281234567813f0
.end
|
stsp/binutils-ia16
| 9,266
|
gdb/testsuite/gdb.disasm/am33.s
|
.globl _main
.globl call_tests
.globl movm_tests
.globl misc_tests
.globl mov_tests
.globl ext_tests
.globl add_tests
.globl sub_tests
.globl cmp_tests
.globl logical_tests
.globl shift_tests
.globl muldiv_tests
.globl movbu_tests
.globl movhu_tests
.globl mac_tests
.globl bit_tests
.globl dsp_add_tests
.globl dsp_cmp_tests
.globl dsp_sub_tests
.globl dsp_mov_tests
.globl dsp_logical_tests
.globl dsp_misc_tests
.globl autoincrement_tests
.globl dsp_autoincrement_tests
.text
.am33
_main:
call_tests:
call 256,[a2,a3,exreg0],9
call 256,[a2,a3,exreg1],9
call 256,[a2,a3,exother],9
call 256,[a2,a3,all],9
call 131071,[a2,a3,exreg0],9
call 131071,[a2,a3,exreg1],9
call 131071,[a2,a3,exother],9
call 131071,[a2,a3,all],9
movm_tests:
movm (sp),[a2,a3,exreg0]
movm (sp),[a2,a3,exreg1]
movm (sp),[a2,a3,exother]
movm (sp),[a2,a3,all]
movm [a2,a3,exreg0],(sp)
movm [a2,a3,exreg1],(sp)
movm [a2,a3,exother],(sp)
movm [a2,a3,all],(sp)
movm (usp),[a2,a3,exreg0]
movm (usp),[a2,a3,exreg1]
movm (usp),[a2,a3,exother]
movm (usp),[a2,a3,all]
movm [a2,a3,exreg0],(usp)
movm [a2,a3,exreg1],(usp)
movm [a2,a3,exother],(usp)
movm [a2,a3,all],(usp)
misc_tests:
syscall 0x4
mcst9 d0
mcst48 d1
getchx d0
getclx d1
clr r9
sat16 r9,r8
mcste r7,r6
swap r5,r4
swaph r3,r2
swhw r1,r0
mov_tests:
mov r0,r1
mov xr0, r1
mov r1, xr2
mov (r1),r2
mov r3,(r4)
mov (sp),r5
mov r6,(sp)
mov 16,r1
mov 16,xr1
mov (16,r1),r2
mov r2,(16,r1)
mov (16,sp),r2
mov r2,(16,sp)
mov 0x1ffeff,r2
mov 0x1ffeff,xr2
mov (0x1ffeff,r1),r2
mov r2,(0x1ffeff,r1)
mov (0x1ffeff,sp),r2
mov r2,(0x1ffeff,sp)
mov (0x1ffeff),r2
mov r2,(0x1ffeff)
mov 0x7ffefdfc,r2
mov 0x7ffefdfc,xr2
mov (0x7ffefdfc,r1),r2
mov r2,(0x7ffefdfc,r1)
mov (0x7ffefdfc,sp),r2
mov r2,(0x7ffefdfc,sp)
mov (0x7ffefdfc),r2
mov r2,(0x7ffefdfc)
movu 16,r1
movu 0x1ffeff,r2
movu 0x7ffefdfc,r2
mov usp,a0
mov ssp,a1
mov msp,a2
mov pc,a3
mov a0,usp
mov a1,ssp
mov a2,msp
mov epsw,d0
mov d1,epsw
mov a0,r1
mov d2,r3
mov r5,a1
mov r7,d3
ext_tests:
ext r2
extb r3,r4
extbu r4,r5
exth r6,r7
exthu r7,r8
add_tests:
add r10,r11
add 16,r1
add 0x1ffeff,r2
add 0x7ffefdfc,r2
add r1,r2,r3
addc r12,r13
addc 16,r1
addc 0x1ffeff,r2
addc 0x7ffefdfc,r2
inc r13
inc4 r12
sub_tests:
sub r14,r15
sub 16,r1
sub 0x1ffeff,r2
sub 0x7ffefdfc,r2
subc r15,r14
subc 16,r1
subc 0x1ffeff,r2
subc 0x7ffefdfc,r2
cmp_tests:
cmp r11,r10
cmp 16,r1
cmp 0x1ffeff,r2
cmp 0x7ffefdfc,r2
logical_tests:
and r0,r1
or r2,r3
xor r4,r5
not r6
and 16,r1
or 16,r1
xor 16,r1
and 0x1ffeff,r2
or 0x1ffeff,r2
xor 0x1ffeff,r2
and 0x7ffefdfc,r2
or 0x7ffefdfc,r2
xor 0x7ffefdfc,r2
and 131072,epsw
or 65535,epsw
shift_tests:
asr r7,r8
lsr r9,r10
asl r11,r12
asl2 r13
ror r14
rol r15
asr 16,r1
lsr 16,r1
asl 16,r1
asr 0x1ffeff,r2
lsr 0x1ffeff,r2
asl 0x1ffeff,r2
asr 0x7ffefdfc,r2
lsr 0x7ffefdfc,r2
asl 0x7ffefdfc,r2
muldiv_tests:
mul r1,r2
mulu r3,r4
mul 16,r1
mulu 16,r1
mul 0x1ffeff,r2
mulu 0x1ffeff,r2
mul 0x7ffefdfc,r2
mulu 0x7ffefdfc,r2
div r5,r6
divu r7,r8
dmulh r13,r12
dmulhu r11,r10
dmulh 0x7ffefdfc,r2
dmulhu 0x7ffefdfc,r2
mul r1,r2,r3,r4
mulu r1,r2,r3,r4
movbu_tests:
movbu (r5),r6
movbu r7,(r8)
movbu (sp),r7
movbu r8,(sp)
movbu (16,r1),r2
movbu r2,(16,r1)
movbu (16,sp),r2
movbu r2,(16,sp)
movbu (0x1ffeff,r1),r2
movbu r2,(0x1ffeff,r1)
movbu (0x1ffeff,sp),r2
movbu r2,(0x1ffeff,sp)
movbu (0x1ffeff),r2
movbu r2,(0x1ffeff)
movbu (0x7ffefdfc,r1),r2
movbu r2,(0x7ffefdfc,r1)
movbu (0x7ffefdfc,sp),r2
movbu r2,(0x7ffefdfc,sp)
movbu (0x7ffefdfc),r2
movbu r2,(0x7ffefdfc)
movhu_tests:
movhu (r9),r10
movhu r11,(r12)
movhu (sp),r9
movhu r10,(sp)
movhu (16,r1),r2
movhu r2,(16,r1)
movhu (16,sp),r2
movhu r2,(16,sp)
movhu (0x1ffeff,r1),r2
movhu r2,(0x1ffeff,r1)
movhu (0x1ffeff,sp),r2
movhu r2,(0x1ffeff,sp)
movhu (0x1ffeff),r2
movhu r2,(0x1ffeff)
movhu (0x7ffefdfc,r1),r2
movhu r2,(0x7ffefdfc,r1)
movhu (0x7ffefdfc,sp),r2
movhu r2,(0x7ffefdfc,sp)
movhu (0x7ffefdfc),r2
movhu r2,(0x7ffefdfc)
mac_tests:
mac r1,r2
macu r3,r4
macb r5,r6
macbu r7,r8
mach r9,r10
machu r11,r12
dmach r13,r14
dmachu r15,r14
mac 16,r1
macu 16,r1
macb 16,r1
macbu 16,r1
mach 16,r1
machu 16,r1
mac 0x1ffeff,r2
macu 0x1ffeff,r2
macb 0x1ffeff,r2
macbu 0x1ffeff,r2
mach 0x1ffeff,r2
machu 0x1ffeff,r2
mac 0x7ffefdfc,r2
macu 0x7ffefdfc,r2
macb 0x7ffefdfc,r2
macbu 0x7ffefdfc,r2
mach 0x7ffefdfc,r2
machu 0x7ffefdfc,r2
dmach 0x7ffefdfc,r2
dmachu 0x7ffefdfc,r2
bit_tests:
bsch r1,r2
btst 16,r1
btst 0x1ffeff,r2
btst 0x7ffefdfc,r2
dsp_add_tests:
add_add r4,r1,r2,r3
add_add r4,r1,2,r3
add_sub r4,r1,r2,r3
add_sub r4,r1,2,r3
add_cmp r4,r1,r2,r3
add_cmp r4,r1,2,r3
add_mov r4,r1,r2,r3
add_mov r4,r1,2,r3
add_asr r4,r1,r2,r3
add_asr r4,r1,2,r3
add_lsr r4,r1,r2,r3
add_lsr r4,r1,2,r3
add_asl r4,r1,r2,r3
add_asl r4,r1,2,r3
add_add 4,r1,r2,r3
add_add 4,r1,2,r3
add_sub 4,r1,r2,r3
add_sub 4,r1,2,r3
add_cmp 4,r1,r2,r3
add_cmp 4,r1,2,r3
add_mov 4,r1,r2,r3
add_mov 4,r1,2,r3
add_asr 4,r1,r2,r3
add_asr 4,r1,2,r3
add_lsr 4,r1,r2,r3
add_lsr 4,r1,2,r3
add_asl 4,r1,r2,r3
add_asl 4,r1,2,r3
dsp_cmp_tests:
cmp_add r4,r1,r2,r3
cmp_add r4,r1,2,r3
cmp_sub r4,r1,r2,r3
cmp_sub r4,r1,2,r3
cmp_mov r4,r1,r2,r3
cmp_mov r4,r1,2,r3
cmp_asr r4,r1,r2,r3
cmp_asr r4,r1,2,r3
cmp_lsr r4,r1,r2,r3
cmp_lsr r4,r1,2,r3
cmp_asl r4,r1,r2,r3
cmp_asl r4,r1,2,r3
cmp_add 4,r1,r2,r3
cmp_add 4,r1,2,r3
cmp_sub 4,r1,r2,r3
cmp_sub 4,r1,2,r3
cmp_mov 4,r1,r2,r3
cmp_mov 4,r1,2,r3
cmp_asr 4,r1,r2,r3
cmp_asr 4,r1,2,r3
cmp_lsr 4,r1,r2,r3
cmp_lsr 4,r1,2,r3
cmp_asl 4,r1,r2,r3
cmp_asl 4,r1,2,r3
dsp_sub_tests:
sub_add r4,r1,r2,r3
sub_add r4,r1,2,r3
sub_sub r4,r1,r2,r3
sub_sub r4,r1,2,r3
sub_cmp r4,r1,r2,r3
sub_cmp r4,r1,2,r3
sub_mov r4,r1,r2,r3
sub_mov r4,r1,2,r3
sub_asr r4,r1,r2,r3
sub_asr r4,r1,2,r3
sub_lsr r4,r1,r2,r3
sub_lsr r4,r1,2,r3
sub_asl r4,r1,r2,r3
sub_asl r4,r1,2,r3
sub_add 4,r1,r2,r3
sub_add 4,r1,2,r3
sub_sub 4,r1,r2,r3
sub_sub 4,r1,2,r3
sub_cmp 4,r1,r2,r3
sub_cmp 4,r1,2,r3
sub_mov 4,r1,r2,r3
sub_mov 4,r1,2,r3
sub_asr 4,r1,r2,r3
sub_asr 4,r1,2,r3
sub_lsr 4,r1,r2,r3
sub_lsr 4,r1,2,r3
sub_asl 4,r1,r2,r3
sub_asl 4,r1,2,r3
dsp_mov_tests:
mov_add r4,r1,r2,r3
mov_add r4,r1,2,r3
mov_sub r4,r1,r2,r3
mov_sub r4,r1,2,r3
mov_cmp r4,r1,r2,r3
mov_cmp r4,r1,2,r3
mov_mov r4,r1,r2,r3
mov_mov r4,r1,2,r3
mov_asr r4,r1,r2,r3
mov_asr r4,r1,2,r3
mov_lsr r4,r1,r2,r3
mov_lsr r4,r1,2,r3
mov_asl r4,r1,r2,r3
mov_asl r4,r1,2,r3
mov_add 4,r1,r2,r3
mov_add 4,r1,2,r3
mov_sub 4,r1,r2,r3
mov_sub 4,r1,2,r3
mov_cmp 4,r1,r2,r3
mov_cmp 4,r1,2,r3
mov_mov 4,r1,r2,r3
mov_mov 4,r1,2,r3
mov_asr 4,r1,r2,r3
mov_asr 4,r1,2,r3
mov_lsr 4,r1,r2,r3
mov_lsr 4,r1,2,r3
mov_asl 4,r1,r2,r3
mov_asl 4,r1,2,r3
dsp_logical_tests:
and_add r4,r1,r2,r3
and_add r4,r1,2,r3
and_sub r4,r1,r2,r3
and_sub r4,r1,2,r3
and_cmp r4,r1,r2,r3
and_cmp r4,r1,2,r3
and_mov r4,r1,r2,r3
and_mov r4,r1,2,r3
and_asr r4,r1,r2,r3
and_asr r4,r1,2,r3
and_lsr r4,r1,r2,r3
and_lsr r4,r1,2,r3
and_asl r4,r1,r2,r3
and_asl r4,r1,2,r3
xor_add r4,r1,r2,r3
xor_add r4,r1,2,r3
xor_sub r4,r1,r2,r3
xor_sub r4,r1,2,r3
xor_cmp r4,r1,r2,r3
xor_cmp r4,r1,2,r3
xor_mov r4,r1,r2,r3
xor_mov r4,r1,2,r3
xor_asr r4,r1,r2,r3
xor_asr r4,r1,2,r3
xor_lsr r4,r1,r2,r3
xor_lsr r4,r1,2,r3
xor_asl r4,r1,r2,r3
xor_asl r4,r1,2,r3
or_add r4,r1,r2,r3
or_add r4,r1,2,r3
or_sub r4,r1,r2,r3
or_sub r4,r1,2,r3
or_cmp r4,r1,r2,r3
or_cmp r4,r1,2,r3
or_mov r4,r1,r2,r3
or_mov r4,r1,2,r3
or_asr r4,r1,r2,r3
or_asr r4,r1,2,r3
or_lsr r4,r1,r2,r3
or_lsr r4,r1,2,r3
or_asl r4,r1,r2,r3
or_asl r4,r1,2,r3
dsp_misc_tests:
dmach_add r4,r1,r2,r3
dmach_add r4,r1,2,r3
dmach_sub r4,r1,r2,r3
dmach_sub r4,r1,2,r3
dmach_cmp r4,r1,r2,r3
dmach_cmp r4,r1,2,r3
dmach_mov r4,r1,r2,r3
dmach_mov r4,r1,2,r3
dmach_asr r4,r1,r2,r3
dmach_asr r4,r1,2,r3
dmach_lsr r4,r1,r2,r3
dmach_lsr r4,r1,2,r3
dmach_asl r4,r1,r2,r3
dmach_asl r4,r1,2,r3
swhw_add r4,r1,r2,r3
swhw_add r4,r1,2,r3
swhw_sub r4,r1,r2,r3
swhw_sub r4,r1,2,r3
swhw_cmp r4,r1,r2,r3
swhw_cmp r4,r1,2,r3
swhw_mov r4,r1,r2,r3
swhw_mov r4,r1,2,r3
swhw_asr r4,r1,r2,r3
swhw_asr r4,r1,2,r3
swhw_lsr r4,r1,r2,r3
swhw_lsr r4,r1,2,r3
swhw_asl r4,r1,r2,r3
swhw_asl r4,r1,2,r3
sat16_add r4,r1,r2,r3
sat16_add r4,r1,2,r3
sat16_sub r4,r1,r2,r3
sat16_sub r4,r1,2,r3
sat16_cmp r4,r1,r2,r3
sat16_cmp r4,r1,2,r3
sat16_mov r4,r1,r2,r3
sat16_mov r4,r1,2,r3
sat16_asr r4,r1,r2,r3
sat16_asr r4,r1,2,r3
sat16_lsr r4,r1,r2,r3
sat16_lsr r4,r1,2,r3
sat16_asl r4,r1,r2,r3
sat16_asl r4,r1,2,r3
autoincrement_tests:
mov (r1+),r2
mov r3,(r4+)
movhu (r6+),r7
movhu r8,(r9+)
mov (r1+,64),r2
mov r1,(r2+,64)
movhu (r1+,64),r2
movhu r1,(r2+,64)
mov (r1+,0x1ffef),r2
mov r1,(r2+,0x1ffef)
movhu (r1+,0x1ffef),r2
movhu r1,(r2+,0x1ffef)
mov (r1+,0x7ffefdfc),r2
mov r1,(r2+,0x7ffefdfc)
movhu (r1+,0x7ffefdfc),r2
movhu r1,(r2+,0x7ffefdfc)
dsp_autoincrement_tests:
mov_llt (r1+,4),r2
mov_lgt (r1+,4),r2
mov_lge (r1+,4),r2
mov_lle (r1+,4),r2
mov_lcs (r1+,4),r2
mov_lhi (r1+,4),r2
mov_lcc (r1+,4),r2
mov_lls (r1+,4),r2
mov_leq (r1+,4),r2
mov_lne (r1+,4),r2
mov_lra (r1+,4),r2
|
stsp/binutils-ia16
| 64,432
|
gdb/testsuite/gdb.disasm/t08_or.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;log_1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
or.b #0x12:8,r1h ;c112
or.b #0x12:8,@er1 ;7d10c012
or.b #0x12:8,@(0x3:2,er1) ;01776818c012
or.b #0x12:8,@er1+ ;01746c18c012
or.b #0x12:8,@-er1 ;01776c18c012
or.b #0x12:8,@+er1 ;01756c18c012
or.b #0x12:8,@er1- ;01766c18c012
or.b #0x12:8,@(0x1234:16,er1) ;01746e181234c012
or.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678c012
or.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234c012
or.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234c012
or.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234c012
or.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678c012
or.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678c012
or.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678c012
or.b #0x12:8,@0xffffff12:8 ;7f12c012
or.b #0x12:8,@0x1234:16 ;6a181234c012
or.b #0x12:8,@0x12345678:32 ;6a3812345678c012
or.b r3h,r1h ;1431
or.b r3h,@er1 ;7d101430
or.b r3h,@(0x3:2,er1) ;01793143
or.b r3h,@er1+ ;01798143
or.b r3h,@-er1 ;0179b143
or.b r3h,@+er1 ;01799143
or.b r3h,@er1- ;0179a143
or.b r3h,@(0x1234:16,er1) ;0179c1431234
or.b r3h,@(0x12345678:32,er1) ;0179c94312345678
or.b r3h,@(0x1234:16,r2l.b) ;0179d2431234
or.b r3h,@(0x1234:16,r2.w) ;0179e2431234
or.b r3h,@(0x1234:16,er2.l) ;0179f2431234
or.b r3h,@(0x12345678:32,r2l.b) ;0179da4312345678
or.b r3h,@(0x12345678:32,r2.w) ;0179ea4312345678
or.b r3h,@(0x12345678:32,er2.l) ;0179fa4312345678
or.b r3h,@0xffffff12:8 ;7f121430
or.b r3h,@0x1234:16 ;6a1812341430
or.b r3h,@0x12345678:32 ;6a38123456781430
or.b @er3,r1h ;7c301401
or.b @(0x3:2,er3),r1h ;017a3341
or.b @er3+,r1h ;017a8341
or.b @-er3,r1h ;017ab341
or.b @+er3,r1h ;017a9341
or.b @er3-,r1h ;017aa341
or.b @(0x1234:16,er1),r1h ;017ac1411234
or.b @(0x12345678:32,er1),r1h ;017ac94112345678
or.b @(0x1234:16,r2l.b),r1h ;017ad2411234
or.b @(0x1234:16,r2.w),r1h ;017ae2411234
or.b @(0x1234:16,er2.l),r1h ;017af2411234
or.b @(0x12345678:32,r2l.b),r1h ;017ada4112345678
or.b @(0x12345678:32,r2.w),r1h ;017aea4112345678
or.b @(0x12345678:32,er2.l),r1h ;017afa4112345678
or.b @0xffffff12:8,r1h ;7e121401
or.b @0x1234:16,r1h ;6a1012341401
or.b @0x12345678:32,r1h ;6a30123456781401
or.b @er3,@er1 ;7c350140
or.b @er3,@(3:2,er1) ;7c353140
or.b @er3,@-er1 ;7c35b140
or.b @er3,@er1+ ;7c358140
or.b @er3,@er1- ;7c35a140
or.b @er3,@+er1 ;7c359140
or.b @er3,@(0xffff9abc:16,er1) ;7c35c1409abc
or.b @er3,@(0x9abcdef0:32,er1) ;7c35c9409abcdef0
or.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2409abc
or.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2409abc
or.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2409abc
or.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da409abcdef0
or.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea409abcdef0
or.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa409abcdef0
or.b @er3,@0xffff9abc:16 ;7c3540409abc
or.b @er3,@0x9abcdef0:32 ;7c3548409abcdef0
or.b @-er3,@er1 ;01776c3c0140
or.b @-er3,@(3:2,er1) ;01776c3c3140
or.b @-er3,@-er1 ;01776c3cb140
or.b @-er3,@er1+ ;01776c3c8140
or.b @-er3,@er1- ;01776c3ca140
or.b @-er3,@+er1 ;01776c3c9140
or.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1409abc
or.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9409abcdef0
or.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2409abc
or.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2409abc
or.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2409abc
or.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda409abcdef0
or.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea409abcdef0
or.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa409abcdef0
or.b @-er3,@0xffff9abc:16 ;01776c3c40409abc
or.b @-er3,@0x9abcdef0:32 ;01776c3c48409abcdef0
or.b @er3+,@er1 ;01746c3c0140
or.b @er3+,@(3:2,er1) ;01746c3c3140
or.b @er3+,@-er1 ;01746c3cb140
or.b @er3+,@er1+ ;01746c3c8140
or.b @er3+,@er1- ;01746c3ca140
or.b @er3+,@+er1 ;01746c3c9140
or.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1409abc
or.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9409abcdef0
or.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2409abc
or.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2409abc
or.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2409abc
or.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda409abcdef0
or.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea409abcdef0
or.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa409abcdef0
or.b @er3+,@0xffff9abc:16 ;01746c3c40409abc
or.b @er3+,@0x9abcdef0:32 ;01746c3c48409abcdef0
or.b @er3-,@er1 ;01766c3c0140
or.b @er3-,@(3:2,er1) ;01766c3c3140
or.b @er3-,@-er1 ;01766c3cb140
or.b @er3-,@er1+ ;01766c3c8140
or.b @er3-,@er1- ;01766c3ca140
or.b @er3-,@+er1 ;01766c3c9140
or.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1409abc
or.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9409abcdef0
or.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2409abc
or.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2409abc
or.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2409abc
or.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda409abcdef0
or.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea409abcdef0
or.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa409abcdef0
or.b @er3-,@0xffff9abc:16 ;01766c3c40409abc
or.b @er3-,@0x9abcdef0:32 ;01766c3c48409abcdef0
or.b @+er3,@er1 ;01756c3c0140
or.b @+er3,@(3:2,er1) ;01756c3c3140
or.b @+er3,@-er1 ;01756c3cb140
or.b @+er3,@er1+ ;01756c3c8140
or.b @+er3,@er1- ;01756c3ca140
or.b @+er3,@+er1 ;01756c3c9140
or.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1409abc
or.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9409abcdef0
or.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2409abc
or.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2409abc
or.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2409abc
or.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda409abcdef0
or.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea409abcdef0
or.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa409abcdef0
or.b @+er3,@0xffff9abc:16 ;01756c3c40409abc
or.b @+er3,@0x9abcdef0:32 ;01756c3c48409abcdef0
or.b @(0x1234:16,er3),@er1 ;01746e3c12340140
or.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343140
or.b @(0x1234:16,er3),@-er1 ;01746e3c1234b140
or.b @(0x1234:16,er3),@er1+ ;01746e3c12348140
or.b @(0x1234:16,er3),@er1- ;01746e3c1234a140
or.b @(0x1234:16,er3),@+er1 ;01746e3c12349140
or.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1409abc
or.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9409abcdef0
or.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2409abc
or.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2409abc
or.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2409abc
or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da409abcdef0
or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea409abcdef0
or.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa409abcdef0
or.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440409abc
or.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448409abcdef0
or.b @(0x12345678:32,er3),@er1 ;78346a2c123456780140
or.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783140
or.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b140
or.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788140
or.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a140
or.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789140
or.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1409abc
or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9409abcdef0
or.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2409abc
or.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2409abc
or.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2409abc
or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da409abcdef0
or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea409abcdef0
or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa409abcdef0
or.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840409abc
or.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848409abcdef0
or.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340140
or.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343140
or.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b140
or.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348140
or.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a140
or.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349140
or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1409abc
or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9409abcdef0
or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2409abc
or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2409abc
or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2409abc
or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da409abcdef0
or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea409abcdef0
or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa409abcdef0
or.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440409abc
or.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448409abcdef0
or.b @(0x1234:16,r3.w),@er1 ;01766e3c12340140
or.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343140
or.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b140
or.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348140
or.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a140
or.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349140
or.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1409abc
or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9409abcdef0
or.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2409abc
or.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2409abc
or.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2409abc
or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da409abcdef0
or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea409abcdef0
or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa409abcdef0
or.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440409abc
or.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448409abcdef0
or.b @(0x1234:16,er3.l),@er1 ;01776e3c12340140
or.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343140
or.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b140
or.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348140
or.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a140
or.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349140
or.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1409abc
or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9409abcdef0
or.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2409abc
or.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2409abc
or.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2409abc
or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da409abcdef0
or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea409abcdef0
or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa409abcdef0
or.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440409abc
or.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448409abcdef0
or.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780140
or.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783140
or.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b140
or.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788140
or.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a140
or.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789140
or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1409abc
or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9409abcdef0
or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2409abc
or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2409abc
or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2409abc
or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da409abcdef0
or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea409abcdef0
or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa409abcdef0
or.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840409abc
or.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848409abcdef0
or.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780140
or.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783140
or.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b140
or.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788140
or.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a140
or.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789140
or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1409abc
or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9409abcdef0
or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2409abc
or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2409abc
or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2409abc
or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da409abcdef0
or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea409abcdef0
or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa409abcdef0
or.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840409abc
or.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848409abcdef0
or.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780140
or.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783140
or.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b140
or.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788140
or.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a140
or.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789140
or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1409abc
or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9409abcdef0
or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2409abc
or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2409abc
or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2409abc
or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da409abcdef0
or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea409abcdef0
or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa409abcdef0
or.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840409abc
or.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848409abcdef0
or.b @0x1234:16,@er1 ;6a1512340140
or.b @0x1234:16,@(3:2,er1) ;6a1512343140
or.b @0x1234:16,@-er1 ;6a151234b140
or.b @0x1234:16,@er1+ ;6a1512348140
or.b @0x1234:16,@er1- ;6a151234a140
or.b @0x1234:16,@+er1 ;6a1512349140
or.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1409abc
or.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9409abcdef0
or.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2409abc
or.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2409abc
or.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2409abc
or.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da409abcdef0
or.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea409abcdef0
or.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa409abcdef0
or.b @0x1234:16,@0xffff9abc:16 ;6a15123440409abc
or.b @0x1234:16,@0x9abcdef0:32 ;6a15123448409abcdef0
or.b @0x12345678:32,@er1 ;6a35123456780140
or.b @0x12345678:32,@(3:2,er1) ;6a35123456783140
or.b @0x12345678:32,@-er1 ;6a3512345678b140
or.b @0x12345678:32,@er1+ ;6a35123456788140
or.b @0x12345678:32,@er1- ;6a3512345678a140
or.b @0x12345678:32,@+er1 ;6a35123456789140
or.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1409abc
or.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9409abcdef0
or.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2409abc
or.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2409abc
or.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2409abc
or.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da409abcdef0
or.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea409abcdef0
or.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa409abcdef0
or.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840409abc
or.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848409abcdef0
or.w #0x1234:16,r1 ;79411234
or.w #0x1234:16,@er1 ;015e01401234
or.w #0x1234:16,@(0x6:2,er1) ;015e31401234
or.w #0x1234:16,@er1+ ;015e81401234
or.w #0x1234:16,@-er1 ;015eb1401234
or.w #0x1234:16,@+er1 ;015e91401234
or.w #0x1234:16,@er1- ;015ea1401234
or.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1409abc1234
or.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9409abcdef01234
or.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2409abc1234
or.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2409abc1234
or.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2409abc1234
or.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda409abcdef01234
or.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea409abcdef01234
or.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa409abcdef01234
or.w #0x1234:16,@0xffff9abc:16 ;015e40409abc1234
or.w #0x1234:16,@0x9abcdef0:32 ;015e48409abcdef01234
or.w r3,r1 ;6431
or.w r3,@er1 ;7d906430
or.w r3,@(0x6:2,er1) ;01593143
or.w r3,@er1+ ;01598143
or.w r3,@-er1 ;0159b143
or.w r3,@+er1 ;01599143
or.w r3,@er1- ;0159a143
or.w r3,@(0x1234:16,er1) ;0159c1431234
or.w r3,@(0x12345678:32,er1) ;0159c94312345678
or.w r3,@(0x1234:16,r2l.b) ;0159d2431234
or.w r3,@(0x1234:16,r2.w) ;0159e2431234
or.w r3,@(0x1234:16,er2.l) ;0159f2431234
or.w r3,@(0x12345678:32,r2l.b) ;0159da4312345678
or.w r3,@(0x12345678:32,r2.w) ;0159ea4312345678
or.w r3,@(0x12345678:32,er2.l) ;0159fa4312345678
or.w r3,@0x1234:16 ;6b1812346430
or.w r3,@0x12345678:32 ;6b38123456786430
or.w @er3,r1 ;7cb06401
or.w @(0x6:2,er3),r1 ;015a3341
or.w @er3+,r1 ;015a8341
or.w @-er3,r1 ;015ab341
or.w @+er3,r1 ;015a9341
or.w @er3-,r1 ;015aa341
or.w @(0x1234:16,er1),r1 ;015ac1411234
or.w @(0x12345678:32,er1),r1 ;015ac94112345678
or.w @(0x1234:16,r2l.b),r1 ;015ad2411234
or.w @(0x1234:16,r2.w),r1 ;015ae2411234
or.w @(0x1234:16,er2.l),r1 ;015af2411234
or.w @(0x12345678:32,r2l.b),r1 ;015ada4112345678
or.w @(0x12345678:32,r2.w),r1 ;015aea4112345678
or.w @(0x12345678:32,er2.l),r1 ;015afa4112345678
or.w @0x1234:16,r1 ;6b1012346401
or.w @0x12345678:32,r1 ;6b30123456786401
or.w @er3,@er1 ;7cb50140
or.w @er3,@(6:2,er1) ;7cb53140
or.w @er3,@-er1 ;7cb5b140
or.w @er3,@er1+ ;7cb58140
or.w @er3,@er1- ;7cb5a140
or.w @er3,@+er1 ;7cb59140
or.w @er3,@(0xffff9abc:16,er1) ;7cb5c1409abc
or.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9409abcdef0
or.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2409abc
or.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2409abc
or.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2409abc
or.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da409abcdef0
or.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea409abcdef0
or.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa409abcdef0
or.w @er3,@0xffff9abc:16 ;7cb540409abc
or.w @er3,@0x9abcdef0:32 ;7cb548409abcdef0
or.w @-er3,@er1 ;01576d3c0140
or.w @-er3,@(6:2,er1) ;01576d3c3140
or.w @-er3,@-er1 ;01576d3cb140
or.w @-er3,@er1+ ;01576d3c8140
or.w @-er3,@er1- ;01576d3ca140
or.w @-er3,@+er1 ;01576d3c9140
or.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1409abc
or.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9409abcdef0
or.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2409abc
or.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2409abc
or.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2409abc
or.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda409abcdef0
or.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea409abcdef0
or.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa409abcdef0
or.w @-er3,@0xffff9abc:16 ;01576d3c40409abc
or.w @-er3,@0x9abcdef0:32 ;01576d3c48409abcdef0
or.w @er3+,@er1 ;01546d3c0140
or.w @er3+,@(6:2,er1) ;01546d3c3140
or.w @er3+,@-er1 ;01546d3cb140
or.w @er3+,@er1+ ;01546d3c8140
or.w @er3+,@er1- ;01546d3ca140
or.w @er3+,@+er1 ;01546d3c9140
or.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1409abc
or.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9409abcdef0
or.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2409abc
or.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2409abc
or.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2409abc
or.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda409abcdef0
or.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea409abcdef0
or.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa409abcdef0
or.w @er3+,@0xffff9abc:16 ;01546d3c40409abc
or.w @er3+,@0x9abcdef0:32 ;01546d3c48409abcdef0
or.w @er3-,@er1 ;01566d3c0140
or.w @er3-,@(6:2,er1) ;01566d3c3140
or.w @er3-,@-er1 ;01566d3cb140
or.w @er3-,@er1+ ;01566d3c8140
or.w @er3-,@er1- ;01566d3ca140
or.w @er3-,@+er1 ;01566d3c9140
or.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1409abc
or.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9409abcdef0
or.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2409abc
or.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2409abc
or.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2409abc
or.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda409abcdef0
or.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea409abcdef0
or.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa409abcdef0
or.w @er3-,@0xffff9abc:16 ;01566d3c40409abc
or.w @er3-,@0x9abcdef0:32 ;01566d3c48409abcdef0
or.w @+er3,@er1 ;01556d3c0140
or.w @+er3,@(6:2,er1) ;01556d3c3140
or.w @+er3,@-er1 ;01556d3cb140
or.w @+er3,@er1+ ;01556d3c8140
or.w @+er3,@er1- ;01556d3ca140
or.w @+er3,@+er1 ;01556d3c9140
or.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1409abc
or.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9409abcdef0
or.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2409abc
or.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2409abc
or.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2409abc
or.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda409abcdef0
or.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea409abcdef0
or.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa409abcdef0
or.w @+er3,@0xffff9abc:16 ;01556d3c40409abc
or.w @+er3,@0x9abcdef0:32 ;01556d3c48409abcdef0
or.w @(0x1234:16,er3),@er1 ;01546f3c12340140
or.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343140
or.w @(0x1234:16,er3),@-er1 ;01546f3c1234b140
or.w @(0x1234:16,er3),@er1+ ;01546f3c12348140
or.w @(0x1234:16,er3),@er1- ;01546f3c1234a140
or.w @(0x1234:16,er3),@+er1 ;01546f3c12349140
or.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1409abc
or.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9409abcdef0
or.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2409abc
or.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2409abc
or.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2409abc
or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da409abcdef0
or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea409abcdef0
or.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa409abcdef0
or.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440409abc
or.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448409abcdef0
or.w @(0x12345678:32,er3),@er1 ;78346b2c123456780140
or.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783140
or.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b140
or.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788140
or.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a140
or.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789140
or.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1409abc
or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9409abcdef0
or.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2409abc
or.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2409abc
or.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2409abc
or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da409abcdef0
or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea409abcdef0
or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa409abcdef0
or.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840409abc
or.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848409abcdef0
or.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340140
or.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343140
or.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b140
or.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348140
or.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a140
or.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349140
or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1409abc
or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9409abcdef0
or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2409abc
or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2409abc
or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2409abc
or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da409abcdef0
or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea409abcdef0
or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa409abcdef0
or.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440409abc
or.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448409abcdef0
or.w @(0x1234:16,r3.w),@er1 ;01566f3c12340140
or.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343140
or.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b140
or.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348140
or.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a140
or.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349140
or.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1409abc
or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9409abcdef0
or.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2409abc
or.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2409abc
or.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2409abc
or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da409abcdef0
or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea409abcdef0
or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa409abcdef0
or.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440409abc
or.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448409abcdef0
or.w @(0x1234:16,er3.l),@er1 ;01576f3c12340140
or.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343140
or.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b140
or.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348140
or.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a140
or.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349140
or.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1409abc
or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9409abcdef0
or.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2409abc
or.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2409abc
or.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2409abc
or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da409abcdef0
or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea409abcdef0
or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa409abcdef0
or.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440409abc
or.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448409abcdef0
or.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780140
or.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783140
or.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b140
or.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788140
or.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a140
or.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789140
or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1409abc
or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9409abcdef0
or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2409abc
or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2409abc
or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2409abc
or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da409abcdef0
or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea409abcdef0
or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa409abcdef0
or.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840409abc
or.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848409abcdef0
or.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780140
or.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783140
or.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b140
or.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788140
or.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a140
or.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789140
or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1409abc
or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9409abcdef0
or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2409abc
or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2409abc
or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2409abc
or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da409abcdef0
or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea409abcdef0
or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa409abcdef0
or.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840409abc
or.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848409abcdef0
or.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780140
or.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783140
or.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b140
or.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788140
or.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a140
or.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789140
or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1409abc
or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9409abcdef0
or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2409abc
or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2409abc
or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2409abc
or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da409abcdef0
or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea409abcdef0
or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa409abcdef0
or.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840409abc
or.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848409abcdef0
or.w @0x1234:16,@er1 ;6b1512340140
or.w @0x1234:16,@(6:2,er1) ;6b1512343140
or.w @0x1234:16,@-er1 ;6b151234b140
or.w @0x1234:16,@er1+ ;6b1512348140
or.w @0x1234:16,@er1- ;6b151234a140
or.w @0x1234:16,@+er1 ;6b1512349140
or.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1409abc
or.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9409abcdef0
or.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2409abc
or.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2409abc
or.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2409abc
or.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da409abcdef0
or.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea409abcdef0
or.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa409abcdef0
or.w @0x1234:16,@0xffff9abc:16 ;6b15123440409abc
or.w @0x1234:16,@0x9abcdef0:32 ;6b15123448409abcdef0
or.w @0x12345678:32,@er1 ;6b35123456780140
or.w @0x12345678:32,@(6:2,er1) ;6b35123456783140
or.w @0x12345678:32,@-er1 ;6b3512345678b140
or.w @0x12345678:32,@er1+ ;6b35123456788140
or.w @0x12345678:32,@er1- ;6b3512345678a140
or.w @0x12345678:32,@+er1 ;6b35123456789140
or.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1409abc
or.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9409abcdef0
or.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2409abc
or.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2409abc
or.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2409abc
or.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da409abcdef0
or.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea409abcdef0
or.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa409abcdef0
or.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840409abc
or.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848409abcdef0
or.l #0x12345678:32,er1 ;7a4112345678
or.l #0x1234:16,er1 ;7a491234
or.l #0x12345678:32,@er1 ;010e014812345678
or.l #0x12345678:32,@(0xc:2,er1) ;010e314812345678
or.l #0x12345678:32,@er1+ ;010e814812345678
or.l #0x12345678:32,@-er1 ;010eb14812345678
or.l #0x12345678:32,@+er1 ;010e914812345678
or.l #0x12345678:32,@er1- ;010ea14812345678
or.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1489abc12345678
or.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9489abcdef012345678
or.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2489abc12345678
or.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2489abc12345678
or.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2489abc12345678
or.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda489abcdef012345678
or.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea489abcdef012345678
or.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa489abcdef012345678
or.l #0x12345678:32,@0xffff9abc:16 ;010e40489abc12345678
or.l #0x12345678:32,@0x9abcdef0:32 ;010e48489abcdef012345678
or.l #0x1234:16,@er1 ;010e01401234
or.l #0x1234:16,@(0xc:2,er1) ;010e31401234
or.l #0x1234:16,@er1+ ;010e81401234
or.l #0x1234:16,@-er1 ;010eb1401234
or.l #0x1234:16,@+er1 ;010e91401234
or.l #0x1234:16,@er1- ;010ea1401234
or.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1409abc1234
or.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9409abcdef01234
or.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2409abc1234
or.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2409abc1234
or.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2409abc1234
or.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda409abcdef01234
or.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea409abcdef01234
or.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa409abcdef01234
or.l #0x1234:16,@0xffff9abc:16 ;010e40409abc1234
or.l #0x1234:16,@0x9abcdef0:32 ;010e48409abcdef01234
or.l er3,er1 ;01f06431
or.l er3,@er1 ;01090143
or.l er3,@(0xc:2,er1) ;01093143
or.l er3,@er1+ ;01098143
or.l er3,@-er1 ;0109b143
or.l er3,@+er1 ;01099143
or.l er3,@er1- ;0109a143
or.l er3,@(0x1234:16,er1) ;0109c1431234
or.l er3,@(0x12345678:32,er1) ;0109c94312345678
or.l er3,@(0x1234:16,r2l.b) ;0109d2431234
or.l er3,@(0x1234:16,r2.w) ;0109e2431234
or.l er3,@(0x1234:16,er2.l) ;0109f2431234
or.l er3,@(0x12345678:32,r2l.b) ;0109da4312345678
or.l er3,@(0x12345678:32,r2.w) ;0109ea4312345678
or.l er3,@(0x12345678:32,er2.l) ;0109fa4312345678
or.l er3,@0x1234:16 ;010940431234
or.l er3,@0x12345678:32 ;0109484312345678
or.l @er3,er1 ;010a0341
or.l @(0xc:2,er3),er1 ;010a3341
or.l @er3+,er1 ;010a8341
or.l @-er3,er1 ;010ab341
or.l @+er3,er1 ;010a9341
or.l @er3-,er1 ;010aa341
or.l @(0x1234:16,er1),er1 ;010ac1411234
or.l @(0x12345678:32,er1),er1 ;010ac94112345678
or.l @(0x1234:16,r2l.b),er1 ;010ad2411234
or.l @(0x1234:16,r2.w),er1 ;010ae2411234
or.l @(0x1234:16,er2.l),er1 ;010af2411234
or.l @(0x12345678:32,r2l.b),er1 ;010ada4112345678
or.l @(0x12345678:32,r2.w),er1 ;010aea4112345678
or.l @(0x12345678:32,er2.l),er1 ;010afa4112345678
or.l @0x1234:16,er1 ;010a40411234
or.l @0x12345678:32,er1 ;010a484112345678
or.l @er3,@er1 ;0104693c0140
or.l @er3,@(0xc:2,er1) ;0104693c3140
or.l @er3,@-er1 ;0104693cb140
or.l @er3,@er1+ ;0104693c8140
or.l @er3,@er1- ;0104693ca140
or.l @er3,@+er1 ;0104693c9140
or.l @er3,@(0xffff9abc:16,er1) ;0104693cc1409abc
or.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9409abcdef0
or.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2409abc
or.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2409abc
or.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2409abc
or.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda409abcdef0
or.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea409abcdef0
or.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa409abcdef0
or.l @er3,@0xffff9abc:16 ;0104693c40409abc
or.l @er3,@0x9abcdef0:32 ;0104693c48409abcdef0
or.l @(0xc:2,er3),@er1 ;0107693c0140
or.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3140
or.l @(0xc:2,er3),@-er1 ;0107693cb140
or.l @(0xc:2,er3),@er1+ ;0107693c8140
or.l @(0xc:2,er3),@er1- ;0107693ca140
or.l @(0xc:2,er3),@+er1 ;0107693c9140
or.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1409abc
or.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9409abcdef0
or.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2409abc
or.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2409abc
or.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2409abc
or.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda409abcdef0
or.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea409abcdef0
or.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa409abcdef0
or.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40409abc
or.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48409abcdef0
or.l @-er3,@er1 ;01076d3c0140
or.l @-er3,@(0xc:2,er1) ;01076d3c3140
or.l @-er3,@-er1 ;01076d3cb140
or.l @-er3,@er1+ ;01076d3c8140
or.l @-er3,@er1- ;01076d3ca140
or.l @-er3,@+er1 ;01076d3c9140
or.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1409abc
or.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9409abcdef0
or.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2409abc
or.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2409abc
or.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2409abc
or.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda409abcdef0
or.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea409abcdef0
or.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa409abcdef0
or.l @-er3,@0xffff9abc:16 ;01076d3c40409abc
or.l @-er3,@0x9abcdef0:32 ;01076d3c48409abcdef0
or.l @er3+,@er1 ;01046d3c0140
or.l @er3+,@(0xc:2,er1) ;01046d3c3140
or.l @er3+,@-er1 ;01046d3cb140
or.l @er3+,@er1+ ;01046d3c8140
or.l @er3+,@er1- ;01046d3ca140
or.l @er3+,@+er1 ;01046d3c9140
or.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1409abc
or.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9409abcdef0
or.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2409abc
or.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2409abc
or.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2409abc
or.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda409abcdef0
or.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea409abcdef0
or.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa409abcdef0
or.l @er3+,@0xffff9abc:16 ;01046d3c40409abc
or.l @er3+,@0x9abcdef0:32 ;01046d3c48409abcdef0
or.l @er3-,@er1 ;01066d3c0140
or.l @er3-,@(0xc:2,er1) ;01066d3c3140
or.l @er3-,@-er1 ;01066d3cb140
or.l @er3-,@er1+ ;01066d3c8140
or.l @er3-,@er1- ;01066d3ca140
or.l @er3-,@+er1 ;01066d3c9140
or.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1409abc
or.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9409abcdef0
or.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2409abc
or.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2409abc
or.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2409abc
or.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda409abcdef0
or.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea409abcdef0
or.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa409abcdef0
or.l @er3-,@0xffff9abc:16 ;01066d3c40409abc
or.l @er3-,@0x9abcdef0:32 ;01066d3c48409abcdef0
or.l @+er3,@er1 ;01056d3c0140
or.l @+er3,@(0xc:2,er1) ;01056d3c3140
or.l @+er3,@-er1 ;01056d3cb140
or.l @+er3,@er1+ ;01056d3c8140
or.l @+er3,@er1- ;01056d3ca140
or.l @+er3,@+er1 ;01056d3c9140
or.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1409abc
or.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9409abcdef0
or.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2409abc
or.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2409abc
or.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2409abc
or.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda409abcdef0
or.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea409abcdef0
or.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa409abcdef0
or.l @+er3,@0xffff9abc:16 ;01056d3c40409abc
or.l @+er3,@0x9abcdef0:32 ;01056d3c48409abcdef0
or.l @(0x1234:16,er3),@er1 ;01046f3c12340140
or.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343140
or.l @(0x1234:16,er3),@-er1 ;01046f3c1234b140
or.l @(0x1234:16,er3),@er1+ ;01046f3c12348140
or.l @(0x1234:16,er3),@er1- ;01046f3c1234a140
or.l @(0x1234:16,er3),@+er1 ;01046f3c12349140
or.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1409abc
or.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9409abcdef0
or.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2409abc
or.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2409abc
or.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2409abc
or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da409abcdef0
or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea409abcdef0
or.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa409abcdef0
or.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440409abc
or.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448409abcdef0
or.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780140
or.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783140
or.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b140
or.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788140
or.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a140
or.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789140
or.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1409abc
or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9409abcdef0
or.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2409abc
or.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2409abc
or.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2409abc
or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da409abcdef0
or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea409abcdef0
or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa409abcdef0
or.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840409abc
or.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848409abcdef0
or.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340140
or.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343140
or.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b140
or.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348140
or.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a140
or.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349140
or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1409abc
or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9409abcdef0
or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2409abc
or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2409abc
or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2409abc
or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da409abcdef0
or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea409abcdef0
or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa409abcdef0
or.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440409abc
or.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448409abcdef0
or.l @(0x1234:16,r3.w),@er1 ;01066f3c12340140
or.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343140
or.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b140
or.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348140
or.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a140
or.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349140
or.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1409abc
or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9409abcdef0
or.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2409abc
or.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2409abc
or.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2409abc
or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da409abcdef0
or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea409abcdef0
or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa409abcdef0
or.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440409abc
or.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448409abcdef0
or.l @(0x1234:16,er3.l),@er1 ;01076f3c12340140
or.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343140
or.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b140
or.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348140
or.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a140
or.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349140
or.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1409abc
or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9409abcdef0
or.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2409abc
or.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2409abc
or.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2409abc
or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da409abcdef0
or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea409abcdef0
or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa409abcdef0
or.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440409abc
or.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448409abcdef0
or.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780140
or.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783140
or.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b140
or.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788140
or.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a140
or.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789140
or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1409abc
or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9409abcdef0
or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2409abc
or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2409abc
or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2409abc
or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da409abcdef0
or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea409abcdef0
or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa409abcdef0
or.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840409abc
or.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848409abcdef0
or.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780140
or.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783140
or.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b140
or.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788140
or.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a140
or.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789140
or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1409abc
or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9409abcdef0
or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2409abc
or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2409abc
or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2409abc
or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da409abcdef0
or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea409abcdef0
or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa409abcdef0
or.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840409abc
or.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848409abcdef0
or.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780140
or.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783140
or.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b140
or.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788140
or.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a140
or.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789140
or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1409abc
or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9409abcdef0
or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2409abc
or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2409abc
or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2409abc
or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da409abcdef0
or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea409abcdef0
or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa409abcdef0
or.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840409abc
or.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848409abcdef0
or.l @0x1234:16,@er1 ;01046b0c12340140
or.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343140
or.l @0x1234:16,@-er1 ;01046b0c1234b140
or.l @0x1234:16,@er1+ ;01046b0c12348140
or.l @0x1234:16,@er1- ;01046b0c1234a140
or.l @0x1234:16,@+er1 ;01046b0c12349140
or.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1409abc
or.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9409abcdef0
or.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2409abc
or.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2409abc
or.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2409abc
or.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da409abcdef0
or.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea409abcdef0
or.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa409abcdef0
or.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440409abc
or.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448409abcdef0
or.l @0x12345678:32,@er1 ;01046b2c123456780140
or.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783140
or.l @0x12345678:32,@-er1 ;01046b2c12345678b140
or.l @0x12345678:32,@er1+ ;01046b2c123456788140
or.l @0x12345678:32,@er1- ;01046b2c12345678a140
or.l @0x12345678:32,@+er1 ;01046b2c123456789140
or.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1409abc
or.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9409abcdef0
or.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2409abc
or.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2409abc
or.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2409abc
or.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da409abcdef0
or.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea409abcdef0
or.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa409abcdef0
or.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840409abc
or.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848409abcdef0
.end
|
stsp/binutils-ia16
| 6,912
|
gdb/testsuite/gdb.disasm/t12_bit.s
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;bit
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.h8300sx
.text
.global _start
_start:
bset #0x7,r1h ;7071
bset #0x7,@er1 ;7d107070
bset #0x7,@0xffffff12:8 ;7f127070
bset #0x7,@0x1234:16 ;6a1812347070
bset #0x7,@0x12345678:32 ;6a38123456787070
bset r3h,r1h ;6031
bset r3h,@er1 ;7d106030
bset r3h,@0xffffff12:8 ;7f126030
bset r3h,@0x1234:16 ;6a1812346030
bset r3h,@0x12345678:32 ;6a38123456786030
bset/eq #0x7,@er1 ;7d107077
bset/eq #0x7,@0xffffff12:8 ;7f127077
bset/eq #0x7,@0x1234:16 ;6a1812347077
bset/eq #0x7,@0x12345678:32 ;6a38123456787077
bset/eq r3h,@er1 ;7d106037
bset/eq r3h,@0xffffff12:8 ;7f126037
bset/eq r3h,@0x1234:16 ;6a1812346037
bset/eq r3h,@0x12345678:32 ;6a38123456786037
bset/ne #0x7,@er1 ;7d107076
bset/ne #0x7,@0xffffff12:8 ;7f127076
bset/ne #0x7,@0x1234:16 ;6a1812347076
bset/ne #0x7,@0x12345678:32 ;6a38123456787076
bset/ne r3h,@er1 ;7d106036
bset/ne r3h,@0xffffff12:8 ;7f126036
bset/ne r3h,@0x1234:16 ;6a1812346036
bset/ne r3h,@0x12345678:32 ;6a38123456786036
bnot #0x7,r1h ;7171
bnot #0x7,@er1 ;7d107170
bnot #0x7,@0xffffff12:8 ;7f127170
bnot #0x7,@0x1234:16 ;6a1812347170
bnot #0x7,@0x12345678:32 ;6a38123456787170
bnot r3h,r1h ;6131
bnot r3h,@er1 ;7d106130
bnot r3h,@0xffffff12:8 ;7f126130
bnot r3h,@0x1234:16 ;6a1812346130
bnot r3h,@0x12345678:32 ;6a38123456786130
bclr #0x7,r1h ;7271
bclr #0x7,@er1 ;7d107270
bclr #0x7,@0xffffff12:8 ;7f127270
bclr #0x7,@0x1234:16 ;6a1812347270
bclr #0x7,@0x12345678:32 ;6a38123456787270
bclr r3h,r1h ;6231
bclr r3h,@er1 ;7d106230
bclr r3h,@0xffffff12:8 ;7f126230
bclr r3h,@0x1234:16 ;6a1812346230
bclr r3h,@0x12345678:32 ;6a38123456786230
bclr/eq #0x7,@er1 ;7d107277
bclr/eq #0x7,@0xffffff12:8 ;7f127277
bclr/eq #0x7,@0x1234:16 ;6a1812347277
bclr/eq #0x7,@0x12345678:32 ;6a38123456787277
bclr/eq r3h,@er1 ;7d106237
bclr/eq r3h,@0xffffff12:8 ;7f126237
bclr/eq r3h,@0x1234:16 ;6a1812346237
bclr/eq r3h,@0x12345678:32 ;6a38123456786237
bclr/ne #0x7,@er1 ;7d107276
bclr/ne #0x7,@0xffffff12:8 ;7f127276
bclr/ne #0x7,@0x1234:16 ;6a1812347276
bclr/ne #0x7,@0x12345678:32 ;6a38123456787276
bclr/ne r3h,@er1 ;7d106236
bclr/ne r3h,@0xffffff12:8 ;7f126236
bclr/ne r3h,@0x1234:16 ;6a1812346236
bclr/ne r3h,@0x12345678:32 ;6a38123456786236
btst #0x7,r1h ;7371
btst #0x7,@er1 ;7c107370
btst #0x7,@0xffffff12:8 ;7e127370
btst #0x7,@0x1234:16 ;6a1012347370
btst #0x7,@0x12345678:32 ;6a30123456787370
btst r3h,r1h ;6331
btst r3h,@er1 ;7c106330
btst r3h,@0xffffff12:8 ;7e126330
btst r3h,@0x1234:16 ;6a1012346330
btst r3h,@0x12345678:32 ;6a30123456786330
bor #0x7,r1h ;7471
bor #0x7,@er1 ;7c107470
bor #0x7,@0xffffff12:8 ;7e127470
bor #0x7,@0x1234:16 ;6a1012347470
bor #0x7,@0x12345678:32 ;6a30123456787470
bior #0x7,r1h ;74f1
bior #0x7,@er1 ;7c1074f0
bior #0x7,@0xffffff12:8 ;7e1274f0
bior #0x7,@0x1234:16 ;6a10123474f0
bior #0x7,@0x12345678:32 ;6a301234567874f0
bxor #0x7,r1h ;7571
bxor #0x7,@er1 ;7c107570
bxor #0x7,@0xffffff12:8 ;7e127570
bxor #0x7,@0x1234:16 ;6a1012347570
bxor #0x7,@0x12345678:32 ;6a30123456787570
bixor #0x7,r1h ;75f1
bixor #0x7,@er1 ;7c1075f0
bixor #0x7,@0xffffff12:8 ;7e1275f0
bixor #0x7,@0x1234:16 ;6a10123475f0
bixor #0x7,@0x12345678:32 ;6a301234567875f0
band #0x7,r1h ;7671
band #0x7,@er1 ;7c107670
band #0x7,@0xffffff12:8 ;7e127670
band #0x7,@0x1234:16 ;6a1012347670
band #0x7,@0x12345678:32 ;6a30123456787670
biand #0x7,r1h ;76f1
biand #0x7,@er1 ;7c1076f0
biand #0x7,@0xffffff12:8 ;7e1276f0
biand #0x7,@0x1234:16 ;6a10123476f0
biand #0x7,@0x12345678:32 ;6a301234567876f0
bld #0x7,r1h ;7771
bld #0x7,@er1 ;7c107770
bld #0x7,@0xffffff12:8 ;7e127770
bld #0x7,@0x1234:16 ;6a1012347770
bld #0x7,@0x12345678:32 ;6a30123456787770
bild #0x7,r1h ;77f1
bild #0x7,@er1 ;7c1077f0
bild #0x7,@0xffffff12:8 ;7e1277f0
bild #0x7,@0x1234:16 ;6a10123477f0
bild #0x7,@0x12345678:32 ;6a301234567877f0
bst #0x7,r1h ;6771
bst #0x7,@er1 ;7d106770
bst #0x7,@0xffffff12:8 ;7f126770
bst #0x7,@0x1234:16 ;6a1812346770
bst #0x7,@0x12345678:32 ;6a38123456786770
bstz #0x7,@er1 ;7d106777
bstz #0x7,@0xffffff12:8 ;7f126777
bstz #0x7,@0x1234:16 ;6a1812346777
bstz #0x7,@0x12345678:32 ;6a38123456786777
bist #0x7,r1h ;67f1
bist #0x7,@er1 ;7d1067f0
bist #0x7,@0xffffff12:8 ;7f1267f0
bist #0x7,@0x1234:16 ;6a18123467f0
bist #0x7,@0x12345678:32 ;6a381234567867f0
bistz #0x7,@er1 ;7d1067f7
bistz #0x7,@0xffffff12:8 ;7f1267f7
bistz #0x7,@0x1234:16 ;6a18123467f7
bistz #0x7,@0x12345678:32 ;6a381234567867f7
bfld #0x34:8,@er1,r3h ;7c10f334
bfld #0x34:8,@0xffffff12:8,r3h ;7e12f334
bfld #0x34:8,@0x1234:16,r3h ;6a101234f334
bfld #0x34:8,@0x12345678:32,r3h ;6a3012345678f334
bfst r3h,#0x34:8,@er1 ;7d10f334
bfst r3h,#0x34:8,@0xffffff12:8 ;7f12f334
bfst r3h,#0x34:8,@0x1234:16 ;6a181234f334
bfst r3h,#0x34:8,@0x12345678:32 ;6a3812345678f334
.end
|
stsp/binutils-ia16
| 9,045
|
gdb/testsuite/gdb.mi/mi-reg-undefined.S
|
/* Copyright 2013-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* The FDE entry for "stop_frame" in the .debug_frame section has
been hand modified to mark a set of registers as undefined.
Otherwise this file is as generated by gcc 4.7.2 for x86_64. */
.file "mi-reg-undefined.c"
.text
.Ltext0:
.globl stop_frame
.type stop_frame, @function
stop_frame:
.LFB0:
.file 1 "mi-reg-undefined.c"
.loc 1 18 0
pushq %rbp
.LCFI0:
movq %rsp, %rbp
.LCFI1:
.loc 1 21 0
popq %rbp
.LCFI2:
ret
.LFE0:
.size stop_frame, .-stop_frame
.globl first_frame
.type first_frame, @function
first_frame:
.LFB1:
.loc 1 25 0
pushq %rbp
.LCFI3:
movq %rsp, %rbp
.LCFI4:
.loc 1 26 0
movl $0, %eax
call stop_frame
.loc 1 27 0
popq %rbp
.LCFI5:
ret
.LFE1:
.size first_frame, .-first_frame
.globl main
.type main, @function
main:
.LFB2:
.loc 1 31 0
pushq %rbp
.LCFI6:
movq %rsp, %rbp
.LCFI7:
.loc 1 32 0
movl $0, %eax
call first_frame
.loc 1 34 0
movl $0, %eax
.loc 1 35 0
popq %rbp
.LCFI8:
ret
.LFE2:
.size main, .-main
.section .debug_frame,"",@progbits
.Lframe0:
.long .LECIE0-.LSCIE0
.LSCIE0:
.long 0xffffffff
.byte 0x1
.string ""
.uleb128 0x1
.sleb128 -8
.byte 0x10
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.byte 0x90
.uleb128 0x1
.align 8
.LECIE0:
/* This FDE entry, for stop_frame was modified to mark
registers 0 -> 6 as being undefined. */
.LSFDE0:
.long .LEFDE0-.LASFDE0
.LASFDE0:
.long .Lframe0
.quad .LFB0
.quad .LFE0-.LFB0
/* START OF NEW CONTENT. */
.byte 0x7 /* DW_CFA_undefined */
.uleb128 0x0 /* ULEB128 register */
.byte 0x7 /* DW_CFA_undefined */
.uleb128 0x1 /* ULEB128 register */
.byte 0x7 /* DW_CFA_undefined */
.uleb128 0x2 /* ULEB128 register */
.byte 0x7 /* DW_CFA_undefined */
.uleb128 0x3 /* ULEB128 register */
.byte 0x7 /* DW_CFA_undefined */
.uleb128 0x4 /* ULEB128 register */
.byte 0x7 /* DW_CFA_undefined */
.uleb128 0x5 /* ULEB128 register */
.byte 0x7 /* DW_CFA_undefined */
.uleb128 0x6 /* ULEB128 register */
.byte 0x7 /* DW_CFA_undefined */
.uleb128 0x7 /* ULEB128 register */
/* END OF NEW CONTENT. */
.byte 0x4
.long .LCFI0-.LFB0
.byte 0xe
.uleb128 0x10
.byte 0x86
.uleb128 0x2
.byte 0x4
.long .LCFI1-.LCFI0
.byte 0xd
.uleb128 0x6
.byte 0x4
.long .LCFI2-.LCFI1
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.align 8
.LEFDE0:
.LSFDE2:
.long .LEFDE2-.LASFDE2
.LASFDE2:
.long .Lframe0
.quad .LFB1
.quad .LFE1-.LFB1
.byte 0x4
.long .LCFI3-.LFB1
.byte 0xe
.uleb128 0x10
.byte 0x86
.uleb128 0x2
.byte 0x4
.long .LCFI4-.LCFI3
.byte 0xd
.uleb128 0x6
.byte 0x4
.long .LCFI5-.LCFI4
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.align 8
.LEFDE2:
.LSFDE4:
.long .LEFDE4-.LASFDE4
.LASFDE4:
.long .Lframe0
.quad .LFB2
.quad .LFE2-.LFB2
.byte 0x4
.long .LCFI6-.LFB2
.byte 0xe
.uleb128 0x10
.byte 0x86
.uleb128 0x2
.byte 0x4
.long .LCFI7-.LCFI6
.byte 0xd
.uleb128 0x6
.byte 0x4
.long .LCFI8-.LCFI7
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.align 8
.LEFDE4:
.section .eh_frame,"a",@progbits
.Lframe1:
.long .LECIE1-.LSCIE1
.LSCIE1:
.long 0
.byte 0x1
.string "zR"
.uleb128 0x1
.sleb128 -8
.byte 0x10
.uleb128 0x1
.byte 0x3
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.byte 0x90
.uleb128 0x1
.align 8
.LECIE1:
.LSFDE7:
.long .LEFDE7-.LASFDE7
.LASFDE7:
.long .LASFDE7-.Lframe1
.long .LFB0
.long .LFE0-.LFB0
.uleb128 0
.byte 0x4
.long .LCFI0-.LFB0
.byte 0xe
.uleb128 0x10
.byte 0x86
.uleb128 0x2
.byte 0x4
.long .LCFI1-.LCFI0
.byte 0xd
.uleb128 0x6
.byte 0x4
.long .LCFI2-.LCFI1
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.align 8
.LEFDE7:
.LSFDE9:
.long .LEFDE9-.LASFDE9
.LASFDE9:
.long .LASFDE9-.Lframe1
.long .LFB1
.long .LFE1-.LFB1
.uleb128 0
.byte 0x4
.long .LCFI3-.LFB1
.byte 0xe
.uleb128 0x10
.byte 0x86
.uleb128 0x2
.byte 0x4
.long .LCFI4-.LCFI3
.byte 0xd
.uleb128 0x6
.byte 0x4
.long .LCFI5-.LCFI4
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.align 8
.LEFDE9:
.LSFDE11:
.long .LEFDE11-.LASFDE11
.LASFDE11:
.long .LASFDE11-.Lframe1
.long .LFB2
.long .LFE2-.LFB2
.uleb128 0
.byte 0x4
.long .LCFI6-.LFB2
.byte 0xe
.uleb128 0x10
.byte 0x86
.uleb128 0x2
.byte 0x4
.long .LCFI7-.LCFI6
.byte 0xd
.uleb128 0x6
.byte 0x4
.long .LCFI8-.LCFI7
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.align 8
.LEFDE11:
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0x8c
.value 0x2
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0x1
.long .LASF2
.byte 0x1
.long .LASF3
.long .LASF4
.quad .Ltext0
.quad .Letext0
.long .Ldebug_line0
.uleb128 0x2
.byte 0x1
.long .LASF0
.byte 0x1
.byte 0x11
.quad .LFB0
.quad .LFE0
.long .LLST0
.byte 0x1
.uleb128 0x3
.byte 0x1
.long .LASF1
.byte 0x1
.byte 0x18
.quad .LFB1
.quad .LFE1
.long .LLST1
.byte 0x1
.uleb128 0x4
.byte 0x1
.long .LASF5
.byte 0x1
.byte 0x1e
.long 0x88
.quad .LFB2
.quad .LFE2
.long .LLST2
.byte 0x1
.uleb128 0x5
.byte 0x4
.byte 0x5
.string "int"
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0xe
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.uleb128 0x1b
.uleb128 0xe
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x10
.uleb128 0x6
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0xc
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x40
.uleb128 0x6
.uleb128 0x2117
.uleb128 0xc
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0xc
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x40
.uleb128 0x6
.uleb128 0x2116
.uleb128 0xc
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0xc
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x40
.uleb128 0x6
.uleb128 0x2116
.uleb128 0xc
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.quad .LFB0-.Ltext0
.quad .LCFI0-.Ltext0
.value 0x2
.byte 0x77
.sleb128 8
.quad .LCFI0-.Ltext0
.quad .LCFI1-.Ltext0
.value 0x2
.byte 0x77
.sleb128 16
.quad .LCFI1-.Ltext0
.quad .LCFI2-.Ltext0
.value 0x2
.byte 0x76
.sleb128 16
.quad .LCFI2-.Ltext0
.quad .LFE0-.Ltext0
.value 0x2
.byte 0x77
.sleb128 8
.quad 0
.quad 0
.LLST1:
.quad .LFB1-.Ltext0
.quad .LCFI3-.Ltext0
.value 0x2
.byte 0x77
.sleb128 8
.quad .LCFI3-.Ltext0
.quad .LCFI4-.Ltext0
.value 0x2
.byte 0x77
.sleb128 16
.quad .LCFI4-.Ltext0
.quad .LCFI5-.Ltext0
.value 0x2
.byte 0x76
.sleb128 16
.quad .LCFI5-.Ltext0
.quad .LFE1-.Ltext0
.value 0x2
.byte 0x77
.sleb128 8
.quad 0
.quad 0
.LLST2:
.quad .LFB2-.Ltext0
.quad .LCFI6-.Ltext0
.value 0x2
.byte 0x77
.sleb128 8
.quad .LCFI6-.Ltext0
.quad .LCFI7-.Ltext0
.value 0x2
.byte 0x77
.sleb128 16
.quad .LCFI7-.Ltext0
.quad .LCFI8-.Ltext0
.value 0x2
.byte 0x76
.sleb128 16
.quad .LCFI8-.Ltext0
.quad .LFE2-.Ltext0
.value 0x2
.byte 0x77
.sleb128 8
.quad 0
.quad 0
.section .debug_aranges,"",@progbits
.long 0x2c
.value 0x2
.long .Ldebug_info0
.byte 0x8
.byte 0
.value 0
.value 0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF0:
.string "stop_frame"
.LASF2:
.string "GNU C 4.7.2"
.LASF3:
.string "mi-reg-undefined.c"
.LASF4:
.string "/home/username/src/gdb/testsuite/gdb.mi"
.LASF1:
.string "first_frame"
.LASF5:
.string "main"
.ident "GCC: (GNU) 4.7.2"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 26,100
|
gdb/testsuite/gdb.mi/mi2-amd64-entry-value.s
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2011-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This file is compiled from gdb.mi/mi2-amd64-entry-value.c
using -g -dA -S -O2. */
.file "mi2-amd64-entry-value.c"
.text
.Ltext0:
.p2align 4,,15
.type e, @function
e:
.LFB0:
.file 1 "gdb.mi/mi2-amd64-entry-value.c"
# gdb.mi/mi2-amd64-entry-value.c:22
.loc 1 22 0
.cfi_startproc
.LVL0:
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.mi/mi2-amd64-entry-value.c:23
.loc 1 23 0
movl $0, v(%rip)
# SUCC: EXIT [100.0%]
# gdb.mi/mi2-amd64-entry-value.c:24
.loc 1 24 0
ret
.cfi_endproc
.LFE0:
.size e, .-e
.p2align 4,,15
.type data, @function
data:
.LFB1:
# gdb.mi/mi2-amd64-entry-value.c:28
.loc 1 28 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.mi/mi2-amd64-entry-value.c:30
.loc 1 30 0
movl $10, %eax
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE1:
.size data, .-data
.p2align 4,,15
.type data2, @function
data2:
.LFB2:
# gdb.mi/mi2-amd64-entry-value.c:34
.loc 1 34 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.mi/mi2-amd64-entry-value.c:36
.loc 1 36 0
movl $20, %eax
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE2:
.size data2, .-data2
.p2align 4,,15
.type different, @function
different:
.LFB3:
# gdb.mi/mi2-amd64-entry-value.c:40
.loc 1 40 0
.cfi_startproc
.LVL1:
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
pushq %rbx
.LCFI0:
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
# gdb.mi/mi2-amd64-entry-value.c:41
.loc 1 41 0
leal 1(%rdi), %ebx
.LVL2:
# gdb.mi/mi2-amd64-entry-value.c:42
.loc 1 42 0
cvtsi2sd %ebx, %xmm0
movl %ebx, %edi
call e
.LVL3:
# gdb.mi/mi2-amd64-entry-value.c:43
.loc 1 43 0
#APP
# 43 "gdb.mi/mi2-amd64-entry-value.c" 1
breakhere_different:
# 0 "" 2
# gdb.mi/mi2-amd64-entry-value.c:45
.loc 1 45 0
#NO_APP
movl %ebx, %eax
popq %rbx
.LCFI1:
.cfi_def_cfa_offset 8
.LVL4:
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE3:
.size different, .-different
.p2align 4,,15
.type validity, @function
validity:
.LFB4:
# gdb.mi/mi2-amd64-entry-value.c:49
.loc 1 49 0
.cfi_startproc
.LVL5:
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.mi/mi2-amd64-entry-value.c:51
.loc 1 51 0
xorpd %xmm0, %xmm0
# gdb.mi/mi2-amd64-entry-value.c:49
.loc 1 49 0
pushq %rbx
.LCFI2:
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
# gdb.mi/mi2-amd64-entry-value.c:51
.loc 1 51 0
xorl %edi, %edi
# gdb.mi/mi2-amd64-entry-value.c:49
.loc 1 49 0
movl %esi, %ebx
# gdb.mi/mi2-amd64-entry-value.c:51
.loc 1 51 0
call e
.LVL6:
# gdb.mi/mi2-amd64-entry-value.c:52
.loc 1 52 0
#APP
# 52 "gdb.mi/mi2-amd64-entry-value.c" 1
breakhere_validity:
# 0 "" 2
# gdb.mi/mi2-amd64-entry-value.c:54
.loc 1 54 0
#NO_APP
movl %ebx, %eax
popq %rbx
.LCFI3:
.cfi_def_cfa_offset 8
.LVL7:
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE4:
.size validity, .-validity
.p2align 4,,15
.type invalid, @function
invalid:
.LFB5:
# gdb.mi/mi2-amd64-entry-value.c:58
.loc 1 58 0
.cfi_startproc
.LVL8:
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.mi/mi2-amd64-entry-value.c:59
.loc 1 59 0
xorpd %xmm0, %xmm0
xorl %edi, %edi
.LVL9:
call e
.LVL10:
# gdb.mi/mi2-amd64-entry-value.c:60
.loc 1 60 0
#APP
# 60 "gdb.mi/mi2-amd64-entry-value.c" 1
breakhere_invalid:
# 0 "" 2
# SUCC: EXIT [100.0%]
# gdb.mi/mi2-amd64-entry-value.c:61
.loc 1 61 0
#NO_APP
ret
.cfi_endproc
.LFE5:
.size invalid, .-invalid
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB6:
# gdb.mi/mi2-amd64-entry-value.c:65
.loc 1 65 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.mi/mi2-amd64-entry-value.c:66
.loc 1 66 0
movl $5, %edi
call different
.LVL11:
# gdb.mi/mi2-amd64-entry-value.c:67
.loc 1 67 0
call data
.LVL12:
movl $5, %edi
movl %eax, %esi
call validity
.LVL13:
# gdb.mi/mi2-amd64-entry-value.c:68
.loc 1 68 0
call data2
.LVL14:
movl %eax, %edi
call invalid
.LVL15:
# gdb.mi/mi2-amd64-entry-value.c:70
.loc 1 70 0
xorl %eax, %eax
.p2align 4,,1
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE6:
.size main, .-main
.local v
.comm v,4,4
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0x24e # Length of Compilation Unit Info
.value 0x2 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x8 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF3 # DW_AT_producer: "GNU C 4.7.0 20110912 (experimental)"
.byte 0x1 # DW_AT_language
.long .LASF4 # DW_AT_name: "gdb.mi/mi2-amd64-entry-value.c"
.long .LASF5 # DW_AT_comp_dir: ""
.long .Ldebug_ranges0+0 # DW_AT_ranges
.quad 0 # DW_AT_low_pc
.quad 0 # DW_AT_entry_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x31) DW_TAG_base_type)
.byte 0x8 # DW_AT_byte_size
.byte 0x4 # DW_AT_encoding
.long .LASF0 # DW_AT_name: "double"
.uleb128 0x3 # (DIE (0x38) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.uleb128 0x4 # (DIE (0x3f) DW_TAG_subprogram)
.ascii "e\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x15 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB0 # DW_AT_low_pc
.quad .LFE0 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.byte 0x1 # DW_AT_GNU_all_call_sites
.long 0x74 # DW_AT_sibling
.uleb128 0x5 # (DIE (0x5d) DW_TAG_formal_parameter)
.ascii "i\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x15 # DW_AT_decl_line
.long 0x38 # DW_AT_type
.byte 0x1 # DW_AT_location
.byte 0x55 # DW_OP_reg5
.uleb128 0x5 # (DIE (0x68) DW_TAG_formal_parameter)
.ascii "j\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x15 # DW_AT_decl_line
.long 0x31 # DW_AT_type
.byte 0x1 # DW_AT_location
.byte 0x61 # DW_OP_reg17
.byte 0 # end of children of DIE 0x3f
.uleb128 0x6 # (DIE (0x74) DW_TAG_subprogram)
.long .LASF1 # DW_AT_name: "data"
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x1b # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.long 0x38 # DW_AT_type
.quad .LFB1 # DW_AT_low_pc
.quad .LFE1 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.byte 0x1 # DW_AT_GNU_all_call_sites
.uleb128 0x6 # (DIE (0x94) DW_TAG_subprogram)
.long .LASF2 # DW_AT_name: "data2"
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x21 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.long 0x38 # DW_AT_type
.quad .LFB2 # DW_AT_low_pc
.quad .LFE2 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.byte 0x1 # DW_AT_GNU_all_call_sites
.uleb128 0x7 # (DIE (0xb4) DW_TAG_subprogram)
.long .LASF6 # DW_AT_name: "different"
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x27 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.long 0x38 # DW_AT_type
.quad .LFB3 # DW_AT_low_pc
.quad .LFE3 # DW_AT_high_pc
.long .LLST0 # DW_AT_frame_base
.byte 0x1 # DW_AT_GNU_all_call_sites
.long 0x107 # DW_AT_sibling
.uleb128 0x8 # (DIE (0xd9) DW_TAG_formal_parameter)
.ascii "val\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x27 # DW_AT_decl_line
.long 0x38 # DW_AT_type
.long .LLST1 # DW_AT_location
.uleb128 0x9 # (DIE (0xe8) DW_TAG_GNU_call_site)
.quad .LVL3 # DW_AT_low_pc
.long 0x3f # DW_AT_abstract_origin
.uleb128 0xa # (DIE (0xf5) DW_TAG_GNU_call_site_parameter)
.byte 0x1 # DW_AT_location
.byte 0x55 # DW_OP_reg5
.byte 0x2 # DW_AT_GNU_call_site_value
.byte 0x73 # DW_OP_breg3
.sleb128 0
.uleb128 0xa # (DIE (0xfb) DW_TAG_GNU_call_site_parameter)
.byte 0x1 # DW_AT_location
.byte 0x61 # DW_OP_reg17
.byte 0x6 # DW_AT_GNU_call_site_value
.byte 0x73 # DW_OP_breg3
.sleb128 0
.byte 0xf7 # DW_OP_GNU_convert
.uleb128 0x38
.byte 0xf7 # DW_OP_GNU_convert
.uleb128 0x31
.byte 0 # end of children of DIE 0xe8
.byte 0 # end of children of DIE 0xb4
.uleb128 0x7 # (DIE (0x107) DW_TAG_subprogram)
.long .LASF7 # DW_AT_name: "validity"
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x30 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.long 0x38 # DW_AT_type
.quad .LFB4 # DW_AT_low_pc
.quad .LFE4 # DW_AT_high_pc
.long .LLST2 # DW_AT_frame_base
.byte 0x1 # DW_AT_GNU_all_call_sites
.long 0x16d # DW_AT_sibling
.uleb128 0xb # (DIE (0x12c) DW_TAG_formal_parameter)
.long .LASF8 # DW_AT_name: "lost"
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x30 # DW_AT_decl_line
.long 0x38 # DW_AT_type
.long .LLST3 # DW_AT_location
.uleb128 0xb # (DIE (0x13b) DW_TAG_formal_parameter)
.long .LASF9 # DW_AT_name: "born"
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x30 # DW_AT_decl_line
.long 0x38 # DW_AT_type
.long .LLST4 # DW_AT_location
.uleb128 0x9 # (DIE (0x14a) DW_TAG_GNU_call_site)
.quad .LVL6 # DW_AT_low_pc
.long 0x3f # DW_AT_abstract_origin
.uleb128 0xa # (DIE (0x157) DW_TAG_GNU_call_site_parameter)
.byte 0x1 # DW_AT_location
.byte 0x55 # DW_OP_reg5
.byte 0x1 # DW_AT_GNU_call_site_value
.byte 0x30 # DW_OP_lit0
.uleb128 0xa # (DIE (0x15c) DW_TAG_GNU_call_site_parameter)
.byte 0x1 # DW_AT_location
.byte 0x61 # DW_OP_reg17
.byte 0xb # DW_AT_GNU_call_site_value
.byte 0xf4 # DW_OP_GNU_const_type
.uleb128 0x31
.byte 0x8
.long 0 # fp or vector constant word 0
.long 0 # fp or vector constant word 1
.byte 0 # end of children of DIE 0x14a
.byte 0 # end of children of DIE 0x107
.uleb128 0xc # (DIE (0x16d) DW_TAG_subprogram)
.long .LASF10 # DW_AT_name: "invalid"
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x39 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB5 # DW_AT_low_pc
.quad .LFE5 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.byte 0x1 # DW_AT_GNU_all_call_sites
.long 0x1bf # DW_AT_sibling
.uleb128 0x8 # (DIE (0x18d) DW_TAG_formal_parameter)
.ascii "inv\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x39 # DW_AT_decl_line
.long 0x38 # DW_AT_type
.long .LLST5 # DW_AT_location
.uleb128 0x9 # (DIE (0x19c) DW_TAG_GNU_call_site)
.quad .LVL10 # DW_AT_low_pc
.long 0x3f # DW_AT_abstract_origin
.uleb128 0xa # (DIE (0x1a9) DW_TAG_GNU_call_site_parameter)
.byte 0x1 # DW_AT_location
.byte 0x55 # DW_OP_reg5
.byte 0x1 # DW_AT_GNU_call_site_value
.byte 0x30 # DW_OP_lit0
.uleb128 0xa # (DIE (0x1ae) DW_TAG_GNU_call_site_parameter)
.byte 0x1 # DW_AT_location
.byte 0x61 # DW_OP_reg17
.byte 0xb # DW_AT_GNU_call_site_value
.byte 0xf4 # DW_OP_GNU_const_type
.uleb128 0x31
.byte 0x8
.long 0 # fp or vector constant word 0
.long 0 # fp or vector constant word 1
.byte 0 # end of children of DIE 0x19c
.byte 0 # end of children of DIE 0x16d
.uleb128 0xd # (DIE (0x1bf) DW_TAG_subprogram)
.byte 0x1 # DW_AT_external
.long .LASF11 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x40 # DW_AT_decl_line
.long 0x38 # DW_AT_type
.quad .LFB6 # DW_AT_low_pc
.quad .LFE6 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.byte 0x1 # DW_AT_GNU_all_call_sites
.long 0x239 # DW_AT_sibling
.uleb128 0xe # (DIE (0x1e3) DW_TAG_GNU_call_site)
.quad .LVL11 # DW_AT_low_pc
.long 0xb4 # DW_AT_abstract_origin
.long 0x1fa # DW_AT_sibling
.uleb128 0xa # (DIE (0x1f4) DW_TAG_GNU_call_site_parameter)
.byte 0x1 # DW_AT_location
.byte 0x55 # DW_OP_reg5
.byte 0x1 # DW_AT_GNU_call_site_value
.byte 0x35 # DW_OP_lit5
.byte 0 # end of children of DIE 0x1e3
.uleb128 0xf # (DIE (0x1fa) DW_TAG_GNU_call_site)
.quad .LVL12 # DW_AT_low_pc
.long 0x74 # DW_AT_abstract_origin
.uleb128 0xe # (DIE (0x207) DW_TAG_GNU_call_site)
.quad .LVL13 # DW_AT_low_pc
.long 0x107 # DW_AT_abstract_origin
.long 0x21e # DW_AT_sibling
.uleb128 0xa # (DIE (0x218) DW_TAG_GNU_call_site_parameter)
.byte 0x1 # DW_AT_location
.byte 0x55 # DW_OP_reg5
.byte 0x1 # DW_AT_GNU_call_site_value
.byte 0x35 # DW_OP_lit5
.byte 0 # end of children of DIE 0x207
.uleb128 0xf # (DIE (0x21e) DW_TAG_GNU_call_site)
.quad .LVL14 # DW_AT_low_pc
.long 0x94 # DW_AT_abstract_origin
.uleb128 0xf # (DIE (0x22b) DW_TAG_GNU_call_site)
.quad .LVL15 # DW_AT_low_pc
.long 0x16d # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x1bf
.uleb128 0x10 # (DIE (0x239) DW_TAG_variable)
.ascii "v\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.mi/mi2-amd64-entry-value.c)
.byte 0x12 # DW_AT_decl_line
.long 0x24c # DW_AT_type
.byte 0x9 # DW_AT_location
.byte 0x3 # DW_OP_addr
.quad v
.uleb128 0x11 # (DIE (0x24c) DW_TAG_volatile_type)
.long 0x38 # DW_AT_type
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x52 # (DW_AT_entry_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x6 # (DW_FORM_data4)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x5 # (TAG: DW_TAG_formal_parameter)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0xa # (DW_FORM_block1)
.byte 0
.byte 0
.uleb128 0x6 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0xc # (DW_FORM_flag)
.byte 0
.byte 0
.uleb128 0x7 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x8 # (abbrev code)
.uleb128 0x5 # (TAG: DW_TAG_formal_parameter)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0x6 # (DW_FORM_data4)
.byte 0
.byte 0
.uleb128 0x9 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0x1 # DW_children_yes
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0xa # (abbrev code)
.uleb128 0x410a # (TAG: DW_TAG_GNU_call_site_parameter)
.byte 0 # DW_children_no
.uleb128 0x2 # (DW_AT_location)
.uleb128 0xa # (DW_FORM_block1)
.uleb128 0x2111 # (DW_AT_GNU_call_site_value)
.uleb128 0xa # (DW_FORM_block1)
.byte 0
.byte 0
.uleb128 0xb # (abbrev code)
.uleb128 0x5 # (TAG: DW_TAG_formal_parameter)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0x6 # (DW_FORM_data4)
.byte 0
.byte 0
.uleb128 0xc # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0xd # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3f # (DW_AT_external)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0xe # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0x1 # DW_children_yes
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0xf # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x10 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0xa # (DW_FORM_block1)
.byte 0
.byte 0
.uleb128 0x11 # (abbrev code)
.uleb128 0x35 # (TAG: DW_TAG_volatile_type)
.byte 0 # DW_children_no
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.quad .LFB3 # Location list begin address (*.LLST0)
.quad .LCFI0 # Location list end address (*.LLST0)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 8
.quad .LCFI0 # Location list begin address (*.LLST0)
.quad .LCFI1 # Location list end address (*.LLST0)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 16
.quad .LCFI1 # Location list begin address (*.LLST0)
.quad .LFE3 # Location list end address (*.LLST0)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 8
.quad 0 # Location list terminator begin (*.LLST0)
.quad 0 # Location list terminator end (*.LLST0)
.LLST1:
.quad .LVL1 # Location list begin address (*.LLST1)
.quad .LVL2 # Location list end address (*.LLST1)
.value 0x1 # Location expression size
.byte 0x55 # DW_OP_reg5
.quad .LVL2 # Location list begin address (*.LLST1)
.quad .LVL4 # Location list end address (*.LLST1)
.value 0x1 # Location expression size
.byte 0x53 # DW_OP_reg3
.quad .LVL4 # Location list begin address (*.LLST1)
.quad .LFE3 # Location list end address (*.LLST1)
.value 0x1 # Location expression size
.byte 0x50 # DW_OP_reg0
.quad 0 # Location list terminator begin (*.LLST1)
.quad 0 # Location list terminator end (*.LLST1)
.LLST2:
.quad .LFB4 # Location list begin address (*.LLST2)
.quad .LCFI2 # Location list end address (*.LLST2)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 8
.quad .LCFI2 # Location list begin address (*.LLST2)
.quad .LCFI3 # Location list end address (*.LLST2)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 16
.quad .LCFI3 # Location list begin address (*.LLST2)
.quad .LFE4 # Location list end address (*.LLST2)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 8
.quad 0 # Location list terminator begin (*.LLST2)
.quad 0 # Location list terminator end (*.LLST2)
.LLST3:
.quad .LVL5 # Location list begin address (*.LLST3)
.quad .LVL5 # Location list end address (*.LLST3)
.value 0x1 # Location expression size
.byte 0x55 # DW_OP_reg5
.quad 0 # Location list terminator begin (*.LLST3)
.quad 0 # Location list terminator end (*.LLST3)
.LLST4:
.quad .LVL5 # Location list begin address (*.LLST4)
.quad .LVL6-1 # Location list end address (*.LLST4)
.value 0x1 # Location expression size
.byte 0x54 # DW_OP_reg4
.quad .LVL6-1 # Location list begin address (*.LLST4)
.quad .LVL7 # Location list end address (*.LLST4)
.value 0x1 # Location expression size
.byte 0x53 # DW_OP_reg3
.quad .LVL7 # Location list begin address (*.LLST4)
.quad .LFE4 # Location list end address (*.LLST4)
.value 0x1 # Location expression size
.byte 0x50 # DW_OP_reg0
.quad 0 # Location list terminator begin (*.LLST4)
.quad 0 # Location list terminator end (*.LLST4)
.LLST5:
.quad .LVL8 # Location list begin address (*.LLST5)
.quad .LVL9 # Location list end address (*.LLST5)
.value 0x1 # Location expression size
.byte 0x55 # DW_OP_reg5
.quad .LVL9 # Location list begin address (*.LLST5)
.quad .LFE5 # Location list end address (*.LLST5)
.value 0x4 # Location expression size
.byte 0xf3 # DW_OP_GNU_entry_value
.uleb128 0x1
.byte 0x55 # DW_OP_reg5
.byte 0x9f # DW_OP_stack_value
.quad 0 # Location list terminator begin (*.LLST5)
.quad 0 # Location list terminator end (*.LLST5)
.section .debug_aranges,"",@progbits
.long 0x3c # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x8 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 16 byte boundary
.value 0
.quad .Ltext0 # Address
.quad .Letext0-.Ltext0 # Length
.quad .LFB6 # Address
.quad .LFE6-.LFB6 # Length
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0 # Offset 0
.quad .Letext0
.quad .LFB6 # Offset 0x10
.quad .LFE6
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF2:
.string "data2"
.LASF3:
.string "GNU C 4.7.0 20110912 (experimental)"
.LASF4:
.string "gdb.mi/mi2-amd64-entry-value.c"
.LASF9:
.string "born"
.LASF6:
.string "different"
.LASF7:
.string "validity"
.LASF10:
.string "invalid"
.LASF0:
.string "double"
.LASF11:
.string "main"
.LASF1:
.string "data"
.LASF8:
.string "lost"
.LASF5:
.string ""
.ident "GCC: (GNU) 4.7.0 20110912 (experimental)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 5,418
|
gdb/testsuite/gdb.mi/dw2-ref-missing-frame.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2007-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Debug information */
.section .debug_info
.Lcu1_begin:
/* CU header */
.4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */
.Lcu1_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev1_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.4byte cu_text_end /* DW_AT_high_pc */
.4byte cu_text_start /* DW_AT_low_pc */
.ascii "file1.txt\0" /* DW_AT_name */
.ascii "GNU C 3.3.3\0" /* DW_AT_producer */
.byte 1 /* DW_AT_language (C) */
.Ltype_int:
.uleb128 3 /* Abbrev: DW_TAG_base_type */
.ascii "int\0" /* DW_AT_name */
.byte 4 /* DW_AT_byte_size */
.byte 5 /* DW_AT_encoding */
/* func_nofb */
.uleb128 5 /* Abbrev: DW_TAG_subprogram (no fb) */
.ascii "func_nofb\0" /* DW_AT_name */
.4byte func_nofb_start /* DW_AT_low_pc */
.4byte func_nofb_end /* DW_AT_high_pc */
.uleb128 7 /* Abbrev: DW_TAG_variable (location) */
.ascii "func_nofb_var\0" /* DW_AT_name */
.byte 2f - 1f /* DW_AT_location */
1: .byte 0x91 /* DW_OP_fbreg */
.sleb128 0 /* 0 */
2: .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.uleb128 7 /* Abbrev: DW_TAG_variable (location) */
.ascii "func_nofb_var2\0" /* DW_AT_name */
.byte 2f - 1f /* DW_AT_location */
1: .byte 0x91 /* DW_OP_fbreg */
.sleb128 0 /* 0 */
2: .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.byte 0 /* End of children of func */
/* func_loopfb */
.uleb128 6 /* Abbrev: DW_TAG_subprogram (loop fb) */
.ascii "func_loopfb\0" /* DW_AT_name */
.4byte func_loopfb_start /* DW_AT_low_pc */
.4byte func_loopfb_end /* DW_AT_high_pc */
.byte 2f - 1f /* DW_AT_frame_base */
1: .byte 0x91 /* DW_OP_fbreg */
.sleb128 0 /* 0 */
2:
.uleb128 7 /* Abbrev: DW_TAG_variable (location) */
.ascii "func_loopfb_var\0" /* DW_AT_name */
.byte 2f - 1f /* DW_AT_location */
1: .byte 0x91 /* DW_OP_fbreg */
.sleb128 0 /* 0 */
2: .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.uleb128 7 /* Abbrev: DW_TAG_variable (location) */
.ascii "func_loopfb_var2\0" /* DW_AT_name */
.byte 2f - 1f /* DW_AT_location */
1: .byte 0x91 /* DW_OP_fbreg */
.sleb128 0 /* 0 */
2: .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.byte 0 /* End of children of func */
.byte 0 /* End of children of CU */
.Lcu1_end:
/* Abbrev table */
.section .debug_abbrev
.Labbrev1_begin:
.uleb128 1 /* Abbrev code */
.uleb128 0x11 /* DW_TAG_compile_unit */
.byte 1 /* has_children */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x25 /* DW_AT_producer */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x13 /* DW_AT_language */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 3 /* Abbrev code */
.uleb128 0x24 /* DW_TAG_base_type */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0xb /* DW_AT_byte_size */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3e /* DW_AT_encoding */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 5 /* Abbrev code */
.uleb128 0x2e /* DW_TAG_subprogram (no fb) */
.byte 1 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 6 /* Abbrev code */
.uleb128 0x2e /* DW_TAG_subprogram (loop fb) */
.byte 1 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x40 /* DW_AT_frame_base */
.uleb128 0xa /* DW_FORM_block1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 7 /* Abbrev code (location) */
.uleb128 0x34 /* DW_TAG_variable */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x2 /* DW_AT_location */
.uleb128 0xa /* DW_FORM_block1 */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
|
stsp/binutils-ia16
| 6,399
|
gdb/testsuite/gdb.linespec/break-asm-file1.s
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2004-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
.text
.Lbegin_text1:
.globl _func3
_func3:
.globl func3
.type func3, %function
func3:
.Lbegin_func3:
nop
nop
.Lend_func3:
.size func3, .-func3
_func:
.type func, %function
func:
.Lbegin_func:
nop
.Lfunc_1:
nop
.Lfunc_2:
nop
.Lend_func:
.size func, .-func
.Lend_text1:
/* Debug information */
.section .debug_info
.Lcu1_begin:
/* CU header */
.4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */
.Lcu1_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev1_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.4byte .Lline1_begin /* DW_AT_stmt_list */
.4byte .Lend_text1 /* DW_AT_high_pc */
.4byte .Lbegin_text1 /* DW_AT_low_pc */
.ascii "b/break-asm-file0.s\0" /* DW_AT_name */
.ascii "GNU C 3.3.3\0" /* DW_AT_producer */
.2byte 0x8001 /* DW_AT_language (Mips Assembler) */
/* func3 */
.uleb128 2 /* Abbrev: DW_TAG_subprogram */
.byte 1 /* DW_AT_external */
.byte 1 /* DW_AT_decl_file */
.byte 2 /* DW_AT_decl_line */
.ascii "func3\0" /* DW_AT_name */
.4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.4byte .Lbegin_func3 /* DW_AT_low_pc */
.4byte .Lend_func3 /* DW_AT_high_pc */
.byte 1 /* DW_AT_frame_base: length */
.byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */
/* func */
.uleb128 2 /* Abbrev: DW_TAG_subprogram */
.byte 0 /* DW_AT_external */
.byte 1 /* DW_AT_decl_file */
.byte 4 /* DW_AT_decl_line */
.ascii "func\0" /* DW_AT_name */
.4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.4byte .Lbegin_func /* DW_AT_low_pc */
.4byte .Lend_func /* DW_AT_high_pc */
.byte 1 /* DW_AT_frame_base: length */
.byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */
.Ltype_int:
.uleb128 3 /* Abbrev: DW_TAG_base_type */
.ascii "int\0" /* DW_AT_name */
.byte 4 /* DW_AT_byte_size */
.byte 5 /* DW_AT_encoding */
.byte 0 /* End of children of CU */
.Lcu1_end:
/* Abbrev table */
.section .debug_abbrev
.Labbrev1_begin:
.uleb128 1 /* Abbrev code */
.uleb128 0x11 /* DW_TAG_compile_unit */
.byte 1 /* has_children */
.uleb128 0x10 /* DW_AT_stmt_list */
.uleb128 0x6 /* DW_FORM_data4 */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x25 /* DW_AT_producer */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x13 /* DW_AT_language */
.uleb128 0x5 /* DW_FORM_data2 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 2 /* Abbrev code */
.uleb128 0x2e /* DW_TAG_subprogram */
.byte 0 /* has_children */
.uleb128 0x3f /* DW_AT_external */
.uleb128 0xc /* DW_FORM_flag */
.uleb128 0x3a /* DW_AT_decl_file */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3b /* DW_AT_decl_line */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x40 /* DW_AT_frame_base */
.uleb128 0xa /* DW_FORM_block1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 3 /* Abbrev code */
.uleb128 0x24 /* DW_TAG_base_type */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0xb /* DW_AT_byte_size */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3e /* DW_AT_encoding */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
/* Line table */
.section .debug_line
.Lline1_begin:
.4byte .Lline1_end - .Lline1_start /* Initial length */
.Lline1_start:
.2byte 2 /* Version */
.4byte .Lline1_lines - .Lline1_hdr /* header_length */
.Lline1_hdr:
.byte 1 /* Minimum insn length */
.byte 1 /* default_is_stmt */
.byte 1 /* line_base */
.byte 1 /* line_range */
.byte 0x10 /* opcode_base */
/* Standard lengths */
.byte 0
.byte 1
.byte 1
.byte 1
.byte 1
.byte 0
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 0
/* Include directories */
.byte 0
/* File names */
.ascii "b/break-asm-file0.s\0"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.Lline1_lines:
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func3
.byte 3 /* DW_LNS_advance_line */
.sleb128 1 /* ... to 2 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func3+1
.byte 3 /* DW_LNS_advance_line */
.sleb128 1 /* ... to 3 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func
.byte 3 /* DW_LNS_advance_line */
.sleb128 4 /* ... to 7 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lfunc_1
/* A line number entry for the same line (7) denotes the end */
/* of prologue. */
.byte 3 /* DW_LNS_advance_line */
.sleb128 0 /* ... to 7 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lfunc_2
.byte 3 /* DW_LNS_advance_line */
.sleb128 1 /* ... to 8 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lend_func
.byte 0 /* DW_LNE_end_of_sequence */
.uleb128 1
.byte 1
.Lline1_end:
|
stsp/binutils-ia16
| 5,483
|
gdb/testsuite/gdb.linespec/break-asm-file0.s
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2004-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
.file "a/break-asm-file0.s"
.text
.Lbegin_text1:
.globl _func2
_func2:
.globl func2
.type func2, %function
func2:
.Lbegin_func2:
nop
nop
.Lend_func2:
.size func2, .-func2
.globl _func
_func:
.globl func
.type func, %function
func:
.Lbegin_func:
.file 1 "a/break-asm-file0.s"
nop
.Lfunc_1:
nop
.Lfunc_2:
nop
.Lend_func:
.size func, .-func
.Lend_text1:
/* Debug information */
.section .debug_info
.Lcu1_begin:
/* CU header */
.4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */
.Lcu1_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev1_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.4byte .Lline1_begin /* DW_AT_stmt_list */
.4byte .Lend_text1 /* DW_AT_high_pc */
.4byte .Lbegin_text1 /* DW_AT_low_pc */
.ascii "a/break-asm-file0.s\0" /* DW_AT_name */
.ascii "GNU C 3.3.3\0" /* DW_AT_producer */
.2byte 0x8001 /* DW_AT_language (Mips Assembler) */
.byte 0 /* End of children of CU */
.Lcu1_end:
/* Abbrev table */
.section .debug_abbrev
.Labbrev1_begin:
.uleb128 1 /* Abbrev code */
.uleb128 0x11 /* DW_TAG_compile_unit */
.byte 1 /* has_children */
.uleb128 0x10 /* DW_AT_stmt_list */
.uleb128 0x6 /* DW_FORM_data4 */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x25 /* DW_AT_producer */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x13 /* DW_AT_language */
.uleb128 0x5 /* DW_FORM_data2 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 2 /* Abbrev code */
.uleb128 0x2e /* DW_TAG_subprogram */
.byte 0 /* has_children */
.uleb128 0x3f /* DW_AT_external */
.uleb128 0xc /* DW_FORM_flag */
.uleb128 0x3a /* DW_AT_decl_file */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3b /* DW_AT_decl_line */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x40 /* DW_AT_frame_base */
.uleb128 0xa /* DW_FORM_block1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 3 /* Abbrev code */
.uleb128 0x24 /* DW_TAG_base_type */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0xb /* DW_AT_byte_size */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3e /* DW_AT_encoding */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
/* Line table */
.section .debug_line
.Lline1_begin:
.4byte .Lline1_end - .Lline1_start /* Initial length */
.Lline1_start:
.2byte 2 /* Version */
.4byte .Lline1_lines - .Lline1_hdr /* header_length */
.Lline1_hdr:
.byte 1 /* Minimum insn length */
.byte 1 /* default_is_stmt */
.byte 1 /* line_base */
.byte 1 /* line_range */
.byte 0x10 /* opcode_base */
/* Standard lengths */
.byte 0
.byte 1
.byte 1
.byte 1
.byte 1
.byte 0
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 0
/* Include directories */
.byte 0
/* File names */
.ascii "a/break-asm-file0.s\0"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.Lline1_lines:
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func2
.byte 3 /* DW_LNS_advance_line */
.sleb128 1 /* ... to 2 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func2+1
.byte 3 /* DW_LNS_advance_line */
.sleb128 1 /* ... to 3 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func
.byte 3 /* DW_LNS_advance_line */
.sleb128 4 /* ... to 7 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lfunc_1
/* A line number entry for the same line (7) denotes the end */
/* of prologue. */
.byte 3 /* DW_LNS_advance_line */
.sleb128 0 /* ... to 7 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lfunc_2
.byte 3 /* DW_LNS_advance_line */
.sleb128 1 /* ... to 8 */
.byte 1 /* DW_LNS_copy */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lend_func
.byte 0 /* DW_LNE_end_of_sequence */
.uleb128 1
.byte 1
.Lline1_end:
|
stsp/binutils-ia16
| 1,903
|
gdb/testsuite/gdb.asm/asmsrc1.s
|
.include "common.inc"
.include "arch.inc"
comment "WARNING: asm-source.exp checks for line numbers printed by gdb."
comment "Be careful about changing this file without also changing"
comment "asm-source.exp."
comment "This file is not linked with crt0."
comment "Provide very simplistic equivalent."
.global _start
gdbasm_declare _start
gdbasm_startup
gdbasm_call main
gdbasm_exit0
gdbasm_end _start
comment "Displaced stepping requires scratch space at _start"
comment "at least as large as the largest instruction. No"
comment "breakpoints should be set within the scratch space."
gdbasm_several_nops
gdbasm_several_nops
gdbasm_several_nops
gdbasm_several_nops
gdbasm_several_nops
gdbasm_several_nops
gdbasm_several_nops
gdbasm_several_nops
comment "main routine for assembly source debugging test"
comment "This particular testcase uses macros in <arch>.inc to achieve"
comment "machine independence."
.global main
gdbasm_declare main
comment "mark: main enter"
gdbasm_enter
comment "Call a macro that consists of several lines of assembler code."
comment "mark: main start"
gdbasm_several_nops
comment "Call a subroutine in another file."
comment "mark: call foo2"
gdbasm_call foo2
comment "All done."
comment "mark: main exit"
gdbasm_exit0
gdbasm_end main
comment "mark: search"
comment "A routine for foo2 to call."
.global foo3
gdbasm_declare foo3
gdbasm_enter
comment "mark: foo3 start"
gdbasm_leave
gdbasm_end foo3
.global exit
gdbasm_declare exit
gdbasm_exit0
gdbasm_end exit
comment "A static function"
gdbasm_declare foostatic
gdbasm_enter
gdbasm_leave
gdbasm_end foostatic
comment "A global variable"
.global globalvar
gdbasm_datavar globalvar 11
comment "A static variable"
gdbasm_datavar staticvar 5
.include "note.inc"
|
stsp/binutils-ia16
| 8,843
|
gdb/testsuite/gdb.reverse/singlejmp-reverse.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2012-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This source file was generated by:
gcc -o gdb.reverse/singlejmp-reverse.S gdb.reverse/singlejmp-reverse.c -Wall -S -dA -O2 -g
*/
.file "singlejmp-reverse.c"
.text
.Ltext0:
.p2align 4,,15
.type g, @function
g:
.LFB0:
.file 1 "gdb.reverse/singlejmp-reverse.c"
# gdb.reverse/singlejmp-reverse.c:22
.loc 1 22 0
.cfi_startproc
# basic block 2
# gdb.reverse/singlejmp-reverse.c:23
.loc 1 23 0
movl $2, v(%rip)
# gdb.reverse/singlejmp-reverse.c:24
.loc 1 24 0
ret
.cfi_endproc
.LFE0:
.size g, .-g
.p2align 4,,15
.type f, @function
f:
.LFB1:
# gdb.reverse/singlejmp-reverse.c:28
.loc 1 28 0
.cfi_startproc
# basic block 2
# gdb.reverse/singlejmp-reverse.c:29
.loc 1 29 0
jmp g
.cfi_endproc
.LFE1:
.size f, .-f
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB2:
# gdb.reverse/singlejmp-reverse.c:36
.loc 1 36 0
.cfi_startproc
# basic block 2
subq $8, %rsp
.LCFI0:
.cfi_def_cfa_offset 16
# gdb.reverse/singlejmp-reverse.c:37
.loc 1 37 0
movl $1, v(%rip)
# gdb.reverse/singlejmp-reverse.c:38
.loc 1 38 0
call f
# gdb.reverse/singlejmp-reverse.c:39
.loc 1 39 0
call nodebug
# gdb.reverse/singlejmp-reverse.c:40
.loc 1 40 0
movl $3, v(%rip)
# gdb.reverse/singlejmp-reverse.c:42
.loc 1 42 0
xorl %eax, %eax
addq $8, %rsp
.LCFI1:
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2:
.size main, .-main
.comm v,4,4
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0xa1 # Length of Compilation Unit Info
.value 0x2 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x8 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF0 # DW_AT_producer: "GNU C 4.6.4 20120911 (prerelease)"
.byte 0x1 # DW_AT_language
.long .LASF1 # DW_AT_name: "gdb.reverse/singlejmp-reverse.c"
.long .LASF2 # DW_AT_comp_dir: ""
.quad 0 # DW_AT_low_pc
.quad 0 # DW_AT_entry_pc
.long .Ldebug_ranges0+0 # DW_AT_ranges
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x31) DW_TAG_subprogram)
.ascii "g\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.reverse/singlejmp-reverse.c)
.byte 0x15 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB0 # DW_AT_low_pc
.quad .LFE0 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.uleb128 0x2 # (DIE (0x4a) DW_TAG_subprogram)
.ascii "f\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.reverse/singlejmp-reverse.c)
.byte 0x1b # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB1 # DW_AT_low_pc
.quad .LFE1 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.uleb128 0x3 # (DIE (0x63) DW_TAG_subprogram)
.byte 0x1 # DW_AT_external
.long .LASF3 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (gdb.reverse/singlejmp-reverse.c)
.byte 0x23 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.long 0x84 # DW_AT_type
.quad .LFB2 # DW_AT_low_pc
.quad .LFE2 # DW_AT_high_pc
.long .LLST0 # DW_AT_frame_base
.uleb128 0x4 # (DIE (0x84) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.uleb128 0x5 # (DIE (0x8b) DW_TAG_variable)
.ascii "v\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.reverse/singlejmp-reverse.c)
.byte 0x12 # DW_AT_decl_line
.long 0x9f # DW_AT_type
.byte 0x1 # DW_AT_external
.byte 0x9 # DW_AT_location
.byte 0x3 # DW_OP_addr
.quad v
.uleb128 0x6 # (DIE (0x9f) DW_TAG_volatile_type)
.long 0x84 # DW_AT_type
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x52 # (DW_AT_entry_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x6 # (DW_FORM_data4)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3f # (DW_AT_external)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0x6 # (DW_FORM_data4)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x3f # (DW_AT_external)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0xa # (DW_FORM_block1)
.byte 0
.byte 0
.uleb128 0x6 # (abbrev code)
.uleb128 0x35 # (TAG: DW_TAG_volatile_type)
.byte 0 # DW_children_no
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.quad .LFB2 # Location list begin address (*.LLST0)
.quad .LCFI0 # Location list end address (*.LLST0)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 8
.quad .LCFI0 # Location list begin address (*.LLST0)
.quad .LCFI1 # Location list end address (*.LLST0)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 16
.quad .LCFI1 # Location list begin address (*.LLST0)
.quad .LFE2 # Location list end address (*.LLST0)
.value 0x2 # Location expression size
.byte 0x77 # DW_OP_breg7
.sleb128 8
.quad 0 # Location list terminator begin (*.LLST0)
.quad 0 # Location list terminator end (*.LLST0)
.section .debug_aranges,"",@progbits
.long 0x3c # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x8 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 16 byte boundary
.value 0
.quad .Ltext0 # Address
.quad .Letext0-.Ltext0 # Length
.quad .LFB2 # Address
.quad .LFE2-.LFB2 # Length
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0 # Offset 0
.quad .Letext0
.quad .LFB2 # Offset 0x10
.quad .LFE2
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF3:
.string "main"
.LASF0:
.string "GNU C 4.6.4 20120911 (prerelease)"
.LASF2:
.string ""
.LASF1:
.string "gdb.reverse/singlejmp-reverse.c"
.ident "GCC: (GNU) 4.6.4 20120911 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 1,198
|
gdb/testsuite/gdb.reverse/singlejmp-reverse-nodebug.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2012-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This source file was generated by:
gcc -o gdb.reverse/singlejmp-reverse-nodebug.S gdb.reverse/singlejmp-reverse-nodebug.c -Wall -S -O2
*/
.file "singlejmp-reverse-nodebug.c"
.text
.p2align 4,,15
.globl nodebug
.type nodebug, @function
nodebug:
.LFB0:
.cfi_startproc
# basic block 2
rep
ret
.cfi_endproc
.LFE0:
.size nodebug, .-nodebug
.ident "GCC: (GNU) 4.6.4 20120911 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 10,325
|
gdb/testsuite/gdb.reverse/amd64-tailcall-reverse.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2012-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This source file was generated by:
gcc -o gdb.reverse/amd64-tailcall-reverse.S gdb.reverse/amd64-tailcall-reverse.c -Wall -S -dA -O2 -g
*/
.file "amd64-tailcall-reverse.c"
.text
.Ltext0:
.p2align 4,,15
.type g, @function
g:
.LFB0:
.file 1 "gdb.reverse/amd64-tailcall-reverse.c"
# gdb.reverse/amd64-tailcall-reverse.c:22
.loc 1 22 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.reverse/amd64-tailcall-reverse.c:23
.loc 1 23 0
movl $2, v(%rip)
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE0:
.size g, .-g
.p2align 4,,15
.type f, @function
f:
.LFB1:
# gdb.reverse/amd64-tailcall-reverse.c:28
.loc 1 28 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.reverse/amd64-tailcall-reverse.c:29
.loc 1 29 0
jmp g
# SUCC: EXIT [100.0%] (ab,sibcall)
.LVL0:
.cfi_endproc
.LFE1:
.size f, .-f
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB2:
# gdb.reverse/amd64-tailcall-reverse.c:34
.loc 1 34 0
.cfi_startproc
# BLOCK 2 freq:10000 seq:0
# PRED: ENTRY [100.0%] (fallthru)
# gdb.reverse/amd64-tailcall-reverse.c:35
.loc 1 35 0
movl $1, v(%rip)
# gdb.reverse/amd64-tailcall-reverse.c:36
.loc 1 36 0
call f
.LVL1:
# gdb.reverse/amd64-tailcall-reverse.c:37
.loc 1 37 0
movl $3, v(%rip)
# gdb.reverse/amd64-tailcall-reverse.c:39
.loc 1 39 0
xorl %eax, %eax
# SUCC: EXIT [100.0%]
ret
.cfi_endproc
.LFE2:
.size main, .-main
.comm v,4,4
.text
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0xc8 # Length of Compilation Unit Info
.value 0x2 # DWARF version number
.long .Ldebug_abbrev0 # Offset Into Abbrev. Section
.byte 0x8 # Pointer Size (in bytes)
.uleb128 0x1 # (DIE (0xb) DW_TAG_compile_unit)
.long .LASF0 # DW_AT_producer: "GNU C 4.7.2 20120911 (prerelease)"
.byte 0x1 # DW_AT_language
.long .LASF1 # DW_AT_name: "gdb.reverse/amd64-tailcall-reverse.c"
.long .LASF2 # DW_AT_comp_dir: ""
.long .Ldebug_ranges0+0 # DW_AT_ranges
.quad 0 # DW_AT_low_pc
.quad 0 # DW_AT_entry_pc
.long .Ldebug_line0 # DW_AT_stmt_list
.uleb128 0x2 # (DIE (0x31) DW_TAG_subprogram)
.ascii "g\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.reverse/amd64-tailcall-reverse.c)
.byte 0x15 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB0 # DW_AT_low_pc
.quad .LFE0 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.byte 0x1 # DW_AT_GNU_all_call_sites
.uleb128 0x3 # (DIE (0x4b) DW_TAG_subprogram)
.ascii "f\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.reverse/amd64-tailcall-reverse.c)
.byte 0x1b # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.quad .LFB1 # DW_AT_low_pc
.quad .LFE1 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.byte 0x1 # DW_AT_GNU_all_call_sites
.long 0x78 # DW_AT_sibling
.uleb128 0x4 # (DIE (0x69) DW_TAG_GNU_call_site)
.quad .LVL0 # DW_AT_low_pc
.byte 0x1 # DW_AT_GNU_tail_call
.long 0x31 # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x4b
.uleb128 0x5 # (DIE (0x78) DW_TAG_subprogram)
.byte 0x1 # DW_AT_external
.long .LASF3 # DW_AT_name: "main"
.byte 0x1 # DW_AT_decl_file (gdb.reverse/amd64-tailcall-reverse.c)
.byte 0x21 # DW_AT_decl_line
.byte 0x1 # DW_AT_prototyped
.long 0xab # DW_AT_type
.quad .LFB2 # DW_AT_low_pc
.quad .LFE2 # DW_AT_high_pc
.byte 0x2 # DW_AT_frame_base
.byte 0x77 # DW_OP_breg7
.sleb128 8
.byte 0x1 # DW_AT_GNU_all_call_sites
.long 0xab # DW_AT_sibling
.uleb128 0x6 # (DIE (0x9d) DW_TAG_GNU_call_site)
.quad .LVL1 # DW_AT_low_pc
.long 0x4b # DW_AT_abstract_origin
.byte 0 # end of children of DIE 0x78
.uleb128 0x7 # (DIE (0xab) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
.uleb128 0x8 # (DIE (0xb2) DW_TAG_variable)
.ascii "v\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.reverse/amd64-tailcall-reverse.c)
.byte 0x12 # DW_AT_decl_line
.long 0xc6 # DW_AT_type
.byte 0x1 # DW_AT_external
.byte 0x9 # DW_AT_location
.byte 0x3 # DW_OP_addr
.quad v
.uleb128 0x9 # (DIE (0xc6) DW_TAG_volatile_type)
.long 0xab # DW_AT_type
.byte 0 # end of children of DIE 0xb
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.uleb128 0x1 # (abbrev code)
.uleb128 0x11 # (TAG: DW_TAG_compile_unit)
.byte 0x1 # DW_children_yes
.uleb128 0x25 # (DW_AT_producer)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x13 # (DW_AT_language)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x1b # (DW_AT_comp_dir)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x55 # (DW_AT_ranges)
.uleb128 0x6 # (DW_FORM_data4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x52 # (DW_AT_entry_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x10 # (DW_AT_stmt_list)
.uleb128 0x6 # (DW_FORM_data4)
.byte 0
.byte 0
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0xc # (DW_FORM_flag)
.byte 0
.byte 0
.uleb128 0x3 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x4 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x2115 # (DW_AT_GNU_tail_call)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x5 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
.uleb128 0x3f # (DW_AT_external)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0xe # (DW_FORM_strp)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x27 # (DW_AT_prototyped)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x12 # (DW_AT_high_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x40 # (DW_AT_frame_base)
.uleb128 0xa # (DW_FORM_block1)
.uleb128 0x2117 # (DW_AT_GNU_all_call_sites)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x1 # (DW_AT_sibling)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x6 # (abbrev code)
.uleb128 0x4109 # (TAG: DW_TAG_GNU_call_site)
.byte 0 # DW_children_no
.uleb128 0x11 # (DW_AT_low_pc)
.uleb128 0x1 # (DW_FORM_addr)
.uleb128 0x31 # (DW_AT_abstract_origin)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.uleb128 0x7 # (abbrev code)
.uleb128 0x24 # (TAG: DW_TAG_base_type)
.byte 0 # DW_children_no
.uleb128 0xb # (DW_AT_byte_size)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3e # (DW_AT_encoding)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.byte 0
.byte 0
.uleb128 0x8 # (abbrev code)
.uleb128 0x34 # (TAG: DW_TAG_variable)
.byte 0 # DW_children_no
.uleb128 0x3 # (DW_AT_name)
.uleb128 0x8 # (DW_FORM_string)
.uleb128 0x3a # (DW_AT_decl_file)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x3b # (DW_AT_decl_line)
.uleb128 0xb # (DW_FORM_data1)
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.uleb128 0x3f # (DW_AT_external)
.uleb128 0xc # (DW_FORM_flag)
.uleb128 0x2 # (DW_AT_location)
.uleb128 0xa # (DW_FORM_block1)
.byte 0
.byte 0
.uleb128 0x9 # (abbrev code)
.uleb128 0x35 # (TAG: DW_TAG_volatile_type)
.byte 0 # DW_children_no
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
.byte 0
.byte 0
.byte 0
.section .debug_aranges,"",@progbits
.long 0x3c # Length of Address Ranges Info
.value 0x2 # DWARF Version
.long .Ldebug_info0 # Offset of Compilation Unit Info
.byte 0x8 # Size of Address
.byte 0 # Size of Segment Descriptor
.value 0 # Pad to 16 byte boundary
.value 0
.quad .Ltext0 # Address
.quad .Letext0-.Ltext0 # Length
.quad .LFB2 # Address
.quad .LFE2-.LFB2 # Length
.quad 0
.quad 0
.section .debug_ranges,"",@progbits
.Ldebug_ranges0:
.quad .Ltext0 # Offset 0
.quad .Letext0
.quad .LFB2 # Offset 0x10
.quad .LFE2
.quad 0
.quad 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF3:
.string "main"
.LASF0:
.string "GNU C 4.7.2 20120911 (prerelease)"
.LASF1:
.string "gdb.reverse/amd64-tailcall-reverse.c"
.LASF2:
.string ""
.ident "GCC: (GNU) 4.7.2 20120911 (prerelease)"
.section .note.GNU-stack,"",@progbits
|
stsp/binutils-ia16
| 35,648
|
gdb/testsuite/gdb.cp/namelessclass.S
|
/* This testcase is part of GDB, the GNU debugger.
Copyright 2014-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This file was generated using:
$ clang++ -g namelessclass.cc -std=c++11 -S -o namelessclass.S
with
$ clang++ -v
clang version 3.3 (tags/RELEASE_33/final)
Target: x86_64-redhat-linux-gnu
Thread model: posix
This is a test for c++/16597. */
.file "namelessclass.cc"
.section .debug_info,"",@progbits
.Lsection_info:
.section .debug_abbrev,"",@progbits
.Lsection_abbrev:
.section .debug_aranges,"",@progbits
.section .debug_macinfo,"",@progbits
.section .debug_line,"",@progbits
.Lsection_line:
.section .debug_loc,"",@progbits
.section .debug_pubtypes,"",@progbits
.section .debug_str,"MS",@progbits,1
.Linfo_string:
.section .debug_ranges,"",@progbits
.Ldebug_range:
.section .debug_loc,"",@progbits
.Lsection_debug_loc:
.text
.Ltext_begin:
.data
.file 1 "namelessclass.cc"
.text
.globl main
.align 16, 0x90
.type main,@function
main: # @main
.cfi_startproc
.Lfunc_begin0:
.loc 1 42 0 # namelessclass.cc:42:0
# BB#0:
pushq %rbp
.Ltmp2:
.cfi_def_cfa_offset 16
.Ltmp3:
.cfi_offset %rbp, -16
movq %rsp, %rbp
.Ltmp4:
.cfi_def_cfa_register %rbp
subq $16, %rsp
leaq -8(%rbp), %rdi
movl $0, -4(%rbp)
.Ltmp5:
#DEBUG_VALUE: main:a <- RDI+0
.loc 1 43 0 prologue_end # namelessclass.cc:43:0
callq _ZN1AC1Ev
leaq -8(%rbp), %rdi
.Ltmp6:
.loc 1 45 0 # namelessclass.cc:45:0
callq _ZN1A4doitEv
addq $16, %rsp
popq %rbp
ret
.Ltmp7:
.Ltmp8:
.size main, .Ltmp8-main
.Lfunc_end0:
.cfi_endproc
.section .text._ZN1AC1Ev,"axG",@progbits,_ZN1AC1Ev,comdat
.weak _ZN1AC1Ev
.align 16, 0x90
.type _ZN1AC1Ev,@function
_ZN1AC1Ev: # @_ZN1AC1Ev
.cfi_startproc
.Lfunc_begin1:
.loc 1 25 0 # namelessclass.cc:25:0
# BB#0:
pushq %rbp
.Ltmp11:
.cfi_def_cfa_offset 16
.Ltmp12:
.cfi_offset %rbp, -16
movq %rsp, %rbp
.Ltmp13:
.cfi_def_cfa_register %rbp
subq $16, %rsp
movq %rdi, -8(%rbp)
movq -8(%rbp), %rdi
.loc 1 25 0 prologue_end # namelessclass.cc:25:0
.Ltmp14:
callq _ZN1AC2Ev
addq $16, %rsp
popq %rbp
ret
.Ltmp15:
.Ltmp16:
.size _ZN1AC1Ev, .Ltmp16-_ZN1AC1Ev
.Lfunc_end1:
.cfi_endproc
.section .text._ZN1A4doitEv,"axG",@progbits,_ZN1A4doitEv,comdat
.weak _ZN1A4doitEv
.align 16, 0x90
.type _ZN1A4doitEv,@function
_ZN1A4doitEv: # @_ZN1A4doitEv
.cfi_startproc
.Lfunc_begin2:
.loc 1 26 0 # namelessclass.cc:26:0
# BB#0:
pushq %rbp
.Ltmp19:
.cfi_def_cfa_offset 16
.Ltmp20:
.cfi_offset %rbp, -16
movq %rsp, %rbp
.Ltmp21:
.cfi_def_cfa_register %rbp
subq $32, %rsp
movq %rdi, -8(%rbp)
movq -8(%rbp), %rdi
.loc 1 27 0 prologue_end # namelessclass.cc:27:0
.Ltmp22:
movq %rdi, -24(%rbp)
movq -24(%rbp), %rsi
callq _ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_
movl %eax, -12(%rbp)
.loc 1 31 0 # namelessclass.cc:31:0
movl -12(%rbp), %eax
addq $32, %rsp
popq %rbp
ret
.Ltmp23:
.Ltmp24:
.size _ZN1A4doitEv, .Ltmp24-_ZN1A4doitEv
.Lfunc_end2:
.cfi_endproc
.section .text._ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_,"axG",@progbits,_ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_,comdat
.weak _ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_
.align 16, 0x90
.type _ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_,@function
_ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_: # @_ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_
.cfi_startproc
.Lfunc_begin3:
.loc 1 36 0 # namelessclass.cc:36:0
# BB#0:
pushq %rbp
.Ltmp27:
.cfi_def_cfa_offset 16
.Ltmp28:
.cfi_offset %rbp, -16
movq %rsp, %rbp
.Ltmp29:
.cfi_def_cfa_register %rbp
subq $16, %rsp
leaq -16(%rbp), %rax
movq %rdi, -8(%rbp)
movq %rsi, -16(%rbp)
#DEBUG_VALUE: fudge<<lambda at namelessclass.cc:27:22> >:func <- RAX+0
.loc 1 36 34 prologue_end # namelessclass.cc:36:34
.Ltmp30:
movq %rax, %rdi
callq _ZZN1A4doitEvENKUlvE_clEv
.Ltmp31:
addq $16, %rsp
popq %rbp
ret
.Ltmp32:
.Ltmp33:
.size _ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_, .Ltmp33-_ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_
.Lfunc_end3:
.cfi_endproc
.section .text._ZZN1A4doitEvENKUlvE_clEv,"axG",@progbits,_ZZN1A4doitEvENKUlvE_clEv,comdat
.weak _ZZN1A4doitEvENKUlvE_clEv
.align 16, 0x90
.type _ZZN1A4doitEvENKUlvE_clEv,@function
_ZZN1A4doitEvENKUlvE_clEv: # @_ZZN1A4doitEvENKUlvE_clEv
.cfi_startproc
.Lfunc_begin4:
.loc 1 27 0 # namelessclass.cc:27:0
# BB#0:
pushq %rbp
.Ltmp36:
.cfi_def_cfa_offset 16
.Ltmp37:
.cfi_offset %rbp, -16
movq %rsp, %rbp
.Ltmp38:
.cfi_def_cfa_register %rbp
movq %rdi, -8(%rbp)
movq -8(%rbp), %rdi
movq (%rdi), %rdi
.loc 1 28 0 prologue_end # namelessclass.cc:28:0
.Ltmp39:
movl (%rdi), %eax
popq %rbp
ret
.Ltmp40:
.Ltmp41:
.size _ZZN1A4doitEvENKUlvE_clEv, .Ltmp41-_ZZN1A4doitEvENKUlvE_clEv
.Lfunc_end4:
.cfi_endproc
.section .text._ZN1AC2Ev,"axG",@progbits,_ZN1AC2Ev,comdat
.weak _ZN1AC2Ev
.align 16, 0x90
.type _ZN1AC2Ev,@function
_ZN1AC2Ev: # @_ZN1AC2Ev
.cfi_startproc
.Lfunc_begin5:
.loc 1 25 0 # namelessclass.cc:25:0
# BB#0:
pushq %rbp
.Ltmp44:
.cfi_def_cfa_offset 16
.Ltmp45:
.cfi_offset %rbp, -16
movq %rsp, %rbp
.Ltmp46:
.cfi_def_cfa_register %rbp
movq %rdi, -8(%rbp)
movq -8(%rbp), %rdi
.loc 1 25 0 prologue_end # namelessclass.cc:25:0
.Ltmp47:
movl $48879, (%rdi) # imm = 0xBEEF
popq %rbp
ret
.Ltmp48:
.Ltmp49:
.size _ZN1AC2Ev, .Ltmp49-_ZN1AC2Ev
.Lfunc_end5:
.cfi_endproc
.text
.Ltext_end:
.data
.Ldata_end:
.text
.Lsection_end1:
.section .debug_info,"",@progbits
.L.debug_info_begin0:
.long 531 # Length of Compilation Unit Info
.short 2 # DWARF version number
.long .L.debug_abbrev_begin # Offset Into Abbrev. Section
.byte 8 # Address Size (in bytes)
.byte 1 # Abbrev [1] 0xb:0x20c DW_TAG_compile_unit
.long .Linfo_string0 # DW_AT_producer
.short 4 # DW_AT_language
.long .Linfo_string1 # DW_AT_name
.quad 0 # DW_AT_low_pc
.long .Lsection_line # DW_AT_stmt_list
.long .Linfo_string2 # DW_AT_comp_dir
.byte 2 # Abbrev [2] 0x26:0x2c DW_TAG_subprogram
.long .Linfo_string3 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 41 # DW_AT_decl_line
.long 82 # DW_AT_type
# DW_AT_external
.quad .Lfunc_begin0 # DW_AT_low_pc
.quad .Lfunc_end0 # DW_AT_high_pc
.byte 1 # DW_AT_frame_base
.byte 86
.byte 3 # Abbrev [3] 0x43:0xe DW_TAG_variable
.long .Linfo_string15 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 43 # DW_AT_decl_line
.long 186 # DW_AT_type
.byte 2 # DW_AT_location
.byte 145
.byte 120
.byte 0 # End Of Children Mark
.byte 4 # Abbrev [4] 0x52:0x7 DW_TAG_base_type
.long .Linfo_string4 # DW_AT_name
.byte 5 # DW_AT_encoding
.byte 4 # DW_AT_byte_size
.byte 5 # Abbrev [5] 0x59:0x5 DW_TAG_pointer_type
.long 186 # DW_AT_type
.byte 5 # Abbrev [5] 0x5e:0x5 DW_TAG_pointer_type
.long 186 # DW_AT_type
.byte 6 # Abbrev [6] 0x63:0x5 DW_TAG_const_type
.long 119 # DW_AT_type
.byte 5 # Abbrev [5] 0x68:0x5 DW_TAG_pointer_type
.long 99 # DW_AT_type
.byte 5 # Abbrev [5] 0x6d:0x5 DW_TAG_pointer_type
.long 119 # DW_AT_type
.byte 7 # Abbrev [7] 0x72:0x5 DW_TAG_rvalue_reference_type
.long 119 # DW_AT_type
.byte 8 # Abbrev [8] 0x77:0x43 DW_TAG_class_type
.byte 8 # DW_AT_byte_size
.byte 1 # DW_AT_decl_file
.byte 27 # DW_AT_decl_line
.byte 9 # Abbrev [9] 0x7b:0xf DW_TAG_member
.long .Linfo_string7 # DW_AT_name
.long 94 # DW_AT_type
.byte 1 # DW_AT_decl_file
.byte 27 # DW_AT_decl_line
.byte 2 # DW_AT_data_member_location
.byte 35
.byte 0
.byte 3 # DW_AT_accessibility
# DW_ACCESS_private
.byte 10 # Abbrev [10] 0x8a:0x12 DW_TAG_subprogram
.long .Linfo_string8 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 27 # DW_AT_decl_line
.long 82 # DW_AT_type
# DW_AT_declaration
# DW_AT_external
.byte 1 # DW_AT_accessibility
# DW_ACCESS_public
.byte 11 # Abbrev [11] 0x96:0x5 DW_TAG_formal_parameter
.long 104 # DW_AT_type
# DW_AT_artificial
.byte 0 # End Of Children Mark
.byte 12 # Abbrev [12] 0x9c:0xe DW_TAG_subprogram
.long .Linfo_string9 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 27 # DW_AT_decl_line
# DW_AT_declaration
# DW_AT_artificial
# DW_AT_external
.byte 1 # DW_AT_accessibility
# DW_ACCESS_public
.byte 11 # Abbrev [11] 0xa4:0x5 DW_TAG_formal_parameter
.long 109 # DW_AT_type
# DW_AT_artificial
.byte 0 # End Of Children Mark
.byte 13 # Abbrev [13] 0xaa:0xf DW_TAG_subprogram
.byte 1 # DW_AT_decl_file
.byte 27 # DW_AT_decl_line
# DW_AT_declaration
# DW_AT_artificial
# DW_AT_external
.byte 1 # DW_AT_accessibility
# DW_ACCESS_public
.byte 11 # Abbrev [11] 0xae:0x5 DW_TAG_formal_parameter
.long 109 # DW_AT_type
# DW_AT_artificial
.byte 14 # Abbrev [14] 0xb3:0x5 DW_TAG_formal_parameter
.long 114 # DW_AT_type
.byte 0 # End Of Children Mark
.byte 0 # End Of Children Mark
.byte 15 # Abbrev [15] 0xba:0x60 DW_TAG_class_type
.long .Linfo_string6 # DW_AT_name
.byte 4 # DW_AT_byte_size
.byte 1 # DW_AT_decl_file
.byte 22 # DW_AT_decl_line
.byte 9 # Abbrev [9] 0xc2:0xf DW_TAG_member
.long .Linfo_string5 # DW_AT_name
.long 82 # DW_AT_type
.byte 1 # DW_AT_decl_file
.byte 37 # DW_AT_decl_line
.byte 2 # DW_AT_data_member_location
.byte 35
.byte 0
.byte 3 # DW_AT_accessibility
# DW_ACCESS_private
.byte 16 # Abbrev [16] 0xd1:0xe DW_TAG_subprogram
.long .Linfo_string6 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 25 # DW_AT_decl_line
# DW_AT_declaration
# DW_AT_external
.byte 1 # DW_AT_accessibility
# DW_ACCESS_public
.byte 11 # Abbrev [11] 0xd9:0x5 DW_TAG_formal_parameter
.long 89 # DW_AT_type
# DW_AT_artificial
.byte 0 # End Of Children Mark
.byte 17 # Abbrev [17] 0xdf:0x16 DW_TAG_subprogram
.byte 1 # DW_AT_accessibility
# DW_ACCESS_public
.long .Linfo_string13 # DW_AT_MIPS_linkage_name
.long .Linfo_string14 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 26 # DW_AT_decl_line
.long 82 # DW_AT_type
# DW_AT_declaration
# DW_AT_external
.byte 11 # Abbrev [11] 0xef:0x5 DW_TAG_formal_parameter
.long 89 # DW_AT_type
# DW_AT_artificial
.byte 0 # End Of Children Mark
.byte 18 # Abbrev [18] 0xf5:0x24 DW_TAG_subprogram
.long .Linfo_string11 # DW_AT_MIPS_linkage_name
.long .Linfo_string12 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 36 # DW_AT_decl_line
.long 82 # DW_AT_type
# DW_AT_declaration
# DW_AT_external
.byte 3 # DW_AT_accessibility
# DW_ACCESS_private
.byte 19 # Abbrev [19] 0x105:0x9 DW_TAG_template_type_parameter
.long 119 # DW_AT_type
.long .Linfo_string10 # DW_AT_name
.byte 11 # Abbrev [11] 0x10e:0x5 DW_TAG_formal_parameter
.long 89 # DW_AT_type
# DW_AT_artificial
.byte 14 # Abbrev [14] 0x113:0x5 DW_TAG_formal_parameter
.long 119 # DW_AT_type
.byte 0 # End Of Children Mark
.byte 0 # End Of Children Mark
.byte 20 # Abbrev [20] 0x11a:0x62 DW_TAG_subprogram
.long 223 # DW_AT_specification
.quad .Lfunc_begin2 # DW_AT_low_pc
.quad .Lfunc_end2 # DW_AT_high_pc
.byte 1 # DW_AT_frame_base
.byte 86
.long 351 # DW_AT_object_pointer
.byte 20 # Abbrev [20] 0x135:0x2a DW_TAG_subprogram
.long 138 # DW_AT_specification
.quad .Lfunc_begin4 # DW_AT_low_pc
.quad .Lfunc_end4 # DW_AT_high_pc
.byte 1 # DW_AT_frame_base
.byte 86
.long 336 # DW_AT_object_pointer
.byte 21 # Abbrev [21] 0x150:0xe DW_TAG_formal_parameter
.long .Linfo_string7 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 27 # DW_AT_decl_line
.long 529 # DW_AT_type
# DW_AT_artificial
.byte 2 # DW_AT_location
.byte 145
.byte 120
.byte 0 # End Of Children Mark
.byte 21 # Abbrev [21] 0x15f:0xe DW_TAG_formal_parameter
.long .Linfo_string7 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 26 # DW_AT_decl_line
.long 94 # DW_AT_type
# DW_AT_artificial
.byte 2 # DW_AT_location
.byte 145
.byte 120
.byte 3 # Abbrev [3] 0x16d:0xe DW_TAG_variable
.long .Linfo_string16 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 27 # DW_AT_decl_line
.long 82 # DW_AT_type
.byte 2 # DW_AT_location
.byte 145
.byte 116
.byte 0 # End Of Children Mark
.byte 20 # Abbrev [20] 0x17c:0x41 DW_TAG_subprogram
.long 245 # DW_AT_specification
.quad .Lfunc_begin3 # DW_AT_low_pc
.quad .Lfunc_end3 # DW_AT_high_pc
.byte 1 # DW_AT_frame_base
.byte 86
.long 416 # DW_AT_object_pointer
.byte 19 # Abbrev [19] 0x197:0x9 DW_TAG_template_type_parameter
.long 119 # DW_AT_type
.long .Linfo_string10 # DW_AT_name
.byte 21 # Abbrev [21] 0x1a0:0xe DW_TAG_formal_parameter
.long .Linfo_string7 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 36 # DW_AT_decl_line
.long 94 # DW_AT_type
# DW_AT_artificial
.byte 2 # DW_AT_location
.byte 145
.byte 120
.byte 22 # Abbrev [22] 0x1ae:0xe DW_TAG_formal_parameter
.long .Linfo_string17 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 36 # DW_AT_decl_line
.long 119 # DW_AT_type
.byte 2 # DW_AT_location
.byte 145
.byte 112
.byte 0 # End Of Children Mark
.byte 20 # Abbrev [20] 0x1bd:0x2a DW_TAG_subprogram
.long 209 # DW_AT_specification
.quad .Lfunc_begin1 # DW_AT_low_pc
.quad .Lfunc_end1 # DW_AT_high_pc
.byte 1 # DW_AT_frame_base
.byte 86
.long 472 # DW_AT_object_pointer
.byte 21 # Abbrev [21] 0x1d8:0xe DW_TAG_formal_parameter
.long .Linfo_string7 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 25 # DW_AT_decl_line
.long 94 # DW_AT_type
# DW_AT_artificial
.byte 2 # DW_AT_location
.byte 145
.byte 120
.byte 0 # End Of Children Mark
.byte 20 # Abbrev [20] 0x1e7:0x2a DW_TAG_subprogram
.long 209 # DW_AT_specification
.quad .Lfunc_begin5 # DW_AT_low_pc
.quad .Lfunc_end5 # DW_AT_high_pc
.byte 1 # DW_AT_frame_base
.byte 86
.long 514 # DW_AT_object_pointer
.byte 21 # Abbrev [21] 0x202:0xe DW_TAG_formal_parameter
.long .Linfo_string7 # DW_AT_name
.byte 1 # DW_AT_decl_file
.byte 25 # DW_AT_decl_line
.long 94 # DW_AT_type
# DW_AT_artificial
.byte 2 # DW_AT_location
.byte 145
.byte 120
.byte 0 # End Of Children Mark
.byte 5 # Abbrev [5] 0x211:0x5 DW_TAG_pointer_type
.long 99 # DW_AT_type
.byte 0 # End Of Children Mark
.L.debug_info_end0:
.section .debug_abbrev,"",@progbits
.L.debug_abbrev_begin:
.byte 1 # Abbreviation Code
.byte 17 # DW_TAG_compile_unit
.byte 1 # DW_CHILDREN_yes
.byte 37 # DW_AT_producer
.byte 14 # DW_FORM_strp
.byte 19 # DW_AT_language
.byte 5 # DW_FORM_data2
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 17 # DW_AT_low_pc
.byte 1 # DW_FORM_addr
.byte 16 # DW_AT_stmt_list
.byte 6 # DW_FORM_data4
.byte 27 # DW_AT_comp_dir
.byte 14 # DW_FORM_strp
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 2 # Abbreviation Code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_CHILDREN_yes
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 63 # DW_AT_external
.byte 25 # DW_FORM_flag_present
.byte 17 # DW_AT_low_pc
.byte 1 # DW_FORM_addr
.byte 18 # DW_AT_high_pc
.byte 1 # DW_FORM_addr
.byte 64 # DW_AT_frame_base
.byte 10 # DW_FORM_block1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 3 # Abbreviation Code
.byte 52 # DW_TAG_variable
.byte 0 # DW_CHILDREN_no
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 2 # DW_AT_location
.byte 10 # DW_FORM_block1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 4 # Abbreviation Code
.byte 36 # DW_TAG_base_type
.byte 0 # DW_CHILDREN_no
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 62 # DW_AT_encoding
.byte 11 # DW_FORM_data1
.byte 11 # DW_AT_byte_size
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 5 # Abbreviation Code
.byte 15 # DW_TAG_pointer_type
.byte 0 # DW_CHILDREN_no
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 6 # Abbreviation Code
.byte 38 # DW_TAG_const_type
.byte 0 # DW_CHILDREN_no
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 7 # Abbreviation Code
.byte 66 # DW_TAG_rvalue_reference_type
.byte 0 # DW_CHILDREN_no
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 8 # Abbreviation Code
.byte 2 # DW_TAG_class_type
.byte 1 # DW_CHILDREN_yes
.byte 11 # DW_AT_byte_size
.byte 11 # DW_FORM_data1
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 9 # Abbreviation Code
.byte 13 # DW_TAG_member
.byte 0 # DW_CHILDREN_no
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 56 # DW_AT_data_member_location
.byte 10 # DW_FORM_block1
.byte 50 # DW_AT_accessibility
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 10 # Abbreviation Code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_CHILDREN_yes
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 60 # DW_AT_declaration
.byte 25 # DW_FORM_flag_present
.byte 63 # DW_AT_external
.byte 25 # DW_FORM_flag_present
.byte 50 # DW_AT_accessibility
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 11 # Abbreviation Code
.byte 5 # DW_TAG_formal_parameter
.byte 0 # DW_CHILDREN_no
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 52 # DW_AT_artificial
.byte 25 # DW_FORM_flag_present
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 12 # Abbreviation Code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_CHILDREN_yes
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 60 # DW_AT_declaration
.byte 25 # DW_FORM_flag_present
.byte 52 # DW_AT_artificial
.byte 25 # DW_FORM_flag_present
.byte 63 # DW_AT_external
.byte 25 # DW_FORM_flag_present
.byte 50 # DW_AT_accessibility
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 13 # Abbreviation Code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_CHILDREN_yes
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 60 # DW_AT_declaration
.byte 25 # DW_FORM_flag_present
.byte 52 # DW_AT_artificial
.byte 25 # DW_FORM_flag_present
.byte 63 # DW_AT_external
.byte 25 # DW_FORM_flag_present
.byte 50 # DW_AT_accessibility
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 14 # Abbreviation Code
.byte 5 # DW_TAG_formal_parameter
.byte 0 # DW_CHILDREN_no
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 15 # Abbreviation Code
.byte 2 # DW_TAG_class_type
.byte 1 # DW_CHILDREN_yes
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 11 # DW_AT_byte_size
.byte 11 # DW_FORM_data1
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 16 # Abbreviation Code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_CHILDREN_yes
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 60 # DW_AT_declaration
.byte 25 # DW_FORM_flag_present
.byte 63 # DW_AT_external
.byte 25 # DW_FORM_flag_present
.byte 50 # DW_AT_accessibility
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 17 # Abbreviation Code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_CHILDREN_yes
.byte 50 # DW_AT_accessibility
.byte 11 # DW_FORM_data1
.ascii "\207@" # DW_AT_MIPS_linkage_name
.byte 14 # DW_FORM_strp
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 60 # DW_AT_declaration
.byte 25 # DW_FORM_flag_present
.byte 63 # DW_AT_external
.byte 25 # DW_FORM_flag_present
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 18 # Abbreviation Code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_CHILDREN_yes
.ascii "\207@" # DW_AT_MIPS_linkage_name
.byte 14 # DW_FORM_strp
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 60 # DW_AT_declaration
.byte 25 # DW_FORM_flag_present
.byte 63 # DW_AT_external
.byte 25 # DW_FORM_flag_present
.byte 50 # DW_AT_accessibility
.byte 11 # DW_FORM_data1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 19 # Abbreviation Code
.byte 47 # DW_TAG_template_type_parameter
.byte 0 # DW_CHILDREN_no
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 20 # Abbreviation Code
.byte 46 # DW_TAG_subprogram
.byte 1 # DW_CHILDREN_yes
.byte 71 # DW_AT_specification
.byte 19 # DW_FORM_ref4
.byte 17 # DW_AT_low_pc
.byte 1 # DW_FORM_addr
.byte 18 # DW_AT_high_pc
.byte 1 # DW_FORM_addr
.byte 64 # DW_AT_frame_base
.byte 10 # DW_FORM_block1
.byte 100 # DW_AT_object_pointer
.byte 19 # DW_FORM_ref4
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 21 # Abbreviation Code
.byte 5 # DW_TAG_formal_parameter
.byte 0 # DW_CHILDREN_no
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 52 # DW_AT_artificial
.byte 25 # DW_FORM_flag_present
.byte 2 # DW_AT_location
.byte 10 # DW_FORM_block1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 22 # Abbreviation Code
.byte 5 # DW_TAG_formal_parameter
.byte 0 # DW_CHILDREN_no
.byte 3 # DW_AT_name
.byte 14 # DW_FORM_strp
.byte 58 # DW_AT_decl_file
.byte 11 # DW_FORM_data1
.byte 59 # DW_AT_decl_line
.byte 11 # DW_FORM_data1
.byte 73 # DW_AT_type
.byte 19 # DW_FORM_ref4
.byte 2 # DW_AT_location
.byte 10 # DW_FORM_block1
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 0 # EOM(3)
.L.debug_abbrev_end:
.section .debug_aranges,"",@progbits
.section .debug_ranges,"",@progbits
.section .debug_macinfo,"",@progbits
.section .debug_str,"MS",@progbits,1
.Linfo_string0:
.asciz "clang version 3.3 (tags/RELEASE_33/final)"
.Linfo_string1:
.asciz "namelessclass.cc"
.Linfo_string2:
.asciz "/tmp"
.Linfo_string3:
.asciz "main"
.Linfo_string4:
.asciz "int"
.Linfo_string5:
.asciz "a_"
.Linfo_string6:
.asciz "A"
.Linfo_string7:
.asciz "this"
.Linfo_string8:
.asciz "operator()"
.Linfo_string9:
.asciz "~"
.Linfo_string10:
.asciz "Func"
.Linfo_string11:
.asciz "_ZN1A5fudgeIZNS_4doitEvEUlvE_EEiT_"
.Linfo_string12:
.asciz "fudge<<lambda at namelessclass.cc:27:22> >"
.Linfo_string13:
.asciz "_ZN1A4doitEv"
.Linfo_string14:
.asciz "doit"
.Linfo_string15:
.asciz "a"
.Linfo_string16:
.asciz "ret"
.Linfo_string17:
.asciz "func"
.section ".note.GNU-stack","",@progbits
|
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