repo_id
stringlengths 5
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| size
int64 590
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| file_path
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stsp/binutils-ia16
| 1,605
|
sim/testsuite/bfin/addsub_flags.S
|
// ACP 5.17 Dual ALU ops
// AZ, AN, AC0, AC1, V and VS are affected
// AV0, AV0S, AV1, AV1S are unaffected
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
A0 = A1 = 0;
r0=0;
r0.h=0x7fff;
r2=0;
r2.h=0x7000;
r1=r0+r2,r3=r0-r2;
r7=astat;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN);
a1=r2;
a0=r0;
r1=a0+a1, r3=a0-a1;
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN);
a0=r2;
a1=r0;
r1=a1+a0, r3=a1-a0;
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN);
r0.h=0xafff;
r2.h=0xa000;
a1=r2;
a0=r0;
r1=a0+a1, r3=a0-a1;
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
r1=a0+a1, r3=a0-a1 (s);
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN);
r0.h=0xafff;
r2.h=0xa000;
a0=r2;
a1=r0;
r1=a1+a0, r3=a1-a0;
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
r1=a1+a0, r3=a1-a0 (s);
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN);
r2.h=0x8001;
r1=r0+r2,r3=r0-r2;
_dbg r1;
_dbg r3;
_dbg astat;
r7=astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
r2.h=0x8000;
r1=r0+r2,r3=r0-r2;
r7=astat;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
pass;
|
stsp/binutils-ia16
| 2,045
|
sim/testsuite/bfin/random_0033.S
|
# Verify registers saturate and ASTAT bits are updated correctly
# with the RND12 subtract insn
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x24a00410 | _VS | _AV1S | _AV0 | _AC0 | _AC0_COPY | _AN);
imm32 R5, 0x0fb35119;
imm32 R6, 0xffffffff;
imm32 R7, 0x80000000;
R6.H = R5 - R7 (RND12);
checkreg R6, 0x7fffffff;
checkreg ASTAT, (0x24a00410 | _VS | _V | _AV1S | _AV0 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
imm32 R3, 0x80003f8f;
imm32 R5, 0x6267c92c;
imm32 R6, 0x80000000;
R5.L = R3 - R6 (RND12);
checkreg R5, 0x62670004;
checkreg ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x04200c10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY);
imm32 R1, 0x7fff0000;
imm32 R5, 0x80000000;
R1.L = R5 - R5 (RND12);
checkreg ASTAT, (0x04200c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AZ);
checkreg R1, 0x7fff0000;
checkreg R5, 0x80000000;
dmm32 ASTAT, (0x40600e90 | _VS | _AV1S | _AV0S | _AQ | _CC);
imm32 R1, 0x80000000;
imm32 R5, 0x00008000;
imm32 R6, 0x00000000;
R5.L = R6 - R1 (RND12);
checkreg R5, 0x00007fff;
checkreg ASTAT, (0x40600e90 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x68300880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ);
imm32 R1, 0xf8ed0000;
imm32 R6, 0x80000000;
R1.H = R1 - R6 (RND12);
checkreg R1, 0x7fff0000;
checkreg ASTAT, (0x68300880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x70d0c410 | _VS | _AV0S | _AQ);
imm32 R0, 0x80000000;
imm32 R1, 0x71455f95;
imm32 R4, 0xd4871012;
R4.H = R1 - R0 (RND12);
checkreg R4, 0x7fff1012;
checkreg ASTAT, (0x70d0c410 | _VS | _V | _AV0S | _AQ | _V_COPY);
dmm32 ASTAT, (0x34500e00 | _VS | _AV0S | _AC1 | _CC | _AZ);
imm32 R2, 0x00000000;
imm32 R5, 0x00000000;
imm32 R6, 0x80000000;
R2.L = R5 - R6 (RND12);
checkreg R2, 0x00007fff;
checkreg ASTAT, (0x34500e00 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY);
pass
|
stsp/binutils-ia16
| 2,492
|
sim/testsuite/bfin/c_logi2op_bitclr.s
|
//Original:/testcases/core/c_logi2op_bitclr/c_logi2op_bitclr.dsp
// Spec Reference: Logi2op functions: bitclr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xffffffff;
imm32 r1, 0xffffffff;
imm32 r2, 0xffffffff;
imm32 r3, 0xffffffff;
imm32 r4, 0xffffffff;
imm32 r5, 0xffffffff;
imm32 r6, 0xffffffff;
imm32 r7, 0xffffffff;
// bit clr
BITCLR( R0 , 0 ); /* r0 = 0x00000001 */
BITCLR( R1 , 1 ); /* r1 = 0x00000002 */
BITCLR( R2 , 2 ); /* r2 = 0x00000004 */
BITCLR( R3 , 3 ); /* r3 = 0x00000008 */
BITCLR( R4 , 4 ); /* r4 = 0x00000010 */
BITCLR( R5 , 5 ); /* r5 = 0x00000020 */
BITCLR( R6 , 6 ); /* r6 = 0x00000040 */
BITCLR( R7 , 7 ); /* r7 = 0x00000080 */
CHECKREG r0, 0xfffffffe;
CHECKREG r1, 0xfffffffd;
CHECKREG r2, 0xfffffffb;
CHECKREG r3, 0xfffffff7;
CHECKREG r4, 0xffffffef;
CHECKREG r5, 0xffffffdf;
CHECKREG r6, 0xffffffbf;
CHECKREG r7, 0xffffff7f;
// bit clr
BITCLR( R0 , 8 ); /* r0 = 0x00000100 */
BITCLR( R1 , 9 ); /* r1 = 0x00000200 */
BITCLR( R2 , 10 ); /* r2 = 0x00000400 */
BITCLR( R3 , 11 ); /* r3 = 0x00000800 */
BITCLR( R4 , 12 ); /* r4 = 0x00001000 */
BITCLR( R5 , 13 ); /* r5 = 0x00002000 */
BITCLR( R6 , 14 ); /* r6 = 0x00004000 */
BITCLR( R7 , 15 ); /* r7 = 0x00008000 */
CHECKREG r0, 0xfffffefe;
CHECKREG r1, 0xfffffdfd;
CHECKREG r2, 0xfffffbfb;
CHECKREG r3, 0xfffff7f7;
CHECKREG r4, 0xffffefef;
CHECKREG r5, 0xffffdfdf;
CHECKREG r6, 0xffffbfbf;
CHECKREG r7, 0xffff7f7f;
// bit clr
BITCLR( R0 , 16 ); /* r0 = 0x00000100 */
BITCLR( R1 , 17 ); /* r1 = 0x00000200 */
BITCLR( R2 , 18 ); /* r2 = 0x00000400 */
BITCLR( R3 , 19 ); /* r3 = 0x00000800 */
BITCLR( R4 , 20 ); /* r4 = 0x00001000 */
BITCLR( R5 , 21 ); /* r5 = 0x00002000 */
BITCLR( R6 , 22 ); /* r6 = 0x00004000 */
BITCLR( R7 , 23 ); /* r7 = 0x00008000 */
CHECKREG r0, 0xfffefefe;
CHECKREG r1, 0xfffdfdfd;
CHECKREG r2, 0xfffbfbfb;
CHECKREG r3, 0xfff7f7f7;
CHECKREG r4, 0xffefefef;
CHECKREG r5, 0xffdfdfdf;
CHECKREG r6, 0xffbfbfbf;
CHECKREG r7, 0xff7f7f7f;
// bit clr
BITCLR( R0 , 24 ); /* r0 = 0x00000100 */
BITCLR( R1 , 25 ); /* r1 = 0x00000200 */
BITCLR( R2 , 26 ); /* r2 = 0x00000400 */
BITCLR( R3 , 27 ); /* r3 = 0x00000800 */
BITCLR( R4 , 28 ); /* r4 = 0x00001000 */
BITCLR( R5 , 29 ); /* r5 = 0x00002000 */
BITCLR( R6 , 30 ); /* r6 = 0x00004000 */
BITCLR( R7 , 31 ); /* r7 = 0x00008000 */
CHECKREG r0, 0xfefefefe;
CHECKREG r1, 0xfdfdfdfd;
CHECKREG r2, 0xfbfbfbfb;
CHECKREG r3, 0xf7f7f7f7;
CHECKREG r4, 0xefefefef;
CHECKREG r5, 0xdfdfdfdf;
CHECKREG r6, 0xbfbfbfbf;
CHECKREG r7, 0x7f7f7f7f;
pass
|
stsp/binutils-ia16
| 1,166
|
sim/testsuite/bfin/c_dsp32shiftim_af.s
|
//Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R0 = R0 << 0;
R1 = R1 << 3;
R2 = R2 << 7;
R3 = R3 << 8;
R4 = R4 << 15;
R5 = R5 << 24;
R6 = R6 << 31;
R7 = R7 << 20;
CHECKREG r0, 0xA1230001;
CHECKREG r1, 0xD9A2B3C0;
CHECKREG r2, 0xE2B3C480;
CHECKREG r3, 0xD6789A00;
CHECKREG r4, 0xC4D58000;
CHECKREG r5, 0xBC000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0xCDE00000;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R6 = R0 >>> 1;
R7 = R1 >>> 3;
R0 = R2 >>> 7;
R1 = R3 >>> 8;
R2 = R4 >>> 15;
R3 = R5 >>> 24;
R4 = R6 >>> 31;
R5 = R7 >>> 20;
CHECKREG r0, 0x00478ACF;
CHECKREG r1, 0x0034D678;
CHECKREG r2, 0xFFFF0B4F;
CHECKREG r3, 0xFFFFFF96;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0x00000036;
CHECKREG r6, 0xD0918000;
CHECKREG r7, 0x03668ACF;
pass
|
stsp/binutils-ia16
| 4,974
|
sim/testsuite/bfin/c_dsp32shift_expadj_r.s
|
//Original:/testcases/core/c_dsp32shift_expadj_r/c_dsp32shift_expadj_r.dsp
// Spec Reference: dsp32shift expadj r
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x08000800;
imm32 r1, 0x08000801;
imm32 r2, 0x08000802;
imm32 r3, 0x08000803;
imm32 r4, 0x08000804;
imm32 r5, 0x08000805;
imm32 r6, 0x08000806;
imm32 r7, 0x08000807;
//rl0 = expadj r0 by rl0;
R1.L = EXPADJ( R1 , R0.L );
R2.L = EXPADJ( R2 , R0.L );
R3.L = EXPADJ( R3 , R0.L );
R4.L = EXPADJ( R4 , R0.L );
R5.L = EXPADJ( R5 , R0.L );
R6.L = EXPADJ( R6 , R0.L );
R7.L = EXPADJ( R7 , R0.L );
CHECKREG r0, 0x08000800;
CHECKREG r1, 0x08000800;
CHECKREG r2, 0x08000800;
CHECKREG r3, 0x08000800;
CHECKREG r4, 0x08000800;
CHECKREG r5, 0x08000800;
CHECKREG r6, 0x08000800;
CHECKREG r7, 0x08000800;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000001;
imm32 r2, 0x0900d002;
imm32 r3, 0x0900d003;
imm32 r4, 0x0900d004;
imm32 r5, 0x0900d005;
imm32 r6, 0x0900d006;
imm32 r7, 0x0900d007;
R0.L = EXPADJ( R0 , R1.L );
R1.L = EXPADJ( R1 , R1.L );
R2.L = EXPADJ( R2 , R1.L );
R3.L = EXPADJ( R3 , R1.L );
R4.L = EXPADJ( R4 , R1.L );
R5.L = EXPADJ( R5 , R1.L );
R6.L = EXPADJ( R6 , R1.L );
R7.L = EXPADJ( R7 , R1.L );
CHECKREG r0, 0x09000001;
CHECKREG r1, 0x09000001;
CHECKREG r2, 0x09000001;
CHECKREG r3, 0x09000001;
CHECKREG r4, 0x09000001;
CHECKREG r5, 0x09000001;
CHECKREG r6, 0x09000001;
CHECKREG r7, 0x09000001;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a00e003;
imm32 r4, 0x0a00e004;
imm32 r5, 0x0a00e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0a00e007;
R0.L = EXPADJ( R0 , R2.L );
R1.L = EXPADJ( R1 , R2.L );
//rl2 = expadj r2 by rl2;
R3.L = EXPADJ( R3 , R2.L );
R4.L = EXPADJ( R4 , R2.L );
R5.L = EXPADJ( R5 , R2.L );
R6.L = EXPADJ( R6 , R2.L );
R7.L = EXPADJ( R7 , R2.L );
CHECKREG r0, 0x0A000003;
CHECKREG r1, 0x0A000003;
CHECKREG r2, 0x0A00000F;
CHECKREG r3, 0x0A000003;
CHECKREG r4, 0x0A000003;
CHECKREG r5, 0x0A000003;
CHECKREG r6, 0x0A000003;
CHECKREG r7, 0x0A000003;
imm32 r0, 0x0b00f001;
imm32 r1, 0x0b00f001;
imm32 r2, 0x0b00f002;
imm32 r3, 0x0b000010;
imm32 r4, 0x0b00f004;
imm32 r5, 0x0b00f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x0b00f007;
R0.L = EXPADJ( R0 , R3.L );
R1.L = EXPADJ( R1 , R3.L );
R2.L = EXPADJ( R2 , R3.L );
R3.L = EXPADJ( R3 , R3.L );
R4.L = EXPADJ( R4 , R3.L );
R5.L = EXPADJ( R5 , R3.L );
R6.L = EXPADJ( R6 , R3.L );
R7.L = EXPADJ( R7 , R3.L );
CHECKREG r0, 0x0B000003;
CHECKREG r1, 0x0B000003;
CHECKREG r2, 0x0B000003;
CHECKREG r3, 0x0B000003;
CHECKREG r4, 0x0B000003;
CHECKREG r5, 0x0B000003;
CHECKREG r6, 0x0B000003;
CHECKREG r7, 0x0B000003;
imm32 r0, 0x0c0000c0;
imm32 r1, 0x0c0100c0;
imm32 r2, 0x0c0200c0;
imm32 r3, 0x0c0300c0;
imm32 r4, 0x0c0400c0;
imm32 r5, 0x0c0500c0;
imm32 r6, 0x0c0600c0;
imm32 r7, 0x0c0700c0;
R0.L = EXPADJ( R0 , R4.L );
R1.L = EXPADJ( R1 , R4.L );
R2.L = EXPADJ( R2 , R4.L );
R3.L = EXPADJ( R3 , R4.L );
R4.L = EXPADJ( R4 , R4.L );
R5.L = EXPADJ( R5 , R4.L );
R6.L = EXPADJ( R6 , R4.L );
R7.L = EXPADJ( R7 , R4.L );
CHECKREG r0, 0x0C0000C0;
CHECKREG r1, 0x0C0100C0;
CHECKREG r2, 0x0C0200C0;
CHECKREG r3, 0x0C0300C0;
CHECKREG r4, 0x0C0400C0;
CHECKREG r5, 0x0C0500C0;
CHECKREG r6, 0x0C0600C0;
CHECKREG r7, 0x0C0700C0;
imm32 r0, 0xa00100d0;
imm32 r1, 0x000100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa00500d0;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R0.L = EXPADJ( R0 , R5.L );
R1.L = EXPADJ( R1 , R5.L );
R2.L = EXPADJ( R2 , R5.L );
R3.L = EXPADJ( R3 , R5.L );
R4.L = EXPADJ( R4 , R5.L );
R5.L = EXPADJ( R5 , R5.L );
R6.L = EXPADJ( R6 , R5.L );
R7.L = EXPADJ( R7 , R5.L );
CHECKREG r0, 0xA0010000;
CHECKREG r1, 0x0001000E;
CHECKREG r2, 0xA0020000;
CHECKREG r3, 0xA0030000;
CHECKREG r4, 0xA0040000;
CHECKREG r5, 0xA0050000;
CHECKREG r6, 0xA0060000;
CHECKREG r7, 0xA0070000;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R0.L = EXPADJ( R0 , R6.L );
R1.L = EXPADJ( R1 , R6.L );
R2.L = EXPADJ( R2 , R6.L );
R3.L = EXPADJ( R3 , R6.L );
R4.L = EXPADJ( R4 , R6.L );
R5.L = EXPADJ( R5 , R6.L );
R6.L = EXPADJ( R6 , R6.L );
R7.L = EXPADJ( R7 , R6.L );
CHECKREG r0, 0xB0010000;
CHECKREG r1, 0xB0010000;
CHECKREG r2, 0xB0020000;
CHECKREG r3, 0xB0030000;
CHECKREG r4, 0xB0040000;
CHECKREG r5, 0xB0050000;
CHECKREG r6, 0xB0060000;
CHECKREG r7, 0xB0070000;
imm32 r0, 0xd00100e0;
imm32 r1, 0xd00100e0;
imm32 r2, 0xd00200e0;
imm32 r3, 0xd00300e0;
imm32 r4, 0xd00400e0;
imm32 r5, 0xd00500e0;
imm32 r6, 0xd00600e0;
imm32 r7, 0xd00700e0;
R0.L = EXPADJ( R0 , R7.L );
R1.L = EXPADJ( R1 , R7.L );
R2.L = EXPADJ( R2 , R7.L );
R3.L = EXPADJ( R3 , R7.L );
R4.L = EXPADJ( R4 , R7.L );
R5.L = EXPADJ( R5 , R7.L );
R6.L = EXPADJ( R6 , R7.L );
R7.L = EXPADJ( R7 , R7.L );
CHECKREG r0, 0xD00100E0;
CHECKREG r1, 0xD00100E0;
CHECKREG r2, 0xD00200E0;
CHECKREG r3, 0xD00300E0;
CHECKREG r4, 0xD00400E0;
CHECKREG r5, 0xD00500E0;
CHECKREG r6, 0xD00600E0;
CHECKREG r7, 0xD00700E0;
pass
|
stsp/binutils-ia16
| 11,826
|
sim/testsuite/bfin/se_loop_mv2lc_stall.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc_stall/se_loop_mv2lc_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE 0x00000500
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
P2 = 0x0100 (Z);
P2.H = 0x00f0;
// 2 pushes of P0 onto the Stack;
[ -- SP ] = P0;
[ -- SP ] = P0;
// Loop 0
LD32_LABEL(r0, L0T);
LD32_LABEL(r1, L0B);
LT0 = r0;
LB0 = r1;
R0 = [ P2 ++ ];
LC0 = p1;
L0T:R3 += 4;
R2 += 3;
R4 += 5;
R5 += 6;
R6 += 7;
L0B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L1T);
LD32_LABEL(r1, L1B);
LT0 = r0;
LB0 = r1;
R0 = [ P2 ++ ];
NOP;
LC0 = p1;
L1T:R4 += 5;
R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
L1B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L2T);
LD32_LABEL(r1, L2B);
LT0 = r0;
LB0 = r1;
R0 = [ P2 ++ ];
NOP;
NOP;
LC0 = p1;
L2T:R5 += 6;
R2 += 3;
R3 += 4;
R4 += 5;
R6 += 7;
L2B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L3T);
LD32_LABEL(r1, L3B);
LT0 = r0;
LB0 = r1;
R0 = [ P2 ++ ];
NOP;
NOP;
NOP;
LC0 = p1;
L3T:R2 += 3;
R5 += 6;
R6 += 7;
R3 += 4;
R4 += 5;
L3B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L4T);
LD32_LABEL(r1, L4B);
LT0 = r0;
LB0 = r1;
R0 = [ P2 ++ ];
NOP;
NOP;
NOP;
NOP;
LC0 = p1;
L4T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
L4B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L5T);
LD32_LABEL(r1, L5B);
LT0 = r0;
LB0 = r1;
R0 = [ P2 ++ ];
LC0 = [sp++];
L5T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
L5B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M0T);
LD32_LABEL(r1, M0B);
LT1 = r0;
LB1 = r1;
R0 = [ P2 ++ ];
LC1 = p1;
M0T:R3 += 4;
R2 += 3;
R4 += 5;
R5 += 6;
R6 += 7;
M0B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M1T);
LD32_LABEL(r1, M1B);
LT1 = r0;
LB1 = r1;
R0 = [ P2 ++ ];
NOP;
LC1 = p1;
M1T:R4 += 5;
R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
M1B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M2T);
LD32_LABEL(r1, M2B);
LT1 = r0;
LB1 = r1;
R0 = [ P2 ++ ];
NOP;
NOP;
LC1 = p1;
M2T:R5 += 6;
R2 += 3;
R3 += 4;
R4 += 5;
R6 += 7;
M2B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M3T);
LD32_LABEL(r1, M3B);
LT1 = r0;
LB1 = r1;
R0 = [ P2 ++ ];
NOP;
NOP;
NOP;
LC1 = p1;
M3T:R2 += 3;
R5 += 6;
R6 += 7;
R3 += 4;
R4 += 5;
M3B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M4T);
LD32_LABEL(r1, M4B);
LT1 = r0;
LB1 = r1;
R0 = [ P2 ++ ];
NOP;
NOP;
NOP;
NOP;
LC1 = p1;
M4T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
M4B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M5T);
LD32_LABEL(r1, M5B);
LT1 = r0;
LB1 = r1;
R0 = [ P2 ++ ];
LC1 = [sp++];
M5T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
M5B:R7 += 8;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_0x00F00100,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
.dd 0x05050505;
.dd 0x06060606;
.dd 0x07070707;
.dd 0x08080808;
.dd 0x09090909;
.dd 0x0a0a0a0a;
.dd 0x0b0b0b0b;
.dd 0x0c0c0c0c;
.dd 0x0d0d0d0d;
.dd 0x0e0e0e0e;
.dd 0x0f0f0f0f;
// Define Kernal Stack
.section MEM_0x00F00210,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 6,415
|
sim/testsuite/bfin/c_interr_pending.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_pending/c_interr_pending.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
// CHECK_INIT(p5, 0x00BFFFFC);
// CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
//.code 0x200
START :
P1 = 0x0;
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
CLI R1; // stop interrupt
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
WR_MMR(TPERIOD, 0x00000050, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000000, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000050);
// RD_MMR(TCOUNT, p0, r3);
// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
RD_MMR(TPERIOD, p0, r4);
CHECKREG(r4, 0x00000050);
// RD_MMR(TCNTL, p0, r5);
// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TPERIOD, 0x00000015, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000002, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1)
CSYNC;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label4;
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label5: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label6;
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
label4: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
JUMP.S label5;
R5.L = 0x2222; // Will be killed
R5.H = 0x2222; // Will be killed
NOP;
NOP;
NOP;
NOP;
label6: R3.H = 0x7999;
R3.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// With auto reload
// Read the contents of the Timer
RAISE 7;
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000015);
CHECKREG(p1, 0x00000000); // no interrupt being serviced
CHECKREG(r7, 0x00000000); // no interrupt being serviced
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
STI R1;
NOP; NOP; NOP;
CHECKREG(r7, 0x00000001); // interrupt being serviced
CHECKREG(p1, 0x00000001); // interrupt being serviced
NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
//.code ITABLE
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
P1 += 1;
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_DATA_ADDR_1,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
stsp/binutils-ia16
| 96,673
|
sim/testsuite/bfin/lmu_cplb_multiple1.S
|
//Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple1/lmu_cplb_multiple1.dsp
// Description: Multiple CPLB Hit exceptions (DAG1)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
// Test LMU/CPLB exceptions
// Basic outline:
// Set exception handler
// program CPLB Entries
// Enable CPLB in DMEM_CNTL
// perform access
// verify exception occurred
CHECK_INIT(p5, 0xEFFFFFFC);
//-------------------------
// Zero the CPLB Address and Data regs.
LD32(p0, DCPLB_ADDR0);
R0 = 0;
[ P0 ++ ] = R0; // 0
[ P0 ++ ] = R0; // 1
[ P0 ++ ] = R0; // 2
[ P0 ++ ] = R0; // 3
[ P0 ++ ] = R0; // 4
[ P0 ++ ] = R0; // 5
[ P0 ++ ] = R0; // 6
[ P0 ++ ] = R0; // 7
[ P0 ++ ] = R0; // 8
[ P0 ++ ] = R0; // 9
[ P0 ++ ] = R0; // 10
[ P0 ++ ] = R0; // 11
[ P0 ++ ] = R0; // 12
[ P0 ++ ] = R0; // 13
[ P0 ++ ] = R0; // 14
[ P0 ++ ] = R0; // 15
LD32(p0, DCPLB_DATA0);
[ P0 ++ ] = R0; // 0
[ P0 ++ ] = R0; // 1
[ P0 ++ ] = R0; // 2
[ P0 ++ ] = R0; // 3
[ P0 ++ ] = R0; // 4
[ P0 ++ ] = R0; // 5
[ P0 ++ ] = R0; // 6
[ P0 ++ ] = R0; // 7
[ P0 ++ ] = R0; // 8
[ P0 ++ ] = R0; // 9
[ P0 ++ ] = R0; // 10
[ P0 ++ ] = R0; // 11
[ P0 ++ ] = R0; // 12
[ P0 ++ ] = R0; // 13
[ P0 ++ ] = R0; // 14
[ P0 ++ ] = R0; // 15
// Now set the CPLB entries we will need
// Data area for the desired error
WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0);
// MMR space
WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0);
WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0);
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
WR_MMR_LABEL(EVT15, int_15, p0, r1);
WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
CSYNC;
A0 = 0;
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
// But first raise interrupt 15 so we can do one test
// in supervisor mode.
RAISE 15;
NOP;
RTI;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
handler:
// generic protection exception handler
// Inputs:
// p2: addr of CPLB entry to be modified ( current test)
//
// Outputs:
// r4: SEQSTAT
// r5: DCPLB_FAULT_ADDR
// r6: DCPLB_STATUS
// r7: RETX (instruction addr where exception occurred)
R4 = SEQSTAT; // Get exception cause
R4 <<= 24; // Clear HWERRCAUSE + SFTRESET
R4 >>= 24;
// read data addr which caused exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r5);
RD_MMR(DCPLB_STATUS, p0, r6);
R7 = RETX; // get address of excepting instruction
// disable the offending CPLB entries
R2 = 0;
[ P2 ] = R2;
CSYNC;
// return from exception and re-execute offending instruction
RTX;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
int_15:
// Interrupt 15 handler - test will run in supervisor mode
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x41C6 (Z);
LD32(p2, DCPLB_DATA1);
X0_1: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1));
CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x167E (Z);
LD32(p2, DCPLB_DATA2);
X0_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2));
CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2781 (Z);
LD32(p2, DCPLB_DATA3);
X0_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3));
CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x446B (Z);
LD32(p2, DCPLB_DATA4);
X0_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4));
CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x794B (Z);
LD32(p2, DCPLB_DATA5);
X0_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5));
CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x15FB (Z);
LD32(p2, DCPLB_DATA6);
X0_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6));
CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x59E2 (Z);
LD32(p2, DCPLB_DATA7);
X0_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7));
CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1CFB (Z);
LD32(p2, DCPLB_DATA8);
X0_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8));
CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3F54 (Z);
LD32(p2, DCPLB_DATA9);
X0_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9));
CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0FF6 (Z);
LD32(p2, DCPLB_DATA10);
X0_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10));
CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0ABD (Z);
LD32(p2, DCPLB_DATA11);
X0_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11));
CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x31DF (Z);
LD32(p2, DCPLB_DATA12);
X0_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12));
CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x237C (Z);
LD32(p2, DCPLB_DATA13);
X0_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13));
CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2F1C (Z);
LD32(p2, DCPLB_DATA14);
X0_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14));
CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7DE1 (Z);
LD32(p2, DCPLB_DATA2);
X1_2: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2));
CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4487 (Z);
LD32(p2, DCPLB_DATA3);
X1_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3));
CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6201 (Z);
LD32(p2, DCPLB_DATA4);
X1_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4));
CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x52BF (Z);
LD32(p2, DCPLB_DATA5);
X1_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5));
CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6231 (Z);
LD32(p2, DCPLB_DATA6);
X1_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6));
CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63DE (Z);
LD32(p2, DCPLB_DATA7);
X1_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7));
CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6956 (Z);
LD32(p2, DCPLB_DATA8);
X1_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8));
CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1372 (Z);
LD32(p2, DCPLB_DATA9);
X1_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9));
CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x500F (Z);
LD32(p2, DCPLB_DATA10);
X1_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10));
CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2847 (Z);
LD32(p2, DCPLB_DATA11);
X1_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11));
CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2C67 (Z);
LD32(p2, DCPLB_DATA12);
X1_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12));
CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7566 (Z);
LD32(p2, DCPLB_DATA13);
X1_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13));
CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4287 (Z);
LD32(p2, DCPLB_DATA14);
X1_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14));
CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3359 (Z);
LD32(p2, DCPLB_DATA3);
X2_3: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3));
CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4DAA (Z);
LD32(p2, DCPLB_DATA4);
X2_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4));
CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6488 (Z);
LD32(p2, DCPLB_DATA5);
X2_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5));
CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x773C (Z);
LD32(p2, DCPLB_DATA6);
X2_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6));
CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6F59 (Z);
LD32(p2, DCPLB_DATA7);
X2_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7));
CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6EEA (Z);
LD32(p2, DCPLB_DATA8);
X2_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8));
CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5656 (Z);
LD32(p2, DCPLB_DATA9);
X2_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9));
CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6113 (Z);
LD32(p2, DCPLB_DATA10);
X2_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10));
CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4A7B (Z);
LD32(p2, DCPLB_DATA11);
X2_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11));
CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x31D2 (Z);
LD32(p2, DCPLB_DATA12);
X2_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12));
CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2D85 (Z);
LD32(p2, DCPLB_DATA13);
X2_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13));
CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x19A1 (Z);
LD32(p2, DCPLB_DATA14);
X2_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14));
CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x69D8 (Z);
LD32(p2, DCPLB_DATA4);
X3_4: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4));
CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x353C (Z);
LD32(p2, DCPLB_DATA5);
X3_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5));
CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3B54 (Z);
LD32(p2, DCPLB_DATA6);
X3_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6));
CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7D55 (Z);
LD32(p2, DCPLB_DATA7);
X3_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7));
CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x102F (Z);
LD32(p2, DCPLB_DATA8);
X3_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8));
CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1B37 (Z);
LD32(p2, DCPLB_DATA9);
X3_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9));
CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7AAE (Z);
LD32(p2, DCPLB_DATA10);
X3_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10));
CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5E65 (Z);
LD32(p2, DCPLB_DATA11);
X3_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11));
CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x345B (Z);
LD32(p2, DCPLB_DATA12);
X3_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12));
CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63DA (Z);
LD32(p2, DCPLB_DATA13);
X3_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13));
CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6102 (Z);
LD32(p2, DCPLB_DATA14);
X3_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14));
CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7A79 (Z);
LD32(p2, DCPLB_DATA5);
X4_5: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5));
CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0398 (Z);
LD32(p2, DCPLB_DATA6);
X4_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6));
CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x28CC (Z);
LD32(p2, DCPLB_DATA7);
X4_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7));
CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x60E3 (Z);
LD32(p2, DCPLB_DATA8);
X4_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8));
CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1F1A (Z);
LD32(p2, DCPLB_DATA9);
X4_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9));
CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4B76 (Z);
LD32(p2, DCPLB_DATA10);
X4_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10));
CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x058E (Z);
LD32(p2, DCPLB_DATA11);
X4_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11));
CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7A5F (Z);
LD32(p2, DCPLB_DATA12);
X4_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12));
CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x28D9 (Z);
LD32(p2, DCPLB_DATA13);
X4_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13));
CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0799 (Z);
LD32(p2, DCPLB_DATA14);
X4_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14));
CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x388F (Z);
LD32(p2, DCPLB_DATA6);
X5_6: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6));
CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x751F (Z);
LD32(p2, DCPLB_DATA7);
X5_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7));
CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x493F (Z);
LD32(p2, DCPLB_DATA8);
X5_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8));
CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0F36 (Z);
LD32(p2, DCPLB_DATA9);
X5_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9));
CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x48EE (Z);
LD32(p2, DCPLB_DATA10);
X5_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10));
CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2043 (Z);
LD32(p2, DCPLB_DATA11);
X5_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11));
CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3F78 (Z);
LD32(p2, DCPLB_DATA12);
X5_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12));
CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1E4D (Z);
LD32(p2, DCPLB_DATA13);
X5_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13));
CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3D0D (Z);
LD32(p2, DCPLB_DATA14);
X5_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14));
CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x33FA (Z);
LD32(p2, DCPLB_DATA7);
X6_7: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7));
CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6FBE (Z);
LD32(p2, DCPLB_DATA8);
X6_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8));
CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x36A6 (Z);
LD32(p2, DCPLB_DATA9);
X6_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9));
CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2DDA (Z);
LD32(p2, DCPLB_DATA10);
X6_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10));
CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x30E4 (Z);
LD32(p2, DCPLB_DATA11);
X6_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11));
CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0586 (Z);
LD32(p2, DCPLB_DATA12);
X6_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12));
CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x148E (Z);
LD32(p2, DCPLB_DATA13);
X6_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13));
CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x42DC (Z);
LD32(p2, DCPLB_DATA14);
X6_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14));
CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5929 (Z);
LD32(p2, DCPLB_DATA8);
X7_8: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8));
CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0C6D (Z);
LD32(p2, DCPLB_DATA9);
X7_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9));
CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x334E (Z);
LD32(p2, DCPLB_DATA10);
X7_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10));
CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x62FF (Z);
LD32(p2, DCPLB_DATA11);
X7_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11));
CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1F56 (Z);
LD32(p2, DCPLB_DATA12);
X7_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12));
CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2BE1 (Z);
LD32(p2, DCPLB_DATA13);
X7_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13));
CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1D70 (Z);
LD32(p2, DCPLB_DATA14);
X7_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14));
CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2620 (Z);
LD32(p2, DCPLB_DATA9);
X8_9: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9));
CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x26FB (Z);
LD32(p2, DCPLB_DATA10);
X8_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10));
CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x718F (Z);
LD32(p2, DCPLB_DATA11);
X8_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11));
CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x04B1 (Z);
LD32(p2, DCPLB_DATA12);
X8_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12));
CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5358 (Z);
LD32(p2, DCPLB_DATA13);
X8_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13));
CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3305 (Z);
LD32(p2, DCPLB_DATA14);
X8_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14));
CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5690 (Z);
LD32(p2, DCPLB_DATA10);
X9_10: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10));
CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5DC5 (Z);
LD32(p2, DCPLB_DATA11);
X9_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11));
CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7809 (Z);
LD32(p2, DCPLB_DATA12);
X9_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12));
CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1DDC (Z);
LD32(p2, DCPLB_DATA13);
X9_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13));
CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6B53 (Z);
LD32(p2, DCPLB_DATA14);
X9_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14));
CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7BCD (Z);
LD32(p2, DCPLB_DATA11);
X10_11: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11));
CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63AA (Z);
LD32(p2, DCPLB_DATA12);
X10_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12));
CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x373B (Z);
LD32(p2, DCPLB_DATA13);
X10_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13));
CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5648 (Z);
LD32(p2, DCPLB_DATA14);
X10_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14));
CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6799 (Z);
LD32(p2, DCPLB_DATA12);
X11_12: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12));
CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1452 (Z);
LD32(p2, DCPLB_DATA13);
X11_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13));
CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x23D3 (Z);
LD32(p2, DCPLB_DATA14);
X11_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14));
CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1152 (Z);
LD32(p2, DCPLB_DATA13);
X12_13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA12, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13));
CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6E9D (Z);
LD32(p2, DCPLB_DATA14);
X12_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA12, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14));
CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6006 (Z);
LD32(p2, DCPLB_DATA14);
X13_14: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA13, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14));
CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
User:
NOP;
dbg_pass;
|
stsp/binutils-ia16
| 3,068
|
sim/testsuite/bfin/c_dsp32mac_mix.s
|
//Original:/testcases/core/c_dsp32mac_mix/c_dsp32mac_mix.dsp
// Spec Reference: dsp32mac mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246700f;
A1 = A0 = 0;
A0.L = R0.L;
A0.H = R0.H;
// test the ROUNDING only on signed fraction T=1
R0.H = (A1 = R4.L * R5.L), R0.L = (A0 = R4.L * R5.H) (T);
R1.H = (A1 = R4.H * R5.L), R1.L = (A0 = R4.H * R5.H) (T);
R2.H = (A1 = R6.L * R7.L), R2.L = (A0 = R6.H * R7.H) (T);
R3.H = (A1 = R6.L * R7.H), R3.L = (A0 = R6.L * R7.L) (T);
CHECKREG r0, 0x066DF95C;
CHECKREG r1, 0x0E0AF17F;
CHECKREG r2, 0x000B0001;
CHECKREG r3, 0x0001000B;
// When two results are stored to a single register, they must be rounded
// or truncated and stored to the 2 halves of a single destination reg dst
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
// The result accumulated in A0 and A1, and stored to a reg half
R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R3.H = A1 , A0 = R7.H * R6.L (T);
R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L;
A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2);
CHECKREG r2, 0xFFD15679;
CHECKREG r3, 0xFFD00007;
CHECKREG r4, 0x00074569;
CHECKREG r5, 0x12358000;
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
// The result accumulated in A0 and A1, and stored to a reg
R5.H = (A1 = R1.L * R0.H), R5.L = (A0 = R1.H * R0.L) (TFU);
R6.H = (A1 = R3.L * R2.H) (M), R6.L = (A0 = R3.H * R2.L) (TFU);
R7.H = (A1 = R1.L * R0.H) (M), R7.L = (A0 = R1.H * R0.L) (IH); // hi-word extraction
CHECKREG r5, 0x133C3D94;
CHECKREG r6, 0x00040002;
CHECKREG r7, 0xFFE8E2D7;
// The result accumulated in A0 and A1, and stored to a reg pair
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R5 = ( A1 = R1.L * R0.H );
R7 = ( A1 += R1.L * R0.H ) (M), A0 -= R1.H * R0.L;
CHECKREG r2, 0xA1245679;
CHECKREG r3, 0xFFD0BC98;
CHECKREG r4, 0xEFBC4569;
CHECKREG r5, 0xFFD0BC98;
CHECKREG r6, 0x000C000D;
CHECKREG r7, 0xFFB91AE4;
A1 = R1.L * R0.H, R2 = ( A0 = R1.H * R0.L );
A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L );
CHECKREG r2, 0xC5AEB798;
CHECKREG r3, 0xFFD0BC98;
CHECKREG r4, 0xEFBC4569;
CHECKREG r5, 0xFFD0BC98;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xFFB91AE4;
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R3 = ( A1 -= R5.L * R4.H ), R2 = ( A0 -= R5.H * R4.L ) (S2RND);
R3 = ( A1 -= R1.L * R0.H ) (M), R2 = ( A0 += R1.H * R0.L ) (S2RND);
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x0002CBB0;
pass
|
stsp/binutils-ia16
| 2,772
|
sim/testsuite/bfin/c_dspldst_st_drlo_i.s
|
//Original:/testcases/core/c_dspldst_st_drlo_i/c_dspldst_st_drlo_i.dsp
// Spec Reference: c_dspldst st_drlo_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
W [ I0 ] = R0.L;
W [ I1 ] = R1.L;
W [ I2 ] = R2.L;
W [ I3 ] = R3.L;
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r4, 0x00014507;
CHECKREG r5, 0x20215618;
CHECKREG r6, 0x40416729;
CHECKREG r7, 0x6061783A;
W [ I0 ] = R3.L;
W [ I1 ] = R2.L;
W [ I2 ] = R1.L;
W [ I3 ] = R0.L;
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r4, 0x0001783A;
CHECKREG r5, 0x20216729;
CHECKREG r6, 0x40415618;
CHECKREG r7, 0x60614507;
imm32 r0, 0x1a334507;
imm32 r1, 0x12345618;
imm32 r2, 0x2c3e6729;
imm32 r3, 0x3d54f83a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f789c5c;
imm32 r6, 0x6089ad7d;
imm32 r7, 0x739abc88;
W [ I0 ] = R4.L;
W [ I1 ] = R5.L;
W [ I2 ] = R6.L;
W [ I3 ] = R7.L;
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I2 ];
R3 = [ I3 ];
CHECKREG r0, 0x0001594B;
CHECKREG r1, 0x20219C5C;
CHECKREG r2, 0x4041AD7D;
CHECKREG r3, 0x6061BC88;
W [ I0 ] = R7.L;
W [ I1 ] = R6.L;
W [ I2 ] = R5.L;
W [ I3 ] = R4.L;
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I2 ];
R3 = [ I3 ];
CHECKREG r0, 0x0001BC88;
CHECKREG r1, 0x2021AD7D;
CHECKREG r2, 0x40419C5C;
CHECKREG r3, 0x6061594B;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 1,667
|
sim/testsuite/bfin/c_br_preg_killed_ac.s
|
//Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
P4 = 4;
P2 = 2;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
IF !CC JUMP LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
JUMP ( PC + P4 ); //brf LABEL2; // (bp);
CC = ! CC;
LABEL2:
JUMP ( PC + P4 ); //brf LABEL3; // (bp);
R2 = - R2; // ALU2op killed
LABEL3:
JUMP ( PC + P4 ); //brf LABEL4;
R3 <<= 2; // LOGI2op killed
LABEL4:
JUMP ( PC + P4 ); //brf LABEL5;
R0 = R1 + R2; // COMP3op killed
LABEL5:
JUMP ( PC + P4 ); //brf LABEL6;
R4 += 3; // COMPI2opD killed
LABEL6:
JUMP ( PC + P4 ); //brf LABEL7; // (bp);
R5 = 25; // LDIMMHALF killed
LABEL7:
JUMP ( PC + P4 ); //brf LABEL8;
R6 = CC; // CC2REG killed
LABEL8:
JUMP ( PC + P4 ); //brf LABEL9;
JUMP ( PC + P2 ); //BAD1; // UJUMP killed
LABEL9:
JUMP ( PC + P4 ); //brf LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
|
stsp/binutils-ia16
| 1,128
|
sim/testsuite/bfin/lsetup.s
|
# Blackfin testcase for playing with LSETUP
# mach: bfin
.include "testutils.inc"
start
R0 = 0x123;
P0 = R0;
LSETUP (.L1, .L1) LC0 = P0;
.L1:
R0 += -1;
R1 = 0;
CC = R1 == R0;
IF CC JUMP 1f;
fail
1:
p0=10;
loadsym i0, _buf
imm32 r0, 0x12345678
LSETUP(.L2, .L3) lc0 = p0;
.L2:
[i0++] = r0;
.L3:
[i0++] = r0;
loadsym R1, _buf
R0 = 0x50;
R1 = R0 + R1;
R0 = I0;
CC = R0 == R1;
if CC JUMP 2f;
fail
2:
r5=10;
p1=r5;
r7=20;
lsetup (.L4, .L5) lc0=p1;
.L4:
nop;
nop;
nop;
nop;
jump .L5;
nop;
nop;
nop;
.L5:
r7 += -1;
R0 = 10 (Z);
CC = R7 == R0;
if CC jump 3f;
fail
3:
r1 = 1;
r2 = 2;
r0 = 0;
p1 = 10;
loadsym p0, _buf;
lsetup (.L6, .L7) lc0 = p1;
.L6:
[p0++] = r1;
.L7:
[p0++] = r2;
r3 = P0;
loadsym r1, _buf
r0 = 80;
r1 = r1 + r0;
CC = R1 == R3
if CC jump 4f;
fail
4:
R0 = 1;
R1 = 2;
R2 = 3;
R4 = 4;
P1 = R1;
LSETUP (.L8, .L8) LC0 = P1;
R5 = 5;
R6 = 6;
R7 = 7;
.L8:
R1 += 1;
R7 = 4;
CC = R7 == R1;
if CC jump 5f;
fail
5:
P1 = R1;
LSETUP (.L9, .L9 ) LC1 = P1;
.L9:
R1 += 1;
R7 = 8;
if CC jump 6f;
fail
6:
pass
.data
_buf:
.rept 0x80
.long 0
.endr
|
stsp/binutils-ia16
| 6,546
|
sim/testsuite/bfin/c_mode_user.S
|
//Original:/proj/frio/dv/testcases/core/c_mode_user/c_mode_user.dsp
// Spec Reference: mode_user
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
A0 = 0; // reset accumulators
A1 = 0;
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI; // execute this instr put us in USER mode
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// USER MODE & go to different RAISE in USER mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
A1 = A0 = 0;
ASTAT = R0;
// R-reg to P-reg to R reg: stall
LD32(r0, 0x1357bdad);
LD32(r1, 0x02dfe804);
LD32(r2, 0x12345679);
LD32(r3, 0x34751975);
LD32(r4, 0x08810990);
LD32(r5, 0x01a1b0b0);
LD32(r6, 0x01c1dd00);
LD32(r7, 0x01e1fff0);
R5 = R3.L * R1.L, R4 = R3.L * R1.L; // dsp32mult_pair
P4 = R5;
R6 = P4;
R1 = ( A1 += R5.L * R6.H ), A0 = R5.H * R6.L; // dsp32mac_pair
P3 = A0.w;
P4 = A1.w;
A1 = A1 (S), A0 = A0 (S); // dsp32alu_sat_aa
R6 = A0.w;
R7 = A1.w;
R0 = R7;
R2 = R0; // regmv
R2 >>>= R3; // c_alu2op_arith_r_sft.dsp
R4 = R2 - R1;
R5.L = ASHIFT R4.L BY R3.L;
R6 += -3; //c_compi2opd_dr_add_i7_n.dsp
I2 = R6;
I2 += 2;
I2 += M1;
R7 = I2;
CHECKREG(r0, 0x015AF820);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x34751975);
CHECKREG(r4, 0xFEA507E0);
CHECKREG(r5, 0xFB3A0000);
CHECKREG(r6, 0x015AF81D);
CHECKREG(r7, 0x015AF81F);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x015AF81F);
CHECKREG(r3, 0x00000000);
CHECKREG(r4, 0xFEA507E0);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = RETN;
R0 += 2;
RETN = r0;
RTN;
XHANDLE: // Exception Handler 3
R1 = RETX;
R0 += 1;
R1 += 2;
R2 += 1;
R3 += 1;
R4 += 1;
R5 += 1;
R6 += 1;
R7 += 1;
RETX = r1;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = RETI;
R2 += 2;
RETI = r2;
RTI;
THANDLE: // Timer Handler 6
R3 = RETI;
R3 += 2;
RETI = r3;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = RETI;
R4 += 2;
RETI = r4;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = RETI;
R5 += 2;
RETI = r5;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = RETI;
R6 += 2;
RETI = r6;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = RETI;
R7 += 2;
RETI = r7;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = RETI;
R0 += 2;
RETI = r0;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = RETI;
R1 += 2;
RETI = r1;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = RETI;
R2 += 2;
RETI = r2;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = RETI;
R3 += 2;
RETI = r3;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
// .space (STACKSIZE); // adding this may solve the problem
|
stsp/binutils-ia16
| 7,791
|
sim/testsuite/bfin/c_mmr_interr_ctl.s
|
# Blackfin testcase for the CEC
# mach: bfin
# sim: --environment operating
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_P_REGS 0;
INIT_I_REGS 0;
INIT_M_REGS 0;
INIT_L_REGS 0;
INIT_B_REGS 0;
CLI R1; // inhibit events during MMR writes
loadsym sp, USTACK; // setup the user stack pointer
usp = sp; // and frame pointer
loadsym sp, KSTACK; // setup the stack pointer
fp = sp; // and frame pointer
imm32 p0, 0xFFE02000;
loadsym r0, EHANDLE; // Emulation Handler (Int0)
[p0++] = r0;
loadsym r0, RHANDLE; // Reset Handler (Int1)
[p0++] = r0;
loadsym r0, NHANDLE; // NMI Handler (Int2)
[p0++] = r0;
loadsym r0, XHANDLE; // Exception Handler (Int3)
[p0++] = r0;
[p0++] = r0; // EVT4 not used global Interr Enable (INT4)
loadsym r0, HWHANDLE; // HW Error Handler (Int5)
[p0++] = r0;
loadsym r0, THANDLE; // Timer Handler (Int6)
[p0++] = r0;
loadsym r0, I7HANDLE; // IVG7 Handler
[p0++] = r0;
loadsym r0, I8HANDLE; // IVG8 Handler
[p0++] = r0;
loadsym r0, I9HANDLE; // IVG9 Handler
[p0++] = r0;
loadsym r0, I10HANDLE;// IVG10 Handler
[p0++] = r0;
loadsym r0, I11HANDLE;// IVG11 Handler
[p0++] = r0;
loadsym r0, I12HANDLE;// IVG12 Handler
[p0++] = r0;
loadsym r0, I13HANDLE;// IVG13 Handler
[p0++] = r0;
loadsym r0, I14HANDLE;// IVG14 Handler
[p0++] = r0;
loadsym r0, I15HANDLE;// IVG15 Handler
[p0++] = r0;
imm32 p0, 0xFFE02100 // EVT_OVERRIDE
r0 = 0;
[p0++] = r0;
r1 = -1; // Change this to mask interrupts (*)
csync; // wait for MMR writes to finish
sti r1; // sync and reenable events (implicit write to IMASK)
imm32 p0, 0xFFE02104;
r0 = [p0];
// ckeck that sti allows the lower 5 bits of imask to be written
CHECKREG r0, 0xffff;
DUMMY:
r0 = 0 (z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
loadsym r0, STARTUSER;// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
loadsym p1, BEGIN;
imm32 p0, (0xFFE02000 + 4 * 15);
CLI R1; // inhibit events during write to MMR
[p0] = p1; // IVG15 (General) handler (Int 15) load with start
csync; // wait for it
sti r1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
// *********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[--sp] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// EVTx
// wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000
imm32 p0, 0xFFE02000;
imm32 r0, 0x00000000
[p0] = r0;
// wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004
imm32 p0, 0xFFE02004;
imm32 r0, 0x00000000
[p0] = r0;
// wrt-rd EVT2 = 0xFFE02008
imm32 p0, 0xFFE02008
imm32 r0, 0xE1DE5D1C
[p0] = r0;
// wrt-rd EVT3 = 0xFFE0200C
imm32 p0, 0xFFE0200C
imm32 r0, 0x9CC20332
[p0] = r0;
// wrt-rd EVT4 = 0xFFE02010
imm32 p0, 0xFFE02010
imm32 r0, 0x00000000
[p0] = r0;
// wrt-rd EVT5 = 0xFFE02014
imm32 p0, 0xFFE02014
imm32 r0, 0x55552345
[p0] = r0;
// wrt-rd EVT6 = 0xFFE02018
imm32 p0, 0xFFE02018
imm32 r0, 0x66663456
[p0] = r0;
// wrt-rd EVT7 = 0xFFE0201C
imm32 p0, 0xFFE0201C
imm32 r0, 0x77774567
[p0] = r0;
// wrt-rd EVT8 = 0xFFE02020
imm32 p0, 0xFFE02020
imm32 r0, 0x88885678
[p0] = r0;
// wrt-rd EVT9 = 0xFFE02024
imm32 p0, 0xFFE02024
imm32 r0, 0x99996789
[p0] = r0;
// wrt-rd EVT10 = 0xFFE02028
imm32 p0, 0xFFE02028
imm32 r0, 0xaaaa1234
[p0] = r0;
// wrt-rd EVT11 = 0xFFE0202C
imm32 p0, 0xFFE0202C
imm32 r0, 0xBBBBABC6
[p0] = r0;
// wrt-rd EVT12 = 0xFFE02030
imm32 p0, 0xFFE02030
imm32 r0, 0xCCCCABC6
[p0] = r0;
// wrt-rd EVT13 = 0xFFE02034
imm32 p0, 0xFFE02034
imm32 r0, 0xDDDDABC6
[p0] = r0;
// wrt-rd EVT14 = 0xFFE02038
imm32 p0, 0xFFE02038
imm32 r0, 0xEEEEABC6
[p0] = r0;
// wrt-rd EVT15 = 0xFFE0203C
imm32 p0, 0xFFE0203C
imm32 r0, 0xFFFFABC6
[p0] = r0;
// wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100
imm32 p0, 0xFFE02100
imm32 r0, 0x000001ff
[p0] = r0;
// wrt-rd IMASK: 16 bits = 0xFFE02104
imm32 p0, 0xFFE02104
imm32 r0, 0x00000fff
[p0] = r0;
// wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108
imm32 p0, 0xFFE02108
imm32 r0, 0x00000000
//[p0] = r0;
raise 12;
raise 13;
// wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C
imm32 p0, 0xFFE0210C
imm32 r0, 0x00000000
//[p0] = r0;
csync;
// *** read ops
imm32 p0, 0xFFE02000
r0 = [p0];
CHECKREG r0, 0;
imm32 p0, 0xFFE02004
r1 = [p0];
CHECKREG r1, 0;
imm32 p0, 0xFFE02008
r2 = [p0];
CHECKREG r2, 0xE1DE5D1C;
imm32 p0, 0xFFE0200C
r3 = [p0];
CHECKREG r3, 0x9CC20332;
imm32 p0, 0xFFE02014
r4 = [p0];
imm32 p0, 0xFFE02018
r5 = [p0];
imm32 p0, 0xFFE0201C
r6 = [p0];
imm32 p0, 0xFFE02020 /* EVT8 */
r7 = [p0];
CHECKREG r0, 0x00000000;
//CHECKREG(r1, 0x00000000); /// mismatch = 00
CHECKREG r2, 0xE1DE5D1C;
CHECKREG r3, 0x9CC20332;
CHECKREG r4, 0x55552345;
CHECKREG r5, 0x66663456;
CHECKREG r6, 0x77774567;
CHECKREG r7, 0x88885678;
imm32 p0, 0xFFE02024 /* EVT9 */
r0 = [p0];
imm32 p0, 0xFFE02028 /* EVT10 */
r1 = [p0];
imm32 p0, 0xFFE0202C /* EVT11 */
r2 = [p0];
imm32 p0, 0xFFE02030 /* EVT12 */
r3 = [p0];
imm32 p0, 0xFFE02034 /* EVT13 */
r4 = [p0];
imm32 p0, 0xFFE02038 /* EVT14 */
r5 = [p0];
imm32 p0, 0xFFE0203C /* EVT15 */
r6 = [p0];
CHECKREG r0, 0x99996789;
CHECKREG r1, 0xaaaa1234;
CHECKREG r2, 0xBBBBABC6;
CHECKREG r3, 0xCCCCABC6;
CHECKREG r4, 0xDDDDABC6;
CHECKREG r5, 0xEEEEABC6;
CHECKREG r6, 0xFFFFABC6;
imm32 p0, 0xFFE02100 /* EVT_OVERRIDE */
r0 = [p0];
imm32 p0, 0xFFE02104 /* IMASK */
r1 = [p0];
imm32 p0, 0xFFE02108 /* IPEND */
r2 = [p0];
imm32 p0, 0xFFE0210C /* ILAT */
r3 = [p0];
CHECKREG r0, 0x000001ff;
CHECKREG r1, 0x00000fff; /* XXX: original had 0xfe0 ?? */
CHECKREG r2, 0x00008000;
CHECKREG r3, 0x00003000;
dbg_pass;
// *********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
r0 = 2;
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
r2 = 5;
RTI;
THANDLE: // Timer Handler 6
r3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
r4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
r5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
r6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
r7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
r0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
r1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
r2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
r3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
r4 = 15;
RTI;
nop;nop;nop;nop;nop;nop;nop; // needed for icache bug
//
// Data Segment
//
.data
// Stack Segments (Both Kernel and User)
.rep 0x10
.byte 0
.endr
KSTACK:
.rep 0x10
.byte 0
.endr
USTACK:
|
stsp/binutils-ia16
| 3,933
|
sim/testsuite/bfin/c_dsp32mult_pair_m_u.s
|
//Original:/testcases/core/c_dsp32mult_pair_m_u/c_dsp32mult_pair_m_u.dsp
// Spec Reference: dsp32mult pair MUNOP u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm32 r7, 0xd246712f;
R0 = R0.L * R0.L (FU);
R2 = R0.L * R1.H (FU);
R4 = R1.H * R1.H (FU);
R6 = R0.L * R0.L (FU);
CHECKREG r0, 0x1CFCE159;
CHECKREG r1, 0x9F7A5127;
CHECKREG r2, 0x8C61AB6A;
CHECKREG r3, 0x00069027;
CHECKREG r4, 0x6358C624;
CHECKREG r5, 0x10ACEF2B;
CHECKREG r6, 0xC65D90F1;
CHECKREG r7, 0xD246712F;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R0 = R2.L * R2.L (FU);
R2 = R2.L * R3.H (FU);
R4 = R3.H * R2.H (FU);
R6 = R2.L * R3.L (FU);
CHECKREG r0, 0x831CD0F9;
CHECKREG r1, 0x6FBA5137;
CHECKREG r2, 0x67121B3E;
CHECKREG r3, 0x90060037;
CHECKREG r4, 0x39FC8A6C;
CHECKREG r5, 0xB0ACEF3B;
CHECKREG r6, 0x0005DA52;
CHECKREG r7, 0x12467003;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x43246755;
imm32 r3, 0x05060055;
imm32 r4, 0x906bc509;
imm32 r5, 0x10a7ef5b;
imm32 r6, 0xb00c805d;
imm32 r7, 0x1246795f;
R0 = R4.L * R4.L (FU);
R2 = R4.L * R5.H (FU);
R4 = R5.H * R5.H (FU);
R6 = R4.L * R5.L (FU);
CHECKREG r0, 0x97A6DA51;
CHECKREG r1, 0xC4BA5157;
CHECKREG r2, 0x0CD118DF;
CHECKREG r3, 0x05060055;
CHECKREG r4, 0x01154CF1;
CHECKREG r5, 0x10A7EF5B;
CHECKREG r6, 0x47F058AB;
CHECKREG r7, 0x1246795F;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
R0 = R6.L * R6.L (FU);
R2 = R6.L * R7.H (FU);
R4 = R7.H * R7.H (FU);
R6 = R6.L * R7.L (FU);
CHECKREG r0, 0x79960E69;
CHECKREG r1, 0xEFBA5166;
CHECKREG r2, 0x0C97E7CE;
CHECKREG r3, 0xF0060066;
CHECKREG r4, 0x014DEB24;
CHECKREG r5, 0x10ACEF6B;
CHECKREG r6, 0x4D7C2F43;
CHECKREG r7, 0x1246706F;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0 = R0.L * R7.L (FU);
R2 = R1.L * R6.H (FU);
R4 = R3.H * R4.H (FU);
R6 = R4.L * R3.L (FU);
CHECKREG r0, 0x9C1770DB;
CHECKREG r1, 0xCFBA5127;
CHECKREG r2, 0x0003CDD4;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0x00036402;
CHECKREG r5, 0x10ACDFDB;
CHECKREG r6, 0x0002BC0E;
CHECKREG r7, 0x1246F00F;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R1 = R7.H * R0.H (FU);
R3 = R6.H * R1.H (FU);
R5 = R5.H * R2.L (FU);
R7 = R4.L * R3.H (FU);
CHECKREG r0, 0xAB235A75;
CHECKREG r1, 0x0C374192;
CHECKREG r2, 0x13246905;
CHECKREG r3, 0x00009294;
CHECKREG r4, 0x90ABCD09;
CHECKREG r5, 0x06D6DF5C;
CHECKREG r6, 0x000C0D0D;
CHECKREG r7, 0x00000000;
imm32 r0, 0x9b235675;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946705;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c009d;
imm32 r7, 0x12467009;
R1 = R6.H * R4.L (FU);
R3 = R5.L * R3.H (FU);
R5 = R3.H * R1.L (FU);
R7 = R1.H * R2.H (FU);
CHECKREG r0, 0x9B235675;
CHECKREG r1, 0x00075C6C;
CHECKREG r2, 0x13946705;
CHECKREG r3, 0x000838B3;
CHECKREG r4, 0x90AB9D09;
CHECKREG r5, 0x0002E360;
CHECKREG r6, 0x000C009D;
CHECKREG r7, 0x0000890C;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R4.L * R0.H (FU);
R3 = R6.H * R1.H (FU);
R5 = R1.L * R2.L (FU);
R7 = R4.H * R2.L (FU);
CHECKREG r0, 0xEB235675;
CHECKREG r1, 0xD9B7AB3B;
CHECKREG r2, 0x13E46705;
CHECKREG r3, 0x000A3494;
CHECKREG r4, 0x90ABED09;
CHECKREG r5, 0x44E81527;
CHECKREG r6, 0x000C00ED;
CHECKREG r7, 0x3A37A057;
pass
|
stsp/binutils-ia16
| 5,875
|
sim/testsuite/bfin/c_interr_timer_reload.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp
// Spec Reference: interrupt on HW TIMER auto-reload
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
// CHECK_INIT(p5, 0x00BFFFFC);
// CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
//.code 0x200
START :
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
WR_MMR(TPERIOD, 0x00000020, p0, r0);
WR_MMR(TCOUNT, 0x00000002, p0, r0);
WR_MMR(TSCALE, 0x00000005, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000020);
RD_MMR(TCOUNT, p0, r3);
CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP;
RD_MMR(TCOUNT, p0, r4);
CHECKREG(r4, 0x00000000);
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000B);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
CHECKREG(r7, 0x00000001);
R7 = 0;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TPERIOD, 0x00000020, p0, r0);
WR_MMR(TCOUNT, 0x00000003, p0, r0);
WR_MMR(TSCALE, 0x00000002, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auo-reload
CSYNC;
NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP;
// With auto reload
// Read the contents of the Timer
// CHECKREG(r7, 0x00000002);
CC = R7 == 0;
IF !CC JUMP LABEL1;
WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE
LABEL1:
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000020);
RD_MMR(TCNTL , p0, r3);
CHECKREG(r3, 0x0000000F);
WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer but not auto-reload
CSYNC;
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
RD_MMR(TCOUNT, p0, r4);
CHECKREG(r4, 0x00000000);
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000B);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP; NOP; NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_DATA_ADDR_1,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
stsp/binutils-ia16
| 5,036
|
sim/testsuite/bfin/c_dsp32mult_dr_m_s.s
|
//Original:/testcases/core/c_dsp32mult_dr_m_s/c_dsp32mult_dr_m_s.dsp
// Spec Reference: dsp32mult single dr munop s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm32 r7, 0xd24f702f;
R4.L = R0.H * R0.L (S2RND);
R5.H = R0.L * R1.L (S2RND);
R6.L = R1.L * R0.H (S2RND);
R7.L = R1.L * R1.L (S2RND);
R0.H = R0.L * R0.L (S2RND);
R1.L = R0.L * R1.L (S2RND);
R2.L = R1.H * R0.L (S2RND);
R3.H = R1.L * R1.L (S2RND);
CHECKREG r0, 0x73F45625;
CHECKREG r1, 0x9FBA6D3B;
CHECKREG r2, 0xA3FF8000;
CHECKREG r3, 0x7FFFF027;
CHECKREG r4, 0xB0ABF974;
CHECKREG r5, 0x6D3BEF2B;
CHECKREG r6, 0xC0FCF9D5;
CHECKREG r7, 0xD24F66E7;
imm32 r0, 0xeb23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b7e5;
imm32 r3, 0x9e060037;
imm32 r4, 0x80ebcd39;
imm32 r5, 0xb0aeef3b;
imm32 r6, 0xa00ce03d;
imm32 r7, 0x12467e03;
R4.H = R2.L * R2.L (S2RND);
R5.L = R2.L * R3.H (S2RND);
R6.L = R3.H * R2.L (S2RND);
R7.H = R3.L * R3.L (S2RND);
R2.H = R2.L * R2.H (S2RND);
R3.L = R2.H * R3.H (S2RND);
R0.H = R3.L * R2.L (S2RND);
R1.L = R3.L * R3.L (S2RND);
CHECKREG r0, 0xDACEA635;
CHECKREG r1, 0x6FBA1108;
CHECKREG r2, 0xEA6FB7E5;
CHECKREG r3, 0x9E062104;
CHECKREG r4, 0x513DCD39;
CHECKREG r5, 0xB0AE6E63;
CHECKREG r6, 0xA00C6E63;
CHECKREG r7, 0x00007E03;
imm32 r0, 0xdd235655;
imm32 r1, 0xc4dd5157;
imm32 r2, 0x6324d755;
imm32 r3, 0x00060055;
imm32 r4, 0x90dbc509;
imm32 r5, 0x10adef5b;
imm32 r6, 0xb00cd05d;
imm32 r7, 0x12467d5f;
R0.L = R4.L * R4.H (S2RND);
R1.H = R4.H * R5.L (S2RND);
R2.L = R5.H * R4.L (S2RND);
R3.L = R5.L * R5.L (S2RND);
R4.H = R4.L * R4.H (S2RND);
R5.L = R4.L * R5.H (S2RND);
R6.H = R5.H * R4.H (S2RND);
R7.L = R5.H * R5.H (S2RND);
CHECKREG r0, 0xDD236666;
CHECKREG r1, 0x1CE85157;
CHECKREG r2, 0x6324F0A3;
CHECKREG r3, 0x00060454;
CHECKREG r4, 0x6666C509;
CHECKREG r5, 0x10ADF0A3;
CHECKREG r6, 0x1AAED05D;
CHECKREG r7, 0x12460458;
imm32 r0, 0xcb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x1c248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90cb9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cc06d;
imm32 r7, 0x12467c6f;
// test the unsigned U=1
R0.L = R6.L * R6.L (S2RND);
R1.H = R6.H * R7.L (S2RND);
R2.L = R7.L * R6.L (S2RND);
R3.L = R7.L * R7.L (S2RND);
R6.L = R6.L * R6.L (S2RND);
R7.L = R6.L * R7.L (S2RND);
R4.L = R7.L * R6.L (S2RND);
R5.L = R7.L * R7.L (S2RND);
CHECKREG r0, 0xCB233F27;
CHECKREG r1, 0x80005166;
CHECKREG r2, 0x1C248465;
CHECKREG r3, 0xF0067FFF;
CHECKREG r4, 0x90CB7929;
CHECKREG r5, 0x10AC7FFF;
CHECKREG r6, 0x800C3F27;
CHECKREG r7, 0x12467AC9;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0xe0060007;
imm32 r4, 0x9eabcd09;
imm32 r5, 0x10ecdfdb;
imm32 r6, 0x000e000d;
imm32 r7, 0x1246e00f;
R0.H = R0.L * R7.H (S2RND);
R1.L = R1.H * R6.H (S2RND);
R2.L = R2.L * R5.L (S2RND);
R3.H = R3.H * R4.H (S2RND);
R4.L = R4.L * R3.H (S2RND);
R5.L = R5.H * R2.H (S2RND);
R6.H = R6.H * R1.L (S2RND);
R7.L = R7.L * R0.H (S2RND);
CHECKREG r0, 0xE66FA675;
CHECKREG r1, 0xCFBAFFF5;
CHECKREG r2, 0x1324CC42;
CHECKREG r3, 0x30A10007;
CHECKREG r4, 0x9EABD947;
CHECKREG r5, 0x10EC0510;
CHECKREG r6, 0x0000000D;
CHECKREG r7, 0x12460CC3;
imm32 r0, 0x9b235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x93246905;
imm32 r3, 0x09060007;
imm32 r4, 0x909bcd09;
imm32 r5, 0x10a9e9db;
imm32 r6, 0x000c9d0d;
imm32 r7, 0x1246790f;
R0.L = R7.L * R0.H (S2RND);
R1.L = R6.L * R1.L (S2RND);
R2.H = R5.L * R2.L (S2RND);
R3.L = R4.H * R3.L (S2RND);
R4.L = R3.H * R4.H (S2RND);
R5.H = R2.H * R5.L (S2RND);
R6.L = R1.H * R6.L (S2RND);
R7.L = R0.L * R7.L (S2RND);
CHECKREG r0, 0x9B238000;
CHECKREG r1, 0xCFBA8288;
CHECKREG r2, 0xDBAA6905;
CHECKREG r3, 0x0906FFF4;
CHECKREG r4, 0x909BF04B;
CHECKREG r5, 0x0C93E9DB;
CHECKREG r6, 0x000C4AA2;
CHECKREG r7, 0x12468000;
imm32 r0, 0xa9235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x08060007;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a88fdb;
imm32 r6, 0x000c080d;
imm32 r7, 0x1246708f;
R2.L = R4.L * R6.L (S2RND);
R3.L = R2.H * R2.L (S2RND);
R0.H = R2.L * R3.L, R0.L = R2.H * R3.H (S2RND);
R1.H = R3.L * R1.L (S2RND);
R4.L = R4.H * R0.L (S2RND);
R5.L = R5.L * R5.L (S2RND);
R6.L = R6.L * R5.H (S2RND);
R7.H = R6.H * R7.L (S2RND);
CHECKREG r0, 0x00310266;
CHECKREG r1, 0xFD915127;
CHECKREG r2, 0x1324F997;
CHECKREG r3, 0x0806FE15;
CHECKREG r4, 0x908BFBD3;
CHECKREG r5, 0x10A87FFF;
CHECKREG r6, 0x000C0218;
CHECKREG r7, 0x0015708F;
imm32 r0, 0x7b235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x17246705;
imm32 r3, 0x00760007;
imm32 r4, 0x907bcd09;
imm32 r5, 0x10a7efdb;
imm32 r6, 0x000c700d;
imm32 r7, 0x1246770f;
R4.L = R5.L * R2.L (S2RND);
R6.L = R6.L * R3.H (S2RND);
R0.H = R7.L * R4.H (S2RND);
R1.L = R0.H * R5.L (S2RND);
R2.L = R1.L * R6.L (S2RND);
R5.L = R2.L * R7.H (S2RND);
R3.H = R3.H * R0.L (S2RND);
R7.L = R4.H * R1.H (S2RND);
CHECKREG r0, 0x80005675;
CHECKREG r1, 0xCFBA204A;
CHECKREG r2, 0x17240068;
CHECKREG r3, 0x009F0007;
CHECKREG r4, 0x907BE603;
CHECKREG r5, 0x10A7001E;
CHECKREG r6, 0x000C00CF;
CHECKREG r7, 0x1246541E;
pass
|
stsp/binutils-ia16
| 8,283
|
sim/testsuite/bfin/c_interr_timer.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp
// Spec Reference: interrupt on HW TIMER
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
// CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
//.code 0x200
START :
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR(0) (active state)
WR_MMR(TPERIOD, 0x00000050, p0, r0);
// WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TCOUNT, 0x00000000, p0, r0);
WR_MMR(TSCALE, 0x00000000, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000050);
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1))
CSYNC; // TIMER interrupt
RD_MMR(TCOUNT, p0, r3);
CSYNC;
CHECKREG(r3, 0x00000000);
CHECKREG(r7, 0x00000001);
WR_MMR(TCNTL, 0x00000001, p0, r0); // enable Timer (TMPWR(0), TMREN(1)=0)
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1))
CSYNC;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
RD_MMR(TCOUNT, p0, r4);
CHECKREG(r4, 0x00000000);
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000B);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Power, EN -> interr
CSYNC;
CHECKREG(r7, 0x00000003); // 3 interr already happened
R7 = 0; // reset r7
WR_MMR(TPERIOD, 0x00000040, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000002, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto load
CSYNC;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label4;
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label5: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label6;
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
label4: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
JUMP.S label5;
R5.L = 0x2222; // Will be killed
R5.H = 0x2222; // Will be killed
NOP;
NOP;
NOP;
NOP;
label6: R3.H = 0x7999;
R3.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// With auto reload
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000040);
// CHECKREG(r7, 0x00000002);
CC = R7 == 0;
IF !CC JUMP LABEL1;
WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE
LABEL1:
NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
RD_MMR(TCNTL , p0, r3);
CHECKREG(r3, 0x0000000F);
WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer
CSYNC;
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000040);
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
RD_MMR(TCOUNT, p0, r4);
CHECKREG(r4, 0x00000000);
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000B);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP; NOP; NOP;
WR_MMR(TPERIOD, 0x00000060, p0, r0);
CSYNC;
NOP;
RD_MMR(TPERIOD, p0, r6);
CHECKREG(r6, 0x00000060);
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_DATA_ADDR_1,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
stsp/binutils-ia16
| 7,518
|
sim/testsuite/bfin/c_seq_ex2_raise_mmrj_mvpop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmrj_mvpop/c_seq_ex2_raise_mmrj_mvpop.dsp
// Spec Reference: sequencer stage ex2 (raise+ mmr + jump+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
LD32(r0, 0x55552345);
RAISE 2; // RTN
[ P1 ] = R0;
JUMP.S LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
CSYNC;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
RAISE 6; // RTI
R0 = [ P1 ];
JUMP.S LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
CHECKREG(r0, 0x55552345);
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
RAISE 8; // RTI
R0 = [ P1 ];
JUMP.S LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
CHECKREG(r0, 0x55552345);
RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 2,387
|
sim/testsuite/bfin/m4.s
|
// MAC test program.
// Test basic edge values
// SIGNED INTEGER mode
// test ops: "+=" "-=" "=" "NOP"
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// 0x7fff * 0x7fff = 0x003fff0001
A1 = A0 = 0;
A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0001 );
DBGA ( R6.H , 0x3fff );
DBGA ( R7.L , 0x0000 );
// 0x8000 * 0x7fff = 0xffc0008000
A1 = A0 = 0;
A1 += R0.H * R1.L, A0 += R0.H * R1.L (IS);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x8000 );
DBGA ( R6.H , 0xc000 );
DBGA ( R7.L , 0xffff );
// 0x8000 * 0x8000 = 0x0040000000
A1 = A0 = 0;
A1 += R0.H * R1.H, A0 += R0.H * R1.H (IS);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x4000 );
DBGA ( R7.L , 0x0000 );
// saturate positive by first loading large value into accums
// expected value is 0x7fffffffff
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.w = R2;
A0.x = R3.L;
A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0x007f );
// saturate negative
// expected value is 0x8000000000
A1 = A0 = 0;
A1.x = R4.L;
A0.x = R4.L;
A1 += R0.L * R1.H, A0 += R0.L * R1.H (IS);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xff80 );
// saturate positive with "-="
// expected value is 0x7fffffffff
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.w = R2;
A0.x = R3.L;
A1 -= R0.H * R1.L, A0 -= R0.H * R1.L (IS);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0x007f );
// saturate negative with "-="
// expected value is 0x8000000000
A1 = A0 = 0;
A1.x = R4.L;
A0.x = R4.L;
A1 -= R0.L * R1.L, A0 -= R0.L * R1.L (IS);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xff80 );
// 0x8000 * 0x8000 = 0xffc0000000 with "-="
A1 = A0 = 0;
A1 -= R0.H * R1.H, A0 -= R0.H * R1.H (IS);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0xc000 );
DBGA ( R7.L , 0xffff );
pass
.data 0x1000;
data0:
.dw 0x7fff
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
stsp/binutils-ia16
| 4,864
|
sim/testsuite/bfin/c_interr_timer_tcount.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp
// Spec Reference: interrupt on HW TIMER tcount
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
// CHECK_INIT(p5, 0x00BFFFFC);
// CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
//.code 0x200
START :
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
WR_MMR(TPERIOD, 0x00000010, p0, r0);
WR_MMR(TCOUNT, 0x00000002, p0, r0);
WR_MMR(TSCALE, 0x00000001, p0, r0);
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000B);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
CHECKREG(r7, 0x00000001);
R7 = 0;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TPERIOD, 0x00000010, p0, r0);
WR_MMR(TCOUNT, 0x00000002, p0, r0);
WR_MMR(TSCALE, 0x00000003, p0, r0);
WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer
CSYNC;
NOP;
NOP;
// Read the contents of the Timer
RD_MMR(TCNTL , p0, r3);
CHECKREG(r3, 0x0000000B);
CHECKREG(r7, 0x00000001);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP; NOP; NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_DATA_ADDR_1,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
stsp/binutils-ia16
| 1,806
|
sim/testsuite/bfin/se_all64bitg1opcodes.S
|
/*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 1)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0x0000 to 0xffff
*/
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
#define SE_ALL_BITS 16
#include "se_allopcodes.h"
.macro se_all_load_insn
R2 = W[P5 + 4];
R0 = R2;
.endm
.macro se_all_next_insn
/* increment, and go again. */
R0 = R2;
R0 += 1;
/* finish once we hit the 32bit limit */
imm32 R1, 0x10000;
CC = R1 == R0;
IF CC JUMP pass_lvl;
W[P5 + 4] = R0;
.endm
.macro se_all_insn_init
MNOP || NOP || NOP;
.endm
.macro se_all_insn_table
/* this table must be sorted, and end with zero */
/* start end SEQSTAT */
.dw 0x0001, 0x7fff, 0x22
.dw 0x9040, 0x9040, 0x22
.dw 0x9049, 0x9049, 0x22
.dw 0x9052, 0x9052, 0x22
.dw 0x905b, 0x905b, 0x22
.dw 0x9064, 0x9064, 0x22
.dw 0x906d, 0x906d, 0x22
.dw 0x9076, 0x9076, 0x22
.dw 0x907f, 0x907f, 0x22
.dw 0x90c0, 0x90c0, 0x22
.dw 0x90c9, 0x90c9, 0x22
.dw 0x90d2, 0x90d2, 0x22
.dw 0x90db, 0x90db, 0x22
.dw 0x90e4, 0x90e4, 0x22
.dw 0x90ed, 0x90ed, 0x22
.dw 0x90f6, 0x90f6, 0x22
.dw 0x90ff, 0x90ff, 0x22
.dw 0x9180, 0x91ff, 0x22
.dw 0x9380, 0x93ff, 0x22
.dw 0x9580, 0x95ff, 0x22
.dw 0x9640, 0x967f, 0x22
.dw 0x96c0, 0x96ff, 0x22
.dw 0x9740, 0x97ff, 0x22
.dw 0x9980, 0x99ff, 0x22
.dw 0x9a40, 0x9a7f, 0x22
.dw 0x9ac0, 0x9aff, 0x22
.dw 0x9b40, 0x9bff, 0x22
.dw 0x9c60, 0x9c7f, 0x22
.dw 0x9ce0, 0x9cff, 0x22
.dw 0x9d60, 0x9d7f, 0x22
.dw 0x9ef0, 0x9eff, 0x22
.dw 0x9f70, 0x9f7f, 0x22
.dw 0xc000, 0xffff, 0x22
.dw 0x0000, 0x0000, 0x00
.endm
se_all_test
|
stsp/binutils-ia16
| 3,322
|
sim/testsuite/bfin/s15.s
|
// reg-based SHIFT test program.
# mach: bfin
.include "testutils.inc"
start
// Test FEXT with no sign extension
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0810; // pos=8 len=16
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0x34de );
DBGA ( R7.H , 0 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0814; // pos=8 len=20
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0x34de );
DBGA ( R7.H , 0x0002 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0800; // pos=8 len=0
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0 );
DBGA ( R7.H , 0 );
R0.L = 0xfff1;
R0.H = 0xffff;
R1.L = 0x0001; // pos=0 len=1
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0x1 );
DBGA ( R7.H , 0 );
R0.L = 0xfff1;
R0.H = 0xffff;
R1.L = 0x0101; // pos=1 len=1
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0 );
DBGA ( R7.H , 0 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xfff1;
R0.H = 0xffff;
R1.L = 0x1810; // pos=24 len=16
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0x00ff );
DBGA ( R7.H , 0 );
R0.L = 0xfff1;
R0.H = 0xffff;
R1.L = 0x0020; // pos=0 len=32 is like pos=0 len=0
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0x0 );
DBGA ( R7.H , 0x0 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xfff1;
R0.H = 0xffff;
R1.L = 0x2020; // pos=32 len=32 is like pos=0 len=0
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0 );
DBGA ( R7.H , 0 );
R0.L = 0xfff1;
R0.H = 0xffff;
R1.L = 0x1f01; // pos=31 len=1
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0x1 );
DBGA ( R7.H , 0 );
R0.L = 0xfff1;
R0.H = 0xffff;
R1.L = 0x1000; // pos=16 len=0
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0 );
DBGA ( R7.H , 0 );
// Test FEXT with sign extension
R0.L = 0xdead;
R0.H = 0x12f4;
R1.L = 0x0810; // pos=8 len=16
R7 = EXTRACT( R0, R1.L ) (X);
DBGA ( R7.L , 0xf4de );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0810; // pos=8 len=16
R7 = EXTRACT( R0, R1.L ) (X);
DBGA ( R7.L , 0x34de );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xdead;
R0.H = 0xf234;
R1.L = 0x1f01; // pos=31 len=1
R7 = EXTRACT( R0, R1.L ) (X);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xdead;
R0.H = 0xf234;
R1.L = 0x1f02; // pos=31 len=2
R7 = EXTRACT( R0, R1.L ) (X);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x101f; // pos=16 len=31
R7 = EXTRACT( R0, R1.L ) (X);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x1001; // pos=16 len=1
R7 = EXTRACT( R0, R1.L ) (X);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x1000; // pos=16 len=0
R7 = EXTRACT( R0, R1.L ) (X);
DBGA ( R7.L , 0 );
DBGA ( R7.H , 0 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
pass
|
stsp/binutils-ia16
| 9,721
|
sim/testsuite/bfin/c_ldstii_ld_preg.s
|
//Original:testcases/core/c_ldstii_ld_preg/c_ldstii_ld_preg.dsp
// Spec Reference: c_ldstii load preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x04;
loadsym i1, DATA_ADDR_3, 0x04;
loadsym p4, DATA_ADDR_1, 0x00;
loadsym p5, DATA_ADDR_2, 0x00;
loadsym fp, DATA_ADDR_3, 0x00;
loadsym i3, DATA_ADDR_4, 0x00;
P3 = I1; SP = I3;
P2 = [ P1 + 0 ];
P3 = [ P1 + 4 ];
P4 = [ P1 + 8 ];
P5 = [ P1 + 12 ];
SP = [ P1 + 16 ];
FP = [ P1 + 20 ];
P1 = [ P1 + 24 ];
CHECKREG p1, 0x18191A1B;
CHECKREG p2, 0x00010203;
CHECKREG p3, 0x04050607;
CHECKREG p4, 0x08090A0B;
CHECKREG p5, 0x0C0D0E0F;
CHECKREG sp, 0x10111213;
CHECKREG fp, 0x14151617;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p2, DATA_ADDR_2, 0x04;
P3 = I1; SP = I3;
P1 = [ P2 + 28 ];
P3 = [ P2 + 36 ];
P4 = [ P2 + 40 ];
P5 = [ P2 + 44 ];
SP = [ P2 + 48 ];
FP = [ P2 + 52 ];
P2 = [ P2 + 32 ];
CHECKREG p1, 0x91929394;
CHECKREG p2, 0x95969798;
CHECKREG p3, 0x99A1A2A3;
CHECKREG p4, 0xA5A6A7A8;
CHECKREG p5, 0xA9B0B1B2;
CHECKREG sp, 0xB3B4B5B6;
CHECKREG fp, 0xB7B8B9C0;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i1, DATA_ADDR_3, 0x00;
P3 = I1; SP = I3;
P1 = [ P3 + 56 ];
P2 = [ P3 + 60 ];
P4 = [ P3 + 60 ];
P5 = [ P3 + 56 ];
SP = [ P3 + 52 ];
FP = [ P3 + 48 ];
P3 = [ P3 + 64 ];
CHECKREG p1, 0xE3E4E5E6;
CHECKREG p2, 0x91E899EA;
CHECKREG p3, 0x92E899EA;
CHECKREG p4, 0x91E899EA;
CHECKREG p5, 0xE3E4E5E6;
CHECKREG sp, 0xDFE0E1E2;
CHECKREG fp, 0xDBDCDDDE;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p4, DATA_ADDR_4, 0x00;
P3 = I1; SP = I3;
P1 = [ P4 + 44 ];
P2 = [ P4 + 40 ];
P3 = [ P4 + 36 ];
P5 = [ P4 + 28 ];
SP = [ P4 + 24 ];
FP = [ P4 + 20 ];
P4 = [ P4 + 32 ];
CHECKREG p1, 0xFBFCFDFE;
CHECKREG p2, 0xF7F8F9FA;
CHECKREG p3, 0xF3F4F5F6;
CHECKREG p4, 0xEBECEDEE;
CHECKREG p5, 0x7C7D7E7F;
CHECKREG sp, 0x78797A7B;
CHECKREG fp, 0x74757677;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
P1 = [ P5 + 16 ];
P2 = [ P5 + 12 ];
P3 = [ P5 + 8 ];
P4 = [ P5 + 0 ];
SP = [ P5 + 4 ];
FP = [ P5 + 8 ];
P5 = [ P5 + 4 ];
CHECKREG p1, 0x10111213;
CHECKREG p2, 0x0C0D0E0F;
CHECKREG p3, 0x08090A0B;
CHECKREG p4, 0x00010203;
CHECKREG p5, 0x04050607;
CHECKREG sp, 0x04050607;
CHECKREG fp, 0x08090A0B;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i3, DATA_ADDR_2, 0x00;
P3 = I1; SP = I3;
P1 = [ SP + 12 ];
P2 = [ SP + 16 ];
P3 = [ SP + 20 ];
P4 = [ SP + 24 ];
P5 = [ SP + 28 ];
FP = [ SP + 32 ];
SP = [ SP + 36 ];
CHECKREG p1, 0x2C2D2E2F;
CHECKREG p2, 0x30313233;
CHECKREG p3, 0x34353637;
CHECKREG p4, 0x38393A3B;
CHECKREG p5, 0x3C3D3E3F;
CHECKREG sp, 0x95969798;
CHECKREG fp, 0x91929394;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_3, 0x00;
P3 = I1; SP = I3;
P1 = [ FP + 40 ];
P2 = [ FP + 44 ];
P3 = [ FP + 48 ];
P4 = [ FP + 52 ];
P5 = [ FP + 56 ];
SP = [ FP + 60 ];
FP = [ FP + 64 ];
CHECKREG p1, 0xD3D4D5D6;
CHECKREG p2, 0xD7D8D9DA;
CHECKREG p3, 0xDBDCDDDE;
CHECKREG p4, 0xDFE0E1E2;
CHECKREG p5, 0xE3E4E5E6;
CHECKREG sp, 0x91E899EA;
CHECKREG fp, 0x92E899EA;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 5,857
|
sim/testsuite/bfin/c_dsp32alu_rl_rnd20_p.s
|
//Original:/testcases/core/c_dsp32alu_rl_rnd20_p/c_dsp32alu_rl_rnd20_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x75678911;
imm32 r1, 0xa789ab1d;
imm32 r2, 0x34745515;
imm32 r3, 0x4b677717;
imm32 r4, 0x5678791b;
imm32 r5, 0xc789a71d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.L = R0 + R0 (RND20);
R1.L = R0 + R1 (RND20);
R2.L = R0 + R2 (RND20);
R3.L = R0 + R3 (RND20);
R4.L = R0 + R4 (RND20);
R5.L = R0 + R5 (RND20);
R6.L = R0 + R6 (RND20);
R7.L = R0 + R7 (RND20);
CHECKREG r0, 0x75670EAD;
CHECKREG r1, 0xA78901CF;
CHECKREG r2, 0x34740A9E;
CHECKREG r3, 0x4B670C0D;
CHECKREG r4, 0x56780CBE;
CHECKREG r5, 0xC78903CF;
CHECKREG r6, 0x74440E9B;
CHECKREG r7, 0x8666FFBD;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3e445515;
imm32 r3, 0x46667717;
imm32 r4, 0x56e8891b;
imm32 r5, 0x678eab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86e67e77;
R0.L = R1 + R0 (RND20);
R1.L = R1 + R1 (RND20);
R2.L = R1 + R2 (RND20);
R3.L = R1 + R3 (RND20);
R4.L = R1 + R4 (RND20);
R5.L = R1 + R5 (RND20);
R6.L = R1 + R6 (RND20);
R7.L = R1 + R7 (RND20);
CHECKREG r0, 0xE56700CF;
CHECKREG r1, 0x278904F1;
CHECKREG r2, 0x3E44065D;
CHECKREG r3, 0x466606DF;
CHECKREG r4, 0x56E807E7;
CHECKREG r5, 0x678E08F1;
CHECKREG r6, 0x744409BD;
CHECKREG r7, 0x86E6FAE7;
imm32 r0, 0xdd678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46667717;
imm32 r4, 0x56d8891b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x86667d77;
R0.L = R2 + R0 (RND20);
R1.L = R2 + R1 (RND20);
R2.L = R2 + R2 (RND20);
R3.L = R2 + R3 (RND20);
R4.L = R2 + R4 (RND20);
R5.L = R2 + R5 (RND20);
R6.L = R2 + R6 (RND20);
R7.L = R2 + R7 (RND20);
CHECKREG r0, 0xDD6701AB;
CHECKREG r1, 0x2789064D;
CHECKREG r2, 0x3D4407A9;
CHECKREG r3, 0x4666083B;
CHECKREG r4, 0x56D80942;
CHECKREG r5, 0x678D0A4D;
CHECKREG r6, 0x74440B19;
CHECKREG r7, 0x8666FC3B;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x567a891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444c515;
imm32 r7, 0x86667c77;
R0.L = R3 + R0 (RND20);
R1.L = R3 + R1 (RND20);
R2.L = R3 + R2 (RND20);
R3.L = R3 + R3 (RND20);
R4.L = R3 + R4 (RND20);
R5.L = R3 + R5 (RND20);
R6.L = R3 + R6 (RND20);
R7.L = R3 + R7 (RND20);
CHECKREG r0, 0xA567FEC1;
CHECKREG r1, 0x2A890713;
CHECKREG r2, 0x344407AF;
CHECKREG r3, 0x46A608D5;
CHECKREG r4, 0x567A09D2;
CHECKREG r5, 0x67890AE3;
CHECKREG r6, 0x74440BAF;
CHECKREG r7, 0x8666FCD1;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.L = R4 + R0 (RND20);
R1.L = R4 + R1 (RND20);
R2.L = R4 + R2 (RND20);
R3.L = R4 + R3 (RND20);
R4.L = R4 + R4 (RND20);
R5.L = R4 + R5 (RND20);
R6.L = R4 + R6 (RND20);
R7.L = R4 + R7 (RND20);
CHECKREG r0, 0x156706BE;
CHECKREG r1, 0x278907E0;
CHECKREG r2, 0x344408AC;
CHECKREG r3, 0x466609CE;
CHECKREG r4, 0x56780ACF;
CHECKREG r5, 0x67890BE0;
CHECKREG r6, 0x74440CAC;
CHECKREG r7, 0x8666FDCE;
imm32 r0, 0x95678911;
imm32 r1, 0x8789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x4a667717;
imm32 r4, 0x56b8891b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x7444e515;
imm32 r7, 0x86667d77;
R0.L = R5 + R0 (RND20);
R1.L = R5 + R1 (RND20);
R2.L = R5 + R2 (RND20);
R3.L = R5 + R3 (RND20);
R4.L = R5 + R4 (RND20);
R5.L = R5 + R5 (RND20);
R6.L = R5 + R6 (RND20);
R7.L = R5 + R7 (RND20);
CHECKREG r0, 0x9567FFCF;
CHECKREG r1, 0x8789FEF1;
CHECKREG r2, 0x74440DBD;
CHECKREG r3, 0x4A660B1F;
CHECKREG r4, 0x56B80BE4;
CHECKREG r5, 0x678D0CF2;
CHECKREG r6, 0x74440DBD;
CHECKREG r7, 0x8666FEDF;
imm32 r0, 0x35678911;
imm32 r1, 0x2459ab1d;
imm32 r2, 0x34465515;
imm32 r3, 0xe6667717;
imm32 r4, 0x5d78891b;
imm32 r5, 0x67b9ab1d;
imm32 r6, 0x744a5515;
imm32 r7, 0x8666c777;
R0.L = R6 + R0 (RND20);
R1.L = R6 + R1 (RND20);
R2.L = R6 + R2 (RND20);
R3.L = R6 + R3 (RND20);
R4.L = R6 + R4 (RND20);
R5.L = R6 + R5 (RND20);
R6.L = R6 + R6 (RND20);
R7.L = R6 + R7 (RND20);
CHECKREG r0, 0x35670A9B;
CHECKREG r1, 0x2459098A;
CHECKREG r2, 0x34460A89;
CHECKREG r3, 0xE66605AB;
CHECKREG r4, 0x5D780D1C;
CHECKREG r5, 0x67B90DC0;
CHECKREG r6, 0x744A0E89;
CHECKREG r7, 0x8666FFAB;
imm32 r0, 0xa5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3a445515;
imm32 r3, 0x4c667717;
imm32 r4, 0x56b8891b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x8666d777;
R0.L = R7 + R0 (RND20);
R1.L = R7 + R1 (RND20);
R2.L = R7 + R2 (RND20);
R3.L = R7 + R3 (RND20);
R4.L = R7 + R4 (RND20);
R5.L = R7 + R5 (RND20);
R6.L = R7 + R6 (RND20);
R7.L = R7 + R7 (RND20);
CHECKREG r0, 0xA567F2BD;
CHECKREG r1, 0x2789FADF;
CHECKREG r2, 0x3A44FC0B;
CHECKREG r3, 0x4C66FD2D;
CHECKREG r4, 0x56B8FDD2;
CHECKREG r5, 0x678DFEDF;
CHECKREG r6, 0x7444FFAB;
CHECKREG r7, 0x8666F0CD;
imm32 r0, 0xabd78911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0x4e667717;
imm32 r4, 0x56f8891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0x86667d77;
R6.L = R2 + R3 (RND20);
R1.L = R4 + R5 (RND20);
R5.L = R7 + R2 (RND20);
R3.L = R0 + R0 (RND20);
R0.L = R3 + R4 (RND20);
R2.L = R5 + R7 (RND20);
R7.L = R6 + R7 (RND20);
R4.L = R1 + R6 (RND20);
CHECKREG r0, 0xABD70A56;
CHECKREG r1, 0x27890BE8;
CHECKREG r2, 0xD444FEDF;
CHECKREG r3, 0x4E66F57B;
CHECKREG r4, 0x56F809BD;
CHECKREG r5, 0x678AF5AB;
CHECKREG r6, 0x7444022B;
CHECKREG r7, 0x8666FFAB;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R3.L = R4 + R0 (RND20);
R1.L = R6 + R3 (RND20);
R4.L = R3 + R2 (RND20);
R6.L = R7 + R1 (RND20);
R2.L = R5 + R4 (RND20);
R7.L = R2 + R7 (RND20);
R0.L = R1 + R6 (RND20);
R5.L = R0 + R5 (RND20);
CHECKREG r0, 0x156709BD;
CHECKREG r1, 0x27890BAB;
CHECKREG r2, 0x34440BE0;
CHECKREG r3, 0x466606BE;
CHECKREG r4, 0x567807AB;
CHECKREG r5, 0x678907CF;
CHECKREG r6, 0x7444FADF;
CHECKREG r7, 0x8666FBAB;
pass
|
stsp/binutils-ia16
| 5,756
|
sim/testsuite/bfin/dbg_tr_basic.S
|
//Original:/proj/frio/dv/testcases/debug/dbg_tr_basic/dbg_tr_basic.dsp
// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
// Supervisor mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfcheck.inc)
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
// This test embeds .text offsets, so pad our test so it lines up.
.space 0x70
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
CHECK_INIT(p5, 0x00BFFFFC);
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
LD32_LABEL(r7, DUMMY);
RETI = r7;
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
START :
WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn ON trace Buffer
// TBUFPWR = 0
// TBUFEN = 0
// TBUFOVF = 0
// CMPLP = 0
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label1; //
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label2: R5.H = 0x7777; //
R5.L = 0x7888;
JUMP.S label3; //
R6.L = 0x1111; // Will be killed
R6.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
label1: R4.H = 0x5555; //
R4.L = 0x6666;
NOP;
WR_MMR(TBUFCTL, 0x00000002, p0, r0); //
// TBUFPWR = 0
// TBUFEN = 1
// TBUFOVF = 0
// CMPLP = 0
NOP;
NOP;
NOP;
NOP;
JUMP.S label2; //
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
label3: R6.H = 0x7999; //
R6.L = 0x7aaa;
NOP;
NOP;
WR_MMR(TBUFCTL, 0x00000001, p0, r0);
NOP;
NOP;
NOP;
WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer
// TBUFPWR = 1
// TBUFEN = 1
// TBUFOVF = 0
// CMPLP = 0
NOP;
NOP;
NOP;
NOP;
JUMP.S label4; //
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
label4: R6.H = 0x1aaa; //
R6.L = 0x2222;
NOP;
NOP;
NOP;
NOP;
WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer
NOP;
NOP;
NOP;
NOP;
// Read the contents of the Trace Buffer
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000001);
// Read 3rd Entry of the Trace Buffer
RD_MMR(TBUF, p0, r0);
CHECKREG(r0, 0x000002d2);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000001);
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x000002c0);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000000);
WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
|
stsp/binutils-ia16
| 4,621
|
sim/testsuite/bfin/c_dsp32mult_pair_s.s
|
//Original:/testcases/core/c_dsp32mult_pair_s/c_dsp32mult_pair_s.dsp
// Spec Reference: dsp32mult pair s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R1 = R0.L * R0.L, R0 = R0.L * R0.L (S2RND);
R3 = R0.L * R1.L, R2 = R0.L * R1.H (S2RND);
R5 = R1.L * R0.L, R4 = R1.H * R0.L (S2RND);
R7 = R1.L * R1.L, R6 = R1.H * R1.H (S2RND);
CHECKREG r0, 0x73F38564;
CHECKREG r1, 0x73F38564;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x7FFFFFFF;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x7FFFFFFF;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0x7FFFFFFF;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R1 = R2.L * R2.L, R0 = R2.L * R2.L (S2RND);
R3 = R2.L * R3.L, R2 = R2.L * R3.H (S2RND);
R5 = R3.L * R2.L, R4 = R3.H * R2.L (S2RND);
R7 = R3.L * R3.L, R6 = R3.H * R3.H (S2RND);
CHECKREG r0, 0x52CB43E4;
CHECKREG r1, 0x52CB43E4;
CHECKREG r2, 0x7F5C6CF8;
CHECKREG r3, 0x3659B18C;
CHECKREG r4, 0x5C88C8E0;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x2E26ABC4;
CHECKREG r7, 0x602B9240;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R1 = R4.L * R4.L, R0 = R4.L * R4.L (S2RND);
R3 = R4.L * R5.L, R2 = R4.L * R5.H (S2RND);
R5 = R5.L * R4.L, R4 = R5.H * R4.L (S2RND);
R7 = R5.L * R5.L, R6 = R5.H * R5.H (S2RND);
CHECKREG r0, 0x36536944;
CHECKREG r1, 0x36536944;
CHECKREG r2, 0xF0A3C830;
CHECKREG r3, 0x0F55C4CC;
CHECKREG r4, 0xF0A3C830;
CHECKREG r5, 0x0F55C4CC;
CHECKREG r6, 0x03AC48E4;
CHECKREG r7, 0x36C40A40;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
R1 = R6.L * R6.L, R0 = R6.L * R6.L (S2RND);
R3 = R6.L * R7.L, R2 = R6.L * R7.H (S2RND);
R5 = R7.L * R6.L, R4 = R7.H * R6.L (S2RND);
R7 = R7.L * R7.L, R6 = R7.H * R7.H (S2RND);
CHECKREG r0, 0x5494A9A4;
CHECKREG r1, 0x5494A9A4;
CHECKREG r2, 0xEAFE2F38;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xEAFE2F38;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x0537AC90;
CHECKREG r7, 0x7FFFFFFF;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (S2RND);
R3 = R1.L * R0.H, R2 = R1.H * R0.L (S2RND);
R5 = R7.H * R4.L, R4 = R7.H * R4.L (S2RND);
R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (S2RND);
CHECKREG r0, 0x000217F0;
CHECKREG r1, 0x0005A246;
CHECKREG r2, 0x0001DEC0;
CHECKREG r3, 0xFFFD1230;
CHECKREG r4, 0xF172C9D8;
CHECKREG r5, 0xF172C9D8;
CHECKREG r6, 0xFFFD0B28;
CHECKREG r7, 0xFFFA7FF0;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R3 = R6.L * R5.L, R2 = R6.L * R5.H (S2RND);
R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (S2RND);
R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (S2RND);
R7 = R2.H * R7.L, R6 = R2.H * R7.L (S2RND);
CHECKREG r0, 0xF9577348;
CHECKREG r1, 0x31F9EE68;
CHECKREG r2, 0x038BD5F0;
CHECKREG r3, 0xFB4A293C;
CHECKREG r4, 0xB2B9DB04;
CHECKREG r5, 0xEA6A5350;
CHECKREG r6, 0x0633BF8C;
CHECKREG r7, 0x0633BF8C;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R3 = R6.H * R5.L, R2 = R6.L * R5.H (S2RND);
R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (S2RND);
R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (S2RND);
R1 = R2.H * R7.L, R0 = R2.L * R7.H (S2RND);
CHECKREG r0, 0x510340C0;
CHECKREG r1, 0xFFDAAA00;
CHECKREG r2, 0x0024BAF0;
CHECKREG r3, 0xFFFBA910;
CHECKREG r4, 0x4B155680;
CHECKREG r5, 0x6B2FA2E0;
CHECKREG r6, 0x0030A1D0;
CHECKREG r7, 0xB4EDBDA0;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R1.H * R4.L, R0 = R1.H * R4.L (S2RND);
R3 = R2.L * R5.L, R2 = R2.L * R5.H (S2RND);
R5 = R3.H * R6.L, R4 = R3.L * R6.L (S2RND);
R7 = R4.L * R0.H, R6 = R4.H * R0.L (S2RND);
CHECKREG r0, 0x0E99DA28;
CHECKREG r1, 0x0E99DA28;
CHECKREG r2, 0x1AD61D70;
CHECKREG r3, 0xE4671D1C;
CHECKREG r4, 0x006BCBB0;
CHECKREG r5, 0xFF99CD6C;
CHECKREG r6, 0xFFC0BAE0;
CHECKREG r7, 0xF41170C0;
pass
|
stsp/binutils-ia16
| 2,922
|
sim/testsuite/bfin/c_dsp32mac_dr_a0_m.s
|
//Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp
// Spec Reference: dsp32mac dr_a0 m
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246700f;
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
A1 -= R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L );
R3 = A0.w;
A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H );
R5 = A0.w;
A1 = R6.H * R7.H, R6.L = ( A0 = R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0x1354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xA124FF27;
CHECKREG r3, 0xFF274DDE;
CHECKREG r4, 0xEFBCFCD7;
CHECKREG r5, 0xFCD701B6;
CHECKREG r6, 0x000C000B;
CHECKREG r7, 0x000A846C;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R0.L = ( A0 += R6.L * R7.L );
R1 = A0.w;
R2.L = ( A0 -= R2.L * R3.H );
R3 = A0.w;
R4.L = ( A0 += R4.H * R5.L );
R5 = A0.w;
R6.L = ( A0 = R0.H * R1.H );
R7 = A0.w;
CHECKREG r0, 0x1354000B;
CHECKREG r1, 0x000A85F2;
CHECKREG r2, 0xA1240006;
CHECKREG r3, 0x00067846;
CHECKREG r4, 0xEFBC0005;
CHECKREG r5, 0x0005126E;
CHECKREG r6, 0x000C0002;
CHECKREG r7, 0x00018290;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
R2.L = ( A0 += R2.H * R3.L );
R3 = A0.w;
R4.L = ( A0 += R4.H * R5.H );
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0x1354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xA124FF1D;
CHECKREG r3, 0xFF1CEDCE;
CHECKREG r4, 0xEFBCFCCD;
CHECKREG r5, 0xFCCCA1A6;
CHECKREG r6, 0x000CFCD7;
CHECKREG r7, 0xFCD72612;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
A1 = R1.L * R0.L (M), R6.L = ( A0 -= R1.L * R0.L );
R7 = A0.w;
A1 -= R2.L * R3.H (M), R2.L = ( A0 += R2.H * R3.L );
R3 = A0.w;
A1 = R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H );
R5 = A0.w;
A1 -= R6.H * R7.H (M), R0.L = ( A0 = R6.L * R7.H );
R1 = A0.w;
CHECKREG r0, 0x1354000B;
CHECKREG r1, 0x000A83F2;
CHECKREG r2, 0xA124FDB0;
CHECKREG r3, 0xFDAFD834;
CHECKREG r4, 0xEFBCFDB0;
CHECKREG r5, 0xFDAFB3D8;
CHECKREG r6, 0x000CFDB5;
CHECKREG r7, 0xFDB5083C;
pass
|
stsp/binutils-ia16
| 1,885
|
sim/testsuite/bfin/c_cactrl_iflush_pr_pp.s
|
//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr_pp/c_cactrl_iflush_pr_pp.dsp
// Spec Reference: c_cactrl iflush_pr [p++]
# mach: bfin
.include "testutils.inc"
start
loadsym p2, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
// The result accumulated in A0 and A1, and stored to a reg half
R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R3.H = A1 , A0 = R7.H * R6.L (T);
// begin of iflush
IFLUSH [ P2 ++ ]; // p2 = 0x448
R7 = 0;
ASTAT = R7;
IF !CC JUMP SUBR1;
JBACK:
R6 = 0;
//r4 = (a1 = l*h) M, a0 = h*l (r3,r2);
//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS;
CHECKREG r2, 0xFFD15679;
CHECKREG r3, 0xFFD00007;
CHECKREG r4, 0x00074569;
CHECKREG r5, 0x12358000;
//CHECKREG p2, 0x00000468;
pass
//.code 0x448
//.code CODE_ADDR_1
SUBR1:
R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L;
A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2);
IF !CC JUMP JBACK;
NOP; NOP; NOP; NOP; NOP;
// Pre-load memory witb known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
|
stsp/binutils-ia16
| 4,017
|
sim/testsuite/bfin/c_cc2stat_cc_an.s
|
//Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp
// Spec Reference: cc2stat cc an
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AN 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
CC = AN; //
R0 = CC; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
CC = AN; //
R1 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
CC = AN; //
R2 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
CC = AN; //
R3 = CC; //
// test cc |= AN (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
CC |= AN; //
R4 = CC; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
CC |= AN; //
R5 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 0
CC |= AN; //
R6 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
CC |= AN; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
// test CC &= AN (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
CC &= AN; //
R4 = CC; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
CC &= AN; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
CC &= AN; //
R6 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
CC &= AN; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
// test CC ^= AN (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
CC ^= AN; //
R4 = CC; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
CC ^= AN; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
CC ^= AN; //
R6 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
CC ^= AN; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
// test AN = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
AN = CC; //
R0 = ASTAT; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
AN = CC; //
R1 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
AN = CC; //
R2 = ASTAT; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
AN = CC; //
R3 = ASTAT; //
// test AN |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
AN |= CC; //
R4 = ASTAT; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
AN |= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
AN |= CC; //
R6 = ASTAT; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
AN |= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
// test AN &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
AN &= CC; //
R4 = ASTAT; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
AN &= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
AN &= CC; //
R6 = ASTAT; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
AN &= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000022;
// test AN ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
AN ^= CC; //
R4 = ASTAT; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
AN ^= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
AN ^= CC; //
R6 = ASTAT; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
AN ^= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000020;
pass
|
stsp/binutils-ia16
| 6,388
|
sim/testsuite/bfin/random_0031.S
|
# Check that VS in ASTAT is set with add/sub insns (and not just V)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2810c010 | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x27f3a149;
imm32 R3, 0x3cae7c58;
imm32 R4, 0x33c97634;
R3.H = R0.L - R4.H (NS);
checkreg R3, 0x6d807c58;
checkreg ASTAT, (0x2810c010 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x64c00680 | _AQ | _AC0_COPY);
imm32 R1, 0x1b7b025c;
imm32 R5, 0x1ba46ce6;
R5.L = R5.L + R1.H (NS);
checkreg R5, 0x1ba48861;
checkreg ASTAT, (0x64c00680 | _VS | _V | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x68b04200 | _AV1S | _AV0 | _AC0 | _AQ | _AN);
imm32 R3, 0x4b91870f;
imm32 R6, 0x5972bae0;
imm32 R7, 0x31f7dfb7;
R7.H = R6.L + R3.L (S);
checkreg R7, 0x8000dfb7;
checkreg ASTAT, (0x68b04200 | _VS | _V | _AV1S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x78208e90 | _CC | _AN);
imm32 R3, 0x40b63bc7;
imm32 R5, 0x49c89df9;
R3.H = R5.L - R3.H (NS);
checkreg R3, 0x5d433bc7;
checkreg ASTAT, (0x78208e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x00904680 | _AV1S | _AV1 | _AV0 | _AC1 | _AQ | _AZ);
imm32 R2, 0x23a2c115;
imm32 R4, 0x6977581e;
imm32 R6, 0x41900942;
R4.L = R2.L - R6.H (NS);
checkreg R4, 0x69777f85;
checkreg ASTAT, (0x00904680 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x78d08210 | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ);
imm32 R0, 0x4317139e;
imm32 R1, 0x49ed40d6;
R0.L = R1.L + R0.H (NS);
checkreg R0, 0x431783ed;
checkreg ASTAT, (0x78d08210 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AN);
dmm32 ASTAT, (0x58d00e10 | _AV1 | _AQ | _CC);
imm32 R0, 0x09ea77a2;
imm32 R1, 0x6ccd0b05;
imm32 R2, 0x761c63af;
R1.H = R0.L + R2.H (NS);
checkreg R1, 0xedbe0b05;
checkreg ASTAT, (0x58d00e10 | _VS | _V | _AV1 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x30c08000 | _AC0 | _AQ | _AC0_COPY);
imm32 R4, 0x36d243cb;
imm32 R5, 0xcd127add;
R4.H = R5.L + R4.L (NS);
checkreg R4, 0xbea843cb;
checkreg ASTAT, (0x30c08000 | _VS | _V | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x74108400 | _V | _AV1 | _AC1 | _AC0 | _AC0_COPY);
imm32 R0, 0x4e1893ea;
imm32 R1, 0x13cf5cc8;
imm32 R3, 0x7441949e;
R1.L = R0.L - R3.H (NS);
checkreg R1, 0x13cf1fa9;
checkreg ASTAT, (0x74108400 | _VS | _V | _AV1 | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x7420ce10 | _AV1S | _AV1 | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
imm32 R4, 0x532c8fb1;
imm32 R6, 0x582420d2;
R6.H = R4.L - R4.H (NS);
checkreg R6, 0x3c8520d2;
checkreg ASTAT, (0x7420ce10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x74704010 | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY);
imm32 R3, 0x6f6a7429;
imm32 R5, 0x2ea5c47e;
R5.H = R5.L - R3.H (NS);
checkreg R5, 0x5514c47e;
checkreg ASTAT, (0x74704010 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x0ce08490 | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AZ);
imm32 R1, 0xfd18a0b0;
imm32 R4, 0x259e2151;
R4.L = R1.L - R4.H (NS);
checkreg R4, 0x259e7b12;
checkreg ASTAT, (0x0ce08490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x54b08810 | _V | _AV1S | _AV0S | _AC0_COPY | _AN);
imm32 R3, 0x7a763675;
imm32 R6, 0x23c4a335;
R3.L = R6.L + R6.L (NS);
checkreg R3, 0x7a76466a;
checkreg ASTAT, (0x54b08810 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x70f0c080 | _AV1S | _AV0S | _AC0);
imm32 R4, 0x55fab7e4;
imm32 R5, 0x7dbd9b06;
R5.H = R5.L - R4.H (S);
checkreg R5, 0x80009b06;
checkreg ASTAT, (0x70f0c080 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x5ce04680 | _AV0 | _AC0 | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x19cacbdb;
imm32 R2, 0x151cb293;
imm32 R4, 0x571c351a;
R0.H = R4.L - R2.L (S);
checkreg R0, 0x7fffcbdb;
checkreg ASTAT, (0x5ce04680 | _VS | _V | _AV0 | _V_COPY);
dmm32 ASTAT, (0x0c604a00 | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AZ);
imm32 R3, 0x5432c45d;
imm32 R6, 0x62519952;
R3.L = R6.L + R6.L (S);
checkreg R3, 0x54328000;
checkreg ASTAT, (0x0c604a00 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x58708c90 | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN | _AZ);
imm32 R0, 0x1f3f3c0e;
imm32 R4, 0x5fae58d2;
R0.H = R0.L + R4.L (NS);
checkreg R0, 0x94e03c0e;
checkreg ASTAT, (0x58708c90 | _VS | _V | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x34b00a00 | _V | _AV1S | _AC1 | _CC | _V_COPY | _AZ);
imm32 R3, 0x6ea226dc;
imm32 R4, 0x045c6d64;
imm32 R7, 0x7e599a25;
R7.L = R3.L + R4.L (NS);
checkreg R7, 0x7e599440;
checkreg ASTAT, (0x34b00a00 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x40a0c010 | _AV1S | _AC0);
imm32 R2, 0x641501ef;
imm32 R7, 0x3acb49aa;
R2.H = R7.L + R7.H (NS);
checkreg R2, 0x847501ef;
checkreg ASTAT, (0x40a0c010 | _VS | _V | _AV1S | _V_COPY | _AN);
dmm32 ASTAT, (0x78f04090 | _AV1S | _AC1 | _AQ | _CC | _AZ);
imm32 R2, 0x65681fdf;
imm32 R3, 0x5fffe0d3;
imm32 R5, 0x37df99cd;
R2.H = R5.L - R3.H (NS);
checkreg R2, 0x39ce1fdf;
checkreg ASTAT, (0x78f04090 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x0cc04e10 | _AV1S | _AQ | _CC);
imm32 R3, 0x571977df;
imm32 R4, 0x029671d0;
R3.L = R4.L + R3.H (NS);
checkreg R3, 0x5719c8e9;
checkreg ASTAT, (0x0cc04e10 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x00104880 | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
imm32 R0, 0x4c98aa07;
imm32 R4, 0x5e9da59f;
R4.H = R0.L + R0.L (S);
checkreg R4, 0x8000a59f;
checkreg ASTAT, (0x00104880 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x08008c00 | _AV1S | _AV0S | _AV0 | _CC | _AC0_COPY);
imm32 R4, 0x58ee2400;
imm32 R6, 0x2e97af3e;
R4.L = R6.L + R6.L (NS);
checkreg R4, 0x58ee5e7c;
checkreg ASTAT, (0x08008c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x2ce0c290 | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R2, 0x2d467e64;
imm32 R6, 0x31aeb601;
imm32 R7, 0x1523a746;
R7.L = R2.L - R6.L (S);
checkreg R7, 0x15237fff;
checkreg ASTAT, (0x2ce0c290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
pass
|
stsp/binutils-ia16
| 14,115
|
sim/testsuite/bfin/random_0020.S
|
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0xfcdbede4;
dmm32 A1.x, 0xffffffff;
imm32 R5, 0x14c5c1c7;
imm32 R7, 0x006a5040;
R5 = (A1 += R7.L * R7.H) (M, IU);
checkreg R5, 0xfcfd2864;
checkreg A1.w, 0xfcfd2864;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x6c508a90 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x0bcd165c;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x439a7ef1;
imm32 R3, 0x47670015;
imm32 R6, 0x00008000;
R3 = (A1 += R6.L * R0.L) (M, IU);
checkreg R3, 0xcc54965c;
checkreg A1.w, 0xcc54965c;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x6c508a90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
dmm32 ASTAT, (0x38900480 | _VS | _AV0S | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x8000ffff;
imm32 R3, 0x0000ffff;
imm32 R6, 0xcb2cf810;
R3 = (A1 += R6.L * R1.L) (M, IU);
checkreg R3, 0xf81007f0;
checkreg A1.w, 0xf81007f0;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x38900480 | _VS | _AV0S | _AN);
dmm32 ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN);
dmm32 A1.w, 0x36491cf0;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x10771108;
imm32 R2, 0x7fb14fe2;
imm32 R7, 0x3649ffff;
R1 = (A1 = R7.L * R2.H) (M, IU);
checkreg R1, 0xffff804f;
checkreg A1.w, 0xffff804f;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN);
dmm32 ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ);
dmm32 A1.w, 0xd831c3b7;
dmm32 A1.x, 0xffffffff;
imm32 R3, 0x3a98144b;
imm32 R7, 0xd831c3b7;
R7 = (A1 -= R3.L * R3.H) (M, IU);
checkreg R7, 0xd38cb92f;
checkreg A1.w, 0xd38cb92f;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ);
dmm32 ASTAT, (0x3c50c810 | _VS | _AV1S | _AN | _AZ);
dmm32 A0.w, 0x13cd1c6c;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x4000e935;
imm32 R3, 0xe0b313cd;
R3.L = (A0 += R3.H * R2.L) (IU);
checkreg R3, 0xe0b3ffff;
checkreg A0.w, 0xe07e8c7b;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x3c50c810 | _VS | _V | _AV1S | _V_COPY | _AN | _AZ);
dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A0.w, 0x057e5874;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x1c0af520;
imm32 R6, 0x7caea317;
imm32 R7, 0x107e8ce4;
R6.L = (A0 += R7.L * R0.L) (IU);
checkreg R6, 0x7caeffff;
checkreg A0.w, 0x8c6628f4;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
dmm32 ASTAT, (0x6cf04090 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
dmm32 A0.w, 0xdc7d7b8c;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x788e00d2;
imm32 R6, 0x03666070;
R0.L = (A0 -= R6.H * R6.H) (IU);
checkreg R0, 0x788effff;
checkreg A0.w, 0xdc71eee8;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x6cf04090 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AZ);
dmm32 ASTAT, (0x4cc04c80 | _VS | _CC);
dmm32 A1.w, 0x41620ea7;
dmm32 A1.x, 0x00000057;
imm32 R1, 0xf611262c;
imm32 R3, 0x7fff7fff;
imm32 R4, 0x247ee19c;
R1 = (A1 += R4.L * R3.L) (IU);
checkreg R1, 0xffffffff;
checkreg A1.w, 0xb22f2d0b;
checkreg A1.x, 0x00000057;
checkreg ASTAT, (0x4cc04c80 | _VS | _V | _CC | _V_COPY);
dmm32 ASTAT, (0x28e04610 | _VS | _AV0S | _AC1 | _AC0 | _AN);
dmm32 A0.w, 0xe1753d16;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x7fffffff;
imm32 R5, 0x2792ffff;
imm32 R7, 0xffffd6fa;
R7.L = (A0 = R0.L * R5.L) (IU);
checkreg R7, 0xffffffff;
checkreg A0.w, 0xfffe0001;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x28e04610 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A0.w, 0x057e5874;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x1c0af520;
imm32 R6, 0x7caea317;
imm32 R7, 0x107e8ce4;
R6.L = (A0 += R7.L * R0.L) (IU);
checkreg R6, 0x7caeffff;
checkreg A0.w, 0x8c6628f4;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
dmm32 ASTAT, (0x00304000 | _VS | _AV1S | _AQ | _AZ);
dmm32 A0.w, 0x615bac86;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x6d2cbec6;
imm32 R3, 0xe09db667;
R3.L = (A0 += R3.H * R2.H) (IU);
checkreg R3, 0xe09dffff;
checkreg A0.w, 0xc1252082;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x00304000 | _VS | _V | _AV1S | _AQ | _V_COPY | _AZ);
dmm32 ASTAT, (0x5cc00080 | _VS | _AV1S | _AC0 | _CC);
dmm32 A1.w, 0x70d9985a;
dmm32 A1.x, 0xffffffd6;
imm32 R1, 0x8000fdeb;
imm32 R2, 0x20e07e89;
R1.H = (A1 += R2.L * R1.L) (M, IU);
checkreg A1.w, 0xee5b251d;
checkreg A1.x, 0xffffffd6;
checkreg ASTAT, (0x5cc00080 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY);
dmm32 ASTAT, (0x60e0ce80 | _VS | _AC0 | _AQ | _CC);
dmm32 A1.w, 0x67798cf6;
dmm32 A1.x, 0x00000044;
imm32 R0, 0x00000000;
imm32 R1, 0x00008e16;
imm32 R7, 0x00000000;
R7 = (A1 -= R0.L * R1.L) (M, IU);
checkreg R7, 0x7fffffff;
checkreg A1.w, 0x67798cf6;
checkreg A1.x, 0x00000044;
checkreg ASTAT, (0x60e0ce80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x6f47fe74;
dmm32 A1.x, 0x00000022;
imm32 R5, 0x3482aa64;
imm32 R6, 0x48320cd9;
R5.H = (A1 -= R6.L * R5.L) (M, IU);
checkreg R5, 0x7fffaa64;
checkreg A1.w, 0x66badfb0;
checkreg A1.x, 0x00000022;
checkreg ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x43fdb94f;
dmm32 A1.x, 0xffffff97;
imm32 R1, 0x80000000;
imm32 R7, 0x0f9b234b;
R1.H = (A1 += R7.L * R1.H) (M, IU);
checkreg A1.w, 0x55a3394f;
checkreg A1.x, 0xffffff97;
checkreg ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x60f0c280 | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x33205f9e;
dmm32 A1.x, 0xfffffffc;
imm32 R3, 0x39e0545d;
imm32 R6, 0x0e133731;
R3 = (A1 -= R3.L * R6.H) (M, IU);
checkreg R3, 0x80000000;
checkreg A1.w, 0x2e7d06b7;
checkreg A1.x, 0xfffffffc;
checkreg ASTAT, (0x60f0c280 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x6c300490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x2a477a36;
dmm32 A1.x, 0xfffffff8;
imm32 R0, 0xff020000;
imm32 R5, 0x00000000;
imm32 R7, 0xffff8000;
R5.H = (A1 -= R0.L * R7.H) (M, IU);
checkreg R5, 0x80000000;
checkreg ASTAT, (0x6c300490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x1400c210 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN);
dmm32 A1.w, 0x68033dca;
dmm32 A1.x, 0xffffffff;
imm32 R1, 0x00000000;
imm32 R3, 0x00a36a42;
imm32 R7, 0x3afd7fff;
R3.H = (A1 -= R1.L * R7.H) (M, IU);
checkreg R3, 0x80006a42;
checkreg ASTAT, (0x1400c210 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x00104810 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0xeb4e9a1d;
dmm32 A1.x, 0xffffff8c;
imm32 R1, 0xffffec05;
imm32 R5, 0x80000000;
imm32 R6, 0x5ffa604a;
R1.H = (A1 += R6.L * R5.H) (M, IU);
checkreg R1, 0x8000ec05;
checkreg A1.w, 0x1b739a1d;
checkreg A1.x, 0xffffff8d;
checkreg ASTAT, (0x00104810 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x48600280 | _VS | _AV1S | _AV0 | _AC1 | _CC | _AC0_COPY);
dmm32 A1.w, 0x54463e5f;
dmm32 A1.x, 0xffffff94;
imm32 R1, 0x2e0d6820;
imm32 R4, 0x37855c3d;
imm32 R6, 0x7b3ca7a0;
R6.H = (A1 += R4.L * R1.L) (M, IU);
checkreg R6, 0x8000a7a0;
checkreg A1.w, 0x79ca8dff;
checkreg A1.x, 0xffffff94;
checkreg ASTAT, (0x48600280 | _VS | _V | _AV1S | _AV0 | _AC1 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x3c008480 | _VS | _AV1S | _AC1 | _AC0 | _CC);
dmm32 A0.w, 0xcdff712a;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x2f3dfc31;
imm32 R2, 0x1b1a4b4c;
imm32 R6, 0x7cbed409;
R2 = (A0 += R6.H * R0.L) (IU);
checkreg R2, 0xffffffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x3c008480 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY);
dmm32 ASTAT, (0x4ce0ce80 | _VS | _AC1 | _AC0 | _CC);
dmm32 A0.w, 0xfefe27a4;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x08270055;
imm32 R1, 0x0000ffc2;
imm32 R6, 0x5ca7213b;
R6.L = (A0 += R1.L * R0.H) (IU);
checkreg R6, 0x5ca7ffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x4ce0ce80 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY);
dmm32 ASTAT, (0x7020ca10 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY);
dmm32 A0.w, 0xec60b144;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x147e9190;
imm32 R1, 0x2b813e9e;
imm32 R4, 0xab65ffff;
R0 = (A0 += R1.L * R4.H) (IU);
checkreg R0, 0xffffffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x7020ca10 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x28e08210 | _VS | _AQ | _AN);
dmm32 A0.w, 0xe650ec98;
dmm32 A0.x, 0xffffffff;
imm32 R1, 0xcca1b6ef;
imm32 R2, 0xd762b783;
imm32 R3, 0xef34e465;
R2 = (A0 += R3.L * R1.H) (IU);
checkreg R2, 0xffffffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x28e08210 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x58904e00 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0xb84b0e88;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x8367ffff;
imm32 R1, 0xb6a1af0a;
R1.L = (A0 += R0.H * R1.H) (IU);
checkreg R1, 0xb6a1ffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x58904e00 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x30900810 | _VS | _AV1S | _AC1 | _AQ | _CC);
dmm32 A1.w, 0xd0762eff;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0x00000000;
imm32 R1, 0x1d9b7fff;
imm32 R3, 0xf32bf32b;
R0.H = (A1 += R1.L * R3.L) (M, IU);
checkreg R0, 0x7fff0000;
checkreg A1.w, 0x4a0abbd4;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x30900810 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
dmm32 A1.w, 0xf1008000;
dmm32 A1.x, 0xffffffff;
imm32 R3, 0x0bb78001;
imm32 R5, 0x0be78000;
imm32 R7, 0x17cd9a40;
R3.H = (A1 += R7.L * R5.L) (M, IU);
checkreg R3, 0x80008001;
checkreg A1.w, 0xbe208000;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x40900490 | _VS | _AV1S);
dmm32 A1.w, 0xa9d97d12;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0x4e01ffff;
imm32 R3, 0x12abdd35;
imm32 R7, 0xa9d966d6;
R7.H = (A1 += R0.L * R3.L) (M, IU);
checkreg R7, 0x800066d6;
checkreg A1.w, 0xa9d89fdd;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x40900490 | _VS | _V | _AV1S | _V_COPY);
dmm32 ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
dmm32 A1.w, 0xe552d880;
dmm32 A1.x, 0xffffffff;
imm32 R3, 0xfe6bf901;
imm32 R5, 0xfae40000;
imm32 R6, 0x3917f106;
R5.H = (A1 += R6.L * R3.H) (M, IU);
checkreg R5, 0x80000000;
checkreg A1.w, 0xd6708a02;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x2050c490 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0xfcd2b056;
dmm32 A1.x, 0xffffffff;
imm32 R2, 0xff36c118;
imm32 R4, 0xfffe0001;
imm32 R7, 0x7fff00f4;
R7.H = (A1 += R2.L * R4.H) (M, IU);
checkreg R7, 0x800000f4;
checkreg A1.w, 0xbdeb2e26;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x2050c490 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x391f1bbc;
dmm32 A1.x, 0x0000004d;
imm32 R3, 0xae387ec2;
imm32 R4, 0x7fff99ff;
imm32 R5, 0x46730cf4;
R5 = (A1 += R4.L * R3.H) (M, IU);
checkreg R5, 0x7fffffff;
checkreg A1.w, 0xf3b41d84;
checkreg A1.x, 0x0000004c;
checkreg ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x60d00200 | _VS | _AV1S | _CC);
dmm32 A1.w, 0x002b5780;
dmm32 A1.x, 0x00000000;
imm32 R1, 0xa07dffff;
imm32 R2, 0xf90db994;
imm32 R4, 0x46150060;
R2.H = (A1 -= R1.L * R4.L) (M, IU);
checkreg R2, 0x7fffb994;
checkreg A1.w, 0x002b57e0;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x60d00200 | _VS | _V | _AV1S | _CC | _V_COPY);
dmm32 ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV1 | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x52768086;
dmm32 A1.x, 0x00000035;
imm32 R2, 0x1e89d049;
imm32 R6, 0x5312dd14;
imm32 R7, 0x02e3d1f4;
R7 = (A1 += R2.L * R6.L) (M, IU);
checkreg R7, 0x7fffffff;
checkreg A1.w, 0x2941cb3a;
checkreg A1.x, 0x00000035;
checkreg ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 A1.w, 0x00005d96;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x00006828;
imm32 R5, 0xfffe5480;
imm32 R7, 0x40000009;
R5 = (A1 -= R1.L * R7.H) (M, IU);
checkreg R5, 0xe5f65d96;
checkreg A1.w, 0xe5f65d96;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x3cb08080 | _VS | _AC1 | _CC | _AC0_COPY | _AZ);
dmm32 A1.w, 0x8b063fca;
dmm32 A1.x, 0xffffffa2;
imm32 R3, 0x5f5b566b;
imm32 R4, 0x800022e6;
imm32 R5, 0x741acdad;
R3 = (A1 += R5.L * R4.L) (M, IU);
checkreg R3, 0x80000000;
checkreg A1.w, 0x842a0338;
checkreg A1.x, 0xffffffa2;
checkreg ASTAT, (0x3cb08080 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x60d08a00 | _VS | _AC0 | _AQ | _AN);
dmm32 A1.w, 0x54eebd9e;
dmm32 A1.x, 0x00000000;
imm32 R5, 0x05fa881c;
imm32 R7, 0xb0728448;
R5 = (A1 -= R7.L * R5.L) (M, IU);
checkreg R5, 0x7fffffff;
checkreg A1.w, 0x96b605be;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x60d08a00 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN);
pass
|
stsp/binutils-ia16
| 1,513
|
sim/testsuite/bfin/c_dsp32alu_rrpm_aa.s
|
//Original:/testcases/core/c_dsp32alu_rrpm_aa/c_dsp32alu_rrpm_aa.dsp
// Spec Reference: dsp32alu (dregs, dregs) = +/- (a, a) amod1
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
imm32 r0, 0x75678911;
imm32 r1, 0xa789ab2d;
imm32 r2, 0x34745515;
imm32 r3, 0x46677757;
imm32 r4, 0xb567a96b;
imm32 r5, 0x6789aa1d;
imm32 r6, 0x744455a5;
imm32 r7, 0x8666777a;
A0 = R0;
A1 = R1;
R0 = A1 + A0, R7 = A1 - A0 (NS);
R1 = A0 + A1, R6 = A0 - A1 (NS);
R2 = A1 + A0, R5 = A1 - A0 (NS);
R3 = A0 + A1, R4 = A0 - A1 (NS);
R4 = A1 + A0, R0 = A1 - A0 (NS);
R5 = A0 + A1, R1 = A0 - A1 (NS);
R6 = A0 + A1, R2 = A0 - A1 (NS);
R7 = A1 + A0, R3 = A1 - A0 (NS);
CHECKREG r0, 0x3222221C;
CHECKREG r1, 0xCDDDDDE4;
CHECKREG r2, 0xCDDDDDE4;
CHECKREG r3, 0x3222221C;
CHECKREG r4, 0x1CF1343E;
CHECKREG r5, 0x1CF1343E;
CHECKREG r6, 0x1CF1343E;
CHECKREG r7, 0x1CF1343E;
imm32 r0, 0x8537891b;
imm32 r1, 0x3759ab2d;
imm32 r2, 0x4e555535;
imm32 r3, 0x16e65747;
imm32 r4, 0x687e9565;
imm32 r5, 0x7a8aeb5b;
imm32 r6, 0x8c9cdd85;
imm32 r7, 0x9eaefe9f;
A0 = R0;
A1 = R1;
R3 = A1 + A0, R7 = A1 - A0 (S);
R4 = A0 + A1, R6 = A0 - A1 (S);
R5 = A1 + A0, R4 = A1 - A0 (S);
R6 = A0 + A1, R5 = A0 - A1 (S);
R7 = A1 + A0, R3 = A1 - A0 (S);
R0 = A0 + A1, R2 = A0 - A1 (S);
R1 = A0 + A1, R0 = A0 - A1 (S);
R2 = A1 + A0, R1 = A1 - A0 (S);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x7FFFFFFF;
CHECKREG r2, 0xBC913448;
CHECKREG r3, 0x7FFFFFFF;
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0xBC913448;
CHECKREG r7, 0xBC913448;
pass
|
stsp/binutils-ia16
| 4,235
|
sim/testsuite/bfin/c_multi_issue_dsp_ld_ld.s
|
//Original:/testcases/core/c_multi_issue_dsp_ld_ld/c_multi_issue_dsp_ld_ld.dsp
// Spec Reference: dsp32mac and 2 loads
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0
loadsym I1, DATA1
loadsym P1, DATA0
loadsym P2, DATA1
// test the default (signed fraction : left )
imm32 r0, 0x12345678;
imm32 r1, 0x33456789;
imm32 r2, 0x5556789a;
imm32 r3, 0x75678912;
imm32 r4, 0x86789123;
imm32 r5, 0xa7891234;
imm32 r6, 0xc1234567;
imm32 r7, 0xf1234567;
A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ];
A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || R5 = [ I1 ++ ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x000A0000;
CHECKREG r1, 0x00F00100;
CHECKREG r2, 0x000B0001;
CHECKREG r3, 0x00E00101;
CHECKREG r4, 0x000A0000;
CHECKREG r5, 0x00D00102;
CHECKREG r6, 0x92793486;
CHECKREG r7, 0xDD2F9BAA;
imm32 r0, 0x12245618;
imm32 r1, 0x23256719;
imm32 r2, 0x3426781a;
imm32 r3, 0x45278912;
imm32 r4, 0x56289113;
imm32 r5, 0x67291214;
imm32 r6, 0xa1234517;
imm32 r7, 0xc1234517;
A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || R6 = [ I0 ++ ];
A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || R3 = [ I1 ++ ];
A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x12245618;
CHECKREG r1, 0x23256719;
CHECKREG r2, 0x00F00100;
CHECKREG r3, 0x00C00103;
CHECKREG r4, 0x000B0001;
CHECKREG r5, 0x67291214;
CHECKREG r6, 0x863ABC70;
CHECKREG r7, 0xB4EF6A10;
imm32 r0, 0x15245648;
imm32 r1, 0x25256749;
imm32 r2, 0x3526784a;
imm32 r3, 0x45278942;
imm32 r4, 0x55389143;
imm32 r5, 0x65391244;
imm32 r6, 0xa5334547;
imm32 r7, 0xc5334547;
A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || R0 = [ I1 -- ];
A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || R4 = [ I0 ++ ];
A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R5 = [ I0 -- ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00A00105;
CHECKREG r1, 0x25256749;
CHECKREG r2, 0x000C0002;
CHECKREG r3, 0x00D00102;
CHECKREG r4, 0x000D0003;
CHECKREG r5, 0x000E0004;
CHECKREG r6, 0xCBDCD104;
CHECKREG r7, 0x0001DAE8;
imm32 r1, 0x02450789;
imm32 r2, 0x0356089a;
imm32 r3, 0x04670912;
imm32 r4, 0x05780123;
imm32 r5, 0x06890234;
imm32 r6, 0x07230567;
imm32 r7, 0x00230567;
R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R1 = [ I1 ++ ] || R0 = [ I0 -- ];
R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || R3 = [ I0 -- ];
R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || R4 = [ I0 ++ ];
CHECKREG r0, 0xFA99FFDD;
CHECKREG r1, 0x0B8A0E79;
CHECKREG r2, 0x00610336;
CHECKREG r3, 0x000C0002;
CHECKREG r4, 0x000B0001;
CHECKREG r5, 0x009F0105;
CHECKREG r6, 0x000D0003;
CHECKREG r7, 0x00230567;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
.dd 0x001d0003
.dd 0x00010004
.dd 0x00010005
.dd 0x02100006
.dd 0x02200007
.dd 0x02300008
.dd 0x02200009
.dd 0x0250000a
.dd 0x0260000b
.dd 0x0270000c
.dd 0x0280000d
.dd 0x0290000e
.dd 0x2100000f
.dd 0x22000010
.dd 0x22000011
.dd 0x24000012
.dd 0x25000013
.dd 0x26000014
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
.dd 0x00b00104
.dd 0x00a00105
.dd 0x00900106
.dd 0x00800107
.dd 0x00100108
.dd 0x00200109
.dd 0x0030010a
.dd 0x0040010b
.dd 0x0050011c
.dd 0x0060010d
.dd 0x0070010e
.dd 0x0080010f
.dd 0x00900110
.dd 0x01000111
.dd 0x02000112
.dd 0x03000113
.dd 0x04000114
.dd 0x05000115
.dd 0x03f00100
.dd 0x03e00101
.dd 0x03d00102
.dd 0x03c00103
.dd 0x03b00104
.dd 0x03a00105
.dd 0x03900106
.dd 0x03800107
.dd 0x03100108
.dd 0x03200109
.dd 0x0330010a
.dd 0x0330010b
.dd 0x0350011c
.dd 0x0360010d
.dd 0x0370010e
.dd 0x0380010f
.dd 0x03900110
.dd 0x31000111
.dd 0x32000112
.dd 0x33000113
.dd 0x34000114
|
stsp/binutils-ia16
| 3,798
|
sim/testsuite/bfin/c_dsp32mac_pair_a1a0_m.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_m/c_dsp32mac_pair_a1a0_m.dsp
// Spec Reference: dsp32mac pair a1a0 M MNOP
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R0.L * R1.L ) (M), R6 = ( A0 = R0.L * R1.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R3.L * R2.L ) (M), R0 = ( A0 = R3.H * R2.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R7.L * R6.L ) (M), R2 = ( A0 += R7.H * R6.H ) (IS);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R5.L * R4.L ) (M), R4 = ( A0 += R5.L * R4.H ) (IS);
FP = A0.w;
CHECKREG r0, 0x002D4356;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0x00061B84;
CHECKREG r3, 0xFF23D196;
CHECKREG r4, 0x07C7B86C;
CHECKREG r5, 0xCED42319;
CHECKREG r6, 0xFF910EEB;
CHECKREG r7, 0x5A4E0EEB;
CHECKREG p1, 0x5A4E0EEB;
CHECKREG p2, 0xFF910EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0x002D4356;
CHECKREG p5, 0xFF23D196;
CHECKREG sp, 0x00061B84;
CHECKREG fp, 0x07C7B86C;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = A1, R4 = ( A0 = R3.L * R1.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R1 = A1, R0 = ( A0 -= R0.H * R5.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R3 = A1, R2 = ( A0 += R2.H * R7.H ) (IS);
P5 = A1.w;
SP = A0.w;
R1 = A1, R0 = ( A0 -= R4.L * R6.H ) (IS);
FP = A1.w;
CHECKREG r0, 0xE7CEC8D1;
CHECKREG r1, 0xCED42319;
CHECKREG r2, 0xE7CC2775;
CHECKREG r3, 0xCED42319;
CHECKREG r4, 0xFFFFC7E3;
CHECKREG r5, 0xCED42319;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xCED42319;
CHECKREG p2, 0xFFFFC7E3;
CHECKREG p3, 0xCED42319;
CHECKREG p4, 0x0E31C25D;
CHECKREG p5, 0xCED42319;
CHECKREG sp, 0xE7CC2775;
CHECKREG fp, 0xCED42319;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R4.H * R3.L ) (M), R4 = ( A0 = R4.L * R3.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R7 = A1, R6 = ( A0 = R5.H * R0.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R2.H * R6.L ) (M), R0 = ( A0 += R2.H * R6.H ) (IS);
P5 = A1.w;
SP = A0.w;
R5 = A1, R4 = ( A0 += R7.L * R1.H ) (IS);
FP = A1.w;
CHECKREG r0, 0xECB84AE7;
CHECKREG r1, 0x5091B70C;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0xD3A83F94;
CHECKREG r5, 0x5091B70C;
CHECKREG r6, 0xF2A0B667;
CHECKREG r7, 0xCED3B05D;
CHECKREG p1, 0xCED3B05D;
CHECKREG p2, 0x000095DF;
CHECKREG p3, 0xCED3B05D;
CHECKREG p4, 0xF2A0B667;
CHECKREG p5, 0x5091B70C;
CHECKREG sp, 0xECB84AE7;
CHECKREG fp, 0x5091B70C;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = A1, R0 = ( A0 = R5.L * R2.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R3.H * R1.H ) (M), R2 = ( A0 -= R3.H * R1.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS);
P5 = A0.w;
SP = A1.w;
R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS);
FP = A0.w;
CHECKREG r0, 0xDA854033;
CHECKREG r1, 0x5091B70C;
CHECKREG r2, 0xCD00D267;
CHECKREG r3, 0xF1127221;
CHECKREG r4, 0xBDCBD4BD;
CHECKREG r5, 0x58A90256;
CHECKREG r6, 0xBB976699;
CHECKREG r7, 0x58A90256;
CHECKREG p1, 0x5091B70C;
CHECKREG p2, 0xDA854033;
CHECKREG p3, 0xF1127221;
CHECKREG p4, 0xCD00D267;
CHECKREG p5, 0xBDCBD4BD;
CHECKREG sp, 0x58A90256;
CHECKREG fp, 0xBB976699;
pass
|
stsp/binutils-ia16
| 7,214
|
sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_brcc_mv_pop/c_seq_ex1_raise_brcc_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
R0 = 0;
ASTAT = R0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
RAISE 2; // RTN
IF !CC JUMP LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
RAISE 6; // RTI
IF !CC JUMP LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
RAISE 7; // RTI
IF CC JUMP LABEL4; // SHOULD NOT EXECUTE
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
LABEL4:
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
RAISE 8; // RTI
IF !CC JUMP LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 1,432
|
sim/testsuite/bfin/m14.s
|
// Test extraction from accumulators:
// UNSIGNED FRACTIONAL and SIGNED INT mode into register PAIR
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffffff0
// load r1=0xfffffff0
// load r2=0x0fffffff
// load r3=0x00000001
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// extract
// 0x00fffffff0 -> 0xffffffff0
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R7 = A1, R6 = A0 (FU);
DBGA ( R7.L , 0xfff0 );
DBGA ( R7.H , 0xffff );
DBGA ( R6.L , 0xfff0 );
DBGA ( R6.H , 0xffff );
// extract with saturation
// 0x01fffffff0 -> 0xfffffffff
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
A1.x = R3.L;
A0.x = R3.L;
R7 = A1, R6 = A0 (FU);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0xffff );
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
// extract with saturation
// 0xfffffffff0 -> 0xfffffffff
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
A1.x = R4.L;
A0.x = R4.L;
R7 = A1, R6 = A0 (FU);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0xffff );
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
// extract unsigned
// 0x00fffffff0 -> 0xffffffff0
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R7 = A1, R6 = A0 (FU);
DBGA ( R7.L , 0xfff0 );
DBGA ( R7.H , 0xffff );
DBGA ( R6.L , 0xfff0 );
DBGA ( R6.H , 0xffff );
pass
.data
data0:
.dw 0xfff0
.dw 0x7fff
.dw 0xfff0
.dw 0xffff
.dw 0xffff
.dw 0x0fff
.dw 0x0001
.dw 0x0000
.dw 0x00ff
.dw 0x0000
|
stsp/binutils-ia16
| 6,210
|
sim/testsuite/bfin/c_dsp32mac_pair_a0_u.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_u/c_dsp32mac_pair_a0_u.dsp
// Spec Reference: dsp32mac pair a0 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (FU);
P1 = A0.w;
A1 -= R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (FU);
P2 = A0.w;
A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (FU);
P3 = A0.w;
A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (FU);
P4 = A0.w;
CHECKREG r0, 0x00049ABC;
CHECKREG r1, 0x86BCFEC7;
CHECKREG r2, 0x60FC9ACC;
CHECKREG r3, 0x00860007;
CHECKREG r4, 0x60FC9ACC;
CHECKREG r5, 0x1235860B;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x678E0086;
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x00049ABC;
CHECKREG p3, 0x60FC9ACC;
CHECKREG p4, 0x60FC9ACC;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A0.w;
A1 -= R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ) (FU);
P2 = A0.w;
A1 = R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (FU);
P3 = A0.w;
A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (FU);
P4 = A0.w;
CHECKREG r0, 0x0523F7E8;
CHECKREG r1, 0xA1BCF4C7;
CHECKREG r2, 0x05183CD2;
CHECKREG r3, 0x00010005;
CHECKREG r4, 0x47763CEB;
CHECKREG r5, 0x1235010B;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x47763CEB;
CHECKREG p2, 0x00032564;
CHECKREG p3, 0x05183CD2;
CHECKREG p4, 0x0523F7E8;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A0.w;
A1 -= R2.H * R3.L, R6 = ( A0 -= R2.H * R3.L ) (FU);
P2 = A0.w;
A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (FU);
P3 = A0.w;
A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (FU);
P4 = A0.w;
CHECKREG r0, 0x2E395300;
CHECKREG r1, 0xABD69EC7;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x8D7C0C72;
CHECKREG r5, 0x1225010B;
CHECKREG r6, 0x2B29EB7F;
CHECKREG r7, 0x678E0561;
CHECKREG p1, 0x2B2D030B;
CHECKREG p2, 0x2B29EB7F;
CHECKREG p3, 0x2E395300;
CHECKREG p4, 0x8D7C0C72;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (FU);
P1 = A0.w;
A1 = R2.H * R1.H, R2 = ( A0 = R2.H * R1.L ) (FU);
P2 = A0.w;
A1 -= R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (FU);
P3 = A0.w;
A1 -= R4.H * R6.H, R6 = ( A0 -= R4.L * R6.H ) (FU);
P4 = A0.w;
CHECKREG r0, 0x0003F74D;
CHECKREG r1, 0x91BCFEC7;
CHECKREG r2, 0xA845468C;
CHECKREG r3, 0xD0910007;
CHECKREG r4, 0xA8467E26;
CHECKREG r5, 0xD235910B;
CHECKREG r6, 0xA1D8A65E;
CHECKREG r7, 0x67DE0009;
CHECKREG p1, 0x0003F74D;
CHECKREG p2, 0xA845468C;
CHECKREG p3, 0xA8467E26;
CHECKREG p4, 0xA1D8A65E;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (FU);
P5 = A1.w;
P1 = A0.w;
A1 = R2.L * R3.L (M), R0 = ( A0 -= R2.H * R3.L ) (FU);
P2 = A0.w;
A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (FU);
P3 = A0.w;
A1 -= R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (FU);
P4 = A0.w;
CHECKREG r0, 0x5A49742F;
CHECKREG r1, 0x86BCFEC7;
CHECKREG r2, 0xBB41743F;
CHECKREG r3, 0x00860007;
CHECKREG r4, 0xBC5110E6;
CHECKREG r5, 0x1235860B;
CHECKREG r6, 0x5A4E0EEB;
CHECKREG r7, 0x678E0086;
CHECKREG p1, 0x5A4E0EEB;
CHECKREG p2, 0x5A49742F;
CHECKREG p3, 0xBB41743F;
CHECKREG p4, 0xBC5110E6;
CHECKREG p5, 0x573CE4B9;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R4 = ( A0 -= R1.L * R0.L ) (FU);
P1 = A0.w;
R0 = ( A0 = R2.H * R3.L ) (FU);
P2 = A0.w;
R2 = ( A0 += R4.H * R5.H ) (FU);
P3 = A0.w;
R0 = ( A0 -= R6.L * R7.H ) (FU);
P4 = A0.w;
CHECKREG r0, 0x0846EF70;
CHECKREG r1, 0xA1BCF4C7;
CHECKREG r2, 0x0852AA86;
CHECKREG r3, 0x00010005;
CHECKREG r4, 0x74DAD3FB;
CHECKREG r5, 0x1235010B;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x74DAD3FB;
CHECKREG p2, 0x00032564;
CHECKREG p3, 0x0852AA86;
CHECKREG p4, 0x0846EF70;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A0.w;
R6 = ( A0 = R2.H * R3.L ) (FU);
P2 = A0.w;
A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (FU);
P3 = A0.w;
R4 = ( A0 += R6.L * R7.H ) (FU);
P4 = A0.w;
CHECKREG r0, 0x03127F0D;
CHECKREG r1, 0xABD69EC7;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x0C98E2B5;
CHECKREG r5, 0x1225010B;
CHECKREG r6, 0x0003178C;
CHECKREG r7, 0x678E0561;
CHECKREG p1, 0x2B2D030B;
CHECKREG p2, 0x0003178C;
CHECKREG p3, 0x03127F0D;
CHECKREG p4, 0x0C98E2B5;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R0 = ( A0 = R5.L * R3.L ) (FU);
P1 = A0.w;
A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (FU);
P2 = A0.w;
A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (FU);
P3 = A0.w;
R6 = ( A0 += R4.L * R6.H ) (FU);
P4 = A0.w;
CHECKREG r0, 0x0003F74D;
CHECKREG r1, 0x91BCFEC7;
CHECKREG r2, 0xA845468C;
CHECKREG r3, 0xD0910007;
CHECKREG r4, 0xA8440EF2;
CHECKREG r5, 0xD235910B;
CHECKREG r6, 0xA9070C4A;
CHECKREG r7, 0x67DE0009;
CHECKREG p1, 0x0003F74D;
CHECKREG p2, 0xA845468C;
CHECKREG p3, 0xA8440EF2;
CHECKREG p4, 0xA9070C4A;
pass
|
stsp/binutils-ia16
| 2,438
|
sim/testsuite/bfin/c_compi2opd_dr_add_i7_p.s
|
//Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp
// Spec Reference: compi2opd dregs += imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 += 0;
R1 += 1;
R2 += 2;
R3 += 3;
R4 += 4;
R5 += 5;
R6 += 6;
R7 += 7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
R0 += 8;
R1 += 9;
R2 += 10;
R3 += 11;
R4 += 12;
R5 += 13;
R6 += 14;
R7 += 15;
CHECKREG r0, 0x00000008;
CHECKREG r1, 0x0000000A;
CHECKREG r2, 0x0000000C;
CHECKREG r3, 0x0000000E;
CHECKREG r4, 0x00000010;
CHECKREG r5, 0x00000012;
CHECKREG r6, 0x00000014;
CHECKREG r7, 0x00000016;
R0 += 16;
R1 += 17;
R2 += 18;
R3 += 19;
R4 += 20;
R5 += 21;
R6 += 22;
R7 += 23;
CHECKREG r0, 0x00000018;
CHECKREG r1, 0x0000001B;
CHECKREG r2, 0x0000001E;
CHECKREG r3, 0x00000021;
CHECKREG r4, 0x00000024;
CHECKREG r5, 0x00000027;
CHECKREG r6, 0x0000002A;
CHECKREG r7, 0x0000002D;
R0 += 24;
R1 += 25;
R2 += 26;
R3 += 27;
R4 += 28;
R5 += 29;
R6 += 30;
R7 += 31;
CHECKREG r0, 0x00000030;
CHECKREG r1, 0x00000034;
CHECKREG r2, 0x00000038;
CHECKREG r3, 0x0000003C;
CHECKREG r4, 0x00000040;
CHECKREG r5, 0x00000044;
CHECKREG r6, 0x00000048;
CHECKREG r7, 0x0000004C;
R0 += 32;
R1 += 33;
R2 += 34;
R3 += 35;
R4 += 36;
R5 += 37;
R6 += 38;
R7 += 39;
CHECKREG r0, 0x00000050;
CHECKREG r1, 0x00000055;
CHECKREG r2, 0x0000005A;
CHECKREG r3, 0x0000005F;
CHECKREG r4, 0x00000064;
CHECKREG r5, 0x00000069;
CHECKREG r6, 0x0000006E;
CHECKREG r7, 0x00000073;
R0 += 40;
R1 += 41;
R2 += 42;
R3 += 43;
R4 += 44;
R5 += 45;
R6 += 46;
R7 += 47;
CHECKREG r0, 0x00000078;
CHECKREG r1, 0x0000007E;
CHECKREG r2, 0x00000084;
CHECKREG r3, 0x0000008A;
CHECKREG r4, 0x00000090;
CHECKREG r5, 0x00000096;
CHECKREG r6, 0x0000009C;
CHECKREG r7, 0x000000A2;
R0 += 48;
R1 += 49;
R2 += 50;
R3 += 51;
R4 += 52;
R5 += 53;
R6 += 54;
R7 += 55;
CHECKREG r0, 0x000000A8;
CHECKREG r1, 0x000000AF;
CHECKREG r2, 0x000000B6;
CHECKREG r3, 0x000000BD;
CHECKREG r4, 0x000000C4;
CHECKREG r5, 0x000000CB;
CHECKREG r6, 0x000000D2;
CHECKREG r7, 0x000000D9;
R0 += 56;
R1 += 57;
R2 += 58;
R3 += 59;
R4 += 60;
R5 += 61;
R6 += 62;
R7 += 63;
CHECKREG r0, 0x000000E0;
CHECKREG r1, 0x000000E8;
CHECKREG r2, 0x000000F0;
CHECKREG r3, 0x000000F8;
CHECKREG r4, 0x00000100;
CHECKREG r5, 0x00000108;
CHECKREG r6, 0x00000110;
CHECKREG r7, 0x00000118;
pass
|
stsp/binutils-ia16
| 6,606
|
sim/testsuite/bfin/c_dsp32alu_rrppmm.s
|
//Original:/testcases/core/c_dsp32alu_rrppmm/c_dsp32alu_rrppmm.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) amod0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x95679911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717;
imm32 r4, 0x5597891b;
imm32 r5, 0x6989ab1d;
imm32 r6, 0x94445515;
imm32 r7, 0x96667777;
R0 = R0 +|+ R0, R7 = R0 -|- R0;
R1 = R0 +|+ R1, R6 = R0 -|- R1;
R2 = R0 +|+ R2, R5 = R0 -|- R2;
R3 = R0 +|+ R3, R4 = R0 -|- R3;
R4 = R0 +|+ R4, R3 = R0 -|- R4;
R5 = R0 +|+ R5, R2 = R0 -|- R5;
R6 = R0 +|+ R6, R1 = R0 -|- R6;
R7 = R0 +|+ R7, R0 = R0 -|- R7;
CHECKREG r0, 0x2ACE3222;
CHECKREG r1, 0x2789AB1D;
CHECKREG r2, 0x34945515;
CHECKREG r3, 0x46967717;
CHECKREG r4, 0x0F06ED2D;
CHECKREG r5, 0x21080F2F;
CHECKREG r6, 0x2E13B927;
CHECKREG r7, 0x2ACE3222;
imm32 r0, 0x11678911;
imm32 r1, 0xa719ab1d;
imm32 r2, 0x3a415515;
imm32 r3, 0x46a67717;
imm32 r4, 0x556a891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0 = R1 +|+ R0, R7 = R1 -|- R0;
R1 = R1 +|+ R1, R6 = R1 -|- R1;
R2 = R1 +|+ R2, R5 = R1 -|- R2;
R3 = R1 +|+ R3, R4 = R1 -|- R3;
R4 = R1 +|+ R4, R3 = R1 -|- R4;
R5 = R1 +|+ R5, R2 = R1 -|- R5;
R6 = R1 +|+ R6, R1 = R1 -|- R6;
R7 = R1 +|+ R7, R0 = R1 -|- R7;
CHECKREG r0, 0xB880342E;
CHECKREG r1, 0x4E32563A;
CHECKREG r2, 0x3A415515;
CHECKREG r3, 0x46A67717;
CHECKREG r4, 0x55BE355D;
CHECKREG r5, 0x6223575F;
CHECKREG r6, 0x4E32563A;
CHECKREG r7, 0xE3E47846;
imm32 r0, 0xb567891b;
imm32 r1, 0x2b89abbd;
imm32 r2, 0x34b45b15;
imm32 r3, 0x466bb717;
imm32 r4, 0x556bb91b;
imm32 r5, 0x67b9ab1d;
imm32 r6, 0x7b4455b5;
imm32 r7, 0xb666777b;
R0 = R2 +|+ R0, R7 = R2 -|- R0;
R1 = R2 +|+ R1, R6 = R2 -|- R1;
R2 = R2 +|+ R2, R5 = R2 -|- R2;
R3 = R2 +|+ R3, R4 = R2 -|- R3;
R4 = R2 +|+ R4, R3 = R2 -|- R4;
R5 = R2 +|+ R5, R2 = R2 -|- R5;
R6 = R2 +|+ R6, R1 = R2 -|- R6;
R7 = R2 +|+ R7, R0 = R2 -|- R7;
CHECKREG r0, 0xEA1BE430;
CHECKREG r1, 0x603D06D2;
CHECKREG r2, 0x6968B62A;
CHECKREG r3, 0x466BB717;
CHECKREG r4, 0x8C65B53D;
CHECKREG r5, 0x6968B62A;
CHECKREG r6, 0x72936582;
CHECKREG r7, 0xE8B58824;
imm32 r0, 0xbc678c11;
imm32 r1, 0x27c9cb1d;
imm32 r2, 0x344c5515;
imm32 r3, 0x46c6c717;
imm32 r4, 0x55678c1b;
imm32 r5, 0x6c89abcd;
imm32 r6, 0x7444551c;
imm32 r7, 0x8c667777;
R0 = R3 +|+ R0, R7 = R3 -|- R0;
R1 = R3 +|+ R1, R6 = R3 -|- R1;
R2 = R3 +|+ R2, R5 = R3 -|- R2;
R3 = R3 +|+ R3, R4 = R3 -|- R3;
R4 = R3 +|+ R4, R3 = R3 -|- R4;
R5 = R3 +|+ R5, R2 = R3 -|- R5;
R6 = R3 +|+ R6, R1 = R3 -|- R6;
R7 = R3 +|+ R7, R0 = R3 -|- R7;
CHECKREG r0, 0x032D5328;
CHECKREG r1, 0x6E8F9234;
CHECKREG r2, 0x7B121C2C;
CHECKREG r3, 0x8D8C8E2E;
CHECKREG r4, 0x8D8C8E2E;
CHECKREG r5, 0xA0060030;
CHECKREG r6, 0xAC898A28;
CHECKREG r7, 0x17EBC934;
imm32 r0, 0xd56789d1;
imm32 r1, 0x2d89abdd;
imm32 r2, 0x34d455d5;
imm32 r3, 0x4d667717;
imm32 r4, 0x5dd7891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xd44d5515;
imm32 r7, 0xd666d777;
R0 = R4 +|+ R0, R7 = R4 -|- R0;
R1 = R4 +|+ R1, R6 = R4 -|- R1;
R2 = R4 +|+ R2, R5 = R4 -|- R2;
R3 = R4 +|+ R3, R4 = R4 -|- R3;
R4 = R4 +|+ R4, R3 = R4 -|- R4;
R5 = R4 +|+ R5, R2 = R4 -|- R5;
R6 = R4 +|+ R6, R1 = R4 -|- R6;
R7 = R4 +|+ R7, R0 = R4 -|- R7;
CHECKREG r0, 0x987224BE;
CHECKREG r1, 0xF09446CA;
CHECKREG r2, 0xF7DFF0C2;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x20E22408;
CHECKREG r5, 0x49E5574E;
CHECKREG r6, 0x51300146;
CHECKREG r7, 0xA9522352;
imm32 r0, 0xc567a911;
imm32 r1, 0x278aab1d;
imm32 r2, 0x3c445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x55c7891b;
imm32 r5, 0x6a8cab1d;
imm32 r6, 0x7444c515;
imm32 r7, 0xa6667c77;
R0 = R5 +|+ R0, R7 = R5 -|- R0;
R1 = R5 +|+ R1, R6 = R5 -|- R1;
R2 = R5 +|+ R2, R5 = R5 -|- R2;
R3 = R5 +|+ R3, R4 = R5 -|- R3;
R4 = R5 +|+ R4, R3 = R5 -|- R4;
R5 = R5 +|+ R5, R2 = R5 -|- R5;
R6 = R5 +|+ R6, R1 = R5 -|- R6;
R7 = R5 +|+ R7, R0 = R5 -|- R7;
CHECKREG r0, 0xB76BAA04;
CHECKREG r1, 0x198EAC10;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x46A67717;
CHECKREG r4, 0x15EA34F9;
CHECKREG r5, 0x5C90AC10;
CHECKREG r6, 0x9F92AC10;
CHECKREG r7, 0x01B5AE1C;
imm32 r0, 0xd5678911;
imm32 r1, 0x2ddddd1d;
imm32 r2, 0x34ddd515;
imm32 r3, 0x46d67717;
imm32 r4, 0x5d6d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445d15;
imm32 r7, 0xd66677d7;
R0 = R6 +|+ R0, R7 = R6 -|- R0;
R1 = R6 +|+ R1, R6 = R6 -|- R1;
R2 = R6 +|+ R2, R5 = R6 -|- R2;
R3 = R6 +|+ R3, R4 = R6 -|- R3;
R4 = R6 +|+ R4, R3 = R6 -|- R4;
R5 = R6 +|+ R5, R2 = R6 -|- R5;
R6 = R6 +|+ R6, R1 = R6 -|- R6;
R7 = R6 +|+ R7, R0 = R6 -|- R7;
CHECKREG r0, 0xEDF12BEC;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x34DDD515;
CHECKREG r3, 0x46D67717;
CHECKREG r4, 0x45F888D9;
CHECKREG r5, 0x57F12ADB;
CHECKREG r6, 0x8CCEFFF0;
CHECKREG r7, 0x2BABD3F4;
imm32 r0, 0xf567a911;
imm32 r1, 0x2f8aab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x4a6f7717;
imm32 r4, 0x5567f91b;
imm32 r5, 0xa789af1d;
imm32 r6, 0x74445515;
imm32 r7, 0x866677f7;
R0 = R7 +|+ R0, R7 = R7 -|- R0;
R1 = R7 +|+ R1, R6 = R7 -|- R1;
R2 = R7 +|+ R2, R5 = R7 -|- R2;
R3 = R7 +|+ R3, R4 = R7 -|- R3;
R4 = R7 +|+ R4, R3 = R7 -|- R4;
R5 = R7 +|+ R5, R2 = R7 -|- R5;
R6 = R7 +|+ R6, R1 = R7 -|- R6;
R7 = R7 +|+ R7, R0 = R7 -|- R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x2F8AAB1D;
CHECKREG r2, 0x34A45515;
CHECKREG r3, 0x4A6F7717;
CHECKREG r4, 0xD78F26B5;
CHECKREG r5, 0xED5A48B7;
CHECKREG r6, 0xF274F2AF;
CHECKREG r7, 0x21FE9DCC;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0x46667717;
imm32 r4, 0x556e891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444e515;
imm32 r7, 0x86667e77;
R4 = R2 +|+ R5, R3 = R2 -|- R5 (S);
R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO);
R2 = R6 +|+ R2, R0 = R6 -|- R2 (SCO);
R3 = R4 +|+ R0, R2 = R4 -|- R0 (S);
R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO);
R6 = R1 +|+ R7, R1 = R1 -|- R7 (SCO);
R5 = R0 +|+ R4, R7 = R0 -|- R4 (S);
R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO);
CHECKREG r0, 0x90003F60;
CHECKREG r1, 0x8FFF7371;
CHECKREG r2, 0x7FFFC0D2;
CHECKREG r3, 0x0FFF3F92;
CHECKREG r4, 0x0BB38FFF;
CHECKREG r5, 0x0FFF3F92;
CHECKREG r6, 0x29330EA9;
CHECKREG r7, 0x80003F2E;
imm32 r0, 0xd5678911;
imm32 r1, 0xff89ab1d;
imm32 r2, 0x34f45515;
imm32 r3, 0x46667717;
imm32 r4, 0x556f891b;
imm32 r5, 0x6789fb1d;
imm32 r6, 0x74445f15;
imm32 r7, 0x866677f7;
R4 = R3 +|+ R3, R5 = R3 -|- R3 (SCO);
R1 = R6 +|+ R1, R6 = R6 -|- R1 (SCO);
R6 = R1 +|+ R4, R4 = R1 -|- R4 (S);
R7 = R4 +|+ R2, R0 = R4 -|- R2 (S);
R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO);
R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO);
R5 = R7 +|+ R7, R3 = R7 -|- R7 (SCO);
R0 = R0 +|+ R0, R2 = R0 -|- R0 (SCO);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0xD516B4F5;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xF3CE8A33;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 8,188
|
sim/testsuite/bfin/c_ldstpmod_ld_lohi.s
|
//Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp
// Spec Reference: c_ldstpmod load dreg lo & hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
R0.L = W [ P5 ++ P1 ];
R1.L = W [ P5 ++ P1 ];
R2.L = W [ P5 ++ P2 ];
R3.L = W [ P5 ++ P3 ];
R4.L = W [ P5 ++ P4 ];
R5.L = W [ P5 ++ SP ];
R6.L = W [ P5 ++ FP ];
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00000405;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00000E0F;
// initial values
P5 = 0x0000;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_2, 0x00;
P3 = I1; SP = I3;
R0.H = W [ P1 ++ P5 ];
R1.H = W [ P1 ++ P2 ];
R2.H = W [ P1 ++ P2 ];
R3.H = W [ P1 ++ P3 ];
R4.H = W [ P1 ++ P4 ];
R5.H = W [ P1 ++ SP ];
R6.H = W [ P1 ++ FP ];
CHECKREG r0, 0x22230203;
CHECKREG r1, 0x22230001;
CHECKREG r2, 0x20210607;
CHECKREG r3, 0x26270405;
CHECKREG r4, 0x24250A0B;
CHECKREG r5, 0x2A2B0809;
CHECKREG r6, 0x28290E0F;
// initial values
P5 = 0x0002;
P1 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p2, DATA_ADDR_2, 0x02;
P3 = I1; SP = I3;
R0.L = W [ P2 ++ P5 ];
R0.H = W [ P2 ++ P1 ];
R1.L = W [ P2 ++ P1 ];
R1.H = W [ P2 ++ P3 ];
R2.H = W [ P2 ++ P4 ];
R2.L = W [ P2 ++ SP ];
R3.L = W [ P2 ++ FP ];
CHECKREG r0, 0x26272021;
CHECKREG r1, 0x2A2B2425;
CHECKREG r2, 0x28292E2F;
CHECKREG r3, 0x26272C2D;
CHECKREG r4, 0x24250A0B;
CHECKREG r5, 0x2A2B0809;
CHECKREG r6, 0x28290E0F;
// initial values
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i1, DATA_ADDR_3, 0x00;
P3 = I1; SP = I3;
R3.L = W [ P3 ++ P5 ];
R3.H = W [ P3 ++ P1 ];
R4.L = W [ P3 ++ P2 ];
R5.H = W [ P3 ++ P1 ];
R5.L = W [ P3 ++ P4 ];
R6.H = W [ P3 ++ SP ];
R6.L = W [ P3 ++ FP ];
CHECKREG r0, 0x26272021;
CHECKREG r1, 0x2A2B2425;
CHECKREG r2, 0x28292E2F;
CHECKREG r3, 0x40414243;
CHECKREG r4, 0x24254647;
CHECKREG r5, 0x44454A4B;
CHECKREG r6, 0x48494E4F;
// initial values
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p4, DATA_ADDR_4, 0x00;
P3 = I1; SP = I3;
R0.H = W [ P4 ++ P5 ];
R0.L = W [ P4 ++ P1 ];
R1.L = W [ P4 ++ P2 ];
R1.H = W [ P4 ++ P3 ];
R2.H = W [ P4 ++ P4 ];
R3.L = W [ P4 ++ SP ];
R3.H = W [ P4 ++ FP ];
CHECKREG r0, 0x62636061;
CHECKREG r1, 0x64656667;
CHECKREG r2, 0x6A6B2E2F;
CHECKREG r3, 0x68696A6B;
CHECKREG r4, 0x24254647;
CHECKREG r5, 0x44454A4B;
CHECKREG r6, 0x48494E4F;
// initial values
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_5, 0x00;
P3 = I1; SP = I3;
R0.H = W [ FP ++ P5 ];
R1.L = W [ FP ++ P1 ];
R2.H = W [ FP ++ P2 ];
R3.H = W [ FP ++ P3 ];
R4.L = W [ FP ++ P4 ];
R5.H = W [ FP ++ SP ];
R6.L = W [ FP ++ P1 ];
CHECKREG r0, 0x82836061;
CHECKREG r1, 0x64658081;
CHECKREG r2, 0x86872E2F;
CHECKREG r3, 0x84856A6B;
CHECKREG r4, 0x24258A8B;
CHECKREG r5, 0x88894A4B;
CHECKREG r6, 0x48498E8F;
// initial values
P5 = 0x0000;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i3, DATA_ADDR_6, 0x00;
P3 = I1; SP = I3;
R0.L = W [ SP ++ P5 ];
R1.H = W [ SP ++ P1 ];
R2.H = W [ SP ++ P2 ];
R3.L = W [ SP ++ P3 ];
R4.H = W [ SP ++ P4 ];
R5.L = W [ SP ++ P5 ];
R6.H = W [ SP ++ FP ];
CHECKREG r0, 0x82830203;
CHECKREG r1, 0x02038081;
CHECKREG r2, 0x00012E2F;
CHECKREG r3, 0x84850607;
CHECKREG r4, 0x04058A8B;
CHECKREG r5, 0x88890A0B;
CHECKREG r6, 0x0A0B8E8F;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 4,351
|
sim/testsuite/bfin/c_multi_issue_dsp_ldst_2.s
|
//Original:/testcases/core/c_multi_issue_dsp_ldst_2/c_multi_issue_dsp_ldst_2.dsp
// Spec Reference: dsp32mac and 2 load/store
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0;
loadsym I1, DATA1;
loadsym P1, DATA0;
loadsym P2, DATA1;
// test the default (signed fraction : left )
imm32 r0, 0x12345678;
imm32 r1, 0x33456789;
imm32 r2, 0x5556789a;
imm32 r3, 0x75678912;
imm32 r4, 0x86789123;
imm32 r5, 0xa7891234;
imm32 r6, 0xc1234567;
imm32 r7, 0xf1234567;
A1 = R0.L * R1.L, A0 = R0.L * R1.L || R2 = B [ P1 ++ ] (X) || R3 = [ I1 ++ ];
A1 += R2.L * R3.L, A0 += R2.L * R3.H || R0 = B [ P1 ++ ] (X) || R1 = [ I1 ++ ];
A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = B [ P2 ++ ] (X) || [ I1 ++ ] = R5;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00E00101;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00F00100;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0xA7891234;
CHECKREG r6, 0x23DB649A;
CHECKREG r7, 0x4D3DD202;
imm32 r0, 0x12245618;
imm32 r1, 0x23256719;
imm32 r2, 0x3426781a;
imm32 r3, 0x45278912;
imm32 r4, 0x56289113;
imm32 r5, 0x67291214;
imm32 r6, 0xa1234517;
imm32 r7, 0xc1234517;
A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = B [ P1 ++ ] (X) || [ I0 ++ ] = R6;
A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = B [ P2 ++ ] (X) || [ I1 ++ ] = R3;
A1 += R4.H * R6.H, A0 -= R4.H * R6.L || R5 = B [ P2 ++ ] (X) || R7 = [ I1 ++ ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x12245618;
CHECKREG r1, 0x23256719;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x45278912;
CHECKREG r4, 0x0000000A;
CHECKREG r5, 0xFFFFFFF0;
CHECKREG r6, 0x863ABC9C;
CHECKREG r7, 0xB4EF6908;
imm32 r0, 0x15245648;
imm32 r1, 0x25256749;
imm32 r2, 0x3526784a;
imm32 r3, 0x45278942;
imm32 r4, 0x55389143;
imm32 r5, 0x65391244;
imm32 r6, 0xa5334547;
imm32 r7, 0xc5334547;
A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = B [ P1 ++ ] (X) || [ I1 -- ] = R3;
A1 += R2.H * R3.H, A0 += R2.L * R3.H || R0 = B [ P2 -- ] (X) || [ I0 ++ ] = R2;
A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = B [ P2 ++ ] (X) || R1 = [ I0 -- ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x000C0002;
CHECKREG r2, 0xFFFFFFA1;
CHECKREG r3, 0xFFFFFFF0;
CHECKREG r4, 0x55389143;
CHECKREG r5, 0x65391244;
CHECKREG r6, 0xD7CFB47A;
CHECKREG r7, 0x0C2925C0;
imm32 r1, 0x02450789;
imm32 r2, 0x0356089a;
imm32 r3, 0x04670912;
imm32 r4, 0x05780123;
imm32 r5, 0x06890234;
imm32 r6, 0x07230567;
imm32 r7, 0x00230567;
R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R0 = B [ P1 ++ ] (X) || [ I0 -- ] = R2;
R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = B [ P1 ] (X) || [ I0 -- ] = R3;
R5 = R4 +|+ R2, R0 = R4 -|- R2 || R3 = B [ P2 ++ ] (X) || R7 = [ I1 ++ ];
CHECKREG r0, 0xFFDDFA99;
CHECKREG r1, 0x0B8A0E79;
CHECKREG r2, 0x001102B3;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFEEFD4C;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00000008;
CHECKREG r7, 0x00B00104;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
.dd 0x001d0003
.dd 0x00010004
.dd 0x00010005
.dd 0x02100006
.dd 0x02200007
.dd 0x02300008
.dd 0x02200009
.dd 0x0250000a
.dd 0x0260000b
.dd 0x0270000c
.dd 0x0280000d
.dd 0x0290000e
.dd 0x2100000f
.dd 0x22000010
.dd 0x22000011
.dd 0x24000012
.dd 0x25000013
.dd 0x26000014
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
.dd 0x00b00104
.dd 0x00a00105
.dd 0x00900106
.dd 0x00800107
.dd 0x00100108
.dd 0x00200109
.dd 0x0030010a
.dd 0x0040010b
.dd 0x0050011c
.dd 0x0060010d
.dd 0x0070010e
.dd 0x0080010f
.dd 0x00900110
.dd 0x01000111
.dd 0x02000112
.dd 0x03000113
.dd 0x04000114
.dd 0x05000115
.dd 0x03f00100
.dd 0x03e00101
.dd 0x03d00102
.dd 0x03c00103
.dd 0x03b00104
.dd 0x03a00105
.dd 0x03900106
.dd 0x03800107
.dd 0x03100108
.dd 0x03200109
.dd 0x0330010a
.dd 0x0330010b
.dd 0x0350011c
.dd 0x0360010d
.dd 0x0370010e
.dd 0x0380010f
.dd 0x03900110
.dd 0x31000111
.dd 0x32000112
.dd 0x33000113
.dd 0x34000114
|
stsp/binutils-ia16
| 4,611
|
sim/testsuite/bfin/c_dsp32shift_signbits_rh.s
|
//Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp
// Spec Reference: dsp32shift signbits dregs_hi
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xd1000000;
imm32 r1, 0xd2000001;
imm32 r2, 0xd3000002;
imm32 r3, 0xd4000003;
imm32 r4, 0xd5000004;
imm32 r5, 0xd6000005;
imm32 r6, 0xd7000006;
imm32 r7, 0xd8000007;
R0.L = SIGNBITS R0.H;
R1.L = SIGNBITS R0.H;
R2.L = SIGNBITS R0.H;
R3.L = SIGNBITS R0.H;
R4.L = SIGNBITS R0.H;
R5.L = SIGNBITS R0.H;
R6.L = SIGNBITS R0.H;
R7.L = SIGNBITS R0.H;
CHECKREG r0, 0xD1000001;
CHECKREG r1, 0xD2000001;
CHECKREG r2, 0xD3000001;
CHECKREG r3, 0xD4000001;
CHECKREG r4, 0xD5000001;
CHECKREG r5, 0xD6000001;
CHECKREG r6, 0xD7000001;
CHECKREG r7, 0xD8000001;
imm32 r0, 0xe200d001;
imm32 r1, 0xe2000001;
imm32 r2, 0xe200d002;
imm32 r3, 0xe200d003;
imm32 r4, 0xe200d004;
imm32 r5, 0xe200d005;
imm32 r6, 0xe200d006;
imm32 r7, 0xe200d007;
R0.L = SIGNBITS R1.H;
R1.L = SIGNBITS R1.H;
R2.L = SIGNBITS R1.H;
R3.L = SIGNBITS R1.H;
R4.L = SIGNBITS R1.H;
R5.L = SIGNBITS R1.H;
R6.L = SIGNBITS R1.H;
R7.L = SIGNBITS R1.H;
CHECKREG r0, 0xE2000002;
CHECKREG r1, 0xE2000002;
CHECKREG r2, 0xE2000002;
CHECKREG r3, 0xE2000002;
CHECKREG r4, 0xE2000002;
CHECKREG r5, 0xE2000002;
CHECKREG r6, 0xE2000002;
CHECKREG r7, 0xE2000002;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0xf000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.L = SIGNBITS R2.H;
R1.L = SIGNBITS R2.H;
R2.L = SIGNBITS R2.H;
R3.L = SIGNBITS R2.H;
R4.L = SIGNBITS R2.H;
R5.L = SIGNBITS R2.H;
R6.L = SIGNBITS R2.H;
R7.L = SIGNBITS R2.H;
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000003;
CHECKREG r2, 0xF0000003;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000003;
CHECKREG r5, 0x00000003;
CHECKREG r6, 0x00000003;
CHECKREG r7, 0x00000003;
imm32 r0, 0x0100f001;
imm32 r1, 0x0100f001;
imm32 r2, 0x0100f002;
imm32 r3, 0x01000010;
imm32 r4, 0x0100f004;
imm32 r5, 0x0100f005;
imm32 r6, 0x0100f006;
imm32 r7, 0x0100f007;
R0.L = SIGNBITS R3.H;
R1.L = SIGNBITS R3.H;
R2.L = SIGNBITS R3.H;
R3.L = SIGNBITS R3.H;
R4.L = SIGNBITS R3.H;
R5.L = SIGNBITS R3.H;
R6.L = SIGNBITS R3.H;
R7.L = SIGNBITS R3.H;
CHECKREG r0, 0x01000006;
CHECKREG r1, 0x01000006;
CHECKREG r2, 0x01000006;
CHECKREG r3, 0x01000006;
CHECKREG r4, 0x01000006;
CHECKREG r5, 0x01000006;
CHECKREG r6, 0x01000006;
CHECKREG r7, 0x01000006;
imm32 r0, 0x04000000;
imm32 r1, 0x04010000;
imm32 r2, 0x04020000;
imm32 r3, 0x04030000;
imm32 r4, 0x04040000;
imm32 r5, 0x04050000;
imm32 r6, 0x04060000;
imm32 r7, 0x04070000;
R0.L = SIGNBITS R4.H;
R1.L = SIGNBITS R4.H;
R2.L = SIGNBITS R4.H;
R3.L = SIGNBITS R4.H;
R4.L = SIGNBITS R4.H;
R5.L = SIGNBITS R4.H;
R6.L = SIGNBITS R4.H;
R7.L = SIGNBITS R4.H;
CHECKREG r0, 0x04000004;
CHECKREG r1, 0x04010004;
CHECKREG r2, 0x04020004;
CHECKREG r3, 0x04030004;
CHECKREG r4, 0x04040004;
CHECKREG r5, 0x04050004;
CHECKREG r6, 0x04060004;
CHECKREG r7, 0x04070004;
imm32 r0, 0xa5010000;
imm32 r1, 0xa5010001;
imm32 r2, 0xa5020000;
imm32 r3, 0xa5030000;
imm32 r4, 0xa5540000;
imm32 r5, 0xa5550000;
imm32 r6, 0xa5060000;
imm32 r7, 0xa5070000;
R0.L = SIGNBITS R5.H;
R1.L = SIGNBITS R5.H;
R2.L = SIGNBITS R5.H;
R3.L = SIGNBITS R5.H;
R4.L = SIGNBITS R5.H;
R5.L = SIGNBITS R5.H;
R6.L = SIGNBITS R5.H;
R7.L = SIGNBITS R5.H;
CHECKREG r0, 0xA5010000;
CHECKREG r1, 0xA5010000;
CHECKREG r2, 0xA5020000;
CHECKREG r3, 0xA5030000;
CHECKREG r4, 0xA5540000;
CHECKREG r5, 0xA5550000;
CHECKREG r6, 0xA5060000;
CHECKREG r7, 0xA5070000;
imm32 r0, 0xb6010000;
imm32 r1, 0xb6010000;
imm32 r2, 0xb602000f;
imm32 r3, 0xb6030000;
imm32 r4, 0xb6040000;
imm32 r5, 0xb6050000;
imm32 r6, 0xb6060000;
imm32 r7, 0xb6670000;
R0.L = SIGNBITS R6.H;
R1.L = SIGNBITS R6.H;
R2.L = SIGNBITS R6.H;
R3.L = SIGNBITS R6.H;
R4.L = SIGNBITS R6.H;
R5.L = SIGNBITS R6.H;
R6.L = SIGNBITS R6.H;
R7.L = SIGNBITS R6.H;
CHECKREG r0, 0xB6010000;
CHECKREG r1, 0xB6010000;
CHECKREG r2, 0xB6020000;
CHECKREG r3, 0xB6030000;
CHECKREG r4, 0xB6040000;
CHECKREG r5, 0xB6050000;
CHECKREG r6, 0xB6060000;
CHECKREG r7, 0xB6670000;
imm32 r0, 0xd7010000;
imm32 r1, 0xd7010000;
imm32 r2, 0xd7020000;
imm32 r3, 0xd7030010;
imm32 r4, 0xd7040000;
imm32 r5, 0xd7050000;
imm32 r6, 0xd7060000;
imm32 r7, 0xd7070000;
R0.L = SIGNBITS R7.H;
R1.L = SIGNBITS R7.H;
R2.L = SIGNBITS R7.H;
R3.L = SIGNBITS R7.H;
R4.L = SIGNBITS R7.H;
R5.L = SIGNBITS R7.H;
R6.L = SIGNBITS R7.H;
R7.L = SIGNBITS R7.H;
CHECKREG r0, 0xD7010001;
CHECKREG r1, 0xD7010001;
CHECKREG r2, 0xD7020001;
CHECKREG r3, 0xD7030001;
CHECKREG r4, 0xD7040001;
CHECKREG r5, 0xD7050001;
CHECKREG r6, 0xD7060001;
CHECKREG r7, 0xD7070001;
pass
|
stsp/binutils-ia16
| 5,233
|
sim/testsuite/bfin/byteop3p.s
|
# Blackfin testcase for BYTEOP3P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop3p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0
dmm32 I1, \i1
R6 = BYTEOP3P (R1:0, R3:2) (LO);
check_it \resL
R6 = BYTEOP3P (R1:0, R3:2) (HI);
check_it \resH
R6 = BYTEOP3P (R1:0, R3:2) (LO, R);
check_it \resLR
R6 = BYTEOP3P (R1:0, R3:2) (HI, R);
check_it \resHR
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop3p 0, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 0, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 0, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 0, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop3p 0, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 0, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 0, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 0, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 1, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 1, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 1, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 1, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 2, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 2, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 2, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 2, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 3, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 3, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 3, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 3, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000
imm32 R0, 0x00010002
imm32 R1, 0x00030004
imm32 R2, 0x10203040
imm32 R3, 0x50607080
test_byteop3p 0, 0, 0x00110032, 0x21004200, 0x00530074, 0x63008400
test_byteop3p 0, 1, 0x00810022, 0x11003200, 0x00430064, 0x53007400
test_byteop3p 0, 2, 0x00710012, 0x81002200, 0x00330054, 0x43006400
test_byteop3p 0, 3, 0x00610082, 0x71001200, 0x00230044, 0x33005400
test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 0, 0x00140031, 0x24004100, 0x00520073, 0x62008300
test_byteop3p 2, 1, 0x00840021, 0x14003100, 0x00420063, 0x52007300
test_byteop3p 2, 2, 0x00740011, 0x84002100, 0x00320053, 0x42006300
test_byteop3p 2, 3, 0x00640081, 0x74001100, 0x00220043, 0x32005300
test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
imm32 R0, 0x00100200
imm32 R1, 0x30000040
imm32 R2, 0x1a2b3c4d
imm32 R3, 0x5e6f7a8b
test_byteop3p 0, 0, 0x002a00ff, 0x3b00ff00, 0x00ff00ba, 0xff00cb00
test_byteop3p 0, 1, 0x009b00ff, 0x2a00ff00, 0x00ff00af, 0xff00ba00
test_byteop3p 0, 2, 0x008a00ff, 0x9b00ff00, 0x00ff009e, 0xff00af00
test_byteop3p 0, 3, 0x007f00ff, 0x8a00ff00, 0x00ff008d, 0xff009e00
test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x008e007a, 0x9f008b00
test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x007d006f, 0x8e007a00
test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x006c005e, 0x7d006f00
test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x005b004d, 0x6c005e00
test_byteop3p 2, 0, 0x005a004c, 0x6b005d00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 1, 0x00cb003b, 0x5a004c00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 2, 0x00ba002a, 0xcb003b00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 3, 0x00af009b, 0xba002a00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 0, 0x001a00ff, 0x2b00ff00, 0x00ff00aa, 0xff00bb00
test_byteop3p 3, 1, 0x008b00ff, 0x1a00ff00, 0x00ff009f, 0xff00aa00
test_byteop3p 3, 2, 0x007a00ff, 0x8b00ff00, 0x00ff008e, 0xff009f00
test_byteop3p 3, 3, 0x006f00ff, 0x7a00ff00, 0x00ff007d, 0xff008e00
pass
|
stsp/binutils-ia16
| 4,081
|
sim/testsuite/bfin/c_cc2stat_cc_aq.s
|
//Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp
// Spec Reference: cc2stat cc aq
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AQ 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
CC = AQ; //
R0 = CC; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
CC = AQ; //
R1 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
CC = AQ; //
R2 = CC; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
CC = AQ; //
R3 = CC; //
// test cc |= AQ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
CC |= AQ; //
R4 = CC; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
CC |= AQ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
CC |= AQ; //
R6 = CC; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
CC |= AQ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
// test CC &= AQ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
CC &= AQ; //
R4 = CC; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
CC &= AQ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
CC &= AQ; //
R6 = CC; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
CC &= AQ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
// test CC ^= AQ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
CC ^= AQ; //
R4 = CC; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
CC ^= AQ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
CC ^= AQ; //
R6 = CC; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
CC ^= AQ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
// test AQ = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
AQ = CC; //
R0 = ASTAT; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
AQ = CC; //
R1 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
AQ = CC; //
R2 = ASTAT; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
AQ = CC; //
R3 = ASTAT; //
// test AQ |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
AQ |= CC; //
R4 = ASTAT; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
AQ |= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
AQ |= CC; //
R6 = ASTAT; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
AQ |= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000060;
CHECKREG r3, 0x00000060;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000040;
CHECKREG r6, 0x00000060;
CHECKREG r7, 0x00000060;
// test AQ &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
AQ &= CC; //
R4 = ASTAT; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
AQ &= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
AQ &= CC; //
R6 = ASTAT; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
AQ &= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000060;
CHECKREG r3, 0x00000060;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000060;
// test AQ ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
AQ ^= CC; //
R4 = ASTAT; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
AQ ^= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
AQ ^= CC; //
R6 = ASTAT; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
AQ ^= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000060;
CHECKREG r3, 0x00000060;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000040;
CHECKREG r6, 0x00000060;
CHECKREG r7, 0x00000020;
pass
|
stsp/binutils-ia16
| 3,151
|
sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s
|
//Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp
// Spec Reference: ptr2op preg -= preg
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0xf0021003;
imm32 p2, 0x2e041005;
imm32 p3, 0x20d61007;
imm32 p4, 0x200a1009;
imm32 p5, 0x200a300b;
imm32 sp, 0x200c180d;
imm32 fp, 0x200e109f;
P1 -= P1;
P2 -= P1;
P3 -= P1;
P4 -= P1;
P5 -= P1;
SP -= P1;
FP -= P1;
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x2E041005;
CHECKREG p3, 0x20D61007;
CHECKREG p4, 0x200A1009;
CHECKREG p5, 0x200A300B;
CHECKREG sp, 0x200C180D;
CHECKREG fp, 0x200E109F;
imm32 p1, 0x50021003;
imm32 p2, 0x26041005;
imm32 p3, 0x20761007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a900b;
imm32 sp, 0x200c1a0d;
imm32 fp, 0x200e10bf;
P1 -= P2;
P2 -= P2;
P3 -= P2;
P4 -= P2;
P5 -= P2;
SP -= P2;
FP -= P2;
CHECKREG p1, 0x29FDFFFE;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x20761007;
CHECKREG p4, 0x20081009;
CHECKREG p5, 0x200A900B;
CHECKREG sp, 0x200C1A0D;
CHECKREG fp, 0x200E10BF;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p3, 0x20061007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 sp, 0x200c100d;
imm32 fp, 0x200e100f;
P1 -= P3;
P2 -= P3;
P3 -= P3;
P4 -= P3;
P5 -= P3;
SP -= P3;
FP -= P3;
CHECKREG p1, 0xFFFBFFFC;
CHECKREG p2, 0xFFFDFFFE;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x20081009;
CHECKREG p5, 0x200A100B;
CHECKREG sp, 0x200C100D;
CHECKREG fp, 0x200E100F;
imm32 p1, 0xa0021003;
imm32 p2, 0x2c041005;
imm32 p3, 0x20b61007;
imm32 p4, 0x200d1009;
imm32 p5, 0x200ae00b;
imm32 sp, 0x200c110d;
imm32 fp, 0x200e104f;
P1 -= P4;
P2 -= P4;
P3 -= P4;
P4 -= P4;
P5 -= P4;
SP -= P4;
FP -= P4;
CHECKREG p1, 0x7FF4FFFA;
CHECKREG p2, 0x0BF6FFFC;
CHECKREG p3, 0x00A8FFFE;
CHECKREG p4, 0x00000000;
CHECKREG p5, 0x200AE00B;
CHECKREG sp, 0x200C110D;
CHECKREG fp, 0x200E104F;
imm32 p1, 0x10021003;
imm32 p2, 0x22041005;
imm32 p3, 0x20361007;
imm32 p4, 0x20041009;
imm32 p5, 0x200aa00b;
imm32 sp, 0x200c1b0d;
imm32 fp, 0x200e10cf;
P1 -= P5;
P2 -= P5;
P3 -= P5;
P4 -= P5;
P5 -= P5;
SP -= P5;
FP -= P5;
CHECKREG p1, 0xEFF76FF8;
CHECKREG p2, 0x01F96FFA;
CHECKREG p3, 0x002B6FFC;
CHECKREG p4, 0xFFF96FFE;
CHECKREG p5, 0x00000000;
CHECKREG sp, 0x200C1B0D;
CHECKREG fp, 0x200E10CF;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p3, 0x20061007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 sp, 0x200c100d;
imm32 fp, 0x200e100f;
P1 -= SP;
P2 -= SP;
P3 -= SP;
P4 -= SP;
P5 -= SP;
SP -= SP;
FP -= SP;
CHECKREG p1, 0xFFF5FFF6;
CHECKREG p2, 0xFFF7FFF8;
CHECKREG p3, 0xFFF9FFFA;
CHECKREG p4, 0xFFFBFFFC;
CHECKREG p5, 0xFFFDFFFE;
CHECKREG sp, 0x00000000;
CHECKREG fp, 0x200E100F;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p3, 0x20061007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 sp, 0x200c100d;
imm32 fp, 0x200e100f;
P1 -= FP;
P2 -= FP;
P3 -= FP;
P4 -= FP;
P5 -= FP;
SP -= FP;
FP -= FP;
CHECKREG p1, 0xFFF3FFF4;
CHECKREG p2, 0xFFF5FFF6;
CHECKREG p3, 0xFFF7FFF8;
CHECKREG p4, 0xFFF9FFFA;
CHECKREG p5, 0xFFFBFFFC;
CHECKREG sp, 0xFFFDFFFE;
CHECKREG fp, 0x00000000;
pass
|
stsp/binutils-ia16
| 1,412
|
sim/testsuite/bfin/cc5.S
|
// ALU test program.
// Test instructions reg = (A0+=A1)
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// add accums and transfer result
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R6 = ( A0 += A1 );
CHECKREG R6, 0x22222222;
R6 = A0.w;
CHECKREG R6, 0x22222222;
R7 = A0.x;
CHECKREG R7, 0;
R6 = A1.w;
CHECKREG R6, 0x11111111;
R7 = A1.x;
CHECKREG R7, 0;
// add accums and transfer result (saturate positive)
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R6 = ( A0 += A1 );
CHECKREG R6, 0x7fffffff;
R6 = A0.w;
CHECKREG R6, 0xfffffffe;
R7 = A0.x;
CHECKREG R7, 0;
R6 = A1.w;
CHECKREG R6, 0x7fffffff;
_DBG ASTAT;
R7 = A1.x;
_DBG ASTAT;
CHECKREG R7, 0;
R7 = ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY);
// add accums and transfer result (saturate negative)
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A0.w = R2;
A1.x = R3.L;
A0.x = R3.L;
R6 = ( A0 += A1 );
CHECKREG R6, 0x80000000;
R6 = A0.w;
CHECKREG R6, 0x00000000;
R7 = A0.x;
CHECKREG R6, 0;
R6 = A1.w;
CHECKREG R6, 0x80000000;
R7 = A1.x;
CHECKREG R7, 0xffffffff;
R7 = ASTAT;
_DBG ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN);
pass
.data
data0:
.dw 0x1111
.dw 0x1111
.dw 0xffff
.dw 0x7fff
.dw 0x0000
.dw 0x8000
.dw 0x00ff
.dw 0x0000
.dw 0x0000
.dw 0x0000
|
stsp/binutils-ia16
| 10,162
|
sim/testsuite/bfin/lmu_excpt_align.S
|
//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp
// Description: LMU data alignment exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
CHECK_INIT(p5, 0xE0000000);
// test address for DAG0
// test address for DAG1
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
// Write fault addr MMR to known state
WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6);
//nop;nop;nop;nop;nop; // in lieu of CSYNC
CSYNC;
A0 = 0;
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
RTI;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
User:
NOP;NOP;NOP;NOP;NOP;
//-------------------------------------------------------
// First do stores
//-------------------------------------------------------
// 16-bit alignment, DAG0
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X01: W [ I1 ] = R1.L; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X02: [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 2)));
LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X03: [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 3)));
LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X04: [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 16-bit alignment, DAG1
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X05: A0 = 0 || NOP || W [ I1 ] = R1.L; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X05, r0); // RETX should be value of X05 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X06: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X06, r0); // RETX should be value of X06 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 2)));
LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X07: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X07, r0); // RETX should be value of X07 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 3)));
LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X08: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X08, r0); // RETX should be value of X08 (HARDCODED ADDR!!)
//-------------------------------------------------------
// Now repeat for Loads
//-------------------------------------------------------
// 16-bit alignment, DAG0
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X11: R1.L = W [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X11, r0); // RETX should be value of X11 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X12: R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X12, r0); // RETX should be value of X12 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 2)));
LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X13: R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X13, r0); // RETX should be value of X13 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 3)));
LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X14: R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X14, r0); // RETX should be value of X14 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 16-bit alignment, DAG1
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X15: A0 = 0 || NOP || R1.L = W [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X15, r0); // RETX should be value of X15 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X16, r0); // RETX should be value of X16 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 2)));
LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X17: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X17, r0); // RETX should be value of X17 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 3)));
LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X18: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X18, r0); // RETX should be value of X18 (HARDCODED ADDR!!)
//-------------------------------------------------------
dbg_pass;
handler:
R5 = SEQSTAT; // Get exception cause
// read and check fail addr (addr_which_causes_exception)
// should not be set for alignment exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r6);
R7 = RETX; // get address of excepting instruction
// align the offending address
I1 = P2;
RTX;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
.section MEM_0x1000,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
stsp/binutils-ia16
| 6,170
|
sim/testsuite/bfin/dbg_tr_umode.S
|
//Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp
// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
// Supervisor mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfcheck.inc)
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x20
#endif
// This test embeds .text offsets, so pad our test so it lines up.
.space 0x64
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
CHECK_INIT(p5, 0x00BFFFFC);
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
LD32_LABEL(r7, DUMMY);
RETI = r7;
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
// .code 0x200
START:
WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer
WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer
// TBUFPWR = 1
// TBUFEN = 1
// TBUFOVF = 0
// CMPLP = 0
NOP;
NOP;
NOP;
NOP;
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
RTI;
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
NOP;
NOP;
NOP;
JUMP.S label1;
R4.L = 0x1111;
R4.H = 0x1111;
NOP;
NOP;
NOP;
label2: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label3;
R6.L = 0x1111;
R6.H = 0x1111;
NOP;
NOP;
NOP;
NOP;
NOP;
label1: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label2;
R5.L = 0x1111;
R5.H = 0x1111;
NOP;
NOP;
NOP;
NOP;
label3:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// Checks the contents of the Trace Buffer
EXCPT 0;
NOP; NOP; NOP; NOP;
CHECKREG(r2, 0x00000006);
CHECKREG(r1, 0x00000416);
CHECKREG(r0, 0x000002aa);
CHECKREG(r3, 0x0000029a);
CHECKREG(r4, 0x00000262);
CHECKREG(r5, 0x00000004);
CHECKREG(r6, 0x0000025a);
CHECKREG(r7, 0x00000288);
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
EXCPT 1;
NOP; NOP; NOP; NOP;
CHECKREG(r2, 0x00000005);
CHECKREG(r1, 0x00000416);
CHECKREG(r0, 0x00000304);
CHECKREG(r3, 0x000002ac);
CHECKREG(r4, 0x00000470);
CHECKREG(r5, 0x00000003);
CHECKREG(r6, 0x00000276);
CHECKREG(r7, 0x0000024a);
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
EXCPT 2;
NOP; NOP; NOP; NOP;
CHECKREG(r2, 0x00000004);
CHECKREG(r1, 0x00000416);
CHECKREG(r0, 0x0000035e);
CHECKREG(r3, 0x00000306);
CHECKREG(r4, 0x00000470);
CHECKREG(r5, 0x00000002);
CHECKREG(r6, 0x00000244);
CHECKREG(r7, 0x00000242);
NOP; NOP; NOP; NOP;
EXCPT 3;
NOP; NOP; NOP; NOP;
CHECKREG(r2, 0x00000003);
CHECKREG(r1, 0x00000416);
CHECKREG(r0, 0x000003b0);
CHECKREG(r3, 0x00000360);
CHECKREG(r4, 0x00000470);
CHECKREG(r5, 0x00000001);
CHECKREG(r6, 0x00000238);
CHECKREG(r7, 0x00000236);
NOP;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
R7 = SEQSTAT;
RD_MMR(TBUFSTAT, p0, r2);
RD_MMR(TBUF, p0, r1);
RD_MMR(TBUF, p0, r0);
RD_MMR(TBUF, p0, r3);
RD_MMR(TBUF, p0, r4);
RD_MMR(TBUFSTAT, p0, r5);
RD_MMR(TBUF, p0, r6);
RD_MMR(TBUF, p0, r7);
NOP; NOP; NOP; NOP;
RTX;
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 6,164
|
sim/testsuite/bfin/c_dsp32mac_pair_a1_is.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_is/c_dsp32mac_pair_a1_is.dsp
// Spec Reference: dsp32mac pair a1 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
imm32 r3, 0x00890007;
imm32 r4, 0xefb89569;
imm32 r5, 0x1235890b;
imm32 r6, 0x000c089d;
imm32 r7, 0x678e0089;
R7 = ( A1 += R5.L * R0.L ), A0 = R5.L * R0.L (ISS2);
P1 = A1.w;
R1 = ( A1 = R4.L * R3.L ), A0 = R4.H * R3.L (ISS2);
P2 = A1.w;
R3 = ( A1 = R7.L * R2.L ), A0 += R7.H * R2.H (ISS2);
P3 = A1.w;
R5 = ( A1 += R6.L * R1.L ), A0 += R6.L * R1.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x93545ABD;
CHECKREG r1, 0xFFFA2BBE;
CHECKREG r2, 0xA8945679;
CHECKREG r3, 0x0F06AE9C;
CHECKREG r4, 0xEFB89569;
CHECKREG r5, 0x11F835A8;
CHECKREG r6, 0x000C089D;
CHECKREG r7, 0xABAC163E;
CHECKREG p1, 0xD5D60B1F;
CHECKREG p2, 0xFFFD15DF;
CHECKREG p3, 0x0783574E;
CHECKREG p4, 0x08FC1AD4;
imm32 r0, 0x98464abd;
imm32 r1, 0xa1b5f4c7;
imm32 r2, 0xa1146649;
imm32 r3, 0x00010805;
imm32 r4, 0xefbc1599;
imm32 r5, 0x12350100;
imm32 r6, 0x200c001d;
imm32 r7, 0x628e0001;
R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (ISS2);
P1 = A1.w;
R1 = ( A1 -= R5.L * R3.H ), A0 = R5.H * R3.L (ISS2);
P2 = A1.w;
R3 = ( A1 -= R4.L * R2.H ), A0 += R4.H * R2.H (ISS2);
P3 = A1.w;
R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x98464ABD;
CHECKREG r1, 0x2B2A1FC8;
CHECKREG r2, 0xA1146649;
CHECKREG r3, 0x2B13CB9C;
CHECKREG r4, 0xEFBC1599;
CHECKREG r5, 0x1B10627C;
CHECKREG r6, 0x200C001D;
CHECKREG r7, 0x628E0001;
CHECKREG p1, 0x0D88313E;
CHECKREG p2, 0x0D87CEC2;
CHECKREG p3, 0x1589E5CE;
CHECKREG p4, 0x15950FE4;
imm32 r0, 0x713a459d;
imm32 r1, 0xabd6aec7;
imm32 r2, 0x7a145a79;
imm32 r3, 0x08a100a7;
imm32 r4, 0xef9a156a;
imm32 r5, 0x1225a10b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0a61;
R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (ISS2);
P1 = A1.w;
R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L (ISS2);
P2 = A1.w;
R1 = ( A1 = R7.H * R5.L ), A0 += R7.H * R5.H (ISS2);
P3 = A1.w;
R5 = ( A1 += R6.H * R4.L ), A0 += R6.L * R4.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x713A459D;
CHECKREG r1, 0xFE604820;
CHECKREG r2, 0x7A145A79;
CHECKREG r3, 0x08A100A7;
CHECKREG r4, 0xEF9A156A;
CHECKREG r5, 0xFE60C89C;
CHECKREG r6, 0x0003401D;
CHECKREG r7, 0xFCC4FA2C;
CHECKREG p1, 0xFEB22022;
CHECKREG p2, 0xFE627D16;
CHECKREG p3, 0xFF302410;
CHECKREG p4, 0xFF30644E;
imm32 r0, 0x773489bd;
imm32 r1, 0x917cfec7;
imm32 r2, 0xa9177679;
imm32 r3, 0xd0910777;
imm32 r4, 0xedb91579;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d077999;
imm32 r7, 0x677e0709;
R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (ISS2);
P1 = A1.w;
R3 = ( A1 = R2.H * R1.H ), A0 = R2.H * R1.L (ISS2);
P2 = A1.w;
R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (ISS2);
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x773489BD;
CHECKREG r1, 0x0F5908A6;
CHECKREG r2, 0xA9177679;
CHECKREG r3, 0xF59443FE;
CHECKREG r4, 0xEDB91579;
CHECKREG r5, 0x953314CE;
CHECKREG r6, 0x0D077999;
CHECKREG r7, 0x9356DEEC;
CHECKREG p1, 0x07AC8453;
CHECKREG p2, 0xFACA21FF;
CHECKREG p3, 0xCA998A67;
CHECKREG p4, 0xC9AB6F76;
imm32 r0, 0x83547abd;
imm32 r1, 0x88bc8ec7;
imm32 r2, 0xa8895679;
imm32 r3, 0x00080007;
imm32 r4, 0xe6b86569;
imm32 r5, 0x1A35860b;
imm32 r6, 0x000c896d;
imm32 r7, 0x67Be0096;
R7 = ( A1 += R1.L * R0.L ) (ISS2);
P1 = A1.w;
R1 = ( A1 = R2.H * R3.L ) (ISS2);
P2 = A1.w;
R3 = ( A1 -= R7.L * R4.H ) (ISS2);
P3 = A1.w;
R5 = ( A1 += R6.H * R5.H ) (ISS2);
P4 = A1.w;
CHECKREG r0, 0x83547ABD;
CHECKREG r1, 0xFFFB377E;
CHECKREG r2, 0xA8895679;
CHECKREG r3, 0xFFFB377E;
CHECKREG r4, 0xE6B86569;
CHECKREG r5, 0xFFFDAC76;
CHECKREG r6, 0x000C896D;
CHECKREG r7, 0x80000000;
CHECKREG p1, 0x9362AE61;
CHECKREG p2, 0xFFFD9BBF;
CHECKREG p3, 0xFFFD9BBF;
CHECKREG p4, 0xFFFED63B;
imm32 r0, 0x9aa64abd;
imm32 r1, 0xa1baf4c7;
imm32 r2, 0xb114a649;
imm32 r3, 0x0b010005;
imm32 r4, 0xefbcdb69;
imm32 r5, 0x123501bb;
imm32 r6, 0x000c0d1b;
imm32 r7, 0x678e0d01;
R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (ISS2);
P1 = A1.w;
R1 = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (ISS2);
P2 = A1.w;
R3 = ( A1 = R4.L * R5.H ) (M), A0 += R4.H * R5.H (ISS2);
P3 = A1.w;
R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x9AA64ABD;
CHECKREG r1, 0xC54D5630;
CHECKREG r2, 0xB114A649;
CHECKREG r3, 0xBAB3123C;
CHECKREG r4, 0xEFBCDB69;
CHECKREG r5, 0xF26E8A8A;
CHECKREG r6, 0x000C0D1B;
CHECKREG r7, 0x678E0D01;
CHECKREG p1, 0xF9374545;
CHECKREG p2, 0xFD127BFC;
CHECKREG p3, 0xDD59891E;
CHECKREG p4, 0xE2A6AB18;
imm32 r0, 0xd136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0xdd010007;
imm32 r4, 0xeddc1569;
imm32 r5, 0x122d010b;
imm32 r6, 0x00e3d01d;
imm32 r7, 0x678e0d61;
R5 = A1 , A0 -= R1.L * R0.L (ISS2);
P1 = A1.w;
R7 = A1 , A0 = R2.H * R3.L (ISS2);
P2 = A1.w;
R1 = A1 , A0 += R4.H * R5.H (ISS2);
P3 = A1.w;
R5 = A1 , A0 += R6.L * R7.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0xD136459D;
CHECKREG r1, 0xC54D5630;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0xDD010007;
CHECKREG r4, 0xEDDC1569;
CHECKREG r5, 0xC54D5630;
CHECKREG r6, 0x00E3D01D;
CHECKREG r7, 0xC54D5630;
CHECKREG p1, 0xE2A6AB18;
CHECKREG p2, 0xE2A6AB18;
CHECKREG p3, 0xE2A6AB18;
CHECKREG p4, 0xE2A6AB18;
imm32 r0, 0x125489bd;
imm32 r1, 0x91b5fec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910507;
imm32 r4, 0x34567859;
imm32 r5, 0xd2359105;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ) (M,ISS2);
P1 = A1.w;
R3 = ( A1 = R2.H * R1.H ) (M,ISS2);
P2 = A1.w;
R5 = ( A1 -= R7.H * R0.H ) (M,ISS2);
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ) (M,ISS2);
P4 = A1.w;
CHECKREG r0, 0x125489BD;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0xA9145679;
CHECKREG r3, 0xA9140000;
CHECKREG r4, 0x34567859;
CHECKREG r5, 0x9A349E50;
CHECKREG r6, 0x0D0C0999;
CHECKREG r7, 0x9F8A4260;
CHECKREG p1, 0xBD57CB1D;
CHECKREG p2, 0xD48A0000;
CHECKREG p3, 0xCD1A4F28;
CHECKREG p4, 0xCFC52130;
pass
|
stsp/binutils-ia16
| 1,638
|
sim/testsuite/bfin/random_0012.S
|
# test VIT_MAX behavior when high Acc bits are set
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0xd81562e8;
dmm32 A0.x, 0xffffffff;
imm32 R4, 0x15c2d815;
imm32 R5, 0xc9bd3a6b;
R4.L = VIT_MAX (R5) (ASR);
checkreg R4, 0x15c23a6b;
checkreg A0.w, 0x6c0ab174;
checkreg A0.x, 0x0000007f;
checkreg ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x715cf6e6;
dmm32 A0.x, 0xffffffb6;
imm32 R3, 0x3a89c7ed;
imm32 R4, 0x4819bbf9;
R3.L = VIT_MAX (R4) (ASR);
checkreg R3, 0x3a89bbf9;
checkreg A0.w, 0x38ae7b73;
checkreg A0.x, 0x0000005b;
checkreg ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 A0.w, 0xea06f130;
dmm32 A0.x, 0xffffffff;
imm32 R2, 0x62ce98f1;
imm32 R5, 0x045415f9;
R2.L = VIT_MAX (R5) (ASR);
checkreg R2, 0x62ce15f9;
checkreg A0.w, 0x75037898;
checkreg A0.x, 0x0000007f;
checkreg ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0xffffffff;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0xc9647fff;
imm32 R6, 0x1d4baeb8;
R6.L = VIT_MAX (R0) (ASR);
checkreg R6, 0x1d4bc964;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0x0000007f;
checkreg ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN);
pass
|
stsp/binutils-ia16
| 7,450
|
sim/testsuite/bfin/c_dsp32mac_pair_a1a0_i.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_i/c_dsp32mac_pair_a1a0_i.dsp
// Spec Reference: dsp32mac pair a1a0 I
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (IS);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (IS);
FP = A1.w;
CHECKREG r0, 0xFFFD9ABC;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0x0004A9F4;
CHECKREG r3, 0x05E8D563;
CHECKREG r4, 0x0114469B;
CHECKREG r5, 0xFECD7B7C;
CHECKREG r6, 0xFF910EEB;
CHECKREG r7, 0xFF910EEB;
CHECKREG p1, 0xFF910EEB;
CHECKREG p2, 0xFF910EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0xFFFD9ABC;
CHECKREG p5, 0x05E8D563;
CHECKREG sp, 0x0004A9F4;
CHECKREG fp, 0xFECD7B7C;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L ) (IS);
P2 = A0.w;
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (IS);
P5 = A1.w;
SP = A0.w;
R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (IS);
FP = A0.w;
CHECKREG r0, 0xFCBBE07C;
CHECKREG r1, 0xFF409C82;
CHECKREG r2, 0xFCB02566;
CHECKREG r3, 0xFF34E16C;
CHECKREG r4, 0xFCB93CEB;
CHECKREG r5, 0x03577736;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x03577736;
CHECKREG p2, 0xFCBB1787;
CHECKREG p3, 0x00005649;
CHECKREG p4, 0xFCBB1787;
CHECKREG p5, 0xFF34E16C;
CHECKREG sp, 0xFCB02566;
CHECKREG fp, 0xFCBBE07C;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R7 = ( A1 = R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 -= R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (IS);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H ) (IS);
FP = A0.w;
CHECKREG r0, 0x0273FCDC;
CHECKREG r1, 0xF76A2B8C;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x02744380;
CHECKREG r5, 0xF76A7230;
CHECKREG r6, 0x0003178C;
CHECKREG r7, 0x0003178C;
CHECKREG p1, 0xE85DACC0;
CHECKREG p2, 0xE590030B;
CHECKREG p3, 0x0003178C;
CHECKREG p5, 0xF76A2B8C;
CHECKREG p4, 0x0003178C;
CHECKREG sp, 0x0273FCDC;
CHECKREG fp, 0x02744380;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 -= R2.H * R1.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (IS);
P5 = A1.w;
SP = A0.w;
R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (IS);
FP = A0.w;
CHECKREG r0, 0xFFFCF74D;
CHECKREG r1, 0xFFE69235;
CHECKREG r2, 0xDAB58E29;
CHECKREG r3, 0x0008D3F8;
CHECKREG r4, 0xDAB3EEB1;
CHECKREG r5, 0xFFFE6088;
CHECKREG r6, 0xD9D21BFD;
CHECKREG r7, 0xFE17B7EC;
CHECKREG p1, 0xFFE69235;
CHECKREG p2, 0xFFFCF74D;
CHECKREG p3, 0x0008D3F8;
CHECKREG p4, 0xDAB58E29;
CHECKREG p5, 0xFFFE6088;
CHECKREG sp, 0xDAB3EEB1;
CHECKREG fp, 0xD9D21BFD;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 -= R7.H * R4.H ) (IS);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (IS);
FP = A0.w;
CHECKREG r0, 0xFFFD9ABC;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0xFFD771FC;
CHECKREG r3, 0x16A6FC20;
CHECKREG r4, 0x00E70EA3;
CHECKREG r5, 0x1E76A239;
CHECKREG r6, 0xFF910EEB;
CHECKREG r7, 0xFDA8C6D7;
CHECKREG p1, 0xFDA8C6D7;
CHECKREG p2, 0xFF910EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0xFFFD9ABC;
CHECKREG p5, 0x16A6FC20;
CHECKREG sp, 0xFFD771FC;
CHECKREG fp, 0x00E70EA3;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = A1, R4 = ( A0 = R1.L * R0.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R1 = A1, R0 = ( A0 = R2.H * R3.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R3 = A1, R2 = ( A0 -= R4.H * R5.H ) (IS);
P5 = A1.w;
SP = A0.w;
R1 = A1, R0 = ( A0 += R6.L * R7.H ) (IS);
FP = A1.w;
CHECKREG r0, 0x006DB534;
CHECKREG r1, 0x1E76A239;
CHECKREG r2, 0x0061FA1E;
CHECKREG r3, 0x1E76A239;
CHECKREG r4, 0xFCB93CEB;
CHECKREG r5, 0x1E76A239;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x1E76A239;
CHECKREG p2, 0xFCB93CEB;
CHECKREG p3, 0x1E76A239;
CHECKREG p4, 0xFFFE2564;
CHECKREG p5, 0x1E76A239;
CHECKREG sp, 0x0061FA1E;
CHECKREG fp, 0x1E76A239;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R7 = A1, R6 = ( A0 = R2.H * R3.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (IS);
P5 = A1.w;
SP = A0.w;
R5 = A1, R4 = ( A0 -= R6.L * R7.H ) (IS);
FP = A1.w;
CHECKREG r0, 0xFF3AD93C;
CHECKREG r1, 0xED91D5F0;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0xFE887FD8;
CHECKREG r5, 0xED91D5F0;
CHECKREG r6, 0x0003178C;
CHECKREG r7, 0x0793B277;
CHECKREG p1, 0x0793B277;
CHECKREG p2, 0xE590030B;
CHECKREG p3, 0x0793B277;
CHECKREG p4, 0x0003178C;
CHECKREG p5, 0xED91D5F0;
CHECKREG sp, 0xFF3AD93C;
CHECKREG fp, 0xED91D5F0;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = A1, R0 = ( A0 = R5.L * R3.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS);
P5 = A0.w;
SP = A1.w;
R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS);
FP = A0.w;
CHECKREG r0, 0xFFFCF74D;
CHECKREG r1, 0xED91D5F0;
CHECKREG r2, 0x0E4826C0;
CHECKREG r3, 0xAF564854;
CHECKREG r4, 0x0E468748;
CHECKREG r5, 0x67DC6088;
CHECKREG r6, 0x081F86A8;
CHECKREG r7, 0x67DC6088;
CHECKREG p1, 0xED91D5F0;
CHECKREG p2, 0xFFFCF74D;
CHECKREG p3, 0xAF564854;
CHECKREG p4, 0x0E4826C0;
CHECKREG p5, 0x0E468748;
CHECKREG sp, 0x67DC6088;
CHECKREG fp, 0x081F86A8;
pass
|
stsp/binutils-ia16
| 2,891
|
sim/testsuite/bfin/c_loopsetup_nested_bot.s
|
//Original:/testcases/core/c_loopsetup_nested_bot/c_loopsetup_nested_bot.dsp
// Spec Reference: loopsetup nested same bottom
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 2;
P2 = 4;
P3 = 6;
P4 = 8;
P5 = 10;
SP = 12;
FP = 14;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x32;
R4 = 0x46 (X);
R5 = 0x50 (X);
R6 = 0x68 (X);
R7 = 0x72 (X);
LSETUP ( start1 , end1 ) LC0 = P1;
start1: R0 += 1;
R1 += -2;
LSETUP ( start2 , end2 ) LC1 = P2;
start2: R4 += 4;
end2: R5 += -5;
R3 += 1;
end1: R2 += 3;
R3 += 4;
LSETUP ( start3 , end3 ) LC1 = P3;
start3: R6 += 6;
LSETUP ( start4 , end3 ) LC0 = P4 >> 1;
start4: R0 += 1;
R1 += -2;
end4: R2 += 3;
R3 += 4;
end3: R7 += -7;
R3 += 1;
CHECKREG r0, 0x00000010;
CHECKREG r1, 0xFFFFFFFA;
CHECKREG r2, 0x00000041;
CHECKREG r3, 0x0000005D;
CHECKREG r4, 0x00000066;
CHECKREG r5, 0x00000028;
CHECKREG r6, 0x0000008C;
CHECKREG r7, 0x00000033;
R0 = 0x05;
R1 = 0x10;
R2 = 0x14;
R3 = 0x18;
R4 = 0x20;
R5 = 0x12;
R6 = 0x24;
R7 = 0x16;
LSETUP ( start5 , end5 ) LC0 = P5;
start5: R4 += 1;
LSETUP ( start6 , end5 ) LC1 = SP >> 1;
start6: R6 += 4;
end6: R7 += -5;
R3 += 6;
end5: R5 += -2;
R3 += 3;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000014;
CHECKREG r3, 0x00000183;
CHECKREG r4, 0x0000002A;
CHECKREG r5, 0xFFFFFF9A;
CHECKREG r6, 0x00000114;
CHECKREG r7, 0xFFFFFEEA;
LSETUP ( start7 , end7 ) LC0 = FP;
start7: R4 += 4;
end7: R5 += -5;
R3 += 6;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000014;
CHECKREG r3, 0x00000189;
CHECKREG r4, 0x00000062;
CHECKREG r5, 0xFFFFFF54;
CHECKREG r6, 0x00000114;
CHECKREG r7, 0xFFFFFEEA;
P1 = 04;
P2 = 08;
P3 = 10;
P4 = 12;
P5 = 14;
SP = 16;
FP = 18;
R0 = 0x05;
R1 = 0x10;
R2 = 0x12;
R3 = 0x20;
R4 = 0x18;
R5 = 0x14;
R6 = 0x16;
R7 = 0x28;
LSETUP ( start11 , end11 ) LC0 = P5;
start11: R0 += 1;
R1 += -1;
LSETUP ( start15 , end15 ) LC1 = P1;
start15: R4 += 1;
end15: R5 += -1;
R3 += 1;
end11: R2 += 1;
R3 += 1;
LSETUP ( start13 , end12 ) LC0 = P2;
start13: R6 += 1;
LSETUP ( start12 , end12 ) LC1 = P3;
start12: R4 += 1;
end12: R5 += -1;
R3 += 1;
end13: R7 += -1;
R3 += 1;
CHECKREG r0, 0x00000013;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000031;
CHECKREG r4, 0x0000005A;
CHECKREG r5, 0xFFFFFFD2;
CHECKREG r6, 0x00000017;
CHECKREG r7, 0x00000027;
R0 = 0x05;
R1 = 0x08;
R2 = 0x12;
R3 = 0x24;
R4 = 0x18;
R5 = 0x20;
R6 = 0x32;
R7 = 0x46 (X);
LSETUP ( start14 , end14 ) LC0 = P4;
start14: R0 += 1;
R1 += -1;
LSETUP ( start16 , end16 ) LC1 = SP;
start16: R6 += 1;
end16: R7 += -1;
R3 += 1;
LSETUP ( start17 , end14 ) LC1 = FP >> 1;
start17: R4 += 1;
end17: R5 += -1;
R3 += 1;
end14: R2 += 1;
R3 += 1;
CHECKREG r0, 0x00000011;
CHECKREG r1, 0xFFFFFFFC;
CHECKREG r2, 0x0000007E;
CHECKREG r3, 0x0000009D;
CHECKREG r4, 0x00000084;
CHECKREG r5, 0xFFFFFFB4;
CHECKREG r6, 0x000000F2;
CHECKREG r7, 0xFFFFFF86;
pass
|
stsp/binutils-ia16
| 1,999
|
sim/testsuite/bfin/c_regmv_dag_lz_dep.s
|
//Original:/testcases/core/c_regmv_dag_lz_dep/c_regmv_dag_lz_dep.dsp
// Spec Reference: regmv dag lz dep forward
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x11111111;
imm32 r1, 0x22223331;
imm32 r2, 0x44445551;
imm32 r3, 0x66667771;
imm32 r4, 0x88889991;
imm32 r5, 0xaaaabbb1;
imm32 r6, 0xccccddd1;
imm32 r7, 0xeeeefff1;
I0 = R0;
I0 = 0x1122 (Z);
R0 = I0;
I1 = R1;
I1 = 0x3344 (Z);
R1 = I1;
I2 = R2;
I2 = 0x5566 (Z);
R2 = I2;
I3 = R3;
I3 = 0x7788 (Z);
R3 = I3;
B0 = R4;
B0 = 0x99aa (Z);
R4 = B0;
B1 = R5;
B1 = 0xbbcc (Z);
R5 = B1;
B2 = R6;
B2 = 0xddee (Z);
R6 = B2;
B3 = R7;
B3 = 0xff01 (Z);
R7 = B3;
CHECKREG r0, 0x00001122;
CHECKREG r1, 0x00003344;
CHECKREG r2, 0x00005566;
CHECKREG r3, 0x00007788;
CHECKREG r4, 0x000099AA;
CHECKREG r5, 0x0000BBCC;
CHECKREG r6, 0x0000DDEE;
CHECKREG r7, 0x0000FF01;
imm32 r0, 0x11111112;
imm32 r1, 0x22223332;
imm32 r2, 0x44445552;
imm32 r3, 0x66667772;
imm32 r4, 0x88889992;
imm32 r5, 0xaaaabbb2;
imm32 r6, 0xccccddd2;
imm32 r7, 0xeeeefff2;
M0 = R0;
M0 = 0xa1a2 (Z);
R0 = M0;
M1 = R1;
M1 = 0xb1b2 (Z);
R1 = M1;
M2 = R2;
M2 = 0xc1c2 (Z);
R2 = M2;
M3 = R3;
M3 = 0xd1d2 (Z);
R3 = M3;
L0 = R4;
L0 = 0xe1e2 (Z);
R4 = L0;
L1 = R5;
L1 = 0xf1f2 (Z);
R5 = L1;
L2 = R6;
L2 = 0x1112 (Z);
R6 = L2;
L3 = R7;
L3 = 0x2122 (Z);
R7 = L3;
CHECKREG r0, 0x0000A1A2;
CHECKREG r1, 0x0000B1B2;
CHECKREG r2, 0x0000C1C2;
CHECKREG r3, 0x0000D1D2;
CHECKREG r4, 0x0000E1E2;
CHECKREG r5, 0x0000F1F2;
CHECKREG r6, 0x00001112;
CHECKREG r7, 0x00002122;
imm32 r0, 0x11111113;
imm32 r1, 0x22223333;
imm32 r2, 0x44445553;
imm32 r3, 0x66667773;
imm32 r4, 0x88889993;
imm32 r5, 0xaaaabbb3;
imm32 r6, 0xccccddd3;
imm32 r7, 0xeeeefff3;
P1 = R1;
P1 = 0x3A3B (Z);
R1 = P1;
P2 = R2;
P2 = 0x4A4B (Z);
R2 = P2;
P3 = R3;
P3 = 0x5A5B (Z);
R3 = P3;
P4 = R4;
P4 = 0x6A6B (Z);
R4 = P4;
P5 = R5;
P5 = 0x7A7B (Z);
R5 = P5;
CHECKREG r1, 0x00003A3B;
CHECKREG r2, 0x00004A4B;
CHECKREG r3, 0x00005A5B;
CHECKREG r4, 0x00006A6B;
CHECKREG r5, 0x00007A7B;
pass
|
stsp/binutils-ia16
| 2,571
|
sim/testsuite/bfin/c_dsp32shift_vmax.s
|
//Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp
// Spec Reference: dsp32shift vmax
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x11001001;
imm32 r1, 0x11001001;
imm32 r2, 0x12345678;
imm32 r3, 0x11001003;
imm32 r4, 0x11001004;
imm32 r5, 0x11001005;
imm32 r6, 0x11001006;
imm32 r7, 0x11001007;
A0 = R2;
R0.L = VIT_MAX( R0 ) (ASL);
R1.L = VIT_MAX( R1 ) (ASL);
R2.L = VIT_MAX( R2 ) (ASL);
R3.L = VIT_MAX( R3 ) (ASL);
R4.L = VIT_MAX( R4 ) (ASL);
R5.L = VIT_MAX( R5 ) (ASL);
R6.L = VIT_MAX( R6 ) (ASL);
R7.L = VIT_MAX( R7 ) (ASL);
CHECKREG r0, 0x11001100;
CHECKREG r1, 0x11001100;
CHECKREG r2, 0x12345678;
CHECKREG r3, 0x11001100;
CHECKREG r4, 0x11001100;
CHECKREG r5, 0x11001100;
CHECKREG r6, 0x11001100;
CHECKREG r7, 0x11001100;
imm32 r0, 0xa1001001;
imm32 r1, 0x1b001001;
imm32 r2, 0x11c01002;
imm32 r3, 0x110d1003;
imm32 r4, 0x1100e004;
imm32 r5, 0x11001f05;
imm32 r6, 0x11001006;
imm32 r7, 0x11001001;
R1.L = VIT_MAX( R0 ) (ASL);
R2.L = VIT_MAX( R1 ) (ASL);
R3.L = VIT_MAX( R2 ) (ASL);
R4.L = VIT_MAX( R3 ) (ASL);
R5.L = VIT_MAX( R4 ) (ASL);
R6.L = VIT_MAX( R5 ) (ASL);
R7.L = VIT_MAX( R6 ) (ASL);
R0.L = VIT_MAX( R7 ) (ASL);
CHECKREG r0, 0xA1001B00;
CHECKREG r1, 0x1B001001;
CHECKREG r2, 0x11C01B00;
CHECKREG r3, 0x110D1B00;
CHECKREG r4, 0x11001B00;
CHECKREG r5, 0x11001B00;
CHECKREG r6, 0x11001B00;
CHECKREG r7, 0x11001B00;
imm32 r0, 0x20000000;
imm32 r1, 0x4300c001;
imm32 r2, 0x4040c002;
imm32 r3, 0x40056003;
imm32 r4, 0x4000c704;
imm32 r5, 0x4000c085;
imm32 r6, 0x4000c096;
imm32 r7, 0x4000c000;
R0.L = VIT_MAX( R0 ) (ASR);
R1.L = VIT_MAX( R1 ) (ASR);
R2.L = VIT_MAX( R2 ) (ASR);
R3.L = VIT_MAX( R3 ) (ASR);
R4.L = VIT_MAX( R4 ) (ASR);
R5.L = VIT_MAX( R5 ) (ASR);
R6.L = VIT_MAX( R6 ) (ASR);
R7.L = VIT_MAX( R7 ) (ASR);
CHECKREG r0, 0x20002000;
CHECKREG r1, 0x4300C001;
CHECKREG r2, 0x4040C002;
CHECKREG r3, 0x40056003;
CHECKREG r4, 0x40004000;
CHECKREG r5, 0x40004000;
CHECKREG r6, 0x40004000;
CHECKREG r7, 0x4000C000;
imm32 r0, 0x10000000;
imm32 r1, 0x4200c001;
imm32 r2, 0x4030c002;
imm32 r3, 0x4004c003;
imm32 r4, 0x40005004;
imm32 r5, 0x4000c605;
imm32 r6, 0x4000c076;
imm32 r7, 0x4000c008;
R2.L = VIT_MAX( R0 ) (ASR);
R3.L = VIT_MAX( R1 ) (ASR);
R4.L = VIT_MAX( R2 ) (ASR);
R5.L = VIT_MAX( R3 ) (ASR);
R6.L = VIT_MAX( R4 ) (ASR);
R7.L = VIT_MAX( R5 ) (ASR);
R0.L = VIT_MAX( R6 ) (ASR);
R1.L = VIT_MAX( R7 ) (ASR);
CHECKREG r0, 0x10004030;
CHECKREG r1, 0x42004000;
CHECKREG r2, 0x40301000;
CHECKREG r3, 0x4004C001;
CHECKREG r4, 0x40004030;
CHECKREG r5, 0x4000C001;
CHECKREG r6, 0x40004030;
CHECKREG r7, 0x40004000;
pass
|
stsp/binutils-ia16
| 1,347
|
sim/testsuite/bfin/c_dsp32alu_saa.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_saa/c_dsp32alu_saa.dsp
// Spec Reference: dsp32alu saa
# mach: bfin
.include "testutils.inc"
start
A1 = 0;
A0 = 0;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
A0 = 0;
A1 = 0;
SAA ( R1:0 , R3:2 );
R4 = A0.w;
R5 = A1.w;
CHECKREG r4, 0x00340004;
CHECKREG r5, 0x001F0023;
SAA ( R3:2 , R1:0 );
R6 = A0.w;
R7 = A1.w;
CHECKREG r6, 0x00680008;
CHECKREG r7, 0x003E0046;
imm32 r0, 0x1567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445525;
imm32 r3, 0x46667727;
imm32 r4, 0x00340004;
imm32 r5, 0x001F0023;
imm32 r6, 0x00680008;
imm32 r7, 0x003E0046;
SAA ( R1:0 , R3:2 );
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x009C000E;
CHECKREG r1, 0x005D0069;
SAA ( R3:2 , R1:0 );
R2 = A0.w;
R3 = A1.w;
CHECKREG r2, 0x00F10025;
CHECKREG r3, 0x009100C1;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0xaeaa4bbb;
imm32 r6, 0xcfccd44d;
imm32 r7, 0xe1eefff4;
SAA ( R3:2 , R1:0 ) (R);
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x0125007B;
CHECKREG r1, 0x009900E6;
SAA ( R1:0 , R3:2 ) (R);
R6 = A0.w;
R7 = A1.w;
CHECKREG r6, 0x019C00EA;
CHECKREG r7, 0x0105011B;
pass
|
stsp/binutils-ia16
| 13,148
|
sim/testsuite/bfin/c_ldst_ld_d_p_ppmm_hbx.s
|
//Original:/testcases/core/c_ldst_ld_d_p_ppmm_hbx/c_ldst_ld_d_p_ppmm_hbx.dsp
// Spec Reference: c_ldst ld d [p++/--] h b xh xb
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = W [ P5 ++ ] (Z);
R1 = W [ P1 ++ ] (Z);
R2 = W [ P2 ++ ] (Z);
R4 = W [ P4 ++ ] (Z);
R5 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
CHECKREG r4, 0x00008283;
CHECKREG r5, 0x00000203;
R1 = W [ P5 ++ ] (Z);
R2 = W [ P1 ++ ] (Z);
R3 = W [ P2 ++ ] (Z);
R5 = W [ P4 ++ ] (Z);
R6 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00002021;
CHECKREG r3, 0x00004041;
CHECKREG r5, 0x00008081;
CHECKREG r6, 0x00000001;
R2 = W [ P5 ++ ] (Z);
R3 = W [ P1 ++ ] (Z);
R4 = W [ P2 ++ ] (Z);
R6 = W [ P4 ++ ] (Z);
R7 = W [ FP ++ ] (Z);
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00002627;
CHECKREG r4, 0x00004647;
CHECKREG r6, 0x00008687;
CHECKREG r7, 0x00000607;
R3 = W [ P5 ++ ] (Z);
R4 = W [ P1 ++ ] (Z);
R5 = W [ P2 ++ ] (Z);
R7 = W [ P4 ++ ] (Z);
R0 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000405;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00000405;
CHECKREG r4, 0x00002425;
CHECKREG r5, 0x00004445;
CHECKREG r7, 0x00008485;
R4 = W [ P5 ++ ] (X);
R5 = W [ P1 ++ ] (X);
R6 = W [ P2 ++ ] (X);
R0 = W [ P4 ++ ] (X);
R1 = W [ FP ++ ] (X);
CHECKREG r0, 0xFFFF8A8B;
CHECKREG r1, 0x00000A0B;
CHECKREG r3, 0x00000405;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00002A2B;
CHECKREG r6, 0x00004A4B;
R5 = W [ P5 ++ ] (X);
R6 = W [ P1 ++ ] (X);
R7 = W [ P2 ++ ] (X);
R1 = W [ P4 ++ ] (X);
R2 = W [ FP ++ ] (X);
CHECKREG r1, 0xFFFF8889;
CHECKREG r2, 0x00000809;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00002829;
CHECKREG r7, 0x00004849;
R6 = W [ P5 ++ ] (X);
R7 = W [ P1 ++ ] (X);
R0 = W [ P2 ++ ] (X);
R2 = W [ P4 ++ ] (X);
R3 = W [ FP ++ ] (X);
CHECKREG r0, 0x00004E4F;
CHECKREG r2, 0xFFFF8E8F;
CHECKREG r3, 0x00000E0F;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00000E0F;
CHECKREG r7, 0x00002E2F;
R7 = W [ P5 ++ ] (X);
R0 = W [ P1 ++ ] (X);
R1 = W [ P2 ++ ] (X);
R3 = W [ P4 ++ ] (X);
R4 = W [ FP ++ ] (X);
CHECKREG r0, 0x00002C2D;
CHECKREG r1, 0x00004C4D;
CHECKREG r3, 0xFFFF8C8D;
CHECKREG r4, 0x00000C0D;
CHECKREG r6, 0x00000E0F;
CHECKREG r7, 0x00000C0D;
R0 = W [ P5 -- ] (Z);
R1 = W [ P1 -- ] (Z);
R2 = W [ P2 -- ] (Z);
R4 = W [ P4 -- ] (Z);
R5 = W [ FP -- ] (Z);
CHECKREG r0, 0x00001213;
CHECKREG r1, 0x00003233;
CHECKREG r2, 0x00005253;
CHECKREG r4, 0x00009293;
CHECKREG r5, 0x00001213;
R1 = W [ P5 -- ] (Z);
R2 = W [ P1 -- ] (Z);
R3 = W [ P2 -- ] (Z);
R5 = W [ P4 -- ] (Z);
R6 = W [ FP -- ] (Z);
CHECKREG r0, 0x00001213;
CHECKREG r1, 0x00000C0D;
CHECKREG r2, 0x00002C2D;
CHECKREG r3, 0x00004C4D;
CHECKREG r5, 0x00008C8D;
CHECKREG r6, 0x00000C0D;
R2 = W [ P5 -- ] (Z);
R3 = W [ P1 -- ] (Z);
R4 = W [ P2 -- ] (Z);
R6 = W [ P4 -- ] (Z);
R7 = W [ FP -- ] (Z);
CHECKREG r1, 0x00000C0D;
CHECKREG r2, 0x00000E0F;
CHECKREG r3, 0x00002E2F;
CHECKREG r4, 0x00004E4F;
CHECKREG r6, 0x00008E8F;
CHECKREG r7, 0x00000E0F;
R3 = W [ P5 -- ] (Z);
R4 = W [ P1 -- ] (Z);
R5 = W [ P2 -- ] (Z);
R7 = W [ P4 -- ] (Z);
R0 = W [ FP -- ] (Z);
CHECKREG r0, 0x00000809;
CHECKREG r2, 0x00000E0F;
CHECKREG r3, 0x00000809;
CHECKREG r4, 0x00002829;
CHECKREG r5, 0x00004849;
CHECKREG r7, 0x00008889;
R4 = W [ P5 -- ] (X);
R5 = W [ P1 -- ] (X);
R6 = W [ P2 -- ] (X);
R0 = W [ P4 -- ] (X);
R1 = W [ FP -- ] (X);
CHECKREG r0, 0xFFFF8A8B;
CHECKREG r1, 0x00000A0B;
CHECKREG r3, 0x00000809;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00002A2B;
CHECKREG r6, 0x00004A4B;
R5 = W [ P5 -- ] (X);
R6 = W [ P1 -- ] (X);
R7 = W [ P2 -- ] (X);
R1 = W [ P4 -- ] (X);
R2 = W [ FP -- ] (X);
CHECKREG r1, 0xFFFF8485;
CHECKREG r2, 0x00000405;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000405;
CHECKREG r6, 0x00002425;
CHECKREG r7, 0x00004445;
R6 = W [ P5 -- ] (X);
R7 = W [ P1 -- ] (X);
R0 = W [ P2 -- ] (X);
R2 = W [ P4 -- ] (X);
R3 = W [ FP -- ] (X);
CHECKREG r0, 0x00004647;
CHECKREG r2, 0xFFFF8687;
CHECKREG r3, 0x00000607;
CHECKREG r5, 0x00000405;
CHECKREG r6, 0x00000607;
CHECKREG r7, 0x00002627;
R7 = W [ P5 -- ] (X);
R0 = W [ P1 -- ] (X);
R1 = W [ P2 -- ] (X);
R3 = W [ P4 -- ] (X);
R4 = W [ FP -- ] (X);
CHECKREG r0, 0x00002021;
CHECKREG r1, 0x00004041;
CHECKREG r3, 0xFFFF8081;
CHECKREG r4, 0x00000001;
CHECKREG r6, 0x00000607;
CHECKREG r7, 0x00000001;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = B [ P5 ++ ] (Z);
R1 = B [ P1 ++ ] (Z);
R2 = B [ P2 ++ ] (Z);
R4 = B [ P4 ++ ] (Z);
R5 = B [ FP ++ ] (Z);
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000023;
CHECKREG r2, 0x00000043;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000003;
R1 = B [ P5 ++ ] (Z);
R2 = B [ P1 ++ ] (Z);
R3 = B [ P2 ++ ] (Z);
R5 = B [ P4 ++ ] (Z);
R6 = B [ FP ++ ] (Z);
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000042;
CHECKREG r5, 0x00000082;
CHECKREG r6, 0x00000002;
R2 = B [ P5 ++ ] (Z);
R3 = B [ P1 ++ ] (Z);
R4 = B [ P2 ++ ] (Z);
R6 = B [ P4 ++ ] (Z);
R7 = B [ FP ++ ] (Z);
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000021;
CHECKREG r4, 0x00000041;
CHECKREG r6, 0x00000081;
CHECKREG r7, 0x00000001;
R3 = B [ P5 ++ ] (Z);
R4 = B [ P1 ++ ] (Z);
R5 = B [ P2 ++ ] (Z);
R7 = B [ P4 ++ ] (Z);
R0 = B [ FP ++ ] (Z);
CHECKREG r0, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000040;
CHECKREG r7, 0x00000080;
R4 = B [ P5 ++ ] (X);
R5 = B [ P1 ++ ] (X);
R6 = B [ P2 ++ ] (X);
R0 = B [ P4 ++ ] (X);
R1 = B [ FP ++ ] (X);
CHECKREG r0, 0xFFFFFF87;
CHECKREG r1, 0x00000007;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000027;
CHECKREG r6, 0x00000047;
R5 = B [ P5 ++ ] (X);
R6 = B [ P1 ++ ] (X);
R7 = B [ P2 ++ ] (X);
R1 = B [ P4 ++ ] (X);
R2 = B [ FP ++ ] (X);
CHECKREG r1, 0xFFFFFF86;
CHECKREG r2, 0x00000006;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000026;
CHECKREG r7, 0x00000046;
R6 = B [ P5 ++ ] (X);
R7 = B [ P1 ++ ] (X);
R0 = B [ P2 ++ ] (X);
R2 = B [ P4 ++ ] (X);
R3 = B [ FP ++ ] (X);
CHECKREG r0, 0x00000045;
CHECKREG r2, 0xFFFFFF85;
CHECKREG r3, 0x00000005;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000005;
CHECKREG r7, 0x00000025;
R7 = B [ P5 ++ ] (X);
R0 = B [ P1 ++ ] (X);
R1 = B [ P2 ++ ] (X);
R3 = B [ P4 ++ ] (X);
R4 = B [ FP ++ ] (X);
CHECKREG r0, 0x00000024;
CHECKREG r1, 0x00000044;
CHECKREG r3, 0xFFFFFF84;
CHECKREG r4, 0x00000004;
CHECKREG r6, 0x00000005;
CHECKREG r7, 0x00000004;
R0 = B [ P5 -- ] (Z);
R1 = B [ P1 -- ] (Z);
R2 = B [ P2 -- ] (Z);
R4 = B [ P4 -- ] (Z);
R5 = B [ FP -- ] (Z);
CHECKREG r0, 0x0000000B;
CHECKREG r1, 0x0000002B;
CHECKREG r2, 0x0000004B;
CHECKREG r4, 0x0000008B;
CHECKREG r5, 0x0000000B;
R1 = B [ P5 -- ] (Z);
R2 = B [ P1 -- ] (Z);
R3 = B [ P2 -- ] (Z);
R5 = B [ P4 -- ] (Z);
R6 = B [ FP -- ] (Z);
CHECKREG r0, 0x0000000B;
CHECKREG r1, 0x00000004;
CHECKREG r2, 0x00000024;
CHECKREG r3, 0x00000044;
CHECKREG r5, 0x00000084;
CHECKREG r6, 0x00000004;
R2 = B [ P5 -- ] (Z);
R3 = B [ P1 -- ] (Z);
R4 = B [ P2 -- ] (Z);
R6 = B [ P4 -- ] (Z);
R7 = B [ FP -- ] (Z);
CHECKREG r1, 0x00000004;
CHECKREG r2, 0x00000005;
CHECKREG r3, 0x00000025;
CHECKREG r4, 0x00000045;
CHECKREG r6, 0x00000085;
CHECKREG r7, 0x00000005;
R3 = B [ P5 -- ] (Z);
R4 = B [ P1 -- ] (Z);
R5 = B [ P2 -- ] (Z);
R7 = B [ P4 -- ] (Z);
R0 = B [ FP -- ] (Z);
CHECKREG r0, 0x00000006;
CHECKREG r2, 0x00000005;
CHECKREG r3, 0x00000006;
CHECKREG r4, 0x00000026;
CHECKREG r5, 0x00000046;
CHECKREG r7, 0x00000086;
R4 = B [ P5 -- ] (X);
R5 = B [ P1 -- ] (X);
R6 = B [ P2 -- ] (X);
R0 = B [ P4 -- ] (X);
R1 = B [ FP -- ] (X);
CHECKREG r0, 0xFFFFFF87;
CHECKREG r1, 0x00000007;
CHECKREG r3, 0x00000006;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000027;
CHECKREG r6, 0x00000047;
R5 = B [ P5 -- ] (X);
R6 = B [ P1 -- ] (X);
R7 = B [ P2 -- ] (X);
R1 = B [ P4 -- ] (X);
R2 = B [ FP -- ] (X);
CHECKREG r1, 0xFFFFFF80;
CHECKREG r2, 0x00000000;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000040;
R6 = B [ P5 -- ] (X);
R7 = B [ P1 -- ] (X);
R0 = B [ P2 -- ] (X);
R2 = B [ P4 -- ] (X);
R3 = B [ FP -- ] (X);
CHECKREG r0, 0x00000041;
CHECKREG r2, 0xFFFFFF81;
CHECKREG r3, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000021;
R7 = B [ P5 -- ] (X);
R0 = B [ P1 -- ] (X);
R1 = B [ P2 -- ] (X);
R3 = B [ P4 -- ] (X);
R4 = B [ FP -- ] (X);
CHECKREG r0, 0x00000022;
CHECKREG r1, 0x00000042;
CHECKREG r3, 0xFFFFFF82;
CHECKREG r4, 0x00000002;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000002;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 2,927
|
sim/testsuite/bfin/c_dspldst_ld_drlo_i.s
|
//Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp
// Spec Reference: c_dspldst ld_drlo_i
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load Lower half of Dregs
R0.L = W [ I0 ];
R1.L = W [ I1 ];
R2.L = W [ I2 ];
R3.L = W [ I3 ];
R4.L = W [ I0 ];
R5.L = W [ I1 ];
R6.L = W [ I2 ];
R7.L = W [ I3 ];
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
CHECKREG r3, 0x00006263;
CHECKREG r4, 0x00000203;
CHECKREG r5, 0x00002223;
CHECKREG r6, 0x00004243;
CHECKREG r7, 0x00006263;
R1.L = W [ I0 ];
R2.L = W [ I1 ];
R3.L = W [ I2 ];
R4.L = W [ I3 ];
R5.L = W [ I0 ];
R6.L = W [ I1 ];
R7.L = W [ I2 ];
R0.L = W [ I3 ];
CHECKREG r0, 0x00006263;
CHECKREG r1, 0x00000203;
CHECKREG r2, 0x00002223;
CHECKREG r3, 0x00004243;
CHECKREG r4, 0x00006263;
CHECKREG r5, 0x00000203;
CHECKREG r6, 0x00002223;
CHECKREG r7, 0x00004243;
R2.L = W [ I0 ];
R3.L = W [ I1 ];
R4.L = W [ I2 ];
R5.L = W [ I3 ];
R6.L = W [ I0 ];
R7.L = W [ I1 ];
R0.L = W [ I2 ];
R1.L = W [ I3 ];
CHECKREG r0, 0x00004243;
CHECKREG r1, 0x00006263;
CHECKREG r2, 0x00000203;
CHECKREG r3, 0x00002223;
CHECKREG r4, 0x00004243;
CHECKREG r5, 0x00006263;
CHECKREG r6, 0x00000203;
CHECKREG r7, 0x00002223;
R3.L = W [ I0 ];
R4.L = W [ I1 ];
R5.L = W [ I2 ];
R6.L = W [ I3 ];
R7.L = W [ I0 ];
R0.L = W [ I1 ];
R1.L = W [ I2 ];
R2.L = W [ I3 ];
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0x00000203;
CHECKREG r4, 0x00002223;
CHECKREG r5, 0x00004243;
CHECKREG r6, 0x00006263;
CHECKREG r7, 0x00000203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 9,135
|
sim/testsuite/bfin/se_all16bitopcodes.S
|
/*
* Blackfin testcase for testing illegal/legal 16-bit opcodes from userspace
* we track all instructions which cause some sort of exception when run from
* userspace, this is normally EXCAUSE :
* - 0x21 : illegal instruction
* - 0x22 : illegal instruction combination
* - 0x2e : use of supervisor resource from userspace
* and walk every instruction from 0x0000 to 0xbfff
*/
# mach: bfin
# sim: --environment operating
#include "test.h"
#define SE_ALL_BITS 16
#define SE_ALL_NEW_INSN_STUB
#include "se_allopcodes.h"
.include "testutils.inc"
.macro se_all_load_insn
R2 = W[P5];
R0 = R2;
.endm
.macro se_all_next_insn
/* increment, and go again. */
R0 = R2;
R0 += 1;
/* finish once we hit the 32bit limit */
R1 = 0xC000 (Z);
CC = R1 == R0;
IF CC JUMP pass_lvl;
W[P5] = R0;
.endm
.macro se_all_new_insn_stub
jump _legal_instruction;
.endm
.macro se_all_insn_init
.dw 0x0000;
.endm
.macro se_all_insn_table
/* this table must be sorted, and end with zero */
/* start end SEQSTAT */
.dw 0x0001, 0x000f, 0x21
.dw 0x0011, 0x0013, 0x2e
.ifndef BFIN_JTAG
.dw 0x0014, 0x0014, 0x2e /* anomaly - RTX works when emulator attached */
.endif
.dw 0x0015, 0x001F, 0x21
.dw 0x0021, 0x0022, 0x21
.dw 0x0026, 0x0026, 0x21
.ifndef BFIN_JTAG
.dw 0x0027, 0x0027, 0x21 /* anomaly 492 - unknown */
.endif
.dw 0x0028, 0x002F, 0x21
.dw 0x0030, 0x0037, 0x2e
.dw 0x0038, 0x003F, 0x21
.dw 0x0040, 0x0047, 0x2e
.dw 0x0048, 0x004F, 0x21
.dw 0x0058, 0x005F, 0x21
.dw 0x0068, 0x006F, 0x21
.dw 0x0078, 0x007F, 0x21
.dw 0x0088, 0x008F, 0x21
.dw 0x0090, 0x009F, 0x2E
.dw 0x00a0, 0x00a0, 0x00
.dw 0x00a1, 0x00a1, 0x01
.dw 0x00a2, 0x00a2, 0x02
.dw 0x00a3, 0x00a3, 0x03
.dw 0x00a4, 0x00a4, 0x04
.dw 0x00a5, 0x00a5, 0x05
.dw 0x00a6, 0x00a6, 0x06
.dw 0x00a7, 0x00a7, 0x07
.dw 0x00a8, 0x00a8, 0x08
.dw 0x00a9, 0x00a9, 0x09
.dw 0x00aa, 0x00aa, 0x0a
.dw 0x00ab, 0x00ab, 0x0b
.dw 0x00ac, 0x00ac, 0x0c
.dw 0x00ad, 0x00ad, 0x0d
.dw 0x00ae, 0x00ae, 0x0e
.dw 0x00af, 0x00af, 0x0f
.dw 0x00b6, 0x010f, 0x21
.dw 0x0124, 0x0124, 0x21
.ifndef BFIN_JTAG
.dw 0x0125, 0x0125, 0x21 /* anomaly 492 res = [SP++] */
.endif
.dw 0x0128, 0x012F, 0x21
.dw 0x0138, 0x0138, 0x22
.dw 0x0139, 0x013F, 0x2E
.dw 0x0164, 0x0164, 0x21
.ifndef BFIN_JTAG
.dw 0x0165, 0x0165, 0x21 /* anomaly 492 [--SP] = res */
.endif
.dw 0x0168, 0x016F, 0x21
.dw 0x0178, 0x017F, 0x2E
.dw 0x0180, 0x01FF, 0x21
.dw 0x0210, 0x0217, 0x21
.ifndef BFIN_JTAG
.dw 0x0219, 0x021F, 0x21 /* anomaly 492 CC = !CC opcode is 0000 0010 0001 1xxx */
.endif
.dw 0x0220, 0x023F, 0x21
.dw 0x0280, 0x02FF, 0x21
.dw 0x0305, 0x0305, 0x21
.dw 0x0325, 0x0325, 0x21
.dw 0x0345, 0x0345, 0x21
.dw 0x0365, 0x0365, 0x21
.dw 0x0385, 0x0385, 0x21
.dw 0x03a5, 0x03a5, 0x21
.dw 0x03c5, 0x03c5, 0x21
.dw 0x03e5, 0x03e5, 0x21
.dw 0x0400, 0x047F, 0x21
.dw 0x0486, 0x04Bf, 0x21
.dw 0x04c6, 0x04FF, 0x21
.dw 0x0501, 0x0507, 0x21
.dw 0x0509, 0x050F, 0x21
.dw 0x0511, 0x0517, 0x21
.dw 0x0519, 0x051F, 0x21
.dw 0x0521, 0x0527, 0x21
.dw 0x0529, 0x052F, 0x21
.dw 0x0531, 0x0537, 0x21
.dw 0x0539, 0x053F, 0x21
.dw 0x0541, 0x0547, 0x21
.dw 0x0549, 0x054F, 0x21
.dw 0x0551, 0x0557, 0x21
.dw 0x0559, 0x055F, 0x21
.dw 0x0561, 0x0567, 0x21
.dw 0x0569, 0x056F, 0x21
.dw 0x0571, 0x0577, 0x21
.dw 0x0579, 0x057F, 0x21
.dw 0x0586, 0x0587, 0x21
.dw 0x058e, 0x058F, 0x21
.dw 0x0596, 0x0597, 0x21
.dw 0x059e, 0x059f, 0x21
.dw 0x05a6, 0x05a7, 0x21
.dw 0x05ae, 0x05af, 0x21
.dw 0x05b6, 0x05b7, 0x21
.dw 0x05be, 0x05bf, 0x21
.dw 0x05c6, 0x05c7, 0x21
.dw 0x05ce, 0x05cf, 0x21
.dw 0x05d6, 0x05d7, 0x21
.dw 0x05de, 0x05df, 0x21
.dw 0x05e6, 0x05e7, 0x21
.dw 0x05ee, 0x05ef, 0x21
.dw 0x05f6, 0x05f7, 0x21
.dw 0x05fe, 0x05ff, 0x21
.dw 0x0a81, 0x0aff, 0x21
.dw 0x0b01, 0x0b7f, 0x21
.dw 0x0b81, 0x0bff, 0x21
.dw 0x0e80, 0x0fff, 0x21
.dw 0x3104, 0x3105, 0x21
.dw 0x310c, 0x310d, 0x21
.dw 0x3114, 0x3115, 0x21
.dw 0x311c, 0x311d, 0x21
.dw 0x3124, 0x3125, 0x21
.dw 0x312c, 0x312d, 0x21
.dw 0x3134, 0x3135, 0x21
.dw 0x313c, 0x313d, 0x21
.dw 0x3140, 0x317F, 0x21
.dw 0x31c0, 0x31ff, 0x2E
.dw 0x3304, 0x3305, 0x21
.dw 0x330c, 0x330d, 0x21
.dw 0x3314, 0x3315, 0x21
.dw 0x331c, 0x331d, 0x21
.dw 0x3324, 0x3325, 0x21
.dw 0x332c, 0x332d, 0x21
.dw 0x3334, 0x3335, 0x21
.dw 0x333c, 0x333d, 0x21
.dw 0x3340, 0x337f, 0x21
.dw 0x33c0, 0x33ff, 0x2e
.dw 0x3504, 0x3507, 0x21
.dw 0x350c, 0x350F, 0x21
.dw 0x3514, 0x3517, 0x21
.dw 0x351c, 0x351F, 0x21
.dw 0x3524, 0x3527, 0x21
.dw 0x352c, 0x352f, 0x21
.dw 0x3534, 0x3537, 0x21
.dw 0x353c, 0x353f, 0x21
.dw 0x3540, 0x35c6, 0x21
.dw 0x35c7, 0x35c7, 0x2e
.dw 0x35c8, 0x35ce, 0x21
.dw 0x35cf, 0x35cf, 0x2e
.dw 0x35d0, 0x35d6, 0x21
.dw 0x35d7, 0x35d7, 0x2e
.dw 0x35d8, 0x35de, 0x21
.dw 0x35df, 0x35df, 0x2e
.dw 0x35e0, 0x35e6, 0x21
.dw 0x35e7, 0x35e7, 0x2e
.dw 0x35e8, 0x35ee, 0x21
.dw 0x35ef, 0x35ef, 0x2e
.dw 0x35f0, 0x35f6, 0x21
.dw 0x35f7, 0x35f7, 0x2e
.dw 0x35f8, 0x35fe, 0x21
.dw 0x35ff, 0x35ff, 0x2e
.dw 0x3704, 0x3707, 0x21
.dw 0x370c, 0x370f, 0x21
.dw 0x3714, 0x3717, 0x21
.dw 0x371c, 0x371f, 0x21
.dw 0x3724, 0x3727, 0x21
.dw 0x372c, 0x372f, 0x21
.dw 0x3734, 0x3737, 0x21
.dw 0x373c, 0x37c6, 0x21
.dw 0x37c7, 0x37c7, 0x2e
.dw 0x37c8, 0x37ce, 0x21
.dw 0x37cf, 0x37cf, 0x2e
.dw 0x37d0, 0x37d6, 0x21
.dw 0x37d7, 0x37d7, 0x2e
.dw 0x37d8, 0x37de, 0x21
.dw 0x37df, 0x37df, 0x2e
.dw 0x37e0, 0x37e6, 0x21
.dw 0x37e7, 0x37e7, 0x2e
.dw 0x37e8, 0x37ee, 0x21
.dw 0x37ef, 0x37ef, 0x2e
.dw 0x37f0, 0x37f6, 0x21
.dw 0x37f7, 0x37f7, 0x2e
.dw 0x37f8, 0x37fe, 0x21
.dw 0x37ff, 0x37ff, 0x2e
.dw 0x3820, 0x382f, 0x21
.dw 0x3860, 0x386f, 0x21
.dw 0x38a0, 0x38af, 0x21
.dw 0x38b0, 0x38bf, 0x21
.dw 0x38e0, 0x38ef, 0x21
.dw 0x38f0, 0x38ff, 0x21
.dw 0x3904, 0x3907, 0x21
.dw 0x390c, 0x390f, 0x21
.dw 0x3914, 0x3917, 0x21
.dw 0x391c, 0x392f, 0x21
.dw 0x3934, 0x3937, 0x21
.dw 0x393c, 0x39bf, 0x21
.dw 0x397f, 0x397f, 0x2e
.dw 0x3980, 0x39bf, 0x21
.dw 0x39c0, 0x39c0, 0x2e
.dw 0x39c1, 0x39c7, 0x21
.dw 0x39c8, 0x39c8, 0x2e
.dw 0x39c9, 0x39cf, 0x21
.dw 0x39d0, 0x39d0, 0x2e
.dw 0x39d1, 0x39d7, 0x21
.dw 0x39d8, 0x39d8, 0x2e
.dw 0x39d9, 0x39ef, 0x21
.dw 0x39f0, 0x39f0, 0x2e
.dw 0x39f1, 0x39f6, 0x21
.dw 0x39f7, 0x39f8, 0x2e
.dw 0x39f9, 0x39fe, 0x21
.dw 0x39ff, 0x39ff, 0x2e
.dw 0x3a00, 0x3bff, 0x21
.dw 0x3c80, 0x3cff, 0x21
.dw 0x3d04, 0x3d07, 0x21
.dw 0x3d0c, 0x3d0f, 0x21
.dw 0x3d14, 0x3d17, 0x21
.dw 0x3d1c, 0x3d1f, 0x21
.dw 0x3d24, 0x3d27, 0x21
.dw 0x3d2c, 0x3d2f, 0x21
.dw 0x3d34, 0x3d37, 0x21
.dw 0x3d3c, 0x3dbf, 0X21
.dw 0x3dc0, 0x3dc0, 0x2e
.dw 0x3dc1, 0x3dc6, 0x21
.dw 0x3dc7, 0x3dc8, 0x2e
.dw 0x3dc9, 0x3dce, 0x21
.dw 0x3dcf, 0x3dd0, 0x2e
.dw 0x3dd1, 0x3dd6, 0x21
.dw 0x3dd7, 0x3dd8, 0x2e
.dw 0x3dd9, 0x3dde, 0x21
.dw 0x3ddf, 0x3de0, 0x2e
.dw 0x3de1, 0x3de6, 0x21
.dw 0x3de7, 0x3de8, 0x2e
.dw 0x3de9, 0x3dee, 0x21
.dw 0x3def, 0x3df0, 0x2e
.dw 0x3df1, 0x3df6, 0x21
.dw 0x3df7, 0x3df8, 0x2e
.dw 0x3df9, 0x3dfe, 0x21
.dw 0x3dff, 0x3e7f, 0x2e
.dw 0x3e80, 0x3eb7, 0x21
.dw 0x3eb8, 0x3ebf, 0x2e
.dw 0x3ec0, 0x3ef7, 0x21
.dw 0x3ef8, 0x3f03, 0x2e
.dw 0x3f04, 0x3f07, 0x21
.dw 0x3f08, 0x3f0b, 0x2e
.dw 0x3f0c, 0x3f0f, 0x21
.dw 0x3f10, 0x3f13, 0x2e
.dw 0x3f14, 0x3f17, 0x21
.dw 0x3f18, 0x3f1b, 0x2e
.dw 0x3f1c, 0x3f1f, 0x21
.dw 0x3f20, 0x3f23, 0x2e
.dw 0x3f24, 0x3f27, 0x21
.dw 0x3f28, 0x3f2b, 0x2e
.dw 0x3f2c, 0x3f2f, 0x21
.dw 0x3f30, 0x3f33, 0x2e
.dw 0x3f34, 0x3f37, 0x21
.dw 0x3f38, 0x3f3b, 0x2e
.dw 0x3f3c, 0x3f3d, 0x21
.dw 0x3f3e, 0x3f3f, 0x2e
.dw 0x3f40, 0x3fb7, 0x21
.dw 0x3fb8, 0x3fc0, 0x2e
.dw 0x3fc1, 0x3fc6, 0x21
.dw 0x3fc7, 0x3fc8, 0x2e
.dw 0x3fc9, 0x3fce, 0x21
.dw 0x3fcf, 0x3fd0, 0x2e
.dw 0x3fd1, 0x3fd6, 0x21
.dw 0x3fd7, 0x3fd8, 0x2e
.dw 0x3fd9, 0x3fde, 0x21
.dw 0x3fdf, 0x3fe0, 0x2e
.dw 0x3fe1, 0x3fe6, 0x21
.dw 0x3fe7, 0x3fe8, 0x2e
.dw 0x3fe9, 0x3fee, 0x21
.dw 0x3fef, 0x3ff0, 0x2e
.dw 0x3ff1, 0x3ff6, 0x21
.dw 0x3ff7, 0x3fff, 0x2e
.dw 0x4180, 0x41FF, 0x21
.dw 0x4480, 0x44bF, 0x21
.dw 0x4600, 0x47FF, 0x21
.dw 0x7000, 0x7FFF, 0x21
.dw 0x9040, 0x9040, 0x22
.dw 0x9049, 0x9049, 0x22
.dw 0x9052, 0x9052, 0x22
.dw 0x905b, 0x905b, 0x22
.dw 0x9064, 0x9064, 0x22
.dw 0x906d, 0x906d, 0x22
.dw 0x9076, 0x9076, 0x22
.dw 0x907f, 0x907f, 0x22
.dw 0x90c0, 0x90c0, 0x22
.dw 0x90c9, 0x90c9, 0x22
.dw 0x90d2, 0x90d2, 0x22
.dw 0x90db, 0x90db, 0x22
.dw 0x90e4, 0x90e4, 0x22
.dw 0x90ed, 0x90ed, 0x22
.dw 0x90f6, 0x90f6, 0x22
.dw 0x90ff, 0x90ff, 0x22
.dw 0x9180, 0x91ff, 0x21
.dw 0x9380, 0x93ff, 0x21
.dw 0x9580, 0x95ff, 0x21
.dw 0x9640, 0x967f, 0x21
.dw 0x96c0, 0x96ff, 0x21
.dw 0x9740, 0x97ff, 0x21
.dw 0x9980, 0x99ff, 0x21
.dw 0x9a40, 0x9a7f, 0x21
.dw 0x9ac0, 0x9aff, 0x21
.dw 0x9b40, 0x9bff, 0x21
.dw 0x9c60, 0x9c7f, 0x21
.dw 0x9ce0, 0x9cff, 0x21
.dw 0x9d60, 0x9d7f, 0x21
.dw 0x9ef0, 0x9eff, 0x21
.dw 0x9f70, 0x9f7f, 0x21
.dw 0x0000, 0x0000, 0x00
.endm
se_all_test
|
stsp/binutils-ia16
| 2,246
|
sim/testsuite/bfin/cec-no-snen-reti.S
|
# Blackfin testcase for having RETI LSB set correctly when not self nested
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set our handler
imm32 P5, EVT11;
loadsym R1, _ivg11;
[P5] = R1;
loadsym R1, _fail_lvl;
[P5 + 4] = R1; /* IVG12 */
[P5 + 12] = R1; /* IVG14 */
loadsym R1, _ivg13;
[P5 + 8] = R1;
# Disable self nesting
R2 = SYSCFG;
BITCLR (R2, 2);
SYSCFG = R2;
CSYNC;
# Enable IVG11/IVG13/IVG14 but not IVG12
cli R3;
BITSET (R3, 11);
BITCLR (R3, 12);
BITSET (R3, 13);
BITSET (R3, 14);
sti R3;
# Counters to keep track of nesting depth
R7 = 0;
R5 = 0;
# Lower ourselves to IVG11
loadsym R4, _fail_lvl;
RETI = R4;
RAISE 11;
RAISE 12;
RAISE 13;
RAISE 14;
RTI;
# This IVG makes sure we don't re-enter when self RAISE is pending
_ivg11:
R0 = RETI;
# Make sure we are indeed at IVG11
imm32 P0, IPEND;
R1 = [P0];
CC = BITTST (R1, 11);
IF !CC JUMP _fail_lvl;
# Should not be re-entering
CC = R5 == 0;
IF !CC JUMP _fail_lvl;
# Make sure LSB of RETI is not set
CC = BITTST (R0, 0);
IF CC JUMP _fail_lvl;
# Try to avoid nesting a few times
R5 += 1;
R6 = 3;
CC = R7 < R6;
IF !CC JUMP 1f;
[--sp] = RETI;
R7 += 1;
RAISE 11;
MNOP;NOP;MNOP;NOP;
R5 = 0;
RTI;
# Move down to IVG13 for next test
1: loadsym R4, _fail_lvl;
RETI = R4;
RTI;
# This IVG makes sure RETI LSB is ignored on transition out (RTI)
_ivg13:
R0 = RETI;
# Make sure we are indeed at IVG13
imm32 P0, IPEND;
R1 = [P0];
CC = BITTST (R1, 13);
IF !CC JUMP _fail_lvl;
# RETI LSB should not be set when entering IVG13
CC = BITTST (R0, 0);
IF CC JUMP _fail_lvl;
# Should get here only after a few IVG11 tests
CC = R7 == R6;
IF !CC JUMP _fail_lvl;
# Make sure IVG13 isn't pending
imm32 P0, ILAT;
R1 = [P0];
CC = BITTST (R1, 13);
IF CC JUMP _fail_lvl;
# Manually set RETI to with LSB set so we should stay at IVG13
# even though SNEN is disabled
loadsym R1, 1f;
BITSET (R1, 0);
RETI = R1;
R7 += 1;
RTI;
1: # Make sure we get here in right number of tests
R6 = 4;
CC = R7 == R6;
IF !CC JUMP _fail_lvl;
# Make sure we are still at IVG13
imm32 P0, IPEND;
R1 = [P0];
CC = BITTST (R1, 13);
IF !CC JUMP _fail_lvl;
dbg_pass
_fail_lvl:
dbg_fail;
|
stsp/binutils-ia16
| 5,691
|
sim/testsuite/bfin/c_dspldst_ld_dr_ippm.s
|
//Original:/testcases/core/c_dspldst_ld_dr_ippm/c_dspldst_ld_dr_ippm.dsp
// Spec Reference: c_dspldst ld_dr_i++m
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
M0 = 0 (X);
M1 = 0x4 (X);
M2 = 0x0 (X);
M3 = 0x4 (X);
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ M0 ];
R1 = [ I1 ++ M1 ];
R2 = [ I2 ++ M2 ];
R3 = [ I3 ++ M3 ];
R4 = [ I0 ++ M1 ];
R5 = [ I1 ++ M2 ];
R6 = [ I2 ++ M3 ];
R7 = [ I3 ++ M0 ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r2, 0x40414243;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x00010203;
CHECKREG r5, 0x24252627;
CHECKREG r6, 0x40414243;
CHECKREG r7, 0x64656667;
R1 = [ I0 ++ M2 ];
R2 = [ I1 ++ M3 ];
R3 = [ I2 ++ M0 ];
R4 = [ I3 ++ M1 ];
R5 = [ I0 ++ M3 ];
R6 = [ I1 ++ M0 ];
R7 = [ I2 ++ M1 ];
R0 = [ I3 ++ M2 ];
CHECKREG r0, 0x68696A6B;
CHECKREG r1, 0x04050607;
CHECKREG r2, 0x24252627;
CHECKREG r3, 0x44454647;
CHECKREG r4, 0x64656667;
CHECKREG r5, 0x04050607;
CHECKREG r6, 0x28292A2B;
CHECKREG r7, 0x44454647;
M0 = 4 (X);
M1 = 0x0 (X);
M2 = 0x4 (X);
M3 = 0x0 (X);
R2 = [ I0 ++ M0 ];
R3 = [ I1 ++ M1 ];
R4 = [ I2 ++ M2 ];
R5 = [ I3 ++ M3 ];
R6 = [ I0 ++ M1 ];
R7 = [ I1 ++ M2 ];
R0 = [ I2 ++ M3 ];
R1 = [ I3 ++ M0 ];
CHECKREG r0, 0x4C4D4E4F;
CHECKREG r1, 0x68696A6B;
CHECKREG r2, 0x08090A0B;
CHECKREG r3, 0x28292A2B;
CHECKREG r4, 0x48494A4B;
CHECKREG r5, 0x68696A6B;
CHECKREG r6, 0x0C0D0E0F;
CHECKREG r7, 0x28292A2B;
R3 = [ I0 ++ M2 ];
R4 = [ I1 ++ M3 ];
R5 = [ I2 ++ M0 ];
R6 = [ I3 ++ M1 ];
R7 = [ I0 ++ M3 ];
R0 = [ I1 ++ M0 ];
R1 = [ I2 ++ M1 ];
R2 = [ I3 ++ M2 ];
CHECKREG r0, 0x2C2D2E2F;
CHECKREG r1, 0x50515253;
CHECKREG r2, 0x6C6D6E6F;
CHECKREG r3, 0x0C0D0E0F;
CHECKREG r4, 0x2C2D2E2F;
CHECKREG r5, 0x4C4D4E4F;
CHECKREG r6, 0x6C6D6E6F;
CHECKREG r7, 0x10111213;
R5 = [ I0 ++ M2 ];
R6 = [ I1 ++ M3 ];
R7 = [ I2 ++ M0 ];
R0 = [ I3 ++ M1 ];
R1 = [ I0 ++ M3 ];
R2 = [ I1 ++ M0 ];
R3 = [ I2 ++ M1 ];
R4 = [ I3 ++ M2 ];
CHECKREG r0, 0x70717273;
CHECKREG r1, 0x14151617;
CHECKREG r2, 0x30313233;
CHECKREG r3, 0x54555657;
CHECKREG r4, 0x70717273;
CHECKREG r5, 0x10111213;
CHECKREG r6, 0x30313233;
CHECKREG r7, 0x50515253;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 2,744
|
sim/testsuite/bfin/c_ldimmhalf_h_ibml.s
|
//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_ibml/c_ldimmhalf_h_ibml.dsp
// Spec Reference: ldimmhalf h ibml
# mach: bfin
.include "testutils.inc"
start
INIT_I_REGS -1;
INIT_L_REGS -1;
INIT_B_REGS -1;
INIT_M_REGS -1;
I0.H = 0x2000;
I1.H = 0x2002;
I2.H = 0x2004;
I3.H = 0x2006;
L0.H = 0x2008;
L1.H = 0x200a;
L2.H = 0x200c;
L3.H = 0x200e;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x2000ffff;
CHECKREG r1, 0x2002ffff;
CHECKREG r2, 0x2004ffff;
CHECKREG r3, 0x2006ffff;
CHECKREG r4, 0x2008ffff;
CHECKREG r5, 0x200affff;
CHECKREG r6, 0x200cffff;
CHECKREG r7, 0x200effff;
I0.H = 0x0111;
I1.H = 0x1111;
I2.H = 0x2222;
I3.H = 0x3333;
L0.H = 0x4444;
L1.H = 0x5555;
L2.H = 0x6666;
L3.H = 0x7777;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x0111ffff;
CHECKREG r1, 0x1111ffff;
CHECKREG r2, 0x2222ffff;
CHECKREG r3, 0x3333ffff;
CHECKREG r4, 0x4444ffff;
CHECKREG r5, 0x5555ffff;
CHECKREG r6, 0x6666ffff;
CHECKREG r7, 0x7777ffff;
I0.H = 0x8888;
I1.H = 0x9aaa;
I2.H = 0xabbb;
I3.H = 0xbccc;
L0.H = 0xcddd;
L1.H = 0xdeee;
L2.H = 0xefff;
L3.H = 0xf111;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x8888ffff;
CHECKREG r1, 0x9aaaffff;
CHECKREG r2, 0xabbbffff;
CHECKREG r3, 0xbcccffff;
CHECKREG r4, 0xcdddffff;
CHECKREG r5, 0xdeeeffff;
CHECKREG r6, 0xefffffff;
CHECKREG r7, 0xf111ffff;
B0.H = 0x3000;
B1.H = 0x3002;
B2.H = 0x3004;
B3.H = 0x3006;
M0.H = 0x3008;
M1.H = 0x300a;
M2.H = 0x300c;
M3.H = 0x300e;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x3000ffff;
CHECKREG r1, 0x3002ffff;
CHECKREG r2, 0x3004ffff;
CHECKREG r3, 0x3006ffff;
CHECKREG r4, 0x3008ffff;
CHECKREG r5, 0x300Affff;
CHECKREG r6, 0x300cffff;
CHECKREG r7, 0x300effff;
B0.H = 0x0110;
B1.H = 0x1110;
B2.H = 0x2220;
B3.H = 0x3330;
M0.H = 0x4440;
M1.H = 0x5550;
M2.H = 0x6660;
M3.H = 0x7770;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x0110FFFF;
CHECKREG r1, 0x1110FFFF;
CHECKREG r2, 0x2220FFFF;
CHECKREG r3, 0x3330FFFF;
CHECKREG r4, 0x4440FFFF;
CHECKREG r5, 0x5550FFFF;
CHECKREG r6, 0x6660FFFF;
CHECKREG r7, 0x7770FFFF;
B0.H = 0xf880;
B1.H = 0xfaa0;
B2.H = 0xfbb0;
B3.H = 0xfcc0;
M0.H = 0xfdd0;
M1.H = 0xfee0;
M2.H = 0xfff0;
M3.H = 0xf110;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xf880ffff;
CHECKREG r1, 0xfaa0ffff;
CHECKREG r2, 0xfbb0ffff;
CHECKREG r3, 0xfcc0ffff;
CHECKREG r4, 0xfdd0ffff;
CHECKREG r5, 0xfee0ffff;
CHECKREG r6, 0xfff0ffff;
CHECKREG r7, 0xf110ffff;
pass
|
stsp/binutils-ia16
| 4,524
|
sim/testsuite/bfin/c_dsp32mult_pair_u.s
|
//Original:/testcases/core/c_dsp32mult_pair_u/c_dsp32mult_pair_u.dsp
// Spec Reference: dsp32mult pair u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R1 = R0.L * R0.L, R0 = R0.L * R0.L (FU);
R3 = R0.L * R1.L, R2 = R0.L * R1.H (FU);
R5 = R1.L * R0.L, R4 = R1.H * R0.L (FU);
R7 = R1.L * R1.L, R6 = R1.H * R1.H (FU);
CHECKREG r0, 0x1CFCE159;
CHECKREG r1, 0x1CFCE159;
CHECKREG r2, 0x19838F9C;
CHECKREG r3, 0xC65D90F1;
CHECKREG r4, 0x19838F9C;
CHECKREG r5, 0xC65D90F1;
CHECKREG r6, 0x03481810;
CHECKREG r7, 0xC65D90F1;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R1 = R2.L * R2.L, R0 = R2.L * R2.L (FU);
R3 = R2.L * R3.L, R2 = R2.L * R3.H (FU);
R5 = R3.L * R2.L, R4 = R3.H * R2.L (FU);
R7 = R3.L * R3.L, R6 = R3.H * R3.H (FU);
CHECKREG r0, 0x831CD0F9;
CHECKREG r1, 0x831CD0F9;
CHECKREG r2, 0x67121B3E;
CHECKREG r3, 0x95026C63;
CHECKREG r4, 0x0FDB4C7C;
CHECKREG r5, 0x0B88B0FA;
CHECKREG r6, 0x56BB5404;
CHECKREG r7, 0x2DE3AE49;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R1 = R4.L * R4.L, R0 = R4.L * R4.L (FU);
R3 = R4.L * R5.L, R2 = R4.L * R5.H (FU);
R5 = R5.L * R4.L, R4 = R5.H * R4.L (FU);
R7 = R5.L * R5.L, R6 = R5.H * R5.H (FU);
CHECKREG r0, 0x97A6DA51;
CHECKREG r1, 0x97A6DA51;
CHECKREG r2, 0x0CD4F20C;
CHECKREG r3, 0xB8397133;
CHECKREG r4, 0x0CD4F20C;
CHECKREG r5, 0xB8397133;
CHECKREG r6, 0x8491FCB1;
CHECKREG r7, 0x320E1029;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
R1 = R6.L * R6.L, R0 = R6.L * R6.L (FU);
R3 = R6.L * R7.L, R2 = R6.L * R7.H (FU);
R5 = R7.L * R6.L, R4 = R7.H * R6.L (FU);
R7 = R7.L * R7.L, R6 = R7.H * R7.H (FU);
CHECKREG r0, 0x81FF2A69;
CHECKREG r1, 0x81FF2A69;
CHECKREG r2, 0x0D058BCE;
CHECKREG r3, 0x502A3013;
CHECKREG r4, 0x0D058BCE;
CHECKREG r5, 0x502A3013;
CHECKREG r6, 0x014DEB24;
CHECKREG r7, 0x316F5F01;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (FU);
R3 = R1.L * R0.H, R2 = R1.H * R0.L (FU);
R5 = R7.H * R4.L, R4 = R7.H * R4.L (FU);
R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (FU);
CHECKREG r0, 0x000085FC;
CHECKREG r1, 0x0002D123;
CHECKREG r2, 0x00010BF8;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x0EA2B276;
CHECKREG r5, 0x0EA2B276;
CHECKREG r6, 0x0000BE3A;
CHECKREG r7, 0xFFFC0FFE;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R3 = R6.L * R5.L, R2 = R6.L * R5.H (FU);
R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (FU);
R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (FU);
R7 = R2.H * R7.L, R6 = R2.H * R7.L (FU);
CHECKREG r0, 0x0464B4BB;
CHECKREG r1, 0xB8ADBDCD;
CHECKREG r2, 0x00E2F57C;
CHECKREG r3, 0x0C6F8A4F;
CHECKREG r4, 0x71489715;
CHECKREG r5, 0xD7646535;
CHECKREG r6, 0x0062E7F2;
CHECKREG r7, 0x0062E7F2;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R3 = R6.H * R5.L, R2 = R6.L * R5.H (FU);
R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (FU);
R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (FU);
R1 = R2.H * R7.L, R0 = R2.L * R7.H (FU);
CHECKREG r0, 0x04A2FAE8;
CHECKREG r1, 0x00043554;
CHECKREG r2, 0x00092EBC;
CHECKREG r3, 0x000AEA44;
CHECKREG r4, 0xB7AF5568;
CHECKREG r5, 0x4A43345C;
CHECKREG r6, 0x00030A1D;
CHECKREG r7, 0x196677B4;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R1.H * R4.L, R0 = R1.H * R4.L (FU);
R3 = R2.L * R5.L, R2 = R2.L * R5.H (FU);
R5 = R3.H * R6.L, R4 = R3.L * R6.L (FU);
R7 = R4.L * R0.H, R6 = R4.H * R0.L (FU);
CHECKREG r0, 0xBF69768A;
CHECKREG r1, 0xBF69768A;
CHECKREG r2, 0x06B5875C;
CHECKREG r3, 0x601EC747;
CHECKREG r4, 0x00B87CBB;
CHECKREG r5, 0x0058FBC6;
CHECKREG r6, 0x00553330;
CHECKREG r7, 0x5D42ADB3;
pass
|
stsp/binutils-ia16
| 9,974
|
sim/testsuite/bfin/a3.s
|
# mach: bfin
.include "testutils.inc"
start
loadsym P1, middle;
R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 );
R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 );
R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 );
R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 );
R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 );
R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 );
R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 );
R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 );
R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 );
R0 = W [ P1 + -20 ] (Z); DBGA ( R0.L , 40 );
R0 = W [ P1 + -22 ] (Z); DBGA ( R0.L , 39 );
R0 = W [ P1 + -24 ] (Z); DBGA ( R0.L , 38 );
R0 = W [ P1 + -26 ] (Z); DBGA ( R0.L , 37 );
R0 = W [ P1 + -28 ] (Z); DBGA ( R0.L , 36 );
R0 = W [ P1 + -30 ] (Z); DBGA ( R0.L , 35 );
R0 = W [ P1 + -32 ] (Z); DBGA ( R0.L , 34 );
R0 = W [ P1 + -34 ] (Z); DBGA ( R0.L , 33 );
R0 = W [ P1 + -36 ] (Z); DBGA ( R0.L , 32 );
R0 = W [ P1 + -38 ] (Z); DBGA ( R0.L , 31 );
R0 = W [ P1 + -40 ] (Z); DBGA ( R0.L , 30 );
R0 = W [ P1 + -42 ] (Z); DBGA ( R0.L , 29 );
R0 = W [ P1 + -44 ] (Z); DBGA ( R0.L , 28 );
R0 = W [ P1 + -46 ] (Z); DBGA ( R0.L , 27 );
R0 = W [ P1 + -48 ] (Z); DBGA ( R0.L , 26 );
R0 = W [ P1 + -50 ] (Z); DBGA ( R0.L , 25 );
R0 = W [ P1 + -52 ] (Z); DBGA ( R0.L , 24 );
R0 = W [ P1 + -54 ] (Z); DBGA ( R0.L , 23 );
R0 = W [ P1 + -56 ] (Z); DBGA ( R0.L , 22 );
R0 = W [ P1 + -58 ] (Z); DBGA ( R0.L , 21 );
R0 = W [ P1 + -60 ] (Z); DBGA ( R0.L , 20 );
R0 = W [ P1 + -62 ] (Z); DBGA ( R0.L , 19 );
R0 = W [ P1 + -64 ] (Z); DBGA ( R0.L , 18 );
R0 = W [ P1 + -66 ] (Z); DBGA ( R0.L , 17 );
R0 = W [ P1 + -68 ] (Z); DBGA ( R0.L , 16 );
R0 = W [ P1 + -70 ] (Z); DBGA ( R0.L , 15 );
R0 = W [ P1 + -72 ] (Z); DBGA ( R0.L , 14 );
R0 = W [ P1 + -74 ] (Z); DBGA ( R0.L , 13 );
R0 = W [ P1 + -76 ] (Z); DBGA ( R0.L , 12 );
R0 = W [ P1 + -78 ] (Z); DBGA ( R0.L , 11 );
R0 = W [ P1 + -80 ] (Z); DBGA ( R0.L , 10 );
R0 = W [ P1 + -82 ] (Z); DBGA ( R0.L , 9 );
R0 = W [ P1 + -84 ] (Z); DBGA ( R0.L , 8 );
R0 = W [ P1 + -86 ] (Z); DBGA ( R0.L , 7 );
R0 = W [ P1 + -88 ] (Z); DBGA ( R0.L , 6 );
R0 = W [ P1 + -90 ] (Z); DBGA ( R0.L , 5 );
R0 = W [ P1 + -92 ] (Z); DBGA ( R0.L , 4 );
R0 = W [ P1 + -94 ] (Z); DBGA ( R0.L , 3 );
R0 = W [ P1 + -96 ] (Z); DBGA ( R0.L , 2 );
R0 = W [ P1 + -98 ] (Z); DBGA ( R0.L , 1 );
R0 = W [ P1 + 0 ] (Z); DBGA ( R0.L , 50 );
R0 = W [ P1 + 2 ] (Z); DBGA ( R0.L , 51 );
R0 = W [ P1 + 4 ] (Z); DBGA ( R0.L , 52 );
R0 = W [ P1 + 6 ] (Z); DBGA ( R0.L , 53 );
R0 = W [ P1 + 8 ] (Z); DBGA ( R0.L , 54 );
R0 = W [ P1 + 10 ] (Z); DBGA ( R0.L , 55 );
R0 = W [ P1 + 12 ] (Z); DBGA ( R0.L , 56 );
R0 = W [ P1 + 14 ] (Z); DBGA ( R0.L , 57 );
R0 = W [ P1 + 16 ] (Z); DBGA ( R0.L , 58 );
R0 = W [ P1 + 18 ] (Z); DBGA ( R0.L , 59 );
R0 = W [ P1 + 20 ] (Z); DBGA ( R0.L , 60 );
R0 = W [ P1 + 22 ] (Z); DBGA ( R0.L , 61 );
R0 = W [ P1 + 24 ] (Z); DBGA ( R0.L , 62 );
R0 = W [ P1 + 26 ] (Z); DBGA ( R0.L , 63 );
R0 = W [ P1 + 28 ] (Z); DBGA ( R0.L , 64 );
R0 = W [ P1 + 30 ] (Z); DBGA ( R0.L , 65 );
R0 = W [ P1 + 32 ] (Z); DBGA ( R0.L , 66 );
R0 = W [ P1 + 34 ] (Z); DBGA ( R0.L , 67 );
R0 = W [ P1 + 36 ] (Z); DBGA ( R0.L , 68 );
R0 = W [ P1 + 38 ] (Z); DBGA ( R0.L , 69 );
R0 = W [ P1 + 40 ] (Z); DBGA ( R0.L , 70 );
R0 = W [ P1 + 42 ] (Z); DBGA ( R0.L , 71 );
R0 = W [ P1 + 44 ] (Z); DBGA ( R0.L , 72 );
R0 = W [ P1 + 46 ] (Z); DBGA ( R0.L , 73 );
R0 = W [ P1 + 48 ] (Z); DBGA ( R0.L , 74 );
R0 = W [ P1 + 50 ] (Z); DBGA ( R0.L , 75 );
R0 = W [ P1 + 52 ] (Z); DBGA ( R0.L , 76 );
R0 = W [ P1 + 54 ] (Z); DBGA ( R0.L , 77 );
R0 = W [ P1 + 56 ] (Z); DBGA ( R0.L , 78 );
R0 = W [ P1 + 58 ] (Z); DBGA ( R0.L , 79 );
R0 = W [ P1 + 60 ] (Z); DBGA ( R0.L , 80 );
R0 = W [ P1 + 62 ] (Z); DBGA ( R0.L , 81 );
R0 = W [ P1 + 64 ] (Z); DBGA ( R0.L , 82 );
R0 = W [ P1 + 66 ] (Z); DBGA ( R0.L , 83 );
R0 = W [ P1 + 68 ] (Z); DBGA ( R0.L , 84 );
R0 = W [ P1 + 70 ] (Z); DBGA ( R0.L , 85 );
R0 = W [ P1 + 72 ] (Z); DBGA ( R0.L , 86 );
R0 = W [ P1 + 74 ] (Z); DBGA ( R0.L , 87 );
R0 = W [ P1 + 76 ] (Z); DBGA ( R0.L , 88 );
R0 = W [ P1 + 78 ] (Z); DBGA ( R0.L , 89 );
R0 = W [ P1 + 80 ] (Z); DBGA ( R0.L , 90 );
R0 = W [ P1 + 82 ] (Z); DBGA ( R0.L , 91 );
R0 = W [ P1 + 84 ] (Z); DBGA ( R0.L , 92 );
R0 = W [ P1 + 86 ] (Z); DBGA ( R0.L , 93 );
R0 = W [ P1 + 88 ] (Z); DBGA ( R0.L , 94 );
R0 = W [ P1 + 90 ] (Z); DBGA ( R0.L , 95 );
R0 = W [ P1 + 92 ] (Z); DBGA ( R0.L , 96 );
R0 = W [ P1 + 94 ] (Z); DBGA ( R0.L , 97 );
R0 = W [ P1 + 96 ] (Z); DBGA ( R0.L , 98 );
R0 = W [ P1 + 98 ] (Z); DBGA ( R0.L , 99 );
FP = P1;
R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 );
R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 );
R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 );
R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 );
R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 );
R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 );
R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 );
R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 );
R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 );
R0 = W [ FP + -20 ] (Z); DBGA ( R0.L , 40 );
R0 = W [ FP + -22 ] (Z); DBGA ( R0.L , 39 );
R0 = W [ FP + -24 ] (Z); DBGA ( R0.L , 38 );
R0 = W [ FP + -26 ] (Z); DBGA ( R0.L , 37 );
R0 = W [ FP + -28 ] (Z); DBGA ( R0.L , 36 );
R0 = W [ FP + -30 ] (Z); DBGA ( R0.L , 35 );
R0 = W [ FP + -32 ] (Z); DBGA ( R0.L , 34 );
R0 = W [ FP + -34 ] (Z); DBGA ( R0.L , 33 );
R0 = W [ FP + -36 ] (Z); DBGA ( R0.L , 32 );
R0 = W [ FP + -38 ] (Z); DBGA ( R0.L , 31 );
R0 = W [ FP + -40 ] (Z); DBGA ( R0.L , 30 );
R0 = W [ FP + -42 ] (Z); DBGA ( R0.L , 29 );
R0 = W [ FP + -44 ] (Z); DBGA ( R0.L , 28 );
R0 = W [ FP + -46 ] (Z); DBGA ( R0.L , 27 );
R0 = W [ FP + -48 ] (Z); DBGA ( R0.L , 26 );
R0 = W [ FP + -50 ] (Z); DBGA ( R0.L , 25 );
R0 = W [ FP + -52 ] (Z); DBGA ( R0.L , 24 );
R0 = W [ FP + -54 ] (Z); DBGA ( R0.L , 23 );
R0 = W [ FP + -56 ] (Z); DBGA ( R0.L , 22 );
R0 = W [ FP + -58 ] (Z); DBGA ( R0.L , 21 );
R0 = W [ FP + -60 ] (Z); DBGA ( R0.L , 20 );
R0 = W [ FP + -62 ] (Z); DBGA ( R0.L , 19 );
R0 = W [ FP + -64 ] (Z); DBGA ( R0.L , 18 );
R0 = W [ FP + -66 ] (Z); DBGA ( R0.L , 17 );
R0 = W [ FP + -68 ] (Z); DBGA ( R0.L , 16 );
R0 = W [ FP + -70 ] (Z); DBGA ( R0.L , 15 );
R0 = W [ FP + -72 ] (Z); DBGA ( R0.L , 14 );
R0 = W [ FP + -74 ] (Z); DBGA ( R0.L , 13 );
R0 = W [ FP + -76 ] (Z); DBGA ( R0.L , 12 );
R0 = W [ FP + -78 ] (Z); DBGA ( R0.L , 11 );
R0 = W [ FP + -80 ] (Z); DBGA ( R0.L , 10 );
R0 = W [ FP + -82 ] (Z); DBGA ( R0.L , 9 );
R0 = W [ FP + -84 ] (Z); DBGA ( R0.L , 8 );
R0 = W [ FP + -86 ] (Z); DBGA ( R0.L , 7 );
R0 = W [ FP + -88 ] (Z); DBGA ( R0.L , 6 );
R0 = W [ FP + -90 ] (Z); DBGA ( R0.L , 5 );
R0 = W [ FP + -92 ] (Z); DBGA ( R0.L , 4 );
R0 = W [ FP + -94 ] (Z); DBGA ( R0.L , 3 );
R0 = W [ FP + -96 ] (Z); DBGA ( R0.L , 2 );
R0 = W [ FP + -98 ] (Z); DBGA ( R0.L , 1 );
R0 = W [ FP + 0 ] (Z); DBGA ( R0.L , 50 );
R0 = W [ FP + 2 ] (Z); DBGA ( R0.L , 51 );
R0 = W [ FP + 4 ] (Z); DBGA ( R0.L , 52 );
R0 = W [ FP + 6 ] (Z); DBGA ( R0.L , 53 );
R0 = W [ FP + 8 ] (Z); DBGA ( R0.L , 54 );
R0 = W [ FP + 10 ] (Z); DBGA ( R0.L , 55 );
R0 = W [ FP + 12 ] (Z); DBGA ( R0.L , 56 );
R0 = W [ FP + 14 ] (Z); DBGA ( R0.L , 57 );
R0 = W [ FP + 16 ] (Z); DBGA ( R0.L , 58 );
R0 = W [ FP + 18 ] (Z); DBGA ( R0.L , 59 );
R0 = W [ FP + 20 ] (Z); DBGA ( R0.L , 60 );
R0 = W [ FP + 22 ] (Z); DBGA ( R0.L , 61 );
R0 = W [ FP + 24 ] (Z); DBGA ( R0.L , 62 );
R0 = W [ FP + 26 ] (Z); DBGA ( R0.L , 63 );
R0 = W [ FP + 28 ] (Z); DBGA ( R0.L , 64 );
R0 = W [ FP + 30 ] (Z); DBGA ( R0.L , 65 );
R0 = W [ FP + 32 ] (Z); DBGA ( R0.L , 66 );
R0 = W [ FP + 34 ] (Z); DBGA ( R0.L , 67 );
R0 = W [ FP + 36 ] (Z); DBGA ( R0.L , 68 );
R0 = W [ FP + 38 ] (Z); DBGA ( R0.L , 69 );
R0 = W [ FP + 40 ] (Z); DBGA ( R0.L , 70 );
R0 = W [ FP + 42 ] (Z); DBGA ( R0.L , 71 );
R0 = W [ FP + 44 ] (Z); DBGA ( R0.L , 72 );
R0 = W [ FP + 46 ] (Z); DBGA ( R0.L , 73 );
R0 = W [ FP + 48 ] (Z); DBGA ( R0.L , 74 );
R0 = W [ FP + 50 ] (Z); DBGA ( R0.L , 75 );
R0 = W [ FP + 52 ] (Z); DBGA ( R0.L , 76 );
R0 = W [ FP + 54 ] (Z); DBGA ( R0.L , 77 );
R0 = W [ FP + 56 ] (Z); DBGA ( R0.L , 78 );
R0 = W [ FP + 58 ] (Z); DBGA ( R0.L , 79 );
R0 = W [ FP + 60 ] (Z); DBGA ( R0.L , 80 );
R0 = W [ FP + 62 ] (Z); DBGA ( R0.L , 81 );
R0 = W [ FP + 64 ] (Z); DBGA ( R0.L , 82 );
R0 = W [ FP + 66 ] (Z); DBGA ( R0.L , 83 );
R0 = W [ FP + 68 ] (Z); DBGA ( R0.L , 84 );
R0 = W [ FP + 70 ] (Z); DBGA ( R0.L , 85 );
R0 = W [ FP + 72 ] (Z); DBGA ( R0.L , 86 );
R0 = W [ FP + 74 ] (Z); DBGA ( R0.L , 87 );
R0 = W [ FP + 76 ] (Z); DBGA ( R0.L , 88 );
R0 = W [ FP + 78 ] (Z); DBGA ( R0.L , 89 );
R0 = W [ FP + 80 ] (Z); DBGA ( R0.L , 90 );
R0 = W [ FP + 82 ] (Z); DBGA ( R0.L , 91 );
R0 = W [ FP + 84 ] (Z); DBGA ( R0.L , 92 );
R0 = W [ FP + 86 ] (Z); DBGA ( R0.L , 93 );
R0 = W [ FP + 88 ] (Z); DBGA ( R0.L , 94 );
R0 = W [ FP + 90 ] (Z); DBGA ( R0.L , 95 );
R0 = W [ FP + 92 ] (Z); DBGA ( R0.L , 96 );
R0 = W [ FP + 94 ] (Z); DBGA ( R0.L , 97 );
R0 = W [ FP + 96 ] (Z); DBGA ( R0.L , 98 );
R0 = W [ FP + 98 ] (Z); DBGA ( R0.L , 99 );
pass
.data
.dw 0
.dw 1
.dw 2
.dw 3
.dw 4
.dw 5
.dw 6
.dw 7
.dw 8
.dw 9
.dw 10
.dw 11
.dw 12
.dw 13
.dw 14
.dw 15
.dw 16
.dw 17
.dw 18
.dw 19
.dw 20
.dw 21
.dw 22
.dw 23
.dw 24
.dw 25
.dw 26
.dw 27
.dw 28
.dw 29
.dw 30
.dw 31
.dw 32
.dw 33
.dw 34
.dw 35
.dw 36
.dw 37
.dw 38
.dw 39
.dw 40
.dw 41
.dw 42
.dw 43
.dw 44
.dw 45
.dw 46
.dw 47
.dw 48
.dw 49
middle:
.dw 50
.dw 51
.dw 52
.dw 53
.dw 54
.dw 55
.dw 56
.dw 57
.dw 58
.dw 59
.dw 60
.dw 61
.dw 62
.dw 63
.dw 64
.dw 65
.dw 66
.dw 67
.dw 68
.dw 69
.dw 70
.dw 71
.dw 72
.dw 73
.dw 74
.dw 75
.dw 76
.dw 77
.dw 78
.dw 79
.dw 80
.dw 81
.dw 82
.dw 83
.dw 84
.dw 85
.dw 86
.dw 87
.dw 88
.dw 89
.dw 90
.dw 91
.dw 92
.dw 93
.dw 94
.dw 95
.dw 96
.dw 97
.dw 98
.dw 99
|
stsp/binutils-ia16
| 1,919
|
sim/testsuite/bfin/c_dsp32alu_byteop3.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop3/c_dsp32alu_byteop3.dsp
// Spec Reference: dsp32alu byteop3
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO);
R5 = BYTEOP3P ( R1:0 , R3:2 ) (HI);
R6 = BYTEOP3P ( R1:0 , R3:2 ) (LO);
R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI);
CHECKREG r4, 0x00FF0000;
CHECKREG r5, 0xFF000000;
CHECKREG r6, 0x00FF0000;
CHECKREG r7, 0xFF000000;
imm32 r0, 0x1567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445525;
imm32 r3, 0x46667727;
imm32 r4, 0x58889929;
imm32 r5, 0x6aaabb2b;
imm32 r6, 0x7cccdd2d;
imm32 r7, 0x8eeeffff;
R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO);
R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO);
R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI);
R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI);
CHECKREG r0, 0x00FF00FF;
CHECKREG r1, 0x00FF00FF;
CHECKREG r2, 0xFF00FF00;
CHECKREG r3, 0x00000000;
imm32 r0, 0x716789ab;
imm32 r1, 0x8289abcd;
imm32 r2, 0x93445555;
imm32 r3, 0xa4667777;
imm32 r4, 0xb56789ab;
imm32 r5, 0xd689abcd;
imm32 r6, 0xe7445555;
imm32 r7, 0x6f661235;
R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO);
R5 = BYTEOP3P ( R1:0 , R3:2 ) (LO);
R6 = BYTEOP3P ( R1:0 , R3:2 ) (HI);
R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI);
CHECKREG r4, 0x00FF0000;
CHECKREG r5, 0x00FF0000;
CHECKREG r6, 0xFF000000;
CHECKREG r7, 0xFF000000;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO);
R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO);
R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI);
R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI);
CHECKREG r0, 0x00FF00FF;
CHECKREG r1, 0x00FF00FF;
CHECKREG r2, 0xFF00FF00;
CHECKREG r3, 0x00000000;
pass
|
stsp/binutils-ia16
| 11,060
|
sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s
|
//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_nostall/c_regmv_imlb_dep_nostall.dsp
// Spec Reference: regmv imlb-dep no stall
# mach: bfin
.include "testutils.inc"
start
// P-reg to I,M-reg to R-reg: no stall
//imm32 p0, 0x00001111;
imm32 p1, 0x12213330;
imm32 p2, 0x14415550;
imm32 p3, 0x16617770;
imm32 p4, 0x18819990;
imm32 p5, 0x1aa1bbb0;
imm32 fp, 0x1cc1ddd0;
imm32 sp, 0x1ee1fff0;
I0 = P0;
R0 = I0;
I1 = P1;
R1 = I1;
I2 = P2;
R2 = I2;
I3 = P3;
R3 = I3;
M0 = P4;
R4 = M0;
M1 = P5;
R5 = M1;
M2 = SP;
R6 = M2;
M3 = FP;
R7 = M3;
CHECKREG r1, 0x12213330;
CHECKREG r2, 0x14415550;
CHECKREG r3, 0x16617770;
CHECKREG r4, 0x18819990;
CHECKREG r5, 0x1aa1bbb0;
CHECKREG r6, 0x1EE1FFF0;
CHECKREG r7, 0x1CC1DDD0;
R0 = M3;
R1 = M2;
R2 = M1;
R3 = M0;
R4 = I3;
R5 = I2;
R6 = I1;
R7 = I0;
CHECKREG r0, 0x1CC1DDD0;
CHECKREG r1, 0x1EE1FFF0;
CHECKREG r2, 0x1AA1BBB0;
CHECKREG r3, 0x18819990;
CHECKREG r4, 0x16617770;
CHECKREG r5, 0x14415550;
CHECKREG r6, 0x12213330;
// P-reg to L,B-reg to R-reg: no stall
//imm32 p0, 0x00001111;
imm32 p1, 0x21213331;
imm32 p2, 0x21415551;
imm32 p3, 0x21617771;
imm32 p4, 0x21819991;
imm32 p5, 0x21a1bbb1;
imm32 fp, 0x21c1ddd1;
imm32 sp, 0x21e1fff1;
L0 = P0;
R0 = L0;
L1 = P1;
R1 = L1;
L2 = P2;
R2 = L2;
L3 = P3;
R3 = L3;
B0 = P4;
R4 = B0;
B1 = P5;
R5 = B1;
B2 = SP;
R6 = B2;
B3 = FP;
R7 = B3;
CHECKREG r1, 0x21213331;
CHECKREG r2, 0x21415551;
CHECKREG r3, 0x21617771;
CHECKREG r4, 0x21819991;
CHECKREG r5, 0x21a1bbb1;
CHECKREG r6, 0x21E1FFF1;
CHECKREG r7, 0x21C1DDD1;
R0 = L3;
R1 = L2;
R2 = L1;
R3 = L0;
R4 = B3;
R5 = B2;
R6 = B1;
R7 = B0;
CHECKREG r0, 0x21617771;
CHECKREG r1, 0x21415551;
CHECKREG r2, 0x21213331;
CHECKREG r4, 0x21C1DDD1;
CHECKREG r5, 0x21E1FFF1;
CHECKREG r6, 0x21A1BBB1;
CHECKREG r7, 0x21819991;
// P-reg to I,M-reg to L,B-reg: no stall
//imm32 p0, 0x00001111;
imm32 p1, 0x72213337;
imm32 p2, 0x74415557;
imm32 p3, 0x76617777;
imm32 p4, 0x78819997;
imm32 p5, 0x7aa1bbb7;
imm32 fp, 0x7cc1ddd7;
imm32 sp, 0x77e1fff7;
I0 = P0;
L0 = I0;
I1 = P1;
L1 = I1;
I2 = P2;
L2 = I2;
I3 = P3;
L3 = I3;
M0 = P4;
B0 = M0;
M1 = P5;
B1 = M1;
M2 = SP;
B2 = M2;
M3 = FP;
B3 = M3;
R0 = L3;
R1 = L2;
R2 = L1;
R3 = L0;
R4 = B3;
R5 = B2;
R6 = B1;
R7 = B0;
CHECKREG r0, 0x76617777;
CHECKREG r1, 0x74415557;
CHECKREG r2, 0x72213337;
CHECKREG r4, 0x7CC1DDD7;
CHECKREG r5, 0x77E1FFF7;
CHECKREG r6, 0x7AA1BBB7;
CHECKREG r7, 0x78819997;
R0 = M3;
R1 = M2;
R2 = M1;
R3 = M0;
R4 = I3;
R5 = I2;
R6 = I1;
R7 = I0;
CHECKREG r0, 0x7CC1DDD7;
CHECKREG r1, 0x77E1FFF7;
CHECKREG r2, 0x7AA1BBB7;
CHECKREG r3, 0x78819997;
CHECKREG r4, 0x76617777;
CHECKREG r5, 0x74415557;
CHECKREG r6, 0x72213337;
// P-reg to L,B-reg to I,Mreg: no stall
//imm32 p0, 0x00001111;
imm32 p1, 0x81213338;
imm32 p2, 0x81415558;
imm32 p3, 0x81617778;
imm32 p4, 0x81819998;
imm32 p5, 0x81a1bbb8;
imm32 fp, 0x81c1ddd8;
imm32 sp, 0x81e1fff8;
L0 = P0;
I0 = L0;
L1 = P1;
I1 = L1;
L2 = P2;
I2 = L2;
L3 = P3;
I3 = L3;
B0 = P4;
M0 = B0;
B1 = P5;
M1 = B1;
B2 = SP;
M2 = B2;
B3 = FP;
M3 = B3;
R0 = M0;
R1 = M1;
R2 = M2;
R3 = M3;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x81819998;
CHECKREG r1, 0x81A1BBB8;
CHECKREG r2, 0x81E1FFF8;
CHECKREG r3, 0x81C1DDD8;
CHECKREG r5, 0x81213338;
CHECKREG r6, 0x81415558;
CHECKREG r7, 0x81617778;
R0 = L3;
R1 = L2;
R2 = L1;
R3 = L0;
R4 = B3;
R5 = B2;
R6 = B1;
R7 = B0;
CHECKREG r0, 0x81617778;
CHECKREG r1, 0x81415558;
CHECKREG r2, 0x81213338;
CHECKREG r4, 0x81C1DDD8;
CHECKREG r5, 0x81E1FFF8;
CHECKREG r6, 0x81A1BBB8;
CHECKREG r7, 0x81819998;
// I-to-M, I-to-I and to R-reg: no stall
imm32 i0, 0x30001111;
imm32 i1, 0x23213332;
imm32 i2, 0x14315552;
imm32 i3, 0x01637772;
imm32 m0, 0x80113992;
imm32 m1, 0xaa01b3b2;
imm32 m2, 0xccc01d32;
imm32 m3, 0xeee101f3;
M0 = I0;
R4 = M0;
M1 = I1;
R5 = M1;
M2 = I2;
R6 = M2;
M3 = I3;
R7 = M3;
I0 = I3;
R0 = I0;
I1 = I2;
R1 = I1;
I3 = I0;
R2 = I3;
I2 = I1;
R3 = I2;
CHECKREG r0, 0x01637772;
CHECKREG r1, 0x14315552;
CHECKREG r2, 0x01637772;
CHECKREG r3, 0x14315552;
CHECKREG r4, 0x30001111;
CHECKREG r5, 0x23213332;
CHECKREG r6, 0x14315552;
CHECKREG r7, 0x01637772;
R0 = M0;
R1 = M1;
R2 = M2;
R3 = M3;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x30001111;
CHECKREG r1, 0x23213332;
CHECKREG r2, 0x14315552;
CHECKREG r3, 0x01637772;
CHECKREG r4, 0x01637772;
CHECKREG r5, 0x14315552;
CHECKREG r6, 0x14315552;
CHECKREG r7, 0x01637772;
// I-to-M, I-to-I and to P-reg: no stall
imm32 i0, 0x00001111;
imm32 i1, 0x42213342;
imm32 i2, 0x44415542;
imm32 i3, 0x46617742;
imm32 m0, 0x48819942;
imm32 m1, 0x4aa1bb42;
imm32 m2, 0x4cc1dd42;
imm32 m3, 0x4ee1ff42;
M0 = I0;
R0 = M0;
M1 = I1;
P1 = M1;
M2 = I2;
P2 = M2;
M3 = I3;
P3 = M3;
I0 = I3;
P4 = I0;
I1 = I2;
P5 = I1;
I2 = I0;
SP = I2;
I3 = I1;
FP = I3;
CHECKREG r0, 0x00001111;
CHECKREG p1, 0x42213342;
CHECKREG p2, 0x44415542;
CHECKREG p3, 0x46617742;
CHECKREG p4, 0x46617742;
CHECKREG p5, 0x44415542;
CHECKREG sp, 0x46617742;
CHECKREG fp, 0x44415542;
R0 = M0;
R1 = M1;
R2 = M2;
R3 = M3;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001111;
CHECKREG r1, 0x42213342;
CHECKREG r2, 0x44415542;
CHECKREG r3, 0x46617742;
CHECKREG r4, 0x46617742;
CHECKREG r5, 0x44415542;
CHECKREG r6, 0x46617742;
CHECKREG r7, 0x44415542;
// L-to-B, L-to-L and to R-reg: no stall
imm32 l0, 0x40001114;
imm32 l1, 0x24213334;
imm32 l2, 0x54415554;
imm32 l3, 0x05647774;
imm32 b0, 0x60514994;
imm32 b1, 0xa605b4b4;
imm32 b2, 0xcc605d44;
imm32 b3, 0xeee605f4;
B0 = L0;
R4 = B0;
B1 = L1;
R5 = B1;
B2 = L2;
R6 = B2;
B3 = L3;
R7 = B3;
L0 = L3;
R0 = L0;
L1 = L2;
R1 = L1;
L3 = L0;
R2 = L3;
L2 = L1;
R3 = L2;
CHECKREG r0, 0x05647774;
CHECKREG r1, 0x54415554;
CHECKREG r2, 0x05647774;
CHECKREG r3, 0x54415554;
CHECKREG r4, 0x40001114;
CHECKREG r5, 0x24213334;
CHECKREG r6, 0x54415554;
CHECKREG r7, 0x05647774;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x05647774;
CHECKREG r1, 0x54415554;
CHECKREG r2, 0x54415554;
CHECKREG r3, 0x05647774;
CHECKREG r4, 0x40001114;
CHECKREG r5, 0x24213334;
CHECKREG r6, 0x54415554;
CHECKREG r7, 0x05647774;
// L-to-B, L-to-L and to P-reg: no stall
imm32 l0, 0x60001116;
imm32 l1, 0x46213346;
imm32 l2, 0x74615546;
imm32 l3, 0x47667746;
imm32 b0, 0x48716946;
imm32 b1, 0x8aa7b646;
imm32 b2, 0x48c17d66;
imm32 b3, 0x4e81f746;
M0 = I0;
R0 = M0;
M1 = I1;
P1 = M1;
M2 = I2;
P2 = M2;
M3 = I3;
P3 = M3;
I0 = I3;
P4 = I0;
I1 = I2;
P5 = I1;
I2 = I0;
SP = I2;
I3 = I1;
FP = I3;
CHECKREG r0, 0x46617742;
CHECKREG p1, 0x44415542;
CHECKREG p2, 0x46617742;
CHECKREG p3, 0x44415542;
CHECKREG p4, 0x44415542;
CHECKREG p5, 0x46617742;
CHECKREG sp, 0x44415542;
CHECKREG fp, 0x46617742;
R0 = M0;
R1 = M1;
R2 = M2;
R3 = M3;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x46617742;
CHECKREG r1, 0x44415542;
CHECKREG r2, 0x46617742;
CHECKREG r3, 0x44415542;
CHECKREG r4, 0x44415542;
CHECKREG r5, 0x46617742;
CHECKREG r6, 0x44415542;
CHECKREG r7, 0x46617742;
// I-to-M-to-L, I-to-I-to-B -reg: no stall
imm32 i0, 0x90001119;
imm32 i1, 0x93213339;
imm32 i2, 0x94315559;
imm32 i3, 0x91637779;
imm32 m0, 0x90113999;
imm32 m1, 0x9a01b3b9;
imm32 m2, 0x9cc01d39;
imm32 m3, 0x9ee101f9;
M0 = I0;
L0 = M0;
M1 = I1;
L1 = M1;
M2 = I2;
L2 = M2;
M3 = I3;
L3 = M3;
I0 = I3;
B0 = I0;
I1 = I2;
B1 = I1;
I3 = I0;
B2 = I3;
I2 = I1;
B3 = I2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x90001119;
CHECKREG r1, 0x93213339;
CHECKREG r2, 0x94315559;
CHECKREG r3, 0x91637779;
CHECKREG r4, 0x91637779;
CHECKREG r5, 0x94315559;
CHECKREG r6, 0x91637779;
CHECKREG r7, 0x94315559;
R0 = M0;
R1 = M1;
R2 = M2;
R3 = M3;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x90001119;
CHECKREG r1, 0x93213339;
CHECKREG r2, 0x94315559;
CHECKREG r3, 0x91637779;
CHECKREG r4, 0x91637779;
CHECKREG r5, 0x94315559;
CHECKREG r6, 0x94315559;
CHECKREG r7, 0x91637779;
// I-to-M-B, I-to-I-L reg: no stall
imm32 i0, 0xa000111a;
imm32 i1, 0xaa21334a;
imm32 i2, 0xa4a1554a;
imm32 i3, 0xa66a774a;
imm32 m0, 0xa881a94a;
imm32 m1, 0xaaa1ba4a;
imm32 m2, 0xacc1ddaa;
imm32 m3, 0xaee1ff4a;
M0 = I0;
B3 = M0;
M1 = I1;
B2 = M1;
M2 = I2;
B1 = M2;
M3 = I3;
B0 = M3;
I0 = I3;
L1 = I0;
I1 = I2;
L2 = I1;
I2 = I0;
L3 = I2;
I3 = I1;
L0 = I3;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0xA4A1554A;
CHECKREG r1, 0xA66A774A;
CHECKREG r2, 0xA4A1554A;
CHECKREG r3, 0xA66A774A;
CHECKREG r4, 0xA66A774A;
CHECKREG r5, 0xA4A1554A;
CHECKREG r6, 0xAA21334A;
CHECKREG r7, 0xA000111A;
R0 = M0;
R1 = M1;
R2 = M2;
R3 = M3;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0xA000111A;
CHECKREG r1, 0xAA21334A;
CHECKREG r2, 0xA4A1554A;
CHECKREG r3, 0xA66A774A;
CHECKREG r4, 0xA66A774A;
CHECKREG r5, 0xA4A1554A;
CHECKREG r6, 0xA66A774A;
CHECKREG r7, 0xA4A1554A;
// L-to-B-to-I, L-to-L-to-M reg: no stall
imm32 l0, 0xb000111b;
imm32 l1, 0xb421333b;
imm32 l2, 0xb441555b;
imm32 l3, 0xb564777b;
imm32 b0, 0xb051499b;
imm32 b1, 0xb605b4bb;
imm32 b2, 0xbc605d4b;
imm32 b3, 0xbee605fb;
B0 = L0;
I2 = B0;
B1 = L1;
I3 = B1;
B2 = L2;
I0 = B2;
B3 = L3;
I1 = B3;
L0 = L3;
M0 = L0;
L1 = L2;
M1 = L1;
L3 = L0;
M2 = L3;
L2 = L1;
M3 = L2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xB441555B;
CHECKREG r1, 0xB564777B;
CHECKREG r2, 0xB000111B;
CHECKREG r3, 0xB421333B;
CHECKREG r4, 0xB564777B;
CHECKREG r5, 0xB441555B;
CHECKREG r6, 0xB564777B;
CHECKREG r7, 0xB441555B;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0xB564777B;
CHECKREG r1, 0xB441555B;
CHECKREG r2, 0xB441555B;
CHECKREG r3, 0xB564777B;
CHECKREG r4, 0xB000111B;
CHECKREG r5, 0xB421333B;
CHECKREG r6, 0xB441555B;
CHECKREG r7, 0xB564777B;
// B-to-L-to-M, B-to-B-to-I reg: no stall
imm32 l0, 0xc000111c;
imm32 l1, 0xc621334c;
imm32 l2, 0xc461554c;
imm32 l3, 0xc766774c;
imm32 b0, 0xc871694c;
imm32 b1, 0xcaa7b64c;
imm32 b2, 0xc8c17d6c;
imm32 b3, 0xce81f74c;
L0 = B0;
M1 = L0;
L1 = B1;
M2 = L1;
L2 = B2;
M3 = L2;
L3 = B3;
M0 = L3;
B3 = B0;
I0 = B3;
B0 = B1;
I1 = B0;
B1 = B2;
I2 = B1;
B2 = B3;
I3 = B2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0xC871694C;
CHECKREG r1, 0xCAA7B64C;
CHECKREG r2, 0xC8C17D6C;
CHECKREG r3, 0xCE81F74C;
CHECKREG r4, 0xCAA7B64C;
CHECKREG r5, 0xC8C17D6C;
CHECKREG r6, 0xC871694C;
CHECKREG r7, 0xC871694C;
R0 = M0;
R1 = M1;
R2 = M2;
R3 = M3;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0xCE81F74C;
CHECKREG r1, 0xC871694C;
CHECKREG r2, 0xCAA7B64C;
CHECKREG r3, 0xC8C17D6C;
CHECKREG r4, 0xC871694C;
CHECKREG r5, 0xCAA7B64C;
CHECKREG r6, 0xC8C17D6C;
CHECKREG r7, 0xC871694C;
pass
|
stsp/binutils-ia16
| 5,635
|
sim/testsuite/bfin/se_misaligned_fetch.S
|
//Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp
// Description: attempt to fetch code from misaligned address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
CLI R0; // hold off nonmaskables while writing EVTs
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC; // wait for MMR writes
STI R0; // reenable events
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
// [--sp] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
LD32_LABEL(p1, TARGET);
P1 += 1; // cause access to be misaligned
JUMP ( P1 ); // should cause misaligned
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
TARGET:
NOP;
NOP;
NOP;
// PUT YOUR TEST HERE!
END:
CHECKREG(r5, 0xFFFFFFFF); // handler sets this if reached
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x2A; // EXCAUSE 0x2A means I-Fetch Misaligned Access
CC = r7 == r6;
IF CC JUMP IFETCHMISALIGNED; // If EXCAUSE != 0x2A then leave
dbg_pass; // if the EXCAUSE is wrong the test will infinite loop
IFETCHMISALIGNED:
R7 = P1; // Fix up return address
BITCLR(r7, 0); // Strip off errant LSB
RETX = r7; // and put back in RETX
R5 = -1; // set flag to indicate success
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 3,203
|
sim/testsuite/bfin/random_0011.S
|
# test acc shifts larger than they should be, and ASTAT flags
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x7cc0c090 | _VS | _V | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x1890bdbc;
dmm32 A0.x, 0x00000079;
A0 = A0 << 0x2;
checkreg A0.w, 0x6242f6f0;
checkreg A0.x, 0xffffffe4;
checkreg ASTAT, (0x7cc0c090 | _VS | _V | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x02fe375e;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x21;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0xffffffaf;
checkreg ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x7c800a10 | _VS | _AV0S | _AV0 | _AC1);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
A0 = A0 << 0x1f;
checkreg ASTAT, (0x7c800a10 | _VS | _AV0S | _AC1 | _AZ);
dmm32 ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x2e4b0bba;
dmm32 A0.x, 0xffffff8c;
A0 = A0 >> 0x25;
checkreg A0.w, 0xd0000000;
checkreg A0.x, 0x0000005d;
checkreg ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC);
dmm32 A1.w, 0x3ae26599;
dmm32 A1.x, 0xfffffff3;
A1 = A1 >> 0x25;
checkreg A1.w, 0xc8000000;
checkreg A1.x, 0x0000002c;
checkreg ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC);
dmm32 ASTAT, (0x3c204000 | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC);
dmm32 A1.w, 0x1686a378;
dmm32 A1.x, 0x0000006a;
A1 = A1 >> 0x16;
checkreg A1.w, 0x0001a85a;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x3c204000 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC);
dmm32 ASTAT, (0x30500800 | _VS | _AV0S | _AQ);
dmm32 A1.w, 0x6575285f;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x2e;
checkreg A1.w, 0xa17c0000;
checkreg A1.x, 0xffffffd4;
checkreg ASTAT, (0x30500800 | _VS | _AV0S | _AQ | _AN);
dmm32 ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC);
dmm32 A1.w, 0x0c7da4e2;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x29;
checkreg A1.w, 0x71000000;
checkreg A1.x, 0xffffffd2;
checkreg ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC | _AN);
dmm32 ASTAT, (0x74000600 | _VS | _AC1 | _AQ);
dmm32 A0.w, 0xd0e47afa;
dmm32 A0.x, 0x00000006;
A0 = A0 >> 0x32;
checkreg A0.w, 0x1ebe8000;
checkreg A0.x, 0x00000039;
checkreg ASTAT, (0x74000600 | _VS | _AC1 | _AQ);
dmm32 ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ);
dmm32 A1.w, 0x1b158860;
dmm32 A1.x, 0x00000068;
A1 = A1 >> 0x21;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000030;
checkreg ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ);
dmm32 ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC | _AN);
dmm32 A1.w, 0x0a2c41e4;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x25;
checkreg A1.w, 0x20000000;
checkreg A1.x, 0x0000000f;
checkreg ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC);
dmm32 ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AZ);
dmm32 A0.w, 0xec125059;
dmm32 A0.x, 0xffffffff;
A0 = A0 >> 0x32;
checkreg A0.w, 0x94164000;
checkreg A0.x, 0x00000004;
checkreg ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY);
pass
|
stsp/binutils-ia16
| 4,311
|
sim/testsuite/bfin/c_dagmodik_lnz_imgebl.s
|
//Original:/testcases/core/c_dagmodik_lnz_imgebl/c_dagmodik_lnz_imgebl.dsp
// Spec Reference: dagmodik l not zero & i+m >= b+l
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x00001000;
imm32 b1, 0x00001000;
imm32 b2, 0x00001000;
imm32 b3, 0x00001000;
imm32 l0, 0x00000001;
imm32 l1, 0x00000002;
imm32 l2, 0x00000003;
imm32 l3, 0x00000004;
imm32 m0, 0x00000015;
imm32 m1, 0x00000016;
imm32 m2, 0x00000017;
imm32 m3, 0x00000018;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00001100;
CHECKREG r2, 0x0000100F;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001002;
CHECKREG r5, 0x00001100;
CHECKREG r6, 0x0000100E;
CHECKREG r7, 0x00001001;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001000;
CHECKREG r1, 0x000010FE;
CHECKREG r2, 0x0000100C;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00000FFF;
CHECKREG r5, 0x000010FC;
CHECKREG r6, 0x0000100A;
CHECKREG r7, 0x00001001;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x000010FE;
CHECKREG r2, 0x0000100B;
CHECKREG r3, 0x00001001;
CHECKREG r4, 0x00001005;
CHECKREG r5, 0x00001100;
CHECKREG r6, 0x0000100C;
CHECKREG r7, 0x00001001;
I0 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG r0, 0x00000FFE;
CHECKREG r1, 0x000010F8;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001001;
CHECKREG r4, 0x00001005;
CHECKREG r5, 0x00001100;
CHECKREG r6, 0x0000100C;
CHECKREG r7, 0x00001001;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00000FFE;
CHECKREG r1, 0x000010F8;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001001;
CHECKREG r4, 0x00000FF8;
CHECKREG r5, 0x000010F0;
CHECKREG r6, 0x00000FFF;
CHECKREG r7, 0x00001001;
// i+m = b+l
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x00001000;
imm32 b1, 0x00001100;
imm32 b2, 0x00001010;
imm32 b3, 0x00001001;
imm32 l0, 0x00000015;
imm32 l1, 0x00000016;
imm32 l2, 0x00000017;
imm32 l3, 0x00000018;
imm32 m0, 0x00000015;
imm32 m1, 0x00000016;
imm32 m2, 0x00000017;
imm32 m3, 0x00000018;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x00001102;
CHECKREG r2, 0x00001012;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001104;
CHECKREG r6, 0x00001014;
CHECKREG r7, 0x00001005;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x00001102;
CHECKREG r2, 0x00001012;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001000;
CHECKREG r5, 0x00001100;
CHECKREG r6, 0x00001010;
CHECKREG r7, 0x00001001;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001004;
CHECKREG r1, 0x00001104;
CHECKREG r2, 0x00001014;
CHECKREG r3, 0x00001005;
CHECKREG r4, 0x00001008;
CHECKREG r5, 0x00001108;
CHECKREG r6, 0x00001018;
CHECKREG r7, 0x00001009;
I0 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG r0, 0x00001000;
CHECKREG r1, 0x00001100;
CHECKREG r2, 0x00001010;
CHECKREG r3, 0x00001001;
CHECKREG r4, 0x00001008;
CHECKREG r5, 0x00001108;
CHECKREG r6, 0x00001018;
CHECKREG r7, 0x00001009;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001000;
CHECKREG r1, 0x00001100;
CHECKREG r2, 0x00001010;
CHECKREG r3, 0x00001001;
CHECKREG r4, 0x0000100D;
CHECKREG r5, 0x0000110E;
CHECKREG r6, 0x0000101F;
CHECKREG r7, 0x00001011;
pass
|
stsp/binutils-ia16
| 5,096
|
sim/testsuite/bfin/c_dsp32shift_fextx.s
|
//Original:/testcases/core/c_dsp32shift_fextx/c_dsp32shift_fextx.dsp
// Spec Reference: dsp32shift fext x
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x08000807;
R1 = EXTRACT( R1, R0.L ) (Z);
R2 = EXTRACT( R2, R0.L ) (Z);
R3 = EXTRACT( R3, R0.L ) (Z);
R4 = EXTRACT( R4, R0.L ) (X);
R5 = EXTRACT( R5, R0.L ) (Z);
R6 = EXTRACT( R6, R0.L ) (Z);
R7 = EXTRACT( R7, R0.L ) (X);
R0 = EXTRACT( R0, R0.L ) (Z);
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000002;
imm32 r2, 0x09000002;
imm32 r3, 0x09100003;
imm32 r4, 0x09020004;
imm32 r5, 0x09003005;
imm32 r6, 0x09000406;
imm32 r7, 0x09000057;
R0 = EXTRACT( R0, R1.L ) (Z);
R2 = EXTRACT( R2, R1.L ) (Z);
R3 = EXTRACT( R3, R1.L ) (Z);
R4 = EXTRACT( R4, R1.L ) (Z);
R5 = EXTRACT( R5, R1.L ) (X);
R6 = EXTRACT( R6, R1.L ) (Z);
R7 = EXTRACT( R7, R1.L ) (X);
R1 = EXTRACT( R1, R1.L ) (Z);
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000002;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a000010;
imm32 r4, 0x0a00e004;
imm32 r5, 0x0a00e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0a00e007;
R0 = EXTRACT( R0, R2.L ) (Z);
R1 = EXTRACT( R1, R2.L ) (Z);
R3 = EXTRACT( R3, R2.L ) (Z);
R4 = EXTRACT( R4, R2.L ) (Z);
R5 = EXTRACT( R5, R2.L ) (Z);
R6 = EXTRACT( R6, R2.L ) (Z);
R7 = EXTRACT( R7, R2.L ) (Z);
R2 = EXTRACT( R2, R2.L ) (Z);
CHECKREG r0, 0x00006001;
CHECKREG r1, 0x00006001;
CHECKREG r2, 0x0000000F;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00006004;
CHECKREG r5, 0x00006005;
CHECKREG r6, 0x00006006;
CHECKREG r7, 0x00006007;
imm32 r0, 0x0b00f001;
imm32 r1, 0x0b00f001;
imm32 r2, 0x0b00f002;
imm32 r3, 0x0b000010;
imm32 r4, 0x0b00f004;
imm32 r5, 0x0b00f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x0b00f007;
R0 = EXTRACT( R0, R3.L ) (Z);
R1 = EXTRACT( R1, R3.L ) (Z);
R2 = EXTRACT( R2, R3.L ) (X);
R4 = EXTRACT( R4, R3.L ) (Z);
R5 = EXTRACT( R5, R3.L ) (Z);
R6 = EXTRACT( R6, R3.L ) (X);
R7 = EXTRACT( R7, R3.L ) (Z);
R3 = EXTRACT( R3, R3.L ) (Z);
CHECKREG r0, 0x0000F001;
CHECKREG r1, 0x0000F001;
CHECKREG r2, 0xFFFFF002;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x0000F004;
CHECKREG r5, 0x0000F005;
CHECKREG r6, 0xFFFFF006;
CHECKREG r7, 0x0000F007;
imm32 r0, 0x0c0000c0;
imm32 r1, 0x0c0100c0;
imm32 r2, 0x0c0200c0;
imm32 r3, 0x0c0300c0;
imm32 r4, 0x0c04000c;
imm32 r5, 0x0c0500c0;
imm32 r6, 0x0c0600c0;
imm32 r7, 0x0c0700c0;
R0 = EXTRACT( R0, R4.L ) (Z);
R1 = EXTRACT( R1, R4.L ) (Z);
R2 = EXTRACT( R2, R4.L ) (Z);
R3 = EXTRACT( R3, R4.L ) (Z);
R5 = EXTRACT( R5, R4.L ) (X);
R6 = EXTRACT( R6, R4.L ) (Z);
R7 = EXTRACT( R7, R4.L ) (Z);
R4 = EXTRACT( R4, R4.L ) (Z);
CHECKREG r0, 0x000000C0;
CHECKREG r1, 0x000000C0;
CHECKREG r2, 0x000000C0;
CHECKREG r3, 0x000000C0;
CHECKREG r4, 0x0000000C;
CHECKREG r5, 0x000000C0;
CHECKREG r6, 0x000000C0;
CHECKREG r7, 0x000000C0;
imm32 r0, 0xa00100d0;
imm32 r1, 0xa00100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa0050007;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R0 = EXTRACT( R0, R5.L ) (Z);
R1 = EXTRACT( R1, R5.L ) (X);
R2 = EXTRACT( R2, R5.L ) (Z);
R3 = EXTRACT( R3, R5.L ) (Z);
R4 = EXTRACT( R4, R5.L ) (X);
R6 = EXTRACT( R6, R5.L ) (Z);
R7 = EXTRACT( R7, R5.L ) (Z);
R5 = EXTRACT( R5, R5.L ) (Z);
CHECKREG r0, 0x00000050;
CHECKREG r1, 0xFFFFFFD1;
CHECKREG r2, 0x00000050;
CHECKREG r3, 0x00000050;
CHECKREG r4, 0xFFFFFFD0;
CHECKREG r5, 0x00000007;
CHECKREG r6, 0x00000050;
CHECKREG r7, 0x00000050;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060009;
imm32 r7, 0xb0070000;
R0 = EXTRACT( R0, R6.L ) (Z);
R1 = EXTRACT( R1, R6.L ) (Z);
R2 = EXTRACT( R2, R6.L ) (Z);
R3 = EXTRACT( R3, R6.L ) (X);
R4 = EXTRACT( R4, R6.L ) (Z);
R5 = EXTRACT( R5, R6.L ) (Z);
R6 = EXTRACT( R6, R6.L ) (Z);
R7 = EXTRACT( R7, R6.L ) (Z);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x0000000F;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000009;
CHECKREG r7, 0x00000000;
imm32 r0, 0xd00100e0;
imm32 r1, 0xd00100e0;
imm32 r2, 0xd00200e0;
imm32 r3, 0xd00300e0;
imm32 r4, 0xd00400e0;
imm32 r5, 0xd00500e0;
imm32 r6, 0xd00600e0;
imm32 r7, 0xd0070023;
R1 = EXTRACT( R0, R7.L ) (Z);
R2 = EXTRACT( R1, R7.L ) (Z);
R3 = EXTRACT( R2, R7.L ) (Z);
R4 = EXTRACT( R3, R7.L ) (Z);
R5 = EXTRACT( R4, R7.L ) (X);
R6 = EXTRACT( R5, R7.L ) (Z);
R7 = EXTRACT( R6, R7.L ) (X);
R0 = EXTRACT( R7, R7.L ) (Z);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 1,549
|
sim/testsuite/bfin/s12.s
|
// Shifter test program.
// Test instructions
// RL5 = EXPADJ R4 BY RL2;
# mach: bfin
.include "testutils.inc"
start
R0.L = 30; // large norm of small value
R0.H = 1; // make sure high half is not used
R1.L = 0x0000;
R1.H = 0x1000; // small norm (2) of large value
R7.L = EXPADJ( R1 , R0.L );
DBGA ( R7.L , 0x0002 );
R0.L = 3; // small norm of large value
R0.H = 1; // make sure high half is not used
R1.L = 0x0000;
R1.H = 0xff00; // small norm (2) of large value
R7.L = EXPADJ( R1 , R0.L );
DBGA ( R7.L , 0x0003 );
R0.L = 3;
R0.H = 1;
R1.L = 0xffff;
R1.H = 0xffff;
R7.L = EXPADJ( R1 , R0.L );
DBGA ( R7.L , 0x0003 );
R0.L = 31;
R0.H = 1;
R1.L = 0x0000; // norm=0
R1.H = 0x8000;
R7.L = EXPADJ( R1 , R0.L );
DBGA ( R7.L , 0x0000 );
// RL5 = EXPADJ/EXPADJ R4 BY RL2;
R0.L = 15;
R1.L = 0x0800;
R1.H = 0x1000;
R7.L = EXPADJ( R1 , R0.L ) (V);
DBGA ( R7.L , 0x0002 );
R0.L = 15;
R1.L = 0x1000;
R1.H = 0x0800;
R7.L = EXPADJ( R1 , R0.L ) (V);
DBGA ( R7.L , 0x0002 );
R0.L = 1;
R1.L = 0x0800;
R1.H = 0x1000;
R7.L = EXPADJ( R1 , R0.L ) (V);
DBGA ( R7.L , 0x0001 );
R0.L = 14;
R1.L = 0xff00;
R1.H = 0xfff0;
R7.L = EXPADJ( R1 , R0.L ) (V);
DBGA ( R7.L , 0x0007 );
// RL5 = EXPADJ RL4 BY RL2;
R0.L = 14;
R1.L = 0xff00;
R1.H = 0x1000;
R7.L = EXPADJ( R1.L , R0.L );
DBGA ( R7.L , 0x0007 );
R0.L = 3;
R1.L = 0xff00;
R1.H = 0x1000;
R7.L = EXPADJ( R1.L , R0.L );
DBGA ( R7.L , 0x0003 );
R0.L = 14;
R1.L = 0x1000;
R1.H = 0xff00;
R7.L = EXPADJ( R1.H , R0.L );
DBGA ( R7.L , 0x0007 );
pass
|
stsp/binutils-ia16
| 8,708
|
sim/testsuite/bfin/c_ldstiifp_ld_preg.s
|
//Original:testcases/core/c_ldstiifp_ld_preg/c_ldstiifp_ld_preg.dsp
// Spec Reference: c_ldstiifp load preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P3 = I1; SP = I3;
p1 = [ fp + 0 ];
P2 = [ FP + -4 ];
P3 = [ FP + -8 ];
P4 = [ FP + -12 ];
P5 = [ FP + -16 ];
SP = [ FP + -20 ];
FP = [ FP + -24 ];
CHECKREG p1, 0x86878889;
CHECKREG p2, 0x82838485;
CHECKREG p3, 0x74757677;
CHECKREG p4, 0x99717273;
CHECKREG p5, 0x55667788;
CHECKREG sp, 0x11223344;
CHECKREG fp, 0x1C1D1E1F;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P1 = [ FP + -28 ];
P2 = [ FP + -32 ];
P3 = [ FP + -36 ];
P4 = [ FP + -40 ];
P5 = [ FP + -44 ];
SP = [ FP + -48 ];
FP = [ FP + -52 ];
CHECKREG p1, 0x18191A1B;
CHECKREG p2, 0x14151617;
CHECKREG p3, 0x10111213;
CHECKREG p4, 0x0C0D0E0F;
CHECKREG p5, 0x08090A0B;
CHECKREG sp, 0x04050607;
CHECKREG fp, 0x00010203;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P1 = [ FP + -56 ];
P2 = [ FP + -60 ];
P3 = [ FP + -64 ];
P4 = [ FP + -68 ];
P5 = [ FP + -72 ];
SP = [ FP + -76 ];
FP = [ FP + -80 ];
CHECKREG p1, 0x76676867;
CHECKREG p2, 0x72636467;
CHECKREG p3, 0x78596067;
CHECKREG p4, 0x74555657;
CHECKREG p5, 0x66676869;
CHECKREG sp, 0x62636465;
CHECKREG fp, 0x58596061;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P1 = [ FP + -84 ];
P2 = [ FP + -88 ];
P3 = [ FP + -92 ];
P4 = [ FP + -96 ];
P5 = [ FP + -100 ];
SP = [ FP + -104 ];
FP = [ FP + -108 ];
CHECKREG p1, 0x54555657;
CHECKREG p2, 0x50515253;
CHECKREG p3, 0x46474849;
CHECKREG p4, 0x42434445;
CHECKREG p5, 0x38394041;
CHECKREG sp, 0x34353637;
CHECKREG fp, 0x30313233;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P1 = [ FP + -112 ];
P2 = [ FP + -116 ];
P3 = [ FP + -120 ];
P4 = [ FP + -124 ];
P5 = [ FP + -128 ];
SP = [ FP + -4 ];
FP = [ FP + -8 ];
CHECKREG p1, 0x26272829;
CHECKREG p2, 0x22232425;
CHECKREG p3, 0x18192021;
CHECKREG p4, 0x14151617;
CHECKREG p5, 0x09101112;
CHECKREG sp, 0x82838485;
CHECKREG fp, 0x74757677;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 3,298
|
sim/testsuite/bfin/c_loopsetup_preg_stld.s
|
//Original:/testcases/core/c_loopsetup_preg_stld/c_loopsetup_preg_stld.dsp
// Spec Reference: loopsetup preg st & ld
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
A0 = 0;
A1 = 0;
ASTAT = r0;
P1 = 9;
P2 = 8;
P0 = 7;
P4 = 6;
P5 = 5;
FP = 3;
imm32 r0, 0x00200005;
imm32 r1, 0x00300010;
imm32 r2, 0x00500012;
imm32 r3, 0x00600024;
imm32 r4, 0x00700016;
imm32 r5, 0x00900028;
imm32 r6, 0x0a000030;
imm32 r7, 0x00b00044;
loadsym I0, DATA0;
loadsym I1, DATA1;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
LSETUP ( start1 , end1 ) LC0 = P1;
start1:
R0 += 1;
R1 += 2;
A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
end1:
R2 += 3;
R3 = ( A0 += A1 );
A0 = 0;
A1 = 0;
LSETUP ( start2 , end2 ) LC0 = P2;
start2:
R4 += 4;
A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 -- ] || R1 = [ I1 -- ];
end2:
R5 += -5;
R6 = ( A0 += A1 );
CHECKREG r0, 0x000D0003;
CHECKREG r1, 0x00C00103;
CHECKREG r2, 0x0050002D;
CHECKREG r3, 0x00010794;
CHECKREG r4, 0x00700036;
CHECKREG r5, 0x00900000;
CHECKREG r6, 0x00011388;
CHECKREG r7, 0x00B00044;
imm32 r0, 0x01200805;
imm32 r1, 0x02300710;
imm32 r2, 0x03500612;
imm32 r3, 0x04600524;
imm32 r4, 0x05700416;
imm32 r5, 0x06900328;
imm32 r6, 0x0a700230;
imm32 r7, 0x08b00044;
loadsym I2, DATA0;
loadsym I3, DATA1;
[ I2 ++ ] = R0;
[ I3 ++ ] = R1;
LSETUP ( start3 , end3 ) LC0 = P1;
start3:
[ I2 ++ ] = R2;
[ I3 ++ ] = R3;
R2 += 1;
end3:
R3 += 1;
A0 = 0;
A1 = 0;
LSETUP ( start4 , end4 ) LC0 = P2;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
start4:
A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I2 -- ] || R1 = [ I3 -- ];
R4 = R4 + R0; // comp3op
end4:
R5 = R5 + R1;
R6 = ( A0 += A1 );
CHECKREG r0, 0x03500614;
CHECKREG r1, 0x04600526;
CHECKREG r2, 0x0350061B;
CHECKREG r3, 0x0460052D;
CHECKREG r4, 0x1CF02EC1;
CHECKREG r5, 0x25602851;
CHECKREG r6, 0x0282F220;
CHECKREG r7, 0x08B00044;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
.dd 0x001d0003
.dd 0x00010004
.dd 0x00010005
.dd 0x02100006
.dd 0x02200007
.dd 0x02300008
.dd 0x02200009
.dd 0x0250000a
.dd 0x0260000b
.dd 0x0270000c
.dd 0x0280000d
.dd 0x0290000e
.dd 0x2100000f
.dd 0x22000010
.dd 0x22000011
.dd 0x24000012
.dd 0x25000013
.dd 0x26000014
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
.dd 0x00b00104
.dd 0x00a00105
.dd 0x00900106
.dd 0x00800107
.dd 0x00100108
.dd 0x00200109
.dd 0x0030010a
.dd 0x0040010b
.dd 0x0050011c
.dd 0x0060010d
.dd 0x0070010e
.dd 0x0080010f
.dd 0x00900110
.dd 0x01000111
.dd 0x02000112
.dd 0x03000113
.dd 0x04000114
.dd 0x05000115
.dd 0x03f00100
.dd 0x03e00101
.dd 0x03d00102
.dd 0x03c00103
.dd 0x03b00104
.dd 0x03a00105
.dd 0x03900106
.dd 0x03800107
.dd 0x03100108
.dd 0x03200109
.dd 0x0330010a
.dd 0x0330010b
.dd 0x0350011c
.dd 0x0360010d
.dd 0x0370010e
.dd 0x0380010f
.dd 0x03900110
.dd 0x31000111
.dd 0x32000112
.dd 0x33000113
.dd 0x34000114
|
stsp/binutils-ia16
| 7,480
|
sim/testsuite/bfin/c_seq_ex2_raise_mmr_mvpop.S
|
//Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmr_mvpop/c_seq_ex2_raise_mmr_mvpop.dsp
// Spec Reference: sequencer stage ex2 (raise+ mmr + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
// [--sp] = (r7-r0);
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
LD32(r0, 0x55552345);
RAISE 2; // RTN
[ P1 ] = R0;
// jump LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
CSYNC;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
RAISE 6; // RTI
R0 = [ P1 ];
// jump LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000024);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x00000027);
CHECKREG(r7, 0x00000028);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
RAISE 8; // RTI
R0 = [ P1 ];
// jump LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
CSYNC;
CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped
CHECKREG(r1, 0x00000012); // so they cannot appear here
CHECKREG(r2, 0x00000013);
CHECKREG(r3, 0x00000013);
CHECKREG(r4, 0x00000015);
CHECKREG(r5, 0x00000016);
CHECKREG(r6, 0x00000017);
CHECKREG(r7, 0x00000018);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
//CHECKREG(r0, 0x55552345);
RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 3,574
|
sim/testsuite/bfin/s16.s
|
// reg-based SHIFT test program.
# mach: bfin
.include "testutils.inc"
start
// Test FDEP with no sign extension
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c08; // pos=12 len=8
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x123f );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c04; // pos=12 len=4
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x1234 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c05; // pos=12 len=5
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x1235 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0010; // pos=0 len=16
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x1234 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0011; // pos=0 len=17
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x1234 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0114; // pos=1 len=20
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x1235 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x001f; // pos=0 len=31
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x1234 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x1c04; // pos=28 len=4
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xdead );
DBGA ( R7.H , 0xf234 );
R0.L = 0xdead;
R0.H = 0x0234;
R1.L = 0x1d04; // pos=29 len=4
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xdead );
DBGA ( R7.H , 0xe234 );
R0.L = 0xdead;
R0.H = 0x0234;
R1.L = 0x1f04; // pos=31 len=4
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xdead );
DBGA ( R7.H , 0x8234 );
R0.L = 0xdead;
R0.H = 0x0234;
R1.L = 0x2004; // pos=32 len=4, same as pos=0 len=4
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xdeaf );
DBGA ( R7.H , 0x0234 );
// Test FDEP with sign extension
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c08; // pos=12 len=8
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c08; // pos=12 len=8
R1.H = 0x007f;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x0007 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0110; // pos=1 len=16
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0xfffe );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0101; // pos=1 len=1
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0xfffe );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0102; // pos=1 len=2
R1.H = 0x0001;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0x0002 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0002; // pos=0 len=2
R1.H = 0x0001;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0000; // pos=0 len=0
R1.H = 0x000f;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
pass
|
stsp/binutils-ia16
| 6,097
|
sim/testsuite/bfin/c_dsp32mult_dr_iu.s
|
//Original:/testcases/core/c_dsp32mult_dr_iu/c_dsp32mult_dr_iu.dsp
// Spec Reference: dsp32mult single dr iu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00010002;
imm32 r1, 0x00023004;
imm32 r2, 0x03843725;
imm32 r3, 0x00084027;
imm32 r4, 0x00ab5d29;
imm32 r5, 0x00ac682b;
imm32 r6, 0x000c708d;
imm32 r7, 0x02462028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IU);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IU);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IU);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IU);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IU);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IU);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IU);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IU);
CHECKREG r0, 0x00040004;
CHECKREG r1, 0xC0100008;
CHECKREG r2, 0x0020FFFF;
CHECKREG r3, 0x0040FFFF;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x60080004;
CHECKREG r6, 0x60080004;
CHECKREG r7, 0xFFFF0004;
imm32 r0, 0x00230635;
imm32 r1, 0x00995137;
imm32 r2, 0x00240735;
imm32 r3, 0x00060037;
imm32 r4, 0x009b0239;
imm32 r5, 0x00a9933b;
imm32 r6, 0x000c093d;
imm32 r7, 0x12407093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IU);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IU);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IU);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IU);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IU);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IU);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IU);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0x2B3E00D8;
CHECKREG r6, 0xFFFF07BC;
CHECKREG r7, 0x014A014A;
imm32 r0, 0x09235655;
imm32 r1, 0x09ba5157;
imm32 r2, 0x03246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x00ab6509;
imm32 r5, 0x00ac7f5b;
imm32 r6, 0x000a005d;
imm32 r7, 0x0246405f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IU);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IU);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IU);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IU);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IU);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IU);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IU);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFF7390;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x00230666;
imm32 r1, 0x00ba0166;
imm32 r2, 0x00240766;
imm32 r3, 0x00060066;
imm32 r4, 0x03ab0d69;
imm32 r5, 0x10ec3f6b;
imm32 r6, 0x000e206d;
imm32 r7, 0x00460e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IU);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IU);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IU);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IU);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IU);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IU);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IU);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IU);
CHECKREG r0, 0x00C4FFFF;
CHECKREG r1, 0x03D4FFFF;
CHECKREG r2, 0x03D4FFFF;
CHECKREG r3, 0x13241324;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00C4FFFF;
CHECKREG r7, 0x3598FFFF;
// mix order
imm32 r0, 0x0023a675;
imm32 r1, 0x00ba5127;
imm32 r2, 0x00c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x00accd09;
imm32 r5, 0x00acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x0246fc0f;
R0.H = R0.L * R7.H, R0.L = R0.H * R7.H (IU);
R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IU);
R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IU);
R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IU);
R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IU);
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IU);
R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IU);
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IU);
CHECKREG r0, 0xFFFF4F92;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x00230a75;
imm32 r1, 0x00ba0127;
imm32 r2, 0x00240905;
imm32 r3, 0x00d60007;
imm32 r4, 0x00ab0d09;
imm32 r5, 0x00ac0ddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x0046000f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IU);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IU);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IU);
R3.H = R4.L * R3.H, R3.L = R4.H * R3.H (IU);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IU);
R5.H = R2.H * R5.L, R5.L = R2.L * R5.H (IU);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IU);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IU);
CHECKREG r0, 0x0992FFFF;
CHECKREG r1, 0x08B8FFFF;
CHECKREG r2, 0x1830FFFF;
CHECKREG r3, 0xFFFF8EF2;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x68A0FFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x0b230675;
imm32 r1, 0x00ba0127;
imm32 r2, 0x03f40705;
imm32 r3, 0x000f0007;
imm32 r4, 0x00ab0d09;
imm32 r5, 0x10ac0fdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246000f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IU);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IU);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IU);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IU);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IU);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IU);
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFF4D7C;
CHECKREG r3, 0xFFFF0AE6;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x002d0675;
imm32 r1, 0x001a0027;
imm32 r2, 0x00240005;
imm32 r3, 0x000600d7;
imm32 r4, 0x008b0d09;
imm32 r5, 0x00a0000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x0006060f;
R3.H = R0.L * R2.L, R3.L = R0.L * R2.H (IU);
R4.H = R1.H * R3.L, R4.L = R1.H * R3.H (IU);
R5.H = R2.L * R4.L, R5.L = R2.L * R4.H (IU);
R6.H = R3.L * R5.H, R6.L = R3.L * R5.L (IU);
R0.H = R4.H * R6.L, R0.L = R4.H * R6.L (IU);
R1.H = R5.L * R7.H, R1.L = R5.H * R7.L (IU);
R2.H = R6.L * R0.L, R2.L = R6.L * R0.H (IU);
R7.H = R7.H * R1.L, R7.L = R7.L * R1.H (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0x2049E874;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
pass
|
stsp/binutils-ia16
| 6,095
|
sim/testsuite/bfin/c_interr_nmi.S
|
//Original:/proj/frio/dv/testcases/core/c_interr_nmi/c_interr_nmi.dsp
// Spec Reference: progctrl raise rti rtn
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
RAISE 2; // RTN
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
RAISE 15; // RTI
CHECKREG(r0, 0x0000000B);
CHECKREG(r1, 0x0000001A);
CHECKREG(r2, 0x00000024);
CHECKREG(r3, 0x00000028);
CHECKREG(r4, 0x0000000E);
CHECKREG(r5, 0x00000010);
CHECKREG(r6, 0x00000012);
CHECKREG(r7, 0x00000014);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
CHECKREG(r0, 0x0000000B);
CHECKREG(r1, 0x0000000E);
CHECKREG(r2, 0x00000017);
CHECKREG(r3, 0x0000001A);
CHECKREG(r4, 0x0000000E);
( R7:0 ) = [ SP ++ ]; // pop
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 += 1;
R1 += 2;
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
RAISE 15; // RTI
[ -- SP ] = ( R7:0 ); // push
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
R2 += 5;
RTI;
THANDLE: // Timer Handler 6
R3 += 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 += 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 += 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 += 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 += 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 += 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 += 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 += 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 += 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 6,609
|
sim/testsuite/bfin/c_dspldst_ld_drhi_ipp.s
|
//Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp
// Spec Reference: c_dspldst ld_drhi_i++/--
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_R_REGS 0;
// initial values
//i0=0x3000;
//i1=0x4000;
//i2=0x5000;
//i3=0x6000;
loadsym I0, DATA_ADDR_3;
loadsym I1, DATA_ADDR_4;
loadsym I2, DATA_ADDR_5;
loadsym I3, DATA_ADDR_6;
// Load Upper half of Dregs
R0.H = W [ I0 ++ ];
R1.H = W [ I1 ++ ];
R2.H = W [ I2 ++ ];
R3.H = W [ I3 ++ ];
R4.H = W [ I0 ++ ];
R5.H = W [ I1 ++ ];
R6.H = W [ I2 ++ ];
R7.H = W [ I3 ++ ];
CHECKREG r0, 0x02030000;
CHECKREG r1, 0x22230000;
CHECKREG r2, 0x42430000;
CHECKREG r3, 0x62630000;
CHECKREG r4, 0x00010000;
CHECKREG r5, 0x20210000;
CHECKREG r6, 0x40410000;
CHECKREG r7, 0x60610000;
R1.H = W [ I0 ++ ];
R2.H = W [ I1 ++ ];
R3.H = W [ I2 ++ ];
R4.H = W [ I3 ++ ];
R5.H = W [ I0 ++ ];
R6.H = W [ I1 ++ ];
R7.H = W [ I2 ++ ];
R0.H = W [ I3 ++ ];
CHECKREG r0, 0x64650000;
CHECKREG r1, 0x06070000;
CHECKREG r2, 0x26270000;
CHECKREG r3, 0x46470000;
CHECKREG r4, 0x66670000;
CHECKREG r5, 0x04050000;
CHECKREG r6, 0x24250000;
CHECKREG r7, 0x44450000;
R2.H = W [ I0 ++ ];
R3.H = W [ I1 ++ ];
R4.H = W [ I2 ++ ];
R5.H = W [ I3 ++ ];
R6.H = W [ I0 ++ ];
R7.H = W [ I1 ++ ];
R0.H = W [ I2 ++ ];
R1.H = W [ I3 ++ ];
CHECKREG r0, 0x48490000;
CHECKREG r1, 0x68690000;
CHECKREG r2, 0x0A0B0000;
CHECKREG r3, 0x2A2B0000;
CHECKREG r4, 0x4A4B0000;
CHECKREG r5, 0x6A6B0000;
CHECKREG r6, 0x08090000;
CHECKREG r7, 0x28290000;
R3.H = W [ I0 ++ ];
R4.H = W [ I1 ++ ];
R5.H = W [ I2 ++ ];
R6.H = W [ I3 ++ ];
R7.H = W [ I0 ++ ];
R0.H = W [ I1 ++ ];
R1.H = W [ I2 ++ ];
R2.H = W [ I3 ++ ];
CHECKREG r0, 0x2C2D0000;
CHECKREG r1, 0x4C4D0000;
CHECKREG r2, 0x6C6D0000;
CHECKREG r3, 0x0E0F0000;
CHECKREG r4, 0x2E2F0000;
CHECKREG r5, 0x4E4F0000;
CHECKREG r6, 0x6E6F0000;
CHECKREG r7, 0x0C0D0000;
// reverse to minus mninus i--
// Load Upper half of Dregs
R0.H = W [ I0 -- ];
R1.H = W [ I1 -- ];
R2.H = W [ I2 -- ];
R3.H = W [ I3 -- ];
R4.H = W [ I0 -- ];
R5.H = W [ I1 -- ];
R6.H = W [ I2 -- ];
R7.H = W [ I3 -- ];
CHECKREG r0, 0x12130000;
CHECKREG r1, 0x32330000;
CHECKREG r2, 0x52530000;
CHECKREG r3, 0x72730000;
CHECKREG r4, 0x0C0D0000;
CHECKREG r5, 0x2C2D0000;
CHECKREG r6, 0x4C4D0000;
CHECKREG r7, 0x6C6D0000;
R1.H = W [ I0 -- ];
R2.H = W [ I1 -- ];
R3.H = W [ I2 -- ];
R4.H = W [ I3 -- ];
R5.H = W [ I0 -- ];
R6.H = W [ I1 -- ];
R7.H = W [ I2 -- ];
R0.H = W [ I3 -- ];
CHECKREG r0, 0x68690000;
CHECKREG r1, 0x0E0F0000;
CHECKREG r2, 0x2E2F0000;
CHECKREG r3, 0x4E4F0000;
CHECKREG r4, 0x6E6F0000;
CHECKREG r5, 0x08090000;
CHECKREG r6, 0x28290000;
CHECKREG r7, 0x48490000;
R2.H = W [ I0 -- ];
R3.H = W [ I1 -- ];
R4.H = W [ I2 -- ];
R5.H = W [ I3 -- ];
R6.H = W [ I0 -- ];
R7.H = W [ I1 -- ];
R0.H = W [ I2 -- ];
R1.H = W [ I3 -- ];
CHECKREG r0, 0x44450000;
CHECKREG r1, 0x64650000;
CHECKREG r2, 0x0A0B0000;
CHECKREG r3, 0x2A2B0000;
CHECKREG r4, 0x4A4B0000;
CHECKREG r5, 0x6A6B0000;
CHECKREG r6, 0x04050000;
CHECKREG r7, 0x24250000;
R3.H = W [ I0 -- ];
R4.H = W [ I1 -- ];
R5.H = W [ I2 -- ];
R6.H = W [ I3 -- ];
R7.H = W [ I0 -- ];
R0.H = W [ I1 -- ];
R1.H = W [ I2 -- ];
R2.H = W [ I3 -- ];
CHECKREG r0, 0x20210000;
CHECKREG r1, 0x40410000;
CHECKREG r2, 0x60610000;
CHECKREG r3, 0x06070000;
CHECKREG r4, 0x26270000;
CHECKREG r5, 0x46470000;
CHECKREG r6, 0x66670000;
CHECKREG r7, 0x00010000;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xBC0DBE26
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 6,340
|
sim/testsuite/bfin/se_usermode_protviol.S
|
//Original:/proj/frio/dv/testcases/seq/se_usermode_protviol/se_usermode_protviol.dsp
// Description: User mode "Illegal Use Supervsor Resource" Exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x100 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
RETI = r0; // prevent Xs later on
RETX = r0;
RETN = r0;
RETE = r0;
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the user stack pointer
FP = SP;
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
// [--sp] = RETI; // enable interrupts in supervisor mode
R0 = 0;
R1 = -1;
// the following instructions should EXCEPT
R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervidor Resource
RAISE 15;
CLI R0;
STI r0;
// TESTSET (p0); // now allowed in user mode
r5 += 1;
// IDLE; // works in user mode
USP = r1;
SEQSTAT = r1;
SYSCFG = r1;
RETI = r1;
RETX = r1;
RETN = r1;
RETE = r1;
R2 = USP;
R2 = SEQSTAT;
R2 = SYSCFG;
R2 = RETI;
R2 = RETX;
R2 = RETN;
R2 = RETE;
[ -- SP ] = USP;
[ -- SP ] = SEQSTAT;
[ -- SP ] = SYSCFG;
[ -- SP ] = RETI;
[ -- SP ] = RETX;
[ -- SP ] = RETN;
[ -- SP ] = RETE;
SEQSTAT = [sp++];
SYSCFG = [sp++];
RETI = [sp++];
RETX = [sp++];
RETN = [sp++];
RETE = [sp++];
RTX;
RTN;
RTI;
RTE;
R6 = 0x22; // EXCAUSE 0x22 means Illegal Insn Combination
USP = [sp++];
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x2B;
CHECKREG(r5, 36); // count of all IF protection violations.
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
CC = r7 == r6;
IF CC JUMP IFETCHPROTVIOL; // If EXCAUSE != 0x2E then leave
dbg_fail; // if the EXCAUSE is wrong the test will infinite loop
IFETCHPROTVIOL:
R7 = RETX; // Fix up return address
R7 += 2; // skip instruction
RETX = r7; // and put back in RETX
R5 += 1; // Count
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
stsp/binutils-ia16
| 6,303
|
sim/testsuite/bfin/c_dsp32mac_pair_a0_s.s
|
//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_s/c_dsp32mac_pair_a0_s.dsp
// Spec Reference: dsp32mac pair a0 S
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (S2RND);
P1 = A0.w;
A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (S2RND);
P2 = A0.w;
A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (S2RND);
P3 = A0.w;
A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (S2RND);
P4 = A0.w;
CHECKREG r0, 0xFFF66AF0;
CHECKREG r1, 0x86BCFEC7;
CHECKREG r2, 0xE59E6B30;
CHECKREG r3, 0x00860007;
CHECKREG r4, 0xD4A4A0C0;
CHECKREG r5, 0x1235860B;
CHECKREG r6, 0x01BBC454;
CHECKREG r7, 0x678E0086;
CHECKREG p1, 0x00DDE22A;
CHECKREG p2, 0xFFFB3578;
CHECKREG p3, 0xF2CF3598;
CHECKREG p4, 0xEA525060;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (S2RND);
P1 = A0.w;
A1 = R2.L * R3.H, R0 = ( A0 = R2.H * R3.L ) (S2RND);
P2 = A0.w;
A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (S2RND);
P3 = A0.w;
A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (S2RND);
P4 = A0.w;
CHECKREG r0, 0xFC6CC6B8;
CHECKREG r1, 0xA1BCF4C7;
CHECKREG r2, 0xFC3DDA60;
CHECKREG r3, 0x00010005;
CHECKREG r4, 0xF2E4F3AC;
CHECKREG r5, 0x1235010B;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xF97279D6;
CHECKREG p2, 0xFFFC4AC8;
CHECKREG p3, 0xFE1EED30;
CHECKREG p4, 0xFE36635C;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (S2RND);
P1 = A0.w;
A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (S2RND);
P2 = A0.w;
A1 = R4.H * R5.L, R0 = ( A0 -= R4.H * R5.H ) (S2RND);
P3 = A0.w;
A1 += R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (S2RND);
P4 = A0.w;
CHECKREG r0, 0xE314ECC0;
CHECKREG r1, 0xABD69EC7;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x7B7B2740;
CHECKREG r5, 0x1225010B;
CHECKREG r6, 0x000C5E30;
CHECKREG r7, 0x678E0561;
CHECKREG p1, 0x33165D46;
CHECKREG p2, 0x00062F18;
CHECKREG p3, 0xF18A7660;
CHECKREG p4, 0x3DBD93A0;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (S2RND);
P1 = A0.w;
A1 -= R2.H * R1.H, R2 = ( A0 = R2.H * R1.L ) (S2RND);
P2 = A0.w;
A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (S2RND);
P3 = A0.w;
A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (S2RND);
P4 = A0.w;
CHECKREG r0, 0xFFF3DD34;
CHECKREG r1, 0x91BCFEC7;
CHECKREG r2, 0x01A91A30;
CHECKREG r3, 0xD0910007;
CHECKREG r4, 0x01940118;
CHECKREG r5, 0xD235910B;
CHECKREG r6, 0x01CD1598;
CHECKREG r7, 0x67DE0009;
CHECKREG p1, 0xFFF9EE9A;
CHECKREG p2, 0x00D48D18;
CHECKREG p3, 0x00CA008C;
CHECKREG p4, 0x00E68ACC;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (S2RND);
P5 = A1.w;
P1 = A0.w;
A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (S2RND);
P2 = A0.w;
A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (S2RND);
P3 = A0.w;
A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (S2RND);
P4 = A0.w;
CHECKREG r0, 0xFFF66AF0;
CHECKREG r1, 0x86BCFEC7;
CHECKREG r2, 0xE59E6B30;
CHECKREG r3, 0x00860007;
CHECKREG r4, 0xF69835A0;
CHECKREG r5, 0x1235860B;
CHECKREG r6, 0xFE443BAC;
CHECKREG r7, 0x678E0086;
CHECKREG p1, 0xFF221DD6;
CHECKREG p2, 0xFFFB3578;
CHECKREG p3, 0xF2CF3598;
CHECKREG p4, 0xFB4C1AD0;
CHECKREG p5, 0xFFAFB03F;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R4 = ( A0 = R1.L * R0.L ) (S2RND);
P1 = A0.w;
R0 = ( A0 = R2.H * R3.L ) (S2RND);
P2 = A0.w;
R2 = ( A0 -= R4.H * R5.H ) (S2RND);
P3 = A0.w;
R0 = ( A0 += R6.L * R7.H ) (S2RND);
P4 = A0.w;
CHECKREG r0, 0x03E23D18;
CHECKREG r1, 0xA1BCF4C7;
CHECKREG r2, 0x03B350C0;
CHECKREG r3, 0x00010005;
CHECKREG r4, 0xF2E4F3AC;
CHECKREG r5, 0x1235010B;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xF97279D6;
CHECKREG p2, 0xFFFC4AC8;
CHECKREG p3, 0x01D9A860;
CHECKREG p4, 0x01F11E8C;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (S2RND);
P1 = A0.w;
R6 = ( A0 = R2.H * R3.L ) (S2RND);
P2 = A0.w;
A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (S2RND);
P3 = A0.w;
R4 = ( A0 += R6.L * R7.H ) (S2RND);
P4 = A0.w;
CHECKREG r0, 0xE2113B30;
CHECKREG r1, 0xABD69EC7;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x7A7775B0;
CHECKREG r5, 0x1225010B;
CHECKREG r6, 0x000C5E30;
CHECKREG r7, 0x678E0561;
CHECKREG p1, 0xCB200616;
CHECKREG p2, 0x00062F18;
CHECKREG p3, 0xF1089D98;
CHECKREG p4, 0x3D3BBAD8;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R0 = ( A0 -= R5.L * R3.L ) (S2RND);
P1 = A0.w;
A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (S2RND);
P2 = A0.w;
A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (S2RND);
P3 = A0.w;
R6 = ( A0 += R4.L * R6.H ) (S2RND);
P4 = A0.w;
CHECKREG r0, 0x7A83987C;
CHECKREG r1, 0x91BCFEC7;
CHECKREG r2, 0x01A91A30;
CHECKREG r3, 0xD0910007;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0xD235910B;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x67DE0009;
CHECKREG p1, 0x3D41CC3E;
CHECKREG p2, 0x00D48D18;
CHECKREG p3, 0x9D6AA7E4;
CHECKREG p4, 0x9D6AA7E4;
pass
|
stsp/binutils-ia16
| 5,914
|
sim/testsuite/bfin/c_dsp32alu_rh_p.s
|
//Original:/testcases/core/c_dsp32alu_rh_p/c_dsp32alu_rh_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34645515;
imm32 r3, 0x46667717;
imm32 r4, 0xd678891b;
imm32 r5, 0x6e89ab1d;
imm32 r6, 0x74b45515;
imm32 r7, 0x866cc777;
R0.H = R0.L + R0.L (NS);
R1.H = R0.L + R1.H (NS);
R2.H = R0.H + R2.L (NS);
R3.H = R0.H + R3.H (NS);
R4.H = R0.L + R4.L (NS);
R5.H = R0.L + R5.H (NS);
R6.H = R0.H + R6.L (NS);
R7.H = R0.H + R7.H (NS);
CHECKREG r4, 0x122C891B;
CHECKREG r5, 0xF79AAB1D;
CHECKREG r6, 0x67375515;
CHECKREG r7, 0x988EC777;
CHECKREG r4, 0x122C891B;
CHECKREG r5, 0xF79AAB1D;
CHECKREG r6, 0x67375515;
CHECKREG r7, 0x988EC777;
imm32 r0, 0x12348911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34f45515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567b891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0x86667a77;
R0.H = R1.L + R0.L (NS);
R1.H = R1.L + R1.H (NS);
R2.H = R1.H + R2.L (NS);
R3.H = R1.H + R3.H (NS);
R4.H = R1.L + R4.L (NS);
R5.H = R1.L + R5.H (NS);
R6.H = R1.H + R6.L (NS);
R7.H = R1.H + R7.H (NS);
CHECKREG r4, 0x3438891B;
CHECKREG r5, 0x12A6AB1D;
CHECKREG r6, 0x8EBBB515;
CHECKREG r7, 0x600C7A77;
CHECKREG r4, 0x3438891B;
CHECKREG r5, 0x12A6AB1D;
CHECKREG r6, 0x8EBBB515;
CHECKREG r7, 0x600C7A77;
imm32 r0, 0x85678911;
imm32 r1, 0x3989ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5e78891b;
imm32 r5, 0x67d9ab1d;
imm32 r6, 0x744b5515;
imm32 r7, 0x86668777;
R0.H = R2.L + R0.L (NS);
R1.H = R2.L + R1.H (NS);
R2.H = R2.H + R2.L (NS);
R3.H = R2.H + R3.H (NS);
R4.H = R2.L + R4.L (NS);
R5.H = R2.L + R5.H (NS);
R6.H = R2.H + R6.L (NS);
R7.L = R2.H + R7.H (NS);
CHECKREG r4, 0xDE30891B;
CHECKREG r5, 0xBCEEAB1D;
CHECKREG r6, 0xDE6E5515;
CHECKREG r7, 0x86660FBF;
CHECKREG r4, 0xDE30891B;
CHECKREG r5, 0xBCEEAB1D;
CHECKREG r6, 0xDE6E5515;
CHECKREG r7, 0x86660FBF;
imm32 r0, 0x25678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3e445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567f891b;
imm32 r5, 0x6789bb1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667b77;
R0.H = R3.L + R0.L (NS);
R1.H = R3.L + R1.H (NS);
R2.H = R3.H + R2.L (NS);
R3.H = R3.H + R3.H (NS);
R4.H = R3.L + R4.L (NS);
R5.H = R3.L + R5.H (NS);
R6.H = R3.H + R6.L (NS);
R7.H = R3.H + R7.H (NS);
CHECKREG r4, 0x0032891B;
CHECKREG r5, 0xDEA0BB1D;
CHECKREG r6, 0xE2C15515;
CHECKREG r7, 0x14127B77;
CHECKREG r4, 0x0032891B;
CHECKREG r5, 0xDEA0BB1D;
CHECKREG r6, 0xE2C15515;
CHECKREG r7, 0x14127B77;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R4.L + R0.L (NS);
R1.H = R4.L + R1.H (NS);
R2.H = R4.H + R2.L (NS);
R3.H = R4.H + R3.H (NS);
R4.H = R4.L + R4.L (NS);
R5.H = R4.L + R5.H (NS);
R6.H = R4.H + R6.L (NS);
R7.H = R4.H + R7.H (NS);
CHECKREG r4, 0x1236891B;
CHECKREG r5, 0xF0A4AB1D;
CHECKREG r6, 0x674B5515;
CHECKREG r7, 0x989C7777;
CHECKREG r4, 0x1236891B;
CHECKREG r5, 0xF0A4AB1D;
CHECKREG r6, 0x674B5515;
CHECKREG r7, 0x989C7777;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34d45515;
imm32 r3, 0x466b7717;
imm32 r4, 0x5678f91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444a515;
imm32 r7, 0x86667b77;
R0.H = R5.L + R0.L (NS);
R1.H = R5.L + R1.H (NS);
R2.H = R5.H + R2.L (NS);
R3.H = R5.H + R3.H (NS);
R4.H = R5.L + R4.L (NS);
R5.H = R5.L + R5.H (NS);
R6.H = R5.H + R6.L (NS);
R7.H = R5.H + R7.H (NS);
CHECKREG r4, 0xA438F91B;
CHECKREG r5, 0x12A6AB1D;
CHECKREG r6, 0xB7BBA515;
CHECKREG r7, 0x990C7B77;
CHECKREG r4, 0xA438F91B;
CHECKREG r5, 0x12A6AB1D;
CHECKREG r6, 0xB7BBA515;
CHECKREG r7, 0x990C7B77;
imm32 r0, 0xf5678911;
imm32 r1, 0x2f89ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46f67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678fab1d;
imm32 r6, 0x7444f515;
imm32 r7, 0x86667f77;
R0.L = R6.L + R0.L (NS);
R1.H = R6.L + R1.H (NS);
R2.H = R6.H + R2.L (NS);
R3.H = R6.H + R3.H (NS);
R4.H = R6.L + R4.L (NS);
R5.H = R6.L + R5.H (NS);
R6.H = R6.H + R6.L (NS);
R7.H = R6.H + R7.H (NS);
CHECKREG r4, 0x7E30891B;
CHECKREG r5, 0x5CA4AB1D;
CHECKREG r6, 0x6959F515;
CHECKREG r7, 0xEFBF7F77;
CHECKREG r4, 0x7E30891B;
CHECKREG r5, 0x5CA4AB1D;
CHECKREG r6, 0x6959F515;
CHECKREG r7, 0xEFBF7F77;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R7.L + R0.L (NS);
R1.H = R7.L + R1.H (NS);
R2.H = R7.H + R2.L (NS);
R3.H = R7.H + R3.H (NS);
R4.H = R7.L + R4.L (NS);
R5.H = R7.L + R5.H (NS);
R6.H = R7.H + R6.L (NS);
R7.H = R7.H + R7.H (NS);
CHECKREG r4, 0x0092891B;
CHECKREG r5, 0xDF00AB1D;
CHECKREG r6, 0xDB7B5515;
CHECKREG r7, 0x0CCC7777;
CHECKREG r4, 0x0092891B;
CHECKREG r5, 0xDF00AB1D;
CHECKREG r6, 0xDB7B5515;
CHECKREG r7, 0x0CCC7777;
imm32 r0, 0x56678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34645515;
imm32 r3, 0x466a7717;
imm32 r4, 0x5678e91b;
imm32 r5, 0x6789af1d;
imm32 r6, 0x744455f5;
imm32 r7, 0x866677b7;
R6.H = R2.L + R3.L (S);
R1.H = R4.L + R5.H (S);
R5.H = R7.H + R2.L (S);
R3.H = R0.H + R0.H (S);
R0.H = R3.L + R4.L (S);
R2.H = R5.L + R7.H (S);
R7.H = R6.H + R7.L (S);
R4.H = R1.H + R6.H (S);
CHECKREG r4, 0x7FFFE91B;
CHECKREG r5, 0xDB7BAF1D;
CHECKREG r6, 0x7FFF55F5;
CHECKREG r7, 0x7FFF77B7;
CHECKREG r4, 0x7FFFE91B;
CHECKREG r5, 0xDB7BAF1D;
CHECKREG r6, 0x7FFF55F5;
CHECKREG r7, 0x7FFF77B7;
imm32 r0, 0x95678911;
imm32 r1, 0x2989ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46967717;
imm32 r4, 0x5679891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74449515;
imm32 r7, 0x86667977;
R3.H = R4.L + R0.L (S);
R1.H = R6.L + R3.H (S);
R4.H = R3.H + R2.L (S);
R6.H = R7.H + R1.H (S);
R2.H = R5.L + R4.L (S);
R7.H = R2.L + R7.H (S);
R0.H = R1.H + R6.L (S);
R5.H = R0.H + R5.H (S);
CHECKREG r4, 0xD515891B;
CHECKREG r5, 0xE789AB1D;
CHECKREG r6, 0x80009515;
CHECKREG r7, 0xDB7B7977;
CHECKREG r4, 0xD515891B;
CHECKREG r5, 0xE789AB1D;
CHECKREG r6, 0x80009515;
CHECKREG r7, 0xDB7B7977;
pass
|
stsp/binutils-ia16
| 10,070
|
sim/testsuite/bfin/c_dsp32shift_ahalf_ln.s
|
//Original:/testcases/core/c_dsp32shift_ahalf_ln/c_dsp32shift_ahalf_ln.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000c006;
imm32 r7, 0x0000c007;
R0.L = ASHIFT R0.L BY R0.L;
R1.L = ASHIFT R1.L BY R0.L;
R2.L = ASHIFT R2.L BY R0.L;
R3.L = ASHIFT R3.L BY R0.L;
R4.L = ASHIFT R4.L BY R0.L;
R5.L = ASHIFT R5.L BY R0.L;
R6.L = ASHIFT R6.L BY R0.L;
R7.L = ASHIFT R7.L BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0000c001;
CHECKREG r2, 0x0000c002;
CHECKREG r3, 0x0000c003;
CHECKREG r4, 0x0000c004;
CHECKREG r5, 0x0000c005;
CHECKREG r6, 0x0000c006;
CHECKREG r7, 0x0000c007;
imm32 r0, 0x00008001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000e007;
R0.L = ASHIFT R0.L BY R1.L;
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L;
R3.L = ASHIFT R3.L BY R1.L;
R4.L = ASHIFT R4.L BY R1.L;
R5.L = ASHIFT R5.L BY R1.L;
R6.L = ASHIFT R6.L BY R1.L;
R7.L = ASHIFT R7.L BY R1.L;
//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x0000a004;
CHECKREG r3, 0x0000c006;
CHECKREG r4, 0x0000e008;
CHECKREG r5, 0x0000800a;
CHECKREG r6, 0x0000a00c;
CHECKREG r7, 0x0000c00e;
imm32 r0, 0x0000c001;
imm32 r1, 0x0000d001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R0.L = ASHIFT R0.L BY R2.L;
R1.L = ASHIFT R1.L BY R2.L;
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L;
R4.L = ASHIFT R4.L BY R2.L;
R5.L = ASHIFT R5.L BY R2.L;
R6.L = ASHIFT R6.L BY R2.L;
R7.L = ASHIFT R7.L BY R2.L;
CHECKREG r0, 0x00008000;
CHECKREG r1, 0x00008000;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x00008000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00008000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00008000;
imm32 r0, 0x00009001;
imm32 r1, 0x0000a001;
imm32 r2, 0x0000b002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000f007;
R0.L = ASHIFT R0.L BY R3.L;
R1.L = ASHIFT R1.L BY R3.L;
R2.L = ASHIFT R2.L BY R3.L;
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L;
R5.L = ASHIFT R5.L BY R3.L;
R6.L = ASHIFT R6.L BY R3.L;
R7.L = ASHIFT R7.L BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R0.L;
R1.L = ASHIFT R1.H BY R0.L;
R2.L = ASHIFT R2.H BY R0.L;
R3.L = ASHIFT R3.H BY R0.L;
R4.L = ASHIFT R4.H BY R0.L;
R5.L = ASHIFT R5.H BY R0.L;
R6.L = ASHIFT R6.H BY R0.L;
R7.L = ASHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x90010000;
imm32 r1, 0x00010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R0.L = ASHIFT R0.H BY R1.L;
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L;
R3.L = ASHIFT R3.H BY R1.L;
R4.L = ASHIFT R4.H BY R1.L;
R5.L = ASHIFT R5.H BY R1.L;
R6.L = ASHIFT R6.H BY R1.L;
R7.L = ASHIFT R7.H BY R1.L;
CHECKREG r0, 0x90012002;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x90022004;
CHECKREG r3, 0x90032006;
CHECKREG r4, 0x90042008;
CHECKREG r5, 0x9005200a;
CHECKREG r6, 0x9006200c;
CHECKREG r7, 0x9007200e;
imm32 r0, 0xa0010000;
imm32 r1, 0xa0010000;
imm32 r2, 0xa002000f;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = ASHIFT R0.H BY R2.L;
R1.L = ASHIFT R1.H BY R2.L;
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L;
R4.L = ASHIFT R4.H BY R2.L;
R5.L = ASHIFT R5.H BY R2.L;
R6.L = ASHIFT R6.H BY R2.L;
R7.L = ASHIFT R7.H BY R2.L;
CHECKREG r0, 0xa0018000;
CHECKREG r1, 0xa0018000;
CHECKREG r2, 0xa002000f;
CHECKREG r3, 0xa0038000;
CHECKREG r4, 0xa0040000;
CHECKREG r5, 0xa0058000;
CHECKREG r6, 0xa0060000;
CHECKREG r7, 0xa0078000;
imm32 r0, 0xc0010001;
imm32 r1, 0xc0010001;
imm32 r2, 0xc0020002;
imm32 r3, 0xc0030010;
imm32 r4, 0xc0040004;
imm32 r5, 0xc0050005;
imm32 r6, 0xc0060006;
imm32 r7, 0xc0070007;
R0.L = ASHIFT R0.H BY R3.L;
R1.L = ASHIFT R1.H BY R3.L;
R2.L = ASHIFT R2.H BY R3.L;
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L;
R5.L = ASHIFT R5.H BY R3.L;
R6.L = ASHIFT R6.H BY R3.L;
R7.L = ASHIFT R7.H BY R3.L;
CHECKREG r0, 0xc0010000;
CHECKREG r1, 0xc0010000;
CHECKREG r2, 0xc0020000;
CHECKREG r3, 0xc0030010;
CHECKREG r4, 0xc0040000;
CHECKREG r5, 0xc0050000;
CHECKREG r6, 0xc0060000;
CHECKREG r7, 0xc0070000;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R0.L;
R1.H = ASHIFT R1.L BY R0.L;
R2.H = ASHIFT R2.L BY R0.L;
R3.H = ASHIFT R3.L BY R0.L;
R4.H = ASHIFT R4.L BY R0.L;
R5.H = ASHIFT R5.L BY R0.L;
R6.H = ASHIFT R6.L BY R0.L;
R7.H = ASHIFT R7.L BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x0000d001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000d003;
imm32 r4, 0x0000d004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000d007;
R0.H = ASHIFT R0.L BY R1.L;
R1.H = ASHIFT R1.L BY R1.L;
R2.H = ASHIFT R2.L BY R1.L;
R3.H = ASHIFT R3.L BY R1.L;
R4.H = ASHIFT R4.L BY R1.L;
R5.H = ASHIFT R5.L BY R1.L;
R6.H = ASHIFT R6.L BY R1.L;
R7.H = ASHIFT R7.L BY R1.L;
CHECKREG r0, 0xa002d001;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0xa004d002;
CHECKREG r3, 0xa006d003;
CHECKREG r4, 0xa008d004;
CHECKREG r5, 0xa00ad005;
CHECKREG r6, 0xa00cd006;
CHECKREG r7, 0xa00ed007;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.H = ASHIFT R0.L BY R2.L;
R1.H = ASHIFT R1.L BY R2.L;
//rh2 = ashift (rl2 by rl2);
R3.H = ASHIFT R3.L BY R2.L;
R4.H = ASHIFT R4.L BY R2.L;
R5.H = ASHIFT R5.L BY R2.L;
R6.H = ASHIFT R6.L BY R2.L;
R7.H = ASHIFT R7.L BY R2.L;
CHECKREG r0, 0x8000e001;
CHECKREG r1, 0x8000e001;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x8000e003;
CHECKREG r4, 0x0000e004;
CHECKREG r5, 0x8000e005;
CHECKREG r6, 0x0000e006;
CHECKREG r7, 0x8000e007;
imm32 r0, 0x0000f001;
imm32 r1, 0x0000f001;
imm32 r2, 0x0000f002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R0.H = ASHIFT R0.L BY R3.L;
R1.H = ASHIFT R1.L BY R3.L;
R2.H = ASHIFT R2.L BY R3.L;
R3.H = ASHIFT R3.L BY R3.L;
R4.H = ASHIFT R4.L BY R3.L;
R5.H = ASHIFT R5.L BY R3.L;
R6.H = ASHIFT R6.L BY R3.L;
R7.H = ASHIFT R7.L BY R3.L;
CHECKREG r0, 0x0000f001;
CHECKREG r1, 0x0000f001;
CHECKREG r2, 0x0000f002;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x0000f004;
CHECKREG r5, 0x0000f005;
CHECKREG r6, 0x0000f006;
CHECKREG r7, 0x0000f007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R0.L;
R1.H = ASHIFT R1.H BY R0.L;
R2.H = ASHIFT R2.H BY R0.L;
R3.H = ASHIFT R3.H BY R0.L;
R4.H = ASHIFT R4.H BY R0.L;
R5.H = ASHIFT R5.H BY R0.L;
R6.H = ASHIFT R6.H BY R0.L;
R7.H = ASHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.H = ASHIFT R0.H BY R1.L;
R1.H = ASHIFT R1.H BY R1.L;
R2.H = ASHIFT R2.H BY R1.L;
R3.H = ASHIFT R3.H BY R1.L;
R4.H = ASHIFT R4.H BY R1.L;
R5.H = ASHIFT R5.H BY R1.L;
R6.H = ASHIFT R6.H BY R1.L;
R7.H = ASHIFT R7.H BY R1.L;
CHECKREG r0, 0x40020000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x40040000;
CHECKREG r3, 0x40060000;
CHECKREG r4, 0x40080000;
CHECKREG r5, 0x400a0000;
CHECKREG r6, 0x400c0000;
CHECKREG r7, 0x400e0000;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R0.L = ASHIFT R0.H BY R2.L;
R1.L = ASHIFT R1.H BY R2.L;
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L;
R4.L = ASHIFT R4.H BY R2.L;
R5.L = ASHIFT R5.H BY R2.L;
R6.L = ASHIFT R6.H BY R2.L;
R7.L = ASHIFT R7.H BY R2.L;
CHECKREG r0, 0xb0018000;
CHECKREG r1, 0xb0018000;
CHECKREG r2, 0xb002000f;
CHECKREG r3, 0xb0038000;
CHECKREG r4, 0xb0040000;
CHECKREG r5, 0xb0058000;
CHECKREG r6, 0xb0060000;
CHECKREG r7, 0xb0078000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xd0070000;
R0.H = ASHIFT R0.H BY R3.L;
R1.H = ASHIFT R1.H BY R3.L;
R2.H = ASHIFT R2.H BY R3.L;
R3.H = ASHIFT R3.H BY R3.L;
R4.H = ASHIFT R4.H BY R3.L;
R5.H = ASHIFT R5.H BY R3.L;
R6.H = ASHIFT R6.H BY R3.L;
R7.H = ASHIFT R7.H BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
stsp/binutils-ia16
| 3,031
|
sim/testsuite/bfin/dotproduct.s
|
# Blackfin testcase for a simple vector dot product using hard
# wired input buffers of 128 samples each. These values are in
# 1.15 signed .
# mach: bfin
.include "testutils.inc"
start
loadsym P0, _buf0
loadsym P1, _buf1
/* loop control
* number of loop iterations is 2^N with r4|=1<<N
* to process 128 samples need 64 iterations
*/
R4 = 64 (X);
A1 = A0 = 0;
/*
* For now, serialize two 32b loads
*/
.L1:
R0 = [ P0 ++ ];
R1 = [ P1 ++ ];
A1 += R0.H * R1.H, A0 += R0.L * R1.L;
R4 += -1;
CC = R4 == 0;
IF !CC JUMP .L1;
/* extract two partial results from accumulators
* and do final addition
*/
R0 = ( A0 += A1 );
imm32 r1, 0x00545600
CC = R0 == R1
if CC jump 1f;
fail
1:
pass
.data
_buf0:
.dw 0x0
.dw 0x2
.dw 0x4
.dw 0x6
.dw 0x8
.dw 0xA
.dw 0xC
.dw 0xE
.dw 0x10
.dw 0x12
.dw 0x14
.dw 0x16
.dw 0x18
.dw 0x1A
.dw 0x1C
.dw 0x1E
.dw 0x20
.dw 0x22
.dw 0x24
.dw 0x26
.dw 0x28
.dw 0x2A
.dw 0x2C
.dw 0x2E
.dw 0x30
.dw 0x32
.dw 0x34
.dw 0x36
.dw 0x38
.dw 0x3A
.dw 0x3C
.dw 0x3E
.dw 0x40
.dw 0x42
.dw 0x44
.dw 0x46
.dw 0x48
.dw 0x4A
.dw 0x4C
.dw 0x4E
.dw 0x50
.dw 0x52
.dw 0x54
.dw 0x56
.dw 0x58
.dw 0x5A
.dw 0x5C
.dw 0x5E
.dw 0x60
.dw 0x62
.dw 0x64
.dw 0x66
.dw 0x68
.dw 0x6A
.dw 0x6C
.dw 0x6E
.dw 0x70
.dw 0x72
.dw 0x74
.dw 0x76
.dw 0x78
.dw 0x7A
.dw 0x7C
.dw 0x7E
.dw 0x80
.dw 0x82
.dw 0x84
.dw 0x86
.dw 0x88
.dw 0x8A
.dw 0x8C
.dw 0x8E
.dw 0x90
.dw 0x92
.dw 0x94
.dw 0x96
.dw 0x98
.dw 0x9A
.dw 0x9C
.dw 0x9E
.dw 0xA0
.dw 0xA2
.dw 0xA4
.dw 0xA6
.dw 0xA8
.dw 0xAA
.dw 0xAC
.dw 0xAE
.dw 0xB0
.dw 0xB2
.dw 0xB4
.dw 0xB6
.dw 0xB8
.dw 0xBA
.dw 0xBC
.dw 0xBE
.dw 0xC0
.dw 0xC2
.dw 0xC4
.dw 0xC6
.dw 0xC8
.dw 0xCA
.dw 0xCC
.dw 0xCE
.dw 0xD0
.dw 0xD2
.dw 0xD4
.dw 0xD6
.dw 0xD8
.dw 0xDA
.dw 0xDC
.dw 0xDE
.dw 0xE0
.dw 0xE2
.dw 0xE4
.dw 0xE6
.dw 0xE8
.dw 0xEA
.dw 0xEC
.dw 0xEE
.dw 0xF0
.dw 0xF2
.dw 0xF4
.dw 0xF6
.dw 0xF8
.dw 0xFA
.dw 0xFC
.dw 0xFE
_buf1:
.dw 0x0
.dw 0x2
.dw 0x4
.dw 0x6
.dw 0x8
.dw 0xA
.dw 0xC
.dw 0xE
.dw 0x10
.dw 0x12
.dw 0x14
.dw 0x16
.dw 0x18
.dw 0x1A
.dw 0x1C
.dw 0x1E
.dw 0x20
.dw 0x22
.dw 0x24
.dw 0x26
.dw 0x28
.dw 0x2A
.dw 0x2C
.dw 0x2E
.dw 0x30
.dw 0x32
.dw 0x34
.dw 0x36
.dw 0x38
.dw 0x3A
.dw 0x3C
.dw 0x3E
.dw 0x40
.dw 0x42
.dw 0x44
.dw 0x46
.dw 0x48
.dw 0x4A
.dw 0x4C
.dw 0x4E
.dw 0x50
.dw 0x52
.dw 0x54
.dw 0x56
.dw 0x58
.dw 0x5A
.dw 0x5C
.dw 0x5E
.dw 0x60
.dw 0x62
.dw 0x64
.dw 0x66
.dw 0x68
.dw 0x6A
.dw 0x6C
.dw 0x6E
.dw 0x70
.dw 0x72
.dw 0x74
.dw 0x76
.dw 0x78
.dw 0x7A
.dw 0x7C
.dw 0x7E
.dw 0x80
.dw 0x82
.dw 0x84
.dw 0x86
.dw 0x88
.dw 0x8A
.dw 0x8C
.dw 0x8E
.dw 0x90
.dw 0x92
.dw 0x94
.dw 0x96
.dw 0x98
.dw 0x9A
.dw 0x9C
.dw 0x9E
.dw 0xA0
.dw 0xA2
.dw 0xA4
.dw 0xA6
.dw 0xA8
.dw 0xAA
.dw 0xAC
.dw 0xAE
.dw 0xB0
.dw 0xB2
.dw 0xB4
.dw 0xB6
.dw 0xB8
.dw 0xBA
.dw 0xBC
.dw 0xBE
.dw 0xC0
.dw 0xC2
.dw 0xC4
.dw 0xC6
.dw 0xC8
.dw 0xCA
.dw 0xCC
.dw 0xCE
.dw 0xD0
.dw 0xD2
.dw 0xD4
.dw 0xD6
.dw 0xD8
.dw 0xDA
.dw 0xDC
.dw 0xDE
.dw 0xE0
.dw 0xE2
.dw 0xE4
.dw 0xE6
.dw 0xE8
.dw 0xEA
.dw 0xEC
.dw 0xEE
.dw 0xF0
.dw 0xF2
.dw 0xF4
.dw 0xF6
.dw 0xF8
.dw 0xFA
.dw 0xFC
.dw 0xFE
|
stsp/binutils-ia16
| 6,264
|
sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s
|
//Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp
// Spec Reference: c_dspldst st_drhi_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// Half reg 16 bit mem store
imm32 r0, 0x0a123456;
imm32 r1, 0x11b12345;
imm32 r2, 0x222c1234;
imm32 r3, 0x3344d012;
imm32 r4, 0x5566e012;
imm32 r5, 0x789abf01;
imm32 r6, 0xabcd0123;
imm32 r7, 0x01234567;
// initial values
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
W [ I0 ++ ] = R0.H;
W [ I1 ++ ] = R1.H;
W [ I2 ++ ] = R2.H;
W [ I3 ++ ] = R3.H;
W [ I0 ++ ] = R1.H;
W [ I1 ++ ] = R2.H;
W [ I2 ++ ] = R3.H;
W [ I3 ++ ] = R4.H;
W [ I0 ++ ] = R3.H;
W [ I1 ++ ] = R4.H;
W [ I2 ++ ] = R5.H;
W [ I3 ++ ] = R6.H;
W [ I0 ++ ] = R4.H;
W [ I1 ++ ] = R5.H;
W [ I2 ++ ] = R6.H;
W [ I3 ++ ] = R7.H;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x11B10A12;
CHECKREG r1, 0x222C11B1;
CHECKREG r2, 0x3344222C;
CHECKREG r3, 0x55663344;
CHECKREG r4, 0x55663344;
CHECKREG r5, 0x789A5566;
CHECKREG r6, 0xABCD789A;
CHECKREG r7, 0x0123ABCD;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x08090A0B;
CHECKREG r1, 0x28292A2B;
CHECKREG r2, 0x48494A4B;
CHECKREG r3, 0x68696A6B;
CHECKREG r4, 0x0C0D0E0F;
CHECKREG r5, 0x2C2D2E2F;
CHECKREG r6, 0x4C4D4E4F;
CHECKREG r7, 0x6C6D6E6F;
// initial values
imm32 r0, 0x01b2c3d4;
imm32 r1, 0x10145618;
imm32 r2, 0xa2016729;
imm32 r3, 0xbb30183a;
imm32 r4, 0xdec4014b;
imm32 r5, 0x5f7d501c;
imm32 r6, 0x3089eb01;
imm32 r7, 0x719abf70;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
W [ I0 -- ] = R0.H;
W [ I1 -- ] = R1.H;
W [ I2 -- ] = R2.H;
W [ I3 -- ] = R3.H;
W [ I0 -- ] = R1.H;
W [ I1 -- ] = R2.H;
W [ I2 -- ] = R3.H;
W [ I3 -- ] = R4.H;
W [ I0 -- ] = R3.H;
W [ I1 -- ] = R4.H;
W [ I2 -- ] = R5.H;
W [ I3 -- ] = R6.H;
W [ I0 -- ] = R4.H;
W [ I1 -- ] = R5.H;
W [ I2 -- ] = R6.H;
W [ I3 -- ] = R7.H;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0x000001B2;
CHECKREG r1, 0x00001014;
CHECKREG r2, 0x0000A201;
CHECKREG r3, 0x0000BB30;
CHECKREG r4, 0x1014BB30;
CHECKREG r5, 0xA201DEC4;
CHECKREG r6, 0xBB305F7D;
CHECKREG r7, 0xDEC43089;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0xDEC41A1B;
CHECKREG r1, 0x5F7D3A3B;
CHECKREG r2, 0x30895A5B;
CHECKREG r3, 0x719A7A7B;
CHECKREG r4, 0x14151617;
CHECKREG r5, 0x34353637;
CHECKREG r6, 0x54555657;
CHECKREG r7, 0x74757677;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 1,831
|
sim/testsuite/bfin/c_except_illopcode.S
|
//Original:/proj/frio/dv/testcases/core/c_except_illopcode/c_except_illopcode.dsp
// Spec Reference: c_exception illegal opcode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
// load address of exception handler
P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION
P0.H = 0xFFE0;
R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3
R0.H = exception_handler;
[ P0 ] = R0;
// Jump to User mode and enable exceptions
R0 = MidUserCode (Z);
R0.H = MidUserCode;
RETI = R0;
RTI; // cause it to go to Midusercode, .dd cause exception
BeginUserCode:
P1 = 1;
P2 = 2;
P3 = 3;
P4 = 4;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000001);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000003);
// CHECKREG(r4, 0x00000098);
CHECKREG(r5, 0x00000005);
CHECKREG(r6, 0x00000006);
CHECKREG(r7, 0x00000007);
CHECKREG(p1, 0x00000001);
CHECKREG(p2, 0x00000002);
CHECKREG(p3, 0x00000003);
CHECKREG(p4, 0x00000004);
dbg_pass;
//jump 2;
//jump -2;
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
//dbg_pass;
MidUserCode:
.dd 0xFFFFFFFF
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
CC = R0;
IF !CC JUMP BeginUserCode;
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
//.code 0x800
exception_handler:
R4 = RETX; // error handler: RETX has the address of the same Illegal instr
R5 = 5;
R6 = 6;
R7 = 7;
R4 += 4; // we have to add 4 to point to next instr after return
RETX = R4;
RTX; // return from exception
//nop;
.section MEM_DATA_ADDR_1,"aw"
.dd 0xDEADBEEF
.dd 0xBAD00BAD
|
stsp/binutils-ia16
| 9,978
|
sim/testsuite/bfin/se_loop_nest_ppm.S
|
//Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm/se_loop_nest_ppm.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x4 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
LSETUP ( l0s , l0s ) LC1 = P1;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l1s , l1e ) LC0 = P0;
LSETUP ( l1e , l1e ) LC1 = P1;
l1s:R5 += 1;
l1e:[ -- SP ] = ( R7:5 );
LSETUP ( l2s , l2e ) LC0 = P0;
LSETUP ( l2e , l2e ) LC1 = P1;
l2s:R5 += 1;
R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
LSETUP ( l3e , l3e ) LC1 = P1;
l3s:R5 += 1;
R6 += 2;
R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LSETUP ( l4s , l4e ) LC0 = P0;
LSETUP ( l4e , l4e ) LC1 = P1;
l4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LSETUP ( l5s , l5e ) LC0 = P0;
LSETUP ( l5e , l5e ) LC1 = P1;
l5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
l5e:[ -- SP ] = ( R7:4 );
LSETUP ( l6s , l6e ) LC0 = P0;
LSETUP ( l6e , l6e ) LC1 = P1;
l6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
stsp/binutils-ia16
| 4,845
|
sim/testsuite/bfin/c_dsp32shift_align24.s
|
//Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp
// Spec Reference: dsp32shift align24
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x08000807;
R1 = ALIGN24 ( R1 , R0 );
R2 = ALIGN24 ( R2 , R0 );
R3 = ALIGN24 ( R3 , R0 );
R4 = ALIGN24 ( R4 , R0 );
R5 = ALIGN24 ( R5 , R0 );
R6 = ALIGN24 ( R6 , R0 );
R7 = ALIGN24 ( R7 , R0 );
R0 = ALIGN24 ( R0 , R0 );
CHECKREG r0, 0x00000100;
CHECKREG r1, 0x00080100;
CHECKREG r2, 0x20080200;
CHECKREG r3, 0x03080300;
CHECKREG r4, 0x00480400;
CHECKREG r5, 0x00050500;
CHECKREG r6, 0x00086600;
CHECKREG r7, 0x00080700;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000002;
imm32 r2, 0x09400002;
imm32 r3, 0x09100003;
imm32 r4, 0x09020004;
imm32 r5, 0x09003005;
imm32 r6, 0x09000406;
imm32 r7, 0x09000057;
R0 = ALIGN24 ( R0 , R1 );
R2 = ALIGN24 ( R2 , R1 );
R3 = ALIGN24 ( R3 , R1 );
R4 = ALIGN24 ( R4 , R1 );
R5 = ALIGN24 ( R5 , R1 );
R6 = ALIGN24 ( R6 , R1 );
R7 = ALIGN24 ( R7 , R1 );
R1 = ALIGN24 ( R1 , R1 );
CHECKREG r0, 0x00D00109;
CHECKREG r1, 0x00000209;
CHECKREG r2, 0x40000209;
CHECKREG r3, 0x10000309;
CHECKREG r4, 0x02000409;
CHECKREG r5, 0x00300509;
CHECKREG r6, 0x00040609;
CHECKREG r7, 0x00005709;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a400010;
imm32 r4, 0x0a05e004;
imm32 r5, 0x0a006005;
imm32 r6, 0x0a00e706;
imm32 r7, 0x0a00e087;
R0 = ALIGN24 ( R0 , R2 );
R1 = ALIGN24 ( R1 , R2 );
R3 = ALIGN24 ( R3 , R2 );
R4 = ALIGN24 ( R4 , R2 );
R5 = ALIGN24 ( R5 , R2 );
R6 = ALIGN24 ( R6 , R2 );
R7 = ALIGN24 ( R7 , R2 );
R2 = ALIGN24 ( R2 , R2 );
CHECKREG r0, 0x00E0010A;
CHECKREG r1, 0x00E0010A;
CHECKREG r2, 0x00000F0A;
CHECKREG r3, 0x4000100A;
CHECKREG r4, 0x05E0040A;
CHECKREG r5, 0x0060050A;
CHECKREG r6, 0x00E7060A;
CHECKREG r7, 0x00E0870A;
imm32 r0, 0x2b00f001;
imm32 r1, 0x0300f001;
imm32 r2, 0x0b40f002;
imm32 r3, 0x0b050010;
imm32 r4, 0x0b006004;
imm32 r5, 0x0b00f705;
imm32 r6, 0x0b00f086;
imm32 r7, 0x0b00f009;
R0 = ALIGN24 ( R0 , R3 );
R1 = ALIGN24 ( R1 , R3 );
R2 = ALIGN24 ( R2 , R3 );
R4 = ALIGN24 ( R4 , R3 );
R5 = ALIGN24 ( R5 , R3 );
R6 = ALIGN24 ( R6 , R3 );
R7 = ALIGN24 ( R7 , R3 );
R3 = ALIGN24 ( R3 , R3 );
CHECKREG r0, 0x00F0010B;
CHECKREG r1, 0x00F0010B;
CHECKREG r2, 0x40F0020B;
CHECKREG r3, 0x0500100B;
CHECKREG r4, 0x0060040B;
CHECKREG r5, 0x00F7050B;
CHECKREG r6, 0x00F0860B;
CHECKREG r7, 0x00F0090B;
imm32 r0, 0x4c0000c0;
imm32 r1, 0x050100c0;
imm32 r2, 0x0c6200c0;
imm32 r3, 0x0c0700c0;
imm32 r4, 0x0c04800c;
imm32 r5, 0x0c0509c0;
imm32 r6, 0x0c060000;
imm32 r7, 0x0c0700ca;
R0 = ALIGN24 ( R0 , R4 );
R1 = ALIGN24 ( R1 , R4 );
R2 = ALIGN24 ( R2 , R4 );
R3 = ALIGN24 ( R3 , R4 );
R5 = ALIGN24 ( R5 , R4 );
R6 = ALIGN24 ( R6 , R4 );
R7 = ALIGN24 ( R7 , R4 );
R4 = ALIGN24 ( R4 , R4 );
CHECKREG r0, 0x0000C00C;
CHECKREG r1, 0x0100C00C;
CHECKREG r2, 0x6200C00C;
CHECKREG r3, 0x0700C00C;
CHECKREG r4, 0x04800C0C;
CHECKREG r5, 0x0509C00C;
CHECKREG r6, 0x0600000C;
CHECKREG r7, 0x0700CA0C;
imm32 r0, 0xa00100d0;
imm32 r1, 0xa00100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa0050007;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R0 = ALIGN24 ( R0 , R5 );
R1 = ALIGN24 ( R1 , R5 );
R2 = ALIGN24 ( R2 , R5 );
R3 = ALIGN24 ( R3 , R5 );
R4 = ALIGN24 ( R4 , R5 );
R6 = ALIGN24 ( R6 , R5 );
R7 = ALIGN24 ( R7 , R5 );
R5 = ALIGN24 ( R5 , R5 );
CHECKREG r0, 0x0100D0A0;
CHECKREG r1, 0x0100D1A0;
CHECKREG r2, 0x0200D0A0;
CHECKREG r3, 0x0300D0A0;
CHECKREG r4, 0x0400D0A0;
CHECKREG r5, 0x050007A0;
CHECKREG r6, 0x0600D0A0;
CHECKREG r7, 0x0700D0A0;
imm32 r0, 0xb2010000;
imm32 r1, 0xb0310000;
imm32 r2, 0xb042000f;
imm32 r3, 0xbf030000;
imm32 r4, 0xba040000;
imm32 r5, 0xbb050000;
imm32 r6, 0xbc060009;
imm32 r7, 0xb0e70000;
R0 = ALIGN24 ( R0 , R6 );
R1 = ALIGN24 ( R1 , R6 );
R2 = ALIGN24 ( R2 , R6 );
R3 = ALIGN24 ( R3 , R6 );
R4 = ALIGN24 ( R4 , R6 );
R5 = ALIGN24 ( R5 , R6 );
R6 = ALIGN24 ( R6 , R6 );
R7 = ALIGN24 ( R7 , R6 );
CHECKREG r0, 0x010000BC;
CHECKREG r1, 0x310000BC;
CHECKREG r2, 0x42000FBC;
CHECKREG r3, 0x030000BC;
CHECKREG r4, 0x040000BC;
CHECKREG r5, 0x050000BC;
CHECKREG r6, 0x060009BC;
CHECKREG r7, 0xE7000006;
imm32 r0, 0xd23100e0;
imm32 r1, 0xd04500e0;
imm32 r2, 0xde32f0e0;
imm32 r3, 0xd90300e0;
imm32 r4, 0xd07400e0;
imm32 r5, 0xdef500e0;
imm32 r6, 0xd06600e0;
imm32 r7, 0xd0080023;
R1 = ALIGN24 ( R0 , R7 );
R2 = ALIGN24 ( R1 , R7 );
R3 = ALIGN24 ( R2 , R7 );
R4 = ALIGN24 ( R3 , R7 );
R5 = ALIGN24 ( R4 , R7 );
R6 = ALIGN24 ( R5 , R7 );
R7 = ALIGN24 ( R6 , R7 );
R0 = ALIGN24 ( R7 , R7 );
CHECKREG r0, 0xD0D0D0D0;
CHECKREG r1, 0x3100E0D0;
CHECKREG r2, 0x00E0D0D0;
CHECKREG r3, 0xE0D0D0D0;
CHECKREG r4, 0xD0D0D0D0;
CHECKREG r5, 0xD0D0D0D0;
CHECKREG r6, 0xD0D0D0D0;
CHECKREG r7, 0xD0D0D0D0;
pass
|
stsp/binutils-ia16
| 2,078
|
sim/testsuite/bfin/c_dagmodik_lz_inc_dec.s
|
//Original:/testcases/core/c_dagmodik_lz_inc_dec/c_dagmodik_lz_inc_dec.dsp
// Spec Reference: dagmodik L=0, I incremented & decremented
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001200;
imm32 i3, 0x00001300;
imm32 m0, 0x00000000;
imm32 m1, 0x00000110;
imm32 m2, 0x00000210;
imm32 m3, 0x00000310;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x00001102;
CHECKREG r2, 0x00001202;
CHECKREG r3, 0x00001302;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001104;
CHECKREG r6, 0x00001204;
CHECKREG r7, 0x00001304;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= 2;
I1 -= 2;
I2 -= 2;
I3 -= 2;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001002;
CHECKREG r1, 0x00001102;
CHECKREG r2, 0x00001202;
CHECKREG r3, 0x00001302;
CHECKREG r4, 0x00001000;
CHECKREG r5, 0x00001100;
CHECKREG r6, 0x00001200;
CHECKREG r7, 0x00001300;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += 4;
I1 += 4;
I2 += 4;
I3 += 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001004;
CHECKREG r1, 0x00001104;
CHECKREG r2, 0x00001204;
CHECKREG r3, 0x00001304;
CHECKREG r4, 0x00001008;
CHECKREG r5, 0x00001108;
CHECKREG r6, 0x00001208;
CHECKREG r7, 0x00001308;
I0 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG r0, 0x00001000;
CHECKREG r1, 0x00001100;
CHECKREG r2, 0x00001200;
CHECKREG r3, 0x00001300;
CHECKREG r4, 0x00001008;
CHECKREG r5, 0x00001108;
CHECKREG r6, 0x00001208;
CHECKREG r7, 0x00001308;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
I0 -= 4;
I1 -= 4;
I2 -= 4;
I3 -= 4;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001000;
CHECKREG r1, 0x00001100;
CHECKREG r2, 0x00001200;
CHECKREG r3, 0x00001300;
CHECKREG r4, 0x00000FF8;
CHECKREG r5, 0x000010F8;
CHECKREG r6, 0x000011F8;
CHECKREG r7, 0x000012F8;
pass
|
stsp/binutils-ia16
| 5,681
|
sim/testsuite/bfin/iir.s
|
# mach: bfin
// GENERIC BIQUAD:
// ---------------
// x ---------+---------|---------+-------y
// | |t1 |
// | D |
// | a1 | b1 |
// +---<-----|---->----+
// | | |
// | D | D's are delays
// | a2 | b2 | ">" represent multiplications
// +---<-----|---->----+
// To test this routine, use a biquad with a pole pair at z = (0.7 +- 0.1j),
// and a double zero at z = -1.0, which is a low-pass. The transfer function is:
// 1 + 2z^-1 + z^-2
// H(z) = ----------------------
// 1 - 1.4z^-1 + 0.5z^-2
// a1 = 1.4
// a2 = -0.5
// b1 = 2
// b2 = 1
// This filter conforms to the biquad test in BDT, since it has coefficients
// larger than 1.0 in magnitude, and b0=1. (Note that the a's have a negative
// sign.)
// This filter can be simulated in matlab. To simulate one biquad, use
// A = [1.0, -1.4, 0.5]
// B = [1, 2, 1]
// Y=filter(B,A,X)
// To simulate two cascaded biquads, use
// Y=filter(B,A,filter(B,A,X))
// SCALED COEFFICIENTS:
// --------------------
// In order to conform to 1.15 representation, must scale coeffs by 0.5.
// This requires an additional internal re-scale. The equations for the Type II
// filter are:
// t1 = x + a1*t1*z^-1 + a2*t1*z^-2
// y = b0*t1 + b1*t1*z^-1 + b2*t1*z^-2
// (Note inclusion of term b0, which in the example is b0 = 1.)
// If all coeffs are replaced by
// ai --> ai' = 0.5*a1
// then the two equations become
// t1 = x + 2*a1'*t1*z^-1 + 2*a2'*t1*z^-2
// 0.5*y = b0'*t1 + b1'*t1*z^-1 + b2'*t1*z^-2
// which can be implemented as:
// 2.0 b0'=0.5
// x ---------+--->-----|---->----+-------y
// | |t1 |
// | D |
// | a1' | b1' |
// +---<-----|---->----+
// | | |
// | D |
// | a2' | b2' |
// +---<-----|---->----+
// But, b0' can be eliminated by:
// x ---------+---------|---------+-------y
// | | |
// | V 2.0 |
// | | |
// | |t1 |
// | D |
// | a1' | b1' |
// +---<-----|---->----+
// | | |
// | D |
// | a2' | b2' |
// +---<-----|---->----+
// Function biquadf() computes this implementation on float data.
// CASCADED BIQUADS
// ----------------
// Cascaded biquads are simulated by simply cascading copies of the
// filter defined above. However, one must be careful with the resulting
// filter, as it is not very stable numerically (double poles in the
// vecinity of +1). It would of course be better to cascade different
// filters, as that would result in more stable structures.
// The functions biquadf() and biquadR() have been tested with up to 3
// stages using this technique, with inputs having small signal amplitude
// (less than 0.001) and under 300 samples.
//
// In order to pipeline, need to maintain two pointers into the state
// array: one to load (I0) and one to store (I2). This is required since
// the load of iteration i+1 is hoisted above the store of iteration i.
.include "testutils.inc"
start
// I3 points to input buffer
loadsym I3, input;
// P1 points to output buffer
loadsym P1, output;
R0 = 0; R7 = 0;
P2 = 10;
LSETUP ( L$0 , L$0end ) LC0 = P2;
L$0:
// I0 and I2 are pointers to state
loadsym I0, state;
I2 = I0;
// pointer to coeffs
loadsym I1, Coeff;
R0.H = W [ I3 ++ ]; // load input value into RH0
A0.w = R0; // A0 holds x
P2 = 2;
LSETUP ( L$1 , L$1end ) LC1 = P2;
// load 2 coeffs into R1 and R2
// load state into R3
R1 = [ I1 ++ ];
MNOP || R2 = [ I1 ++ ] || R3 = [ I0 ++ ];
L$1:
// A1=b1*s0 A0=a1*s0+x
A1 = R1.L * R3.L, A0 += R1.H * R3.L || R1 = [ I1 ++ ] || NOP;
// A1+=b2*s1 A0+=a2*s1
// and move scaled value in A0 (t1) into RL4
A1 += R2.L * R3.H, R4.L = ( A0 += R2.H * R3.H ) (S2RND) || R2 = [ I1 ++ ] || NOP;
// Advance state. before:
// R4 = uuuu t1
// R3 = stat[1] stat[0]
// after PACKLL:
// R3 = stat[0] t1
R5 = PACK( R3.L , R4.L ) || R3 = [ I0 ++ ] || NOP;
// collect output into A0, and move to RL0.
// Keep output value in A0, since it is also
// the accumulator used to store the input to
// the next stage. Also, store updated state
L$1end:
R0.L = ( A0 += A1 ) || [ I2 ++ ] = R5 || NOP;
// store output
L$0end:
W [ P1 ++ ] = R0;
// Check results
loadsym I2, output;
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0028 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0110 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0373 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x075b );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0c00 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1064 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x13d3 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x15f2 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x16b9 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1650 );
pass
.data
state:
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.data
Coeff:
.dw 0x7fff
.dw 0x5999
.dw 0x4000
.dw 0xe000
.dw 0x7fff
.dw 0x5999
.dw 0x4000
.dw 0xe000
input:
.dw 0x0028
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
output:
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
|
stsp/binutils-ia16
| 3,485
|
sim/testsuite/bfin/dotproduct2.s
|
/* Vector Dot Product
* This program computes a simple vector dot product using hard
* wired input buffers of 128 samples each. These values are in
* 1.15 signed .
*/
# mach: bfin
.include "testutils.inc"
start
// load buffer addresses into pointer regs
loadsym I0, data0;
loadsym I1, data1;
// loop control
// number of loop iterations is 2^N with r4|=1<<N
// to process 128 samples need 64 iterations
P4 = 63;
LSETUP ( loop1 , loop1 ) LC0 = P4;
A1 = A0 = 0;
// For now, serialize two 32b loads.
// These should be done in parallel with the dual mac.
R0 = [ I0 ++ ]; R1 = [ I1 ++ ];
loop1: A1 += R0.H * R1.H, A0 += R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
A1 += R0.H * R1.H, A0 += R0.L * R1.L;
// extract two partial results from accumulators
// and do final addition
R0 = ( A0 += A1 );
DBGA ( R0.L , 0x5600 ); // 0x00545600 = 0.002574 fract
DBGA ( R0.H , 0x0054 );
pass
.data
data0:
.dw 0x0
.dw 0x2
.dw 0x4
.dw 0x6
.dw 0x8
.dw 0xA
.dw 0xC
.dw 0xE
.dw 0x10
.dw 0x12
.dw 0x14
.dw 0x16
.dw 0x18
.dw 0x1A
.dw 0x1C
.dw 0x1E
.dw 0x20
.dw 0x22
.dw 0x24
.dw 0x26
.dw 0x28
.dw 0x2A
.dw 0x2C
.dw 0x2E
.dw 0x30
.dw 0x32
.dw 0x34
.dw 0x36
.dw 0x38
.dw 0x3A
.dw 0x3C
.dw 0x3E
.dw 0x40
.dw 0x42
.dw 0x44
.dw 0x46
.dw 0x48
.dw 0x4A
.dw 0x4C
.dw 0x4E
.dw 0x50
.dw 0x52
.dw 0x54
.dw 0x56
.dw 0x58
.dw 0x5A
.dw 0x5C
.dw 0x5E
.dw 0x60
.dw 0x62
.dw 0x64
.dw 0x66
.dw 0x68
.dw 0x6A
.dw 0x6C
.dw 0x6E
.dw 0x70
.dw 0x72
.dw 0x74
.dw 0x76
.dw 0x78
.dw 0x7A
.dw 0x7C
.dw 0x7E
.dw 0x80
.dw 0x82
.dw 0x84
.dw 0x86
.dw 0x88
.dw 0x8A
.dw 0x8C
.dw 0x8E
.dw 0x90
.dw 0x92
.dw 0x94
.dw 0x96
.dw 0x98
.dw 0x9A
.dw 0x9C
.dw 0x9E
.dw 0xA0
.dw 0xA2
.dw 0xA4
.dw 0xA6
.dw 0xA8
.dw 0xAA
.dw 0xAC
.dw 0xAE
.dw 0xB0
.dw 0xB2
.dw 0xB4
.dw 0xB6
.dw 0xB8
.dw 0xBA
.dw 0xBC
.dw 0xBE
.dw 0xC0
.dw 0xC2
.dw 0xC4
.dw 0xC6
.dw 0xC8
.dw 0xCA
.dw 0xCC
.dw 0xCE
.dw 0xD0
.dw 0xD2
.dw 0xD4
.dw 0xD6
.dw 0xD8
.dw 0xDA
.dw 0xDC
.dw 0xDE
.dw 0xE0
.dw 0xE2
.dw 0xE4
.dw 0xE6
.dw 0xE8
.dw 0xEA
.dw 0xEC
.dw 0xEE
.dw 0xF0
.dw 0xF2
.dw 0xF4
.dw 0xF6
.dw 0xF8
.dw 0xFA
.dw 0xFC
.dw 0xFE
data1:
.dw 0x0
.dw 0x2
.dw 0x4
.dw 0x6
.dw 0x8
.dw 0xA
.dw 0xC
.dw 0xE
.dw 0x10
.dw 0x12
.dw 0x14
.dw 0x16
.dw 0x18
.dw 0x1A
.dw 0x1C
.dw 0x1E
.dw 0x20
.dw 0x22
.dw 0x24
.dw 0x26
.dw 0x28
.dw 0x2A
.dw 0x2C
.dw 0x2E
.dw 0x30
.dw 0x32
.dw 0x34
.dw 0x36
.dw 0x38
.dw 0x3A
.dw 0x3C
.dw 0x3E
.dw 0x40
.dw 0x42
.dw 0x44
.dw 0x46
.dw 0x48
.dw 0x4A
.dw 0x4C
.dw 0x4E
.dw 0x50
.dw 0x52
.dw 0x54
.dw 0x56
.dw 0x58
.dw 0x5A
.dw 0x5C
.dw 0x5E
.dw 0x60
.dw 0x62
.dw 0x64
.dw 0x66
.dw 0x68
.dw 0x6A
.dw 0x6C
.dw 0x6E
.dw 0x70
.dw 0x72
.dw 0x74
.dw 0x76
.dw 0x78
.dw 0x7A
.dw 0x7C
.dw 0x7E
.dw 0x80
.dw 0x82
.dw 0x84
.dw 0x86
.dw 0x88
.dw 0x8A
.dw 0x8C
.dw 0x8E
.dw 0x90
.dw 0x92
.dw 0x94
.dw 0x96
.dw 0x98
.dw 0x9A
.dw 0x9C
.dw 0x9E
.dw 0xA0
.dw 0xA2
.dw 0xA4
.dw 0xA6
.dw 0xA8
.dw 0xAA
.dw 0xAC
.dw 0xAE
.dw 0xB0
.dw 0xB2
.dw 0xB4
.dw 0xB6
.dw 0xB8
.dw 0xBA
.dw 0xBC
.dw 0xBE
.dw 0xC0
.dw 0xC2
.dw 0xC4
.dw 0xC6
.dw 0xC8
.dw 0xCA
.dw 0xCC
.dw 0xCE
.dw 0xD0
.dw 0xD2
.dw 0xD4
.dw 0xD6
.dw 0xD8
.dw 0xDA
.dw 0xDC
.dw 0xDE
.dw 0xE0
.dw 0xE2
.dw 0xE4
.dw 0xE6
.dw 0xE8
.dw 0xEA
.dw 0xEC
.dw 0xEE
.dw 0xF0
.dw 0xF2
.dw 0xF4
.dw 0xF6
.dw 0xF8
.dw 0xFA
.dw 0xFC
.dw 0xFE
|
stsp/binutils-ia16
| 9,932
|
sim/testsuite/bfin/c_dsp32shift_lhalf_rp.s
|
//Original:/testcases/core/c_dsp32shift_lhalf_rp/c_dsp32shift_lhalf_rp.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
//rl0 = lshift (rl0 by rl0);
R1.L = LSHIFT R1.L BY R0.L;
R2.L = LSHIFT R2.L BY R0.L;
R3.L = LSHIFT R3.L BY R0.L;
R4.L = LSHIFT R4.L BY R0.L;
R5.L = LSHIFT R5.L BY R0.L;
R6.L = LSHIFT R6.L BY R0.L;
R7.L = LSHIFT R7.L BY R0.L;
//CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000003;
CHECKREG r7, 0x00000003;
imm32 r0, 0x00001001;
R1.L = -1;
imm32 r2, 0x00002002;
imm32 r3, 0x00003003;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
imm32 r6, 0x00006006;
imm32 r7, 0x00007007;
R0.L = LSHIFT R0.L BY R1.L;
//rl1 = lshift (rl1 by rl1);
R2.L = LSHIFT R2.L BY R1.L;
R3.L = LSHIFT R3.L BY R1.L;
R4.L = LSHIFT R4.L BY R1.L;
R5.L = LSHIFT R5.L BY R1.L;
R6.L = LSHIFT R6.L BY R1.L;
R7.L = LSHIFT R7.L BY R1.L;
CHECKREG r0, 0x00000800;
//CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00001001;
CHECKREG r3, 0x00001801;
CHECKREG r4, 0x00002002;
CHECKREG r5, 0x00002802;
CHECKREG r6, 0x00003003;
CHECKREG r7, 0x00003803;
imm32 r0, 0x00001001;
imm32 r1, 0x00001001;
R2.L = -15;
imm32 r3, 0x00003003;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
imm32 r6, 0x00006006;
imm32 r7, 0x00007007;
R0.L = LSHIFT R0.L BY R2.L;
R1.L = LSHIFT R1.L BY R2.L;
//rl2 = lshift (rl2 by rl2);
R3.L = LSHIFT R3.L BY R2.L;
R4.L = LSHIFT R4.L BY R2.L;
R5.L = LSHIFT R5.L BY R2.L;
R6.L = LSHIFT R6.L BY R2.L;
R7.L = LSHIFT R7.L BY R2.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
//CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x00001001;
imm32 r1, 0x00001001;
imm32 r2, 0x00002002;
R3.L = -16;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
imm32 r6, 0x00006006;
imm32 r7, 0x00007007;
R0.L = LSHIFT R0.L BY R3.L;
R1.L = LSHIFT R1.L BY R3.L;
R2.L = LSHIFT R2.L BY R3.L;
//rl3 = lshift (rl3 by rl3);
R4.L = LSHIFT R4.L BY R3.L;
R5.L = LSHIFT R5.L BY R3.L;
R6.L = LSHIFT R6.L BY R3.L;
R7.L = LSHIFT R7.L BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
//CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = LSHIFT R0.H BY R0.L;
R1.L = LSHIFT R1.H BY R0.L;
R2.L = LSHIFT R2.H BY R0.L;
R3.L = LSHIFT R3.H BY R0.L;
R4.L = LSHIFT R4.H BY R0.L;
R5.L = LSHIFT R5.H BY R0.L;
R6.L = LSHIFT R6.H BY R0.L;
R7.L = LSHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x10010000;
R1.L = -1;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.L = LSHIFT R0.H BY R1.L;
//rl1 = lshift (rh1 by rl1);
R2.L = LSHIFT R2.H BY R1.L;
R3.L = LSHIFT R3.H BY R1.L;
R4.L = LSHIFT R4.H BY R1.L;
R5.L = LSHIFT R5.H BY R1.L;
R6.L = LSHIFT R6.H BY R1.L;
R7.L = LSHIFT R7.H BY R1.L;
CHECKREG r0, 0x10010800;
//CHECKREG r1, 0x00010001;
CHECKREG r2, 0x20021001;
CHECKREG r3, 0x30031801;
CHECKREG r4, 0x40042002;
CHECKREG r5, 0x50052802;
CHECKREG r6, 0x60063003;
CHECKREG r7, 0x70073803;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
R2.L = -15;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.L = LSHIFT R0.H BY R2.L;
R1.L = LSHIFT R1.H BY R2.L;
//rl2 = lshift (rh2 by rl2);
R3.L = LSHIFT R3.H BY R2.L;
R4.L = LSHIFT R4.H BY R2.L;
R5.L = LSHIFT R5.H BY R2.L;
R6.L = LSHIFT R6.H BY R2.L;
R7.L = LSHIFT R7.H BY R2.L;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
//CHECKREG r2, 0x2002000f;
CHECKREG r3, 0x30030000;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
imm32 r0, 0x10010001;
imm32 r1, 0x10010001;
imm32 r2, 0x20020002;
R3.L = -16;
imm32 r4, 0x40040004;
imm32 r5, 0x50050005;
imm32 r6, 0x60060006;
imm32 r7, 0x70070007;
R0.L = LSHIFT R0.H BY R3.L;
R1.L = LSHIFT R1.H BY R3.L;
R2.L = LSHIFT R2.H BY R3.L;
//rl3 = lshift (rh3 by rl3);
R4.L = LSHIFT R4.H BY R3.L;
R5.L = LSHIFT R5.H BY R3.L;
R6.L = LSHIFT R6.H BY R3.L;
R7.L = LSHIFT R7.H BY R3.L;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020000;
//CHECKREG r3, 0x30030010;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000000;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = LSHIFT R0.L BY R4.L;
R1.H = LSHIFT R1.L BY R4.L;
R2.H = LSHIFT R2.L BY R4.L;
R3.H = LSHIFT R3.L BY R4.L;
//rh4 = lshift (rl4 by rl4);
R5.H = LSHIFT R5.L BY R4.L;
R6.H = LSHIFT R6.L BY R4.L;
R7.H = LSHIFT R7.L BY R4.L;
CHECKREG r0, 0x00010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
//CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
R5.L = -1;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = LSHIFT R0.L BY R5.L;
R1.H = LSHIFT R1.L BY R5.L;
R2.H = LSHIFT R2.L BY R5.L;
R3.H = LSHIFT R3.L BY R5.L;
R4.H = LSHIFT R4.L BY R5.L;
//rh5 = lshift (rl5 by rl5);
R6.H = LSHIFT R6.L BY R5.L;
R7.H = LSHIFT R7.L BY R5.L;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00010002;
CHECKREG r3, 0x00010003;
CHECKREG r4, 0x00020004;
//CHECKREG r5, 0x00020005;
CHECKREG r6, 0x00030006;
CHECKREG r7, 0x00030007;
imm32 r0, 0x00001001;
imm32 r1, 0x00001001;
imm32 r1, 0x00002002;
imm32 r3, 0x00003003;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
R6.L = -15;
imm32 r7, 0x00007007;
R0.H = LSHIFT R0.L BY R6.L;
R1.H = LSHIFT R1.L BY R6.L;
R2.H = LSHIFT R2.L BY R6.L;
R3.H = LSHIFT R3.L BY R6.L;
R4.H = LSHIFT R4.L BY R6.L;
R5.H = LSHIFT R5.L BY R6.L;
//rh6 = lshift (rl6 by rl6);
R7.H = LSHIFT R7.L BY R6.L;
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00002002;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00003003;
CHECKREG r4, 0x00004004;
CHECKREG r5, 0x00005005;
//CHECKREG r6, 0x00006006;
CHECKREG r7, 0x00007007;
imm32 r0, 0x00001001;
imm32 r1, 0x00002001;
imm32 r2, 0x00002002;
imm32 r3, 0x00003003;
imm32 r4, 0x00004004;
imm32 r5, 0x00005005;
imm32 r6, 0x00006006;
R7.L = -16;
R0.H = LSHIFT R0.L BY R7.L;
R1.H = LSHIFT R1.L BY R7.L;
R2.H = LSHIFT R2.L BY R7.L;
R3.H = LSHIFT R3.L BY R7.L;
R4.H = LSHIFT R4.L BY R7.L;
R5.H = LSHIFT R5.L BY R7.L;
R6.H = LSHIFT R6.L BY R7.L;
R7.H = LSHIFT R7.L BY R7.L;
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00002001;
CHECKREG r2, 0x00002002;
CHECKREG r3, 0x00003003;
CHECKREG r4, 0x00004004;
CHECKREG r5, 0x00005005;
CHECKREG r6, 0x00006006;
//CHECKREG r7, 0x00007007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
R4.L = -1;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = LSHIFT R0.H BY R4.L;
R1.H = LSHIFT R1.H BY R4.L;
R2.H = LSHIFT R2.H BY R4.L;
R3.H = LSHIFT R3.H BY R4.L;
//rh4 = lshift (rh4 by rl4);
R5.H = LSHIFT R5.H BY R4.L;
R6.H = LSHIFT R6.H BY R4.L;
R7.H = LSHIFT R7.H BY R4.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00010000;
CHECKREG r3, 0x00010000;
//CHECKREG r4, 0x00020000;
CHECKREG r5, 0x00020000;
CHECKREG r6, 0x00030000;
CHECKREG r7, 0x00030000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
R5.L = -1;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.H = LSHIFT R0.H BY R5.L;
R1.H = LSHIFT R1.H BY R5.L;
R2.H = LSHIFT R2.H BY R5.L;
R3.H = LSHIFT R3.H BY R5.L;
R4.H = LSHIFT R4.H BY R5.L;
//rh5 = lshift (rh5 by rl5);
R6.H = LSHIFT R6.H BY R5.L;
R7.H = LSHIFT R7.H BY R5.L;
CHECKREG r0, 0x08000000;
CHECKREG r1, 0x08000000;
CHECKREG r2, 0x10010000;
CHECKREG r3, 0x18010000;
CHECKREG r4, 0x20020000;
//CHECKREG r5, 0x28020000;
CHECKREG r6, 0x30030000;
CHECKREG r7, 0x38030000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
R6.L = -15;
imm32 r7, 0x70070000;
R0.L = LSHIFT R0.H BY R6.L;
R1.L = LSHIFT R1.H BY R6.L;
R2.L = LSHIFT R2.H BY R6.L;
R3.L = LSHIFT R3.H BY R6.L;
R4.L = LSHIFT R4.H BY R6.L;
R5.L = LSHIFT R5.H BY R6.L;
//rl6 = lshift (rh6 by rl6);
R7.L = LSHIFT R7.H BY R6.L;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020000;
CHECKREG r3, 0x30030000;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
//CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r2, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
R7.L = -16;
R0.H = LSHIFT R0.H BY R7.L;
R1.H = LSHIFT R1.H BY R7.L;
R2.H = LSHIFT R2.H BY R7.L;
R3.H = LSHIFT R3.H BY R7.L;
R4.H = LSHIFT R4.H BY R7.L;
R5.H = LSHIFT R5.H BY R7.L;
R6.H = LSHIFT R6.H BY R7.L;
//rh7 = lshift (rh7 by rl7);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
//CHECKREG r7, -16;
pass
|
stsp/binutils-ia16
| 3,498
|
sim/testsuite/bfin/c_dsp32mac_dr_a1_iu.s
|
//Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp
// Spec Reference: dsp32mac dr_a1 iu (unsigned integer)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x7890afc7;
imm32 r2, 0x52248679;
imm32 r3, 0xd5069007;
imm32 r4, 0xef5c4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c500d;
imm32 r7, 0xf78e950f;
R0.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (IU);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ), A0 = R2.H * R3.L (IU);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ), A0 += R4.H * R5.H (IU);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IU);
R7 = A1.w;
CHECKREG r0, 0xFFFF5ABD;
CHECKREG r1, 0x3E4DBBEB;
CHECKREG r2, 0xFFFF8679;
CHECKREG r3, 0xAE338FC1;
CHECKREG r4, 0xFFFF4569;
CHECKREG r5, 0xF90A98B5;
CHECKREG r6, 0xFFFF500D;
CHECKREG r7, 0x2062BE0D;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0xd3548abd;
imm32 r1, 0x9dbcfec7;
imm32 r2, 0xa9d45679;
imm32 r3, 0xb09d9007;
imm32 r4, 0xcfb9d569;
imm32 r5, 0xd2359d0b;
imm32 r6, 0xe00ca90d;
imm32 r7, 0x678e709f;
R0.H = ( A1 += R1.L * R0.L ) (IU);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (IU);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ) (IU);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (IU);
R7 = A1.w;
CHECKREG r0, 0xFFFF8ABD;
CHECKREG r1, 0xAA761CF8;
CHECKREG r2, 0xFFFF5679;
CHECKREG r3, 0x6ECDE4C3;
CHECKREG r4, 0xFFFFD569;
CHECKREG r5, 0x7F6D61F3;
CHECKREG r6, 0xFFFFA90D;
CHECKREG r7, 0x24CC474B;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0xa354babd;
imm32 r1, 0x9abcdec7;
imm32 r2, 0x77a4e679;
imm32 r3, 0x805a7007;
imm32 r4, 0x9fb3a569;
imm32 r5, 0xa2352a0b;
imm32 r6, 0xb00c10ad;
imm32 r7, 0x9876a10a;
R0.H = A1 , A0 -= R1.L * R0.L (IU);
R1 = A1.w;
R2.H = A1 , A0 += R2.H * R3.L (IU);
R3 = A1.w;
R4.H = A1 , A0 = R4.H * R5.H (IU);
R5 = A1.w;
R6.H = A1 , A0 -= R6.L * R7.H (IU);
R7 = A1.w;
CHECKREG r0, 0xFFFFBABD;
CHECKREG r1, 0x24CC474B;
CHECKREG r2, 0xFFFFE679;
CHECKREG r3, 0x24CC474B;
CHECKREG r4, 0xFFFFA569;
CHECKREG r5, 0x24CC474B;
CHECKREG r6, 0xFFFF10AD;
CHECKREG r7, 0x24CC474B;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x9dbcfec7;
imm32 r2, 0x81245679;
imm32 r3, 0x97060007;
imm32 r4, 0xaf6c4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00c400d;
imm32 r7, 0x678ed30f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (IU);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IU);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IU);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IU);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x80005679;
CHECKREG r3, 0xCC8DA915;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xD2A949A4;
CHECKREG r6, 0x8000400D;
CHECKREG r7, 0xB8CAA44C;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0xe2005ABD;
imm32 r1, 0x0e300000;
imm32 r2, 0x56e49679;
imm32 r3, 0x30Ae5000;
imm32 r4, 0xa000e669;
imm32 r5, 0x01000e70;
imm32 r6, 0xdf4560eD;
imm32 r7, 0x1234567e;
R0.H = ( A1 -= R1.L * R0.L ) (M,IU);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M,IU);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M,IU);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (M,IU);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xB8CAA44C;
CHECKREG r2, 0x80009679;
CHECKREG r3, 0xA4B99A8A;
CHECKREG r4, 0x8000E669;
CHECKREG r5, 0xAA239A8A;
CHECKREG r6, 0x800060ED;
CHECKREG r7, 0xAC776686;
pass
|
stsp/binutils-ia16
| 1,180
|
sim/testsuite/bfin/ashift_flags.s
|
# mach: bfin
.include "testutils.inc"
start
// load r1=0x7fffffff
// load r2=0x80000000
// load r3=0x000000ff
// load r4=0x00000000
loadsym p0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
_dbg r0;
_dbg r1;
_dbg r2;
_dbg r3;
_dbg r4;
R7 = 0;
ASTAT = R7;
r5 = r1 << 0x4 (s);
_DBG ASTAT;
r7=astat;
dbga (r5.h, 0x7fff);
dbga (r5.l, 0xffff);
dbga (r7.h, 0x0300); // V=1, VS=1
dbga (r7.l, 0x8);
R7 = 0;
ASTAT = R7;
r5.h = r1.h << 0x4 (s);
_DBG ASTAT;
r7=astat;
dbga (r5.h, 0x7fff);
dbga (r7.h, 0x0300); // V=1, VS=1
dbga (r7.l, 0x8);
A0 = 0;
A0.w = r1;
A0.x = r0.l;
r6 = 0x3;
_dbg r6;
_dbg A0;
R7 = 0;
ASTAT = R7;
A0 = ASHIFT A0 BY R6.L;
_DBG ASTAT;
_DBG A0;
r7 = astat;
dbga (r7.h, 0x0); // AV0=0, AV0S=0
dbga (r7.l, 0x2); // AN = 1
A1 = 0;
A1 = r1;
A1.x = r0.l;
r6 = 0x3;
_dbg A1;
R7 = 0;
ASTAT = R7;
A1 = ASHIFT A1 BY R6.L;
_DBG ASTAT;
_DBG A1;
r7 = astat;
dbga (r7.h, 0x0); // AV1=0, AV1S=0
dbga (r7.l, 0x2); // AN = 1
pass
.data 0x1000;
data0:
.dw 0x1111
.dw 0x1111
.dw 0xffff
.dw 0x7fff
.dw 0x0000
.dw 0x8000
.dw 0x00ff
.dw 0x0000
.dw 0x0000
.dw 0x0000
|
stsp/binutils-ia16
| 4,914
|
sim/testsuite/bfin/fir.s
|
# mach: bfin
// FIR FILTER COMPTUED DIRECTLY ON INPUT WITH NO
// INTERNAL STATE
// TWO OUTPUTS PER ITERATION
// This program computes a FIR filter without maintaining a buffer of internal
// state.
// This example computes two output samples per inner loop. The following
// diagram shows the alignment required for signal x and coefficients c:
// x0 x1 x2 x3 x4 x5
// c0 c1 c2 c3 c4 -> output z(0)=x0*c0 + x1*c1 + ...
// c0 c1 c2 c3 c4 -> z(1)=x1*c0 + x2*c1 + ...
// L-1
// ---
// Z(k) = \ c(n) * x(n+k)
// /
// ---
// n=0
// Naive, first stab at spliting this for dual MACS.
// L/2-1 L/2-1
// --- ---
// R(k) = \ (x(2n) * y(2n+k)) + \ (x(2n-1) * y(2n-1+k))
// / /
// --- ---
// n=0 n=0
// Alternate, better partitioning for the machine.
// L-1
// ---
// R(0) = \ x(n) * y(n)
// /
// ---
// n=0
// L-1
// ---
// R(1) = \ x(n) * y(n+1)
// /
// ---
// n=0
// L-1
// ---
// R(2) = \ x(n) * y(n+2)
// /
// ---
// n=0
// L-1
// ---
// R(3) = \ x(n) * y(n+3)
// /
// ---
// n=0
// .
// .
// .
// .
// Okay in this verion the inner loop will compute R(2k) and R(2k+1) in parallel
// L-1
// ---
// R(2k) = \ x(n) * y(n+2k)
// /
// ---
// n=0
// L-1
// ---
// R(2k+1) = \ x(n) * y(n+2k+1)
// /
// ---
// n=0
// Implementation
// --------------
// Sample pair x1 x0 is loaded into register R0, and coefficients c1 c0
// is loaded into register R1:
// +-------+ R0
// | x1 x0 |
// +-------+
// +-------+ R1
// | c1 c0 | compute two MACs: z(0)+=x0*c0, and z(1)+=x1*c0
// +-------+
// Now load x2 into lo half of R0, and compute the next two MACs:
// +-------+ R0
// | x1 x2 |
// +-------+
// +-------+ R1
// | c1 c0 | compute z(0)+=x1*c1 and z(1)+=x2*c1 (c0 not used)
// +-------+
// Meanwhile, load coefficient pair c3 c2 into R2, and x3 into hi half of R0:
// +-------+ R0
// | x3 x2 |
// +-------+
// +-------+ R2
// | c3 c2 | compute z(0)+=x2*c2 and z(1)+=x3*c2 (c3 not used)
// +-------+
// Load x4 into low half of R0:
// +-------+ R0
// | x3 x4 |
// +-------+
// +-------+ R1
// | c3 c2 | compute z(0)+=x3*c3 and z(1)+=x4*c3 (c2 not used)
// +-------+
// //This is a reference FIR function used to test: */
//void firf (float input[], float output[], float coeffs[],
// long input_size, long coeffs_size)
//{
// long i, k;
// for(i=0; i< input_size; i++){
// output[i] = 0;
// for(k=0; k < coeffs_size; k++)
// output[i] += input[k+i] * coeffs[k];
// }
//}
.include "testutils.inc"
start
R0 = 0; R1 = 0; R2 = 0;
P1 = 128 (X); // Load loop bounds in R5, R6, and divide by 2
P2 = 64 (X);
// P0 holds pointer to input data in one memory
// bank. Increments by 2 after each inner-loop iter
loadsym P0, input;
// Pointer to coeffs in alternate memory bank.
loadsym I1, coef;
// Pointer to outputs in any memory bank.
loadsym I2, output;
// Setup outer do-loop for M/2 iterations
// (2 outputs are computed per pass)
LSETUP ( L$0 , L$0end ) LC0 = P1 >> 1;
L$0:
loadsym I1, coef;
I0 = P0;
// Set-up inner do-loop for L/2 iterations
// (2 MACs are computed per pass)
LSETUP ( L$1 , L$1end ) LC1 = P2 >> 1;
// Load first two data elements in r0,
// and two coeffs into r1:
R0.L = W [ I0 ++ ];
A1 = A0 = 0 || R0.H = W [ I0 ++ ] || R1 = [ I1 ++ ];
L$1:
A1 += R0.H * R1.L, A0 += R0.L * R1.L || R0.L = W [ I0 ++ ] || NOP;
L$1end:
A1 += R0.L * R1.H, A0 += R0.H * R1.H || R0.H = W [ I0 ++ ] || R1 = [ I1 ++ ];
// Line 1: do 2 MACs and load next data element into RL0.
// Line 2: do 2 MACs, load next data element into RH0,
// and load next 2 coeffs
R0.H = A1, R0.L = A0;
// advance data pointer by 2 16b elements
P0 += 4;
L$0end:
[ I2 ++ ] = R0; // store 2 outputs
// Check results
loadsym I2, output;
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0800 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1000 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2000 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1000 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0800 );
pass
.data
input:
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x4000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
.space ((128-10)*2); // must pad with zeros or uninitialized values.
.data
coef:
.dw 0x1000
.dw 0x2000
.dw 0x4000
.dw 0x2000
.dw 0x1000
.dw 0x0000
.space ((64-6)*2); // must pad with zeros or uninitialized values.
.data
output:
.space (128*4)
|
stsp/binutils-ia16
| 6,094
|
sim/testsuite/bfin/c_dsp32mult_dr_u.s
|
//Original:/testcases/core/c_dsp32mult_dr_u/c_dsp32mult_dr_u.dsp
// Spec Reference: dsp32mult single dr u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (FU);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (FU);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (FU);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (FU);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (FU);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (FU);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (FU);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (FU);
CHECKREG r0, 0x1CFD1CFD;
CHECKREG r1, 0x0930114B;
CHECKREG r2, 0x01F5010A;
CHECKREG r3, 0x012B0054;
CHECKREG r4, 0x1CFD1CFD;
CHECKREG r5, 0x1B4F3365;
CHECKREG r6, 0x1B4F3365;
CHECKREG r7, 0x19BA5B1D;
imm32 r0, 0x9923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1324b735;
imm32 r3, 0x99060037;
imm32 r4, 0x809bcd39;
imm32 r5, 0xb0a99f3b;
imm32 r6, 0xa00c093d;
imm32 r7, 0x12467093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (FU);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (FU);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (FU);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (FU);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (FU);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (FU);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (FU);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (FU);
CHECKREG r0, 0x00700070;
CHECKREG r1, 0x00430043;
CHECKREG r2, 0x0DB30DB3;
CHECKREG r3, 0x08300830;
CHECKREG r4, 0x0DB30DB3;
CHECKREG r5, 0x6D830B71;
CHECKREG r6, 0x00270004;
CHECKREG r7, 0x00210021;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (FU);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (FU);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (FU);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (FU);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (FU);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (FU);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (FU);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (FU);
CHECKREG r0, 0x6F5997A7;
CHECKREG r1, 0x87430CD5;
CHECKREG r2, 0x0CD50CD5;
CHECKREG r3, 0xDFCB0116;
CHECKREG r4, 0x6F5997A7;
CHECKREG r5, 0x681C8DCB;
CHECKREG r6, 0x53FF3DAC;
CHECKREG r7, 0x39AA2A57;
imm32 r0, 0xb9235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x19248766;
imm32 r3, 0xe0960066;
imm32 r4, 0x9ea99d69;
imm32 r5, 0x10ec9f6b;
imm32 r6, 0x800e906d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (FU);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (FU);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (FU);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (FU);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (FU);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (FU);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (FU);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (FU);
CHECKREG r0, 0x400E517B;
CHECKREG r1, 0x09240A4F;
CHECKREG r2, 0x09240A4F;
CHECKREG r3, 0x014E014E;
CHECKREG r4, 0x01250174;
CHECKREG r5, 0x00150015;
CHECKREG r6, 0x400E517B;
CHECKREG r7, 0x049205D1;
// mix order
imm32 r0, 0x9923a675;
imm32 r1, 0xcf995127;
imm32 r2, 0x13c49705;
imm32 r3, 0x05069007;
imm32 r4, 0x90accd09;
imm32 r5, 0x10ac9fdb;
imm32 r6, 0x000cc90d;
imm32 r7, 0x1246fc9f;
R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (FU);
R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (FU);
R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (FU);
R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (FU);
R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (FU);
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (FU);
R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (FU);
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (FU);
CHECKREG r0, 0xA4430AEE;
CHECKREG r1, 0x3FBC0004;
CHECKREG r2, 0x0C580C58;
CHECKREG r3, 0x735B735B;
CHECKREG r4, 0x5C645C64;
CHECKREG r5, 0x00CE00CE;
CHECKREG r6, 0x00030003;
CHECKREG r7, 0x00C80BBA;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (FU);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (FU);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (FU);
R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (FU);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (FU);
R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (FU);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (FU);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (FU);
CHECKREG r0, 0x0C370675;
CHECKREG r1, 0x000A0423;
CHECKREG r2, 0x0E6706D7;
CHECKREG r3, 0x0079758F;
CHECKREG r4, 0x00440061;
CHECKREG r5, 0x00F00D62;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x007600DF;
imm32 r0, 0xee235675;
imm32 r1, 0xcfea5127;
imm32 r2, 0x13fe6705;
imm32 r3, 0x000fe007;
imm32 r4, 0x90abfe09;
imm32 r5, 0x10acefeb;
imm32 r6, 0x000c00fe;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (FU);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (FU);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (FU);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (FU);
R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (FU);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (FU);
R6.H = R6.H * R5.L, R6.L = R6.L * R5.H (FU);
R7.H = R7.L * R4.L, R7.L = R7.H * R4.H (FU);
CHECKREG r0, 0x00010050;
CHECKREG r1, 0x1CDA0C0D;
CHECKREG r2, 0x00560004;
CHECKREG r3, 0x0ED75B03;
CHECKREG r4, 0x00040055;
CHECKREG r5, 0x0DE805ED;
CHECKREG r6, 0x0000000E;
CHECKREG r7, 0x00250000;
imm32 r0, 0xfb2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13f46d05;
imm32 r3, 0x000f00d7;
imm32 r4, 0x908bfd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c5f0d;
imm32 r7, 0x124676ff;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (FU);
R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (FU);
R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (FU);
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (FU);
R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (FU);
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (FU);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (FU);
R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (FU);
CHECKREG r0, 0x08B12F7B;
CHECKREG r1, 0x03172C7C;
CHECKREG r2, 0x00010000;
CHECKREG r3, 0x00280007;
CHECKREG r4, 0x662512B2;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x11C0003A;
pass
|
stsp/binutils-ia16
| 2,626
|
sim/testsuite/bfin/m3.s
|
// MAC test program.
// Test basic edge values
// UNSIGNED FRACTIONAL mode U
// test ops: "+=" "-="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
// load r5=0xffffffff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
dbga(r0.h, 0x8000);
dbga(r0.l, 0x7fff);
dbga(r1.h, 0x8000);
dbga(r1.l, 0x7fff);
dbga(r2.h, 0xf000);
dbga(r2.l, 0);
// 0x8000 * 0x7fff = 0x003fff8000
A1 = A0 = 0;
A1 += R0.H * R1.L, A0 += R0.H * R1.L (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x8000 );
DBGA ( R6.H , 0x3fff );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x8000 );
DBGA ( R6.H , 0x3fff );
DBGA ( R7.L , 0x0000 );
// 0x8000 * 0x8000 = 0x0040000000
A1 = A0 = 0;
A1 += R0.H * R1.H, A0 += R0.H * R1.H (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x4000 );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x4000 );
DBGA ( R7.L , 0x0000 );
// 0xffff * 0xffff = 0x00fffe0001
A1 = A0 = 0;
A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0001 );
DBGA ( R6.H , 0xfffe );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0001 );
DBGA ( R6.H , 0xfffe );
DBGA ( R7.L , 0x0000 );
// saturate high by first loading large value into accums
// expected value is 0xffffffffff
A1 = A0 = 0;
A1.w = R5;
A1.x = R5.L;
A0.w = R5;
A0.x = R5.L;
A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0xffff );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0xffff );
// saturate low with "-="
// expected value is 0x0000000000
A1 = A0 = 0;
A1 -= R4.L * R4.L, A0 -= R4.L * R4.L (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
// saturate low with "-="
// expected value is 0x0000000000
A1 = A0 = 0;
A1 -= R1.H * R0.H, A0 -= R1.H * R0.H (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
pass
.data
data0:
.dw 0x7fff
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
.dw 0xffff
.dw 0xffff
|
stsp/binutils-ia16
| 7,160
|
sim/testsuite/bfin/c_ldstpmod_ld_dr_lo.s
|
//Original:testcases/core/c_ldstpmod_ld_dr_lo/c_ldstpmod_ld_dr_lo.dsp
// Spec Reference: c_ldstpmod load dr lo
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS(0);
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_2, 0x04;
loadsym p2, DATA_ADDR_3, 0x04;
loadsym i1, DATA_ADDR_4, 0x04;
loadsym p4, DATA_ADDR_5, 0x08;
loadsym p5, DATA_ADDR_1, 0x08;
loadsym fp, DATA_ADDR_6, 0x08;
loadsym i3, DATA_ADDR_7, 0x0c;
P3 = I1; SP = I3;
R0.L = W [ P1 ];
R1.L = W [ P1 ];
R2.L = W [ P1 ];
R3.L = W [ P1 ];
R4.L = W [ P1 ];
R5.L = W [ P1 ];
R6.L = W [ P1 ];
R7.L = W [ P1 ];
CHECKREG r0, 0x00002627;
CHECKREG r1, 0x00002627;
CHECKREG r2, 0x00002627;
CHECKREG r3, 0x00002627;
CHECKREG r4, 0x00002627;
CHECKREG r5, 0x00002627;
CHECKREG r6, 0x00002627;
CHECKREG r7, 0x00002627;
R0.L = W [ P2 ];
R1.L = W [ P2 ];
R2.L = W [ P2 ];
R3.L = W [ P2 ];
R4.L = W [ P2 ];
R5.L = W [ P2 ];
R6.L = W [ P2 ];
R7.L = W [ P2 ];
CHECKREG r0, 0x00004647;
CHECKREG r1, 0x00004647;
CHECKREG r2, 0x00004647;
CHECKREG r3, 0x00004647;
CHECKREG r4, 0x00004647;
CHECKREG r5, 0x00004647;
CHECKREG r6, 0x00004647;
CHECKREG r7, 0x00004647;
R0.L = W [ P3 ];
R1.L = W [ P3 ];
R2.L = W [ P3 ];
R3.L = W [ P3 ];
R4.L = W [ P3 ];
R5.L = W [ P3 ];
R6.L = W [ P3 ];
R7.L = W [ P3 ];
CHECKREG r0, 0x00006667;
CHECKREG r1, 0x00006667;
CHECKREG r2, 0x00006667;
CHECKREG r3, 0x00006667;
CHECKREG r4, 0x00006667;
CHECKREG r5, 0x00006667;
CHECKREG r6, 0x00006667;
CHECKREG r7, 0x00006667;
R0.L = W [ P4 ];
R1.L = W [ P4 ];
R2.L = W [ P4 ];
R3.L = W [ P4 ];
R4.L = W [ P4 ];
R5.L = W [ P4 ];
R6.L = W [ P4 ];
R7.L = W [ P4 ];
CHECKREG r0, 0x00008A8B;
CHECKREG r1, 0x00008A8B;
CHECKREG r2, 0x00008A8B;
CHECKREG r3, 0x00008A8B;
CHECKREG r4, 0x00008A8B;
CHECKREG r5, 0x00008A8B;
CHECKREG r6, 0x00008A8B;
CHECKREG r7, 0x00008A8B;
R0.L = W [ P5 ];
R1.L = W [ P5 ];
R2.L = W [ P5 ];
R3.L = W [ P5 ];
R4.L = W [ P5 ];
R5.L = W [ P5 ];
R6.L = W [ P5 ];
R7.L = W [ P5 ];
CHECKREG r0, 0x00000A0B;
CHECKREG r1, 0x00000A0B;
CHECKREG r2, 0x00000A0B;
CHECKREG r3, 0x00000A0B;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000A0B;
CHECKREG r6, 0x00000A0B;
CHECKREG r7, 0x00000A0B;
R0.L = W [ SP ];
R1.L = W [ SP ];
R2.L = W [ SP ];
R3.L = W [ SP ];
R4.L = W [ SP ];
R5.L = W [ SP ];
R6.L = W [ SP ];
R7.L = W [ SP ];
CHECKREG r0, 0x00008E8F;
CHECKREG r1, 0x00008E8F;
CHECKREG r2, 0x00008E8F;
CHECKREG r3, 0x00008E8F;
CHECKREG r4, 0x00008E8F;
CHECKREG r5, 0x00008E8F;
CHECKREG r6, 0x00008E8F;
CHECKREG r7, 0x00008E8F;
R0.L = W [ FP ];
R1.L = W [ FP ];
R2.L = W [ FP ];
R3.L = W [ FP ];
R4.L = W [ FP ];
R5.L = W [ FP ];
R6.L = W [ FP ];
R7.L = W [ FP ];
CHECKREG r0, 0x00000A0B;
CHECKREG r1, 0x00000A0B;
CHECKREG r2, 0x00000A0B;
CHECKREG r3, 0x00000A0B;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000A0B;
CHECKREG r6, 0x00000A0B;
CHECKREG r7, 0x00000A0B;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
stsp/binutils-ia16
| 5,107
|
sim/testsuite/bfin/c_dsp32shift_expadj_l.s
|
//Original:/testcases/core/c_dsp32shift_expadj_l/c_dsp32shift_expadj_l.dsp
// Spec Reference: dsp32shift expadj rl
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000c006;
imm32 r7, 0x0000c007;
R1.L = EXPADJ( R1.L , R0.L );
R2.L = EXPADJ( R2.L , R0.L );
R3.L = EXPADJ( R3.L , R0.L );
R4.L = EXPADJ( R4.L , R0.L );
R5.L = EXPADJ( R5.L , R0.L );
R6.L = EXPADJ( R6.L , R0.L );
R7.L = EXPADJ( R7.L , R0.L );
R0.L = EXPADJ( R0.L , R0.L );
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x11001001;
imm32 r1, 0x11001001;
imm32 r2, 0x11001002;
imm32 r3, 0x11001003;
imm32 r4, 0x11001004;
imm32 r5, 0x11001005;
imm32 r6, 0x11001006;
imm32 r7, 0x11001007;
R0.L = EXPADJ( R0.L , R1.L );
R2.L = EXPADJ( R2.L , R1.L );
R3.L = EXPADJ( R3.L , R1.L );
R4.L = EXPADJ( R4.L , R1.L );
R5.L = EXPADJ( R5.L , R1.L );
R6.L = EXPADJ( R6.L , R1.L );
R7.L = EXPADJ( R7.L , R1.L );
R1.L = EXPADJ( R1.L , R1.L );
CHECKREG r0, 0x11001001;
CHECKREG r1, 0x11001001;
CHECKREG r2, 0x11001001;
CHECKREG r3, 0x11001001;
CHECKREG r4, 0x11001001;
CHECKREG r5, 0x11001001;
CHECKREG r6, 0x11001001;
CHECKREG r7, 0x11001001;
imm32 r0, 0x2000c001;
imm32 r1, 0x2000d001;
imm32 r2, 0x2000000f;
imm32 r3, 0x2000e003;
imm32 r4, 0x2000f004;
imm32 r5, 0x2000f005;
imm32 r6, 0x2000f006;
imm32 r7, 0x2000f007;
R0.L = EXPADJ( R0.L , R2.L );
R1.L = EXPADJ( R1.L , R2.L );
R3.L = EXPADJ( R3.L , R2.L );
R4.L = EXPADJ( R4.L , R2.L );
R5.L = EXPADJ( R5.L , R2.L );
R6.L = EXPADJ( R6.L , R2.L );
R7.L = EXPADJ( R7.L , R2.L );
R2.L = EXPADJ( R2.L , R2.L );
CHECKREG r0, 0x20000001;
CHECKREG r1, 0x20000001;
CHECKREG r2, 0x2000000B;
CHECKREG r3, 0x20000002;
CHECKREG r4, 0x20000003;
CHECKREG r5, 0x20000003;
CHECKREG r6, 0x20000003;
CHECKREG r7, 0x20000003;
imm32 r0, 0x30009001;
imm32 r1, 0x3000a001;
imm32 r2, 0x3000b002;
imm32 r3, 0x30000010;
imm32 r4, 0x3000c004;
imm32 r5, 0x3000d005;
imm32 r6, 0x3000e006;
imm32 r7, 0x3000f007;
R0.L = EXPADJ( R0.L , R3.L );
R1.L = EXPADJ( R1.L , R3.L );
R2.L = EXPADJ( R2.L , R3.L );
R4.L = EXPADJ( R4.L , R3.L );
R5.L = EXPADJ( R5.L , R3.L );
R6.L = EXPADJ( R6.L , R3.L );
R7.L = EXPADJ( R7.L , R3.L );
R3.L = EXPADJ( R3.L , R3.L );
CHECKREG r0, 0x30000010;
CHECKREG r1, 0x30000010;
CHECKREG r2, 0x30000010;
CHECKREG r3, 0x30000010;
CHECKREG r4, 0x30000010;
CHECKREG r5, 0x30000010;
CHECKREG r6, 0x30000010;
CHECKREG r7, 0x30000010;
imm32 r0, 0x40000000;
imm32 r1, 0x4000c001;
imm32 r2, 0x4000c002;
imm32 r3, 0x4000c003;
imm32 r4, 0x4000c004;
imm32 r5, 0x4000c005;
imm32 r6, 0x4000c006;
imm32 r7, 0x4000c007;
R0.L = EXPADJ( R1.L , R4.L );
R1.L = EXPADJ( R2.L , R4.L );
R2.L = EXPADJ( R3.L , R4.L );
R3.L = EXPADJ( R4.L , R4.L );
R5.L = EXPADJ( R5.L , R4.L );
R6.L = EXPADJ( R6.L , R4.L );
R7.L = EXPADJ( R7.L , R4.L );
R4.L = EXPADJ( R0.L , R4.L );
CHECKREG r0, 0x40000001;
CHECKREG r1, 0x40000001;
CHECKREG r2, 0x40000001;
CHECKREG r3, 0x40000001;
CHECKREG r4, 0x4000C004;
CHECKREG r5, 0x40000001;
CHECKREG r6, 0x40000001;
CHECKREG r7, 0x40000001;
imm32 r0, 0x51001001;
imm32 r1, 0x51001001;
imm32 r2, 0x51001002;
imm32 r3, 0x51001003;
imm32 r4, 0x51001004;
imm32 r5, 0x51001005;
imm32 r6, 0x51001006;
imm32 r7, 0x51001007;
R0.L = EXPADJ( R0.L , R5.L );
R1.L = EXPADJ( R2.L , R5.L );
R2.L = EXPADJ( R3.L , R5.L );
R3.L = EXPADJ( R4.L , R5.L );
R4.L = EXPADJ( R5.L , R5.L );
R6.L = EXPADJ( R6.L , R5.L );
R7.L = EXPADJ( R7.L , R5.L );
R5.L = EXPADJ( R1.L , R5.L );
CHECKREG r0, 0x51000002;
CHECKREG r1, 0x51000002;
CHECKREG r2, 0x51000002;
CHECKREG r3, 0x51000002;
CHECKREG r4, 0x51000002;
CHECKREG r5, 0x51001005;
CHECKREG r6, 0x51000002;
CHECKREG r7, 0x51000002;
imm32 r0, 0x6000c001;
imm32 r1, 0x6000d001;
imm32 r2, 0x6000000f;
imm32 r3, 0x6000e003;
imm32 r4, 0x6000f004;
imm32 r5, 0x6000f005;
imm32 r6, 0x6000f006;
imm32 r7, 0x6000f007;
R0.L = EXPADJ( R0.L , R6.L );
R1.L = EXPADJ( R1.L , R6.L );
R2.L = EXPADJ( R3.L , R6.L );
R3.L = EXPADJ( R4.L , R6.L );
R4.L = EXPADJ( R5.L , R6.L );
R5.L = EXPADJ( R6.L , R6.L );
R7.L = EXPADJ( R7.L , R6.L );
R6.L = EXPADJ( R2.L , R6.L );
CHECKREG r0, 0x60000001;
CHECKREG r1, 0x60000001;
CHECKREG r2, 0x60000002;
CHECKREG r3, 0x60000003;
CHECKREG r4, 0x60000003;
CHECKREG r5, 0x60000003;
CHECKREG r6, 0x6000F006;
CHECKREG r7, 0x60000003;
imm32 r0, 0x70009001;
imm32 r1, 0x7000a001;
imm32 r2, 0x7000b002;
imm32 r3, 0x70000010;
imm32 r4, 0x7000c004;
imm32 r5, 0x7000d005;
imm32 r6, 0x7000e006;
imm32 r7, 0x7000f007;
R0.L = EXPADJ( R0.L , R7.L );
R1.L = EXPADJ( R1.L , R7.L );
R2.L = EXPADJ( R2.L , R7.L );
R3.L = EXPADJ( R4.L , R7.L );
R4.L = EXPADJ( R5.L , R7.L );
R5.L = EXPADJ( R6.L , R7.L );
R6.L = EXPADJ( R7.L , R7.L );
R7.L = EXPADJ( R3.L , R7.L );
CHECKREG r0, 0x70000000;
CHECKREG r1, 0x70000000;
CHECKREG r2, 0x70000000;
CHECKREG r3, 0x70000001;
CHECKREG r4, 0x70000001;
CHECKREG r5, 0x70000002;
CHECKREG r6, 0x70000003;
CHECKREG r7, 0x7000F007;
pass
|
stsp/binutils-ia16
| 4,844
|
sim/testsuite/bfin/c_dsp32mult_dr_m_i.s
|
//Original:/testcases/core/c_dsp32mult_dr_m_i/c_dsp32mult_dr_m_i.dsp
// Spec Reference: dsp32mult single dr munop i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm32 r7, 0xd24f702f;
R4.L = R0.H * R0.L (IS);
R5.H = R0.L * R1.L (IS);
R6.L = R1.L * R0.H (IS);
R7.L = R1.L * R1.L (IS);
R0.H = R0.L * R0.L (IS);
R1.L = R0.L * R1.L (IS);
R2.L = R1.H * R0.L (IS);
R3.H = R1.L * R1.L (IS);
CHECKREG r0, 0x7FFF5625;
CHECKREG r1, 0x9FBA7FFF;
CHECKREG r2, 0xA3FF8000;
CHECKREG r3, 0x7FFFF027;
CHECKREG r4, 0xB0AB8000;
CHECKREG r5, 0x7FFFEF2B;
CHECKREG r6, 0xC0FC8000;
CHECKREG r7, 0xD24F7FFF;
imm32 r0, 0xeb23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b7e5;
imm32 r3, 0x9e060037;
imm32 r4, 0x80ebcd39;
imm32 r5, 0xb0aeef3b;
imm32 r6, 0xa00ce03d;
imm32 r7, 0x12467e03;
R5.H = R2.L * R2.L (IS);
R6.L = R2.L * R3.H (IS);
R7.L = R3.H * R2.L (IS);
R0.H = R3.L * R3.L (IS);
R1.H = R2.L * R2.H (IS);
R2.L = R2.H * R3.H (IS);
R3.H = R3.L * R2.L (IS);
R4.L = R3.L * R3.L (IS);
CHECKREG r0, 0x0BD1A635;
CHECKREG r1, 0x80005137;
CHECKREG r2, 0x13248000;
CHECKREG r3, 0x80000037;
CHECKREG r4, 0x80EB0BD1;
CHECKREG r5, 0x7FFFEF3B;
CHECKREG r6, 0xA00C7FFF;
CHECKREG r7, 0x12467FFF;
imm32 r0, 0xdd235655;
imm32 r1, 0xc4dd5157;
imm32 r2, 0x6324d755;
imm32 r3, 0x00060055;
imm32 r4, 0x90dbc509;
imm32 r5, 0x10adef5b;
imm32 r6, 0xb00cd05d;
imm32 r7, 0x12467d5f;
R0.L = R4.L * R4.H (IS);
R1.H = R4.H * R5.L (IS);
R2.L = R5.H * R4.L (IS);
R3.L = R5.L * R5.L (IS);
R4.H = R4.L * R4.H (IS);
R5.L = R4.L * R5.H (IS);
R6.H = R5.H * R4.H (IS);
R7.L = R5.H * R5.H (IS);
CHECKREG r0, 0xDD237FFF;
CHECKREG r1, 0x7FFF5157;
CHECKREG r2, 0x63248000;
CHECKREG r3, 0x00067FFF;
CHECKREG r4, 0x7FFFC509;
CHECKREG r5, 0x10AD8000;
CHECKREG r6, 0x7FFFD05D;
CHECKREG r7, 0x12467FFF;
imm32 r0, 0xcb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x1c248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90cb9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cc06d;
imm32 r7, 0x12467c6f;
// test the unsigned U=1
R0.L = R6.L * R6.L (IS);
R1.H = R6.H * R7.L (IS);
R2.L = R7.L * R6.L (IS);
R3.L = R7.L * R7.L (IS);
R6.H = R6.H * R6.H (IS);
R7.L = R6.L * R7.L (IS);
R4.H = R7.H * R6.H (IS);
R5.L = R7.L * R7.L (IS);
CHECKREG r0, 0xCB237FFF;
CHECKREG r1, 0x80005166;
CHECKREG r2, 0x1C248000;
CHECKREG r3, 0xF0067FFF;
CHECKREG r4, 0x7FFF9D69;
CHECKREG r5, 0x10AC7FFF;
CHECKREG r6, 0x7FFFC06D;
CHECKREG r7, 0x12468000;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0xe0060007;
imm32 r4, 0x9eabcd09;
imm32 r5, 0x10ecdfdb;
imm32 r6, 0x000e000d;
imm32 r7, 0x1246e00f;
R0.H = R0.L * R7.H (IS);
R1.L = R1.H * R6.H (IS);
R2.L = R2.L * R5.L (IS);
R3.H = R3.H * R4.H (IS);
R4.L = R4.L * R3.H (IS);
R5.L = R5.H * R2.H (IS);
R6.H = R6.H * R1.L (IS);
R7.L = R7.L * R0.H (IS);
CHECKREG r0, 0x8000A675;
CHECKREG r1, 0xCFBA8000;
CHECKREG r2, 0x13248000;
CHECKREG r3, 0x7FFF0007;
CHECKREG r4, 0x9EAB8000;
CHECKREG r5, 0x10EC7FFF;
CHECKREG r6, 0x8000000D;
CHECKREG r7, 0x12467FFF;
imm32 r0, 0x9b235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x93246905;
imm32 r3, 0x09060007;
imm32 r4, 0x909bcd09;
imm32 r5, 0x10a9e9db;
imm32 r6, 0x000c9d0d;
imm32 r7, 0x1246790f;
R0.L = R7.L * R0.H (IS);
R1.L = R6.L * R1.L (IS);
R2.H = R5.L * R2.L (IS);
R3.L = R4.H * R3.L (IS);
R4.L = R3.H * R4.H (IS);
R5.H = R2.H * R5.L (IS);
R6.L = R1.H * R6.L (IS);
R7.L = R0.L * R7.L (IS);
CHECKREG r0, 0x9B238000;
CHECKREG r1, 0xCFBA8000;
CHECKREG r2, 0x80006905;
CHECKREG r3, 0x09068000;
CHECKREG r4, 0x909B8000;
CHECKREG r5, 0x7FFFE9DB;
CHECKREG r6, 0x000C7FFF;
CHECKREG r7, 0x12468000;
imm32 r0, 0xa9235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x08060007;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a88fdb;
imm32 r6, 0x000c080d;
imm32 r7, 0x1246708f;
R2.L = R0.L * R6.L (IS);
R3.L = R1.H * R7.L (IS);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS);
R1.H = R3.L * R1.L (IS);
R4.L = R4.H * R2.L (IS);
R5.L = R5.L * R3.L (IS);
R6.L = R6.L * R4.L (IS);
R7.H = R7.H * R5.L (IS);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x80005127;
CHECKREG r2, 0x13247FFF;
CHECKREG r3, 0x08068000;
CHECKREG r4, 0x908B8000;
CHECKREG r5, 0x10A87FFF;
CHECKREG r6, 0x000C8000;
CHECKREG r7, 0x7FFF708F;
imm32 r0, 0x7b235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x17246705;
imm32 r3, 0x00760007;
imm32 r4, 0x907bcd09;
imm32 r5, 0x10a7efdb;
imm32 r6, 0x000c700d;
imm32 r7, 0x1246770f;
R4.L = R5.L * R2.L (IS);
R6.L = R6.L * R3.H (IS);
R0.H = R7.L * R4.H (IS);
R1.L = R0.H * R5.L (IS);
R2.L = R1.L * R6.L (IS);
R5.L = R2.L * R7.H (IS);
R3.H = R3.H * R0.L (IS);
R7.L = R4.H * R1.H (IS);
CHECKREG r0, 0x80005675;
CHECKREG r1, 0xCFBA7FFF;
CHECKREG r2, 0x17247FFF;
CHECKREG r3, 0x7FFF0007;
CHECKREG r4, 0x907B8000;
CHECKREG r5, 0x10A77FFF;
CHECKREG r6, 0x000C7FFF;
CHECKREG r7, 0x12467FFF;
pass
|
stsp/binutils-ia16
| 7,579
|
sim/testsuite/bfin/c_ldst_st_p_d_pp_h.s
|
//Original:/testcases/core/c_ldst_st_p_d_pp_h/c_ldst_st_p_d_pp_h.dsp
// Spec Reference: c_ldst st_p++/p-- h half
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// half word 16-bit store incremented by 2
W [ P5 ++ ] = R0;
W [ P1 ++ ] = R1;
W [ P2 ++ ] = R2;
W [ P4 ++ ] = R4;
W [ FP ++ ] = R5;
W [ P5 ++ ] = R1;
W [ P1 ++ ] = R2;
W [ P2 ++ ] = R3;
W [ P4 ++ ] = R5;
W [ FP ++ ] = R6;
W [ P5 ++ ] = R2;
W [ P1 ++ ] = R3;
W [ P2 ++ ] = R4;
W [ P4 ++ ] = R6;
W [ FP ++ ] = R7;
W [ P5 ++ ] = R3;
W [ P1 ++ ] = R4;
W [ P2 ++ ] = R5;
W [ P4 ++ ] = R7;
W [ FP ++ ] = R0;
W [ P5 ++ ] = R4;
W [ P1 ++ ] = R5;
W [ P2 ++ ] = R6;
W [ P4 ++ ] = R0;
W [ FP ++ ] = R1;
W [ P5 ++ ] = R5;
W [ P1 ++ ] = R6;
W [ P2 ++ ] = R7;
W [ P4 ++ ] = R1;
W [ FP ++ ] = R2;
W [ P5 ++ ] = R6;
W [ P1 ++ ] = R7;
W [ P2 ++ ] = R0;
W [ P4 ++ ] = R2;
W [ FP ++ ] = R3;
W [ P5 ++ ] = R7;
W [ P1 ++ ] = R0;
W [ P2 ++ ] = R1;
W [ P4 ++ ] = R3;
W [ FP ++ ] = R4;
// Read back and check
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P1 ++ ];
R1 = [ P2 ++ ];
R3 = [ P4 ++ ];
R4 = [ P5 ++ ];
R5 = [ FP ++ ];
CHECKREG r0, 0x37292618;
CHECKREG r1, 0x483A3729;
CHECKREG r3, 0x6A5C594B;
CHECKREG r4, 0x26181507;
CHECKREG r5, 0x7B6D6A5C;
CHECKREG r7, 0x719A8C7E;
R1 = [ P1 ++ ];
R2 = [ P2 ++ ];
R4 = [ P4 ++ ];
R5 = [ P5 ++ ];
R6 = [ FP ++ ];
CHECKREG r0, 0x37292618;
CHECKREG r1, 0x594B483A;
CHECKREG r2, 0x6A5C594B;
CHECKREG r4, 0x8C7E7B6D;
CHECKREG r5, 0x483A3729;
CHECKREG r6, 0x15078C7E;
R2 = [ P1 ++ ];
R3 = [ P2 ++ ];
R5 = [ P4 ++ ];
R6 = [ P5 ++ ];
R7 = [ FP ++ ];
CHECKREG r1, 0x594B483A;
CHECKREG r2, 0x7B6D6A5C;
CHECKREG r3, 0x8C7E7B6D;
CHECKREG r5, 0x26181507;
CHECKREG r6, 0x6A5C594B;
CHECKREG r7, 0x37292618;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
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