q115/random_k4/random_2.md

®
| MOTOROLA  |     |     | Me6S0gE  |     |
| --------- | --- | --- | -------- | --- |
8-BIT MICROPROCESSING UNIT
HMOS
The MC6809E is a revolutionary high performance 8-bit microprocessor
(HIGH-DENSITY N-CHANNEL, SILICON-GATE)
which supports modern programming techniques such as position independ
ence, reentrancy, and modular programming.
a-BIT
This third-generation addition to the M6800 Family has major architectural
improvements which include additional registers, instructions, and addressing  MICROPROCESSING
| modes.                                                       |     |         | UNIT  |     |
| ------------------------------------------------------------ | --- | ------- | ----- | --- |
| The basic instructions of any computer are greatly enhanced  |     | by the  |       |     |
presence of powerful addressing modes. The MC6809E has the most com
plete set of addressing modes available on any 8-bit microprocessor today.
The MC6809E has hardware and software features which make it an ideal
processor for higher level language execution or standard controller applica
| tions.  External clock  inputs are  | provided to allow synchronization with  |     |     |     |
| ----------------------------------- | --------------------------------------- | --- | --- | --- |
peripherals, systems, or other MPUs.
MC6800 COMPATIBLE
L SUFFIX
•  Hardware ~ Interfaces with All M6800 Peripherals
CERAMIC PACKAGE
•  Software  ~ Upward  Source Code  Compatible Instruction  Set  and  CASE 715
Addressing Modes
ARCHITECTURAL FEATURES
•  Two 16-Bit Index Registers
•  Two 16-Bit Indexable Stack Pointers
| •  Two 8-Bit Accumulators can  | be  Concatenated to Form One  | 16-Bit  |     |     |
| ------------------------------ | ----------------------------- | ------- | --- | --- |
Accumulator
•  Direct Page Register Allows Direct Addressing Throughout Memory
HARDWARE FEATURES
•  External Clock Inputs, E and Q, Allow Synchronization
•  TSC Input Controls Internal Bus Buffers
•  LlC Indicates Opcode Fetch
•  AVMA Allows Efficient Use of Common Resources in a Multiprocessor
System
PIN ASSIGNMENT
•  BUSY is a Status Line for Multiprocessing
•  Fast Interrupt Request Input Stacks Only Condition Code Register and  VSS  HACi
| Program Counter  |     |     | NMi  | TSe  |
| ---------------- | --- | --- | ---- | ---- |
•  Interrupt Acknowledge Output Allows Vectoring By Devices
|     |     |     | iAQ  | Lie  |
| --- | --- | --- | ---- | ---- |
•  Sync Acknowledge Output Allows for Synchronization to External Event
•  Single Bus-Cycle RESET
RESET
•  Single 5-Volt Supply Operation
•  NMI Inhibited After RESET Until After First Load of Stack Pointer  BS  AVMA
| •  Early Address Valid Allows Use With Slower Memories  |     |     |      | Q   |
| ------------------------------------------------------- | --- | --- | ---- | --- |
| •  Early Write Data for Dynamic Memories                |     |     | Vee  |     |
SOFlWARE FEATURES
|     |     |     | AO  | BUSY  |
| --- | --- | --- | --- | ----- |
•  10 Addressing Modes
| •  M6800 Upward Compatible Addressing Modes  |     |     | Al  | R/W  |
| -------------------------------------------- | --- | --- | --- | ---- |
| •  Direct Addressing Anywhere in Memory Map  |     |     | A2  | DO   |
•  Long Relative Branches
Dl
| •  Program Counter Relative  |     |     | A3  |     |
| ---------------------------- | --- | --- | --- | --- |
| • True Indirect Addressing   |     |     | A4  |     |
D2
•  Expanded Indexed Addressing
D3
0-, 5-, 8-, or 16-Bit Constant Offsets
| 8-or 16-Bit Accumulator Offsets      |     |     |     | D4  |
| ------------------------------------ | --- | --- | --- | --- |
| Auto-Increment/ Decrement by 1 or 2  |     |     | A7  | D5  |
•  Improved Stack Manipulation
|     |     |     | AS  | D6  |
| --- | --- | --- | --- | --- |
•  1464 Instruction with Unique Addressing Modes
| •  8 x 8 Unsigned Multiply  |     |     |     | D7   |
| --------------------------- | --- | --- | --- | ---- |
| •  16-Bit Arithmetic        |     |     |     | A15  |
•  Transfer/Exchange All Registers
|     |     |     | All  | A14  |
| --- | --- | --- | ---- | ---- |
•  Push/ Pull Any Registers or Any Set of Registers
| •  Load Effective Address  |     |     |     | A13  |
| -------------------------- | --- | --- | --- | ---- |

Me6S09E
MAXIMUM RATINGS  This device contains circuitry to protect the
Unit
Rating  Symbol  Value  inputs against damage due to high static
Supply Voltage  -0.3 to + 7.0  V  voltages or electric fields; however, it is ad
VCC
Input Voltage  Vin  0.3 to + 7.0  V  vi s e d   th a t   n o r m a l   p re c a u ti o n s   b e   t a k e n   to
|     |     |     |     |     |     |     | a v o i d  a p | p l ic a ti o n   | o f  a n y  v o l ta g | e   h i g h e r   th a n   |
| --- | --- | --- | --- | --- | --- | --- | -------------- | ----------------- | ---------------------- | -------------------------- |
Operating Temperature Range  TL to TH  maximum rated voltages to this high im
|                              |     |     |     |     | o to + 70  | 'c  |                   |     |     |     |
| ---------------------------- | --- | --- | --- | --- | ---------- | --- | ----------------- | --- | --- | --- |
| MC6809E, MC68A09E, MC68809E  |     |     | TA  |     |            |     | pedance circuit.  |     |     |     |
MC6809EC, MC68A09EC, MC68809EC  -40 to +85  Reliability of operation is enhanced if unus
Storage Temperature Range  Tstg  -55to+150  'c  ed inputs are tied to an appropriate logic
voltage levelle.g., either VSS or VCCI.
THERMAL CHARACTERISTICS
|     | Characteristic  |     | Symbol  |     | Value  | Unit  |     |     |     |     |
| --- | --------------- | --- | ------- | --- | ------ | ----- | --- | --- | --- | --- |
Thermal Resistance
| Ceramic  |     |     |     |     | 50  |       |     |     |     |     |
| -------- | --- | --- | --- | --- | --- | ----- | --- | --- | --- | --- |
| Cerdip   |     |     |     |     | 60  | 'C/W  |     |     |     |     |
8JA
| Plastic  |     |     |     |     | 100  |     |     |     |     |     |
| -------- | --- | --- | --- | --- | ---- | --- | --- | --- | --- | --- |
POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in 'c can be obtained from:
| T J = TA + IPDoOJA)  |     |     |     |     |     |     |     |     |     | (1)  |
| -------------------- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---- |
Where:
T A"" Ambient Temperature, 'c
OJAE Package Thermal Resistance, Junction-to-Ambient, °C/W
PD'" PINT+ PPORT
|     | PINTEICC x VCC, Watts -                 |     | Chip Internal Power  |     |                  |     |     |     |     |     |
| --- | --------------------------------------- | --- | -------------------- | --- | ---------------- | --- | --- | --- | --- | --- |
|     | PPORT'" Port Power Dissipation, Watts - |     |                      |     | User Determined  |     |     |     |     |     |
For most applications PPORT<C PINT and can be neglected. PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.
An approximate relationship between PD and T J lif PPORT is neglected) is:
| PD=K+ITJ+273'C)  |     |     |     |     |     |     |     |     |     | (2)  |
| ---------------- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---- |
Solving equations 1 and 2 for K gives:
| K = PDolT A + 273'C) + OJAoPD2  |     |     |     |     |     |     |     |     |     | (3)  |
| ------------------------------- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---- |
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known T A. Using this value of K the values of PD and T J can be obtained by solving equations (1) and (2) Iteratively for any
value of T A.
DC ELECTRICAL CHARACTERISTICS IVCC=5.0 V ±5%, Vss=O Vdc, TA=TL to TH unless otherwise notedl
|                     |     | Characteristic  |     |     |            | Symbol  | Min        | Typ  | Max      | Unit  |
| ------------------- | --- | --------------- | --- | --- | ---------- | ------- | ---------- | ---- | -------- | ----- |
| Input High Voltage  |     |                 |     |     | Logic, a,  | VIH     | VSS + 2.0  |      | VCC      |       |
|                     |     |                 |     |     | RESET      | VIHR    | VSS + 4.0  | -    | VCC      | V     |
|                     |     |                 |     |     |            | E       | VCC-0.75   | -    | VCC+0.3  |       |
VIHC
Input Low Voltage  Logic, RESET  VIL  VSS-0.3  - VSS + 0.8  V
|                                 |     |     |     |                  |     | E  VILC  | VSS-0.3  | -     | VSS+04     | V   |
| ------------------------------- | --- | --- | --- | ---------------- | --- | -------- | -------- | ----- | ---------- | --- |
|                                 |     |     |     |                  |     | a  VILa  | Vss -    | 03  - | Vss + 0.6  | V   |
| Input Leakage Current           |     |     |     | Logic, a, RESET  |     |          | -        | -     | 2.5        |     |
|                                 |     |     |     |                  |     | lin      | -        | -     | 100        | ~A  |
| IVin = 0 to 5.25 V, VCC = max)  |     |     |     |                  |     | E        |          |       |            |     |
de Output High Voltage
-
I I L o a d   =   - 2 0 5   ~ A ,   V C C   =   m i n i  0 0 - 0 7  V S S   +   2 4   - V
I I L o a d   =   - 1 4 5   ~ A ,   V e c   =  m i n i   AO-A15,   R / W   VOH  V S S   +   2 4  - -
| IILoad =  | -100 ~A, VCC = mini  |     |     |     |     |     | VSS + 24  | -   | -   |     |
| --------- | -------------------- | --- | --- | --- | --- | --- | --------- | --- | --- | --- |
8A, 8S, L1C, AVMA, 8USY
| de  O u tp u t  L | o w   V o lt a g e              |     |     |     |     |      |     |     |            |     |
| ----------------- | ------------------------------- | --- | --- | --- | --- | ---- | --- | --- | ---------- | --- |
|                   |                                 |     |     |     |     | VOL  | -   | -   | VSS + 0.5  | V   |
| (I Lo a d   =     |   2 .0   rn A ,   V C C = mini  |     |     |     |     |      |     |     |            |     |
Internal Power Dissipation (Measured at TA ~ GOC in Steady State Operation)  PINT  1.0  W
| Capacitance  |     |     |     |     |     | Cin  |     |     |     |     |
| ------------ | --- | --- | --- | --- | --- | ---- | --- | --- | --- | --- |
IVin = 0, TA = 25'C, f = 1.0 MHzl  00-07, Logic Inputs, a, RESET  - 10  15
pF
|     |     |     |     |     |     | E   | -   | 30  | 50  |     |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
AO-A15, R/W, SA, 85,
|                                 |     |     |     | Lie. AVMA, 8USY  |           | Cout  | -       | 10   | 15   | pF   |
| ------------------------------- | --- | --- | --- | ---------------- | --------- | ----- | ------- | ---- | ---- | ---- |
| Frequency of Operation          |     |     |     |                  | MC6809E   |       | 0.1     | -    | 1.0  |      |
|                                 |     |     |     |                  |           |       | f  0.1  | -    | 1.5  | MHz  |
| IE and a Inputsl                |     |     |     |                  | MC68A09E  |       |         |      |      |      |
|                                 |     |     |     |                  | MC68809E  |       | 0.1     | -    | 2.0  |      |
| Hi-Z 10ff Statel Input Current  |     |     |     |                  | 00-07     |       | -       | 2.0  | 10   |      |
IVin = 0.4 to 2.4 V, VCC = max)  AO-A15, R/W  ITS I  - - 100  ~A
• Capacitances are periodically tested rather than 100% tested.

MC6809E
BUS TIMING CHARACTERISTICS (See Notes 1 2 3 and 41
| Ident.  |     | MC6809E  | MC68A09E  | MC68B09E  |     |
| ------- | --- | -------- | --------- | --------- | --- |
Number  Characteristics  Symbol  Min  Max  Min  Max  Min  Max  Unit
| 1  Cycle Time  | tcyc  | 1.0  | 10  0.667  | 10  0.5  | 10  ~s  |
| -------------- | ----- | ---- | ---------- | -------- | ------- |
2  Pulse Width, E Low  PWEL  450  9500  295  9500  210  9500  ns
3  Pulse Width, E High  PWEH  450  9500  280  9500  220  9500  ns
| 4  Clock Rise and Fall Time  | tr, tf  | -   | 25  | 25  | 20  ns  |
| ---------------------------- | ------- | --- | --- | --- | ------- |
|                              |         |     | -   | -   |         |
5  Pulse Width, 0 High  PWOH  450  9500  280  9500  220  9500  ns
| 7  Delay Time, E to Q Rise        | tEOl  | 200  | - 130  | ~.  100  | - ns  |
| --------------------------------- | ----- | ---- | ------ | -------- | ----- |
|                                   |       |      | -      | -        | -     |
| 7A  Delay Time, Q High to E Rise  | tE02  | 200  | 130    | 100      | ns    |
|                                   |       | 200  | 130    | 100      | ns    |
| 7B  Delay Time, E High to 0 Fall  | tE03  |      |        |          |       |
7C  Delay Time, Q Hlg\1 to c Fall  tE04  200  130  - 100  ns
| 9  Address Hold Time  | tAH  | 20  | - 20  | - 20  | - ns  |
| --------------------- | ---- | --- | ----- | ----- | ----- |
11  Address Delay Time from E Low (BA, BS, R/WI  tAD  - 200  - 140  - 110  ns
|                           |       |     | -     | -     |       |
| ------------------------- | ----- | --- | ----- | ----- | ----- |
| 17  Read Data Setup Time  | tDSR  | 80  | 60    | 40    | ns    |
| 18  Read Data Hold Time   |       | 10  | - 10  | - 10  | - ns  |
tDHR
| 20  Data Delay Time from 0  | to DO  | -    | 200  - | 140  - | 110  ns  |
| --------------------------- | ------ | ---- | ------ | ------ | -------- |
| 21  Write Data Hold Time    | tDHW   | 30   | - 30   | - 30   | - ns     |
| 29  Usable Access Time      | tACC   | 695  | - 440  | - 330  | - ns     |
|                             |        | -    |        | -      | ns       |
| 30  Control Delay Time      | tCD    |      | 300  - | 250    | 200      |
Interrupts, HALT, RESET, and TSC Setup Time  tpcs  200  - 140  - 110  - ns
(Figures 6, 7, 8, 9, 12, and 131
|                                             |       |     | 210  | 150  | 120  ns  |
| ------------------------------------------- | ----- | --- | ---- | ---- | -------- |
| TSC Drive to Valid Logic Level (Figure 131  | tTSV  | -   |      |      |          |
TSC Release MaS Buffers to High Impedance {Figure 131  tTSR  - 200  - 140  - 110  ns
TSC Hi-Z Delay Time (Figure 131  lTSD  - 120  - 85  - 80  ns
|                                                  | tPCr'  |     | 100  - | 100  - | 100  ns  |
| ------------------------------------------------ | ------ | --- | ------ | ------ | -------- |
| Processor Control Rise and Fall Time (Figure 7)  | tPCf   | -   |        |        |          |
FIGURE 1 - READ/WRITE DATA TO MEMORY OR PERIPHERALS TIMING DIAGRAM
}-------------~,r-----------------------------~~IHC
VIH  VILC
0.
)~t";'\~1k----@
~--=--\V
o
R/W, Address,---ttlCJ-VO:7\x~r't--------------------=--------ttiv\~"
BA, BS
Non-Muxed ____~ ~---_Jj__t--------~~~----------~~-----~-~  Read Data
Write Data
BUSY, LlC,
AVMA
X>OOQ<)!
Not Valid
NOTES:
1. Voltage levels shown are VL:SO.4 V, VH~2.4 V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified.
®
3. Hold time.1  I for BA and BS is not specified.
4. Usable access time is computed-by: 1-4-11 max-17.

Me6S09E
FIGURE 2 - EXPANDED BLOCK DIAGRAM
-+--VCC
-+--VSS
Instruction
Register
FIRQ
IRQ
'--.:;==---l~ LlC
AVMA
R/W
TSC
HAri'
BA
BS
'-----:l~ BUS Y
* Internal Three-State Control
PROGRAMMING MODEL
As shown in Figure 4, the MC6809E adds three registers to
FIGURE 3 - BUS TIMING TEST LOAD the set available in the MC6800. The added registers include
a direct page register, the user stack pointer." and a second
5.0 V index register.
ACCUMULATORS lA, B, D)
MMD6150 The A and B registers are general purpose accumulators
or Equiv. which are used for arithmetic calculations and manipulation
Test Point O-' ....- e--+t--. of data.
Certain instructions concatenate the A and B registers to
C R MMD7000 form a single 16-bit accumulator. This is referred to as theD·
or Equiv. register, and is formed with the A register as the most signifi
cant byte.
DIRECT PAGE REGISTER lOP)
C=3O pF for BA, BS, LlC, AVMA, BUSY The direct page register of the MC6809E serves to enhance
130 pF for 00-07 the direct addressing mode. The content of this register
90 pF for AO-A15, Riw appears at the higher address outputs (A8-A15) during direct
R = 11.7 kO for 00-07 addressing instruction execution. This allows the direct
16.5 kO for AO-A 15, R/W mode to be used at any place in memory, under program
24 kO for BA, BS, LlC, AVMA, BUSY control. To ensure M6800 compatibility, all bits of this
register are cleared during processor reset.

Me6S09E
FIGURE 4 - PROGRAMMING MODEL OF THE MICROPROCESSING UNIT
15 o
x ~ Index Register }
Y - Index Register
""'"'" ",""'"'
U - User Stack Pointer
S - Hardware Stack Pointer
PC Program Counter
, A I B Accumulators
/
V
D
7 0
I I
DP Direct Page Register
~--------------~
7 0
I I I I I I I I
ElF H I N z V C cc - Condition Code Register
INDEX REGISTERS (X, VI FIGURE 5 - CONDITION CODE REGISTER FORMAT
The index registers are used in indexed mode of address
ing. The 16-bit address in this register takes part in the cal
culation of effective addresses. This address may be used to
point to data directly or may be modified by an optional con Carry
stant or register offset. During some indexed modes, the Overflow
contents of the index register are incremented and decre '-----Zero
mented to point to the next item of tabular type data. All four '-------Negative
pointer registers (X, V, U, SI may be used as index registers. '-----·---IRO Mask
'---------Half Carry
STACK POINTER (U, SI '-----------FIRO Mask
'------------Entire Flag
The hardware stack pointer (SI is used automatically by
the processor during subroutine calls and interrupts. The
user stack pointer (UI is controlled exclusively by the pro
grammer. This allows arguments to be passed to and from
subroutines with ease. The U register is frequently used as a
stack marker. Both stack pointers have the same indexed
mode addressing capabilities as the X and Y registers, but
also support Push and Pull instructions. This allows the CONDITION CODE REGISTER
MC6809E to be used efficiently as a stack processor, greatly DESCRIPTION
enhancing its ability to support higher level languages and
modular programming. BITO (CI
Bit 0 is the carry flag and is usually the carry from the
NOTE binary ALU. C is also used to represent a "borrow" from
The stack pointers of the MC6809E point to the top of subtract like instructions (CMP, NEG, SUB, SBCI and is the
the stack in contrast to the MC6800 stack pointer, complement of the carry from the binary ALU.
which pointed to the next free location on stack.
BIT 1 (VI
PROGRAM COUNTER Bit 1 is the overflow flag and is set to a one by an operation
The program counter is used by the processor to point to which causes a Signed twos complement arithmetic over
the address of the next instruction to be executed by the pro flow. This overflow is detected in an operation in which the
cessor. Relative addressing is provided allowing the program carry from the MSB in the ALU does not match the carry
counter to be used like an index register in some situations. from the MSB-l.
CONDITION CODE REGISTER BIT2(ZI
The condition code register defines the state of the pro Bit 2 is the zero flag and is set to a one if the result of the
cessor at any given time. See Figure 4. previous operation was identically zero.

Me6S09E
BIT3 (N)  reset vectors are fetched from locations FFFE16 and FFFF16
Bit 3 is the negative flag, which contains exactly the value  !Table 11 when interrupt acknowledge is true, IBAoBS= 11.
of the MSB of the result of the preceding operation. Thus, a  During initial power on, the reset line should be held low until
negative twos complement result will leave N set to a one.  the clock input Signals are fully operational.
Because the MC6809E RESET pin has a Schmitt-trigger in
BIT4 (I)  put with a threshold voltage higher than that of standard
Bit 4 is the TRCi mask bit. The processor will not recognize  peripherals, a simple R/e network may be used to reset the
interrupts from the TRCi line if this bit is set to a one. NliilT,  entire system. This higher threshold voltage ensures that all
FIRO, iRQ, RESET, and SWI all set I to a one. SWI2 and  peripherals are out of the reset state before the processor.
SWI3 do not affect I.
HALT
BIT 5 (H)  A low level on this input pin will cause the MPU to stop
Bit 5 is the half-carry bit. and is used to indicate a carry  running at the end of the present instruction and remain
from bit 3 in the ALU as a result of an 8-bit addition only  halted indefinitely without loss of data. When halted, the BA
IADC or ADDI. This bit is used by the DAA instruction to  output is driven high  indicating the buses are high im
pedance. BS is also high which indicates the processor is in
perform a BCD decimal add adjust operation. The state of
this flag is undefined in all subtract-like instructions.  the halt state. While halted, the M PU will not respond to ex
|     |     |     |     | ternal  real-time  | requests  IFIRO,  | IROI  although  | NMI  or  |
| --- | --- | --- | --- | ------------------ | ----------------- | --------------- | -------- |
BIT6 (F)  RESET will be latched for later response.  During the halt
state, 0 and E should continue to run normally. A halted
| Bit 6  is  | the  FIRO  mask  bit.  The  | processor will  | not  |                    |                                      |     |     |
| ---------- | --------------------------- | --------------- | ---- | ------------------ | ------------------------------------ | --- | --- |
|            |                             |                 |      | state IBAoBS = 11  | can be achieved by pulling HALT low  |     |     |
recognize interrupts from the FI RO line if this bit is a one.
NMI, FIRO, SWI, and RESET all set F to a one. TRQ, SWI2,  while RESET is still low. See Figure 7.
and SWI3 do not affect F.
BUS AVAILABLE, BUS STATUS (BA, BS)
BIT7 (E)  The bus available output is an indication of an internal
control signal which makes the MOS buses of the M PU high
Bit 7 is the entire flag, and when set to a one indicates that
the complete machine state fall the registersl was stacked,  impedance. When BA goes low, a dead cycle will elapse
before the MPU acquires the bus. BA will not be asserted
as opposed to the subset state I PC and CCI. The E bit of the
when TSC is active, thus allowing dead cycle consistency.
stacked CC is used on a return from interrupt I RTII to deter  The bus status output signal, when decoded with BA,
mine the extent of the unstacking. Therefore, the current E
represents the MPU state Ivalid with leading edge of 01.
left in the condition code register represents past action.
|     | PIN DESCRIPTIONS  |     |     | MPU State  |     |     |     |
| --- | ----------------- | --- | --- | ---------- | --- | --- | --- |
MPU State Definition
|     |     |     |     | BA  | BS  |     |     |
| --- | --- | --- | --- | --- | --- | --- | --- |
POWER IVSS, Vee)
Two pins are used to supply power to the part: VSS is  0  0  Normal (Running)
|     |     |     |     | 0   | 1  Interrupt or Reset Acknowledge  |     |     |
| --- | --- | --- | --- | --- | ---------------------------------- | --- | --- |
ground or 0 volts, while Vce is +5.0 V ±5%.
|                       |     |     |     | 1   | 0  Sync Acknowledge  |     |     |
| --------------------- | --- | --- | --- | --- | -------------------- | --- | --- |
| ADDRESS BUS (AO-A15)  |     |     |     | 1   | 1  Halt Acknowledge  |     |     |
Sixteen pins are used to output address information from
the M PU onto the address bus. When the processor does  Interrupt Acknowledge is indicated during both cycles of a
not require the bus for a data transfer, it will output address
|     |     |     |     | hardware vector fetch  | IRESET,  | NMI,  FIRQ,  | IRQ,  SWI,  |
| --- | --- | --- | --- | ---------------------- | -------- | ------------ | ----------- |
FFFF16, R/W= 1, and BS=O; this is a "dummy access" or  SWI2, SW131. This signal, plus decoding of the lower four
| VMA  cycle.  | All  address  bus  drivers  | are  made  | high  |     |     |     |     |
| ------------ | --------------------------- | ---------- | ----- | --- | --- | --- | --- |
address lines, can provide the user with an indication of
impedance when output bus available I BAI is high or when
TSe is asserted. Each pin will drive one Schottky TTL load or  which interrupt level is being serviced and allow vectoring by
device. See Table 1.
four LSTTL loads and 90 pF.
DATA BUS (00-07)
|                                                         |     |     |     | TABLE 1 -       | MEMORY MAP FOR INTERRUPT VECTORS  |     |     |
| ------------------------------------------------------- | --- | --- | --- | --------------- | --------------------------------- | --- | --- |
| These eight pins provide communication with the system  |     |     |     | Memory Map For  |                                   |     |     |
bidirectional data bus. Each pin will drive one Schottky TTL  Interrupt Vector
Vector Locations
| load or four LSTTL loads and 130 pF.  |     |     |     | MS    | LS    | Description  |          |
| ------------------------------------- | --- | --- | --- | ----- | ----- | ------------ | -------- |
|                                       |     |     |     | FFFE  | FFFF  |              | R ES ET  |
| READ/WRITE (R/W)                      |     |     |     |       |       |              | - -      |
|                                       |     |     |     | FFFC  | FFFD  |              | NMI      |
This signal indicates the direction of data transfer on the
|     |     |     |     | FFFA  | FFFB  |     | SWI  |
| --- | --- | --- | --- | ----- | ----- | --- | ---- |
data bus. A low indicates that the MPU is writing data onto  FFF8  FFF9  IRO
the data bus. R/W is made high impedance when BA is high
|     |     |     |     | FFF6  | FFF7  |     | Fi'R6  |
| --- | --- | --- | --- | ----- | ----- | --- | ------ |
or when TSe is asserted.
|     |     |     |     | FFF4  | FFF5  |     | SWI2  |
| --- | --- | --- | --- | ----- | ----- | --- | ----- |
RESET
|     |     |     |     | FFF2  | FFF3  |     | SWI3  |
| --- | --- | --- | --- | ----- | ----- | --- | ----- |
A low level on this Schmitt-trigger input for greater than
|     |     |     |     | FFFO  | FFFI  | Reserved  |     |
| --- | --- | --- | --- | ----- | ----- | --------- | --- |
one bus cycle will reset the MPU, as shown in Figure 6. The

s:
en  (")
co
<:)
CD  m
FIGURE 6 - RESET TIMING
I  I m+1  I m+2 I m+31 m+41 m+5 I m+6 I m+7 I  I  I n + 1 I n + 2 I n + 3 I n + 4 I n + 5  I n + 6 I n + 7 I n + 8 I n + 9 I n + 10 I
m  n
E
Q
RESET _____
| Address ==l.Y\._---"'---_..JL_~.L, _  | _"_ _  __"'____J'__   | __"'____J'__   _1.'__"_--"'--- |     |     |     |
| ------------------------------------- | --------------------- | ------------------------------ | --- | --- | --- |
Data .ll.I.ll.I=l.Y\._~''---_J'-_--'  =
R/W~
S\\ill\\\
BA
\~------------------~====~-----
ill\\\\\\\
| B S  |     | \~--------~r_--------------------------~  |     |     | \   |
| ---- | --- | ----------------------------------------- | --- | --- | --- |
AVMA
|                            |         | ________                     | ____________  |          | ______ ___  |
| -------------------------- | ------- | ---------------------------- | ------------- | -------- | ----------- |
| BUSY~~w-________________~  | r---\~  | ~                            | ~             | ~r---\~  |             |
| Lie                        |         | r--""",,~--v----'.~-,r----'  |               |          |             |
'---------------------~
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

3:
n
0»
CO
C)
FIGURE 7 - HALT AND SINGLE INSTRUCTION EXECUTION TIMING FOR SYSTEM DEBUG CD
m
2nd to Last Last Cycle
Cycle 9f of
Current Current Dead
Halted Halted
Q
I
~ __________ \~ _____.. ~ t~tJC_f ________________ __
~
----2t-ltpcs
Address ---,,--~v--
Bus
Fetch Execute
R/W
~!~----~\ \~ __________ ~/
BA ________________
BS ________________~ !~-----\~----------------~\ /~---------
Data -----,l,--__"r----.
Bus ___. .J\_
Instruction
Opcode
~ ~\,_--------------------~/ \'------
AVMA __________ ____
\--------------.~
------------'/
L1C
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

Me6S09E
Sync Acknowledge is indicated while the MPU is waiting defer the rearbitration of the next bus cycle to insure the in
for external synchronization on an interrupt line. tegrity of the above operations. This difference provides the
Halt Acknowledge is indicated when the MC6809E is in a indivisible memory access required for a "test-and-set"
halt condition. primitive, using anyone of several read-modify-write instruc
tions.
NON MASKABLE INTERRUPT (NMI)" BUSY does not become active during PSH or PUL opera
A negative transition on this input requests that a non tions. A typical read-modify-write instruction IASLl is shown
maskable interrupt sequence be generated. A non-maskable in Figure 11. Timing information is given in Figure 12. BUSY
interrupt cannot be inhibited by the program and also has a is valid tCD after the rising edge of Q.
higher priority than FIRQ, IRQ, or software interrupts. Dur
ing recognition of an NMI, the entire machine state is saved
AVMA
on the hardware stack. After reset, an NMI will not be recog'
nized until the first program load of the hardware stack AVMA is the advanced VMA signal and indicates that the
pointer IS), The pulse width of NMIIow must be at least one MPU will use the bus in the following bus cycle. The predic
E cycle. If the NMI input does not meet the minimum set up tive nature of the AVMA signal allows efficient shared-bus
with respect to Q, the interrupt will not be recognized until multiprocessor systems. AVMA is low when the MPU is in
the next cycle. See Figure 8. either a HALT or SYNC state. AVMA is valid tCD after the
rising edge of Q.
FAST-INTERRUPT REOUEST (FIRO)"
A low level on this input pin will initiate a fast interrupt se
quence, provided its mask bit IFI in the CC is clear. This se LlC
quence has priority over the standard interrupt request IIRQI LlC lIast instruction cycle) is high during the last cycle of
and ·is fast in the sense that it stacks only the contents of the every instruction, and its transition from high to low will indi
condition code register and the program counter. The inter cate that the first byte of an opcode will be latched at the end
rupt service routine should clear the source of the interrupt of the present bus cycle. LlC will be high when the MPU is
before doing an RTI. See Figure 9. halted at the end of an instruction (i.e., not in CWAI or
RESET), in sync state, or while stacking during interrupts.
INTERRUPT REOUEST (IRO)" LlC is valid tCD after the rising edge of Q.
A low level input on this pin will initiate an interrupt re
quest sequence provided the mask bit (I) in the CC is clear.
Since IRQ stacks the entire machine state, it provides a TSC
slower response to interrupts than FIRQ. IRQ also has a TSC (three-state control) will cause MOS address, data,
lower priority than FIRQ. Again, the interrupt service routine and R/IN buffers to assume a high-impedance state. The
should clear the source of the interrupt before doing an RTI. control signals IBA, BS, BUSY, AVMA, and LlC) will not go
See Figure 8. to the high-impedance state. TSC is intended to allow a
single bus to be shared with other bus masters (processors
CLOCK INPUTS E, 0 or DMA controllers).
E and Q are the clock signals required by the MC6809E. Q While E is low, TSC controls the address buffers and R/IN
must lead E; that is, a transition on Q must be followed by a directly. The data bus buffers during·a write operation are in
similar transition on E after a minimum delay. Addresses will a high-impedance state until Q rises at which time, if TSC is
be valid from the MPU, tAD after the falling edge of E, and true, they will remain in a high-impedance state. If TSC is
data will be latched from the bus by the falling edge of E. held beyond the rising edge of E, then it will be internally
While the Q input is fully TTL compatible, the E input directly latched, keeping the bus drivers in a high-impedance state
drives internal MOS circuitry and, thus, requires a high level for the remainder of the bus cycle. See Figure 13.
above normal TTL levels. This approach minimizes clock
skew inherent with an internal buffer. Refer to BUS TIMING
CHARACTERISTICS for E and Q and to Figure 10 which
shows a simple clock generator for the MC6809E. MPU OPERATION
BUSY During normal operation, the MPU fetches an instruction
BUSY will be high for the read and modify cycles of a from memory and then executes the requested function.
read-modify-write instruction and during the .access of the This sequence begins after RESET and is repeated indefinite
first byte of a dbuble-byte operation (e.g., LDX, STD, ly unless altered by a special instruction or hardware occur
ADDD)' BUSY is also high during the first byte of any in rence. Software instructions that alter normal MPU opera
direct or other vector fetch (e.g., jump extended, SWI in- tion are: SWI, SWI2, SWI3, CWAI, RTI, and SYNC. An
direct, etc.). . interrupt or HALT input can also alter the normal execution
In a multiprocessor system, BUSY indicates the need to of instructions. Figure 14 is the flowchart for the MC6809E.
rim
"NMI. RRQ, and requests are sampled on the fallin~ edge of Q. One cycle is required for synchronization before these interrupts are recog
nized. Th~ndlng Interru~t(sl Will not be serviced until completion of the current instruction unless a SYNC or CWAI condition is present. If
IRQ and FIRQ do not remain low until completion of the current Instrucnan, they may not be reco~nSed. However, f\/1iiii is latched and need
onlSEfmain low for one cycle. No interrupts are recognized or latched between the. falling edge of E ET and the rising edge of BS indicating
RE acknowledge. See I'fEID sequence in the MPU flowchart in Figure 14.

~
o
en
co
~
m
FIGUR~ 8 - IRO AND NMI INTERRUPT TIMING
Last Cycle
of Current Instruction
Instruction Interrupt Stacking and Vector Fetch Sequence Fetch
I ... )01 ... )01... .1
I m-2 I m-l I m I m+ 1 I m+21 m+31 m+41 m+5 I m+61 m+ 71 m+SI m+9Im+ 10 Im+ lllm+ 121m+ 131m+ 141m+ 151m+ 161m+ 171m+ lsi n n+ 1 I
o
Address I
Bus -P~~~J~---1~-p-c~L-p-c~L-__J L_ _~ L-__J L_ _- fi~ __J L_ _- A_ ___J L_ _~ ____A -__- A~~~~~~~~~~~~~~~~~~~~~~~
-...r
I
1RQ or PCS
~~-~--------------------------------------------------------------------------------~~~~~---------------
NMI
Data __~ ____J L_ _- 1\_ ___J L_ _- A~~/L __- -'\~~/L~--'\~~'~~~~ __~ L-__J L_ _~ ~ __J L_ _~ ____J L_ _~ ~==A-__- A_ ___J ~==~ ____l L_ _- A
R/W~ \ ______ ___
BA~~ ________________________________________________~ ====~
BS~~~~~================================~ ~~/
___ ___- , \
AVMA __- A_ ___~ __- 1
BUSY~~~==================================================~r--\~~====~---c===
LlC ______~
* E clock shown for reference only.
NOTE: Timing measurements are refererlced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

|     |     |     | FIGURE 9 - FIRQ INTERRUPT TIMING  |     |     |     |     |
| --- | --- | --- | --------------------------------- | --- | --- | --- | --- |
last Cycle
|     | of Current           |               |                                               |     |        | Instruction   |     |
| --- | -------------------- | ------------- | --------------------------------------------- | --- | ------ | ------------- | --- |
|     | I I   n structio n   |               | Interrupt Stacking and Vector Fetch Sequence  |     |        |               | .1  |
|     | 0 (  . ,  ...        |               |                                               |     |        | ., ... Fetch  |     |
| I   |                      | I m+l  1 m+2  |                                               | I   | I m+7  |               |     |
m-2  ,  m-l  m  ,  m+3  ,  m+4  m+5  ,  m+6  ,  m+8  m+9  n+1  n+
Q
Address
Bus
f_r_
~
t_pc_s_ ____________________________________________________________________________________ _
RRQ  __
Data
|     |     |     | PCl  | PCH  CCR  | VMA  New PCH  New PCl  | VMA  |     |
| --- | --- | --- | ---- | --------- | ---------------------- | ---- | --- |
\'-____- --'J
R/W~
BA~~ _____________________________________________________ _
..J/
BS~ _____________
\'-------
AVMA
r-----\,.---
| BUSY ~ ____________________________________________  |     |     |     |     | ____    |     |     |
| ---------------------------------------------------- | --- | --- | --- | --- | ------- | --- | --- |
| ~                                                    |     |     |     |     | ~f  \~  |     | ~~  |
LlC --'-__- --J
* E clock shown for reference only.
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

Me6S09E
FIGURE 10 - CLOCK GENERATOR
r  ------------------,
I  I
|     | +5V  | I   |
| --- | ---- | --- |
I
I  I
I  I
I
I
Optional
IMRDY  MRDY fireuit
I
I  I
I
I  L ____ _  I
_ __ ...1
~--I----------~~Q to System and Processor
I.!.!.+_------,--!:> E to System
+5V
4 MHz  NOTE: If optional circuit is not included the CLR and PRE
inputs of U2 and U3 must be tied high.
o
MRDY
Si'RE'i'CH ---------V/.
FIGURE 11 - READ-M-ODI-FY-WRITE INSTRUCTION EXAMPLE IASL EXTENDED INDIRECT)
| Memory    | Memory  |                       |
| --------- | ------- | --------------------- |
| Location  | ~       | Contents Description  |
PC-$0200
|        | $68  | ASL Indexed Opcode          |
| ------ | ---- | --------------------------- |
| $0201  | $9F  | Extended Indirect Postbyte  |
| $0202  | $63  | Indirect Address Hi-Byte    |
-
| $0203  | $00  | Indirect Address La-Byte  |
| ------ | ---- | ------------------------- |
| $0204  |      | Next Main Instruction     |
L--
$6300~
Effective Address Hi-Byte
$6301~ Effective Address La-Byte
Target Data

3:
|     | Last Cycle of   |     |     | FIGURE 12 - | BUSY TIMING  |     |     |     |     |     |     | (')  |
| --- | --------------- | --- | --- | ----------- | ------------ | --- | --- | --- | --- | --- | --- | ---- |
|     | Current Instr.  |     |     |             |              |     |     |     |     |     |     | en   |
m-l  m  I  m+l  m+2  I  m+3  I  m+4  I  m+5  I  m+6  m+7  m+S  1  m+9  I m+l0  I  C O
0
CD
m
Q
$0200  $0201  $0202  $0203  $FFFF  $6300  $6301  $FFFF  $E3D6  $FFFF  $E3D6  $0204
| Data  | X   | ~ X       | X    | X         | X   | X         | X      | X    | X      | X    | X   |     |
| ----- | --- | --------- | ---- | --------- | --- | --------- | ------ | ---- | ------ | ---- | --- | --- |
|       |     | $68  $9F  | $63  | $00  VMA  |     | $E3  $D6  | VlVIA  | $5C  | VI'AA  | $SS  |     |     |
r
| R/W~  |     |     |     |     |     |     |     |     |     | \   | /   |     |
| ----- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
|       | },  |     |     |     | /   | \   |     | /   |     | \   |     |     |
BUSY
|     | /   | \   |     |     |     |     |     |     |     | I   | \   |     |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
LlC
AVMA
|     |     |       |     | FIGURE 13 - | TSC TIMING  |     |     |                 |     |     |     |     |
| --- | --- | ----- | --- | ----------- | ----------- | --- | --- | --------------- | --- | --- | --- | --- |
|     |     | ~C-.  |     |             |             |     |     | 1~---...:ftPCS  |     |     |     |     |
======-=-:Jf...!.-! __
|     |     | Q  __''_'~ '_k        |     |     |       |         |     |     |     |     |     |     |
| --- | --- | --------------------- | --- | --- | ----- | ------- | --- | --- | --- | --- | --- | --- |
|     |     |                       |     |     |       | I       |     | I   |     |     |     |     |
|     |     | ==-~~_1-'--'-...J7_/  |     |     | .""~  | ~: ""~  |     |     |     |     |     |     |
-.:..,J :"'"
|     |               | TSC  |     |     |     | <     |          | <..... _ __ '---__  ;--!-lTSV_  |       |     |     |     |
| --- | ------------- | ---- | --- | --- | --- | ----- | -------- | ------------------------------- | ----- | --- | --- | --- |
|     |               |      |     |     |     | I     | }--      |                                 |       |     |     |     |
|     | R/w' Address  |      |     | }-  |     |       |          |                                 |       |     |     |     |
|     |               |      |     |     |     | ---1  |          | ~ ~;..-.tT.:...:Sc.:.V          |       |     |     |     |
|     |               |      |     |     |     |       | \.-tDDW  |                                 | ___   |     |     |     |
___
|     |     | MPUData ________  |     | ----')---------<~  |     |     |     | (~  |     |     |     |     |
| --- | --- | ----------------- | --- | ------------------ | --- | --- | --- | --- | --- | --- | --- | --- |
~seeNotelJ
NOTES:
1. Data will be asserted by the MPU only during the inte~val while R/W is low and (E or 0) is high. A composite bus cycle is shown to give most cases of
timing.
2. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

Me6S09E
ADDRESSING MODES
| The basic instructions of any computer are greatly en  |     |     | EXTENDED INDIRECT  |     |     |
| ------------------------------------------------------ | --- | --- | ------------------ | --- | --- |
hanced by the presence of powerful addressing modes. The
|     |     |     | As  a special  | case  of  indexed  | addressing  (discussed  |
| --- | --- | --- | -------------- | ------------------ | ----------------------- |
MC6809E has the most complete set of addressing modes  below), one level of indirection may be added to extended
available on any microcomputer today.  For example, the  addressing. In extended indirect, the two bytes following the
MC6809E has 59 basic instructions; however, it recognizes
postbyte of an indexed instruction contain the address of the
| 1464  different variations  | of instructions and  | addressing  | data.  |     |     |
| --------------------------- | -------------------- | ----------- | ------ | --- | --- |
modes. The addressing modes support modern program
LDA  [CAT]
ming techniques. The following addressing modes are avail
| able on the M C6809E:             |     |     | LDX  [$FFFE]  |     |     |
| --------------------------------- | --- | --- | ------------- | --- | --- |
| Inherent .!Includes Accumulator)  |     |     | STU  [DOG]    |     |     |
Immediate
| Extended  |     |     | DIRECT ADDRESSING  |     |     |
| --------- | --- | --- | ------------------ | --- | --- |
Extended Indirect  Direct addressing is similar to extended addressing except
Direct  that only one byte of address follows the opcode. This byte
Register  specifies the lower eight bits of the address to be used. The
upper eight bits of the address are supplied by the direct
Indexed
page register. Since only one byte of address is required in
Zero-Offset  direct addressing, this mode requires less memory and exe
Constant Offset
cutes faster than extended addressing. Of course, only 256
Accumulator Offset  locations (one page) can be accessed without redefining the
Auto In crement/ Decrement
contents of the DP register. Since the DP register is set to
Indexed Indirect
$00 on reset, direct addressing on the MC6809E is upward
Relative  compatible with direct addressing on the M6800. Indirection
Short/Long Relative Branching
is not allowed in direct addressing. Some examples of direct
| Program Counter Relative Addressing  |     |     | addressing are:  |     |     |
| ------------------------------------ | --- | --- | ---------------- | --- | --- |
LDA  where DP=$oo
INHERENT (INCLUDES ACCUMULATOR)
LDB  where DP= $10
In this addressing mode, the opcode of the instruction
| contains all the address information necessary. Examples of  |                             |     | LDD  <CAT  |     |     |
| ------------------------------------------------------------ | --------------------------- | --- | ---------- | --- | --- |
| inherent addressing are:                                     | ABX,  DAA,  SWI, ASRA, and  |     |            |     |     |
CLRB.
NOTE
|     |     |     | <  is  an  assembler  | directive  which  | forces  direct  |
| --- | --- | --- | --------------------- | ----------------- | --------------- |
IMMEDIATE ADDRESSING
| In immediate addressing, the effective address of the data  |     |     | addressing.  |     |     |
| ----------------------------------------------------------- | --- | --- | ------------ | --- | --- |
is the location immediately following the opcode ii.e., the
data to be used in the instruction immediately following the  REGISTER ADDRESSING
opcode of the instruction). The MC6809E uses both 8-and  Some opcodes are followed by a byte that defines a
16-bit immediate values depending on the size of argument  register or set of registers to be used by the instruction. This
specified by the opcode. Examples of instructions with im
is called a postbyte. Some examples of register addressing
| mediate addressing are:  |     |     | are:  |                           |     |
| ------------------------ | --- | --- | ----- | ------------------------- | --- |
|                          |     |     | TFR   | X, Y  Transfers X into Y  |     |
LDA  #$20
|     |     |     | EXG  | A, B  Exchanges A with B  |     |
| --- | --- | --- | ---- | ------------------------- | --- |
LDX  #$FOOO
|            |       |     | PSHS  | A, B,X, Y Push Y, X, B and A onto S  |     |
| ---------- | ----- | --- | ----- | ------------------------------------ | --- |
| LDY  #CAT  |       |     |       | stack                                |     |
|            | NOTE  |     | PULU  | X, Y, D  Pull D, X, and Y from U     |     |
# signifies immediate addressing; $ signifies hexadeci  stack
mal value to the MC6809 assembler.
| EXTENDED ADDRESSING  |     |     | INDEXED ADDRESSING  |     |     |
| -------------------- | --- | --- | ------------------- | --- | --- |
In all indexed addressing, one of the pointer registers (X,
In extended addressing, the contents of the two bytes
Y, U, S, and sometimes PC) is used in a calculation of the ef
immediately following the opcode fully specify the 16-bit
effective address used by the instruction.  Note that the  fective address of the operand to be used by the instruction.
Five basic types of indexing are available and are discussed
address generated by an extended instruction defines an
absolute address and is not position independent. Examples  below. The post byte of an indexed instruction specifies the
basic type and variation of the addressing mode, as well as
of extended addressing include:
the pointer register to be used. Figure 15 lists the legal for
LDA  CAT  mats for the postbyte. Table 2 gives the assembler form and
STX  MOUSE
the number of cycles and bytes added to the basic values for
| LOD  $2000  |     |     | indexed addressing for each variation.  |     |     |
| ----------- | --- | --- | --------------------------------------- | --- | --- |

s:
FIGURE 14 ~ FLOWCHART FOR MC6809E INSTRUCTIONS (')
~
o
CD
m
Bus State BA BS
Running o 0
Interrupt or Reset Acknowledge 0
NOTES: 1. Asserting RESET will result in entering the reset Sync Acknowledge o
sequence from any point in the flowchart. Halt Acknowledge
2. BUSY is high during first vector fetch cycle.

Me6809E
FIGURE 15 - INDEXED ADDRESSING POSTBYTE  ZERO-OFFSET INDEXED - In this mode, the selected
REGISTER BIT ASSIGNMENTS  pointer register contains the effective address of the data to
be used by the instruction. This is the fastest indexing mode.
| Poet-Byte Ragiatar Bit  |       |                                  | I nd e xe d   |     |                |      |     |     |     |
| ----------------------- | ----- | -------------------------------- | ------------- | --- | -------------- | ---- | --- | --- | --- |
|                         |       |                                  | A d d _ in g  |     | Examples are:  |      |     |     |     |
| 7  6  6                 | 4  3  | 2  1  0                          | Mode          |     | LOO            | O,X  |     |     |     |
| 0  R  R                 | d  d  | d  d  d  EA = ,R + 5 Bit Offset  |               |     | LDA            | ,5   |     |     |     |
| 1  R  R                 | 0  0  | 0  0  0                          | ,R+           |     |                |      |     |     |     |
1  R  R  i  0  0  0  1  ,R+ +  CONSTANT OFFSET INDEXED - In this mode, twos
1  R  R  0  0  0  1  0  ,-R  complement offset and the contents of one of the pointer
1  R  R  i  0  0  1  1  ,--R  registers are added to form the effective address of the
operand. The pointer register's initial content is unchanged
| 1  R  R  | i  0  | 1  0  0                        | EA = ,R +0 Offset  |     |                   |     |     |     |     |
| -------- | ----- | ------------------------------ | ------------------ | --- | ----------------- | --- | --- | --- | --- |
| 1  R  R  | 0     | 1  0  1  EA =,R + ACCB Offset  |                    |     | by the addition.  |     |     |     |     |
Three sizes of offset are available:
| 1  R  R  | 0   | 1  1  0  EA - | ,R + ACCA Offset  |     |     |     |     |     |     |
| -------- | --- | ------------- | ----------------- | --- | --- | --- | --- | --- | --- |
5-bit (-16 to + 15)
| 1  R  R  | 1   | 0  0  0  EA = ,R + B Bit Offset  |     |     |     |     |     |     |     |
| -------- | --- | -------------------------------- | --- | --- | --- | --- | --- | --- | --- |
8-bit (-128 to + 127)
| 1  R  R  | 1   | 0  0  1  EA = ,R + 16 Bit Offset  |     |     |     |     |     |     |     |
| -------- | --- | --------------------------------- | --- | --- | --- | --- | --- | --- | --- |
1  R  R  1  0  1  1  EA - ,R + 0 Offset  lS-bit (-32768 to + 32767)
1  x  x  1  1  0  0  EA - ,PC +8 Bit Offset  The twos complement 5-bit offset is included in the post
byte and, therefore, is most efficient in use of bytes and
| 1 -x  x  | 1   | 1  0  1  EA = ,PC + 16 Bit Offset  |     |     |     |     |     |     |     |
| -------- | --- | ---------------------------------- | --- | --- | --- | --- | --- | --- | --- |
1  R  R  1  1 .. 1  1  EA = (.Addressl  cycles. The twos complement 8-bit offset is contained in a
| -~  |     |     |     |     | single byte following the postbyte. The twos complement  |     |     |     |     |
| --- | --- | --- | --- | --- | -------------------------------------------------------- | --- | --- | --- | --- |
'----Addressing Mode Field  16-bit offset is in the two bytes following the postbyte. In
most cases the programmer need not be concerned with the
L.-------Indirect Field  size of this offset since the assembler will select the optimal
|     |     | (Sign Bit when b7 = 01  |     |     | size automatically.  |     |     |     |     |
| --- | --- | ----------------------- | --- | --- | -------------------- | --- | --- | --- | --- |
Examples of constant-offset indexing are:
|     |     |     |     |     | LOA  | 23,X  |     |     |     |
| --- | --- | --- | --- | --- | ---- | ----- | --- | --- | --- |
L.----------'--Register Field: RR
|     |     |     | 00 = X  |     | LOX  | -2,5  |     |     |     |
| --- | --- | --- | ------- | --- | ---- | ----- | --- | --- | --- |
x = Don't Care
|                     |     |     | 01 = Y  |     | LOY  | 3OO,X  |     |     |     |
| ------------------- | --- | --- | ------- | --- | ---- | ------ | --- | --- | --- |
| d = Offset Bit      |     |     | 10 = U  |     |      |        |     |     |     |
| .  0= Not Indirect  |     |     |         |     | LOU  | CAT,Y  |     |     |     |
11 = S
1= 1 = Indirect
|     |     |     | TABLE 2 - | INDEXED ADDRESSING MODE  |                   |     |     |              |     |
| --- | --- | --- | --------- | ------------------------ | ----------------- | --- | --- | ------------ | --- |
|     |     |     |           |                          | Non Ind i re c t  | ,   |     | Indire c t   | -   |
Type  Forma  Aaaembler  P o e tb yte  - Assembler  P o e tbyte  ,
|     |     |     |     |       |         | +  +   |       |         | +  +   |
| --- | --- | --- | --- | ----- | ------- | ------ | ----- | ------- | ------ |
|     |     |     |     | Form  | Opcode  |        | Form  | Opcode  |        |
Constant Offset From R  No Offset  R  lRROO100  0  0  [ RI  1B B.1.lllOO. i  3 lJl.
(2s Complement Offsets)  5-Bit Offset  n, R  ORRn"nnn  1  0  defaults to B-bit
|     |     | B-BitOffset  |     | n, R  | lRR01000  | 1  1  | (n, RI  | lRR11000  | 4  1  |
| --- | --- | ------------ | --- | ----- | --------- | ----- | ------- | --------- | ----- |
16-Bit Offset
|     |     |     |     | n, R  | lRR0100l  | 4  2  | (n, RI  | lRRll00l  | 7  2  |
| --- | --- | --- | --- | ----- | --------- | ----- | ------- | --------- | ----- |
Accumulator Offset From R  A Register Offset  A, R  lRROO110  1  0  (A, RI  lRR10110  4  0
(2s Complement Offsets)  B Register Offset  B, R  lRROO101  1  0  (B, RI  lRR10l0l  4  0
o Register Offset  0, R  lRR01011  4  0  (0, RI  lRRll011  7  0
Auto Increment/Decrement R  Increment By 1  ,R+  lRROOOOO  2  0  not allowed
Increment By 2  ,R+ +  lRROOOOl  3  0  (,R+ +1  lRR1000l  l 6  0
|     |     | Decrement By 1  |     | ,-R  | lRROOO10  | 2  0  | not allowed  |     |     |
| --- | --- | --------------- | --- | ---- | --------- | ----- | ------------ | --- | --- |
Decrement By 2  ,--R  lRROOO11  3  0  (.--RI  lRR10011  6  0
Constant Offset From PC  B-BitOffset  n, PCR  lxxOl100  1  1  [n, peRI  lxxl1100  4  1
(2s Complement Offsets)  lS-Bit Offset  n, PCR  lxxOl101  5  2  [n, PCRI  lxxl1101  8  2
|                    |     |                 |     | -   | -   | - - |      |           |       |
| ------------------ | --- | --------------- | --- | --- | --- | --- | ---- | --------- | ----- |
| Extended Indirect  |     | lS-Bit Address  |     |     |     |     | [nl  | 10011111  | 5  2  |
| R = X, Y, U or 5   |     | RR:             |     |     |     |     |      |           |       |
| x = Don't Care     |     | 00= X           |     |     |     |     |      |           |       |
01=Y
10=U
11=5
!..and ~ indicate the number of additional cycles and bytes respectively for the particular indexing variation.

Me6809E
ACCUMULATOR-OFFSET INDEXED  - This  mode is  $0100  LDA [$10,X]  EA is now $F010
similar to constant offset indexed except that the twos com
plement value.in one of the accumulators (A, B, or D) and  $F010  $Fl  $Fl50 is now the
the contents of one of the pOinter registers are added to form  $FOll  $50  new EA
the effective address of the operand. The contents of both
| the accumulator and the pointer register are unchanged by  |     | $Fl50  | $AA  |     |
| ---------------------------------------------------------- | --- | ------ | ---- | --- |
the addition. The post byte specifies which accumulator to
| use as an offset and no additional bytes are required. The ad  |     | After Execution  |     |     |
| -------------------------------------------------------------- | --- | ---------------- | --- | --- |
vantage of an accumulator offset is that the value of the off  A= $AA (actual data loaded)
set can be calculated by a program at run-time.
X= $Fooo
Some examples are:
LDA  B, Y  All modes of indexed indirect are included except those
which are meaningless (e.g., auto increment/decrement by
LDX  0, Y
1 indirect!. Some examples of indexed indirect are:
LEAX  B, X
LDA  [,X]
LDD  [10,5]
AUTO INCREMENT/DEC.REMENT INDEXED  - In the
| auto increment addressing mode, the pointer register con   |     | LDA  | [B,Y]   |     |
| ---------------------------------------------------------- | --- | ---- | ------- | --- |
| tains the address of the operand. Then, after the pointer  |     | LDD  | [,X++]  |     |
register is used, it is incremented by one or two. This ad
dressing mode is useful in stepping through tables, moving
RELATIVE ADDRESSING
data, or creating software stacks. In auto decrement, the
pointer register is decremented prior to use as the address of  The byte(s) following the branch opcode is (are) treated as
the data. The use of auto decrement is similar to that of auto  a signed offset which may be added to the program counter.
increment, but the tables, etc., are scanned from the high to  If the branch condition is true, then the calculated address
low addresses. The size of the increment/ decrement can be  (PC +  signed offset) is loaded into the program counter.
either one or two to allow for tables of either 8-or 16-bit data
Program execution continues at the new location as indi
to be accessed and is selectable by the programmer. The  cated by the PC; short (one byte offset) and long (two bytes
pre-decrement,  post-increment  nature  of  these  modes  offset)  relative  addressing  modes  are  available.  All  of
allows them to be used to create additional software stacks  memory can be reached in long relative addressing as an ef
that behave identically to the U and 5 stacks.  fective address interpreted modulo 216. Some examples of
| Some  examples  | of  the  auto  increment/ decrement  | relative addressing are:  |     |     |
| --------------- | ------------------------------------ | ------------------------- | --- | --- |
addressing modes are:
| LDA  ,X+  |     |     | BEQ  CAT  | (short)  |
| --------- | --- | --- | --------- | -------- |
|           |     |     | BGT  DOG  | (short)  |
STD  ,Y+ +
| LDB  ,-V  |     | CAT  | LBEQ  RAT     | Iiong)  |
| --------- | --- | ---- | ------------- | ------- |
|           |     | DOG  | LBGT  RABBIT  | lIong)  |
LDX  ,--5
Care should be taken in performing operations on 16-bit
pointer registers (X, Y, U, 5) where the same register is used
| to calculate the effective address.  |     | RAT  |     |     |
| ------------------------------------ | --- | ---- | --- | --- |
NOP
| Consider the following instruction:  |     | RABBIT  | NOP  |     |
| ------------------------------------ | --- | ------- | ---- | --- |
STX O,X+ + (X initialized to 0)
The desired result is to store a zero in locations $0000 and
$0001, then increment X to point to $0002. In reality, the fol
| lowing occurs:  |     | PROGRAM COUNTER RELATIVE  |     |     |
| --------------- | --- | ------------------------- | --- | --- |
O-temp
calculate theEA; temp is a holding register  The PC can be used as the pointer register with 8-or 16-bit
| X+2-X  | perform auto increment  |     |     |     |
| ------ | ----------------------- | --- | --- | --- |
signed offsets. As in relative addressing, the offset is added
X-(temp)  do store operation  to the current PC to create the effective address. The effec
tive address is then used as the address of the operand or
INDEXED INDIRECT  data. Program counter relative addressing is used for writing
All of the indexing modes, with the exception of auto in
position independent programs. Tables related to a particular
crement/ decrement by one or a ± 5-bit offset, may have an
routine will maintain the same relationship after the routine is
additional level of indirection specified: In indirect address  moved,  if  referenced  relative  to the  program  counter.
| ing,  the effective address  | is  contained at the location  |     |     |     |
| ---------------------------- | ------------------------------ | --- | --- | --- |
Examples are:
| specified by the contents of the index register plus any off  |     | LDA  | CAT, PCR  |     |
| ------------------------------------------------------------- | --- | ---- | --------- | --- |
set. In the example below, the A accumulator is loaded in
LEAX  TABLE, PCR
directly using an effective address calculated from the index
register and an offset.  Since program counter relative is a type of indexing, an
Before Execution  additional level of indirection is available.
| A= XX (don't care)  |     | LDA  | [CAT, PCR]  |     |
| ------------------- | --- | ---- | ----------- | --- |
| X= $Fooo            |     | LDU  | [DOG, PCR]  |     |

Me6S09E
INSTRUCTION SET
The instruction set of the MC6809E is similar to that of the  Transfer/Exchange Postbyte
I I
MC6800 and is upward compatible at the source code level.  ISou:rce  D~sti~ati~n
The number of opcodes has been reduced from 72 to 59, but
because of the expanded architecture and additional ad  Register Field
dressing modes, the number of available opcodes (with dif
|     |     |     |     | ()()()()=D IA:8)  | 1000= A  |     |
| --- | --- | --- | --- | ----------------- | -------- | --- |
ferent addressing modes) has risen from 197 to 1464.  000l=X  1001=8
Some of the new instructions are described in detail
|         |     |     |     | OO10=Y  | 1010= CCR   |     |
| ------- | --- | --- | --- | ------- | ----------- | --- |
| below.  |     |     |     | ooll=U  | 1011 = DPR  |     |
0100= S
0101 = PC
| PSHU/PSHS  |     |     |     | NOTE  |     |     |
| ---------- | --- | --- | --- | ----- | --- | --- |
The push instructions have the capability of pushing onto  All other combinations are undefined and INVALID.
either the hardware stack (S) or user stack (U) any single
register or set of registers with a single instruction.  LEAX/LEAY/LEAU/LEAS
The LEA (load effective address) works by calculating the
effective address used in an indexed instruction and stores
PULU/PULS  that address value, rather than the data at that address, in a
pointer register. This makes all the features of the internal
The pull instructions have the same capability of the push
instruction, in reverse order. The byte immediately following  addressing hardware available to the programmer. Some of
the implications of this instruction are illustrated in Table 3.
| the push  or pull  | opcode  determines which  | register or  |     |     |     |     |
| ------------------ | ------------------------- | ------------ | --- | --- | --- | --- |
registers are to be pushed or pulled. The actual pushl pull se  The LEA instruction also allows the user to access data
and tables in a position independent manner. For example:
quence is fixed; each bit defines a unique register to push or
LEAX  MSG1, PCR
pull, as shown below.
LBSR  PDATA (Print message routine)
| Push/Pull Postbyte  |     | Stacking Order  |       |                 |     |     |
| ------------------- | --- | --------------- | ----- | --------------- | --- | --- |
|                     |     |                 | MSG1  | FCC  'MESSAGE'  |     |     |
Pull Order
I  I  I  I  I  I  I  I  I  T hi s   sa m p le   p ro g ra m   p r in t s:   ' M E S S A G E '.   B y   w rit in g
|     | l   | +         |             |                               |                                    |                  |
| --- | --- | --------- | ----------- | ----------------------------- | ---------------------------------- | ---------------- |
|     |     | CCR  C C  | MS G 1 ,  P | C R ,  th e  a ss e m b le r  | c o m p u t es   th e  d is ta n c | e   be tw e e n  |
I  A  the present address and MSG1. This result is placed as a
A
|     |     | 8  8  | constant into the LEAX instruction which will be indexed  |     |     |     |
| --- | --- | ----- | --------------------------------------------------------- | --- | --- | --- |
DP
|     |     | DPR      | from the PC value at the time of execution. No matter where   |     |     |     |
| --- | --- | -------- | ------------------------------------------------------------- | --- | --- | --- |
|     |     | X  X Hi  | the code is located when it is executed, the computed offset  |     |     |     |
X Lo
|     |     | Y          | from the PC will put the absolute address of MSG1 into the X  |     |     |     |
| --- | --- | ---------- | ------------------------------------------------------------- | --- | --- | --- |
|     |     | Stu  Y Hi  | pointer register. This code is totally position independent.  |     |     |     |
Y Lo
|     |     | PC      | The LEA instructions are very powerful and use an internal  |     |     |     |
| --- | --- | ------- | ----------------------------------------------------------- | --- | --- | --- |
|     |     | U/S Hi  | holding register (tempI. Care must be exercised when using  |     |     |     |
U/S Lo
the LEA instructions with the auto increment and auto
PC Hi
|     |     | PC Lo  | decrement addressing modes due to the sequence of internal  |     |     |     |
| --- | --- | ------ | ----------------------------------------------------------- | --- | --- | --- |
t  operations. The LEA internal sequence is outlined as follows:
|     |     | Push Order  | LEAa ,b+  | (any of the 16-bit pointer registers X, Y,  |     |     |
| --- | --- | ----------- | --------- | ------------------------------------------- | --- | --- |
U, or S may be substituted for a and b.)
|     |     | Increasing  |            | (calculate the EA)         |     |     |
| --- | --- | ----------- | ---------- | -------------------------- | --- | --- |
|     |     | Memory      | 1. b-temp  |                            |     |     |
|     |     |             | 2.  b+1-b  | (modify b, postincrementl  |     |     |
+
|     |     |     | 3. temp-a  | (load a)  |     |     |
| --- | --- | --- | ---------- | --------- | --- | --- |
TFR/EXG
| Within the MC6809E, any register may be transferred to or  |     |     | LEAa ,-b  |     |     |     |
| ---------------------------------------------------------- | --- | --- | --------- | --- | --- | --- |
exchanged with another of like size; i. e., 8-bit to 8-bit or
16-bit to 16-bit.  Bits 4-7 of postbyte define the source  1. b-1-temp  (calculate EA with predecrement)
|     |     |     | 2: b-1-b  | (modify b, predecrement)  |     |     |
| --- | --- | --- | --------- | ------------------------- | --- | --- |
register, while bits 0-3 represent the destination register.
| These are denoted as follows:  |              |                    | 3. temp-a                        | (load a)  |     |     |
| ------------------------------ | ------------ | ------------------ | -------------------------------- | --------- | --- | --- |
|                                |              | TABLE 3 -          | LEA EXAMPLES                     |           |     |     |
|                                | Instruction  | Operation          |                                  | Comment   |     |     |
|                                | LEAX         | 10,X  X + 10  -X   | Adds 5'8it Constant 10 to X      |           |     |     |
|                                | LEAX         | 5OO,X  X+500-X     | Adds 16-8it Constant 500 to X    |           |     |     |
|                                | LEAY         | A,Y  Y+A  -Y       | Adds 8-Bit A Accumulator to Y    |           |     |     |
|                                | LEAY         | D,Y  Y+D  -Y       | Adds 16-08it D Accumulator to Y  |           |     |     |
|                                | LEAU -10, U  | U - 10  -U         | Substracts 10 from U             |           |     |     |
|                                | LEAS -10, S  | S - 10  -S         | Used to Reserve Area on Stack    |           |     |     |
|                                | LEAS         | 10, S  S + 10  -S  | Used to 'Clean Up' Stack         |           |     |     |
|                                | LEAX         | -X                 |                                  |           |     |     |
|                                |              | 5, S  S+5          | Transfers As Well As Adds        |           |     |     |

Me6S09E
Auto increment-by-two and auto decrement-by-two instruc  Example 1: LBSR IBranch Taken)
tions work similarly. Note that LEAX, ,X+ does not change  Before Execution S P = FOOO
|     | X does decrement X. LEAX 1X  |  should  |     |     |     |
| --- | ---------------------------- | -------- | --- | --- | --- |
X; however lEAX, -
be used to increrpent X by one.
MUL
Multiplies the unsigned binary numbers in the A and B ac  $8000  LBSR  CAT
cumulator and places the unsigned result into the 16-bit D
accumulator. This unsigned multiply also allows multiple
precision multiplications.
$AOOO  CAT
LONG AND SHORT RELATIVE BRANCHES
| The  MC6809E has  | the capability of program counter  |     |     |     |     |
| ----------------- | ---------------------------------- | --- | --- | --- | --- |
CYCLE-BY-CYCLE FLOW
relative branching throughout the entire memory map. In
this mode, if the branch is to be taken, the 6-or 16-bit signed
|     |     |     | Cycle #  Address  | Data  RfW Description  |     |
| --- | --- | --- | ----------------- | ---------------------- | --- |
offset is added to the value of the program counter to be
used as 'the effective address. This allows the program to  1  8000  17  1  Opcode Fetch
|     |     |     | 2  8001  | 20  1  | Offset High Byte  |
| --- | --- | --- | -------- | ------ | ----------------- |
branch anywhere in the 64K memory map. Position indepen
dent code can be easily generated through the use of .relative  3   80 0 2   0 0   1   O ffs e t  L o w   Byte
|     |     |     | 4   F F F | F   *   1  V | M A   C y c le   |
| --- | --- | --- | --------- | ------------ | ---------------- |
branching. Both short (B bit) and long (16 bit) branches are
|             |     |     | 5  FFFF  | *  1   | VMA Cycle                 |
| ----------- | --- | --- | -------- | ------ | ------------------------- |
| available.  |     |     | 6  AOOO  | *  1   | Computed Branch Address   |
|             |     |     | 7  FFFF  | *  1   | VM,A Cycle                |
| <SYNC       |     |     | 8  EFFF  | 80  0  | Stack High Order Byte of  |
Aftar encountering a sync instruction, the MPUenters a  Return Address
sync state, stops processing instructions, and waits for an  9  EFFE  03  0  Stack Low Order Byte of
interrupt. If the pending interrupt is non-maskable (NMII or  Return Address
maskable (FIRO, IRO) with its mask bit (F 0,11 clear, the pro
cessor will clear the sync state and perform the normal inter
rupt stacking and serVice routine. Since FIROand IRO are  Example 2: DEC (Extended)
not edge-triggered, a low level·with a minimum duration of
three bus cycles is required to assure that the interrupt will  $8000  DEC  $AOOO
be taken. If the pending interrupt is maskable (FIRO, IRO)  $AOOO  FCB  $80
with its mask bit (F or I) set, the processor will clear the sync
state and continue processing by executing the next in-line
instruction. Figure 1,6 depicts sync timing.  CYCLE-BY-CYCLE FLOW
| SOFnNAREINTERRUPTS  |     |     | Cycle #  Address  | Data  RfW Description  |               |
| ------------------- | --- | --- | ----------------- | ---------------------- | ------------- |
|                     |     |     | 1  8000           | 7A  1                  | Opcode Fetch  |
A software interrupt is an instruction which will cause an
|     |     |     | 2  8001  | AO  1  | Operand Address, High Byte  |
| --- | --- | --- | -------- | ------ | --------------------------- |
'interrupt and its associated vector fetch. These software in  3  8002  00  1  Operand Address, Low Byte
| terrupts  are useful  | in  operating  system  | calls,  software  |          |                    |     |
| --------------------- | ---------------------- | ----------------- | -------- | ------------------ | --- |
|                       |                        |                   | 4  FFFF  | *  1  Vf:lA Cycle  |     |
debugging, trace operations, memory mapping, and soft  5  AOOO  80  1  Read the Data
ware development systems. Three levels of SWI are available  6  FFFF  *  1  Vf:lA Cycle
on this MC6809E and are prioritized in the following order:  7  FFFF  7F  0  S tore the Decremented Data
SWI, SWI2, SWI3.
* The data bus has the data at that particular address.
16-BIT OPERATION
The MC6809E has the capability of processing 16-bit data.
These instructions include loads, stores, compares, adds,  INSTRUCTION SET TABLES
subtracts, transfers, exchanges, pushes, and p·ulls.
The inStructions of the M C68Ci9E have been broken down
into five different categories. They are ,as follows:
| CYCLE-BY-CYCLE OPERATION  |     |     | B-bit operation (Table 4)  |     |     |
| ------------------------- | --- | --- | -------------------------- | --- | --- |
16-bit operation (Table 5)
Index register/stack pointer instructions (Table 6)
The address bus cycle-by-cycle performance chart (Figure
16) illustrates the memory-access sequence corresponding  Relative branches (long or short) (Table 7)
Miscellaneous instructions (Table B)
to each possible instruction and addressing mode in the
MC6809E. Each instruction begins with an opcode fetch.  Hexadecimal  values  for the instructions are given in
| While that opcode is being internally decoded, the next pro  |     |     | Table 9.  |     |     |
| ------------------------------------------------------------ | --- | --- | --------- | --- | --- |
gram byte is always fetched. (Most instru,ctions will use the
next byte, so this technique con.siderably speed~ th~.()ugh­
put.) Next, the operation of each opcode 'will follow the  PROGRAMMING AID
flowchart. VMA is an indication of FFFF16 on the address
bus, R/W=1 and BS=O .. The following examples illustrate  Figure 18 contains a co~pilation of data that will assist
| the use of the chart.  |     |     | you in programming·theMC6809E.  |     |     |
| ---------------------- | --- | --- | ------------------------------- | --- | --- |

|              |         | FIGURE 16 -       | SYNC TIMING  |             |
| ------------ | ------- | ----------------- | ------------ | ----------- |
| Last Cycle   | Sync    |                   |              | Last Cycle  |
| of Previous  | Opcode  | Sync Acknowledge  |              | of Sync     |
__________________
| 1~10~( ns_t_ru_•c_.ti•~o ~nr~F_e.t._0c_(h~ I~Ex_e_.c_u_te~I~---.- | .   | ;~yr-- ------------------------~_+I~ns-t--rIu.-c -ti~o.n1~   |     |     |
| ----------------------------------------------------------------- | --- | ------------------------------------------------------------ | --- | --- |
G
Address======X=======X=~~:J~~~~~----------------------~-----------l------------------------~~~~~c=====~~====)(====~
Data=>c======x=======x======J(======)---------------------~----------_1---------------------------1c======X======~C=====:J
R/W~
~--------------------~~~,-----------7-----------------------J
SA ==:)_  ____- ----11  \.-------~----------~\~-------------------------
__________________________, ,-____  _______________________________ __
| SS~~  |     |     | ~   |     |
| ----- | --- | --- | --- | --- |
AVMA~_ ___________~ \ __________~ l~, _ _____~
----------~/
_______
|           |          | .'  | I         |                                  |
| --------- | -------- | --- | --------- | -------------------------------- |
| LlC  ~ ,  |          |     |           | x~  S_e_e_N_o_t_e_1_ _______ __  |
| _---'I    | '-----1  |     | ~tiltPcf  |                                  |
NIRMOI,,  -----------------------------------------------------J.~,----------V-IL
See Note 2
~
FIRG
~tPcs
NOTES: 1. If the associated mask bit is set when the interrupt is requested, Lie will go low and this cycle will be an instruction fetch from address
location PC + 1. However, if the interrupt is accepted (N M loran unmasked Fl RQ or fRO) LIe will remain high and interrupt processing
will start with this cycle as m on Figures 8 and 9 (Interrupt TimingJ.
2. If mask bits are clear, IRQ andFiRO must be held low for three cycles 10 guarantee that interrupt will be taken, although only one cycle
is necessary to bring the processor out of SYNC.
3. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

MC6809E
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE ISheet 1 of 5)
NOTES
Data Bus
Address Bus L-........' -'--=~
2 Address NNNN is location of opcode
3 If opcode is a two byte opcode sUbSequent
addresses are in parenthesis (-).
4. Two-byte opcodes are highlighted No

Me6S0gE
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 2 of 5)
~  Inherer\tAddressmgModf'
| ABxt  | RTSI     |                                   |     | RTll  |         |        |     |
| ----- | -------- | --------------------------------- | --- | ----- | ------- | ------ | --- |
|       | :;~:;~   | ........,M,...U..JLL,! --,S~~"f4  |     |       | SYNC ~  | CWAlt  |     |
|       | ~?~~,B,  |                                   |     |       |         | l      | J   |
Don'teare  DOr1'tCare  Don't Care  Don't Care  Don'teare  Don I Cilr~  CCMask  co~~n~~~~;'er
| NNN•N+  1  | •         |     |     | NNN N + 1  | NNN N+ 1  |     |        |
| ---------- | --------- | --- | --- | ---------- | --------- | --- | ------ |
|            | DEC;A'_'  | +   | +   | t          |           | +   | Stack  |
~
Don'teare  PC High  LSLA',~  0011 1 Care  Don't Care  CCA  Don tCare  Don'teare
|     | St ack     | FF FF  |     |     |     | NNN N +2  |     |
| --- | ---------- | ------ | --- | --- | --- | --------- | --- |
|     | +   0~~AB  | +      | +   |     |     | i         |     |
~ ? , ~ i '
|     | PC Low   : ~ : M B   | Don 'lea re  | P C   L o w   |     |     | DOr1'tCare  |     |
| --- | -------------------- | ------------ | ------------- | --- | --- | ----------- | --- |
|     | •                    |              | S t •a c k    |     |     | ~C""C"NO    |     |
|     |                      | •            |               |     |     | +           |     |
Presentl
|     | Don't Care  | Don'teare  | PCH,gh  |     |     | PC Low  |     |
| --- | ----------- | ---------- | ------- | --- | --- | ------- | --- |
|     |             | FFFF       | Stack   |     |     | Stack   | y"  |
|     |             | +          | +       |     |     | +       |     |
3 State
|     |     | Don'leare  | Us€,StackLow  |     |     | PC High  |     |
| --- | --- | ---------- | ------------- | --- | --- | -------- | --- |
|     |     | FFFF       | Stack         |     |     | Stack    |     |
+  BReglster
|     |     | ~           |                 | Stack           |     | i  l                        | J         |
| --- | --- | ----------- | --------------- | --------------- | --- | --------------------------- | --------- |
|     |     | Don't Care  | UserStackH,gh   |                 |     | User Stack Low  v:~7~;~~    |           |
|     |     | FF FF       | •               |                 |     | Sta ck                      | FFF X +l  |
|     |     | +           |                 |                 |     | t                           | t         |
|     |     | Don'teare   | YReglsterLow    |                 |     | User Stack High  Don tCare  |           |
|     |     | FF•FF       | St•ack          |                 |     | S t ack                     |           |
|     |     |             |                 | £AeglsterHogh   |     | i                           |           |
|     |     | Don'teare   | Y ReglsterH'gh  |                 |     | y Register Low              |           |
|     |     | FFFF        | Stack           |                 |     | Stack                       |           |
|     |     | +           | +               | X Register Low  |     | J                           |           |
Stack
|     |     | Don'leare  | X Aeg,ster Low   | t               |     | y Register High  |     |
| --- | --- | ---------- | ---------------- | --------------- | --- | ---------------- | --- |
|     |     |            | Stack            |                 |     | Stack            |     |
|     |     |            | i                | Y AeglsterH'gh  |     | i                |     |
|     |     | ~          |                  | Stack           |     |                  |     |
|     |     |            | X Aeglster High  |                 |     | X Register Low   |     |
|     |     |            | Sl ack           |                 |     | Sta ck           |     |
|     |     |            | +                | Y Register low  |     | +                |     |
Stack
|     |     |     |     | +   |     | X Register HLgh  |     |
| --- | --- | --- | --- | --- | --- | ---------------- | --- |
Stack
|     |     |     | •   | User Stack High  |     | i   |     |
| --- | --- | --- | --- | ---------------- | --- | --- | --- |
|     |     |     |     | St a ck          |     | J   |     |
L D'~~~t,~:;e
|     |     |     | BReglster  | i -             |     |        |     |
| --- | --- | --- | ---------- | --------------- | --- | ------ | --- |
|     |     |     | Stack      | User Stack Low  |     | Stack  |     |
+
Stack
|     |     |     | A Register  |        |     | BReglster   |     |
| --- | --- | --- | ----------- | ------ | --- | ----------- | --- |
|     |     |     | St•ack      |        |     | Stack       |     |
|     |     |     |             | Stack  |     | t           |     |
|     |     |     |             | +      |     | A Register  |     |
Stack  L-
+-
Stack
|     |     |     | Don't Care  | ~   |     |     |     |
| --- | --- | --- | ----------- | --- | --- | --- | --- |
FFFF
t
|     |     |     | I v~n~t~;~~h  | I   |     |     |     |
| --- | --- | --- | ------------- | --- | --- | --- | --- |
FF•FX
I
I v:~:;U~~
FFF•X+ l
t

MC6809E
FIGURE 17 -CYCLE-BY-CYLE PERFORMANCE (Sheet 3 of 5)
.-____ Direct
~~~----~~-------------L------~~~--~--------------~~~,A'?~:~:~;"~g~_,
Except
PSHU NNNN -!; 112)
PSHS,
PULS,
HR, Don'fCare Address Low
"'"G' NNNN+2131

Me6S09E
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE iSheet4of51
xxxx
Constant Olfsetfrom A
No Offset IndexA&glster
8·BilOffSP.t Index RegISter + Offset Byte
16-BIIOffset Index Register + Offset High Byte" Offset Low Bvte
AccurnulalorOffsel from R
A Regis\erOflset Index Register + A Register
B Register Offset Index RegIster + B Register
o RegisterOlfsel Index Register + 0 Register
Auto Increme/II/Dec/ernen! R
InCfementby2 InOeJ(Reglsler
Decrement by2 Index Register -2
Constant Offsetlrom PC
8-8110115el Program Counter + Offset Byte
16-bltDllsel Program Counter + Offset High Byte Offset Low Byte
Extendedlndirecl
~ Address High Bvte Addles Low Byte
The ,ndel( register IS Incremented folloWII'lg the In(!exed access

Me6S09E
FIGURE 17 - CYCL.E-BY-CYClE PERFORMANCE (Sheet 5 of 5)
ANDCC,
DRce IAII Except ~STX. CLR, COM. (All Except (All Except
(Immediate Immediatel _(All DEC,INC, Immediate) Immediate~
Only), Except LSL.LSR.
• Immediate) NEG, ROL,
RDA (All
Except
Immediatel
Effective Address lEAl
Conslartt Offset from A
No 0ffset Index Aegls,ler
5-Bll0ffset Index Register
8-81t Ollset. Index Register + Post Byte
1&-811 Offset Index Register + Post Byte High: Post Byle Low
Accumulator Offset from R
A Register Oilse! Index Reglster'+ A Register
S"Reglster Offset Index Register + B Reg~lster
o Register Offset Index Register + 0 Register
A-uto Increment/Decrement R
Increment by 1 Index Register.
Incrementby2 Index Register
Decrement by 1 Index Reglster-1
Oecremer'ltby2 Index Reglster'-2
ConstantO/lsB! from PC
8-BltOffset Program Counter + Ollset Byte
16·BI\ Offset Program Counter + Ollset High Byte. Ollset Low Byte
Direct Page Register: Address Low
Address .Hlgh. Address Low
Immediate NNNN+l
*.:rhemdex register is Incremented followmg thelndElxedaccess

Me6S09E
| TABLE 4 -        | B-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS           |            |
| ---------------- | --------------------------------------------------- | ---------- |
| Mnemonic(s)      |                                                     | Operation  |
| ADCA,ADCB        | Add memory to accumulator with carry                |            |
| ADDA,ADDB        | Add memory to accumulator                           |            |
| ANDA,ANDB        | And memory with accumulator                         |            |
| ASL, ASLA, ASLB  | Arithmetic shift of accumulator or memory left      |            |
| ASR,ASRA,ASRB    | Arithmetic shift of accumulator or memory right     |            |
| BITA, BITB       | Bit test memory with accumulator                    |            |
| CLR, CLRA, CLRB  | Clear accumulator or memory location                |            |
| CMPA, CMPB       | Compare memory from accumulator                     |            |
| COM, COMA, COMB  | Complement accumulator or memory location           |            |
| DAA              | Decimal adjust A accumulator                        |            |
| DEC,DECA,DECB    | Decrement accumulator or memory location            |            |
| EORA, EORB       | Exclusive or memory with accumulator                |            |
| EXG Rl, R2       | Exchange Rl with R2 (Rl, R2 = A, B, CC, DP)         |            |
| INC, INCA, INCB  | Increment accumulator or memory location            |            |
| LOA, LOB         | Load accumulator from memory                        |            |
| LSL, LSLA, LSLB  | Logical shift left accumulator or memory location   |            |
| LSR, LSRA, LSRB  | Logical shift right accumulator or memory location  |            |
| MUL              | Unsigned multiply (A x B -                          | D)         |
| NEG, NEGA, NEGB  | Negate accumulator or memory                        |            |
| ORA,ORB          | Or memory with accumulator                          |            |
| ROL, ROLA, ROLB  | Rotate accumulator or memory left                   |            |
| ROR, RORA, RORB  | Rotate accumulator or memory right                  |            |
| SBCA, SBCB       | Subtract memory from accumulator with borrow        |            |
| STA,STB          | Store accumulator. to memory                        |            |
| SUBA,SUBB        | Subtract memory from accumulator                    |            |
| TST,TSTA, TSTB   | Test accumulator or memory location                 |            |
| TFR Rl, R2       | Transfer Rl to R2 (Rl, R2 = A, B, CC, DP)           |            |
NOTE: A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU (PULS,
. PULU) instructions.
| TABLE 5 -    | l6-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS  |     |
| ------------ | ------------------------------------------- | --- |
| Mnemonic(s)  | Operation                                   |     |
| ADDD         | Add memory to 0 accumulator                 |     |
| CMPD         | Compare memory from 0 accumulator           |     |
| EXG 0, R     | Exchange 0 with X, Y, S, U or PC            |     |
| LDD          | Load 0 accumulator from memory              |     |
SEX
Sign Extend B accumulator into A accumulator
| STD       | Store 0 accumulator to memory       |     |
| --------- | ----------------------------------- | --- |
| SUBD      | Subtract memory from 0 accumulator  |     |
| TFR 0, R  | Transfer 0 to X, Y, S, U or PC      |     |
| TFR R, 0  | Transfer X, Y, S, U or PC to 0      |     |
NOTE: 0 may be pushed (pulled) to either stack with PSH5., PSHU (PULS,
PULU) instructions.
| TABLE 6 -    | INDEX REG)STERISTACKPOINTER INSTRUCTIONS                  |     |
| ------------ | --------------------------------------------------------- | --- |
| Instruction  | Description                                               |     |
| CMPS, CMPU   | Compare memory from stac~.· pointer                       |     |
| CMPX, CMPY   | Compare memory from index register                        |     |
| EXG Rl, R2   | Exchange 0, X, Y, S, U or PC with D, X, Y, S, U or PC     |     |
| LEAS, LEAU   | Load effective ~ddress into stack pointer                 |     |
| LEAX, LEAY   | Load effective address into index regtster                |     |
| LOS, LOU     | Load stack pointer from memOfY                            |     |
| LDX, LDY     | Load index register from memory                           |     |
| PSHS         | Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack  |     |
| PSHU         | Push A, B, CC, DP, 0, X, Y, S, or PC onto user stack      |     |
| PULS         | Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack   |     |
| PULU         | Pull A, B, CC, DP, 0, X, Y, S or PC from hardware stack   |     |
| STS, STU     | Store stack pointer to memory                             |     |
| STX, STY     | Store index register to memory                            |     |
| TFR Rl, R2   | Transfer 0, X, Y, S, U or PC to D, X, y, S, U or PC       |     |
| ABX          | Add B accumulator to ?< (unsigned)                        |     |

Me6S09E
TABLE 7 - BRANCH INSTRUCTIONS
Instruction Description
SIMPLE BRANCHES
BEQ, LBEQ Branch if equal
BNE, LBNE Branch if not equal
BMI, LBMI Branch if minus
BPL, LBPL Branch if plus
BCS, LBCS Branch if carry set.
BCC, LBCC Branch if carry clear
BVS, LBVS Branch if overflow set
BVC, LBVC Branch if overflow clear
SIGNED BRANCHES
BGT, LBGT Branch if greater (signed)
BVS, LBVS Branch if invalid 2'5 complement result
BGE~ LBGE Branch if greater tha'n or equal (signed)
BEQ, LBEQ Branch if equal
BNE, LBNE Branch if not equal
BLE, LBLE Branch if less than or equal (signed)
BVC, LBVC Branch if valid 2's complement result
BLT, LBLT Branch If less than (signed)
UNSIGNED BRANCHES
BHI, LBHI Branch if higher (unsigned)
BCC, LBCC Branch if higher or same (unsigned)
BHS, LBHS Branch if higher or same (unsigned)
BEQ, LBEQ Branch if equal
BNE, LBNE Branch if not equal
BLS, LBLS Branch if lower or same' (:unsignedl
BCS, LBCS Branch if lower (unsigned)
BLO, LBLO Branch if lower (unsigned)
OTHER BRANCHES
BSR, LBSR Branch to subroutine
BRA, LBRA Branch always
BRN, LBRN Branch never
TABLE 8 - MISCELLANEOUS INSTRUCTIONS
Instruction Description
ANDCC AND condition code regi,ster
CWAI AND condition code register, then wait for interrupt
NOP No operation
ORCC OR condition code register
JMP Jump
JSR Jump to subroutine
RTI Return from interrupt
RTS Return from subroutine
SWI, SWI2, SWI3 Software interrupt (absolute indirect)
SYNC Synchronize with interrupt line

Me6S0gE
|               |         |       | TABLE 9 - HEXADECIMAL VALUES OF MACHINE CODES  |           |       |               |          |         |
| ------------- | ------- | ----- | ---------------------------------------------- | --------- | ----- | ------------- | -------- | ------- |
|               |         | -     |                                                |           | -     |               |          | -       |
| OP  Mnem      | Mode    | #     | OP  Mnem                                       | Mode      | #     | OP  Mnem      | Mode     | #       |
| ·NE G         |         |       |                                                |           |       | ·NE G         |          |         |
| ()()          | Direct  | 6  2  | 30  LEAX                                       |           | 4+    | 2+  60        | Indexed  | 6+  2+  |
| 01  ·         |         |       | 31  LEAY                                       | :~:[: 4+  |       | 2+  61  ·     |          |         |
| 02            |         |       | 32  LEAS                                       |           | 4+    | 2+  62        |          |         |
| 03  COM       |         | 6  2  | 33  LEAU                                       |           | 4+    | 2+  63  COM   |          | 6+  2+  |
| ·LS R         |         |       |                                                | Immed     |       | ·LS R         |          |         |
| 04            |         | 6  2  | 34  PSHS                                       |           | 5+    | 2  64         |          | 6+  2+  |
| 05            |         |       | 35  PULS                                       | Immed     | 5+    | 2  65         |          |         |
|               |         |       |                                                | Immed     |       | 2  ROR        |          |         |
| 06  ROR       |         | 6  2  | 36  PSHU                                       |           | 5+    | 66            |          | 6+  2+  |
| 07  ASR       |         | 6  2  | 37  ·PU LU                                     | Immed     | 5+    | 2  67  ASH    |          | 6+  2+  |
|               |         |       |                                                |           | -     | 68  ASL, LSL  |          |         |
| 08  ASL, LSL  |         | 6  2  | 38                                             |           |       |               |          | 6+  2+  |
| 09  ROL       |         | 6  2  | 39  RTS                                        | Inherent  | 5     | 1  69  ROL    |          | 6+  2+  |
| ·DE C         |         |       | ABX                                            |           | t 3   | 1  6A  ·DE C  |          | 6+  2+  |
| OA            |         | 6  2  | 3A                                             |           |       |               |          |         |
| OB            |         |       | 3B  RTI                                        |           | 6/15  | 1  6B         |          |         |
|               |         |       | CWAI                                           |           |       | 2  6C  INC    |          | 6+  2+  |
| OC  INC       |         | 6  2  | 3C                                             |           | ~20   |               |          |         |
| 00  TST       |         | 6  2  | 3D  ·MU L                                      | Inherent  | 11    | 1  60  lST    |          | 6+  2+  |
| OE  JMP       |         |       | 3E                                             |           | -     | 6E  JMP       |          | 3+  2+  |
|               |         | 3  2  |                                                |           |       |               |          |         |
OF  CLR  Direct  6  2  3F  SWI  Inherent  19  1  6F  CLR  Indexed  6+  2+
10  Page 2  - - - 40  NEGA  Inherent  2  1  70  NEG  Extended 7  3
| 11  Page 3  |     | - - | 41  *  |     |     | 71  *  |     |     |
| ----------- | --- | --- | ------ | --- | --- | ------ | --- | --- |
-
| 12  NOP     | Inherent     | 2  1  | 42  *           |     |     | 72  *            |     |       |
| ----------- | ------------ | ----- | --------------- | --- | --- | ---------------- | --- | ----- |
| 13  SYNC    | Inherent ~4  | 1     | 43  COMA        |     | 2   | 1  73  COM       |     | 7  3  |
| 14  *       |              |       | 44  LSRA        |     | 2   | 1  74  LSR       |     | 7  3  |
| 15  *       |              |       | 45  *           |     |     | 75  *            |     |       |
| 16  LBRA    | Relative     | 5  3  | 46  RORA        |     | 2   | 1  76  ROR       |     | 7  3  |
| 17  ·LB SR  | Relative     | 9  3  | 47  ASRA        |     | 2   | 1  77  ASR       |     | 7  3  |
| 18          |              |       | 48  ASLA, LSLA  |     | 2   | 1  78  ASL, LSL  |     | 7  3  |
| 19  OAA     | Inherent     | 2  1  | 49  ROLA        |     | 2   | 1  79  ROL       |     | 7  3  |
| 1A  ORCC    | Immed        | 3  2  | 4A  ·OE CA      |     | 2   | 1  7A  OEC       |     | 7  3  |
| 1B  *       |              |       | 4B              |     |     | 7B  *            |     |       |
-
| 1C  ANOCC  | Immed     | 3  2  | 4C  INCA  |     | 2   | 1  7C  INC  |     | 7  3  |
| ---------- | --------- | ----- | --------- | --- | --- | ----------- | --- | ----- |
| 10  SEX    | Inherent  | 2  1  | 40  TSTA  |     | 2   | 1  70  TST  |     | 7  3  |
| 1E  EXG    | Immed     | 8  2  | 4E  *     |     |     | 7E  JMP     |     | 4  3  |
1F  TFR  Immed  6  2  4F  CLRA  Inherent  2  1  7F  CLR  Extended 7  3
20  BRA  Relative  3  2  50  NEGB  Inherent  2  1  80  SUBA  Immed  2  2
| 21  BRN       |           | 3  2  | 51  *           |           |     | 81  CMPA      |           | 2  2  |
| ------------- | --------- | ----- | --------------- | --------- | --- | ------------- | --------- | ----- |
| 22  BHI       |           | 3  2  | 52  *           |           |     | 82  SBCA      |           | 2  2  |
| 23  BLS       |           | 3  2  | 53  COMB        |           | 2   | 1  83  SUBO   |           | 4  3  |
| 24  BHS, BCC  |           | 3  2  | 54  LSRB        |           | 2   | 1  84  ANOA   |           | 2  2  |
| 25  BLD, BCS  |           | 3  2  | 55  *           |           |     | 85  BITA      |           | 2  2  |
| 26  BNE       |           | 3  2  | 56  RORB        |           | 2   | 1  86  ·LO A  |           | 2  2  |
| 27  BEQ       |           | 3  2  | 57  ASRB        |           | 2   | 1  87         |           |       |
| 28  BVC       |           | 3  2  | 68  ASLB, LSLB  |           | 2   | 1  68  EORA   |           | 2  2  |
|               |           |       |                 |           |     | 1  AOCA       |           | 2     |
| 29  BVS       |           | 3  2  | 59  ROLB        |           | 2   | 89            |           | 2     |
| 2A  BPL       |           | 3  2  | 5A  OECB        |           | 2   | 1  8A  ORA    |           | 2  2  |
|               |           |       | *               |           |     | 8B  AOOA      |           | 2  2  |
| 2B  BMI       |           | 3  2  | 5B              |           |     |               |           |       |
| 2C  BGE       |           | 3  2  | 5C  INCB        |           | 2   | 1  8C  CMPX   | Immed     | 4  3  |
| 20  BLT       |           |       | 50  TSTB        |           | 2   | 1  80  BSR    | Relative  | 7  2  |
|               |           | 3  2  |                 |           |     |               |           |       |
| 2E  BGT       |           | 3  2  | 5E  *           |           |     | 8E  ·LO X     | Immed     | 3  3  |
|               |           |       | 5F  CLRB        | Inherent  | 2   | 1  8F         |           |       |
| 2F  BLE       | Relative  | 3  2  |                 |           |     |               |           |       |
LEGEND:
- Number of MPU cycles (Jess possible push pull or indexed-mode cycles)
# Number of program bytes
* Denotes unused opcode

Me6S09E
|               |         | TABLE 9 - | HEXADECIMAL VALUES OF MACHINE CODES (CONTINUED)  |                 |         |                 |               |                       |           |               |
| ------------- | ------- | --------- | ------------------------------------------------ | --------------- | ------- | --------------- | ------------- | --------------------- | --------- | ------------- |
|               |         | -         |                                                  |                 |         | -               |               | I                     |           | I- I          |
| OP  Mnem      | Mode    |           | #                                                | OP  Mnem        | Mode    |                 | #  OP         | M nem                 | 1  Mode   | #             |
| 90  SUBA      |         | 4         |                                                  |                 |         |                 |               |                       |           |               |
|               | Direct  |           | 2                                                | CO  SUBB        | Immed   | 2               | 2             |                       |           |               |
| 91  CMPA      |         | 4         | 2                                                | Cl  CMPB        |         | 2               | 2             |                       |           |               |
| 92  SBCA      |         |           |                                                  |                 |         | r               |               | Page 2 and 3 Machine  |           |               |
|               |         | 4         | 2                                                | C2  SBCB        |         | 2               | 2             |                       | Codes     |               |
| 93  SUBD      |         | 6         | 2                                                | C3  ADDD        |         | 4               | 3             |                       |           |               |
| 94  ANDA      |         | 4         | 2                                                |                 |         |                 |               |                       |           |               |
|               |         |           |                                                  | C4  ANDB        |         | 2               | 2  1021       | LBRN                  | Relative  | 5  4          |
| 95  BITA      |         | 4         | 2                                                | C5  BITB        | Immed   | 2               | 2             | LBHI                  |           |               |
| 9 6   L D A   |         | 4         | 2                                                |                 |         |                 | 1022          |                       |           | 5161  4       |
|               |         |           |                                                  | C 6   L D B     | ImImed  | 2               | 2  1 0 2 3    | L B L S               |           | 5 1 6 1   4   |
| 97   S T A    |         | 4         | 2                                                | C 7   *         |         |                 |               | L B H S , LBCC        |           |               |
| 98  EORA      |         | 4         | 2                                                |                 |         |                 | 1 0 2 4       |                       |           | 5 1 6 1   4   |
|               |         |           |                                                  | C8  EORB        |         | 2               | 2  1025       | LBCS, LBLO            |           | 5(6)  4       |
| 99  ADCA      |         | 4         | 2                                                | C9  ADCB        |         | 2               | 2  1026       | LBNE                  |           | 5161  4       |
| 9A  ORA       |         | 4         | 2                                                |                 |         |                 |               |                       |           |               |
|               |         |           |                                                  | CA  ORB         |         | 2               | 2  1027       | LBEQ                  |           | 5161  4       |
| 9B  ADDA      |         | 4         | 2                                                | CB  .AD DB"     |         | 2               | 2  1028       | LBVC                  |           | 5161  4       |
| 9C  CMPX      |         | 6         | 2                                                |                 |         |                 |               |                       |           |               |
|               |         |           |                                                  | CC  LDD         |         | 3               | 3  1029       | LBVS                  |           | 5(6)  4       |
| 9D  JSR       |         | 7         | 2                                                | CD  .           |         |                 | 102A          | LBPL                  |           | 5161  4       |
| 9E  LDX       |         | 5         | 2                                                |                 |         |                 |               |                       |           |               |
|               |         |           |                                                  | CE  LDU         | Immed   | 3               | 3  102B       | LBMI                  |           | 5161  4       |
| 9F  STX       | Direct  | 5         | 2                                                | CF              |         |                 | 102C          | LBGE                  |           | 5(6)  4       |
|               |         |           |                                                  | D O   S U B B   | D       | i r e c t   4   | 2   1 0 2 D   | L B L T               |           | 5 1 6 1   4   |
A O   S U B A   I n d e x e d   4 +   2 +   1 0 2 E   L B G T   5 1 6 1   4
| A I  C M P A   |     | 4 + |   2 +   | D l  C M P B    |     | 4   | 2             |           |     |                               |
| -------------- | --- | --- | ------- | --------------- | --- | --- | ------------- | --------- | --- | ----------------------------- |
|                |     |     |         | D 2   S B C B   |     | 4   | 2   1 0 2 F   | L B L E   | R   | e l a t i v e   5 1 6 1   4   |
A 2   S B C A   4 +   2 +   I 0 3 F   S W I 2   I n h e r e n t   2 0   2
| A 3   S U B D   |     | 6 + |   2 +   | D 3   A D D D   |     | 6   | 2             |           |     |                 |
| --------------- | --- | --- | ------- | --------------- | --- | --- | ------------- | --------- | --- | --------------- |
|                 |     |     |         | D 4   A N D B   |     | 4   | 2   1 0 8 3   | C M P b   | I m | m e d   5   4   |
| A 4   A N D A   |     | 4 + |   2 +   |                 |     |     | 1 0 8 C       | C M P Y   |     | I   5   4       |
| A 5   B I T A   |     | 4 + |   2 +   | D 5   B I T B   |     | 4   | 2             |           |     |                 |
|                 |     |     |         | D 6   L D B     |     | 4   | 2   1 0 8 E   | L D Y     | I m | m e d   4   4   |
A 6   L D A   4 +   2 +   1 0 9 3   C M P D   D i r t e c t    7   3
| A 7   S T A     |     | 4 + |   2 +   | D 7   S T B     |     | 4   | 2             |           |     |                     |
| --------------- | --- | --- | ------- | --------------- | --- | --- | ------------- | --------- | --- | ------------------- |
|                 |     |     |         | D 8   E O R B   |     | 4   | 2   I 0 9 C   | C M P Y   |     | 7   3               |
| A 8   E O R A   |     | 4 + |   2 +   |                 |     |     | 1 0 9 E       | L D Y     |     | 6   3               |
| A 9   A D C A   |     | 4 + |   2 +   | D 9   A D C B   |     | 4   | 2             |           |     |                     |
|                 |     |     |         | D A   O R B     |     | 4   | 2   I 0 9 F   | S T Y     | D   | i r e c t   6   3   |
A A   O R A   4 +   2 +   1 0 A 3   C M P D   I n d e x e d   7 +   3 +
| A B   A D D A   |     | 4 + |   2 +   | D B   A D D B   |     | 4   | 2           |             |     | t           |
| --------------- | --- | --- | ------- | --------------- | --- | --- | ----------- | ----------- | --- | ----------- |
|                 |     |     |         | D C   L D D     |     | 5   | 2   l O A C |   C M P Y   |     | 7 +   3 +   |
| A C   C M P X   |     | 6 + |   2 +   |                 |     |     | 1 0 A E     | L D Y       |     | 6 +   3 +   |
| A D   J S R     |     | 7 + |   2 +   | D D   S T D     |     | 5   | 2           |             |     |             |
A E   L D X   D E   L D U   5   2   lO A F   S T Y   I n d e x e d   6 +   3 +
|               |             | 5 +           |   2 +   |               |          |                 | 1 0 B 3   | C M P D     | E x         | t e n d e d   8   4   |
| ------------- | ----------- | ------------- | ------- | ------------- | -------- | --------------- | --------- | ----------- | ----------- | --------------------- |
| A F   S T X   | I n d       | e x e d   5 + |   2 +   | D F   S T U   | D        | i r e c t   5   | 2         |             |             |                       |
|               |             |               |         |               |          |                 | 1 0 B C   |   C M P Y   |             | ~   8   4             |
|               |             |               |         | EO  SUBB      | Indexed  | 4+              | 2+  lOBE  | LDY         |             | 7  4                  |
| BO  SUBA      | Extended 5  |               | 3       | El  CMPB      |          | 4+              | 2+        |             |             |                       |
| Bl  CMPA      |             |               |         |               |          |                 | 10BF      | STY         | Extended 7  | 4                     |
|               |             | 5             | 3       | E2  SBCB      |          | 4+              | 2+  lOCE  | LDS         | Immed       | 4  4                  |
| B2  SBCA      |             | 5             | 3       | E3  ADDD      |          | 6+              | 2+        |             |             |                       |
| B3  SUBD      |             | 7             | 3       |               |          |                 | lODE      | LDS         | Direct      | 6  3                  |
|               |             |               |         | E4  ANDB      |          | 4+              | 2+  10DF  | STS         | Direct      | 6  3                  |
| B4  ANDA      |             | 5             | 3       | E5  BITB      |          | 4+              | 2+        |             |             |                       |
| B5  BITA      |             | 5             | 3       |               |          |                 | 10EE      | LDS         | Indexed     | 6+  3+                |
|               |             |               |         | E6  LDB       |          | 4+              | 2+  10EF  | STS         | Indexed     | 6+  3+                |
| B6  LDA       |             | 5             | 3       | E7  STB       |          | 4+              | 2+  10FE  | LDS         | Extended 7  |                       |
| B7  STA       |             | 5             | 3       |               |          |                 |           |             |             | 4                     |
|               |             |               |         | E8  EORB      |          | 4+              | 2+  10FF  | STS         | Extended 7  | 4                     |
| B8  EORA      |             | 5             | 3       | E9  ADCB      |          | 4+              | 2+  113F  | SWI3        |             |                       |
| B9  ADCA      |             | 5             | 3       |               |          |                 |           |             | Inherent    | 20  2                 |
|               |             |               |         | EA  ORB       |          | 4+              | 2+  1183  | CMPU        | Immed       | 5  4                  |
| BA  ORA       |             | 5             | 3       | EB  ADDB      |          | 4+              | 2+  118C  | CMPS        | Immed       | 5  4                  |
| BB  ADDA      |             | 5             | 3       |               |          |                 |           |             |             |                       |
|               |             |               |         | EC  LDD       |          | 5+              | 2+  1193  | CMPU        | Direct      | 7  3                  |
B C   C M P X  7   3  E D   S TO   5 +   2 +   1 1 9C   C M P S  D ir e c t   7  3
| B D   J S R   |     | 8   | a   |             |     |       |               |          |     |                       |
| ------------- | --- | --- | --- | ----------- | --- | ----- | ------------- | -------- | --- | --------------------- |
|               |     |     |     | EE   L O U  |     | 5 +   | 2+   l1 A 3   | CM P U   | In  | d e x e d   7 +  3 +  |
BE  LDX  6  3  EF  STU  Indexed  5+  2+  llAC CMPS  Indexed  7+  3+
| BF  STX  | Extende d 6  |     | 3   |           |             |       |               |       |             |     |
| -------- | ------------ | --- | --- | --------- | ----------- | ----- | ------------- | ----- | ----------- | --- |
|          |              |     |     | FO  SUBB  | Extended 5  |       | l1B3          | CMPU  | Extended 8  | 4   |
|          |              |     |     |           |             |       | 3  11BC CMPS  |       | Extended 8  | 4   |
|          |              |     |     | Fl  CMPB  |             | !  5  | 3             |       |             |     |
|          |              |     |     | F2  SBCB  |             | 5     |               |       |             |     |
3
|     |     |     |     | F3  ADDD   |     | 7   | 3   |     |     |     |
| --- | --- | --- | --- | ---------- | --- | --- | --- | --- | --- | --- |
|     |     |     |     | F4  AN DB  |     | 5   | 3   |     |     |     |
|     |     |     |     | F5  BITB   |     | 5   | 3   |     |     |     |
|     |     |     |     | F6  LDB    |     | 5   | 3   |     |     |     |
|     |     |     |     | F7  STB    |     | 5   | 3   |     |     |     |
|     |     |     |     | F8  EORB   |     | 5   | 3   |     |     |     |
NOTE: All unused opcodes are both undefined
| and illegal  |     |     |     | F9  ADCB  |               | 5   | 3   |     |     |     |
| ------------ | --- | --- | --- | --------- | ------------- | --- | --- | --- | --- | --- |
|              |     |     |     | FA  ORB   |               | 5   | 3   |     |     |     |
|              |     |     |     | FB  AODB  | Extended 5    |     | 3   |     |     |     |
|              |     |     |     | FC  LDD   | Extetnd ed 6  |     | 3   |     |     |     |
|              |     |     |     | FD  STD   |               | 6   | 3   |     |     |     |
|              |     |     |     | FE  LOU   |               | 6   | 3   |     |     |     |
|              |     |     |     | FF  STU   | Extende d 6   |     | 3   |     |     |     |

Me6S09E
|     |     |     |     |     | FIGURE 18 - | PROGRAMMING AID  |     |     |     |     |     |
| --- | --- | --- | --- | --- | ----------- | ---------------- | --- | --- | --- | --- | --- |
Addressing Modes
Imme-diate  Dir-ect  Indexed  Exte-nded  Inhe-rent  5  3  2  1  0
Instruction  Forms  Op  #  Op  #  Op  #  Op  #  Op  #  Description  H·  N·  ·Z  V·  C·
| ABX  |     |     |     |     |     | 3A  | 3  1  B + X-X (Unsigned)  |     |     |     |     |
| ---- | --- | --- | --- | --- | --- | --- | ------------------------- | --- | --- | --- | --- |
ADC  ADCA  89  2  2  99  4  2  A9  B9  5  A+M+C-A  I  I  I  I  I
|     |     |     |     |     | 4+  2+  | 3   |     |     |     |     |     |
| --- | --- | --- | --- | --- | ------- | --- | --- | --- | --- | --- | --- |
ADCB  C9  2  2  D9  4  2  E9  4+  2+  F9  5  3  B+M+C-B  I  I  I  I  I
ADD  ADDA  8B  2  2  9B  4  2  AB  4+  2+  BB  5  3  A+M-A  I  I  I  I  I
ADDB  CB  2  2  DB  4  2  EB  4+  2+  FB  5  3  B+M-B  ·I  I  I  I  I
ADDD  C3  4  3  D3  6  2  E3  6+  2+  F3  7  3  D+M:M+1-D  · I  I  I  ·I
| AND  | ANOA  | 84  |       | 94  4  |             |           |       |     |     | · I  | 0  ·  |
| ---- | ----- | --- | ----- | ------ | ----------- | --------- | ----- | --- | --- | ---- | ----- |
|      |       |     | 2  2  | 2      | A4  4+  2+  | B4  5  3  | AA M  | A   |     |      | I     |
ANOB  C4  2  2  D4  4  2  E4  4+  2+  F4  5  3  B A M-8  I  I  0
|      | ANOCC  | 1C  | 3  2  |     |     |     | CC A IMM-CC  |                  |     |       | 7        |
| ---- | ------ | --- | ----- | --- | --- | --- | ------------ | ---------------- | --- | ----- | -------- |
| ASL  | ASLA   |     |       |     |     | 48  | 2  1         | ~1[H I lim If-o  |     | B  I  | I  I  I  |
|      | ASLB   |     |       |     |     | 58  | 2  1         |                  |     | B  I  | I  I  I  |
ASL  08  6  2  68  6+  2+  78  7  3  M  c  b7  bO  8  I  I  ·I  I
| ASR  | A S R | A   |     |           |         | 4 7    | 2   1   | A ~     | -       | 8   I   | I   ·   I   |
| ---- | ----- | --- | --- | --------- | ------- | ------ | ------- | ------- | ------- | ------- | ----------- |
|      | A S R | 8   |     |           |         | 5 7    | 2   1   | ~ll lli | ll iHJ  | 8   I   | I   ·   I   |
|      | ASR   |     |     | 07  6  2  | 67      | 7      |         |         | Eo      | ·8  I   | I  ·I       |
|      |       |     |     |           | 6+  2+  | 77  3  |         | 7       |         | c       |             |
81T  BITA  85  2  2  95  4  2  A5  4+  2T  B5  5  3  Bit Test A (M A AI  · I  I  0  ·
BITB  C5  2  2  D5  4  2  E5  4+  2+  F5  5  3  Bit Test B (M A BJ  · I  I  0
| CLR  | CLRA  |     |     |           |             | 4F        | 2  1 O-A   |     |     | · 0  | 1  0  0  |
| ---- | ----- | --- | --- | --------- | ----------- | --------- | ---------- | --- | --- | ---- | -------- |
|      | CLR8  |     |     |           |             | 5F        | 2  1  O-B  |     |     | · 0  | 1  0  0  |
|      | CLR   |     |     | OF  6  2  | 6F  6+  2+  | 7F  7  3  | O-M        |     |     | 0    | 1  0  0  |
CMP  CMPA  81  2  2  91  4  2  A1  4+  2+  B1  5  3  Compare M from A  8  I  I  I  I
CMPB  C1  2  2  D1  4  2  El  4+  2+  F1  5  3  Compare M from B  ·8  I  I  I  I
CMPO  10  5  4  10  7  3  10  7+  3+  10  8  4  Compare M:M + 1 from D  I  t  I  I
|     |     | 83  |     | 93  | A3  | B3  |     |     |     | ·   |     |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
CMPS  11  5  4  11  7  3  11  7+  3+  11  8  4  Compare M: M + 1 from S  I  I  I  I
|     |     | 8C  |     | 9C  | AC  | 8C  |     |     |     | ·   |     |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
CMPU  11  5  4  11  7  3  11  7+  3+  11  8  4  Compare M.M + 1 from U  I  I  I  I
|     |       | 83  |       | 93        | A3          | B3        |                         |     |     | ·    |          |
| --- | ----- | --- | ----- | --------- | ----------- | --------- | ----------------------- | --- | --- | ---- | -------- |
|     |       |     |       |           |             |           | Compare M M + 1 from X  |     |     | · I  |          |
|     | CMPX  | 8C  | 4  3  | 9C  6  2  | AC  6+  2+  | BC  7  3  |                         |     |     |      | I  I  I  |
CMPY  10  5  4  10  7  3  10  7+  3+  10  8  4  Compare M.M + 1 from Y  I  I  I  I
|       |       | 8C  |           | 9C        | AC          | BC        |                                 |     |     | ·    |          |
| ----- | ----- | --- | --------- | --------- | ----------- | --------- | ------------------------------- | --- | --- | ---- | -------- |
| COM   | COMA  |     |           |           |             | 43        | 2  1  A-A                       |     |     | · I  | I  0  1  |
|       | COMB  |     |           |           |             | 53        | 2  1 B-B                        |     |     | · t  | I  0  1  |
|       | COM   |     |           | 03  6  2  | 63  6+  2+  | 73  7  3  | liii-M                          |     |     | I    | I  0  1  |
| CWAI  |       | 3C  | 2:l2C  2  |           |             |           | CC A IMM-CC Walt for Interrupt  |     |     | ·    | 7        |
|       |       |     |           |           |             |           | 1  DeCimal Adjust A             |     |     | · I  | 0  ·I    |
| DAA   |       |     |           |           |             | 19        | 2                               |     |     |      | I        |
| DEC   | OECA  |     |           |           |             | 4A        | 2  1  A-1                       | A   |     | · I  | I  t  ·  |
|       | DECB  |     |           |           |             | 5A        | 2  1  B-1-B                     |     |     | · t  | t  t  ·  |
|       | DEC   |     |           | OA  6  2  | 6A  6+  2+  | 7A  7  3  | M-1-M                           |     |     | · t  | I  t  ·  |
EOR  EORA  B8  2  2  98  4  2  A8  4+  2+  B8  5  3  A-II-M-A  · t  I  0  ·
|      |         |     |       |           |             |           | B¥M-B               |     |     | · ·t  ·t  ·0  ·  |          |
| ---- | ------- | --- | ----- | --------- | ----------- | --------- | ------------------- | --- | --- | ---------------- | -------- |
|      | EORB    | C8  | 2  2  | D8  4  2  | E8  4+  2+  | F8  5  3  |                     |     |     |                  |          |
| EXG  | R1, R2  | 1E  | 8  2  |           |             |           | R1-R22              |     |     | ·                | ·        |
| INC  | INCA    |     |       |           |             | 4C        | 2  1  A+ 1--A       |     |     | · I              | t  t  ·  |
|      | INCB    |     |       |           |             | 5C        | 2  1  B+ 1-B        |     |     | · t              | t  t  ·  |
|      | INC     |     |       | DC  6  2  | 6C  6+  2+  | 7C  7  3  | M+1-M               |     |     | · ·t  ·t  ·t  ·  |          |
| JMP  |         |     |       | OE  3  2  | 6E  3+  2+  | 7E  4  3  | EA3_PC              |     |     | · · · · ·        |          |
| JSR  |         |     |       | 90  7  2  | AD  7+  2+  | BD  8     | Jump to Subroutine  |     |     |                  |          |
|      |         |     |       |           |             | 3         |                     |     |     | ·                | ·        |
LD  LDA  86  2  2  96  4  2  A6  4+  2+  B6  5  3  M-A  · t  I  0  ·
LDB  C6  2  2  D6  4  2  E6  4+  2+  F6  5  3  M-B  · t  t  0  ·
LDD  CC  3  3  DC  5  2  EC  5+  2+  FC  6  3  M M+1-D  · t  t  0  ·
LDS  10  4  4  10  6  3  10  6+  3+  10  7  4  MM+1-S  t  t  0
|     |     | CE  |     | DE  | EE  | FE  |     |     |     | ·    | ·   |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---- | --- |
|     |     |     |     |     |     |     |     |     |     | · t  | ·   |
LDU  CE  3  3  DE  5  2  EE  5+  2+  FE  6  3  M.M+1-U  t  0
LDX  8E  3  3  9E  5  2  AE  5+  2+  BE  6  3  M.M+1-X  · t  t  0  ·
LDY  10  4  4  10  6  3  10  6+  3+  10  7  4  MM+1-Y  t  t  0
|     |     | 8E  |     | 9E  | AE  | BE  |     |     |     |     |     |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
· · · · ·
| LEA  | LEAS  |     |     |     | 32  4+  2+  |     | EA3_S  |     |     | · · · · ·  |      |
| ---- | ----- | --- | --- | --- | ----------- | --- | ------ | --- | --- | ---------- | ---- |
|      | LEAU  |     |     |     | 33  4+  2+  |     | EA3_U  |     |     | · ·        | · ·  |
|      | LEAX  |     |     |     | 30  4+  2+  |     | EA3_X  |     |     | · · t      | · ·  |
|      | LEAY  |     |     |     | 31  4+  2+  |     | EA3_y  |     |     |            | I    |
LEGEND:  liii  Complement of M  Test and set if true, cleared otherwise
OP  Operation Code (Hexadecimal)  Transfer Into  Not Affected
Number of MPU Cycles  H  Half-carry (from bit 3)  CC  Condition Code Register
Number of Program Bytes  N  Negative (sign bit)  Concatenation
| +  Arithmetic Plus  |     |     |     | Z   | Zero result  |     |     | V  Logical or  |     |     |     |
| ------------------- | --- | --- | --- | --- | ------------ | --- | --- | -------------- | --- | --- | --- |
Arithmetic Minus  V  Overflow, 2's complement  A  Logical and
| Multiply  |     |     |     | C   |     |     |     | ¥  Logical Exclusive or  |     |     |     |
| --------- | --- | --- | --- | --- | --- | --- | --- | ------------------------ | --- | --- | --- |
Carry from ALU

Me6S09E
|     |     |     | FIGURE 18 - | PilOGRAMMING AID (CONTINUED)  |           |     |     |     |     |     |
| --- | --- | --- | ----------- | ----------------------------- | --------- | --- | --- | --- | --- | --- |
|     |     |     | A d         | dr e~ i n g   ·               | M ~ e,s   | ,   | ,   |     |     |     |
I m me-dtate   Di-rect  ,   I n d e- x e d 1  E xte-nded   I nhe-rent  5  3   2   1  0
In~ruction  Forms  u p   •   up  u p   up   Op   Description  H    N ,   Z ,   V,   C ,
· ,   ,  ,
| LSL  | l S L  | A   |            |         |         | 4 8   2 |   1   ~I[H liTIIIl f-o' · |      | ·      |             |
| ---- | ------ | --- | ---------- | ------- | ------- | ------- | ------------------------- | ---- | ------ | ----------- |
|      | L S LB |     |            |         |         | 5 8     | 2   1                     |      |   , j  |  ,   ,   ,  |
|      |        |     |            |         |         |         |                           | bQ   |        | , · ,       |
|      | LSL    |     | (1)  6  2  | 58  6+  | 2+  78  | 7  3    | M                         | cb7  | ·      |             |
LSR  'L S R A   4 4   2   1   -.1 11 I 11111-0  ·   0   ,   ·   ,
|      |       |     |           |         |         |         | . ~A I               | 0       |               | ,   ,         |
| ---- | ----- | --- | --------- | ------- | ------- | ------- | -------------------- | ------- | ------------- | ------------- |
|      | L SR  | B   |           |         |         | 5 4     | 2   1                |         | ·  Q          | ·             |
|      | LSR   |     | 04  6  2  | 54  6+  | 2+  74  | 7  3    |                      | b7  bQ  | C  · ·0  , ·  |               |
| MUL  |       |     |           |         |         |         | A x B--D (UnsIgned)  |         | , , , 9,      |               |
|      |       |     |           |         |         | 30  11  | 1                    |         | ,             |   ,   ,   ,   |
| NEG  | N E G | A   |           |         |         | 4 0     | 2   1   A +          | 1 - A   | 8             |               |
|      | NE G  | B   |           |         |         | 5 0     | 2   1  8 +  1        | - B     | 8   ,         |   ,   ,   ,   |
|      | NEG   |     | 00  6  2  | 60  6+  | 2+  70  | 7  3    | M+.1-M               |         | ·8  · · · ·   |               |
| NOP  |       |     |           |         |         | 12      | 2  1 No Operation    |         | ·  , ,        | ·             |
· , ,
OR  ORA  8A  2  2  9A  4  2  AA 4+  2+  BA  5  3  AV M-A  0  ·
|     | ORB   | CA  | 2  2  OA  4  2  | EA  4+  | 2+  FA  | 5  3  | B V M-B  |     |              | 0   |
| --- | ----- | --- | --------------- | ------- | ------- | ----- | -------- | --- | ------------ | --- |
|     | ORCC  | 1A  | 3  2            |         |         |       |          |     | · · · ·7  ·  |     |
CC V 'MM-CC
| PSH  | PSHS  | 34 5+4  | 2   |     |     |     | Push Registers on S .Stack  |     | · · · · ·  |     |
| ---- | ----- | ------- | --- | --- | --- | --- | --------------------------- | --- | ---------- | --- |
|      | PSHU  | 36 5+4  | 2   |     |     |     | Push ReQisters on U Stack   |     |            |     |
· · · · ·
P\JL'  PULS  35 5+  2  Pull Registers from S Stack  · · · · ·
PU L U   37  5+4  2  Pull Registers from U Stack  ·   ,   ,   ,  ,
,   ,  ,   ,
| ROl'  | R O L | A   |           |         |         | 49    | 2  1  ~} ~ III 1111 ~ · , , , ,  |            | ·          |          |
| ----- | ----- | --- | --------- | ------- | ------- | ----- | -------------------------------- | ---------- | ---------- | -------- |
|       | ROLB  |     |           |         |         | 59    | 2  1                             |            |            |          |
|       | ROL   |     | 09  6  2  | 69  6+  | 2+  79  | 7  3  |                                  |            | · , , · ,  |          |
|       |       |     |           |         |         |       |                                  | C  b7  60  | ,          | ,  ,     |
| ROR   | R O R | A   |           |         |         | 4 6   | 2   1   ~}~IIIIIIIP ·            |            | ·          | ·        |
|       | RO R  | B   |           |         |         | 5 8   | 2   1                            |            |  ,         |  ,   ·   |
bQ
|      | ROR  |     | 06  6  2  | 66  6+  | 2+  76  | 7  3     |                           | C  b7  |              | 1   |
| ---- | ---- | --- | --------- | ------- | ------- | -------- | ------------------------- | ------ | ------------ | --- |
| RT'  |      |     |           |         |         | 3B 6115  | 1  Return From Interrupt  |        | · · · · ·7   |     |
, , , ,
| RTS  |     |     |     |     |     | 39  | 5  1  Return from Subroutine  |     |     |     |
| ---- | --- | --- | --- | --- | --- | --- | ----------------------------- | --- | --- | --- |
SBC  SBCA  82  2  2  92  4  2  A2  4+  2+  B2  5  3  A  M  C-A  8  ,  , ,
·8  , ,j
|        | 'SBCB  | C2  | 2  2  02  4  2  | E2  4+  | 2+  F2  | 5  3  | B-M-C-B       |                 |     | ·          |
| ------ | ------ | --- | --------------- | ------- | ------- | ----- | ------------- | --------------- | --- | ---------- |
| S E X  |        |     |                 |         |         | 10    | 2  1  Sig n E | xtend B into A  | ,   | ,  0   ·   |
•  ,   ,
S T  S T A   97   4   2   A 7   4 +  2 +   B 7   5   3   A - M   ·   ,   ,  o 0
ST B   D 7   4   2   E 7  4 +   2 +   F7   5   3   B -M   ·    ' ·.
|     | STD  |     | DD  5  2  | ED  5+  | 2+  FD  | 6  3  | D-M:M+1  |     | · ,  | 0  ·  |
| --- | ---- | --- | --------- | ------- | ------- | ----- | -------- | --- | ---- | ----- |
STS  10   6  3  1 0  6+  3+  1 0   7  4  S-M:M+1  , , I    0
|     |     |     | D F   | E F   | F F   |     |     |     | ·   | ·   |
| --- | --- | --- | ----- | ----- | ----- | --- | --- | --- | --- | --- |
S T U   D F   5   2   E F  5 +   2 +   FF   6   3   U - M : M + 1   ·  ,   ,   0   ·
|     |     |     |     |     | 2 +   |     |     |     | ·   , |  ,   |
| --- | --- | --- | --- | --- | ----- | --- | --- | --- | ----- | ---- |
S T X  9F   5   2   A F   5 +   B F   6   3   X- M : M + 1   O.   ·
|     | STY  |     | 10  6  3  | 10      | 10       | 7  4  | Y-M:M+1  |     |          | 0   |
| --- | ---- | --- | --------- | ------- | -------- | ----- | -------- | --- | -------- | --- |
|     |      |     | 9F        | AF  6+  | 3+.  8F  |       |          |     | , , , ,  |     |
, , , ,
SUB  SUBA  80  2  2  90  4  2  AO  4+  2+  BO  5  3  A-·M  A  8
SUBB  CO  2  2  DO  4  2  EO  4+  2+  FO  5  3  B-M-B  ·8  , , , ,
|       |         |     |                 | 6+. '2+  |     | 1         |                           |     | · · · · ·  |     |
| ----- | ------- | --- | --------------- | -------- | --- | --------- | ------------------------- | --- | ---------- | --- |
|       | SUBD    | 83  | 4  3  93  6  2  | A3       | B3  | 3         | D-M:M+1-D                 |     |            |     |
| SWI   | SWlo    |     |                 |          |     | 3F  19    | 1  Software"·lnterrupf 1  |     | · · · · ·  |     |
|       | SWIz6   |     |                 |          |     | 10  20    | 2  Software Interrupt 2   |     |            |     |
|       |         |     |                 |          |     | 3F        |                           |     | · · · · ·  |     |
|       | SWIJ6   |     |                 |          |     | 11  20    | 1  Software Interrupt 3   |     |            |     |
|       |         |     |                 |          |     | 3F        |                           |     | · · · · ·  |     |
| SYNC  |         |     |                 |          |     | 13  ~4 1  | Synchronize to Interrupt  |     | · · · · ·  |     |
| TFR   | R1, R2  | 1F  | 6  2            |          |     |           | R1-R2"                    |     | · ,        | ·   |
 ,
| TSJ  | T S T | A   |            |         |         | 4 D   | 2  1   Te s t  | A    | ·    |  ,j    0   ·   |
| ---- | ----- | --- | ---------- | ------- | ------- | ----- | -------------- | ---- | ---- | -------------- |
|      | TS T  | B   |            |         |         | 5 D   | 2   1   T e st |   8  | ·  , | j   0   ·      |
|      | TST   |     | OD  .6  2  | 6D  6+  | 2+  70  | 7  3  | Test M         |      |      | 0              |
NOTES:
1. 'This column gives a basa cycle and byte count. To obtain total count, add the values obtained from the INDEXED ADDRESSING MODE table,
Table 2 .
. 2:  Rl and R2 may be any pair of a bit or· any pair of 16 bit registers .
.T he.a biuegisters are: A, B, CC, DP
The 16 bit registers are: X, Y, U., S, D, PC
. 3.  EA is the effective address.
4.  The PSH andPUL ·instr,uctions require 5 cycles plus 1 cycle for each byte pushed 'or pulled.
5.  5(61 means: 5 cycles if branch not taken, 6 cycles if taken !Branch instructions).
SWI sets. I and F bits:··swi2 and SWI3 do not affect I imd F.
6.
7.  Conditions Codes set as a direct result of the instruction.
8.  Vaue of half-carry flag is undefined.
| 9.  | Special Casa - | Carry sat il b7 is SET.  |     |     |     |     |     |     |     |     |
| --- | -------------- | ------------------------ | --- | --- | --- | --- | --- | --- | --- | --- |

Me6809E
|     |     | . FIGURE 18 - | PROGRAMMING AID (CONTINUED)  |     |     |     |     |
| --- | --- | ------------- | ---------------------------- | --- | --- | --- | --- |
Branch Instructions
-
|     | AddreuOIg  |     |                |     | AdMdraB_li ng  |     |          |
| --- | ---------- | --- | -------------- | --- | -------------- | --- | -------- |
|     |            | ,   |                |     |                | ,   |          |
|     | Relative   |     | 5  3  2  1  0  |     |                |     | 2  I  0  |
Il"IIItrUction  Forms  OP  -5  Delcription  ·H   N•  ·Z  ·V  ·e   Instruction  Form.  OP  -5  Desc:ription  H·  N·  Z·  V·  C·
..
Bee  Bee  24  3  2  Branch C-O  · · · ·  BlS  BlS  23  3  2  Branch Lower
| lBCC  | 10 5161  | 4  Long Branch  |            |       |           | or Same               | · · · · ·  |
| ----- | -------- | --------------- | ---------- | ----- | --------- | --------------------- | ---------- |
|       | 24       | C=O             | · · · · ·  | lBlS  | 10  5161  | 4  Long Branch Lower  |            |
BeS  BeS  25  3  2  Branch C= 1  · · · · ·  23  or· Same  · · · · ·
· · · · ·
lBCS  10 5161  4  Long Branch  BlT  BlT  2D  3  2  8ranch<Zero
|     | 25  | C=1  | · · · · ·  | lBlT  | 10  5161  | 4  Long 8ranch<Zero  |     |
| --- | --- | ---- | ---------- | ----- | --------- | -------------------- | --- |
BEO  BEO  'n  3  2  Branch Z;:::: 1  · · · · ·  2D  · · · · ·
lBEO  10 5161  4  Long Branch  BMI  BMI  2B  3  2  Branch Minus  · · · · ·
27  Z=1  · · · · ·  lBMI  10  5161  4  Long Branch Minus  · · · · ·
| BGE  BGE  | 2C  | 3  2  Branch O!: Zero  | · · · · ·  |     | 2B  |     |     |
| --------- | --- | ---------------------- | ---------- | --- | --- | --- | --- |
lBGE  10 5161  4  Long Branch i!': Zero·  BNE  BNE  26  3  2  Branch Z"" 0  · · · · ·
|           | 2C  |                     | · · · · ·  | cBNE  | 10  5161  | 4  Long Branch  |            |
| --------- | --- | ------------------- | ---------- | ----- | --------- | --------------- | ---------- |
|           |     |                     | · · · · ·  |       | 26        | Z=O             | · · · · ·  |
| BGT  BGT  | 2E  | 3  2  Branch> Zero  |            |       |           |                 |            |
lBGT  10 5161  4  Long Branch> Zero  BPl  BPl  2A  3  2  Branch Plus  · · · · ·
|     | 2 E   |     | ·   ·   ·  ·   ·   | lBPl  | 1 0  5161  | 4  Long Branch Plus  |     |
| --- | ----- | --- | ------------------ | ----- | ---------- | -------------------- | --- |
f-sHj-'  BHI  2 2  3  2  Branch Higher  ·   ·  ·  ·   ·   2 A   · · · · ·
· · · · ·
lBHI  10 5161  4  Long Branch Higher  BRA  BRA  20  3  2  Branch Always
22  · · · · ·  lBRA  16  5.  3  Long Branch Always  · · · · ·
BHS  BHS  24  3  2  Branch Higher  BRN  BRN  21  3  2  Branch Never  · · · · ·
|       |          | or Same                | · · · · ·  | LBRN  | 10  | 5  4  Long Branch Never  |     |
| ----- | -------- | ---------------------- | ---------- | ----- | --- | ------------------------ | --- |
| lBHS  | 10 5161  | 4  Long Branch Higher  |            |       | 21  |                          |     |
· · · · ·
24  or Same  · · · · ·  BSR  BSR  aD  7  2  Branch to S·ubroutine · · · · ·
BlE  BlE  2F  3  2  Branch:s Zero  · · · · ·  lBSR  17  9  .3  Long Branch to
lBlE  10  5161  4  Long Bran9h:s Zero  Subroutine  · · · · ·
|     | 2F  |     | · · · · ·  |           |     |                   |            |
| --- | --- | --- | ---------- | --------- | --- | ----------------- | ---------- |
|     |     |     |            | BVe  BVC  | 28  | 3  2  Branch V=O  | · · · · ·  |
BlO  BlO  25  3  2  Branch lower  · · · · ·  lBVC  10  5161  4  Long Branch
| lBlO  | 10  5161  | 4  Long Branch Lower  |     |           | 2B        | v=o              | · · · · ·  |
| ----- | --------- | --------------------- | --- | --------- | --------- | ---------------- | ---------- |
|       | 25        |                       |     |           | 29        | 3                | · · ·      |
|       |           |                       |     | BVS  BVS  |           | 2  B.ranch V-1   |            |
|       |           |                       |     | lBVS      | 10  5161  | 4  Lc;mg Branch  | .1.  1     |
29  V=I
SIMPLE BRANCHES
|       |     | OP          |     | SIMPLE CONDITIONAL BRANCHES (Notes 1-41  |       |             |          |
| ----- | --- | ----------- | --- | ---------------------------------------- | ----- | ----------- | -------- |
| BRA   |     | 20  3  2    |     | T8111                                    | True  | OP  F. ...  | OP       |
| LBRA  |     | 16  5  3    |     | N=1                                      | BMI   | 2B          | BPl  2A  |
| BRN   |     | 21  3  2    |     |                                          |       |             |          |
|       |     |             |     | Z=1                                      | BEQ   | 27          | BNE  26  |
| lBRN  |     | 1021  5  4  |     | V=1                                      | BVS   | 29  BVC     | 28       |
| BSA   |     | 80  7  2    |     | C=1                                      | BCS   | 25  BCC     | 24       |
| lBSR  |     | 17  9  3    |     |                                          |       |             |          |
SIGNED CONDITIONAL BRANCHES (Notes 1-4)  UNSIGNED CONDmONAL BRANCHES (Notes 1-41
| T8111  | True  | OP  False  | OP  | T8111  | True  | .OP  False  | OP  |
| ------ | ----- | ---------- | --- | ------ | ----- | ----------- | --- |
| r>m    | BGT   | 2E  BlE    | 2F  | r>m    | BHI   | 22  BlS     | 23  |
|        |       |            |     |        | BHS   | .24  BlO    | 25  |
| r~m    | BGE   | 2C  BlT    | 20  | r~m    |       |             |     |
| .r=m   | BEQ   | 27  BNE    | 26  | r=m    | BEQ   | 27  BNE     | 26  |
| rsm    | BlE   | 2F  BGT    | 2E  | rsm    | BLS   | 23  BHI     | 22  |
| r<m    | BlT   | 20  BGE    | 2C  | r<m    | BlO   | 25  BHS     | 24  |
NOTES:
1.  All condilional branches have both short and long variations.
2.  All short branches are 2 bytes and require 3 cycles.
3.  All conditional long branches are formed by prefixing the short branch opcode with $10 and using a 16-bit destinalion offset.
4.  All conditional long branches require 4 by1~s and 6 cycles if the branch is laken or 5 cycles if the branch is not laken.
5.  5161 means: 5 cycles if branch not taken, 6 cycles if laken.

Me6S09E
INDEXED ADDRESSING MODES
|       |     |     |        |            | Nondirect  |                              | Indirect      |      |
| ----- | --- | --- | ------ | ---------- | ---------- | ---------------------------- | ------------- | ---- |
|       |     |     |        | Assembler  | Post-Byte  | ++ Assembler ,Post-Byte + +  |               |      |
| Type  |     |     | Fonns  | Form       | Opcode     | - #                          | Form  Opcode  |      |
|       |     |     |        |            |            |                              |               | - #  |
Constant Offset From R  No Offset  ,R  lRR00100 a a  L Rl  ..I~ RR10lOO  3 a
|     |     |     | 5-Bit Offset   |       |               | 1 a  |                    |      |
| --- | --- | --- | -------------- | ----- | ------------- | ---- | ------------------ | ---- |
|     |     |     |                | n, R  | ORRnnnnn      |      | defaults to a:bit  |      |
|     |     |     | 8-Bit Offset   | n, R  | 1RROlooo      | 1 1  | in, Rl  lRR11000   | 4 1  |
|     |     |     | 16-Bit Offset  | n, R  | 1RROlool A 2  |      | in, Rl  lRRllool   | 7 2  |
Accumulator Offset From R  A - Register Offset  A, R  1RR00110  1 a  lA, Rl  lRR10ll0  4 a
|     |     |     |                       |       |           | 1 a  |                    | 4 a  |
| --- | --- | --- | --------------------- | ----- | --------- | ---- | ------------------ | ---- |
|     |     |     | B - Register Offset'  | B, R  | lRRool0l  |      | [8, Rl  l11Rl0l0l  |      |
|     |     |     | D - Register Offset   | D, R  | lRR010l1  | 4 a  | [D, Rl  lRRll0ll   | 7 a  |
2 a
Auto I ncrement/Decremenf R  Increment By 1  ,R+  lRROOOOO  not allowed
|     |     |     | Increment By 2  | ,R + +  | lRRooool  | 3 a  L R ++111RRlOOOl  |     | 6 a  |
| --- | --- | --- | --------------- | ------- | --------- | ---------------------- | --- | ---- |
lRRoool0 2 a
|     |     |     | Decrement By 1  | ,-R    |           |      | not allowed        |      |
| --- | --- | --- | --------------- | ------ | --------- | ---- | ------------------ | ---- |
|     |     |     | Decrement By 2  | , --R  | lRRoooll  | 3 a  | [, --Rl  lRRlOOll  | 6 a  |
Constant Offset From PC  8-Bit Offset  n, PCR  lXXOlloo 1 1  in, PCRl  lXXllloo  4 1
|     |     |     | 16-Bit Offset  | n, PCR  | lXXOll01  | 5 2  | [n, PCRl  lXXlll0l  | 8 2  |
| --- | --- | --- | -------------- | ------- | --------- | ---- | ------------------- | ---- |
Extended Indirect  16-Bit Address  - - -- [nl  10011111  5 2
|     |     |     | R -X, Y, U, or S  | RR.oo -X  | 10 -U  |     |     |     |
| --- | --- | --- | ----------------- | --------- | ------ | --- | --- | --- |
|     |     |     | X = Don't Care    | 01=Y      | 11=S   |     |     |     |
INDEXED ADDRESSING POSTBYTE
REGISTER BIT ASSIGNMENTS
Indexed
| Post-Byte Register Bit  |     |     |     | ~~:::::' r}'~o .. ,,,._  |     |     |     |     |
| ----------------------- | --- | --- | --- | ------------------------ | --- | --- | --- | --- |
Addressing
| 7  6  5  4  | 3  2  t  | 0   | Mode  |     |     |     |     |     |
| ----------- | -------- | --- | ----- | --- | --- | --- | --- | --- |
a R
| R  x                | x  x  x  | x  EA  | , R + 5 Bit Offset  |     |     |     |     |     |
| ------------------- | -------- | ------ | ------------------- | --- | --- | --- | --- | --- |
| 1  R  R  a a a a a  |          |        | ,R +                |     |     | I   |     |     |
U - User Stack
| 1  R  R  I  | a a a 1  |     | , II. +  +  |     |                 |     |     |     |
| ----------- | -------- | --- | ----------- | --- | --------------- | --- | --- | --- |
| a a a 1 a   |          |     |             |     |                 | I   |     |     |
| 1  R II.    |          |     | ,-R         |     |                 |     |     |     |
| 1  R  R  I  | a a 1    | 1   | , -- R      | S - | Hardware Stack  |     |     |     |
I
| 1  R  R  I  | a 1  a a   | EA=,R+OOffset             |     |     |     |                  |     |     |
| ----------- | ---------- | ------------------------- | --- | --- | --- | ---------------- | --- | --- |
|             | a 1  a 1   |                           |     |     | PC  | Program Counter  |     |     |
| 1  R  R  I  |            | EA = , R + ACCB Offset    |     |     |     |                  |     |     |
|             | a 1        | a  EA = , R + ACCAOffset  |     |     |     |                  |     |     |
| 1  R  R  I  | 1          |                           |     |     |     | Accumulators     |     |     |
| 1  R  R  I  | 1  0  a a  | EA = ,R+ 8-BitOffset      |     |     |     |                  |     |     |
| 1  R 'R  I  | 1  a a 1   | EA = , R + 16-Bit Offset  |     |     |     |                  |     |     |
a 1
| 1  R  R  I      | 1          | 1  EA= ,11.+ DOffset      |     |     |     |     |     |     |
| --------------- | ---------- | ------------------------- | --- | --- | --- | --- | --- | --- |
| 1r  x  x. .  I  | 1  1  a a  | EA - , PC + 8-Bit Offset  |     |     |     |     |     |     |
Direct Page Register
| 1  x .•  I  | 1  1  a 1  | EA - , PC + 16-Bit Offset  |              |     | DP  |                    |     |     |
| ----------- | ---------- | -------------------------- | ------------ | --- | --- | ------------------ | --- | --- |
| 1  R  R  1  | 1  1  1    | 1  EA -                    | [, Addressl  |     |     | CC-Condition Code  |     |     |
| I  I  I     |            | I                          |              |     |     |                    |     |     |
|             |            | ~ddressing                 |              |     |     | Carry-Borrow       |     |     |
Overflow
| 1...  | . 'r'.  | '.,                        |     |     |     |            |     |     |
| ----- | ------- | -------------------------- | --- | --- | --- | ---------- | --- | --- |
| ".    |         | Indirect FieldM ode Field  |     |     |     | L----Zero  |     |     |
1-____ Negative
ISign bit when b7 = 01
'--'-----IRO Interrupt Mask
|     | .  ."  | . ,. Register Field: RR  |     |                                    | '-------Half Carry             |     |     |     |
| --- | ------ | ------------------------ | --- | ---------------------------------- | ------------------------------ | --- | --- | --- |
|     |        | 00 = X                   |     |                                    | 1-_______ Fast Interrupt Mask  |     |     |     |
|     |        | 01 = Y                   |     | I-----'--~--Entire State on Stack  |                                |     |     |     |
10 = U
| X = Don't Care  |     | 11 = S  |     |     |     |     |     |     |
| --------------- | --- | ------- | --- | --- | --- | --- | --- | --- |

Me6S09E
| Pushl Pull Post Byte  |     |     |     | 6809 Stacking Order  |     |     |
| --------------------- | --- | --- | --- | -------------------- | --- | --- |
Pull Order
CCR
~
|     |     |     | A   |     | CC  |     |
| --- | --- | --- | --- | --- | --- | --- |
'-----B
A
|     |             | L-----DPR     |     |     | B                 |     |
| --- | ----------- | ------------- | --- | --- | ----------------- | --- |
|     |             | '----,..---X  |     |     | DP  6809 Vectors  |     |
|     | '--------Y  |               |     |     | FFFE Restart      |     |
X Hi
|     | '---------S/U  |     |     |     | X Lo  FFFC NMI  |     |
| --- | -------------- | --- | --- | --- | --------------- | --- |
FFFA SWI
| L---~------PC  |      |                  |     |     | Y Hi                  |              |
| -------------- | ---- | ---------------- | --- | --- | --------------------- | ------------ |
|                |      |                  |     |     | Y  L FFF8 IRQ         |              |
| Transfer/E     | x ch | an ge Post Byte  |     |     | o   F F F             | 6   F I RQ   |
|                | I    | I                |     |     | U /S   H i            |              |
| ~ouice         |      | De~tin~tion:     |     |     | F F F                 | 4   S W 12   |
|                |      |                  |     |     | U/S Lo  FFF2 SW13     |              |
|                |      |                  |     |     | PC Hi  FFFO Reserved  |              |
Register Field
PC Lo
| 0000= D IA-BI  |     | 0101 = PC  |     |     | t           |     |
| -------------- | --- | ---------- | --- | --- | ----------- | --- |
| 000l=X         |     | l000=A     |     |     | Push Order  |     |
| 0010=Y         |     | 1001 = B   |     |     |             |     |
~
| OO11=U   |     | 101O=CCR   |     | Increasing Memory  |     |     |
| -------- | --- | ---------- | --- | ------------------ | --- | --- |
| 0100= S  |     | 1011 =DPR  |     |                    |     |     |
ORDERING INFORMATION
|     | Package   |                  | Temperature    |        |               |     |
| --- | --------- | ---------------- | -------------- | ------ | ------------- | --- |
|     |           | Type  Frequency  |                | Range  | Order Number  |     |
|     | Ceramic   | 1.0 MHz          | O°C to lO°C    |        | MC6809EL      |     |
|     | L Suffix  | 1.0 MHz          | -40°C to 85°C  |        | MC6809ECL     |     |
|     |           | 1.5 MHz          | O°C to lO°C    |        | MC6BA09EL     |     |
|     |           | 1.5 MHz          | -40°C to 85°C  |        | MC6BA09ECL    |     |
|     |           | 2.0 MHz          | OOC to lOoC    |        | MC6BB09EL     |     |
|     |           | 2.0 MHz          | -40°C to 85°C  |        | MC6BB09ECL    |     |
|     | Plastic   | 1.0 MHz          | O°C to lO°C    |        | MC6809EP      |     |
|     | P Suffix  | 1.0 MHz          | -40°C to B5°C  |        | MC6B09ECP     |     |
|     |           | 1.5 MHz          | OOC to lO°C    |        | MC6BA09EP     |     |
|     |           | 1.5 MHz          | -40°C to 85°C  |        | MC6BA09ECP    |     |
|     |           | 2.0 MHz          | OOC to lOoC    |        | MC6BB09EP     |     |
|     |           | 2.0 MHz          | -40°C to B5°C  |        | MC6BB09ECP    |     |
|     | Cerdip    | 1.0 MHz          | OOC to lO°C    |        | MC6809ES      |     |
|     | S Suffix  | 1.0 MHz          | -40°C to 85°C  |        | MC6809ECS     |     |
|     |           | 1.5 MHz          | OOC to lO°C    |        | MC6BA09ES     |     |
|     |           | 1.5 MHz          | -40°C to B5°C  |        | MC6BA09ECS    |     |
|     |           | 2.0 MHz          | OOC to lO°C    |        | MC6BB09ES     |     |
|     |           | 2.0 MHz          | -40°C to 85°C  |        | MC6BB09ECS    |     |