text stringlengths 1 1.05M |
|---|
lda {m1}
cmp {m2}
bne !+
lda {m1}+1
cmp {m2}+1
beq {la1}
!:
|
_ln: file format elf64-x86-64
Disassembly of section .text:
0000000000001000 <main>:
#include "stat.h"
#include "user.h"
int
main(int argc, char *argv[])
{
1000: f3 0f 1e fa endbr64
1004: 55 push %rbp
1005: 48 89 e5 mov %rsp,%rbp
1008: 48 83 ec 10 sub $0x10,%rsp
100c: 89 7d fc mov %edi,-0x4(%rbp)
100f: 48 89 75 f0 mov %rsi,-0x10(%rbp)
if(argc != 3){
1013: 83 7d fc 03 cmpl $0x3,-0x4(%rbp)
1017: 74 2c je 1045 <main+0x45>
printf(2, "Usage: ln old new\n");
1019: 48 be 08 1e 00 00 00 movabs $0x1e08,%rsi
1020: 00 00 00
1023: bf 02 00 00 00 mov $0x2,%edi
1028: b8 00 00 00 00 mov $0x0,%eax
102d: 48 ba f4 16 00 00 00 movabs $0x16f4,%rdx
1034: 00 00 00
1037: ff d2 callq *%rdx
exit();
1039: 48 b8 fd 13 00 00 00 movabs $0x13fd,%rax
1040: 00 00 00
1043: ff d0 callq *%rax
}
if(link(argv[1], argv[2]) < 0)
1045: 48 8b 45 f0 mov -0x10(%rbp),%rax
1049: 48 83 c0 10 add $0x10,%rax
104d: 48 8b 10 mov (%rax),%rdx
1050: 48 8b 45 f0 mov -0x10(%rbp),%rax
1054: 48 83 c0 08 add $0x8,%rax
1058: 48 8b 00 mov (%rax),%rax
105b: 48 89 d6 mov %rdx,%rsi
105e: 48 89 c7 mov %rax,%rdi
1061: 48 b8 99 14 00 00 00 movabs $0x1499,%rax
1068: 00 00 00
106b: ff d0 callq *%rax
106d: 85 c0 test %eax,%eax
106f: 79 3d jns 10ae <main+0xae>
printf(2, "link %s %s: failed\n", argv[1], argv[2]);
1071: 48 8b 45 f0 mov -0x10(%rbp),%rax
1075: 48 83 c0 10 add $0x10,%rax
1079: 48 8b 10 mov (%rax),%rdx
107c: 48 8b 45 f0 mov -0x10(%rbp),%rax
1080: 48 83 c0 08 add $0x8,%rax
1084: 48 8b 00 mov (%rax),%rax
1087: 48 89 d1 mov %rdx,%rcx
108a: 48 89 c2 mov %rax,%rdx
108d: 48 be 1b 1e 00 00 00 movabs $0x1e1b,%rsi
1094: 00 00 00
1097: bf 02 00 00 00 mov $0x2,%edi
109c: b8 00 00 00 00 mov $0x0,%eax
10a1: 49 b8 f4 16 00 00 00 movabs $0x16f4,%r8
10a8: 00 00 00
10ab: 41 ff d0 callq *%r8
exit();
10ae: 48 b8 fd 13 00 00 00 movabs $0x13fd,%rax
10b5: 00 00 00
10b8: ff d0 callq *%rax
00000000000010ba <stosb>:
"cc");
}
static inline void
stosb(void *addr, int data, int cnt)
{
10ba: f3 0f 1e fa endbr64
10be: 55 push %rbp
10bf: 48 89 e5 mov %rsp,%rbp
10c2: 48 83 ec 10 sub $0x10,%rsp
10c6: 48 89 7d f8 mov %rdi,-0x8(%rbp)
10ca: 89 75 f4 mov %esi,-0xc(%rbp)
10cd: 89 55 f0 mov %edx,-0x10(%rbp)
asm volatile("cld; rep stosb" :
10d0: 48 8b 4d f8 mov -0x8(%rbp),%rcx
10d4: 8b 55 f0 mov -0x10(%rbp),%edx
10d7: 8b 45 f4 mov -0xc(%rbp),%eax
10da: 48 89 ce mov %rcx,%rsi
10dd: 48 89 f7 mov %rsi,%rdi
10e0: 89 d1 mov %edx,%ecx
10e2: fc cld
10e3: f3 aa rep stos %al,%es:(%rdi)
10e5: 89 ca mov %ecx,%edx
10e7: 48 89 fe mov %rdi,%rsi
10ea: 48 89 75 f8 mov %rsi,-0x8(%rbp)
10ee: 89 55 f0 mov %edx,-0x10(%rbp)
"=D" (addr), "=c" (cnt) :
"0" (addr), "1" (cnt), "a" (data) :
"memory", "cc");
}
10f1: 90 nop
10f2: c9 leaveq
10f3: c3 retq
00000000000010f4 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, char *t)
{
10f4: f3 0f 1e fa endbr64
10f8: 55 push %rbp
10f9: 48 89 e5 mov %rsp,%rbp
10fc: 48 83 ec 20 sub $0x20,%rsp
1100: 48 89 7d e8 mov %rdi,-0x18(%rbp)
1104: 48 89 75 e0 mov %rsi,-0x20(%rbp)
char *os;
os = s;
1108: 48 8b 45 e8 mov -0x18(%rbp),%rax
110c: 48 89 45 f8 mov %rax,-0x8(%rbp)
while((*s++ = *t++) != 0)
1110: 90 nop
1111: 48 8b 55 e0 mov -0x20(%rbp),%rdx
1115: 48 8d 42 01 lea 0x1(%rdx),%rax
1119: 48 89 45 e0 mov %rax,-0x20(%rbp)
111d: 48 8b 45 e8 mov -0x18(%rbp),%rax
1121: 48 8d 48 01 lea 0x1(%rax),%rcx
1125: 48 89 4d e8 mov %rcx,-0x18(%rbp)
1129: 0f b6 12 movzbl (%rdx),%edx
112c: 88 10 mov %dl,(%rax)
112e: 0f b6 00 movzbl (%rax),%eax
1131: 84 c0 test %al,%al
1133: 75 dc jne 1111 <strcpy+0x1d>
;
return os;
1135: 48 8b 45 f8 mov -0x8(%rbp),%rax
}
1139: c9 leaveq
113a: c3 retq
000000000000113b <strcmp>:
int
strcmp(const char *p, const char *q)
{
113b: f3 0f 1e fa endbr64
113f: 55 push %rbp
1140: 48 89 e5 mov %rsp,%rbp
1143: 48 83 ec 10 sub $0x10,%rsp
1147: 48 89 7d f8 mov %rdi,-0x8(%rbp)
114b: 48 89 75 f0 mov %rsi,-0x10(%rbp)
while(*p && *p == *q)
114f: eb 0a jmp 115b <strcmp+0x20>
p++, q++;
1151: 48 83 45 f8 01 addq $0x1,-0x8(%rbp)
1156: 48 83 45 f0 01 addq $0x1,-0x10(%rbp)
while(*p && *p == *q)
115b: 48 8b 45 f8 mov -0x8(%rbp),%rax
115f: 0f b6 00 movzbl (%rax),%eax
1162: 84 c0 test %al,%al
1164: 74 12 je 1178 <strcmp+0x3d>
1166: 48 8b 45 f8 mov -0x8(%rbp),%rax
116a: 0f b6 10 movzbl (%rax),%edx
116d: 48 8b 45 f0 mov -0x10(%rbp),%rax
1171: 0f b6 00 movzbl (%rax),%eax
1174: 38 c2 cmp %al,%dl
1176: 74 d9 je 1151 <strcmp+0x16>
return (uchar)*p - (uchar)*q;
1178: 48 8b 45 f8 mov -0x8(%rbp),%rax
117c: 0f b6 00 movzbl (%rax),%eax
117f: 0f b6 d0 movzbl %al,%edx
1182: 48 8b 45 f0 mov -0x10(%rbp),%rax
1186: 0f b6 00 movzbl (%rax),%eax
1189: 0f b6 c0 movzbl %al,%eax
118c: 29 c2 sub %eax,%edx
118e: 89 d0 mov %edx,%eax
}
1190: c9 leaveq
1191: c3 retq
0000000000001192 <strlen>:
uint
strlen(char *s)
{
1192: f3 0f 1e fa endbr64
1196: 55 push %rbp
1197: 48 89 e5 mov %rsp,%rbp
119a: 48 83 ec 18 sub $0x18,%rsp
119e: 48 89 7d e8 mov %rdi,-0x18(%rbp)
int n;
for(n = 0; s[n]; n++)
11a2: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%rbp)
11a9: eb 04 jmp 11af <strlen+0x1d>
11ab: 83 45 fc 01 addl $0x1,-0x4(%rbp)
11af: 8b 45 fc mov -0x4(%rbp),%eax
11b2: 48 63 d0 movslq %eax,%rdx
11b5: 48 8b 45 e8 mov -0x18(%rbp),%rax
11b9: 48 01 d0 add %rdx,%rax
11bc: 0f b6 00 movzbl (%rax),%eax
11bf: 84 c0 test %al,%al
11c1: 75 e8 jne 11ab <strlen+0x19>
;
return n;
11c3: 8b 45 fc mov -0x4(%rbp),%eax
}
11c6: c9 leaveq
11c7: c3 retq
00000000000011c8 <memset>:
void*
memset(void *dst, int c, uint n)
{
11c8: f3 0f 1e fa endbr64
11cc: 55 push %rbp
11cd: 48 89 e5 mov %rsp,%rbp
11d0: 48 83 ec 10 sub $0x10,%rsp
11d4: 48 89 7d f8 mov %rdi,-0x8(%rbp)
11d8: 89 75 f4 mov %esi,-0xc(%rbp)
11db: 89 55 f0 mov %edx,-0x10(%rbp)
stosb(dst, c, n);
11de: 8b 55 f0 mov -0x10(%rbp),%edx
11e1: 8b 4d f4 mov -0xc(%rbp),%ecx
11e4: 48 8b 45 f8 mov -0x8(%rbp),%rax
11e8: 89 ce mov %ecx,%esi
11ea: 48 89 c7 mov %rax,%rdi
11ed: 48 b8 ba 10 00 00 00 movabs $0x10ba,%rax
11f4: 00 00 00
11f7: ff d0 callq *%rax
return dst;
11f9: 48 8b 45 f8 mov -0x8(%rbp),%rax
}
11fd: c9 leaveq
11fe: c3 retq
00000000000011ff <strchr>:
char*
strchr(const char *s, char c)
{
11ff: f3 0f 1e fa endbr64
1203: 55 push %rbp
1204: 48 89 e5 mov %rsp,%rbp
1207: 48 83 ec 10 sub $0x10,%rsp
120b: 48 89 7d f8 mov %rdi,-0x8(%rbp)
120f: 89 f0 mov %esi,%eax
1211: 88 45 f4 mov %al,-0xc(%rbp)
for(; *s; s++)
1214: eb 17 jmp 122d <strchr+0x2e>
if(*s == c)
1216: 48 8b 45 f8 mov -0x8(%rbp),%rax
121a: 0f b6 00 movzbl (%rax),%eax
121d: 38 45 f4 cmp %al,-0xc(%rbp)
1220: 75 06 jne 1228 <strchr+0x29>
return (char*)s;
1222: 48 8b 45 f8 mov -0x8(%rbp),%rax
1226: eb 15 jmp 123d <strchr+0x3e>
for(; *s; s++)
1228: 48 83 45 f8 01 addq $0x1,-0x8(%rbp)
122d: 48 8b 45 f8 mov -0x8(%rbp),%rax
1231: 0f b6 00 movzbl (%rax),%eax
1234: 84 c0 test %al,%al
1236: 75 de jne 1216 <strchr+0x17>
return 0;
1238: b8 00 00 00 00 mov $0x0,%eax
}
123d: c9 leaveq
123e: c3 retq
000000000000123f <gets>:
char*
gets(char *buf, int max)
{
123f: f3 0f 1e fa endbr64
1243: 55 push %rbp
1244: 48 89 e5 mov %rsp,%rbp
1247: 48 83 ec 20 sub $0x20,%rsp
124b: 48 89 7d e8 mov %rdi,-0x18(%rbp)
124f: 89 75 e4 mov %esi,-0x1c(%rbp)
int i, cc;
char c;
for(i=0; i+1 < max; ){
1252: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%rbp)
1259: eb 4f jmp 12aa <gets+0x6b>
cc = read(0, &c, 1);
125b: 48 8d 45 f7 lea -0x9(%rbp),%rax
125f: ba 01 00 00 00 mov $0x1,%edx
1264: 48 89 c6 mov %rax,%rsi
1267: bf 00 00 00 00 mov $0x0,%edi
126c: 48 b8 24 14 00 00 00 movabs $0x1424,%rax
1273: 00 00 00
1276: ff d0 callq *%rax
1278: 89 45 f8 mov %eax,-0x8(%rbp)
if(cc < 1)
127b: 83 7d f8 00 cmpl $0x0,-0x8(%rbp)
127f: 7e 36 jle 12b7 <gets+0x78>
break;
buf[i++] = c;
1281: 8b 45 fc mov -0x4(%rbp),%eax
1284: 8d 50 01 lea 0x1(%rax),%edx
1287: 89 55 fc mov %edx,-0x4(%rbp)
128a: 48 63 d0 movslq %eax,%rdx
128d: 48 8b 45 e8 mov -0x18(%rbp),%rax
1291: 48 01 c2 add %rax,%rdx
1294: 0f b6 45 f7 movzbl -0x9(%rbp),%eax
1298: 88 02 mov %al,(%rdx)
if(c == '\n' || c == '\r')
129a: 0f b6 45 f7 movzbl -0x9(%rbp),%eax
129e: 3c 0a cmp $0xa,%al
12a0: 74 16 je 12b8 <gets+0x79>
12a2: 0f b6 45 f7 movzbl -0x9(%rbp),%eax
12a6: 3c 0d cmp $0xd,%al
12a8: 74 0e je 12b8 <gets+0x79>
for(i=0; i+1 < max; ){
12aa: 8b 45 fc mov -0x4(%rbp),%eax
12ad: 83 c0 01 add $0x1,%eax
12b0: 39 45 e4 cmp %eax,-0x1c(%rbp)
12b3: 7f a6 jg 125b <gets+0x1c>
12b5: eb 01 jmp 12b8 <gets+0x79>
break;
12b7: 90 nop
break;
}
buf[i] = '\0';
12b8: 8b 45 fc mov -0x4(%rbp),%eax
12bb: 48 63 d0 movslq %eax,%rdx
12be: 48 8b 45 e8 mov -0x18(%rbp),%rax
12c2: 48 01 d0 add %rdx,%rax
12c5: c6 00 00 movb $0x0,(%rax)
return buf;
12c8: 48 8b 45 e8 mov -0x18(%rbp),%rax
}
12cc: c9 leaveq
12cd: c3 retq
00000000000012ce <stat>:
int
stat(char *n, struct stat *st)
{
12ce: f3 0f 1e fa endbr64
12d2: 55 push %rbp
12d3: 48 89 e5 mov %rsp,%rbp
12d6: 48 83 ec 20 sub $0x20,%rsp
12da: 48 89 7d e8 mov %rdi,-0x18(%rbp)
12de: 48 89 75 e0 mov %rsi,-0x20(%rbp)
int fd;
int r;
fd = open(n, O_RDONLY);
12e2: 48 8b 45 e8 mov -0x18(%rbp),%rax
12e6: be 00 00 00 00 mov $0x0,%esi
12eb: 48 89 c7 mov %rax,%rdi
12ee: 48 b8 65 14 00 00 00 movabs $0x1465,%rax
12f5: 00 00 00
12f8: ff d0 callq *%rax
12fa: 89 45 fc mov %eax,-0x4(%rbp)
if(fd < 0)
12fd: 83 7d fc 00 cmpl $0x0,-0x4(%rbp)
1301: 79 07 jns 130a <stat+0x3c>
return -1;
1303: b8 ff ff ff ff mov $0xffffffff,%eax
1308: eb 2f jmp 1339 <stat+0x6b>
r = fstat(fd, st);
130a: 48 8b 55 e0 mov -0x20(%rbp),%rdx
130e: 8b 45 fc mov -0x4(%rbp),%eax
1311: 48 89 d6 mov %rdx,%rsi
1314: 89 c7 mov %eax,%edi
1316: 48 b8 8c 14 00 00 00 movabs $0x148c,%rax
131d: 00 00 00
1320: ff d0 callq *%rax
1322: 89 45 f8 mov %eax,-0x8(%rbp)
close(fd);
1325: 8b 45 fc mov -0x4(%rbp),%eax
1328: 89 c7 mov %eax,%edi
132a: 48 b8 3e 14 00 00 00 movabs $0x143e,%rax
1331: 00 00 00
1334: ff d0 callq *%rax
return r;
1336: 8b 45 f8 mov -0x8(%rbp),%eax
}
1339: c9 leaveq
133a: c3 retq
000000000000133b <atoi>:
int
atoi(const char *s)
{
133b: f3 0f 1e fa endbr64
133f: 55 push %rbp
1340: 48 89 e5 mov %rsp,%rbp
1343: 48 83 ec 18 sub $0x18,%rsp
1347: 48 89 7d e8 mov %rdi,-0x18(%rbp)
int n;
n = 0;
134b: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%rbp)
while('0' <= *s && *s <= '9')
1352: eb 28 jmp 137c <atoi+0x41>
n = n*10 + *s++ - '0';
1354: 8b 55 fc mov -0x4(%rbp),%edx
1357: 89 d0 mov %edx,%eax
1359: c1 e0 02 shl $0x2,%eax
135c: 01 d0 add %edx,%eax
135e: 01 c0 add %eax,%eax
1360: 89 c1 mov %eax,%ecx
1362: 48 8b 45 e8 mov -0x18(%rbp),%rax
1366: 48 8d 50 01 lea 0x1(%rax),%rdx
136a: 48 89 55 e8 mov %rdx,-0x18(%rbp)
136e: 0f b6 00 movzbl (%rax),%eax
1371: 0f be c0 movsbl %al,%eax
1374: 01 c8 add %ecx,%eax
1376: 83 e8 30 sub $0x30,%eax
1379: 89 45 fc mov %eax,-0x4(%rbp)
while('0' <= *s && *s <= '9')
137c: 48 8b 45 e8 mov -0x18(%rbp),%rax
1380: 0f b6 00 movzbl (%rax),%eax
1383: 3c 2f cmp $0x2f,%al
1385: 7e 0b jle 1392 <atoi+0x57>
1387: 48 8b 45 e8 mov -0x18(%rbp),%rax
138b: 0f b6 00 movzbl (%rax),%eax
138e: 3c 39 cmp $0x39,%al
1390: 7e c2 jle 1354 <atoi+0x19>
return n;
1392: 8b 45 fc mov -0x4(%rbp),%eax
}
1395: c9 leaveq
1396: c3 retq
0000000000001397 <memmove>:
void*
memmove(void *vdst, void *vsrc, int n)
{
1397: f3 0f 1e fa endbr64
139b: 55 push %rbp
139c: 48 89 e5 mov %rsp,%rbp
139f: 48 83 ec 28 sub $0x28,%rsp
13a3: 48 89 7d e8 mov %rdi,-0x18(%rbp)
13a7: 48 89 75 e0 mov %rsi,-0x20(%rbp)
13ab: 89 55 dc mov %edx,-0x24(%rbp)
char *dst, *src;
dst = vdst;
13ae: 48 8b 45 e8 mov -0x18(%rbp),%rax
13b2: 48 89 45 f8 mov %rax,-0x8(%rbp)
src = vsrc;
13b6: 48 8b 45 e0 mov -0x20(%rbp),%rax
13ba: 48 89 45 f0 mov %rax,-0x10(%rbp)
while(n-- > 0)
13be: eb 1d jmp 13dd <memmove+0x46>
*dst++ = *src++;
13c0: 48 8b 55 f0 mov -0x10(%rbp),%rdx
13c4: 48 8d 42 01 lea 0x1(%rdx),%rax
13c8: 48 89 45 f0 mov %rax,-0x10(%rbp)
13cc: 48 8b 45 f8 mov -0x8(%rbp),%rax
13d0: 48 8d 48 01 lea 0x1(%rax),%rcx
13d4: 48 89 4d f8 mov %rcx,-0x8(%rbp)
13d8: 0f b6 12 movzbl (%rdx),%edx
13db: 88 10 mov %dl,(%rax)
while(n-- > 0)
13dd: 8b 45 dc mov -0x24(%rbp),%eax
13e0: 8d 50 ff lea -0x1(%rax),%edx
13e3: 89 55 dc mov %edx,-0x24(%rbp)
13e6: 85 c0 test %eax,%eax
13e8: 7f d6 jg 13c0 <memmove+0x29>
return vdst;
13ea: 48 8b 45 e8 mov -0x18(%rbp),%rax
}
13ee: c9 leaveq
13ef: c3 retq
00000000000013f0 <fork>:
mov $SYS_ ## name, %rax; \
mov %rcx, %r10 ;\
syscall ;\
ret
SYSCALL(fork)
13f0: 48 c7 c0 01 00 00 00 mov $0x1,%rax
13f7: 49 89 ca mov %rcx,%r10
13fa: 0f 05 syscall
13fc: c3 retq
00000000000013fd <exit>:
SYSCALL(exit)
13fd: 48 c7 c0 02 00 00 00 mov $0x2,%rax
1404: 49 89 ca mov %rcx,%r10
1407: 0f 05 syscall
1409: c3 retq
000000000000140a <wait>:
SYSCALL(wait)
140a: 48 c7 c0 03 00 00 00 mov $0x3,%rax
1411: 49 89 ca mov %rcx,%r10
1414: 0f 05 syscall
1416: c3 retq
0000000000001417 <pipe>:
SYSCALL(pipe)
1417: 48 c7 c0 04 00 00 00 mov $0x4,%rax
141e: 49 89 ca mov %rcx,%r10
1421: 0f 05 syscall
1423: c3 retq
0000000000001424 <read>:
SYSCALL(read)
1424: 48 c7 c0 05 00 00 00 mov $0x5,%rax
142b: 49 89 ca mov %rcx,%r10
142e: 0f 05 syscall
1430: c3 retq
0000000000001431 <write>:
SYSCALL(write)
1431: 48 c7 c0 10 00 00 00 mov $0x10,%rax
1438: 49 89 ca mov %rcx,%r10
143b: 0f 05 syscall
143d: c3 retq
000000000000143e <close>:
SYSCALL(close)
143e: 48 c7 c0 15 00 00 00 mov $0x15,%rax
1445: 49 89 ca mov %rcx,%r10
1448: 0f 05 syscall
144a: c3 retq
000000000000144b <kill>:
SYSCALL(kill)
144b: 48 c7 c0 06 00 00 00 mov $0x6,%rax
1452: 49 89 ca mov %rcx,%r10
1455: 0f 05 syscall
1457: c3 retq
0000000000001458 <exec>:
SYSCALL(exec)
1458: 48 c7 c0 07 00 00 00 mov $0x7,%rax
145f: 49 89 ca mov %rcx,%r10
1462: 0f 05 syscall
1464: c3 retq
0000000000001465 <open>:
SYSCALL(open)
1465: 48 c7 c0 0f 00 00 00 mov $0xf,%rax
146c: 49 89 ca mov %rcx,%r10
146f: 0f 05 syscall
1471: c3 retq
0000000000001472 <mknod>:
SYSCALL(mknod)
1472: 48 c7 c0 11 00 00 00 mov $0x11,%rax
1479: 49 89 ca mov %rcx,%r10
147c: 0f 05 syscall
147e: c3 retq
000000000000147f <unlink>:
SYSCALL(unlink)
147f: 48 c7 c0 12 00 00 00 mov $0x12,%rax
1486: 49 89 ca mov %rcx,%r10
1489: 0f 05 syscall
148b: c3 retq
000000000000148c <fstat>:
SYSCALL(fstat)
148c: 48 c7 c0 08 00 00 00 mov $0x8,%rax
1493: 49 89 ca mov %rcx,%r10
1496: 0f 05 syscall
1498: c3 retq
0000000000001499 <link>:
SYSCALL(link)
1499: 48 c7 c0 13 00 00 00 mov $0x13,%rax
14a0: 49 89 ca mov %rcx,%r10
14a3: 0f 05 syscall
14a5: c3 retq
00000000000014a6 <mkdir>:
SYSCALL(mkdir)
14a6: 48 c7 c0 14 00 00 00 mov $0x14,%rax
14ad: 49 89 ca mov %rcx,%r10
14b0: 0f 05 syscall
14b2: c3 retq
00000000000014b3 <chdir>:
SYSCALL(chdir)
14b3: 48 c7 c0 09 00 00 00 mov $0x9,%rax
14ba: 49 89 ca mov %rcx,%r10
14bd: 0f 05 syscall
14bf: c3 retq
00000000000014c0 <dup>:
SYSCALL(dup)
14c0: 48 c7 c0 0a 00 00 00 mov $0xa,%rax
14c7: 49 89 ca mov %rcx,%r10
14ca: 0f 05 syscall
14cc: c3 retq
00000000000014cd <getpid>:
SYSCALL(getpid)
14cd: 48 c7 c0 0b 00 00 00 mov $0xb,%rax
14d4: 49 89 ca mov %rcx,%r10
14d7: 0f 05 syscall
14d9: c3 retq
00000000000014da <sbrk>:
SYSCALL(sbrk)
14da: 48 c7 c0 0c 00 00 00 mov $0xc,%rax
14e1: 49 89 ca mov %rcx,%r10
14e4: 0f 05 syscall
14e6: c3 retq
00000000000014e7 <sleep>:
SYSCALL(sleep)
14e7: 48 c7 c0 0d 00 00 00 mov $0xd,%rax
14ee: 49 89 ca mov %rcx,%r10
14f1: 0f 05 syscall
14f3: c3 retq
00000000000014f4 <uptime>:
SYSCALL(uptime)
14f4: 48 c7 c0 0e 00 00 00 mov $0xe,%rax
14fb: 49 89 ca mov %rcx,%r10
14fe: 0f 05 syscall
1500: c3 retq
0000000000001501 <aread>:
SYSCALL(aread)
1501: 48 c7 c0 16 00 00 00 mov $0x16,%rax
1508: 49 89 ca mov %rcx,%r10
150b: 0f 05 syscall
150d: c3 retq
000000000000150e <putc>:
#include <stdarg.h>
static void
putc(int fd, char c)
{
150e: f3 0f 1e fa endbr64
1512: 55 push %rbp
1513: 48 89 e5 mov %rsp,%rbp
1516: 48 83 ec 10 sub $0x10,%rsp
151a: 89 7d fc mov %edi,-0x4(%rbp)
151d: 89 f0 mov %esi,%eax
151f: 88 45 f8 mov %al,-0x8(%rbp)
write(fd, &c, 1);
1522: 48 8d 4d f8 lea -0x8(%rbp),%rcx
1526: 8b 45 fc mov -0x4(%rbp),%eax
1529: ba 01 00 00 00 mov $0x1,%edx
152e: 48 89 ce mov %rcx,%rsi
1531: 89 c7 mov %eax,%edi
1533: 48 b8 31 14 00 00 00 movabs $0x1431,%rax
153a: 00 00 00
153d: ff d0 callq *%rax
}
153f: 90 nop
1540: c9 leaveq
1541: c3 retq
0000000000001542 <print_x64>:
static char digits[] = "0123456789abcdef";
static void
print_x64(int fd, addr_t x)
{
1542: f3 0f 1e fa endbr64
1546: 55 push %rbp
1547: 48 89 e5 mov %rsp,%rbp
154a: 48 83 ec 20 sub $0x20,%rsp
154e: 89 7d ec mov %edi,-0x14(%rbp)
1551: 48 89 75 e0 mov %rsi,-0x20(%rbp)
int i;
for (i = 0; i < (sizeof(addr_t) * 2); i++, x <<= 4)
1555: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%rbp)
155c: eb 35 jmp 1593 <print_x64+0x51>
putc(fd, digits[x >> (sizeof(addr_t) * 8 - 4)]);
155e: 48 8b 45 e0 mov -0x20(%rbp),%rax
1562: 48 c1 e8 3c shr $0x3c,%rax
1566: 48 ba 60 21 00 00 00 movabs $0x2160,%rdx
156d: 00 00 00
1570: 0f b6 04 02 movzbl (%rdx,%rax,1),%eax
1574: 0f be d0 movsbl %al,%edx
1577: 8b 45 ec mov -0x14(%rbp),%eax
157a: 89 d6 mov %edx,%esi
157c: 89 c7 mov %eax,%edi
157e: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
1585: 00 00 00
1588: ff d0 callq *%rax
for (i = 0; i < (sizeof(addr_t) * 2); i++, x <<= 4)
158a: 83 45 fc 01 addl $0x1,-0x4(%rbp)
158e: 48 c1 65 e0 04 shlq $0x4,-0x20(%rbp)
1593: 8b 45 fc mov -0x4(%rbp),%eax
1596: 83 f8 0f cmp $0xf,%eax
1599: 76 c3 jbe 155e <print_x64+0x1c>
}
159b: 90 nop
159c: 90 nop
159d: c9 leaveq
159e: c3 retq
000000000000159f <print_x32>:
static void
print_x32(int fd, uint x)
{
159f: f3 0f 1e fa endbr64
15a3: 55 push %rbp
15a4: 48 89 e5 mov %rsp,%rbp
15a7: 48 83 ec 20 sub $0x20,%rsp
15ab: 89 7d ec mov %edi,-0x14(%rbp)
15ae: 89 75 e8 mov %esi,-0x18(%rbp)
int i;
for (i = 0; i < (sizeof(uint) * 2); i++, x <<= 4)
15b1: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%rbp)
15b8: eb 36 jmp 15f0 <print_x32+0x51>
putc(fd, digits[x >> (sizeof(uint) * 8 - 4)]);
15ba: 8b 45 e8 mov -0x18(%rbp),%eax
15bd: c1 e8 1c shr $0x1c,%eax
15c0: 89 c2 mov %eax,%edx
15c2: 48 b8 60 21 00 00 00 movabs $0x2160,%rax
15c9: 00 00 00
15cc: 89 d2 mov %edx,%edx
15ce: 0f b6 04 10 movzbl (%rax,%rdx,1),%eax
15d2: 0f be d0 movsbl %al,%edx
15d5: 8b 45 ec mov -0x14(%rbp),%eax
15d8: 89 d6 mov %edx,%esi
15da: 89 c7 mov %eax,%edi
15dc: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
15e3: 00 00 00
15e6: ff d0 callq *%rax
for (i = 0; i < (sizeof(uint) * 2); i++, x <<= 4)
15e8: 83 45 fc 01 addl $0x1,-0x4(%rbp)
15ec: c1 65 e8 04 shll $0x4,-0x18(%rbp)
15f0: 8b 45 fc mov -0x4(%rbp),%eax
15f3: 83 f8 07 cmp $0x7,%eax
15f6: 76 c2 jbe 15ba <print_x32+0x1b>
}
15f8: 90 nop
15f9: 90 nop
15fa: c9 leaveq
15fb: c3 retq
00000000000015fc <print_d>:
static void
print_d(int fd, int v)
{
15fc: f3 0f 1e fa endbr64
1600: 55 push %rbp
1601: 48 89 e5 mov %rsp,%rbp
1604: 48 83 ec 30 sub $0x30,%rsp
1608: 89 7d dc mov %edi,-0x24(%rbp)
160b: 89 75 d8 mov %esi,-0x28(%rbp)
char buf[16];
int64 x = v;
160e: 8b 45 d8 mov -0x28(%rbp),%eax
1611: 48 98 cltq
1613: 48 89 45 f8 mov %rax,-0x8(%rbp)
if (v < 0)
1617: 83 7d d8 00 cmpl $0x0,-0x28(%rbp)
161b: 79 04 jns 1621 <print_d+0x25>
x = -x;
161d: 48 f7 5d f8 negq -0x8(%rbp)
int i = 0;
1621: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%rbp)
do {
buf[i++] = digits[x % 10];
1628: 48 8b 4d f8 mov -0x8(%rbp),%rcx
162c: 48 ba 67 66 66 66 66 movabs $0x6666666666666667,%rdx
1633: 66 66 66
1636: 48 89 c8 mov %rcx,%rax
1639: 48 f7 ea imul %rdx
163c: 48 c1 fa 02 sar $0x2,%rdx
1640: 48 89 c8 mov %rcx,%rax
1643: 48 c1 f8 3f sar $0x3f,%rax
1647: 48 29 c2 sub %rax,%rdx
164a: 48 89 d0 mov %rdx,%rax
164d: 48 c1 e0 02 shl $0x2,%rax
1651: 48 01 d0 add %rdx,%rax
1654: 48 01 c0 add %rax,%rax
1657: 48 29 c1 sub %rax,%rcx
165a: 48 89 ca mov %rcx,%rdx
165d: 8b 45 f4 mov -0xc(%rbp),%eax
1660: 8d 48 01 lea 0x1(%rax),%ecx
1663: 89 4d f4 mov %ecx,-0xc(%rbp)
1666: 48 b9 60 21 00 00 00 movabs $0x2160,%rcx
166d: 00 00 00
1670: 0f b6 14 11 movzbl (%rcx,%rdx,1),%edx
1674: 48 98 cltq
1676: 88 54 05 e0 mov %dl,-0x20(%rbp,%rax,1)
x /= 10;
167a: 48 8b 4d f8 mov -0x8(%rbp),%rcx
167e: 48 ba 67 66 66 66 66 movabs $0x6666666666666667,%rdx
1685: 66 66 66
1688: 48 89 c8 mov %rcx,%rax
168b: 48 f7 ea imul %rdx
168e: 48 c1 fa 02 sar $0x2,%rdx
1692: 48 89 c8 mov %rcx,%rax
1695: 48 c1 f8 3f sar $0x3f,%rax
1699: 48 29 c2 sub %rax,%rdx
169c: 48 89 d0 mov %rdx,%rax
169f: 48 89 45 f8 mov %rax,-0x8(%rbp)
} while(x != 0);
16a3: 48 83 7d f8 00 cmpq $0x0,-0x8(%rbp)
16a8: 0f 85 7a ff ff ff jne 1628 <print_d+0x2c>
if (v < 0)
16ae: 83 7d d8 00 cmpl $0x0,-0x28(%rbp)
16b2: 79 32 jns 16e6 <print_d+0xea>
buf[i++] = '-';
16b4: 8b 45 f4 mov -0xc(%rbp),%eax
16b7: 8d 50 01 lea 0x1(%rax),%edx
16ba: 89 55 f4 mov %edx,-0xc(%rbp)
16bd: 48 98 cltq
16bf: c6 44 05 e0 2d movb $0x2d,-0x20(%rbp,%rax,1)
while (--i >= 0)
16c4: eb 20 jmp 16e6 <print_d+0xea>
putc(fd, buf[i]);
16c6: 8b 45 f4 mov -0xc(%rbp),%eax
16c9: 48 98 cltq
16cb: 0f b6 44 05 e0 movzbl -0x20(%rbp,%rax,1),%eax
16d0: 0f be d0 movsbl %al,%edx
16d3: 8b 45 dc mov -0x24(%rbp),%eax
16d6: 89 d6 mov %edx,%esi
16d8: 89 c7 mov %eax,%edi
16da: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
16e1: 00 00 00
16e4: ff d0 callq *%rax
while (--i >= 0)
16e6: 83 6d f4 01 subl $0x1,-0xc(%rbp)
16ea: 83 7d f4 00 cmpl $0x0,-0xc(%rbp)
16ee: 79 d6 jns 16c6 <print_d+0xca>
}
16f0: 90 nop
16f1: 90 nop
16f2: c9 leaveq
16f3: c3 retq
00000000000016f4 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
16f4: f3 0f 1e fa endbr64
16f8: 55 push %rbp
16f9: 48 89 e5 mov %rsp,%rbp
16fc: 48 81 ec f0 00 00 00 sub $0xf0,%rsp
1703: 89 bd 1c ff ff ff mov %edi,-0xe4(%rbp)
1709: 48 89 b5 10 ff ff ff mov %rsi,-0xf0(%rbp)
1710: 48 89 95 60 ff ff ff mov %rdx,-0xa0(%rbp)
1717: 48 89 8d 68 ff ff ff mov %rcx,-0x98(%rbp)
171e: 4c 89 85 70 ff ff ff mov %r8,-0x90(%rbp)
1725: 4c 89 8d 78 ff ff ff mov %r9,-0x88(%rbp)
172c: 84 c0 test %al,%al
172e: 74 20 je 1750 <printf+0x5c>
1730: 0f 29 45 80 movaps %xmm0,-0x80(%rbp)
1734: 0f 29 4d 90 movaps %xmm1,-0x70(%rbp)
1738: 0f 29 55 a0 movaps %xmm2,-0x60(%rbp)
173c: 0f 29 5d b0 movaps %xmm3,-0x50(%rbp)
1740: 0f 29 65 c0 movaps %xmm4,-0x40(%rbp)
1744: 0f 29 6d d0 movaps %xmm5,-0x30(%rbp)
1748: 0f 29 75 e0 movaps %xmm6,-0x20(%rbp)
174c: 0f 29 7d f0 movaps %xmm7,-0x10(%rbp)
va_list ap;
int i, c;
char *s;
va_start(ap, fmt);
1750: c7 85 20 ff ff ff 10 movl $0x10,-0xe0(%rbp)
1757: 00 00 00
175a: c7 85 24 ff ff ff 30 movl $0x30,-0xdc(%rbp)
1761: 00 00 00
1764: 48 8d 45 10 lea 0x10(%rbp),%rax
1768: 48 89 85 28 ff ff ff mov %rax,-0xd8(%rbp)
176f: 48 8d 85 50 ff ff ff lea -0xb0(%rbp),%rax
1776: 48 89 85 30 ff ff ff mov %rax,-0xd0(%rbp)
for (i = 0; (c = fmt[i] & 0xff) != 0; i++) {
177d: c7 85 4c ff ff ff 00 movl $0x0,-0xb4(%rbp)
1784: 00 00 00
1787: e9 41 03 00 00 jmpq 1acd <printf+0x3d9>
if (c != '%') {
178c: 83 bd 3c ff ff ff 25 cmpl $0x25,-0xc4(%rbp)
1793: 74 24 je 17b9 <printf+0xc5>
putc(fd, c);
1795: 8b 85 3c ff ff ff mov -0xc4(%rbp),%eax
179b: 0f be d0 movsbl %al,%edx
179e: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
17a4: 89 d6 mov %edx,%esi
17a6: 89 c7 mov %eax,%edi
17a8: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
17af: 00 00 00
17b2: ff d0 callq *%rax
continue;
17b4: e9 0d 03 00 00 jmpq 1ac6 <printf+0x3d2>
}
c = fmt[++i] & 0xff;
17b9: 83 85 4c ff ff ff 01 addl $0x1,-0xb4(%rbp)
17c0: 8b 85 4c ff ff ff mov -0xb4(%rbp),%eax
17c6: 48 63 d0 movslq %eax,%rdx
17c9: 48 8b 85 10 ff ff ff mov -0xf0(%rbp),%rax
17d0: 48 01 d0 add %rdx,%rax
17d3: 0f b6 00 movzbl (%rax),%eax
17d6: 0f be c0 movsbl %al,%eax
17d9: 25 ff 00 00 00 and $0xff,%eax
17de: 89 85 3c ff ff ff mov %eax,-0xc4(%rbp)
if (c == 0)
17e4: 83 bd 3c ff ff ff 00 cmpl $0x0,-0xc4(%rbp)
17eb: 0f 84 0f 03 00 00 je 1b00 <printf+0x40c>
break;
switch(c) {
17f1: 83 bd 3c ff ff ff 25 cmpl $0x25,-0xc4(%rbp)
17f8: 0f 84 74 02 00 00 je 1a72 <printf+0x37e>
17fe: 83 bd 3c ff ff ff 25 cmpl $0x25,-0xc4(%rbp)
1805: 0f 8c 82 02 00 00 jl 1a8d <printf+0x399>
180b: 83 bd 3c ff ff ff 78 cmpl $0x78,-0xc4(%rbp)
1812: 0f 8f 75 02 00 00 jg 1a8d <printf+0x399>
1818: 83 bd 3c ff ff ff 63 cmpl $0x63,-0xc4(%rbp)
181f: 0f 8c 68 02 00 00 jl 1a8d <printf+0x399>
1825: 8b 85 3c ff ff ff mov -0xc4(%rbp),%eax
182b: 83 e8 63 sub $0x63,%eax
182e: 83 f8 15 cmp $0x15,%eax
1831: 0f 87 56 02 00 00 ja 1a8d <printf+0x399>
1837: 89 c0 mov %eax,%eax
1839: 48 8d 14 c5 00 00 00 lea 0x0(,%rax,8),%rdx
1840: 00
1841: 48 b8 38 1e 00 00 00 movabs $0x1e38,%rax
1848: 00 00 00
184b: 48 01 d0 add %rdx,%rax
184e: 48 8b 00 mov (%rax),%rax
1851: 3e ff e0 notrack jmpq *%rax
case 'c':
putc(fd, va_arg(ap, int));
1854: 8b 85 20 ff ff ff mov -0xe0(%rbp),%eax
185a: 83 f8 2f cmp $0x2f,%eax
185d: 77 23 ja 1882 <printf+0x18e>
185f: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
1866: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
186c: 89 d2 mov %edx,%edx
186e: 48 01 d0 add %rdx,%rax
1871: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
1877: 83 c2 08 add $0x8,%edx
187a: 89 95 20 ff ff ff mov %edx,-0xe0(%rbp)
1880: eb 12 jmp 1894 <printf+0x1a0>
1882: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax
1889: 48 8d 50 08 lea 0x8(%rax),%rdx
188d: 48 89 95 28 ff ff ff mov %rdx,-0xd8(%rbp)
1894: 8b 00 mov (%rax),%eax
1896: 0f be d0 movsbl %al,%edx
1899: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
189f: 89 d6 mov %edx,%esi
18a1: 89 c7 mov %eax,%edi
18a3: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
18aa: 00 00 00
18ad: ff d0 callq *%rax
break;
18af: e9 12 02 00 00 jmpq 1ac6 <printf+0x3d2>
case 'd':
print_d(fd, va_arg(ap, int));
18b4: 8b 85 20 ff ff ff mov -0xe0(%rbp),%eax
18ba: 83 f8 2f cmp $0x2f,%eax
18bd: 77 23 ja 18e2 <printf+0x1ee>
18bf: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
18c6: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
18cc: 89 d2 mov %edx,%edx
18ce: 48 01 d0 add %rdx,%rax
18d1: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
18d7: 83 c2 08 add $0x8,%edx
18da: 89 95 20 ff ff ff mov %edx,-0xe0(%rbp)
18e0: eb 12 jmp 18f4 <printf+0x200>
18e2: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax
18e9: 48 8d 50 08 lea 0x8(%rax),%rdx
18ed: 48 89 95 28 ff ff ff mov %rdx,-0xd8(%rbp)
18f4: 8b 10 mov (%rax),%edx
18f6: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
18fc: 89 d6 mov %edx,%esi
18fe: 89 c7 mov %eax,%edi
1900: 48 b8 fc 15 00 00 00 movabs $0x15fc,%rax
1907: 00 00 00
190a: ff d0 callq *%rax
break;
190c: e9 b5 01 00 00 jmpq 1ac6 <printf+0x3d2>
case 'x':
print_x32(fd, va_arg(ap, uint));
1911: 8b 85 20 ff ff ff mov -0xe0(%rbp),%eax
1917: 83 f8 2f cmp $0x2f,%eax
191a: 77 23 ja 193f <printf+0x24b>
191c: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
1923: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
1929: 89 d2 mov %edx,%edx
192b: 48 01 d0 add %rdx,%rax
192e: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
1934: 83 c2 08 add $0x8,%edx
1937: 89 95 20 ff ff ff mov %edx,-0xe0(%rbp)
193d: eb 12 jmp 1951 <printf+0x25d>
193f: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax
1946: 48 8d 50 08 lea 0x8(%rax),%rdx
194a: 48 89 95 28 ff ff ff mov %rdx,-0xd8(%rbp)
1951: 8b 10 mov (%rax),%edx
1953: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
1959: 89 d6 mov %edx,%esi
195b: 89 c7 mov %eax,%edi
195d: 48 b8 9f 15 00 00 00 movabs $0x159f,%rax
1964: 00 00 00
1967: ff d0 callq *%rax
break;
1969: e9 58 01 00 00 jmpq 1ac6 <printf+0x3d2>
case 'p':
print_x64(fd, va_arg(ap, addr_t));
196e: 8b 85 20 ff ff ff mov -0xe0(%rbp),%eax
1974: 83 f8 2f cmp $0x2f,%eax
1977: 77 23 ja 199c <printf+0x2a8>
1979: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
1980: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
1986: 89 d2 mov %edx,%edx
1988: 48 01 d0 add %rdx,%rax
198b: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
1991: 83 c2 08 add $0x8,%edx
1994: 89 95 20 ff ff ff mov %edx,-0xe0(%rbp)
199a: eb 12 jmp 19ae <printf+0x2ba>
199c: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax
19a3: 48 8d 50 08 lea 0x8(%rax),%rdx
19a7: 48 89 95 28 ff ff ff mov %rdx,-0xd8(%rbp)
19ae: 48 8b 10 mov (%rax),%rdx
19b1: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
19b7: 48 89 d6 mov %rdx,%rsi
19ba: 89 c7 mov %eax,%edi
19bc: 48 b8 42 15 00 00 00 movabs $0x1542,%rax
19c3: 00 00 00
19c6: ff d0 callq *%rax
break;
19c8: e9 f9 00 00 00 jmpq 1ac6 <printf+0x3d2>
case 's':
if ((s = va_arg(ap, char*)) == 0)
19cd: 8b 85 20 ff ff ff mov -0xe0(%rbp),%eax
19d3: 83 f8 2f cmp $0x2f,%eax
19d6: 77 23 ja 19fb <printf+0x307>
19d8: 48 8b 85 30 ff ff ff mov -0xd0(%rbp),%rax
19df: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
19e5: 89 d2 mov %edx,%edx
19e7: 48 01 d0 add %rdx,%rax
19ea: 8b 95 20 ff ff ff mov -0xe0(%rbp),%edx
19f0: 83 c2 08 add $0x8,%edx
19f3: 89 95 20 ff ff ff mov %edx,-0xe0(%rbp)
19f9: eb 12 jmp 1a0d <printf+0x319>
19fb: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax
1a02: 48 8d 50 08 lea 0x8(%rax),%rdx
1a06: 48 89 95 28 ff ff ff mov %rdx,-0xd8(%rbp)
1a0d: 48 8b 00 mov (%rax),%rax
1a10: 48 89 85 40 ff ff ff mov %rax,-0xc0(%rbp)
1a17: 48 83 bd 40 ff ff ff cmpq $0x0,-0xc0(%rbp)
1a1e: 00
1a1f: 75 41 jne 1a62 <printf+0x36e>
s = "(null)";
1a21: 48 b8 30 1e 00 00 00 movabs $0x1e30,%rax
1a28: 00 00 00
1a2b: 48 89 85 40 ff ff ff mov %rax,-0xc0(%rbp)
while (*s)
1a32: eb 2e jmp 1a62 <printf+0x36e>
putc(fd, *(s++));
1a34: 48 8b 85 40 ff ff ff mov -0xc0(%rbp),%rax
1a3b: 48 8d 50 01 lea 0x1(%rax),%rdx
1a3f: 48 89 95 40 ff ff ff mov %rdx,-0xc0(%rbp)
1a46: 0f b6 00 movzbl (%rax),%eax
1a49: 0f be d0 movsbl %al,%edx
1a4c: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
1a52: 89 d6 mov %edx,%esi
1a54: 89 c7 mov %eax,%edi
1a56: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
1a5d: 00 00 00
1a60: ff d0 callq *%rax
while (*s)
1a62: 48 8b 85 40 ff ff ff mov -0xc0(%rbp),%rax
1a69: 0f b6 00 movzbl (%rax),%eax
1a6c: 84 c0 test %al,%al
1a6e: 75 c4 jne 1a34 <printf+0x340>
break;
1a70: eb 54 jmp 1ac6 <printf+0x3d2>
case '%':
putc(fd, '%');
1a72: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
1a78: be 25 00 00 00 mov $0x25,%esi
1a7d: 89 c7 mov %eax,%edi
1a7f: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
1a86: 00 00 00
1a89: ff d0 callq *%rax
break;
1a8b: eb 39 jmp 1ac6 <printf+0x3d2>
default:
// Print unknown % sequence to draw attention.
putc(fd, '%');
1a8d: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
1a93: be 25 00 00 00 mov $0x25,%esi
1a98: 89 c7 mov %eax,%edi
1a9a: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
1aa1: 00 00 00
1aa4: ff d0 callq *%rax
putc(fd, c);
1aa6: 8b 85 3c ff ff ff mov -0xc4(%rbp),%eax
1aac: 0f be d0 movsbl %al,%edx
1aaf: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax
1ab5: 89 d6 mov %edx,%esi
1ab7: 89 c7 mov %eax,%edi
1ab9: 48 b8 0e 15 00 00 00 movabs $0x150e,%rax
1ac0: 00 00 00
1ac3: ff d0 callq *%rax
break;
1ac5: 90 nop
for (i = 0; (c = fmt[i] & 0xff) != 0; i++) {
1ac6: 83 85 4c ff ff ff 01 addl $0x1,-0xb4(%rbp)
1acd: 8b 85 4c ff ff ff mov -0xb4(%rbp),%eax
1ad3: 48 63 d0 movslq %eax,%rdx
1ad6: 48 8b 85 10 ff ff ff mov -0xf0(%rbp),%rax
1add: 48 01 d0 add %rdx,%rax
1ae0: 0f b6 00 movzbl (%rax),%eax
1ae3: 0f be c0 movsbl %al,%eax
1ae6: 25 ff 00 00 00 and $0xff,%eax
1aeb: 89 85 3c ff ff ff mov %eax,-0xc4(%rbp)
1af1: 83 bd 3c ff ff ff 00 cmpl $0x0,-0xc4(%rbp)
1af8: 0f 85 8e fc ff ff jne 178c <printf+0x98>
}
}
}
1afe: eb 01 jmp 1b01 <printf+0x40d>
break;
1b00: 90 nop
}
1b01: 90 nop
1b02: c9 leaveq
1b03: c3 retq
0000000000001b04 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
1b04: f3 0f 1e fa endbr64
1b08: 55 push %rbp
1b09: 48 89 e5 mov %rsp,%rbp
1b0c: 48 83 ec 18 sub $0x18,%rsp
1b10: 48 89 7d e8 mov %rdi,-0x18(%rbp)
Header *bp, *p;
bp = (Header*)ap - 1;
1b14: 48 8b 45 e8 mov -0x18(%rbp),%rax
1b18: 48 83 e8 10 sub $0x10,%rax
1b1c: 48 89 45 f0 mov %rax,-0x10(%rbp)
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
1b20: 48 b8 90 21 00 00 00 movabs $0x2190,%rax
1b27: 00 00 00
1b2a: 48 8b 00 mov (%rax),%rax
1b2d: 48 89 45 f8 mov %rax,-0x8(%rbp)
1b31: eb 2f jmp 1b62 <free+0x5e>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
1b33: 48 8b 45 f8 mov -0x8(%rbp),%rax
1b37: 48 8b 00 mov (%rax),%rax
1b3a: 48 39 45 f8 cmp %rax,-0x8(%rbp)
1b3e: 72 17 jb 1b57 <free+0x53>
1b40: 48 8b 45 f0 mov -0x10(%rbp),%rax
1b44: 48 3b 45 f8 cmp -0x8(%rbp),%rax
1b48: 77 2f ja 1b79 <free+0x75>
1b4a: 48 8b 45 f8 mov -0x8(%rbp),%rax
1b4e: 48 8b 00 mov (%rax),%rax
1b51: 48 39 45 f0 cmp %rax,-0x10(%rbp)
1b55: 72 22 jb 1b79 <free+0x75>
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
1b57: 48 8b 45 f8 mov -0x8(%rbp),%rax
1b5b: 48 8b 00 mov (%rax),%rax
1b5e: 48 89 45 f8 mov %rax,-0x8(%rbp)
1b62: 48 8b 45 f0 mov -0x10(%rbp),%rax
1b66: 48 3b 45 f8 cmp -0x8(%rbp),%rax
1b6a: 76 c7 jbe 1b33 <free+0x2f>
1b6c: 48 8b 45 f8 mov -0x8(%rbp),%rax
1b70: 48 8b 00 mov (%rax),%rax
1b73: 48 39 45 f0 cmp %rax,-0x10(%rbp)
1b77: 73 ba jae 1b33 <free+0x2f>
break;
if(bp + bp->s.size == p->s.ptr){
1b79: 48 8b 45 f0 mov -0x10(%rbp),%rax
1b7d: 8b 40 08 mov 0x8(%rax),%eax
1b80: 89 c0 mov %eax,%eax
1b82: 48 c1 e0 04 shl $0x4,%rax
1b86: 48 89 c2 mov %rax,%rdx
1b89: 48 8b 45 f0 mov -0x10(%rbp),%rax
1b8d: 48 01 c2 add %rax,%rdx
1b90: 48 8b 45 f8 mov -0x8(%rbp),%rax
1b94: 48 8b 00 mov (%rax),%rax
1b97: 48 39 c2 cmp %rax,%rdx
1b9a: 75 2d jne 1bc9 <free+0xc5>
bp->s.size += p->s.ptr->s.size;
1b9c: 48 8b 45 f0 mov -0x10(%rbp),%rax
1ba0: 8b 50 08 mov 0x8(%rax),%edx
1ba3: 48 8b 45 f8 mov -0x8(%rbp),%rax
1ba7: 48 8b 00 mov (%rax),%rax
1baa: 8b 40 08 mov 0x8(%rax),%eax
1bad: 01 c2 add %eax,%edx
1baf: 48 8b 45 f0 mov -0x10(%rbp),%rax
1bb3: 89 50 08 mov %edx,0x8(%rax)
bp->s.ptr = p->s.ptr->s.ptr;
1bb6: 48 8b 45 f8 mov -0x8(%rbp),%rax
1bba: 48 8b 00 mov (%rax),%rax
1bbd: 48 8b 10 mov (%rax),%rdx
1bc0: 48 8b 45 f0 mov -0x10(%rbp),%rax
1bc4: 48 89 10 mov %rdx,(%rax)
1bc7: eb 0e jmp 1bd7 <free+0xd3>
} else
bp->s.ptr = p->s.ptr;
1bc9: 48 8b 45 f8 mov -0x8(%rbp),%rax
1bcd: 48 8b 10 mov (%rax),%rdx
1bd0: 48 8b 45 f0 mov -0x10(%rbp),%rax
1bd4: 48 89 10 mov %rdx,(%rax)
if(p + p->s.size == bp){
1bd7: 48 8b 45 f8 mov -0x8(%rbp),%rax
1bdb: 8b 40 08 mov 0x8(%rax),%eax
1bde: 89 c0 mov %eax,%eax
1be0: 48 c1 e0 04 shl $0x4,%rax
1be4: 48 89 c2 mov %rax,%rdx
1be7: 48 8b 45 f8 mov -0x8(%rbp),%rax
1beb: 48 01 d0 add %rdx,%rax
1bee: 48 39 45 f0 cmp %rax,-0x10(%rbp)
1bf2: 75 27 jne 1c1b <free+0x117>
p->s.size += bp->s.size;
1bf4: 48 8b 45 f8 mov -0x8(%rbp),%rax
1bf8: 8b 50 08 mov 0x8(%rax),%edx
1bfb: 48 8b 45 f0 mov -0x10(%rbp),%rax
1bff: 8b 40 08 mov 0x8(%rax),%eax
1c02: 01 c2 add %eax,%edx
1c04: 48 8b 45 f8 mov -0x8(%rbp),%rax
1c08: 89 50 08 mov %edx,0x8(%rax)
p->s.ptr = bp->s.ptr;
1c0b: 48 8b 45 f0 mov -0x10(%rbp),%rax
1c0f: 48 8b 10 mov (%rax),%rdx
1c12: 48 8b 45 f8 mov -0x8(%rbp),%rax
1c16: 48 89 10 mov %rdx,(%rax)
1c19: eb 0b jmp 1c26 <free+0x122>
} else
p->s.ptr = bp;
1c1b: 48 8b 45 f8 mov -0x8(%rbp),%rax
1c1f: 48 8b 55 f0 mov -0x10(%rbp),%rdx
1c23: 48 89 10 mov %rdx,(%rax)
freep = p;
1c26: 48 ba 90 21 00 00 00 movabs $0x2190,%rdx
1c2d: 00 00 00
1c30: 48 8b 45 f8 mov -0x8(%rbp),%rax
1c34: 48 89 02 mov %rax,(%rdx)
}
1c37: 90 nop
1c38: c9 leaveq
1c39: c3 retq
0000000000001c3a <morecore>:
static Header*
morecore(uint nu)
{
1c3a: f3 0f 1e fa endbr64
1c3e: 55 push %rbp
1c3f: 48 89 e5 mov %rsp,%rbp
1c42: 48 83 ec 20 sub $0x20,%rsp
1c46: 89 7d ec mov %edi,-0x14(%rbp)
char *p;
Header *hp;
if(nu < 4096)
1c49: 81 7d ec ff 0f 00 00 cmpl $0xfff,-0x14(%rbp)
1c50: 77 07 ja 1c59 <morecore+0x1f>
nu = 4096;
1c52: c7 45 ec 00 10 00 00 movl $0x1000,-0x14(%rbp)
p = sbrk(nu * sizeof(Header));
1c59: 8b 45 ec mov -0x14(%rbp),%eax
1c5c: 48 c1 e0 04 shl $0x4,%rax
1c60: 48 89 c7 mov %rax,%rdi
1c63: 48 b8 da 14 00 00 00 movabs $0x14da,%rax
1c6a: 00 00 00
1c6d: ff d0 callq *%rax
1c6f: 48 89 45 f8 mov %rax,-0x8(%rbp)
if(p == (char*)-1)
1c73: 48 83 7d f8 ff cmpq $0xffffffffffffffff,-0x8(%rbp)
1c78: 75 07 jne 1c81 <morecore+0x47>
return 0;
1c7a: b8 00 00 00 00 mov $0x0,%eax
1c7f: eb 36 jmp 1cb7 <morecore+0x7d>
hp = (Header*)p;
1c81: 48 8b 45 f8 mov -0x8(%rbp),%rax
1c85: 48 89 45 f0 mov %rax,-0x10(%rbp)
hp->s.size = nu;
1c89: 48 8b 45 f0 mov -0x10(%rbp),%rax
1c8d: 8b 55 ec mov -0x14(%rbp),%edx
1c90: 89 50 08 mov %edx,0x8(%rax)
free((void*)(hp + 1));
1c93: 48 8b 45 f0 mov -0x10(%rbp),%rax
1c97: 48 83 c0 10 add $0x10,%rax
1c9b: 48 89 c7 mov %rax,%rdi
1c9e: 48 b8 04 1b 00 00 00 movabs $0x1b04,%rax
1ca5: 00 00 00
1ca8: ff d0 callq *%rax
return freep;
1caa: 48 b8 90 21 00 00 00 movabs $0x2190,%rax
1cb1: 00 00 00
1cb4: 48 8b 00 mov (%rax),%rax
}
1cb7: c9 leaveq
1cb8: c3 retq
0000000000001cb9 <malloc>:
void*
malloc(uint nbytes)
{
1cb9: f3 0f 1e fa endbr64
1cbd: 55 push %rbp
1cbe: 48 89 e5 mov %rsp,%rbp
1cc1: 48 83 ec 30 sub $0x30,%rsp
1cc5: 89 7d dc mov %edi,-0x24(%rbp)
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
1cc8: 8b 45 dc mov -0x24(%rbp),%eax
1ccb: 48 83 c0 0f add $0xf,%rax
1ccf: 48 c1 e8 04 shr $0x4,%rax
1cd3: 83 c0 01 add $0x1,%eax
1cd6: 89 45 ec mov %eax,-0x14(%rbp)
if((prevp = freep) == 0){
1cd9: 48 b8 90 21 00 00 00 movabs $0x2190,%rax
1ce0: 00 00 00
1ce3: 48 8b 00 mov (%rax),%rax
1ce6: 48 89 45 f0 mov %rax,-0x10(%rbp)
1cea: 48 83 7d f0 00 cmpq $0x0,-0x10(%rbp)
1cef: 75 4a jne 1d3b <malloc+0x82>
base.s.ptr = freep = prevp = &base;
1cf1: 48 b8 80 21 00 00 00 movabs $0x2180,%rax
1cf8: 00 00 00
1cfb: 48 89 45 f0 mov %rax,-0x10(%rbp)
1cff: 48 ba 90 21 00 00 00 movabs $0x2190,%rdx
1d06: 00 00 00
1d09: 48 8b 45 f0 mov -0x10(%rbp),%rax
1d0d: 48 89 02 mov %rax,(%rdx)
1d10: 48 b8 90 21 00 00 00 movabs $0x2190,%rax
1d17: 00 00 00
1d1a: 48 8b 00 mov (%rax),%rax
1d1d: 48 ba 80 21 00 00 00 movabs $0x2180,%rdx
1d24: 00 00 00
1d27: 48 89 02 mov %rax,(%rdx)
base.s.size = 0;
1d2a: 48 b8 80 21 00 00 00 movabs $0x2180,%rax
1d31: 00 00 00
1d34: c7 40 08 00 00 00 00 movl $0x0,0x8(%rax)
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
1d3b: 48 8b 45 f0 mov -0x10(%rbp),%rax
1d3f: 48 8b 00 mov (%rax),%rax
1d42: 48 89 45 f8 mov %rax,-0x8(%rbp)
if(p->s.size >= nunits){
1d46: 48 8b 45 f8 mov -0x8(%rbp),%rax
1d4a: 8b 40 08 mov 0x8(%rax),%eax
1d4d: 39 45 ec cmp %eax,-0x14(%rbp)
1d50: 77 65 ja 1db7 <malloc+0xfe>
if(p->s.size == nunits)
1d52: 48 8b 45 f8 mov -0x8(%rbp),%rax
1d56: 8b 40 08 mov 0x8(%rax),%eax
1d59: 39 45 ec cmp %eax,-0x14(%rbp)
1d5c: 75 10 jne 1d6e <malloc+0xb5>
prevp->s.ptr = p->s.ptr;
1d5e: 48 8b 45 f8 mov -0x8(%rbp),%rax
1d62: 48 8b 10 mov (%rax),%rdx
1d65: 48 8b 45 f0 mov -0x10(%rbp),%rax
1d69: 48 89 10 mov %rdx,(%rax)
1d6c: eb 2e jmp 1d9c <malloc+0xe3>
else {
p->s.size -= nunits;
1d6e: 48 8b 45 f8 mov -0x8(%rbp),%rax
1d72: 8b 40 08 mov 0x8(%rax),%eax
1d75: 2b 45 ec sub -0x14(%rbp),%eax
1d78: 89 c2 mov %eax,%edx
1d7a: 48 8b 45 f8 mov -0x8(%rbp),%rax
1d7e: 89 50 08 mov %edx,0x8(%rax)
p += p->s.size;
1d81: 48 8b 45 f8 mov -0x8(%rbp),%rax
1d85: 8b 40 08 mov 0x8(%rax),%eax
1d88: 89 c0 mov %eax,%eax
1d8a: 48 c1 e0 04 shl $0x4,%rax
1d8e: 48 01 45 f8 add %rax,-0x8(%rbp)
p->s.size = nunits;
1d92: 48 8b 45 f8 mov -0x8(%rbp),%rax
1d96: 8b 55 ec mov -0x14(%rbp),%edx
1d99: 89 50 08 mov %edx,0x8(%rax)
}
freep = prevp;
1d9c: 48 ba 90 21 00 00 00 movabs $0x2190,%rdx
1da3: 00 00 00
1da6: 48 8b 45 f0 mov -0x10(%rbp),%rax
1daa: 48 89 02 mov %rax,(%rdx)
return (void*)(p + 1);
1dad: 48 8b 45 f8 mov -0x8(%rbp),%rax
1db1: 48 83 c0 10 add $0x10,%rax
1db5: eb 4e jmp 1e05 <malloc+0x14c>
}
if(p == freep)
1db7: 48 b8 90 21 00 00 00 movabs $0x2190,%rax
1dbe: 00 00 00
1dc1: 48 8b 00 mov (%rax),%rax
1dc4: 48 39 45 f8 cmp %rax,-0x8(%rbp)
1dc8: 75 23 jne 1ded <malloc+0x134>
if((p = morecore(nunits)) == 0)
1dca: 8b 45 ec mov -0x14(%rbp),%eax
1dcd: 89 c7 mov %eax,%edi
1dcf: 48 b8 3a 1c 00 00 00 movabs $0x1c3a,%rax
1dd6: 00 00 00
1dd9: ff d0 callq *%rax
1ddb: 48 89 45 f8 mov %rax,-0x8(%rbp)
1ddf: 48 83 7d f8 00 cmpq $0x0,-0x8(%rbp)
1de4: 75 07 jne 1ded <malloc+0x134>
return 0;
1de6: b8 00 00 00 00 mov $0x0,%eax
1deb: eb 18 jmp 1e05 <malloc+0x14c>
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
1ded: 48 8b 45 f8 mov -0x8(%rbp),%rax
1df1: 48 89 45 f0 mov %rax,-0x10(%rbp)
1df5: 48 8b 45 f8 mov -0x8(%rbp),%rax
1df9: 48 8b 00 mov (%rax),%rax
1dfc: 48 89 45 f8 mov %rax,-0x8(%rbp)
if(p->s.size >= nunits){
1e00: e9 41 ff ff ff jmpq 1d46 <malloc+0x8d>
}
}
1e05: c9 leaveq
1e06: c3 retq
|
<%
import collections
import pwnlib.abi
import pwnlib.constants
import pwnlib.shellcraft
import six
%>
<%docstring>open(file, oflag, mode) -> str
Invokes the syscall open.
See 'man 2 open' for more information.
Arguments:
file(char*): file
oflag(int): oflag
vararg(int): vararg
Returns:
int
</%docstring>
<%page args="file=0, oflag=0, mode=0"/>
<%
abi = pwnlib.abi.ABI.syscall()
stack = abi.stack
regs = abi.register_arguments[1:]
allregs = pwnlib.shellcraft.registers.current()
can_pushstr = ['file']
can_pushstr_array = []
argument_names = ['file', 'oflag', 'mode']
argument_values = [file, oflag, mode]
# Load all of the arguments into their destination registers / stack slots.
register_arguments = dict()
stack_arguments = collections.OrderedDict()
string_arguments = dict()
dict_arguments = dict()
array_arguments = dict()
syscall_repr = []
for name, arg in zip(argument_names, argument_values):
if arg is not None:
syscall_repr.append('%s=%s' % (name, pwnlib.shellcraft.pretty(arg, False)))
# If the argument itself (input) is a register...
if arg in allregs:
index = argument_names.index(name)
if index < len(regs):
target = regs[index]
register_arguments[target] = arg
elif arg is not None:
stack_arguments[index] = arg
# The argument is not a register. It is a string value, and we
# are expecting a string value
elif name in can_pushstr and isinstance(arg, (six.binary_type, six.text_type)):
if isinstance(arg, six.text_type):
arg = arg.encode('utf-8')
string_arguments[name] = arg
# The argument is not a register. It is a dictionary, and we are
# expecting K:V paris.
elif name in can_pushstr_array and isinstance(arg, dict):
array_arguments[name] = ['%s=%s' % (k,v) for (k,v) in arg.items()]
# The arguent is not a register. It is a list, and we are expecting
# a list of arguments.
elif name in can_pushstr_array and isinstance(arg, (list, tuple)):
array_arguments[name] = arg
# The argument is not a register, string, dict, or list.
# It could be a constant string ('O_RDONLY') for an integer argument,
# an actual integer value, or a constant.
else:
index = argument_names.index(name)
if index < len(regs):
target = regs[index]
register_arguments[target] = arg
elif arg is not None:
stack_arguments[target] = arg
# Some syscalls have different names on various architectures.
# Determine which syscall number to use for the current architecture.
for syscall in ['SYS_open']:
if hasattr(pwnlib.constants, syscall):
break
else:
raise Exception("Could not locate any syscalls: %r" % syscalls)
%>
/* open(${', '.join(syscall_repr)}) */
%for name, arg in string_arguments.items():
${pwnlib.shellcraft.pushstr(arg, append_null=(b'\x00' not in arg))}
${pwnlib.shellcraft.mov(regs[argument_names.index(name)], abi.stack)}
%endfor
%for name, arg in array_arguments.items():
${pwnlib.shellcraft.pushstr_array(regs[argument_names.index(name)], arg)}
%endfor
%for name, arg in stack_arguments.items():
${pwnlib.shellcraft.push(arg)}
%endfor
${pwnlib.shellcraft.setregs(register_arguments)}
${pwnlib.shellcraft.syscall(syscall)}
|
default rel
%define XMMWORD
%define YMMWORD
%define ZMMWORD
global dummy_chacha20_poly1305_asm
dummy_chacha20_poly1305_asm:
DB 0F3h,0C3h ;repret
|
; A302942: a(n) = (2^n-1)^2*(2^n + 2).
; Submitted by Christian Krause
; 0,4,54,490,4050,32674,261954,2096770,16776450,134216194,1073738754,8589928450,68719464450,549755789314,4398046461954,35184371990530,281474976514050,2251799813292034,18014398508695554,144115188074283010,1152921504603701250,9223372036848484354
mov $3,2
pow $3,$0
mov $0,$3
mov $1,3
pow $3,2
sub $1,$3
mul $1,$0
mov $2,2
sub $2,$1
mov $0,$2
|
; A007291: Series expansion for rectilinear polymers on square lattice.
; 7,63,254,710,1605,3157,5628,9324,14595,21835,31482,44018,59969,79905,104440,134232,169983,212439,262390,320670,388157,465773,554484,655300,769275,897507,1041138,1201354,1379385
mov $17,$0
mov $19,$0
add $19,1
lpb $19,1
clr $0,17
mov $0,$17
sub $19,1
sub $0,$19
mov $14,$0
mov $16,$0
add $16,1
lpb $16,1
clr $0,14
mov $0,$14
sub $16,1
sub $0,$16
mov $11,$0
mov $13,$0
add $13,1
lpb $13,1
mov $0,$11
sub $13,1
sub $0,$13
mul $0,11
mov $1,1
lpb $0,1
mov $4,4
mul $4,$0
mov $0,6
mov $9,$1
add $9,1
lpe
mov $2,$4
add $9,1
add $10,$0
sub $2,$10
trn $2,$9
add $2,7
trn $5,$10
mov $10,$5
add $12,$2
lpe
add $15,$12
lpe
add $18,$15
lpe
mov $1,$18
|
db DEX_PINSIR ; pokedex id
db 65 ; base hp
db 125 ; base attack
db 100 ; base defense
db 85 ; base speed
db 55 ; base special
db BUG ; species type 1
db BUG ; species type 2
db 46 ; catch rate
db 200 ; base exp yield
INCBIN "pic/ymon/pinsir.pic",0,1 ; 77, sprite dimensions
dw PinsirPicFront
dw PinsirPicBack
; attacks known at lvl 0
db VICEGRIP
db 0
db 0
db 0
db 5 ; growth rate
; learnset
tmlearn 3,6,8
tmlearn 9,10,15
tmlearn 17,19,20
tmlearn 31,32
tmlearn 34
tmlearn 44
tmlearn 50,51,54
db BANK(PinsirPicFront)
|
/*
This file is part of:
NoahFrame
https://github.com/ketoo/NoahGameFrame
Copyright 2009 - 2019 NoahFrame(NoahGameFrame)
File creator: lvsheng.huang
NoahFrame is open-source software and you can redistribute it and/or modify
it under the terms of the License; besides, anyone who use this file/software must include this copyright announcement.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "NFDBNet_ServerPlugin.h"
#include "NFDBNet_ServerModule.h"
//
//
#ifdef NF_DYNAMIC_PLUGIN
NF_EXPORT void DllStartPlugin(NFIPluginManager* pm)
{
CREATE_PLUGIN(pm, NFDBNet_ServerPlugin)
};
NF_EXPORT void DllStopPlugin(NFIPluginManager* pm)
{
DESTROY_PLUGIN(pm, NFDBNet_ServerPlugin)
};
#endif
//////////////////////////////////////////////////////////////////////////
const int NFDBNet_ServerPlugin::GetPluginVersion()
{
return 0;
}
const std::string NFDBNet_ServerPlugin::GetPluginName()
{
return GET_CLASS_NAME(NFDBNet_ServerPlugin);
}
void NFDBNet_ServerPlugin::Install()
{
REGISTER_MODULE(pPluginManager, NFIDBNet_ServerModule, NFDBNet_ServerModule)
}
void NFDBNet_ServerPlugin::Uninstall()
{
UNREGISTER_MODULE(pPluginManager, NFIDBNet_ServerModule, NFDBNet_ServerModule)
} |
PUBLIC TestIpRead
PUBLIC TestIpWrite
PUBLIC Dummy
.code
TestIpRead PROC
mov eax, DWORD PTR [mylabelR]
mylabelR:
ret
TestIpRead ENDP
TestIpWrite PROC
mov BYTE PTR [mylabelW], 90H
mylabelW:
nop
ret
TestIpWrite ENDP
Dummy PROC
ret
Dummy ENDP
end
|
SECTION code_clib
SECTION code_fp_math48
PUBLIC asm_ldexp
EXTERN am48_ldexp
defc asm_ldexp = am48_ldexp
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r13
push %r14
push %r15
push %rax
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_normal_ht+0x1b6d3, %r14
nop
cmp $53050, %rbp
movw $0x6162, (%r14)
nop
cmp %rdi, %rdi
lea addresses_A_ht+0x13265, %r10
nop
nop
nop
nop
nop
lfence
mov (%r10), %r15d
nop
nop
nop
nop
dec %rdi
lea addresses_UC_ht+0x82d3, %r15
nop
nop
nop
nop
nop
add $41043, %r13
movl $0x61626364, (%r15)
nop
nop
nop
cmp %r10, %r10
lea addresses_D_ht+0x1a2d3, %r14
nop
add $35457, %rbp
mov $0x6162636465666768, %r13
movq %r13, %xmm7
vmovups %ymm7, (%r14)
nop
nop
nop
nop
nop
xor $463, %rax
lea addresses_D_ht+0xb5d3, %r13
sub $52257, %r14
movw $0x6162, (%r13)
nop
nop
nop
cmp %rax, %rax
lea addresses_UC_ht+0x15b13, %r15
sub $8641, %rbp
vmovups (%r15), %ymm7
vextracti128 $0, %ymm7, %xmm7
vpextrq $0, %xmm7, %rdi
nop
nop
nop
cmp %rax, %rax
lea addresses_WT_ht+0xaf93, %r13
clflush (%r13)
sub $34062, %rbp
movl $0x61626364, (%r13)
nop
nop
nop
nop
sub $44893, %r15
lea addresses_A_ht+0xee2b, %rsi
lea addresses_UC_ht+0xced3, %rdi
nop
nop
nop
and %r14, %r14
mov $46, %rcx
rep movsb
inc %r15
lea addresses_A_ht+0x16bd3, %rsi
nop
nop
nop
xor $14391, %rdi
movl $0x61626364, (%rsi)
nop
nop
nop
nop
nop
and $49070, %r13
lea addresses_D_ht+0x97d3, %r13
nop
nop
nop
and %rbp, %rbp
mov $0x6162636465666768, %r15
movq %r15, (%r13)
add %r14, %r14
lea addresses_UC_ht+0xdb03, %rbp
sub $46349, %r10
mov $0x6162636465666768, %r13
movq %r13, (%rbp)
nop
nop
nop
nop
dec %r10
lea addresses_D_ht+0x88b3, %rsi
lea addresses_WC_ht+0x1903, %rdi
nop
add %r15, %r15
mov $20, %rcx
rep movsw
nop
add $30584, %rsi
lea addresses_WT_ht+0x414b, %rdi
nop
cmp $15121, %r10
mov (%rdi), %rax
nop
nop
nop
cmp %r14, %r14
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %rax
pop %r15
pop %r14
pop %r13
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r12
push %r14
push %rcx
push %rdi
push %rsi
// Store
mov $0xeeb, %rdi
nop
nop
nop
nop
add $1968, %r14
mov $0x5152535455565758, %r11
movq %r11, %xmm2
movntdq %xmm2, (%rdi)
nop
sub %r12, %r12
// Store
lea addresses_UC+0x6d93, %r10
nop
nop
nop
add %rsi, %rsi
movw $0x5152, (%r10)
nop
nop
nop
add $39343, %r12
// Store
lea addresses_PSE+0x6943, %r11
nop
nop
nop
nop
and %r12, %r12
mov $0x5152535455565758, %rdi
movq %rdi, (%r11)
nop
add $26900, %rcx
// Store
lea addresses_normal+0x9ad3, %rdi
nop
nop
nop
cmp $21735, %rcx
movw $0x5152, (%rdi)
nop
nop
nop
sub $23775, %r14
// Faulty Load
lea addresses_D+0x8ad3, %r12
nop
nop
nop
nop
nop
add $36113, %r11
movups (%r12), %xmm0
vpextrq $0, %xmm0, %rdi
lea oracles, %r14
and $0xff, %rdi
shlq $12, %rdi
mov (%r14,%rdi,1), %rdi
pop %rsi
pop %rdi
pop %rcx
pop %r14
pop %r12
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'same': False, 'congruent': 0, 'type': 'addresses_D', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': True, 'same': False, 'congruent': 3, 'type': 'addresses_P', 'AVXalign': False, 'size': 16}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 5, 'type': 'addresses_UC', 'AVXalign': False, 'size': 2}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 3, 'type': 'addresses_PSE', 'AVXalign': False, 'size': 8}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_normal', 'AVXalign': True, 'size': 2}}
[Faulty Load]
{'src': {'NT': False, 'same': True, 'congruent': 0, 'type': 'addresses_D', 'AVXalign': False, 'size': 16}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 10, 'type': 'addresses_normal_ht', 'AVXalign': False, 'size': 2}}
{'src': {'NT': False, 'same': False, 'congruent': 1, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 4}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 9, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 4}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 11, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 32}}
{'OP': 'STOR', 'dst': {'NT': True, 'same': False, 'congruent': 8, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 2}}
{'src': {'NT': False, 'same': False, 'congruent': 4, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 32}, 'OP': 'LOAD'}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 6, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 4}}
{'src': {'same': False, 'congruent': 3, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'dst': {'same': False, 'congruent': 10, 'type': 'addresses_UC_ht'}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': True, 'congruent': 8, 'type': 'addresses_A_ht', 'AVXalign': False, 'size': 4}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': True, 'congruent': 5, 'type': 'addresses_D_ht', 'AVXalign': False, 'size': 8}}
{'OP': 'STOR', 'dst': {'NT': False, 'same': False, 'congruent': 3, 'type': 'addresses_UC_ht', 'AVXalign': False, 'size': 8}}
{'src': {'same': False, 'congruent': 5, 'type': 'addresses_D_ht'}, 'OP': 'REPM', 'dst': {'same': True, 'congruent': 4, 'type': 'addresses_WC_ht'}}
{'src': {'NT': False, 'same': False, 'congruent': 2, 'type': 'addresses_WT_ht', 'AVXalign': False, 'size': 8}, 'OP': 'LOAD'}
{'36': 21829}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
|
.MODEL small
.STACK
.DATA
num db -50
.CODE
.STARTUP
mov al,num
rcl al,1
jb next
mov dl,00h
.EXIT
next: mov dl,01h
.EXIT
end |
bits 64
v4fmaddps zmm0,zmm1+3,[rax]
v4fnmaddps zmm2,zmm3,[rax]
v4fmaddss zmm4,zmm5+3,[rax]
v4fnmaddss zmm6,zmm7+3,[rax]
v4dpwssds zmm8,zmm9,[rax]
v4dpwssd zmm10,zmm11+3,[rax]
v4dpwssd zmm10+0,zmm11+3,[rax]
; v4dpwssd zmm10+1,zmm11+3,[rax]
; v4dpwssd zmm10,zmm11+4,[rax]
; v4dpwssd zmm10,zmm11+7,[rax]
|
<%
from pwnlib.shellcraft.powerpc.linux import syscall
%>
<%page args="name, length"/>
<%docstring>
Invokes the syscall sethostname. See 'man 2 sethostname' for more information.
Arguments:
name(char): name
len(size_t): len
</%docstring>
${syscall('SYS_sethostname', name, length)}
|
; A292543: Number of 5-cycles in the n-Sierpinski tetrahedron graph.
; 0,96,384,1536,6144,24576,98304,393216,1572864,6291456,25165824,100663296,402653184,1610612736,6442450944,25769803776,103079215104,412316860416,1649267441664,6597069766656,26388279066624,105553116266496,422212465065984,1688849860263936
mov $1,4
pow $1,$0
div $1,4
mul $1,96
|
; A170677: Number of reduced words of length n in Coxeter group on 44 generators S_i with relations (S_i)^2 = (S_i S_j)^49 = I.
; Submitted by Jon Maiga
; 1,44,1892,81356,3498308,150427244,6468371492,278139974156,11960018888708,514280812214444,22114074925221092,950905221784506956,40888924536733799108,1758223755079553361644,75603621468420794550692
add $0,1
mov $3,1
lpb $0
sub $0,1
add $2,$3
div $3,$2
mul $2,43
lpe
mov $0,$2
div $0,43
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r14
push %r9
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_WT_ht+0x17b0, %r14
nop
nop
nop
sub $63382, %r9
movl $0x61626364, (%r14)
nop
nop
xor $17217, %rsi
lea addresses_UC_ht+0x65f0, %r11
and %r14, %r14
movb (%r11), %cl
nop
nop
sub %rsi, %rsi
lea addresses_A_ht+0x14eb0, %rsi
lea addresses_A_ht+0x6350, %rdi
nop
nop
nop
nop
xor $34166, %r10
mov $38, %rcx
rep movsb
cmp $39376, %rcx
lea addresses_UC_ht+0x132b0, %rsi
lea addresses_WT_ht+0x106b0, %rdi
clflush (%rdi)
nop
nop
nop
cmp $51598, %r11
mov $40, %rcx
rep movsb
nop
nop
nop
add $3661, %r11
lea addresses_UC_ht+0x78be, %rsi
lea addresses_WT_ht+0x19570, %rdi
nop
nop
nop
nop
cmp %r11, %r11
mov $58, %rcx
rep movsq
nop
nop
nop
sub %r9, %r9
lea addresses_UC_ht+0xe758, %rdi
nop
nop
nop
and %rcx, %rcx
mov (%rdi), %r11w
nop
cmp $13915, %rdi
lea addresses_normal_ht+0x5a70, %rsi
lea addresses_A_ht+0x13470, %rdi
nop
inc %rbp
mov $2, %rcx
rep movsl
nop
nop
cmp $37936, %rcx
lea addresses_normal_ht+0x16450, %rbp
xor $59904, %rcx
mov $0x6162636465666768, %rsi
movq %rsi, %xmm6
movups %xmm6, (%rbp)
nop
add $15270, %r11
lea addresses_WC_ht+0x18e2, %rsi
lea addresses_A_ht+0x180f2, %rdi
nop
nop
nop
and %rbp, %rbp
mov $25, %rcx
rep movsw
inc %rdi
lea addresses_WC_ht+0x133f0, %rsi
lea addresses_WT_ht+0x15f0, %rdi
nop
nop
nop
xor %r11, %r11
mov $36, %rcx
rep movsl
nop
nop
nop
nop
dec %r11
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r14
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r13
push %r14
push %r15
push %r9
push %rax
push %rbp
// Faulty Load
mov $0x251b350000000ab0, %r15
nop
nop
nop
nop
nop
and %rax, %rax
mov (%r15), %r12
lea oracles, %r9
and $0xff, %r12
shlq $12, %r12
mov (%r9,%r12,1), %r12
pop %rbp
pop %rax
pop %r9
pop %r15
pop %r14
pop %r13
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_NC', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 0}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'type': 'addresses_NC', 'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_WT_ht', 'NT': True, 'AVXalign': False, 'size': 4, 'congruent': 7}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 5}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 4, 'type': 'addresses_A_ht'}, 'dst': {'same': False, 'congruent': 5, 'type': 'addresses_A_ht'}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 10, 'type': 'addresses_UC_ht'}, 'dst': {'same': False, 'congruent': 8, 'type': 'addresses_WT_ht'}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 1, 'type': 'addresses_UC_ht'}, 'dst': {'same': False, 'congruent': 4, 'type': 'addresses_WT_ht'}}
{'OP': 'LOAD', 'src': {'same': False, 'type': 'addresses_UC_ht', 'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 2}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 2, 'type': 'addresses_normal_ht'}, 'dst': {'same': False, 'congruent': 6, 'type': 'addresses_A_ht'}}
{'OP': 'STOR', 'dst': {'same': False, 'type': 'addresses_normal_ht', 'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 2}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 1, 'type': 'addresses_WC_ht'}, 'dst': {'same': False, 'congruent': 1, 'type': 'addresses_A_ht'}}
{'OP': 'REPM', 'src': {'same': False, 'congruent': 6, 'type': 'addresses_WC_ht'}, 'dst': {'same': False, 'congruent': 6, 'type': 'addresses_WT_ht'}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
%define BE(a) ( ((((a)>>24)&0xFF) << 0) + ((((a)>>16)&0xFF) << 8) + ((((a)>>8)&0xFF) << 16) + ((((a)>>0)&0xFF) << 24))
ftyp_start:
dd BE(ftyp_end - ftyp_start)
db "ftyp"
db "isom"
dd BE(0x00)
db "mif1", "miaf"
ftyp_end:
meta_start:
dd BE(meta_end - meta_start)
db "meta"
dd BE(0)
hdlr_start:
dd BE(hdlr_end - hdlr_start)
db "hdlr"
db 0x00 ; version(8)
db 0x00, 0x00, 0x00 ; flags(24)
db 0x00, 0x00, 0x00, 0x00 ; pre_defined(32)
db 0x70, 0x69, 0x63, 0x74 ; handler_type(32) ('pict')
db 0x00, 0x00, 0x00, 0x00 ; reserved1(32)
db 0x00, 0x00, 0x00, 0x00 ; reserved2(32)
db 0x00, 0x00, 0x00, 0x00 ; reserved3(32)
db 0x00 ; name(8)
hdlr_end:
pitm_start:
dd BE(pitm_end - pitm_start)
db "pitm"
dd BE(0)
db 0x00, 0x00
pitm_end:
iinf_start:
dd BE(iinf_end - iinf_start)
db "iinf"
dd BE(0)
db 0x00, 0x00
iinf_end:
iprp_start:
dd BE(iprp_end - iprp_start)
db "iprp"
ipco_start:
dd BE(ipco_end - ipco_start)
db "ipco"
ispe_start:
dd BE(ispe_end - ispe_start)
db "ispe"
dd 0, 0, 0
ispe_end:
ipco_end:
iprp_end:
meta_end:
moov_start:
dd BE(moov_end - moov_start)
db "moov"
mvhd_start:
dd BE(mvhd_end - mvhd_start)
db "mvhd"
mvhd_end:
trak_start:
dd BE(trak_end - trak_start)
db "trak"
mdia_start:
dd BE(mdia_end - mdia_start)
db "mdia"
hdlr2_start:
dd BE(hdlr2_end - hdlr2_start)
db "hdlr"
db 0x00 ; version(8)
db 0x00, 0x00, 0x00 ; flags(24)
db 0x00, 0x00, 0x00, 0x00 ; pre_defined(32)
db 0x70, 0x69, 0x63, 0x74 ; handler_type(32) ('pict')
db 0x00, 0x00, 0x00, 0x00 ; reserved1(32)
db 0x00, 0x00, 0x00, 0x00 ; reserved2(32)
db 0x00, 0x00, 0x00, 0x00 ; reserved3(32)
db 0x00 ; name(8)
hdlr2_end:
mdia_end:
tkhd_start:
dd BE(tkhd_end - tkhd_start)
db "tkhd"
dd BE(0)
dd BE(0)
dd BE(0)
dd BE(0)
dd BE(0)
dd BE(0)
dd BE(0)
dd BE(0)
dd BE(0)
dd BE(0)
dd 0x11111111, 0x11111111, 0x11111111, 0x11111111, 0x11111111, 0x11111111, 0x11111111, 0x11111111, 0x11111111
dd BE(0) ; width
dd BE(0) ; height
tkhd_end:
trak_end:
moov_end: |
; A049393: Expansion of (1-25*x)^(1/5).
; Submitted by Jon Maiga
; 1,-5,-50,-750,-13125,-249375,-4987500,-103312500,-2195390625,-47566796875,-1046469531250,-23307730468750,-524423935546875,-11900389306640625,-272008898437500000,-6256204664062500000,-144674732856445312500,-3361559969311523437500,-78436399283935546875000,-1837063035860595703125000,-43170981342723999023437500,-1017601703078494262695312500,-24052403890946228027343750000,-569937396546334533691406250000,-13536013167975445175170898437500,-322157113397815595169067382812500
mul $0,2
mov $1,1
mov $2,1
mov $3,$0
mov $4,5
lpb $3
mul $1,$2
mul $1,$4
sub $3,2
mov $4,$2
sub $5,1
div $1,$5
sub $2,5
sub $4,$2
lpe
mov $0,$1
|
SECTION "Map_0523", ROM0[$B800]
Map_0523_Header:
hdr_tileset 0
hdr_dimensions 15, 9
hdr_pointers_a Map_0523_Blocks, Map_0523_TextPointers
hdr_pointers_b Map_0523_Script, Map_0523_Objects
hdr_pointers_c Map_0523_InitScript, Map_0523_RAMScript
hdr_palette $06
hdr_music MUSIC_ROUTES3, AUDIO_1
hdr_connection NORTH, $062F, 16, 26
hdr_connection SOUTH, $0210, 7, 1
hdr_connection WEST, $0000, 0, 0
hdr_connection EAST, $0000, 0, 0
Map_0523_Objects:
hdr_border $0f
hdr_warp_count 1
hdr_warp 10, 5, 5, 11, $0565
hdr_sign_count 1
hdr_signpost 11, 7, $03
hdr_object_count 2
hdr_object SPRITE_BALDING_GUY, 22, 7, STAY, NONE, $01
hdr_object SPRITE_BLACKBELT, 5, 10, STAY, NONE, $02
Map_0523_RAMScript:
rs_write_3 $c70b, $74, $31, $4d
rs_write_3 $c720, $0a, $31, $4d
rs_write_3 $c7e9, $0a, $31, $0a
rs_write_3 $c7fe, $0a, $31, $74
rs_end
Map_0523_Blocks:
db $0f,$0f,$0f,$0f,$68,$7f,$7f,$69,$0f,$0f,$0f,$0a,$31,$4d,$0f
db $0f,$0f,$0f,$0f,$68,$7f,$7f,$69,$0f,$0f,$0f,$74,$31,$4d,$0f
db $0f,$0f,$0f,$0f,$37,$3a,$7d,$7e,$0f,$0f,$0f,$0a,$31,$4d,$0f
db $0f,$0f,$0a,$74,$0a,$08,$0a,$74,$0a,$0a,$74,$0a,$31,$4d,$0f
db $0f,$0f,$0a,$31,$31,$31,$31,$31,$31,$31,$31,$31,$31,$4d,$0f
db $0f,$0f,$74,$31,$0a,$52,$52,$52,$52,$52,$52,$52,$52,$4f,$0f
db $0f,$0f,$0a,$31,$74,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f
db $0f,$0f,$0a,$31,$0a,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f
db $0f,$0f,$74,$31,$0a,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f
Map_0523_TextPointers:
dw Map_0523_TX1
dw Map_0523_TX2
dw Map_0523_TX3
Map_0523_InitScript:
ret
Map_0523_Script:
ret
Map_0523_TX1:
db 8
jp EnhancedTextOnly
text "The Glitch Research Lab in"
next "Northern Glitchland is well"
cont "known for its discoveries"
cont "in the field of glitchology."
done
Map_0523_TX2:
db 8
jp EnhancedTextOnly
text "Living near the Glitch"
next "Research Lab is a real"
cont "struggle..."
para "They keep playing the GSC"
next "Lucky Channel theme every"
cont "single night..."
para "And on the weekends, the"
next "SM64 File Select theme."
para "It's seriously driving me"
next "crazy. I'm moving away!"
done
Map_0523_TX3:
db 8
jp EnhancedTextOnly
text "NORTHERN GLITCHLAND"
next "GLITCH RESEARCH LAB"
done
|
; A077997: Expansion of (1-x)/(1-2*x-x^2-x^3).
; 1,1,3,8,20,51,130,331,843,2147,5468,13926,35467,90328,230049,585893,1492163,3800268,9678592,24649615,62778090,159884387,407196479,1037055435,2641191736,6726635386,17131517943,43630863008,111119879345,283002139641,720755021635,1835632062256,4675021285788,11906429655467,30323512658978,77228476259211,196686894832867,500925778583923,1275766928259924,3249146529936638,8274985766717123,21074884991630808,53673902279915377,136697675318178685,348144137907903555,886659853413901172,2258161520053884584
mov $1,1
mov $3,1
lpb $0
sub $0,1
add $2,$3
sub $3,$1
add $1,$3
add $1,$3
sub $1,$2
add $3,$2
lpe
add $0,1
mov $1,3
sub $3,$0
add $1,$3
sub $1,2
mov $0,$1
|
//===- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass -------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file This file contains a pass that performs load / store related peephole
/// optimizations. This pass should be run after register allocation.
//
//===----------------------------------------------------------------------===//
#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMISelLowering.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <utility>
using namespace llvm;
#define DEBUG_TYPE "arm-ldst-opt"
STATISTIC(NumLDMGened , "Number of ldm instructions generated");
STATISTIC(NumSTMGened , "Number of stm instructions generated");
STATISTIC(NumVLDMGened, "Number of vldm instructions generated");
STATISTIC(NumVSTMGened, "Number of vstm instructions generated");
STATISTIC(NumLdStMoved, "Number of load / store instructions moved");
STATISTIC(NumLDRDFormed,"Number of ldrd created before allocation");
STATISTIC(NumSTRDFormed,"Number of strd created before allocation");
STATISTIC(NumLDRD2LDM, "Number of ldrd instructions turned back into ldm");
STATISTIC(NumSTRD2STM, "Number of strd instructions turned back into stm");
STATISTIC(NumLDRD2LDR, "Number of ldrd instructions turned back into ldr's");
STATISTIC(NumSTRD2STR, "Number of strd instructions turned back into str's");
/// This switch disables formation of double/multi instructions that could
/// potentially lead to (new) alignment traps even with CCR.UNALIGN_TRP
/// disabled. This can be used to create libraries that are robust even when
/// users provoke undefined behaviour by supplying misaligned pointers.
/// \see mayCombineMisaligned()
static cl::opt<bool>
AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
cl::init(false), cl::desc("Be more conservative in ARM load/store opt"));
#define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
namespace {
/// Post- register allocation pass the combine load / store instructions to
/// form ldm / stm instructions.
struct ARMLoadStoreOpt : public MachineFunctionPass {
static char ID;
const MachineFunction *MF;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
const ARMSubtarget *STI;
const TargetLowering *TL;
ARMFunctionInfo *AFI;
LivePhysRegs LiveRegs;
RegisterClassInfo RegClassInfo;
MachineBasicBlock::const_iterator LiveRegPos;
bool LiveRegsValid;
bool RegClassInfoValid;
bool isThumb1, isThumb2;
ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs);
}
StringRef getPassName() const override { return ARM_LOAD_STORE_OPT_NAME; }
private:
/// A set of load/store MachineInstrs with same base register sorted by
/// offset.
struct MemOpQueueEntry {
MachineInstr *MI;
int Offset; ///< Load/Store offset.
unsigned Position; ///< Position as counted from end of basic block.
MemOpQueueEntry(MachineInstr &MI, int Offset, unsigned Position)
: MI(&MI), Offset(Offset), Position(Position) {}
};
using MemOpQueue = SmallVector<MemOpQueueEntry, 8>;
/// A set of MachineInstrs that fulfill (nearly all) conditions to get
/// merged into a LDM/STM.
struct MergeCandidate {
/// List of instructions ordered by load/store offset.
SmallVector<MachineInstr*, 4> Instrs;
/// Index in Instrs of the instruction being latest in the schedule.
unsigned LatestMIIdx;
/// Index in Instrs of the instruction being earliest in the schedule.
unsigned EarliestMIIdx;
/// Index into the basic block where the merged instruction will be
/// inserted. (See MemOpQueueEntry.Position)
unsigned InsertPos;
/// Whether the instructions can be merged into a ldm/stm instruction.
bool CanMergeToLSMulti;
/// Whether the instructions can be merged into a ldrd/strd instruction.
bool CanMergeToLSDouble;
};
SpecificBumpPtrAllocator<MergeCandidate> Allocator;
SmallVector<const MergeCandidate*,4> Candidates;
SmallVector<MachineInstr*,4> MergeBaseCandidates;
void moveLiveRegsBefore(const MachineBasicBlock &MBB,
MachineBasicBlock::const_iterator Before);
unsigned findFreeReg(const TargetRegisterClass &RegClass);
void UpdateBaseRegUses(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
unsigned Base, unsigned WordOffset,
ARMCC::CondCodes Pred, unsigned PredReg);
MachineInstr *CreateLoadStoreMulti(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
ArrayRef<std::pair<unsigned, bool>> Regs,
ArrayRef<MachineInstr*> Instrs);
MachineInstr *CreateLoadStoreDouble(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
ArrayRef<std::pair<unsigned, bool>> Regs,
ArrayRef<MachineInstr*> Instrs) const;
void FormCandidates(const MemOpQueue &MemOps);
MachineInstr *MergeOpsUpdate(const MergeCandidate &Cand);
bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI);
bool MergeBaseUpdateLoadStore(MachineInstr *MI);
bool MergeBaseUpdateLSMultiple(MachineInstr *MI);
bool MergeBaseUpdateLSDouble(MachineInstr &MI) const;
bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
bool CombineMovBx(MachineBasicBlock &MBB);
};
} // end anonymous namespace
char ARMLoadStoreOpt::ID = 0;
INITIALIZE_PASS(ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false,
false)
static bool definesCPSR(const MachineInstr &MI) {
for (const auto &MO : MI.operands()) {
if (!MO.isReg())
continue;
if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
// If the instruction has live CPSR def, then it's not safe to fold it
// into load / store.
return true;
}
return false;
}
static int getMemoryOpOffset(const MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
unsigned NumOperands = MI.getDesc().getNumOperands();
unsigned OffField = MI.getOperand(NumOperands - 3).getImm();
if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
return OffField;
// Thumb1 immediate offsets are scaled by 4
if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi ||
Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
return OffField * 4;
int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField)
: ARM_AM::getAM5Offset(OffField) * 4;
ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField)
: ARM_AM::getAM5Op(OffField);
if (Op == ARM_AM::sub)
return -Offset;
return Offset;
}
static const MachineOperand &getLoadStoreBaseOp(const MachineInstr &MI) {
return MI.getOperand(1);
}
static const MachineOperand &getLoadStoreRegOp(const MachineInstr &MI) {
return MI.getOperand(0);
}
static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) {
switch (Opcode) {
default: llvm_unreachable("Unhandled opcode!");
case ARM::LDRi12:
++NumLDMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::LDMIA;
case ARM_AM::da: return ARM::LDMDA;
case ARM_AM::db: return ARM::LDMDB;
case ARM_AM::ib: return ARM::LDMIB;
}
case ARM::STRi12:
++NumSTMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::STMIA;
case ARM_AM::da: return ARM::STMDA;
case ARM_AM::db: return ARM::STMDB;
case ARM_AM::ib: return ARM::STMIB;
}
case ARM::tLDRi:
case ARM::tLDRspi:
// tLDMIA is writeback-only - unless the base register is in the input
// reglist.
++NumLDMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::tLDMIA;
}
case ARM::tSTRi:
case ARM::tSTRspi:
// There is no non-writeback tSTMIA either.
++NumSTMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::tSTMIA_UPD;
}
case ARM::t2LDRi8:
case ARM::t2LDRi12:
++NumLDMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::t2LDMIA;
case ARM_AM::db: return ARM::t2LDMDB;
}
case ARM::t2STRi8:
case ARM::t2STRi12:
++NumSTMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::t2STMIA;
case ARM_AM::db: return ARM::t2STMDB;
}
case ARM::VLDRS:
++NumVLDMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VLDMSIA;
case ARM_AM::db: return 0; // Only VLDMSDB_UPD exists.
}
case ARM::VSTRS:
++NumVSTMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VSTMSIA;
case ARM_AM::db: return 0; // Only VSTMSDB_UPD exists.
}
case ARM::VLDRD:
++NumVLDMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VLDMDIA;
case ARM_AM::db: return 0; // Only VLDMDDB_UPD exists.
}
case ARM::VSTRD:
++NumVSTMGened;
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VSTMDIA;
case ARM_AM::db: return 0; // Only VSTMDDB_UPD exists.
}
}
}
static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(unsigned Opcode) {
switch (Opcode) {
default: llvm_unreachable("Unhandled opcode!");
case ARM::LDMIA_RET:
case ARM::LDMIA:
case ARM::LDMIA_UPD:
case ARM::STMIA:
case ARM::STMIA_UPD:
case ARM::tLDMIA:
case ARM::tLDMIA_UPD:
case ARM::tSTMIA_UPD:
case ARM::t2LDMIA_RET:
case ARM::t2LDMIA:
case ARM::t2LDMIA_UPD:
case ARM::t2STMIA:
case ARM::t2STMIA_UPD:
case ARM::VLDMSIA:
case ARM::VLDMSIA_UPD:
case ARM::VSTMSIA:
case ARM::VSTMSIA_UPD:
case ARM::VLDMDIA:
case ARM::VLDMDIA_UPD:
case ARM::VSTMDIA:
case ARM::VSTMDIA_UPD:
return ARM_AM::ia;
case ARM::LDMDA:
case ARM::LDMDA_UPD:
case ARM::STMDA:
case ARM::STMDA_UPD:
return ARM_AM::da;
case ARM::LDMDB:
case ARM::LDMDB_UPD:
case ARM::STMDB:
case ARM::STMDB_UPD:
case ARM::t2LDMDB:
case ARM::t2LDMDB_UPD:
case ARM::t2STMDB:
case ARM::t2STMDB_UPD:
case ARM::VLDMSDB_UPD:
case ARM::VSTMSDB_UPD:
case ARM::VLDMDDB_UPD:
case ARM::VSTMDDB_UPD:
return ARM_AM::db;
case ARM::LDMIB:
case ARM::LDMIB_UPD:
case ARM::STMIB:
case ARM::STMIB_UPD:
return ARM_AM::ib;
}
}
static bool isT1i32Load(unsigned Opc) {
return Opc == ARM::tLDRi || Opc == ARM::tLDRspi;
}
static bool isT2i32Load(unsigned Opc) {
return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
}
static bool isi32Load(unsigned Opc) {
return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ;
}
static bool isT1i32Store(unsigned Opc) {
return Opc == ARM::tSTRi || Opc == ARM::tSTRspi;
}
static bool isT2i32Store(unsigned Opc) {
return Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8;
}
static bool isi32Store(unsigned Opc) {
return Opc == ARM::STRi12 || isT1i32Store(Opc) || isT2i32Store(Opc);
}
static bool isLoadSingle(unsigned Opc) {
return isi32Load(Opc) || Opc == ARM::VLDRS || Opc == ARM::VLDRD;
}
static unsigned getImmScale(unsigned Opc) {
switch (Opc) {
default: llvm_unreachable("Unhandled opcode!");
case ARM::tLDRi:
case ARM::tSTRi:
case ARM::tLDRspi:
case ARM::tSTRspi:
return 1;
case ARM::tLDRHi:
case ARM::tSTRHi:
return 2;
case ARM::tLDRBi:
case ARM::tSTRBi:
return 4;
}
}
static unsigned getLSMultipleTransferSize(const MachineInstr *MI) {
switch (MI->getOpcode()) {
default: return 0;
case ARM::LDRi12:
case ARM::STRi12:
case ARM::tLDRi:
case ARM::tSTRi:
case ARM::tLDRspi:
case ARM::tSTRspi:
case ARM::t2LDRi8:
case ARM::t2LDRi12:
case ARM::t2STRi8:
case ARM::t2STRi12:
case ARM::VLDRS:
case ARM::VSTRS:
return 4;
case ARM::VLDRD:
case ARM::VSTRD:
return 8;
case ARM::LDMIA:
case ARM::LDMDA:
case ARM::LDMDB:
case ARM::LDMIB:
case ARM::STMIA:
case ARM::STMDA:
case ARM::STMDB:
case ARM::STMIB:
case ARM::tLDMIA:
case ARM::tLDMIA_UPD:
case ARM::tSTMIA_UPD:
case ARM::t2LDMIA:
case ARM::t2LDMDB:
case ARM::t2STMIA:
case ARM::t2STMDB:
case ARM::VLDMSIA:
case ARM::VSTMSIA:
return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 4;
case ARM::VLDMDIA:
case ARM::VSTMDIA:
return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 8;
}
}
/// Update future uses of the base register with the offset introduced
/// due to writeback. This function only works on Thumb1.
void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, unsigned Base,
unsigned WordOffset,
ARMCC::CondCodes Pred,
unsigned PredReg) {
assert(isThumb1 && "Can only update base register uses for Thumb1!");
// Start updating any instructions with immediate offsets. Insert a SUB before
// the first non-updateable instruction (if any).
for (; MBBI != MBB.end(); ++MBBI) {
bool InsertSub = false;
unsigned Opc = MBBI->getOpcode();
if (MBBI->readsRegister(Base)) {
int Offset;
bool IsLoad =
Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi;
bool IsStore =
Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi;
if (IsLoad || IsStore) {
// Loads and stores with immediate offsets can be updated, but only if
// the new offset isn't negative.
// The MachineOperand containing the offset immediate is the last one
// before predicates.
MachineOperand &MO =
MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
// The offsets are scaled by 1, 2 or 4 depending on the Opcode.
Offset = MO.getImm() - WordOffset * getImmScale(Opc);
// If storing the base register, it needs to be reset first.
Register InstrSrcReg = getLoadStoreRegOp(*MBBI).getReg();
if (Offset >= 0 && !(IsStore && InstrSrcReg == Base))
MO.setImm(Offset);
else
InsertSub = true;
} else if ((Opc == ARM::tSUBi8 || Opc == ARM::tADDi8) &&
!definesCPSR(*MBBI)) {
// SUBS/ADDS using this register, with a dead def of the CPSR.
// Merge it with the update; if the merged offset is too large,
// insert a new sub instead.
MachineOperand &MO =
MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
Offset = (Opc == ARM::tSUBi8) ?
MO.getImm() + WordOffset * 4 :
MO.getImm() - WordOffset * 4 ;
if (Offset >= 0 && TL->isLegalAddImmediate(Offset)) {
// FIXME: Swap ADDS<->SUBS if Offset < 0, erase instruction if
// Offset == 0.
MO.setImm(Offset);
// The base register has now been reset, so exit early.
return;
} else {
InsertSub = true;
}
} else {
// Can't update the instruction.
InsertSub = true;
}
} else if (definesCPSR(*MBBI) || MBBI->isCall() || MBBI->isBranch()) {
// Since SUBS sets the condition flags, we can't place the base reset
// after an instruction that has a live CPSR def.
// The base register might also contain an argument for a function call.
InsertSub = true;
}
if (InsertSub) {
// An instruction above couldn't be updated, so insert a sub.
BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
.add(t1CondCodeOp(true))
.addReg(Base)
.addImm(WordOffset * 4)
.addImm(Pred)
.addReg(PredReg);
return;
}
if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base))
// Register got killed. Stop updating.
return;
}
// End of block was reached.
if (!MBB.succ_empty()) {
// FIXME: Because of a bug, live registers are sometimes missing from
// the successor blocks' live-in sets. This means we can't trust that
// information and *always* have to reset at the end of a block.
// See PR21029.
if (MBBI != MBB.end()) --MBBI;
BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
.add(t1CondCodeOp(true))
.addReg(Base)
.addImm(WordOffset * 4)
.addImm(Pred)
.addReg(PredReg);
}
}
/// Return the first register of class \p RegClass that is not in \p Regs.
unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
if (!RegClassInfoValid) {
RegClassInfo.runOnMachineFunction(*MF);
RegClassInfoValid = true;
}
for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
if (LiveRegs.available(MF->getRegInfo(), Reg))
return Reg;
return 0;
}
/// Compute live registers just before instruction \p Before (in normal schedule
/// direction). Computes backwards so multiple queries in the same block must
/// come in reverse order.
void ARMLoadStoreOpt::moveLiveRegsBefore(const MachineBasicBlock &MBB,
MachineBasicBlock::const_iterator Before) {
// Initialize if we never queried in this block.
if (!LiveRegsValid) {
LiveRegs.init(*TRI);
LiveRegs.addLiveOuts(MBB);
LiveRegPos = MBB.end();
LiveRegsValid = true;
}
// Move backward just before the "Before" position.
while (LiveRegPos != Before) {
--LiveRegPos;
LiveRegs.stepBackward(*LiveRegPos);
}
}
static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,
unsigned Reg) {
for (const std::pair<unsigned, bool> &R : Regs)
if (R.first == Reg)
return true;
return false;
}
/// Create and insert a LDM or STM with Base as base register and registers in
/// Regs as the register operands that would be loaded / stored. It returns
/// true if the transformation is done.
MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
ArrayRef<std::pair<unsigned, bool>> Regs,
ArrayRef<MachineInstr*> Instrs) {
unsigned NumRegs = Regs.size();
assert(NumRegs > 1);
// For Thumb1 targets, it might be necessary to clobber the CPSR to merge.
// Compute liveness information for that register to make the decision.
bool SafeToClobberCPSR = !isThumb1 ||
(MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) ==
MachineBasicBlock::LQR_Dead);
bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
// Exception: If the base register is in the input reglist, Thumb1 LDM is
// non-writeback.
// It's also not possible to merge an STR of the base register in Thumb1.
if (isThumb1 && ContainsReg(Regs, Base)) {
assert(Base != ARM::SP && "Thumb1 does not allow SP in register list");
if (Opcode == ARM::tLDRi)
Writeback = false;
else if (Opcode == ARM::tSTRi)
return nullptr;
}
ARM_AM::AMSubMode Mode = ARM_AM::ia;
// VFP and Thumb2 do not support IB or DA modes. Thumb1 only supports IA.
bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1;
if (Offset == 4 && haveIBAndDA) {
Mode = ARM_AM::ib;
} else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) {
Mode = ARM_AM::da;
} else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) {
// VLDM/VSTM do not support DB mode without also updating the base reg.
Mode = ARM_AM::db;
} else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
// Check if this is a supported opcode before inserting instructions to
// calculate a new base register.
if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return nullptr;
// If starting offset isn't zero, insert a MI to materialize a new base.
// But only do so if it is cost effective, i.e. merging more than two
// loads / stores.
if (NumRegs <= 2)
return nullptr;
// On Thumb1, it's not worth materializing a new base register without
// clobbering the CPSR (i.e. not using ADDS/SUBS).
if (!SafeToClobberCPSR)
return nullptr;
unsigned NewBase;
if (isi32Load(Opcode)) {
// If it is a load, then just use one of the destination registers
// as the new base. Will no longer be writeback in Thumb1.
NewBase = Regs[NumRegs-1].first;
Writeback = false;
} else {
// Find a free register that we can use as scratch register.
moveLiveRegsBefore(MBB, InsertBefore);
// The merged instruction does not exist yet but will use several Regs if
// it is a Store.
if (!isLoadSingle(Opcode))
for (const std::pair<unsigned, bool> &R : Regs)
LiveRegs.addReg(R.first);
NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass);
if (NewBase == 0)
return nullptr;
}
int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm
: ARM::t2ADDri)
: (isThumb1 && Base == ARM::SP)
? ARM::tADDrSPi
: (isThumb1 && Offset < 8)
? ARM::tADDi3
: isThumb1 ? ARM::tADDi8 : ARM::ADDri;
if (Offset < 0) {
// FIXME: There are no Thumb1 load/store instructions with negative
// offsets. So the Base != ARM::SP might be unnecessary.
Offset = -Offset;
BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm
: ARM::t2SUBri)
: (isThumb1 && Offset < 8 && Base != ARM::SP)
? ARM::tSUBi3
: isThumb1 ? ARM::tSUBi8 : ARM::SUBri;
}
if (!TL->isLegalAddImmediate(Offset))
// FIXME: Try add with register operand?
return nullptr; // Probably not worth it then.
// We can only append a kill flag to the add/sub input if the value is not
// used in the register list of the stm as well.
bool KillOldBase = BaseKill &&
(!isi32Store(Opcode) || !ContainsReg(Regs, Base));
if (isThumb1) {
// Thumb1: depending on immediate size, use either
// ADDS NewBase, Base, #imm3
// or
// MOV NewBase, Base
// ADDS NewBase, #imm8.
if (Base != NewBase &&
(BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) {
// Need to insert a MOV to the new base first.
if (isARMLowRegister(NewBase) && isARMLowRegister(Base) &&
!STI->hasV6Ops()) {
// thumbv4t doesn't have lo->lo copies, and we can't predicate tMOVSr
if (Pred != ARMCC::AL)
return nullptr;
BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase)
.addReg(Base, getKillRegState(KillOldBase));
} else
BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase)
.addReg(Base, getKillRegState(KillOldBase))
.add(predOps(Pred, PredReg));
// The following ADDS/SUBS becomes an update.
Base = NewBase;
KillOldBase = true;
}
if (BaseOpc == ARM::tADDrSPi) {
assert(Offset % 4 == 0 && "tADDrSPi offset is scaled by 4");
BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
.addReg(Base, getKillRegState(KillOldBase))
.addImm(Offset / 4)
.add(predOps(Pred, PredReg));
} else
BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
.add(t1CondCodeOp(true))
.addReg(Base, getKillRegState(KillOldBase))
.addImm(Offset)
.add(predOps(Pred, PredReg));
} else {
BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
.addReg(Base, getKillRegState(KillOldBase))
.addImm(Offset)
.add(predOps(Pred, PredReg))
.add(condCodeOp());
}
Base = NewBase;
BaseKill = true; // New base is always killed straight away.
}
bool isDef = isLoadSingle(Opcode);
// Get LS multiple opcode. Note that for Thumb1 this might be an opcode with
// base register writeback.
Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
if (!Opcode)
return nullptr;
// Check if a Thumb1 LDM/STM merge is safe. This is the case if:
// - There is no writeback (LDM of base register),
// - the base register is killed by the merged instruction,
// - or it's safe to overwrite the condition flags, i.e. to insert a SUBS
// to reset the base register.
// Otherwise, don't merge.
// It's safe to return here since the code to materialize a new base register
// above is also conditional on SafeToClobberCPSR.
if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)
return nullptr;
MachineInstrBuilder MIB;
if (Writeback) {
assert(isThumb1 && "expected Writeback only inThumb1");
if (Opcode == ARM::tLDMIA) {
assert(!(ContainsReg(Regs, Base)) && "Thumb1 can't LDM ! with Base in Regs");
// Update tLDMIA with writeback if necessary.
Opcode = ARM::tLDMIA_UPD;
}
MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
// Thumb1: we might need to set base writeback when building the MI.
MIB.addReg(Base, getDefRegState(true))
.addReg(Base, getKillRegState(BaseKill));
// The base isn't dead after a merged instruction with writeback.
// Insert a sub instruction after the newly formed instruction to reset.
if (!BaseKill)
UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
} else {
// No writeback, simply build the MachineInstr.
MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
MIB.addReg(Base, getKillRegState(BaseKill));
}
MIB.addImm(Pred).addReg(PredReg);
for (const std::pair<unsigned, bool> &R : Regs)
MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
MIB.cloneMergedMemRefs(Instrs);
return MIB.getInstr();
}
MachineInstr *ARMLoadStoreOpt::CreateLoadStoreDouble(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
ArrayRef<std::pair<unsigned, bool>> Regs,
ArrayRef<MachineInstr*> Instrs) const {
bool IsLoad = isi32Load(Opcode);
assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");
unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8;
assert(Regs.size() == 2);
MachineInstrBuilder MIB = BuildMI(MBB, InsertBefore, DL,
TII->get(LoadStoreOpcode));
if (IsLoad) {
MIB.addReg(Regs[0].first, RegState::Define)
.addReg(Regs[1].first, RegState::Define);
} else {
MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
.addReg(Regs[1].first, getKillRegState(Regs[1].second));
}
MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
MIB.cloneMergedMemRefs(Instrs);
return MIB.getInstr();
}
/// Call MergeOps and update MemOps and merges accordingly on success.
MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) {
const MachineInstr *First = Cand.Instrs.front();
unsigned Opcode = First->getOpcode();
bool IsLoad = isLoadSingle(Opcode);
SmallVector<std::pair<unsigned, bool>, 8> Regs;
SmallVector<unsigned, 4> ImpDefs;
DenseSet<unsigned> KilledRegs;
DenseSet<unsigned> UsedRegs;
// Determine list of registers and list of implicit super-register defs.
for (const MachineInstr *MI : Cand.Instrs) {
const MachineOperand &MO = getLoadStoreRegOp(*MI);
Register Reg = MO.getReg();
bool IsKill = MO.isKill();
if (IsKill)
KilledRegs.insert(Reg);
Regs.push_back(std::make_pair(Reg, IsKill));
UsedRegs.insert(Reg);
if (IsLoad) {
// Collect any implicit defs of super-registers, after merging we can't
// be sure anymore that we properly preserved these live ranges and must
// removed these implicit operands.
for (const MachineOperand &MO : MI->implicit_operands()) {
if (!MO.isReg() || !MO.isDef() || MO.isDead())
continue;
assert(MO.isImplicit());
Register DefReg = MO.getReg();
if (is_contained(ImpDefs, DefReg))
continue;
// We can ignore cases where the super-reg is read and written.
if (MI->readsRegister(DefReg))
continue;
ImpDefs.push_back(DefReg);
}
}
}
// Attempt the merge.
using iterator = MachineBasicBlock::iterator;
MachineInstr *LatestMI = Cand.Instrs[Cand.LatestMIIdx];
iterator InsertBefore = std::next(iterator(LatestMI));
MachineBasicBlock &MBB = *LatestMI->getParent();
unsigned Offset = getMemoryOpOffset(*First);
Register Base = getLoadStoreBaseOp(*First).getReg();
bool BaseKill = LatestMI->killsRegister(Base);
Register PredReg;
ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
DebugLoc DL = First->getDebugLoc();
MachineInstr *Merged = nullptr;
if (Cand.CanMergeToLSDouble)
Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,
Opcode, Pred, PredReg, DL, Regs,
Cand.Instrs);
if (!Merged && Cand.CanMergeToLSMulti)
Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,
Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);
if (!Merged)
return nullptr;
// Determine earliest instruction that will get removed. We then keep an
// iterator just above it so the following erases don't invalidated it.
iterator EarliestI(Cand.Instrs[Cand.EarliestMIIdx]);
bool EarliestAtBegin = false;
if (EarliestI == MBB.begin()) {
EarliestAtBegin = true;
} else {
EarliestI = std::prev(EarliestI);
}
// Remove instructions which have been merged.
for (MachineInstr *MI : Cand.Instrs)
MBB.erase(MI);
// Determine range between the earliest removed instruction and the new one.
if (EarliestAtBegin)
EarliestI = MBB.begin();
else
EarliestI = std::next(EarliestI);
auto FixupRange = make_range(EarliestI, iterator(Merged));
if (isLoadSingle(Opcode)) {
// If the previous loads defined a super-reg, then we have to mark earlier
// operands undef; Replicate the super-reg def on the merged instruction.
for (MachineInstr &MI : FixupRange) {
for (unsigned &ImpDefReg : ImpDefs) {
for (MachineOperand &MO : MI.implicit_operands()) {
if (!MO.isReg() || MO.getReg() != ImpDefReg)
continue;
if (MO.readsReg())
MO.setIsUndef();
else if (MO.isDef())
ImpDefReg = 0;
}
}
}
MachineInstrBuilder MIB(*Merged->getParent()->getParent(), Merged);
for (unsigned ImpDef : ImpDefs)
MIB.addReg(ImpDef, RegState::ImplicitDefine);
} else {
// Remove kill flags: We are possibly storing the values later now.
assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD);
for (MachineInstr &MI : FixupRange) {
for (MachineOperand &MO : MI.uses()) {
if (!MO.isReg() || !MO.isKill())
continue;
if (UsedRegs.count(MO.getReg()))
MO.setIsKill(false);
}
}
assert(ImpDefs.empty());
}
return Merged;
}
static bool isValidLSDoubleOffset(int Offset) {
unsigned Value = abs(Offset);
// t2LDRDi8/t2STRDi8 supports an 8 bit immediate which is internally
// multiplied by 4.
return (Value % 4) == 0 && Value < 1024;
}
/// Return true for loads/stores that can be combined to a double/multi
/// operation without increasing the requirements for alignment.
static bool mayCombineMisaligned(const TargetSubtargetInfo &STI,
const MachineInstr &MI) {
// vldr/vstr trap on misaligned pointers anyway, forming vldm makes no
// difference.
unsigned Opcode = MI.getOpcode();
if (!isi32Load(Opcode) && !isi32Store(Opcode))
return true;
// Stack pointer alignment is out of the programmers control so we can trust
// SP-relative loads/stores.
if (getLoadStoreBaseOp(MI).getReg() == ARM::SP &&
STI.getFrameLowering()->getTransientStackAlign() >= Align(4))
return true;
return false;
}
/// Find candidates for load/store multiple merge in list of MemOpQueueEntries.
void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) {
const MachineInstr *FirstMI = MemOps[0].MI;
unsigned Opcode = FirstMI->getOpcode();
bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
unsigned Size = getLSMultipleTransferSize(FirstMI);
unsigned SIndex = 0;
unsigned EIndex = MemOps.size();
do {
// Look at the first instruction.
const MachineInstr *MI = MemOps[SIndex].MI;
int Offset = MemOps[SIndex].Offset;
const MachineOperand &PMO = getLoadStoreRegOp(*MI);
Register PReg = PMO.getReg();
unsigned PRegNum = PMO.isUndef() ? std::numeric_limits<unsigned>::max()
: TRI->getEncodingValue(PReg);
unsigned Latest = SIndex;
unsigned Earliest = SIndex;
unsigned Count = 1;
bool CanMergeToLSDouble =
STI->isThumb2() && isNotVFP && isValidLSDoubleOffset(Offset);
// ARM errata 602117: LDRD with base in list may result in incorrect base
// register when interrupted or faulted.
if (STI->isCortexM3() && isi32Load(Opcode) &&
PReg == getLoadStoreBaseOp(*MI).getReg())
CanMergeToLSDouble = false;
bool CanMergeToLSMulti = true;
// On swift vldm/vstm starting with an odd register number as that needs
// more uops than single vldrs.
if (STI->hasSlowOddRegister() && !isNotVFP && (PRegNum % 2) == 1)
CanMergeToLSMulti = false;
// LDRD/STRD do not allow SP/PC. LDM/STM do not support it or have it
// deprecated; LDM to PC is fine but cannot happen here.
if (PReg == ARM::SP || PReg == ARM::PC)
CanMergeToLSMulti = CanMergeToLSDouble = false;
// Should we be conservative?
if (AssumeMisalignedLoadStores && !mayCombineMisaligned(*STI, *MI))
CanMergeToLSMulti = CanMergeToLSDouble = false;
// vldm / vstm limit are 32 for S variants, 16 for D variants.
unsigned Limit;
switch (Opcode) {
default:
Limit = UINT_MAX;
break;
case ARM::VLDRD:
case ARM::VSTRD:
Limit = 16;
break;
}
// Merge following instructions where possible.
for (unsigned I = SIndex+1; I < EIndex; ++I, ++Count) {
int NewOffset = MemOps[I].Offset;
if (NewOffset != Offset + (int)Size)
break;
const MachineOperand &MO = getLoadStoreRegOp(*MemOps[I].MI);
Register Reg = MO.getReg();
if (Reg == ARM::SP || Reg == ARM::PC)
break;
if (Count == Limit)
break;
// See if the current load/store may be part of a multi load/store.
unsigned RegNum = MO.isUndef() ? std::numeric_limits<unsigned>::max()
: TRI->getEncodingValue(Reg);
bool PartOfLSMulti = CanMergeToLSMulti;
if (PartOfLSMulti) {
// Register numbers must be in ascending order.
if (RegNum <= PRegNum)
PartOfLSMulti = false;
// For VFP / NEON load/store multiples, the registers must be
// consecutive and within the limit on the number of registers per
// instruction.
else if (!isNotVFP && RegNum != PRegNum+1)
PartOfLSMulti = false;
}
// See if the current load/store may be part of a double load/store.
bool PartOfLSDouble = CanMergeToLSDouble && Count <= 1;
if (!PartOfLSMulti && !PartOfLSDouble)
break;
CanMergeToLSMulti &= PartOfLSMulti;
CanMergeToLSDouble &= PartOfLSDouble;
// Track MemOp with latest and earliest position (Positions are
// counted in reverse).
unsigned Position = MemOps[I].Position;
if (Position < MemOps[Latest].Position)
Latest = I;
else if (Position > MemOps[Earliest].Position)
Earliest = I;
// Prepare for next MemOp.
Offset += Size;
PRegNum = RegNum;
}
// Form a candidate from the Ops collected so far.
MergeCandidate *Candidate = new(Allocator.Allocate()) MergeCandidate;
for (unsigned C = SIndex, CE = SIndex + Count; C < CE; ++C)
Candidate->Instrs.push_back(MemOps[C].MI);
Candidate->LatestMIIdx = Latest - SIndex;
Candidate->EarliestMIIdx = Earliest - SIndex;
Candidate->InsertPos = MemOps[Latest].Position;
if (Count == 1)
CanMergeToLSMulti = CanMergeToLSDouble = false;
Candidate->CanMergeToLSMulti = CanMergeToLSMulti;
Candidate->CanMergeToLSDouble = CanMergeToLSDouble;
Candidates.push_back(Candidate);
// Continue after the chain.
SIndex += Count;
} while (SIndex < EIndex);
}
static unsigned getUpdatingLSMultipleOpcode(unsigned Opc,
ARM_AM::AMSubMode Mode) {
switch (Opc) {
default: llvm_unreachable("Unhandled opcode!");
case ARM::LDMIA:
case ARM::LDMDA:
case ARM::LDMDB:
case ARM::LDMIB:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::LDMIA_UPD;
case ARM_AM::ib: return ARM::LDMIB_UPD;
case ARM_AM::da: return ARM::LDMDA_UPD;
case ARM_AM::db: return ARM::LDMDB_UPD;
}
case ARM::STMIA:
case ARM::STMDA:
case ARM::STMDB:
case ARM::STMIB:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::STMIA_UPD;
case ARM_AM::ib: return ARM::STMIB_UPD;
case ARM_AM::da: return ARM::STMDA_UPD;
case ARM_AM::db: return ARM::STMDB_UPD;
}
case ARM::t2LDMIA:
case ARM::t2LDMDB:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::t2LDMIA_UPD;
case ARM_AM::db: return ARM::t2LDMDB_UPD;
}
case ARM::t2STMIA:
case ARM::t2STMDB:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::t2STMIA_UPD;
case ARM_AM::db: return ARM::t2STMDB_UPD;
}
case ARM::VLDMSIA:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VLDMSIA_UPD;
case ARM_AM::db: return ARM::VLDMSDB_UPD;
}
case ARM::VLDMDIA:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VLDMDIA_UPD;
case ARM_AM::db: return ARM::VLDMDDB_UPD;
}
case ARM::VSTMSIA:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VSTMSIA_UPD;
case ARM_AM::db: return ARM::VSTMSDB_UPD;
}
case ARM::VSTMDIA:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VSTMDIA_UPD;
case ARM_AM::db: return ARM::VSTMDDB_UPD;
}
}
}
/// Check if the given instruction increments or decrements a register and
/// return the amount it is incremented/decremented. Returns 0 if the CPSR flags
/// generated by the instruction are possibly read as well.
static int isIncrementOrDecrement(const MachineInstr &MI, Register Reg,
ARMCC::CondCodes Pred, Register PredReg) {
bool CheckCPSRDef;
int Scale;
switch (MI.getOpcode()) {
case ARM::tADDi8: Scale = 4; CheckCPSRDef = true; break;
case ARM::tSUBi8: Scale = -4; CheckCPSRDef = true; break;
case ARM::t2SUBri:
case ARM::t2SUBspImm:
case ARM::SUBri: Scale = -1; CheckCPSRDef = true; break;
case ARM::t2ADDri:
case ARM::t2ADDspImm:
case ARM::ADDri: Scale = 1; CheckCPSRDef = true; break;
case ARM::tADDspi: Scale = 4; CheckCPSRDef = false; break;
case ARM::tSUBspi: Scale = -4; CheckCPSRDef = false; break;
default: return 0;
}
Register MIPredReg;
if (MI.getOperand(0).getReg() != Reg ||
MI.getOperand(1).getReg() != Reg ||
getInstrPredicate(MI, MIPredReg) != Pred ||
MIPredReg != PredReg)
return 0;
if (CheckCPSRDef && definesCPSR(MI))
return 0;
return MI.getOperand(2).getImm() * Scale;
}
/// Searches for an increment or decrement of \p Reg before \p MBBI.
static MachineBasicBlock::iterator
findIncDecBefore(MachineBasicBlock::iterator MBBI, Register Reg,
ARMCC::CondCodes Pred, Register PredReg, int &Offset) {
Offset = 0;
MachineBasicBlock &MBB = *MBBI->getParent();
MachineBasicBlock::iterator BeginMBBI = MBB.begin();
MachineBasicBlock::iterator EndMBBI = MBB.end();
if (MBBI == BeginMBBI)
return EndMBBI;
// Skip debug values.
MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI);
while (PrevMBBI->isDebugInstr() && PrevMBBI != BeginMBBI)
--PrevMBBI;
Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
return Offset == 0 ? EndMBBI : PrevMBBI;
}
/// Searches for a increment or decrement of \p Reg after \p MBBI.
static MachineBasicBlock::iterator
findIncDecAfter(MachineBasicBlock::iterator MBBI, Register Reg,
ARMCC::CondCodes Pred, Register PredReg, int &Offset,
const TargetRegisterInfo *TRI) {
Offset = 0;
MachineBasicBlock &MBB = *MBBI->getParent();
MachineBasicBlock::iterator EndMBBI = MBB.end();
MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
while (NextMBBI != EndMBBI) {
// Skip debug values.
while (NextMBBI != EndMBBI && NextMBBI->isDebugInstr())
++NextMBBI;
if (NextMBBI == EndMBBI)
return EndMBBI;
unsigned Off = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);
if (Off) {
Offset = Off;
return NextMBBI;
}
// SP can only be combined if it is the next instruction after the original
// MBBI, otherwise we may be incrementing the stack pointer (invalidating
// anything below the new pointer) when its frame elements are still in
// use. Other registers can attempt to look further, until a different use
// or def of the register is found.
if (Reg == ARM::SP || NextMBBI->readsRegister(Reg, TRI) ||
NextMBBI->definesRegister(Reg, TRI))
return EndMBBI;
++NextMBBI;
}
return EndMBBI;
}
/// Fold proceeding/trailing inc/dec of base register into the
/// LDM/STM/VLDM{D|S}/VSTM{D|S} op when possible:
///
/// stmia rn, <ra, rb, rc>
/// rn := rn + 4 * 3;
/// =>
/// stmia rn!, <ra, rb, rc>
///
/// rn := rn - 4 * 3;
/// ldmia rn, <ra, rb, rc>
/// =>
/// ldmdb rn!, <ra, rb, rc>
bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
// Thumb1 is already using updating loads/stores.
if (isThumb1) return false;
LLVM_DEBUG(dbgs() << "Attempting to merge update of: " << *MI);
const MachineOperand &BaseOP = MI->getOperand(0);
Register Base = BaseOP.getReg();
bool BaseKill = BaseOP.isKill();
Register PredReg;
ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
unsigned Opcode = MI->getOpcode();
DebugLoc DL = MI->getDebugLoc();
// Can't use an updating ld/st if the base register is also a dest
// register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
if (MO.getReg() == Base)
return false;
int Bytes = getLSMultipleTransferSize(MI);
MachineBasicBlock &MBB = *MI->getParent();
MachineBasicBlock::iterator MBBI(MI);
int Offset;
MachineBasicBlock::iterator MergeInstr
= findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
ARM_AM::AMSubMode Mode = getLoadStoreMultipleSubMode(Opcode);
if (Mode == ARM_AM::ia && Offset == -Bytes) {
Mode = ARM_AM::db;
} else if (Mode == ARM_AM::ib && Offset == -Bytes) {
Mode = ARM_AM::da;
} else {
MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
if (((Mode != ARM_AM::ia && Mode != ARM_AM::ib) || Offset != Bytes) &&
((Mode != ARM_AM::da && Mode != ARM_AM::db) || Offset != -Bytes)) {
// We couldn't find an inc/dec to merge. But if the base is dead, we
// can still change to a writeback form as that will save us 2 bytes
// of code size. It can create WAW hazards though, so only do it if
// we're minimizing code size.
if (!STI->hasMinSize() || !BaseKill)
return false;
bool HighRegsUsed = false;
for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
if (MO.getReg() >= ARM::R8) {
HighRegsUsed = true;
break;
}
if (!HighRegsUsed)
MergeInstr = MBB.end();
else
return false;
}
}
if (MergeInstr != MBB.end()) {
LLVM_DEBUG(dbgs() << " Erasing old increment: " << *MergeInstr);
MBB.erase(MergeInstr);
}
unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
.addReg(Base, getDefRegState(true)) // WB base register
.addReg(Base, getKillRegState(BaseKill))
.addImm(Pred).addReg(PredReg);
// Transfer the rest of operands.
for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 3))
MIB.add(MO);
// Transfer memoperands.
MIB.setMemRefs(MI->memoperands());
LLVM_DEBUG(dbgs() << " Added new load/store: " << *MIB);
MBB.erase(MBBI);
return true;
}
static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc,
ARM_AM::AddrOpc Mode) {
switch (Opc) {
case ARM::LDRi12:
return ARM::LDR_PRE_IMM;
case ARM::STRi12:
return ARM::STR_PRE_IMM;
case ARM::VLDRS:
return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD;
case ARM::VLDRD:
return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD;
case ARM::VSTRS:
return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD;
case ARM::VSTRD:
return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD;
case ARM::t2LDRi8:
case ARM::t2LDRi12:
return ARM::t2LDR_PRE;
case ARM::t2STRi8:
case ARM::t2STRi12:
return ARM::t2STR_PRE;
default: llvm_unreachable("Unhandled opcode!");
}
}
static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc,
ARM_AM::AddrOpc Mode) {
switch (Opc) {
case ARM::LDRi12:
return ARM::LDR_POST_IMM;
case ARM::STRi12:
return ARM::STR_POST_IMM;
case ARM::VLDRS:
return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD;
case ARM::VLDRD:
return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD;
case ARM::VSTRS:
return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD;
case ARM::VSTRD:
return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD;
case ARM::t2LDRi8:
case ARM::t2LDRi12:
return ARM::t2LDR_POST;
case ARM::t2LDRBi8:
case ARM::t2LDRBi12:
return ARM::t2LDRB_POST;
case ARM::t2LDRSBi8:
case ARM::t2LDRSBi12:
return ARM::t2LDRSB_POST;
case ARM::t2LDRHi8:
case ARM::t2LDRHi12:
return ARM::t2LDRH_POST;
case ARM::t2LDRSHi8:
case ARM::t2LDRSHi12:
return ARM::t2LDRSH_POST;
case ARM::t2STRi8:
case ARM::t2STRi12:
return ARM::t2STR_POST;
case ARM::t2STRBi8:
case ARM::t2STRBi12:
return ARM::t2STRB_POST;
case ARM::t2STRHi8:
case ARM::t2STRHi12:
return ARM::t2STRH_POST;
case ARM::MVE_VLDRBS16:
return ARM::MVE_VLDRBS16_post;
case ARM::MVE_VLDRBS32:
return ARM::MVE_VLDRBS32_post;
case ARM::MVE_VLDRBU16:
return ARM::MVE_VLDRBU16_post;
case ARM::MVE_VLDRBU32:
return ARM::MVE_VLDRBU32_post;
case ARM::MVE_VLDRHS32:
return ARM::MVE_VLDRHS32_post;
case ARM::MVE_VLDRHU32:
return ARM::MVE_VLDRHU32_post;
case ARM::MVE_VLDRBU8:
return ARM::MVE_VLDRBU8_post;
case ARM::MVE_VLDRHU16:
return ARM::MVE_VLDRHU16_post;
case ARM::MVE_VLDRWU32:
return ARM::MVE_VLDRWU32_post;
case ARM::MVE_VSTRB16:
return ARM::MVE_VSTRB16_post;
case ARM::MVE_VSTRB32:
return ARM::MVE_VSTRB32_post;
case ARM::MVE_VSTRH32:
return ARM::MVE_VSTRH32_post;
case ARM::MVE_VSTRBU8:
return ARM::MVE_VSTRBU8_post;
case ARM::MVE_VSTRHU16:
return ARM::MVE_VSTRHU16_post;
case ARM::MVE_VSTRWU32:
return ARM::MVE_VSTRWU32_post;
default: llvm_unreachable("Unhandled opcode!");
}
}
/// Fold proceeding/trailing inc/dec of base register into the
/// LDR/STR/FLD{D|S}/FST{D|S} op when possible:
bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
// Thumb1 doesn't have updating LDR/STR.
// FIXME: Use LDM/STM with single register instead.
if (isThumb1) return false;
LLVM_DEBUG(dbgs() << "Attempting to merge update of: " << *MI);
Register Base = getLoadStoreBaseOp(*MI).getReg();
bool BaseKill = getLoadStoreBaseOp(*MI).isKill();
unsigned Opcode = MI->getOpcode();
DebugLoc DL = MI->getDebugLoc();
bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);
if (isi32Load(Opcode) || isi32Store(Opcode))
if (MI->getOperand(2).getImm() != 0)
return false;
if (isAM5 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
return false;
// Can't do the merge if the destination register is the same as the would-be
// writeback register.
if (MI->getOperand(0).getReg() == Base)
return false;
Register PredReg;
ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
int Bytes = getLSMultipleTransferSize(MI);
MachineBasicBlock &MBB = *MI->getParent();
MachineBasicBlock::iterator MBBI(MI);
int Offset;
MachineBasicBlock::iterator MergeInstr
= findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
unsigned NewOpc;
if (!isAM5 && Offset == Bytes) {
NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
} else if (Offset == -Bytes) {
NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
} else {
MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
if (MergeInstr == MBB.end())
return false;
NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
if ((isAM5 && Offset != Bytes) ||
(!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) {
NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII))
return false;
}
}
LLVM_DEBUG(dbgs() << " Erasing old increment: " << *MergeInstr);
MBB.erase(MergeInstr);
ARM_AM::AddrOpc AddSub = Offset < 0 ? ARM_AM::sub : ARM_AM::add;
bool isLd = isLoadSingle(Opcode);
if (isAM5) {
// VLDM[SD]_UPD, VSTM[SD]_UPD
// (There are no base-updating versions of VLDR/VSTR instructions, but the
// updating load/store-multiple instructions can be used with only one
// register.)
MachineOperand &MO = MI->getOperand(0);
auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
.addReg(Base, getDefRegState(true)) // WB base register
.addReg(Base, getKillRegState(isLd ? BaseKill : false))
.addImm(Pred)
.addReg(PredReg)
.addReg(MO.getReg(), (isLd ? getDefRegState(true)
: getKillRegState(MO.isKill())))
.cloneMemRefs(*MI);
(void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
} else if (isLd) {
if (isAM2) {
// LDR_PRE, LDR_POST
if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
auto MIB =
BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
.addReg(Base, RegState::Define)
.addReg(Base)
.addImm(Offset)
.addImm(Pred)
.addReg(PredReg)
.cloneMemRefs(*MI);
(void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
} else {
int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift);
auto MIB =
BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
.addReg(Base, RegState::Define)
.addReg(Base)
.addReg(0)
.addImm(Imm)
.add(predOps(Pred, PredReg))
.cloneMemRefs(*MI);
(void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
}
} else {
// t2LDR_PRE, t2LDR_POST
auto MIB =
BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
.addReg(Base, RegState::Define)
.addReg(Base)
.addImm(Offset)
.add(predOps(Pred, PredReg))
.cloneMemRefs(*MI);
(void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
}
} else {
MachineOperand &MO = MI->getOperand(0);
// FIXME: post-indexed stores use am2offset_imm, which still encodes
// the vestigal zero-reg offset register. When that's fixed, this clause
// can be removed entirely.
if (isAM2 && NewOpc == ARM::STR_POST_IMM) {
int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift);
// STR_PRE, STR_POST
auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
.addReg(MO.getReg(), getKillRegState(MO.isKill()))
.addReg(Base)
.addReg(0)
.addImm(Imm)
.add(predOps(Pred, PredReg))
.cloneMemRefs(*MI);
(void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
} else {
// t2STR_PRE, t2STR_POST
auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
.addReg(MO.getReg(), getKillRegState(MO.isKill()))
.addReg(Base)
.addImm(Offset)
.add(predOps(Pred, PredReg))
.cloneMemRefs(*MI);
(void)MIB;
LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
}
}
MBB.erase(MBBI);
return true;
}
bool ARMLoadStoreOpt::MergeBaseUpdateLSDouble(MachineInstr &MI) const {
unsigned Opcode = MI.getOpcode();
assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) &&
"Must have t2STRDi8 or t2LDRDi8");
if (MI.getOperand(3).getImm() != 0)
return false;
LLVM_DEBUG(dbgs() << "Attempting to merge update of: " << MI);
// Behaviour for writeback is undefined if base register is the same as one
// of the others.
const MachineOperand &BaseOp = MI.getOperand(2);
Register Base = BaseOp.getReg();
const MachineOperand &Reg0Op = MI.getOperand(0);
const MachineOperand &Reg1Op = MI.getOperand(1);
if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base)
return false;
Register PredReg;
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
MachineBasicBlock::iterator MBBI(MI);
MachineBasicBlock &MBB = *MI.getParent();
int Offset;
MachineBasicBlock::iterator MergeInstr = findIncDecBefore(MBBI, Base, Pred,
PredReg, Offset);
unsigned NewOpc;
if (Offset == 8 || Offset == -8) {
NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE;
} else {
MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
if (MergeInstr == MBB.end())
return false;
NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST;
if (!isLegalAddressImm(NewOpc, Offset, TII))
return false;
}
LLVM_DEBUG(dbgs() << " Erasing old increment: " << *MergeInstr);
MBB.erase(MergeInstr);
DebugLoc DL = MI.getDebugLoc();
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) {
MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define);
} else {
assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST);
MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op);
}
MIB.addReg(BaseOp.getReg(), RegState::Kill)
.addImm(Offset).addImm(Pred).addReg(PredReg);
assert(TII->get(Opcode).getNumOperands() == 6 &&
TII->get(NewOpc).getNumOperands() == 7 &&
"Unexpected number of operands in Opcode specification.");
// Transfer implicit operands.
for (const MachineOperand &MO : MI.implicit_operands())
MIB.add(MO);
MIB.cloneMemRefs(MI);
LLVM_DEBUG(dbgs() << " Added new load/store: " << *MIB);
MBB.erase(MBBI);
return true;
}
/// Returns true if instruction is a memory operation that this pass is capable
/// of operating on.
static bool isMemoryOp(const MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
switch (Opcode) {
case ARM::VLDRS:
case ARM::VSTRS:
case ARM::VLDRD:
case ARM::VSTRD:
case ARM::LDRi12:
case ARM::STRi12:
case ARM::tLDRi:
case ARM::tSTRi:
case ARM::tLDRspi:
case ARM::tSTRspi:
case ARM::t2LDRi8:
case ARM::t2LDRi12:
case ARM::t2STRi8:
case ARM::t2STRi12:
break;
default:
return false;
}
if (!MI.getOperand(1).isReg())
return false;
// When no memory operands are present, conservatively assume unaligned,
// volatile, unfoldable.
if (!MI.hasOneMemOperand())
return false;
const MachineMemOperand &MMO = **MI.memoperands_begin();
// Don't touch volatile memory accesses - we may be changing their order.
// TODO: We could allow unordered and monotonic atomics here, but we need to
// make sure the resulting ldm/stm is correctly marked as atomic.
if (MMO.isVolatile() || MMO.isAtomic())
return false;
// Unaligned ldr/str is emulated by some kernels, but unaligned ldm/stm is
// not.
if (MMO.getAlign() < Align(4))
return false;
// str <undef> could probably be eliminated entirely, but for now we just want
// to avoid making a mess of it.
// FIXME: Use str <undef> as a wildcard to enable better stm folding.
if (MI.getOperand(0).isReg() && MI.getOperand(0).isUndef())
return false;
// Likewise don't mess with references to undefined addresses.
if (MI.getOperand(1).isUndef())
return false;
return true;
}
static void InsertLDR_STR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI, int Offset,
bool isDef, unsigned NewOpc, unsigned Reg,
bool RegDeadKill, bool RegUndef, unsigned BaseReg,
bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,
unsigned PredReg, const TargetInstrInfo *TII,
MachineInstr *MI) {
if (isDef) {
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
TII->get(NewOpc))
.addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
.addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
// FIXME: This is overly conservative; the new instruction accesses 4
// bytes, not 8.
MIB.cloneMemRefs(*MI);
} else {
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
TII->get(NewOpc))
.addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
.addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
// FIXME: This is overly conservative; the new instruction accesses 4
// bytes, not 8.
MIB.cloneMemRefs(*MI);
}
}
bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI) {
MachineInstr *MI = &*MBBI;
unsigned Opcode = MI->getOpcode();
// FIXME: Code/comments below check Opcode == t2STRDi8, but this check returns
// if we see this opcode.
if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8)
return false;
const MachineOperand &BaseOp = MI->getOperand(2);
Register BaseReg = BaseOp.getReg();
Register EvenReg = MI->getOperand(0).getReg();
Register OddReg = MI->getOperand(1).getReg();
unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
// ARM errata 602117: LDRD with base in list may result in incorrect base
// register when interrupted or faulted.
bool Errata602117 = EvenReg == BaseReg &&
(Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3();
// ARM LDRD/STRD needs consecutive registers.
bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) &&
(EvenRegNum % 2 != 0 || EvenRegNum + 1 != OddRegNum);
if (!Errata602117 && !NonConsecutiveRegs)
return false;
bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
bool EvenDeadKill = isLd ?
MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
bool EvenUndef = MI->getOperand(0).isUndef();
bool OddDeadKill = isLd ?
MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
bool OddUndef = MI->getOperand(1).isUndef();
bool BaseKill = BaseOp.isKill();
bool BaseUndef = BaseOp.isUndef();
assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) &&
"register offset not handled below");
int OffImm = getMemoryOpOffset(*MI);
Register PredReg;
ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
if (OddRegNum > EvenRegNum && OffImm == 0) {
// Ascending register numbers and no offset. It's safe to change it to a
// ldm or stm.
unsigned NewOpc = (isLd)
? (isT2 ? ARM::t2LDMIA : ARM::LDMIA)
: (isT2 ? ARM::t2STMIA : ARM::STMIA);
if (isLd) {
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
.addReg(BaseReg, getKillRegState(BaseKill))
.addImm(Pred).addReg(PredReg)
.addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
.addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill))
.cloneMemRefs(*MI);
++NumLDRD2LDM;
} else {
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
.addReg(BaseReg, getKillRegState(BaseKill))
.addImm(Pred).addReg(PredReg)
.addReg(EvenReg,
getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
.addReg(OddReg,
getKillRegState(OddDeadKill) | getUndefRegState(OddUndef))
.cloneMemRefs(*MI);
++NumSTRD2STM;
}
} else {
// Split into two instructions.
unsigned NewOpc = (isLd)
? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
: (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
// Be extra careful for thumb2. t2LDRi8 can't reference a zero offset,
// so adjust and use t2LDRi12 here for that.
unsigned NewOpc2 = (isLd)
? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
: (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
// If this is a load, make sure the first load does not clobber the base
// register before the second load reads it.
if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {
assert(!TRI->regsOverlap(OddReg, BaseReg));
InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,
false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);
InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
MI);
} else {
if (OddReg == EvenReg && EvenDeadKill) {
// If the two source operands are the same, the kill marker is
// probably on the first one. e.g.
// t2STRDi8 killed %r5, %r5, killed %r9, 0, 14, %reg0
EvenDeadKill = false;
OddDeadKill = true;
}
// Never kill the base register in the first instruction.
if (EvenReg == BaseReg)
EvenDeadKill = false;
InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,
MI);
InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,
OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
MI);
}
if (isLd)
++NumLDRD2LDR;
else
++NumSTRD2STR;
}
MBBI = MBB.erase(MBBI);
return true;
}
/// An optimization pass to turn multiple LDR / STR ops of the same base and
/// incrementing offset into LDM / STM ops.
bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
MemOpQueue MemOps;
unsigned CurrBase = 0;
unsigned CurrOpc = ~0u;
ARMCC::CondCodes CurrPred = ARMCC::AL;
unsigned Position = 0;
assert(Candidates.size() == 0);
assert(MergeBaseCandidates.size() == 0);
LiveRegsValid = false;
for (MachineBasicBlock::iterator I = MBB.end(), MBBI; I != MBB.begin();
I = MBBI) {
// The instruction in front of the iterator is the one we look at.
MBBI = std::prev(I);
if (FixInvalidRegPairOp(MBB, MBBI))
continue;
++Position;
if (isMemoryOp(*MBBI)) {
unsigned Opcode = MBBI->getOpcode();
const MachineOperand &MO = MBBI->getOperand(0);
Register Reg = MO.getReg();
Register Base = getLoadStoreBaseOp(*MBBI).getReg();
Register PredReg;
ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
int Offset = getMemoryOpOffset(*MBBI);
if (CurrBase == 0) {
// Start of a new chain.
CurrBase = Base;
CurrOpc = Opcode;
CurrPred = Pred;
MemOps.push_back(MemOpQueueEntry(*MBBI, Offset, Position));
continue;
}
// Note: No need to match PredReg in the next if.
if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
// Watch out for:
// r4 := ldr [r0, #8]
// r4 := ldr [r0, #4]
// or
// r0 := ldr [r0]
// If a load overrides the base register or a register loaded by
// another load in our chain, we cannot take this instruction.
bool Overlap = false;
if (isLoadSingle(Opcode)) {
Overlap = (Base == Reg);
if (!Overlap) {
for (const MemOpQueueEntry &E : MemOps) {
if (TRI->regsOverlap(Reg, E.MI->getOperand(0).getReg())) {
Overlap = true;
break;
}
}
}
}
if (!Overlap) {
// Check offset and sort memory operation into the current chain.
if (Offset > MemOps.back().Offset) {
MemOps.push_back(MemOpQueueEntry(*MBBI, Offset, Position));
continue;
} else {
MemOpQueue::iterator MI, ME;
for (MI = MemOps.begin(), ME = MemOps.end(); MI != ME; ++MI) {
if (Offset < MI->Offset) {
// Found a place to insert.
break;
}
if (Offset == MI->Offset) {
// Collision, abort.
MI = ME;
break;
}
}
if (MI != MemOps.end()) {
MemOps.insert(MI, MemOpQueueEntry(*MBBI, Offset, Position));
continue;
}
}
}
}
// Don't advance the iterator; The op will start a new chain next.
MBBI = I;
--Position;
// Fallthrough to look into existing chain.
} else if (MBBI->isDebugInstr()) {
continue;
} else if (MBBI->getOpcode() == ARM::t2LDRDi8 ||
MBBI->getOpcode() == ARM::t2STRDi8) {
// ARMPreAllocLoadStoreOpt has already formed some LDRD/STRD instructions
// remember them because we may still be able to merge add/sub into them.
MergeBaseCandidates.push_back(&*MBBI);
}
// If we are here then the chain is broken; Extract candidates for a merge.
if (MemOps.size() > 0) {
FormCandidates(MemOps);
// Reset for the next chain.
CurrBase = 0;
CurrOpc = ~0u;
CurrPred = ARMCC::AL;
MemOps.clear();
}
}
if (MemOps.size() > 0)
FormCandidates(MemOps);
// Sort candidates so they get processed from end to begin of the basic
// block later; This is necessary for liveness calculation.
auto LessThan = [](const MergeCandidate* M0, const MergeCandidate *M1) {
return M0->InsertPos < M1->InsertPos;
};
llvm::sort(Candidates, LessThan);
// Go through list of candidates and merge.
bool Changed = false;
for (const MergeCandidate *Candidate : Candidates) {
if (Candidate->CanMergeToLSMulti || Candidate->CanMergeToLSDouble) {
MachineInstr *Merged = MergeOpsUpdate(*Candidate);
// Merge preceding/trailing base inc/dec into the merged op.
if (Merged) {
Changed = true;
unsigned Opcode = Merged->getOpcode();
if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8)
MergeBaseUpdateLSDouble(*Merged);
else
MergeBaseUpdateLSMultiple(Merged);
} else {
for (MachineInstr *MI : Candidate->Instrs) {
if (MergeBaseUpdateLoadStore(MI))
Changed = true;
}
}
} else {
assert(Candidate->Instrs.size() == 1);
if (MergeBaseUpdateLoadStore(Candidate->Instrs.front()))
Changed = true;
}
}
Candidates.clear();
// Try to fold add/sub into the LDRD/STRD formed by ARMPreAllocLoadStoreOpt.
for (MachineInstr *MI : MergeBaseCandidates)
MergeBaseUpdateLSDouble(*MI);
MergeBaseCandidates.clear();
return Changed;
}
/// If this is a exit BB, try merging the return ops ("bx lr" and "mov pc, lr")
/// into the preceding stack restore so it directly restore the value of LR
/// into pc.
/// ldmfd sp!, {..., lr}
/// bx lr
/// or
/// ldmfd sp!, {..., lr}
/// mov pc, lr
/// =>
/// ldmfd sp!, {..., pc}
bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
// Thumb1 LDM doesn't allow high registers.
if (isThumb1) return false;
if (MBB.empty()) return false;
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
if (MBBI != MBB.begin() && MBBI != MBB.end() &&
(MBBI->getOpcode() == ARM::BX_RET ||
MBBI->getOpcode() == ARM::tBX_RET ||
MBBI->getOpcode() == ARM::MOVPCLR)) {
MachineBasicBlock::iterator PrevI = std::prev(MBBI);
// Ignore any debug instructions.
while (PrevI->isDebugInstr() && PrevI != MBB.begin())
--PrevI;
MachineInstr &PrevMI = *PrevI;
unsigned Opcode = PrevMI.getOpcode();
if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||
Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||
Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
MachineOperand &MO = PrevMI.getOperand(PrevMI.getNumOperands() - 1);
if (MO.getReg() != ARM::LR)
return false;
unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET);
assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||
Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
PrevMI.setDesc(TII->get(NewOpc));
MO.setReg(ARM::PC);
PrevMI.copyImplicitOps(*MBB.getParent(), *MBBI);
MBB.erase(MBBI);
// We now restore LR into PC so it is not live-out of the return block
// anymore: Clear the CSI Restored bit.
MachineFrameInfo &MFI = MBB.getParent()->getFrameInfo();
// CSI should be fixed after PrologEpilog Insertion
assert(MFI.isCalleeSavedInfoValid() && "CSI should be valid");
for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
if (Info.getReg() == ARM::LR) {
Info.setRestored(false);
break;
}
}
return true;
}
}
return false;
}
bool ARMLoadStoreOpt::CombineMovBx(MachineBasicBlock &MBB) {
MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
if (MBBI == MBB.begin() || MBBI == MBB.end() ||
MBBI->getOpcode() != ARM::tBX_RET)
return false;
MachineBasicBlock::iterator Prev = MBBI;
--Prev;
if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR))
return false;
for (auto Use : Prev->uses())
if (Use.isKill()) {
assert(STI->hasV4TOps());
BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX))
.addReg(Use.getReg(), RegState::Kill)
.add(predOps(ARMCC::AL))
.copyImplicitOps(*MBBI);
MBB.erase(MBBI);
MBB.erase(Prev);
return true;
}
llvm_unreachable("tMOVr doesn't kill a reg before tBX_RET?");
}
bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
if (skipFunction(Fn.getFunction()))
return false;
MF = &Fn;
STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
TL = STI->getTargetLowering();
AFI = Fn.getInfo<ARMFunctionInfo>();
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
RegClassInfoValid = false;
isThumb2 = AFI->isThumb2Function();
isThumb1 = AFI->isThumbFunction() && !isThumb2;
bool Modified = false;
for (MachineBasicBlock &MBB : Fn) {
Modified |= LoadStoreMultipleOpti(MBB);
if (STI->hasV5TOps() && !AFI->shouldSignReturnAddress())
Modified |= MergeReturnIntoLDM(MBB);
if (isThumb1)
Modified |= CombineMovBx(MBB);
}
Allocator.DestroyAll();
return Modified;
}
#define ARM_PREALLOC_LOAD_STORE_OPT_NAME \
"ARM pre- register allocation load / store optimization pass"
namespace {
/// Pre- register allocation pass that move load / stores from consecutive
/// locations close to make it more likely they will be combined later.
struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass{
static char ID;
AliasAnalysis *AA;
const DataLayout *TD;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
const ARMSubtarget *STI;
MachineRegisterInfo *MRI;
MachineDominatorTree *DT;
MachineFunction *MF;
ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &Fn) override;
StringRef getPassName() const override {
return ARM_PREALLOC_LOAD_STORE_OPT_NAME;
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<MachineDominatorTree>();
AU.addPreserved<MachineDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU);
}
private:
bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
unsigned &NewOpc, Register &EvenReg, Register &OddReg,
Register &BaseReg, int &Offset, Register &PredReg,
ARMCC::CondCodes &Pred, bool &isT2);
bool RescheduleOps(MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &Ops,
unsigned Base, bool isLd,
DenseMap<MachineInstr*, unsigned> &MI2LocMap);
bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
bool DistributeIncrements();
bool DistributeIncrements(Register Base);
};
} // end anonymous namespace
char ARMPreAllocLoadStoreOpt::ID = 0;
INITIALIZE_PASS_BEGIN(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_END(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false)
// Limit the number of instructions to be rescheduled.
// FIXME: tune this limit, and/or come up with some better heuristics.
static cl::opt<unsigned> InstReorderLimit("arm-prera-ldst-opt-reorder-limit",
cl::init(8), cl::Hidden);
bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
if (AssumeMisalignedLoadStores || skipFunction(Fn.getFunction()))
return false;
TD = &Fn.getDataLayout();
STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
MRI = &Fn.getRegInfo();
DT = &getAnalysis<MachineDominatorTree>();
MF = &Fn;
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
bool Modified = DistributeIncrements();
for (MachineBasicBlock &MFI : Fn)
Modified |= RescheduleLoadStoreInstrs(&MFI);
return Modified;
}
static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
MachineBasicBlock::iterator I,
MachineBasicBlock::iterator E,
SmallPtrSetImpl<MachineInstr*> &MemOps,
SmallSet<unsigned, 4> &MemRegs,
const TargetRegisterInfo *TRI,
AliasAnalysis *AA) {
// Are there stores / loads / calls between them?
SmallSet<unsigned, 4> AddedRegPressure;
while (++I != E) {
if (I->isDebugInstr() || MemOps.count(&*I))
continue;
if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
return false;
if (I->mayStore() || (!isLd && I->mayLoad()))
for (MachineInstr *MemOp : MemOps)
if (I->mayAlias(AA, *MemOp, /*UseTBAA*/ false))
return false;
for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {
MachineOperand &MO = I->getOperand(j);
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
if (MO.isDef() && TRI->regsOverlap(Reg, Base))
return false;
if (Reg != Base && !MemRegs.count(Reg))
AddedRegPressure.insert(Reg);
}
}
// Estimate register pressure increase due to the transformation.
if (MemRegs.size() <= 4)
// Ok if we are moving small number of instructions.
return true;
return AddedRegPressure.size() <= MemRegs.size() * 2;
}
bool ARMPreAllocLoadStoreOpt::CanFormLdStDWord(
MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc,
Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset,
Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {
// Make sure we're allowed to generate LDRD/STRD.
if (!STI->hasV5TEOps())
return false;
// FIXME: VLDRS / VSTRS -> VLDRD / VSTRD
unsigned Scale = 1;
unsigned Opcode = Op0->getOpcode();
if (Opcode == ARM::LDRi12) {
NewOpc = ARM::LDRD;
} else if (Opcode == ARM::STRi12) {
NewOpc = ARM::STRD;
} else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {
NewOpc = ARM::t2LDRDi8;
Scale = 4;
isT2 = true;
} else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {
NewOpc = ARM::t2STRDi8;
Scale = 4;
isT2 = true;
} else {
return false;
}
// Make sure the base address satisfies i64 ld / st alignment requirement.
// At the moment, we ignore the memoryoperand's value.
// If we want to use AliasAnalysis, we should check it accordingly.
if (!Op0->hasOneMemOperand() ||
(*Op0->memoperands_begin())->isVolatile() ||
(*Op0->memoperands_begin())->isAtomic())
return false;
Align Alignment = (*Op0->memoperands_begin())->getAlign();
const Function &Func = MF->getFunction();
Align ReqAlign =
STI->hasV6Ops() ? TD->getABITypeAlign(Type::getInt64Ty(Func.getContext()))
: Align(8); // Pre-v6 need 8-byte align
if (Alignment < ReqAlign)
return false;
// Then make sure the immediate offset fits.
int OffImm = getMemoryOpOffset(*Op0);
if (isT2) {
int Limit = (1 << 8) * Scale;
if (OffImm >= Limit || (OffImm <= -Limit) || (OffImm & (Scale-1)))
return false;
Offset = OffImm;
} else {
ARM_AM::AddrOpc AddSub = ARM_AM::add;
if (OffImm < 0) {
AddSub = ARM_AM::sub;
OffImm = - OffImm;
}
int Limit = (1 << 8) * Scale;
if (OffImm >= Limit || (OffImm & (Scale-1)))
return false;
Offset = ARM_AM::getAM3Opc(AddSub, OffImm);
}
FirstReg = Op0->getOperand(0).getReg();
SecondReg = Op1->getOperand(0).getReg();
if (FirstReg == SecondReg)
return false;
BaseReg = Op0->getOperand(1).getReg();
Pred = getInstrPredicate(*Op0, PredReg);
dl = Op0->getDebugLoc();
return true;
}
bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &Ops,
unsigned Base, bool isLd,
DenseMap<MachineInstr*, unsigned> &MI2LocMap) {
bool RetVal = false;
// Sort by offset (in reverse order).
llvm::sort(Ops, [](const MachineInstr *LHS, const MachineInstr *RHS) {
int LOffset = getMemoryOpOffset(*LHS);
int ROffset = getMemoryOpOffset(*RHS);
assert(LHS == RHS || LOffset != ROffset);
return LOffset > ROffset;
});
// The loads / stores of the same base are in order. Scan them from first to
// last and check for the following:
// 1. Any def of base.
// 2. Any gaps.
while (Ops.size() > 1) {
unsigned FirstLoc = ~0U;
unsigned LastLoc = 0;
MachineInstr *FirstOp = nullptr;
MachineInstr *LastOp = nullptr;
int LastOffset = 0;
unsigned LastOpcode = 0;
unsigned LastBytes = 0;
unsigned NumMove = 0;
for (MachineInstr *Op : llvm::reverse(Ops)) {
// Make sure each operation has the same kind.
unsigned LSMOpcode
= getLoadStoreMultipleOpcode(Op->getOpcode(), ARM_AM::ia);
if (LastOpcode && LSMOpcode != LastOpcode)
break;
// Check that we have a continuous set of offsets.
int Offset = getMemoryOpOffset(*Op);
unsigned Bytes = getLSMultipleTransferSize(Op);
if (LastBytes) {
if (Bytes != LastBytes || Offset != (LastOffset + (int)Bytes))
break;
}
// Don't try to reschedule too many instructions.
if (NumMove == InstReorderLimit)
break;
// Found a mergable instruction; save information about it.
++NumMove;
LastOffset = Offset;
LastBytes = Bytes;
LastOpcode = LSMOpcode;
unsigned Loc = MI2LocMap[Op];
if (Loc <= FirstLoc) {
FirstLoc = Loc;
FirstOp = Op;
}
if (Loc >= LastLoc) {
LastLoc = Loc;
LastOp = Op;
}
}
if (NumMove <= 1)
Ops.pop_back();
else {
SmallPtrSet<MachineInstr*, 4> MemOps;
SmallSet<unsigned, 4> MemRegs;
for (size_t i = Ops.size() - NumMove, e = Ops.size(); i != e; ++i) {
MemOps.insert(Ops[i]);
MemRegs.insert(Ops[i]->getOperand(0).getReg());
}
// Be conservative, if the instructions are too far apart, don't
// move them. We want to limit the increase of register pressure.
bool DoMove = (LastLoc - FirstLoc) <= NumMove*4; // FIXME: Tune this.
if (DoMove)
DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,
MemOps, MemRegs, TRI, AA);
if (!DoMove) {
for (unsigned i = 0; i != NumMove; ++i)
Ops.pop_back();
} else {
// This is the new location for the loads / stores.
MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
while (InsertPos != MBB->end() &&
(MemOps.count(&*InsertPos) || InsertPos->isDebugInstr()))
++InsertPos;
// If we are moving a pair of loads / stores, see if it makes sense
// to try to allocate a pair of registers that can form register pairs.
MachineInstr *Op0 = Ops.back();
MachineInstr *Op1 = Ops[Ops.size()-2];
Register FirstReg, SecondReg;
Register BaseReg, PredReg;
ARMCC::CondCodes Pred = ARMCC::AL;
bool isT2 = false;
unsigned NewOpc = 0;
int Offset = 0;
DebugLoc dl;
if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
FirstReg, SecondReg, BaseReg,
Offset, PredReg, Pred, isT2)) {
Ops.pop_back();
Ops.pop_back();
const MCInstrDesc &MCID = TII->get(NewOpc);
const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
MRI->constrainRegClass(FirstReg, TRC);
MRI->constrainRegClass(SecondReg, TRC);
// Form the pair instruction.
if (isLd) {
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
.addReg(FirstReg, RegState::Define)
.addReg(SecondReg, RegState::Define)
.addReg(BaseReg);
// FIXME: We're converting from LDRi12 to an insn that still
// uses addrmode2, so we need an explicit offset reg. It should
// always by reg0 since we're transforming LDRi12s.
if (!isT2)
MIB.addReg(0);
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
MIB.cloneMergedMemRefs({Op0, Op1});
LLVM_DEBUG(dbgs() << "Formed " << *MIB << "\n");
++NumLDRDFormed;
} else {
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
.addReg(FirstReg)
.addReg(SecondReg)
.addReg(BaseReg);
// FIXME: We're converting from LDRi12 to an insn that still
// uses addrmode2, so we need an explicit offset reg. It should
// always by reg0 since we're transforming STRi12s.
if (!isT2)
MIB.addReg(0);
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
MIB.cloneMergedMemRefs({Op0, Op1});
LLVM_DEBUG(dbgs() << "Formed " << *MIB << "\n");
++NumSTRDFormed;
}
MBB->erase(Op0);
MBB->erase(Op1);
if (!isT2) {
// Add register allocation hints to form register pairs.
MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg);
MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg);
}
} else {
for (unsigned i = 0; i != NumMove; ++i) {
MachineInstr *Op = Ops.pop_back_val();
MBB->splice(InsertPos, MBB, Op);
}
}
NumLdStMoved += NumMove;
RetVal = true;
}
}
}
return RetVal;
}
bool
ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
bool RetVal = false;
DenseMap<MachineInstr*, unsigned> MI2LocMap;
using MapIt = DenseMap<unsigned, SmallVector<MachineInstr *, 4>>::iterator;
using Base2InstMap = DenseMap<unsigned, SmallVector<MachineInstr *, 4>>;
using BaseVec = SmallVector<unsigned, 4>;
Base2InstMap Base2LdsMap;
Base2InstMap Base2StsMap;
BaseVec LdBases;
BaseVec StBases;
unsigned Loc = 0;
MachineBasicBlock::iterator MBBI = MBB->begin();
MachineBasicBlock::iterator E = MBB->end();
while (MBBI != E) {
for (; MBBI != E; ++MBBI) {
MachineInstr &MI = *MBBI;
if (MI.isCall() || MI.isTerminator()) {
// Stop at barriers.
++MBBI;
break;
}
if (!MI.isDebugInstr())
MI2LocMap[&MI] = ++Loc;
if (!isMemoryOp(MI))
continue;
Register PredReg;
if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
continue;
int Opc = MI.getOpcode();
bool isLd = isLoadSingle(Opc);
Register Base = MI.getOperand(1).getReg();
int Offset = getMemoryOpOffset(MI);
bool StopHere = false;
auto FindBases = [&] (Base2InstMap &Base2Ops, BaseVec &Bases) {
MapIt BI = Base2Ops.find(Base);
if (BI == Base2Ops.end()) {
Base2Ops[Base].push_back(&MI);
Bases.push_back(Base);
return;
}
for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
if (Offset == getMemoryOpOffset(*BI->second[i])) {
StopHere = true;
break;
}
}
if (!StopHere)
BI->second.push_back(&MI);
};
if (isLd)
FindBases(Base2LdsMap, LdBases);
else
FindBases(Base2StsMap, StBases);
if (StopHere) {
// Found a duplicate (a base+offset combination that's seen earlier).
// Backtrack.
--Loc;
break;
}
}
// Re-schedule loads.
for (unsigned i = 0, e = LdBases.size(); i != e; ++i) {
unsigned Base = LdBases[i];
SmallVectorImpl<MachineInstr *> &Lds = Base2LdsMap[Base];
if (Lds.size() > 1)
RetVal |= RescheduleOps(MBB, Lds, Base, true, MI2LocMap);
}
// Re-schedule stores.
for (unsigned i = 0, e = StBases.size(); i != e; ++i) {
unsigned Base = StBases[i];
SmallVectorImpl<MachineInstr *> &Sts = Base2StsMap[Base];
if (Sts.size() > 1)
RetVal |= RescheduleOps(MBB, Sts, Base, false, MI2LocMap);
}
if (MBBI != E) {
Base2LdsMap.clear();
Base2StsMap.clear();
LdBases.clear();
StBases.clear();
}
}
return RetVal;
}
// Get the Base register operand index from the memory access MachineInst if we
// should attempt to distribute postinc on it. Return -1 if not of a valid
// instruction type. If it returns an index, it is assumed that instruction is a
// r+i indexing mode, and getBaseOperandIndex() + 1 is the Offset index.
static int getBaseOperandIndex(MachineInstr &MI) {
switch (MI.getOpcode()) {
case ARM::MVE_VLDRBS16:
case ARM::MVE_VLDRBS32:
case ARM::MVE_VLDRBU16:
case ARM::MVE_VLDRBU32:
case ARM::MVE_VLDRHS32:
case ARM::MVE_VLDRHU32:
case ARM::MVE_VLDRBU8:
case ARM::MVE_VLDRHU16:
case ARM::MVE_VLDRWU32:
case ARM::MVE_VSTRB16:
case ARM::MVE_VSTRB32:
case ARM::MVE_VSTRH32:
case ARM::MVE_VSTRBU8:
case ARM::MVE_VSTRHU16:
case ARM::MVE_VSTRWU32:
case ARM::t2LDRHi8:
case ARM::t2LDRHi12:
case ARM::t2LDRSHi8:
case ARM::t2LDRSHi12:
case ARM::t2LDRBi8:
case ARM::t2LDRBi12:
case ARM::t2LDRSBi8:
case ARM::t2LDRSBi12:
case ARM::t2STRBi8:
case ARM::t2STRBi12:
case ARM::t2STRHi8:
case ARM::t2STRHi12:
return 1;
case ARM::MVE_VLDRBS16_post:
case ARM::MVE_VLDRBS32_post:
case ARM::MVE_VLDRBU16_post:
case ARM::MVE_VLDRBU32_post:
case ARM::MVE_VLDRHS32_post:
case ARM::MVE_VLDRHU32_post:
case ARM::MVE_VLDRBU8_post:
case ARM::MVE_VLDRHU16_post:
case ARM::MVE_VLDRWU32_post:
case ARM::MVE_VSTRB16_post:
case ARM::MVE_VSTRB32_post:
case ARM::MVE_VSTRH32_post:
case ARM::MVE_VSTRBU8_post:
case ARM::MVE_VSTRHU16_post:
case ARM::MVE_VSTRWU32_post:
case ARM::MVE_VLDRBS16_pre:
case ARM::MVE_VLDRBS32_pre:
case ARM::MVE_VLDRBU16_pre:
case ARM::MVE_VLDRBU32_pre:
case ARM::MVE_VLDRHS32_pre:
case ARM::MVE_VLDRHU32_pre:
case ARM::MVE_VLDRBU8_pre:
case ARM::MVE_VLDRHU16_pre:
case ARM::MVE_VLDRWU32_pre:
case ARM::MVE_VSTRB16_pre:
case ARM::MVE_VSTRB32_pre:
case ARM::MVE_VSTRH32_pre:
case ARM::MVE_VSTRBU8_pre:
case ARM::MVE_VSTRHU16_pre:
case ARM::MVE_VSTRWU32_pre:
return 2;
}
return -1;
}
static bool isPostIndex(MachineInstr &MI) {
switch (MI.getOpcode()) {
case ARM::MVE_VLDRBS16_post:
case ARM::MVE_VLDRBS32_post:
case ARM::MVE_VLDRBU16_post:
case ARM::MVE_VLDRBU32_post:
case ARM::MVE_VLDRHS32_post:
case ARM::MVE_VLDRHU32_post:
case ARM::MVE_VLDRBU8_post:
case ARM::MVE_VLDRHU16_post:
case ARM::MVE_VLDRWU32_post:
case ARM::MVE_VSTRB16_post:
case ARM::MVE_VSTRB32_post:
case ARM::MVE_VSTRH32_post:
case ARM::MVE_VSTRBU8_post:
case ARM::MVE_VSTRHU16_post:
case ARM::MVE_VSTRWU32_post:
return true;
}
return false;
}
static bool isPreIndex(MachineInstr &MI) {
switch (MI.getOpcode()) {
case ARM::MVE_VLDRBS16_pre:
case ARM::MVE_VLDRBS32_pre:
case ARM::MVE_VLDRBU16_pre:
case ARM::MVE_VLDRBU32_pre:
case ARM::MVE_VLDRHS32_pre:
case ARM::MVE_VLDRHU32_pre:
case ARM::MVE_VLDRBU8_pre:
case ARM::MVE_VLDRHU16_pre:
case ARM::MVE_VLDRWU32_pre:
case ARM::MVE_VSTRB16_pre:
case ARM::MVE_VSTRB32_pre:
case ARM::MVE_VSTRH32_pre:
case ARM::MVE_VSTRBU8_pre:
case ARM::MVE_VSTRHU16_pre:
case ARM::MVE_VSTRWU32_pre:
return true;
}
return false;
}
// Given a memory access Opcode, check that the give Imm would be a valid Offset
// for this instruction (same as isLegalAddressImm), Or if the instruction
// could be easily converted to one where that was valid. For example converting
// t2LDRi12 to t2LDRi8 for negative offsets. Works in conjunction with
// AdjustBaseAndOffset below.
static bool isLegalOrConvertableAddressImm(unsigned Opcode, int Imm,
const TargetInstrInfo *TII,
int &CodesizeEstimate) {
if (isLegalAddressImm(Opcode, Imm, TII))
return true;
// We can convert AddrModeT2_i12 to AddrModeT2_i8neg.
const MCInstrDesc &Desc = TII->get(Opcode);
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
switch (AddrMode) {
case ARMII::AddrModeT2_i12:
CodesizeEstimate += 1;
return Imm < 0 && -Imm < ((1 << 8) * 1);
}
return false;
}
// Given an MI adjust its address BaseReg to use NewBaseReg and address offset
// by -Offset. This can either happen in-place or be a replacement as MI is
// converted to another instruction type.
static void AdjustBaseAndOffset(MachineInstr *MI, Register NewBaseReg,
int Offset, const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
// Set the Base reg
unsigned BaseOp = getBaseOperandIndex(*MI);
MI->getOperand(BaseOp).setReg(NewBaseReg);
// and constrain the reg class to that required by the instruction.
MachineFunction *MF = MI->getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
const MCInstrDesc &MCID = TII->get(MI->getOpcode());
const TargetRegisterClass *TRC = TII->getRegClass(MCID, BaseOp, TRI, *MF);
MRI.constrainRegClass(NewBaseReg, TRC);
int OldOffset = MI->getOperand(BaseOp + 1).getImm();
if (isLegalAddressImm(MI->getOpcode(), OldOffset - Offset, TII))
MI->getOperand(BaseOp + 1).setImm(OldOffset - Offset);
else {
unsigned ConvOpcode;
switch (MI->getOpcode()) {
case ARM::t2LDRHi12:
ConvOpcode = ARM::t2LDRHi8;
break;
case ARM::t2LDRSHi12:
ConvOpcode = ARM::t2LDRSHi8;
break;
case ARM::t2LDRBi12:
ConvOpcode = ARM::t2LDRBi8;
break;
case ARM::t2LDRSBi12:
ConvOpcode = ARM::t2LDRSBi8;
break;
case ARM::t2STRHi12:
ConvOpcode = ARM::t2STRHi8;
break;
case ARM::t2STRBi12:
ConvOpcode = ARM::t2STRBi8;
break;
default:
llvm_unreachable("Unhandled convertable opcode");
}
assert(isLegalAddressImm(ConvOpcode, OldOffset - Offset, TII) &&
"Illegal Address Immediate after convert!");
const MCInstrDesc &MCID = TII->get(ConvOpcode);
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
.add(MI->getOperand(0))
.add(MI->getOperand(1))
.addImm(OldOffset - Offset)
.add(MI->getOperand(3))
.add(MI->getOperand(4))
.cloneMemRefs(*MI);
MI->eraseFromParent();
}
}
static MachineInstr *createPostIncLoadStore(MachineInstr *MI, int Offset,
Register NewReg,
const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
MachineFunction *MF = MI->getMF();
MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned NewOpcode = getPostIndexedLoadStoreOpcode(
MI->getOpcode(), Offset > 0 ? ARM_AM::add : ARM_AM::sub);
const MCInstrDesc &MCID = TII->get(NewOpcode);
// Constrain the def register class
const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
MRI.constrainRegClass(NewReg, TRC);
// And do the same for the base operand
TRC = TII->getRegClass(MCID, 2, TRI, *MF);
MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC);
unsigned AddrMode = (MCID.TSFlags & ARMII::AddrModeMask);
switch (AddrMode) {
case ARMII::AddrModeT2_i7:
case ARMII::AddrModeT2_i7s2:
case ARMII::AddrModeT2_i7s4:
// Any MVE load/store
return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
.addReg(NewReg, RegState::Define)
.add(MI->getOperand(0))
.add(MI->getOperand(1))
.addImm(Offset)
.add(MI->getOperand(3))
.add(MI->getOperand(4))
.add(MI->getOperand(5))
.cloneMemRefs(*MI);
case ARMII::AddrModeT2_i8:
if (MI->mayLoad()) {
return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
.add(MI->getOperand(0))
.addReg(NewReg, RegState::Define)
.add(MI->getOperand(1))
.addImm(Offset)
.add(MI->getOperand(3))
.add(MI->getOperand(4))
.cloneMemRefs(*MI);
} else {
return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
.addReg(NewReg, RegState::Define)
.add(MI->getOperand(0))
.add(MI->getOperand(1))
.addImm(Offset)
.add(MI->getOperand(3))
.add(MI->getOperand(4))
.cloneMemRefs(*MI);
}
default:
llvm_unreachable("Unhandled createPostIncLoadStore");
}
}
// Given a Base Register, optimise the load/store uses to attempt to create more
// post-inc accesses and less register moves. We do this by taking zero offset
// loads/stores with an add, and convert them to a postinc load/store of the
// same type. Any subsequent accesses will be adjusted to use and account for
// the post-inc value.
// For example:
// LDR #0 LDR_POSTINC #16
// LDR #4 LDR #-12
// LDR #8 LDR #-8
// LDR #12 LDR #-4
// ADD #16
//
// At the same time if we do not find an increment but do find an existing
// pre/post inc instruction, we can still adjust the offsets of subsequent
// instructions to save the register move that would otherwise be needed for the
// in-place increment.
bool ARMPreAllocLoadStoreOpt::DistributeIncrements(Register Base) {
// We are looking for:
// One zero offset load/store that can become postinc
MachineInstr *BaseAccess = nullptr;
MachineInstr *PrePostInc = nullptr;
// An increment that can be folded in
MachineInstr *Increment = nullptr;
// Other accesses after BaseAccess that will need to be updated to use the
// postinc value.
SmallPtrSet<MachineInstr *, 8> OtherAccesses;
for (auto &Use : MRI->use_nodbg_instructions(Base)) {
if (!Increment && getAddSubImmediate(Use) != 0) {
Increment = &Use;
continue;
}
int BaseOp = getBaseOperandIndex(Use);
if (BaseOp == -1)
return false;
if (!Use.getOperand(BaseOp).isReg() ||
Use.getOperand(BaseOp).getReg() != Base)
return false;
if (isPreIndex(Use) || isPostIndex(Use))
PrePostInc = &Use;
else if (Use.getOperand(BaseOp + 1).getImm() == 0)
BaseAccess = &Use;
else
OtherAccesses.insert(&Use);
}
int IncrementOffset;
Register NewBaseReg;
if (BaseAccess && Increment) {
if (PrePostInc || BaseAccess->getParent() != Increment->getParent())
return false;
Register PredReg;
if (Increment->definesRegister(ARM::CPSR) ||
getInstrPredicate(*Increment, PredReg) != ARMCC::AL)
return false;
LLVM_DEBUG(dbgs() << "\nAttempting to distribute increments on VirtualReg "
<< Base.virtRegIndex() << "\n");
// Make sure that Increment has no uses before BaseAccess.
for (MachineInstr &Use :
MRI->use_nodbg_instructions(Increment->getOperand(0).getReg())) {
if (!DT->dominates(BaseAccess, &Use) || &Use == BaseAccess) {
LLVM_DEBUG(dbgs() << " BaseAccess doesn't dominate use of increment\n");
return false;
}
}
// Make sure that Increment can be folded into Base
IncrementOffset = getAddSubImmediate(*Increment);
unsigned NewPostIncOpcode = getPostIndexedLoadStoreOpcode(
BaseAccess->getOpcode(), IncrementOffset > 0 ? ARM_AM::add : ARM_AM::sub);
if (!isLegalAddressImm(NewPostIncOpcode, IncrementOffset, TII)) {
LLVM_DEBUG(dbgs() << " Illegal addressing mode immediate on postinc\n");
return false;
}
}
else if (PrePostInc) {
// If we already have a pre/post index load/store then set BaseAccess,
// IncrementOffset and NewBaseReg to the values it already produces,
// allowing us to update and subsequent uses of BaseOp reg with the
// incremented value.
if (Increment)
return false;
LLVM_DEBUG(dbgs() << "\nAttempting to distribute increments on already "
<< "indexed VirtualReg " << Base.virtRegIndex() << "\n");
int BaseOp = getBaseOperandIndex(*PrePostInc);
IncrementOffset = PrePostInc->getOperand(BaseOp+1).getImm();
BaseAccess = PrePostInc;
NewBaseReg = PrePostInc->getOperand(0).getReg();
}
else
return false;
// And make sure that the negative value of increment can be added to all
// other offsets after the BaseAccess. We rely on either
// dominates(BaseAccess, OtherAccess) or dominates(OtherAccess, BaseAccess)
// to keep things simple.
// This also adds a simple codesize metric, to detect if an instruction (like
// t2LDRBi12) which can often be shrunk to a thumb1 instruction (tLDRBi)
// cannot because it is converted to something else (t2LDRBi8). We start this
// at -1 for the gain from removing the increment.
SmallPtrSet<MachineInstr *, 4> SuccessorAccesses;
int CodesizeEstimate = -1;
for (auto *Use : OtherAccesses) {
if (DT->dominates(BaseAccess, Use)) {
SuccessorAccesses.insert(Use);
unsigned BaseOp = getBaseOperandIndex(*Use);
if (!isLegalOrConvertableAddressImm(Use->getOpcode(),
Use->getOperand(BaseOp + 1).getImm() -
IncrementOffset,
TII, CodesizeEstimate)) {
LLVM_DEBUG(dbgs() << " Illegal addressing mode immediate on use\n");
return false;
}
} else if (!DT->dominates(Use, BaseAccess)) {
LLVM_DEBUG(
dbgs() << " Unknown dominance relation between Base and Use\n");
return false;
}
}
if (STI->hasMinSize() && CodesizeEstimate > 0) {
LLVM_DEBUG(dbgs() << " Expected to grow instructions under minsize\n");
return false;
}
if (!PrePostInc) {
// Replace BaseAccess with a post inc
LLVM_DEBUG(dbgs() << "Changing: "; BaseAccess->dump());
LLVM_DEBUG(dbgs() << " And : "; Increment->dump());
NewBaseReg = Increment->getOperand(0).getReg();
MachineInstr *BaseAccessPost =
createPostIncLoadStore(BaseAccess, IncrementOffset, NewBaseReg, TII, TRI);
BaseAccess->eraseFromParent();
Increment->eraseFromParent();
(void)BaseAccessPost;
LLVM_DEBUG(dbgs() << " To : "; BaseAccessPost->dump());
}
for (auto *Use : SuccessorAccesses) {
LLVM_DEBUG(dbgs() << "Changing: "; Use->dump());
AdjustBaseAndOffset(Use, NewBaseReg, IncrementOffset, TII, TRI);
LLVM_DEBUG(dbgs() << " To : "; Use->dump());
}
// Remove the kill flag from all uses of NewBaseReg, in case any old uses
// remain.
for (MachineOperand &Op : MRI->use_nodbg_operands(NewBaseReg))
Op.setIsKill(false);
return true;
}
bool ARMPreAllocLoadStoreOpt::DistributeIncrements() {
bool Changed = false;
SmallSetVector<Register, 4> Visited;
for (auto &MBB : *MF) {
for (auto &MI : MBB) {
int BaseOp = getBaseOperandIndex(MI);
if (BaseOp == -1 || !MI.getOperand(BaseOp).isReg())
continue;
Register Base = MI.getOperand(BaseOp).getReg();
if (!Base.isVirtual() || Visited.count(Base))
continue;
Visited.insert(Base);
}
}
for (auto Base : Visited)
Changed |= DistributeIncrements(Base);
return Changed;
}
/// Returns an instance of the load / store optimization pass.
FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) {
if (PreAlloc)
return new ARMPreAllocLoadStoreOpt();
return new ARMLoadStoreOpt();
}
|
pla
sta {m1}
lda #0
sta {m1}+1
|
; A227121: Number of n X 2 0,1 arrays indicating 2 X 2 subblocks of some larger (n+1) X 3 binary array having a sum of zero, with rows and columns of the latter in lexicographically nondecreasing order.
; Submitted by Jamie Morken(s3.)
; 3,7,13,23,40,68,112,178,273,405,583,817,1118,1498,1970,2548,3247,4083,5073,6235,7588,9152,10948,12998,15325,17953,20907,24213,27898,31990,36518,41512,47003,53023,59605,66783,74592,83068,92248,102170,112873,124397,136783,150073,164310,179538,195802,213148,231623,251275,272153,294307,317788,342648,368940,396718,426037,456953,489523,523805,559858,597742,637518,679248,722995,768823,816797,866983,919448,974260,1031488,1091202,1153473,1218373,1285975,1356353,1429582,1505738,1584898,1667140,1752543
mov $2,$0
add $0,4
add $2,2
bin $0,$2
bin $2,4
add $2,$0
mov $0,$2
sub $0,3
|
; Listing generated by Microsoft (R) Optimizing Compiler Version 16.00.40219.01
TITLE C:\Work\daspirum\Source\src\notifymyandroid.cpp
.686P
.XMM
include listing.inc
.model flat
INCLUDELIB OLDNAMES
ORG $+2
$SG-77049 DB 'www.notifymyandroid.com', 00H
$SG-77050 DB '%20', 00H
$SG-77051 DB 0dH, 0aH, 0dH, 0aH, 00H
ORG $+3
$SG-77052 DB '&application=daspirum&event=Battlefield-3-Event&descript'
DB 'ion=', 00H
ORG $+3
$SG-77053 DB 'GET /publicapi/notify?apikey=', 00H
ORG $+2
$SG-77054 DB 'rror', 00H
ORG $+3
$SG-77055 DB 'notifymyandroid::notificate', 00H
$SG-77056 DB '..\src\notifymyandroid.cpp', 00H
ORG $+1
$SG-77101 DB '.', 0aH, 00H
ORG $+1
$SG-77102 DB 0aH, 0aH, 'Error detected at line ', 00H
ORG $+2
$SG-77103 DB '.', 0aH, 00H
ORG $+1
$SG-77104 DB 'e:\library\dlib\dlib\set/set_kernel_c.h', 00H
$SG-77105 DB 'Error detected in file ', 00H
$SG-77106 DB '.', 0aH, 0aH, 00H
$SG-77108 DB 'Error detected in function ', 00H
$SG-77107 DB 'void __thiscall dlib::set_kernel_c<class dlib::set_kerne'
DB 'l_1<unsigned long,class dlib::binary_search_tree_kernel_2<uns'
DB 'igned long,char,class dlib::memory_manager_kernel_2<char,100>'
DB ',struct std::less<unsigned long> >,class dlib::memory_manager'
DB '_kernel_2<char,100> > >::remove_any(unsigned long &)', 00H
$SG-77109 DB '.', 0aH, 00H
ORG $+1
$SG-77110 DB 'this->size() != 0', 00H
ORG $+2
$SG-77111 DB 'Failing expression was ', 00H
$SG-77112 DB 0aH, 00H
ORG $+2
$SG-77113 DB 0aH, 09H, 'this: ', 00H
ORG $+3
$SG-77114 DB 0aH, 09H, 'size must be greater than zero if an item is t'
DB 'o be removed', 00H
ORG $+3
$SG-77115 DB 09H, 'void set::remove_any', 00H
ORG $+2
$SG-77116 DB '.', 0aH, 00H
ORG $+1
$SG-77117 DB 0aH, 0aH, 'Error detected at line ', 00H
ORG $+2
$SG-77118 DB '.', 0aH, 00H
ORG $+1
$SG-77119 DB 'e:\library\dlib\dlib\set/set_kernel_c.h', 00H
$SG-77120 DB 'Error detected in file ', 00H
$SG-77121 DB '.', 0aH, 0aH, 00H
$SG-77123 DB 'Error detected in function ', 00H
$SG-77122 DB 'const unsigned long &__thiscall dlib::set_kernel_c<class'
DB ' dlib::set_kernel_1<unsigned long,class dlib::binary_search_t'
DB 'ree_kernel_2<unsigned long,char,class dlib::memory_manager_ke'
DB 'rnel_2<char,100>,struct std::less<unsigned long> >,class dlib'
DB '::memory_manager_kernel_2<char,100> > >::element(void) const', 00H
$SG-77124 DB '.', 0aH, 00H
ORG $+1
$SG-77125 DB 'this->current_element_valid() == true', 00H
ORG $+2
$SG-77126 DB 'Failing expression was ', 00H
$SG-77127 DB 0aH, 00H
ORG $+2
$SG-77128 DB 0aH, 09H, 'this: ', 00H
ORG $+3
$SG-77129 DB 0aH, 09H, 'you can''t access the current element if it do'
DB 'esn''t exist', 00H
ORG $+1
$SG-77130 DB 09H, 'const T& set::element() const', 00H
ORG $+1
$SG-77131 DB '.', 0aH, 00H
ORG $+1
$SG-77132 DB 0aH, 0aH, 'Error detected at line ', 00H
ORG $+2
$SG-77133 DB '.', 0aH, 00H
ORG $+1
$SG-77134 DB 'e:\library\dlib\dlib\set/set_kernel_c.h', 00H
$SG-77135 DB 'Error detected in file ', 00H
$SG-77136 DB '.', 0aH, 0aH, 00H
$SG-77138 DB 'Error detected in function ', 00H
$SG-77137 DB 'const unsigned long &__thiscall dlib::set_kernel_c<class'
DB ' dlib::set_kernel_1<unsigned long,class dlib::binary_search_t'
DB 'ree_kernel_2<unsigned long,char,class dlib::memory_manager_ke'
DB 'rnel_2<char,100>,struct std::less<unsigned long> >,class dlib'
DB '::memory_manager_kernel_2<char,100> > >::element(void)', 00H
ORG $+2
$SG-77139 DB '.', 0aH, 00H
ORG $+1
$SG-77140 DB 'this->current_element_valid() == true', 00H
ORG $+2
$SG-77141 DB 'Failing expression was ', 00H
$SG-77142 DB 0aH, 00H
ORG $+2
$SG-77143 DB 0aH, 09H, 'this: ', 00H
ORG $+3
$SG-77144 DB 0aH, 09H, 'you can''t access the current element if it do'
DB 'esn''t exist', 00H
ORG $+1
$SG-77145 DB 09H, 'const T& set::element', 00H
ORG $+1
$SG-77146 DB '.', 0aH, 00H
ORG $+1
$SG-77147 DB 0aH, 0aH, 'Error detected at line ', 00H
ORG $+2
$SG-77148 DB '.', 0aH, 00H
ORG $+1
$SG-77150 DB 'Error detected in file ', 00H
$SG-77151 DB '.', 0aH, 0aH, 00H
$SG-77149 DB 'e:\library\dlib\dlib\binary_search_tree/binary_search_tr'
DB 'ee_kernel_c.h', 00H
ORG $+2
$SG-77152 DB 'void __thiscall dlib::binary_search_tree_kernel_c<class '
DB 'dlib::binary_search_tree_kernel_2<unsigned long,class dlib::m'
DB 'ember_function_pointer<void,void,void,void>,class dlib::memor'
DB 'y_manager_kernel_2<char,10>,struct std::less<unsigned long> >'
DB ' >::remove_any(unsigned long &,class dlib::member_function_po'
DB 'inter<void,void,void,void> &)', 00H
ORG $+2
$SG-77153 DB 'Error detected in function ', 00H
$SG-77154 DB '.', 0aH, 00H
ORG $+1
$SG-77156 DB 'Failing expression was ', 00H
$SG-77157 DB 0aH, 00H
ORG $+2
$SG-77155 DB 'this->size() != 0 && (static_cast<const void*>(&d) != st'
DB 'atic_cast<void*>(&r))', 00H
ORG $+2
$SG-77158 DB 0aH, 09H, '&r: ', 00H
ORG $+3
$SG-77159 DB 0aH, 09H, '&d: ', 00H
ORG $+3
$SG-77160 DB 0aH, 09H, 'this: ', 00H
ORG $+3
$SG-77161 DB 0aH, 09H, 'tree must not be empty if something is going t'
DB 'o be removed', 00H
ORG $+3
$SG-77162 DB 09H, 'void binary_search_tree::remove_any', 00H
ORG $+3
$SG-77163 DB '.', 0aH, 00H
ORG $+1
$SG-77164 DB 0aH, 0aH, 'Error detected at line ', 00H
ORG $+2
$SG-77165 DB '.', 0aH, 00H
ORG $+1
$SG-77166 DB 'e:\library\dlib\dlib\binary_search_tree/binary_search_tr'
DB 'ee_kernel_c.h', 00H
ORG $+2
$SG-77167 DB 'Error detected in file ', 00H
$SG-77168 DB '.', 0aH, 0aH, 00H
$SG-77170 DB 'Error detected in function ', 00H
$SG-77169 DB 'class dlib::map_pair<unsigned long,class dlib::member_fu'
DB 'nction_pointer<void,void,void,void> > &__thiscall dlib::binar'
DB 'y_search_tree_kernel_c<class dlib::binary_search_tree_kernel_'
DB '2<unsigned long,class dlib::member_function_pointer<void,void'
DB ',void,void>,class dlib::memory_manager_kernel_2<char,10>,stru'
DB 'ct std::less<unsigned long> > >::element(void)', 00H
ORG $+1
$SG-77171 DB '.', 0aH, 00H
ORG $+1
$SG-77172 DB 'this->current_element_valid() == true', 00H
ORG $+2
$SG-77173 DB 'Failing expression was ', 00H
$SG-77174 DB 0aH, 00H
ORG $+2
$SG-77175 DB 0aH, 09H, 'this: ', 00H
ORG $+3
$SG-77176 DB 0aH, 09H, 'you can''t access the current element if it do'
DB 'esn''t exist', 00H
ORG $+1
$SG-77177 DB 09H, 'map_pair<domain,range>& binary_search_tree::element'
DB '()', 00H
ORG $+1
$SG-77178 DB '.', 0aH, 00H
ORG $+1
$SG-77179 DB 0aH, 0aH, 'Error detected at line ', 00H
ORG $+2
$SG-77180 DB '.', 0aH, 00H
ORG $+1
$SG-77181 DB 'e:\library\dlib\dlib\binary_search_tree/binary_search_tr'
DB 'ee_kernel_c.h', 00H
ORG $+2
$SG-77182 DB 'Error detected in file ', 00H
$SG-77183 DB '.', 0aH, 0aH, 00H
$SG-77185 DB 'Error detected in function ', 00H
$SG-77184 DB 'const class dlib::map_pair<unsigned long,class dlib::mem'
DB 'ber_function_pointer<void,void,void,void> > &__thiscall dlib:'
DB ':binary_search_tree_kernel_c<class dlib::binary_search_tree_k'
DB 'ernel_2<unsigned long,class dlib::member_function_pointer<voi'
DB 'd,void,void,void>,class dlib::memory_manager_kernel_2<char,10'
DB '>,struct std::less<unsigned long> > >::element(void) const', 00H
ORG $+1
$SG-77186 DB '.', 0aH, 00H
ORG $+1
$SG-77187 DB 'this->current_element_valid() == true', 00H
ORG $+2
$SG-77188 DB 'Failing expression was ', 00H
$SG-77189 DB 0aH, 00H
ORG $+2
$SG-77190 DB 0aH, 09H, 'this: ', 00H
ORG $+3
$SG-77191 DB 0aH, 09H, 'you can''t access the current element if it do'
DB 'esn''t exist', 00H
ORG $+1
$SG-77192 DB 09H, 'const map_pair<domain,range>& binary_search_tree::e'
DB 'lement() const', 00H
PUBLIC __$ArrayPad$
PUBLIC ?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z ; notifymyandroid::notificate
; COMDAT xdata$x
; File c:\work\daspirum\source\src\notifymyandroid.cpp
xdata$x SEGMENT
__unwindtable$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z DD 0ffffffffH
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$2
DD 00H
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$3
DD 01H
DD 00H
DD 02H
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$4
DD 03H
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$5
DD 02H
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$5
DD 05H
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$6
DD 06H
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$7
DD 07H
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$8
DD 08H
DD FLAT:__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$9
DD 01H
DD 00H
__catchsym$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$12 DD 08H
DD FLAT:??_R0?AVexception@std@@@8
DD 0fffffe30H
DD FLAT:__catch$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$0
__tryblocktable$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z DD 02H
DD 09H
DD 0aH
DD 01H
DD FLAT:__catchsym$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$12
__ehfuncinfo$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z DD 019930522H
DD 0bH
DD FLAT:__unwindtable$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z
DD 01H
DD FLAT:__tryblocktable$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z
DD 2 DUP(00H)
DD 00H
DD 01H
; Function compile flags: /Odtp
xdata$x ENDS
; COMDAT ?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z
_TEXT SEGMENT
tv221 = -532 ; size = 4
tv216 = -528 ; size = 4
tv211 = -524 ; size = 4
tv229 = -520 ; size = 4
tv209 = -516 ; size = 4
tv228 = -512 ; size = 4
tv207 = -508 ; size = 4
tv227 = -504 ; size = 4
tv205 = -500 ; size = 4
tv67 = -496 ; size = 4
tv226 = -492 ; size = 4
tv225 = -488 ; size = 4
$T369476 = -481 ; size = 1
$T369475 = -480 ; size = 4
$T369474 = -473 ; size = 1
$T369473 = -472 ; size = 4
$T369472 = -465 ; size = 1
_e$148889 = -464 ; size = 4
_i$148804 = -460 ; size = 4
_con$148801 = -456 ; size = 4
_size$148803 = -452 ; size = 4
_sBuffer$148795 = -448 ; size = 256
$T148884 = -188 ; size = 28
$T148877 = -160 ; size = 28
$T148876 = -132 ; size = 28
$T148811 = -104 ; size = 28
$T148810 = -76 ; size = 28
$T148800 = -48 ; size = 28
__$ArrayPad$ = -20 ; size = 4
__$EHRec$ = -16 ; size = 16
_sAPIKey$ = 8 ; size = 28
_sMessage$ = 36 ; size = 28
?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z PROC ; notifymyandroid::notificate, COMDAT
; Line 10
push ebp
mov ebp, esp
push -1
push __ehhandler$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z
mov eax, DWORD PTR fs:0
push eax
push ecx
sub esp, 516 ; 00000204H
mov eax, DWORD PTR ___security_cookie
xor eax, ebp
mov DWORD PTR __$ArrayPad$[ebp], eax
push ebx
push esi
push edi
push eax
lea eax, DWORD PTR __$EHRec$[ebp+4]
mov DWORD PTR fs:0, eax
mov DWORD PTR __$EHRec$[ebp], esp
mov DWORD PTR __$EHRec$[ebp+12], 1
; Line 12
mov BYTE PTR __$EHRec$[ebp+12], 2
; Line 14
push OFFSET $SG-77049
lea ecx, DWORD PTR $T148800[ebp]
call ??0?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@PBD@Z ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::basic_string<char,std::char_traits<char>,std::allocator<char> >
mov DWORD PTR tv225[ebp], eax
mov BYTE PTR __$EHRec$[ebp+12], 3
push 80 ; 00000050H
lea eax, DWORD PTR $T148800[ebp]
push eax
call ?connect@dlib@@YAPAVconnection@1@ABV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@G@Z ; dlib::connect
add esp, 8
mov DWORD PTR tv226[ebp], eax
mov ecx, DWORD PTR tv226[ebp]
push ecx
lea ecx, DWORD PTR _con$148801[ebp]
call ??0?$scoped_ptr@Vconnection@dlib@@U?$default_deleter@Vconnection@dlib@@@2@@dlib@@QAE@PAVconnection@1@@Z ; dlib::scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >::scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >
mov BYTE PTR __$EHRec$[ebp+12], 5
lea ecx, DWORD PTR $T148800[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
; Line 17
lea ecx, DWORD PTR _sMessage$[ebp]
call ?length@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QBEIXZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::length
mov DWORD PTR _size$148803[ebp], eax
; Line 18
mov DWORD PTR _i$148804[ebp], 0
jmp SHORT $LN6@notificate
$LN5@notificate:
mov edx, DWORD PTR _i$148804[ebp]
add edx, 1
mov DWORD PTR _i$148804[ebp], edx
$LN6@notificate:
mov eax, DWORD PTR _i$148804[ebp]
cmp eax, DWORD PTR _size$148803[ebp]
jae SHORT $LN4@notificate
; Line 19
mov ecx, DWORD PTR _i$148804[ebp]
push ecx
lea ecx, DWORD PTR _sMessage$[ebp]
call ??A?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAEAADI@Z ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::operator[]
movsx edx, BYTE PTR [eax]
cmp edx, 32 ; 00000020H
jne SHORT $LN3@notificate
; Line 20
push OFFSET $SG-77050
push 1
mov eax, DWORD PTR _i$148804[ebp]
push eax
lea ecx, DWORD PTR _sMessage$[ebp]
call ?replace@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAEAAV12@IIPBD@Z ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::replace
$LN3@notificate:
; Line 23
jmp SHORT $LN5@notificate
$LN4@notificate:
lea ecx, DWORD PTR _sAPIKey$[ebp]
push ecx
push OFFSET $SG-77053
lea edx, DWORD PTR $T148810[ebp]
push edx
call ??$?HDU?$char_traits@D@std@@V?$allocator@D@1@@std@@YA?AV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@0@PBDABV10@@Z ; std::operator+<char,std::char_traits<char>,std::allocator<char> >
add esp, 12 ; 0000000cH
mov DWORD PTR tv67[ebp], eax
mov eax, DWORD PTR tv67[ebp]
mov DWORD PTR tv205[ebp], eax
mov BYTE PTR __$EHRec$[ebp+12], 6
push OFFSET $SG-77052
mov ecx, DWORD PTR tv205[ebp]
push ecx
lea edx, DWORD PTR $T148811[ebp]
push edx
call ??$?HDU?$char_traits@D@std@@V?$allocator@D@1@@std@@YA?AV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@0@$$QAV10@PBD@Z ; std::operator+<char,std::char_traits<char>,std::allocator<char> >
add esp, 12 ; 0000000cH
mov DWORD PTR tv227[ebp], eax
mov eax, DWORD PTR tv227[ebp]
mov DWORD PTR tv207[ebp], eax
mov BYTE PTR __$EHRec$[ebp+12], 7
lea ecx, DWORD PTR _sMessage$[ebp]
push ecx
mov edx, DWORD PTR tv207[ebp]
push edx
lea eax, DWORD PTR $T148876[ebp]
push eax
call ??$?HDU?$char_traits@D@std@@V?$allocator@D@1@@std@@YA?AV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@0@$$QAV10@ABV10@@Z ; std::operator+<char,std::char_traits<char>,std::allocator<char> >
add esp, 12 ; 0000000cH
mov DWORD PTR tv228[ebp], eax
mov ecx, DWORD PTR tv228[ebp]
mov DWORD PTR tv209[ebp], ecx
mov BYTE PTR __$EHRec$[ebp+12], 8
push OFFSET $SG-77051
mov edx, DWORD PTR tv209[ebp]
push edx
lea eax, DWORD PTR $T148877[ebp]
push eax
call ??$?HDU?$char_traits@D@std@@V?$allocator@D@1@@std@@YA?AV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@0@$$QAV10@PBD@Z ; std::operator+<char,std::char_traits<char>,std::allocator<char> >
add esp, 12 ; 0000000cH
mov DWORD PTR tv229[ebp], eax
mov ecx, DWORD PTR tv229[ebp]
mov DWORD PTR tv211[ebp], ecx
mov BYTE PTR __$EHRec$[ebp+12], 9
mov edx, DWORD PTR tv211[ebp]
push edx
lea ecx, DWORD PTR _sMessage$[ebp]
call ??4?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAEAAV01@$$QAV01@@Z ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::operator=
mov BYTE PTR __$EHRec$[ebp+12], 8
lea ecx, DWORD PTR $T148877[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov BYTE PTR __$EHRec$[ebp+12], 7
lea ecx, DWORD PTR $T148876[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov BYTE PTR __$EHRec$[ebp+12], 6
lea ecx, DWORD PTR $T148811[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov BYTE PTR __$EHRec$[ebp+12], 5
lea ecx, DWORD PTR $T148810[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
; Line 24
lea ecx, DWORD PTR _sMessage$[ebp]
call ?size@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QBEIXZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::size
mov esi, eax
lea ecx, DWORD PTR _sMessage$[ebp]
call ?size@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QBEIXZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::size
push eax
lea ecx, DWORD PTR _sMessage$[ebp]
call ?c_str@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QBEPBDXZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::c_str
push eax
lea ecx, DWORD PTR _con$148801[ebp]
call ??C?$scoped_ptr@Vconnection@dlib@@U?$default_deleter@Vconnection@dlib@@@2@@dlib@@QBEPAVconnection@1@XZ ; dlib::scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >::operator->
mov ecx, eax
call ?write@connection@dlib@@QAEJPBDJ@Z ; dlib::connection::write
cmp eax, esi
je SHORT $LN2@notificate
; Line 25
mov BYTE PTR $T369472[ebp], 0
mov BYTE PTR __$EHRec$[ebp+12], 2
lea ecx, DWORD PTR _con$148801[ebp]
call ??1?$scoped_ptr@Vconnection@dlib@@U?$default_deleter@Vconnection@dlib@@@2@@dlib@@QAE@XZ ; dlib::scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >::~scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >
mov BYTE PTR __$EHRec$[ebp+12], 0
lea ecx, DWORD PTR _sAPIKey$[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov DWORD PTR __$EHRec$[ebp+12], -1
lea ecx, DWORD PTR _sMessage$[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov al, BYTE PTR $T369472[ebp]
jmp $LN8@notificate
$LN2@notificate:
; Line 28
push 200 ; 000000c8H
push 256 ; 00000100H
lea eax, DWORD PTR _sBuffer$148795[ebp]
push eax
lea ecx, DWORD PTR _con$148801[ebp]
call ??C?$scoped_ptr@Vconnection@dlib@@U?$default_deleter@Vconnection@dlib@@@2@@dlib@@QBEPAVconnection@1@XZ ; dlib::scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >::operator->
mov ecx, eax
call ?read@connection@dlib@@QAEJPADJK@Z ; dlib::connection::read
; Line 30
lea ecx, DWORD PTR _sBuffer$148795[ebp]
push ecx
lea ecx, DWORD PTR $T148884[ebp]
call ??0?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@PBD@Z ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::basic_string<char,std::char_traits<char>,std::allocator<char> >
mov DWORD PTR tv216[ebp], eax
push 0
push OFFSET $SG-77054
mov ecx, DWORD PTR tv216[ebp]
call ?find@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QBEIPBDI@Z ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::find
mov DWORD PTR $T369473[ebp], eax
lea ecx, DWORD PTR $T148884[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
cmp DWORD PTR $T369473[ebp], 0
je SHORT $LN1@notificate
; Line 31
mov BYTE PTR $T369474[ebp], 0
mov BYTE PTR __$EHRec$[ebp+12], 2
lea ecx, DWORD PTR _con$148801[ebp]
call ??1?$scoped_ptr@Vconnection@dlib@@U?$default_deleter@Vconnection@dlib@@@2@@dlib@@QAE@XZ ; dlib::scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >::~scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >
mov BYTE PTR __$EHRec$[ebp+12], 0
lea ecx, DWORD PTR _sAPIKey$[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov DWORD PTR __$EHRec$[ebp+12], -1
lea ecx, DWORD PTR _sMessage$[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov al, BYTE PTR $T369474[ebp]
jmp $LN8@notificate
$LN1@notificate:
; Line 33
push 500 ; 000001f4H
lea edx, DWORD PTR _con$148801[ebp]
push edx
call ?close_gracefully@dlib@@YAXAAV?$scoped_ptr@Vconnection@dlib@@U?$default_deleter@Vconnection@dlib@@@2@@1@K@Z ; dlib::close_gracefully
add esp, 8
; Line 34
mov BYTE PTR __$EHRec$[ebp+12], 2
lea ecx, DWORD PTR _con$148801[ebp]
call ??1?$scoped_ptr@Vconnection@dlib@@U?$default_deleter@Vconnection@dlib@@@2@@dlib@@QAE@XZ ; dlib::scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >::~scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >
jmp SHORT $LN10@notificate
__catch$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$0:
; Line 37
mov eax, DWORD PTR _e$148889[ebp]
mov edx, DWORD PTR [eax]
mov ecx, DWORD PTR _e$148889[ebp]
mov eax, DWORD PTR [edx+4]
call eax
sub esp, 28 ; 0000001cH
mov ecx, esp
mov DWORD PTR $T369475[ebp], esp
push eax
call ??0?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@PBD@Z ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::basic_string<char,std::char_traits<char>,std::allocator<char> >
mov DWORD PTR tv221[ebp], eax
push 37 ; 00000025H
push OFFSET $SG-77055
push OFFSET $SG-77056
call ?error@log@helper@@YAXPBD0JV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@@Z ; helper::log::error
add esp, 40 ; 00000028H
; Line 38
mov DWORD PTR __$EHRec$[ebp+12], 1
mov eax, __tryend$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$1
ret 0
$LN10@notificate:
mov DWORD PTR __$EHRec$[ebp+12], 1
__tryend$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$1:
; Line 40
mov BYTE PTR $T369476[ebp], 1
mov BYTE PTR __$EHRec$[ebp+12], 0
lea ecx, DWORD PTR _sAPIKey$[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov DWORD PTR __$EHRec$[ebp+12], -1
lea ecx, DWORD PTR _sMessage$[ebp]
call ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
mov al, BYTE PTR $T369476[ebp]
$LN8@notificate:
; Line 41
mov ecx, DWORD PTR __$EHRec$[ebp+4]
mov DWORD PTR fs:0, ecx
pop ecx
pop edi
pop esi
pop ebx
mov ecx, DWORD PTR __$ArrayPad$[ebp]
xor ecx, ebp
call @__security_check_cookie@4
mov esp, ebp
pop ebp
ret 0
_TEXT ENDS
; COMDAT text$x
text$x SEGMENT
__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$2:
lea ecx, DWORD PTR _sMessage$[ebp]
jmp ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$3:
lea ecx, DWORD PTR _sAPIKey$[ebp]
jmp ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$4:
lea ecx, DWORD PTR $T148800[ebp]
jmp ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$5:
lea ecx, DWORD PTR _con$148801[ebp]
jmp ??1?$scoped_ptr@Vconnection@dlib@@U?$default_deleter@Vconnection@dlib@@@2@@dlib@@QAE@XZ ; dlib::scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >::~scoped_ptr<dlib::connection,dlib::default_deleter<dlib::connection> >
__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$6:
lea ecx, DWORD PTR $T148810[ebp]
jmp ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$7:
lea ecx, DWORD PTR $T148811[ebp]
jmp ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$8:
lea ecx, DWORD PTR $T148876[ebp]
jmp ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
__unwindfunclet$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z$9:
lea ecx, DWORD PTR $T148877[ebp]
jmp ??1?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAE@XZ ; std::basic_string<char,std::char_traits<char>,std::allocator<char> >::~basic_string<char,std::char_traits<char>,std::allocator<char> >
__ehhandler$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z:
mov edx, DWORD PTR [esp+8]
lea eax, DWORD PTR [edx+12]
mov ecx, DWORD PTR [edx-536]
xor ecx, eax
call @__security_check_cookie@4
mov ecx, DWORD PTR [edx-8]
xor ecx, eax
call @__security_check_cookie@4
mov eax, OFFSET __ehfuncinfo$?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z
jmp ___CxxFrameHandler3
text$x ENDS
?notificate@notifymyandroid@@YA_NV?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@0@Z ENDP ; notifymyandroid::notificate
END
|
; A094328: Iterate the map in A006369 starting at 4.
; 4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6,4,5,7,9,6
mod $0,5
mov $1,7
lpb $0
sub $1,$0
sub $0,1
mul $1,2
lpe
sub $1,4
div $1,3
add $1,3
mov $0,$1
|
; A023620: Convolution of Lucas numbers and odd numbers.
; 1,6,18,41,82,152,269,462,778,1293,2130,3488,5689,9254,15026,24369,39490,63960,103557,167630,271306,439061,710498,1149696,1860337,3010182,4870674,7881017,12751858,20633048,33385085,54018318,87403594,141422109,228825906
mov $2,$0
add $2,1
mov $7,$0
lpb $2
mov $0,$7
sub $2,1
sub $0,$2
mov $5,0
mov $6,2
lpb $0
sub $0,1
mov $3,$6
add $6,4
add $6,$5
mov $5,$3
lpe
mov $4,$0
add $4,$6
div $4,2
add $5,$4
add $1,$5
lpe
mov $0,$1
|
;;
;; Copyright (c) 2021, Intel Corporation
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;; * Redistributions of source code must retain the above copyright notice,
;; this list of conditions and the following disclaimer.
;; * Redistributions in binary form must reproduce the above copyright
;; notice, this list of conditions and the following disclaimer in the
;; documentation and/or other materials provided with the distribution.
;; * Neither the name of Intel Corporation nor the names of its contributors
;; may be used to endorse or promote products derived from this software
;; without specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;
%include "include/os.asm"
%include "include/reg_sizes.asm"
%include "include/cet.inc"
%include "include/memcpy.asm"
%include "include/const.inc"
%include "include/aes_common.asm"
%define APPEND(a,b) a %+ b
%define APPEND3(a,b,c) a %+ b %+ c
%ifdef LINUX
%define arg1 rdi
%define arg2 rsi
%define arg3 rdx
%define arg4 rcx
%else
%define arg1 rcx
%define arg2 rdx
%define arg3 r8
%define arg4 r9
%endif
%define E rax
%define qword_len r12
%define offset r10
%define tmp r10
%define tmp2 arg4
%define tmp3 r11
%define tmp4 r13
%define tmp5 r14
%define tmp6 r15
%define in_ptr arg1
%define KS arg2
%define bit_len arg3
%define end_offset tmp3
%define EV xmm2
%define SNOW3G_CONST xmm7
%define P1 xmm8
%define BSWAP64_MASK zmm12
%define INSERT_HIGH64_MASK k1
section .data
default rel
align 64
snow3g_constant:
dq 0x000000000000001b, 0x0000000000000000
dq 0x000000000000001b, 0x0000000000000000
dq 0x000000000000001b, 0x0000000000000000
dq 0x000000000000001b, 0x0000000000000000
align 64
bswap64:
dq 0x0001020304050607, 0x08090a0b0c0d0e0f
dq 0x0001020304050607, 0x08090a0b0c0d0e0f
dq 0x0001020304050607, 0x08090a0b0c0d0e0f
dq 0x0001020304050607, 0x08090a0b0c0d0e0f
align 64
mask64:
dq 0xffffffffffffffff,
dq 0xff,
dq 0xffff,
dq 0xffffff,
dq 0xffffffff,
dq 0xffffffffff,
dq 0xffffffffffff,
dq 0xffffffffffffff
align 64
swap_qwords:
dq 0x0f0e0d0c0b0a0908, 0x0706050403020100
dq 0x0f0e0d0c0b0a0908, 0x0706050403020100
dq 0x0f0e0d0c0b0a0908, 0x0706050403020100
dq 0x0f0e0d0c0b0a0908, 0x0706050403020100
section .text
%ifidn __OUTPUT_FORMAT__, win64
%define XMM_STORAGE 16*7
%define GP_STORAGE 8*8
%else
%define XMM_STORAGE 0
%define GP_STORAGE 6*8
%endif
%define CONSTANTS_STORAGE 8*32 ;; 32 8 byte blocks
%define VARIABLE_OFFSET XMM_STORAGE + GP_STORAGE + CONSTANTS_STORAGE
%define GP_OFFSET XMM_STORAGE
%define CONSTANTS_OFFSET XMM_STORAGE + GP_STORAGE
%macro FUNC_SAVE 0
mov r11, rsp
sub rsp, VARIABLE_OFFSET
and rsp, ~15
%ifidn __OUTPUT_FORMAT__, win64
; maintain xmms on Windows
vmovdqa [rsp + 0*16], xmm6
vmovdqa [rsp + 1*16], xmm7
vmovdqa [rsp + 2*16], xmm8
vmovdqa [rsp + 3*16], xmm9
vmovdqa [rsp + 4*16], xmm10
vmovdqa [rsp + 5*16], xmm11
vmovdqa [rsp + 6*16], xmm12
mov [rsp + GP_OFFSET + 48], rdi
mov [rsp + GP_OFFSET + 56], rsi
%endif
mov [rsp + GP_OFFSET], r12
mov [rsp + GP_OFFSET + 8], r13
mov [rsp + GP_OFFSET + 16], r14
mov [rsp + GP_OFFSET + 24], r15
mov [rsp + GP_OFFSET + 32], rbx
mov [rsp + GP_OFFSET + 40], r11 ;; rsp pointer
%endmacro
%macro FUNC_RESTORE 0
%ifidn __OUTPUT_FORMAT__, win64
vmovdqa xmm6, [rsp + 0*16]
vmovdqa xmm7, [rsp + 1*16]
vmovdqa xmm8, [rsp + 2*16]
vmovdqa xmm9, [rsp + 3*16]
vmovdqa xmm10, [rsp + 4*16]
vmovdqa xmm11, [rsp + 5*16]
vmovdqa xmm12, [rsp + 6*16]
mov rdi, [rsp + GP_OFFSET + 48]
mov rsi, [rsp + GP_OFFSET + 56]
%endif
mov r12, [rsp + GP_OFFSET]
mov r13, [rsp + GP_OFFSET + 8]
mov r14, [rsp + GP_OFFSET + 16]
mov r15, [rsp + GP_OFFSET + 24]
mov rbx, [rsp + GP_OFFSET + 32]
mov rsp, [rsp + GP_OFFSET + 40]
%endmacro
;; Horizontal XOR - 4 x 128bits xored together
%macro VHPXORI4x128 2
%define %%REG %1 ;; [in/out] zmm with 4x128bits to xor; 128bit output
%define %%TMP %2 ;; [clobbered] zmm temporary register
vextracti64x4 YWORD(%%TMP), %%REG, 1
vpxorq YWORD(%%REG), YWORD(%%REG), YWORD(%%TMP)
vextracti32x4 XWORD(%%TMP), YWORD(%%REG), 1
vpxorq XWORD(%%REG), XWORD(%%REG), XWORD(%%TMP)
%endmacro
;; Horizontal XOR - 2 x 128bits xored together
%macro VHPXORI2x128 2
%define %%REG %1 ; [in/out] YMM/ZMM with 2x128bits to xor; 128bit output
%define %%TMP %2 ; [clobbered] XMM/YMM/ZMM temporary register
vextracti32x4 XWORD(%%TMP), %%REG, 1
vpxorq XWORD(%%REG), XWORD(%%REG), XWORD(%%TMP)
%endmacro
;; Reduce from 128 bits to 64 bits
%macro REDUCE_TO_64 2
%define %%IN_OUT %1 ;; [in/out]
%define %%XTMP %2 ;; [clobbered]
vpclmulqdq %%XTMP, %%IN_OUT, SNOW3G_CONST, 0x01
vpxor %%IN_OUT, %%IN_OUT, %%XTMP
vpclmulqdq %%XTMP, %%XTMP, SNOW3G_CONST, 0x01
vpxor %%IN_OUT, %%IN_OUT, %%XTMP
%endmacro
;; Multiply 64b x 64b and reduce result to 64 bits
;; Lower 64-bits of xmms are multiplied
%macro MUL_AND_REDUCE_64x64_LOW 2-3
%define %%IN0_OUT %1 ;; [in/out]
%define %%IN1 %2 ;; [in] Note: clobbered when only 2 args passed
%define %%XTMP %3 ;; [clobbered]
vpclmulqdq %%IN0_OUT, %%IN0_OUT, %%IN1, 0x00
%if %0 == 2
;; clobber XTMP1 if 3 args passed, otherwise preserve
REDUCE_TO_64 %%IN0_OUT, %%IN1
%else
REDUCE_TO_64 %%IN0_OUT, %%XTMP
%endif
%endmacro
;; Multiply 64b x 64b blocks and reduce result to 64 bits.
;; Lower and higher 64-bits of all 128-bit lanes are multiplied.
;; Passing different size regs will operate on a different number of blocks
;; - xmms => 2x2 blocks
;; - ymms => 4x4 blocks
;; - zmms => 8x8 blocks
;; Results are combined and returned in single register
%macro MUL_AND_REDUCE_64x64 7
%define %%IN0_OUT %1 ;; [in/out] xmm/ymm/zmm with multiply first operands
%define %%IN1 %2 ;; [in] xmm/ymm/zmm with multiply second operands
%define %%T1 %3 ;; [clobbered] xmm/ymm/zmm
%define %%T2 %4 ;; [clobbered] xmm/ymm/zmm
%define %%T3 %5 ;; [clobbered] xmm/ymm/zmm
%define %%T4 %6 ;; [clobbered] xmm/ymm/zmm
%define %%SNOW3G_CONST %7 ;; [in] xmm/ymm/zmm with SNOW3G constant
;; perform multiplication
vpclmulqdq %%T1, %%IN0_OUT, %%IN1, 0x00 ; %%T1 = a0*b0 (for xmms)
vpclmulqdq %%T2, %%IN0_OUT, %%IN1, 0x11 ; %%T2 = a1*b1
;; perform reduction on results
vpclmulqdq %%T3, %%T1, %%SNOW3G_CONST, 0x01
vpclmulqdq %%T4, %%T2, %%SNOW3G_CONST, 0x01
vpxorq %%T1, %%T1, %%T3
vpxorq %%T2, %%T2, %%T4
vpclmulqdq %%T3, %%T3, %%SNOW3G_CONST, 0x01
vpclmulqdq %%T4, %%T4, %%SNOW3G_CONST, 0x01
vpxorq %%IN0_OUT, %%T1, %%T3
vpxorq %%T2, %%T2, %%T4
;; combine results into single register
vpunpcklqdq %%IN0_OUT, %%IN0_OUT, %%T2
%endmacro
;; Precompute powers of P up to P^4 or P^32
;; Results are arranged from highest power to lowest at 128b granularity
;; Example:
;; For up to P^4, results are returned in a 2 XMM registers
;; register in the following order:
;; OUT0[P1P2]
;; OUT1[P3P4]
;; For up to P^32, results are returned in 4 ZMM registers
;; in the following order:
;; OUT0[P7P8, P5P6, P3P4, P1P2]
;; OUT1[P15P16, P13P14, P11P12, P9P10]
;; OUT2[P23P24, P21P22, P19P20, P17P18]
;; OUT3[P31P32, P29P30, P27P28, P25P26]
;; Powers are also reorganized and stored on the stack for processing final <32 blocks
%macro PRECOMPUTE_CONSTANTS 8-11
%define %%P1 %1 ;; [in] initial P^1 to be multiplied
%define %%HIGHEST_POWER %2 ;; [in] highest power to calculate (4 or 32)
%define %%OUT0 %3 ;; [out] ymm/zmm containing results
%define %%OUT1 %4 ;; [out] ymm/zmm containing results
%define %%T1 %5 ;; [clobbered] xmm
%define %%T2 %6 ;; [clobbered] xmm
%define %%T3 %7 ;; [clobbered] xmm
%define %%T4 %8 ;; [clobbered] xmm
%define %%T5 %9 ;; [clobbered] xmm
%define %%OUT2 %10 ;; [out] zmm containing results
%define %%OUT3 %11 ;; [out] zmm containing results
%if %0 > 8
%xdefine %%Y_OUT0 YWORD(%%OUT0)
%xdefine %%Y_OUT1 YWORD(%%OUT1)
%xdefine %%YT1 YWORD(%%T1)
%xdefine %%YT2 YWORD(%%T2)
%xdefine %%YT3 YWORD(%%T3)
%xdefine %%YT4 YWORD(%%T4)
%xdefine %%YT5 YWORD(%%T5)
%xdefine %%Z_OUT0 ZWORD(%%OUT0)
%xdefine %%Z_OUT1 ZWORD(%%OUT1)
%xdefine %%Z_OUT2 ZWORD(%%OUT2)
%xdefine %%Z_OUT3 ZWORD(%%OUT3)
%xdefine %%ZT1 ZWORD(%%T1)
%xdefine %%ZT2 ZWORD(%%T2)
%xdefine %%ZT3 ZWORD(%%T3)
%xdefine %%ZT4 ZWORD(%%T4)
%xdefine %%ZT5 ZWORD(%%T5)
%endif
vmovdqa %%T1, %%P1
MUL_AND_REDUCE_64x64_LOW %%T1, %%P1, %%T4 ;; %%T1 = P2
vmovdqa %%T2, %%T1
MUL_AND_REDUCE_64x64_LOW %%T2, %%P1, %%T4 ;; %%T2 = P3
vmovq %%T2, %%T2
vmovdqa %%T3, %%T2
MUL_AND_REDUCE_64x64_LOW %%T3, %%P1, %%T4 ;; %%T3 = P4
%if %%HIGHEST_POWER <= 4
;; if highest power is 4 then put
;; P1P2 in OUT0 and P3P4 OUT1 and finish
vpunpcklqdq %%OUT0, %%P1, %%T1 ;; P1P2
vpunpcklqdq %%OUT1, %%T2, %%T3 ;; P3P4
%else
;; otherwise arrange powers later
vpunpcklqdq %%OUT0, %%P1, %%T1 ;; P1P2
vpunpcklqdq %%T1, %%T2, %%T3 ;; P3P4
vinserti64x2 %%Y_OUT0, %%Y_OUT0, %%T1, 0x1 ;; P1P2P3P4
vpermq %%YT1, %%Y_OUT0, 0xff ;; broadcast P4 across T1
;; P1 P2 P3 P4
;; * P4 P4 P4 P4
;; ------------------
;; P5 P6 P7 P8
MUL_AND_REDUCE_64x64 %%YT1, %%Y_OUT0, %%YT2, %%YT3, %%YT4, %%YT5, YWORD(SNOW3G_CONST)
;; T1 contains P5-P8
;; insert P5P6P7P8 into high 256bits of OUT0
vinserti64x4 %%Z_OUT0, %%Z_OUT0, %%YT1, 0x1
;; broadcast P8 across OUT1 and multiply
valignq %%YT1, %%YT1, %%YT1, 3
vpbroadcastq %%Z_OUT1, %%T1
;; P1 P2 P3 P4 P5 P6 P7 P8
;; * P8 P8 P8 P8 P8 P8 P8 P8
;; -------------------------
;; P9P10P11P12P13P14P15P16
MUL_AND_REDUCE_64x64 %%Z_OUT1, %%Z_OUT0, %%ZT2, %%ZT3, %%ZT4, %%ZT5, ZWORD(SNOW3G_CONST)
;; broadcast P16 across OUT2 and multiply
valignq %%ZT1, %%Z_OUT1, %%Z_OUT1, 7
vpbroadcastq %%Z_OUT2, %%T1
;; P1 P2 P3 P4 P5 P6 P7 P8
;; * P16 P16 P16 P16 P16 P16 P16 P16
;; -------------------------
;; P17 P18 P19 P20 P21 P22 P23 P24
MUL_AND_REDUCE_64x64 %%Z_OUT2, %%Z_OUT0, %%ZT2, %%ZT3, %%ZT4, %%ZT5, ZWORD(SNOW3G_CONST)
;; broadcast P24 across OUT3 and multiply
valignq %%ZT1, %%Z_OUT2, %%Z_OUT2, 7
vpbroadcastq %%Z_OUT3, %%T1
;; P1 P2 P3 P4 P5 P6 P7 P8
;; * P24 P24 P24 P24 P24 P24 P24 P24
;; -------------------------
;; P25 P26 P27 P28 P29 P30 P31 P32
MUL_AND_REDUCE_64x64 %%Z_OUT3, %%Z_OUT0, %%ZT2, %%ZT3, %%ZT4, %%ZT5, ZWORD(SNOW3G_CONST)
;; put the highest powers to the lower lanes
vshufi64x2 %%Z_OUT0, %%Z_OUT0, %%Z_OUT0, 00_01_10_11b ;; P7P8P, P5P6, P3P4, P1P2
vshufi64x2 %%Z_OUT1, %%Z_OUT1, %%Z_OUT1, 00_01_10_11b ;; P15P16, P13P14, P11P12, P9P10
vshufi64x2 %%Z_OUT2, %%Z_OUT2, %%Z_OUT2, 00_01_10_11b ;; P23P24, P21P22, P19P20, P17P18
vshufi64x2 %%Z_OUT3, %%Z_OUT3, %%Z_OUT3, 00_01_10_11b ;; P31P32, P29P30, P27P28, P25P26
;; store powers on stack in sequential order
;; (e.g. P32, P31 ... P2, P1) for processing final blocks
vmovdqa64 %%ZT5, [rel swap_qwords]
vpshufb %%ZT1, %%Z_OUT0, %%ZT5
vpshufb %%ZT2, %%Z_OUT1, %%ZT5
vpshufb %%ZT3, %%Z_OUT2, %%ZT5
vpshufb %%ZT4, %%Z_OUT3, %%ZT5
vmovdqu64 [rsp + CONSTANTS_OFFSET + 0*64], %%ZT4
vmovdqu64 [rsp + CONSTANTS_OFFSET + 1*64], %%ZT3
vmovdqu64 [rsp + CONSTANTS_OFFSET + 2*64], %%ZT2
vmovdqu64 [rsp + CONSTANTS_OFFSET + 3*64], %%ZT1
%endif
%endmacro
;; Process final 1 - 31 blocks
%macro PROCESS_FINAL_BLOCKS 21
%define %%MAX_BLOCKS %1 ;; [in] max possible number of final blocks
%define %%IN %2 ;; [in] gp reg with input pointer
%define %%NUM_BLOCKS %3 ;; [in] gp reg with number remaining full blocks
%define %%MASK %4 ;; [in] final 1-8 blocks mask
%define %%CONST_TAB_OFFSET %5 ;; [in] gp reg with constants table offset
%define %%DATA0 %6 ;; [clobbered] zmm to store message data
%define %%DATA1 %7 ;; [clobbered] zmm to store message data
%define %%DATA2 %8 ;; [clobbered] zmm to store message data
%define %%DATA3 %9 ;; [clobbered] zmm to store message data
%define %%TMP0 %10 ;; [clobbered] zmm
%define %%TMP1 %11 ;; [clobbered] zmm
%define %%TMP2 %12 ;; [clobbered] zmm
%define %%TMP3 %13 ;; [clobbered] zmm
%define %%TMP4 %14 ;; [clobbered] zmm
%define %%TMP5 %15 ;; [clobbered] zmm
%define %%TMP6 %16 ;; [clobbered] zmm
%define %%TMP7 %17 ;; [clobbered] zmm
%define %%TMP8 %18 ;; [clobbered] zmm
%define %%TMP9 %19 ;; [clobbered] zmm
%define %%TMP10 %20 ;; [clobbered] zmm
%define %%TMP11 %21 ;; [clobbered] zmm
%ifidn %%MAX_BLOCKS, 31
;; up to 31 blocks
ZMM_LOAD_MASKED_BLOCKS_0_16 16, %%IN, 0, %%DATA0, %%DATA1, %%DATA2, %%DATA3, %%MASK
ZMM_LOAD_MASKED_BLOCKS_0_16 16, rsp, %%CONST_TAB_OFFSET*8 + CONSTANTS_OFFSET, \
%%TMP0, %%TMP1, %%TMP2, %%TMP3, %%MASK
%endif
%ifidn %%MAX_BLOCKS, 24
;; up to 24 blocks
ZMM_LOAD_MASKED_BLOCKS_0_16 12, %%IN, 0, %%DATA0, %%DATA1, %%DATA2, %%DATA3, %%MASK
ZMM_LOAD_MASKED_BLOCKS_0_16 12, rsp, %%CONST_TAB_OFFSET*8 + CONSTANTS_OFFSET, \
%%TMP0, %%TMP1, %%TMP2, %%TMP3, %%MASK
;; zero unused blocks
vpxorq %%DATA3, %%DATA3, %%DATA3
vpxorq %%TMP3, %%TMP3, %%TMP3
%endif
%ifidn %%MAX_BLOCKS, 16
;; up to 16 blocks
ZMM_LOAD_MASKED_BLOCKS_0_16 8, %%IN, 0, %%DATA0, %%DATA1, %%DATA2, %%DATA3, %%MASK
ZMM_LOAD_MASKED_BLOCKS_0_16 8, rsp, %%CONST_TAB_OFFSET*8 + CONSTANTS_OFFSET, \
%%TMP0, %%TMP1, %%TMP2, %%TMP3, %%MASK
;; zero unused blocks
vpxorq %%DATA2, %%DATA2, %%DATA2
vpxorq %%DATA3, %%DATA3, %%DATA3
vpxorq %%TMP2, %%TMP2, %%TMP2
vpxorq %%TMP3, %%TMP3, %%TMP3
%endif
%ifidn %%MAX_BLOCKS, 8
;; 1 to 8 blocks
ZMM_LOAD_MASKED_BLOCKS_0_16 4, %%IN, 0, %%DATA0, %%DATA1, %%DATA2, %%DATA3, %%MASK
ZMM_LOAD_MASKED_BLOCKS_0_16 4, rsp, %%CONST_TAB_OFFSET*8 + CONSTANTS_OFFSET, \
%%TMP0, %%TMP1, %%TMP2, %%TMP3, %%MASK
;; zero unused blocks
vpxorq %%DATA1, %%DATA1, %%DATA1
vpxorq %%DATA2, %%DATA2, %%DATA2
vpxorq %%DATA3, %%DATA3, %%DATA3
vpxorq %%TMP1, %%TMP1, %%TMP1
vpxorq %%TMP2, %%TMP2, %%TMP2
vpxorq %%TMP3, %%TMP3, %%TMP3
%endif
;; reverse block byte order
vpshufb %%DATA0, %%DATA0, BSWAP64_MASK
vpshufb %%DATA1, %%DATA1, BSWAP64_MASK
vpshufb %%DATA2, %%DATA2, BSWAP64_MASK
vpshufb %%DATA3, %%DATA3, BSWAP64_MASK
;; add EV
vpxorq %%DATA0, %%DATA0, ZWORD(EV)
;; perform multiplication
vpclmulqdq %%TMP4, %%DATA0, %%TMP0, 0x00
vpclmulqdq %%TMP5, %%DATA0, %%TMP0, 0x11
vpclmulqdq %%TMP6, %%DATA1, %%TMP1, 0x00
vpclmulqdq %%TMP7, %%DATA1, %%TMP1, 0x11
vpclmulqdq %%TMP8, %%DATA2, %%TMP2, 0x00
vpclmulqdq %%TMP9, %%DATA2, %%TMP2, 0x11
vpclmulqdq %%TMP10, %%DATA3, %%TMP3, 0x00
vpclmulqdq %%TMP11, %%DATA3, %%TMP3, 0x11
;; sum results
vpternlogq %%TMP6, %%TMP4, %%TMP5, 0x96
vpternlogq %%TMP7, %%TMP8, %%TMP9, 0x96
vpternlogq %%TMP6, %%TMP10, %%TMP11, 0x96
vpxorq ZWORD(EV), %%TMP6, %%TMP7
VHPXORI4x128 ZWORD(EV), %%TMP0
REDUCE_TO_64 EV, XWORD(%%TMP0)
vmovq XWORD(EV), XWORD(EV)
;; update input pointer
shl %%NUM_BLOCKS, 3
add %%IN, %%NUM_BLOCKS
%endmacro
;; uint32_t
;; snow3g_f9_1_buffer_internal_vaes_avx512(const uint64_t *pBufferIn,
;; const uint32_t KS[5],
;; const uint64_t lengthInBits);
align 64
MKGLOBAL(snow3g_f9_1_buffer_internal_vaes_avx512,function,internal)
snow3g_f9_1_buffer_internal_vaes_avx512:
endbranch64
FUNC_SAVE
vmovdqa64 ZWORD(SNOW3G_CONST), [rel snow3g_constant]
vmovdqa64 BSWAP64_MASK, [rel bswap64]
mov tmp, 10101010b
kmovq INSERT_HIGH64_MASK, tmp
vpxor EV, EV
;; P1 = ((uint64_t)KS[0] << 32) | ((uint64_t)KS[1])
vmovq P1, [KS]
vpshufd P1, P1, 1110_0001b
mov qword_len, bit_len ;; lenInBits -> lenInQwords
shr qword_len, 6
cmp qword_len, 32 ;; >=32 blocks go to 32 blocks loop
jae init_32_block_loop
cmp qword_len, 4 ;; check at least 4 blocks
jae init_4_block_loop
jmp single_block_check
init_32_block_loop:
;; precompute up to P^32
PRECOMPUTE_CONSTANTS P1, 32, xmm0, xmm1, xmm3, xmm4, xmm5, xmm6, xmm9, xmm20, xmm21
start_32_block_loop:
vmovdqu64 zmm3, [in_ptr]
vmovdqu64 zmm4, [in_ptr + 64]
vmovdqu64 zmm23, [in_ptr + 128]
vmovdqu64 zmm24, [in_ptr + 192]
vpshufb zmm3, zmm3, BSWAP64_MASK
vpshufb zmm4, zmm4, BSWAP64_MASK
vpshufb zmm23, zmm23, BSWAP64_MASK
vpshufb zmm24, zmm24, BSWAP64_MASK
vpxorq zmm3, zmm3, ZWORD(EV)
vpclmulqdq zmm5, zmm24, zmm0, 0x10 ;; p8 - p1
vpclmulqdq zmm6, zmm24, zmm0, 0x01 ;; x m24 - m31
vpclmulqdq zmm10, zmm23, zmm1, 0x10 ;; p16 - p9
vpclmulqdq zmm11, zmm23, zmm1, 0x01 ;; x m16 - m23
vpclmulqdq zmm25, zmm4, zmm20, 0x10 ;; p24 - p17
vpclmulqdq zmm26, zmm4, zmm20, 0x01 ;; x m8 - m15
vpclmulqdq zmm30, zmm3, zmm21, 0x10 ;; p32 - p25
vpclmulqdq zmm31, zmm3, zmm21, 0x01 ;; x m0 - m7
;; sum results
vpternlogq zmm10, zmm5, zmm6, 0x96
vpternlogq zmm11, zmm25, zmm26, 0x96
vpternlogq zmm10, zmm30, zmm31, 0x96
vpxorq ZWORD(EV), zmm10, zmm11
VHPXORI4x128 ZWORD(EV), zmm4
REDUCE_TO_64 EV, xmm3
vmovq XWORD(EV), XWORD(EV)
add in_ptr, 32*8
sub qword_len, 32
;; check no more full blocks
jz full_blocks_complete
;; check less than 32 blocks left
cmp qword_len, 32
jb lt32_blocks
jmp start_32_block_loop
lt32_blocks:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Less than 32 blocks remaining
;; Process between 1 and 31 final full blocks
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; set mask to load final 1-8 blocks
mov tmp, qword_len
and tmp, 0x7
lea tmp2, [rel mask64]
kmovq k2, [tmp2 + tmp*8]
;; calculate offset to load constants from stack
mov tmp4, 32
sub tmp4, qword_len
cmp qword_len, 16
jbe le16_blocks
cmp qword_len, 24
jbe le24_blocks
gt24_blocks:
;; 25 - 31 blocks
PROCESS_FINAL_BLOCKS 31, in_ptr, qword_len, k2, tmp4, zmm3, zmm4, zmm23, zmm24, zmm0, \
zmm1, zmm20, zmm21, zmm5, zmm6, zmm10, zmm11, zmm25, zmm26, zmm30, zmm31
jmp full_blocks_complete
le24_blocks:
;; 17 - 24 blocks
PROCESS_FINAL_BLOCKS 24, in_ptr, qword_len, k2, tmp4, zmm3, zmm4, zmm23, zmm24, zmm0, \
zmm1, zmm20, zmm21, zmm5, zmm6, zmm10, zmm11, zmm25, zmm26, zmm30, zmm31
jmp full_blocks_complete
le16_blocks:
cmp qword_len, 8
jbe le8_blocks
gt8_blocks:
;; 9 - 16 blocks
PROCESS_FINAL_BLOCKS 16, in_ptr, qword_len, k2, tmp4, zmm3, zmm4, zmm23, zmm24, zmm0, \
zmm1, zmm20, zmm21, zmm5, zmm6, zmm10, zmm11, zmm25, zmm26, zmm30, zmm31
jmp full_blocks_complete
le8_blocks:
;; 1 - 8 blocks
PROCESS_FINAL_BLOCKS 8, in_ptr, qword_len, k2, tmp4, zmm3, zmm4, zmm23, zmm24, zmm0, \
zmm1, zmm20, zmm21, zmm5, zmm6, zmm10, zmm11, zmm25, zmm26, zmm30, zmm31
jmp full_blocks_complete
init_4_block_loop:
;; precompute up to P^4
PRECOMPUTE_CONSTANTS P1, 4, xmm0, xmm1, xmm3, xmm4, xmm5, xmm6
start_4_block_loop:
vmovdqu xmm3, [in_ptr]
vmovdqu xmm4, [in_ptr + 16]
vpshufb xmm3, xmm3, XWORD(BSWAP64_MASK)
vpshufb xmm4, xmm4, XWORD(BSWAP64_MASK)
vpxor xmm3, xmm3, EV
vpclmulqdq xmm5, xmm4, xmm0, 0x10
vpclmulqdq xmm6, xmm4, xmm0, 0x01
vpclmulqdq xmm10, xmm3, xmm1, 0x10
vpclmulqdq xmm11, xmm3, xmm1, 0x01
vpxor xmm5, xmm5, xmm6
vpxor xmm6, xmm10, xmm11
vpxor EV, xmm6, xmm5
REDUCE_TO_64 EV, xmm3
vmovq EV, EV
add in_ptr, 4*8
sub qword_len, 4
cmp qword_len, 4
;; less than 4 blocks left
jb single_block_check
jmp start_4_block_loop
start_single_block_loop:
vmovq xmm0, [in_ptr]
vpshufb xmm0, xmm0, XWORD(BSWAP64_MASK)
vpxor EV, xmm0
MUL_AND_REDUCE_64x64_LOW EV, P1, xmm1
add in_ptr, 1*8
dec qword_len
single_block_check:
cmp qword_len, 0
jne start_single_block_loop
full_blocks_complete:
mov tmp5, 0x3f ;; len_in_bits % 64
and tmp5, bit_len
jz skip_rem_bits
;; load last N bytes
mov tmp2, tmp5 ;; (rem_bits + 7) / 8
add tmp2, 7
shr tmp2, 3
simd_load_avx_15_1 xmm3, in_ptr, tmp2
vmovq tmp3, xmm3
bswap tmp3
mov tmp, 0xffffffffffffffff
mov tmp6, 64
sub tmp6, tmp5
SHIFT_GP tmp, tmp6, tmp, tmp5, left
and tmp3, tmp ;; V &= (((uint64_t)-1) << (64 - rem_bits)); /* mask extra bits */
vmovq xmm0, tmp3
vpxor EV, xmm0
MUL_AND_REDUCE_64x64_LOW EV, P1, xmm3
skip_rem_bits:
;; /* Multiply by Q */
;; E = multiply_and_reduce64(E ^ lengthInBits,
;; (((uint64_t)z[2] << 32) | ((uint64_t)z[3])));
;; /* Final MAC */
;; *(uint32_t *)pDigest =
;; (uint32_t)BSWAP64(E ^ ((uint64_t)z[4] << 32));
vmovq xmm3, bit_len
vpxor EV, xmm3
vmovq xmm1, [KS + 8] ;; load z[2:3]
vpshufd xmm1, xmm1, 1110_0001b
mov DWORD(tmp4), [KS + (4 * 4)] ;; tmp4 == z[4] << 32
shl tmp4, 32
MUL_AND_REDUCE_64x64_LOW EV, xmm1, xmm3
vmovq E, EV
xor E, tmp4
bswap E ;; return E (rax/eax)
FUNC_RESTORE
ret
%ifdef LINUX
section .note.GNU-stack noalloc noexec nowrite progbits
%endif
|
; ===============================================================
; Apr 2016
; ===============================================================
;
; uint16_t htons(uint16_t)
;
; Change host byte order to network byte order.
;
; ===============================================================
SECTION code_clib
SECTION code_network
PUBLIC asm_htons
asm_htons:
; enter : hl = host order port
;
; exit : hl = network order port
;
; uses : a, hl
ld a,l
ld l,h
ld h,a
ret
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r13
push %r15
push %r9
push %rax
push %rcx
push %rdi
push %rsi
lea addresses_A_ht+0x194f7, %rsi
lea addresses_D_ht+0xe9bb, %rdi
add %r13, %r13
mov $122, %rcx
rep movsb
nop
dec %r10
lea addresses_WC_ht+0x7e37, %r9
nop
nop
nop
nop
and $3257, %r15
mov (%r9), %esi
nop
nop
nop
nop
nop
sub %rsi, %rsi
lea addresses_A_ht+0x19cf7, %rsi
lea addresses_normal_ht+0x1c4f7, %rdi
nop
inc %rax
mov $101, %rcx
rep movsl
nop
nop
nop
nop
cmp $15209, %rcx
lea addresses_WT_ht+0x1a2d7, %r9
nop
nop
nop
nop
cmp $29119, %rcx
mov (%r9), %r15w
nop
nop
nop
and $10253, %r10
lea addresses_A_ht+0x102ab, %r13
nop
sub %r15, %r15
movw $0x6162, (%r13)
nop
sub $33862, %r9
lea addresses_WT_ht+0xe323, %rdi
clflush (%rdi)
nop
nop
nop
add %rsi, %rsi
movb $0x61, (%rdi)
nop
nop
nop
nop
cmp $32639, %rsi
lea addresses_A_ht+0x9137, %r15
nop
nop
nop
nop
add $63088, %rax
mov $0x6162636465666768, %r9
movq %r9, (%r15)
nop
nop
sub $12185, %rsi
lea addresses_A_ht+0x18cd7, %rdi
nop
nop
nop
nop
nop
xor %rcx, %rcx
movups (%rdi), %xmm1
vpextrq $1, %xmm1, %rax
nop
nop
nop
dec %r15
lea addresses_WC_ht+0x1026d, %r9
nop
sub $47729, %r10
movups (%r9), %xmm7
vpextrq $0, %xmm7, %r15
nop
nop
nop
nop
nop
inc %rcx
lea addresses_A_ht+0x17ce7, %r13
nop
nop
nop
inc %rdi
movups (%r13), %xmm6
vpextrq $1, %xmm6, %r9
nop
nop
xor $40024, %r13
pop %rsi
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r15
pop %r13
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r15
push %r8
push %rbp
push %rbx
push %rdi
push %rdx
// Store
mov $0x4f7, %r8
nop
nop
nop
nop
xor $9259, %rbx
mov $0x5152535455565758, %rdi
movq %rdi, %xmm2
vmovups %ymm2, (%r8)
cmp $14848, %r12
// Faulty Load
lea addresses_normal+0x134f7, %rdx
nop
sub %rbp, %rbp
movaps (%rdx), %xmm2
vpextrq $0, %xmm2, %r15
lea oracles, %rbp
and $0xff, %r15
shlq $12, %r15
mov (%rbp,%r15,1), %r15
pop %rdx
pop %rdi
pop %rbx
pop %rbp
pop %r8
pop %r15
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'size': 32, 'NT': False, 'type': 'addresses_normal', 'same': True, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 32, 'NT': False, 'type': 'addresses_P', 'same': False, 'AVXalign': False, 'congruent': 11}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_normal', 'same': True, 'AVXalign': True, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_A_ht', 'congruent': 9}, 'dst': {'same': False, 'type': 'addresses_D_ht', 'congruent': 2}}
{'OP': 'LOAD', 'src': {'size': 4, 'NT': False, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': False, 'congruent': 3}}
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_A_ht', 'congruent': 11}, 'dst': {'same': False, 'type': 'addresses_normal_ht', 'congruent': 6}}
{'OP': 'LOAD', 'src': {'size': 2, 'NT': True, 'type': 'addresses_WT_ht', 'same': False, 'AVXalign': False, 'congruent': 5}}
{'OP': 'STOR', 'dst': {'size': 2, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 1, 'NT': False, 'type': 'addresses_WT_ht', 'same': False, 'AVXalign': False, 'congruent': 2}}
{'OP': 'STOR', 'dst': {'size': 8, 'NT': True, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 3}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 5}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_WC_ht', 'same': True, 'AVXalign': False, 'congruent': 1}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 4}}
{'00': 2758, '58': 4792, '5f': 14279}
00 5f 5f 00 58 5f 5f 5f 5f 5f 5f 00 5f 5f 00 58 5f 5f 5f 5f 5f 5f 58 58 00 5f 5f 58 00 5f 5f 5f 5f 5f 5f 5f 00 00 5f 5f 00 00 5f 5f 5f 5f 5f 5f 5f 5f 5f 00 58 58 5f 00 5f 5f 5f 58 5f 5f 00 5f 58 58 00 00 5f 5f 5f 58 58 5f 5f 5f 5f 5f 58 00 5f 5f 5f 00 5f 58 5f 58 5f 00 00 5f 5f 5f 5f 00 5f 5f 5f 5f 5f 00 00 58 5f 5f 5f 58 5f 58 00 5f 5f 58 00 5f 5f 00 5f 5f 5f 5f 00 5f 5f 58 58 5f 00 5f 58 5f 5f 5f 58 58 5f 58 5f 58 5f 58 58 5f 5f 58 5f 5f 5f 5f 5f 58 5f 5f 5f 58 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 58 5f 00 58 00 5f 5f 5f 5f 5f 5f 58 58 58 5f 5f 5f 5f 5f 58 5f 5f 5f 58 58 5f 5f 00 5f 5f 58 00 5f 00 5f 5f 00 5f 00 5f 5f 00 58 5f 5f 5f 00 5f 5f 5f 5f 5f 58 5f 5f 5f 00 5f 5f 5f 58 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 5f 5f 5f 00 5f 58 00 58 5f 5f 5f 5f 00 5f 5f 58 5f 5f 58 58 5f 58 5f 58 5f 00 5f 00 5f 5f 5f 58 5f 5f 58 5f 5f 5f 5f 58 00 58 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 58 58 58 5f 5f 5f 5f 5f 58 5f 5f 00 58 5f 5f 5f 5f 5f 5f 5f 00 5f 58 5f 5f 5f 5f 00 5f 5f 58 58 5f 5f 5f 5f 5f 5f 58 5f 58 5f 5f 00 5f 5f 5f 58 5f 00 5f 58 5f 58 58 5f 58 5f 5f 5f 5f 00 5f 58 58 58 00 5f 5f 5f 58 5f 5f 58 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 58 00 00 5f 5f 5f 5f 5f 00 00 5f 58 5f 5f 58 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 5f 5f 58 5f 58 00 5f 5f 58 58 5f 00 5f 00 58 58 58 58 5f 5f 5f 58 5f 5f 5f 00 58 58 5f 5f 5f 58 5f 58 5f 5f 00 5f 00 5f 58 5f 5f 5f 5f 58 5f 5f 5f 00 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 00 00 5f 5f 58 5f 00 5f 00 5f 5f 5f 5f 5f 58 5f 00 00 5f 00 5f 58 58 5f 5f 5f 5f 5f 58 58 5f 5f 5f 5f 5f 00 5f 5f 58 5f 5f 58 58 58 00 5f 5f 58 58 58 58 5f 00 5f 5f 5f 58 5f 5f 5f 58 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 58 5f 5f 5f 58 58 5f 00 00 5f 5f 00 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 00 5f 5f 5f 58 5f 58 5f 5f 58 5f 5f 5f 5f 5f 00 5f 5f 5f 5f 5f 5f 58 5f 00 58 00 5f 5f 5f 00 5f 58 00 58 5f 58 5f 5f 5f 58 5f 5f 00 5f 00 58 5f 5f 58 5f 58 5f 5f 5f 5f 5f 58 5f 5f 5f 00 58 5f 5f 5f 5f 5f 5f 5f 00 5f 00 5f 5f 5f 00 58 5f 5f 5f 5f 5f 5f 5f 00 5f 00 5f 5f 58 5f 5f 5f 58 58 00 00 58 5f 00 00 5f 5f 00 5f 5f 58 5f 00 5f 00 5f 5f 00 00 5f 58 58 5f 58 00 5f 5f 58 58 5f 5f 5f 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 5f 58 5f 00 5f 58 58 5f 5f 58 5f 5f 5f 58 5f 5f 58 00 00 5f 58 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 58 5f 00 58 00 58 00 00 00 5f 5f 5f 58 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 00 5f 00 5f 00 5f 5f 5f 58 58 58 58 5f 58 5f 58 5f 5f 5f 5f 5f 58 5f 5f 5f 5f 58 5f 5f 58 58 58 5f 58 5f 5f 58 58 5f 5f 00 58 5f 5f 58 58 00 58 5f 5f 00 00 5f 5f 58 5f 5f 5f 00 5f 5f 5f 58 5f 5f 5f 5f 5f 5f 5f 5f 00 58 5f 58 5f 58 5f 5f 58 58 5f 5f 5f 5f 00 00 5f 5f 5f 58 58 58 00 5f 00 5f 58 5f 5f 5f 00 5f 58 5f 00 5f 5f 5f 58 5f 5f 5f 5f 5f 5f 58 58 5f 5f 5f 5f 58 5f 58 5f 5f 58 58 5f 00 5f 5f 58 5f 58 58 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 00 00 5f 58 00 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 58 5f 5f 5f 5f 00 5f 5f 5f 00 5f 5f 58 5f 5f 58 5f 00 58 00 5f 5f 58 58 5f 5f 00 5f 00 5f 5f 5f 5f 5f 58 00 5f 5f 58 5f 5f 5f 5f 5f 58 00 5f 5f 5f 5f 58 5f 5f 5f 5f 5f 58 58 00 00 5f 5f 5f
*/
|
SECTION rodata_font_fzx
PUBLIC _ff_dkud4_Font10
_ff_dkud4_Font10:
BINARY "font/fzx/fonts/dkud4/Font10/font10.fzx"
|
#include "source/extensions/transport_sockets/tls/cert_validator/default_validator.h"
#include <array>
#include <deque>
#include <functional>
#include <string>
#include <vector>
#include "envoy/network/transport_socket.h"
#include "envoy/ssl/context.h"
#include "envoy/ssl/context_config.h"
#include "envoy/ssl/private_key/private_key.h"
#include "envoy/ssl/ssl_socket_extended_info.h"
#include "source/common/common/assert.h"
#include "source/common/common/base64.h"
#include "source/common/common/fmt.h"
#include "source/common/common/hex.h"
#include "source/common/common/matchers.h"
#include "source/common/common/utility.h"
#include "source/common/config/utility.h"
#include "source/common/network/address_impl.h"
#include "source/common/protobuf/utility.h"
#include "source/common/runtime/runtime_features.h"
#include "source/common/stats/symbol_table.h"
#include "source/common/stats/utility.h"
#include "source/extensions/transport_sockets/tls/cert_validator/cert_validator.h"
#include "source/extensions/transport_sockets/tls/cert_validator/factory.h"
#include "source/extensions/transport_sockets/tls/cert_validator/utility.h"
#include "source/extensions/transport_sockets/tls/stats.h"
#include "source/extensions/transport_sockets/tls/utility.h"
#include "absl/synchronization/mutex.h"
#include "openssl/ssl.h"
#include "openssl/x509v3.h"
namespace Envoy {
namespace Extensions {
namespace TransportSockets {
namespace Tls {
DefaultCertValidator::DefaultCertValidator(
const Envoy::Ssl::CertificateValidationContextConfig* config, SslStats& stats,
TimeSource& time_source)
: config_(config), stats_(stats), time_source_(time_source) {
if (config_ != nullptr) {
allow_untrusted_certificate_ = config_->trustChainVerification() ==
envoy::extensions::transport_sockets::tls::v3::
CertificateValidationContext::ACCEPT_UNTRUSTED;
}
};
int DefaultCertValidator::initializeSslContexts(std::vector<SSL_CTX*> contexts,
bool provides_certificates) {
int verify_mode = SSL_VERIFY_NONE;
int verify_mode_validation_context = SSL_VERIFY_PEER | SSL_VERIFY_FAIL_IF_NO_PEER_CERT;
if (config_ != nullptr) {
envoy::extensions::transport_sockets::tls::v3::CertificateValidationContext::
TrustChainVerification verification = config_->trustChainVerification();
if (verification == envoy::extensions::transport_sockets::tls::v3::
CertificateValidationContext::ACCEPT_UNTRUSTED) {
verify_mode = SSL_VERIFY_PEER; // Ensure client-certs will be requested even if we have
// nothing to verify against
verify_mode_validation_context = SSL_VERIFY_PEER;
}
}
if (config_ != nullptr && !config_->caCert().empty() && !provides_certificates) {
ca_file_path_ = config_->caCertPath();
bssl::UniquePtr<BIO> bio(
BIO_new_mem_buf(const_cast<char*>(config_->caCert().data()), config_->caCert().size()));
RELEASE_ASSERT(bio != nullptr, "");
// Based on BoringSSL's X509_load_cert_crl_file().
bssl::UniquePtr<STACK_OF(X509_INFO)> list(
PEM_X509_INFO_read_bio(bio.get(), nullptr, nullptr, nullptr));
if (list == nullptr) {
throw EnvoyException(
absl::StrCat("Failed to load trusted CA certificates from ", config_->caCertPath()));
}
for (auto& ctx : contexts) {
X509_STORE* store = SSL_CTX_get_cert_store(ctx);
bool has_crl = false;
for (const X509_INFO* item : list.get()) {
if (item->x509) {
X509_STORE_add_cert(store, item->x509);
if (ca_cert_ == nullptr) {
X509_up_ref(item->x509);
ca_cert_.reset(item->x509);
}
}
if (item->crl) {
X509_STORE_add_crl(store, item->crl);
has_crl = true;
}
}
if (ca_cert_ == nullptr) {
throw EnvoyException(
absl::StrCat("Failed to load trusted CA certificates from ", config_->caCertPath()));
}
if (has_crl) {
X509_STORE_set_flags(store, config_->onlyVerifyLeafCertificateCrl()
? X509_V_FLAG_CRL_CHECK
: X509_V_FLAG_CRL_CHECK | X509_V_FLAG_CRL_CHECK_ALL);
}
verify_mode = SSL_VERIFY_PEER;
verify_trusted_ca_ = true;
// NOTE: We're using SSL_CTX_set_cert_verify_callback() instead of X509_verify_cert()
// directly. However, our new callback is still calling X509_verify_cert() under
// the hood. Therefore, to ignore cert expiration, we need to set the callback
// for X509_verify_cert to ignore that error.
if (config_->allowExpiredCertificate()) {
X509_STORE_set_verify_cb(store, CertValidatorUtil::ignoreCertificateExpirationCallback);
}
}
}
if (config_ != nullptr && !config_->certificateRevocationList().empty()) {
bssl::UniquePtr<BIO> bio(
BIO_new_mem_buf(const_cast<char*>(config_->certificateRevocationList().data()),
config_->certificateRevocationList().size()));
RELEASE_ASSERT(bio != nullptr, "");
// Based on BoringSSL's X509_load_cert_crl_file().
bssl::UniquePtr<STACK_OF(X509_INFO)> list(
PEM_X509_INFO_read_bio(bio.get(), nullptr, nullptr, nullptr));
if (list == nullptr) {
throw EnvoyException(
absl::StrCat("Failed to load CRL from ", config_->certificateRevocationListPath()));
}
for (auto& ctx : contexts) {
X509_STORE* store = SSL_CTX_get_cert_store(ctx);
for (const X509_INFO* item : list.get()) {
if (item->crl) {
X509_STORE_add_crl(store, item->crl);
}
}
X509_STORE_set_flags(store, config_->onlyVerifyLeafCertificateCrl()
? X509_V_FLAG_CRL_CHECK
: X509_V_FLAG_CRL_CHECK | X509_V_FLAG_CRL_CHECK_ALL);
}
}
const Envoy::Ssl::CertificateValidationContextConfig* cert_validation_config = config_;
if (cert_validation_config != nullptr) {
if (!cert_validation_config->subjectAltNameMatchers().empty()) {
for (const envoy::extensions::transport_sockets::tls::v3::SubjectAltNameMatcher& matcher :
cert_validation_config->subjectAltNameMatchers()) {
auto san_matcher = createStringSanMatcher(matcher);
if (san_matcher == nullptr) {
throw EnvoyException(
absl::StrCat("Failed to create string SAN matcher of type ", matcher.san_type()));
}
subject_alt_name_matchers_.push_back(std::move(san_matcher));
}
verify_mode = verify_mode_validation_context;
}
if (!cert_validation_config->verifyCertificateHashList().empty()) {
for (auto hash : cert_validation_config->verifyCertificateHashList()) {
// Remove colons from the 95 chars long colon-separated "fingerprint"
// in order to get the hex-encoded string.
if (hash.size() == 95) {
hash.erase(std::remove(hash.begin(), hash.end(), ':'), hash.end());
}
const auto& decoded = Hex::decode(hash);
if (decoded.size() != SHA256_DIGEST_LENGTH) {
throw EnvoyException(absl::StrCat("Invalid hex-encoded SHA-256 ", hash));
}
verify_certificate_hash_list_.push_back(decoded);
}
verify_mode = verify_mode_validation_context;
}
if (!cert_validation_config->verifyCertificateSpkiList().empty()) {
for (const auto& hash : cert_validation_config->verifyCertificateSpkiList()) {
const auto decoded = Base64::decode(hash);
if (decoded.size() != SHA256_DIGEST_LENGTH) {
throw EnvoyException(absl::StrCat("Invalid base64-encoded SHA-256 ", hash));
}
verify_certificate_spki_list_.emplace_back(decoded.begin(), decoded.end());
}
verify_mode = verify_mode_validation_context;
}
}
return verify_mode;
}
int DefaultCertValidator::doVerifyCertChain(
X509_STORE_CTX* store_ctx, Ssl::SslExtendedSocketInfo* ssl_extended_info, X509& leaf_cert,
const Network::TransportSocketOptions* transport_socket_options) {
if (verify_trusted_ca_) {
int ret = X509_verify_cert(store_ctx);
if (ssl_extended_info) {
ssl_extended_info->setCertificateValidationStatus(
ret == 1 ? Envoy::Ssl::ClientValidationStatus::Validated
: Envoy::Ssl::ClientValidationStatus::Failed);
}
if (ret <= 0) {
stats_.fail_verify_error_.inc();
ENVOY_LOG(debug, "{}", Utility::getX509VerificationErrorInfo(store_ctx));
return allow_untrusted_certificate_ ? 1 : ret;
}
}
Envoy::Ssl::ClientValidationStatus validated =
verifyCertificate(&leaf_cert,
transport_socket_options != nullptr
? transport_socket_options->verifySubjectAltNameListOverride()
: std::vector<std::string>{},
subject_alt_name_matchers_);
if (ssl_extended_info) {
if (ssl_extended_info->certificateValidationStatus() ==
Envoy::Ssl::ClientValidationStatus::NotValidated) {
ssl_extended_info->setCertificateValidationStatus(validated);
} else if (validated != Envoy::Ssl::ClientValidationStatus::NotValidated) {
ssl_extended_info->setCertificateValidationStatus(validated);
}
}
// If `trusted_ca` exists, it is already verified in the code above. Thus, we just need to make
// sure the verification for other validation context configurations doesn't fail (i.e. either
// `NotValidated` or `Validated`). If `trusted_ca` doesn't exist, we will need to make sure
// other configurations are verified and the verification succeed.
int validation_status = verify_trusted_ca_
? validated != Envoy::Ssl::ClientValidationStatus::Failed
: validated == Envoy::Ssl::ClientValidationStatus::Validated;
return allow_untrusted_certificate_ ? 1 : validation_status;
}
Envoy::Ssl::ClientValidationStatus DefaultCertValidator::verifyCertificate(
X509* cert, const std::vector<std::string>& verify_san_list,
const std::vector<SanMatcherPtr>& subject_alt_name_matchers) {
Envoy::Ssl::ClientValidationStatus validated = Envoy::Ssl::ClientValidationStatus::NotValidated;
if (!verify_san_list.empty()) {
if (!verifySubjectAltName(cert, verify_san_list)) {
stats_.fail_verify_san_.inc();
return Envoy::Ssl::ClientValidationStatus::Failed;
}
validated = Envoy::Ssl::ClientValidationStatus::Validated;
}
if (!subject_alt_name_matchers.empty()) {
if (!matchSubjectAltName(cert, subject_alt_name_matchers)) {
stats_.fail_verify_san_.inc();
return Envoy::Ssl::ClientValidationStatus::Failed;
}
validated = Envoy::Ssl::ClientValidationStatus::Validated;
}
if (!verify_certificate_hash_list_.empty() || !verify_certificate_spki_list_.empty()) {
const bool valid_certificate_hash =
!verify_certificate_hash_list_.empty() &&
verifyCertificateHashList(cert, verify_certificate_hash_list_);
const bool valid_certificate_spki =
!verify_certificate_spki_list_.empty() &&
verifyCertificateSpkiList(cert, verify_certificate_spki_list_);
if (!valid_certificate_hash && !valid_certificate_spki) {
stats_.fail_verify_cert_hash_.inc();
return Envoy::Ssl::ClientValidationStatus::Failed;
}
validated = Envoy::Ssl::ClientValidationStatus::Validated;
}
return validated;
}
bool DefaultCertValidator::verifySubjectAltName(X509* cert,
const std::vector<std::string>& subject_alt_names) {
bssl::UniquePtr<GENERAL_NAMES> san_names(
static_cast<GENERAL_NAMES*>(X509_get_ext_d2i(cert, NID_subject_alt_name, nullptr, nullptr)));
if (san_names == nullptr) {
return false;
}
for (const GENERAL_NAME* general_name : san_names.get()) {
const std::string san = Utility::generalNameAsString(general_name);
for (auto& config_san : subject_alt_names) {
if (general_name->type == GEN_DNS ? Utility::dnsNameMatch(config_san, san.c_str())
: config_san == san) {
return true;
}
}
}
return false;
}
bool DefaultCertValidator::matchSubjectAltName(
X509* cert, const std::vector<SanMatcherPtr>& subject_alt_name_matchers) {
bssl::UniquePtr<GENERAL_NAMES> san_names(
static_cast<GENERAL_NAMES*>(X509_get_ext_d2i(cert, NID_subject_alt_name, nullptr, nullptr)));
if (san_names == nullptr) {
return false;
}
for (const auto& config_san_matcher : subject_alt_name_matchers) {
for (const GENERAL_NAME* general_name : san_names.get()) {
if (config_san_matcher->match(general_name)) {
return true;
}
}
}
return false;
}
bool DefaultCertValidator::verifyCertificateSpkiList(
X509* cert, const std::vector<std::vector<uint8_t>>& expected_hashes) {
X509_PUBKEY* pubkey = X509_get_X509_PUBKEY(cert);
if (pubkey == nullptr) {
return false;
}
uint8_t* spki = nullptr;
const int len = i2d_X509_PUBKEY(pubkey, &spki);
if (len < 0) {
return false;
}
bssl::UniquePtr<uint8_t> free_spki(spki);
std::vector<uint8_t> computed_hash(SHA256_DIGEST_LENGTH);
SHA256(spki, len, computed_hash.data());
for (const auto& expected_hash : expected_hashes) {
if (computed_hash == expected_hash) {
return true;
}
}
return false;
}
bool DefaultCertValidator::verifyCertificateHashList(
X509* cert, const std::vector<std::vector<uint8_t>>& expected_hashes) {
std::vector<uint8_t> computed_hash(SHA256_DIGEST_LENGTH);
unsigned int n;
X509_digest(cert, EVP_sha256(), computed_hash.data(), &n);
RELEASE_ASSERT(n == computed_hash.size(), "");
for (const auto& expected_hash : expected_hashes) {
if (computed_hash == expected_hash) {
return true;
}
}
return false;
}
void DefaultCertValidator::updateDigestForSessionId(bssl::ScopedEVP_MD_CTX& md,
uint8_t hash_buffer[EVP_MAX_MD_SIZE],
unsigned hash_length) {
int rc;
// Hash all the settings that affect whether the server will allow/accept
// the client connection. This ensures that the client is always validated against
// the correct settings, even if session resumption across different listeners
// is enabled.
if (ca_cert_ != nullptr) {
rc = X509_digest(ca_cert_.get(), EVP_sha256(), hash_buffer, &hash_length);
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
RELEASE_ASSERT(hash_length == SHA256_DIGEST_LENGTH,
fmt::format("invalid SHA256 hash length {}", hash_length));
rc = EVP_DigestUpdate(md.get(), hash_buffer, hash_length);
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
}
for (const auto& hash : verify_certificate_hash_list_) {
rc = EVP_DigestUpdate(md.get(), hash.data(),
hash.size() *
sizeof(std::remove_reference<decltype(hash)>::type::value_type));
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
}
for (const auto& hash : verify_certificate_spki_list_) {
rc = EVP_DigestUpdate(md.get(), hash.data(),
hash.size() *
sizeof(std::remove_reference<decltype(hash)>::type::value_type));
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
}
rc = EVP_DigestUpdate(md.get(), &verify_trusted_ca_, sizeof(verify_trusted_ca_));
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
if (config_ != nullptr) {
for (const auto& matcher : config_->subjectAltNameMatchers()) {
size_t hash = MessageUtil::hash(matcher);
rc = EVP_DigestUpdate(md.get(), &hash, sizeof(hash));
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
}
const std::string& crl = config_->certificateRevocationList();
if (!crl.empty()) {
rc = EVP_DigestUpdate(md.get(), crl.data(), crl.length());
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
}
bool allow_expired = config_->allowExpiredCertificate();
rc = EVP_DigestUpdate(md.get(), &allow_expired, sizeof(allow_expired));
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
auto trust_chain_verification = config_->trustChainVerification();
rc = EVP_DigestUpdate(md.get(), &trust_chain_verification, sizeof(trust_chain_verification));
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
auto only_leaf_crl = config_->onlyVerifyLeafCertificateCrl();
rc = EVP_DigestUpdate(md.get(), &only_leaf_crl, sizeof(only_leaf_crl));
RELEASE_ASSERT(rc == 1, Utility::getLastCryptoError().value_or(""));
}
}
void DefaultCertValidator::addClientValidationContext(SSL_CTX* ctx, bool require_client_cert) {
if (config_ == nullptr || config_->caCert().empty()) {
return;
}
bssl::UniquePtr<BIO> bio(
BIO_new_mem_buf(const_cast<char*>(config_->caCert().data()), config_->caCert().size()));
RELEASE_ASSERT(bio != nullptr, "");
// Based on BoringSSL's SSL_add_file_cert_subjects_to_stack().
bssl::UniquePtr<STACK_OF(X509_NAME)> list(sk_X509_NAME_new(
[](const X509_NAME** a, const X509_NAME** b) -> int { return X509_NAME_cmp(*a, *b); }));
RELEASE_ASSERT(list != nullptr, "");
for (;;) {
bssl::UniquePtr<X509> cert(PEM_read_bio_X509(bio.get(), nullptr, nullptr, nullptr));
if (cert == nullptr) {
break;
}
X509_NAME* name = X509_get_subject_name(cert.get());
if (name == nullptr) {
throw EnvoyException(absl::StrCat("Failed to load trusted client CA certificates from ",
config_->caCertPath()));
}
// Check for duplicates.
if (sk_X509_NAME_find(list.get(), nullptr, name)) {
continue;
}
bssl::UniquePtr<X509_NAME> name_dup(X509_NAME_dup(name));
if (name_dup == nullptr || !sk_X509_NAME_push(list.get(), name_dup.release())) {
throw EnvoyException(absl::StrCat("Failed to load trusted client CA certificates from ",
config_->caCertPath()));
}
}
// Check for EOF.
const uint32_t err = ERR_peek_last_error();
if (ERR_GET_LIB(err) == ERR_LIB_PEM && ERR_GET_REASON(err) == PEM_R_NO_START_LINE) {
ERR_clear_error();
} else {
throw EnvoyException(
absl::StrCat("Failed to load trusted client CA certificates from ", config_->caCertPath()));
}
SSL_CTX_set_client_CA_list(ctx, list.release());
if (require_client_cert) {
SSL_CTX_set_verify(ctx, SSL_VERIFY_PEER | SSL_VERIFY_FAIL_IF_NO_PEER_CERT, nullptr);
}
}
Envoy::Ssl::CertificateDetailsPtr DefaultCertValidator::getCaCertInformation() const {
if (ca_cert_ == nullptr) {
return nullptr;
}
return Utility::certificateDetails(ca_cert_.get(), getCaFileName(), time_source_);
}
size_t DefaultCertValidator::daysUntilFirstCertExpires() const {
return Utility::getDaysUntilExpiration(ca_cert_.get(), time_source_);
}
class DefaultCertValidatorFactory : public CertValidatorFactory {
public:
CertValidatorPtr createCertValidator(const Envoy::Ssl::CertificateValidationContextConfig* config,
SslStats& stats, TimeSource& time_source) override {
return std::make_unique<DefaultCertValidator>(config, stats, time_source);
}
absl::string_view name() override { return "envoy.tls.cert_validator.default"; }
};
REGISTER_FACTORY(DefaultCertValidatorFactory, CertValidatorFactory);
} // namespace Tls
} // namespace TransportSockets
} // namespace Extensions
} // namespace Envoy
|
//===--- HlslTypes.cpp - Type system for HLSL ----*- C++
///////////////////////////////////////////////////////////////////////////////
// //
// HlslTypes.cpp //
// Copyright (C) Microsoft Corporation. All rights reserved. //
// This file is distributed under the University of Illinois Open Source //
// License. See LICENSE.TXT for details. //
// //
///
/// \file //
/// \brief Defines the HLSL type system interface. //
///
// //
///////////////////////////////////////////////////////////////////////////////
#include "dxc/Support/Global.h"
#include "clang/AST/CanonicalType.h"
#include "clang/AST/DeclTemplate.h"
#include "clang/AST/HlslTypes.h"
#include "clang/AST/Type.h"
#include "clang/Sema/AttributeList.h" // conceptually ParsedAttributes
#include "clang/AST/ASTContext.h"
using namespace clang;
namespace hlsl {
/// <summary>Try to convert HLSL template vector/matrix type to
/// ExtVectorType.</summary>
const clang::ExtVectorType *
ConvertHLSLVecMatTypeToExtVectorType(const clang::ASTContext &context,
clang::QualType type) {
const Type *Ty = type.getCanonicalType().getTypePtr();
if (const RecordType *RT = dyn_cast<RecordType>(Ty)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getDecl())) {
// TODO: check pointer instead of name
if (templateDecl->getName() == "vector") {
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
const TemplateArgument &arg0 = argList[0];
const TemplateArgument &arg1 = argList[1];
QualType elemTy = arg0.getAsType();
llvm::APSInt elmSize = arg1.getAsIntegral();
return context.getExtVectorType(elemTy, elmSize.getLimitedValue())
->getAs<ExtVectorType>();
}
}
}
return nullptr;
}
bool IsHLSLVecMatType(clang::QualType type) {
const Type *Ty = type.getCanonicalType().getTypePtr();
if (const RecordType *RT = dyn_cast<RecordType>(Ty)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getDecl())) {
if (templateDecl->getName() == "vector") {
return true;
} else if (templateDecl->getName() == "matrix") {
return true;
}
}
}
return false;
}
bool IsHLSLMatType(clang::QualType type) {
const clang::Type *Ty = type.getCanonicalType().getTypePtr();
if (const RecordType *RT = dyn_cast<RecordType>(Ty)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getDecl())) {
if (templateDecl->getName() == "matrix") {
return true;
}
}
}
return false;
}
bool IsHLSLVecType(clang::QualType type) {
const clang::Type *Ty = type.getCanonicalType().getTypePtr();
if (const RecordType *RT = dyn_cast<RecordType>(Ty)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getDecl())) {
if (templateDecl->getName() == "vector") {
return true;
}
}
}
return false;
}
bool IsHLSLNumeric(clang::QualType type) {
const clang::Type *Ty = type.getCanonicalType().getTypePtr();
if (isa<RecordType>(Ty)) {
if (IsHLSLVecMatType(type))
return true;
return IsHLSLNumericUserDefinedType(type);
} else if (type->isArrayType()) {
return IsHLSLNumeric(QualType(type->getArrayElementTypeNoTypeQual(), 0));
}
return Ty->isBuiltinType();
}
bool IsHLSLNumericUserDefinedType(clang::QualType type) {
const clang::Type *Ty = type.getCanonicalType().getTypePtr();
if (const RecordType *RT = dyn_cast<RecordType>(Ty)) {
const RecordDecl *RD = RT->getDecl();
if (isa<ClassTemplateSpecializationDecl>(RD)) {
return false; // UDT are not templates
}
// TODO: avoid check by name
StringRef name = RD->getName();
if (name == "ByteAddressBuffer" ||
name == "RWByteAddressBuffer" ||
name == "RaytracingAccelerationStructure")
return false;
for (auto member : RD->fields()) {
if (!IsHLSLNumeric(member->getType()))
return false;
}
return true;
}
return false;
}
clang::QualType GetElementTypeOrType(clang::QualType type) {
if (const RecordType *RT = type->getAs<RecordType>()) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getDecl())) {
// TODO: check pointer instead of name
if (templateDecl->getName() == "vector") {
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
return argList[0].getAsType();
}
else if (templateDecl->getName() == "matrix") {
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
return argList[0].getAsType();
}
}
}
return type;
}
bool HasHLSLMatOrientation(clang::QualType type, bool *pIsRowMajor) {
const AttributedType *AT = type->getAs<AttributedType>();
while (AT) {
AttributedType::Kind kind = AT->getAttrKind();
switch (kind) {
case AttributedType::attr_hlsl_row_major:
if (pIsRowMajor) *pIsRowMajor = true;
return true;
case AttributedType::attr_hlsl_column_major:
if (pIsRowMajor) *pIsRowMajor = false;
return true;
}
AT = AT->getLocallyUnqualifiedSingleStepDesugaredType()->getAs<AttributedType>();
}
return false;
}
bool HasHLSLUNormSNorm(clang::QualType type, bool *pIsSNorm) {
// snorm/unorm can be on outer vector/matrix as well as element type
// in the template form. Outer-most type attribute wins.
// The following drills into attributed type for outer type,
// setting *pIsSNorm and returning true if snorm/unorm found.
// If not found on outer type, fall back to element type if different,
// indicating a vector or matrix, and try again.
clang::QualType elementType = GetElementTypeOrType(type);
while (true) {
const AttributedType *AT = type->getAs<AttributedType>();
while (AT) {
AttributedType::Kind kind = AT->getAttrKind();
switch (kind) {
case AttributedType::attr_hlsl_snorm:
if (pIsSNorm) *pIsSNorm = true;
return true;
case AttributedType::attr_hlsl_unorm:
if (pIsSNorm) *pIsSNorm = false;
return true;
}
AT = AT->getLocallyUnqualifiedSingleStepDesugaredType()->getAs<AttributedType>();
}
if (type == elementType)
break;
type = elementType;
}
return false;
}
/// Checks whether the pAttributes indicate a parameter is inout or out; if
/// inout, pIsIn will be set to true.
bool IsParamAttributedAsOut(_In_opt_ clang::AttributeList *pAttributes,
_Out_opt_ bool *pIsIn);
/// <summary>Gets the type with structural information (elements and shape) for
/// the given type.</summary>
/// <remarks>This function will strip lvalue/rvalue references, attributes and
/// qualifiers.</remarks>
QualType GetStructuralForm(QualType type) {
if (type.isNull()) {
return type;
}
const ReferenceType *RefType = nullptr;
const AttributedType *AttrType = nullptr;
while ((RefType = dyn_cast<ReferenceType>(type)) ||
(AttrType = dyn_cast<AttributedType>(type))) {
type = RefType ? RefType->getPointeeType() : AttrType->getEquivalentType();
}
return type->getCanonicalTypeUnqualified();
}
uint32_t GetElementCount(clang::QualType type) {
uint32_t rowCount, colCount;
GetRowsAndColsForAny(type, rowCount, colCount);
return rowCount * colCount;
}
/// <summary>Returns the number of elements in the specified array
/// type.</summary>
uint32_t GetArraySize(clang::QualType type) {
assert(type->isArrayType() && "otherwise caller shouldn't be invoking this");
if (type->isConstantArrayType()) {
const ConstantArrayType *arrayType =
(const ConstantArrayType *)type->getAsArrayTypeUnsafe();
return arrayType->getSize().getLimitedValue();
} else {
return 0;
}
}
/// <summary>Returns the number of elements in the specified vector
/// type.</summary>
uint32_t GetHLSLVecSize(clang::QualType type) {
type = GetStructuralForm(type);
const Type *Ty = type.getCanonicalType().getTypePtr();
const RecordType *RT = dyn_cast<RecordType>(Ty);
assert(RT != nullptr && "otherwise caller shouldn't be invoking this");
const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
assert(templateDecl != nullptr &&
"otherwise caller shouldn't be invoking this");
assert(templateDecl->getName() == "vector" &&
"otherwise caller shouldn't be invoking this");
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
const TemplateArgument &arg1 = argList[1];
llvm::APSInt vecSize = arg1.getAsIntegral();
return vecSize.getLimitedValue();
}
void GetRowsAndCols(clang::QualType type, uint32_t &rowCount,
uint32_t &colCount) {
type = GetStructuralForm(type);
const Type *Ty = type.getCanonicalType().getTypePtr();
const RecordType *RT = dyn_cast<RecordType>(Ty);
assert(RT != nullptr && "otherwise caller shouldn't be invoking this");
const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
assert(templateDecl != nullptr &&
"otherwise caller shouldn't be invoking this");
assert(templateDecl->getName() == "matrix" &&
"otherwise caller shouldn't be invoking this");
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
const TemplateArgument &arg1 = argList[1];
const TemplateArgument &arg2 = argList[2];
llvm::APSInt rowSize = arg1.getAsIntegral();
llvm::APSInt colSize = arg2.getAsIntegral();
rowCount = rowSize.getLimitedValue();
colCount = colSize.getLimitedValue();
}
bool IsArrayConstantStringType(const QualType type) {
DXASSERT_NOMSG(type->isArrayType());
return type->getArrayElementTypeNoTypeQual()->isSpecificBuiltinType(BuiltinType::Char_S);
}
bool IsPointerStringType(const QualType type) {
DXASSERT_NOMSG(type->isPointerType());
return type->getPointeeType()->isSpecificBuiltinType(BuiltinType::Char_S);
}
bool IsStringType(const QualType type) {
QualType canType = type.getCanonicalType();
return canType->isPointerType() && IsPointerStringType(canType);
}
bool IsStringLiteralType(const QualType type) {
QualType canType = type.getCanonicalType();
return canType->isArrayType() && IsArrayConstantStringType(canType);
}
void GetRowsAndColsForAny(QualType type, uint32_t &rowCount,
uint32_t &colCount) {
assert(!type.isNull());
type = GetStructuralForm(type);
rowCount = 1;
colCount = 1;
const Type *Ty = type.getCanonicalType().getTypePtr();
if (type->isArrayType() && !IsArrayConstantStringType(type)) {
if (type->isConstantArrayType()) {
const ConstantArrayType *arrayType =
(const ConstantArrayType *)type->getAsArrayTypeUnsafe();
colCount = arrayType->getSize().getLimitedValue();
} else {
colCount = 0;
}
} else if (const RecordType *RT = dyn_cast<RecordType>(Ty)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(
RT->getAsCXXRecordDecl())) {
if (templateDecl->getName() == "matrix") {
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
const TemplateArgument &arg1 = argList[1];
const TemplateArgument &arg2 = argList[2];
llvm::APSInt rowSize = arg1.getAsIntegral();
llvm::APSInt colSize = arg2.getAsIntegral();
rowCount = rowSize.getLimitedValue();
colCount = colSize.getLimitedValue();
} else if (templateDecl->getName() == "vector") {
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
const TemplateArgument &arg1 = argList[1];
llvm::APSInt rowSize = arg1.getAsIntegral();
colCount = rowSize.getLimitedValue();
}
}
}
}
void GetHLSLMatRowColCount(clang::QualType type, unsigned int &row,
unsigned int &col) {
GetRowsAndColsForAny(type, row, col);
}
clang::QualType GetHLSLVecElementType(clang::QualType type) {
type = GetStructuralForm(type);
const Type *Ty = type.getCanonicalType().getTypePtr();
const RecordType *RT = dyn_cast<RecordType>(Ty);
assert(RT != nullptr && "otherwise caller shouldn't be invoking this");
const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
assert(templateDecl != nullptr &&
"otherwise caller shouldn't be invoking this");
assert(templateDecl->getName() == "vector" &&
"otherwise caller shouldn't be invoking this");
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
const TemplateArgument &arg0 = argList[0];
QualType elemTy = arg0.getAsType();
return elemTy;
}
clang::QualType GetHLSLMatElementType(clang::QualType type) {
type = GetStructuralForm(type);
const Type *Ty = type.getCanonicalType().getTypePtr();
const RecordType *RT = dyn_cast<RecordType>(Ty);
assert(RT != nullptr && "otherwise caller shouldn't be invoking this");
const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
assert(templateDecl != nullptr &&
"otherwise caller shouldn't be invoking this");
assert(templateDecl->getName() == "matrix" &&
"otherwise caller shouldn't be invoking this");
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
const TemplateArgument &arg0 = argList[0];
QualType elemTy = arg0.getAsType();
return elemTy;
}
// TODO: Add type cache to ASTContext.
bool IsHLSLInputPatchType(QualType type) {
type = type.getCanonicalType();
if (const RecordType *RT = dyn_cast<RecordType>(type)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(
RT->getAsCXXRecordDecl())) {
if (templateDecl->getName() == "InputPatch") {
return true;
}
}
}
return false;
}
bool IsHLSLOutputPatchType(QualType type) {
type = type.getCanonicalType();
if (const RecordType *RT = dyn_cast<RecordType>(type)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(
RT->getAsCXXRecordDecl())) {
if (templateDecl->getName() == "OutputPatch") {
return true;
}
}
}
return false;
}
bool IsHLSLPointStreamType(QualType type) {
type = type.getCanonicalType();
if (const RecordType *RT = dyn_cast<RecordType>(type)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(
RT->getAsCXXRecordDecl())) {
if (templateDecl->getName() == "PointStream")
return true;
}
}
return false;
}
bool IsHLSLLineStreamType(QualType type) {
type = type.getCanonicalType();
if (const RecordType *RT = dyn_cast<RecordType>(type)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(
RT->getAsCXXRecordDecl())) {
if (templateDecl->getName() == "LineStream")
return true;
}
}
return false;
}
bool IsHLSLTriangleStreamType(QualType type) {
type = type.getCanonicalType();
if (const RecordType *RT = dyn_cast<RecordType>(type)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(
RT->getAsCXXRecordDecl())) {
if (templateDecl->getName() == "TriangleStream")
return true;
}
}
return false;
}
bool IsHLSLStreamOutputType(QualType type) {
type = type.getCanonicalType();
if (const RecordType *RT = dyn_cast<RecordType>(type)) {
if (const ClassTemplateSpecializationDecl *templateDecl =
dyn_cast<ClassTemplateSpecializationDecl>(
RT->getAsCXXRecordDecl())) {
if (templateDecl->getName() == "PointStream")
return true;
if (templateDecl->getName() == "LineStream")
return true;
if (templateDecl->getName() == "TriangleStream")
return true;
}
}
return false;
}
bool IsHLSLResourceType(clang::QualType type) {
if (const RecordType *RT = type->getAs<RecordType>()) {
StringRef name = RT->getDecl()->getName();
if (name == "Texture1D" || name == "RWTexture1D")
return true;
if (name == "Texture2D" || name == "RWTexture2D")
return true;
if (name == "Texture2DMS" || name == "RWTexture2DMS")
return true;
if (name == "Texture3D" || name == "RWTexture3D")
return true;
if (name == "TextureCube" || name == "RWTextureCube")
return true;
if (name == "Texture1DArray" || name == "RWTexture1DArray")
return true;
if (name == "Texture2DArray" || name == "RWTexture2DArray")
return true;
if (name == "Texture2DMSArray" || name == "RWTexture2DMSArray")
return true;
if (name == "TextureCubeArray" || name == "RWTextureCubeArray")
return true;
if (name == "ByteAddressBuffer" || name == "RWByteAddressBuffer")
return true;
if (name == "StructuredBuffer" || name == "RWStructuredBuffer")
return true;
if (name == "AppendStructuredBuffer" || name == "ConsumeStructuredBuffer")
return true;
if (name == "Buffer" || name == "RWBuffer")
return true;
if (name == "SamplerState" || name == "SamplerComparisonState")
return true;
if (name == "ConstantBuffer")
return true;
if (name == "RaytracingAccelerationStructure")
return true;
}
return false;
}
QualType GetHLSLResourceResultType(QualType type) {
type = type.getCanonicalType();
const RecordType *RT = cast<RecordType>(type);
StringRef name = RT->getDecl()->getName();
if (name == "ByteAddressBuffer" || name == "RWByteAddressBuffer") {
RecordDecl *RD = RT->getDecl();
QualType resultTy = RD->field_begin()->getType();
return resultTy;
}
const ClassTemplateSpecializationDecl *templateDecl =
cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
return argList[0].getAsType();
}
bool IsIncompleteHLSLResourceArrayType(clang::ASTContext &context,
clang::QualType type) {
if (type->isIncompleteArrayType()) {
const IncompleteArrayType *IAT = context.getAsIncompleteArrayType(type);
QualType EltTy = IAT->getElementType();
if (IsHLSLResourceType(EltTy))
return true;
}
return false;
}
QualType GetHLSLInputPatchElementType(QualType type) {
type = type.getCanonicalType();
const RecordType *RT = cast<RecordType>(type);
const ClassTemplateSpecializationDecl *templateDecl =
cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
return argList[0].getAsType();
}
unsigned GetHLSLInputPatchCount(QualType type) {
type = type.getCanonicalType();
const RecordType *RT = cast<RecordType>(type);
const ClassTemplateSpecializationDecl *templateDecl =
cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
return argList[1].getAsIntegral().getLimitedValue();
}
clang::QualType GetHLSLOutputPatchElementType(QualType type) {
type = type.getCanonicalType();
const RecordType *RT = cast<RecordType>(type);
const ClassTemplateSpecializationDecl *templateDecl =
cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
return argList[0].getAsType();
}
unsigned GetHLSLOutputPatchCount(QualType type) {
type = type.getCanonicalType();
const RecordType *RT = cast<RecordType>(type);
const ClassTemplateSpecializationDecl *templateDecl =
cast<ClassTemplateSpecializationDecl>(RT->getAsCXXRecordDecl());
const TemplateArgumentList &argList = templateDecl->getTemplateArgs();
return argList[1].getAsIntegral().getLimitedValue();
}
_Use_decl_annotations_
bool IsParamAttributedAsOut(clang::AttributeList *pAttributes, bool *pIsIn) {
bool anyFound = false;
bool inFound = false;
bool outFound = false;
while (pAttributes != nullptr) {
switch (pAttributes->getKind()) {
case AttributeList::AT_HLSLIn:
anyFound = true;
inFound = true;
break;
case AttributeList::AT_HLSLOut:
anyFound = true;
outFound = true;
break;
case AttributeList::AT_HLSLInOut:
anyFound = true;
outFound = true;
inFound = true;
break;
default:
// Ignore the majority of attributes that don't have in/out characteristics
break;
}
pAttributes = pAttributes->getNext();
}
if (pIsIn)
*pIsIn = inFound || anyFound == false;
return outFound;
}
_Use_decl_annotations_
hlsl::ParameterModifier ParamModFromAttributeList(clang::AttributeList *pAttributes) {
bool isIn, isOut;
isOut = IsParamAttributedAsOut(pAttributes, &isIn);
return ParameterModifier::FromInOut(isIn, isOut);
}
hlsl::ParameterModifier ParamModFromAttrs(llvm::ArrayRef<InheritableAttr *> attributes) {
bool isIn = false, isOut = false;
for (InheritableAttr * attr : attributes) {
if (isa<HLSLInAttr>(attr))
isIn = true;
else if (isa<HLSLOutAttr>(attr))
isOut = true;
else if (isa<HLSLInOutAttr>(attr))
isIn = isOut = true;
}
// Without any specifications, default to in.
if (!isIn && !isOut) {
isIn = true;
}
return ParameterModifier::FromInOut(isIn, isOut);
}
HLSLScalarType MakeUnsigned(HLSLScalarType T) {
switch (T) {
case HLSLScalarType_int:
return HLSLScalarType_uint;
case HLSLScalarType_int_min16:
return HLSLScalarType_uint_min16;
case HLSLScalarType_int64:
return HLSLScalarType_uint64;
case HLSLScalarType_int16:
return HLSLScalarType_uint16;
default:
// Only signed int types are relevant.
break;
}
return T;
}
}
|
// Copyright (c) 2009-2014 The Bitcoin developers
// Copyright (c) 2014-2015 The Dash developers
// Copyright (c) 2015-2017 The Brewhaust developers
// Distributed under the MIT software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
#include "bip38.h"
#include "init.h"
#include "main.h"
#include "rpcserver.h"
#include "script/script.h"
#include "script/standard.h"
#include "sync.h"
#include "util.h"
#include "utilstrencodings.h"
#include "utiltime.h"
#include "wallet.h"
#include <fstream>
#include <secp256k1.h>
#include <stdint.h>
#include <boost/algorithm/string.hpp>
#include <boost/date_time/posix_time/posix_time.hpp>
#include <openssl/aes.h>
#include <openssl/sha.h>
#include <univalue.h>
using namespace std;
void EnsureWalletIsUnlocked();
std::string static EncodeDumpTime(int64_t nTime)
{
return DateTimeStrFormat("%Y-%m-%dT%H:%M:%SZ", nTime);
}
int64_t static DecodeDumpTime(const std::string& str)
{
static const boost::posix_time::ptime epoch = boost::posix_time::from_time_t(0);
static const std::locale loc(std::locale::classic(),
new boost::posix_time::time_input_facet("%Y-%m-%dT%H:%M:%SZ"));
std::istringstream iss(str);
iss.imbue(loc);
boost::posix_time::ptime ptime(boost::date_time::not_a_date_time);
iss >> ptime;
if (ptime.is_not_a_date_time())
return 0;
return (ptime - epoch).total_seconds();
}
std::string static EncodeDumpString(const std::string& str)
{
std::stringstream ret;
BOOST_FOREACH (unsigned char c, str) {
if (c <= 32 || c >= 128 || c == '%') {
ret << '%' << HexStr(&c, &c + 1);
} else {
ret << c;
}
}
return ret.str();
}
std::string DecodeDumpString(const std::string& str)
{
std::stringstream ret;
for (unsigned int pos = 0; pos < str.length(); pos++) {
unsigned char c = str[pos];
if (c == '%' && pos + 2 < str.length()) {
c = (((str[pos + 1] >> 6) * 9 + ((str[pos + 1] - '0') & 15)) << 4) |
((str[pos + 2] >> 6) * 9 + ((str[pos + 2] - '0') & 15));
pos += 2;
}
ret << c;
}
return ret.str();
}
UniValue importprivkey(const UniValue& params, bool fHelp)
{
if (fHelp || params.size() < 1 || params.size() > 3)
throw runtime_error(
"importprivkey \"brewhaustprivkey\" ( \"label\" rescan )\n"
"\nAdds a private key (as returned by dumpprivkey) to your wallet.\n"
"\nArguments:\n"
"1. \"brewhaustprivkey\" (string, required) The private key (see dumpprivkey)\n"
"2. \"label\" (string, optional, default=\"\") An optional label\n"
"3. rescan (boolean, optional, default=true) Rescan the wallet for transactions\n"
"\nNote: This call can take minutes to complete if rescan is true.\n"
"\nExamples:\n"
"\nDump a private key\n" +
HelpExampleCli("dumpprivkey", "\"myaddress\"") +
"\nImport the private key with rescan\n" + HelpExampleCli("importprivkey", "\"mykey\"") +
"\nImport using a label and without rescan\n" + HelpExampleCli("importprivkey", "\"mykey\" \"testing\" false") +
"\nAs a JSON-RPC call\n" + HelpExampleRpc("importprivkey", "\"mykey\", \"testing\", false"));
LOCK2(cs_main, pwalletMain->cs_wallet);
EnsureWalletIsUnlocked();
string strSecret = params[0].get_str();
string strLabel = "";
if (params.size() > 1)
strLabel = params[1].get_str();
// Whether to perform rescan after import
bool fRescan = true;
if (params.size() > 2)
fRescan = params[2].get_bool();
CBitcoinSecret vchSecret;
bool fGood = vchSecret.SetString(strSecret);
if (!fGood) throw JSONRPCError(RPC_INVALID_ADDRESS_OR_KEY, "Invalid private key encoding");
CKey key = vchSecret.GetKey();
if (!key.IsValid()) throw JSONRPCError(RPC_INVALID_ADDRESS_OR_KEY, "Private key outside allowed range");
CPubKey pubkey = key.GetPubKey();
assert(key.VerifyPubKey(pubkey));
CKeyID vchAddress = pubkey.GetID();
{
pwalletMain->MarkDirty();
pwalletMain->SetAddressBook(vchAddress, strLabel, "receive");
// Don't throw error in case a key is already there
if (pwalletMain->HaveKey(vchAddress))
return NullUniValue;
pwalletMain->mapKeyMetadata[vchAddress].nCreateTime = 1;
if (!pwalletMain->AddKeyPubKey(key, pubkey))
throw JSONRPCError(RPC_WALLET_ERROR, "Error adding key to wallet");
// whenever a key is imported, we need to scan the whole chain
pwalletMain->nTimeFirstKey = 1; // 0 would be considered 'no value'
if (fRescan) {
pwalletMain->ScanForWalletTransactions(chainActive.Genesis(), true);
}
}
return NullUniValue;
}
UniValue importaddress(const UniValue& params, bool fHelp)
{
if (fHelp || params.size() < 1 || params.size() > 3)
throw runtime_error(
"importaddress \"address\" ( \"label\" rescan )\n"
"\nAdds an address or script (in hex) that can be watched as if it were in your wallet but cannot be used to spend.\n"
"\nArguments:\n"
"1. \"address\" (string, required) The address\n"
"2. \"label\" (string, optional, default=\"\") An optional label\n"
"3. rescan (boolean, optional, default=true) Rescan the wallet for transactions\n"
"\nNote: This call can take minutes to complete if rescan is true.\n"
"\nExamples:\n"
"\nImport an address with rescan\n" +
HelpExampleCli("importaddress", "\"myaddress\"") +
"\nImport using a label without rescan\n" + HelpExampleCli("importaddress", "\"myaddress\" \"testing\" false") +
"\nAs a JSON-RPC call\n" + HelpExampleRpc("importaddress", "\"myaddress\", \"testing\", false"));
LOCK2(cs_main, pwalletMain->cs_wallet);
CScript script;
CBitcoinAddress address(params[0].get_str());
if (address.IsValid()) {
script = GetScriptForDestination(address.Get());
} else if (IsHex(params[0].get_str())) {
std::vector<unsigned char> data(ParseHex(params[0].get_str()));
script = CScript(data.begin(), data.end());
} else {
throw JSONRPCError(RPC_INVALID_ADDRESS_OR_KEY, "Invalid Brewhaust address or script");
}
string strLabel = "";
if (params.size() > 1)
strLabel = params[1].get_str();
// Whether to perform rescan after import
bool fRescan = true;
if (params.size() > 2)
fRescan = params[2].get_bool();
{
if (::IsMine(*pwalletMain, script) == ISMINE_SPENDABLE)
throw JSONRPCError(RPC_WALLET_ERROR, "The wallet already contains the private key for this address or script");
// add to address book or update label
if (address.IsValid())
pwalletMain->SetAddressBook(address.Get(), strLabel, "receive");
// Don't throw error in case an address is already there
if (pwalletMain->HaveWatchOnly(script))
return NullUniValue;
pwalletMain->MarkDirty();
if (!pwalletMain->AddWatchOnly(script))
throw JSONRPCError(RPC_WALLET_ERROR, "Error adding address to wallet");
if (fRescan) {
pwalletMain->ScanForWalletTransactions(chainActive.Genesis(), true);
pwalletMain->ReacceptWalletTransactions();
}
}
return NullUniValue;
}
UniValue importwallet(const UniValue& params, bool fHelp)
{
if (fHelp || params.size() != 1)
throw runtime_error(
"importwallet \"filename\"\n"
"\nImports keys from a wallet dump file (see dumpwallet).\n"
"\nArguments:\n"
"1. \"filename\" (string, required) The wallet file\n"
"\nExamples:\n"
"\nDump the wallet\n" +
HelpExampleCli("dumpwallet", "\"test\"") +
"\nImport the wallet\n" + HelpExampleCli("importwallet", "\"test\"") +
"\nImport using the json rpc call\n" + HelpExampleRpc("importwallet", "\"test\""));
LOCK2(cs_main, pwalletMain->cs_wallet);
EnsureWalletIsUnlocked();
ifstream file;
file.open(params[0].get_str().c_str(), std::ios::in | std::ios::ate);
if (!file.is_open())
throw JSONRPCError(RPC_INVALID_PARAMETER, "Cannot open wallet dump file");
int64_t nTimeBegin = chainActive.Tip()->GetBlockTime();
bool fGood = true;
int64_t nFilesize = std::max((int64_t)1, (int64_t)file.tellg());
file.seekg(0, file.beg);
pwalletMain->ShowProgress(_("Importing..."), 0); // show progress dialog in GUI
while (file.good()) {
pwalletMain->ShowProgress("", std::max(1, std::min(99, (int)(((double)file.tellg() / (double)nFilesize) * 100))));
std::string line;
std::getline(file, line);
if (line.empty() || line[0] == '#')
continue;
std::vector<std::string> vstr;
boost::split(vstr, line, boost::is_any_of(" "));
if (vstr.size() < 2)
continue;
CBitcoinSecret vchSecret;
if (!vchSecret.SetString(vstr[0]))
continue;
CKey key = vchSecret.GetKey();
CPubKey pubkey = key.GetPubKey();
assert(key.VerifyPubKey(pubkey));
CKeyID keyid = pubkey.GetID();
if (pwalletMain->HaveKey(keyid)) {
LogPrintf("Skipping import of %s (key already present)\n", CBitcoinAddress(keyid).ToString());
continue;
}
int64_t nTime = DecodeDumpTime(vstr[1]);
std::string strLabel;
bool fLabel = true;
for (unsigned int nStr = 2; nStr < vstr.size(); nStr++) {
if (boost::algorithm::starts_with(vstr[nStr], "#"))
break;
if (vstr[nStr] == "change=1")
fLabel = false;
if (vstr[nStr] == "reserve=1")
fLabel = false;
if (boost::algorithm::starts_with(vstr[nStr], "label=")) {
strLabel = DecodeDumpString(vstr[nStr].substr(6));
fLabel = true;
}
}
LogPrintf("Importing %s...\n", CBitcoinAddress(keyid).ToString());
if (!pwalletMain->AddKeyPubKey(key, pubkey)) {
fGood = false;
continue;
}
pwalletMain->mapKeyMetadata[keyid].nCreateTime = nTime;
if (fLabel)
pwalletMain->SetAddressBook(keyid, strLabel, "receive");
nTimeBegin = std::min(nTimeBegin, nTime);
}
file.close();
pwalletMain->ShowProgress("", 100); // hide progress dialog in GUI
CBlockIndex* pindex = chainActive.Tip();
while (pindex && pindex->pprev && pindex->GetBlockTime() > nTimeBegin - 7200)
pindex = pindex->pprev;
if (!pwalletMain->nTimeFirstKey || nTimeBegin < pwalletMain->nTimeFirstKey)
pwalletMain->nTimeFirstKey = nTimeBegin;
LogPrintf("Rescanning last %i blocks\n", chainActive.Height() - pindex->nHeight + 1);
pwalletMain->ScanForWalletTransactions(pindex);
pwalletMain->MarkDirty();
if (!fGood)
throw JSONRPCError(RPC_WALLET_ERROR, "Error adding some keys to wallet");
return NullUniValue;
}
UniValue dumpprivkey(const UniValue& params, bool fHelp)
{
if (fHelp || params.size() != 1)
throw runtime_error(
"dumpprivkey \"brewhaustaddress\"\n"
"\nReveals the private key corresponding to 'brewhaustaddress'.\n"
"Then the importprivkey can be used with this output\n"
"\nArguments:\n"
"1. \"brewhaustaddress\" (string, required) The brewhaust address for the private key\n"
"\nResult:\n"
"\"key\" (string) The private key\n"
"\nExamples:\n" +
HelpExampleCli("dumpprivkey", "\"myaddress\"") + HelpExampleCli("importprivkey", "\"mykey\"") + HelpExampleRpc("dumpprivkey", "\"myaddress\""));
LOCK2(cs_main, pwalletMain->cs_wallet);
EnsureWalletIsUnlocked();
string strAddress = params[0].get_str();
CBitcoinAddress address;
if (!address.SetString(strAddress))
throw JSONRPCError(RPC_INVALID_ADDRESS_OR_KEY, "Invalid Brewhaust address");
CKeyID keyID;
if (!address.GetKeyID(keyID))
throw JSONRPCError(RPC_TYPE_ERROR, "Address does not refer to a key");
CKey vchSecret;
if (!pwalletMain->GetKey(keyID, vchSecret))
throw JSONRPCError(RPC_WALLET_ERROR, "Private key for address " + strAddress + " is not known");
return CBitcoinSecret(vchSecret).ToString();
}
UniValue dumpwallet(const UniValue& params, bool fHelp)
{
if (fHelp || params.size() != 1)
throw runtime_error(
"dumpwallet \"filename\"\n"
"\nDumps all wallet keys in a human-readable format.\n"
"\nArguments:\n"
"1. \"filename\" (string, required) The filename\n"
"\nExamples:\n" +
HelpExampleCli("dumpwallet", "\"test\"") + HelpExampleRpc("dumpwallet", "\"test\""));
LOCK2(cs_main, pwalletMain->cs_wallet);
EnsureWalletIsUnlocked();
ofstream file;
file.open(params[0].get_str().c_str());
if (!file.is_open())
throw JSONRPCError(RPC_INVALID_PARAMETER, "Cannot open wallet dump file");
std::map<CKeyID, int64_t> mapKeyBirth;
std::set<CKeyID> setKeyPool;
pwalletMain->GetKeyBirthTimes(mapKeyBirth);
pwalletMain->GetAllReserveKeys(setKeyPool);
// sort time/key pairs
std::vector<std::pair<int64_t, CKeyID> > vKeyBirth;
for (std::map<CKeyID, int64_t>::const_iterator it = mapKeyBirth.begin(); it != mapKeyBirth.end(); it++) {
vKeyBirth.push_back(std::make_pair(it->second, it->first));
}
mapKeyBirth.clear();
std::sort(vKeyBirth.begin(), vKeyBirth.end());
// produce output
file << strprintf("# Wallet dump created by Brewhaust %s (%s)\n", CLIENT_BUILD, CLIENT_DATE);
file << strprintf("# * Created on %s\n", EncodeDumpTime(GetTime()));
file << strprintf("# * Best block at time of backup was %i (%s),\n", chainActive.Height(), chainActive.Tip()->GetBlockHash().ToString());
file << strprintf("# mined on %s\n", EncodeDumpTime(chainActive.Tip()->GetBlockTime()));
file << "\n";
for (std::vector<std::pair<int64_t, CKeyID> >::const_iterator it = vKeyBirth.begin(); it != vKeyBirth.end(); it++) {
const CKeyID& keyid = it->second;
std::string strTime = EncodeDumpTime(it->first);
std::string strAddr = CBitcoinAddress(keyid).ToString();
CKey key;
if (pwalletMain->GetKey(keyid, key)) {
if (pwalletMain->mapAddressBook.count(keyid)) {
file << strprintf("%s %s label=%s # addr=%s\n", CBitcoinSecret(key).ToString(), strTime, EncodeDumpString(pwalletMain->mapAddressBook[keyid].name), strAddr);
} else if (setKeyPool.count(keyid)) {
file << strprintf("%s %s reserve=1 # addr=%s\n", CBitcoinSecret(key).ToString(), strTime, strAddr);
} else {
file << strprintf("%s %s change=1 # addr=%s\n", CBitcoinSecret(key).ToString(), strTime, strAddr);
}
}
}
file << "\n";
file << "# End of dump\n";
file.close();
return NullUniValue;
}
UniValue bip38encrypt(const UniValue& params, bool fHelp)
{
if (fHelp || params.size() != 2)
throw runtime_error(
"bip38encrypt \"brewhaustaddress\"\n"
"\nEncrypts a private key corresponding to 'brewhaustaddress'.\n"
"\nArguments:\n"
"1. \"brewhaustaddress\" (string, required) The brewhaust address for the private key (you must hold the key already)\n"
"2. \"passphrase\" (string, required) The passphrase you want the private key to be encrypted with - Valid special chars: !#$%&'()*+,-./:;<=>?`{|}~ \n"
"\nResult:\n"
"\"key\" (string) The encrypted private key\n"
"\nExamples:\n");
LOCK2(cs_main, pwalletMain->cs_wallet);
EnsureWalletIsUnlocked();
string strAddress = params[0].get_str();
string strPassphrase = params[1].get_str();
CBitcoinAddress address;
if (!address.SetString(strAddress))
throw JSONRPCError(RPC_INVALID_ADDRESS_OR_KEY, "Invalid Brewhaust address");
CKeyID keyID;
if (!address.GetKeyID(keyID))
throw JSONRPCError(RPC_TYPE_ERROR, "Address does not refer to a key");
CKey vchSecret;
if (!pwalletMain->GetKey(keyID, vchSecret))
throw JSONRPCError(RPC_WALLET_ERROR, "Private key for address " + strAddress + " is not known");
uint256 privKey = vchSecret.GetPrivKey_256();
string encryptedOut = BIP38_Encrypt(strAddress, strPassphrase, privKey, vchSecret.IsCompressed());
UniValue result(UniValue::VOBJ);
result.push_back(Pair("Addess", strAddress));
result.push_back(Pair("Encrypted Key", encryptedOut));
return result;
}
UniValue bip38decrypt(const UniValue& params, bool fHelp)
{
if (fHelp || params.size() != 2)
throw runtime_error(
"bip38decrypt \"brewhaustaddress\"\n"
"\nDecrypts and then imports password protected private key.\n"
"\nArguments:\n"
"1. \"encryptedkey\" (string, required) The encrypted private key\n"
"2. \"passphrase\" (string, required) The passphrase you want the private key to be encrypted with\n"
"\nResult:\n"
"\"key\" (string) The decrypted private key\n"
"\nExamples:\n");
LOCK2(cs_main, pwalletMain->cs_wallet);
EnsureWalletIsUnlocked();
/** Collect private key and passphrase **/
string strKey = params[0].get_str();
string strPassphrase = params[1].get_str();
uint256 privKey;
bool fCompressed;
if (!BIP38_Decrypt(strPassphrase, strKey, privKey, fCompressed))
throw JSONRPCError(RPC_WALLET_ERROR, "Failed To Decrypt");
UniValue result(UniValue::VOBJ);
result.push_back(Pair("privatekey", HexStr(privKey)));
CKey key;
key.Set(privKey.begin(), privKey.end(), fCompressed);
if (!key.IsValid())
throw JSONRPCError(RPC_WALLET_ERROR, "Private Key Not Valid");
CPubKey pubkey = key.GetPubKey();
pubkey.IsCompressed();
assert(key.VerifyPubKey(pubkey));
result.push_back(Pair("Address", CBitcoinAddress(pubkey.GetID()).ToString()));
CKeyID vchAddress = pubkey.GetID();
{
pwalletMain->MarkDirty();
pwalletMain->SetAddressBook(vchAddress, "", "receive");
// Don't throw error in case a key is already there
if (pwalletMain->HaveKey(vchAddress))
throw JSONRPCError(RPC_WALLET_ERROR, "Key already held by wallet");
pwalletMain->mapKeyMetadata[vchAddress].nCreateTime = 1;
if (!pwalletMain->AddKeyPubKey(key, pubkey))
throw JSONRPCError(RPC_WALLET_ERROR, "Error adding key to wallet");
// whenever a key is imported, we need to scan the whole chain
pwalletMain->nTimeFirstKey = 1; // 0 would be considered 'no value'
pwalletMain->ScanForWalletTransactions(chainActive.Genesis(), true);
}
return result;
}
|
; Roughly taken from:
; https://github.com/Sakura-IT/Amiga-programming-examples/blob/master/ASM/HelloWorld/helloworld.s
; See also:
; http://amigadev.elowar.com/read/ADCD_2.1/Includes_and_Autodocs_2._guide/node0367.html
; open library
lea dosname, a1
moveq #36, d0 ; version 36 = Kick 2.0
moveal (4).W, a6
jsr (-552, a6) ; -552 = OpenLibrary
lea txt, a6 ; load string name
movel a6, d1 ; d1 = string to print
moveal d0, a6 ; Move dosbase to a6
jsr (-948, a6) ; -948 = PutStr
; close library
moveal a6, a1 ; Library to close
moveal (4).W, a6
jsr (-414, a6) ; -414 = CloseLibrary
; clr.l d0
moveq #0, d0
rts
dosname:
; TODO: ds "dos.library", 0
db 0x64
db 0x6f
db 0x73
db 0x2e
db 0x6c
db 0x69
db 0x62
db 0x72
db 0x61
db 0x72
db 0x79
db 0
txt:
; "Hoi!", 0
db 0x48
db 0x6f
db 0x69
db 0x21
db 0
|
#include <bits/stdc++.h>
#define uset unordered_set
#define umap unordered_map
using namespace std;
int n;
char g[20][20];
int ans = 0;
uset<string> as;
umap<string, int> b;
string s;
int dfs(int x, int y, int dep)
{
if (dep >= n && s[dep] != s[n * 2 - 2 - dep])
{
return 0;
}
if (dep == n - 1 && b.find(s) != b.end())
{
return b[s];
}
int tmp = 0;
if (x + 1 < n)
{
s.push_back(g[x + 1][y]);
tmp += dfs(x + 1, y, dep + 1);
s.pop_back();
}
if (y + 1 < n)
{
s.push_back(g[x][y + 1]);
tmp += dfs(x, y + 1, dep + 1);
s.pop_back();
}
if (dep == n - 1)
{
b[s] = tmp;
}
if (dep >= n * 2 - 2)
{
if (as.find(s) == as.end())
{
ans++;
as.insert(s);
}
return 1;
}
}
int main()
{
cin >> n;
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
{
cin >> g[i][j];
}
}
s.push_back(g[0][0]);
dfs(0, 0, 0);
cout << ans << endl;
return 0;
} |
; A027468: 9 times the triangular numbers A000217.
; 0,9,27,54,90,135,189,252,324,405,495,594,702,819,945,1080,1224,1377,1539,1710,1890,2079,2277,2484,2700,2925,3159,3402,3654,3915,4185,4464,4752,5049,5355,5670,5994,6327,6669,7020,7380,7749,8127,8514,8910,9315,9729,10152,10584,11025,11475,11934,12402,12879,13365,13860,14364,14877,15399,15930,16470,17019,17577,18144,18720,19305,19899,20502,21114,21735,22365,23004,23652,24309,24975,25650,26334,27027,27729,28440,29160,29889,30627,31374,32130,32895,33669,34452,35244,36045,36855,37674,38502,39339
sub $1,$0
bin $1,2
mul $1,9
mov $0,$1
|
/* Copyright 2021 The TensorFlow Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
==============================================================================*/
// This file implements logic for some optimizations to reduce size on export.
#include <memory>
#include "mlir/IR/BuiltinAttributes.h" // from @llvm-project
#include "mlir/IR/BuiltinOps.h" // from @llvm-project
#include "mlir/IR/BuiltinTypes.h" // from @llvm-project
#include "mlir/IR/ImplicitLocOpBuilder.h" // from @llvm-project
#include "mlir/IR/Matchers.h" // from @llvm-project
#include "mlir/IR/Operation.h" // from @llvm-project
#include "mlir/IR/Types.h" // from @llvm-project
#include "mlir/Pass/Pass.h" // from @llvm-project
#include "tensorflow/compiler/mlir/hlo/include/mlir-hlo/Dialect/mhlo/IR/hlo_ops.h"
#include "tensorflow/compiler/mlir/xla/transforms/xla_passes_detail.h"
#define DEBUG_TYPE "xla-prepare-for-export"
namespace mlir {
namespace mhlo {
namespace {
// Prepare module for export to XLA HLO.
struct PrepareForExportPass : PrepareForExportPassBase<PrepareForExportPass> {
void runOnFunction() override;
};
static PassRegistration<PrepareForExportPass> registration(
"xla-prepare-for-export", "Prepare for XLA export");
} // end namespace
void PrepareForExportPass::runOnFunction() {
getFunction().walk([&](Operation *op) {
mlir::SplatElementsAttr attr;
if (!matchPattern(op, m_Constant(&attr))) return;
// Only consider int or floats for now.
if (!attr.getType().getElementType().isIntOrFloat()) return;
// Arbitrarialy chosen "small" number. This could be chosen based on the
// proto size too.
if (attr.getNumElements() < 32) return;
ShapedType return_type = op->getResultTypes().front().cast<ShapedType>();
ImplicitLocOpBuilder b(op->getLoc(), op);
auto cst = b.create<::mlir::mhlo::ConstOp>(attr.getSplatValue());
auto broadcast = b.create<::mlir::mhlo::BroadcastInDimOp>(
return_type, cst, b.getI64TensorAttr({}));
op->replaceAllUsesWith(broadcast);
op->erase();
});
}
std::unique_ptr<OperationPass<FuncOp>> CreatePrepareForExport() {
return std::make_unique<PrepareForExportPass>();
}
} // end namespace mhlo
} // end namespace mlir
|
// This file is part of BOINC.
// http://boinc.berkeley.edu
// Copyright (C) 2019 University of California
//
// BOINC is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License
// as published by the Free Software Foundation,
// either version 3 of the License, or (at your option) any later version.
//
// BOINC is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with BOINC. If not, see <http://www.gnu.org/licenses/>.
// burn up to one CPU second
#include "config.h"
#include <cstdio>
#include <ctime>
int main() {
int now = time(0), i;
double x=0;
while (1) {
for (i=0; i<1000000; i++) x += 1;
if (time(0) != now) break;
}
FILE* f = fopen("out", "w");
fprintf(f, "done\n");
fclose(f);
}
|
.size 8000
.text@48
jp lstatint
.text@100
jp lbegin
.data@143
c0
.text@150
lbegin:
ld a, 00
ldff(ff), a
ld a, 30
ldff(00), a
ld a, 01
ldff(4d), a
stop, 00
ld a, ff
ldff(45), a
ld b, 03
call lwaitly_b
ld c, 41
lbegin_waitm0:
ldff a, (c)
and a, b
jrnz lbegin_waitm0
ld a, 80
ldff(68), a
ld a, ff
ld c, 69
ldff(c), a
ldff(c), a
ldff(c), a
ldff(c), a
ldff(c), a
ldff(c), a
xor a, a
ldff(c), a
ldff(c), a
ld a, 40
ldff(41), a
ld a, 02
ldff(ff), a
ei
ld a, b
inc a
inc a
ldff(45), a
ld c, 0f
.text@1000
lstatint:
nop
.text@10d8
inc a
ldff(45), a
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
ldff a, (c)
and a, b
jp lprint_a
.text@7000
lprint_a:
push af
ld b, 91
call lwaitly_b
xor a, a
ldff(40), a
pop af
ld(9800), a
ld bc, 7a00
ld hl, 8000
ld d, a0
lprint_copytiles:
ld a, (bc)
inc bc
ld(hl++), a
dec d
jrnz lprint_copytiles
ld a, c0
ldff(47), a
ld a, 80
ldff(68), a
ld a, ff
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
xor a, a
ldff(69), a
ldff(69), a
ldff(43), a
ld a, 91
ldff(40), a
lprint_limbo:
jr lprint_limbo
.text@7400
lwaitly_b:
ld c, 44
lwaitly_b_loop:
ldff a, (c)
cmp a, b
jrnz lwaitly_b_loop
ret
.data@7a00
00 00 7f 7f 41 41 41 41
41 41 41 41 41 41 7f 7f
00 00 08 08 08 08 08 08
08 08 08 08 08 08 08 08
00 00 7f 7f 01 01 01 01
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 01 01 01 01
3f 3f 01 01 01 01 7f 7f
00 00 41 41 41 41 41 41
7f 7f 01 01 01 01 01 01
00 00 7f 7f 40 40 40 40
7e 7e 01 01 01 01 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 41 41 41 41 7f 7f
00 00 7f 7f 01 01 02 02
04 04 08 08 10 10 10 10
00 00 3e 3e 41 41 41 41
3e 3e 41 41 41 41 3e 3e
00 00 7f 7f 41 41 41 41
7f 7f 01 01 01 01 7f 7f
|
CGAClub9 label byte
word C_BLACK
Bitmap <67,41,BMC_PACKBITS,BMF_MONO>
db 0xf8, 0x00
db 0xf8, 0x00
db 0x08, 0x0f, 0xe0, 0x07, 0x00, 0x00, 0x1c, 0x00,
0x08, 0x00
db 0x08, 0x18, 0x30, 0x1f, 0xc0, 0x00, 0x7f, 0x00,
0x1c, 0x00
db 0x08, 0x18, 0x30, 0x1f, 0xc0, 0x00, 0x7f, 0x00,
0x2a, 0x00
db 0x08, 0x0f, 0xf0, 0x77, 0x70, 0x01, 0xdd, 0xc0,
0x7f, 0x00
db 0x08, 0x00, 0x31, 0xff, 0xfc, 0x07, 0xff, 0xf0,
0x2a, 0x00
db 0x08, 0x18, 0x31, 0xff, 0xfc, 0x07, 0xff, 0xf0,
0x08, 0x00
db 0x08, 0x0f, 0xe0, 0x77, 0x70, 0x01, 0xdd, 0xc0,
0x1c, 0x00
db 0x05, 0x00, 0x00, 0x0f, 0x80, 0x00, 0x3e, 0xfe,
0x00
db 0xf8, 0x00
db 0x05, 0x00, 0x00, 0x07, 0x00, 0x00, 0x1c, 0xfe,
0x00
db 0x05, 0x00, 0x00, 0x1f, 0xc0, 0x00, 0x7f, 0xfe,
0x00
db 0x05, 0x00, 0x00, 0x1f, 0xc0, 0x00, 0x7f, 0xfe,
0x00
db 0x08, 0x00, 0x00, 0x77, 0x70, 0x01, 0xdd, 0xc0,
0x00, 0x00
db 0x08, 0x00, 0x01, 0xff, 0xfc, 0x07, 0xff, 0xf0,
0x00, 0x00
db 0x08, 0x00, 0x01, 0xff, 0xfc, 0xe7, 0xff, 0xf0,
0x00, 0x00
db 0x08, 0x00, 0x00, 0x77, 0x73, 0xf9, 0xdd, 0xc0,
0x00, 0x00
db 0x05, 0x00, 0x00, 0x0f, 0x83, 0xf8, 0x3e, 0xfe,
0x00
db 0xfe, 0x00, 0x01, 0x0e, 0xee, 0xfd, 0x00
db 0xfe, 0x00, 0x02, 0x3f, 0xff, 0x80, 0xfe, 0x00
db 0xfe, 0x00, 0x02, 0x3f, 0xff, 0x80, 0xfe, 0x00
db 0x05, 0x00, 0x00, 0x0f, 0x8e, 0xee, 0x3e, 0xfe,
0x00
db 0x08, 0x00, 0x00, 0x77, 0x71, 0xf1, 0xdd, 0xc0,
0x00, 0x00
db 0x08, 0x00, 0x01, 0xff, 0xfc, 0x07, 0xff, 0xf0,
0x00, 0x00
db 0x08, 0x00, 0x01, 0xff, 0xfc, 0x07, 0xff, 0xf0,
0x00, 0x00
db 0x08, 0x00, 0x00, 0x77, 0x70, 0x01, 0xdd, 0xc0,
0x00, 0x00
db 0x05, 0x00, 0x00, 0x1f, 0xc0, 0x00, 0x7f, 0xfe,
0x00
db 0x05, 0x00, 0x00, 0x1f, 0xc0, 0x00, 0x7f, 0xfe,
0x00
db 0x05, 0x00, 0x00, 0x07, 0x00, 0x00, 0x1c, 0xfe,
0x00
db 0xf8, 0x00
db 0x05, 0x00, 0x00, 0x0f, 0x80, 0x00, 0x3e, 0xfe,
0x00
db 0x08, 0x07, 0x00, 0x77, 0x70, 0x01, 0xdd, 0xc0,
0xfe, 0x00
db 0x08, 0x02, 0x01, 0xff, 0xfc, 0x07, 0xff, 0xf1,
0x83, 0x00
db 0x08, 0x0a, 0x81, 0xff, 0xfc, 0x07, 0xff, 0xf1,
0x80, 0x00
db 0x08, 0x1f, 0xc0, 0x77, 0x70, 0x01, 0xdd, 0xc1,
0xfe, 0x00
db 0x08, 0x0a, 0x80, 0x1f, 0xc0, 0x00, 0x7f, 0x01,
0x83, 0x00
db 0x08, 0x07, 0x00, 0x1f, 0xc0, 0x00, 0x7f, 0x01,
0x83, 0x00
db 0x08, 0x02, 0x00, 0x07, 0x00, 0x00, 0x1c, 0x00,
0xfe, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
|
; A114960: Expansion of (-1+3*x-5*x^2+4*x^3) / ((1-2*x)*(2*x^2-1)*(x-1)^2).
; 1,1,6,11,30,57,128,247,518,1013,2068,4083,8242,16369,32880,65519,131310,262125,524780,1048555,2098154,4194281,8390632,16777191,33558502,67108837,134225892,268435427,536887266,1073741793,2147516384,4294967263,8590000094,17179869149,34359869404,68719476699,137439215578,274877906905,549756338136,1099511627735,2199024304086,4398046511061,8796095119316,17592186044371,35184376283090,70368744177617,140737496743888,281474976710607,562949970198478,1125899906842573,2251799847239628,4503599627370443,9007199321849802
mov $9,$0
mov $11,$0
add $11,1
lpb $11,1
mov $0,$9
sub $11,1
sub $0,$11
mov $5,$0
mov $7,2
lpb $7,1
clr $0,5
mov $0,$5
sub $7,1
add $0,$7
sub $0,1
add $3,2
add $3,$0
mov $4,$3
cal $4,52957 ; Expansion of 2*(1-x-x^2)/((1-2*x)*(1-2*x^2)).
mov $1,$4
sub $1,4
div $1,2
mul $1,4
add $1,4
mov $8,$7
lpb $8,1
mov $6,$1
sub $8,1
lpe
lpe
lpb $5,1
mov $5,0
sub $6,$1
lpe
mov $1,$6
div $1,4
sub $1,1
add $10,$1
lpe
mov $1,$10
|
Snd_SpecialS_Header:
smpsHeaderStartSong 3
smpsHeaderVoice Snd_SpecialS_Voices
smpsHeaderChan $06, $03
smpsHeaderTempo $01, $25
smpsHeaderDAC Snd_SpecialS_DAC
smpsHeaderFM Snd_SpecialS_FM1, $00, $17
smpsHeaderFM Snd_SpecialS_FM2, $00, $0F
smpsHeaderFM Snd_SpecialS_FM3, $00, $17
smpsHeaderFM Snd_SpecialS_FM4, $00, $17
smpsHeaderFM Snd_SpecialS_FM5, $00, $1F
smpsHeaderPSG Snd_SpecialS_PSG1, $0C, $05, $00, sTone_0C
smpsHeaderPSG Snd_SpecialS_PSG2, $0C, $05, $00, sTone_0C
smpsHeaderPSG Snd_SpecialS_PSG3, $00, $04, $00, sTone_02
; FM1 Data
Snd_SpecialS_FM1:
smpsSetvoice $01
dc.b nE5, $06, nRst, $0C, nE4, $06, nB3, nRst, nE4, nRst, nFs4, nRst
dc.b nAb4, nRst, nB4, nRst, nD5, nRst, nE5, nE5, nRst, nE5, nE5, nRst
dc.b nE5, nE5, nRst, nD5, nRst, nD5, nD5, $0C, nE5, nRst, $60
Snd_SpecialS_Jump03:
smpsSetvoice $03
smpsModSet $14, $01, $06, $06
smpsCall Snd_SpecialS_Call00
smpsCall Snd_SpecialS_Call01
smpsCall Snd_SpecialS_Call02
dc.b nE6
smpsFMAlterVol $06
smpsSetvoice $04
dc.b nA6, $66, nA5, $06, nA6, nA5, nA6, $0C
smpsCall Snd_SpecialS_Call03
dc.b nEb4
smpsFMAlterVol $FA
smpsJump Snd_SpecialS_Jump03
Snd_SpecialS_Call00:
dc.b nA5, $0C, nE5, $06, nA5, nRst, nB5, nRst, nC6, $02, smpsNoAttack, nCs6
dc.b smpsNoAttack, nD6, $08, nCs6, $06, nB5, nRst, nA5, $0C, nB5, nA5, $0C
dc.b nE5, $06, nA5, nRst, nB5, nRst, nC6, $02, smpsNoAttack, nCs6, smpsNoAttack, nD6
dc.b $08, nCs6, $06, nB5, nRst, nA5, $18
smpsLoop $00, $02, Snd_SpecialS_Call00
dc.b nFs5, $12, nAb5, nA5, $0C, nBb5, $03, smpsNoAttack, nB5, $09, nA5, $06
dc.b nAb5, nRst, nFs5, $12, nE5, $12, nB5, nA5, $24, nE5, $18, nFs5
dc.b $12, nAb5, nA5, $0C, nAb5, $12, nA5, nB5, $0C, nCs6, $18, nB5
dc.b nCs6, nE6
smpsReturn
Snd_SpecialS_Call01:
dc.b nFs6, $12, nFs6, nE6, $0C, nFs6, $12, nFs6, nE6, $06, nFs6, nA6
dc.b $12, nAb6, nE6, $0C, nCs6, $24, nD6, $06, nE6, nFs6, $12, nFs6
dc.b nE6, $0C, nFs6, $12, nFs6, nE6, $06, nFs6, nA6, $12, nAb6, nCs7
dc.b $3C, nFs6, $12, nFs6, nE6, $0C, nFs6, $12, nFs6, nE6, $06, nFs6
dc.b nA6, $12, nAb6, nE6, $0C, nCs6, $24, nD6, $06, nE6, nFs6, $12
dc.b nFs6, nE6, $0C, nFs6, $12, nFs6, nE6, $06, nFs6, nA6, $12, nAb6
dc.b nCs7, $24, nAb6, $18, nFs6, $24, $06, nAb6, nA6, $12, nAb6, nE6
dc.b $0C, nA6, $60
smpsReturn
Snd_SpecialS_Call02:
dc.b nFs6, $24, $06, $06, $12, nE6, nD6, $0C, nE6, $60, nD6, $24
dc.b $06, $06, $12, nCs6, nB5, $0C, nCs6, $48, nB5, $18, nA5, $24
dc.b $06, $06, $12, nB5, nCs6, $0C
Snd_SpecialS_Loop22:
dc.b nA5, $30, $12, nB5, nCs6, $0C
smpsLoop $00, $02, Snd_SpecialS_Loop22
dc.b nCs6, $18, nB5, nCs6
smpsReturn
Snd_SpecialS_Call03:
dc.b nG6, $06, nE6, nD6, $0C, nD6, $02, nE6, $04, nD6, $0C, nE6
dc.b nD6, nD5, $06, nB4, nA4, nG4, nE4, nD4, nE4, nG4, nE4, nG4
dc.b nA4, nB4, nA4, nB4, nD5, nD5, $03, nE5, $09, nD5, $0C, nB4
dc.b $06, nA4, nB4, nD5, nE5, nD5, nE5, nFs5, nG5, nA5, nB5, nCs6
dc.b nD6, nCs6, nB5, nG6, nFs6, nE6, nFs6, nE6, nD6, nFs6, nE6, nD6
dc.b nCs6, $04, nD6, nCs6, nB5, $06, nA5, nFs5, nE5, nD5, nCs5, $04
dc.b nD5, $06, nCs5, $08, nB4, $06, nA4, nG4, $0C, nA4, $06, nG4
dc.b $0C, nFs4, nE4, nFs4, $06, nD4, nE4, nFs4, nG4, nA4, nB4, nG4
dc.b nA4, nCs5, nD5, nE5, nFs5, nG5, nFs5, nG5, $03, nA5, $09, nG5
dc.b $06, nE5, $0C, nD5, $06, nRst, nE5, nRst, nD5, nA4, nG4, smpsNoAttack
dc.b $0C, nFs4, $03, nF4, nE4
smpsReturn
; FM2 Data
Snd_SpecialS_FM2:
smpsSetvoice $00
dc.b nRst, $12, nA2, $06, nE2, nRst, nA2, nRst, nB2, nRst, nCs3, nRst
dc.b nE2, nRst, nFs2, nRst, nA2, nA2, nE3, nA3, nA3, nRst, nA3, nA3
dc.b nRst, nG3, nRst, nG3, nG2, nD3, nG3, $0C, nRst, $60
Snd_SpecialS_Loop0D:
dc.b nA2, $12, nE3, nA2, $0C, nG2, $12, nD3, nG2, $0C
smpsLoop $00, $04, Snd_SpecialS_Loop0D
Snd_SpecialS_Loop0E:
dc.b nFs2, $12, nCs3, nFs2, $0C, nB2, $12, nFs2, nB2, $0C, nE2, $12
dc.b nB2, nE2, $0C, nA2, $12, nE3, nA2, $0C
smpsLoop $00, $02, Snd_SpecialS_Loop0E
Snd_SpecialS_Loop0F:
dc.b nD2, $12, nA2, nD3, $0C, nD2, $12, nA2, nD2, $0C, nA2, $12
dc.b nA2, $06, nRst, $0C, nE2, nA2, $18, nE2
smpsLoop $00, $04, Snd_SpecialS_Loop0F
dc.b nD2, $12, nA2, nD2, $0C, nE2, $12, nAb2, nB2, $0C, nA2, $06
dc.b nA2, nE3, nA3, nA3, nRst, nA3, nA3, nRst, nG3, nRst, nG3, nG2
dc.b nD3, nG3, $0C
Snd_SpecialS_Loop10:
dc.b nD2, $12, nA2, $06, nRst, $0C, nD3, $3C, nA2, $12, nA2, $06
dc.b nRst, $0C, nA2, $3C
smpsLoop $00, $02, Snd_SpecialS_Loop10
dc.b nFs2, $12, nA2, $06, nRst, $0C, nCs3, $3C, nF2, $12, nA2, $06
dc.b nRst, $0C, nCs3, $3C, nE2, $12, nA2, $06, nRst, $0C, nCs3, $3C
dc.b nA2, $18, nAb2, nFs2, nE2
Snd_SpecialS_Loop11:
dc.b nA2, $12, nE3, nA2, $0C, nG2, $12, nD3, nG2, $0C
smpsLoop $00, $07, Snd_SpecialS_Loop11
dc.b nA2, $12, nE3, nA2, $0C, nG2, $06, $0C, nG3, $12, nA3, $0C
smpsJump Snd_SpecialS_Loop0D
; FM3 Data
Snd_SpecialS_FM3:
smpsSetvoice $01
smpsPan panRight, $00
dc.b nA4, $06, nRst, $0C, nA3, $06, nE3, nRst, nA3, nRst, nB3, nRst
dc.b nCs4, nRst, nE4, nRst, nG4, nRst, nA4, nA4, nRst, nA4, nA4, nRst
dc.b nA4, nA4, nRst, nG4, nRst, nG4, nG4, $0C, nA4, nRst, $60
Snd_SpecialS_Jump02:
smpsSetvoice $02
Snd_SpecialS_Loop09:
dc.b nCs4, $0C, nA3, $06, nE3, nRst, nA3, nRst, nB3, $0C, nG3, $06
dc.b nG3, nG3, $0C, nD3, $06, nB3, nB3
smpsLoop $00, $04, Snd_SpecialS_Loop09
Snd_SpecialS_Loop0A:
dc.b nA3, $0C, nFs3, $06, nA3, nRst, nFs3, nRst, nB3, $0C, nD3, $06
dc.b nD3, nFs3, $0C, nD3, $06, nFs3, nB3, nE3, $0C, nB2, $06, nB2
dc.b nRst, nE3, nRst, nA3, $0C, nE3, $06, nE3, nA3, $0C, nA2, $06
dc.b nE3, nCs3
smpsLoop $00, $02, Snd_SpecialS_Loop0A
Snd_SpecialS_Loop0B:
dc.b nA3, $12, $06, nRst, $18
smpsLoop $00, $02, Snd_SpecialS_Loop0B
dc.b nCs4, $12, $06, nRst, $0C, nA3, $3C
smpsLoop $01, $04, Snd_SpecialS_Loop0B
dc.b nA3, $30, nB3, $12, nB3, nB3, $0C
smpsSetvoice $01
dc.b nA4, $06, nA4, nRst, nA4, nA4, nRst, nA4, nA4, nRst, nG4, nRst
dc.b nG4, nG4, $0C, nA4
smpsSetvoice $02
dc.b nA3, $60, nA3, nA3, nA3, nFs3, nF3, nE3, nA3, $18, nAb3, nFs3
dc.b nE3
Snd_SpecialS_Loop0C:
dc.b nCs4, $0C, nA3, $06, nE3, nRst, nA3, nRst, nB3, $0C, nG3, $06
dc.b nG3, nG3, $0C, nD3, $06, nB3, nB3
smpsLoop $00, $07, Snd_SpecialS_Loop0C
smpsSetvoice $01
smpsFMAlterVol $08
dc.b nE4, $12
smpsFMAlterVol $FC
dc.b nA4
smpsFMAlterVol $FC
dc.b nA4
smpsFMAlterVol $FB
dc.b nG4, $0C, $12, nA4, $0C
smpsFMAlterVol $05
smpsJump Snd_SpecialS_Jump02
; FM4 Data
Snd_SpecialS_FM4:
smpsSetvoice $01
smpsPan panLeft, $00
dc.b nA5, $06, nRst, $0C, nA4, $06, nE4, nRst, nA4, nRst, nB4, nRst
dc.b nCs5, nRst, nE5, nRst, nG5, nRst, nA5, nA5, nRst, nA5, nA5, nRst
dc.b nA5, nA5, nRst, nG5, nRst, nG5, nG5, $0C, nA5, nRst, $60
Snd_SpecialS_Jump01:
smpsSetvoice $02
Snd_SpecialS_Loop05:
dc.b nE4, $0C, nA4, $06, nCs4, nRst, nE4, nRst, nD4, $12, nB3, $06
dc.b nD4, $0C, nG3, $06, nG4, nD4
smpsLoop $00, $04, Snd_SpecialS_Loop05
Snd_SpecialS_Loop06:
dc.b nCs4, $0C, nFs4, $06, nCs4, nRst, nCs4, nRst, nD4, $0C, nFs3, $06
dc.b nB3, nD4, $0C, nFs3, $06, nB3, nD4, nB3, $0C, nE3, $06, nAb3
dc.b nRst, nB3, nRst, nCs4, $0C, nA3, $06, nB3, nCs4, $0C, nE3, $06
dc.b nA3, nCs4
smpsLoop $00, $02, Snd_SpecialS_Loop06
Snd_SpecialS_Loop07:
dc.b nFs4, $12, nFs4, $06, nRst, $18
smpsLoop $00, $02, Snd_SpecialS_Loop07
dc.b nA4, $12, nA4, $06, nRst, $0C, nE4, $3C
smpsLoop $01, $04, Snd_SpecialS_Loop07
dc.b nFs4, $30, nAb4, $12, nAb4, nAb4, $0C
smpsSetvoice $01
dc.b nA5, $06, nA5, nRst, nA5, nA5, nRst, nA5, nA5, nRst, nG5, nRst
dc.b nG5, nG5, $0C, nA5
smpsSetvoice $02
dc.b nFs4, $60, nE4, nD4, nCs4, nCs4, nCs4, nCs4, nCs4, $18, nB3, nA3
dc.b nAb3
Snd_SpecialS_Loop08:
dc.b nE4, $0C, nA4, $06, nCs4, nRst, nE4, nRst, nD4, $12, nB3, $06
dc.b nD4, $0C, nG3, $06, nG4, nD4
smpsLoop $00, $07, Snd_SpecialS_Loop08
smpsSetvoice $01
smpsFMAlterVol $08
dc.b nA4, $12
smpsFMAlterVol $FC
dc.b nCs5
smpsFMAlterVol $FC
dc.b nE5
smpsFMAlterVol $FB
dc.b nG5, $0C, $12, nA5, $0C
smpsFMAlterVol $05
smpsJump Snd_SpecialS_Jump01
; FM5 Data
Snd_SpecialS_FM5:
smpsSetvoice $02
dc.b nA5, $06, nRst, $0C, nA4, $06, nE4, nRst, nA4, nRst, nB4, nRst
dc.b nCs5, nRst, nE5, nRst, nG5, nRst, nA5, nA5, nRst, nA5, nA5, nRst
dc.b nA5, nA5, nRst, nG5, nRst, nG5, nG5, $0C, nA5, nRst, $60
smpsAlterNote $F8
Snd_SpecialS_Jump00:
smpsSetvoice $03
smpsModSet $14, $01, $06, $06
dc.b nRst, $12
smpsCall Snd_SpecialS_Call00
smpsCall Snd_SpecialS_Call01
smpsCall Snd_SpecialS_Call02
dc.b nE6, $06
smpsSetvoice $04
smpsFMAlterVol $FB
dc.b nE6, $66, nRst, $06, nE6, nRst, nE6, $0C
smpsFMAlterVol $0A
dc.b nRst, $03
smpsCall Snd_SpecialS_Call03
smpsFMAlterVol $FB
smpsJump Snd_SpecialS_Jump00
; PSG1 Data
Snd_SpecialS_PSG1:
dc.b nRst, $12, nA2, $06, nE2, nRst, nA2, nRst, nB2, nRst, nCs3, nRst
dc.b nE3, nRst, nG3, nRst, nA3, nA3, nRst, nA3, nA3, nRst, nA3, nA3
dc.b nRst, nG3, nRst, nG3, nG3, $0C, nA3, nRst, $60
Snd_SpecialS_Loop1E:
dc.b nE2, $0C, nA2, $06, nCs2, nRst, nE2, nRst, nD2, $12, nB1, $06
dc.b nD2, $0C, nG1, $06, nG2, nD2
smpsLoop $00, $04, Snd_SpecialS_Loop1E
Snd_SpecialS_Loop1F:
dc.b nCs2, $0C, nFs2, $06, nCs2, nRst, nCs2, nRst, nD2, $0C, nFs1, $06
dc.b nB1, nD2, $0C, nFs1, $06, nB1, nD2, nB1, $0C, nE1, $06, nAb1
dc.b nRst, nB1, nRst, nCs2, $0C, nA1, $06, nB1, nCs2, $0C, nE1, $06
dc.b nA1, nCs2
smpsLoop $00, $02, Snd_SpecialS_Loop1F
smpsPSGvoice sTone_09
Snd_SpecialS_Loop20:
dc.b nFs2, $60, nE2, nFs2, nA2
smpsLoop $00, $02, Snd_SpecialS_Loop20
dc.b nFs2, $30, nAb2, $12, nAb2, nAb2, $0C
smpsPSGvoice sTone_0C
dc.b nA3, $06, nA3, nRst, nA3, nA3, nRst, nA3, nA3, nRst, nG3, nRst
dc.b nG3, nG3, $0C, nA3
smpsPSGvoice sTone_09
smpsCall Snd_SpecialS_Call04
dc.b nG1, nAb1, nA1, nBb1, nB1, nC2
smpsPSGAlterVol $02
smpsPSGvoice sTone_0C
Snd_SpecialS_Loop21:
dc.b nE2, $0C, nA2, $06, nCs2, nRst, nE2, nRst, nD2, $12, nB1, $06
dc.b nD2, $0C, nG1, $06, nG2, nD2
smpsLoop $00, $07, Snd_SpecialS_Loop21
dc.b nE2, $0C, nA2, $06, nCs2, nRst, nE2, nRst, nD2, $0C, nG2, $0C
dc.b $12, nA2, $0C
smpsJump Snd_SpecialS_Loop1E
; PSG2 Data
Snd_SpecialS_PSG2:
dc.b nRst, $12, nA1, $06, nE1, nRst, nA1, nRst, nB1, nRst, nCs2, nRst
dc.b nE2, nRst, nG2, nRst, nE2, nE2, nRst, nE2, nE2, nRst, nE2, nE2
dc.b nRst, nD2, nRst, nD2, nD2, $0C, nE2, nRst, $60
Snd_SpecialS_Loop1A:
dc.b nCs2, $0C, nA1, $06, nE1, nRst, nA1, nRst, nB1, $0C, nG1, $06
dc.b nG1, nG1, $0C, nD1, $06, nB1, nB1
smpsLoop $00, $04, Snd_SpecialS_Loop1A
Snd_SpecialS_Loop1B:
dc.b nA1, $0C, nFs1, $06, nA1, nRst, nFs1, nRst, nB1, $0C, nD1, $06
dc.b nD1, nFs1, $0C, nD1, $06, nFs1, nB1, nE1, $0C, nB0, $06, nB0
dc.b nRst, nE1, nRst, nA1, $0C, nE1, $06, nE1, nA1, $0C, nA0, $06
dc.b nE1, nCs1
smpsLoop $00, $02, Snd_SpecialS_Loop1B
smpsPSGvoice sTone_09
Snd_SpecialS_Loop1C:
dc.b nD2, $60, nCs2, nD2, nE2
smpsLoop $00, $02, Snd_SpecialS_Loop1C
dc.b nD2, $30, nE2, $12, nE2, nE2, $0C
smpsPSGvoice sTone_0C
dc.b nE2, $06, nE2, nRst, nE2, nE2, nRst, nE2, nE2, nRst, nD2, nRst
dc.b nD2, nD2, $0C, nE2
smpsPSGvoice sTone_09
smpsAlterNote $FE
smpsPSGAlterVol $02
dc.b nRst, $12
smpsCall Snd_SpecialS_Call04
smpsPSGvoice sTone_0C
Snd_SpecialS_Loop1D:
dc.b nCs2, $0C, nA1, $06, nE1, nRst, nA1, nRst, nB1, $0C, nG1, $06
dc.b nG1, nG1, $0C, nD1, $06, nB1, nB1
smpsLoop $00, $07, Snd_SpecialS_Loop1D
dc.b nCs2, $0C, nA1, $06, nE1, nRst, nA1, nRst, nB1, $0C, nD2, $0C
dc.b $12, nCs2, $0C
smpsJump Snd_SpecialS_Loop1A
Snd_SpecialS_Call04:
dc.b nD2, $24, $06, $06, $12, nCs2, nB1, $0C, nCs2, $60, nA1, $24
dc.b $06, $06, $12, $12, nE1, $0C, nA1, $48, nAb1, $18, nFs1, $24
dc.b $06, $06, $12, nAb1, nA1, $0C, nF1, $30, $12, nAb1, nA1, $0C
dc.b nE1, $30, $12, nAb1, nA1, $0C, nA1, $18, nAb1
smpsPSGAlterVol $FE
dc.b nA0, $03, nBb0, nB0, nC1, nCs1, nD1, nEb1, nE1, nF1, nFs1
smpsReturn
; PSG3 Data
Snd_SpecialS_PSG3:
smpsPSGform $E7
smpsPSGvoice sTone_02
dc.b nMaxPSG2, $06, nMaxPSG2
smpsPSGvoice sTone_01
dc.b nMaxPSG2, $0C
Snd_SpecialS_Loop12:
smpsPSGvoice sTone_02
dc.b nMaxPSG2, $06
smpsPSGvoice sTone_01
dc.b nMaxPSG2
smpsPSGvoice sTone_02
dc.b nMaxPSG2
smpsPSGvoice sTone_01
dc.b nMaxPSG2
smpsLoop $00, $03, Snd_SpecialS_Loop12
Snd_SpecialS_Loop13:
smpsPSGvoice sTone_02
dc.b nMaxPSG2, nMaxPSG2
smpsPSGAlterVol $FC
dc.b nMaxPSG2
smpsPSGAlterVol $04
dc.b nMaxPSG2
smpsLoop $00, $07, Snd_SpecialS_Loop13
dc.b nMaxPSG2, nMaxPSG2, nMaxPSG2
smpsPSGvoice sTone_01
dc.b nMaxPSG2
Snd_SpecialS_Loop14:
smpsPSGvoice sTone_02
dc.b nMaxPSG2, nMaxPSG2
smpsPSGAlterVol $FC
dc.b nMaxPSG2
smpsPSGAlterVol $04
dc.b nMaxPSG2
smpsLoop $00, $03, Snd_SpecialS_Loop14
dc.b nMaxPSG2, nMaxPSG2, nMaxPSG2
smpsPSGvoice sTone_01
dc.b nMaxPSG2
smpsLoop $01, $04, Snd_SpecialS_Loop14
Snd_SpecialS_Loop15:
smpsPSGvoice sTone_02
dc.b nMaxPSG2, nMaxPSG2
smpsPSGAlterVol $FC
dc.b nMaxPSG2
smpsPSGAlterVol $04
dc.b nMaxPSG2
smpsLoop $00, $0F, Snd_SpecialS_Loop15
dc.b nMaxPSG2, nMaxPSG2, nMaxPSG2
smpsPSGvoice sTone_01
dc.b nMaxPSG2
Snd_SpecialS_Loop16:
smpsPSGvoice sTone_02
dc.b nMaxPSG2, $06, nMaxPSG2
smpsPSGvoice sTone_01
dc.b nMaxPSG2, $0C
smpsPSGvoice sTone_02
dc.b nMaxPSG2, $06, nMaxPSG2
smpsPSGAlterVol $FC
dc.b nMaxPSG2
smpsPSGAlterVol $04
dc.b nMaxPSG2
smpsLoop $00, $10, Snd_SpecialS_Loop16
Snd_SpecialS_Loop17:
dc.b nMaxPSG2, $06, nMaxPSG2
smpsPSGAlterVol $FC
dc.b nMaxPSG2
smpsPSGAlterVol $04
dc.b nMaxPSG2
smpsLoop $00, $03, Snd_SpecialS_Loop17
dc.b nMaxPSG2, $06, nMaxPSG2, nMaxPSG2
smpsPSGvoice sTone_01
dc.b nMaxPSG2
smpsPSGvoice sTone_02
smpsLoop $01, $02, Snd_SpecialS_Loop17
Snd_SpecialS_Loop18:
dc.b nMaxPSG2, $06, nMaxPSG2
smpsPSGAlterVol $FC
dc.b nMaxPSG2
smpsPSGAlterVol $04
dc.b nMaxPSG2
smpsLoop $00, $20, Snd_SpecialS_Loop18
Snd_SpecialS_Loop19:
smpsPSGvoice sTone_02
dc.b nMaxPSG2, nMaxPSG2
smpsPSGAlterVol $FC
dc.b nMaxPSG2
smpsPSGAlterVol $04
dc.b nMaxPSG2
smpsLoop $00, $03, Snd_SpecialS_Loop19
dc.b nMaxPSG2, nMaxPSG2, nMaxPSG2
smpsPSGvoice sTone_01
dc.b nMaxPSG2
smpsLoop $01, $08, Snd_SpecialS_Loop19
smpsJump Snd_SpecialS_Loop14
; DAC Data
Snd_SpecialS_DAC:
dc.b dQuickLooseSnare, $06, dKickS3, $0C, dQuickLooseSnare, $06, dKickS3, $0C, dKickS3, dKickS3, dKickS3, dQuickLooseSnare
dc.b dKickS3, dQuickLooseSnare, $06, dQuickLooseSnare, $0C, dQuickLooseSnare, $06, dKickS3, $0C, dQuickLooseSnare, $06, dQuickLooseSnare
dc.b $0C, dKickS3, dKickS3, $06, dQuickLooseSnare, $0C, dQuickLooseSnare, $06, dQuickLooseSnare, dKickS3, $06, dElectricHighTom
dc.b $03, dElectricHighTom, dElectricHighTom, $06, dElectricHighTom, dElectricMidTom, dElectricMidTom, dElectricMidTom, dElectricLowTom, dElectricLowTom, dElectricLowTom, dKickS3
dc.b dKickS3, dQuickLooseSnare, dKickS3, $12
Snd_SpecialS_Loop00:
dc.b dKickS3, $12, dKickS3, $06, dQuickLooseSnare, dKickS3, $0C, dKickS3, dKickS3, $12, dQuickLooseSnare, $06
dc.b dKickS3, $12
smpsLoop $00, $03, Snd_SpecialS_Loop00
dc.b dKickS3, $12, dKickS3, $06, dQuickLooseSnare, dKickS3, $0C, dKickS3, dKickS3, $12, dQuickLooseSnare, $0C
dc.b dQuickLooseSnare, $06, dQuickLooseSnare
Snd_SpecialS_Loop01:
dc.b dKickS3, $12, dKickS3, $06, dQuickLooseSnare, $0C, dKickS3, $06, dQuickLooseSnare, $12, dKickS3, $0C
dc.b dQuickLooseSnare, dKickS3, $06, dKickS3
smpsLoop $00, $03, Snd_SpecialS_Loop01
dc.b dKickS3, $12, dKickS3, $06, dQuickLooseSnare, $0C, dKickS3, dQuickLooseSnare, dKickS3, dQuickLooseSnare, dKickS3
Snd_SpecialS_Loop02:
dc.b dKickS3, $12, dKickS3, $06, dQuickLooseSnare, $0C, dKickS3
smpsLoop $00, $10, Snd_SpecialS_Loop02
dc.b dKickS3, $12, dKickS3, $06, dQuickLooseSnare, $0C, dKickS3, $12, dKickS3, dQuickLooseSnare, $06, dKickS3
dc.b $12, dQuickLooseSnare, $06, dQuickLooseSnare, $0C, dQuickLooseSnare, $06, dKickS3, $0C, dQuickLooseSnare, $06, dQuickLooseSnare
dc.b $0C, dKickS3, dKickS3, $06, dQuickLooseSnare, $0C, dQuickLooseSnare, $06, dQuickLooseSnare, $06
Snd_SpecialS_Loop03:
dc.b dKickS3, $12, dKickS3, dKickS3, $24, dQuickLooseSnare, $18
smpsLoop $00, $07, Snd_SpecialS_Loop03
dc.b dKickS3, $12, dKickS3, $06, dQuickLooseSnare, $0C, dKickS3, $1E, dKickS3, $06, dQuickLooseSnare, dQuickLooseSnare
dc.b dQuickLooseSnare, dQuickLooseSnare
Snd_SpecialS_Loop04:
dc.b dKickS3, $12, dKickS3, $06, dQuickLooseSnare, dKickS3, $0C, dKickS3, dKickS3, $12, dQuickLooseSnare, $06
dc.b dKickS3, $12
smpsLoop $00, $07, Snd_SpecialS_Loop04
dc.b dKickS3, $06, dKickS3, dQuickLooseSnare, dKickS3, dKickS3, dQuickLooseSnare, $0C, dQuickLooseSnare, $06, dKickS3, dElectricHighTom
dc.b $03, dElectricHighTom, dElectricHighTom, $06, dElectricHighTom, dElectricMidTom, dElectricMidTom, dElectricLowTom, dElectricLowTom
smpsJump Snd_SpecialS_Loop00
Snd_SpecialS_Voices:
; Voice $00
; $3C
; $01, $00, $00, $00, $1F, $1F, $15, $1F, $11, $0D, $12, $05
; $07, $04, $09, $02, $55, $3A, $25, $1A, $1A, $80, $07, $80
smpsVcAlgorithm $04
smpsVcFeedback $07
smpsVcUnusedBits $00
smpsVcDetune $00, $00, $00, $00
smpsVcCoarseFreq $00, $00, $00, $01
smpsVcRateScale $00, $00, $00, $00
smpsVcAttackRate $1F, $15, $1F, $1F
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $05, $12, $0D, $11
smpsVcDecayRate2 $02, $09, $04, $07
smpsVcDecayLevel $01, $02, $03, $05
smpsVcReleaseRate $0A, $05, $0A, $05
smpsVcTotalLevel $00, $07, $00, $1A
; Voice $01
; $3D
; $01, $01, $01, $01, $94, $19, $19, $19, $0F, $0D, $0D, $0D
; $07, $04, $04, $04, $25, $1A, $1A, $1A, $15, $80, $80, $80
smpsVcAlgorithm $05
smpsVcFeedback $07
smpsVcUnusedBits $00
smpsVcDetune $00, $00, $00, $00
smpsVcCoarseFreq $01, $01, $01, $01
smpsVcRateScale $00, $00, $00, $02
smpsVcAttackRate $19, $19, $19, $14
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $0D, $0D, $0D, $0F
smpsVcDecayRate2 $04, $04, $04, $07
smpsVcDecayLevel $01, $01, $01, $02
smpsVcReleaseRate $0A, $0A, $0A, $05
smpsVcTotalLevel $00, $00, $00, $15
; Voice $02
; $03
; $00, $D7, $33, $02, $5F, $9F, $5F, $1F, $13, $0F, $0A, $0A
; $10, $0F, $02, $09, $35, $15, $25, $1A, $13, $16, $15, $80
smpsVcAlgorithm $03
smpsVcFeedback $00
smpsVcUnusedBits $00
smpsVcDetune $00, $03, $0D, $00
smpsVcCoarseFreq $02, $03, $07, $00
smpsVcRateScale $00, $01, $02, $01
smpsVcAttackRate $1F, $1F, $1F, $1F
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $0A, $0A, $0F, $13
smpsVcDecayRate2 $09, $02, $0F, $10
smpsVcDecayLevel $01, $02, $01, $03
smpsVcReleaseRate $0A, $05, $05, $05
smpsVcTotalLevel $00, $15, $16, $13
; Voice $03
; $34
; $00, $02, $01, $01, $1F, $1F, $1F, $1F, $10, $06, $06, $06
; $01, $06, $06, $06, $35, $1A, $15, $1A, $10, $80, $18, $80
smpsVcAlgorithm $04
smpsVcFeedback $06
smpsVcUnusedBits $00
smpsVcDetune $00, $00, $00, $00
smpsVcCoarseFreq $01, $01, $02, $00
smpsVcRateScale $00, $00, $00, $00
smpsVcAttackRate $1F, $1F, $1F, $1F
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $06, $06, $06, $10
smpsVcDecayRate2 $06, $06, $06, $01
smpsVcDecayLevel $01, $01, $01, $03
smpsVcReleaseRate $0A, $05, $0A, $05
smpsVcTotalLevel $00, $18, $00, $10
; Voice $04
; $3E
; $07, $01, $02, $01, $1F, $1F, $1F, $1F, $0D, $06, $00, $00
; $08, $06, $00, $00, $15, $0A, $0A, $0A, $1B, $80, $80, $80
smpsVcAlgorithm $06
smpsVcFeedback $07
smpsVcUnusedBits $00
smpsVcDetune $00, $00, $00, $00
smpsVcCoarseFreq $01, $02, $01, $07
smpsVcRateScale $00, $00, $00, $00
smpsVcAttackRate $1F, $1F, $1F, $1F
smpsVcAmpMod $00, $00, $00, $00
smpsVcDecayRate1 $00, $00, $06, $0D
smpsVcDecayRate2 $00, $00, $06, $08
smpsVcDecayLevel $00, $00, $00, $01
smpsVcReleaseRate $0A, $0A, $0A, $05
smpsVcTotalLevel $00, $00, $00, $1B
|
// boost asinh.hpp header file
// (C) Copyright Eric Ford 2001 & Hubert Holin.
// (C) Copyright John Maddock 2008.
// Distributed under the Boost Software License, Version 1.0. (See
// accompanying file LICENSE_1_0.txt or copy at
// http://www.boost.org/LICENSE_1_0.txt)
// See http://www.boost.org for updates, documentation, and revision history.
#ifndef BOOST_ACOSH_HPP
#define BOOST_ACOSH_HPP
#ifdef _MSC_VER
#pragma once
#endif
#include <boost/config/no_tr1/cmath.hpp>
#include <boost/config.hpp>
#include <boost/math/tools/precision.hpp>
#include <boost/math/policies/error_handling.hpp>
#include <boost/math/special_functions/math_fwd.hpp>
#include <boost/math/special_functions/log1p.hpp>
// This is the inverse of the hyperbolic cosine function.
namespace boost
{
namespace math
{
namespace detail
{
#if defined(__GNUC__) && (__GNUC__ < 3)
// gcc 2.x ignores function scope using declarations,
// put them in the scope of the enclosing namespace instead:
using ::std::abs;
using ::std::sqrt;
using ::std::log;
using ::std::numeric_limits;
#endif
template<typename T, typename Policy>
inline T acosh_imp(const T x, const Policy& pol)
{
BOOST_MATH_STD_USING
if(x < 1)
{
return policies::raise_domain_error<T>(
"boost::math::acosh<%1%>(%1%)",
"acosh requires x >= 1, but got x = %1%.", x, pol);
}
else if ((x - 1) >= tools::root_epsilon<T>())
{
if (x > 1 / tools::root_epsilon<T>())
{
// http://functions.wolfram.com/ElementaryFunctions/ArcCosh/06/01/06/01/0001/
// approximation by laurent series in 1/x at 0+ order from -1 to 0
return( log( x * 2) );
}
else if(x < 1.5f)
{
// This is just a rearrangement of the standard form below
// devised to minimse loss of precision when x ~ 1:
T y = x - 1;
return boost::math::log1p(y + sqrt(y * y + 2 * y), pol);
}
else
{
// http://functions.wolfram.com/ElementaryFunctions/ArcCosh/02/
return( log( x + sqrt(x * x - 1) ) );
}
}
else
{
// see http://functions.wolfram.com/ElementaryFunctions/ArcCosh/06/01/04/01/0001/
T y = x - 1;
// approximation by taylor series in y at 0 up to order 2
T result = sqrt(2 * y) * (1 + y /12 + 3 * y * y / 160);
return result;
}
}
}
template<typename T, typename Policy>
inline typename tools::promote_args<T>::type acosh(T x, const Policy&)
{
typedef typename tools::promote_args<T>::type result_type;
typedef typename policies::evaluation<result_type, Policy>::type value_type;
typedef typename policies::normalise<
Policy,
policies::promote_float<false>,
policies::promote_double<false>,
policies::discrete_quantile<>,
policies::assert_undefined<> >::type forwarding_policy;
return policies::checked_narrowing_cast<result_type, forwarding_policy>(
detail::acosh_imp(static_cast<value_type>(x), forwarding_policy()),
"boost::math::acosh<%1%>(%1%)");
}
template<typename T>
inline typename tools::promote_args<T>::type acosh(T x)
{
return boost::math::acosh(x, policies::policy<>());
}
}
}
#endif /* BOOST_ACOSH_HPP */
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r13
push %r9
push %rax
push %rbx
lea addresses_WT_ht+0xc825, %rax
nop
xor $1013, %r11
mov (%rax), %r13d
nop
inc %rbx
lea addresses_D_ht+0x20f5, %r9
clflush (%r9)
nop
nop
nop
nop
nop
xor $28401, %rax
vmovups (%r9), %ymm4
vextracti128 $0, %ymm4, %xmm4
vpextrq $0, %xmm4, %rbx
and $42658, %r13
pop %rbx
pop %rax
pop %r9
pop %r13
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r8
push %r9
push %rax
push %rcx
push %rdi
// Store
lea addresses_RW+0x14d65, %rdi
nop
nop
nop
xor %r8, %r8
movw $0x5152, (%rdi)
nop
nop
nop
nop
nop
xor %r8, %r8
// Store
lea addresses_normal+0x1bdff, %rax
nop
sub %rcx, %rcx
mov $0x5152535455565758, %r11
movq %r11, (%rax)
nop
nop
nop
cmp $26693, %r11
// Faulty Load
lea addresses_US+0x15825, %rax
nop
nop
nop
nop
nop
xor $7952, %r10
mov (%rax), %r9d
lea oracles, %r8
and $0xff, %r9
shlq $12, %r9
mov (%r8,%r9,1), %r9
pop %rdi
pop %rcx
pop %rax
pop %r9
pop %r8
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'type': 'addresses_US', 'same': False, 'size': 4, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'dst': {'type': 'addresses_RW', 'same': False, 'size': 2, 'congruent': 6, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
{'dst': {'type': 'addresses_normal', 'same': False, 'size': 8, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'type': 'addresses_US', 'same': True, 'size': 4, 'congruent': 0, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'type': 'addresses_WT_ht', 'same': False, 'size': 4, 'congruent': 8, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'src': {'type': 'addresses_D_ht', 'same': False, 'size': 32, 'congruent': 4, 'NT': False, 'AVXalign': False}, 'OP': 'LOAD'}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
/* Copyright Institute of Sound and Vibration Research - All rights reserved */
#include "diffuse_source.hpp"
namespace visr
{
namespace objectmodel
{
DiffuseSource::DiffuseSource( ObjectId id )
: Object( id )
{
}
/*virtual*/ DiffuseSource::~DiffuseSource() = default;
/*virtual*/ ObjectTypeId
DiffuseSource::type() const
{
return ObjectTypeId::DiffuseSource;
}
/*virtual*/ std::unique_ptr<Object>
DiffuseSource::clone() const
{
return std::unique_ptr<Object>( new DiffuseSource( *this ) );
}
} // namespace objectmodel
} // namespace visr
|
; A082107: Diagonal sums of number array A082105.
; 1,2,8,28,79,190,406,792,1437,2458,4004,6260,9451,13846,19762,27568,37689,50610,66880,87116,112007,142318,178894,222664,274645,335946,407772,491428,588323,699974,828010,974176,1140337,1328482,1540728
mov $16,$0
mov $18,$0
add $18,1
lpb $18,1
clr $0,16
mov $0,$16
sub $18,1
sub $0,$18
mov $13,$0
mov $15,$0
add $15,1
lpb $15,1
mov $0,$13
sub $15,1
sub $0,$15
mov $9,$0
mov $11,2
lpb $11,1
mov $0,$9
sub $11,1
add $0,$11
sub $0,1
mov $3,$0
mul $3,$0
sub $3,$0
mov $0,7
add $0,$3
mov $7,6
add $7,$0
mul $7,$3
mov $1,$7
div $1,2
mov $2,3
add $2,$1
mov $1,$2
mov $12,$11
lpb $12,1
mov $10,$1
sub $12,1
lpe
lpe
lpb $9,1
mov $9,0
sub $10,$1
lpe
mov $1,$10
div $1,3
add $14,$1
lpe
add $17,$14
lpe
mov $1,$17
|
; A017365: a(n) = 10n + 8.
; 8,18,28,38,48,58,68,78,88,98,108,118,128,138,148,158,168,178,188,198,208,218,228,238,248,258,268,278,288,298,308,318,328,338,348,358,368,378,388,398,408,418,428,438,448,458,468,478,488,498,508,518,528,538,548,558,568,578,588,598,608,618,628,638,648,658,668,678,688,698,708,718,728,738,748,758,768,778,788,798,808,818,828,838,848,858,868,878,888,898,908,918,928,938,948,958,968,978,988,998,1008,1018,1028,1038,1048,1058,1068,1078,1088,1098,1108,1118,1128,1138,1148,1158,1168,1178,1188,1198,1208,1218,1228,1238,1248,1258,1268,1278,1288,1298,1308,1318,1328,1338,1348,1358,1368,1378,1388,1398,1408,1418,1428,1438,1448,1458,1468,1478,1488,1498,1508,1518,1528,1538,1548,1558,1568,1578,1588,1598,1608,1618,1628,1638,1648,1658,1668,1678,1688,1698,1708,1718,1728,1738,1748,1758,1768,1778,1788,1798,1808,1818,1828,1838,1848,1858,1868,1878,1888,1898,1908,1918,1928,1938,1948,1958,1968,1978,1988,1998,2008,2018,2028,2038,2048,2058,2068,2078,2088,2098,2108,2118,2128,2138,2148,2158,2168,2178,2188,2198,2208,2218,2228,2238,2248,2258,2268,2278,2288,2298,2308,2318,2328,2338,2348,2358,2368,2378,2388,2398,2408,2418,2428,2438,2448,2458,2468,2478,2488,2498
mov $1,$0
mul $1,10
add $1,8
|
.include "defaults_mod.asm"
table_file_jp equ "exe4-utf8.tbl"
table_file_en equ "bn4-utf8.tbl"
game_code_len equ 3
game_code equ 0x4234574A // B4WJ
game_code_2 equ 0x42345745 // B4WE
game_code_3 equ 0x42345750 // B4WP
card_type equ 1
card_id equ 70
card_no equ "070"
card_sub equ "Mod Card 070"
card_sub_x equ 64
card_desc_len equ 2
card_desc_1 equ "Address 0D"
card_desc_2 equ "B+Left PnlRetrn"
card_desc_3 equ ""
card_name_jp_full equ "B+左でパネルリターン"
card_name_jp_game equ "B+左でパネルリターン"
card_name_en_full equ "B+Left PnlRetrn"
card_name_en_game equ "B+Left PnlRetrn"
card_address equ "0D"
card_address_id equ 3
card_bug equ 0
card_wrote_en equ "B+Left PnlRetrn"
card_wrote_jp equ "B+左でパネルリターン" |
; A321237: Start with a square of dimension 1 X 1, and repeatedly append along the squares of the previous step squares with half their side length that do not overlap with any prior square; a(n) gives the number of squares appended at n-th step.
; 1,8,28,68,148,308,628,1268,2548,5108,10228,20468,40948,81908,163828,327668,655348,1310708,2621428,5242868,10485748,20971508,41943028,83886068,167772148,335544308,671088628,1342177268,2684354548,5368709108,10737418228,21474836468,42949672948,85899345908,171798691828,343597383668,687194767348,1374389534708,2748779069428,5497558138868,10995116277748,21990232555508,43980465111028,87960930222068,175921860444148,351843720888308,703687441776628,1407374883553268,2814749767106548,5629499534213108,11258999068426228,22517998136852468,45035996273704948,90071992547409908,180143985094819828,360287970189639668,720575940379279348,1441151880758558708,2882303761517117428,5764607523034234868,11529215046068469748,23058430092136939508,46116860184273879028,92233720368547758068,184467440737095516148,368934881474191032308,737869762948382064628,1475739525896764129268,2951479051793528258548,5902958103587056517108,11805916207174113034228,23611832414348226068468,47223664828696452136948,94447329657392904273908,188894659314785808547828,377789318629571617095668,755578637259143234191348,1511157274518286468382708,3022314549036572936765428,6044629098073145873530868,12089258196146291747061748,24178516392292583494123508,48357032784585166988247028,96714065569170333976494068,193428131138340667952988148,386856262276681335905976308,773712524553362671811952628,1547425049106725343623905268,3094850098213450687247810548,6189700196426901374495621108,12379400392853802748991242228,24758800785707605497982484468,49517601571415210995964968948,99035203142830421991929937908,198070406285660843983859875828,396140812571321687967719751668,792281625142643375935439503348,1584563250285286751870879006708,3169126500570573503741758013428,6338253001141147007483516026868
mov $1,2
pow $1,$0
mul $1,10
trn $1,13
add $1,1
mov $0,$1
|
//#define GOOGLE_CUDA 1
#if GOOGLE_CUDA
#define EIGEN_USE_GPU
#include "select_knn_grad_kernel.h"
#include "helpers.h"
#include "tensorflow/core/util/gpu_kernel_helper.h"
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include "cuda_helpers.h"
namespace tensorflow {
namespace functor {
namespace gpu{
/*
__device__
static float calculateDistance(size_t i_v, size_t j_v, const float * d_coord, size_t n_coords){
float distsq=0;
if(i_v == j_v)
return 0;
for(size_t i=0;i<n_coords;i++){
float dist = d_coord[I2D(i_v,i,n_coords)] - d_coord[I2D(j_v,i,n_coords)];
distsq += dist*dist;
}
return distsq;
}
__device__
static int searchLargestDistance(int i_v, float* d_dist, int n_neigh, float& maxdist){
maxdist=0;
int maxidx=0;
if(n_neigh < 2)
return maxidx;
for(size_t n=1;n<n_neigh;n++){ //0 is self
float distsq = d_dist[I2D(i_v,n,n_neigh)];
if(distsq > maxdist){
maxdist = distsq;
maxidx = n;
}
}
return maxidx;
}
__global__
static void set_defaults(
int *d_indices,
float *d_dist,
const bool tf_compat,
const int n_vert,
const int n_neigh
){
const size_t i_v = blockIdx.x * blockDim.x + threadIdx.x;
if(i_v >= n_vert)
return;
const size_t n = blockIdx.y * blockDim.y + threadIdx.y;
if(n >= n_neigh)
return;
if(n){
if(tf_compat)
d_indices[I2D(i_v,n,n_neigh)] = i_v;
else
d_indices[I2D(i_v,n,n_neigh)] = -1;
}
else{
d_indices[I2D(i_v,n,n_neigh)] = i_v;
}
d_dist[I2D(i_v,n,n_neigh)] = 0;
}
*/
__global__
static void select_knn_grad_selfloop_kernel(
const float *d_grad_dist, // V x N
const int *d_neigh_indices,
const float *d_dist,
const float *d_coord,
float * d_grad_coord,
const int n_vert,
const int n_neigh,
const int n_coords) {
size_t i_v = blockIdx.x * blockDim.x + threadIdx.x;
if(i_v >= n_vert)
return;
size_t nu_c= blockIdx.y * blockDim.y + threadIdx.y;
if(nu_c >= n_coords)
return;
const float xinu = d_coord[I2D(i_v,nu_c,n_coords)];
float self_contrib=0;
for(size_t i_i_n = 0; i_i_n < n_neigh; i_i_n++){
int k = d_neigh_indices[I2D(i_v, i_i_n, n_neigh)];
if(k<0 || k>= n_vert){
if( k>= n_vert)
printf("select_knn_grad_kernel: k out of range\n");
continue;
}
const float gik = d_grad_dist[I2D(i_v,i_i_n,n_neigh)];
const float xknu = d_coord[I2D(k,nu_c,n_coords)];
self_contrib -= 2. * gik * (xknu - xinu);
}
d_grad_coord[I2D(i_v,nu_c,n_coords)] = self_contrib;
}
__global__
static void select_knn_grad_neighloop_kernel(
const float *d_grad_dist, // V x N
const int *d_neigh_indices,
const float *d_dist,
const float *d_coord,
float * d_grad_coord,
const int n_vert,
const int n_neigh,
const int n_coords){
size_t i_v = blockIdx.x * blockDim.x + threadIdx.x;
if(i_v >= n_vert)
return;
size_t nu_c= blockIdx.y * blockDim.y + threadIdx.y;
if(nu_c >= n_coords)
return;
const float xinu = d_coord[I2D(i_v,nu_c,n_coords)];
for(size_t i_i_n = 0; i_i_n < n_neigh; i_i_n++){
int m = d_neigh_indices[I2D(i_v, i_i_n, n_neigh)];
if(m<0 || m>= n_vert){
if(m>= n_vert)
printf("select_knn_grad_kernel: m out of range\n");
continue;
}
const float gim = d_grad_dist[I2D(i_v,i_i_n,n_neigh)];
const float xmnu = d_coord[I2D(m,nu_c,n_coords)];
float add = 2. * gim * (xmnu - xinu);
atomicAdd( &d_grad_coord[I2D(m, nu_c, n_coords)], add);
}
}
}//gpu
typedef Eigen::GpuDevice GPUDevice;
template <typename dummy>
struct SelectKnnGradOpFunctor<GPUDevice, dummy> {
void operator()(const GPUDevice& d,
const float *d_grad_dist,
const int *d_indices,
const float *d_dist,
const float *d_coord,
float * d_grad_coord,
const int n_vert,
const int n_neigh,
const int n_coords) {
//for too low n, d_indices might need to be initialised with some number the
// rest of the code understands.. maybe -1?
//just loop over n_rs, in a realistic setting these shouldn't be more than a handful entries
grid_and_block gb(n_vert,256,n_coords,4);
gpu::select_knn_grad_selfloop_kernel<<<gb.grid(),gb.block(), 0, d.stream()>>>(
d_grad_dist,
d_indices,
d_dist,
d_coord,
d_grad_coord,
n_vert,
n_neigh,
n_coords
);
cudaDeviceSynchronize();
gpu::select_knn_grad_neighloop_kernel<<<gb.grid(),gb.block(), 0, d.stream()>>>(
d_grad_dist,
d_indices,
d_dist,
d_coord,
d_grad_coord,
n_vert,
n_neigh,
n_coords
);
cudaDeviceSynchronize();
}
};
template struct SelectKnnGradOpFunctor<GPUDevice, int>;
}//functor
}//tensorflow
#endif // GOOGLE_CUDA
|
// Copyright 2021 Rainer Schoenberger
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <inttypes.h>
#include <string.h>
namespace ZCMessagePack
{
class Encoder
{
public:
/// Constructs the encoder.
/// The given buffer f_out_borrow_messageBuffer will be used to write
/// encoded data to.
Encoder(uint8_t * f_out_borrow_messageBuffer, uint8_t f_bufferSize);
/// Encodes an unsigned integer into the buffer.
bool addUint(uint32_t f_number);
/// Encodes a string into the buffer.
/// f_string needs to be null terminated.
bool addString(const char * f_string);
/// Encodes given binary data into the buffer.
bool addBinary(const uint8_t * f_data, uint8_t f_size);
/// Encodes given boolean value into the buffer.
bool addBool(bool f_value);
/// Encodes "Nil" into the buffer.
bool addNil();
/// Add a Map header for the given number of elements.
/// NOTE: The user needs to ensure that the resulting message is well formed.
/// After this header the following tuple needs to be added
/// f_numElements times:
/// - a string
/// - any MessagePack element
bool addMap(uint8_t f_numElements);
/// Add an Array header for the given number of elements.
/// NOTE: The user needs to ensure that the resulting message is well formed.
/// After this header f_numElements need to be encoded.
bool addArray(uint8_t f_numElements);
/// Returns the size of the encoded message
uint8_t getMessageSize() const;
private:
uint8_t sizeLeft();
bool addNestedStructure(uint8_t f_numElements, uint8_t f_smallPrefix, uint8_t f_bigPrefix);
uint8_t * m_messageBuffer;
uint8_t m_bufferSize;
uint8_t m_position = 0;
};
}
|
#include "drape/gl_constants.hpp"
#include "drape/gl_includes.hpp"
#if !defined(GL_RGBA8_OES)
#define GL_RGBA8_OES 0x8058
#endif
#if !defined(GL_RGBA4_OES)
#define GL_RGBA4_OES 0x8056
#endif
#if !defined(GL_ALPHA8_OES)
#define GL_ALPHA8_OES 0x803C
#endif
#if !defined(GL_LUMINANCE8_OES)
#define GL_LUMINANCE8_OES 0x8040
#endif
#if !defined(GL_LUMINANCE8_ALPHA8_OES)
#define GL_LUMINANCE8_ALPHA8_OES 0x8045
#endif
#if !defined(GL_LUMINANCE8_ALPHA4_OES)
#define GL_LUMINANCE8_ALPHA4_OES 0x8043
#endif
#if !defined(GL_LUMINANCE)
#define GL_LUMINANCE 0x1909
#endif
#if !defined(GL_LUMINANCE_ALPHA)
#define GL_LUMINANCE_ALPHA 0x190A
#endif
#if defined(GL_WRITE_ONLY)
#define WRITE_ONLY_DEF GL_WRITE_ONLY
#elif defined(GL_WRITE_ONLY_OES)
#define WRITE_ONLY_DEF GL_WRITE_ONLY_OES
#else
#define WRITE_ONLY_DEF 0x88B9
#endif
#if defined(GL_READ_ONLY)
#define READ_ONLY_DEF GL_READ_ONLY
#else
#define READ_ONLY_DEF 0x88B8
#endif
#if defined(GL_MAP_READ_BIT_EXT)
#define READ_BIT_DEF GL_MAP_READ_BIT_EXT
#else
#define READ_BIT_DEF 0x0001
#endif
#if defined(GL_MAP_WRITE_BIT_EXT)
#define WRITE_BIT_DEF GL_MAP_WRITE_BIT_EXT
#else
#define WRITE_BIT_DEF 0x0002
#endif
#if defined(GL_MAP_INVALIDATE_RANGE_BIT_EXT)
#define INVALIDATE_RANGE_BIT_DEF GL_MAP_INVALIDATE_RANGE_BIT_EXT
#else
#define INVALIDATE_RANGE_BIT_DEF 0x0004
#endif
#if defined(GL_MAP_INVALIDATE_BUFFER_BIT_EXT)
#define INVALIDATE_BUFFER_BIT_DEF GL_MAP_INVALIDATE_BUFFER_BIT_EXT
#else
#define INVALIDATE_BUFFER_BIT_DEF 0x0008
#endif
#if defined(GL_MAP_FLUSH_EXPLICIT_BIT_EXT)
#define FLUSH_EXPLICIT_BIT_DEF GL_MAP_FLUSH_EXPLICIT_BIT_EXT
#else
#define FLUSH_EXPLICIT_BIT_DEF 0x0010
#endif
#if defined(GL_MAP_UNSYNCHRONIZED_BIT_EXT)
#define UNSYNCHRONIZED_BIT_DEF GL_MAP_UNSYNCHRONIZED_BIT_EXT
#else
#define UNSYNCHRONIZED_BIT_DEF 0x0020
#endif
#if !defined(GL_FUNC_ADD)
#define GL_FUNC_ADD 0x8006
#endif
#if !defined(GL_FUNC_SUBTRACT)
#define GL_FUNC_SUBTRACT 0x800A
#endif
#if !defined(GL_FUNC_REVERSE_SUBTRACT)
#define GL_FUNC_REVERSE_SUBTRACT 0x800B
#endif
namespace gl_const
{
const glConst GLUnpackAlignment = GL_UNPACK_ALIGNMENT;
const glConst GLRenderer = GL_RENDERER;
const glConst GLVendor = GL_VENDOR;
const glConst GLVersion = GL_VERSION;
#ifdef GL_VERSION_3_0
const glConst glContextFlags = GL_CONTEXT_FLAGS;
#else
const glConst glContextFlags = 0;
#endif
const glConst GLColorBit = GL_COLOR_BUFFER_BIT;
const glConst GLDepthBit = GL_DEPTH_BUFFER_BIT;
const glConst GLStencilBit = GL_STENCIL_BUFFER_BIT;
const glConst GLMaxFragmentTextures = GL_MAX_TEXTURE_IMAGE_UNITS;
const glConst GLMaxVertexTextures = GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS;
const glConst GLMaxTextureSize = GL_MAX_TEXTURE_SIZE;
const glConst GLArrayBuffer = GL_ARRAY_BUFFER;
const glConst GLElementArrayBuffer = GL_ELEMENT_ARRAY_BUFFER;
const glConst GLPixelBufferWrite = GL_PIXEL_UNPACK_BUFFER;
const glConst GLBufferSize = GL_BUFFER_SIZE;
const glConst GLBufferUsage = GL_BUFFER_USAGE;
const glConst GLWriteOnly = WRITE_ONLY_DEF;
const glConst GLReadOnly = READ_ONLY_DEF;
const glConst GLReadBufferBit = READ_BIT_DEF;
const glConst GLWriteBufferBit = WRITE_BIT_DEF;
const glConst GLInvalidateRange = INVALIDATE_RANGE_BIT_DEF;
const glConst GLInvalidateBuffer = INVALIDATE_BUFFER_BIT_DEF;
const glConst GLFlushExplicit = FLUSH_EXPLICIT_BIT_DEF;
const glConst GLUnsynchronized = UNSYNCHRONIZED_BIT_DEF;
const glConst GLStaticDraw = GL_STATIC_DRAW;
const glConst GLStreamDraw = GL_STREAM_DRAW;
const glConst GLDynamicDraw = GL_DYNAMIC_DRAW;
const glConst GLVertexShader = GL_VERTEX_SHADER;
const glConst GLFragmentShader = GL_FRAGMENT_SHADER;
const glConst GLCurrentProgram = GL_CURRENT_PROGRAM;
const glConst GLRGBA = GL_RGBA;
const glConst GLRGB = GL_RGB;
const glConst GLAlpha = GL_ALPHA;
const glConst GLLuminance = GL_LUMINANCE;
const glConst GLAlphaLuminance = GL_LUMINANCE_ALPHA;
const glConst GLDepthComponent = GL_DEPTH_COMPONENT;
const glConst GLDepthStencil = GL_DEPTH_STENCIL;
const glConst GLRGBA8 = GL_RGBA8_OES;
const glConst GLRGBA4 = GL_RGBA4_OES;
const glConst GLAlpha8 = GL_ALPHA8_OES;
const glConst GLLuminance8 = GL_LUMINANCE8_OES;
const glConst GLAlphaLuminance8 = GL_LUMINANCE8_ALPHA8_OES;
const glConst GLAlphaLuminance4 = GL_LUMINANCE8_ALPHA4_OES;
const glConst GLRed = GL_RED;
const glConst GLRedGreen = GL_RG;
const glConst GL8BitOnChannel = GL_UNSIGNED_BYTE;
const glConst GL4BitOnChannel = GL_UNSIGNED_SHORT_4_4_4_4;
const glConst GLTexture2D = GL_TEXTURE_2D;
const glConst GLTexture0 = GL_TEXTURE0;
const glConst GLMinFilter = GL_TEXTURE_MIN_FILTER;
const glConst GLMagFilter = GL_TEXTURE_MAG_FILTER;
const glConst GLWrapS = GL_TEXTURE_WRAP_S;
const glConst GLWrapT = GL_TEXTURE_WRAP_T;
const glConst GLRepeat = GL_REPEAT;
const glConst GLMirroredRepeat = GL_MIRRORED_REPEAT;
const glConst GLClampToEdge = GL_CLAMP_TO_EDGE;
const glConst GLLinear = GL_LINEAR;
const glConst GLNearest = GL_NEAREST;
const glConst GLByteType = GL_BYTE;
const glConst GLUnsignedByteType = GL_UNSIGNED_BYTE;
const glConst GLShortType = GL_SHORT;
const glConst GLUnsignedShortType = GL_UNSIGNED_SHORT;
const glConst GLIntType = GL_INT;
const glConst GLUnsignedIntType = GL_UNSIGNED_INT;
const glConst GLFloatType = GL_FLOAT;
const glConst GLUnsignedInt24_8Type = GL_UNSIGNED_INT_24_8;
const glConst GLFloatVec2 = GL_FLOAT_VEC2;
const glConst GLFloatVec3 = GL_FLOAT_VEC3;
const glConst GLFloatVec4 = GL_FLOAT_VEC4;
const glConst GLIntVec2 = GL_INT_VEC2;
const glConst GLIntVec3 = GL_INT_VEC3;
const glConst GLIntVec4 = GL_INT_VEC4;
const glConst GLFloatMat4 = GL_FLOAT_MAT4;
const glConst GLSampler2D = GL_SAMPLER_2D;
const glConst GLAddBlend = GL_FUNC_ADD;
const glConst GLSubstractBlend = GL_FUNC_SUBTRACT;
const glConst GLReverseSubstrBlend = GL_FUNC_REVERSE_SUBTRACT;
const glConst GLZero = GL_ZERO;
const glConst GLOne = GL_ONE;
const glConst GLSrcColor = GL_SRC_COLOR;
const glConst GLOneMinusSrcColor = GL_ONE_MINUS_SRC_COLOR;
const glConst GLDstColor = GL_DST_COLOR;
const glConst GLOneMinusDstColor = GL_ONE_MINUS_DST_COLOR;
const glConst GLSrcAlpha = GL_SRC_ALPHA;
const glConst GLOneMinusSrcAlpha = GL_ONE_MINUS_SRC_ALPHA;
const glConst GLDstAlpha = GL_DST_ALPHA;
const glConst GLOneMinusDstAlpha = GL_ONE_MINUS_DST_ALPHA;
const glConst GLDepthTest = GL_DEPTH_TEST;
const glConst GLBlending = GL_BLEND;
const glConst GLCullFace = GL_CULL_FACE;
const glConst GLScissorTest = GL_SCISSOR_TEST;
const glConst GLStencilTest = GL_STENCIL_TEST;
const glConst GLDontCare = GL_DONT_CARE;
const glConst GLTrue = GL_TRUE;
const glConst GLFalse = GL_FALSE;
#ifdef GL_VERSION_4_3
const glConst GLDebugOutput = GL_DEBUG_OUTPUT;
const glConst GLDebugOutputSynchronous = GL_DEBUG_OUTPUT_SYNCHRONOUS;
const glConst GLDebugSourceApi = GL_DEBUG_SOURCE_API;
const glConst GLDebugSourceShaderCompiler = GL_DEBUG_SOURCE_SHADER_COMPILER;
const glConst GLDebugSourceThirdParty = GL_DEBUG_SOURCE_THIRD_PARTY;
const glConst GLDebugSourceApplication = GL_DEBUG_SOURCE_APPLICATION;
const glConst GLDebugSourceOther = GL_DEBUG_SOURCE_OTHER;
const glConst GLDebugTypeError = GL_DEBUG_TYPE_ERROR;
const glConst GLDebugDeprecatedBehavior = GL_DEBUG_TYPE_DEPRECATED_BEHAVIOR;
const glConst GLDebugUndefinedBehavior = GL_DEBUG_TYPE_UNDEFINED_BEHAVIOR;
const glConst GLDebugPortability = GL_DEBUG_TYPE_PORTABILITY;
const glConst GLDebugPerformance = GL_DEBUG_TYPE_PERFORMANCE;
const glConst GLDebugOther = GL_DEBUG_TYPE_OTHER;
const glConst GLDebugSeverityLow = GL_DEBUG_SEVERITY_LOW;
const glConst GLDebugSeverityMedium = GL_DEBUG_SEVERITY_MEDIUM;
const glConst GLDebugSeverityHigh = GL_DEBUG_SEVERITY_HIGH;
const glConst GLDebugSeverityNotification = GL_DEBUG_SEVERITY_NOTIFICATION;
const glConst glContextFlagDebugBit = GL_CONTEXT_FLAG_DEBUG_BIT;
#else
const glConst GLDebugOutput = 0;
const glConst GLDebugOutputSynchronous = 0;
const glConst GLDebugSourceApi = 0;
const glConst GLDebugSourceShaderCompiler = 0;
const glConst GLDebugSourceThirdParty = 0;
const glConst GLDebugSourceApplication = 0;
const glConst GLDebugSourceOther = 0;
const glConst GLDebugTypeError = 0;
const glConst GLDebugDeprecatedBehavior = 0;
const glConst GLDebugUndefinedBehavior = 0;
const glConst GLDebugPortability = 0;
const glConst GLDebugPerformance = 0;
const glConst GLDebugOther = 0;
const glConst GLDebugSeverityLow = 0;
const glConst GLDebugSeverityMedium = 0;
const glConst GLDebugSeverityHigh = 0;
const glConst GLDebugSeverityNotification = 0;
const glConst glContextFlagDebugBit = 0;
#endif
const glConst GLClockwise = GL_CW;
const glConst GLCounterClockwise = GL_CCW;
const glConst GLFront = GL_FRONT;
const glConst GLBack = GL_BACK;
const glConst GLFrontAndBack = GL_FRONT_AND_BACK;
const glConst GLNever = GL_NEVER;
const glConst GLLess = GL_LESS;
const glConst GLEqual = GL_EQUAL;
const glConst GLLessOrEqual = GL_LEQUAL;
const glConst GLGreat = GL_GREATER;
const glConst GLNotEqual = GL_NOTEQUAL;
const glConst GLGreatOrEqual = GL_GEQUAL;
const glConst GLAlways = GL_ALWAYS;
const glConst GLKeep = GL_KEEP;
const glConst GLIncr = GL_INCR;
const glConst GLDecr = GL_DECR;
const glConst GLInvert = GL_INVERT;
const glConst GLReplace = GL_REPLACE;
const glConst GLIncrWrap = GL_INCR_WRAP;
const glConst GLDecrWrap = GL_DECR_WRAP;
const glConst GLActiveUniforms = GL_ACTIVE_UNIFORMS;
const glConst GLLines = GL_LINES;
const glConst GLLineStrip = GL_LINE_STRIP;
const glConst GLTriangles = GL_TRIANGLES;
const glConst GLTriangleStrip = GL_TRIANGLE_STRIP;
const glConst GLColorAttachment = GL_COLOR_ATTACHMENT0;
const glConst GLDepthAttachment = GL_DEPTH_ATTACHMENT;
const glConst GLStencilAttachment = GL_STENCIL_ATTACHMENT;
const glConst GLDepthStencilAttachment = GL_DEPTH_STENCIL_ATTACHMENT;
const glConst GLFramebufferComplete = GL_FRAMEBUFFER_COMPLETE;
} // namespace GLConst
|
/* ====================================================================
* The Vovida Software License, Version 1.0
*
* Copyright (c) 2000 Vovida Networks, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* 3. The names "VOCAL", "Vovida Open Communication Application Library",
* and "Vovida Open Communication Application Library (VOCAL)" must
* not be used to endorse or promote products derived from this
* software without prior written permission. For written
* permission, please contact vocal@vovida.org.
*
* 4. Products derived from this software may not be called "VOCAL", nor
* may "VOCAL" appear in their name, without prior written
* permission of Vovida Networks, Inc.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL VOVIDA
* NETWORKS, INC. OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT DAMAGES
* IN EXCESS OF $1,000, NOR FOR ANY INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* ====================================================================
*
* This software consists of voluntary contributions made by Vovida
* Networks, Inc. and many individuals on behalf of Vovida Networks,
* Inc. For more information on Vovida Networks, Inc., please see
* <http://www.vovida.org/>.
*
*/
#include "Literal.hxx"
Literal::Literal() : Data()
{}
Literal::Literal( const char* str, int length )
: Data (str, length)
{}
Literal::Literal( const char* str )
: Data (str)
{}
Literal::Literal( const string& str)
: Data (str)
{}
/*
Literal::Literal( const mstring& mstr)
: Data (mstr)
{}
*/
Literal::Literal( int value)
: Data (value)
{}
Literal::Literal( const Data& data )
: Data (data)
{}
bool
Literal::operator==( const Data& data) const
{
// return static_cast < LiteralImplType* > (dataImpl__)->
// operator==(*(static_cast < LiteralImplType* > (data.dataImpl__)));
return isEqualNoCase(*this, data);
}
bool
Literal::operator==( const char* data) const
{
// return static_cast < LiteralImplType* > (dataImpl__)->
// operator==(*(static_cast < LiteralImplType* > (data.dataImpl__)));
return isEqualNoCase(*this, data);
}
bool
Literal::operator!=(const Data& data) const
{
// return static_cast < LiteralImplType* > (dataImpl__)->operator!=(*(static_cast < LiteralImplType* > (data.dataImpl__)));
return !isEqualNoCase(*this, data);
}
bool
Literal::operator!=(const char* data) const
{
// return static_cast < LiteralImplType* > (dataImpl__)->operator!=(*(static_cast < LiteralImplType* > (data.dataImpl__)));
return !isEqualNoCase(*this, data);
}
bool
operator==(const char* s, const Literal& data)
{
// return static_cast < LiteralImplType* > (data.dataImpl__)->operator==(s);
return isEqualNoCase(data,s);
}
bool
operator==(const Data& s, const Literal& data)
{
// return static_cast < LiteralImplType* > (data.dataImpl__)->operator==(s);
return isEqualNoCase(data,s);
}
bool
operator!=(const char* s, const Literal& data)
{
// return static_cast < LiteralImplType* > (data.dataImpl__)->operator!=(s);
return !isEqualNoCase(data,s);
}
bool
operator!=(const Data& s, const Literal& data)
{
// return static_cast < LiteralImplType* > (data.dataImpl__)->operator!=(s);
return !isEqualNoCase(data,s);
}
/* Local Variables: */
/* c-file-style:"stroustrup" */
/* c-basic-offset:4 */
/* c-file-offsets:((inclass . ++)) */
/* indent-tabs-mode:nil */
/* End: */
|
; ===============================================================
; Dec 2013
; ===============================================================
;
; void *heap_realloc(void *heap, void *p, size_t size)
;
; Resize the memory block p to size bytes. If this cannot
; be done in-place, a new memory block is allocated and the
; data at address p is copied to the new block.
;
; If p == 0, an effective malloc is performed, except a
; successful allocation occurs from the largest block available
; in the heap to allow for further quick growth via realloc.
;
; If p != 0 and size == 0, the block is reduced to zero size
; but is not freed. You must call free to free blocks.
;
; If successful, returns ptr to the reallocated memory block,
; which may be p if the block was resized in place.
;
; If unsuccessful, returns 0 with carry set.
;
; ===============================================================
INCLUDE "clib_cfg.asm"
SECTION code_clib
SECTION code_alloc_malloc
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IF __CLIB_OPT_MULTITHREAD & $01
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PUBLIC asm_heap_realloc
EXTERN asm_heap_realloc_unlocked
EXTERN __heap_lock_acquire, __heap_lock_release_0, error_enolck_zc
asm_heap_realloc:
; Attempt to resize the memory block p. If this cannot be done
; in-place, a new memory block is allocated and the data at p
; is copied to the new block.
;
; If p == 0, an effective malloc is performed, except a successful
; allocation allocates from the largest block available in the heap
; to allow further quick growth via realloc().
;
; If p != 0 and size == 0, the block is reduced to zero size but
; is not freed. You must call free() to free blocks.
;
; If successful, returns a pointer to the reallocated block, which
; may be p is the block was resized in place.
;
; enter : de = void *heap
; hl = void *p (existing pointer to memory)
; bc = uint size (realloc size)
;
; exit : success
;
; hl = void *p_new
; carry reset
;
; fail on insufficient memory
;
; hl = 0
; carry set, errno = ENOMEM
;
; fail on lock acquisition
;
; hl = 0
; carry set, errno = ENOLCK
;
; uses : af, bc, de, hl
call __heap_lock_acquire
jp c, error_enolck_zc
push de ; save void *heap
call asm_heap_realloc_unlocked
jp __heap_lock_release_0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ELSE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PUBLIC asm_heap_realloc
EXTERN asm_heap_realloc_unlocked
defc asm_heap_realloc = asm_heap_realloc_unlocked
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ENDIF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
#include "base/modules/ml/include/HaasMLMnn.h"
#include "ulog/ulog.h"
#include "base/modules/core/include/HaasErrno.h"
#define LOG_TAG "HAAS_ML_MNN"
HaasMLMnn::HaasMLMnn()
{
LOGD(LOG_TAG, "entern\n");
}
HaasMLMnn::~HaasMLMnn()
{
LOGD(LOG_TAG, "entern\n");
}
int HaasMLMnn::SetInputData(const char *dataPath, const char *compareDataPath)
{
LOGD(LOG_TAG, "entern\n");
return STATUS_OK;
}
int HaasMLMnn::LoadNet(const char* modePath)
{
LOGD(LOG_TAG, "entern\n");
return STATUS_OK;
}
int HaasMLMnn::Predict()
{
LOGD(LOG_TAG, "entern\n");
return STATUS_OK;
}
int HaasMLMnn::GetPredictResponses(char* outResult, int len)
{
LOGD(LOG_TAG, "entern\n");
return STATUS_OK;
}
int HaasMLMnn::UnLoadNet()
{
LOGD(LOG_TAG, "entern\n");
return STATUS_OK;
}
|
;
; Amstrad CPC specific routines
; by Stefano Bodrato, Fall 2013
;
; int set_psg(int reg, int val);
;
; Play a sound by PSG
;
;
; $Id: set_psg.asm,v 1.3 2016-06-10 21:13:58 dom Exp $
;
SECTION code_clib
PUBLIC set_psg
PUBLIC _set_psg
EXTERN set_psg_callee
EXTERN ASMDISP_SET_PSG_CALLEE
set_psg:
_set_psg:
pop bc
pop de
pop hl
push hl
push de
push bc
jp set_psg_callee + ASMDISP_SET_PSG_CALLEE
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r15
push %r9
push %rbp
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_normal_ht+0xa02, %r9
nop
cmp %r15, %r15
mov $0x6162636465666768, %rdx
movq %rdx, %xmm2
vmovups %ymm2, (%r9)
nop
nop
nop
nop
nop
cmp %r10, %r10
lea addresses_WC_ht+0xe222, %rdi
nop
nop
nop
add $56904, %rcx
movb (%rdi), %r10b
nop
nop
nop
nop
nop
and %r10, %r10
lea addresses_WT_ht+0x1b502, %rsi
lea addresses_A_ht+0x12d02, %rdi
nop
nop
nop
nop
inc %r9
mov $102, %rcx
rep movsw
nop
nop
sub %rdi, %rdi
lea addresses_normal_ht+0x1b31a, %rsi
lea addresses_D_ht+0x162c3, %rdi
clflush (%rdi)
nop
dec %rbp
mov $76, %rcx
rep movsw
xor $9340, %rcx
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r15
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r13
push %rax
push %rdi
push %rdx
push %rsi
// Faulty Load
lea addresses_WT+0x1c102, %r13
nop
nop
sub %rdx, %rdx
movups (%r13), %xmm0
vpextrq $0, %xmm0, %rax
lea oracles, %rsi
and $0xff, %rax
shlq $12, %rax
mov (%rsi,%rax,1), %rax
pop %rsi
pop %rdx
pop %rdi
pop %rax
pop %r13
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_WT', 'size': 32, 'AVXalign': True, 'NT': False, 'congruent': 0, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_WT', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'STOR', 'dst': {'type': 'addresses_normal_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 8, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WC_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 10, 'same': True}}
{'OP': 'REPM', 'src': {'type': 'addresses_normal_ht', 'congruent': 3, 'same': False}, 'dst': {'type': 'addresses_D_ht', 'congruent': 0, 'same': False}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r12
push %r14
push %rax
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_A_ht+0xcf99, %rsi
nop
nop
nop
nop
nop
dec %rdx
movb (%rsi), %r14b
nop
sub %r12, %r12
lea addresses_WT_ht+0x2d21, %rsi
sub %r10, %r10
mov (%rsi), %ecx
and $42844, %rcx
lea addresses_A_ht+0x9121, %rsi
lea addresses_WC_ht+0x8121, %rdi
nop
cmp %rax, %rax
mov $123, %rcx
rep movsl
nop
nop
cmp %r12, %r12
lea addresses_UC_ht+0xce41, %rdx
nop
inc %rsi
mov $0x6162636465666768, %r12
movq %r12, %xmm3
vmovups %ymm3, (%rdx)
nop
nop
nop
cmp %r10, %r10
lea addresses_A_ht+0x11561, %rsi
sub $36952, %rcx
movb (%rsi), %al
nop
nop
nop
nop
add $64510, %rsi
lea addresses_D_ht+0x8ef4, %r12
nop
nop
nop
nop
and $52654, %rdi
mov (%r12), %si
nop
xor $29750, %r12
lea addresses_normal_ht+0x1c0b1, %r14
nop
xor $53910, %rax
movups (%r14), %xmm5
vpextrq $1, %xmm5, %rdx
nop
nop
nop
nop
add $19449, %rdx
lea addresses_WC_ht+0x14521, %rcx
nop
nop
and $7651, %rdx
movb (%rcx), %r12b
and %r14, %r14
lea addresses_normal_ht+0x1b21, %rdi
nop
nop
nop
and $60514, %r10
mov (%rdi), %ax
nop
nop
nop
nop
nop
sub $48469, %r10
lea addresses_D_ht+0x1121, %r10
nop
nop
add %rsi, %rsi
movb (%r10), %r14b
nop
nop
nop
nop
and %r12, %r12
lea addresses_D_ht+0x1b721, %rsi
nop
nop
nop
xor $20386, %rdx
movb (%rsi), %cl
inc %r12
lea addresses_WT_ht+0x18ce7, %rax
sub %rdi, %rdi
movb (%rax), %r10b
nop
nop
and $24170, %r10
lea addresses_UC_ht+0x5937, %r14
nop
sub $20734, %rax
mov $0x6162636465666768, %r12
movq %r12, (%r14)
nop
nop
nop
xor %rdx, %rdx
lea addresses_UC_ht+0xd321, %rax
nop
add %r12, %r12
mov (%rax), %rdi
nop
nop
nop
and %r12, %r12
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rax
pop %r14
pop %r12
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r12
push %rbp
push %rbx
push %rdi
push %rsi
// Faulty Load
lea addresses_normal+0x13921, %rbp
nop
and %rbx, %rbx
movb (%rbp), %r12b
lea oracles, %rbx
and $0xff, %r12
shlq $12, %r12
mov (%rbx,%r12,1), %r12
pop %rsi
pop %rdi
pop %rbx
pop %rbp
pop %r12
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_normal', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_normal', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'type': 'addresses_A_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WT_ht', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_WC_ht', 'congruent': 8, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 5, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_A_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 6, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WC_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 9, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 9, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 9, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WT_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC_ht', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 1, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_UC_ht', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 9, 'same': False}}
{'34': 21829}
34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34
*/
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r14
push %rax
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_A_ht+0x1b54b, %rsi
lea addresses_A_ht+0xfd4b, %rdi
nop
add $4197, %r14
mov $93, %rcx
rep movsb
nop
nop
sub %rcx, %rcx
lea addresses_D_ht+0x1640b, %rax
nop
nop
nop
nop
add %rbx, %rbx
mov $0x6162636465666768, %r11
movq %r11, (%rax)
nop
nop
xor $4061, %rax
lea addresses_WC_ht+0x1ac0b, %rsi
lea addresses_normal_ht+0x10c0b, %rdi
xor $21374, %rdx
mov $37, %rcx
rep movsq
nop
nop
nop
nop
xor $17416, %rdx
lea addresses_A_ht+0x1240b, %rsi
lea addresses_A_ht+0x688b, %rdi
nop
nop
nop
add $22897, %rdx
mov $6, %rcx
rep movsb
cmp %rax, %rax
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r14
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %rbx
push %rcx
push %rsi
// Faulty Load
lea addresses_PSE+0xb40b, %rbx
and %rsi, %rsi
movb (%rbx), %cl
lea oracles, %rbx
and $0xff, %rcx
shlq $12, %rcx
mov (%rbx,%rcx,1), %rcx
pop %rsi
pop %rcx
pop %rbx
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_PSE', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_PSE', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 5, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 6, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'size': 8, 'AVXalign': False, 'NT': True, 'congruent': 9, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 11, 'same': True}}
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 11, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 7, 'same': False}}
{'33': 21829}
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
*/
|
//
// Created by zmy on 21-1-11.
//
#include "jni.h"
#include "android/log.h"
#include "libyuv.h"
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_I420Format(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_u,
jint stride_v, jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_u = src_y + height * stride_y;
auto src_v = src_u + height / 2 * stride_u;
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_u = dst_y + height * width;
auto dst_v = dst_u + height / 2 * width / 2;
return libyuv::I420Copy(src_y, stride_y, src_u, stride_u, src_v, stride_v, dst_y, width, dst_u,
width / 2, dst_v, width / 2, width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_I420ToNV21(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_u,
jint stride_v, jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_u = src_y + height * stride_y;
auto src_v = src_u + height / 2 * stride_u;
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_uv = dst_y + height * width;
return libyuv::I420ToNV21(src_y, stride_y, src_u, stride_u, src_v, stride_v, dst_y, width,
dst_uv, width, width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_I420ToNV12(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_u,
jint stride_v, jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_u = src_y + height * stride_y;
auto src_v = src_u + height / 2 * stride_u;
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_uv = dst_y + height * width;
return libyuv::I420ToNV12(src_y, stride_y, src_u, stride_u, src_v, stride_v, dst_y, width,
dst_uv, width, width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_I420ToRGBA(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_u,
jint stride_v, jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_u = src_y + height * stride_y;
auto src_v = src_u + height / 2 * stride_u;
auto dst_rgba = (uint8_t *) env->GetDirectBufferAddress(out);
return libyuv::I420ToABGR(src_y, stride_y, src_u, stride_u, src_v, stride_v, dst_rgba,
width * 4, width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_NV12Format(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_uv,
jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_uv = src_y + height * stride_y;
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_uv = dst_y + height * width;
return libyuv::NV12Copy(src_y, stride_y, src_uv, stride_uv, dst_y, width, dst_uv, width, width,
height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_NV12ToI420(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_uv,
jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_uv = src_y + height * stride_y;
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_u = dst_y + height * width;
auto dst_v = dst_u + height * width / 4;
return libyuv::NV12ToI420(src_y, stride_y, src_uv, stride_uv, dst_y, width, dst_u, width / 2,
dst_v, width / 2, width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_NV12ToRGBA(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_uv,
jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_uv = src_y + height * stride_y;
auto dst_rgba = (uint8_t *) env->GetDirectBufferAddress(out);
return libyuv::NV12ToABGR(src_y, stride_y, src_uv, stride_uv, dst_rgba, width * 4, width,
height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_NV21Format(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_uv,
jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_uv = src_y + height * stride_y;
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_uv = dst_y + height * width;
return libyuv::NV21Copy(src_y, stride_y, src_uv, stride_uv, dst_y, width, dst_uv, width, width,
height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_NV21ToI420(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_uv,
jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_uv = src_y + height * stride_y;
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_u = dst_y + height * width;
auto dst_v = dst_u + height / 2 * width / 2;
return libyuv::NV21ToI420(src_y, stride_y, src_uv, stride_uv, dst_y, width, dst_u, width / 2,
dst_v, width / 2, width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_NV21ToRGBA(JNIEnv *env, jclass clazz, jint width, jint height,
jobject yuv, jint stride_y, jint stride_uv,
jobject out) {
auto src_y = (uint8_t *) env->GetDirectBufferAddress(yuv);
auto src_uv = src_y + height * stride_y;
auto dst_rgba = (uint8_t *) env->GetDirectBufferAddress(out);
return libyuv::NV21ToABGR(src_y, stride_y, src_uv, stride_uv, dst_rgba, width * 4, width,
height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_RGBAFormat(JNIEnv *env, jclass clazz, jint width, jint height,
jobject rgba, jint stride, jobject out) {
auto src_rgba = (uint8_t *) env->GetDirectBufferAddress(rgba);
auto dst_rgba = (uint8_t *) env->GetDirectBufferAddress(out);
return libyuv::ARGBCopy(src_rgba, stride, dst_rgba, width * 4, width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_RGBAToI420(JNIEnv *env, jclass clazz, jint width, jint height,
jobject rgba, jint stride, jobject out) {
auto src_rgba = (uint8_t *) env->GetDirectBufferAddress(rgba);
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_u = dst_y + height * width;
auto dst_v = dst_u + height / 2 * width / 2;
return libyuv::ABGRToI420(src_rgba, stride, dst_y, width, dst_u, width / 2, dst_v, width / 2,
width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_RGBAToNV12(JNIEnv *env, jclass clazz, jint width, jint height,
jobject rgba, jint stride, jobject out) {
auto src_rgba = (uint8_t *) env->GetDirectBufferAddress(rgba);
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_uv = dst_y + height * width;
return libyuv::ABGRToNV12(src_rgba, stride, dst_y, width, dst_uv, width, width, height);
}
extern "C"
JNIEXPORT jint JNICALL
Java_com_zmy_yuv_1convert_YUVConvert_RGBAToNV21(JNIEnv *env, jclass clazz, jint width, jint height,
jobject rgba, jint stride, jobject out) {
auto src_rgba = (uint8_t *) env->GetDirectBufferAddress(rgba);
auto dst_y = (uint8_t *) env->GetDirectBufferAddress(out);
auto dst_uv = dst_y + height * width;
return libyuv::ABGRToNV21(src_rgba, stride, dst_y, width, dst_uv, width, width, height);
} |
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <lv2.h>
#include "wdfJTM45Tree.hpp"
/**********************************************************************************************************************************************************/
#define PLUGIN_URI "http://aidadsp.cc/plugins/wt-rdf_lv2/JTM45"
#define TAMANHO_DO_BUFFER 1024
enum {IN, OUT_1, TRIM, GAIN, VOLUME, PLUGIN_PORT_COUNT};
static const float_t DB_SCALE = std::log(10.0)/20;
inline float_t db2a(float_t db)
{
return std::exp(DB_SCALE*db);
}
/**********************************************************************************************************************************************************/
class JTM45
{
public:
JTM45() {}
~JTM45() {}
static LV2_Handle instantiate(const LV2_Descriptor* descriptor, double samplerate, const char* bundle_path, const LV2_Feature* const* features);
static void activate(LV2_Handle instance);
static void deactivate(LV2_Handle instance);
static void connect_port(LV2_Handle instance, uint32_t port, void *data);
static void run(LV2_Handle instance, uint32_t n_samples);
static void cleanup(LV2_Handle instance);
static const void* extension_data(const char* uri);
float *in;
float *out_1;
float *trim;
float *gain;
float *volume;
float t;
float g;
float v;
private:
wdfJTM45Tree *JTM45Tree;
};
/**********************************************************************************************************************************************************/
static const LV2_Descriptor Descriptor = {
PLUGIN_URI,
JTM45::instantiate,
JTM45::connect_port,
JTM45::activate,
JTM45::run,
JTM45::deactivate,
JTM45::cleanup,
JTM45::extension_data
};
/**********************************************************************************************************************************************************/
LV2_SYMBOL_EXPORT
const LV2_Descriptor* lv2_descriptor(uint32_t index)
{
if (index == 0) return &Descriptor;
else return NULL;
}
/**********************************************************************************************************************************************************/
LV2_Handle JTM45::instantiate(const LV2_Descriptor* descriptor, double samplerate, const char* bundle_path, const LV2_Feature* const* features)
{
JTM45 *plugin = new JTM45();
plugin->JTM45Tree = new wdfJTM45Tree();
plugin->t = 0.1;
plugin->g = 0.1;
plugin->v = 0.1;
plugin->JTM45Tree->initTree();
//plugin->JTM45Tree->setSamplerate(48000);
plugin->JTM45Tree->adaptTree();
plugin->JTM45Tree->setParam(0, plugin->v); // Volume
plugin->JTM45Tree->setParam(1, plugin->g); // Gain
return (LV2_Handle)plugin;
}
/**********************************************************************************************************************************************************/
void JTM45::activate(LV2_Handle instance)
{
// TODO: include the activate function code here
}
/**********************************************************************************************************************************************************/
void JTM45::deactivate(LV2_Handle instance)
{
// TODO: include the deactivate function code here
}
/**********************************************************************************************************************************************************/
void JTM45::connect_port(LV2_Handle instance, uint32_t port, void *data)
{
JTM45 *plugin;
plugin = (JTM45 *) instance;
switch (port)
{
case IN:
plugin->in = (float*) data;
break;
case OUT_1:
plugin->out_1 = (float*) data;
break;
case TRIM:
plugin->trim = (float*)data;
case GAIN:
plugin->gain = (float*) data;
break;
case VOLUME:
plugin->volume = (float*) data;
break;
}
}
/**********************************************************************************************************************************************************/
void JTM45::run(LV2_Handle instance, uint32_t n_samples)
{
JTM45 *plugin;
plugin = (JTM45 *) instance;
if (plugin->t != *plugin->trim)
{
plugin->t = *plugin->trim;
plugin->JTM45Tree->setParam(0, db2a(plugin->t)); // Trim
}
if (plugin->g != *plugin->gain)
{
plugin->g = *plugin->gain;
plugin->JTM45Tree->setParam(1, (plugin->g)); // Amp gain
}
if (plugin->v != *plugin->volume)
{
plugin->v = *plugin->volume;
plugin->JTM45Tree->setParam(2, db2a(plugin->v)); // Volumne
}
// Oversample?
for (uint32_t i=0; i<n_samples; i++)
{
float inVoltage = plugin->in[i];
plugin->JTM45Tree->setInputValue(inVoltage);
plugin->JTM45Tree->cycleWave();
plugin->out_1[i] = (float)(plugin->JTM45Tree->getOutputValue());
}
// Downsample?
}
/**********************************************************************************************************************************************************/
void JTM45::cleanup(LV2_Handle instance)
{
delete ((JTM45 *) instance);
}
/**********************************************************************************************************************************************************/
const void* JTM45::extension_data(const char* uri)
{
return NULL;
}
|
<%
import collections
import pwnlib.abi
import pwnlib.constants
import pwnlib.shellcraft
import six
%>
<%docstring>capset(hdrp, datap) -> str
Invokes the syscall capset.
See 'man 2 capset' for more information.
Arguments:
hdrp(cap_user_header_t): hdrp
datap(cap_user_data_t): datap
Returns:
int
</%docstring>
<%page args="hdrp=0, datap=0"/>
<%
abi = pwnlib.abi.ABI.syscall()
stack = abi.stack
regs = abi.register_arguments[1:]
allregs = pwnlib.shellcraft.registers.current()
can_pushstr = []
can_pushstr_array = []
argument_names = ['hdrp', 'datap']
argument_values = [hdrp, datap]
# Load all of the arguments into their destination registers / stack slots.
register_arguments = dict()
stack_arguments = collections.OrderedDict()
string_arguments = dict()
dict_arguments = dict()
array_arguments = dict()
syscall_repr = []
for name, arg in zip(argument_names, argument_values):
if arg is not None:
syscall_repr.append('%s=%s' % (name, pwnlib.shellcraft.pretty(arg, False)))
# If the argument itself (input) is a register...
if arg in allregs:
index = argument_names.index(name)
if index < len(regs):
target = regs[index]
register_arguments[target] = arg
elif arg is not None:
stack_arguments[index] = arg
# The argument is not a register. It is a string value, and we
# are expecting a string value
elif name in can_pushstr and isinstance(arg, (six.binary_type, six.text_type)):
if isinstance(arg, six.text_type):
arg = arg.encode('utf-8')
string_arguments[name] = arg
# The argument is not a register. It is a dictionary, and we are
# expecting K:V paris.
elif name in can_pushstr_array and isinstance(arg, dict):
array_arguments[name] = ['%s=%s' % (k,v) for (k,v) in arg.items()]
# The arguent is not a register. It is a list, and we are expecting
# a list of arguments.
elif name in can_pushstr_array and isinstance(arg, (list, tuple)):
array_arguments[name] = arg
# The argument is not a register, string, dict, or list.
# It could be a constant string ('O_RDONLY') for an integer argument,
# an actual integer value, or a constant.
else:
index = argument_names.index(name)
if index < len(regs):
target = regs[index]
register_arguments[target] = arg
elif arg is not None:
stack_arguments[target] = arg
# Some syscalls have different names on various architectures.
# Determine which syscall number to use for the current architecture.
for syscall in ['SYS_capset']:
if hasattr(pwnlib.constants, syscall):
break
else:
raise Exception("Could not locate any syscalls: %r" % syscalls)
%>
/* capset(${', '.join(syscall_repr)}) */
%for name, arg in string_arguments.items():
${pwnlib.shellcraft.pushstr(arg, append_null=(b'\x00' not in arg))}
${pwnlib.shellcraft.mov(regs[argument_names.index(name)], abi.stack)}
%endfor
%for name, arg in array_arguments.items():
${pwnlib.shellcraft.pushstr_array(regs[argument_names.index(name)], arg)}
%endfor
%for name, arg in stack_arguments.items():
${pwnlib.shellcraft.push(arg)}
%endfor
${pwnlib.shellcraft.setregs(register_arguments)}
${pwnlib.shellcraft.syscall(syscall)}
|
; A120069: Denominators of partial sums of a convergent series involving scaled Catalan numbers A000108.
; 1,2,16,32,128,256,4096,8192,32768,65536,524288,1048576,4194304,8388608,268435456,536870912,2147483648,4294967296,34359738368,68719476736,274877906944,549755813888,8796093022208,17592186044416,70368744177664,140737488355328,1125899906842624,2251799813685248,9007199254740992
mov $3,$0
sub $0,$0
trn $0,3
add $3,1
mov $4,$3
mul $4,2
add $0,$4
mov $1,1
mov $2,$0
lpb $0
sub $0,1
mul $1,2
gcd $1,$2
trn $2,$1
lpe
sub $1,4
div $1,4
add $1,1
|
// ==++==
//
//
// Copyright (c) 2006 Microsoft Corporation. All rights reserved.
//
// The use and distribution terms for this software are contained in the file
// named license.txt, which can be found in the root of this distribution.
// By using this software in any fashion, you are agreeing to be bound by the
// terms of this license.
//
// You must not remove this notice, or any other, from this software.
//
//
// ==--==
#include "stdafx.h"
#include "mscoree.h"
#include "clrinternal.h"
#include "hostimpl.h"
#include "predeftlsslot.h"
#include "unsafe.h"
// to avoid to include clrhost.h in this file
#ifdef _DEBUG
extern BOOL IsInIEEInit();
extern void BeginIEEInit();
extern void EndIEEInit();
#endif
static DWORD TlsIndex = TLS_OUT_OF_INDEXES;
static PTLS_CALLBACK_FUNCTION Callbacks[MAX_PREDEFINED_TLS_SLOT];
#ifdef SELF_NO_HOST
HANDLE g_ExecutableHeapHandle = NULL;
#endif
//
// utility functions for tls functionality
//
static void **CheckThreadState(DWORD slot, BOOL force = TRUE)
{
// Treat as a runtime assertion, since the invariant spans many DLLs.
_ASSERTE(slot < MAX_PREDEFINED_TLS_SLOT);
// Ensure we have a TLS Index
if (TlsIndex == TLS_OUT_OF_INDEXES)
{
DWORD tmp = UnsafeTlsAlloc();
if (InterlockedCompareExchange((LONG*)&TlsIndex, tmp, TLS_OUT_OF_INDEXES) != (LONG) TLS_OUT_OF_INDEXES)
{
// We lost the race
UnsafeTlsFree(tmp);
}
}
_ASSERTE(TlsIndex != TLS_OUT_OF_INDEXES);
void **pTlsData = (void **)TlsGetValue(TlsIndex);
if (pTlsData == 0 && force) {
// !!! Contract uses our TLS support. Contract may be used before our host support is set up.
// !!! To better support contract, we call into OS for memory allocation.
pTlsData = (void**) ::HeapAlloc(GetProcessHeap(),0,MAX_PREDEFINED_TLS_SLOT*sizeof(void*));
if (pTlsData == NULL)
{
if (slot == TlsIdx_ClrDebugState || slot == TlsIdx_StackProbe)
{
return NULL;
}
RaiseException(STATUS_NO_MEMORY, 0, 0, NULL);
}
for (int i=0; i<MAX_PREDEFINED_TLS_SLOT; i++)
pTlsData[i] = 0;
UnsafeTlsSetValue(TlsIndex, pTlsData);
}
return pTlsData;
} // static void **CheckThreadState()
// This function should only be called during process detatch for
// mscoree.dll.
VOID STDMETHODCALLTYPE TLS_FreeMasterSlotIndex()
{
if (TlsIndex != TLS_OUT_OF_INDEXES)
if (UnsafeTlsFree(TlsIndex))
TlsIndex = TLS_OUT_OF_INDEXES;
}// TLS_FreeMasterSlotIndex
HRESULT STDMETHODCALLTYPE UtilExecutionEngine::QueryInterface(REFIID id, void **pInterface)
{
if (!pInterface)
return E_POINTER;
*pInterface = NULL;
if (id == IID_IExecutionEngine)
*pInterface = (IExecutionEngine *)this;
else if (id == IID_IEEMemoryManager)
*pInterface = (IEEMemoryManager *)this;
else if (id == IID_IUnknown)
*pInterface = (IUnknown *)(IExecutionEngine *)this;
else
return E_NOINTERFACE;
AddRef();
return S_OK;
} // HRESULT STDMETHODCALLTYPE UtilExecutionEngine::QueryInterface()
//
// lifetime of this object is that of the app it lives in so no point in AddRef/Release
//
ULONG STDMETHODCALLTYPE UtilExecutionEngine::AddRef()
{
return 1;
}
ULONG STDMETHODCALLTYPE UtilExecutionEngine::Release()
{
return 1;
}
VOID STDMETHODCALLTYPE UtilExecutionEngine::TLS_AssociateCallback(DWORD slot, PTLS_CALLBACK_FUNCTION callback)
{
CheckThreadState(slot);
// They can toggle between a callback and no callback. But anything else looks like
// confusion on their part.
//
// (TlsIdx_ClrDebugState associates its callback from utilcode.lib - which can be replicated. But
// all the callbacks are equally good.)
_ASSERTE(slot == TlsIdx_ClrDebugState || Callbacks[slot] == 0 || Callbacks[slot] == callback || callback == 0);
Callbacks[slot] = callback;
}
DWORD STDMETHODCALLTYPE UtilExecutionEngine::TLS_GetMasterSlotIndex()
{
CheckThreadState(0, FALSE);
return TlsIndex;
}
LPVOID STDMETHODCALLTYPE UtilExecutionEngine::TLS_GetValue(DWORD slot)
{
void **pTlsData = CheckThreadState(slot, FALSE);
if (pTlsData)
return pTlsData[slot];
else
return NULL;
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::TLS_CheckValue(DWORD slot, LPVOID * pValue)
{
void **pTlsData = CheckThreadState(slot, FALSE);
if (pTlsData)
{
*pValue = pTlsData[slot];
return TRUE;
}
return FALSE;
}
VOID STDMETHODCALLTYPE UtilExecutionEngine::TLS_SetValue(DWORD slot, LPVOID pData)
{
void **pTlsData = CheckThreadState(slot);
if (pTlsData) // Yes, CheckThreadState(slot, TRUE) can return NULL now.
{
pTlsData[slot] = pData;
}
}
VOID STDMETHODCALLTYPE UtilExecutionEngine::TLS_ThreadDetaching()
{
void **pTlsData = CheckThreadState(0, FALSE);
if (pTlsData)
{
for (int i=0; i<MAX_PREDEFINED_TLS_SLOT; i++)
{
// If we have some data and a callback, issue it.
if (Callbacks[i] != 0 && pTlsData[i] != 0)
(*Callbacks[i])(pTlsData[i]);
}
::HeapFree (GetProcessHeap(),0,pTlsData);
}
}
CRITSEC_COOKIE STDMETHODCALLTYPE UtilExecutionEngine::CreateLock(LPCSTR szTag, LPCSTR level, CrstFlags flags)
{
CRITICAL_SECTION *cs = (CRITICAL_SECTION*)malloc(sizeof(CRITICAL_SECTION));
UnsafeInitializeCriticalSection(cs);
return (CRITSEC_COOKIE)cs;
}
void STDMETHODCALLTYPE UtilExecutionEngine::DestroyLock(CRITSEC_COOKIE lock)
{
_ASSERTE(lock);
UnsafeDeleteCriticalSection((CRITICAL_SECTION*)lock);
free(lock);
}
void STDMETHODCALLTYPE UtilExecutionEngine::AcquireLock(CRITSEC_COOKIE lock)
{
_ASSERTE(lock);
UnsafeEnterCriticalSection((CRITICAL_SECTION*)lock);
}
void STDMETHODCALLTYPE UtilExecutionEngine::ReleaseLock(CRITSEC_COOKIE lock)
{
_ASSERTE(lock);
UnsafeLeaveCriticalSection((CRITICAL_SECTION*)lock);
}
EVENT_COOKIE STDMETHODCALLTYPE UtilExecutionEngine::CreateAutoEvent(BOOL bInitialState)
{
HANDLE handle = UnsafeCreateEvent(NULL, FALSE, bInitialState, NULL);
_ASSERTE(handle);
return (EVENT_COOKIE)handle;
}
EVENT_COOKIE STDMETHODCALLTYPE UtilExecutionEngine::CreateManualEvent(BOOL bInitialState)
{
HANDLE handle = UnsafeCreateEvent(NULL, TRUE, bInitialState, NULL);
_ASSERTE(handle);
return (EVENT_COOKIE)handle;
}
void STDMETHODCALLTYPE UtilExecutionEngine::CloseEvent(EVENT_COOKIE event)
{
_ASSERTE(event);
CloseHandle((HANDLE)event);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrSetEvent(EVENT_COOKIE event)
{
_ASSERTE(event);
return UnsafeSetEvent((HANDLE)event);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrResetEvent(EVENT_COOKIE event)
{
_ASSERTE(event);
return UnsafeResetEvent((HANDLE)event);
}
DWORD STDMETHODCALLTYPE UtilExecutionEngine::WaitForEvent(EVENT_COOKIE event, DWORD dwMilliseconds, BOOL bAlertable)
{
_ASSERTE(event);
return WaitForSingleObjectEx((HANDLE)event, dwMilliseconds, bAlertable);
}
DWORD STDMETHODCALLTYPE UtilExecutionEngine::WaitForSingleObject(HANDLE handle, DWORD dwMilliseconds)
{
_ASSERTE(handle);
return WaitForSingleObject(handle, dwMilliseconds);
}
SEMAPHORE_COOKIE STDMETHODCALLTYPE UtilExecutionEngine::ClrCreateSemaphore(DWORD dwInitial, DWORD dwMax)
{
HANDLE handle = UnsafeCreateSemaphore(NULL, (LONG)dwInitial, (LONG)dwMax, NULL);
_ASSERTE(handle);
return (SEMAPHORE_COOKIE)handle;
}
void STDMETHODCALLTYPE UtilExecutionEngine::ClrCloseSemaphore(SEMAPHORE_COOKIE semaphore)
{
_ASSERTE(semaphore);
CloseHandle((HANDLE)semaphore);
}
DWORD STDMETHODCALLTYPE UtilExecutionEngine::ClrWaitForSemaphore(SEMAPHORE_COOKIE semaphore, DWORD dwMilliseconds, BOOL bAlertable)
{
_ASSERTE(semaphore);
return WaitForSingleObjectEx((HANDLE)semaphore, dwMilliseconds, bAlertable);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrReleaseSemaphore(SEMAPHORE_COOKIE semaphore, LONG lReleaseCount, LONG *lpPreviousCount)
{
_ASSERTE(semaphore);
return UnsafeReleaseSemaphore((HANDLE)semaphore, lReleaseCount, lpPreviousCount);
}
MUTEX_COOKIE STDMETHODCALLTYPE UtilExecutionEngine::ClrCreateMutex(LPSECURITY_ATTRIBUTES lpMutexAttributes,
BOOL bInitialOwner,
LPCTSTR lpName)
{
return (MUTEX_COOKIE)WszCreateMutex(lpMutexAttributes,bInitialOwner,lpName);
}
void STDMETHODCALLTYPE UtilExecutionEngine::ClrCloseMutex(MUTEX_COOKIE mutex)
{
_ASSERTE(mutex);
CloseHandle((HANDLE)mutex);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrReleaseMutex(MUTEX_COOKIE mutex)
{
_ASSERTE(mutex);
return ReleaseMutex((HANDLE)mutex);
}
DWORD STDMETHODCALLTYPE UtilExecutionEngine::ClrWaitForMutex(MUTEX_COOKIE mutex,
DWORD dwMilliseconds,
BOOL bAlertable)
{
_ASSERTE(mutex);
return WaitForSingleObjectEx ((HANDLE)mutex, dwMilliseconds, bAlertable);
}
DWORD STDMETHODCALLTYPE UtilExecutionEngine::ClrSleepEx(DWORD dwMilliseconds, BOOL bAlertable)
{
return SleepEx (dwMilliseconds, bAlertable);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrAllocationDisallowed()
{
return FALSE;
}
LPVOID STDMETHODCALLTYPE UtilExecutionEngine::ClrVirtualAlloc(LPVOID lpAddress, SIZE_T dwSize, DWORD flAllocationType, DWORD flProtect)
{
#ifdef _DEBUG
if (0 && !IsInIEEInit())
_ASSERTE (!ClrAllocationDisallowed());
#endif
return VirtualAlloc(lpAddress, dwSize, flAllocationType, flProtect);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrVirtualFree(LPVOID lpAddress, SIZE_T dwSize, DWORD dwFreeType)
{
return VirtualFree(lpAddress, dwSize, dwFreeType);
}
SIZE_T STDMETHODCALLTYPE UtilExecutionEngine::ClrVirtualQuery(LPCVOID lpAddress, PMEMORY_BASIC_INFORMATION lpBuffer, SIZE_T dwLength)
{
return VirtualQuery(lpAddress, lpBuffer, dwLength);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrVirtualProtect(LPVOID lpAddress, SIZE_T dwSize, DWORD flNewProtect, PDWORD lpflOldProtect)
{
return VirtualProtect(lpAddress, dwSize, flNewProtect, lpflOldProtect);
}
HANDLE STDMETHODCALLTYPE UtilExecutionEngine::ClrGetProcessHeap()
{
return GetProcessHeap();
}
HANDLE STDMETHODCALLTYPE UtilExecutionEngine::ClrGetProcessExecutableHeap()
{
return NULL;
}
HANDLE STDMETHODCALLTYPE UtilExecutionEngine::ClrHeapCreate(DWORD flOptions, SIZE_T dwInitialSize, SIZE_T dwMaximumSize)
{
return NULL;
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrHeapDestroy(HANDLE hHeap)
{
return TRUE;
}
LPVOID STDMETHODCALLTYPE UtilExecutionEngine::ClrHeapAlloc(HANDLE hHeap, DWORD dwFlags, SIZE_T dwBytes)
{
#ifdef _DEBUG
if (0 && !IsInIEEInit())
_ASSERTE (!ClrAllocationDisallowed());
#endif
return HeapAlloc(hHeap, dwFlags, dwBytes);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrHeapFree(HANDLE hHeap, DWORD dwFlags, LPVOID lpMem)
{
return HeapFree(hHeap, dwFlags, lpMem);
}
BOOL STDMETHODCALLTYPE UtilExecutionEngine::ClrHeapValidate(HANDLE hHeap, DWORD dwFlags, LPCVOID lpMem)
{
return TRUE;
}
//------------------------------------------------------------------------------
// Helper function to get an exception from outside the exception. In
// the CLR, it may be from the Thread object. Non-CLR users have no thread object,
// and it will do nothing.
void UtilExecutionEngine::GetLastThrownObjectExceptionFromThread(void **ppvException)
{
// Declare class so we can declare Exception**
class Exception;
// Cast to our real type.
Exception **ppException = reinterpret_cast<Exception**>(ppvException);
*ppException = NULL;
} // HRESULT UtilExecutionEngine::GetLastThrownObjectExceptionFromThread()
|
; A113532: a(n) = 1 + 2*n + 3*n^2 + 4*n^3 + 5*n^4 + 6*n^5 + 7*n^6.
; 1,28,769,7108,36409,131836,380713,937924,2054353,4110364,7654321,13446148,22505929,36167548,56137369,84557956,124076833,177920284,249972193,344857924,468033241,625878268,825796489,1076318788,1387212529,1769595676,2236055953,2800775044,3479657833,4290466684,5252960761,6389040388,7722896449,9281164828,11093085889,13190668996,15608862073,18385726204,21562615273,25184360644,29299460881,33960276508,39223229809,45149009668,51802781449,59254401916,67578639193,76855397764,87169948513,98613163804,111281757601,125278530628,140712620569,157699757308,176362523209,196830618436,219241131313,243738813724,270476361553,299614700164,331323274921,365780346748,403173292729,443698911748,487563735169,534984342556,586187682433,641411398084,700904158393,764925993724,833748636841,907655868868,986943870289,1071921576988,1162911041329,1260247798276,1364281236553,1475374974844,1593907243033,1720271268484,1854875667361,1998144840988,2150519377249,2312456457028,2484430265689,2666932409596,2860472337673,3065577768004,3282795119473,3512689948444,3755847390481,4012872607108,4284391237609,4571049855868,4873516432249,5192480800516,5528655129793,5882774401564,6255596891713,6647904657604,7060504030201,7494226111228,7949927275369,8428489677508,8930821765009,9457858795036,10010563356913,10589925899524,11196965263753,11832729219964,12498295010521,13194769897348,13923291714529,14685029425948,15481183687969,16312987417156,17181706363033,18088639685884,19035120539593,20022516659524,21052230955441,22125702109468,23244405179089,24409852205188,25623592825129,26887214890876,28202345092153,29570649584644,30993834623233,32473647200284,34011875688961,35610350491588,37270944693049,38995574719228,40786201000489,42644828640196,44573508088273,46574335819804,48649455018673,50801056266244,53031378235081,55342708387708,57737383680409,60217791272068,62786369238049,65445607289116,68198047495393,71046285015364,73992968829913,77040802481404,80192544817801,83451010741828,86819071965169,90299657767708,93895755761809,97610412661636,101446735057513,105407890195324,109497106760953,113717675669764,118072950861121,122566350097948,127201355771329,131981515710148,136910443995769,141991821781756,147229398118633,152626990783684,158188487115793,163917844855324,169819092989041,175896332600068,182153737722889,188595556203388,195226110563929,202049798873476,209071095622753,216294552604444,223724799798433,231366546262084,239224581025561,247303773992188,255609076843849,264145523951428,272918233290289,281932407360796,291193334113873,300706387881604,310477030312873,320510811314044,330813369994681,341390435618308,352247828558209,363391461258268,374827339198849,386561561867716,398600323735993,410949915239164,423616723763113,436607234635204,449928032120401,463585800422428,477587324689969,491939492027908,506649292513609,521723820218236,537170274233113,552995959701124,569208288853153,585814782049564,602823068826721,620240888948548,638076093463129,656336645764348,675030622658569,694166215436356,713751730949233,733795592691484,754306341886993,775292638581124,796763262737641,818727115340668,841193219501689,864170721571588,887668892257729,911697127746076,936264950828353,961382012034244,987058090768633,1013303096453884,1040127069677161,1067540183342788,1095552743829649,1124175192153628,1153418105135089,1183292196571396,1213808318414473,1244977461953404,1276810759002073,1309319483091844,1342515050669281,1376409022298908,1411013103871009,1446339147814468,1482399154314649,1519205272536316,1556769801851593,1595105193072964,1634224049691313,1674139129119004
mov $3,$0
mul $0,2
mov $1,$0
lpb $0,1
add $1,$0
sub $0,1
sub $1,1
lpe
add $1,1
mov $2,1
mov $4,$3
lpb $2,1
add $1,$4
sub $2,1
lpe
mov $6,$3
lpb $6,1
add $5,$4
sub $6,1
lpe
mov $2,1
mov $4,$5
lpb $2,1
add $1,$4
sub $2,1
lpe
mov $5,0
mov $6,$3
lpb $6,1
add $5,$4
sub $6,1
lpe
mov $2,4
mov $4,$5
lpb $2,1
add $1,$4
sub $2,1
lpe
mov $5,0
mov $6,$3
lpb $6,1
add $5,$4
sub $6,1
lpe
mov $2,5
mov $4,$5
lpb $2,1
add $1,$4
sub $2,1
lpe
mov $5,0
mov $6,$3
lpb $6,1
add $5,$4
sub $6,1
lpe
mov $2,6
mov $4,$5
lpb $2,1
add $1,$4
sub $2,1
lpe
mov $5,0
mov $6,$3
lpb $6,1
add $5,$4
sub $6,1
lpe
mov $2,7
mov $4,$5
lpb $2,1
add $1,$4
sub $2,1
lpe
|
#include <errno.h>
#include <node.h>
#include <nan.h>
#include "./i2c-dev.h"
#include "./writequick.h"
#include "./util.h"
static __s32 WriteQuick(int fd, __u8 bit) {
return i2c_smbus_write_quick(fd, bit);
}
class WriteQuickWorker : public I2cAsyncWorker {
public:
WriteQuickWorker(Nan::Callback *callback, int fd, __u8 bit)
: I2cAsyncWorker(callback), fd(fd), bit(bit) {}
~WriteQuickWorker() {}
void Execute() {
__s32 ret = WriteQuick(fd, bit);
if (ret == -1) {
SetErrorNo(errno);
SetErrorSyscall("writeQuick");
}
}
void HandleOKCallback() {
Nan::HandleScope scope;
v8::Local<v8::Value> argv[] = {
Nan::Null()
};
callback->Call(1, argv, async_resource);
}
private:
int fd;
__u8 bit;
};
NAN_METHOD(WriteQuickAsync) {
if (info.Length() < 3 || !info[0]->IsInt32() || !info[1]->IsInt32() || !info[2]->IsFunction()) {
return Nan::ThrowError(Nan::ErrnoException(EINVAL, "writeQuick",
"incorrect arguments passed to writeQuick(int fd, int bit, function cb)"));
}
int fd = info[0]->Int32Value();
__u8 bit = info[1]->Int32Value();
Nan::Callback *callback = new Nan::Callback(info[2].As<v8::Function>());
Nan::AsyncQueueWorker(new WriteQuickWorker(callback, fd, bit));
}
NAN_METHOD(WriteQuickSync) {
if (info.Length() < 2 || !info[0]->IsInt32() || !info[1]->IsInt32()) {
return Nan::ThrowError(Nan::ErrnoException(EINVAL, "writeQuickSync",
"incorrect arguments passed to writeQuickSync(int fd, int bit)"));
}
int fd = info[0]->Int32Value();
__u8 bit = info[1]->Int32Value();
__s32 ret = WriteQuick(fd, bit);
if (ret == -1) {
return Nan::ThrowError(Nan::ErrnoException(errno, "writeQuickSync", ""));
}
}
|
#include "HTTPDictionarySource.h"
#include <DataStreams/IBlockOutputStream.h>
#include <DataStreams/OwningBlockInputStream.h>
#include <IO/ConnectionTimeouts.h>
#include <IO/ReadWriteBufferFromHTTP.h>
#include <IO/WriteBufferFromOStream.h>
#include <IO/WriteBufferFromString.h>
#include <IO/WriteHelpers.h>
#include <Interpreters/Context.h>
#include <Poco/Net/HTTPRequest.h>
#include <common/logger_useful.h>
#include "DictionarySourceFactory.h"
#include "DictionarySourceHelpers.h"
#include "DictionaryStructure.h"
#include "registerDictionaries.h"
namespace DB
{
static const UInt64 max_block_size = 8192;
HTTPDictionarySource::HTTPDictionarySource(
const DictionaryStructure & dict_struct_,
const Poco::Util::AbstractConfiguration & config,
const std::string & config_prefix,
Block & sample_block_,
const Context & context_,
bool check_config)
: log(&Logger::get("HTTPDictionarySource"))
, update_time{std::chrono::system_clock::from_time_t(0)}
, dict_struct{dict_struct_}
, url{config.getString(config_prefix + ".url", "")}
, update_field{config.getString(config_prefix + ".update_field", "")}
, format{config.getString(config_prefix + ".format")}
, sample_block{sample_block_}
, context(context_)
, timeouts(ConnectionTimeouts::getHTTPTimeouts(context))
{
if (check_config)
context.getRemoteHostFilter().checkURL(Poco::URI(url));
const auto & credentials_prefix = config_prefix + ".credentials";
if (config.has(credentials_prefix))
{
credentials.setUsername(config.getString(credentials_prefix + ".user", ""));
credentials.setPassword(config.getString(credentials_prefix + ".password", ""));
}
const auto & headers_prefix = config_prefix + ".headers";
if (config.has(headers_prefix))
{
Poco::Util::AbstractConfiguration::Keys config_keys;
config.keys(headers_prefix, config_keys);
header_entries.reserve(config_keys.size());
for (const auto & key : config_keys)
{
const auto header_key = config.getString(headers_prefix + "." + key + ".name", "");
const auto header_value = config.getString(headers_prefix + "." + key + ".value", "");
header_entries.emplace_back(std::make_tuple(header_key, header_value));
}
}
}
HTTPDictionarySource::HTTPDictionarySource(const HTTPDictionarySource & other)
: log(&Logger::get("HTTPDictionarySource"))
, update_time{other.update_time}
, dict_struct{other.dict_struct}
, url{other.url}
, header_entries{other.header_entries}
, update_field{other.update_field}
, format{other.format}
, sample_block{other.sample_block}
, context(other.context)
, timeouts(ConnectionTimeouts::getHTTPTimeouts(context))
{
credentials.setUsername(other.credentials.getUsername());
credentials.setPassword(other.credentials.getPassword());
}
void HTTPDictionarySource::getUpdateFieldAndDate(Poco::URI & uri)
{
if (update_time != std::chrono::system_clock::from_time_t(0))
{
auto tmp_time = update_time;
update_time = std::chrono::system_clock::now();
time_t hr_time = std::chrono::system_clock::to_time_t(tmp_time) - 1;
WriteBufferFromOwnString out;
writeDateTimeText(hr_time, out);
uri.addQueryParameter(update_field, out.str());
}
else
{
update_time = std::chrono::system_clock::now();
}
}
BlockInputStreamPtr HTTPDictionarySource::loadAll()
{
LOG_TRACE(log, "loadAll " + toString());
Poco::URI uri(url);
auto in_ptr = std::make_unique<ReadWriteBufferFromHTTP>(
uri, Poco::Net::HTTPRequest::HTTP_GET, ReadWriteBufferFromHTTP::OutStreamCallback(), timeouts,
0, credentials, DBMS_DEFAULT_BUFFER_SIZE, header_entries);
auto input_stream = context.getInputFormat(format, *in_ptr, sample_block, max_block_size);
return std::make_shared<OwningBlockInputStream<ReadWriteBufferFromHTTP>>(input_stream, std::move(in_ptr));
}
BlockInputStreamPtr HTTPDictionarySource::loadUpdatedAll()
{
Poco::URI uri(url);
getUpdateFieldAndDate(uri);
LOG_TRACE(log, "loadUpdatedAll " + uri.toString());
auto in_ptr = std::make_unique<ReadWriteBufferFromHTTP>(
uri, Poco::Net::HTTPRequest::HTTP_GET, ReadWriteBufferFromHTTP::OutStreamCallback(), timeouts,
0, credentials, DBMS_DEFAULT_BUFFER_SIZE, header_entries);
auto input_stream = context.getInputFormat(format, *in_ptr, sample_block, max_block_size);
return std::make_shared<OwningBlockInputStream<ReadWriteBufferFromHTTP>>(input_stream, std::move(in_ptr));
}
BlockInputStreamPtr HTTPDictionarySource::loadIds(const std::vector<UInt64> & ids)
{
LOG_TRACE(log, "loadIds " << toString() << " size = " << ids.size());
ReadWriteBufferFromHTTP::OutStreamCallback out_stream_callback = [&](std::ostream & ostr)
{
WriteBufferFromOStream out_buffer(ostr);
auto output_stream = context.getOutputFormat(format, out_buffer, sample_block);
formatIDs(output_stream, ids);
};
Poco::URI uri(url);
auto in_ptr = std::make_unique<ReadWriteBufferFromHTTP>(
uri, Poco::Net::HTTPRequest::HTTP_POST, out_stream_callback, timeouts,
0, credentials, DBMS_DEFAULT_BUFFER_SIZE, header_entries);
auto input_stream = context.getInputFormat(format, *in_ptr, sample_block, max_block_size);
return std::make_shared<OwningBlockInputStream<ReadWriteBufferFromHTTP>>(input_stream, std::move(in_ptr));
}
BlockInputStreamPtr HTTPDictionarySource::loadKeys(const Columns & key_columns, const std::vector<size_t> & requested_rows)
{
LOG_TRACE(log, "loadKeys " << toString() << " size = " << requested_rows.size());
ReadWriteBufferFromHTTP::OutStreamCallback out_stream_callback = [&](std::ostream & ostr)
{
WriteBufferFromOStream out_buffer(ostr);
auto output_stream = context.getOutputFormat(format, out_buffer, sample_block);
formatKeys(dict_struct, output_stream, key_columns, requested_rows);
};
Poco::URI uri(url);
auto in_ptr = std::make_unique<ReadWriteBufferFromHTTP>(
uri, Poco::Net::HTTPRequest::HTTP_POST, out_stream_callback, timeouts,
0, credentials, DBMS_DEFAULT_BUFFER_SIZE, header_entries);
auto input_stream = context.getInputFormat(format, *in_ptr, sample_block, max_block_size);
return std::make_shared<OwningBlockInputStream<ReadWriteBufferFromHTTP>>(input_stream, std::move(in_ptr));
}
bool HTTPDictionarySource::isModified() const
{
return true;
}
bool HTTPDictionarySource::supportsSelectiveLoad() const
{
return true;
}
bool HTTPDictionarySource::hasUpdateField() const
{
return !update_field.empty();
}
DictionarySourcePtr HTTPDictionarySource::clone() const
{
return std::make_unique<HTTPDictionarySource>(*this);
}
std::string HTTPDictionarySource::toString() const
{
Poco::URI uri(url);
return uri.toString();
}
void registerDictionarySourceHTTP(DictionarySourceFactory & factory)
{
auto createTableSource = [=](const DictionaryStructure & dict_struct,
const Poco::Util::AbstractConfiguration & config,
const std::string & config_prefix,
Block & sample_block,
const Context & context,
bool check_config) -> DictionarySourcePtr
{
if (dict_struct.has_expressions)
throw Exception{"Dictionary source of type `http` does not support attribute expressions", ErrorCodes::LOGICAL_ERROR};
return std::make_unique<HTTPDictionarySource>(
dict_struct, config, config_prefix + ".http",
sample_block, context, check_config);
};
factory.registerSource("http", createTableSource);
}
}
|
#include "stdafx.h"
#include "ReleaseMutex.h"
CReleaseMutex::~CReleaseMutex()
{
if (m_hObject)
{
ReleaseMutex(m_hObject);
}
}
|
;
;==================================================================================================
; SC130 STANDARD CONFIGURATION
;==================================================================================================
;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#DEFINE PLATFORM_NAME "SC130"
;
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
;
#include "cfg_scz180.asm"
;
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
;
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
;
LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED)
;
DIAGENABLE .SET FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
;
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
;
AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
;
FDENABLE .SET TRUE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
;
IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
;
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
;;
;; Copyright (c) 2017-2021, Intel Corporation
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;; * Redistributions of source code must retain the above copyright notice,
;; this list of conditions and the following disclaimer.
;; * Redistributions in binary form must reproduce the above copyright
;; notice, this list of conditions and the following disclaimer in the
;; documentation and/or other materials provided with the distribution.
;; * Neither the name of Intel Corporation nor the names of its contributors
;; may be used to endorse or promote products derived from this software
;; without specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;
;; In System V AMD64 ABI
;; callee saves: RBX, RBP, R12-R15
;; Windows x64 ABI
;; callee saves: RBX, RBP, RDI, RSI, R12-R15
;;
;; Clobbers ZMM0-31
%include "include/os.asm"
%include "include/imb_job.asm"
%include "include/mb_mgr_datastruct.asm"
%include "include/reg_sizes.asm"
%include "include/cet.inc"
extern sha512_x8_avx512
section .data
default rel
align 16
dupw: ;ddq 0x01000100010001000100010001000100
dq 0x0100010001000100, 0x0100010001000100
align 16
byteswap: ;ddq 0x08090a0b0c0d0e0f0001020304050607
dq 0x0001020304050607, 0x08090a0b0c0d0e0f
align 16
len_masks:
;ddq 0x0000000000000000000000000000FFFF
dq 0x000000000000FFFF, 0x0000000000000000
;ddq 0x000000000000000000000000FFFF0000
dq 0x00000000FFFF0000, 0x0000000000000000
;ddq 0x00000000000000000000FFFF00000000
dq 0x0000FFFF00000000, 0x0000000000000000
;ddq 0x0000000000000000FFFF000000000000
dq 0xFFFF000000000000, 0x0000000000000000
;ddq 0x000000000000FFFF0000000000000000
dq 0x0000000000000000, 0x000000000000FFFF
;ddq 0x00000000FFFF00000000000000000000
dq 0x0000000000000000, 0x00000000FFFF0000
;ddq 0x0000FFFF000000000000000000000000
dq 0x0000000000000000, 0x0000FFFF00000000
;ddq 0xFFFF0000000000000000000000000000
dq 0x0000000000000000, 0xFFFF000000000000
lane_1: dq 1
lane_2: dq 2
lane_3: dq 3
lane_4: dq 4
lane_5: dq 5
lane_6: dq 6
lane_7: dq 7
section .text
%ifdef LINUX
%define arg1 rdi
%define arg2 rsi
%else
%define arg1 rcx
%define arg2 rdx
%endif
%define state arg1
%define job arg2
%define len2 arg2
; idx needs to be in rbp
%define idx rbp
%define unused_lanes rbx
%define lane_data rbx
%define tmp2 rbx
%define job_rax rax
%define size_offset rax
%define tmp rax
%define start_offset rax
%define extra_blocks arg2
%define p arg2
%define tmp4 r8
%define tmp5 r9
%define tmp6 r10
struc STACK
_gpr_save: resq 7 ; rbx, rbp, r12-r15, rdi (windows)
_rsp_save: resq 1
endstruc
%define APPEND(a,b) a %+ b
%ifndef SHA384
; JOB* flush_job_hmac_sha_384_avx512(MB_MGR_HMAC_SHA_512_OOO *state)
; arg 1 : state
%define SHA_X_DIGEST_SIZE 512
MKGLOBAL(flush_job_hmac_sha_512_avx512,function,internal)
align 64
flush_job_hmac_sha_512_avx512:
endbranch64
%else
; JOB* flush_job_hmac_sha_512_avx512(MB_MGR_HMAC_SHA_512_OOO *state)
; arg 1 : state
%define SHA_X_DIGEST_SIZE 384
MKGLOBAL(flush_job_hmac_sha_384_avx512,function,internal)
align 64
flush_job_hmac_sha_384_avx512:
endbranch64
%endif
mov rax, rsp
sub rsp, STACK_size
and rsp, -32
mov [rsp + _gpr_save + 8*0], rbx
mov [rsp + _gpr_save + 8*1], rbp
mov [rsp + _gpr_save + 8*2], r12
mov [rsp + _gpr_save + 8*3], r13
mov [rsp + _gpr_save + 8*4], r14
mov [rsp + _gpr_save + 8*5], r15
%ifndef LINUX
mov [rsp + _gpr_save + 8*6], rdi
%endif
mov [rsp + _rsp_save], rax ; original SP
mov unused_lanes, [state + _unused_lanes_sha512]
bt unused_lanes, 32+3
jc return_null
; find a lane with a non-null job
xor idx, idx
%assign I 1
%rep 7
cmp qword [state + _ldata_sha512 + I * _SHA512_LANE_DATA_size + _job_in_lane_sha512], 0
cmovne idx, [rel APPEND(lane_, I)]
%assign I (I+1)
%endrep
copy_lane_data:
; copy good lane (idx) to empty lanes
vmovdqa xmm0, [state + _lens_sha512]
mov tmp, [state + _args_sha512 + _data_ptr_sha512 + PTR_SZ*idx]
%assign I 0
%rep 8
cmp qword [state + _ldata_sha512 + I * _SHA512_LANE_DATA_size + _job_in_lane_sha512], 0
jne APPEND(skip_,I)
mov [state + _args_sha512 + _data_ptr_sha512 + PTR_SZ*I], tmp
vpor xmm0, xmm0, [rel len_masks + 16*I]
APPEND(skip_,I):
%assign I (I+1)
%endrep
vmovdqa [state + _lens_sha512], xmm0
vphminposuw xmm1, xmm0
vpextrw DWORD(len2), xmm1, 0 ; min value
vpextrw DWORD(idx), xmm1, 1 ; min index (0...7)
cmp len2, 0
je len_is_0
vpshufb xmm1, [rel dupw] ; duplicate words across all 8 lanes
vpsubw xmm0, xmm0, xmm1
vmovdqa [state + _lens_sha512], xmm0
; "state" and "args" are the same address, arg1
; len is arg2
call sha512_x8_avx512
; state and idx are intact
len_is_0:
; process completed job "idx"
imul lane_data, idx, _SHA512_LANE_DATA_size
lea lane_data, [state + _ldata_sha512 + lane_data]
mov DWORD(extra_blocks), [lane_data + _extra_blocks_sha512]
cmp extra_blocks, 0
jne proc_extra_blocks
cmp dword [lane_data + _outer_done_sha512], 0
jne end_loop
proc_outer:
mov dword [lane_data + _outer_done_sha512], 1
mov DWORD(size_offset), [lane_data + _size_offset_sha512]
mov qword [lane_data + _extra_block_sha512 + size_offset], 0
mov word [state + _lens_sha512 + 2*idx], 1
lea tmp, [lane_data + _outer_block_sha512]
mov job, [lane_data + _job_in_lane_sha512]
mov [state + _args_data_ptr_sha512 + PTR_SZ*idx], tmp
; move digest into data location
%assign I 0
%rep (SHA_X_DIGEST_SIZE / (8*16))
vmovq xmm0, [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 2*I*SHA512_DIGEST_ROW_SIZE]
vpinsrq xmm0, [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + (2*I + 1)*SHA512_DIGEST_ROW_SIZE], 1
vpshufb xmm0, [rel byteswap]
vmovdqa [lane_data + _outer_block_sha512 + I*2*SHA512_DIGEST_WORD_SIZE], xmm0
%assign I (I+1)
%endrep
; move the opad key into digest
mov tmp, [job + _auth_key_xor_opad]
%assign I 0
%rep 4
vmovdqu xmm0, [tmp + I * 16]
vmovq [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + (2*I + 0)*SHA512_DIGEST_ROW_SIZE], xmm0
vpextrq [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + (2*I + 1)*SHA512_DIGEST_ROW_SIZE], xmm0, 1
%assign I (I+1)
%endrep
jmp copy_lane_data
align 32
proc_extra_blocks:
mov DWORD(start_offset), [lane_data + _start_offset_sha512]
mov [state + _lens_sha512 + 2*idx], WORD(extra_blocks)
lea tmp, [lane_data + _extra_block_sha512 + start_offset]
mov [state + _args_data_ptr_sha512 + PTR_SZ*idx], tmp
mov dword [lane_data + _extra_blocks_sha512], 0
jmp copy_lane_data
return_null:
xor job_rax, job_rax
jmp return
align 32
end_loop:
mov job_rax, [lane_data + _job_in_lane_sha512]
mov qword [lane_data + _job_in_lane_sha512], 0
or dword [job_rax + _status], IMB_STATUS_COMPLETED_AUTH
mov unused_lanes, [state + _unused_lanes_sha512]
shl unused_lanes, 4
or unused_lanes, idx
mov [state + _unused_lanes_sha512], unused_lanes
mov p, [job_rax + _auth_tag_output]
%if (SHA_X_DIGEST_SIZE != 384)
cmp qword [job_rax + _auth_tag_output_len_in_bytes], 32
jne copy_full_digest
%else
cmp qword [job_rax + _auth_tag_output_len_in_bytes], 24
jne copy_full_digest
%endif
;; copy 32 bytes for SHA512 / 24 bytes for SHA384
mov QWORD(tmp2), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 0*SHA512_DIGEST_ROW_SIZE]
mov QWORD(tmp4), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 1*SHA512_DIGEST_ROW_SIZE]
mov QWORD(tmp6), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 2*SHA512_DIGEST_ROW_SIZE]
%if (SHA_X_DIGEST_SIZE != 384)
mov QWORD(tmp5), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 3*SHA512_DIGEST_ROW_SIZE]
%endif
bswap QWORD(tmp2)
bswap QWORD(tmp4)
bswap QWORD(tmp6)
%if (SHA_X_DIGEST_SIZE != 384)
bswap QWORD(tmp5)
%endif
mov [p + 0*8], QWORD(tmp2)
mov [p + 1*8], QWORD(tmp4)
mov [p + 2*8], QWORD(tmp6)
%if (SHA_X_DIGEST_SIZE != 384)
mov [p + 3*8], QWORD(tmp5)
%endif
jmp clear_ret
copy_full_digest:
;; copy 64 bytes for SHA512 / 48 bytes for SHA384
mov QWORD(tmp2), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 0*SHA512_DIGEST_ROW_SIZE]
mov QWORD(tmp4), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 1*SHA512_DIGEST_ROW_SIZE]
mov QWORD(tmp6), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 2*SHA512_DIGEST_ROW_SIZE]
mov QWORD(tmp5), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 3*SHA512_DIGEST_ROW_SIZE]
bswap QWORD(tmp2)
bswap QWORD(tmp4)
bswap QWORD(tmp6)
bswap QWORD(tmp5)
mov [p + 0*8], QWORD(tmp2)
mov [p + 1*8], QWORD(tmp4)
mov [p + 2*8], QWORD(tmp6)
mov [p + 3*8], QWORD(tmp5)
mov QWORD(tmp2), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 4*SHA512_DIGEST_ROW_SIZE]
mov QWORD(tmp4), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 5*SHA512_DIGEST_ROW_SIZE]
%if (SHA_X_DIGEST_SIZE != 384)
mov QWORD(tmp6), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 6*SHA512_DIGEST_ROW_SIZE]
mov QWORD(tmp5), [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*idx + 7*SHA512_DIGEST_ROW_SIZE]
%endif
bswap QWORD(tmp2)
bswap QWORD(tmp4)
%if (SHA_X_DIGEST_SIZE != 384)
bswap QWORD(tmp6)
bswap QWORD(tmp5)
%endif
mov [p + 4*8], QWORD(tmp2)
mov [p + 5*8], QWORD(tmp4)
%if (SHA_X_DIGEST_SIZE != 384)
mov [p + 6*8], QWORD(tmp6)
mov [p + 7*8], QWORD(tmp5)
%endif
clear_ret:
%ifdef SAFE_DATA
vpxorq zmm0, zmm0
;; Clear digest (48B/64B), outer_block (48B/64B) and extra_block (128B) of returned job
%assign I 0
%rep 8
cmp qword [state + _ldata_sha512 + (I*_SHA512_LANE_DATA_size) + _job_in_lane_sha512], 0
jne APPEND(skip_clear_,I)
;; Clear digest (48 bytes for SHA-384, 64 bytes for SHA-512 bytes)
%assign J 0
%rep 6
mov qword [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*I + J*SHA512_DIGEST_ROW_SIZE], 0
%assign J (J+1)
%endrep
%if (SHA_X_DIGEST_SIZE != 384)
mov qword [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*I + 6*SHA512_DIGEST_ROW_SIZE], 0
mov qword [state + _args_digest_sha512 + SHA512_DIGEST_WORD_SIZE*I + 7*SHA512_DIGEST_ROW_SIZE], 0
%endif
lea lane_data, [state + _ldata_sha512 + (I*_SHA512_LANE_DATA_size)]
;; Clear first 128 bytes of extra_block
vmovdqu64 [lane_data + _extra_block], zmm0
vmovdqu64 [lane_data + _extra_block + 64], zmm0
;; Clear first 48 bytes (SHA-384) or 64 bytes (SHA-512) of outer_block
%if (SHA_X_DIGEST_SIZE == 384)
vmovdqu64 [lane_data + _outer_block], ymm0
vmovdqa64 [lane_data + _outer_block + 32], xmm0
%else
vmovdqu64 [lane_data + _outer_block], zmm0
%endif
APPEND(skip_clear_,I):
%assign I (I+1)
%endrep
%endif ;; SAFE_DATA
return:
vzeroupper
mov rbx, [rsp + _gpr_save + 8*0]
mov rbp, [rsp + _gpr_save + 8*1]
mov r12, [rsp + _gpr_save + 8*2]
mov r13, [rsp + _gpr_save + 8*3]
mov r14, [rsp + _gpr_save + 8*4]
mov r15, [rsp + _gpr_save + 8*5]
%ifndef LINUX
mov rdi, [rsp + _gpr_save + 8*6]
%endif
mov rsp, [rsp + _rsp_save] ; original SP
ret
%ifdef LINUX
section .note.GNU-stack noalloc noexec nowrite progbits
%endif
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r8
push %r9
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_normal_ht+0x182e9, %rsi
lea addresses_D_ht+0xee59, %rdi
clflush (%rsi)
nop
nop
nop
nop
nop
xor %r10, %r10
mov $9, %rcx
rep movsw
nop
nop
lfence
lea addresses_A_ht+0xce59, %r10
nop
nop
cmp %rdx, %rdx
mov $0x6162636465666768, %rsi
movq %rsi, %xmm1
movups %xmm1, (%r10)
nop
nop
nop
nop
nop
sub $32312, %rdi
lea addresses_UC_ht+0xc82b, %rsi
clflush (%rsi)
nop
nop
cmp %r8, %r8
movups (%rsi), %xmm4
vpextrq $0, %xmm4, %rcx
nop
nop
nop
nop
nop
add %rdx, %rdx
lea addresses_WT_ht+0x1b961, %rdi
nop
add %rbx, %rbx
movb (%rdi), %r10b
nop
nop
nop
dec %rdx
lea addresses_WC_ht+0x163c1, %rsi
lea addresses_A_ht+0x8779, %rdi
nop
nop
and $38788, %r9
mov $39, %rcx
rep movsb
inc %rdi
lea addresses_WC_ht+0xe869, %r10
nop
nop
add $15396, %rdi
movw $0x6162, (%r10)
sub %rdi, %rdi
lea addresses_normal_ht+0x1d829, %rdi
nop
add %rcx, %rcx
mov (%rdi), %r10d
nop
nop
sub %rdi, %rdi
lea addresses_D_ht+0x6c59, %rcx
nop
nop
nop
xor $9559, %rsi
movw $0x6162, (%rcx)
nop
nop
nop
sub %rdx, %rdx
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %r9
pop %r8
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r13
push %r8
push %rcx
push %rdi
push %rdx
// Store
lea addresses_normal+0x809f, %rdi
nop
nop
nop
nop
lfence
movl $0x51525354, (%rdi)
inc %rdi
// Store
mov $0x24595500000006d9, %rcx
sub $41849, %r11
mov $0x5152535455565758, %rdi
movq %rdi, (%rcx)
nop
nop
sub $14218, %r8
// Faulty Load
lea addresses_normal+0x11459, %rcx
nop
nop
nop
nop
nop
add %r8, %r8
mov (%rcx), %r11
lea oracles, %r13
and $0xff, %r11
shlq $12, %r11
mov (%r13,%r11,1), %r11
pop %rdx
pop %rdi
pop %rcx
pop %r8
pop %r13
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_normal', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 4, 'NT': False, 'type': 'addresses_normal', 'same': False, 'AVXalign': False, 'congruent': 0}}
{'OP': 'STOR', 'dst': {'size': 8, 'NT': False, 'type': 'addresses_NC', 'same': False, 'AVXalign': True, 'congruent': 7}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'size': 8, 'NT': False, 'type': 'addresses_normal', 'same': True, 'AVXalign': False, 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'same': False, 'type': 'addresses_normal_ht', 'congruent': 4}, 'dst': {'same': False, 'type': 'addresses_D_ht', 'congruent': 9}}
{'OP': 'STOR', 'dst': {'size': 16, 'NT': False, 'type': 'addresses_A_ht', 'same': False, 'AVXalign': False, 'congruent': 9}}
{'OP': 'LOAD', 'src': {'size': 16, 'NT': False, 'type': 'addresses_UC_ht', 'same': True, 'AVXalign': False, 'congruent': 1}}
{'OP': 'LOAD', 'src': {'size': 1, 'NT': False, 'type': 'addresses_WT_ht', 'same': False, 'AVXalign': False, 'congruent': 3}}
{'OP': 'REPM', 'src': {'same': True, 'type': 'addresses_WC_ht', 'congruent': 2}, 'dst': {'same': False, 'type': 'addresses_A_ht', 'congruent': 5}}
{'OP': 'STOR', 'dst': {'size': 2, 'NT': False, 'type': 'addresses_WC_ht', 'same': False, 'AVXalign': False, 'congruent': 3}}
{'OP': 'LOAD', 'src': {'size': 4, 'NT': False, 'type': 'addresses_normal_ht', 'same': False, 'AVXalign': False, 'congruent': 3}}
{'OP': 'STOR', 'dst': {'size': 2, 'NT': False, 'type': 'addresses_D_ht', 'same': False, 'AVXalign': False, 'congruent': 10}}
{'34': 992}
34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34
*/
|
; A103569: Sum of the (primes > 5 modulo 11).
; 7,7,9,15,23,24,31,40,44,52,62,65,74,78,84,85,90,97,99,105,106,115,117,121,129,139,142,148,158,163,170,176,184,187,196,198,206,209,214,218,224,234,235,237,240,247,256,258,266,276,285,289,299,304,311,313,319
mov $2,$0
mov $3,$0
add $3,1
lpb $3
mov $0,$2
sub $3,1
sub $0,$3
add $0,3
seq $0,40 ; The prime numbers.
mod $0,11
add $1,$0
lpe
mov $0,$1
|
; A332192: a(n) = 10^(2n+1) - 1 - 7*10^n.
; 2,929,99299,9992999,999929999,99999299999,9999992999999,999999929999999,99999999299999999,9999999992999999999,999999999929999999999,99999999999299999999999,9999999999992999999999999,999999999999929999999999999,99999999999999299999999999999,9999999999999992999999999999999
add $0,1
mov $1,10
pow $1,$0
sub $1,3
bin $1,2
sub $1,15
div $1,5
add $1,1
mov $0,$1
|
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.30.9200.16384
//
//
///
// Buffer Definitions:
//
// cbuffer cbInit
// {
//
// float4 g_vMaterialColor; // Offset: 0 Size: 16 [unused]
// float4 g_vAmbientColor; // Offset: 16 Size: 16 [unused]
// float4 g_vSpecularColor; // Offset: 32 Size: 16 [unused]
// float4 g_vScreenSize; // Offset: 48 Size: 16
// float4 g_vFlags; // Offset: 64 Size: 16 [unused]
//
// }
//
// cbuffer cbUpdate
// {
//
// float4x4 g_mWorld; // Offset: 0 Size: 64 [unused]
// float4x4 g_mViewProjection; // Offset: 64 Size: 64
// float4x4 g_mWorldViewProjection; // Offset: 128 Size: 64 [unused]
// float4 g_vTessellationFactor; // Offset: 192 Size: 16
// float4 g_vDisplacementScaleBias; // Offset: 208 Size: 16 [unused]
// float4 g_vLightPosition; // Offset: 224 Size: 16 [unused]
// float4 g_vEyePosition; // Offset: 240 Size: 16
//
// }
//
// cbuffer cbDamage
// {
//
// float4 g_vNormal[50]; // Offset: 0 Size: 800
// float4 g_vBinormal[50]; // Offset: 800 Size: 800 [unused]
// float4 g_vTangent[50]; // Offset: 1600 Size: 800 [unused]
// float4 g_vDecalPositionSize[50]; // Offset: 2400 Size: 800
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cbInit cbuffer NA NA 0 1
// cbUpdate cbuffer NA NA 1 1
// cbDamage cbuffer NA NA 2 1
//
//
//
// Patch Constant signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_TessFactor 0 x 0 TRIEDGE float x
// SV_TessFactor 1 x 1 TRIEDGE float x
// SV_TessFactor 2 x 2 TRIEDGE float x
// SV_InsideTessFactor 0 x 3 TRIINT float x
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xyz
// TEXCOORD 0 xy 1 NONE float xy
// NORMAL 0 xyz 2 NONE float xyz
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// WORLDPOS 0 xyz 0 NONE float xyz
// TEXCOORD 0 xy 1 NONE float xy
// NORMAL 0 xyz 2 NONE float xyz
//
// Tessellation Domain # of control points
// -------------------- --------------------
// Triangle 3
//
// Tessellation Output Primitive Partitioning Type
// ------------------------------ ------------------
// Clockwise Triangles Odd Fractional
//
hs_5_0
hs_decls
dcl_input_control_point_count 3
dcl_output_control_point_count 3
dcl_tessellator_domain domain_tri
dcl_tessellator_partitioning partitioning_fractional_odd
dcl_tessellator_output_primitive output_triangle_cw
dcl_hs_max_tessfactor l(64.000000)
dcl_globalFlags refactoringAllowed
dcl_constantbuffer cb0[4], immediateIndexed
dcl_constantbuffer cb1[16], immediateIndexed
dcl_constantbuffer cb2[200], dynamicIndexed
hs_fork_phase
dcl_input vicp[3][0].xyz
dcl_output_siv o0.x, finalTriUeq0EdgeTessFactor
dcl_output_siv o1.x, finalTriVeq0EdgeTessFactor
dcl_output_siv o2.x, finalTriWeq0EdgeTessFactor
dcl_output_siv o3.x, finalTriInsideTessFactor
dcl_temps 13
add r0.xyz, -vicp[1][0].xyzx, vicp[2][0].xyzx
add r1.xyz, -vicp[1][0].xyzx, vicp[0][0].xyzx
ne r0.w, l(0.000000, 0.000000, 0.000000, 0.000000), cb1[12].z
if_nz r0.w
mul r2.xyz, r0.yzxy, r1.zxyz
mad r2.xyz, r1.yzxy, r0.zxyz, -r2.xyzx
dp3 r0.w, r2.xyzx, r2.xyzx
rsq r0.w, r0.w
mul r2.xyz, r0.wwww, r2.xyzx
add r3.xyz, -cb1[15].xyzx, vicp[1][0].xyzx
dp3 r0.w, r3.xyzx, r3.xyzx
rsq r0.w, r0.w
mul r3.xyz, r0.wwww, r3.xyzx
dp3 r0.w, r3.xyzx, r2.xyzx
lt r0.w, l(-0.250000), r0.w
if_z r0.w
mov o0.x, l(0)
mov o1.x, l(0)
mov o2.x, l(0)
mov o3.x, l(0)
ret
endif
endif
ne r2.xy, l(0.000000, 0.000000, 0.000000, 0.000000), cb1[12].ywyy
mov r3.xyz, vicp[1][0].xyzx
mov r3.w, l(1.000000)
dp4 r4.x, r3.xyzw, cb1[4].xyzw
dp4 r4.y, r3.xyzw, cb1[5].xyzw
dp4 r0.w, r3.xyzw, cb1[7].xyzw
div r2.zw, r4.xxxy, r0.wwww
add r2.zw, r2.zzzw, l(0.000000, 0.000000, 1.000000, 1.000000)
mov r3.x, cb0[3].x
mov r3.y, l(0.500000)
mul r2.zw, r2.zzzw, r3.xxxy
mul r3.x, r2.z, l(0.500000)
mul r3.y, r2.w, -cb0[3].y
mov r4.xyz, vicp[2][0].xyzx
mov r4.w, l(1.000000)
dp4 r5.x, r4.xyzw, cb1[4].xyzw
dp4 r5.y, r4.xyzw, cb1[5].xyzw
dp4 r0.w, r4.xyzw, cb1[7].xyzw
div r2.zw, r5.xxxy, r0.wwww
add r2.zw, r2.zzzw, l(0.000000, 0.000000, 1.000000, 1.000000)
mul r4.x, r2.z, cb0[3].x
mul r4.y, r2.w, -cb0[3].y
mov r5.xyz, vicp[0][0].xyzx
mov r5.w, l(1.000000)
dp4 r6.x, r5.xyzw, cb1[4].xyzw
dp4 r6.y, r5.xyzw, cb1[5].xyzw
dp4 r0.w, r5.xyzw, cb1[7].xyzw
div r2.zw, r6.xxxy, r0.wwww
add r2.zw, r2.zzzw, l(0.000000, 0.000000, 1.000000, 1.000000)
mul r5.x, r2.z, cb0[3].x
mul r5.y, r2.w, -cb0[3].y
mul r2.zw, r5.xxxy, l(0.000000, 0.000000, 0.500000, 0.500000)
mad r3.zw, -r4.xxxy, l(0.000000, 0.000000, 0.500000, 0.500000), r3.xxxy
dp2 r0.w, r3.zwzz, r3.zwzz
sqrt r0.w, r0.w
mul r0.w, r0.w, l(0.062500)
div_sat r0.w, r0.w, cb1[12].x
mul r6.x, r0.w, cb1[12].x
mad r2.zw, r4.xxxy, l(0.000000, 0.000000, 0.500000, 0.500000), -r2.zzzw
dp2 r0.w, r2.zwzz, r2.zwzz
sqrt r0.w, r0.w
mul r0.w, r0.w, l(0.062500)
div_sat r0.w, r0.w, cb1[12].x
mul r6.y, r0.w, cb1[12].x
mad r2.zw, r5.xxxy, l(0.000000, 0.000000, 0.500000, 0.500000), -r3.xxxy
dp2 r0.w, r2.zwzz, r2.zwzz
sqrt r0.w, r0.w
mul r0.w, r0.w, l(0.062500)
div_sat r0.w, r0.w, cb1[12].x
mul r6.z, r0.w, cb1[12].x
max r0.w, r6.z, r6.y
max r6.w, r0.w, r6.x
movc r3.xyzw, r2.xxxx, r6.xyzw, cb1[12].xxxx
if_z r2.y
min r2.xyzw, r3.xyzw, l(64.000000, 64.000000, 64.000000, 64.000000)
mov o0.x, r2.x
mov o1.x, r2.y
mov o2.x, r2.z
mov o3.x, r2.w
ret
endif
dp3 r0.w, r0.xyzx, r0.xyzx
add r2.xyz, -vicp[2][0].xyzx, vicp[0][0].xyzx
dp3 r1.w, r2.xyzx, r2.xyzx
dp3 r2.w, r1.xyzx, r1.xyzx
dp3 r4.x, r0.xyzx, r1.xyzx
mul r4.y, r4.x, r4.x
mad r4.y, r0.w, r2.w, -r4.y
div r4.y, l(1.000000, 1.000000, 1.000000, 1.000000), r4.y
mul r5.xyz, r0.zxyz, r1.yzxy
mad r5.xyz, r0.yzxy, r1.zxyz, -r5.xyzx
dp3 r4.z, r5.xyzx, r5.xyzx
rsq r4.z, r4.z
mul r5.xyz, r4.zzzz, r5.xyzx
mov r6.xz, r3.xxyx
mov r6.yw, l(0,-1,0,-1)
mov r7.x, r3.z
mov r7.y, l(-1)
mov r8.xyzw, l(1.000000,1.000000,1.000000,1.000000)
mov r3.y, l(0)
loop
ige r3.z, r3.y, l(50)
breakc_nz r3.z
eq r9.xyz, l(0.000000, 0.000000, 0.000000, 0.000000), cb2[r3.y + 0].xyzx
and r3.z, r9.y, r9.x
and r3.z, r9.z, r3.z
if_nz r3.z
break
endif
mul r3.z, cb2[r3.y + 150].w, cb2[r3.y + 150].w
add r9.xyz, cb2[r3.y + 150].xyzx, -vicp[1][0].xyzx
dp3 r4.z, r9.xyzx, r9.xyzx
add r10.xyz, cb2[r3.y + 150].xyzx, -vicp[2][0].xyzx
dp3 r4.w, r10.xyzx, r10.xyzx
add r11.xyz, cb2[r3.y + 150].xyzx, -vicp[0][0].xyzx
dp3 r5.w, r11.xyzx, r11.xyzx
ge r7.zw, r3.zzzz, r4.zzzw
or r9.w, r7.w, r7.z
dp3 r10.w, r9.xyzx, r0.xyzx
div r11.w, r10.w, r0.w
mul r12.xyz, r0.xyzx, r11.wwww
dp3 r11.w, r12.xyzx, r12.xyzx
add r4.z, r4.z, -r11.w
ge r4.z, r3.z, r4.z
dp3 r12.x, r12.xyzx, r0.xyzx
ge r12.x, r12.x, l(0.000000)
and r4.z, r4.z, r12.x
ge r11.w, r0.w, r11.w
and r12.y, r4.z, r11.w
movc r12.x, r12.y, r3.x, r8.x
movc r12.xy, r9.wwww, r6.xyxx, r12.xyxx
ge r4.z, r3.z, r5.w
or r7.w, r4.z, r7.w
dp3 r9.w, r10.xyzx, r2.xyzx
div r9.w, r9.w, r1.w
mul r10.xyz, r2.xyzx, r9.wwww
dp3 r9.w, r10.xyzx, r10.xyzx
add r4.w, r4.w, -r9.w
ge r4.w, r3.z, r4.w
dp3 r10.x, r10.xyzx, r2.xyzx
ge r10.x, r10.x, l(0.000000)
and r4.w, r4.w, r10.x
ge r9.w, r1.w, r9.w
and r4.w, r4.w, r9.w
or r4.zw, r4.zzzw, r7.zzzw
mov r12.z, r8.y
movc r8.xy, r4.wwww, r6.wzww, r12.yzyy
dp3 r4.w, r11.xyzx, -r1.xyzx
div r4.w, r4.w, r2.w
mul r10.xyz, -r1.xyzx, r4.wwww
dp3 r4.w, r10.xyzx, r10.xyzx
add r5.w, -r4.w, r5.w
ge r3.z, r3.z, r5.w
dp3 r5.w, r10.xyzx, -r1.xyzx
ge r5.w, r5.w, l(0.000000)
and r3.z, r3.z, r5.w
ge r4.w, r2.w, r4.w
and r3.z, r3.z, r4.w
or r3.z, r4.z, r3.z
movc r8.xz, r3.zzzz, r7.yyxy, r8.xxzx
dp3 r3.z, r5.xyzx, r9.xyzx
ge r3.z, cb2[r3.y + 150].w, |r3.z|
dp3 r4.z, r1.xyzx, r9.xyzx
mul r4.w, r4.z, r4.x
mad r4.w, r2.w, r10.w, -r4.w
mul r5.w, r4.y, r4.w
mul r7.z, r4.x, r10.w
mad r4.z, r0.w, r4.z, -r7.z
mul r4.z, r4.y, r4.z
lt r5.w, l(0.000000), r5.w
lt r7.z, l(0.000000), r4.z
and r5.w, r5.w, r7.z
mad r4.z, r4.w, r4.y, r4.z
lt r4.z, r4.z, l(1.000000)
and r4.z, r4.z, r5.w
or r4.z, r8.x, r4.z
movc r4.z, r4.z, r3.w, r8.w
movc r8.w, r3.z, r4.z, r8.w
mov r8.x, r12.x
iadd r3.y, r3.y, l(1)
endloop
min r0.xyzw, r8.xyzw, l(64.000000, 64.000000, 64.000000, 64.000000)
mov o0.x, r0.x
mov o1.x, r0.y
mov o2.x, r0.z
mov o3.x, r0.w
ret
// Approximately 190 instruction slots used
|
#include <pch.hpp>
#include "Input.hpp"
#include <GLFW/glfw3.h>
#include <Application/Application.hpp>
NS_ENIGMA_BEGIN
bool Input::IsKeyPressed(KeyCode keycode) noexcept
{
GLFWwindow* window = Application::GetInstance()->GetWindow()->GetGLFWwindow();
i32 state = glfwGetKey(window, static_cast<i32>(keycode));
return state == GLFW_PRESS || state == GLFW_REPEAT;
}
bool Input::IsMouseButtonPressed(MouseCode button) noexcept
{
GLFWwindow* window = Application::GetInstance()->GetWindow()->GetGLFWwindow();
i32 state = glfwGetMouseButton(window, static_cast<i32>(button));
return state == GLFW_PRESS;
}
std::pair<f32, f32> Input::GetMousePosition() noexcept
{
GLFWwindow* window = Application::GetInstance()->GetWindow()->GetGLFWwindow();
f64 xPos{0.0}, yPos{0.0};
glfwGetCursorPos(window, &xPos, &yPos);
return std::make_pair( static_cast<f32>(xPos), static_cast<f32>(yPos) );
}
f32 Input::GetMouseX() noexcept
{
const auto [x, y] = GetMousePosition();
return x;
}
f32 Input::GetMouseY() noexcept
{
const auto [x, y] = GetMousePosition();
return y;
}
NS_ENIGMA_END
|
.data
String_message: .asciiz "Input string is: "
Notice_message: .asciiz "Number of different characters is: "
Message: .space 100 # Buffer 100 byte
.text
main:
li $v0, 8
la $a0, Message
li $a1, 100
syscall
addi $sp, $sp, -100 # Load appear_character to $sp
la $s0, Message # Load Message to $s0
add $t0, $0, $0 # init $t0 = i = 0
add $t1, $0, $0 # init $t1 = count = 0
add $t2, $0, $0 # init $t2 = j = 0
jal check
nop
print: li $v0, 59
la $a0, String_message
la $a1, Message
syscall
add $a1, $t1, $0
li $v0, 56
la $a0, Notice_message
syscall
quit: li $v0, 10
syscall
#-------------------------------------------------------------------------------------
# @brief Check character in input string Message, reomove space_character
#-------------------------------------------------------------------------------------
check: add $t3, $s0, $t0 # $t3 = Address of Message[i]
lb $t4, 0($t3) # Load word $t4 = Message[i]
beq $t4, 10, check_done # If $t4 = 10 ==> check done
nop
beq $t0, 24, check_done # If appear_char = 24, 'a' - 'z' appeared ==> check done
nop
add $t2, $0, $0 # init $t2 = j = 0
addi $t0, $t0, 1 # i = i+1
add $t5, $0, $sp
check_appear:
slti $t6, $t4, 'a' # If message[i] < 'a' ==> check next character
bne $t6, $0, check
slti $t6, $t4, 128 # If Message[i] > 128 ('z') ==> check next character
beq $t6, $0, check
slt $t7, $t1, $t2 # if j > count, add current character to appear_character
bne $t7, $0, add_char
nop
lw $t7, 0($t5) # load value of appear_character[j]
beq $t7, $t4, check # if Massage[i] = appear_character[j]
nop
addi $t2, $t2, 1 # j = j+1
addi $t5, $t5, 4
j check_appear
nop
add_char: sw $t4, 0($t5) # Message[i] is new character
# add to appear_character[count]
addi $t1, $t1, 1 # count = count+1
j check
nop
check_done:
jr $ra
|
; find out hardware map
HWN I
:query_loop
SUB I, 1
HWQ I
IFE B, 0x7349
IFE A, 0xf615
SET [monitor_n], I
IFN I, 0
SET PC, query_loop
; set up monitor
SET A, 0
SET B, 0x8000
HWI [monitor_n]
SET A, 0x001f
SET B, 0x0020
:main_loop
SET [0x8000+A], 0xff00
ADD A, B
IFG 0x180, A
SET PC, check1
SET B, 0xFFE0
ADD A, B
:check1
IFG 0x1000, A
SET PC, check2
SET B, 0x0020
ADD A, B
ADD A, B
:check2
JSR scroll
SET PC, main_loop
; scrolls video memory to the left by one
:scroll
SET PUSH, A
SET PUSH, B
SET A, 0x8000
:scroll_loop
SET [A], [1+A]
; check for last column (make it 0)
SET B, A
ADD B, 1
AND B, 0x1f
IFE B, 0
SET [A], 0
ADD A, 1
IFG 0x8180, A
SET PC, scroll_loop
SET B, POP
SET A, POP
SET PC, POP
:monitor_n
DAT 0
|
; void *zx_cyx2aaddr_callee(uchar row, uchar col)
SECTION code_arch
PUBLIC _zx_cyx2aaddr_callee, l0_zx_cyx2aaddr_callee
_zx_cyx2aaddr_callee:
pop hl
pop de
ex (sp),hl
l0_zx_cyx2aaddr_callee:
ld h,e
INCLUDE "arch/zx/display/z80/asm_zx_cyx2aaddr.asm"
|
; A129196: a(n) = denominator(3*(3+(-1)^n)/(n+1)^3).
; 1,4,9,32,125,36,343,256,243,500,1331,288,2197,1372,1125,2048,4913,972,6859,4000,3087,5324,12167,2304,15625,8788,6561,10976,24389,4500,29791,16384,11979,19652,42875,7776,50653,27436,19773,32000,68921,12348,79507,42592
add $0,1
pow $0,3
mov $1,$0
gcd $1,6
div $0,$1
|
orig 0x100
//
// A program to add some numbers
//
//
// print a string. Address of string is in A register
//
ps0: 0
prints: sta ps0 // store pointer, for indirect addressing
ps1: lda i ps0
sza rss
ret // return on zero (end of string)
iota 4,0 // print character
isz ps0
jmp ps1
// print contents of A as a decimal number
// uses a (input), b (10), c (digit)
parray: 0
0
0
0
0
0
pradd: parray
prptr: parray
m10: 10
czero: '0'
printn: ldb pradd
stb prptr // set up pointer
ldb m10 // base 10 printing
pr2: mod c,a,b // get low-order digit (c = a mod 10)
addc czero // convert to character code
stc i prptr // save digit
isz prptr // increment pointer
div a,a,b // divide a/10 -> a
sza
jmp pr2 // non-zero means print char array
pr3: lda prptr
dca // --prptr;
sta prptr
ldc i prptr // load the digit
iotc 4,0 // print the digit
suba pradd
sma sza
jmp pr3
ret
//
// read a decimal number from input and return the value
// if there is a number, skip; if EOF, do not skip
// uses a (running total), b (10), c (input char), d (comparison)
//
rra: 0
readn: pop rra // get return address
cla // a holds running sum
ldb m10 // b holds 10
rn1: iotc 3,0 // read character
smc rss
jmp i rra // EOF causes exit with A=0
subc czero // c - '0'
smc rss
jmp rn1 // bad input, skip and keep reading
sub d,c,b // (c - '0') < 10?
smd
jmp rn1 // still bad input,
// we have skipped all the non-digit input before the number
// start reading the number
cla
rn2: mul a,a,b // a = a*10
add a,a,c // a = a*10 + c - '0'
iotc 3,0 // read character
subc czero // c - '0'
smc rss
jmp rn3 // bad input, done with number
sub d,c,b // (c - '0') < 10?
smd rss
jmp rn2 // loop back for another character
rn3: isz rra
jmp i rra
///////////////////////////////////
// Main program.
//
// 1. write a prompt.
// 2. read numbers until EOF (0xFFFF)
// 3. add all numbers together
// 4. print numbers and sum
//
stsize: 40
sum: 0
loopctr: 0
ninputs: 0
nptr: 0
naddr: addr_of_numbers
main: cla dca // a = 0xFFFF
and sp,a,a // move a to sp
suba stsize
and spl,a,a // move a minus stack size to spl
lda prompt
call prints // print the prompt
cla // set up count and array for numbers
sta ninputs
lda naddr
sta nptr
iloop: call readn // read a number
jmp endinput // if EOF
sta I nptr // save the number
isz nptr
isz ninputs // increase count of numbers
jmp iloop
// EOF on input, now add numbers
endinput:
lda ninputs
cma ina
sta loopctr // define -n as loop count
lda naddr
sta nptr // rest pointer to numbers
cld cll // d holds running sum
oloop: lda I nptr // print number
call printn
lda I nptr // add number
add d,d,a
smd snl rss // check for overflow
jmp overflow
isz nptr
isz loopctr
jmp oloop1
jmp oloop2
oloop1: lda separator1 // +
call prints
jmp oloop
// print sum
oloop2: lda separator2 // =
call prints
and a,d,d // print sum in d
call printn
oloop3:
lda separator3 // newline
call prints
hlt
overflow:
lda separator2
call prints
lda overmsg
call prints
jmp oloop3
overmsg: overs
overs: '*'
'*'
'*'
' '
'O'
'v'
'e'
'r'
'f'
'l'
'o'
'w'
' '
'*'
'*'
'*'
0
///////////////////////////////////
prompt: prompts
prompts: 'P'
'l'
'e'
'a'
's'
'e'
' '
't'
'y'
'p'
'e'
' '
'n'
'u'
'm'
'b'
'e'
'r'
's'
' '
't'
'o'
' '
'a'
'd'
'd'
':'
' '
0
separator1: str1
str1: ' '
'+'
' '
0
separator2: str2
str2: ' '
'='
' '
0
separator3: str3
str3: 10
0
// numbers continue as long as memory allows
addr_of_numbers:
end main
|
; A285976: Positions of 0 in A285975; complement of A285977.
; Submitted by Christian Krause
; 1,4,6,9,11,14,16,18,21,24,26,29,31,34,37,39,41,44,46,49,51,54,56,58,61,64,66,68,71,73,76,78,81,84,86,89,91,94,96,98,101,104,106,109,111,114,117,119,121,124,126,129,131,134,137,139,142,144,147,149,151,154,157,159,161,164,166,169,171,174,176,178,181,184,186,189,191,194,197,199,201,204,206,209,211,214,216,218,221,224,226,228,231,233,236,238,241,244,246,249
mov $9,$0
mov $11,$0
add $11,1
lpb $11
mov $0,$9
mov $6,0
sub $11,1
sub $0,$11
mov $5,$0
mov $7,2
lpb $7
mov $0,$5
mov $1,0
sub $7,1
add $0,$7
mov $2,$0
sub $0,1
pow $2,2
lpb $2
mov $3,$1
seq $3,127254 ; (0,1) sequence whose zero positions are indexed by twice the odious numbers given by A091855.
sub $0,$3
add $1,2
mov $4,$0
max $4,0
cmp $4,$0
mul $2,$4
sub $2,1
lpe
mov $0,$1
mov $8,$7
mul $8,$1
add $6,$8
lpe
min $5,1
mul $5,$0
mov $0,$6
sub $0,$5
div $0,2
add $0,1
add $10,$0
lpe
mov $0,$10
|
#include "BaseComponent.h"
BaseComponent::BaseComponent(PScene owner, bool isDisabled)
{
_owner = owner;
_isDisabled = isDisabled;
}
//============================================={NOTE}===============================================//
// These two are not mistake, base on the decision table:
//
// C\P | Enable | Disable | Result
// -------+--------+---------+-----------
// Enable | X | | OnEnabled
// Disable| X | | Nothing
// Enable | | X | OnDisabled
// Disable| | X | Nothing
//
// You can see that only when an object is enabled it would care about what the parent do,
// that make sense but will cause error because the OnEnabled doesn't know whether it is
// it own event or other so it check by using.
// if (IsDisabled())
// So to make thing work we have to set isDisabled first on Enable and after in Disable.
// Got that future me?
void BaseComponent::Disable()
{
if (_isDisabled)
return;
OnDisabled();
_isDisabled = true;
}
void BaseComponent::Enable()
{
if (!_isDisabled)
return;
_isDisabled = false;
OnEnabled();
}
//============================================={NOTE}===============================================//
bool BaseComponent::IsDeleted() const
{
return _isDeleted;
}
bool BaseComponent::IsDisabled() const
{
return _isDisabled;
}
bool BaseComponent::CallDestroy()
{
if (_owner && !IsDeleted())
{
_owner->AddToTrashBin(_this.lock());
return true;
}
return false;
}
void BaseComponent::Destroy()
{
if (!_isDisabled)
this->Disable();
// Call on end when the object is destroyed
this->OnEnd();
delete this;
}
void BaseComponent::SetName(const std::string& name)
{
_name = name;
}
std::string BaseComponent::GetName() const
{
return _name;
}
bool BaseComponent::SetToDeleted()
{
if (IsDeleted())
return false;
_isDeleted = true;
return true;
}
std::list<SBaseComponent>::iterator BaseComponent::GetIterator() const
{
return _iterator;
}
std::shared_ptr<BaseComponent> BaseComponent::GetSharedPtr() const
{
return _this.lock();
}
void BaseComponent::AssignPtr(std::list<SBaseComponent>::iterator iterator)
{
_iterator = iterator;
_this = *iterator;
}
PScene BaseComponent::GetOwner() const
{
return _owner;
}
void BaseComponent::SetOwner(PScene owner)
{
_owner = owner;
}
|
; A081674: Generalized Poly-Bernoulli numbers.
; 0,1,6,29,130,561,2366,9829,40410,164921,669526,2707629,10919090,43942081,176565486,708653429,2841788170,11388676041,45619274246,182670807229,731264359650,2926800830801,11712433499806,46865424529029,187508769705530,750176293590361,3001128818666166,12005786207578829,48026957629057810,192119268912458721,768511390838517326,3074148508920116629,12296902872378608490,49188537999608859881,196756931528718717286,787036064705724702429,3148169274595448309570,12592752145699441737841,50371233724750712450046
mov $1,4
mov $2,3
mov $3,$0
add $3,1
pow $1,$3
pow $2,$3
sub $1,$2
div $1,6
mov $0,$1
|
ldy #{c2}
lda ({z1}),y
ldy #{c1}
clc
adc ({z1}),y
sta ({z1}),y
ldy #{c2}+1
lda ({z1}),y
ldy #{c1}+1
adc ({z1}),y
sta ({z1}),y
|
showText:
DISPLAY "show text: ", $
xor a : ld (show_offset), a, (s_half), a
reRenderText:
call renderTextScreen
showTxLp:
call txControls
xor a : call changeBank
dup 5
halt
edup
jp showTxLp
txControls:
call inkey
and a : ret z
cp 'q' : jp z, txUp
cp 'o' : jp z, txUp
cp 'a' : jp z, txDn
cp 'p' : jp z, txDn
cp 'b' : jp z, .justBack
cp 'n' : jp z, openURI
cp 32 : jp z, .toggleHalf
ret
.justBack
pop af
jp historyBack
.toggleHalf
pop af
ld a, (s_half) : xor #ff : ld (s_half), a
jp reRenderText
txUp:
ld a, (show_offset)
and a : ret z
sub 20 : ld (show_offset), a
call renderTextScreen
ret
txDn:
ld a, (show_offset)
add 20 : ld (show_offset), a
call renderTextScreen
ret
renderTextScreen:
DISPLAY "renderTextScreen: ", $
call renderHeader
ld b, 20
.loop
push bc
ld a, 20 : sub b : ld b, a : ld a, (show_offset) : add b : ld b, a
call renderTextLine
pop bc
djnz .loop
ret
renderTextLine:
call findLine
ld a, h : or l : ret z
ld a, (hl) : and a : ret z
ld a, (s_half) : and a : call nz, skipHalf64T
call printL64
call mvCR
ret
|
///
/// \file AliFemtoEventReaderAOD.cxx
///
#include "AliFemtoEventReaderAOD.h"
#include "TFile.h"
#include "TTree.h"
#include "TRandom3.h"
#include "AliAODEvent.h"
#include "AliAODTrack.h"
#include "AliAODVertex.h"
#include "AliAODMCHeader.h"
#include "AliESDtrack.h"
#include "AliFmPhysicalHelixD.h"
#include "AliFmThreeVectorF.h"
#include "SystemOfUnits.h"
#include "AliFemtoEvent.h"
#include "AliFemtoModelHiddenInfo.h"
#include "AliFemtoModelGlobalHiddenInfo.h"
#include "AliPID.h"
#include "AliAODpidUtil.h"
#include "AliAnalysisUtils.h"
#include "AliGenHijingEventHeader.h"
#include "AliExternalTrackParam.h"
#include <algorithm>
#include <cassert>
#include <memory>
#include <map>
#ifdef __ROOT__
/// \cond CLASSIMP
ClassImp(AliFemtoEventReaderAOD);
/// \endcond
#endif
#if !(ST_NO_NAMESPACES)
using namespace units;
#endif
using namespace std;
double fV1[3];
//____________________________
//constructor with 0 parameters , look at default settings
AliFemtoEventReaderAOD::AliFemtoEventReaderAOD():
fNumberofEvent(0),
fCurEvent(0),
fEvent(nullptr),
fAllTrue(160),
fAllFalse(160),
fFilterBit(0),
fFilterMask(0),
// fPWG2AODTracks(0x0),
fReadMC(0),
fReadV0(0),
fReadCascade(0),
fUsePreCent(0),
fEstEventMult(kCentrality),
fAODpidUtil(nullptr),
fAODheader(nullptr),
fAnaUtils(nullptr),
fEventCuts(nullptr),
fUseAliEventCuts(0),
fReadFullMCData(false),
fInputFile(""),
fTree(nullptr),
fAodFile(nullptr),
fMagFieldSign(1),
fisEPVZ(kTRUE),
fpA2013(kFALSE),
fisPileUp(kFALSE),
fCascadePileUpRemoval(kFALSE),
fV0PileUpRemoval(kFALSE),
fTrackPileUpRemoval(kFALSE),
fMVPlp(kFALSE),
fOutOfBunchPlp(kFALSE),
fMinVtxContr(0),
fMinPlpContribMV(0),
fMinPlpContribSPD(0),
fDCAglobalTrack(0),
fFlatCent(kFALSE),
fPrimaryVertexCorrectionTPCPoints(kFALSE),
fShiftPosition(0.),
f1DcorrectionsPions(0),
f1DcorrectionsKaons(0),
f1DcorrectionsProtons(0),
f1DcorrectionsPionsMinus(0),
f1DcorrectionsKaonsMinus(0),
f1DcorrectionsProtonsMinus(0),
f1DcorrectionsDeuterons(0),
f1DcorrectionsTritons(0),
f1DcorrectionsHe3s(0),
f1DcorrectionsAlphas(0),
f1DcorrectionsDeuteronsMinus(0),
f1DcorrectionsTritonsMinus(0),
f1DcorrectionsHe3sMinus(0),
f1DcorrectionsAlphasMinus(0),
f1DcorrectionsAll(0),
f1DcorrectionsLambdas(0),
f1DcorrectionsLambdasMinus(0),
f1DcorrectionsXiPlus(0),
f1DcorrectionsXiMinus(0),
f4DcorrectionsPions(0),
f4DcorrectionsKaons(0),
f4DcorrectionsProtons(0),
f4DcorrectionsPionsMinus(0),
f4DcorrectionsKaonsMinus(0),
f4DcorrectionsProtonsMinus(0),
f4DcorrectionsAll(0),
f4DcorrectionsLambdas(0),
f4DcorrectionsLambdasMinus(0),
fIsKaonAnalysis(kFALSE),
fIsProtonAnalysis(kFALSE),
fIsPionAnalysis(kFALSE),
fIsElectronAnalysis(kFALSE)
{
// default constructor
fAllTrue.ResetAllBits(kTRUE);
fAllFalse.ResetAllBits(kFALSE);
fCentRange[0] = 0;
fCentRange[1] = 1000;
}
AliFemtoEventReaderAOD::AliFemtoEventReaderAOD(const AliFemtoEventReaderAOD &aReader):
AliFemtoEventReader(),
fNumberofEvent(aReader.fNumberofEvent),
fCurEvent(aReader.fCurEvent),
fEvent(new AliAODEvent()),
fAllTrue(160),
fAllFalse(160),
fFilterBit(aReader.fFilterBit),
fFilterMask(aReader.fFilterMask),
// fPWG2AODTracks(0x0),
fReadMC(aReader.fReadMC),
fReadV0(aReader.fReadV0),
fReadCascade(aReader.fReadCascade),
fUsePreCent(aReader.fUsePreCent),
fEstEventMult(aReader.fEstEventMult),
fAODpidUtil(aReader.fAODpidUtil),
fAODheader(aReader.fAODheader),
fAnaUtils(aReader.fAnaUtils),
fEventCuts(aReader.fEventCuts),
fUseAliEventCuts(aReader.fUseAliEventCuts),
fReadFullMCData(aReader.fReadFullMCData),
fInputFile(aReader.fInputFile),
fTree(nullptr),
fAodFile(new TFile(aReader.fAodFile->GetName())),
fMagFieldSign(aReader.fMagFieldSign),
fisEPVZ(aReader.fisEPVZ),
fpA2013(aReader.fpA2013),
fisPileUp(aReader.fisPileUp),
fCascadePileUpRemoval(aReader.fCascadePileUpRemoval),
fV0PileUpRemoval(aReader.fV0PileUpRemoval),
fTrackPileUpRemoval(aReader.fTrackPileUpRemoval),
fMVPlp(aReader.fMVPlp),
fOutOfBunchPlp(aReader.fOutOfBunchPlp),
fMinVtxContr(aReader.fMinVtxContr),
fMinPlpContribMV(aReader.fMinPlpContribMV),
fMinPlpContribSPD(aReader.fMinPlpContribSPD),
fDCAglobalTrack(aReader.fDCAglobalTrack),
fFlatCent(aReader.fFlatCent),
fPrimaryVertexCorrectionTPCPoints(aReader.fPrimaryVertexCorrectionTPCPoints),
fShiftPosition(aReader.fShiftPosition),
f1DcorrectionsPions(aReader.f1DcorrectionsPions),
f1DcorrectionsKaons(aReader.f1DcorrectionsKaons),
f1DcorrectionsProtons(aReader.f1DcorrectionsProtons),
f1DcorrectionsPionsMinus(aReader.f1DcorrectionsPionsMinus),
f1DcorrectionsKaonsMinus(aReader.f1DcorrectionsKaonsMinus),
f1DcorrectionsProtonsMinus(aReader.f1DcorrectionsProtonsMinus),
f1DcorrectionsDeuterons(aReader.f1DcorrectionsDeuterons),
f1DcorrectionsTritons(aReader.f1DcorrectionsTritons),
f1DcorrectionsHe3s(aReader.f1DcorrectionsHe3s),
f1DcorrectionsAlphas(aReader.f1DcorrectionsAlphas),
f1DcorrectionsDeuteronsMinus(aReader.f1DcorrectionsDeuteronsMinus),
f1DcorrectionsTritonsMinus(aReader.f1DcorrectionsTritonsMinus),
f1DcorrectionsHe3sMinus(aReader.f1DcorrectionsHe3sMinus),
f1DcorrectionsAlphasMinus(aReader.f1DcorrectionsAlphasMinus),
f1DcorrectionsAll(aReader.f1DcorrectionsAll),
f1DcorrectionsLambdas(aReader.f1DcorrectionsLambdas),
f1DcorrectionsLambdasMinus(aReader.f1DcorrectionsLambdasMinus),
f1DcorrectionsXiPlus(aReader.f1DcorrectionsXiPlus),
f1DcorrectionsXiMinus(aReader.f1DcorrectionsXiMinus),
f4DcorrectionsPions(aReader.f4DcorrectionsPions),
f4DcorrectionsKaons(aReader.f4DcorrectionsKaons),
f4DcorrectionsProtons(aReader.f4DcorrectionsProtons),
f4DcorrectionsPionsMinus(aReader.f4DcorrectionsPionsMinus),
f4DcorrectionsKaonsMinus(aReader.f4DcorrectionsKaonsMinus),
f4DcorrectionsProtonsMinus(aReader.f4DcorrectionsProtonsMinus),
f4DcorrectionsAll(aReader.f4DcorrectionsAll),
f4DcorrectionsLambdas(aReader.f4DcorrectionsLambdas),
f4DcorrectionsLambdasMinus(aReader.f4DcorrectionsLambdasMinus),
fIsKaonAnalysis(aReader.fIsKaonAnalysis),
fIsProtonAnalysis(aReader.fIsProtonAnalysis),
fIsPionAnalysis(aReader.fIsPionAnalysis),
fIsElectronAnalysis(aReader.fIsElectronAnalysis),
fIsDeuteronAnalysis(aReader.fIsDeuteronAnalysis),
fIsTritonAnalysis(aReader.fIsTritonAnalysis),
fIsHe3Analysis(aReader.fIsHe3Analysis),
fIsAlphaAnalysis(aReader.fIsAlphaAnalysis)
{
// copy constructor
fAllTrue.ResetAllBits(kTRUE);
fAllFalse.ResetAllBits(kFALSE);
// fPWG2AODTracks = aReader.fPWG2AODTracks;
fCentRange[0] = aReader.fCentRange[0];
fCentRange[1] = aReader.fCentRange[1];
}
//__________________
AliFemtoEventReaderAOD::~AliFemtoEventReaderAOD()
{ // destructor
delete fEventCuts;
delete fTree;
delete fEvent;
delete fAodFile;
// if (fPWG2AODTracks) {
// fPWG2AODTracks->Delete();
// delete fPWG2AODTracks;
// }
}
//__________________
AliFemtoEventReaderAOD &AliFemtoEventReaderAOD::operator=(const AliFemtoEventReaderAOD &aReader)
{ // assignment operator
if (this == &aReader) {
return *this;
}
fInputFile = aReader.fInputFile;
fNumberofEvent = aReader.fNumberofEvent;
fCurEvent = aReader.fCurEvent;
delete fTree;
delete fEvent;
fEvent = new AliAODEvent();
delete fAodFile;
fAodFile = new TFile(aReader.fAodFile->GetName());
fAllTrue.ResetAllBits(kTRUE);
fAllFalse.ResetAllBits(kFALSE);
fFilterBit = aReader.fFilterBit;
fFilterMask = aReader.fFilterMask;
fReadMC = aReader.fReadMC;
fReadV0 = aReader.fReadV0;
fReadCascade = aReader.fReadCascade;
fReadFullMCData = aReader.fReadFullMCData;
// fPWG2AODTracks = aReader.fPWG2AODTracks;
fAODpidUtil = aReader.fAODpidUtil;
fAODheader = aReader.fAODheader;
fAnaUtils = aReader.fAnaUtils;
fEventCuts = aReader.fEventCuts;
fUseAliEventCuts = aReader.fUseAliEventCuts;
fCentRange[0] = aReader.fCentRange[0];
fCentRange[1] = aReader.fCentRange[1];
fUsePreCent = aReader.fUsePreCent;
fEstEventMult = aReader.fEstEventMult;
fMagFieldSign = aReader.fMagFieldSign;
fpA2013 = aReader.fpA2013;
fisPileUp = aReader.fisPileUp;
fCascadePileUpRemoval = aReader.fCascadePileUpRemoval;
fV0PileUpRemoval = aReader.fV0PileUpRemoval;
fTrackPileUpRemoval = aReader.fTrackPileUpRemoval;
fMVPlp = aReader.fMVPlp;
fOutOfBunchPlp = aReader.fOutOfBunchPlp;
fMinVtxContr = aReader.fMinVtxContr;
fMinPlpContribMV = aReader.fMinPlpContribMV;
fMinPlpContribSPD = aReader.fMinPlpContribSPD;
fDCAglobalTrack = aReader.fDCAglobalTrack;
fFlatCent = aReader.fFlatCent;
fPrimaryVertexCorrectionTPCPoints = aReader.fPrimaryVertexCorrectionTPCPoints;
fShiftPosition = aReader.fShiftPosition;
f1DcorrectionsPions = aReader.f1DcorrectionsPions;
f1DcorrectionsKaons = aReader.f1DcorrectionsKaons;
f1DcorrectionsProtons = aReader.f1DcorrectionsProtons;
f1DcorrectionsPionsMinus = aReader.f1DcorrectionsPionsMinus;
f1DcorrectionsKaonsMinus = aReader.f1DcorrectionsKaonsMinus;
f1DcorrectionsProtonsMinus = aReader.f1DcorrectionsProtonsMinus;
f1DcorrectionsDeuterons = aReader.f1DcorrectionsDeuterons;
f1DcorrectionsTritons = aReader.f1DcorrectionsTritons;
f1DcorrectionsHe3s = aReader.f1DcorrectionsHe3s;
f1DcorrectionsAlphas = aReader.f1DcorrectionsAlphas;
f1DcorrectionsDeuteronsMinus = aReader.f1DcorrectionsDeuteronsMinus;
f1DcorrectionsTritonsMinus = aReader.f1DcorrectionsTritonsMinus;
f1DcorrectionsHe3sMinus = aReader.f1DcorrectionsHe3sMinus;
f1DcorrectionsAlphasMinus = aReader.f1DcorrectionsAlphasMinus;
f1DcorrectionsAll = aReader.f1DcorrectionsAll;
f1DcorrectionsLambdas = aReader.f1DcorrectionsLambdas;
f1DcorrectionsLambdasMinus = aReader.f1DcorrectionsLambdasMinus;
f1DcorrectionsXiPlus = aReader.f1DcorrectionsXiPlus;
f1DcorrectionsXiMinus = aReader.f1DcorrectionsXiMinus;
f4DcorrectionsPions = aReader.f4DcorrectionsPions;
f4DcorrectionsKaons = aReader.f4DcorrectionsKaons;
f4DcorrectionsProtons = aReader.f4DcorrectionsProtons;
f4DcorrectionsPionsMinus = aReader.f4DcorrectionsPionsMinus;
f4DcorrectionsKaonsMinus = aReader.f4DcorrectionsKaonsMinus;
f4DcorrectionsProtonsMinus = aReader.f4DcorrectionsProtonsMinus;
f4DcorrectionsAll = aReader.f4DcorrectionsAll;
f4DcorrectionsLambdas = aReader.f4DcorrectionsLambdas;
f4DcorrectionsLambdasMinus = aReader.f4DcorrectionsLambdasMinus;
fIsKaonAnalysis = aReader.fIsKaonAnalysis;
fIsProtonAnalysis = aReader.fIsProtonAnalysis;
fIsPionAnalysis = aReader.fIsPionAnalysis;
fIsElectronAnalysis = aReader.fIsElectronAnalysis;
return *this;
}
//__________________
AliFemtoString AliFemtoEventReaderAOD::Report()
{
// create reader report
AliFemtoString temp = "\n This is the AliFemtoEventReaderAOD\n";
return temp;
}
//__________________
void AliFemtoEventReaderAOD::SetInputFile(const char *inputFile)
{
/// Reads a list of filenames from the file 'inputFile'. Each filename is
/// checked for a AOD TTree, if present it is added to the fTree chain.
fInputFile = inputFile;
ifstream infile(inputFile);
delete fTree;
fTree = new TChain("aodTree");
for (std::string line; std::getline(infile, line);) {
const char *filename = line.c_str();
TFile *aodFile = TFile::Open(filename, "READ");
if (aodFile) {
TTree *tree = static_cast<TTree*>(aodFile->Get("aodTree"));
if (tree) {
fTree->AddFile(filename);
delete tree;
}
aodFile->Close();
}
delete aodFile;
}
}
AliFemtoEvent *AliFemtoEventReaderAOD::ReturnHbtEvent()
{
/// Reads in the next event from the chain and converts it to an AliFemtoEvent
AliFemtoEvent *hbtEvent = nullptr;
// We have hit the end of our range -> open the next file
if (fCurEvent == fNumberofEvent) {
// We haven't loaded anything yet - open
if (fNumberofEvent == 0) {
// cout << "fEvent: " << fEvent << "\n";
fEvent = new AliAODEvent();
fEvent->ReadFromTree(fTree);
fNumberofEvent = fTree->GetEntries();
// cout << "Number of entries in file " << fNumberofEvent << endl;
fCurEvent = 0;
} else {
//no more data to read
fReaderStatus = 1;
return nullptr;
}
}
// cout << "starting to read event " << fCurEvent << endl;
fTree->GetEvent(fCurEvent);
// cout << "Read event " << fEvent << " from file " << fTree << endl;
hbtEvent = CopyAODtoFemtoEvent();
fCurEvent++;
return hbtEvent;
}
AliFemtoEvent *AliFemtoEventReaderAOD::CopyAODtoFemtoEvent()
{
// A function that reads in the AOD event
// and transfers the neccessary information into
// the internal AliFemtoEvent
AliFemtoEvent *tEvent = new AliFemtoEvent();
// setting global event characteristics
tEvent->SetRunNumber(fEvent->GetRunNumber());
tEvent->SetMagneticField(fEvent->GetMagneticField() * kilogauss); //to check if here is ok
tEvent->SetZDCN1Energy(fEvent->GetZDCN1Energy());
tEvent->SetZDCP1Energy(fEvent->GetZDCP1Energy());
tEvent->SetZDCN2Energy(fEvent->GetZDCN2Energy());
tEvent->SetZDCP2Energy(fEvent->GetZDCP2Energy());
tEvent->SetZDCEMEnergy(fEvent->GetZDCEMEnergy(0));
tEvent->SetZDCParticipants(0);
tEvent->SetTriggerMask(fEvent->GetTriggerMask());
tEvent->SetTriggerCluster(fEvent->GetTriggerCluster());
// Attempt to access MC header
AliAODMCHeader *mcH = nullptr;
TClonesArray *mcP = nullptr;
if (fReadMC) {
mcH = (AliAODMCHeader *)fEvent->FindListObject(AliAODMCHeader::StdBranchName());
if (!mcH) {
cout << "AOD MC information requested, but no header found!" << endl;
}
mcP = (TClonesArray *)fEvent->FindListObject(AliAODMCParticle::StdBranchName());
if (!mcP) {
cout << "AOD MC information requested, but no particle array found!" << endl;
}
}
AliAODHeader *header = dynamic_cast<AliAODHeader *>(fEvent->GetHeader());
assert(header && "Not a standard AOD");
tEvent->SetReactionPlaneAngle(header->GetQTheta(0) / 2.0);
// Int_t *motherids=0;
// if (mcP) {
// const int motherTabSize = ((AliAODMCParticle *) mcP->At(mcP->GetEntries()-1))->GetLabel();
// motherids = new int[motherTabSize+1];
// for (int ip=0; ip<motherTabSize+1; ip++) motherids[ip] = 0;
// // Read in mother ids
// AliAODMCParticle *motherpart;
// for (int ip=0; ip<mcP->GetEntries(); ip++) {
// motherpart = (AliAODMCParticle *) mcP->At(ip);
// if (motherpart->GetDaughter(0) > 0)
// motherids[motherpart->GetDaughter(0)] = ip;
// if (motherpart->GetDaughter(1) > 0)
// motherids[motherpart->GetDaughter(1)] = ip;
// }
// }
//******* Ali Event Cuts - applied on AOD event ************
if (fUseAliEventCuts) {
if (!fEventCuts->AcceptEvent(fEvent)) {
return nullptr;
}
}
//**************************************
// AliAnalysisUtils
if (fisPileUp || fpA2013) {
fAnaUtils = new AliAnalysisUtils();
if (fMinVtxContr) {
fAnaUtils->SetMinVtxContr(fMinVtxContr);
}
if (fpA2013 && fAnaUtils->IsVertexSelected2013pA(fEvent) == kFALSE) {
delete fAnaUtils;
delete tEvent;
return nullptr; // Vertex rejection for pA analysis.
}
fAnaUtils->SetUseMVPlpSelection(fMVPlp);
fAnaUtils->SetUseOutOfBunchPileUp(fOutOfBunchPlp);
if (fMinPlpContribMV) {
fAnaUtils->SetMinPlpContribMV(fMinPlpContribMV);
}
if (fMinPlpContribSPD) {
fAnaUtils->SetMinPlpContribSPD(fMinPlpContribSPD);
}
if (fisPileUp && fAnaUtils->IsPileUpEvent(fEvent)) {
delete fAnaUtils;
delete tEvent;
return nullptr; // Pile-up rejection.
}
delete fAnaUtils;
}
// Primary Vertex position
const auto *aodvertex = (fUseAliEventCuts)
? static_cast<const AliAODVertex *>(fEventCuts->GetPrimaryVertex())
: static_cast<const AliAODVertex *>(fEvent->GetPrimaryVertex());
if (!aodvertex || aodvertex->GetNContributors() < 1) {
delete tEvent; // Bad vertex, skip event.
return nullptr;
}
aodvertex->GetPosition(fV1);
AliFmThreeVectorF vertex(fV1[0], fV1[1], fV1[2]);
tEvent->SetPrimVertPos(vertex);
//starting to reading tracks
int nofTracks = 0; //number of reconstructed tracks in event
nofTracks = fEvent->GetNumberOfTracks();
//cout<<"NEW: ======> nofTracks "<<nofTracks<<endl;
AliEventplane *ep = fEvent->GetEventplane();
if (ep) {
const float event_plane_angle = (fisEPVZ)
? ep->GetEventplane("V0", fEvent, 2)
: ep->GetEventplane("Q");
tEvent->SetEP(ep);
tEvent->SetReactionPlaneAngle(event_plane_angle);
}
AliCentrality *cent = fEvent->GetCentrality();
if (!fEstEventMult && cent && fUsePreCent) {
if ((cent->GetCentralityPercentile("V0M") * 10 < fCentRange[0]) ||
(cent->GetCentralityPercentile("V0M") * 10 > fCentRange[1])) {
delete tEvent;
return nullptr;
}
}
const Float_t percent = cent->GetCentralityPercentile("V0M");
// Flatten centrality distribution
if (percent < 9 && fFlatCent) {
bool reject_event = RejectEventCentFlat(fEvent->GetMagneticField(), percent);
if (reject_event) {
delete tEvent;
return nullptr;
}
}
int realnofTracks = 0; // number of track which we use in a analysis
int tracksPrim = 0;
// constant indicating label has been unset
const int UNDEFINED_LABEL = -1;
// 'labels' maps a track's id to the track's index in the Event
// i.e. labels[Event->GetTrack(x)->GetID()] == x
std::vector<int> labels(nofTracks, UNDEFINED_LABEL);
// looking for global tracks and saving their numbers to copy from
// them PID information to TPC-only tracks in the main loop over tracks
for (int i = 0; i < nofTracks; i++) {
const auto *aodtrack = static_cast<AliAODTrack *>(fEvent->GetTrack(i));
if (!aodtrack->TestFilterBit(fFilterBit)) {
// Skip TPC-only tracks
const int id = aodtrack->GetID();
if (id < 0) {
continue;
}
// Resize labels vector if "id" is larger than mapping allows
if (static_cast<size_t>(id) >= labels.size()) {
labels.resize(id + 1024, UNDEFINED_LABEL);
}
labels[id] = i;
}
}
int tNormMult = 0;
Int_t norm_mult = 0;
for (int i = 0; i < nofTracks; i++) {
// const AliAODTrack *aodtrack=dynamic_cast<AliAODTrack*>(fEvent->GetTrack(i));
AliAODTrack *aodtrack = static_cast<AliAODTrack *>(fEvent->GetTrack(i));
assert(aodtrack && "Not a standard AOD"); // Getting the AODtrack directly
if (aodtrack->IsPrimaryCandidate()) {
tracksPrim++;
}
if ((fFilterBit && !aodtrack->TestFilterBit(fFilterBit)) ||
(fFilterMask && !aodtrack->TestFilterBit(fFilterMask))) {
continue;
}
// Check the sanity of the tracks - reject zero momentum tracks
if (aodtrack->P() == 0.0) {
continue;
}
// Counting particles to set multiplicity
if ((fEstEventMult == kGlobalCount)
//&& (aodtrack->IsPrimaryCandidate()) //? instead of kinks?
&& (aodtrack->Chi2perNDF() < 4.0)
&& (0.15 <= aodtrack->Pt() && aodtrack->Pt() < 20)
&& (aodtrack->GetTPCNcls() > 70)
&& (aodtrack->Eta() < 0.8)) {
tNormMult++;
}
norm_mult = tracksPrim;
if (cent) {
switch (fEstEventMult) {
case kCentrality:
norm_mult = lrint(10 * cent->GetCentralityPercentile("V0M"));
break;
case kCentralityV0A:
norm_mult = lrint(10 * cent->GetCentralityPercentile("V0A"));
break;
case kCentralityV0C:
norm_mult = lrint(10 * cent->GetCentralityPercentile("V0C"));
break;
case kCentralityZNA:
norm_mult = lrint(10 * cent->GetCentralityPercentile("ZNA"));
break;
case kCentralityZNC:
norm_mult = lrint(10 * cent->GetCentralityPercentile("ZNC"));
break;
case kCentralityCL1:
norm_mult = lrint(10 * cent->GetCentralityPercentile("CL1"));
break;
case kCentralityCL0:
norm_mult = lrint(10 * cent->GetCentralityPercentile("CL0"));
break;
case kCentralityTRK:
norm_mult = lrint(10 * cent->GetCentralityPercentile("TRK"));
break;
case kCentralityTKL:
norm_mult = lrint(10 * cent->GetCentralityPercentile("TKL"));
break;
case kCentralityCND:
norm_mult = lrint(10 * cent->GetCentralityPercentile("CND"));
break;
case kCentralityNPA:
norm_mult = lrint(10 * cent->GetCentralityPercentile("NPA"));
break;
case kCentralityFMD:
norm_mult = lrint(10 * cent->GetCentralityPercentile("FMD"));
break;
case kGlobalCount:
norm_mult = tNormMult; // Particles counted in the loop, trying to reproduce GetReferenceMultiplicity. If better (default) method appears it should be changed
break;
case kReference:
norm_mult = fAODheader->GetRefMultiplicity();
break;
case kTPCOnlyRef:
norm_mult = fAODheader->GetTPConlyRefMultiplicity();
break;
case kVZERO:
Float_t multV0 = 0.0;
for (Int_t i = 0; i < 64; i++)
multV0 += fEvent->GetVZEROData()->GetMultiplicity(i);
norm_mult = lrint(multV0);
}
}
tEvent->SetNormalizedMult(norm_mult);
std::unique_ptr<AliFemtoTrack> trackCopy(CopyAODtoFemtoTrack(aodtrack));
trackCopy->SetMultiplicity(norm_mult);
trackCopy->SetZvtx(fV1[2]);
// copying PID information from the correspondent track
// const AliAODTrack *aodtrackpid = fEvent->GetTrack(labels[-1-fEvent->GetTrack(i)->GetID()]);
// For TPC Only tracks we have to copy PID information from corresponding global tracks
const Int_t pid_track_id = (fFilterBit == (1 << 7) || fFilterMask == 128)
? labels[-1 - fEvent->GetTrack(i)->GetID()]
: i;
const auto *aodtrackpid = static_cast<AliAODTrack *>(fEvent->GetTrack(pid_track_id));
assert(aodtrackpid && "Not a standard AOD");
//Pile-up removal
if (fTrackPileUpRemoval) {
//method which checks if track
//have at least 1 hit in ITS or TOF.
bool passTrackPileUp = false;
// does tof timing exist for our track?
if (aodtrackpid->GetTOFBunchCrossing() == 0) {
passTrackPileUp = true;
}
// check ITS refit
if (!(aodtrackpid->GetStatus() & AliESDtrack::kITSrefit)) {
continue;
}
//loop over the 4 ITS Layrs and check for a hit!
for (int i = 0; i < 2; ++i) {
//we use layers 0, 1 /OR/ 0, 1, 4, 5
// if(i==2 || i==3) i+=2;
if (aodtrackpid->HasPointOnITSLayer(i)) {
passTrackPileUp = true;
}
}
if (!passTrackPileUp) {
continue;
}
}
CopyPIDtoFemtoTrack(aodtrackpid, trackCopy.get());
if (mcP) {
// Fill the hidden information with the simulated data
Int_t track_label = aodtrack->GetLabel();
const AliAODMCParticle *tPart = (track_label > -1)
? static_cast<const AliAODMCParticle *>(mcP->At(track_label))
: !fReadFullMCData ? nullptr
: static_cast<const AliAODMCParticle *>(mcP->At(std::abs(track_label)));
AliFemtoModelGlobalHiddenInfo *tInfo = new AliFemtoModelGlobalHiddenInfo();
double fpx = 0.0, fpy = 0.0, fpz = 0.0, fpt = 0.0;
if (!tPart) {
fpx = fV1[0];
fpy = fV1[1];
fpz = fV1[2];
tInfo->SetGlobalEmissionPoint(fpx, fpy, fpz);
tInfo->SetPDGPid(0);
tInfo->SetTrueMomentum(0.0, 0.0, 0.0);
tInfo->SetEmissionPoint(0.0, 0.0, 0.0, 0.0);
tInfo->SetMass(0);
} else {
// Check the mother information
// Using the new way of storing the freeze-out information
// Final state particle is stored twice on the stack
// one copy (mother) is stored with original freeze-out information
// and is not tracked
// the other one (daughter) is stored with primary vertex position
// and is tracked
// Freeze-out coordinates
fpx = tPart->Xv() - fV1[0];
fpy = tPart->Yv() - fV1[1];
fpz = tPart->Zv() - fV1[2];
// fpt = tPart->T();
tInfo->SetGlobalEmissionPoint(fpx, fpy, fpz);
fpx *= 1e13;
fpy *= 1e13;
fpz *= 1e13;
// fpt *= 1e13;
// cout << "Looking for mother ids " << endl;
//if (motherids[TMath::Abs(aodtrack->GetLabel())]>0) {
if (tPart->GetMother() > -1) {
//MC particle has a mother
// cout << "Got mother id" << endl;
// AliAODMCParticle *mother = GetParticleWithLabel(mcP, motherids[TMath::Abs(aodtrack->GetLabel())]);
AliAODMCParticle *mother = static_cast<AliAODMCParticle *>(mcP->At(tPart->GetMother()));
// Check if this is the same particle stored twice on the stack
if (mother) {
if ((mother->GetPdgCode() == tPart->GetPdgCode() || (mother->Px() == tPart->Px()))) {
// It is the same particle
// Read in the original freeze-out information
// and convert it from to [fm]
// EPOS style
// fpx = mother->Xv()*1e13*0.197327;
// fpy = mother->Yv()*1e13*0.197327;
// fpz = mother->Zv()*1e13*0.197327;
// fpt = mother->T() *1e13*0.197327*0.5;
// Therminator style
fpx = mother->Xv() * 1e13;
fpy = mother->Yv() * 1e13;
fpz = mother->Zv() * 1e13;
// fpt = mother->T() *1e13*3e10;
} else { //particle's mother exists and the information about it can be added to hiddeninfo:
tInfo->SetMotherPdgCode(mother->GetPdgCode());
tInfo->SetMotherMomentum(mother->Px(), mother->Py(), mother->Pz());
}
}
}
// if (fRotateToEventPlane) {
// double tPhi = TMath::ATan2(fpy, fpx);
// double tRad = TMath::Hypot(fpx, fpy);
// fpx = tRad*TMath::Cos(tPhi - tReactionPlane);
// fpy = tRad*TMath::Sin(tPhi - tReactionPlane);
// }
tInfo->SetPDGPid(tPart->GetPdgCode());
// if (fRotateToEventPlane) {
// double tPhi = TMath::ATan2(tPart->Py(), tPart->Px());
// double tRad = TMath::Hypot(tPart->Px(), tPart->Py());
// tInfo->SetTrueMomentum(tRad*TMath::Cos(tPhi - tReactionPlane),
// tRad*TMath::Sin(tPhi - tReactionPlane),
// tPart->Pz());
// }
// else
tInfo->SetTrueMomentum(tPart->Px(), tPart->Py(), tPart->Pz());
Double_t mass2 = (tPart->E() * tPart->E()
- tPart->Px() * tPart->Px()
- tPart->Py() * tPart->Py()
- tPart->Pz() * tPart->Pz());
tInfo->SetMass(mass2 <= 0.0 ? 0.0 : TMath::Sqrt(mass2));
tInfo->SetEmissionPoint(fpx, fpy, fpz, fpt);
tInfo->SetOrigin(tPart->IsPhysicalPrimary() ? 0
: tPart->IsSecondaryFromWeakDecay() ? 1
: tPart->IsSecondaryFromMaterial() ? 2
: -1);
// // fillDCA
// //if (TMath::Abs(impact[0]) > 0.001) {
// if (tPart->IsPhysicalPrimary()){
// tInfo->SetPartOrigin(0);
// // trackCopy->SetImpactDprim(impact[0]);
// //cout << "Read prim" << endl;
// }
// else if (tPart->IsSecondaryFromWeakDecay()) {
// tInfo->SetPartOrigin(1);
// // trackCopy->SetImpactDweak(impact[0]);
// //cout << "Read wea" << endl;
// }
// else if (tPart->IsSecondaryFromMaterial()) {
// tInfo->SetPartOrigin(2);
// // trackCopy->SetImpactDmat(impact[0]);
// //cout << "Read mat" << endl;
// }
// //}
// // end fillDCA
}
trackCopy->SetHiddenInfo(tInfo);
}
//AliExternalTrackParam *param = new AliExternalTrackParam(*aodtrack->GetInnerParam());
trackCopy->SetInnerMomentum(aodtrack->GetTPCmomentum());
//Special MC analysis for pi,K,p,e slected by PDG code -->
if (fIsKaonAnalysis || fIsProtonAnalysis || fIsPionAnalysis || fIsElectronAnalysis) {
const auto *hidden_info = static_cast<const AliFemtoModelHiddenInfo *>(trackCopy->GetHiddenInfo());
Int_t pdg = hidden_info->GetPDGPid();
Double_t ptrue = hidden_info->GetTrueMomentum()->Mag();
//if(fIsKaonAnalysis&&TMath::Abs(pdg) == 321)cout<<"AOD REader pdg cod "<<pdg<<" ptrue "<<ptrue<< endl;
Bool_t trackAccept = true;
if (fIsKaonAnalysis == true && TMath::Abs(pdg) != 321) {
trackAccept = false;
}
if (fIsProtonAnalysis == true && TMath::Abs(pdg) != 2212) {
trackAccept = false;
}
if (fIsPionAnalysis == true && TMath::Abs(pdg) != 211) {
trackAccept = false;
}
if (fIsElectronAnalysis == true && TMath::Abs(pdg) != 11) {
trackAccept = false;
}
/***************************************************/
//
if (fIsDeuteronAnalysis == true && TMath::Abs(pdg) != 1000010020) {
trackAccept = false;
}
if (fIsTritonAnalysis == true && TMath::Abs(pdg) != 1000010040) {
trackAccept = false;
}
if (fIsHe3Analysis == true && TMath::Abs(pdg) != 700302) {
trackAccept = false; //temporary pdg
}
if (fIsAlphaAnalysis == true && TMath::Abs(pdg) != 700202) {
trackAccept = false; //temporary pdg
}
//
/*****************************************************/
if (trackAccept == true && ptrue > 0) {
tEvent->TrackCollection()->push_back(trackCopy.release()); //adding track to analysis
realnofTracks++; //real number of tracks
} else {
// cout<<"bad track : AOD REader pdg cod"<<pdg<<" ptrue "<<ptrue<<endl;
}
//Special MC analysis for pi,K,p,e slected by PDG code <--
} else {
tEvent->TrackCollection()->push_back(trackCopy.release()); // Adding track to analysis
realnofTracks++; // Real number of tracks
}
}
//cout<<"======================> realnofTracks"<<realnofTracks<<endl;
tEvent->SetNumberOfTracks(realnofTracks); // Setting number of track which we read in event
if (cent) {
tEvent->SetCentralityV0(cent->GetCentralityPercentile("V0M"));
tEvent->SetCentralityV0A(cent->GetCentralityPercentile("V0A"));
tEvent->SetCentralityV0C(cent->GetCentralityPercentile("V0C"));
tEvent->SetCentralityZNA(cent->GetCentralityPercentile("ZNA"));
tEvent->SetCentralityZNC(cent->GetCentralityPercentile("ZNC"));
tEvent->SetCentralityCL1(cent->GetCentralityPercentile("CL1"));
tEvent->SetCentralityCL0(cent->GetCentralityPercentile("CL0"));
tEvent->SetCentralityTKL(cent->GetCentralityPercentile("TKL"));
tEvent->SetCentralityFMD(cent->GetCentralityPercentile("FMD"));
tEvent->SetCentralityFMD(cent->GetCentralityPercentile("NPA"));
// tEvent->SetCentralitySPD1(cent->GetCentralityPercentile("CL1"));
tEvent->SetCentralityTrk(cent->GetCentralityPercentile("TRK"));
tEvent->SetCentralityCND(cent->GetCentralityPercentile("CND"));
}
if (fReadV0) {
int count_pass = 0;
for (Int_t i = 0; i < fEvent->GetNumberOfV0s(); i++) {
AliAODv0 *aodv0 = fEvent->GetV0(i);
// ensure a "good" v0 particle passes these conditions
if (!aodv0
|| aodv0->GetNDaughters() > 2
|| aodv0->GetNProngs() > 2
|| aodv0->GetCharge() != 0
|| aodv0->ChargeProng(0) == aodv0->ChargeProng(1)
|| aodv0->CosPointingAngle(fV1) < 0.98) {
continue;
}
AliAODTrack *daughterTrackPos = (AliAODTrack *)aodv0->GetDaughter(0), // getting positive daughter track
*daughterTrackNeg = (AliAODTrack *)aodv0->GetDaughter(1); // getting negative daughter track
if (daughterTrackPos == nullptr || daughterTrackNeg == nullptr) {
continue; // daughter tracks must exist
}
if (daughterTrackNeg->Charge() == daughterTrackPos->Charge()) {
continue; // and have different charge
}
// ensure that pos and neg are pointing to the correct children
if (daughterTrackPos->Charge() < 0 && daughterTrackNeg->Charge() > 0) {
std::swap(daughterTrackPos, daughterTrackNeg); // can we use this?
}
if (fV0PileUpRemoval) {
//method which checks if each of the v0 daughters
//have at least 1 hit in ITS or TOF.
bool passPos = false;
bool passNeg = false;
//does tof timing exist for our track?
if (daughterTrackPos->GetTOFBunchCrossing() == 0) {
passPos = true;
}
if (daughterTrackNeg->GetTOFBunchCrossing() == 0) {
passNeg = true;
}
//loop over the 4 ITS Layrs and check for a hit!
for (int i = 0; i < 4; ++i) {
//checking layers 0, 1, 4, 5
if (i == 2 || i == 3) {
i += 2;
}
if (daughterTrackPos->HasPointOnITSLayer(i)) {
passPos = true;
}
if (daughterTrackNeg->HasPointOnITSLayer(i)) {
passNeg = true;
}
}
if (!passPos || !passNeg) {
continue;
}
}
std::unique_ptr<AliFemtoV0> trackCopyV0(CopyAODtoFemtoV0(aodv0));
trackCopyV0->SetMultiplicity(norm_mult);
trackCopyV0->SetZvtx(fV1[2]);
if (mcP) {
daughterTrackPos->SetAODEvent(fEvent);
daughterTrackNeg->SetAODEvent(fEvent);
if (daughterTrackPos->GetLabel() > 0 && daughterTrackNeg->GetLabel() > 0) {
// get the MC data for the two daughter particles
const AliAODMCParticle *mcParticlePos = static_cast<AliAODMCParticle *>(mcP->At(daughterTrackPos->GetLabel())),
*mcParticleNeg = static_cast<AliAODMCParticle *>(mcP->At(daughterTrackNeg->GetLabel()));
// They daughter info MUST exist for both
if ((mcParticlePos != nullptr) && (mcParticleNeg != nullptr)) {
// Get the mother ID of the two daughters
const int motherOfPosID = mcParticlePos->GetMother(),
motherOfNegID = mcParticleNeg->GetMother();
// If both daughter tracks refer to the same mother, we can continue
if ((motherOfPosID > -1) && (motherOfPosID == motherOfNegID)) {
// Create the MC data store
AliFemtoModelHiddenInfo *tInfo = new AliFemtoModelHiddenInfo();
// Our V0 particle
const AliAODMCParticle *v0 = static_cast<AliAODMCParticle *>(mcP->At(motherOfPosID));
if (v0 == nullptr) {
tInfo->SetPDGPid(0);
tInfo->SetTrueMomentum(0.0, 0.0, 0.0);
tInfo->SetMass(0);
} else {
//-----v0 particle-----
const int v0MotherId = v0->GetMother();
if (v0MotherId > -1) { //V0 particle has a mother
AliAODMCParticle *motherOfV0 = static_cast<AliAODMCParticle *>(mcP->At(v0MotherId));
tInfo->SetMotherPdgCode(motherOfV0->GetPdgCode());
}
tInfo->SetPDGPid(v0->GetPdgCode());
tInfo->SetMass(v0->GetCalcMass());
tInfo->SetTrueMomentum(v0->Px(), v0->Py(), v0->Pz());
tInfo->SetEmissionPoint(v0->Xv(), v0->Yv(), v0->Zv(), v0->T());
if (v0->IsPhysicalPrimary()) {
tInfo->SetOrigin(0);
} else if (v0->IsSecondaryFromWeakDecay()) {
tInfo->SetOrigin(1);
} else if (v0->IsSecondaryFromMaterial()) {
tInfo->SetOrigin(2);
} else {
tInfo->SetOrigin(-1);
}
//-----Positive daughter of v0-----
tInfo->SetPDGPidPos(mcParticlePos->GetPdgCode());
tInfo->SetMassPos(mcParticlePos->GetCalcMass());
tInfo->SetTrueMomentumPos(mcParticlePos->Px(), mcParticlePos->Py(), mcParticlePos->Pz());
tInfo->SetEmissionPointPos(mcParticlePos->Xv(), mcParticlePos->Yv(), mcParticlePos->Zv(), mcParticlePos->T());
//-----Negative daughter of v0-----
tInfo->SetPDGPidNeg(mcParticleNeg->GetPdgCode());
tInfo->SetMassNeg(mcParticleNeg->GetCalcMass());
tInfo->SetTrueMomentumNeg(mcParticleNeg->Px(), mcParticleNeg->Py(), mcParticleNeg->Pz());
tInfo->SetEmissionPointNeg(mcParticleNeg->Xv(), mcParticleNeg->Yv(), mcParticleNeg->Zv(), mcParticleNeg->T());
}
trackCopyV0->SetHiddenInfo(tInfo);
}
}
}
}
tEvent->V0Collection()->push_back(trackCopyV0.release());
count_pass++;
}
}
if (fReadCascade) {
int count_pass = 0;
for (Int_t i = 0; i < fEvent->GetNumberOfCascades(); i++) {
AliAODcascade *aodxi = fEvent->GetCascade(i);
if (!aodxi) {
continue;
}
//if (aodxi->GetNDaughters() > 2) continue;
//if (aodxi->GetNProngs() > 2) continue;
//if (aodxi->GetCharge() != 0) continue;
if ((aodxi->ChargeProng(0) == aodxi->ChargeProng(1))
|| (aodxi->CosPointingAngle(fV1) < 0.9)
|| (aodxi->CosPointingAngleXi(fV1[0], fV1[1], fV1[2]) < 0.98)) {
continue;
}
AliAODTrack *daughterTrackPos = (AliAODTrack *)aodxi->GetDaughter(0), // getting positive daughter track
*daughterTrackNeg = (AliAODTrack *)aodxi->GetDaughter(1), // getting negative daughter track
*bachTrack = (AliAODTrack *)aodxi->GetDecayVertexXi()->GetDaughter(0);
if (daughterTrackPos == nullptr || daughterTrackNeg == nullptr || bachTrack == nullptr) {
continue; // daughter tracks must exist
}
if (daughterTrackNeg->Charge() == daughterTrackPos->Charge()) {
continue; // and have different charge
}
if (fCascadePileUpRemoval) {
//method which checks if each of the v0 daughters and bachelor
//have at least 1 hit in ITS or TOF.
bool passPos = false;
bool passNeg = false;
bool passBac = false;
//does tof timing exist for our track?
if (daughterTrackPos->GetTOFBunchCrossing() == 0) {
passPos = true;
}
if (daughterTrackNeg->GetTOFBunchCrossing() == 0) {
passNeg = true;
}
if (bachTrack->GetTOFBunchCrossing() == 0) {
passBac = true;
}
//loop over the 4 ITS Layrs and check for a hit!
for (int i = 0; i < 4; ++i) {
if (i == 2 || i == 3) {
i += 2; //checking layers 0, 1, 4, 5
}
if (daughterTrackPos->HasPointOnITSLayer(i)) {
passPos = true;
}
if (daughterTrackNeg->HasPointOnITSLayer(i)) {
passNeg = true;
}
if (bachTrack->HasPointOnITSLayer(i)) {
passBac = true;
}
}
if (!passPos || !passNeg || !passBac) {
continue;
}
}
std::unique_ptr<AliFemtoXi> trackCopyXi(CopyAODtoFemtoXi(aodxi));
//TODO for now, in AliFemtoHiddenInfo, consider V0 as positive daughter and bachelor pion as negative daughter
//Methods will either be added to AliFemtoHiddenInfo to handle the Cascade case, or a new class will be constructed
if (mcP) {
daughterTrackPos->SetAODEvent(fEvent);
daughterTrackNeg->SetAODEvent(fEvent);
bachTrack->SetAODEvent(fEvent);
if (daughterTrackPos->GetLabel() > 0 && daughterTrackNeg->GetLabel() > 0 && bachTrack->GetLabel()) {
// get the MC data for the two daughter particles
const AliAODMCParticle *mcParticlePos = static_cast<AliAODMCParticle *>(mcP->At(daughterTrackPos->GetLabel())),
*mcParticleNeg = static_cast<AliAODMCParticle *>(mcP->At(daughterTrackNeg->GetLabel()));
//TODO double check this
const AliAODMCParticle *mcParticleBac;
if (bachTrack->GetLabel() > -1) {
mcParticleBac = static_cast<AliAODMCParticle *>(mcP->At(bachTrack->GetLabel()));
} else {
mcParticleBac = static_cast<AliAODMCParticle *>(mcP->At(-1 - bachTrack->GetLabel()));
}
// They daughter info MUST exist for both
if ((mcParticlePos != nullptr) && (mcParticleNeg != nullptr) && (mcParticleBac != nullptr)) {
// Get the mother ID of the two daughters
const int motherOfPosID = mcParticlePos->GetMother(),
motherOfNegID = mcParticleNeg->GetMother(),
motherOfBacID = mcParticleBac->GetMother();
// If both daughter tracks refer to the same mother, we can continue
if ((motherOfPosID > -1) && (motherOfPosID == motherOfNegID)) {
// Our V0 particle
const AliAODMCParticle *v0 = static_cast<AliAODMCParticle *>(mcP->At(motherOfPosID));
const int motherOfV0ID = v0->GetMother();
// If both V0 and bachelor pion trakcs refer to the same mother, we can continue
if ((motherOfV0ID > -1) && (motherOfV0ID == motherOfBacID)) {
// Create the MC data store
AliFemtoModelHiddenInfo *tInfo = new AliFemtoModelHiddenInfo();
const AliAODMCParticle *xi = static_cast<AliAODMCParticle *>(mcP->At(motherOfV0ID));
if (xi == nullptr) {
tInfo->SetPDGPid(0);
tInfo->SetTrueMomentum(0.0, 0.0, 0.0);
tInfo->SetMass(0);
} else {
//-----xi particle-----
const int xiMotherId = xi->GetMother();
if (xiMotherId > -1)
{ //V0 particle has a mother
AliAODMCParticle *motherOfXi = static_cast<AliAODMCParticle *>(mcP->At(xiMotherId));
tInfo->SetMotherPdgCode(motherOfXi->GetPdgCode());
}
tInfo->SetPDGPid(xi->GetPdgCode());
tInfo->SetMass(xi->GetCalcMass());
tInfo->SetTrueMomentum(xi->Px(), xi->Py(), xi->Pz());
tInfo->SetEmissionPoint(xi->Xv(), xi->Yv(), xi->Zv(), xi->T());
if (xi->IsPhysicalPrimary()) {
tInfo->SetOrigin(0);
} else if (xi->IsSecondaryFromWeakDecay()) {
tInfo->SetOrigin(1);
} else if (xi->IsSecondaryFromMaterial()) {
tInfo->SetOrigin(2);
} else {
tInfo->SetOrigin(-1);
}
//-----Positive daughter (//TODO for now, V0 daughter) of xi-----
tInfo->SetPDGPidPos(v0->GetPdgCode());
tInfo->SetMassPos(v0->GetCalcMass());
tInfo->SetTrueMomentumPos(v0->Px(), v0->Py(), v0->Pz());
tInfo->SetEmissionPointPos(v0->Xv(), v0->Yv(), v0->Zv(), v0->T());
//-----Negative daughter (//TODO for now, bachelor pion) of xi-----
tInfo->SetPDGPidNeg(mcParticleBac->GetPdgCode());
tInfo->SetMassNeg(mcParticleBac->GetCalcMass());
tInfo->SetTrueMomentumNeg(mcParticleBac->Px(), mcParticleBac->Py(), mcParticleBac->Pz());
tInfo->SetEmissionPointNeg(mcParticleBac->Xv(), mcParticleBac->Yv(), mcParticleBac->Zv(), mcParticleBac->T());
}
trackCopyXi->SetHiddenInfo(tInfo);
}
}
}
}
}
tEvent->XiCollection()->push_back(trackCopyXi.release());
count_pass++;
}
}
return tEvent;
}
AliFemtoTrack *AliFemtoEventReaderAOD::CopyAODtoFemtoTrack(AliAODTrack *tAodTrack)
{
// Copy the track information from the AOD into the internal AliFemtoTrack
// If it exists, use the additional information from the PWG2 AOD
AliFemtoTrack *tFemtoTrack = new AliFemtoTrack();
// Primary Vertex position
fEvent->GetPrimaryVertex()->GetPosition(fV1);
// fEvent->GetPrimaryVertex()->GetXYZ(fV1);
tFemtoTrack->SetPrimaryVertex(fV1);
tFemtoTrack->SetCharge(tAodTrack->Charge());
double pxyz[3];
tAodTrack->PxPyPz(pxyz); //reading noconstrained momentum
AliFemtoThreeVector v(pxyz[0], pxyz[1], pxyz[2]);
tFemtoTrack->SetP(v); //setting momentum
tFemtoTrack->SetPt(sqrt(pxyz[0] * pxyz[0] + pxyz[1] * pxyz[1]));
const AliFmThreeVectorD kOrigin(fV1[0], fV1[1], fV1[2]);
//setting track helix
const AliFmThreeVectorD ktP(pxyz[0], pxyz[1], pxyz[2]);
AliFmPhysicalHelixD helix(ktP, kOrigin, (double)(fEvent->GetMagneticField()) * kilogauss, (double)(tFemtoTrack->Charge()));
tFemtoTrack->SetHelix(helix);
// Flags
tFemtoTrack->SetTrackId(tAodTrack->GetID());
tFemtoTrack->SetFlags(tAodTrack->GetFlags());
tFemtoTrack->SetLabel(tAodTrack->GetLabel());
// Track quality information
float covmat[6];
tAodTrack->GetCovMatrix(covmat);
if (fDCAglobalTrack == 0) {
tFemtoTrack->SetImpactD(tAodTrack->DCA());
tFemtoTrack->SetImpactZ(tAodTrack->ZAtDCA());
tFemtoTrack->SetXatDCA(tAodTrack->XAtDCA());
tFemtoTrack->SetYatDCA(tAodTrack->YAtDCA());
tFemtoTrack->SetZatDCA(tAodTrack->ZAtDCA());
}
// tFemtoTrack->SetCdd(covmat[0]);
// tFemtoTrack->SetCdz(covmat[1]);
// tFemtoTrack->SetCzz(covmat[2]);
tFemtoTrack->SetTPCchi2(tAodTrack->GetTPCchi2());
tFemtoTrack->SetTPCncls(tAodTrack->GetTPCNcls());
tFemtoTrack->SetTPCnclsF(tAodTrack->GetTPCNclsF());
tFemtoTrack->SetTPCsignal(tAodTrack->GetTPCsignal());
tFemtoTrack->SetTPCClusterMap(tAodTrack->GetTPCClusterMap());
tFemtoTrack->SetTPCSharedMap(tAodTrack->GetTPCSharedMap());
float globalPositionsAtRadii[9][3];
float bfield = 5 * fMagFieldSign;
GetGlobalPositionAtGlobalRadiiThroughTPC(tAodTrack, bfield, globalPositionsAtRadii);
AliFemtoThreeVector tpcPositions[9];
std::copy_n(globalPositionsAtRadii, 9, tpcPositions);
if (fPrimaryVertexCorrectionTPCPoints) {
for (int i = 0; i < 9; i++) {
tpcPositions[i] -= kOrigin;
}
}
tFemtoTrack->SetNominalTPCEntrancePoint(tpcPositions[0]);
tFemtoTrack->SetNominalTPCPoints(tpcPositions);
tFemtoTrack->SetNominalTPCExitPoint(tpcPositions[8]);
if (fShiftPosition > 0.) {
Float_t posShifted[3];
SetShiftedPositions(tAodTrack, bfield, posShifted, fShiftPosition);
tFemtoTrack->SetNominalTPCPointShifted(posShifted);
}
int kink_indexes[3] = { 0, 0, 0 };
tFemtoTrack->SetKinkIndexes(kink_indexes);
//Corrections
if (f1DcorrectionsPions) {
tFemtoTrack->SetCorrectionPion(f1DcorrectionsPions->GetBinContent(f1DcorrectionsPions->FindFixBin(tAodTrack->Pt())));
}
else if (f4DcorrectionsPions) {
Int_t idx[4] = {f4DcorrectionsPions->GetAxis(0)->FindFixBin(tAodTrack->Eta()),
f4DcorrectionsPions->GetAxis(1)->FindFixBin(tAodTrack->Pt()),
f4DcorrectionsPions->GetAxis(2)->FindFixBin(tAodTrack->Zv()),
f4DcorrectionsPions->GetAxis(3)->FindFixBin(tAodTrack->Phi())};
//cout<<"Track with pT "<<tAodTrack->Pt()<<" eta: "<<tAodTrack->Eta()<<" zv: "<<tAodTrack->Zv()<<" phi: "<<tAodTrack->Phi()<<endl;
//cout<<"Pion bin: "<<idx[0]<<" "<<idx[1]<<" "<<idx[2]<<" "<<idx[3]<<" val: "<<f4DcorrectionsPions->GetBinContent(idx)<<endl;
double correction = f4DcorrectionsPions->GetBinContent(idx);
tFemtoTrack->SetCorrectionPion(correction == 0.0 ? 1.0 : correction);
}
else {
tFemtoTrack->SetCorrectionPion(1.0);
}
if (f1DcorrectionsKaons) {
tFemtoTrack->SetCorrectionKaon(f1DcorrectionsKaons->GetBinContent(f1DcorrectionsKaons->FindFixBin(tAodTrack->Pt())));
}
else if (f4DcorrectionsKaons) {
Int_t idx[4] = {f4DcorrectionsKaons->GetAxis(0)->FindFixBin(tAodTrack->Eta()),
f4DcorrectionsKaons->GetAxis(1)->FindFixBin(tAodTrack->Pt()),
f4DcorrectionsKaons->GetAxis(2)->FindFixBin(tAodTrack->Zv()),
f4DcorrectionsKaons->GetAxis(3)->FindFixBin(tAodTrack->Phi())};
if (f4DcorrectionsKaons->GetBinContent(idx) != 0) {
tFemtoTrack->SetCorrectionKaon(f4DcorrectionsKaons->GetBinContent(idx));
} else {
tFemtoTrack->SetCorrectionKaon(1.0);
}
}
else {
tFemtoTrack->SetCorrectionKaon(1.0);
}
if (f1DcorrectionsProtons) {
tFemtoTrack->SetCorrectionProton(f1DcorrectionsProtons->GetBinContent(f1DcorrectionsProtons->FindFixBin(tAodTrack->Pt())));
}
else if (f4DcorrectionsProtons) {
Int_t idx[4] = {f4DcorrectionsProtons->GetAxis(0)->FindFixBin(tAodTrack->Eta()),
f4DcorrectionsProtons->GetAxis(1)->FindFixBin(tAodTrack->Pt()),
f4DcorrectionsProtons->GetAxis(2)->FindFixBin(tAodTrack->Zv()),
f4DcorrectionsProtons->GetAxis(3)->FindFixBin(tAodTrack->Phi())};
if (f4DcorrectionsProtons->GetBinContent(idx) != 0) {
tFemtoTrack->SetCorrectionProton(f4DcorrectionsProtons->GetBinContent(idx));
} else {
tFemtoTrack->SetCorrectionProton(1.0);
}
}
else {
tFemtoTrack->SetCorrectionProton(1.0);
}
if (f1DcorrectionsPionsMinus) {
tFemtoTrack->SetCorrectionPionMinus(f1DcorrectionsPionsMinus->GetBinContent(f1DcorrectionsPionsMinus->FindFixBin(tAodTrack->Pt())));
}
else if (f4DcorrectionsPionsMinus) {
Int_t idx[4] = {f4DcorrectionsPionsMinus->GetAxis(0)->FindFixBin(tAodTrack->Eta()),
f4DcorrectionsPionsMinus->GetAxis(1)->FindFixBin(tAodTrack->Pt()),
f4DcorrectionsPionsMinus->GetAxis(2)->FindFixBin(tAodTrack->Zv()),
f4DcorrectionsPionsMinus->GetAxis(3)->FindFixBin(tAodTrack->Phi())};
if (f4DcorrectionsPionsMinus->GetBinContent(idx) != 0) {
tFemtoTrack->SetCorrectionPionMinus(f4DcorrectionsPionsMinus->GetBinContent(idx));
} else {
tFemtoTrack->SetCorrectionPionMinus(1.0);
}
}
else {
tFemtoTrack->SetCorrectionPionMinus(1.0);
}
if (f1DcorrectionsKaonsMinus) {
tFemtoTrack->SetCorrectionKaonMinus(f1DcorrectionsKaonsMinus->GetBinContent(f1DcorrectionsKaonsMinus->FindFixBin(tAodTrack->Pt())));
}
else if (f4DcorrectionsKaonsMinus) {
Int_t idx[4] = {f4DcorrectionsKaonsMinus->GetAxis(0)->FindFixBin(tAodTrack->Eta()),
f4DcorrectionsKaonsMinus->GetAxis(1)->FindFixBin(tAodTrack->Pt()),
f4DcorrectionsKaonsMinus->GetAxis(2)->FindFixBin(tAodTrack->Zv()),
f4DcorrectionsKaonsMinus->GetAxis(3)->FindFixBin(tAodTrack->Phi())};
if (f4DcorrectionsKaonsMinus->GetBinContent(idx) != 0) {
tFemtoTrack->SetCorrectionKaonMinus(f4DcorrectionsKaonsMinus->GetBinContent(idx));
} else {
tFemtoTrack->SetCorrectionKaonMinus(1.0);
}
}
else {
tFemtoTrack->SetCorrectionKaonMinus(1.0);
}
if (f1DcorrectionsProtonsMinus) {
tFemtoTrack->SetCorrectionProtonMinus(f1DcorrectionsProtonsMinus->GetBinContent(f1DcorrectionsProtonsMinus->FindFixBin(tAodTrack->Pt())));
}
else if (f4DcorrectionsProtonsMinus) {
Int_t idx[4] = {f4DcorrectionsProtonsMinus->GetAxis(0)->FindFixBin(tAodTrack->Eta()),
f4DcorrectionsProtonsMinus->GetAxis(1)->FindFixBin(tAodTrack->Pt()),
f4DcorrectionsProtonsMinus->GetAxis(2)->FindFixBin(tAodTrack->Zv()),
f4DcorrectionsProtonsMinus->GetAxis(3)->FindFixBin(tAodTrack->Phi())};
if (f4DcorrectionsProtonsMinus->GetBinContent(idx) != 0) {
tFemtoTrack->SetCorrectionProtonMinus(f4DcorrectionsProtonsMinus->GetBinContent(idx));
} else {
tFemtoTrack->SetCorrectionProtonMinus(1.0);
}
}
else {
tFemtoTrack->SetCorrectionProtonMinus(1.0);
}
if (f1DcorrectionsAll) {
tFemtoTrack->SetCorrectionAll(f1DcorrectionsAll->GetBinContent(f1DcorrectionsAll->FindFixBin(tAodTrack->Pt())));
}
else if (f4DcorrectionsAll) {
Int_t idx[4] = {f4DcorrectionsAll->GetAxis(0)->FindFixBin(tAodTrack->Eta()),
f4DcorrectionsAll->GetAxis(1)->FindFixBin(tAodTrack->Pt()),
f4DcorrectionsAll->GetAxis(2)->FindFixBin(tAodTrack->Zv()),
f4DcorrectionsAll->GetAxis(3)->FindFixBin(tAodTrack->Phi())};
if (f4DcorrectionsAll->GetBinContent(idx) != 0) {
tFemtoTrack->SetCorrectionAll(f4DcorrectionsAll->GetBinContent(idx));
} else {
tFemtoTrack->SetCorrectionAll(1.0);
}
}
else {
tFemtoTrack->SetCorrectionAll(1.0);
}
/*******************************************************************/
//
if (f1DcorrectionsDeuterons) {
tFemtoTrack->SetCorrectionDeuteron(f1DcorrectionsDeuterons->GetBinContent(f1DcorrectionsDeuterons->FindFixBin(tAodTrack->Pt())));
} else {
tFemtoTrack->SetCorrectionDeuteron(1.0);
}
if (f1DcorrectionsTritons) {
tFemtoTrack->SetCorrectionTriton(f1DcorrectionsTritons->GetBinContent(f1DcorrectionsTritons->FindFixBin(tAodTrack->Pt())));
} else {
tFemtoTrack->SetCorrectionTriton(1.0);
}
if (f1DcorrectionsHe3s) {
tFemtoTrack->SetCorrectionHe3(f1DcorrectionsHe3s->GetBinContent(f1DcorrectionsHe3s->FindFixBin(tAodTrack->Pt())));
} else {
tFemtoTrack->SetCorrectionHe3(1.0);
}
if (f1DcorrectionsAlphas) {
tFemtoTrack->SetCorrectionAlpha(f1DcorrectionsAlphas->GetBinContent(f1DcorrectionsAlphas->FindFixBin(tAodTrack->Pt())));
} else {
tFemtoTrack->SetCorrectionAlpha(1.0);
}
if (f1DcorrectionsDeuteronsMinus) {
tFemtoTrack->SetCorrectionDeuteronMinus(f1DcorrectionsDeuteronsMinus->GetBinContent(f1DcorrectionsDeuteronsMinus->FindFixBin(tAodTrack->Pt())));
} else {
tFemtoTrack->SetCorrectionDeuteronMinus(1.0);
}
if (f1DcorrectionsTritonsMinus) {
tFemtoTrack->SetCorrectionTritonMinus(f1DcorrectionsTritonsMinus->GetBinContent(f1DcorrectionsTritonsMinus->FindFixBin(tAodTrack->Pt())));
} else {
tFemtoTrack->SetCorrectionTritonMinus(1.0);
}
if (f1DcorrectionsHe3sMinus) {
tFemtoTrack->SetCorrectionHe3Minus(f1DcorrectionsHe3sMinus->GetBinContent(f1DcorrectionsHe3sMinus->FindFixBin(tAodTrack->Pt())));
} else {
tFemtoTrack->SetCorrectionHe3Minus(1.0);
}
if (f1DcorrectionsAlphasMinus) {
tFemtoTrack->SetCorrectionAlphaMinus(f1DcorrectionsAlphasMinus->GetBinContent(f1DcorrectionsAlphasMinus->FindFixBin(tAodTrack->Pt())));
} else {
tFemtoTrack->SetCorrectionAlphaMinus(1.0);
}
//
/*******************************************************************/
return tFemtoTrack;
}
AliFemtoV0 *AliFemtoEventReaderAOD::CopyAODtoFemtoV0(AliAODv0 *tAODv0)
{
AliFemtoV0 *tFemtoV0 = new AliFemtoV0();
tFemtoV0->SetdecayLengthV0(tAODv0->DecayLength(fV1));
tFemtoV0->SetdecayVertexV0X(tAODv0->DecayVertexV0X());
tFemtoV0->SetdecayVertexV0Y(tAODv0->DecayVertexV0Y());
tFemtoV0->SetdecayVertexV0Z(tAODv0->DecayVertexV0Z());
AliFemtoThreeVector decayvertex(tAODv0->DecayVertexV0X(), tAODv0->DecayVertexV0Y(), tAODv0->DecayVertexV0Z());
tFemtoV0->SetdecayVertexV0(decayvertex);
tFemtoV0->SetdcaV0Daughters(tAODv0->DcaV0Daughters());
tFemtoV0->SetdcaV0ToPrimVertex(tAODv0->DcaV0ToPrimVertex());
tFemtoV0->SetdcaPosToPrimVertex(tAODv0->DcaPosToPrimVertex());
tFemtoV0->SetdcaNegToPrimVertex(tAODv0->DcaNegToPrimVertex());
tFemtoV0->SetmomPosX(tAODv0->MomPosX());
tFemtoV0->SetmomPosY(tAODv0->MomPosY());
tFemtoV0->SetmomPosZ(tAODv0->MomPosZ());
AliFemtoThreeVector mompos(tAODv0->MomPosX(), tAODv0->MomPosY(), tAODv0->MomPosZ());
tFemtoV0->SetmomPos(mompos);
tFemtoV0->SetmomNegX(tAODv0->MomNegX());
tFemtoV0->SetmomNegY(tAODv0->MomNegY());
tFemtoV0->SetmomNegZ(tAODv0->MomNegZ());
AliFemtoThreeVector momneg(tAODv0->MomNegX(), tAODv0->MomNegY(), tAODv0->MomNegZ());
tFemtoV0->SetmomNeg(momneg);
tFemtoV0->SetradiusV0(tAODv0->RadiusV0());
tFemtoV0->SetprimaryVertex(fV1);
//jest cos takiego w AliFemtoV0.h czego nie ma w AliAODv0.h
//void SettpcHitsPos(const int& i);
//void SettpcHitsNeg(const int& i);
//void SetTrackTopologyMapPos(unsigned int word, const unsigned long& m);
//void SetTrackTopologyMapNeg(unsigned int word, const unsigned long& m);
tFemtoV0->SetmomV0X(tAODv0->MomV0X());
tFemtoV0->SetmomV0Y(tAODv0->MomV0Y());
tFemtoV0->SetmomV0Z(tAODv0->MomV0Z());
AliFemtoThreeVector momv0(tAODv0->MomV0X(), tAODv0->MomV0Y(), tAODv0->MomV0Z());
tFemtoV0->SetmomV0(momv0);
tFemtoV0->SetalphaV0(tAODv0->AlphaV0());
tFemtoV0->SetptArmV0(tAODv0->PtArmV0());
tFemtoV0->SeteLambda(tAODv0->ELambda());
tFemtoV0->SeteK0Short(tAODv0->EK0Short());
tFemtoV0->SetePosProton(tAODv0->EPosProton());
tFemtoV0->SeteNegProton(tAODv0->ENegProton());
tFemtoV0->SetmassLambda(tAODv0->MassLambda());
tFemtoV0->SetmassAntiLambda(tAODv0->MassAntiLambda());
tFemtoV0->SetmassK0Short(tAODv0->MassK0Short());
tFemtoV0->SetrapLambda(tAODv0->RapLambda());
tFemtoV0->SetrapK0Short(tAODv0->RapK0Short());
//void SetcTauLambda( float x);
//void SetcTauK0Short( float x);
//tFemtoV0->SetptV0(::sqrt(tAODv0->Pt2V0())); //!
tFemtoV0->SetptV0(tAODv0->Pt());
if (f1DcorrectionsLambdas) {
tFemtoV0->SetCorrectionLambdas(f1DcorrectionsLambdas->GetBinContent(f1DcorrectionsLambdas->FindFixBin(tAODv0->Pt())));
}
else if (f4DcorrectionsLambdas) {
Int_t idx[4] = {f4DcorrectionsLambdas->GetAxis(0)->FindFixBin(tAODv0->Eta()),
f4DcorrectionsLambdas->GetAxis(1)->FindFixBin(tAODv0->Pt()),
f4DcorrectionsLambdas->GetAxis(2)->FindFixBin(tAODv0->Zv()),
f4DcorrectionsLambdas->GetAxis(3)->FindFixBin(tAODv0->Phi())};
if (f4DcorrectionsLambdas->GetBinContent(idx) != 0) {
tFemtoV0->SetCorrectionLambdas(1. / f4DcorrectionsLambdas->GetBinContent(idx));
} else {
tFemtoV0->SetCorrectionLambdas(1.0);
}
}
else {
tFemtoV0->SetCorrectionLambdas(1.0);
}
if (f1DcorrectionsLambdasMinus) {
tFemtoV0->SetCorrectionLambdasMinus(f1DcorrectionsLambdasMinus->GetBinContent(f1DcorrectionsLambdasMinus->FindFixBin(tAODv0->Pt())));
}
else if (f4DcorrectionsLambdasMinus) {
Int_t idx[4] = {f4DcorrectionsLambdasMinus->GetAxis(0)->FindFixBin(tAODv0->Eta()),
f4DcorrectionsLambdasMinus->GetAxis(1)->FindFixBin(tAODv0->Pt()),
f4DcorrectionsLambdasMinus->GetAxis(2)->FindFixBin(tAODv0->Zv()),
f4DcorrectionsLambdasMinus->GetAxis(3)->FindFixBin(tAODv0->Phi())};
if (f4DcorrectionsLambdasMinus->GetBinContent(idx) != 0) {
tFemtoV0->SetCorrectionLambdasMinus(1. / f4DcorrectionsLambdasMinus->GetBinContent(idx));
} else {
tFemtoV0->SetCorrectionLambdasMinus(1.0);
}
}
else {
tFemtoV0->SetCorrectionLambdasMinus(1.0);
}
tFemtoV0->SetptotV0(::sqrt(tAODv0->Ptot2V0()));
//tFemtoV0->SetptPos(::sqrt(tAODv0->MomPosX()*tAODv0->MomPosX()+tAODv0->MomPosY()*tAODv0->MomPosY()));
//tFemtoV0->SetptotPos(::sqrt(tAODv0->Ptot2Pos()));
//tFemtoV0->SetptNeg(::sqrt(tAODv0->MomNegX()*tAODv0->MomNegX()+tAODv0->MomNegY()*tAODv0->MomNegY()));
//tFemtoV0->SetptotNeg(::sqrt(tAODv0->Ptot2Neg()));
tFemtoV0->SetidNeg(tAODv0->GetNegID());
//cout<<"tAODv0->GetNegID(): "<<tAODv0->GetNegID()<<endl;
//cout<<"tFemtoV0->IdNeg(): "<<tFemtoV0->IdNeg()<<endl;
tFemtoV0->SetidPos(tAODv0->GetPosID());
tFemtoV0->SetEtaV0(tAODv0->Eta());
tFemtoV0->SetPhiV0(tAODv0->Phi());
tFemtoV0->SetCosPointingAngle(tAODv0->CosPointingAngle(fV1));
//tFemtoV0->SetYV0(tAODv0->Y());
//void SetdedxNeg(float x);
//void SeterrdedxNeg(float x);//Gael 04Fev2002
//void SetlendedxNeg(float x);//Gael 04Fev2002
//void SetdedxPos(float x);
//void SeterrdedxPos(float x);//Gael 04Fev2002
//void SetlendedxPos(float x);//Gael 04Fev2002
//tFemtoV0->SetEtaPos(tAODv0->PseudoRapPos());
//tFemtoV0->SetEtaNeg(tAODv0->PseudoRapNeg());
AliAODTrack *trackpos = (AliAODTrack *)tAODv0->GetDaughter(0);
AliAODTrack *trackneg = (AliAODTrack *)tAODv0->GetDaughter(1);
// ensure that trackpos and trackneg are pointing to the correct children
// This confusion seems to arise when fOnFlyStatusV0 = true
if (trackpos->Charge() < 0 && trackneg->Charge() > 0) {
AliAODTrack *tmp = trackpos;
trackpos = trackneg;
trackneg = tmp;
}
if (trackpos && trackneg) {
tFemtoV0->SetEtaPos(trackpos->Eta());
tFemtoV0->SetEtaNeg(trackneg->Eta());
tFemtoV0->SetptotPos(tAODv0->PProng(0));
tFemtoV0->SetptotNeg(tAODv0->PProng(1));
tFemtoV0->SetptPos(trackpos->Pt());
tFemtoV0->SetptNeg(trackneg->Pt());
//tFemtoV0->SetEtaPos(trackpos->Eta()); //tAODv0->PseudoRapPos()
//tFemtoV0->SetEtaNeg(trackneg->Eta()); //tAODv0->PseudoRapNeg()
tFemtoV0->SetTPCNclsPos(trackpos->GetTPCNcls());
tFemtoV0->SetTPCNclsNeg(trackneg->GetTPCNcls());
tFemtoV0->SetTPCclustersPos(trackpos->GetTPCClusterMap());
tFemtoV0->SetTPCclustersNeg(trackneg->GetTPCClusterMap());
tFemtoV0->SetTPCsharingPos(trackpos->GetTPCSharedMap());
tFemtoV0->SetTPCsharingNeg(trackneg->GetTPCSharedMap());
tFemtoV0->SetNdofPos(trackpos->Chi2perNDF());
tFemtoV0->SetNdofNeg(trackneg->Chi2perNDF());
tFemtoV0->SetStatusPos(trackpos->GetStatus());
tFemtoV0->SetStatusNeg(trackneg->GetStatus());
tFemtoV0->SetPosNSigmaTPCK(fAODpidUtil->NumberOfSigmasTPC(trackpos, AliPID::kKaon));
tFemtoV0->SetNegNSigmaTPCK(fAODpidUtil->NumberOfSigmasTPC(trackneg, AliPID::kKaon));
tFemtoV0->SetPosNSigmaTPCP(fAODpidUtil->NumberOfSigmasTPC(trackpos, AliPID::kProton));
tFemtoV0->SetNegNSigmaTPCP(fAODpidUtil->NumberOfSigmasTPC(trackneg, AliPID::kProton));
tFemtoV0->SetPosNSigmaTPCPi(fAODpidUtil->NumberOfSigmasTPC(trackpos, AliPID::kPion));
tFemtoV0->SetNegNSigmaTPCPi(fAODpidUtil->NumberOfSigmasTPC(trackneg, AliPID::kPion));
float bfield = 5 * fMagFieldSign;
float globalPositionsAtRadiiPos[9][3];
GetGlobalPositionAtGlobalRadiiThroughTPC(trackpos, bfield, globalPositionsAtRadiiPos);
double tpcEntrancePos[3] = {globalPositionsAtRadiiPos[0][0], globalPositionsAtRadiiPos[0][1], globalPositionsAtRadiiPos[0][2]};
double tpcExitPos[3] = {globalPositionsAtRadiiPos[8][0], globalPositionsAtRadiiPos[8][1], globalPositionsAtRadiiPos[8][2]};
float globalPositionsAtRadiiNeg[9][3];
GetGlobalPositionAtGlobalRadiiThroughTPC(trackneg, bfield, globalPositionsAtRadiiNeg);
double tpcEntranceNeg[3] = {globalPositionsAtRadiiNeg[0][0], globalPositionsAtRadiiNeg[0][1], globalPositionsAtRadiiNeg[0][2]};
double tpcExitNeg[3] = {globalPositionsAtRadiiNeg[8][0], globalPositionsAtRadiiNeg[8][1], globalPositionsAtRadiiNeg[8][2]};
if (fPrimaryVertexCorrectionTPCPoints) {
tpcEntrancePos[0] -= fV1[0];
tpcEntrancePos[1] -= fV1[1];
tpcEntrancePos[2] -= fV1[2];
tpcExitPos[0] -= fV1[0];
tpcExitPos[1] -= fV1[1];
tpcExitPos[2] -= fV1[2];
tpcEntranceNeg[0] -= fV1[0];
tpcEntranceNeg[1] -= fV1[1];
tpcEntranceNeg[2] -= fV1[2];
tpcExitNeg[0] -= fV1[0];
tpcExitNeg[1] -= fV1[1];
tpcExitNeg[2] -= fV1[2];
}
AliFemtoThreeVector tmpVec;
tmpVec.SetX(tpcEntrancePos[0]);
tmpVec.SetY(tpcEntrancePos[1]);
tmpVec.SetZ(tpcEntrancePos[2]);
tFemtoV0->SetNominalTpcEntrancePointPos(tmpVec);
tmpVec.SetX(tpcExitPos[0]);
tmpVec.SetY(tpcExitPos[1]);
tmpVec.SetZ(tpcExitPos[2]);
tFemtoV0->SetNominalTpcExitPointPos(tmpVec);
tmpVec.SetX(tpcEntranceNeg[0]);
tmpVec.SetY(tpcEntranceNeg[1]);
tmpVec.SetZ(tpcEntranceNeg[2]);
tFemtoV0->SetNominalTpcEntrancePointNeg(tmpVec);
tmpVec.SetX(tpcExitNeg[0]);
tmpVec.SetY(tpcExitNeg[1]);
tmpVec.SetZ(tpcExitNeg[2]);
tFemtoV0->SetNominalTpcExitPointNeg(tmpVec);
AliFemtoThreeVector vecTpcPos[9];
AliFemtoThreeVector vecTpcNeg[9];
for (int i = 0; i < 9; i++) {
vecTpcPos[i].SetX(globalPositionsAtRadiiPos[i][0]);
vecTpcPos[i].SetY(globalPositionsAtRadiiPos[i][1]);
vecTpcPos[i].SetZ(globalPositionsAtRadiiPos[i][2]);
vecTpcNeg[i].SetX(globalPositionsAtRadiiNeg[i][0]);
vecTpcNeg[i].SetY(globalPositionsAtRadiiNeg[i][1]);
vecTpcNeg[i].SetZ(globalPositionsAtRadiiNeg[i][2]);
}
if (fPrimaryVertexCorrectionTPCPoints) {
AliFemtoThreeVector tmpVertexVec;
tmpVertexVec.SetX(fV1[0]);
tmpVertexVec.SetY(fV1[1]);
tmpVertexVec.SetZ(fV1[2]);
for (int i = 0; i < 9; i++) {
vecTpcPos[i] -= tmpVertexVec;
vecTpcNeg[i] -= tmpVertexVec;
}
}
tFemtoV0->SetNominalTpcPointPos(vecTpcPos);
tFemtoV0->SetNominalTpcPointNeg(vecTpcNeg);
if (fShiftPosition > 0.) {
Float_t posShiftedPos[3];
Float_t posShiftedNeg[3];
SetShiftedPositions(trackpos, bfield, posShiftedPos, fShiftPosition);
SetShiftedPositions(trackneg, bfield, posShiftedNeg, fShiftPosition);
AliFemtoThreeVector tmpVecPos;
AliFemtoThreeVector tmpVecNeg;
tmpVecPos.SetX(posShiftedPos[0]);
tmpVecPos.SetY(posShiftedPos[1]);
tmpVecPos.SetZ(posShiftedPos[2]);
tmpVecNeg.SetX(posShiftedNeg[0]);
tmpVecNeg.SetY(posShiftedNeg[1]);
tmpVecNeg.SetZ(posShiftedNeg[2]);
tFemtoV0->SetNominalTpcPointPosShifted(tmpVecPos);
tFemtoV0->SetNominalTpcPointNegShifted(tmpVecNeg);
}
tFemtoV0->SetTPCMomentumPos(trackpos->GetTPCmomentum());
tFemtoV0->SetTPCMomentumNeg(trackneg->GetTPCmomentum());
tFemtoV0->SetdedxPos(trackpos->GetTPCsignal());
tFemtoV0->SetdedxNeg(trackneg->GetTPCsignal());
Float_t probMisPos = 1.0;
Float_t probMisNeg = 1.0;
if (((tFemtoV0->StatusPos() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoV0->StatusPos() & AliVTrack::kTIME) == AliVTrack::kTIME)) {
// if (tFemtoV0->StatusPos() & AliESDtrack::kTOFout & AliESDtrack::kTIME) { //AliESDtrack::kTOFpid=0x8000
probMisPos = fAODpidUtil->GetTOFMismatchProbability(trackpos);
}
if (((tFemtoV0->StatusNeg() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoV0->StatusNeg() & AliVTrack::kTIME) == AliVTrack::kTIME)) {
// if (tFemtoV0->StatusNeg() & AliESDtrack::kTOFout & AliESDtrack::kTIME) { //AliESDtrack::kTOFpid=0x8000
probMisNeg = fAODpidUtil->GetTOFMismatchProbability(trackneg);
}
// if(// (tFemtoV0->StatusPos()& AliESDtrack::kTOFpid)==0 ||
// (tFemtoV0->StatusPos()&AliESDtrack::kTIME)==0 || (tFemtoV0->StatusPos()&AliESDtrack::kTOFout)==0 || probMisPos > 0.01)
if (!(((tFemtoV0->StatusPos() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoV0->StatusPos() & AliVTrack::kTIME) == AliVTrack::kTIME))
|| probMisPos > 0.01) {
// if(// (tFemtoV0->StatusNeg()&AliESDtrack::kTOFpid)==0 ||
// (tFemtoV0->StatusNeg()&AliESDtrack::kTIME)==0 || (tFemtoV0->StatusNeg()&AliESDtrack::kTOFout)==0 || probMisNeg > 0.01)
if (!(((tFemtoV0->StatusNeg() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoV0->StatusNeg() & AliVTrack::kTIME) == AliVTrack::kTIME))
|| probMisNeg > 0.01) {
tFemtoV0->SetPosNSigmaTOFK(-1000);
tFemtoV0->SetNegNSigmaTOFK(-1000);
tFemtoV0->SetPosNSigmaTOFP(-1000);
tFemtoV0->SetNegNSigmaTOFP(-1000);
tFemtoV0->SetPosNSigmaTOFPi(-1000);
tFemtoV0->SetNegNSigmaTOFPi(-1000);
tFemtoV0->SetTOFProtonTimePos(-1000);
tFemtoV0->SetTOFPionTimePos(-1000);
tFemtoV0->SetTOFKaonTimePos(-1000);
tFemtoV0->SetTOFProtonTimeNeg(-1000);
tFemtoV0->SetTOFPionTimeNeg(-1000);
tFemtoV0->SetTOFKaonTimeNeg(-1000);
}
} else {
if (((tFemtoV0->StatusPos() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoV0->StatusPos() & AliVTrack::kTIME) == AliVTrack::kTIME)
&& probMisPos < 0.01) {
// if(trackpos->IsOn(AliESDtrack::kTOFout & AliESDtrack::kTIME)) {
tFemtoV0->SetPosNSigmaTOFK(fAODpidUtil->NumberOfSigmasTOF(trackpos, AliPID::kKaon));
tFemtoV0->SetPosNSigmaTOFP(fAODpidUtil->NumberOfSigmasTOF(trackpos, AliPID::kProton));
tFemtoV0->SetPosNSigmaTOFPi(fAODpidUtil->NumberOfSigmasTOF(trackpos, AliPID::kPion));
}
if (((tFemtoV0->StatusNeg() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoV0->StatusNeg() & AliVTrack::kTIME) == AliVTrack::kTIME)
&& probMisNeg < 0.01) {
// if(trackneg->IsOn(AliESDtrack::kTOFout & AliESDtrack::kTIME)) {
tFemtoV0->SetNegNSigmaTOFK(fAODpidUtil->NumberOfSigmasTOF(trackneg, AliPID::kKaon));
tFemtoV0->SetNegNSigmaTOFP(fAODpidUtil->NumberOfSigmasTOF(trackneg, AliPID::kProton));
tFemtoV0->SetNegNSigmaTOFPi(fAODpidUtil->NumberOfSigmasTOF(trackneg, AliPID::kPion));
}
double TOFSignalPos = trackpos->GetTOFsignal();
double TOFSignalNeg = trackneg->GetTOFsignal();
TOFSignalPos -= fAODpidUtil->GetTOFResponse().GetStartTime(trackpos->P());
TOFSignalNeg -= fAODpidUtil->GetTOFResponse().GetStartTime(trackneg->P());
double pidPos[5];
double pidNeg[5];
trackpos->GetIntegratedTimes(pidPos);
trackneg->GetIntegratedTimes(pidNeg);
tFemtoV0->SetTOFPionTimePos(TOFSignalPos - pidPos[2]);
tFemtoV0->SetTOFKaonTimePos(TOFSignalPos - pidPos[3]);
tFemtoV0->SetTOFProtonTimePos(TOFSignalPos - pidPos[4]);
tFemtoV0->SetTOFPionTimeNeg(TOFSignalNeg - pidNeg[2]);
tFemtoV0->SetTOFKaonTimeNeg(TOFSignalNeg - pidNeg[3]);
tFemtoV0->SetTOFProtonTimeNeg(TOFSignalNeg - pidNeg[4]);
}
} else {
tFemtoV0->SetStatusPos(999);
tFemtoV0->SetStatusNeg(999);
}
tFemtoV0->SetOnFlyStatusV0(tAODv0->GetOnFlyStatus());
return tFemtoV0;
}
AliFemtoXi *AliFemtoEventReaderAOD::CopyAODtoFemtoXi(AliAODcascade *tAODxi)
{
AliFemtoXi *tFemtoXi = nullptr;
{ // this is to keep tmpV0 in its own scope
AliFemtoV0 *tmpV0 = CopyAODtoFemtoV0(tAODxi);
tFemtoXi = new AliFemtoXi(tmpV0);
delete tmpV0;
}
//The above lines set the V0 attributes. However, some of these are now set incorrectly
//For instance:
// tFemtoV0->SetdecayLengthV0(tAODv0->DecayLength(fV1)); in CopyAODtoFemtoXi now sets the decay length
// of the V0 roughly equal to the decay length of the cascade + decay length of V0
// This is fixed by:
// tFemtoXi->SetdecayLengthV0(tAODv0->DecayLengthV0());
// Or:
// double temp[3];
// temp[0] = tAODxi->DecayVertexXiX();
// temp[1] = tAODxi->DecayVertexXiY();
// temp[2] = tAODxi->DecayVertexXiZ();
// tFemtoXi->SetdecayLengthV0(tAODxi->DecayLength(temp));
//-- Include any fixes to V0 attributes set in CopyAODtoFemtoXi
tFemtoXi->SetdecayLengthV0(tAODxi->DecayLengthV0());
//xi
tFemtoXi->SetmassXi(tAODxi->MassXi());
tFemtoXi->SetmassOmega(tAODxi->MassOmega());
tFemtoXi->SetdecayLengthXi(tAODxi->DecayLengthXi(fV1[0], fV1[1], fV1[2]));
tFemtoXi->SetdecayVertexXiX(tAODxi->DecayVertexXiX());
tFemtoXi->SetdecayVertexXiY(tAODxi->DecayVertexXiY());
tFemtoXi->SetdecayVertexXiZ(tAODxi->DecayVertexXiZ());
tFemtoXi->SetdcaXiDaughters(tAODxi->DcaXiDaughters());
//tFemtoXi->SetdcaXiToPrimVertex(tAODxi->DcaXiToPrimVertex()); //This doesn't work because fDcaXiToPrimVertex was not set
tFemtoXi->SetdcaXiToPrimVertex(tAODxi->DcaXiToPrimVertex(fV1[0], fV1[1], fV1[2]));
tFemtoXi->SetdcaBacToPrimVertex(tAODxi->DcaBachToPrimVertex());
tFemtoXi->SetmomBacX(tAODxi->MomBachX());
tFemtoXi->SetmomBacY(tAODxi->MomBachY());
tFemtoXi->SetmomBacZ(tAODxi->MomBachZ());
tFemtoXi->SetmomXiX(tAODxi->MomXiX());
tFemtoXi->SetmomXiY(tAODxi->MomXiY());
tFemtoXi->SetmomXiZ(tAODxi->MomXiZ());
AliFemtoThreeVector momxi(tAODxi->MomXiX(), tAODxi->MomXiY(), tAODxi->MomXiZ());
tFemtoXi->SetmomXi(momxi);
tFemtoXi->SetRadiusXi(TMath::Sqrt(tAODxi->DecayVertexXiX() * tAODxi->DecayVertexXiX()
+ tAODxi->DecayVertexXiY() * tAODxi->DecayVertexXiY()));
tFemtoXi->SetidBac(tAODxi->GetBachID());
double tEtaXi = 0.5 * TMath::Log((TMath::Sqrt(tAODxi->Ptot2Xi()) + tAODxi->MomXiZ())
/ (TMath::Sqrt(tAODxi->Ptot2Xi()) - tAODxi->MomXiZ() + 1.e-13));
tFemtoXi->SetEtaXi(tEtaXi);
double tPhiXi = TMath::Pi() + TMath::ATan2(-tAODxi->MomXiY(), -tAODxi->MomXiX());
tFemtoXi->SetPhiXi(tPhiXi);
tFemtoXi->SetCosPointingAngleXi(tAODxi->CosPointingAngleXi(fV1[0], fV1[1], fV1[2]));
tFemtoXi->SetCosPointingAngleV0toXi(tAODxi->CosPointingAngle(tAODxi->GetDecayVertexXi()));
tFemtoXi->SetChargeXi(tAODxi->ChargeXi());
tFemtoXi->SetptXi(std::sqrt(tAODxi->Pt2Xi()));
if (f1DcorrectionsXiPlus) {
tFemtoXi->SetCorrectionXiPlus(f1DcorrectionsXiPlus->GetBinContent(f1DcorrectionsXiPlus->FindFixBin(tAODxi->Pt())));
}
if (f1DcorrectionsXiMinus) {
tFemtoXi->SetCorrectionXiMinus(f1DcorrectionsXiMinus->GetBinContent(f1DcorrectionsXiMinus->FindFixBin(tAODxi->Pt())));
}
AliAODTrack *trackbac = (AliAODTrack *)tAODxi->GetDecayVertexXi()->GetDaughter(0);
if (trackbac) {
tFemtoXi->SetptBac(trackbac->Pt()); //setting pt? px and py was set!
tFemtoXi->SetEtaBac(trackbac->Eta()); //bac!
tFemtoXi->SetTPCNclsBac(trackbac->GetTPCNcls()); //bac!
tFemtoXi->SetNdofBac(trackbac->Chi2perNDF()); //bac!
tFemtoXi->SetStatusBac(trackbac->GetStatus()); //bac!
tFemtoXi->SetBacNSigmaTPCK(fAODpidUtil->NumberOfSigmasTPC(trackbac, AliPID::kKaon));
tFemtoXi->SetBacNSigmaTPCP(fAODpidUtil->NumberOfSigmasTPC(trackbac, AliPID::kProton));
tFemtoXi->SetBacNSigmaTPCPi(fAODpidUtil->NumberOfSigmasTPC(trackbac, AliPID::kPion));
//NEED TO ADD:
// tFemtoXi->SetNominalTpcEntrancePointBac(tmpVec);
// tFemtoXi->SetNominalTpcExitPointBac(tmpVec);
// tFemtoXi->SetNominalTpcPointBac(vecTpcPos);
// tFemtoXi->SetTPCMomentumBac(trackbac->GetTPCmomentum());
// if (fShiftPosition > 0.)
float bfield = 5 * fMagFieldSign;
float globalPositionsAtRadiiBac[9][3];
GetGlobalPositionAtGlobalRadiiThroughTPC(trackbac, bfield, globalPositionsAtRadiiBac);
double tpcEntranceBac[3] = {globalPositionsAtRadiiBac[0][0],
globalPositionsAtRadiiBac[0][1],
globalPositionsAtRadiiBac[0][2]};
double tpcExitBac[3] = {globalPositionsAtRadiiBac[8][0],
globalPositionsAtRadiiBac[8][1],
globalPositionsAtRadiiBac[8][2]};
if (fPrimaryVertexCorrectionTPCPoints) {
tpcEntranceBac[0] -= fV1[0];
tpcEntranceBac[1] -= fV1[1];
tpcEntranceBac[2] -= fV1[2];
tpcExitBac[0] -= fV1[0];
tpcExitBac[1] -= fV1[1];
tpcExitBac[2] -= fV1[2];
}
AliFemtoThreeVector tmpVec;
tmpVec.SetX(tpcEntranceBac[0]);
tmpVec.SetY(tpcEntranceBac[1]);
tmpVec.SetZ(tpcEntranceBac[2]);
tFemtoXi->SetNominalTpcEntrancePointBac(tmpVec);
tmpVec.SetX(tpcExitBac[0]);
tmpVec.SetY(tpcExitBac[1]);
tmpVec.SetZ(tpcExitBac[2]);
tFemtoXi->SetNominalTpcExitPointBac(tmpVec);
AliFemtoThreeVector vecTpcBac[9];
for (int i = 0; i < 9; i++) {
vecTpcBac[i].SetX(globalPositionsAtRadiiBac[i][0]);
vecTpcBac[i].SetY(globalPositionsAtRadiiBac[i][1]);
vecTpcBac[i].SetZ(globalPositionsAtRadiiBac[i][2]);
}
if (fPrimaryVertexCorrectionTPCPoints) {
AliFemtoThreeVector tmpVertexVec;
tmpVertexVec.SetX(fV1[0]);
tmpVertexVec.SetY(fV1[1]);
tmpVertexVec.SetZ(fV1[2]);
for (int i = 0; i < 9; i++) {
vecTpcBac[i] -= tmpVertexVec;
}
}
tFemtoXi->SetNominalTpcPointBac(vecTpcBac);
if (fShiftPosition > 0.) {
Float_t posShiftedBac[3];
SetShiftedPositions(trackbac, bfield, posShiftedBac, fShiftPosition);
AliFemtoThreeVector tmpVecBac;
tmpVecBac.SetX(posShiftedBac[0]);
tmpVecBac.SetY(posShiftedBac[1]);
tmpVecBac.SetZ(posShiftedBac[2]);
tFemtoXi->SetNominalTpcPointBacShifted(tmpVecBac);
}
tFemtoXi->SetTPCMomentumBac(trackbac->GetTPCmomentum());
tFemtoXi->SetdedxBac(trackbac->GetTPCsignal());
Float_t probMisBac = 1.0;
if (((tFemtoXi->StatusBac() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoXi->StatusBac() & AliVTrack::kTIME) == AliVTrack::kTIME)) {
// if (tFemtoXi->StatusBac() & AliESDtrack::kTOFout & AliESDtrack::kTIME) { //AliESDtrack::kTOFpid=0x8000
probMisBac = fAODpidUtil->GetTOFMismatchProbability(trackbac);
}
// if(// (tFemtoXi->StatusPos()& AliESDtrack::kTOFpid)==0 ||
// (tFemtoXi->StatusPos()&AliESDtrack::kTIME)==0 || (tFemtoXi->StatusPos()&AliESDtrack::kTOFout)==0 || probMisPos > 0.01)
if (!(((tFemtoXi->StatusBac() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoXi->StatusBac() & AliVTrack::kTIME) == AliVTrack::kTIME))
|| probMisBac > 0.01) {
tFemtoXi->SetBacNSigmaTOFK(-1000);
tFemtoXi->SetBacNSigmaTOFP(-1000);
tFemtoXi->SetBacNSigmaTOFPi(-1000);
tFemtoXi->SetTOFProtonTimeBac(-1000);
tFemtoXi->SetTOFPionTimeBac(-1000);
tFemtoXi->SetTOFKaonTimeBac(-1000);
} else {
if (((tFemtoXi->StatusBac() & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((tFemtoXi->StatusBac() & AliVTrack::kTIME) == AliVTrack::kTIME)
&& probMisBac < 0.01) {
tFemtoXi->SetBacNSigmaTOFK(fAODpidUtil->NumberOfSigmasTOF(trackbac, AliPID::kKaon));
tFemtoXi->SetBacNSigmaTOFP(fAODpidUtil->NumberOfSigmasTOF(trackbac, AliPID::kProton));
tFemtoXi->SetBacNSigmaTOFPi(fAODpidUtil->NumberOfSigmasTOF(trackbac, AliPID::kPion));
}
double TOFSignalBac = trackbac->GetTOFsignal();
TOFSignalBac -= fAODpidUtil->GetTOFResponse().GetStartTime(trackbac->P());
double pidBac[5];
trackbac->GetIntegratedTimes(pidBac);
tFemtoXi->SetTOFPionTimeBac(TOFSignalBac - pidBac[2]);
tFemtoXi->SetTOFKaonTimeBac(TOFSignalBac - pidBac[3]);
tFemtoXi->SetTOFProtonTimeBac(TOFSignalBac - pidBac[4]);
}
} else {
tFemtoXi->SetStatusBac(999);
}
return tFemtoXi;
}
void AliFemtoEventReaderAOD::SetFilterBit(UInt_t ibit)
{
fFilterBit = (1 << (ibit));
}
void AliFemtoEventReaderAOD::SetFilterMask(int ibit)
{
fFilterMask = ibit;
}
void AliFemtoEventReaderAOD::SetReadMC(unsigned char a)
{
fReadMC = a;
}
void AliFemtoEventReaderAOD::SetReadV0(unsigned char a)
{
fReadV0 = a;
}
void AliFemtoEventReaderAOD::SetReadCascade(unsigned char a)
{
fReadCascade = a;
}
void AliFemtoEventReaderAOD::SetUseMultiplicity(EstEventMult aType)
{
fEstEventMult = aType;
}
AliAODMCParticle *AliFemtoEventReaderAOD::GetParticleWithLabel(TClonesArray *mcP, Int_t aLabel)
{
if (aLabel < 0) {
return nullptr;
}
Int_t posstack = TMath::Min(aLabel, mcP->GetEntries());
AliAODMCParticle *aodP = static_cast<AliAODMCParticle *>(mcP->At(posstack));
if (aodP->GetLabel() > posstack) {
do {
aodP = static_cast<AliAODMCParticle *>(mcP->At(posstack));
if (aodP->GetLabel() == aLabel) {
return aodP;
}
posstack--;
} while (posstack > 0);
} else {
do {
aodP = static_cast<AliAODMCParticle *>(mcP->At(posstack));
if (aodP->GetLabel() == aLabel) {
return aodP;
}
posstack++;
} while (posstack < mcP->GetEntries());
}
return nullptr;
}
void AliFemtoEventReaderAOD::CopyPIDtoFemtoTrack(const AliAODTrack *tAodTrack, AliFemtoTrack *tFemtoTrack)
{
// A cache which maps vertices to the number of tracks used to determine the vertex
// Added due to slow calculation in AliAODVertex::GetNContributors - if that changes, remove this.
static std::map<Short_t, Int_t> _vertex_NContributors_cache;
if (fDCAglobalTrack == 1) {
// code from Michael and Prabhat from AliAnalysisTaskDptDptCorrelations
auto *vertex = static_cast<const AliAODVertex *>(fEvent->GetPrimaryVertex());
float vertexX = -999.;
float vertexY = -999.;
float vertexZ = -999.;
if (vertex) {
Double_t fCov[6] = {0.0};
vertex->GetCovarianceMatrix(fCov);
if (fCov[5] != 0.0) {
vertexX = vertex->GetX();
vertexY = vertex->GetY();
vertexZ = vertex->GetZ();
}
}
Double_t pos[3];
tAodTrack->GetXYZ(pos);
Double_t DCAX = pos[0] - vertexX;
Double_t DCAY = pos[1] - vertexY;
Double_t DCAZ = pos[2] - vertexZ;
Double_t DCAXY = TMath::Sqrt((DCAX * DCAX) + (DCAY * DCAY));
tFemtoTrack->SetImpactD(DCAXY);
tFemtoTrack->SetImpactZ(DCAZ);
tFemtoTrack->SetXatDCA(pos[0]);
tFemtoTrack->SetYatDCA(pos[1]);
tFemtoTrack->SetZatDCA(pos[2]);
} else if (fDCAglobalTrack == 2) {
Double_t DCAXY = -999;
Double_t DCAZ = -999;
//DCA for TPC only - from PropagateToDCA method
AliExternalTrackParam aliextparam;
aliextparam.CopyFromVTrack(tAodTrack);
if (aliextparam.GetX() > 3.0) {
DCAXY = -999;
DCAZ = -999;
} else {
Double_t covar[3] = {0, 0, 0};
Double_t DCA[2] = {0, 0};
if (!aliextparam.PropagateToDCA(fEvent->GetPrimaryVertex(), fEvent->GetMagneticField(), 99999.0, DCA, covar)) {
DCAXY = -999;
DCAZ = -999;
} else {
DCAXY = DCA[0];
DCAZ = DCA[1];
}
}
tFemtoTrack->SetImpactD(DCAXY);
tFemtoTrack->SetImpactZ(DCAZ);
}
double aodpid[10];
tAodTrack->GetPID(aodpid);
tFemtoTrack->SetPidProbElectron(aodpid[0]);
tFemtoTrack->SetPidProbMuon(aodpid[1]);
tFemtoTrack->SetPidProbPion(aodpid[2]);
tFemtoTrack->SetPidProbKaon(aodpid[3]);
tFemtoTrack->SetPidProbProton(aodpid[4]);
aodpid[0] = -100000.0;
aodpid[1] = -100000.0;
aodpid[2] = -100000.0;
aodpid[3] = -100000.0;
aodpid[4] = -100000.0;
double tTOF = 0.0;
Float_t probMis = 1.0;
//what is that code? for what do we need it? nsigma values are not enough?
// if (tAodTrack->GetStatus() & AliESDtrack::kTOFout & AliESDtrack::kTIME) { //AliESDtrack::kTOFpid=0x8000
ULong_t status = tAodTrack->GetStatus();
if (((status & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((status & AliVTrack::kTIME) == AliVTrack::kTIME))
{
tTOF = tAodTrack->GetTOFsignal();
tAodTrack->GetIntegratedTimes(aodpid);
tTOF -= fAODpidUtil->GetTOFResponse().GetStartTime(tAodTrack->P());
probMis = fAODpidUtil->GetTOFMismatchProbability(tAodTrack);
}
// tFemtoTrack->SetTOFsignal(tTOF);
tFemtoTrack->SetTOFsignal(tAodTrack->GetTOFsignal());
tFemtoTrack->SetTofExpectedTimes(tTOF - aodpid[2], tTOF - aodpid[3], tTOF - aodpid[4], tTOF);
////// TPC ////////////////////////////////////////////
const float nsigmaTPCK = fAODpidUtil->NumberOfSigmasTPC(tAodTrack, AliPID::kKaon);
const float nsigmaTPCPi = fAODpidUtil->NumberOfSigmasTPC(tAodTrack, AliPID::kPion);
const float nsigmaTPCP = fAODpidUtil->NumberOfSigmasTPC(tAodTrack, AliPID::kProton);
const float nsigmaTPCE = fAODpidUtil->NumberOfSigmasTPC(tAodTrack, AliPID::kElectron);
/*************************************************************************************/
const float nsigmaTPCD = fAODpidUtil->NumberOfSigmasTPC(tAodTrack, AliPID::kDeuteron);
const float nsigmaTPCT = fAODpidUtil->NumberOfSigmasTPC(tAodTrack, AliPID::kTriton);
const float nsigmaTPCH = fAODpidUtil->NumberOfSigmasTPC(tAodTrack, AliPID::kHe3);
const float nsigmaTPCA = fAODpidUtil->NumberOfSigmasTPC(tAodTrack, AliPID::kAlpha);
/*************************************************************************************/
tFemtoTrack->SetNSigmaTPCPi(nsigmaTPCPi);
tFemtoTrack->SetNSigmaTPCK(nsigmaTPCK);
tFemtoTrack->SetNSigmaTPCP(nsigmaTPCP);
tFemtoTrack->SetNSigmaTPCE(nsigmaTPCE);
/***************************************/
tFemtoTrack->SetNSigmaTPCD(nsigmaTPCD);
tFemtoTrack->SetNSigmaTPCT(nsigmaTPCT);
tFemtoTrack->SetNSigmaTPCH(nsigmaTPCH);
tFemtoTrack->SetNSigmaTPCA(nsigmaTPCA);
/****************************************/
tFemtoTrack->SetTPCsignalN(tAodTrack->GetTPCsignalN());
tFemtoTrack->SetTPCsignalS(1);
tFemtoTrack->SetTPCsignal(tAodTrack->GetTPCsignal());
tFemtoTrack->SetITSchi2(tAodTrack->GetITSchi2());
tFemtoTrack->SetITSncls(tAodTrack->GetITSNcls());
for (int ii = 0; ii < 6; ii++) {
tFemtoTrack->SetITSHitOnLayer(ii, tAodTrack->HasPointOnITSLayer(ii));
}
////// TOF ////////////////////////////////////////////
float vp = -1000.;
float nsigmaTOFPi = -1000.;
float nsigmaTOFK = -1000.;
float nsigmaTOFP = -1000.;
float nsigmaTOFE = -1000.;
/*****************************/
//
float nsigmaTOFD = -1000.;
float nsigmaTOFT = -1000.;
float nsigmaTOFH = -1000.;
float nsigmaTOFA = -1000.;
//
/*******************************/
Double_t trackLength = tAodTrack->GetIntegratedLength();
Double_t trackTime = tAodTrack->GetTOFsignal() - fAODpidUtil->GetTOFResponse().GetStartTime(tAodTrack->P());
if (((status & AliVTrack::kTOFout) == AliVTrack::kTOFout)
&& ((status & AliVTrack::kTIME) == AliVTrack::kTIME)
&& probMis < 0.01) {
nsigmaTOFPi = fAODpidUtil->NumberOfSigmasTOF(tAodTrack, AliPID::kPion);
nsigmaTOFK = fAODpidUtil->NumberOfSigmasTOF(tAodTrack, AliPID::kKaon);
nsigmaTOFP = fAODpidUtil->NumberOfSigmasTOF(tAodTrack, AliPID::kProton);
nsigmaTOFE = fAODpidUtil->NumberOfSigmasTOF(tAodTrack, AliPID::kElectron);
/********************************************************************/
nsigmaTOFD = fAODpidUtil->NumberOfSigmasTOF(tAodTrack, AliPID::kDeuteron);
nsigmaTOFT = fAODpidUtil->NumberOfSigmasTOF(tAodTrack, AliPID::kTriton);
nsigmaTOFH = fAODpidUtil->NumberOfSigmasTOF(tAodTrack, AliPID::kHe3);
nsigmaTOFA = fAODpidUtil->NumberOfSigmasTOF(tAodTrack, AliPID::kAlpha);
/*********************************************************************/
// double trackTime=tAodTrack->GetTOFsignal();
}
if (trackTime > 0. && trackLength > 0.) {
vp = trackLength / trackTime / 0.03;
tFemtoTrack->SetVTOF(vp);
double momentum = tFemtoTrack->P().Mag();
double massTof = momentum * momentum * (1 / (vp * vp) - 1);
tFemtoTrack->SetMassTOF(massTof);
}
tFemtoTrack->SetNSigmaTOFPi(nsigmaTOFPi);
tFemtoTrack->SetNSigmaTOFK(nsigmaTOFK);
tFemtoTrack->SetNSigmaTOFP(nsigmaTOFP);
tFemtoTrack->SetNSigmaTOFE(nsigmaTOFE);
/*****************************************/
tFemtoTrack->SetNSigmaTOFD(nsigmaTOFD);
tFemtoTrack->SetNSigmaTOFT(nsigmaTOFT);
tFemtoTrack->SetNSigmaTOFH(nsigmaTOFH);
tFemtoTrack->SetNSigmaTOFA(nsigmaTOFA);
/******************************************/
//////////////////////////////////////
}
void AliFemtoEventReaderAOD::SetCentralityPreSelection(double min, double max)
{
fCentRange[0] = min;
fCentRange[1] = max;
fUsePreCent = 1;
fEstEventMult = kCentrality;
}
void AliFemtoEventReaderAOD::SetNoCentrality(bool anocent)
{
if (anocent == false) {
fEstEventMult = kCentrality;
} else {
fEstEventMult = kReference;
fUsePreCent = 0;
}
}
void AliFemtoEventReaderAOD::SetAODpidUtil(AliAODpidUtil *aAODpidUtil)
{
fAODpidUtil = aAODpidUtil;
// printf("fAODpidUtil: %x\n",fAODpidUtil);
}
void AliFemtoEventReaderAOD::SetAODheader(AliAODHeader *aAODheader)
{
fAODheader = aAODheader;
}
void AliFemtoEventReaderAOD::SetMagneticFieldSign(int s)
{
if (s > 0)
fMagFieldSign = 1;
else if (s < 0)
fMagFieldSign = -1;
else
fMagFieldSign = 0;
}
void AliFemtoEventReaderAOD::SetEPVZERO(Bool_t iepvz)
{
fisEPVZ = iepvz;
}
void AliFemtoEventReaderAOD
::GetGlobalPositionAtGlobalRadiiThroughTPC(AliAODTrack *track,
Float_t bfield,
Float_t globalPositionsAtRadii[9][3])
{
// Gets the global position of the track at nine different radii in the TPC
// params:
// track - the track to propagate
// bfield - magnetic field of event
// globalPositionsAtRadii - Output array of global positions in the radii and xyz
const Float_t DEFAULT_VALUE = -9999.0;
// The radii at which we get the global positions
// IROC (OROC) from 84.1 cm to 132.1 cm (134.6 cm to 246.6 cm)
const Float_t Rwanted[9] = {85., 105., 125., 145., 165., 185., 205., 225., 245.};
// Make a copy of the track to not change parameters of the track
AliExternalTrackParam etp;
etp.CopyFromVTrack(track);
// index of global position we are filling
// - first we use AliExternalTrackParam, then just default value
Int_t radius_index = 0;
// loop over the array of radii
for (; radius_index < 9; radius_index++) {
// extracted radius
const Float_t radius = Rwanted[radius_index];
// buffer to store position
Double_t pos_buffer[3] = {0.0, 0.0, 0.0};
// get the global position of the track at this radial location
bool good = etp.GetXYZatR(radius, bfield, pos_buffer, nullptr);
// if value is not good, break loading loop
if (!good || fabs(AliFemtoThreeVector(pos_buffer).Perp() - radius) > 0.5) {
radius_index--; // decrement to fill current location with default value
break;
}
// store the global position
std::copy_n(pos_buffer, 3, globalPositionsAtRadii[radius_index]);
}
// Fill any remaining positions with the default value
for (; radius_index < 9; radius_index++) {
std::fill_n(globalPositionsAtRadii[radius_index], 3, DEFAULT_VALUE);
}
}
//________________________________________________________________________
void AliFemtoEventReaderAOD::SetShiftedPositions(const AliAODTrack *track,
const Float_t bfield,
Float_t posShifted[3],
const Double_t radius)
{
// Sets the spatial position of the track at the radius R=1.25m in
// the shifted coordinate system, code adapted from Hans Beck analysis
// Initialize the array to something indicating there was no propagation
posShifted[0] = -9999.; // THIS IS THE DATA MEMBER OF YOUR FEMTOTRACK
posShifted[1] = -9999.;
posShifted[2] = -9999.;
// Make a copy of the track to not change parameters of the track
AliExternalTrackParam etp;
etp.CopyFromVTrack(track);
// The global position of the the track
Double_t xyz[3] = {-9999., -9999., -9999.};
// The radius in cm we want to propagate to, squared
const Float_t RSquaredWanted(radius * radius * 1e4);
// Propagation is done in local x of the track
for (Float_t x = 58.; x < 247.; x += 1.) {
// Starts at 83 / Sqrt(2) and goes outwards. 85/Sqrt(2) is the smallest local x
// for global radius 85 cm. x = 245 is the outer radial limit of the TPC when
// the track is straight, i.e. has inifinite pt and doesn't get bent.
// If the track's momentum is smaller than infinite, it will develop a y-component,
// which adds to the global radius
// Stop if the propagation was not succesful. This can happen for low pt tracks
// that don't reach outer radii
if (!etp.PropagateTo(x, bfield)) {
break;
}
etp.GetXYZ(xyz); // GetXYZ returns global coordinates
// Calculate the shifted radius we are at, squared.
// Compare squared radii for faster code
Float_t shiftedRadiusSquared = (xyz[0] - fV1[0]) * (xyz[0] - fV1[0])
+ (xyz[1] - fV1[1]) * (xyz[1] - fV1[1]);
// Roughly reached the radius we want
if (shiftedRadiusSquared > RSquaredWanted) {
// Bigger loop has bad precision, we're nearly one centimeter too far,
// go back in small steps.
while (shiftedRadiusSquared > RSquaredWanted) {
// Propagate a mm inwards
x -= 0.1;
if (!etp.PropagateTo(x, bfield)) {
// Propagation failed but we're already with a
// cm precision at R=1.25m so we only break the
// inner loop
break;
}
// Get the global position
etp.GetXYZ(xyz);
// Calculate shifted radius, squared
shiftedRadiusSquared = (xyz[0] - fV1[0]) * (xyz[0] - fV1[0])
+ (xyz[1] - fV1[1]) * (xyz[1] - fV1[1]);
}
// We reached R=1.25m with a precission of a cm to a mm,
// set the spatial position
posShifted[0] = xyz[0] - fV1[0];
posShifted[1] = xyz[1] - fV1[1];
posShifted[2] = xyz[2] - fV1[2];
// Done
return;
} // End of if roughly reached radius
} // End of coarse propagation loop
}
void AliFemtoEventReaderAOD::SetUseAliEventCuts(Bool_t useAliEventCuts)
{
fUseAliEventCuts = useAliEventCuts;
fEventCuts = new AliEventCuts();
}
void AliFemtoEventReaderAOD::SetpA2013(Bool_t pa2013)
{
fpA2013 = pa2013;
}
void AliFemtoEventReaderAOD::SetUseMVPlpSelection(Bool_t mvplp)
{
fMVPlp = mvplp;
}
void AliFemtoEventReaderAOD::SetUseOutOfBunchPlpSelection(Bool_t outOfBunchPlp)
{
fOutOfBunchPlp = outOfBunchPlp;
}
void AliFemtoEventReaderAOD::SetIsPileUpEvent(Bool_t ispileup)
{
fisPileUp = ispileup;
}
void AliFemtoEventReaderAOD::SetCascadePileUpRemoval(Bool_t cascadePileUpRemoval)
{
fCascadePileUpRemoval = cascadePileUpRemoval;
}
void AliFemtoEventReaderAOD::SetV0PileUpRemoval(Bool_t v0PileUpRemoval)
{
fV0PileUpRemoval = v0PileUpRemoval;
}
void AliFemtoEventReaderAOD::SetTrackPileUpRemoval(Bool_t trackPileUpRemoval)
{
fTrackPileUpRemoval = trackPileUpRemoval;
}
void AliFemtoEventReaderAOD::SetDCAglobalTrack(Int_t dcagt)
{
fDCAglobalTrack = dcagt;
}
bool AliFemtoEventReaderAOD::RejectEventCentFlat(float MagField, float CentPercent)
{
// Flattens the centrality distribution
// Setting 0 as seed ensures random seed every time.
TRandom3 RNG(0); // for 3D, random sign switching
float kCentWeight[2][9] = {
{0.878, .876, .860, .859, .859, .880, .873, .879, .894},
{0.828, .793, .776, .772, .775, .796, .788, .804, .839}};
int weightBinCent = (int)CentPercent,
weightBinSign = (MagField > 0) ? 0 : 1;
bool rejectEvent = RNG.Rndm() > kCentWeight[weightBinSign][weightBinCent];
return rejectEvent;
}
void AliFemtoEventReaderAOD::SetCentralityFlattening(Bool_t dcagt)
{
fFlatCent = dcagt;
}
void AliFemtoEventReaderAOD::SetShiftPosition(Double_t dcagt)
{
fShiftPosition = dcagt;
}
void AliFemtoEventReaderAOD::SetPrimaryVertexCorrectionTPCPoints(bool correctTpcPoints)
{
fPrimaryVertexCorrectionTPCPoints = correctTpcPoints;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsPions(TH1D *h1)
{
f1DcorrectionsPions = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsKaons(TH1D *h1)
{
f1DcorrectionsKaons = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsProtons(TH1D *h1)
{
f1DcorrectionsProtons = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsPionsMinus(TH1D *h1)
{
f1DcorrectionsPionsMinus = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsKaonsMinus(TH1D *h1)
{
f1DcorrectionsKaonsMinus = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsProtonsMinus(TH1D *h1)
{
f1DcorrectionsProtonsMinus = h1;
}
/*************************************/
//
void AliFemtoEventReaderAOD::Set1DCorrectionsDeuterons(TH1D *h1)
{
f1DcorrectionsDeuterons = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsTritons(TH1D *h1)
{
f1DcorrectionsTritons = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsHe3s(TH1D *h1)
{
f1DcorrectionsHe3s = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsAlphas(TH1D *h1)
{
f1DcorrectionsAlphas = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsDeuteronsMinus(TH1D *h1)
{
f1DcorrectionsDeuteronsMinus = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsTritonsMinus(TH1D *h1)
{
f1DcorrectionsTritonsMinus = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsHe3sMinus(TH1D *h1)
{
f1DcorrectionsHe3sMinus = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsAlphasMinus(TH1D *h1)
{
f1DcorrectionsAlphasMinus = h1;
}
//
/************************************/
void AliFemtoEventReaderAOD::Set1DCorrectionsAll(TH1D *h1)
{
f1DcorrectionsAll = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsLambdas(TH1D *h1)
{
f1DcorrectionsLambdas = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsLambdasMinus(TH1D *h1)
{
f1DcorrectionsLambdasMinus = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsXiPlus(TH1D *h1)
{
f1DcorrectionsXiPlus = h1;
}
void AliFemtoEventReaderAOD::Set1DCorrectionsXiMinus(TH1D *h1)
{
f1DcorrectionsXiMinus = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsPions(THnSparse *h1)
{
f4DcorrectionsPions = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsKaons(THnSparse *h1)
{
f4DcorrectionsKaons = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsProtons(THnSparse *h1)
{
f4DcorrectionsProtons = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsPionsMinus(THnSparse *h1)
{
f4DcorrectionsPionsMinus = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsKaonsMinus(THnSparse *h1)
{
f4DcorrectionsKaonsMinus = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsProtonsMinus(THnSparse *h1)
{
f4DcorrectionsProtonsMinus = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsLambdas(THnSparse *h1)
{
f4DcorrectionsLambdas = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsLambdasMinus(THnSparse *h1)
{
f4DcorrectionsLambdasMinus = h1;
}
void AliFemtoEventReaderAOD::Set4DCorrectionsAll(THnSparse *h1)
{
f4DcorrectionsAll = h1;
}
//Special MC analysis for pi,K,p,e selected by PDG code -->
void AliFemtoEventReaderAOD::SetPionAnalysis(Bool_t aSetPionAna)
{
fIsPionAnalysis = aSetPionAna;
}
void AliFemtoEventReaderAOD::SetKaonAnalysis(Bool_t aSetKaonAna)
{
fIsKaonAnalysis = aSetKaonAna;
}
void AliFemtoEventReaderAOD::SetProtonAnalysis(Bool_t aSetProtonAna)
{
fIsProtonAnalysis = aSetProtonAna;
}
void AliFemtoEventReaderAOD::SetElectronAnalysis(Bool_t aSetElectronAna)
{
fIsElectronAnalysis = aSetElectronAna;
}
//Special MC analysis for pi,K,p,e selected by PDG code <--
/**************************************************/
//
void AliFemtoEventReaderAOD::SetDeuteronAnalysis(Bool_t aSetDeuteronAna)
{
fIsDeuteronAnalysis = aSetDeuteronAna;
}
void AliFemtoEventReaderAOD::SetTritonAnalysis(Bool_t aSetTritonAna)
{
fIsTritonAnalysis = aSetTritonAna;
}
void AliFemtoEventReaderAOD::SetHe3Analysis(Bool_t aSetHe3Ana)
{
fIsHe3Analysis = aSetHe3Ana;
}
void AliFemtoEventReaderAOD::SetAlphaAnalysis(Bool_t aSetAlphaAna)
{
fIsAlphaAnalysis = aSetAlphaAna;
}
//
/*************************************************/
|
/*******************************************************************************
Banana Qt Libraries
Copyright (c) 2016 Alexandra Cherdantseva
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*******************************************************************************/
#include "ChildFilter.h"
namespace Banana
{
bool ChildFilter::filterMatch(QObject *object) const
{
for (auto &item : filters)
{
if (!item.first->filterMatch(object))
return false;
}
return true;
}
bool ChildFilter::shouldFilterDeeper(QObject *) const
{
return true;
}
ChildFilters ChildFilter::getFilters() const
{
ChildFilters result;
for (auto &item : filters)
{
result.push_back(item.first);
}
return result;
}
int ChildFilter::getFiltersCount() const
{
return static_cast<int>(filters.size());
}
void ChildFilter::addFilter(IChildFilter *filter, bool own)
{
auto it = filters.find(filter);
if (filters.end() == it)
{
beforeChangeFilters();
filters[filter] = own ? FilterPtr(filter) : FilterPtr();
afterChangeFilters();
} else if ((it->second != nullptr) != own)
{
if (own)
{
it->second = FilterPtr(filter);
} else
{
it->second.release();
}
}
}
void ChildFilter::removeFilter(IChildFilter *filter)
{
auto it = filters.find(filter);
if (filters.end() != it)
{
beforeChangeFilters();
filters.erase(it);
afterChangeFilters();
}
}
void ChildFilter::clearFilters()
{
filters.clear();
}
void ChildFilter::beforeChangeFilters() {}
void ChildFilter::afterChangeFilters() {}
}
|
; ===============================================================
; Jan 2014
; ===============================================================
;
; FILE *_fmemopen_(void **bufp, size_t *sizep, const char *mode)
;
; Associate a memory buffer with a stream.
;
; More general than the proposed standard functions which only
; allow read/write-able fixed buffers (fmemopen) and write-only
; expanding buffers (open_memstream). This function allows
; all combinations, treating a buffer exactly like a file.
; The mode flag "x" is re-purposed to indicate the buffer is
; allowed to expand via realloc.
;
; ===============================================================
INCLUDE "clib_cfg.asm"
SECTION code_stdio
PUBLIC asm__fmemopen
PUBLIC asm0__fmemopen
EXTERN error_einval_zc, error_zc, __stdio_file_add_list, __stdio_heap
EXTERN __stdio_parse_mode, asm_heap_alloc, __stdio_file_constructor, l_setmem_hl
EXTERN __stdio_memstream_driver, asm_realloc, __stdio_file_destructor, asm_free
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IF __CLIB_OPT_MULTITHREAD & $04
EXTERN __stdio_lock_file_list, __stdio_unlock_file_list
ENDIF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
asm__fmemopen:
; enter : hl = char **bufp
; bc = size_t *sizep
; de = char *mode
; a = mode mask (0TXC BAWR, set bit disallows)
;
; exit : success
;
; hl = FILE *
; ix = FILE *
; carry reset
;
; fail
;
; hl = 0
; carry set, errno set
;
; uses : af, bc, de, hl, ix
push hl ; save bufp
push bc ; save sizep
push af ; save mode mask
ld a,h
or l
jp z, error_einval_zc - 3 ; if bufp == 0
ld a,b
or c
jp z, error_einval_zc - 3 ; if sizep == 0
call __stdio_parse_mode
jp c, error_einval_zc - 3 ; if mode string is invalid
pop af
and c
jp nz, error_einval_zc - 2 ; if mode byte is disallowed
push bc ; save mode byte
; allocate FILE structs from stdio's heap
ld hl,31 ; sizeof(memstream FILE *)
ld de,(__stdio_heap)
call asm_heap_alloc
jp c, error_zc - 3 ; if malloc failed
inc hl
inc hl ; hl = FILE *
asm0__fmemopen:
; hl = FILE * (29 bytes uninitialized)
; stack = bufp, sizep, mode byte
ld e,l
ld d,h ; de = FILE *
push de
pop ix ; ix = FILE *
call __stdio_file_constructor
ld hl,13
add hl,de ; hl = & FILE.memstream_flags
xor a
call l_setmem_hl - 30
; FILE structure set to default
; de = FILE *
; ix = FILE *
; stack = bufp, sizep, mode byte
ex de,hl ; hl = FILE *
inc hl
ld (hl),__stdio_memstream_driver % 256
inc hl
ld (hl),__stdio_memstream_driver / 256
pop de ; e = mode byte = 0TXC BAWR
ld (ix+28),e ; save original mode byte
ld a,e
rrca
rrca
and $c0
add a,$27
ld (ix+3),a ; set r/w bits, memstream type
ld a,e
rla
and $02
ld (ix+4),a ; if r mode, indicate last op was read
; FILE portion is initialized, memstream portion remains
ld a,e
and $24
ld d,a
; ix = FILE *
; e = mode byte = 0TXC BAWR
; d = memstream mode = F0X0 0A00
; stack = bufp, sizep
; must allocate a buffer ?
pop hl ; hl = size_t *sizep
ld (ix+16),l
ld (ix+17),h ; store in FILE structure
ld c,(hl)
inc hl
ld b,(hl) ; bc = size
pop hl ; hl = char **bufp
ld (ix+14),l
ld (ix+15),h ; store in FILE structure
ld a,(hl)
inc hl
ld h,(hl)
ld l,a ; hl = void *buf
ld a,b
or c
jr z, must_allocate_size_0
ld a,h
or l
jr z, must_allocate_buf_0
rejoin_0:
; ix = FILE *
; e = mode byte = 0TXC BAWR
; d = memstream mode = F0X0 0A00
; hl = void *buf
; bc = size_t size
ld (ix+13),d ; store final memstream mode
ld a,e ; a = mode byte = 0TXC BAWR
push hl ; save buf
push ix
pop de
ld hl,18
add hl,de ; hl = & vector.array
pop de ; de = void *buf
ld (hl),e
inc hl
ld (hl),d ; vector.array = buf
inc hl
push bc
; a = mode byte = 0TXC BAWR
; hl = & vector.size
; bc = capacity
; de = void *buf
; stack = capacity
and $50
jr z, mode_TC_00
cp $50
jr z, mode_TC_11
mode_TC_01:
push hl ; save & vector.size
ld l,e
ld h,d ; hl = void *buf
ld a,b
or c
jr z, skip_cpir
xor a
cpir ; look for '\0'
scf
skip_cpir:
sbc hl,de ; hl = index of '\0' or end of buf
ex de,hl ; de = position_index @ '\0'
ld c,e
ld b,d ; bc = append_index @ '\0'
pop hl
jr rejoin_1
mode_TC_11:
ld bc,0 ; bc = append_index = 0
mode_TC_00:
ld de,0 ; de = position_index = 0
rejoin_1:
; bc = append_index
; de = position_index
; hl = & vector.size
; stack = capacity
ld (hl),c
inc hl
ld (hl),b ; vector.size = append_index
inc hl
pop bc ; bc = capacity
ld (hl),c
inc hl
ld (hl),b ; vector.capacity = capacity
inc hl
bit 5,(ix+13) ; vector allowed to grow ?
jr z, vector_no_grow
ld bc,$ffff ; max_size = all of memory
vector_no_grow:
ld (hl),c
inc hl
ld (hl),b ; vector.max_size = capacity
inc hl
ld (hl),e
inc hl
ld (hl),d ; fptr = position_index
; add FILE to open list
push ix
pop de ; de = FILE *
call __stdio_file_add_list
; return FILE*
push ix
pop hl ; hl = FILE *
or a ; carry reset for success
ret
must_allocate_size_0:
; ix = FILE *
; e = mode byte = 0TXC BAWR
; d = memstream mode = F0X0 0A00
; hl = void *buf
; bc = size_t size = 0
bit 5,d
call z, error_einval_zc
jr z, allocate_fail ; if not allowed to grow buffer
inc bc ; make room for '\0'
ld hl,0 ; void *buf = 0
must_allocate_buf_0:
push bc
push de
call asm_realloc
pop de
pop bc
jr c, allocate_fail
bit 5,d
jr nz, _skip
set 7,d ; if not allowed to expand, must free buffer on close
_skip:
dec bc ; make capacity smaller to hide terminating '\0'
add hl,bc ; hl = & end of buffer
ld (hl),0 ; zero terminate
sbc hl,bc
jp rejoin_0
allocate_fail:
; ix = FILE *
call __stdio_file_destructor
push ix
pop hl
dec hl
dec hl ; hl = & FILE.link
call asm_free ; free(FILE *)
jp error_zc
|
# On boot the BIOS does not know how to load the OS
# so the boot sector must do that. The boot sector is stored
# in a known location. That is the first sector of the disk,
# which is cylinder 0, header 0 and sector 0.
# The size of the boot sector is 512 bytes.
# To mark the region as bootable, the 511th and 512th byte must be a magic byte.
# So the 511th byte must be 0x55, and the 512th byte must be 0xAA, a 16 bit value.
# Because x86 is little endian, we need to store them in reverse order
# Naming conventions:
# Where $MODE is the processor mode such as RM (Real Mode) or PM (Protected Mode) etc..
# Where $NAME is the identifier name
# Procedures -> _$MODE_$NAME
# Labels -> __$MODE_$NAME
# Variables -> ___$MODE_$NAME
.text
.code16 # we are using 16 bit protected mode
.global _RM_ENTRY_
################################ ENTRY ################################
# This is the main entry of our bootloader.
# We are in 16-bit real mode,
# 8 and 16 bit registers only, we can use segmentation, no virtual memory, no paging.
_RM_ENTRY:
JMP _RM_MAIN
.space 3 - (.-_RM_ENTRY)
# Configuration for a 2.88MB floppy using FAT 12
OEMname: .ascii "BOOSTER "
___BytesPerSector: .word 512
___SectPerCluster: .byte 1
___ReservedSectors: .word 1
___NumFAT: .byte 2
___NumRootDirEntries: .word 240
___NumSectors: .word 5760
___MediaType: .byte 0xF0
___NumFATsectors: .word 9
___SectorsPerTrack: .word 36
___NumHeads: .word 2
___NumHiddenSectors: .long 0
___NumSectorsHuge: .long 0
___DriveNum: .byte 0
___Reserved: .byte 0x00
___Signature: .byte 0x29
___VolumeID: .long 0x54428E71
___VolumeLabel: .ascii "NO NAME "
___FileSysType: .ascii "FAT12 "
_RM_MAIN:
MOVW $___RM_WELCOME, %SI
CALLW _RM_PRINT_STR
__RM_ENTRY:
JMP __RM_ENTRY
################################ ROUTINES ################################
# This routine does a warm reboot.
# This is done by jumping to the reset vector.
# This basically means that the system will execute the code from the
# first insturction again without actually rebooting.
_RM_REBOOT:
LJMPW $0xFFFF, $0x0
_RM_ERROR:
MOVW $___RM_ERROR, %SI
CALLW _RM_PRINT_STR
__RM_ERROR:
JMP __RM_ERROR
# Prints a single 8-bit ASCII character using BIOS interrupts.
# The char to print must be in %al
_RM_PUTCHAR:
MOVB $0x0E, %AH # Set to teletype
INT $0x10 # Call BIOS interrupt
RETW
# Prints a null terminated string using BIOS interrupts.
# The address of the null terminated string must be in %si
_RM_PRINT_STR:
MOVB $0x0E, %AH # Set to teletype
TESTW %SI, %SI # Set ZF if %si == 0
JE __RM_PRINT_STR_END # Exit if input was null
__RM_PRINT_STR_LOOP:
MOVB (%SI), %AL # Load one byte from address of %si into %al
INT $0x10 # Call BIOS interrupt
INCW %SI # Increment pointer, move to next character byte
TESTB %AL, %AL # Check for null terminator, set ZF if %al == 0
JNE __RM_PRINT_STR_LOOP # Jump to end if we reached the end of the string.
__RM_PRINT_STR_END:
RETW
################################ DATA ################################
___RM_WELCOME: .asciz "\rParadox OS (C) Copyright Mario Sieg \"pinsrq\" <mt3000@gmx.de>\n\rBooted into 16-bit real mode!\n"
___RM_ERROR: .asciz "\rUnknown real mode boot loader error!\n"
.fill 510-(.-_RM_ENTRY), 1, 0 # Fill the rest of the bytes with zeroes
.word 0xAA55 # The 2 magic bytes 0x55AA but because x86 is little endian, we need to swap them.
|
; This is a comment
; 8086 Template example: Hello World
; contant declaration section
; directives for the compiler
.MODEL small
.STACK
.DATA ; variable declaration section
message db "HANUMAN$"
; code section
.CODE
.STARTUP ; interrup to print a string with $ at the end
mov ah,09h
mov dx,offset message
int 21h
.EXIT
END ; end of the program
|
; A081611: Number of numbers <= n having no 2 in their ternary representation.
; 1,2,2,3,4,4,4,4,4,5,6,6,7,8,8,8,8,8,8,8,8,8,8,8,8,8,8,9,10,10,11,12,12,12,12,12,13,14,14,15,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,17,18,18,19,20,20,20,20,20,21,22,22,23,24,24,24,24,24,24,24,24,24,24,24,24,24,24,25,26,26,27,28,28,28,28,28,29,30,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,33,34,34,35,36,36,36
mov $5,$0
add $5,1
lpb $5
mov $0,$2
sub $5,1
sub $0,$5
mov $3,2
mov $6,1
mul $6,$0
mul $6,2
mov $4,$6
lpb $4
gcd $3,$4
div $4,3
lpe
mov $6,$3
sub $6,1
add $1,$6
lpe
|
; A017783: Binomial coefficients C(67,n).
; 1,67,2211,47905,766480,9657648,99795696,869648208,6522361560,42757703560,247994680648,1285063345176,5996962277488,25371763481680,97862516286480,345780890878896,1123787895356412,3371363686069236,9364899127970100,24151581961607100,57963796707857040,129728497393775280,271250494550621040,530707489338171600,972963730453314600,1673497616379701112,2703342303382594104,4105075349580976232,5864393356544251760,7886597962249166160,9989690752182277136,11923179284862717872,13413576695470557606,14226520737620288370,14226520737620288370,13413576695470557606,11923179284862717872,9989690752182277136,7886597962249166160,5864393356544251760,4105075349580976232,2703342303382594104,1673497616379701112,972963730453314600,530707489338171600,271250494550621040,129728497393775280,57963796707857040,24151581961607100,9364899127970100,3371363686069236,1123787895356412,345780890878896,97862516286480,25371763481680,5996962277488,1285063345176,247994680648,42757703560,6522361560,869648208,99795696,9657648,766480,47905,2211,67,1
mov $1,67
bin $1,$0
mov $0,$1
|
print:
pusha
; keep this in mind:
; while (string[i] != 0) { print string[i]; i++ }
; the comparison for string end (null byte)
start:
mov al, [bx] ; 'bx' is the base address for the string
cmp al, 0
je done
; the part where we print with the BIOS help
mov ah, 0x0e
int 0x10 ; 'al' already contains the char
; increment pointer and do next loop
add bx, 1
jmp start
done:
popa
ret
TEST_MSG db "test",0
print_test:
pusha
mov bx, TEST_MSG
call print
call print_nl
popa
ret
print_nl:
pusha
mov ah, 0x0e
mov al, 0x0a ; newline char
int 0x10
mov al, 0x0d ; carriage return
int 0x10
popa
ret
|
; A156856: 2025*n^2 + n.
; 2026,8102,18228,32404,50630,72906,99232,129608,164034,202510,245036,291612,342238,396914,455640,518416,585242,656118,731044,810020,893046,980122,1071248,1166424,1265650,1368926,1476252,1587628,1703054,1822530,1946056,2073632,2205258,2340934,2480660,2624436,2772262,2924138,3080064,3240040,3404066,3572142,3744268,3920444,4100670,4284946,4473272,4665648,4862074,5062550,5267076,5475652,5688278,5904954,6125680,6350456,6579282,6812158,7049084,7290060,7535086,7784162,8037288,8294464,8555690,8820966,9090292,9363668,9641094,9922570,10208096,10497672,10791298,11088974,11390700,11696476,12006302,12320178,12638104,12960080,13286106,13616182,13950308,14288484,14630710,14976986,15327312,15681688,16040114,16402590,16769116,17139692,17514318,17892994,18275720,18662496,19053322,19448198,19847124,20250100
mov $1,1
add $1,$0
mul $1,45
pow $1,2
add $1,1
add $1,$0
mov $0,$1
|
/* ************************************************************************** */
/* */
/* ::: :::::::: */
/* Animal.cpp :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: vminomiy <vminomiy@student.42sp.org.br> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2022/03/16 00:20:44 by vminomiy #+# #+# */
/* Updated: 2022/03/16 02:50:05 by vminomiy ### ########.fr */
/* */
/* ************************************************************************** */
#include "Animal.hpp"
// Construtor padrão
Animal::Animal(void) {
Animal::type = "Harl";
std::cout << Animal::type << "/Animal: Default Constructor Called." << std::endl;
}
// Destrutor
Animal::~Animal(void) { std::cout << Animal::type << "/Animal: Destructor Called." << std::endl; }
// Copy Constructor shallow
Animal::Animal(Animal const &obj) {
std::cout << Animal::type << "/Animal: Copy Constructor Called." << std::endl;
(void)obj;
*this = obj;
}
// Atribuir operador
Animal &Animal::operator=(Animal const &obj) {
if (this != &obj)
this->type = obj.type;
return (*this);
}
// getters Para pegar Tipo do animal e A ideia
std::string Animal::getType(void) const { return (Animal::type); }
|
/*
*********************************************************************************************************
* uC/LIB
* Custom Library Modules
*
* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
*
* SPDX-License-Identifier: APACHE-2.0
*
* This software is subject to an open source license and is distributed by
* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
*
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* STANDARD MEMORY OPERATIONS
*
* AVR32 AP7000
* IAR Compiler
*
* Filename : lib_mem_a.asm
* Version : V1.39.01
*********************************************************************************************************
* Note(s) : (1) NO compiler-supplied standard library functions are used in library or product software.
*
* (a) ALL standard library functions are implemented in the custom library modules :
*
* (1) \<Custom Library Directory>\lib*.*
*
* (2) \<Custom Library Directory>\Ports\<cpu>\<compiler>\lib*_a.*
*
* where
* <Custom Library Directory> directory path for custom library software
* <cpu> directory name for specific processor (CPU)
* <compiler> directory name for specific compiler
*
* (b) Product-specific library functions are implemented in individual products.
*
* (2) Assumes AVR32 CPU mode configured for Big Endian.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* PUBLIC FUNCTIONS
*********************************************************************************************************
*/
MODULE LIB_MEM
PUBLIC Mem_Copy
/*
*********************************************************************************************************
* CODE GENERATION DIRECTIVES
*********************************************************************************************************
*/
RSEG CODE32:CODE:NOROOT(2)
/*
*********************************************************************************************************
* Mem_Copy()
*
* Description : Copy data octets from one buffer to another buffer.
*
* Argument(s) : pdest Pointer to destination memory buffer.
*
* psrc Pointer to source memory buffer.
*
* size Number of data buffer octets to copy.
*
* Return(s) : none.
*
* Caller(s) : Application.
*
* Note(s) : (1) Null copies allowed (i.e. 0-octet size).
*
* (2) Memory buffers NOT checked for overlapping.
*
* (3) Modulo arithmetic is used to determine whether a memory buffer starts on a 'CPU_ALIGN'
* address boundary.
*********************************************************************************************************
*/
/*
void Mem_Copy (void *pdest, ; ==> R12
void *psrc, ; ==> R11
CPU_SIZE_T size) ; ==> R10
*/
#define pdest R12
#define psrc R11
#define size R10
Mem_Copy:
CP.W pdest, 0
BRNE Mem_Copy_1 /* return if pdest == NULL. */
MOV PC, LR /* Restore Program Counter (return) */
Mem_Copy_1:
CP.W psrc, 0
BRNE Mem_Copy_2 /* return if psrc == NULL. */
MOV PC, LR /* Restore Program Counter (return) */
Mem_Copy_2:
CP.W size, 0
BRNE Mem_Copy_3 /* return if size == 0. */
MOV PC, LR /* Restore Program Counter (return) */
Mem_Copy_3:
PREF psrc[0]
MOV pdest, R12
Mem_Copy_Chk_32: /* If less than 32 bytes, copy byte-by-byte. */
CP.W size, 32
BRGE Mem_Copy_More_31
SUB size, 1
RETLT R12
Mem_Copy_01_1:
LD.UB R8, psrc++
ST.B pdest++, R8
SUB size, 1
BRGE Mem_Copy_01_1
RETAL R12
Mem_Copy_More_31:
PUSHM R0-R7, LR
Chk_Align_32: /* Check if both dest & src 32-bit aligned. */
MOV R8, psrc
ANDL R8, 31, COH
BRNE Mem_Copy_Unaligned_src
MOV R8, pdest
ANDL R8, 3, COH
BRNE Mem_Copy_Unaligned_dest
Mem_Copy_Aligned:
SUB size, 32
BRLT Mem_Copy_Chk_16
Mem_Copy_32_1: /* Copy 32 bytes at a time */
LDM psrc, R0-R7
SUB psrc, -32
STM pdest, R0-R7
SUB pdest, -32
SUB size, 32
BRGE Mem_Copy_32_1
Mem_Copy_Chk_16:
SUB size, -16
BRLT Mem_Copy_01_2
Mem_Copy_16_1: /* Copy 16 more bytes if possible */
LDM psrc, r0-r3
SUB psrc, -16
SUB size, 16
STM pdest, r0-r3
SUB pdest, -16
Mem_Copy_01_2: /* Copy remaining byte-by-byte. */
NEG size
ADD PC, PC, size << 2 /* Jump to remaining copies position. */
REPT 15
LD.UB R0, psrc++
ST.B pdest++, R0
ENDR
POPM R0-R7, PC
Mem_Copy_Unaligned_src:
RSUB R8, R8, 32 /* Make src cacheline-aligned. R8 = (psrc & 31) */
SUB size, R8
Mem_Copy_01_3:
LD.UB R0, psrc++
ST.B pdest++, R0
SUB R8, 1
BRNE Mem_Copy_01_3
Chk_Align_dest: /* Check if dest 32-bit aligned. */
PREF psrc[0]
MOV R8, 3
TST pdest, R8
BREQ Mem_Copy_Aligned
Mem_Copy_Unaligned_dest: /* Bad performance, src is aligned but dest is not. */
SUB size, 4
BRLT Mem_Copy_01_4
Mem_Copy_04_1:
LD.W R0, psrc++
ST.W pdest++, R0
SUB size, 4
BRGE Mem_Copy_04_1
Mem_Copy_01_4:
NEG size
ADD PC, PC, size << 2
REPT 3
LD.UB R0, psrc++
ST.B pdest++, R0
ENDR
POPM R0-R7, PC
ENDMOD
END
|
_zombie: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
#include "stat.h"
#include "user.h"
int
main(void)
{
0: 8d 4c 24 04 lea 0x4(%esp),%ecx
4: 83 e4 f0 and $0xfffffff0,%esp
7: ff 71 fc pushl -0x4(%ecx)
a: 55 push %ebp
b: 89 e5 mov %esp,%ebp
d: 51 push %ecx
e: 83 ec 04 sub $0x4,%esp
if(fork() > 0)
11: e8 54 02 00 00 call 26a <fork>
16: 85 c0 test %eax,%eax
18: 7e 0d jle 27 <main+0x27>
sleep(5); // Let child exit before parent.
1a: 83 ec 0c sub $0xc,%esp
1d: 6a 05 push $0x5
1f: e8 de 02 00 00 call 302 <sleep>
24: 83 c4 10 add $0x10,%esp
exit();
27: e8 46 02 00 00 call 272 <exit>
2c: 66 90 xchg %ax,%ax
2e: 66 90 xchg %ax,%ax
00000030 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, char *t)
{
30: 55 push %ebp
31: 89 e5 mov %esp,%ebp
33: 53 push %ebx
34: 8b 45 08 mov 0x8(%ebp),%eax
37: 8b 4d 0c mov 0xc(%ebp),%ecx
char *os;
os = s;
while((*s++ = *t++) != 0)
3a: 89 c2 mov %eax,%edx
3c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
40: 83 c1 01 add $0x1,%ecx
43: 0f b6 59 ff movzbl -0x1(%ecx),%ebx
47: 83 c2 01 add $0x1,%edx
4a: 84 db test %bl,%bl
4c: 88 5a ff mov %bl,-0x1(%edx)
4f: 75 ef jne 40 <strcpy+0x10>
;
return os;
}
51: 5b pop %ebx
52: 5d pop %ebp
53: c3 ret
54: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
5a: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
00000060 <strcmp>:
int
strcmp(const char *p, const char *q)
{
60: 55 push %ebp
61: 89 e5 mov %esp,%ebp
63: 56 push %esi
64: 53 push %ebx
65: 8b 55 08 mov 0x8(%ebp),%edx
68: 8b 4d 0c mov 0xc(%ebp),%ecx
while(*p && *p == *q)
6b: 0f b6 02 movzbl (%edx),%eax
6e: 0f b6 19 movzbl (%ecx),%ebx
71: 84 c0 test %al,%al
73: 75 1e jne 93 <strcmp+0x33>
75: eb 29 jmp a0 <strcmp+0x40>
77: 89 f6 mov %esi,%esi
79: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
p++, q++;
80: 83 c2 01 add $0x1,%edx
}
int
strcmp(const char *p, const char *q)
{
while(*p && *p == *q)
83: 0f b6 02 movzbl (%edx),%eax
p++, q++;
86: 8d 71 01 lea 0x1(%ecx),%esi
}
int
strcmp(const char *p, const char *q)
{
while(*p && *p == *q)
89: 0f b6 59 01 movzbl 0x1(%ecx),%ebx
8d: 84 c0 test %al,%al
8f: 74 0f je a0 <strcmp+0x40>
91: 89 f1 mov %esi,%ecx
93: 38 d8 cmp %bl,%al
95: 74 e9 je 80 <strcmp+0x20>
p++, q++;
return (uchar)*p - (uchar)*q;
97: 29 d8 sub %ebx,%eax
}
99: 5b pop %ebx
9a: 5e pop %esi
9b: 5d pop %ebp
9c: c3 ret
9d: 8d 76 00 lea 0x0(%esi),%esi
}
int
strcmp(const char *p, const char *q)
{
while(*p && *p == *q)
a0: 31 c0 xor %eax,%eax
p++, q++;
return (uchar)*p - (uchar)*q;
a2: 29 d8 sub %ebx,%eax
}
a4: 5b pop %ebx
a5: 5e pop %esi
a6: 5d pop %ebp
a7: c3 ret
a8: 90 nop
a9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
000000b0 <strlen>:
uint
strlen(char *s)
{
b0: 55 push %ebp
b1: 89 e5 mov %esp,%ebp
b3: 8b 4d 08 mov 0x8(%ebp),%ecx
int n;
for(n = 0; s[n]; n++)
b6: 80 39 00 cmpb $0x0,(%ecx)
b9: 74 12 je cd <strlen+0x1d>
bb: 31 d2 xor %edx,%edx
bd: 8d 76 00 lea 0x0(%esi),%esi
c0: 83 c2 01 add $0x1,%edx
c3: 80 3c 11 00 cmpb $0x0,(%ecx,%edx,1)
c7: 89 d0 mov %edx,%eax
c9: 75 f5 jne c0 <strlen+0x10>
;
return n;
}
cb: 5d pop %ebp
cc: c3 ret
uint
strlen(char *s)
{
int n;
for(n = 0; s[n]; n++)
cd: 31 c0 xor %eax,%eax
;
return n;
}
cf: 5d pop %ebp
d0: c3 ret
d1: eb 0d jmp e0 <memset>
d3: 90 nop
d4: 90 nop
d5: 90 nop
d6: 90 nop
d7: 90 nop
d8: 90 nop
d9: 90 nop
da: 90 nop
db: 90 nop
dc: 90 nop
dd: 90 nop
de: 90 nop
df: 90 nop
000000e0 <memset>:
void*
memset(void *dst, int c, uint n)
{
e0: 55 push %ebp
e1: 89 e5 mov %esp,%ebp
e3: 57 push %edi
e4: 8b 55 08 mov 0x8(%ebp),%edx
}
static inline void
stosb(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosb" :
e7: 8b 4d 10 mov 0x10(%ebp),%ecx
ea: 8b 45 0c mov 0xc(%ebp),%eax
ed: 89 d7 mov %edx,%edi
ef: fc cld
f0: f3 aa rep stos %al,%es:(%edi)
stosb(dst, c, n);
return dst;
}
f2: 89 d0 mov %edx,%eax
f4: 5f pop %edi
f5: 5d pop %ebp
f6: c3 ret
f7: 89 f6 mov %esi,%esi
f9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000100 <strchr>:
char*
strchr(const char *s, char c)
{
100: 55 push %ebp
101: 89 e5 mov %esp,%ebp
103: 53 push %ebx
104: 8b 45 08 mov 0x8(%ebp),%eax
107: 8b 5d 0c mov 0xc(%ebp),%ebx
for(; *s; s++)
10a: 0f b6 10 movzbl (%eax),%edx
10d: 84 d2 test %dl,%dl
10f: 74 1d je 12e <strchr+0x2e>
if(*s == c)
111: 38 d3 cmp %dl,%bl
113: 89 d9 mov %ebx,%ecx
115: 75 0d jne 124 <strchr+0x24>
117: eb 17 jmp 130 <strchr+0x30>
119: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
120: 38 ca cmp %cl,%dl
122: 74 0c je 130 <strchr+0x30>
}
char*
strchr(const char *s, char c)
{
for(; *s; s++)
124: 83 c0 01 add $0x1,%eax
127: 0f b6 10 movzbl (%eax),%edx
12a: 84 d2 test %dl,%dl
12c: 75 f2 jne 120 <strchr+0x20>
if(*s == c)
return (char*)s;
return 0;
12e: 31 c0 xor %eax,%eax
}
130: 5b pop %ebx
131: 5d pop %ebp
132: c3 ret
133: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
139: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000140 <gets>:
char*
gets(char *buf, int max)
{
140: 55 push %ebp
141: 89 e5 mov %esp,%ebp
143: 57 push %edi
144: 56 push %esi
145: 53 push %ebx
int i, cc;
char c;
for(i=0; i+1 < max; ){
146: 31 f6 xor %esi,%esi
cc = read(0, &c, 1);
148: 8d 7d e7 lea -0x19(%ebp),%edi
return 0;
}
char*
gets(char *buf, int max)
{
14b: 83 ec 1c sub $0x1c,%esp
int i, cc;
char c;
for(i=0; i+1 < max; ){
14e: eb 29 jmp 179 <gets+0x39>
cc = read(0, &c, 1);
150: 83 ec 04 sub $0x4,%esp
153: 6a 01 push $0x1
155: 57 push %edi
156: 6a 00 push $0x0
158: e8 2d 01 00 00 call 28a <read>
if(cc < 1)
15d: 83 c4 10 add $0x10,%esp
160: 85 c0 test %eax,%eax
162: 7e 1d jle 181 <gets+0x41>
break;
buf[i++] = c;
164: 0f b6 45 e7 movzbl -0x19(%ebp),%eax
168: 8b 55 08 mov 0x8(%ebp),%edx
16b: 89 de mov %ebx,%esi
if(c == '\n' || c == '\r')
16d: 3c 0a cmp $0xa,%al
for(i=0; i+1 < max; ){
cc = read(0, &c, 1);
if(cc < 1)
break;
buf[i++] = c;
16f: 88 44 1a ff mov %al,-0x1(%edx,%ebx,1)
if(c == '\n' || c == '\r')
173: 74 1b je 190 <gets+0x50>
175: 3c 0d cmp $0xd,%al
177: 74 17 je 190 <gets+0x50>
gets(char *buf, int max)
{
int i, cc;
char c;
for(i=0; i+1 < max; ){
179: 8d 5e 01 lea 0x1(%esi),%ebx
17c: 3b 5d 0c cmp 0xc(%ebp),%ebx
17f: 7c cf jl 150 <gets+0x10>
break;
buf[i++] = c;
if(c == '\n' || c == '\r')
break;
}
buf[i] = '\0';
181: 8b 45 08 mov 0x8(%ebp),%eax
184: c6 04 30 00 movb $0x0,(%eax,%esi,1)
return buf;
}
188: 8d 65 f4 lea -0xc(%ebp),%esp
18b: 5b pop %ebx
18c: 5e pop %esi
18d: 5f pop %edi
18e: 5d pop %ebp
18f: c3 ret
break;
buf[i++] = c;
if(c == '\n' || c == '\r')
break;
}
buf[i] = '\0';
190: 8b 45 08 mov 0x8(%ebp),%eax
gets(char *buf, int max)
{
int i, cc;
char c;
for(i=0; i+1 < max; ){
193: 89 de mov %ebx,%esi
break;
buf[i++] = c;
if(c == '\n' || c == '\r')
break;
}
buf[i] = '\0';
195: c6 04 30 00 movb $0x0,(%eax,%esi,1)
return buf;
}
199: 8d 65 f4 lea -0xc(%ebp),%esp
19c: 5b pop %ebx
19d: 5e pop %esi
19e: 5f pop %edi
19f: 5d pop %ebp
1a0: c3 ret
1a1: eb 0d jmp 1b0 <stat>
1a3: 90 nop
1a4: 90 nop
1a5: 90 nop
1a6: 90 nop
1a7: 90 nop
1a8: 90 nop
1a9: 90 nop
1aa: 90 nop
1ab: 90 nop
1ac: 90 nop
1ad: 90 nop
1ae: 90 nop
1af: 90 nop
000001b0 <stat>:
int
stat(char *n, struct stat *st)
{
1b0: 55 push %ebp
1b1: 89 e5 mov %esp,%ebp
1b3: 56 push %esi
1b4: 53 push %ebx
int fd;
int r;
fd = open(n, O_RDONLY);
1b5: 83 ec 08 sub $0x8,%esp
1b8: 6a 00 push $0x0
1ba: ff 75 08 pushl 0x8(%ebp)
1bd: e8 f0 00 00 00 call 2b2 <open>
if(fd < 0)
1c2: 83 c4 10 add $0x10,%esp
1c5: 85 c0 test %eax,%eax
1c7: 78 27 js 1f0 <stat+0x40>
return -1;
r = fstat(fd, st);
1c9: 83 ec 08 sub $0x8,%esp
1cc: ff 75 0c pushl 0xc(%ebp)
1cf: 89 c3 mov %eax,%ebx
1d1: 50 push %eax
1d2: e8 f3 00 00 00 call 2ca <fstat>
1d7: 89 c6 mov %eax,%esi
close(fd);
1d9: 89 1c 24 mov %ebx,(%esp)
1dc: e8 b9 00 00 00 call 29a <close>
return r;
1e1: 83 c4 10 add $0x10,%esp
1e4: 89 f0 mov %esi,%eax
}
1e6: 8d 65 f8 lea -0x8(%ebp),%esp
1e9: 5b pop %ebx
1ea: 5e pop %esi
1eb: 5d pop %ebp
1ec: c3 ret
1ed: 8d 76 00 lea 0x0(%esi),%esi
int fd;
int r;
fd = open(n, O_RDONLY);
if(fd < 0)
return -1;
1f0: b8 ff ff ff ff mov $0xffffffff,%eax
1f5: eb ef jmp 1e6 <stat+0x36>
1f7: 89 f6 mov %esi,%esi
1f9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000200 <atoi>:
return r;
}
int
atoi(const char *s)
{
200: 55 push %ebp
201: 89 e5 mov %esp,%ebp
203: 53 push %ebx
204: 8b 4d 08 mov 0x8(%ebp),%ecx
int n;
n = 0;
while('0' <= *s && *s <= '9')
207: 0f be 11 movsbl (%ecx),%edx
20a: 8d 42 d0 lea -0x30(%edx),%eax
20d: 3c 09 cmp $0x9,%al
20f: b8 00 00 00 00 mov $0x0,%eax
214: 77 1f ja 235 <atoi+0x35>
216: 8d 76 00 lea 0x0(%esi),%esi
219: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
n = n*10 + *s++ - '0';
220: 8d 04 80 lea (%eax,%eax,4),%eax
223: 83 c1 01 add $0x1,%ecx
226: 8d 44 42 d0 lea -0x30(%edx,%eax,2),%eax
atoi(const char *s)
{
int n;
n = 0;
while('0' <= *s && *s <= '9')
22a: 0f be 11 movsbl (%ecx),%edx
22d: 8d 5a d0 lea -0x30(%edx),%ebx
230: 80 fb 09 cmp $0x9,%bl
233: 76 eb jbe 220 <atoi+0x20>
n = n*10 + *s++ - '0';
return n;
}
235: 5b pop %ebx
236: 5d pop %ebp
237: c3 ret
238: 90 nop
239: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
00000240 <memmove>:
void*
memmove(void *vdst, void *vsrc, int n)
{
240: 55 push %ebp
241: 89 e5 mov %esp,%ebp
243: 56 push %esi
244: 53 push %ebx
245: 8b 5d 10 mov 0x10(%ebp),%ebx
248: 8b 45 08 mov 0x8(%ebp),%eax
24b: 8b 75 0c mov 0xc(%ebp),%esi
char *dst, *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
24e: 85 db test %ebx,%ebx
250: 7e 14 jle 266 <memmove+0x26>
252: 31 d2 xor %edx,%edx
254: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
*dst++ = *src++;
258: 0f b6 0c 16 movzbl (%esi,%edx,1),%ecx
25c: 88 0c 10 mov %cl,(%eax,%edx,1)
25f: 83 c2 01 add $0x1,%edx
{
char *dst, *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
262: 39 da cmp %ebx,%edx
264: 75 f2 jne 258 <memmove+0x18>
*dst++ = *src++;
return vdst;
}
266: 5b pop %ebx
267: 5e pop %esi
268: 5d pop %ebp
269: c3 ret
0000026a <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
26a: b8 01 00 00 00 mov $0x1,%eax
26f: cd 40 int $0x40
271: c3 ret
00000272 <exit>:
SYSCALL(exit)
272: b8 02 00 00 00 mov $0x2,%eax
277: cd 40 int $0x40
279: c3 ret
0000027a <wait>:
SYSCALL(wait)
27a: b8 03 00 00 00 mov $0x3,%eax
27f: cd 40 int $0x40
281: c3 ret
00000282 <pipe>:
SYSCALL(pipe)
282: b8 04 00 00 00 mov $0x4,%eax
287: cd 40 int $0x40
289: c3 ret
0000028a <read>:
SYSCALL(read)
28a: b8 05 00 00 00 mov $0x5,%eax
28f: cd 40 int $0x40
291: c3 ret
00000292 <write>:
SYSCALL(write)
292: b8 10 00 00 00 mov $0x10,%eax
297: cd 40 int $0x40
299: c3 ret
0000029a <close>:
SYSCALL(close)
29a: b8 15 00 00 00 mov $0x15,%eax
29f: cd 40 int $0x40
2a1: c3 ret
000002a2 <kill>:
SYSCALL(kill)
2a2: b8 06 00 00 00 mov $0x6,%eax
2a7: cd 40 int $0x40
2a9: c3 ret
000002aa <exec>:
SYSCALL(exec)
2aa: b8 07 00 00 00 mov $0x7,%eax
2af: cd 40 int $0x40
2b1: c3 ret
000002b2 <open>:
SYSCALL(open)
2b2: b8 0f 00 00 00 mov $0xf,%eax
2b7: cd 40 int $0x40
2b9: c3 ret
000002ba <mknod>:
SYSCALL(mknod)
2ba: b8 11 00 00 00 mov $0x11,%eax
2bf: cd 40 int $0x40
2c1: c3 ret
000002c2 <unlink>:
SYSCALL(unlink)
2c2: b8 12 00 00 00 mov $0x12,%eax
2c7: cd 40 int $0x40
2c9: c3 ret
000002ca <fstat>:
SYSCALL(fstat)
2ca: b8 08 00 00 00 mov $0x8,%eax
2cf: cd 40 int $0x40
2d1: c3 ret
000002d2 <link>:
SYSCALL(link)
2d2: b8 13 00 00 00 mov $0x13,%eax
2d7: cd 40 int $0x40
2d9: c3 ret
000002da <mkdir>:
SYSCALL(mkdir)
2da: b8 14 00 00 00 mov $0x14,%eax
2df: cd 40 int $0x40
2e1: c3 ret
000002e2 <chdir>:
SYSCALL(chdir)
2e2: b8 09 00 00 00 mov $0x9,%eax
2e7: cd 40 int $0x40
2e9: c3 ret
000002ea <dup>:
SYSCALL(dup)
2ea: b8 0a 00 00 00 mov $0xa,%eax
2ef: cd 40 int $0x40
2f1: c3 ret
000002f2 <getpid>:
SYSCALL(getpid)
2f2: b8 0b 00 00 00 mov $0xb,%eax
2f7: cd 40 int $0x40
2f9: c3 ret
000002fa <sbrk>:
SYSCALL(sbrk)
2fa: b8 0c 00 00 00 mov $0xc,%eax
2ff: cd 40 int $0x40
301: c3 ret
00000302 <sleep>:
SYSCALL(sleep)
302: b8 0d 00 00 00 mov $0xd,%eax
307: cd 40 int $0x40
309: c3 ret
0000030a <uptime>:
SYSCALL(uptime)
30a: b8 0e 00 00 00 mov $0xe,%eax
30f: cd 40 int $0x40
311: c3 ret
00000312 <date>:
SYSCALL(date)
312: b8 16 00 00 00 mov $0x16,%eax
317: cd 40 int $0x40
319: c3 ret
0000031a <virt2real>:
SYSCALL(virt2real)
31a: b8 17 00 00 00 mov $0x17,%eax
31f: cd 40 int $0x40
321: c3 ret
00000322 <num_pages>:
SYSCALL(num_pages)
322: b8 18 00 00 00 mov $0x18,%eax
327: cd 40 int $0x40
329: c3 ret
0000032a <forkcow>:
SYSCALL(forkcow)
32a: b8 19 00 00 00 mov $0x19,%eax
32f: cd 40 int $0x40
331: c3 ret
332: 66 90 xchg %ax,%ax
334: 66 90 xchg %ax,%ax
336: 66 90 xchg %ax,%ax
338: 66 90 xchg %ax,%ax
33a: 66 90 xchg %ax,%ax
33c: 66 90 xchg %ax,%ax
33e: 66 90 xchg %ax,%ax
00000340 <printint>:
write(fd, &c, 1);
}
static void
printint(int fd, int xx, int base, int sgn)
{
340: 55 push %ebp
341: 89 e5 mov %esp,%ebp
343: 57 push %edi
344: 56 push %esi
345: 53 push %ebx
346: 89 c6 mov %eax,%esi
348: 83 ec 3c sub $0x3c,%esp
char buf[16];
int i, neg;
uint x;
neg = 0;
if(sgn && xx < 0){
34b: 8b 5d 08 mov 0x8(%ebp),%ebx
34e: 85 db test %ebx,%ebx
350: 74 7e je 3d0 <printint+0x90>
352: 89 d0 mov %edx,%eax
354: c1 e8 1f shr $0x1f,%eax
357: 84 c0 test %al,%al
359: 74 75 je 3d0 <printint+0x90>
neg = 1;
x = -xx;
35b: 89 d0 mov %edx,%eax
int i, neg;
uint x;
neg = 0;
if(sgn && xx < 0){
neg = 1;
35d: c7 45 c4 01 00 00 00 movl $0x1,-0x3c(%ebp)
x = -xx;
364: f7 d8 neg %eax
366: 89 75 c0 mov %esi,-0x40(%ebp)
} else {
x = xx;
}
i = 0;
369: 31 ff xor %edi,%edi
36b: 8d 5d d7 lea -0x29(%ebp),%ebx
36e: 89 ce mov %ecx,%esi
370: eb 08 jmp 37a <printint+0x3a>
372: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
do{
buf[i++] = digits[x % base];
378: 89 cf mov %ecx,%edi
37a: 31 d2 xor %edx,%edx
37c: 8d 4f 01 lea 0x1(%edi),%ecx
37f: f7 f6 div %esi
381: 0f b6 92 08 07 00 00 movzbl 0x708(%edx),%edx
}while((x /= base) != 0);
388: 85 c0 test %eax,%eax
x = xx;
}
i = 0;
do{
buf[i++] = digits[x % base];
38a: 88 14 0b mov %dl,(%ebx,%ecx,1)
}while((x /= base) != 0);
38d: 75 e9 jne 378 <printint+0x38>
if(neg)
38f: 8b 45 c4 mov -0x3c(%ebp),%eax
392: 8b 75 c0 mov -0x40(%ebp),%esi
395: 85 c0 test %eax,%eax
397: 74 08 je 3a1 <printint+0x61>
buf[i++] = '-';
399: c6 44 0d d8 2d movb $0x2d,-0x28(%ebp,%ecx,1)
39e: 8d 4f 02 lea 0x2(%edi),%ecx
3a1: 8d 7c 0d d7 lea -0x29(%ebp,%ecx,1),%edi
3a5: 8d 76 00 lea 0x0(%esi),%esi
3a8: 0f b6 07 movzbl (%edi),%eax
#include "user.h"
static void
putc(int fd, char c)
{
write(fd, &c, 1);
3ab: 83 ec 04 sub $0x4,%esp
3ae: 83 ef 01 sub $0x1,%edi
3b1: 6a 01 push $0x1
3b3: 53 push %ebx
3b4: 56 push %esi
3b5: 88 45 d7 mov %al,-0x29(%ebp)
3b8: e8 d5 fe ff ff call 292 <write>
buf[i++] = digits[x % base];
}while((x /= base) != 0);
if(neg)
buf[i++] = '-';
while(--i >= 0)
3bd: 83 c4 10 add $0x10,%esp
3c0: 39 df cmp %ebx,%edi
3c2: 75 e4 jne 3a8 <printint+0x68>
putc(fd, buf[i]);
}
3c4: 8d 65 f4 lea -0xc(%ebp),%esp
3c7: 5b pop %ebx
3c8: 5e pop %esi
3c9: 5f pop %edi
3ca: 5d pop %ebp
3cb: c3 ret
3cc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
neg = 0;
if(sgn && xx < 0){
neg = 1;
x = -xx;
} else {
x = xx;
3d0: 89 d0 mov %edx,%eax
static char digits[] = "0123456789ABCDEF";
char buf[16];
int i, neg;
uint x;
neg = 0;
3d2: c7 45 c4 00 00 00 00 movl $0x0,-0x3c(%ebp)
3d9: eb 8b jmp 366 <printint+0x26>
3db: 90 nop
3dc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
000003e0 <printf>:
}
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
3e0: 55 push %ebp
3e1: 89 e5 mov %esp,%ebp
3e3: 57 push %edi
3e4: 56 push %esi
3e5: 53 push %ebx
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
3e6: 8d 45 10 lea 0x10(%ebp),%eax
}
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
3e9: 83 ec 2c sub $0x2c,%esp
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
3ec: 8b 75 0c mov 0xc(%ebp),%esi
}
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
3ef: 8b 7d 08 mov 0x8(%ebp),%edi
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
3f2: 89 45 d0 mov %eax,-0x30(%ebp)
3f5: 0f b6 1e movzbl (%esi),%ebx
3f8: 83 c6 01 add $0x1,%esi
3fb: 84 db test %bl,%bl
3fd: 0f 84 b0 00 00 00 je 4b3 <printf+0xd3>
403: 31 d2 xor %edx,%edx
405: eb 39 jmp 440 <printf+0x60>
407: 89 f6 mov %esi,%esi
409: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
410: 83 f8 25 cmp $0x25,%eax
413: 89 55 d4 mov %edx,-0x2c(%ebp)
state = '%';
416: ba 25 00 00 00 mov $0x25,%edx
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
41b: 74 18 je 435 <printf+0x55>
#include "user.h"
static void
putc(int fd, char c)
{
write(fd, &c, 1);
41d: 8d 45 e2 lea -0x1e(%ebp),%eax
420: 83 ec 04 sub $0x4,%esp
423: 88 5d e2 mov %bl,-0x1e(%ebp)
426: 6a 01 push $0x1
428: 50 push %eax
429: 57 push %edi
42a: e8 63 fe ff ff call 292 <write>
42f: 8b 55 d4 mov -0x2c(%ebp),%edx
432: 83 c4 10 add $0x10,%esp
435: 83 c6 01 add $0x1,%esi
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
438: 0f b6 5e ff movzbl -0x1(%esi),%ebx
43c: 84 db test %bl,%bl
43e: 74 73 je 4b3 <printf+0xd3>
c = fmt[i] & 0xff;
if(state == 0){
440: 85 d2 test %edx,%edx
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
c = fmt[i] & 0xff;
442: 0f be cb movsbl %bl,%ecx
445: 0f b6 c3 movzbl %bl,%eax
if(state == 0){
448: 74 c6 je 410 <printf+0x30>
if(c == '%'){
state = '%';
} else {
putc(fd, c);
}
} else if(state == '%'){
44a: 83 fa 25 cmp $0x25,%edx
44d: 75 e6 jne 435 <printf+0x55>
if(c == 'd'){
44f: 83 f8 64 cmp $0x64,%eax
452: 0f 84 f8 00 00 00 je 550 <printf+0x170>
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
458: 81 e1 f7 00 00 00 and $0xf7,%ecx
45e: 83 f9 70 cmp $0x70,%ecx
461: 74 5d je 4c0 <printf+0xe0>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
463: 83 f8 73 cmp $0x73,%eax
466: 0f 84 84 00 00 00 je 4f0 <printf+0x110>
s = "(null)";
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
46c: 83 f8 63 cmp $0x63,%eax
46f: 0f 84 ea 00 00 00 je 55f <printf+0x17f>
putc(fd, *ap);
ap++;
} else if(c == '%'){
475: 83 f8 25 cmp $0x25,%eax
478: 0f 84 c2 00 00 00 je 540 <printf+0x160>
#include "user.h"
static void
putc(int fd, char c)
{
write(fd, &c, 1);
47e: 8d 45 e7 lea -0x19(%ebp),%eax
481: 83 ec 04 sub $0x4,%esp
484: c6 45 e7 25 movb $0x25,-0x19(%ebp)
488: 6a 01 push $0x1
48a: 50 push %eax
48b: 57 push %edi
48c: e8 01 fe ff ff call 292 <write>
491: 83 c4 0c add $0xc,%esp
494: 8d 45 e6 lea -0x1a(%ebp),%eax
497: 88 5d e6 mov %bl,-0x1a(%ebp)
49a: 6a 01 push $0x1
49c: 50 push %eax
49d: 57 push %edi
49e: 83 c6 01 add $0x1,%esi
4a1: e8 ec fd ff ff call 292 <write>
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
4a6: 0f b6 5e ff movzbl -0x1(%esi),%ebx
#include "user.h"
static void
putc(int fd, char c)
{
write(fd, &c, 1);
4aa: 83 c4 10 add $0x10,%esp
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
}
state = 0;
4ad: 31 d2 xor %edx,%edx
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
4af: 84 db test %bl,%bl
4b1: 75 8d jne 440 <printf+0x60>
putc(fd, c);
}
state = 0;
}
}
}
4b3: 8d 65 f4 lea -0xc(%ebp),%esp
4b6: 5b pop %ebx
4b7: 5e pop %esi
4b8: 5f pop %edi
4b9: 5d pop %ebp
4ba: c3 ret
4bb: 90 nop
4bc: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
} else if(state == '%'){
if(c == 'd'){
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
printint(fd, *ap, 16, 0);
4c0: 83 ec 0c sub $0xc,%esp
4c3: b9 10 00 00 00 mov $0x10,%ecx
4c8: 6a 00 push $0x0
4ca: 8b 5d d0 mov -0x30(%ebp),%ebx
4cd: 89 f8 mov %edi,%eax
4cf: 8b 13 mov (%ebx),%edx
4d1: e8 6a fe ff ff call 340 <printint>
ap++;
4d6: 89 d8 mov %ebx,%eax
4d8: 83 c4 10 add $0x10,%esp
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
}
state = 0;
4db: 31 d2 xor %edx,%edx
if(c == 'd'){
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
printint(fd, *ap, 16, 0);
ap++;
4dd: 83 c0 04 add $0x4,%eax
4e0: 89 45 d0 mov %eax,-0x30(%ebp)
4e3: e9 4d ff ff ff jmp 435 <printf+0x55>
4e8: 90 nop
4e9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
} else if(c == 's'){
s = (char*)*ap;
4f0: 8b 45 d0 mov -0x30(%ebp),%eax
4f3: 8b 18 mov (%eax),%ebx
ap++;
4f5: 83 c0 04 add $0x4,%eax
4f8: 89 45 d0 mov %eax,-0x30(%ebp)
if(s == 0)
s = "(null)";
4fb: b8 00 07 00 00 mov $0x700,%eax
500: 85 db test %ebx,%ebx
502: 0f 44 d8 cmove %eax,%ebx
while(*s != 0){
505: 0f b6 03 movzbl (%ebx),%eax
508: 84 c0 test %al,%al
50a: 74 23 je 52f <printf+0x14f>
50c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
510: 88 45 e3 mov %al,-0x1d(%ebp)
#include "user.h"
static void
putc(int fd, char c)
{
write(fd, &c, 1);
513: 8d 45 e3 lea -0x1d(%ebp),%eax
516: 83 ec 04 sub $0x4,%esp
519: 6a 01 push $0x1
ap++;
if(s == 0)
s = "(null)";
while(*s != 0){
putc(fd, *s);
s++;
51b: 83 c3 01 add $0x1,%ebx
#include "user.h"
static void
putc(int fd, char c)
{
write(fd, &c, 1);
51e: 50 push %eax
51f: 57 push %edi
520: e8 6d fd ff ff call 292 <write>
} else if(c == 's'){
s = (char*)*ap;
ap++;
if(s == 0)
s = "(null)";
while(*s != 0){
525: 0f b6 03 movzbl (%ebx),%eax
528: 83 c4 10 add $0x10,%esp
52b: 84 c0 test %al,%al
52d: 75 e1 jne 510 <printf+0x130>
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
}
state = 0;
52f: 31 d2 xor %edx,%edx
531: e9 ff fe ff ff jmp 435 <printf+0x55>
536: 8d 76 00 lea 0x0(%esi),%esi
539: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
#include "user.h"
static void
putc(int fd, char c)
{
write(fd, &c, 1);
540: 83 ec 04 sub $0x4,%esp
543: 88 5d e5 mov %bl,-0x1b(%ebp)
546: 8d 45 e5 lea -0x1b(%ebp),%eax
549: 6a 01 push $0x1
54b: e9 4c ff ff ff jmp 49c <printf+0xbc>
} else {
putc(fd, c);
}
} else if(state == '%'){
if(c == 'd'){
printint(fd, *ap, 10, 1);
550: 83 ec 0c sub $0xc,%esp
553: b9 0a 00 00 00 mov $0xa,%ecx
558: 6a 01 push $0x1
55a: e9 6b ff ff ff jmp 4ca <printf+0xea>
55f: 8b 5d d0 mov -0x30(%ebp),%ebx
#include "user.h"
static void
putc(int fd, char c)
{
write(fd, &c, 1);
562: 83 ec 04 sub $0x4,%esp
565: 8b 03 mov (%ebx),%eax
567: 6a 01 push $0x1
569: 88 45 e4 mov %al,-0x1c(%ebp)
56c: 8d 45 e4 lea -0x1c(%ebp),%eax
56f: 50 push %eax
570: 57 push %edi
571: e8 1c fd ff ff call 292 <write>
576: e9 5b ff ff ff jmp 4d6 <printf+0xf6>
57b: 66 90 xchg %ax,%ax
57d: 66 90 xchg %ax,%ax
57f: 90 nop
00000580 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
580: 55 push %ebp
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
581: a1 a0 09 00 00 mov 0x9a0,%eax
static Header base;
static Header *freep;
void
free(void *ap)
{
586: 89 e5 mov %esp,%ebp
588: 57 push %edi
589: 56 push %esi
58a: 53 push %ebx
58b: 8b 5d 08 mov 0x8(%ebp),%ebx
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
58e: 8b 10 mov (%eax),%edx
void
free(void *ap)
{
Header *bp, *p;
bp = (Header*)ap - 1;
590: 8d 4b f8 lea -0x8(%ebx),%ecx
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
593: 39 c8 cmp %ecx,%eax
595: 73 19 jae 5b0 <free+0x30>
597: 89 f6 mov %esi,%esi
599: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
5a0: 39 d1 cmp %edx,%ecx
5a2: 72 1c jb 5c0 <free+0x40>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
5a4: 39 d0 cmp %edx,%eax
5a6: 73 18 jae 5c0 <free+0x40>
static Header base;
static Header *freep;
void
free(void *ap)
{
5a8: 89 d0 mov %edx,%eax
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
5aa: 39 c8 cmp %ecx,%eax
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
5ac: 8b 10 mov (%eax),%edx
free(void *ap)
{
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
5ae: 72 f0 jb 5a0 <free+0x20>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
5b0: 39 d0 cmp %edx,%eax
5b2: 72 f4 jb 5a8 <free+0x28>
5b4: 39 d1 cmp %edx,%ecx
5b6: 73 f0 jae 5a8 <free+0x28>
5b8: 90 nop
5b9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
break;
if(bp + bp->s.size == p->s.ptr){
5c0: 8b 73 fc mov -0x4(%ebx),%esi
5c3: 8d 3c f1 lea (%ecx,%esi,8),%edi
5c6: 39 d7 cmp %edx,%edi
5c8: 74 19 je 5e3 <free+0x63>
bp->s.size += p->s.ptr->s.size;
bp->s.ptr = p->s.ptr->s.ptr;
} else
bp->s.ptr = p->s.ptr;
5ca: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
5cd: 8b 50 04 mov 0x4(%eax),%edx
5d0: 8d 34 d0 lea (%eax,%edx,8),%esi
5d3: 39 f1 cmp %esi,%ecx
5d5: 74 23 je 5fa <free+0x7a>
p->s.size += bp->s.size;
p->s.ptr = bp->s.ptr;
} else
p->s.ptr = bp;
5d7: 89 08 mov %ecx,(%eax)
freep = p;
5d9: a3 a0 09 00 00 mov %eax,0x9a0
}
5de: 5b pop %ebx
5df: 5e pop %esi
5e0: 5f pop %edi
5e1: 5d pop %ebp
5e2: c3 ret
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
break;
if(bp + bp->s.size == p->s.ptr){
bp->s.size += p->s.ptr->s.size;
5e3: 03 72 04 add 0x4(%edx),%esi
5e6: 89 73 fc mov %esi,-0x4(%ebx)
bp->s.ptr = p->s.ptr->s.ptr;
5e9: 8b 10 mov (%eax),%edx
5eb: 8b 12 mov (%edx),%edx
5ed: 89 53 f8 mov %edx,-0x8(%ebx)
} else
bp->s.ptr = p->s.ptr;
if(p + p->s.size == bp){
5f0: 8b 50 04 mov 0x4(%eax),%edx
5f3: 8d 34 d0 lea (%eax,%edx,8),%esi
5f6: 39 f1 cmp %esi,%ecx
5f8: 75 dd jne 5d7 <free+0x57>
p->s.size += bp->s.size;
5fa: 03 53 fc add -0x4(%ebx),%edx
p->s.ptr = bp->s.ptr;
} else
p->s.ptr = bp;
freep = p;
5fd: a3 a0 09 00 00 mov %eax,0x9a0
bp->s.size += p->s.ptr->s.size;
bp->s.ptr = p->s.ptr->s.ptr;
} else
bp->s.ptr = p->s.ptr;
if(p + p->s.size == bp){
p->s.size += bp->s.size;
602: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
605: 8b 53 f8 mov -0x8(%ebx),%edx
608: 89 10 mov %edx,(%eax)
} else
p->s.ptr = bp;
freep = p;
}
60a: 5b pop %ebx
60b: 5e pop %esi
60c: 5f pop %edi
60d: 5d pop %ebp
60e: c3 ret
60f: 90 nop
00000610 <malloc>:
return freep;
}
void*
malloc(uint nbytes)
{
610: 55 push %ebp
611: 89 e5 mov %esp,%ebp
613: 57 push %edi
614: 56 push %esi
615: 53 push %ebx
616: 83 ec 0c sub $0xc,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
619: 8b 45 08 mov 0x8(%ebp),%eax
if((prevp = freep) == 0){
61c: 8b 15 a0 09 00 00 mov 0x9a0,%edx
malloc(uint nbytes)
{
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
622: 8d 78 07 lea 0x7(%eax),%edi
625: c1 ef 03 shr $0x3,%edi
628: 83 c7 01 add $0x1,%edi
if((prevp = freep) == 0){
62b: 85 d2 test %edx,%edx
62d: 0f 84 a3 00 00 00 je 6d6 <malloc+0xc6>
633: 8b 02 mov (%edx),%eax
635: 8b 48 04 mov 0x4(%eax),%ecx
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
if(p->s.size >= nunits){
638: 39 cf cmp %ecx,%edi
63a: 76 74 jbe 6b0 <malloc+0xa0>
63c: 81 ff 00 10 00 00 cmp $0x1000,%edi
642: be 00 10 00 00 mov $0x1000,%esi
647: 8d 1c fd 00 00 00 00 lea 0x0(,%edi,8),%ebx
64e: 0f 43 f7 cmovae %edi,%esi
651: ba 00 80 00 00 mov $0x8000,%edx
656: 81 ff ff 0f 00 00 cmp $0xfff,%edi
65c: 0f 46 da cmovbe %edx,%ebx
65f: eb 10 jmp 671 <malloc+0x61>
661: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
668: 8b 02 mov (%edx),%eax
if(p->s.size >= nunits){
66a: 8b 48 04 mov 0x4(%eax),%ecx
66d: 39 cf cmp %ecx,%edi
66f: 76 3f jbe 6b0 <malloc+0xa0>
p->s.size = nunits;
}
freep = prevp;
return (void*)(p + 1);
}
if(p == freep)
671: 39 05 a0 09 00 00 cmp %eax,0x9a0
677: 89 c2 mov %eax,%edx
679: 75 ed jne 668 <malloc+0x58>
char *p;
Header *hp;
if(nu < 4096)
nu = 4096;
p = sbrk(nu * sizeof(Header));
67b: 83 ec 0c sub $0xc,%esp
67e: 53 push %ebx
67f: e8 76 fc ff ff call 2fa <sbrk>
if(p == (char*)-1)
684: 83 c4 10 add $0x10,%esp
687: 83 f8 ff cmp $0xffffffff,%eax
68a: 74 1c je 6a8 <malloc+0x98>
return 0;
hp = (Header*)p;
hp->s.size = nu;
68c: 89 70 04 mov %esi,0x4(%eax)
free((void*)(hp + 1));
68f: 83 ec 0c sub $0xc,%esp
692: 83 c0 08 add $0x8,%eax
695: 50 push %eax
696: e8 e5 fe ff ff call 580 <free>
return freep;
69b: 8b 15 a0 09 00 00 mov 0x9a0,%edx
}
freep = prevp;
return (void*)(p + 1);
}
if(p == freep)
if((p = morecore(nunits)) == 0)
6a1: 83 c4 10 add $0x10,%esp
6a4: 85 d2 test %edx,%edx
6a6: 75 c0 jne 668 <malloc+0x58>
return 0;
6a8: 31 c0 xor %eax,%eax
6aa: eb 1c jmp 6c8 <malloc+0xb8>
6ac: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
if(p->s.size >= nunits){
if(p->s.size == nunits)
6b0: 39 cf cmp %ecx,%edi
6b2: 74 1c je 6d0 <malloc+0xc0>
prevp->s.ptr = p->s.ptr;
else {
p->s.size -= nunits;
6b4: 29 f9 sub %edi,%ecx
6b6: 89 48 04 mov %ecx,0x4(%eax)
p += p->s.size;
6b9: 8d 04 c8 lea (%eax,%ecx,8),%eax
p->s.size = nunits;
6bc: 89 78 04 mov %edi,0x4(%eax)
}
freep = prevp;
6bf: 89 15 a0 09 00 00 mov %edx,0x9a0
return (void*)(p + 1);
6c5: 83 c0 08 add $0x8,%eax
}
if(p == freep)
if((p = morecore(nunits)) == 0)
return 0;
}
}
6c8: 8d 65 f4 lea -0xc(%ebp),%esp
6cb: 5b pop %ebx
6cc: 5e pop %esi
6cd: 5f pop %edi
6ce: 5d pop %ebp
6cf: c3 ret
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
if(p->s.size >= nunits){
if(p->s.size == nunits)
prevp->s.ptr = p->s.ptr;
6d0: 8b 08 mov (%eax),%ecx
6d2: 89 0a mov %ecx,(%edx)
6d4: eb e9 jmp 6bf <malloc+0xaf>
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
6d6: c7 05 a0 09 00 00 a4 movl $0x9a4,0x9a0
6dd: 09 00 00
6e0: c7 05 a4 09 00 00 a4 movl $0x9a4,0x9a4
6e7: 09 00 00
base.s.size = 0;
6ea: b8 a4 09 00 00 mov $0x9a4,%eax
6ef: c7 05 a8 09 00 00 00 movl $0x0,0x9a8
6f6: 00 00 00
6f9: e9 3e ff ff ff jmp 63c <malloc+0x2c>
|
; IntToStr
.proc @ValueToStr (.word ya) .reg
sta adr
sty adr+1
mva #{bit*} @printVALUE.pout
mva <@buf+1 @printVALUE.pbuf
jsr $ffff
adr equ *-2
ldy @printVALUE.pbuf
dey
sty @buf
rts
.endp
; Value To Record
.proc @ValueToRec (.word ya) .reg
sta adr
sty adr+1
mva #{bit*} @printVALUE.pout
mva <@buf @printVALUE.pbuf
jsr $ffff
adr equ *-2
ldy @printVALUE.pbuf
rts
.endp
|
db 0 ; species ID placeholder
db 80, 105, 65, 70, 100, 60
; hp atk def spd sat sdf
db GRASS, POISON ; type
db 45 ; catch rate
db 191 ; base exp
db NO_ITEM, NO_ITEM ; items
db GENDER_F0 ; gender ratio
db 100 ; unknown 1
db 20 ; step cycles to hatch
db 5 ; unknown 2
INCBIN "gfx/pokemon/victreebel/front.dimensions"
db 0, 0, 0, 0 ; padding
db GROWTH_MEDIUM_SLOW ; growth rate
dn EGG_PLANT, EGG_PLANT ; egg groups
; tm/hm learnset
tmhm CURSE, TOXIC, HIDDEN_POWER, SUNNY_DAY, SWEET_SCENT, SNORE, HYPER_BEAM, PROTECT, GIGA_DRAIN, ENDURE, FRUSTRATION, SOLARBEAM, RETURN, DOUBLE_TEAM, SWAGGER, SLEEP_TALK, SLUDGE_BOMB, REST, ATTRACT, CUT, FLASH
; end
|
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