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%define SYS_READ 0
%define SYS_WRITE 1
%define SYS_OPEN 2
%define SYS_CLOSE 3
%define SYS_STAT 4
%define SYS_FSTAT 5
%define SYS_LSTAT 6
%define SYS_POLL 7
%define SYS_LSEEK 8
%define SYS_MMAP 9
%define SYS_MPROTECT 10
%define SYS_MUNMAP 11
%define SYS_BRK 12
%define SYS_RT_SIGACTION 13
%define SYS_RT_SIGPROCMASK 14
%define SYS_RT_SIGRETURN 15
%define SYS_IOCTL 16
%define SYS_PREAD64 17
%define SYS_PWRITE64 18
%define SYS_READVV 2
%define SYS_PIPE 22
%define SYS_SELECT 23
%define SYS_SCHED_YIELD 24
%define SYS_MREMAP 25
%define SYS_MSYNC 26
%define SYS_MINCORE 27
%define SYS_MADVISE 28
%define SYS_SHMGET 29
%define SYS_SHMAT 30
%define SYS_SHMCTL 31
%define SYS_DUP 32
%define SYS_DUP2 33
%define SYS_PAUSE 34
%define SYS_NANOSLEEP 35
%define SYS_GETITIMER 36
%define SYS_ALARM 37
%define SYS_SETITIMER 38
%define SYS_GETPID 39
%define SYS_SENDFILE 40
%define SYS_SOCKET 41
%define SYS_CONNECT 42
%define SYS_ACCEPT 43
%define SYS_SENDTO 44
%define SYS_RECVFROM 45
%define SYS_SENDMSG 46
%define SYS_RECVMSG 47
%define SYS_SHUTDOWN 48
%define SYS_BIND 49
%define SYS_LISTEN 50
%define SYS_GETSOCKNAME 51
%define SYS_GETPEERNAME 52
%define SYS_SOCKETPAIR 53
%define SYS_SETSOCKOPT 54
%define SYS_GETSOCKOPT 55
%define SYS_CLONE 56
%define SYS_FORK 57
%define SYS_VFORK 58
%define SYS_EXECVE 59
%define SYS_EXIT 60
%define SYS_WAIT4 61
%define SYS_KILL 62
%define SYS_UNAME 63
%define SYS_SEMGET 64
%define SYS_SEMOP 65
%define SYS_SEMCTL 66
%define SYS_SHMDT 67
%define SYS_MSGGET 68
%define SYS_MSGSND 69
%define SYS_MSGRCV 70
%define SYS_MSGCTL 71
%define SYS_FCNTL 72
%define SYS_FLOCK 73
%define SYS_FSYNC 74
%define SYS_FDATASYNC 75
%define SYS_TRUNCATE 76
%define SYS_FTRUNCATE 77
%define SYS_GETDENTS 78
%define SYS_GETCWD 79
%define SYS_CHDIR 80
%define SYS_FCHDIR 81
%define SYS_RENAME 82
%define SYS_MKDIR 83
%define SYS_RMDIR 84
%define SYS_CREAT 85
%define SYS_LINK 86
%define SYS_UNLINK 87
%define SYS_SYMLINK 88
%define SYS_READLINK 89
%define SYS_CHMOD 90
%define SYS_FCHMOD 91
%define SYS_CHOWN 92
%define SYS_FCHOWN 93
%define SYS_LCHOWN 94
%define SYS_UMASK 95
%define SYS_GETTIMEOFDAY 96
%define SYS_GETRLIMIT 97
%define SYS_GETRUSAGE 98
%define SYS_SYSINFO 99
%define SYS_TIMES 100
%define SYS_PTRACE 101
%define SYS_GETUID 102
%define SYS_SYSLOG 103
%define SYS_GETGID 104
%define SYS_SETUID 105
%define SYS_SETGID 106
%define SYS_GETEUID 107
%define SYS_GETEGID 108
%define SYS_SETPGID 109
%define SYS_GETPPID 110
%define SYS_GETPGRP 111
%define SYS_SETSID 112
%define SYS_SETREUID 113
%define SYS_SETREGID 114
%define SYS_GETGROUPS 115
%define SYS_SETGROUPS 116
%define SYS_SETRESUID 117
%define SYS_GETRESUID 118
%define SYS_SETRESGID 119
%define SYS_GETRESGID 120
%define SYS_GETPGID 121
%define SYS_SETFSUID 122
%define SYS_SETFSGID 123
%define SYS_GETSID 124
%define SYS_CAPGET 125
%define SYS_CAPSET 126
%define SYS_RT_SIGPENDING 127
%define SYS_RT_SIGTIMEDWAIT 128
%define SYS_RT_SIGQUEUEINFO 129
%define SYS_RT_SIGSUSPEND 130
%define SYS_SIGALTSTACK 131
%define SYS_UTIME 132
%define SYS_MKNOD 133
%define SYS_USELIB 134
%define SYS_PERSONALITY 135
%define SYS_USTAT 136
%define SYS_STATFS 137
%define SYS_FSTATFS 138
%define SYS_SYSFS 139
%define SYS_GETPRIORITY 140
%define SYS_SETPRIORITY 141
%define SYS_SCHED_SETPARAM 142
%define SYS_SCHED_GETPARAM 143
%define SYS_SCHED_SETSCHEDULER 144
%define SYS_SCHED_GETSCHEDULER 145
%define SYS_SCHED_GET_PRIORITY_MAX 146
%define SYS_SCHED_GET_PRIORITY_MIN 147
%define SYS_SCHED_RR_GET_INTERVAL 148
%define SYS_MLOCK 149
%define SYS_MUNLOCK 150
%define SYS_MLOCKALL 151
%define SYS_MUNLOCKALL 152
%define SYS_VHANGUP 153
%define SYS_MODIFY_LDT 154
%define SYS_PIVOT_ROOT 155
%define SYS__SYSCTL 156
%define SYS_PRCTL 157
%define SYS_ARCH_PRCTL 158
%define SYS_ADJTIMEX 159
%define SYS_SETRLIMIT 160
%define SYS_CHROOT 161
%define SYS_SYNC 162
%define SYS_ACCT 163
%define SYS_SETTIMEOFDAY 164
%define SYS_MOUNT 165
%define SYS_UMOUNT2 166
%define SYS_SWAPON 167
%define SYS_SWAPOFF 168
%define SYS_REBOOT 169
%define SYS_SETHOSTNAME 170
%define SYS_SETDOMAINNAME 171
%define SYS_IOPL 172
%define SYS_IOPERM 173
%define SYS_CREATE_MODULE 174
%define SYS_INIT_MODULE 175
%define SYS_DELETE_MODULE 176
%define SYS_GET_KERNEL_SYMS 177
%define SYS_QUERY_MODULE 178
%define SYS_QUOTACTL 179
%define SYS_NFSSERVCTL 180
%define SYS_GETPMSG 181
%define SYS_PUTPMSG 182
%define SYS_AFS_SYSCALL 183
%define SYS_TUXCALL 184
%define SYS_SECURITY 185
%define SYS_GETTID 186
%define SYS_READAHEAD 187
%define SYS_SETXATTR 188
%define SYS_LSETXATTR 189
%define SYS_FSETXATTR 190
%define SYS_GETXATTR 191
%define SYS_LGETXATTR 192
%define SYS_FGETXATTR 193
%define SYS_LISTXATTR 194
%define SYS_LLISTXATTR 195
%define SYS_FLISTXATTR 196
%define SYS_REMOVEXATTR 197
%define SYS_LREMOVEXATTR 198
%define SYS_FREMOVEXATTR 199
%define SYS_TKILL 200
%define SYS_TIME 201
%define SYS_FUTEX 202
%define SYS_SCHED_SETAFFINITY 203
%define SYS_SCHED_GETAFFINITY 204
%define SYS_SET_THREAD_AREA 205
%define SYS_IO_SETUP 206
%define SYS_IO_DESTROY 207
%define SYS_IO_GETEVENTS 208
%define SYS_IO_SUBMIT 209
%define SYS_IO_CANCEL 210
%define SYS_GET_THREAD_AREA 211
%define SYS_LOOKUP_DCOOKIE 212
%define SYS_EPOLL_CREATE 213
%define SYS_EPOLL_CTL_OLD 214
%define SYS_EPOLL_WAIT_OLD 215
%define SYS_REMAP_FILE_PAGES 216
%define SYS_GETDENTS64 217
%define SYS_SET_TID_ADDRESS 218
%define SYS_RESTART_SYSCALL 219
%define SYS_SEMTIMEDOP 220
%define SYS_FADVISE64 221
%define SYS_TIMER_CREATE 222
%define SYS_TIMER_SETTIME 223
%define SYS_TIMER_GETTIME 224
%define SYS_TIMER_GETOVERRUN 225
%define SYS_TIMER_DELETE 226
%define SYS_CLOCK_SETTIME 227
%define SYS_CLOCK_GETTIME 228
%define SYS_CLOCK_GETRES 229
%define SYS_CLOCK_NANOSLEEP 230
%define SYS_EXIT_GROUP 231
%define SYS_EPOLL_WAIT 232
%define SYS_EPOLL_CTL 233
%define SYS_TGKILL 234
%define SYS_UTIMES 235
%define SYS_VSERVER 236
%define SYS_MBIND 237
%define SYS_SET_MEMPOLICY 238
%define SYS_GET_MEMPOLICY 239
%define SYS_MQ_OPEN 240
%define SYS_MQ_UNLINK 241
%define SYS_MQ_TIMEDSEND 242
%define SYS_MQ_TIMEDRECEIVE 243
%define SYS_MQ_NOTIFY 244
%define SYS_MQ_GETSETATTR 245
%define SYS_KEXEC_LOAD 246
%define SYS_WAITID 247
%define SYS_ADD_KEY 248
%define SYS_REQUEST_KEY 249
%define SYS_KEYCTL 250
%define SYS_IOPRIO_SET 251
%define SYS_IOPRIO_GET 252
%define SYS_INOTIFY_INIT 253
%define SYS_INOTIFY_ADD_WATCH 254
%define SYS_INOTIFY_RM_WATCH 255
%define SYS_MIGRATE_PAGES 256
%define SYS_OPENAT 257
%define SYS_MKDIRAT 258
%define SYS_MKNODAT 259
%define SYS_FCHOWNAT 260
%define SYS_FUTIMESAT 261
%define SYS_NEWFSTATAT 262
%define SYS_UNLINKAT 263
%define SYS_RENAMEAT 264
%define SYS_LINKAT 265
%define SYS_SYMLINKAT 266
%define SYS_READLINKAT 267
%define SYS_FCHMODAT 268
%define SYS_FACCESSAT 269
%define SYS_PSELECT6 270
%define SYS_PPOLL 271
%define SYS_UNSHARE 272
%define SYS_SET_ROBUST_LIST 273
%define SYS_GET_ROBUST_LIST 274
%define SYS_SPLICE 275
%define SYS_TEE 276
%define SYS_SYNC_FILE_RANGE 277
%define SYS_VMSPLICE 278
%define SYS_MOVE_PAGES 279
%define SYS_UTIMENSAT 280
%define SYS_EPOLL_PWAIT 281
%define SYS_SIGNALFD 282
%define SYS_TIMERFD_CREATE 283
%define SYS_EVENTFD 284
%define SYS_FALLOCATE 285
%define SYS_TIMERFD_SETTIME 286
%define SYS_TIMERFD_GETTIME 287
%define SYS_ACCEPT4 288
%define SYS_SIGNALFD4 289
%define SYS_EVENTFD2 290
%define SYS_EPOLL_CREATE1 291
%define SYS_DUP3 292
%define SYS_PIPE2 293
%define SYS_INOTIFY_INIT1 294
%define SYS_PREADV 295
%define SYS_PWRITEV 296
%define SYS_RT_TGSIGQUEUEINFO 297
%define SYS_PERF_EVENT_OPEN 298
%define SYS_RECVMMSG 299
%define SYS_FANOTIFY_INIT 300
%define SYS_FANOTIFY_MARK 301
%define SYS_PRLIMIT64 302
%define SYS_NAME_TO_HANDLE_AT 303
%define SYS_OPEN_BY_HANDLE_AT 304
%define SYS_CLOCK_ADJTIME 305
%define SYS_SYNCFS 306
%define SYS_SENDMMSG 307
%define SYS_SETNS 308
%define SYS_GETCPU 309
%define SYS_PROCESS_VM_READV 310
%define SYS_PROCESS_VM_WRITEV 311
%define SYS_KCMP 312
%define SYS_FINIT_MODULE 313
%define SYS_SCHED_SETATTR 314
%define SYS_SCHED_GETATTR 315
%define SYS_RENAMEAT2 316
%define SYS_SECCOMP 317
%define SYS_GETRANDOM 318
%define SYS_MEMFD_CREATE 319
%define SYS_KEXEC_FILE_LOAD 320
%define SYS_BPF 321
%define SYS_EXECVEAT 322
%define SYS_USERFAULTFD 323
%define SYS_MEMBARRIER 324
%define SYS_MLOCK2 325
%define CAP_CHOWN 0
%define CAP_DAC_OVERRIDE 1
%define CAP_DAC_READ_SEARCH 2
%define CAP_FOWNER 3
%define CAP_FSETID 4
%define CAP_KILL 5
%define CAP_SETGID 6
%define CAP_SETUID 7
%define CAP_SETPCAP 8
%define CAP_LINUX_IMMUTABLE 9
%define CAP_NET_BIND_SERVICE 10
%define CAP_NET_BROADCAST 11
%define CAP_NET_ADMIN 12
%define CAP_NET_RAW 13
%define CAP_IPC_LOCK 14
%define CAP_IPC_OWNER 15
%define CAP_SYS_MODULE 16
%define CAP_SYS_RAWIO 17
%define CAP_SYS_CHROOT 18
%define CAP_SYS_PTRACE 19
%define CAP_SYS_PACCT 20
%define CAP_SYS_ADMIN 21
%define CAP_SYS_BOOT 22
%define CAP_SYS_NICE 23
%define CAP_SYS_RESOURCE 24
%define CAP_SYS_TIME 25
%define CAP_SYS_TTY_CONFIG 26
%define CAP_MKNOD 27
%define CAP_LEASE 28
%define CAP_AUDIT_WRITE 29
%define CAP_AUDIT_CONTROL 30
%define CAP_SETFCAP 31
%define CAP_MAC_OVERRIDE 32
%define CAP_MAC_ADMIN 33
%define CAP_SYSLOG 34
%define CAP_WAKE_ALARM 35
%define CAP_BLOCK_SUSPEND 36
%define CAP_AUDIT_READ 37
%define CAP_PERFMON 38
%define CAP_BPF 39
%define PR_SET_PDEATHSIG 1
%define PR_GET_PDEATHSIG 2
%define PR_GET_DUMPABLE 3
%define PR_SET_DUMPABLE 4
%define PR_GET_UNALIGN 5
%define PR_SET_UNALIGN 6
%define PR_GET_KEEPCAPS 7
%define PR_SET_KEEPCAPS 8
%define PR_GET_FPEMU 9
%define PR_SET_FPEMU 10
%define PR_GET_FPEXC 11
%define PR_SET_FPEXC 12
%define PR_GET_TIMING 13
%define PR_SET_TIMING 14
%define PR_TIMING_STATISTICAL 0
%define PR_TIMING_TIMESTAMP 1
%define PR_SET_NAME 15
%define PR_GET_NAME 16
%define PR_GET_ENDIAN 19
%define PR_SET_ENDIAN 20
%define PR_ENDIAN_BIG 0
%define PR_ENDIAN_LITTLE 1
%define PR_ENDIAN_PPC_LITTLE 2
%define PR_GET_SECCOMP 21
%define PR_SET_SECCOMP 22
%define PR_CAPBSET_READ 23
%define PR_CAPBSET_DROP 24
%define PR_GET_TSC 25
%define PR_SET_TSC 26
%define PR_TSC_ENABLE 1
%define PR_TSC_SIGSEGV 2
%define PR_GET_SECUREBITS 27
%define PR_SET_SECUREBITS 28
%define PR_SET_TIMERSLACK 29
%define PR_GET_TIMERSLACK 30
%define PR_TASK_PERF_EVENTS_DISABLE 31
%define PR_TASK_PERF_EVENTS_ENABLE 32
%define PR_MCE_KILL 33
%define PR_MCE_KILL_CLEAR 0
%define PR_MCE_KILL_SET 1
%define PR_MCE_KILL_LATE 0
%define PR_MCE_KILL_EARLY 1
%define PR_MCE_KILL_DEFAULT 2
%define PR_MCE_KILL_GET 34
%define PR_SET_MM 35
%define PR_SET_MM_START_CODE 1
%define PR_SET_MM_END_CODE 2
%define PR_SET_MM_START_DATA 3
%define PR_SET_MM_END_DATA 4
%define PR_SET_MM_START_STACK 5
%define PR_SET_MM_START_BRK 6
%define PR_SET_MM_BRK 7
%define PR_SET_MM_ARG_START 8
%define PR_SET_MM_ARG_END 9
%define PR_SET_MM_ENV_START 10
%define PR_SET_MM_ENV_END 11
%define PR_SET_MM_AUXV 12
%define PR_SET_MM_EXE_FILE 13
%define PR_SET_MM_MAP 14
%define PR_SET_MM_MAP_SIZE 15
%define PR_SET_PTRACER 0x59616d61
%define PR_SET_CHILD_SUBREAPER 36
%define PR_GET_CHILD_SUBREAPER 37
%define PR_SET_NO_NEW_PRIVS 38
%define PR_GET_NO_NEW_PRIVS 39
%define PR_GET_TID_ADDRESS 40
%define PR_SET_THP_DISABLE 41
%define PR_GET_THP_DISABLE 42
%define PR_MPX_ENABLE_MANAGEMENT 43
%define PR_MPX_DISABLE_MANAGEMENT 44
%define PR_SET_FP_MODE 45
%define PR_GET_FP_MODE 46
%define PR_CAP_AMBIENT 47
%define PR_CAP_AMBIENT_IS_SET 1
%define PR_CAP_AMBIENT_RAISE 2
%define PR_CAP_AMBIENT_LOWER 3
%define PR_CAP_AMBIENT_CLEAR_ALL 4
%define SECONDS 1
%define MINUTES 60
%define HOURS 3600
%define DAYS 86400
%define YES 1
%define NO 0
%define TRUE 1
%define FALSE 0
%define MAX_PRIO -20
%define MIN_PRIO 19
%define _ASM_X86_SIGNAL_H
%define NSIG 32
%define SIGHUP 1
%define SIGINT 2
%define SIGQUIT 3
%define SIGILL 4
%define SIGTRAP 5
%define SIGABRT 6
%define SIGIOT 6
%define SIGBUS 7
%define SIGFPE 8
%define SIGKILL 9
%define SIGUSR1 10
%define SIGSEGV 11
%define SIGUSR2 12
%define SIGPIPE 13
%define SIGALRM 14
%define SIGTERM 15
%define SIGSTKFLT 16
%define SIGCHLD 17
%define SIGCONT 18
%define SIGSTOP 19
%define SIGTSTP 20
%define SIGTTIN 21
%define SIGTTOU 22
%define SIGURG 23
%define SIGXCPU 24
%define SIGXFSZ 25
%define SIGVTALRM 26
%define SIGPROF 27
%define SIGWINCH 28
%define SIGIO 29
%define SIGPOLL SIGIO
%define SIGLOST 29
%define SIGPWR 30
%define SIGSYS 31
%define SIGUNUSED 31
%define SIGRTMIN 32
%define SA_NOCLDSTOP 0x00000001u
%define SA_NOCLDWAIT 0x00000002u
%define SA_SIGINFO 0x00000004u
%define SA_ONSTACK 0x08000000u
%define SA_RESTART 0x10000000u
%define SA_NODEFER 0x40000000u
%define SA_RESETHAND 0x80000000u
%define SA_NOMASK SA_NODEFER
%define SA_ONESHOT SA_RESETHAND
%define SIG_BLOCK 1
%define SIG_UNBLOCK 2
%define SIG_SETMASK 3
%define O_ACCMODE 00000003
%define O_RDONLY 00000000
%define O_WRONLY 00000001
%define O_RDWR 00000002
%define O_CREAT 00000100
%define O_EXCL 00000200
%define O_NOCTTY 00000400
%define O_TRUNC 00001000
%define O_APPEND 00002000
%define O_NONBLOCK 00004000
%define O_DSYNC 00010000
%define FASYNC 00020000
%define O_DIRECT 00040000
%define O_LARGEFILE 00100000
%define O_DIRECTORY 00200000
%define O_NOFOLLOW 00400000
%define O_NOATIME 01000000
%define O_CLOEXEC 02000000
%define __O_SYNC 04000000
%define O_SYNC (__O_SYNC|O_DSYNC)
%define O_PATH 010000000
%define O_NDELAY O_NONBLOCK%
%define F_DUPFD 0
%define F_GETFD 1
%define F_SETFD 2
%define F_GETFL 3
%define F_SETFL 4
%define F_GETLK 5
%define F_SETLK 6
%define F_SETLKW 7
%define F_SETOWN 8
%define F_GETOWN 9
%define F_SETSIG 10
%define F_GETSIG 11
%define F_SETLK64 13
%define F_SETOWN_EX 15
%define F_OFD_GETLK 36
%define F_OFD_SETLK 37
%define F_OWNER_TID 0
%define F_OWNER_PID 1
%define F_OWNER_PGRP 2
%define FD_CLOEXEC 1
%define F_RDLCK 0
%define F_WRLCK 1
%define F_UNLCK 2
%define F_EXLCK 4
%define F_SHLCK 8
%define LOCK_SH 1
%define LOCK_EX 2
%define LOCK_NB 4
%define LOCK_MAND 32
%define LOCK_READ 64
%define LOCK_WRITE 128
%define LOCK_RW 192
%define F_LINUX_SPECIFIC_BASE 1024
%define _SYS_REBOOT_H 1
%define RB_AUTOBOOT 0x01234567
%define RB_HALT_SYSTEM 0xcdef0123
%define RB_ENABLE_CAD 0x89abcdef
%define RB_DISABLE_CAD 0
%define RB_POWER_OFF 0x4321fedc
%define RB_SW_SUSPEND 0xd000fce2
%define RB_KEXEC 0x45584543
%define INFO "[ * ] --- "
%define ERROR "[ x ] --- "
%define GOOD "[ + ] --- "
%define RW 0x402
%define EMPTY_STRING ""
%define MODULE_INIT_IGNORE_MODVERSIONS 1
%define MODULE_INIT_IGNORE_VERMAGIC 2
%define MFD_CLOEXEC 0x0001U
%define MFD_ALLOW_SEALING 0x0002U
%define MFD_HUGETLB 0x0004U
%define HUGETLB_FLAG_ENCODE_SHIFT 26
%define HUGETLB_FLAG_ENCODE_16KB 14 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_64KB 16 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_512KB 19 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_1MB 20 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_2MB 21 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_8MB 23 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_16MB 24 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_32MB 25 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_256MB 28 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_512MB 29 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_1GB 30 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_2GB 31 << HUGETLB_FLAG_ENCODE_SHIFT
%define HUGETLB_FLAG_ENCODE_16GB 34 << HUGETLB_FLAG_ENCODE_SHIFT
%define F_SEAL_SEAL 0x0001
%define F_SEAL_SHRINK 0x0002
%define F_SEAL_GROW 0x0004
%define F_SEAL_WRITE 0x0008
%define F_SEAL_FUTURE_WRITE 0x0010
%define F_GET_RW_HINT F_LINUX_SPECIFIC_BASE + 11
%define F_SET_RW_HINT F_LINUX_SPECIFIC_BASE + 12
%define F_GET_FILE_RW_HINT F_LINUX_SPECIFIC_BASE + 13
%define F_SET_FILE_RW_HINT F_LINUX_SPECIFIC_BASE + 14
%define RWH_WRITE_LIFE_NOT_SET 0
%define RWH_WRITE_LIFE_NONE 1
%define RWH_WRITE_LIFE_SHORT 2
%define RWH_WRITE_LIFE_MEDIUM 3
%define RWH_WRITE_LIFE_LONG 4
%define RWH_WRITE_LIFE_EXTREME 5
%define DN_ACCESS 0x00000001
%define DN_MODIFY 0x00000002
%define DN_CREATE 0x00000004
%define DN_DELETE 0x00000008
%define DN_RENAME 0x00000010
%define DN_ATTRIB 0x00000020
%define DN_MULTISHOT 0x80000000
%define AT_FDCWD -100
%define AT_SYMLINK_NOFOLLOW 0x100
%define AT_EACCESS 0x200
%define AT_REMOVEDIR 0x200
%define AT_SYMLINK_FOLLOW 0x400
%define AT_NO_AUTOMOUNT 0x800
%define AT_EMPTY_PATH 0x1000
%define AT_STATX_SYNC_TYPE 0x6000
%define AT_STATX_SYNC_AS_STAT 0x0000
%define AT_STATX_FORCE_SYNC 0x2000
%define AT_STATX_DONT_SYNC 0x4000
%define AT_RECURSIVE 0x8000
%define SOCK_STREAM 1
%define SOCK_DGRAM 2
%define SOCK_RAW 3
%define SOCK_RDM 4
%define SOCK_SEQPACKET 5
%define SOCK_DCCP 6
%define SOCK_PACKET 10
%define AF_UNSPEC 0
%define AF_UNIX 1
%define AF_LOCAL 1
%define AF_INET 2
%define AF_AX25 3
%define AF_IPX 4
%define AF_APPLETALK 5
%define AF_NETROM 6
%define AF_BRIDGE 7
%define AF_ATMPVC 8
%define AF_X25 9
%define AF_INET6 10
%define AF_ROSE 11
%define AF_DECnet 12
%define AF_NETBEUI 13
%define AF_SECURITY 14
%define AF_KEY 15
%define AF_NETLINK 16
%define AF_ROUTE AF_NETLINK
%define AF_PACKET 17
%define AF_ASH 18
%define AF_ECONET 19
%define AF_ATMSVC 20
%define AF_RDS 21
%define AF_SNA 22
%define AF_IRDA 23
%define AF_PPPOX 24
%define AF_WANPIPE 25
%define AF_LLC 26
%define AF_IB 27
%define AF_MPLS 28
%define AF_CAN 29
%define AF_TIPC 30
%define AF_BLUETOOTH 31
%define AF_IUCV 32
%define AF_RXRPC 33
%define AF_ISDN 34
%define AF_PHONET 35
%define AF_IEEE802154 36
%define AF_CAIF 37
%define AF_ALG 38
%define AF_NFC 39
%define AF_VSOCK 40
%define AF_KCM 41
%define AF_QIPCRTR 42
%define AF_SMC 43
%define AF_XDP 44
%define AF_MAX 45
%define PF_UNSPEC AF_UNSPEC
%define PF_UNIX AF_UNIX
%define PF_LOCAL AF_LOCAL
%define PF_INET AF_INET
%define PF_AX25 AF_AX25
%define PF_IPX AF_IPX
%define PF_APPLETALK AF_APPLETALK
%define PF_NETROM AF_NETROM
%define PF_BRIDGE AF_BRIDGE
%define PF_ATMPVC AF_ATMPVC
%define PF_X25 AF_X25
%define PF_INET6 AF_INET6
%define PF_ROSE AF_ROSE
%define PF_DECnet AF_DECnet
%define PF_NETBEUI AF_NETBEUI
%define PF_SECURITY AF_SECURITY
%define PF_KEY AF_KEY
%define PF_NETLINK AF_NETLINK
%define PF_ROUTE AF_ROUTE
%define PF_PACKET AF_PACKET
%define PF_ASH AF_ASH
%define PF_ECONET AF_ECONET
%define PF_ATMSVC AF_ATMSVC
%define PF_RDS AF_RDS
%define PF_SNA AF_SNA
%define PF_IRDA AF_IRDA
%define PF_PPPOX AF_PPPOX
%define PF_WANPIPE AF_WANPIPE
%define PF_LLC AF_LLC
%define PF_IB AF_IB
%define PF_MPLS AF_MPLS
%define PF_CAN AF_CAN
%define PF_TIPC AF_TIPC
%define PF_BLUETOOTH AF_BLUETOOTH
%define PF_IUCV AF_IUCV
%define PF_RXRPC AF_RXRPC
%define PF_ISDN AF_ISDN
%define PF_PHONET AF_PHONET
%define PF_IEEE802154 AF_IEEE802154
%define PF_CAIF AF_CAIF
%define PF_ALG AF_ALG
%define PF_NFC AF_NFC
%define PF_VSOCK AF_VSOCK
%define PF_KCM AF_KCM
%define PF_QIPCRTR AF_QIPCRTR
%define PF_SMC AF_SMC
%define PF_XDP AF_XDP
%define PF_MAX AF_MAX
%define SOMAXCONN 4096%
%define MSG_OOB 1
%define MSG_PEEK 2
%define MSG_DONTROUTE 4
%define MSG_TRYHARD 4
%define MSG_CTRUNC 8
%define MSG_PROBE 0x10
%define MSG_TRUNC 0x20
%define MSG_DONTWAIT 0x40
%define MSG_EOR 0x80
%define MSG_WAITALL 0x100
%define MSG_FIN 0x200
%define MSG_SYN 0x400
%define MSG_CONFIRM 0x800
%define MSG_RST 0x1000
%define MSG_ERRQUEUE 0x2000
%define MSG_NOSIGNAL 0x4000
%define MSG_MORE 0x8000
%define MSG_WAITFORONE 0x10000
%define MSG_SENDPAGE_NOPOLICY 0x10000
%define MSG_SENDPAGE_NOTLAST 0x20000
%define MSG_BATCH 0x40000
%define MSG_EOF MSG_FIN
%define MSG_NO_SHARED_FRAGS 0x80000
%define MSG_SENDPAGE_DECRYPTED 0x100000
%define MSG_ZEROCOPY 0x4000000
%define MSG_FASTOPEN 0x20000000
%define MSG_CMSG_CLOEXEC 0x40000000
%define MSG_CMSG_COMPAT 0
%define SOL_IP 0
%define SOL_TCP 6
%define SOL_UDP 17
%define SOL_IPV6 41
%define SOL_ICMPV6 58
%define SOL_SCTP 132
%define SOL_UDPLITE 136
%define SOL_RAW 255
%define SOL_IPX 256
%define SOL_AX25 257
%define SOL_ATALK 258
%define SOL_NETROM 259
%define SOL_ROSE 260
%define SOL_DECNET 261
%define SOL_X25 262
%define SOL_PACKET 263
%define SOL_ATM 264
%define SOL_AAL 265
%define SOL_IRDA 266
%define SOL_NETBEUI 267
%define SOL_LLC 268
%define SOL_DCCP 269
%define SOL_NETLINK 270
%define SOL_TIPC 271
%define SOL_RXRPC 272
%define SOL_PPPOL2TP 273
%define SOL_BLUETOOTH 274
%define SOL_PNPIPE 275
%define SOL_RDS 276
%define SOL_IUCV 277
%define SOL_CAIF 278
%define SOL_ALG 279
%define SOL_NFC 280
%define SOL_KCM 281
%define SOL_TLS 282
%define SOL_XDP 283
%define IPX_TYPE 1
%define LOCALHOST 0x0100007f
%define LOOPBACK 0x00000000
%define BROADCAST 0xffffffff
%define PRESENT 0x00000000
%define FUTURE 0xffffffff
%define SEEK_SET 0
%define SEEK_CUR 1
%define SEEK_END 2
%define SEEK_DATA 3
%define SEEK_HOLE 4
%define SEEK_MAX SEEK_HOLE
%define RUSAGE_SELF 0
%define RUSAGE_CHILDREN -1
%define RUSAGE_BOTH -2
%define RUSAGE_THREAD 1
%define PRIO_MIN -20
%define PRIO_MAX 20
%define ADDR_NO_RANDOMIZE 0x0040000
%define PRIO_PROCESS 0
%define PRIO_PGRP 1
%define PRIO_USER 2
%define _STK_LIM (8*1024*1024)
%define EHDR_SIZE 64
%define ELF64 2
%define O_RDONLY 0
%define O_RDWR 2
%define SEEK_END 2
%define DIRENT_BUFSIZE 1024
%define MFD_CLOEXEC 1
%define DT_REG 8
%define PT_LOAD 1
%define PT_NOTE 4
%define PF_X 1
%define PF_R 4
%define PAGE_SIZE 4096
%define EM_X86_64 0x3e
%define MAP_PRIVATE 0x2
%define PROT_READ 0x1
%define PROT_WRITE 0x2
%define DT_REG 0x8
%define PT_LOAD 0x1
%define STDOUT 1
%define SHT_NULL 0
%define SHT_PROGBITS 1
%define SHT_SYMTAB 2
%define SHT_STRTAB 3
%define SHT_RELA 4
%define SHT_HASH 5
%define SHT_DYNAMIC 6
%define SHT_NOTE 7
%define SHT_NOBITS 8
%define SHT_REL 9
%define SHT_SHLIB 10
%define SHT_DYNSYM 11
%define SHT_NUM 12
%define SHT_LOPROC 0x70000000
%define SHT_HIPROC 0x7fffffff
%define SHT_LOUSER 0x80000000
%define SHT_HIUSER 0xffffffff
%define SHF_WRITE 0x1
%define SHF_ALLOC 0x2
%define SHF_EXECINSTR 0x4
%define SHF_RELA_LIVEPATCH 0x00100000
%define SHF_RO_AFTER_INIT 0x00200000
%define SHF_MASKPROC 0xf0000000
%define SHN_UNDEF 0
%define SHN_LORESERVE 0xff00
%define SHN_LOPROC 0xff00
%define SHN_HIPROC 0xff1f
%define SHN_LIVEPATCH 0xff20
%define SHN_ABS 0xfff1
%define SHN_COMMON 0xfff2
%define SHN_HIRESERVE 0xffff |
; A342710: Solutions x to the Pell-Fermat equation x^2 - 5*y^2 = 4.
; 3,18,123,843,5778,39603,271443,1860498,12752043,87403803,599074578,4106118243,28143753123,192900153618,1322157322203,9062201101803,62113250390418,425730551631123,2918000611027443,20000273725560978,137083915467899403,939587134549734843
mov $1,1
lpb $0
sub $0,1
sub $2,$1
sub $1,$2
lpe
pow $1,2
div $1,3
mul $1,15
add $1,3
mov $0,$1
|
// Created on: 1996-08-30
// Created by: Yves FRICAUD
// Copyright (c) 1996-1999 Matra Datavision
// Copyright (c) 1999-2014 OPEN CASCADE SAS
//
// This file is part of Open CASCADE Technology software library.
//
// This library is free software; you can redistribute it and/or modify it under
// the terms of the GNU Lesser General Public License version 2.1 as published
// by the Free Software Foundation, with special exception defined in the file
// OCCT_LGPL_EXCEPTION.txt. Consult the file LICENSE_LGPL_21.txt included in OCCT
// distribution for complete text of the license and disclaimer of any warranty.
//
// Alternatively, this file may be used under the terms of Open CASCADE
// commercial license or contractual agreement.
#ifndef _BRepOffset_Inter3d_HeaderFile
#define _BRepOffset_Inter3d_HeaderFile
#include <Message_ProgressRange.hxx>
#include <Standard.hxx>
#include <Standard_DefineAlloc.hxx>
#include <Standard_Handle.hxx>
#include <TopTools_IndexedMapOfShape.hxx>
#include <TopTools_DataMapOfShapeListOfShape.hxx>
#include <TopAbs_State.hxx>
#include <Standard_Real.hxx>
#include <TopTools_ListOfShape.hxx>
#include <BRepOffset_DataMapOfShapeOffset.hxx>
#include <TopTools_DataMapOfShapeShape.hxx>
#include <Standard_Boolean.hxx>
class BRepAlgo_AsDes;
class BRepAlgo_Image;
class TopoDS_Face;
class TopoDS_Shape;
class BRepOffset_Analyse;
//! Computes the connection of the offset and not offset faces
//! according to the connection type required.
//! Store the result in AsDes tool.
class BRepOffset_Inter3d
{
public:
DEFINE_STANDARD_ALLOC
public:
//! Constructor
Standard_EXPORT BRepOffset_Inter3d (const Handle (BRepAlgo_AsDes)& AsDes,
const TopAbs_State Side,
const Standard_Real Tol);
// Computes intersection of the given faces among each other
Standard_EXPORT void CompletInt (const TopTools_ListOfShape& SetOfFaces,
const BRepAlgo_Image& InitOffsetFace,
const Message_ProgressRange& theRange);
//! Computes intersection of pair of faces
Standard_EXPORT void FaceInter (const TopoDS_Face& F1,
const TopoDS_Face& F2,
const BRepAlgo_Image& InitOffsetFace);
//! Computes connections of the offset faces that have to be connected by arcs.
Standard_EXPORT void ConnexIntByArc (const TopTools_ListOfShape& SetOfFaces,
const TopoDS_Shape& ShapeInit,
const BRepOffset_Analyse& Analyse,
const BRepAlgo_Image& InitOffsetFace,
const Message_ProgressRange& theRange);
//! Computes intersection of the offset faces that have to be connected by
//! sharp edges, i.e. it computes intersection between extended offset faces.
Standard_EXPORT void ConnexIntByInt (const TopoDS_Shape& SI,
const BRepOffset_DataMapOfShapeOffset& MapSF,
const BRepOffset_Analyse& A,
TopTools_DataMapOfShapeShape& MES,
TopTools_DataMapOfShapeShape& Build,
TopTools_ListOfShape& Failed,
const Message_ProgressRange& theRange,
const Standard_Boolean bIsPlanar = Standard_False);
//! Computes intersection with not offset faces .
Standard_EXPORT void ContextIntByInt (const TopTools_IndexedMapOfShape& ContextFaces,
const Standard_Boolean ExtentContext,
const BRepOffset_DataMapOfShapeOffset& MapSF,
const BRepOffset_Analyse& A,
TopTools_DataMapOfShapeShape& MES,
TopTools_DataMapOfShapeShape& Build,
TopTools_ListOfShape& Failed,
const Message_ProgressRange& theRange,
const Standard_Boolean bIsPlanar = Standard_False);
//! Computes connections of the not offset faces that have to be connected by arcs
Standard_EXPORT void ContextIntByArc (const TopTools_IndexedMapOfShape& ContextFaces,
const Standard_Boolean ExtentContext,
const BRepOffset_Analyse& Analyse,
const BRepAlgo_Image& InitOffsetFace,
BRepAlgo_Image& InitOffsetEdge,
const Message_ProgressRange& theRange);
//! Marks the pair of faces as already intersected
Standard_EXPORT void SetDone (const TopoDS_Face& F1, const TopoDS_Face& F2);
//! Checks if the pair of faces has already been treated.
Standard_EXPORT Standard_Boolean IsDone (const TopoDS_Face& F1,
const TopoDS_Face& F2) const;
//! Returns touched faces
TopTools_IndexedMapOfShape& TouchedFaces() { return myTouched; };
//! Returns AsDes tool
Handle (BRepAlgo_AsDes) AsDes() const { return myAsDes; }
//! Returns new edges
TopTools_IndexedMapOfShape& NewEdges() { return myNewEdges; }
private:
//! Stores the intersection results into AsDes
Standard_EXPORT void Store (const TopoDS_Face& F1,
const TopoDS_Face& F2,
const TopTools_ListOfShape& LInt1,
const TopTools_ListOfShape& LInt2);
private:
Handle (BRepAlgo_AsDes) myAsDes;
TopTools_IndexedMapOfShape myTouched;
TopTools_DataMapOfShapeListOfShape myDone;
TopTools_IndexedMapOfShape myNewEdges;
TopAbs_State mySide;
Standard_Real myTol;
};
#endif // _BRepOffset_Inter3d_HeaderFile
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r13
push %r14
push %r8
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x1db13, %r8
nop
nop
nop
sub %rbp, %rbp
movups (%r8), %xmm2
vpextrq $0, %xmm2, %r13
inc %r11
lea addresses_WT_ht+0xc8cd, %rsi
xor $17093, %r14
movb $0x61, (%rsi)
and %r13, %r13
lea addresses_WC_ht+0x18c2f, %rsi
lea addresses_A_ht+0xe0fb, %rdi
clflush (%rsi)
nop
nop
nop
nop
and %r11, %r11
mov $120, %rcx
rep movsq
nop
nop
nop
nop
nop
sub $62480, %rdi
lea addresses_A_ht+0xb21b, %rbp
nop
nop
nop
nop
nop
xor $13886, %r14
mov $0x6162636465666768, %rcx
movq %rcx, %xmm6
movups %xmm6, (%rbp)
and %r8, %r8
lea addresses_D_ht+0x1262b, %rbp
nop
nop
nop
nop
nop
xor $1438, %r14
mov (%rbp), %rdi
nop
and $40067, %rbp
lea addresses_A_ht+0x1247b, %r14
add $8055, %r13
mov (%r14), %cx
sub %rdi, %rdi
lea addresses_WT_ht+0xbe7b, %rdi
nop
nop
nop
nop
nop
cmp $20906, %r8
mov $0x6162636465666768, %rbp
movq %rbp, (%rdi)
nop
nop
nop
nop
and %r8, %r8
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r8
pop %r14
pop %r13
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r13
push %r9
push %rbx
push %rdx
push %rsi
// Faulty Load
lea addresses_WT+0x16c7b, %r13
nop
nop
nop
nop
add $25458, %rbx
movb (%r13), %dl
lea oracles, %r9
and $0xff, %rdx
shlq $12, %rdx
mov (%r9,%rdx,1), %rdx
pop %rsi
pop %rdx
pop %rbx
pop %r9
pop %r13
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_WT', 'congruent': 0}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': False, 'size': 1, 'type': 'addresses_WT', 'congruent': 0}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_D_ht', 'congruent': 3}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 1, 'type': 'addresses_WT_ht', 'congruent': 1}, 'OP': 'STOR'}
{'dst': {'same': False, 'congruent': 7, 'type': 'addresses_A_ht'}, 'OP': 'REPM', 'src': {'same': False, 'congruent': 0, 'type': 'addresses_WC_ht'}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 16, 'type': 'addresses_A_ht', 'congruent': 5}, 'OP': 'STOR'}
{'OP': 'LOAD', 'src': {'same': False, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_D_ht', 'congruent': 2}}
{'OP': 'LOAD', 'src': {'same': True, 'NT': False, 'AVXalign': True, 'size': 2, 'type': 'addresses_A_ht', 'congruent': 10}}
{'dst': {'same': False, 'NT': False, 'AVXalign': False, 'size': 8, 'type': 'addresses_WT_ht', 'congruent': 9}, 'OP': 'STOR'}
{'39': 21829}
39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39
*/
|
; A192687: Male-female differences: a(n) = A005378(n) - A005379(n).
; 1,1,1,0,1,0,0,1,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
mov $23,$0
mov $25,2
lpb $25
clr $0,23
mov $0,$23
sub $25,1
add $0,$25
sub $0,1
lpb $0
mul $0,100
mov $3,$0
div $3,6
mov $0,$3
mov $1,4
mov $3,1
lpb $1
div $0,3
div $1,2
add $4,$3
lpe
lpe
mov $1,$4
div $1,3
add $1,1
mov $26,$25
lpb $26
mov $24,$1
sub $26,1
lpe
lpe
lpb $23
mov $23,0
sub $24,$1
lpe
mov $1,$24
|
; A086273: Rectangular array T(n,k) of central polygonal numbers, by antidiagonals.
; Submitted by Christian Krause
; 1,1,3,1,4,7,1,5,10,13,1,6,13,19,21,1,7,16,25,31,31,1,8,19,31,41,46,43,1,9,22,37,51,61,64,57,1,10,25,43,61,76,85,85,73,1,11,28,49,71,91,106,113,109,91,1,12,31,55,81,106,127,141,145,136,111,1,13,34,61,91,121,148
lpb $0
add $1,1
sub $0,$1
lpe
add $0,1
sub $1,$0
bin $0,2
add $1,3
mul $1,$0
mov $0,$1
add $0,1
|
;
; bootRogue game in 512 bytes (boot sector)
;
; by Oscar Toledo G.
; http://nanochess.org/
;
; (c) Copyright 2019 Oscar Toledo G.
;
; Creation date: Sep/19/2019. Generates room boxes.
; Revision date: Sep/20/2019. Connect rooms. Allows to navigate.
;
CPU 8086
ROW_WIDTH: EQU $00A0
BOX_MAX_WIDTH: EQU 23
BOX_MAX_HEIGHT: EQU 6
BOX_WIDTH: EQU 26
BOX_HEIGHT: EQU 8
GR_TOP_LEFT: EQU 0xc9
GR_HORIZ: EQU 0xcd
GR_TOP_RIGHT: EQU 0xbb
GR_VERT: EQU 0xba
GR_BOT_LEFT: EQU 0xc8
GR_BOT_RIGHT: EQU 0xbc
GR_DOOR: EQU 0xce
GR_TUNNEL: EQU 0xb1
GR_FLOOR: EQU 0xfa
GR_HERO: EQU 0x01
%ifdef com_file
org 0x0100
%else
org 0x7c00
%endif
rnd: equ 0x0fa0
level: equ 0x0fa2
conn: equ 0x0fa4
start:
mov ax,0x0002
int 0x10
mov ax,0xb800
mov ds,ax
mov es,ax
in al,0x40 ; Read timer counter
mov [rnd],al ; Setup pseudorandom number generator
xor al,al
mov [level],al
;
; Start a dungeon
;
mov di,conn
push di
pop si
;
; Cell connection in map: (each cell only connects right/down)
;
; 0 1 2
;
; 3 4 5
;
; 6 7 8
;
call random2 ; Top left corner connections
stosb ; Cell 0, random right/down connection
call random2 ; Top right corner connections
mov ah,al
and ah,2 ; Cell 2, random down connection
or al,2 ; Cell 1, always down, random right connection
stosw
call random2 ; Bottom left corner connections
mov bl,al
or al,1 ; Cell 3, always right, random down connection
mov ah,3 ; Cell 4, always right and down connection
stosw
call random2 ; Bottom right corner connections
mov ah,bl
and ah,1 ; Cell 6, random right connection.
mov bl,al
and al,2 ; Cell 5, random down connection.
stosw
mov al,bl ; Cell 7, random right connection.
and al,1
mov ah,0 ; Cell 8, no connections.
stosw
xor di,di
call fill_row
call fill_row
call fill_row
mov si,11*ROW_WIDTH+38*2
game_loop:
push word [si]
mov word [si],0x0e00+GR_HERO
mov ah,0x00
int 0x16
pop word [si]
mov al,ah
cmp al,0x01
jne .1
int 0x20
.1: sub al,0x48
jc .2
cmp al,0x09
jnc .2
mov bx,dirs
cs xlat
cbw
mov bx,ax
shl bx,1
mov al,[si+bx]
cmp al,GR_FLOOR
je .3
cmp al,GR_DOOR
je .3
cmp al,GR_TUNNEL
jne .2
.3:
lea si,[si+bx]
.2:
jmp game_loop
dirs: db -80,0,0,-1,0,1,0,0,80
fill_row:
call fill_column
call fill_column
call fill_column
add di,ROW_WIDTH*7+4
ret
fill_column:
push di
add di,4*ROW_WIDTH+(BOX_WIDTH/2-1)*2
lodsb
shr al,1
mov ax,0x0700+GR_TUNNEL
mov cx,BOX_WIDTH
jnc .3
push di
.2:
rep stosw
pop di
.3:
jz .5
mov cl,BOX_HEIGHT
.4:
stosw
add di,ROW_WIDTH-2
loop .4
.5:
pop di
mov bh,BOX_MAX_WIDTH-2
call random
inc ax
inc ax
mov cl,al
mov bh,BOX_MAX_HEIGHT-2
call random
inc ax
inc ax
mov ch,al
mov al,BOX_MAX_WIDTH
sub al,cl
and al,0xfe
cbw
xchg ax,bx
mov al,BOX_MAX_HEIGHT
sub al,ch
shr al,1
mov ah,ROW_WIDTH
mul ah
add ax,bx
push di
add di,ax
mov dx,GR_TOP_LEFT*256+GR_HORIZ
mov bh,GR_TOP_RIGHT
call fill
.1:
mov dx,GR_VERT*256+GR_FLOOR
mov bh,GR_VERT
call fill
dec ch
jnz .1
mov dx,GR_BOT_LEFT*256+GR_HORIZ
mov bh,GR_BOT_RIGHT
call fill
pop di
add di,26*2
ret
fill: push cx
push di
mov ah,0x06
mov al,dh
call door
mov ch,0
.1: mov al,dl
call door
loop .1
mov al,bh
call door
pop di
pop cx
add di,0x00a0
ret
door:
cmp al,GR_HORIZ
jz .1
cmp al,GR_VERT
jnz .2
.1: cmp byte [di],GR_TUNNEL
jnz .2
mov al,GR_DOOR
.2: stosw
ret
random2:
mov bh,4
.1:
call random
or al,al
jz .1
ret
random:
mov ax,[rnd]
push cx
mov cx,7841
mul cx
add ax,83
mov [rnd],ax
pop cx
; rdtsc ; Would make it dependent on Pentium II
; in al,(0x40) ; Only works for slow requirements.
xor ah,ah
div bh
mov al,ah
ret
|
;------------------------------------------------------------------------------
;
; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; Switch the stack from temporary memory to permenent memory.
;
;------------------------------------------------------------------------------
.586p
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT32
; EFIAPI
; Pei2LoaderSwitchStack (
; VOID
; )
;------------------------------------------------------------------------------
EXTERNDEF C MeasurePoint:PROC
Pei2LoaderSwitchStack PROC C PUBLIC
xor eax, eax
jmp FspSwitchStack
Pei2LoaderSwitchStack ENDP
;------------------------------------------------------------------------------
; UINT32
; EFIAPI
; Loader2PeiSwitchStack (
; VOID
; )
;------------------------------------------------------------------------------
Loader2PeiSwitchStack PROC C PUBLIC
jmp FspSwitchStack
Loader2PeiSwitchStack ENDP
;------------------------------------------------------------------------------
; UINT32
; EFIAPI
; FspSwitchStack (
; VOID
; )
;------------------------------------------------------------------------------
EXTERNDEF C SwapStack:PROC
FspSwitchStack PROC C PUBLIC
; Save current contexts
push eax
pushfd
cli
pushad
sub esp, 8
sidt fword ptr [esp]
; Load new stack
push esp
call SwapStack
mov esp, eax
; Restore previous contexts
lidt fword ptr [esp]
add esp, 8
popad
popfd
add esp, 4
ret
FspSwitchStack ENDP
END
|
;
; Copyright (c) 2014 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing project authors may
; be found in the AUTHORS file in the root of the source tree.
;
%include "third_party/x86inc/x86inc.asm"
%include "vpx_dsp/x86/bitdepth_conversion_sse2.asm"
SECTION .text
%if VPX_ARCH_X86_64
; matrix transpose
%macro TRANSPOSE8X8 10
; stage 1
punpcklwd m%9, m%1, m%2
punpcklwd m%10, m%3, m%4
punpckhwd m%1, m%2
punpckhwd m%3, m%4
punpcklwd m%2, m%5, m%6
punpcklwd m%4, m%7, m%8
punpckhwd m%5, m%6
punpckhwd m%7, m%8
; stage 2
punpckldq m%6, m%9, m%10
punpckldq m%8, m%1, m%3
punpckhdq m%9, m%10
punpckhdq m%1, m%3
punpckldq m%10, m%2, m%4
punpckldq m%3, m%5, m%7
punpckhdq m%2, m%4
punpckhdq m%5, m%7
; stage 3
punpckhqdq m%4, m%9, m%2 ; out3
punpcklqdq m%9, m%2 ; out2
punpcklqdq m%7, m%1, m%5 ; out6
punpckhqdq m%1, m%5 ; out7
punpckhqdq m%2, m%6, m%10 ; out1
punpcklqdq m%6, m%10 ; out0
punpcklqdq m%5, m%8, m%3 ; out4
punpckhqdq m%8, m%3 ; out5
SWAP %6, %1
SWAP %3, %9
SWAP %8, %6
%endmacro
%macro HMD8_1D 0
psubw m8, m0, m1
psubw m9, m2, m3
paddw m0, m1
paddw m2, m3
SWAP 1, 8
SWAP 3, 9
psubw m8, m4, m5
psubw m9, m6, m7
paddw m4, m5
paddw m6, m7
SWAP 5, 8
SWAP 7, 9
psubw m8, m0, m2
psubw m9, m1, m3
paddw m0, m2
paddw m1, m3
SWAP 2, 8
SWAP 3, 9
psubw m8, m4, m6
psubw m9, m5, m7
paddw m4, m6
paddw m5, m7
SWAP 6, 8
SWAP 7, 9
psubw m8, m0, m4
psubw m9, m1, m5
paddw m0, m4
paddw m1, m5
SWAP 4, 8
SWAP 5, 9
psubw m8, m2, m6
psubw m9, m3, m7
paddw m2, m6
paddw m3, m7
SWAP 6, 8
SWAP 7, 9
%endmacro
INIT_XMM ssse3
cglobal hadamard_8x8, 3, 5, 11, input, stride, output
lea r3, [2 * strideq]
lea r4, [4 * strideq]
mova m0, [inputq]
mova m1, [inputq + r3]
lea inputq, [inputq + r4]
mova m2, [inputq]
mova m3, [inputq + r3]
lea inputq, [inputq + r4]
mova m4, [inputq]
mova m5, [inputq + r3]
lea inputq, [inputq + r4]
mova m6, [inputq]
mova m7, [inputq + r3]
HMD8_1D
TRANSPOSE8X8 0, 1, 2, 3, 4, 5, 6, 7, 9, 10
HMD8_1D
STORE_TRAN_LOW 0, outputq, 0, 8, 9
STORE_TRAN_LOW 1, outputq, 8, 8, 9
STORE_TRAN_LOW 2, outputq, 16, 8, 9
STORE_TRAN_LOW 3, outputq, 24, 8, 9
STORE_TRAN_LOW 4, outputq, 32, 8, 9
STORE_TRAN_LOW 5, outputq, 40, 8, 9
STORE_TRAN_LOW 6, outputq, 48, 8, 9
STORE_TRAN_LOW 7, outputq, 56, 8, 9
RET
%endif
|
; A177073: (9*n+4)*(9*n+5).
; 20,182,506,992,1640,2450,3422,4556,5852,7310,8930,10712,12656,14762,17030,19460,22052,24806,27722,30800,34040,37442,41006,44732,48620,52670,56882,61256,65792,70490,75350,80372,85556,90902,96410,102080,107912,113906,120062,126380,132860,139502,146306,153272,160400,167690,175142,182756,190532,198470,206570,214832,223256,231842,240590,249500,258572,267806,277202,286760,296480,306362,316406,326612,336980,347510,358202,369056,380072,391250,402590,414092,425756,437582,449570,461720,474032,486506,499142,511940,524900,538022,551306,564752,578360,592130,606062,620156,634412,648830,663410,678152,693056,708122,723350,738740,754292,770006,785882,801920,818120,834482,851006,867692,884540,901550,918722,936056,953552,971210,989030,1007012,1025156,1043462,1061930,1080560,1099352,1118306,1137422,1156700,1176140,1195742,1215506,1235432,1255520,1275770,1296182,1316756,1337492,1358390,1379450,1400672,1422056,1443602,1465310,1487180,1509212,1531406,1553762,1576280,1598960,1621802,1644806,1667972,1691300,1714790,1738442,1762256,1786232,1810370,1834670,1859132,1883756,1908542,1933490,1958600,1983872,2009306,2034902,2060660,2086580,2112662,2138906,2165312,2191880,2218610,2245502,2272556,2299772,2327150,2354690,2382392,2410256,2438282,2466470,2494820,2523332,2552006,2580842,2609840,2639000,2668322,2697806,2727452,2757260,2787230,2817362,2847656,2878112,2908730,2939510,2970452,3001556,3032822,3064250,3095840,3127592,3159506,3191582,3223820,3256220,3288782,3321506,3354392,3387440,3420650,3454022,3487556,3521252,3555110,3589130,3623312,3657656,3692162,3726830,3761660,3796652,3831806,3867122,3902600,3938240,3974042,4010006,4046132,4082420,4118870,4155482,4192256,4229192,4266290,4303550,4340972,4378556,4416302,4454210,4492280,4530512,4568906,4607462,4646180,4685060,4724102,4763306,4802672,4842200,4881890,4921742,4961756,5001932,5042270
sub $1,$0
bin $1,2
mul $1,162
add $1,20
|
.global s_prepare_buffers
s_prepare_buffers:
push %r12
push %r13
push %r9
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_D_ht+0x1980b, %rsi
lea addresses_D_ht+0x5263, %rdi
sub $23672, %rbx
mov $48, %rcx
rep movsw
xor $43180, %r9
lea addresses_WT_ht+0xca63, %r12
nop
nop
sub $25826, %r13
vmovups (%r12), %ymm3
vextracti128 $1, %ymm3, %xmm3
vpextrq $0, %xmm3, %rcx
nop
sub $62569, %r9
lea addresses_WC_ht+0x1d063, %rdi
nop
nop
nop
xor $5582, %rsi
mov $0x6162636465666768, %r12
movq %r12, %xmm7
movups %xmm7, (%rdi)
nop
nop
nop
nop
nop
xor $4117, %r13
lea addresses_UC_ht+0x1e443, %rsi
nop
dec %r12
movl $0x61626364, (%rsi)
nop
and $47166, %r13
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %r9
pop %r13
pop %r12
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r13
push %r15
push %r9
push %rbp
push %rbx
push %rcx
// Store
mov $0x463, %rbx
nop
nop
nop
nop
nop
dec %rcx
movb $0x51, (%rbx)
nop
nop
dec %r11
// Store
mov $0x812, %r13
nop
nop
nop
nop
nop
xor $58219, %rbp
mov $0x5152535455565758, %r11
movq %r11, (%r13)
nop
nop
nop
and $22297, %r9
// Store
mov $0x273, %rbx
nop
nop
nop
nop
dec %rcx
mov $0x5152535455565758, %r11
movq %r11, (%rbx)
nop
xor $5762, %r15
// Faulty Load
lea addresses_normal+0x14263, %r15
clflush (%r15)
nop
nop
xor $3704, %rbp
movntdqa (%r15), %xmm0
vpextrq $0, %xmm0, %r13
lea oracles, %rbx
and $0xff, %r13
shlq $12, %r13
mov (%rbx,%r13,1), %r13
pop %rcx
pop %rbx
pop %rbp
pop %r9
pop %r15
pop %r13
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 0, 'same': False, 'type': 'addresses_normal'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 9, 'same': False, 'type': 'addresses_P'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 0, 'same': False, 'type': 'addresses_P'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 2, 'same': False, 'type': 'addresses_P'}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'NT': True, 'AVXalign': False, 'size': 16, 'congruent': 0, 'same': True, 'type': 'addresses_normal'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'congruent': 3, 'same': False, 'type': 'addresses_D_ht'}, 'dst': {'congruent': 11, 'same': False, 'type': 'addresses_D_ht'}, 'OP': 'REPM'}
{'src': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 11, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 9, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 5, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'STOR'}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
page ,132
;----------------------------Module-Header------------------------------;
; Module Name: FLAT.ASM
;
; init/term routines for using flat pointers
;
; LocalAlloc should go through here!
;
;-----------------------------------------------------------------------;
.286
?PLM=1
?WIN=0
.xlist
include cmacros.inc
.list
;--------------------------------------------------------------------------;
;--------------------------------------------------------------------------;
sBegin Data
public flatBase
public flatSel
flatSel dw 0
flatBase dd 0
KernelLocalAlloc dd 0
sEnd
ifndef SEGNAME
SEGNAME equ <_TEXT>
endif
createSeg %SEGNAME, CodeSeg, word, public, CODE
sBegin CodeSeg
assumes cs,CodeSeg
assumes ds,Data
assumes es,nothing
externFP GetSelectorBase ; in KERNEL
externFP SetSelectorBase ; in KERNEL
externFP GetSelectorLimit ; in KERNEL
externFP SetSelectorLimit ; in KERNEL
externFP GlobalWire ; in KERNEL
externFP GlobalUnwire ; in KERNEL
externFP GlobalFix ; in KERNEL
externFP GlobalUnfix ; in KERNEL
; externFP KernelLocalAlloc ; in KERNEL
externFP GetProcAddress ; in KERNEL
externFP GetModuleHandle ; in KERNEL
externFP AllocSelector ; in KERNEL
externFP FreeSelector ; in KERNEL
;--------------------------------------------------------------------------;
;
; FlatInit
;
;--------------------------------------------------------------------------;
cProc FlatInit, <FAR, PUBLIC, PASCAL>
cBegin
; cCall GlobalWire, <ds>
cCall GlobalFix, <ds>
cCall AllocSelector,<ds>
mov [flatSel],ax
mov bx,ax
mov ax,0008h ; DPMI Set Limit
mov cx,-1
mov dx,-1
int 31h
; cCall SetSelectorLimit,<ax,-1,-1>
cCall GetSelectorBase, <ds>
mov word ptr flatBase[0],ax
mov word ptr flatBase[2],dx
cEnd
;--------------------------------------------------------------------------;
;
; FlatTerm
;
;--------------------------------------------------------------------------;
cProc FlatTerm, <FAR, PUBLIC, PASCAL>
cBegin
cCall SetSelectorLimit,<[flatSel],0,0>
cCall FreeSelector,<[flatSel]>
; cCall GlobalUnwire, <ds>
cCall GlobalUnfix, <ds>
mov word ptr [flatBase][0],0
mov word ptr [flatBase][2],0
mov [flatSel],0
cEnd
;--------------------------------------------------------------------------;
;
; LocalAlloc
;
;--------------------------------------------------------------------------;
szKernel: db "KERNEL",0
cProc LocalAlloc, <FAR, PUBLIC, PASCAL>
ParmW flags
ParmW bytes
cBegin
mov ax,word ptr [KernelLocalAlloc][0]
or ax,word ptr [KernelLocalAlloc][2]
jnz @f
lea ax,szKernel
cCall GetModuleHandle,<cs,ax>
cCall GetProcAddress,<ax, 0, 5>
mov word ptr [KernelLocalAlloc][0],ax
mov word ptr [KernelLocalAlloc][2],dx
@@: mov ax,word ptr [flatBase][0]
or ax,word ptr [flatBase][2]
pushf
jz @f
cCall FlatTerm
@@: cCall KernelLocalAlloc, <flags, bytes>
popf
jz @f
push ax
cCall FlatInit
pop ax
@@:
cEnd
;--------------------------------------------------------------------------;
;
; MapFlat - convert a 16:16 pointer into a 0:32 pointer
;
; note this function assumes the memory will *not* move
; while being accessed. If this is not true call GlobalFix
; on the memory
;
; INPUT:
; ptr16 16:16 pointer to map flat.
;
; OUTPUT:
; dx:ax flat pointer
;
;--------------------------------------------------------------------------;
assumes ds,Data
assumes es,nothing
cProc MapFlat, <NEAR>
ParmD ptr16
cBegin
mov ds,[flatSel]
push word ptr ptr16[2]
cCall GetSelectorBase
add ax,word ptr ptr16[0]
adc dx,0
sub ax,word ptr flatBase[0]
sbb dx,word ptr flatBase[2]
cEnd
sEnd
end
|
; A096446: Number of reduced primitive positive definite binary quadratic forms of determinant n.
; 1,1,2,1,2,2,2,3,2,2,4,2
mov $2,$0
lpb $0
mov $0,$2
div $0,2
add $1,1
bin $2,2
add $3,1
div $0,$3
lpb $1,2
sub $0,$3
add $1,$0
dif $1,6
div $2,2
mov $3,$2
lpe
mul $3,2
add $4,1
lpe
mov $0,$4
add $0,1
|
; A033383: a(n) = floor(63/n).
; 63,31,21,15,12,10,9,7,7,6,5,5,4,4,4,3,3,3,3,3,3,2,2,2,2,2,2,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
add $0,1
mov $1,63
div $1,$0
mov $0,$1
|
.global s_prepare_buffers
s_prepare_buffers:
push %r11
push %r15
push %rbp
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
lea addresses_D_ht+0x18fe2, %rsi
lea addresses_A_ht+0x3a62, %rdi
nop
cmp $58117, %r11
mov $116, %rcx
rep movsq
nop
nop
nop
nop
and %rbp, %rbp
lea addresses_normal_ht+0x14932, %rdx
nop
sub %rdi, %rdi
mov (%rdx), %si
nop
and $27029, %rcx
lea addresses_WC_ht+0xfde8, %rsi
lea addresses_UC_ht+0x9862, %rdi
inc %rbx
mov $78, %rcx
rep movsb
nop
nop
nop
nop
dec %rdx
lea addresses_UC_ht+0xb362, %rsi
lea addresses_A_ht+0x3862, %rdi
nop
nop
nop
add $51022, %rbp
mov $29, %rcx
rep movsl
nop
nop
cmp $50586, %rbx
lea addresses_D_ht+0x1d122, %rsi
lea addresses_UC_ht+0xc562, %rdi
nop
nop
nop
nop
nop
and %r15, %r15
mov $23, %rcx
rep movsw
nop
nop
nop
nop
xor $8037, %rdi
lea addresses_WC_ht+0x1a9be, %rsi
lea addresses_UC_ht+0x12462, %rdi
inc %rbx
mov $43, %rcx
rep movsw
nop
nop
sub %rbp, %rbp
lea addresses_WT_ht+0x158e2, %rsi
nop
cmp %rdx, %rdx
mov (%rsi), %r11d
nop
nop
nop
nop
sub $43061, %rbx
lea addresses_A_ht+0x44c2, %rsi
lea addresses_UC_ht+0xb5e2, %rdi
nop
nop
dec %rbx
mov $36, %rcx
rep movsw
nop
nop
mfence
lea addresses_normal_ht+0x1593a, %rdi
nop
nop
nop
add $45744, %rbp
movb (%rdi), %bl
nop
xor $21682, %rdi
lea addresses_D_ht+0x157e2, %rsi
nop
nop
and %r11, %r11
mov $0x6162636465666768, %rcx
movq %rcx, (%rsi)
nop
inc %rcx
lea addresses_D_ht+0x7a12, %r11
nop
nop
nop
lfence
mov (%r11), %cx
nop
nop
nop
nop
nop
inc %rdi
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r15
pop %r11
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r11
push %r12
push %r14
push %rax
push %rbx
push %rcx
// Store
lea addresses_D+0x1d1e2, %rcx
nop
nop
nop
nop
nop
add $33096, %r10
movb $0x51, (%rcx)
nop
sub $48353, %r14
// Load
lea addresses_UC+0x17aa6, %r11
nop
nop
nop
cmp $51968, %r12
vmovups (%r11), %ymm4
vextracti128 $1, %ymm4, %xmm4
vpextrq $0, %xmm4, %r14
nop
nop
and %r10, %r10
// Store
mov $0xb14, %rax
nop
nop
nop
and $27264, %rcx
movb $0x51, (%rax)
nop
sub %rax, %rax
// Faulty Load
mov $0x3ddd6800000009e2, %rcx
clflush (%rcx)
nop
nop
nop
cmp $5271, %r11
movb (%rcx), %r10b
lea oracles, %rbx
and $0xff, %r10
shlq $12, %r10
mov (%rbx,%r10,1), %r10
pop %rcx
pop %rbx
pop %rax
pop %r14
pop %r12
pop %r11
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_NC', 'size': 4, 'AVXalign': True, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 11, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_UC', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_P', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_NC', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 9, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 6, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 2, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 0, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 6, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_UC_ht', 'congruent': 7, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 7, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_D_ht', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 7, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 7, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WT_ht', 'size': 4, 'AVXalign': False, 'NT': False, 'congruent': 7, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_A_ht', 'congruent': 5, 'same': False}, 'dst': {'type': 'addresses_UC_ht', 'congruent': 8, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 3, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_D_ht', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 9, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 3, 'same': False}}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
//===----------------------------------------------------------------------===//
//
// BusTub
//
// buffer_pool_manager_test.cpp
//
// Identification: test/buffer/buffer_pool_manager_test.cpp
//
// Copyright (c) 2015-2019, Carnegie Mellon University Database Group
//
//===----------------------------------------------------------------------===//
#include "buffer/buffer_pool_manager.h"
#include <cstdio>
#include <random>
#include <string>
#include "gtest/gtest.h"
namespace bustub {
// NOLINTNEXTLINE
// Check whether pages containing terminal characters can be recovered
TEST(BufferPoolManagerTest, BinaryDataTest) {
const std::string db_name = "test.db";
const size_t buffer_pool_size = 10;
std::random_device r;
std::default_random_engine rng(r());
std::uniform_int_distribution<char> uniform_dist(0);
auto *disk_manager = new DiskManager(db_name);
auto *bpm = new BufferPoolManager(buffer_pool_size, disk_manager);
page_id_t page_id_temp;
auto *page0 = bpm->NewPage(&page_id_temp);
// Scenario: The buffer pool is empty. We should be able to create a new page.
ASSERT_NE(nullptr, page0);
EXPECT_EQ(0, page_id_temp);
char random_binary_data[PAGE_SIZE];
// Generate random binary data
for (char &i : random_binary_data) {
i = uniform_dist(rng);
}
// Insert terminal characters both in the middle and at end
random_binary_data[PAGE_SIZE / 2] = '\0';
random_binary_data[PAGE_SIZE - 1] = '\0';
// Scenario: Once we have a page, we should be able to read and write content.
std::memcpy(page0->GetData(), random_binary_data, PAGE_SIZE);
EXPECT_EQ(0, std::memcmp(page0->GetData(), random_binary_data, PAGE_SIZE));
// Scenario: We should be able to create new pages until we fill up the buffer pool.
for (size_t i = 1; i < buffer_pool_size; ++i) {
EXPECT_NE(nullptr, bpm->NewPage(&page_id_temp));
}
// Scenario: Once the buffer pool is full, we should not be able to create any new pages.
for (size_t i = buffer_pool_size; i < buffer_pool_size * 2; ++i) {
EXPECT_EQ(nullptr, bpm->NewPage(&page_id_temp));
}
// Scenario: After unpinning pages {0, 1, 2, 3, 4} and pinning another 4 new pages,
// there would still be one cache frame left for reading page 0.
for (int i = 0; i < 5; ++i) {
EXPECT_EQ(true, bpm->UnpinPage(i, true));
bpm->FlushPage(i);
}
for (int i = 0; i < 5; ++i) {
EXPECT_NE(nullptr, bpm->NewPage(&page_id_temp));
bpm->UnpinPage(page_id_temp, false);
}
// Scenario: We should be able to fetch the data we wrote a while ago.
page0 = bpm->FetchPage(0);
EXPECT_EQ(0, memcmp(page0->GetData(), random_binary_data, PAGE_SIZE));
EXPECT_EQ(true, bpm->UnpinPage(0, true));
// Shutdown the disk manager and remove the temporary file we created.
disk_manager->ShutDown();
remove("test.db");
remove("test.log");
delete bpm;
delete disk_manager;
}
// NOLINTNEXTLINE
TEST(BufferPoolManagerTest, SampleTest) {
const std::string db_name = "test.db";
const size_t buffer_pool_size = 10;
auto *disk_manager = new DiskManager(db_name);
auto *bpm = new BufferPoolManager(buffer_pool_size, disk_manager);
page_id_t page_id_temp;
auto *page0 = bpm->NewPage(&page_id_temp);
// Scenario: The buffer pool is empty. We should be able to create a new page.
ASSERT_NE(nullptr, page0);
EXPECT_EQ(0, page_id_temp);
// Scenario: Once we have a page, we should be able to read and write content.
snprintf(page0->GetData(), PAGE_SIZE, "Hello");
EXPECT_EQ(0, strcmp(page0->GetData(), "Hello"));
// Scenario: We should be able to create new pages until we fill up the buffer pool.
for (size_t i = 1; i < buffer_pool_size; ++i) {
EXPECT_NE(nullptr, bpm->NewPage(&page_id_temp));
}
// Scenario: Once the buffer pool is full, we should not be able to create any new pages.
for (size_t i = buffer_pool_size; i < buffer_pool_size * 2; ++i) {
EXPECT_EQ(nullptr, bpm->NewPage(&page_id_temp));
}
// Scenario: After unpinning pages {0, 1, 2, 3, 4} and pinning another 4 new pages,
// there would still be one buffer page left for reading page 0.
for (int i = 0; i < 5; ++i) {
EXPECT_EQ(true, bpm->UnpinPage(i, true));
}
for (int i = 0; i < 4; ++i) {
EXPECT_NE(nullptr, bpm->NewPage(&page_id_temp));
}
// Scenario: We should be able to fetch the data we wrote a while ago.
page0 = bpm->FetchPage(0);
EXPECT_EQ(0, strcmp(page0->GetData(), "Hello"));
// Scenario: If we unpin page 0 and then make a new page, all the buffer pages should
// now be pinned. Fetching page 0 should fail.
EXPECT_EQ(true, bpm->UnpinPage(0, true));
EXPECT_NE(nullptr, bpm->NewPage(&page_id_temp));
EXPECT_EQ(nullptr, bpm->FetchPage(0));
// Shutdown the disk manager and remove the temporary file we created.
disk_manager->ShutDown();
remove("test.db");
remove("test.log");
delete bpm;
delete disk_manager;
}
} // namespace bustub
|
; A227161: Number of n X 2 0,1 arrays indicating 2 X 2 subblocks of some larger (n+1) X 3 binary array having a sum of one or less, with rows and columns of the latter in lexicographically nondecreasing order.
; 1,3,8,18,36,66,113,183,283,421,606,848,1158,1548,2031,2621,3333,4183,5188,6366,7736,9318,11133,13203,15551,18201,21178,24508,28218,32336,36891,41913,47433,53483,60096,67306,75148,83658,92873,102831,113571,125133,137558,150888,165166,180436,196743,214133,232653,252351,273276,295478,319008,343918,370261,398091,427463,458433,491058,525396,561506,599448,639283,681073,724881,770771,818808,869058,921588,976466,1033761,1093543,1155883,1220853,1288526,1358976,1432278,1508508,1587743,1670061,1755541
add $0,1
bin $0,2
add $0,6
bin $0,2
div $0,3
sub $0,4
|
COMMENT @-----------------------------------------------------------------------
Copyright (c) GeoWorks 1991 -- All Rights Reserved
PROJECT: PC GEOS
MODULE: Text Library
FILE: uiEdit.asm
ROUTINES:
Name Description
---- -----------
GLB GenEditControlClass Style menu object
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 7/91 Initial version
DESCRIPTION:
This file contains routines to implement GenEditControlClass
$Id: uiEdit.asm,v 1.3 98/05/08 09:48:04 gene Exp $
-------------------------------------------------------------------------------@
;---------------------------------------------------
UserClassStructures segment resource
GenEditControlClass ;declare the class record
UserClassStructures ends
;---------------------------------------------------
if not NO_CONTROLLERS ;++++++++++++++++++++++++++++++++++++++++++++++++++++
ControlCommon segment resource
COMMENT @----------------------------------------------------------------------
MESSAGE: GenEditControlGetInfo --
MSG_GEN_CONTROL_GET_INFO for GenEditControlClass
DESCRIPTION: Return group
PASS:
*ds:si - instance data
es - segment of GenEditControlClass
ax - The message
cx:dx - GenControlBuildInfo structure to fill in
RETURN:
none
DESTROYED:
bx, si, di, ds, es (message handler)
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 10/31/91 Initial version
------------------------------------------------------------------------------@
GenEditControlGetInfo method dynamic GenEditControlClass,
MSG_GEN_CONTROL_GET_INFO
mov si, offset GEC_dupInfo
FALL_THRU CopyDupInfoCommon
GenEditControlGetInfo endm
; Do *NOT* call this routine from another code resource,
; as you will not be happy with the results!
;
CopyDupInfoCommon proc far
mov es, cx
mov di, dx ;es:di = dest
segmov ds, cs
CheckHack <(((size GenControlBuildInfo)/2)*2) eq (size GenControlBuildInfo)>
mov cx, (size GenControlBuildInfo) / 2
rep movsw
ret
CopyDupInfoCommon endp
GEC_dupInfo GenControlBuildInfo <
; GCBI_flags
mask GCBF_ALWAYS_UPDATE or mask GCBF_CUSTOM_ENABLE_DISABLE,
GEC_IniFileKey, ; GCBI_initFileKey
GEC_gcnList, ; GCBI_gcnList
length GEC_gcnList, ; GCBI_gcnCount
GEC_notifyTypeList, ; GCBI_notificationList
length GEC_notifyTypeList, ; GCBI_notificationCount
GECName, ; GCBI_controllerName
handle GenEditControlUI, ; GCBI_dupBlock
GEC_childList, ; GCBI_childList
length GEC_childList, ; GCBI_childCount
GEC_featuresList, ; GCBI_featuresList
length GEC_featuresList, ; GCBI_featuresCount
GEC_DEFAULT_FEATURES, ; GCBI_features
handle GenEditControlToolboxUI, ; GCBI_toolBlock
GEC_toolList, ; GCBI_toolList
length GEC_toolList, ; GCBI_toolCount
GEC_toolFeaturesList, ; GCBI_toolFeaturesList
length GEC_toolFeaturesList, ; GCBI_toolFeaturesCount
GEC_DEFAULT_TOOLBOX_FEATURES> ; GCBI_toolFeatures
if FULL_EXECUTE_IN_PLACE
UIControlInfoXIP segment resource
endif
GEC_IniFileKey char "editControl", 0
GEC_gcnList GCNListType \
<MANUFACTURER_ID_GEOWORKS, GAGCNLT_APP_TARGET_NOTIFY_SELECT_STATE_CHANGE>, \
<MANUFACTURER_ID_GEOWORKS, GAGCNLT_EDIT_CONTROL_NOTIFY_UNDO_STATE_CHANGE>
GEC_notifyTypeList NotificationType \
<MANUFACTURER_ID_GEOWORKS, GWNT_SELECT_STATE_CHANGE>, \
<MANUFACTURER_ID_GEOWORKS, GWNT_UNDO_STATE_CHANGE>
;---
GEC_childList GenControlChildInfo \
<offset FirstEditGroup, mask GECF_UNDO or \
mask GECF_CUT or \
mask GECF_COPY or \
mask GECF_PASTE or \
mask GECF_DELETE, 0>,
<offset SelectAllGroup, mask GECF_SELECT_ALL,
mask GCCF_IS_DIRECTLY_A_FEATURE>,
<offset CharMapGroup, mask GECF_CHAR_MAP,
mask GCCF_IS_DIRECTLY_A_FEATURE>,
<offset ClipArtGroup, mask GECF_CLIP_ART,
mask GCCF_IS_DIRECTLY_A_FEATURE>
; Careful, this table is in the *opposite* order as the record which
; it corresponds to.
GEC_featuresList GenControlFeaturesInfo \
<offset DeleteTrigger, DeleteName>,
<offset SelectAllGroup, SelectAllName>,
<offset PasteTrigger, PasteName>,
<offset CopyTrigger, CopyName>,
<offset CutTrigger, CutName>,
<offset UndoTrigger, UndoName>,
<offset CharMapTrigger, CharMapName>,
<offset ClipArtTrigger, ClipArtName>
;---
GEC_toolList GenControlChildInfo \
<offset UndoToolTrigger, mask GECTF_UNDO,
mask GCCF_IS_DIRECTLY_A_FEATURE>,
<offset CutToolTrigger, mask GECTF_CUT,
mask GCCF_IS_DIRECTLY_A_FEATURE>,
<offset CopyToolTrigger, mask GECTF_COPY,
mask GCCF_IS_DIRECTLY_A_FEATURE>,
<offset PasteToolTrigger, mask GECTF_PASTE,
mask GCCF_IS_DIRECTLY_A_FEATURE>,
<offset SelectAllToolTrigger, mask GECTF_SELECT_ALL,
mask GCCF_IS_DIRECTLY_A_FEATURE>,
<offset DeleteToolTrigger, mask GECTF_DELETE,
mask GCCF_IS_DIRECTLY_A_FEATURE>
; Careful, this table is in the *opposite* order as the record which
; it corresponds to.
GEC_toolFeaturesList GenControlFeaturesInfo \
<offset DeleteToolTrigger, DeleteName>,
<offset SelectAllToolTrigger, SelectAllName>,
<offset PasteToolTrigger, PasteName>,
<offset CopyToolTrigger, CopyName>,
<offset CutToolTrigger, CutName>,
<offset UndoToolTrigger, UndoName>
if FULL_EXECUTE_IN_PLACE
UIControlInfoXIP ends
endif
COMMENT @----------------------------------------------------------------------
MESSAGE: GenEditControlGenerateUI -- MSG_GEN_CONTROL_GENERATE_UI for
GenEditControlClass
DESCRIPTION: Before building our UI, add ourselves to clipboard notification
list so that we'll be able to set the state of that UI
correctly.
PASS:
*ds:si - instance data
es - segment of GenEditControlClass
ax - The message
cx - ?
dx - ?
bp - ?
RETURN:
DESTROYED:
bx, si, di, ds, es (message handler)
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
brianc 7/15/92 Initial version
------------------------------------------------------------------------------@
GenEditControlGenerateUI method dynamic GenEditControlClass,
MSG_GEN_CONTROL_GENERATE_UI,
MSG_GEN_CONTROL_GENERATE_TOOLBOX_UI
push ax, cx, dx, bp
mov ax, TEMP_CLIPBOARD_NOTIFICATION_LIST_COUNT
call ObjVarFindData
jc found
mov cx, size word
call ObjVarAddData
mov {word} ds:[bx], 0
found:
inc {word} ds:[bx]
cmp {word} ds:[bx], 1
jne noAdd
; Add the item to the notification list if the ref count is 1
mov cx, ds:[LMBH_handle]
mov dx, si
call ClipboardAddToNotificationList
;
; if we add ourselves to the clipboard notification list, make sure
; that we are on the active list, as that is the only way that we'll
; get removed from the clipboard notification list.
;
sub sp, size GCNListParams
mov bp, sp
movdw ss:[bp].GCNLP_optr, cxdx
mov ss:[bp].GCNLP_ID.GCNLT_manuf, MANUFACTURER_ID_GEOWORKS
mov ss:[bp].GCNLP_ID.GCNLT_type, MGCNLT_ACTIVE_LIST or \
mask GCNLTF_SAVE_TO_STATE
mov dx, size GCNListParams
mov ax, MSG_META_GCN_LIST_ADD
call GenCallApplication
add sp, size GCNListParams
noAdd:
pop ax, cx, dx, bp
;
; do the superclass thing
;
mov di, offset GenEditControlClass
call ObjCallSuperNoLock
;
; if desired, set up the alternate shortcuts
;
call SetupAlternateShortcuts
ret
GenEditControlGenerateUI endm
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SetupAlternateShortcuts
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: set up the alternate keyboard shortcuts if desired
CALLED BY: GenEditControlGenerateUI()
PASS: *ds:si - GenEditControl object
RETURN: none
DESTROYED: none
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
eca 5/1/98 Initial version.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
objList lptr \
UndoTrigger,
CutTrigger,
CopyTrigger,
PasteTrigger,
SelectAllTrigger
idata segment
;p a c s s c
;h l t h e h
;y t r f t a
;s l t r
mainShortcutList KeyboardShortcut \
<0, 0, 1, 0, 0, C_SMALL_Z>, ;<z> = undo
<0, 0, 1, 0, 0, C_SMALL_X>, ;<x> = cut
<0, 0, 1, 0, 0, C_SMALL_C>, ;<c> = copy
<0, 0, 1, 0, 0, C_SMALL_V>, ;<p> = paste
<0, 0, 1, 0, 0, C_SMALL_A> ;<a> = select all
idata ends
idata segment
altShortcutList KeyboardShortcut \
<1, 1, 0, 0, CS_CONTROL and 0xf, VC_BACKSPACE>, ;<alt><bkspace> = undo
<1, 0, 0, 1, CS_CONTROL and 0xf, VC_DEL>, ;<shift><delete> = cut
<1, 0, 1, 0, CS_CONTROL and 0xf, VC_INS>, ;<ctrl><insert> = copy
<1, 0, 0, 1, CS_CONTROL and 0xf, VC_INS>, ;<shift><insert> =paste
<0, 0, 1, 0, 0, C_SLASH> ;<ctrl>-/ = select all
idata ends
featureList word \
mask GECF_UNDO,
mask GECF_CUT,
mask GECF_COPY,
mask GECF_PASTE,
mask GECF_SELECT_ALL
CheckHack <length mainShortcutList eq length objList>
CheckHack <length altShortcutList eq length objList>
CheckHack <length featureList eq length objList>
uiFeaturesCat char "uiFeatures",0
useAltEditKeys char "altEditKeys",0
SetupAlternateShortcuts proc near
uses ax, bx, cx, dx, si, di, bp, es
.enter
segmov es, dgroup
;
; See if we want the alternates
;
push ds, si
segmov ds, cs, cx
mov si, offset uiFeaturesCat
mov dx, offset useAltEditKeys
call InitFileReadBoolean
pop ds, si
jc noAlt ;branch if not there
tst ax
jz noAlt ;branch if false
;
;
; Loop through the list and change the shortcuts
;
mov ax, TEMP_GEN_CONTROL_INSTANCE
call ObjVarDerefData
mov ax, ds:[bx].TGCI_features ;ax <- features
mov bx, ds:[bx].TGCI_childBlock ;bx <- child block
mov cx, length mainShortcutList ;cx <- # shortcuts
clr di ;di <- table index
childLoop:
test ax, cs:featureList[di] ;feature exists?
jz skipObj ;branch if no feature
push ax, cx, di
mov si, cs:objList[di] ;^bx:si <- OD
mov cx, es:mainShortcutList[di] ;cx <- new shortcut
push es:altShortcutList[di]
mov di, mask MF_FIXUP_DS
mov dl, VUM_DELAYED_VIA_APP_QUEUE
mov ax, MSG_GEN_SET_KBD_ACCELERATOR
call ObjMessage
pop dx
tst dx
jz noExtra
call ObjSwapLock
push bx
mov ax, ATTR_GEN_EXTRA_KBD_ACCELERATORS
mov cx, size KeyboardShortcut
call ObjVarAddData
mov ds:[bx], dx
pop bx
call ObjSwapUnlock
noExtra:
pop ax, cx, di
skipObj:
add di, (size lptr)
loop childLoop
noAlt:
.leave
ret
SetupAlternateShortcuts endp
COMMENT @----------------------------------------------------------------------
MESSAGE: GenEditControlAddAppUI -- MSG_GEN_CONTROL_ADD_APP_UI
for GenEditControlClass
DESCRIPTION: Add application UI
PASS:
*ds:si - instance data
es - segment of GenEditControlClass
ax - The message
cx:dx - object
RETURN:
DESTROYED:
bx, si, di, ds, es (message handler)
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 11/24/92 Initial version
------------------------------------------------------------------------------@
GenEditControlAddAppUI method dynamic GenEditControlClass,
MSG_GEN_CONTROL_ADD_APP_UI
mov bp, 1
mov ax, MSG_GEN_ADD_CHILD
GOTO ObjCallInstanceNoLock
GenEditControlAddAppUI endm
COMMENT @----------------------------------------------------------------------
MESSAGE: GenEditControlNotifyNormalTransferItemChanged --
MSG_META_CLIPBOARD_NOTIFY_NORMAL_TRANSFER_ITEM_CHANGED
for GenEditControlClass
DESCRIPTION: Cause target to update transfer stuff
PASS:
*ds:si - instance data
es - segment of GenEditControlClass
ax - The message
RETURN:
DESTROYED:
bx, si, di, ds, es (message handler)
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 12/10/91 Initial version
------------------------------------------------------------------------------@
GenEditControlNotifyNormalTransferItemChanged method dynamic \
GenEditControlClass,
MSG_META_CLIPBOARD_NOTIFY_NORMAL_TRANSFER_ITEM_CHANGED
mov ax, MSG_META_UI_FORCE_CONTROLLER_UPDATE
mov cx, MANUFACTURER_ID_GEOWORKS
mov dx, GWNT_SELECT_STATE_CHANGE
GOTO OutputNoClass
GenEditControlNotifyNormalTransferItemChanged endm
COMMENT @----------------------------------------------------------------------
MESSAGE: GenEditControlUpdateUI -- MSG_GEN_CONTROL_UPDATE_UI
for GenEditControlClass
DESCRIPTION: Handle notification of attributes change
PASS:
*ds:si - instance data
es - segment of GenEditControlClass
ax - The message
ss:bp - GenControlUpdateUIParams
RETURN:
DESTROYED:
bx, si, di, ds, es (message handler)
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 11/12/91 Initial version
------------------------------------------------------------------------------@
GenEditControlUpdateUI method dynamic GenEditControlClass,
MSG_GEN_CONTROL_UPDATE_UI
; get notification data
mov bx, ss:[bp].GCUUIP_dataBlock
tst bx
jnz lockDataBlock
segmov es, cs
mov bx, offset nullNotification
jmp noLock
lockDataBlock:
call MemLock
mov es, ax
clr bx
noLock:
cmp ss:[bp].GCUUIP_changeType, GWNT_UNDO_STATE_CHANGE
jz doUndoChange
; update the copy trigger
EC < cmp es:[bx].NSSC_selectionType, SelectionDataType >
EC < ERROR_AE BAD_SELECTION_TYPE >
mov ax, mask GECF_COPY
mov dx, mask GECTF_COPY
mov cl, es:[bx].NSSC_clipboardableSelection
mov ch, VUM_NOW
mov si, offset CopyTrigger
mov di, offset CopyToolTrigger
call GEC_EnableOrDisable
; update the cut trigger
mov ax, mask GECF_CUT
mov dx, mask GECTF_CUT
and cl, es:[bx].NSSC_deleteableSelection
mov si, offset CutTrigger
mov di, offset CutToolTrigger
call GEC_EnableOrDisable
; update the paste trigger
mov ax, mask GECF_PASTE
mov dx, mask GECTF_PASTE
mov cl, es:[bx].NSSC_pasteable
mov si, offset PasteTrigger
mov di, offset PasteToolTrigger
call GEC_EnableOrDisable
; update the delete trigger
mov ax, mask GECF_DELETE
mov dx, mask GECTF_DELETE
mov cl, es:[bx].NSSC_deleteableSelection
mov si, offset DeleteTrigger
mov di, offset DeleteToolTrigger
call GEC_EnableOrDisable
; update the select all trigger
mov ax, mask GECF_SELECT_ALL
mov dx, mask GECTF_SELECT_ALL
mov cl, es:[bx].NSSC_selectAllAvailable
mov si, offset SelectAllTrigger
mov di, offset SelectAllToolTrigger
call GEC_EnableOrDisable
exit:
mov bx, ss:[bp].GCUUIP_dataBlock
tst bx
jz noUnlock
call MemUnlock
noUnlock:
ret
doUndoChange:
; update the undo trigger
push si
mov ax, mask GECF_UNDO
mov dx, mask GECTF_UNDO
mov cx, es:[bx].NUSC_undoTitle.handle
or cl, ch
mov ch, VUM_DELAYED_VIA_UI_QUEUE
mov si, offset UndoTrigger
mov di, offset UndoToolTrigger
call GEC_EnableOrDisable
pop si
; update the moniker for the undo trigger (if needed)
test ss:[bp].GCUUIP_features, mask GECF_UNDO
jz exit
mov di, bx ;ES:DI <- NotifyUndoStateChange
mov ax, TEMP_UNDO_DESCRIPTION ;If there was already a
call ObjVarFindData ; description, branch.
jc descFound
; set undo trigger to passed string
mov ax, TEMP_UNDO_DESCRIPTION
mov cx, size NotifyUndoStateChange
call ObjVarAddData ;ds:bx = data
setDesc:
movdw ds:[bx].NUSC_undoTitle, es:[di].NUSC_undoTitle, ax
mov al, es:[di].NUSC_undoType
mov ds:[bx].NUSC_undoType, al
; set the moniker
mov bx, ss:[bp].GCUUIP_childBlock
mov si, offset UndoTrigger
call GEC_SetUndoMoniker
jmp exit
; found previous string -- compare them
descFound:
; If this is now a redo, branch
mov al, es:[di].NUSC_undoType
cmp al, ds:[bx].NUSC_undoType
jnz setDesc
cmpdw es:[di].NUSC_undoTitle, ds:[bx].NUSC_undoTitle, ax
jz exit
tst es:[di].NUSC_undoTitle.handle ;New moniker is null, but old
jz setDesc ; is non-null, branch.
tst ds:[bx].NUSC_undoTitle.handle
;If old moniker is null, but new is
jz setDesc ; non-null, branch to set the
; moniker
; We have two non-null undo monikers - compare them.
call CompareUndoStrings ;If setting it to the same string,
jnz setDesc ; branch to exit.
jmp exit
GenEditControlUpdateUI endm
nullNotification NotifySelectStateChange <0,0,0,0,0>
.assert size NotifyUndoStateChange le size NotifySelectStateChange
;---
; ax = bit to test to normal
; dx = bit to test for tool
; cl = non-zero to enable, 0 to disable
; ch = VisUpdateMode
; si = offset for normal obj
; di = offset for tool obj
; ss:bp = GenControlUpdateUIParams
GEC_EnableOrDisable proc near uses bx, cx
.enter
test ax, ss:[bp].GCUUIP_features
jz noNormal
mov bx, ss:[bp].GCUUIP_childBlock
call GEC_EnableOrDisableLow
noNormal:
test dx, ss:[bp].GCUUIP_toolboxFeatures
jz noToolBox
mov bx, ss:[bp].GCUUIP_toolBlock
mov si, di
call GEC_EnableOrDisableLow
noToolBox:
.leave
ret
GEC_EnableOrDisable endp
;---
;bx:si - obj
;cl - state
;ch - VisUpdateMode
GEC_EnableOrDisableLow proc near uses dx, di
.enter
mov ax, MSG_GEN_SET_ENABLED
mov dl, ch
tst cl
jnz pasteCommon
mov ax, MSG_GEN_SET_NOT_ENABLED
pasteCommon:
mov di, mask MF_FIXUP_DS
call ObjMessage
.leave
ret
GEC_EnableOrDisableLow endp
;---
OutputNoClass proc far
clr bx ;any class -- this is a meta message
clr di
call GenControlOutputActionRegs
ret
OutputNoClass endp
ControlCommon ends
;---
ControlCode segment resource
COMMENT @----------------------------------------------------------------------
MESSAGE: GenEditControlDestroyUI -- MSG_GEN_CONTROL_DESTROY_UI for
GenEditControlClass
DESCRIPTION: Remove ourselves from clipboard notification list
PASS:
*ds:si - instance data
es - segment of GenEditControlClass
ax - The message
RETURN:
DESTROYED:
bx, si, di, ds, es (message handler)
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
brianc 7/15/92 Initial version
------------------------------------------------------------------------------@
GenEditControlDestroyUI method dynamic GenEditControlClass,
MSG_GEN_CONTROL_DESTROY_UI,
MSG_GEN_CONTROL_DESTROY_TOOLBOX_UI,
MSG_META_DETACH
push ax
mov di, offset GenEditControlClass
call ObjCallSuperNoLock
pop ax
cmp ax, MSG_META_DETACH
jz forceRemove
; Only remove the object from the notification list when the ref count
; is zero
mov ax, TEMP_CLIPBOARD_NOTIFICATION_LIST_COUNT
call ObjVarFindData
EC < ERROR_NC GEN_CONTROL_INTERNAL_ERROR >
dec {word} ds:[bx]
EC < ERROR_S GEN_CONTROL_INTERNAL_ERROR >
jnz noRemove
forceRemove:
mov cx, ds:[LMBH_handle]
mov dx, si
call ClipboardRemoveFromNotificationList
noRemove:
ret
GenEditControlDestroyUI endm
COMMENT @----------------------------------------------------------------------
MESSAGE: GenEditControlClipboardUndo -- MSG_UNDO for GenEditControlClass
DESCRIPTION: Handle "undo" (and others)
PASS:
*ds:si - instance data
es - segment of GenEditControlClass
ax - The message
RETURN:
DESTROYED:
bx, si, di, ds, es (message handler)
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 10/31/91 Initial version
------------------------------------------------------------------------------@
GenEditControlClipboardUndo method GenEditControlClass,
MSG_META_UNDO
mov ax, MSG_GEN_PROCESS_UNDO_PLAYBACK_CHAIN
call GeodeGetProcessHandle
mov di, mask MF_FIXUP_DS
GOTO ObjMessage
GenEditControlClipboardUndo endm
;---
GenEditControlClipboardCut method GenEditControlClass,
MSG_META_CLIPBOARD_CUT,
MSG_META_CLIPBOARD_COPY,
MSG_META_CLIPBOARD_PASTE
EC < mov cx, 0xcccc >
EC < mov dx, 0xcccc >
EC < mov bp, 0xcccc >
push ax
mov ax, MSG_GEN_APPLICATION_MARK_BUSY
call GenCallApplication
pop ax
call OutputNoClass
push si
mov ax, MSG_GEN_APPLICATION_MARK_NOT_BUSY
clr bx
call GeodeGetAppObject
mov di, mask MF_RECORD
call ObjMessage
mov cx, di
pop si
clr dx
mov ax, MSG_META_DISPATCH_EVENT
call OutputNoClass
ret
GenEditControlClipboardCut endm
;---
GenEditControlClipboardSelectAll method GenEditControlClass,
MSG_META_SELECT_ALL,
MSG_META_DELETE
EC < mov cx, 0xcccc >
EC < mov dx, 0xcccc >
EC < mov bp, 0xcccc >
call OutputNoClass
ret
GenEditControlClipboardSelectAll endm
;---
serverAppToken GeodeToken <"Scrp",MANUFACTURER_ID_GEOWORKS>
GenEditControlClipArt method GenEditControlClass,
MSG_GEC_LAUNCH_CLIP_ART
uses ax,bx,cx,dx,si,di,bp
.enter
EC < mov cx, 0xcccc >
EC < mov dx, 0xcccc >
EC < mov bp, 0xcccc >
;
; Create a launch block to pass to IACPConnect
;
mov dx, MSG_GEN_PROCESS_OPEN_APPLICATION
call IACPCreateDefaultLaunchBlock ; dx = handle to AppLaunchBlock
;
; Clear launch flags
;
mov bx, dx ; bx <- handle of AppLaunchBlock
call MemLock ; ax = AppLaunchBlock segment
mov es, ax
mov es:[ALB_launchFlags], mask ALF_OVERRIDE_MULTIPLE_INSTANCE
push bx
lea di, es:[ALB_dataFile]
mov {byte}es:[di], 0 ; leave the first byte empty
inc di
mov ax, GGIT_PERM_NAME_AND_EXT
clr bx
call GeodeGetInfo ; es:di = GeodeToken
pop bx
call MemUnlock
;
; Connect to the desired server
;
mov di, offset cs:[serverAppToken]
segmov es, cs, dx ; es:di points to GeodeToken
mov ax, mask IACPCF_FIRST_ONLY ; ax <- connect flag
call IACPConnect ; bp = IACPConnection
jc done
;
; Shut down connection
;
clr cx, dx
call IACPShutdown
done:
.leave
ret
GenEditControlClipArt endm
;---
server2AppToken GeodeToken <"CHRm",16426> ; BREAK_BOX_MANUFACTURE_ID
GenEditControlCharMap method GenEditControlClass,
MSG_GEC_LAUNCH_CHAR_MAP
uses ax,bx,cx,dx,si,di,bp
.enter
EC < mov cx, 0xcccc >
EC < mov dx, 0xcccc >
EC < mov bp, 0xcccc >
;
; Create a launch block to pass to IACPConnect
;
mov dx, MSG_GEN_PROCESS_OPEN_APPLICATION
call IACPCreateDefaultLaunchBlock ; dx = handle to AppLaunchBlock
;
; Clear launch flags
;
mov bx, dx ; bx <- handle of AppLaunchBlock
call MemLock ; ax = AppLaunchBlock segment
mov es, ax
mov es:[ALB_launchFlags], mask ALF_OVERRIDE_MULTIPLE_INSTANCE
push bx
lea di, es:[ALB_dataFile]
mov {byte}es:[di], 0 ; leave the first byte empty
inc di
mov ax, GGIT_PERM_NAME_AND_EXT
clr bx
call GeodeGetInfo ; es:di = GeodeToken
pop bx
call MemUnlock
;
; Connect to the desired server
;
mov di, offset cs:[server2AppToken]
segmov es, cs, dx ; es:di points to GeodeToken
mov ax, mask IACPCF_FIRST_ONLY ; ax <- connect flag
call IACPConnect ; bp = IACPConnection
jc done
;
; Shut down connection
;
clr cx, dx
call IACPShutdown
done:
.leave
ret
GenEditControlCharMap endm
;---
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
CompareUndoStrings
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Compares the passed undo strings
CALLED BY: GLOBAL
PASS: es:di - ptr to optr of one null terminated string
ds:bx - ptr to optr of the other null terminated string
(es:di and ds:bx *cannot* be pointing into the movable XIP code
resource.)
RETURN: zero flag set if match (jz if match)
DESTROYED: ax, cx, dx
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 6/ 4/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
CompareUndoStrings proc far uses es, ds, di, si, bx, bp
destHan local hptr \
push ds:[bx].handle
sourceHan local hptr
.enter
if FULL_EXECUTE_IN_PLACE
;
; Make sure the fptr passed in is valid
;
EC < pushdw bxsi >
EC < mov si, bx >
EC < mov bx, ds >
EC < call ECAssertValidFarPointerXIP >
EC < movdw bxsi, esdi >
EC < call ECAssertValidFarPointerXIP >
EC < popdw bxsi >
endif
mov si, ds:[bx].chunk
mov bx, es:[di].NUSC_undoTitle.handle
mov sourceHan, bx
mov di, es:[di].NUSC_undoTitle.chunk
call MemLock
mov es, ax
mov di, es:[di]
mov bx, destHan
call MemLock
mov ds, ax
mov si, ds:[si]
ChunkSizePtr es, di, cx ;CX <- size of source
; chunk
ChunkSizePtr ds, si, ax ;AX <- size of dest
cmp ax, cx ;If size are not equal,
jnz doUnlock ; exit
repe cmpsb ;Compare the strings
doUnlock:
mov bx, sourceHan
call MemUnlock
mov bx, destHan
call MemUnlock
.leave
ret
CompareUndoStrings endp
;---
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
CopyUndoMonikerString
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: Creates an undo moniker string by prepending a prefix string
to the passed app-supplied string, then appends a suffix.
CALLED BY: GLOBAL
PASS: ^lcx:dx - optr of app-supplied title string
al - undo type
es:di - place to store string
RETURN: es:di - end of string (points at null terminator)
DESTROYED: ax, cx, dx
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
atw 6/ 8/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
CopyUndoMonikerString proc uses bx, si
.enter
push ax
pushdw cxdx
mov si, offset UndoTriggerMonikerPrefix
tst al
jz undoPrefix
mov si, offset RedoTriggerMonikerPrefix
undoPrefix:
call GEC_CopyFromControlStrings
; Copy app-supplied string
popdw bxsi
call GEC_CopyFromChunk
pop ax
mov si, offset UndoTriggerMonikerSuffix
tst al
jz undoSuffix
mov si, offset RedoTriggerMonikerSuffix
undoSuffix:
call GEC_CopyFromControlStrings
SBCS < mov {char} es:[di], 0 >
DBCS < mov {wchar} es:[di], 0 >
.leave
ret
CopyUndoMonikerString endp
; es:[di].NUSC_undoTitle = optr of name
; bx:si = undo trigger
SBCS <MAX_UNDO_MONIKER_LENGTH = 128 >
DBCS <MAX_UNDO_MONIKER_LENGTH = 256 >
GEC_SetUndoMoniker proc far uses bp
.enter
if FULL_EXECUTE_IN_PLACE
;
; Make sure the fptr passed in is valid
;
EC < pushdw bxsi >
EC < movdw bxsi, esdi >
EC < call ECAssertValidFarPointerXIP >
EC < popdw bxsi >
endif
mov_tr ax, di
mov di, 600
call ThreadBorrowStackSpace
push di
mov_tr di, ax
movdw cxdx, es:[di].NUSC_undoTitle
mov al, es:[di].NUSC_undoType
cmp al, UD_NOT_UNDOABLE
jz setCannotUndoMoniker
tst cx ;Can't do jcxz - it's too far.
jz setNullMoniker
sub sp, MAX_UNDO_MONIKER_LENGTH + size VisMoniker + size VisMonikerText
mov di, sp
segmov es, ss ;ES:DI <- dest for
; moniker
mov es:[di].VM_type, DAR_NORMAL shl offset VMT_GS_ASPECT_RATIO or DC_TEXT shl offset VMT_GS_COLOR
clr es:[di].VM_width
clr es:[di].VM_data.VMT_mnemonicOffset
add di, offset VM_data.VMT_text
;
; Create the moniker string for the undo/redo trigger
;
; ^lcx:dx - title string for current undo chain
; al - non-zero if we are doing a redo, else an undo
; ^lbx:si - undo trigger
; ES:DI <- ptr to store the undo moniker string
;
call CopyUndoMonikerString
mov cx, di
inc cx ;+1 for NULL
DBCS < inc cx >
sub cx, sp ;CX <- # bytes
mov di, sp
; Set the vis moniker for the undo trigger
mov dx, size ReplaceVisMonikerFrame
sub sp, dx
mov bp, sp
movdw ss:[bp].RVMF_source, esdi
mov ss:[bp].RVMF_sourceType, VMST_FPTR
mov ss:[bp].RVMF_dataType, VMDT_VIS_MONIKER
mov ss:[bp].RVMF_length, cx
clr ss:[bp].RVMF_width
clr ss:[bp].RVMF_height
mov ss:[bp].RVMF_updateMode, VUM_DELAYED_VIA_UI_QUEUE
mov ax, MSG_GEN_REPLACE_VIS_MONIKER
mov di, mask MF_FIXUP_DS
call ObjMessage
add sp, size ReplaceVisMonikerFrame + MAX_UNDO_MONIKER_LENGTH + size VisMoniker + size VisMonikerText
exit:
mov_tr ax, di
pop di
call ThreadReturnStackSpace
mov_tr di, ax
.leave
ret
setCannotUndoMoniker:
EC < tst cx >
EC < ERROR_NZ NON_ZERO_TITLE_PASSED_WITH_UD_NOT_UNDOABLE >
mov dx, offset CannotUndoMoniker
jmp setMonikerCommon
setNullMoniker:
mov dx, offset NoUndoMoniker
setMonikerCommon:
mov ax, MSG_GEN_REPLACE_VIS_MONIKER_OPTR
mov cx, handle ControlStrings
mov bp, VUM_DELAYED_VIA_UI_QUEUE
mov di, mask MF_FIXUP_DS
call ObjMessage
jmp exit
GEC_SetUndoMoniker endp
;---
; ^lbx:si = source
; ss:di = dest
GEC_CopyFromControlStrings proc near
mov bx, handle ControlStrings
FALL_THRU GEC_CopyFromChunk
GEC_CopyFromControlStrings endp
;-
GEC_CopyFromChunk proc near uses ds, es
.enter
call MemLock
mov ds, ax
mov si, ds:[si] ;ds:si = source
ChunkSizePtr ds, si, cx ;cx = length
DBCS < shr cx, 1 >
dec cx ;Don't copy the null
segmov es, ss ;es:di = dest
SBCS < rep movsb >
DBCS < rep movsw >
call MemUnlock
.leave
ret
GEC_CopyFromChunk endp
ControlCode ends
endif ; NO_CONTROLLERS ++++++++++++++++++++++++++++++++++++
|
// Copyright (c) Microsoft Corporation.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#include <algorithm>
#include <array>
#include <assert.h>
#include <iterator>
#include <numeric>
#include <random>
#include <stdio.h>
#include <type_traits>
#include "adapterator.hpp"
using namespace std;
namespace {
constexpr unsigned int Pop = 1000;
array<int, Pop> source;
array<int, Pop> dest0;
array<int, Pop> dest1;
void clear() {
dest0.fill(0);
dest1.fill(0);
}
template <class SourceCategory, class DestCategory, class URNG>
void test_source_dest_size(URNG& urng, unsigned int n) {
using SI = adapterator<decltype(cbegin(source)), SourceCategory>;
using DI = adapterator<decltype(begin(dest0)), DestCategory>;
clear();
auto const result = static_cast<ptrdiff_t>(min(n, Pop));
auto cpy = urng;
assert(
sample(SI{cbegin(source)}, SI{cend(source)}, DI{begin(dest0)}, n, urng).base() == cbegin(dest0) + result);
// Verify repeatability
assert(sample(SI{cbegin(source)}, SI{cend(source)}, DI{begin(dest1)}, n, cpy).base() == cbegin(dest1) + result);
assert(equal(cbegin(dest0), cbegin(dest0) + result, cbegin(dest1), cbegin(dest1) + result));
if (is_base_of_v<forward_iterator_tag, SourceCategory>) {
// Verify stability
assert(is_sorted(cbegin(dest0), cbegin(dest0) + result));
} else {
// Ensure ordering for set_difference
sort(begin(dest0), begin(dest0) + result);
}
// Verify sample is a subset (i.e., sample - population is the empty set)
assert(set_difference(cbegin(dest0), cbegin(dest0) + result, cbegin(source), cend(source), begin(dest1))
== begin(dest1));
}
constexpr unsigned int div_ceil(unsigned int dividend, unsigned int divisor) {
return (dividend + divisor - 1) / divisor;
}
template <class SourceCategory, class DestCategory, class URNG>
void test_source_dest(URNG& gen) {
for (auto n : {div_ceil(Pop, 100), div_ceil(Pop, 2), Pop, 2 * Pop}) {
test_source_dest_size<SourceCategory, DestCategory>(gen, n);
}
}
template <class SourceCategory, class URNG>
void test_source(URNG& gen) {
test_source_dest<SourceCategory, output_iterator_tag>(gen);
test_source_dest<SourceCategory, input_iterator_tag>(gen);
test_source_dest<SourceCategory, forward_iterator_tag>(gen);
test_source_dest<SourceCategory, bidirectional_iterator_tag>(gen);
test_source_dest<SourceCategory, random_access_iterator_tag>(gen);
}
} // unnamed namespace
int main() {
iota(begin(source), end(source), 0);
const unsigned int seed = random_device{}();
printf("Using seed: %u\n", seed);
mt19937 gen{seed};
test_source_dest<input_iterator_tag, random_access_iterator_tag>(gen);
test_source<forward_iterator_tag>(gen);
test_source<bidirectional_iterator_tag>(gen);
test_source<random_access_iterator_tag>(gen);
}
|
COMMENT @-----------------------------------------------------------------------
Copyright (c) GeoWorks 1988 -- All Rights Reserved
PROJECT: PC GEOS
MODULE: UserInterface/User
FILE: userLibrary.asm
ROUTINES:
Name Description
---- -----------
GLB ??? ???
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 2/89 Initial version
DESCRIPTION:
This file contains routines to implement the User Interface library.
$Id: userLibrary.asm,v 1.1 97/04/07 11:46:02 newdeal Exp $
-------------------------------------------------------------------------------@
Init segment resource
if 0
COMMENT @----------------------------------------------------------------------
FUNCTION: LibraryEntry
DESCRIPTION: Library entry/exit routine for UI library.
CALLED BY: GLOBAL
PASS: ds - core block
di - LibraryCallType - LCT_ATTACH or LCT_DETACH
cx:dx - command line parameters
RETURN:
carry - clear to indicate no error
DESTROYED:
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Doug 3/89 Initial version
------------------------------------------------------------------------------@
LibraryEntry proc far
; cmp di, LCT_ATTACH
; jnz LE_exit
clc
ret
;LE_exit:
; clc
; ret
LibraryEntry endp
endif
Init ends
|
; A104221: a(n) = Fibonacci(n) - (Fibonacci(n) mod 2).
; 0,0,0,2,2,4,8,12,20,34,54,88,144,232,376,610,986,1596,2584,4180,6764,10946,17710,28656,46368,75024,121392,196418,317810,514228,832040,1346268,2178308,3524578,5702886,9227464,14930352,24157816,39088168,63245986,102334154,165580140,267914296,433494436,701408732,1134903170,1836311902,2971215072,4807526976,7778742048,12586269024,20365011074,32951280098,53316291172,86267571272,139583862444,225851433716,365435296162,591286729878,956722026040,1548008755920,2504730781960,4052739537880,6557470319842,10610209857722,17167680177564,27777890035288,44945570212852,72723460248140,117669030460994,190392490709134,308061521170128,498454011879264,806515533049392,1304969544928656,2111485077978050,3416454622906706,5527939700884756,8944394323791464,14472334024676220,23416728348467684,37889062373143906,61305790721611590,99194853094755496,160500643816367088,259695496911122584,420196140727489672,679891637638612258,1100087778366101930,1779979416004714188,2880067194370816120,4660046610375530308,7540113804746346428,12200160415121876738,19740274219868223166,31940434634990099904,51680708854858323072,83621143489848422976,135301852344706746048,218922995834555169026
trn $0,1
seq $0,71 ; a(n) = Fibonacci(n) - 1.
add $0,1
div $0,2
mul $0,2
|
; A098713: a(n) = (2n+1)*2^(2n+1) - 1.
; 1,23,159,895,4607,22527,106495,491519,2228223,9961471,44040191,192937983,838860799,3623878655,15569256447,66571993087,283467841535,1202590842879,5085241278463,21440476741631,90159953477631,378231999954943,1583296743997439,6614661952700415,27584547717644287
mov $1,$0
mul $1,2
add $1,1
mov $2,4
pow $2,$0
mul $1,$2
mul $1,2
sub $1,1
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r11
push %r9
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_UC_ht+0xa0b0, %rsi
lea addresses_A_ht+0xfbae, %rdi
nop
nop
sub %r11, %r11
mov $114, %rcx
rep movsl
nop
nop
nop
nop
nop
xor $24294, %rcx
lea addresses_D_ht+0x1958, %r9
nop
and $44190, %r10
movl $0x61626364, (%r9)
nop
nop
nop
add %rsi, %rsi
lea addresses_UC_ht+0x1428, %r10
cmp $37568, %rsi
movb (%r10), %cl
nop
nop
nop
nop
nop
and $65405, %r10
lea addresses_WC_ht+0x1fb0, %rsi
nop
nop
add %rdi, %rdi
movups (%rsi), %xmm2
vpextrq $0, %xmm2, %r10
nop
nop
nop
nop
add $51134, %r11
lea addresses_WT_ht+0x17e02, %r9
nop
nop
nop
nop
nop
xor $25710, %r11
mov $0x6162636465666768, %rsi
movq %rsi, %xmm0
vmovups %ymm0, (%r9)
nop
nop
nop
nop
nop
xor $15287, %r10
lea addresses_normal_ht+0xc288, %r10
nop
nop
nop
nop
nop
cmp $49872, %r9
movb (%r10), %cl
nop
nop
nop
nop
nop
sub %r10, %r10
lea addresses_WT_ht+0x13057, %rdi
sub $29119, %rcx
vmovups (%rdi), %ymm1
vextracti128 $1, %ymm1, %xmm1
vpextrq $1, %xmm1, %rbp
and $28032, %r10
lea addresses_normal_ht+0x7b90, %rsi
lea addresses_WC_ht+0xd2c0, %rdi
nop
nop
nop
nop
cmp $21126, %r10
mov $65, %rcx
rep movsq
nop
nop
nop
cmp %r10, %r10
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r11
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r12
push %r13
push %r15
push %rax
push %rbx
push %rdi
push %rdx
// Load
mov $0xa80f10000000470, %r13
nop
nop
cmp %rdi, %rdi
mov (%r13), %r15d
nop
nop
nop
nop
nop
cmp $34314, %rbx
// Store
mov $0x61, %rdx
dec %rax
mov $0x5152535455565758, %r13
movq %r13, %xmm4
movntdq %xmm4, (%rdx)
nop
nop
cmp %rdx, %rdx
// Faulty Load
mov $0xa80f10000000470, %r15
nop
nop
nop
nop
nop
cmp $14465, %rdx
mov (%r15), %r12
lea oracles, %rdx
and $0xff, %r12
shlq $12, %r12
mov (%rdx,%r12,1), %r12
pop %rdx
pop %rdi
pop %rbx
pop %rax
pop %r15
pop %r13
pop %r12
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': True, 'AVXalign': False, 'size': 32, 'congruent': 0, 'same': False, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': True, 'size': 4, 'congruent': 0, 'same': True, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
{'dst': {'NT': True, 'AVXalign': False, 'size': 16, 'congruent': 0, 'same': False, 'type': 'addresses_P'}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'NT': False, 'AVXalign': False, 'size': 8, 'congruent': 0, 'same': True, 'type': 'addresses_NC'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'congruent': 6, 'same': False, 'type': 'addresses_UC_ht'}, 'dst': {'congruent': 1, 'same': False, 'type': 'addresses_A_ht'}, 'OP': 'REPM'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 3, 'same': False, 'type': 'addresses_D_ht'}, 'OP': 'STOR'}
{'src': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 3, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 6, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 1, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'STOR'}
{'src': {'NT': False, 'AVXalign': False, 'size': 1, 'congruent': 1, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 0, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'LOAD'}
{'src': {'congruent': 4, 'same': True, 'type': 'addresses_normal_ht'}, 'dst': {'congruent': 1, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'REPM'}
{'00': 21829}
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*/
|
; A026056: a(n) = (d(n)-r(n))/5, where d = A026054 and r is the periodic sequence with fundamental period (3,3,0,0,4).
; 2,5,10,16,23,33,45,60,77,96,119,145,175,208,244,285,330,380,434,492,556,625,700,780,865,957,1055,1160,1271,1388,1513,1645,1785,1932,2086,2249,2420,2600,2788,2984,3190,3405,3630,3864,4107,4361,4625,4900,5185,5480,5787,6105,6435,6776,7128,7493
mov $6,$0
add $6,1
mov $18,$0
lpb $6
mov $0,$18
sub $6,1
sub $0,$6
mov $15,$0
mov $16,0
mov $17,$0
add $17,1
lpb $17
mov $0,$15
sub $17,1
sub $0,$17
mov $11,$0
mov $13,2
lpb $13
mov $0,$11
sub $13,1
add $0,$13
sub $0,1
mov $7,$0
mov $9,2
lpb $9
mov $0,$7
sub $9,1
add $0,$9
sub $0,1
mov $4,$0
mul $0,2
add $4,2
bin $4,3
lpb $0
mul $0,2
mov $3,$0
mov $0,$5
add $4,$3
lpe
add $4,8
mov $2,$4
div $2,5
mov $10,$9
mov $19,$2
lpb $10
mov $8,$19
sub $10,1
lpe
lpe
lpb $7
mov $7,0
sub $8,$19
lpe
mov $14,$13
mov $19,$8
lpb $14
mov $12,$19
sub $14,1
lpe
lpe
lpb $11
mov $11,0
sub $12,$19
lpe
mov $19,$12
add $19,1
add $16,$19
lpe
add $1,$16
lpe
mov $0,$1
|
MVI A,1
CALL Fib
JMP End
Fib: ;A -> HL
CPI 1
JZ RetOne
JC RetOne
DCR A
PUSH PSW
CALL Fib
POP PSW
DCR A
PUSH H
CALL Fib
POP D
DAD D
RET
RetOne:
LXI H,1
RET
End:
HLT
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r13
push %r9
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_normal_ht+0x1cac7, %rsi
nop
nop
nop
nop
nop
xor $16980, %rcx
vmovups (%rsi), %ymm1
vextracti128 $1, %ymm1, %xmm1
vpextrq $1, %xmm1, %r9
nop
nop
nop
nop
sub $5218, %rcx
lea addresses_WT_ht+0x11587, %rbx
cmp $180, %r13
movups (%rbx), %xmm4
vpextrq $0, %xmm4, %r10
nop
nop
nop
cmp $7228, %rbx
lea addresses_WT_ht+0x165c7, %rsi
lea addresses_A_ht+0xfe4, %rdi
nop
add $4206, %r13
mov $71, %rcx
rep movsl
cmp $25229, %rsi
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %r9
pop %r13
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r11
push %r12
push %r14
push %r8
push %r9
push %rcx
push %rdi
push %rsi
// Store
lea addresses_UC+0x10987, %r12
xor $43384, %rdi
movb $0x51, (%r12)
xor %rdi, %rdi
// REPMOV
lea addresses_RW+0x1fd87, %rsi
lea addresses_D+0x4587, %rdi
cmp %r8, %r8
mov $39, %rcx
rep movsq
nop
nop
nop
nop
nop
and %rdi, %rdi
// Faulty Load
lea addresses_UC+0x10987, %rcx
nop
sub %r14, %r14
vmovups (%rcx), %ymm1
vextracti128 $1, %ymm1, %xmm1
vpextrq $0, %xmm1, %r9
lea oracles, %rcx
and $0xff, %r9
shlq $12, %r9
mov (%rcx,%r9,1), %r9
pop %rsi
pop %rdi
pop %rcx
pop %r9
pop %r8
pop %r14
pop %r12
pop %r11
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_UC', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_UC', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
{'OP': 'REPM', 'src': {'type': 'addresses_RW', 'congruent': 10, 'same': False}, 'dst': {'type': 'addresses_D', 'congruent': 10, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_UC', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'LOAD', 'src': {'type': 'addresses_normal_ht', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 4, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_WT_ht', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 8, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_WT_ht', 'congruent': 6, 'same': False}, 'dst': {'type': 'addresses_A_ht', 'congruent': 0, 'same': False}}
{'37': 956}
37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37
*/
|
/* The XML parser processes an XML file into a tree data structure composed of
* pugi::xml_nodes. Each node represents an XML element. For example
* <a> <b/> </a> will generate two pugi::xml_nodes. One called "a" and its
* child "b". Each pugi::xml_node can contain various XML data such as attribute
* information and text content. The XML parser provides several functions to
* help the developer build, and traverse tree (this is also somtime referred to
* as the Document Object Model or DOM).
*
* For convenience it often makes sense to use some wraper functions (provided in
* the pugiutil namespace of libvtrutil) which simplify loading an XML file and
* error handling.
*
* The function pugiutil::load_xml() reads in an xml file.
*
* The function pugiutil::get_single_child() returns a child xml_node for a given parent
* xml_node if there is a child which matches the name provided by the developer.
*
* The function pugiutil::get_attribute() is used to extract attributes from an
* xml_node, returning a pugi::xml_attribute. xml_attribute objects support accessors
* such as as_float(), as_int() to retrieve semantic values. See pugixml documentation
* for more details.
*
* Architecture file checks already implemented (Daniel Chen):
* - Duplicate pb_types, pb_type ports, models, model ports,
* interconnects, interconnect annotations.
* - Port and pin range checking (port with 4 pins can only be
* accessed within [0:3].
* - LUT delay matrix size matches # of LUT inputs
* - Ensures XML tags are ordered.
* - Clocked primitives that have timing annotations must have a clock
* name matching the primitive.
* - Enforced VPR definition of LUT and FF must have one input port (n pins)
* and one output port(1 pin).
* - Checks file extension for blif and architecture xml file, avoid crashes if
* the two files are swapped on command line.
*
*/
#include <string.h>
#include <map>
#include <set>
#include <string>
#include <sstream>
#include <algorithm>
#include "pugixml.hpp"
#include "pugixml_util.hpp"
#include "vtr_assert.h"
#include "vtr_log.h"
#include "vtr_util.h"
#include "vtr_memory.h"
#include "vtr_digest.h"
#include "vtr_token.h"
#include "vtr_bimap.h"
#include "arch_types.h"
#include "arch_util.h"
#include "arch_error.h"
#include "read_xml_arch_file.h"
#include "read_xml_util.h"
#include "parse_switchblocks.h"
using namespace std::string_literals;
using pugiutil::ReqOpt;
struct t_fc_override {
std::string port_name;
std::string seg_name;
e_fc_value_type fc_value_type;
float fc_value;
};
struct t_pin_counts {
int input = 0;
int output = 0;
int clock = 0;
int total() {
return input + output + clock;
}
};
struct t_pin_locs {
private:
// Distribution must be set once for each physical tile type
// and must be equal for each sub tile within a physical tile.
bool distribution_set = false;
public:
enum e_pin_location_distr distribution = E_SPREAD_PIN_DISTR;
/* [0..num_sub_tiles-1][0..width-1][0..height-1][0..3][0..num_tokens-1] */
vtr::NdMatrix<std::vector<std::string>, 4> assignments;
bool is_distribution_set() {
return distribution_set;
}
void set_distribution() {
VTR_ASSERT(distribution_set == false);
distribution_set = true;
}
};
/* This gives access to the architecture file name to
* all architecture-parser functions */
static const char* arch_file_name = nullptr;
/* Function prototypes */
/* Populate data */
static void SetupPinClasses(t_physical_tile_type* PhysicalTileType);
static void LoadPinLoc(pugi::xml_node Locations,
t_physical_tile_type* type,
t_pin_locs* pin_locs,
const pugiutil::loc_data& loc_data);
template<typename T>
static std::pair<int, int> ProcessPinString(pugi::xml_node Locations,
T type,
const char* pin_loc_string,
const pugiutil::loc_data& loc_data);
/* Process XML hierarchy */
static void ProcessTiles(pugi::xml_node Node,
std::vector<t_physical_tile_type>& PhysicalTileTypes,
std::vector<t_logical_block_type>& LogicalBlockTypes,
const t_default_fc_spec& arch_def_fc,
t_arch& arch,
const pugiutil::loc_data& loc_data);
// TODO: Remove block_type_contains_blif_model / pb_type_contains_blif_model
// as part of
// https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193
static void MarkIoTypes(std::vector<t_physical_tile_type>& PhysicalTileTypes);
static void ProcessTileProps(pugi::xml_node Node,
t_physical_tile_type* PhysicalTileType,
const pugiutil::loc_data& loc_data);
static t_pin_counts ProcessSubTilePorts(pugi::xml_node Parent,
t_sub_tile* SubTile,
std::unordered_map<std::string, t_physical_tile_port>& tile_port_names,
const pugiutil::loc_data& loc_data);
static void ProcessTilePort(pugi::xml_node Node,
t_physical_tile_port* port,
const pugiutil::loc_data& loc_data);
static void ProcessTileEquivalentSites(pugi::xml_node Parent,
t_sub_tile* SubTile,
t_physical_tile_type* PhysicalTileType,
std::vector<t_logical_block_type>& LogicalBlockTypes,
const pugiutil::loc_data& loc_data);
static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent,
t_sub_tile* SubTile,
t_physical_tile_type* PhysicalTileType,
t_logical_block_type* LogicalBlockType,
const pugiutil::loc_data& loc_data);
static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent,
t_sub_tile* SubTile,
t_physical_tile_type* PhysicalTileType,
t_logical_block_type* LogicalBlockType,
std::string site_name,
const pugiutil::loc_data& loc_data);
static void ProcessPinLocations(pugi::xml_node Locations,
t_physical_tile_type* PhysicalTileType,
t_sub_tile* SubTile,
t_pin_locs* pin_locs,
const pugiutil::loc_data& loc_data);
static void ProcessSubTiles(pugi::xml_node Node,
t_physical_tile_type* PhysicalTileType,
std::vector<t_logical_block_type>& LogicalBlockTypes,
std::vector<t_segment_inf>& segments,
const t_default_fc_spec& arch_def_fc,
const pugiutil::loc_data& loc_data);
static void ProcessPb_Type(vtr::string_internment* strings,
pugi::xml_node Parent,
t_pb_type* pb_type,
t_mode* mode,
const bool timing_enabled,
const t_arch& arch,
const pugiutil::loc_data& loc_data);
static void ProcessPb_TypePort(pugi::xml_node Parent,
t_port* port,
e_power_estimation_method power_method,
const bool is_root_pb_type,
const pugiutil::loc_data& loc_data);
static void ProcessPinToPinAnnotations(pugi::xml_node parent,
t_pin_to_pin_annotation* annotation,
t_pb_type* parent_pb_type,
const pugiutil::loc_data& loc_data);
static void ProcessInterconnect(vtr::string_internment* strings, pugi::xml_node Parent, t_mode* mode, const pugiutil::loc_data& loc_data);
static void ProcessMode(vtr::string_internment* strings, pugi::xml_node Parent, t_mode* mode, const bool timing_enabled, const t_arch& arch, const pugiutil::loc_data& loc_data);
static t_metadata_dict ProcessMetadata(vtr::string_internment* strings, pugi::xml_node Parent, const pugiutil::loc_data& loc_data);
static void Process_Fc_Values(pugi::xml_node Node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data);
static void Process_Fc(pugi::xml_node Node,
t_physical_tile_type* PhysicalTileType,
t_sub_tile* SubTile,
t_pin_counts pin_counts,
std::vector<t_segment_inf>& segments,
const t_default_fc_spec& arch_def_fc,
const pugiutil::loc_data& loc_data);
static t_fc_override Process_Fc_override(pugi::xml_node node, const pugiutil::loc_data& loc_data);
static void ProcessSwitchblockLocations(pugi::xml_node switchblock_locations,
t_physical_tile_type* type,
const t_arch& arch,
const pugiutil::loc_data& loc_data);
static e_fc_value_type string_to_fc_value_type(const std::string& str, pugi::xml_node node, const pugiutil::loc_data& loc_data);
static void ProcessChanWidthDistr(pugi::xml_node Node,
t_arch* arch,
const pugiutil::loc_data& loc_data);
static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pugiutil::loc_data& loc_data);
static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data);
static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::set<std::string>& port_names, const pugiutil::loc_data& loc_data);
static void ProcessLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data);
static t_grid_def ProcessGridLayout(vtr::string_internment* strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data);
static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data);
static void ProcessComplexBlocks(vtr::string_internment* strings, pugi::xml_node Node, std::vector<t_logical_block_type>& LogicalBlockTypes, t_arch& arch, const bool timing_enabled, const pugiutil::loc_data& loc_data);
static void ProcessSwitches(pugi::xml_node Node,
t_arch_switch_inf** Switches,
int* NumSwitches,
const bool timing_enabled,
const pugiutil::loc_data& loc_data);
static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, const int switch_index, t_arch_switch_inf* Switches, const pugiutil::loc_data& loc_data);
static void ProcessDirects(pugi::xml_node Parent, t_direct_inf** Directs, int* NumDirects, const t_arch_switch_inf* Switches, const int NumSwitches, const pugiutil::loc_data& loc_data);
static void ProcessClockMetalLayers(pugi::xml_node parent,
std::unordered_map<std::string, t_metal_layer>& metal_layers,
pugiutil::loc_data& loc_data);
static void ProcessClockNetworks(pugi::xml_node parent,
std::vector<t_clock_network_arch>& clock_networks,
const t_arch_switch_inf* switches,
const int num_switches,
pugiutil::loc_data& loc_data);
static void ProcessClockSwitchPoints(pugi::xml_node parent,
t_clock_network_arch& clock_network,
const t_arch_switch_inf* switches,
const int num_switches,
pugiutil::loc_data& loc_data);
static void ProcessClockRouting(pugi::xml_node parent,
std::vector<t_clock_connection_arch>& clock_connections,
const t_arch_switch_inf* switches,
const int num_switches,
pugiutil::loc_data& loc_data);
static void ProcessSegments(pugi::xml_node Parent,
std::vector<t_segment_inf>& Segs,
const t_arch_switch_inf* Switches,
const int NumSwitches,
const bool timing_enabled,
const bool switchblocklist_required,
const pugiutil::loc_data& loc_data);
static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiutil::loc_data& loc_data);
static void ProcessCB_SB(pugi::xml_node Node, std::vector<bool>& list, const pugiutil::loc_data& loc_data);
static void ProcessPower(pugi::xml_node parent,
t_power_arch* power_arch,
const pugiutil::loc_data& loc_data);
static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data);
static void ProcessPb_TypePowerEstMethod(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data);
static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const pugiutil::loc_data& loc_data);
bool check_model_combinational_sinks(pugi::xml_node model_tag, const pugiutil::loc_data& loc_data, const t_model* model);
void warn_model_missing_timing(pugi::xml_node model_tag, const pugiutil::loc_data& loc_data, const t_model* model);
bool check_model_clocks(pugi::xml_node model_tag, const pugiutil::loc_data& loc_data, const t_model* model);
bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_arch& arch);
const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* port, enum e_pin_to_pin_delay_annotations annot_type);
const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string in_port, std::string out_port);
std::string inst_port_to_port_name(std::string inst_port);
static bool attribute_to_bool(const pugi::xml_node node,
const pugi::xml_attribute attr,
const pugiutil::loc_data& loc_data);
int find_switch_by_name(const t_arch& arch, std::string switch_name);
e_side string_to_side(std::string side_str);
static void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTileTypes,
std::vector<t_logical_block_type>& LogicalBlockTypes);
static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_tile* sub_tile, t_logical_block_type_ptr logical_block);
static const t_physical_tile_port* get_port_by_name(t_sub_tile* sub_tile, const char* port_name);
static const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* port_name);
static const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin);
static const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin);
template<typename T>
static T* get_type_by_name(const char* type_name, std::vector<T>& types);
/*
*
*
* External Function Implementations
*
*
*/
/* Loads the given architecture file. */
void XmlReadArch(const char* ArchFile,
const bool timing_enabled,
t_arch* arch,
std::vector<t_physical_tile_type>& PhysicalTileTypes,
std::vector<t_logical_block_type>& LogicalBlockTypes) {
pugi::xml_node Next;
ReqOpt POWER_REQD, SWITCHBLOCKLIST_REQD;
if (vtr::check_file_name_extension(ArchFile, ".xml") == false) {
VTR_LOG_WARN(
"Architecture file '%s' may be in incorrect format. "
"Expecting .xml format for architecture files.\n",
ArchFile);
}
//Create a unique identifier for this architecture file based on it's contents
arch->architecture_id = vtr::strdup(vtr::secure_digest_file(ArchFile).c_str());
/* Parse the file */
pugi::xml_document doc;
pugiutil::loc_data loc_data;
t_default_fc_spec arch_def_fc;
try {
loc_data = pugiutil::load_xml(doc, ArchFile);
arch_file_name = ArchFile;
/* Root node should be architecture */
auto architecture = get_single_child(doc, "architecture", loc_data);
/* TODO: do version processing properly with string delimiting on the . */
#if 0
char* Prop = get_attribute(architecture, "version", loc_data, ReqOpt::OPTIONAL).as_string(NULL);
if (Prop != NULL) {
if (atof(Prop) > atof(VPR_VERSION)) {
VTR_LOG_WARN( "This architecture version is for VPR %f while your current VPR version is " VPR_VERSION ", compatability issues may arise\n",
atof(Prop));
}
}
#endif
/* Process models */
Next = get_single_child(architecture, "models", loc_data);
ProcessModels(Next, arch, loc_data);
CreateModelLibrary(arch);
/* Process layout */
Next = get_single_child(architecture, "layout", loc_data);
ProcessLayout(Next, arch, loc_data);
/* Process device */
Next = get_single_child(architecture, "device", loc_data);
ProcessDevice(Next, arch, arch_def_fc, loc_data);
/* Process switches */
Next = get_single_child(architecture, "switchlist", loc_data);
ProcessSwitches(Next, &(arch->Switches), &(arch->num_switches),
timing_enabled, loc_data);
/* Process switchblocks. This depends on switches */
bool switchblocklist_required = (arch->SBType == CUSTOM); //require this section only if custom switchblocks are used
SWITCHBLOCKLIST_REQD = BoolToReqOpt(switchblocklist_required);
/* Process segments. This depends on switches */
Next = get_single_child(architecture, "segmentlist", loc_data);
ProcessSegments(Next, arch->Segments,
arch->Switches, arch->num_switches, timing_enabled, switchblocklist_required, loc_data);
Next = get_single_child(architecture, "switchblocklist", loc_data, SWITCHBLOCKLIST_REQD);
if (Next) {
ProcessSwitchblocks(Next, arch, loc_data);
}
/* Process logical block types */
Next = get_single_child(architecture, "complexblocklist", loc_data);
ProcessComplexBlocks(&arch->strings, Next, LogicalBlockTypes, *arch, timing_enabled, loc_data);
/* Process logical block types */
Next = get_single_child(architecture, "tiles", loc_data);
ProcessTiles(Next, PhysicalTileTypes, LogicalBlockTypes, arch_def_fc, *arch, loc_data);
/* Link Physical Tiles with Logical Blocks */
link_physical_logical_types(PhysicalTileTypes, LogicalBlockTypes);
/* Process directs */
Next = get_single_child(architecture, "directlist", loc_data, ReqOpt::OPTIONAL);
if (Next) {
ProcessDirects(Next, &(arch->Directs), &(arch->num_directs),
arch->Switches, arch->num_switches,
loc_data);
}
/* Process Clock Networks */
Next = get_single_child(architecture, "clocknetworks", loc_data, ReqOpt::OPTIONAL);
if (Next) {
std::vector<std::string> expected_children = {"metal_layers", "clock_network", "clock_routing"};
expect_only_children(Next, expected_children, loc_data);
ProcessClockMetalLayers(Next, arch->clock_arch.clock_metal_layers, loc_data);
ProcessClockNetworks(Next,
arch->clock_arch.clock_networks_arch,
arch->Switches,
arch->num_switches,
loc_data);
ProcessClockRouting(Next,
arch->clock_arch.clock_connections_arch,
arch->Switches,
arch->num_switches,
loc_data);
}
/* Process architecture power information */
/* If arch->power has been initialized, meaning the user has requested power estimation,
* then the power architecture information is required.
*/
if (arch->power) {
POWER_REQD = ReqOpt::REQUIRED;
} else {
POWER_REQD = ReqOpt::OPTIONAL;
}
Next = get_single_child(architecture, "power", loc_data, POWER_REQD);
if (Next) {
if (arch->power) {
ProcessPower(Next, arch->power, loc_data);
} else {
/* This information still needs to be read, even if it is just
* thrown away.
*/
t_power_arch* power_arch_fake = (t_power_arch*)vtr::calloc(1,
sizeof(t_power_arch));
ProcessPower(Next, power_arch_fake, loc_data);
free(power_arch_fake);
}
}
// Process Clocks
Next = get_single_child(architecture, "clocks", loc_data, POWER_REQD);
if (Next) {
if (arch->clocks) {
ProcessClocks(Next, arch->clocks, loc_data);
} else {
/* This information still needs to be read, even if it is just
* thrown away.
*/
t_clock_arch* clocks_fake = (t_clock_arch*)vtr::calloc(1,
sizeof(t_clock_arch));
ProcessClocks(Next, clocks_fake, loc_data);
free(clocks_fake->clock_inf);
free(clocks_fake);
}
}
SyncModelsPbTypes(arch, LogicalBlockTypes);
UpdateAndCheckModels(arch);
MarkIoTypes(PhysicalTileTypes);
} catch (pugiutil::XmlError& e) {
archfpga_throw(ArchFile, e.line(),
"%s", e.what());
}
}
/*
*
*
* File-scope function implementations
*
*
*/
/* Sets up the pin classes for the type. */
static void SetupPinClasses(t_physical_tile_type* PhysicalTileType) {
int i, k;
int pin_count;
int num_class;
pugi::xml_node Cur;
for (i = 0; i < PhysicalTileType->num_pins; i++) {
PhysicalTileType->pin_class.push_back(OPEN);
PhysicalTileType->is_ignored_pin.push_back(true);
PhysicalTileType->is_pin_global.push_back(true);
}
pin_count = 0;
t_class_range class_range;
/* Equivalent pins share the same class, non-equivalent pins belong to different pin classes */
for (auto& sub_tile : PhysicalTileType->sub_tiles) {
int capacity = sub_tile.capacity.total();
class_range.low = PhysicalTileType->class_inf.size();
class_range.high = class_range.low - 1;
for (i = 0; i < capacity; ++i) {
for (const auto& port : sub_tile.ports) {
if (port.equivalent != PortEquivalence::NONE) {
t_class class_inf;
num_class = (int)PhysicalTileType->class_inf.size();
class_inf.num_pins = port.num_pins;
class_inf.equivalence = port.equivalent;
if (port.type == IN_PORT) {
class_inf.type = RECEIVER;
} else {
VTR_ASSERT(port.type == OUT_PORT);
class_inf.type = DRIVER;
}
for (k = 0; k < port.num_pins; ++k) {
class_inf.pinlist.push_back(pin_count);
PhysicalTileType->pin_class[pin_count] = num_class;
// clock pins and other specified global ports are initially specified
// as ignored pins (i.e. connections are not created in the rr_graph and
// nets connected to the port are ignored as well).
PhysicalTileType->is_ignored_pin[pin_count] = port.is_clock || port.is_non_clock_global;
// clock pins and other specified global ports are flaged as global
PhysicalTileType->is_pin_global[pin_count] = port.is_clock || port.is_non_clock_global;
if (port.is_clock) {
PhysicalTileType->clock_pin_indices.push_back(pin_count);
}
pin_count++;
}
PhysicalTileType->class_inf.push_back(class_inf);
class_range.high++;
} else if (port.equivalent == PortEquivalence::NONE) {
for (k = 0; k < port.num_pins; ++k) {
t_class class_inf;
num_class = (int)PhysicalTileType->class_inf.size();
class_inf.num_pins = 1;
class_inf.pinlist.push_back(pin_count);
class_inf.equivalence = port.equivalent;
if (port.type == IN_PORT) {
class_inf.type = RECEIVER;
} else {
VTR_ASSERT(port.type == OUT_PORT);
class_inf.type = DRIVER;
}
PhysicalTileType->pin_class[pin_count] = num_class;
// clock pins and other specified global ports are initially specified
// as ignored pins (i.e. connections are not created in the rr_graph and
// nets connected to the port are ignored as well).
PhysicalTileType->is_ignored_pin[pin_count] = port.is_clock || port.is_non_clock_global;
// clock pins and other specified global ports are flaged as global
PhysicalTileType->is_pin_global[pin_count] = port.is_clock || port.is_non_clock_global;
if (port.is_clock) {
PhysicalTileType->clock_pin_indices.push_back(pin_count);
}
pin_count++;
PhysicalTileType->class_inf.push_back(class_inf);
class_range.high++;
}
}
}
}
PhysicalTileType->sub_tiles[sub_tile.index].class_range = class_range;
}
VTR_ASSERT(pin_count == PhysicalTileType->num_pins);
}
static void LoadPinLoc(pugi::xml_node Locations,
t_physical_tile_type* type,
t_pin_locs* pin_locs,
const pugiutil::loc_data& loc_data) {
type->pin_width_offset.resize(type->num_pins, 0);
type->pin_height_offset.resize(type->num_pins, 0);
std::vector<int> physical_pin_counts(type->num_pins, 0);
if (pin_locs->distribution == E_SPREAD_PIN_DISTR) {
/* evenly distribute pins starting at bottom left corner */
int num_sides = 4 * (type->width * type->height);
int side_index = 0;
int count = 0;
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
for (int width = 0; width < type->width; ++width) {
for (int height = 0; height < type->height; ++height) {
for (int pin_offset = 0; pin_offset < (type->num_pins / num_sides) + 1; ++pin_offset) {
int pin_num = side_index + pin_offset * num_sides;
if (pin_num < type->num_pins) {
type->pinloc[width][height][side][pin_num] = true;
type->pin_width_offset[pin_num] += width;
type->pin_height_offset[pin_num] += height;
physical_pin_counts[pin_num] += 1;
count++;
}
}
side_index++;
}
}
}
VTR_ASSERT(side_index == num_sides);
VTR_ASSERT(count == type->num_pins);
} else if (pin_locs->distribution == E_PERIMETER_PIN_DISTR) {
//Add one pin at-a-time to perimeter sides in round-robin order
int ipin = 0;
while (ipin < type->num_pins) {
for (int width = 0; width < type->width; ++width) {
for (int height = 0; height < type->height; ++height) {
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
if (((width == 0 && side == LEFT)
|| (height == type->height - 1 && side == TOP)
|| (width == type->width - 1 && side == RIGHT)
|| (height == 0 && side == BOTTOM))
&& ipin < type->num_pins) {
//On a side, with pins still to allocate
type->pinloc[width][height][side][ipin] = true;
type->pin_width_offset[ipin] += width;
type->pin_height_offset[ipin] += height;
physical_pin_counts[ipin] += 1;
++ipin;
}
}
}
}
}
VTR_ASSERT(ipin == type->num_pins);
} else if (pin_locs->distribution == E_SPREAD_INPUTS_PERIMETER_OUTPUTS_PIN_DISTR) {
//Collect the sets of block input/output pins
std::vector<int> input_pins;
std::vector<int> output_pins;
for (int pin_num = 0; pin_num < type->num_pins; ++pin_num) {
int iclass = type->pin_class[pin_num];
if (type->class_inf[iclass].type == RECEIVER) {
input_pins.push_back(pin_num);
} else {
VTR_ASSERT(type->class_inf[iclass].type == DRIVER);
output_pins.push_back(pin_num);
}
}
//Allocate the inputs one pin at-a-time in a round-robin order
//to all sides
size_t ipin = 0;
while (ipin < input_pins.size()) {
for (int width = 0; width < type->width; ++width) {
for (int height = 0; height < type->height; ++height) {
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
if (ipin < input_pins.size()) {
//Pins still to allocate
int pin_num = input_pins[ipin];
type->pinloc[width][height][side][pin_num] = true;
type->pin_width_offset[pin_num] += width;
type->pin_height_offset[pin_num] += height;
physical_pin_counts[pin_num] += 1;
++ipin;
}
}
}
}
}
VTR_ASSERT(ipin == input_pins.size());
//Allocate the outputs one pin at-a-time to perimeter sides in round-robin order
ipin = 0;
while (ipin < output_pins.size()) {
for (int width = 0; width < type->width; ++width) {
for (int height = 0; height < type->height; ++height) {
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
if (((width == 0 && side == LEFT)
|| (height == type->height - 1 && side == TOP)
|| (width == type->width - 1 && side == RIGHT)
|| (height == 0 && side == BOTTOM))
&& ipin < output_pins.size()) {
//On a perimeter side, with pins still to allocate
int pin_num = output_pins[ipin];
type->pinloc[width][height][side][pin_num] = true;
type->pin_width_offset[pin_num] += width;
type->pin_height_offset[pin_num] += height;
physical_pin_counts[pin_num] += 1;
++ipin;
}
}
}
}
}
VTR_ASSERT(ipin == output_pins.size());
} else {
VTR_ASSERT(pin_locs->distribution == E_CUSTOM_PIN_DISTR);
for (auto& sub_tile : type->sub_tiles) {
int sub_tile_index = sub_tile.index;
int sub_tile_capacity = sub_tile.capacity.total();
for (int width = 0; width < type->width; ++width) {
for (int height = 0; height < type->height; ++height) {
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
for (auto token : pin_locs->assignments[sub_tile_index][width][height][side]) {
auto pin_range = ProcessPinString<t_sub_tile*>(Locations,
&sub_tile,
token.c_str(),
loc_data);
for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) {
VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity);
for (int capacity = 0; capacity < sub_tile_capacity; ++capacity) {
int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity;
int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index];
type->pinloc[width][height][side][physical_pin_index] = true;
type->pin_width_offset[physical_pin_index] += width;
type->pin_height_offset[physical_pin_index] += height;
physical_pin_counts[physical_pin_index] += 1;
}
}
}
}
}
}
}
}
for (int ipin = 0; ipin < type->num_pins; ++ipin) {
VTR_ASSERT(physical_pin_counts[ipin] >= 1);
type->pin_width_offset[ipin] /= physical_pin_counts[ipin];
type->pin_height_offset[ipin] /= physical_pin_counts[ipin];
VTR_ASSERT(type->pin_width_offset[ipin] >= 0 && type->pin_width_offset[ipin] < type->width);
VTR_ASSERT(type->pin_height_offset[ipin] >= 0 && type->pin_height_offset[ipin] < type->height);
}
}
template<typename T>
static std::pair<int, int> ProcessPinString(pugi::xml_node Locations,
T type,
const char* pin_loc_string,
const pugiutil::loc_data& loc_data) {
int num_tokens;
auto tokens = GetTokensFromString(pin_loc_string, &num_tokens);
int token_index = 0;
auto token = tokens[token_index];
if (token.type != TOKEN_STRING || 0 != strcmp(token.data, type->name)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"Wrong physical type name of the port: %s\n", pin_loc_string);
}
token_index++;
token = tokens[token_index];
if (token.type != TOKEN_DOT) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"No dot is present to separate type name and port name: %s\n", pin_loc_string);
}
token_index++;
token = tokens[token_index];
if (token.type != TOKEN_STRING) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"No port name is present: %s\n", pin_loc_string);
}
auto port = get_port_by_name(type, token.data);
if (port == nullptr) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"Port %s for %s could not be found: %s\n",
type->name, token.data,
pin_loc_string);
}
int abs_first_pin_idx = port->absolute_first_pin_index;
token_index++;
// All the pins of the port are taken or the port has a single pin
if (token_index == num_tokens) {
freeTokens(tokens, num_tokens);
return std::make_pair(abs_first_pin_idx, abs_first_pin_idx + port->num_pins);
}
token = tokens[token_index];
if (token.type != TOKEN_OPEN_SQUARE_BRACKET) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"No open square bracket present: %s\n", pin_loc_string);
}
token_index++;
token = tokens[token_index];
if (token.type != TOKEN_INT) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"No integer to indicate least significant pin index: %s\n", pin_loc_string);
}
int first_pin = vtr::atoi(token.data);
token_index++;
token = tokens[token_index];
// Single pin is specified
if (token.type != TOKEN_COLON) {
if (token.type != TOKEN_CLOSE_SQUARE_BRACKET) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"No closing bracket: %s\n", pin_loc_string);
}
token_index++;
if (token_index != num_tokens) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"pin location should be completed, but more tokens are present: %s\n", pin_loc_string);
}
freeTokens(tokens, num_tokens);
return std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + first_pin + 1);
}
token_index++;
token = tokens[token_index];
if (token.type != TOKEN_INT) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"No integer to indicate most significant pin index: %s\n", pin_loc_string);
}
int last_pin = vtr::atoi(token.data);
token_index++;
token = tokens[token_index];
if (token.type != TOKEN_CLOSE_SQUARE_BRACKET) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"No closed square bracket: %s\n", pin_loc_string);
}
token_index++;
if (token_index != num_tokens) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"pin location should be completed, but more tokens are present: %s\n", pin_loc_string);
}
if (first_pin > last_pin) {
std::swap(first_pin, last_pin);
}
freeTokens(tokens, num_tokens);
return std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + last_pin + 1);
}
static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
t_pin_to_pin_annotation* annotation,
t_pb_type* parent_pb_type,
const pugiutil::loc_data& loc_data) {
int i = 0;
const char* Prop;
if (get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr)) {
i++;
}
if (get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr)) {
i++;
}
if (get_attribute(Parent, "type", loc_data, ReqOpt::OPTIONAL).as_string(nullptr)) {
i++;
}
if (get_attribute(Parent, "value", loc_data, ReqOpt::OPTIONAL).as_string(nullptr)) {
i++;
}
if (0 == strcmp(Parent.name(), "C_constant")
|| 0 == strcmp(Parent.name(), "C_matrix")
|| 0 == strcmp(Parent.name(), "pack_pattern")) {
i = 1;
}
annotation->num_value_prop_pairs = i;
annotation->prop = (int*)vtr::calloc(i, sizeof(int));
annotation->value = (char**)vtr::calloc(i, sizeof(char*));
annotation->line_num = loc_data.line(Parent);
/* Todo: This is slow, I should use a case lookup */
i = 0;
if (0 == strcmp(Parent.name(), "delay_constant")) {
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (Prop) {
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX;
annotation->value[i] = vtr::strdup(Prop);
i++;
}
Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (Prop) {
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN;
annotation->value[i] = vtr::strdup(Prop);
i++;
}
Prop = get_attribute(Parent, "in_port", loc_data).value();
annotation->input_pins = vtr::strdup(Prop);
Prop = get_attribute(Parent, "out_port", loc_data).value();
annotation->output_pins = vtr::strdup(Prop);
} else if (0 == strcmp(Parent.name(), "delay_matrix")) {
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX;
Prop = get_attribute(Parent, "type", loc_data).value();
annotation->value[i] = vtr::strdup(Parent.child_value());
if (0 == strcmp(Prop, "max")) {
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MAX;
} else {
VTR_ASSERT(0 == strcmp(Prop, "min"));
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_MIN;
}
i++;
Prop = get_attribute(Parent, "in_port", loc_data).value();
annotation->input_pins = vtr::strdup(Prop);
Prop = get_attribute(Parent, "out_port", loc_data).value();
annotation->output_pins = vtr::strdup(Prop);
} else if (0 == strcmp(Parent.name(), "C_constant")) {
annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE;
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
Prop = get_attribute(Parent, "C", loc_data).value();
annotation->value[i] = vtr::strdup(Prop);
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C;
i++;
Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
annotation->input_pins = vtr::strdup(Prop);
Prop = get_attribute(Parent, "out_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
annotation->output_pins = vtr::strdup(Prop);
VTR_ASSERT(annotation->output_pins != nullptr || annotation->input_pins != nullptr);
} else if (0 == strcmp(Parent.name(), "C_matrix")) {
annotation->type = E_ANNOT_PIN_TO_PIN_CAPACITANCE;
annotation->format = E_ANNOT_PIN_TO_PIN_MATRIX;
annotation->value[i] = vtr::strdup(Parent.child_value());
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_CAPACITANCE_C;
i++;
Prop = get_attribute(Parent, "in_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
annotation->input_pins = vtr::strdup(Prop);
Prop = get_attribute(Parent, "out_port", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
annotation->output_pins = vtr::strdup(Prop);
VTR_ASSERT(annotation->output_pins != nullptr || annotation->input_pins != nullptr);
} else if (0 == strcmp(Parent.name(), "T_setup")) {
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
Prop = get_attribute(Parent, "value", loc_data).value();
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_TSETUP;
annotation->value[i] = vtr::strdup(Prop);
i++;
Prop = get_attribute(Parent, "port", loc_data).value();
annotation->input_pins = vtr::strdup(Prop);
Prop = get_attribute(Parent, "clock", loc_data).value();
annotation->clock = vtr::strdup(Prop);
primitives_annotation_clock_match(annotation, parent_pb_type);
} else if (0 == strcmp(Parent.name(), "T_clock_to_Q")) {
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
Prop = get_attribute(Parent, "max", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
bool found_min_max_attrib = false;
if (Prop) {
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX;
annotation->value[i] = vtr::strdup(Prop);
i++;
found_min_max_attrib = true;
}
Prop = get_attribute(Parent, "min", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (Prop) {
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN;
annotation->value[i] = vtr::strdup(Prop);
i++;
found_min_max_attrib = true;
}
if (!found_min_max_attrib) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Failed to find either 'max' or 'min' attribute required for <%s> in <%s>",
Parent.name(), Parent.parent().name());
}
Prop = get_attribute(Parent, "port", loc_data).value();
annotation->input_pins = vtr::strdup(Prop);
Prop = get_attribute(Parent, "clock", loc_data).value();
annotation->clock = vtr::strdup(Prop);
primitives_annotation_clock_match(annotation, parent_pb_type);
} else if (0 == strcmp(Parent.name(), "T_hold")) {
annotation->type = E_ANNOT_PIN_TO_PIN_DELAY;
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
Prop = get_attribute(Parent, "value", loc_data).value();
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_DELAY_THOLD;
annotation->value[i] = vtr::strdup(Prop);
i++;
Prop = get_attribute(Parent, "port", loc_data).value();
annotation->input_pins = vtr::strdup(Prop);
Prop = get_attribute(Parent, "clock", loc_data).value();
annotation->clock = vtr::strdup(Prop);
primitives_annotation_clock_match(annotation, parent_pb_type);
} else if (0 == strcmp(Parent.name(), "pack_pattern")) {
annotation->type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
annotation->format = E_ANNOT_PIN_TO_PIN_CONSTANT;
Prop = get_attribute(Parent, "name", loc_data).value();
annotation->prop[i] = (int)E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME;
annotation->value[i] = vtr::strdup(Prop);
i++;
Prop = get_attribute(Parent, "in_port", loc_data).value();
annotation->input_pins = vtr::strdup(Prop);
Prop = get_attribute(Parent, "out_port", loc_data).value();
annotation->output_pins = vtr::strdup(Prop);
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Unknown port type %s in %s in %s", Parent.name(),
Parent.parent().name(), Parent.parent().parent().name());
}
VTR_ASSERT(i == annotation->num_value_prop_pairs);
}
static void ProcessPb_TypePowerPinToggle(pugi::xml_node parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) {
pugi::xml_node cur;
const char* prop;
t_port* port;
int high, low;
cur = get_first_child(parent, "port", loc_data, ReqOpt::OPTIONAL);
while (cur) {
prop = get_attribute(cur, "name", loc_data).value();
port = findPortByName(prop, pb_type, &high, &low);
if (!port) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Could not find port '%s' needed for energy per toggle.",
prop);
}
if (high != port->num_pins - 1 || low != 0) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Pin-toggle does not support pin indices (%s)", prop);
}
if (port->port_power->pin_toggle_initialized) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Duplicate pin-toggle energy for port '%s'", port->name);
}
port->port_power->pin_toggle_initialized = true;
/* Get energy per toggle */
port->port_power->energy_per_toggle = get_attribute(cur,
"energy_per_toggle", loc_data)
.as_float(0.);
/* Get scaled by factor */
bool reverse_scaled = false;
prop = get_attribute(cur, "scaled_by_static_prob", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (!prop) {
prop = get_attribute(cur, "scaled_by_static_prob_n", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (prop) {
reverse_scaled = true;
}
}
if (prop) {
port->port_power->scaled_by_port = findPortByName(prop, pb_type,
&high, &low);
if (high != low) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Pin-toggle 'scaled_by_static_prob' must be a single pin (%s)",
prop);
}
port->port_power->scaled_by_port_pin_idx = high;
port->port_power->reverse_scaled = reverse_scaled;
}
cur = cur.next_sibling(cur.name());
}
}
static void ProcessPb_TypePower(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) {
pugi::xml_node cur, child;
bool require_dynamic_absolute = false;
bool require_static_absolute = false;
bool require_dynamic_C_internal = false;
cur = get_first_child(Parent, "power", loc_data, ReqOpt::OPTIONAL);
if (!cur) {
return;
}
switch (pb_type->pb_type_power->estimation_method) {
case POWER_METHOD_TOGGLE_PINS:
ProcessPb_TypePowerPinToggle(cur, pb_type, loc_data);
require_static_absolute = true;
break;
case POWER_METHOD_C_INTERNAL:
require_dynamic_C_internal = true;
require_static_absolute = true;
break;
case POWER_METHOD_ABSOLUTE:
require_dynamic_absolute = true;
require_static_absolute = true;
break;
default:
break;
}
if (require_static_absolute) {
child = get_single_child(cur, "static_power", loc_data);
pb_type->pb_type_power->absolute_power_per_instance.leakage = get_attribute(child, "power_per_instance", loc_data).as_float(0.);
}
if (require_dynamic_absolute) {
child = get_single_child(cur, "dynamic_power", loc_data);
pb_type->pb_type_power->absolute_power_per_instance.dynamic = get_attribute(child, "power_per_instance", loc_data).as_float(0.);
}
if (require_dynamic_C_internal) {
child = get_single_child(cur, "dynamic_power", loc_data);
pb_type->pb_type_power->C_internal = get_attribute(child,
"C_internal", loc_data)
.as_float(0.);
}
}
static void ProcessPb_TypePowerEstMethod(pugi::xml_node Parent, t_pb_type* pb_type, const pugiutil::loc_data& loc_data) {
pugi::xml_node cur;
const char* prop;
e_power_estimation_method parent_power_method;
prop = nullptr;
cur = get_first_child(Parent, "power", loc_data, ReqOpt::OPTIONAL);
if (cur) {
prop = get_attribute(cur, "method", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
}
if (pb_type->parent_mode && pb_type->parent_mode->parent_pb_type) {
parent_power_method = pb_type->parent_mode->parent_pb_type->pb_type_power->estimation_method;
} else {
parent_power_method = POWER_METHOD_AUTO_SIZES;
}
if (!prop) {
/* default method is auto-size */
pb_type->pb_type_power->estimation_method = power_method_inherited(parent_power_method);
} else if (strcmp(prop, "auto-size") == 0) {
pb_type->pb_type_power->estimation_method = POWER_METHOD_AUTO_SIZES;
} else if (strcmp(prop, "specify-size") == 0) {
pb_type->pb_type_power->estimation_method = POWER_METHOD_SPECIFY_SIZES;
} else if (strcmp(prop, "pin-toggle") == 0) {
pb_type->pb_type_power->estimation_method = POWER_METHOD_TOGGLE_PINS;
} else if (strcmp(prop, "c-internal") == 0) {
pb_type->pb_type_power->estimation_method = POWER_METHOD_C_INTERNAL;
} else if (strcmp(prop, "absolute") == 0) {
pb_type->pb_type_power->estimation_method = POWER_METHOD_ABSOLUTE;
} else if (strcmp(prop, "ignore") == 0) {
pb_type->pb_type_power->estimation_method = POWER_METHOD_IGNORE;
} else if (strcmp(prop, "sum-of-children") == 0) {
pb_type->pb_type_power->estimation_method = POWER_METHOD_SUM_OF_CHILDREN;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Invalid power estimation method for pb_type '%s'",
pb_type->name);
}
}
/* Takes in a pb_type, allocates and loads data for it and recurses downwards */
static void ProcessPb_Type(vtr::string_internment* strings, pugi::xml_node Parent, t_pb_type* pb_type, t_mode* mode, const bool timing_enabled, const t_arch& arch, const pugiutil::loc_data& loc_data) {
int num_ports, i, j, k, num_annotations;
const char* Prop;
pugi::xml_node Cur;
bool is_root_pb_type = !(mode != nullptr && mode->parent_pb_type != nullptr);
bool is_leaf_pb_type = bool(get_attribute(Parent, "blif_model", loc_data, ReqOpt::OPTIONAL));
std::vector<std::string> children_to_expect = {"input", "output", "clock", "mode", "power", "metadata"};
if (!is_leaf_pb_type) {
//Non-leafs may have a model/pb_type children
children_to_expect.push_back("model");
children_to_expect.push_back("pb_type");
children_to_expect.push_back("interconnect");
if (is_root_pb_type) {
VTR_ASSERT(!is_leaf_pb_type);
//Top level pb_type's may also have the following tag types
children_to_expect.push_back("fc");
children_to_expect.push_back("pinlocations");
children_to_expect.push_back("switchblock_locations");
}
} else {
VTR_ASSERT(is_leaf_pb_type);
VTR_ASSERT(!is_root_pb_type);
//Leaf pb_type's may also have the following tag types
children_to_expect.push_back("T_setup");
children_to_expect.push_back("T_hold");
children_to_expect.push_back("T_clock_to_Q");
children_to_expect.push_back("delay_constant");
children_to_expect.push_back("delay_matrix");
}
//Sanity check contained tags
expect_only_children(Parent, children_to_expect, loc_data);
char* class_name;
/* STL maps for checking various duplicate names */
std::map<std::string, int> pb_port_names;
std::map<std::string, int> mode_names;
std::pair<std::map<std::string, int>::iterator, bool> ret_pb_ports;
std::pair<std::map<std::string, int>::iterator, bool> ret_mode_names;
int num_in_ports, num_out_ports, num_clock_ports;
int num_delay_constant, num_delay_matrix, num_C_constant, num_C_matrix,
num_T_setup, num_T_cq, num_T_hold;
pb_type->parent_mode = mode;
if (mode != nullptr && mode->parent_pb_type != nullptr) {
pb_type->depth = mode->parent_pb_type->depth + 1;
Prop = get_attribute(Parent, "name", loc_data).value();
pb_type->name = vtr::strdup(Prop);
} else {
pb_type->depth = 0;
/* same name as type */
}
Prop = get_attribute(Parent, "blif_model", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
pb_type->blif_model = vtr::strdup(Prop);
pb_type->class_type = UNKNOWN_CLASS;
Prop = get_attribute(Parent, "class", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
class_name = vtr::strdup(Prop);
if (class_name) {
if (0 == strcmp(class_name, PB_TYPE_CLASS_STRING[LUT_CLASS])) {
pb_type->class_type = LUT_CLASS;
} else if (0 == strcmp(class_name, PB_TYPE_CLASS_STRING[LATCH_CLASS])) {
pb_type->class_type = LATCH_CLASS;
} else if (0 == strcmp(class_name, PB_TYPE_CLASS_STRING[MEMORY_CLASS])) {
pb_type->class_type = MEMORY_CLASS;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Unknown class '%s' in pb_type '%s'\n", class_name,
pb_type->name);
}
free(class_name);
}
if (mode == nullptr) {
pb_type->num_pb = 1;
} else {
pb_type->num_pb = get_attribute(Parent, "num_pb", loc_data).as_int(0);
}
VTR_ASSERT(pb_type->num_pb > 0);
num_ports = num_in_ports = num_out_ports = num_clock_ports = 0;
num_in_ports = count_children(Parent, "input", loc_data, ReqOpt::OPTIONAL);
num_out_ports = count_children(Parent, "output", loc_data, ReqOpt::OPTIONAL);
num_clock_ports = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL);
num_ports = num_in_ports + num_out_ports + num_clock_ports;
pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
pb_type->num_ports = num_ports;
/* Enforce VPR's definition of LUT/FF by checking number of ports */
if (pb_type->class_type == LUT_CLASS
|| pb_type->class_type == LATCH_CLASS) {
if (num_in_ports != 1 || num_out_ports != 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"%s primitives must contain exactly one input port and one output port."
"Found '%d' input port(s) and '%d' output port(s) for '%s'",
(pb_type->class_type == LUT_CLASS) ? "LUT" : "Latch",
num_in_ports, num_out_ports, pb_type->name);
}
}
/* Initialize Power Structure */
pb_type->pb_type_power = (t_pb_type_power*)vtr::calloc(1,
sizeof(t_pb_type_power));
ProcessPb_TypePowerEstMethod(Parent, pb_type, loc_data);
/* process ports */
j = 0;
int absolute_port_first_pin_index = 0;
for (i = 0; i < 3; i++) {
if (i == 0) {
k = 0;
Cur = get_first_child(Parent, "input", loc_data, ReqOpt::OPTIONAL);
} else if (i == 1) {
k = 0;
Cur = get_first_child(Parent, "output", loc_data, ReqOpt::OPTIONAL);
} else {
k = 0;
Cur = get_first_child(Parent, "clock", loc_data, ReqOpt::OPTIONAL);
}
while (Cur) {
pb_type->ports[j].parent_pb_type = pb_type;
pb_type->ports[j].index = j;
pb_type->ports[j].port_index_by_type = k;
ProcessPb_TypePort(Cur, &pb_type->ports[j],
pb_type->pb_type_power->estimation_method, is_root_pb_type, loc_data);
pb_type->ports[j].absolute_first_pin_index = absolute_port_first_pin_index;
absolute_port_first_pin_index += pb_type->ports[j].num_pins;
//Check port name duplicates
ret_pb_ports = pb_port_names.insert(std::pair<std::string, int>(pb_type->ports[j].name, 0));
if (!ret_pb_ports.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Duplicate port names in pb_type '%s': port '%s'\n",
pb_type->name, pb_type->ports[j].name);
}
/* get next iteration */
j++;
k++;
Cur = Cur.next_sibling(Cur.name());
}
}
VTR_ASSERT(j == num_ports);
/* Count stats on the number of each type of pin */
pb_type->num_clock_pins = pb_type->num_input_pins = pb_type->num_output_pins = 0;
for (i = 0; i < pb_type->num_ports; i++) {
if (pb_type->ports[i].type == IN_PORT
&& pb_type->ports[i].is_clock == false) {
pb_type->num_input_pins += pb_type->ports[i].num_pins;
} else if (pb_type->ports[i].type == OUT_PORT) {
pb_type->num_output_pins += pb_type->ports[i].num_pins;
} else {
VTR_ASSERT(pb_type->ports[i].is_clock
&& pb_type->ports[i].type == IN_PORT);
pb_type->num_clock_pins += pb_type->ports[i].num_pins;
}
}
pb_type->num_pins = pb_type->num_input_pins + pb_type->num_output_pins + pb_type->num_clock_pins;
//Warn that max_internal_delay is no longer supported
//TODO: eventually remove
try {
expect_child_node_count(Parent, "max_internal_delay", 0, loc_data);
} catch (pugiutil::XmlError& e) {
std::string msg = e.what();
msg += ". <max_internal_delay> has been replaced with <delay_constant>/<delay_matrix> between sequential primitive ports.";
msg += " Please upgrade your architecture file.";
archfpga_throw(e.filename().c_str(), e.line(), msg.c_str());
}
pb_type->annotations = nullptr;
pb_type->num_annotations = 0;
i = 0;
/* Determine if this is a leaf or container pb_type */
if (pb_type->blif_model != nullptr) {
/* Process delay and capacitance annotations */
num_annotations = 0;
num_delay_constant = count_children(Parent, "delay_constant", loc_data, ReqOpt::OPTIONAL);
num_delay_matrix = count_children(Parent, "delay_matrix", loc_data, ReqOpt::OPTIONAL);
num_C_constant = count_children(Parent, "C_constant", loc_data, ReqOpt::OPTIONAL);
num_C_matrix = count_children(Parent, "C_matrix", loc_data, ReqOpt::OPTIONAL);
num_T_setup = count_children(Parent, "T_setup", loc_data, ReqOpt::OPTIONAL);
num_T_cq = count_children(Parent, "T_clock_to_Q", loc_data, ReqOpt::OPTIONAL);
num_T_hold = count_children(Parent, "T_hold", loc_data, ReqOpt::OPTIONAL);
num_annotations = num_delay_constant + num_delay_matrix + num_C_constant
+ num_C_matrix + num_T_setup + num_T_cq + num_T_hold;
pb_type->annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations, sizeof(t_pin_to_pin_annotation));
pb_type->num_annotations = num_annotations;
j = 0;
for (i = 0; i < 7; i++) {
if (i == 0) {
Cur = get_first_child(Parent, "delay_constant", loc_data, ReqOpt::OPTIONAL);
} else if (i == 1) {
Cur = get_first_child(Parent, "delay_matrix", loc_data, ReqOpt::OPTIONAL);
} else if (i == 2) {
Cur = get_first_child(Parent, "C_constant", loc_data, ReqOpt::OPTIONAL);
} else if (i == 3) {
Cur = get_first_child(Parent, "C_matrix", loc_data, ReqOpt::OPTIONAL);
} else if (i == 4) {
Cur = get_first_child(Parent, "T_setup", loc_data, ReqOpt::OPTIONAL);
} else if (i == 5) {
Cur = get_first_child(Parent, "T_clock_to_Q", loc_data, ReqOpt::OPTIONAL);
} else if (i == 6) {
Cur = get_first_child(Parent, "T_hold", loc_data, ReqOpt::OPTIONAL);
}
while (Cur) {
ProcessPinToPinAnnotations(Cur, &pb_type->annotations[j],
pb_type, loc_data);
/* get next iteration */
j++;
Cur = Cur.next_sibling(Cur.name());
}
}
VTR_ASSERT(j == num_annotations);
if (timing_enabled) {
check_leaf_pb_model_timing_consistency(pb_type, arch);
}
/* leaf pb_type, if special known class, then read class lib otherwise treat as primitive */
if (pb_type->class_type == LUT_CLASS) {
ProcessLutClass(pb_type);
} else if (pb_type->class_type == MEMORY_CLASS) {
ProcessMemoryClass(pb_type);
} else {
/* other leaf pb_type do not have modes */
pb_type->num_modes = 0;
VTR_ASSERT(count_children(Parent, "mode", loc_data, ReqOpt::OPTIONAL) == 0);
}
} else {
/* container pb_type, process modes */
VTR_ASSERT(pb_type->class_type == UNKNOWN_CLASS);
pb_type->num_modes = count_children(Parent, "mode", loc_data, ReqOpt::OPTIONAL);
pb_type->pb_type_power->leakage_default_mode = 0;
if (pb_type->num_modes == 0) {
/* The pb_type operates in an implied one mode */
pb_type->num_modes = 1;
pb_type->modes = new t_mode[pb_type->num_modes];
pb_type->modes[i].parent_pb_type = pb_type;
pb_type->modes[i].index = i;
ProcessMode(strings, Parent, &pb_type->modes[i], timing_enabled, arch, loc_data);
i++;
} else {
pb_type->modes = new t_mode[pb_type->num_modes];
Cur = get_first_child(Parent, "mode", loc_data);
while (Cur != nullptr) {
if (0 == strcmp(Cur.name(), "mode")) {
pb_type->modes[i].parent_pb_type = pb_type;
pb_type->modes[i].index = i;
ProcessMode(strings, Cur, &pb_type->modes[i], timing_enabled, arch, loc_data);
ret_mode_names = mode_names.insert(std::pair<std::string, int>(pb_type->modes[i].name, 0));
if (!ret_mode_names.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Duplicate mode name: '%s' in pb_type '%s'.\n",
pb_type->modes[i].name, pb_type->name);
}
/* get next iteration */
i++;
Cur = Cur.next_sibling(Cur.name());
}
}
}
VTR_ASSERT(i == pb_type->num_modes);
}
pb_port_names.clear();
mode_names.clear();
pb_type->meta = ProcessMetadata(strings, Parent, loc_data);
ProcessPb_TypePower(Parent, pb_type, loc_data);
}
static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const pugiutil::loc_data& loc_data) {
pugi::xml_node cur;
const char* prop;
bool wire_defined = false;
port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power));
//Defaults
if (power_method == POWER_METHOD_AUTO_SIZES) {
port->port_power->wire_type = POWER_WIRE_TYPE_AUTO;
port->port_power->buffer_type = POWER_BUFFER_TYPE_AUTO;
} else if (power_method == POWER_METHOD_SPECIFY_SIZES) {
port->port_power->wire_type = POWER_WIRE_TYPE_IGNORED;
port->port_power->buffer_type = POWER_BUFFER_TYPE_NONE;
}
cur = get_single_child(Parent, "power", loc_data, ReqOpt::OPTIONAL);
if (cur) {
/* Wire capacitance */
/* Absolute C provided */
prop = get_attribute(cur, "wire_capacitance", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (prop) {
if (!(power_method == POWER_METHOD_AUTO_SIZES
|| power_method == POWER_METHOD_SPECIFY_SIZES)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Wire capacitance defined for port '%s'. This is an invalid option for the parent pb_type '%s' power estimation method.",
port->name, port->parent_pb_type->name);
} else {
wire_defined = true;
port->port_power->wire_type = POWER_WIRE_TYPE_C;
port->port_power->wire.C = (float)atof(prop);
}
}
/* Wire absolute length provided */
prop = get_attribute(cur, "wire_length", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (prop) {
if (!(power_method == POWER_METHOD_AUTO_SIZES
|| power_method == POWER_METHOD_SPECIFY_SIZES)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Wire length defined for port '%s'. This is an invalid option for the parent pb_type '%s' power estimation method.",
port->name, port->parent_pb_type->name);
} else if (wire_defined) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Multiple wire properties defined for port '%s', pb_type '%s'.",
port->name, port->parent_pb_type->name);
} else if (strcmp(prop, "auto") == 0) {
wire_defined = true;
port->port_power->wire_type = POWER_WIRE_TYPE_AUTO;
} else {
wire_defined = true;
port->port_power->wire_type = POWER_WIRE_TYPE_ABSOLUTE_LENGTH;
port->port_power->wire.absolute_length = (float)atof(prop);
}
}
/* Wire relative length provided */
prop = get_attribute(cur, "wire_relative_length", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (prop) {
if (!(power_method == POWER_METHOD_AUTO_SIZES
|| power_method == POWER_METHOD_SPECIFY_SIZES)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Wire relative length defined for port '%s'. This is an invalid option for the parent pb_type '%s' power estimation method.",
port->name, port->parent_pb_type->name);
} else if (wire_defined) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Multiple wire properties defined for port '%s', pb_type '%s'.",
port->name, port->parent_pb_type->name);
} else {
wire_defined = true;
port->port_power->wire_type = POWER_WIRE_TYPE_RELATIVE_LENGTH;
port->port_power->wire.relative_length = (float)atof(prop);
}
}
/* Buffer Size */
prop = get_attribute(cur, "buffer_size", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (prop) {
if (!(power_method == POWER_METHOD_AUTO_SIZES
|| power_method == POWER_METHOD_SPECIFY_SIZES)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(cur),
"Buffer size defined for port '%s'. This is an invalid option for the parent pb_type '%s' power estimation method.",
port->name, port->parent_pb_type->name);
} else if (strcmp(prop, "auto") == 0) {
port->port_power->buffer_type = POWER_BUFFER_TYPE_AUTO;
} else {
port->port_power->buffer_type = POWER_BUFFER_TYPE_ABSOLUTE_SIZE;
port->port_power->buffer_size = (float)atof(prop);
}
}
}
}
static void ProcessPb_TypePort(pugi::xml_node Parent, t_port* port, e_power_estimation_method power_method, const bool is_root_pb_type, const pugiutil::loc_data& loc_data) {
std::vector<std::string> expected_attributes = {"name", "num_pins", "port_class"};
if (is_root_pb_type) {
expected_attributes.push_back("equivalent");
if (Parent.name() == "input"s || Parent.name() == "clock"s) {
expected_attributes.push_back("is_non_clock_global");
}
}
expect_only_attributes(Parent, expected_attributes, loc_data);
const char* Prop;
Prop = get_attribute(Parent, "name", loc_data).value();
port->name = vtr::strdup(Prop);
Prop = get_attribute(Parent, "port_class", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
port->port_class = vtr::strdup(Prop);
Prop = get_attribute(Parent, "equivalent", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (Prop) {
if (Prop == "none"s) {
port->equivalent = PortEquivalence::NONE;
} else if (Prop == "full"s) {
port->equivalent = PortEquivalence::FULL;
} else if (Prop == "instance"s) {
if (Parent.name() == "output"s) {
port->equivalent = PortEquivalence::INSTANCE;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Invalid pin equivalence '%s' for %s port.", Prop, Parent.name());
}
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Invalid pin equivalence '%s'.", Prop);
}
}
port->num_pins = get_attribute(Parent, "num_pins", loc_data).as_int(0);
port->is_non_clock_global = get_attribute(Parent,
"is_non_clock_global", loc_data, ReqOpt::OPTIONAL)
.as_bool(false);
if (port->num_pins <= 0) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Invalid number of pins %d for %s port.", port->num_pins, Parent.name());
}
if (0 == strcmp(Parent.name(), "input")) {
port->type = IN_PORT;
port->is_clock = false;
/* Check if LUT/FF port class is lut_in/D */
if (port->parent_pb_type->class_type == LUT_CLASS) {
if ((!port->port_class) || strcmp("lut_in", port->port_class)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Inputs to LUT primitives must have a port class named "
"as \"lut_in\".");
}
} else if (port->parent_pb_type->class_type == LATCH_CLASS) {
if ((!port->port_class) || strcmp("D", port->port_class)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Input to flipflop primitives must have a port class named "
"as \"D\".");
}
/* Only allow one input pin for FF's */
if (port->num_pins != 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Input port of flipflop primitives must have exactly one pin. "
"Found %d.",
port->num_pins);
}
}
} else if (0 == strcmp(Parent.name(), "output")) {
port->type = OUT_PORT;
port->is_clock = false;
/* Check if LUT/FF port class is lut_out/Q */
if (port->parent_pb_type->class_type == LUT_CLASS) {
if ((!port->port_class) || strcmp("lut_out", port->port_class)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Output to LUT primitives must have a port class named "
"as \"lut_in\".");
}
/* Only allow one output pin for LUT's */
if (port->num_pins != 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Output port of LUT primitives must have exactly one pin. "
"Found %d.",
port->num_pins);
}
} else if (port->parent_pb_type->class_type == LATCH_CLASS) {
if ((!port->port_class) || strcmp("Q", port->port_class)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Output to flipflop primitives must have a port class named "
"as \"D\".");
}
/* Only allow one output pin for FF's */
if (port->num_pins != 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Output port of flipflop primitives must have exactly one pin. "
"Found %d.",
port->num_pins);
}
}
} else if (0 == strcmp(Parent.name(), "clock")) {
port->type = IN_PORT;
port->is_clock = true;
if (port->is_non_clock_global == true) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Port %s cannot be both a clock and a non-clock simultaneously\n",
Parent.name());
}
if (port->parent_pb_type->class_type == LATCH_CLASS) {
if ((!port->port_class) || strcmp("clock", port->port_class)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Clock to flipflop primitives must have a port class named "
"as \"clock\".");
}
/* Only allow one output pin for FF's */
if (port->num_pins != 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Clock port of flipflop primitives must have exactly one pin. "
"Found %d.",
port->num_pins);
}
}
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Unknown port type %s", Parent.name());
}
ProcessPb_TypePort_Power(Parent, port, power_method, loc_data);
}
static void ProcessInterconnect(vtr::string_internment* strings, pugi::xml_node Parent, t_mode* mode, const pugiutil::loc_data& loc_data) {
int num_interconnect = 0;
int num_complete, num_direct, num_mux;
int i, j, k, L_index, num_annotations;
int num_delay_constant, num_delay_matrix, num_C_constant, num_C_matrix,
num_pack_pattern;
const char* Prop;
pugi::xml_node Cur;
pugi::xml_node Cur2;
std::map<std::string, int> interc_names;
std::pair<std::map<std::string, int>::iterator, bool> ret_interc_names;
num_complete = num_direct = num_mux = 0;
num_complete = count_children(Parent, "complete", loc_data, ReqOpt::OPTIONAL);
num_direct = count_children(Parent, "direct", loc_data, ReqOpt::OPTIONAL);
num_mux = count_children(Parent, "mux", loc_data, ReqOpt::OPTIONAL);
num_interconnect = num_complete + num_direct + num_mux;
mode->num_interconnect = num_interconnect;
mode->interconnect = new t_interconnect[num_interconnect];
i = 0;
for (L_index = 0; L_index < 3; L_index++) {
if (L_index == 0) {
Cur = get_first_child(Parent, "complete", loc_data, ReqOpt::OPTIONAL);
} else if (L_index == 1) {
Cur = get_first_child(Parent, "direct", loc_data, ReqOpt::OPTIONAL);
} else {
Cur = get_first_child(Parent, "mux", loc_data, ReqOpt::OPTIONAL);
}
while (Cur != nullptr) {
if (0 == strcmp(Cur.name(), "complete")) {
mode->interconnect[i].type = COMPLETE_INTERC;
} else if (0 == strcmp(Cur.name(), "direct")) {
mode->interconnect[i].type = DIRECT_INTERC;
} else {
VTR_ASSERT(0 == strcmp(Cur.name(), "mux"));
mode->interconnect[i].type = MUX_INTERC;
}
mode->interconnect[i].line_num = loc_data.line(Cur);
mode->interconnect[i].parent_mode_index = mode->index;
mode->interconnect[i].parent_mode = mode;
Prop = get_attribute(Cur, "input", loc_data).value();
mode->interconnect[i].input_string = vtr::strdup(Prop);
Prop = get_attribute(Cur, "output", loc_data).value();
mode->interconnect[i].output_string = vtr::strdup(Prop);
Prop = get_attribute(Cur, "name", loc_data).value();
mode->interconnect[i].name = vtr::strdup(Prop);
mode->interconnect[i].meta = ProcessMetadata(strings, Cur, loc_data);
ret_interc_names = interc_names.insert(std::pair<std::string, int>(mode->interconnect[i].name, 0));
if (!ret_interc_names.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Duplicate interconnect name: '%s' in mode: '%s'.\n",
mode->interconnect[i].name, mode->name);
}
/* Process delay and capacitance annotations */
num_annotations = 0;
num_delay_constant = count_children(Cur, "delay_constant", loc_data, ReqOpt::OPTIONAL);
num_delay_matrix = count_children(Cur, "delay_matrix", loc_data, ReqOpt::OPTIONAL);
num_C_constant = count_children(Cur, "C_constant", loc_data, ReqOpt::OPTIONAL);
num_C_matrix = count_children(Cur, "C_matrix", loc_data, ReqOpt::OPTIONAL);
num_pack_pattern = count_children(Cur, "pack_pattern", loc_data, ReqOpt::OPTIONAL);
num_annotations = num_delay_constant + num_delay_matrix
+ num_C_constant + num_C_matrix + num_pack_pattern;
mode->interconnect[i].annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations,
sizeof(t_pin_to_pin_annotation));
mode->interconnect[i].num_annotations = num_annotations;
k = 0;
for (j = 0; j < 5; j++) {
if (j == 0) {
Cur2 = get_first_child(Cur, "delay_constant", loc_data, ReqOpt::OPTIONAL);
} else if (j == 1) {
Cur2 = get_first_child(Cur, "delay_matrix", loc_data, ReqOpt::OPTIONAL);
} else if (j == 2) {
Cur2 = get_first_child(Cur, "C_constant", loc_data, ReqOpt::OPTIONAL);
} else if (j == 3) {
Cur2 = get_first_child(Cur, "C_matrix", loc_data, ReqOpt::OPTIONAL);
} else if (j == 4) {
Cur2 = get_first_child(Cur, "pack_pattern", loc_data, ReqOpt::OPTIONAL);
}
while (Cur2 != nullptr) {
ProcessPinToPinAnnotations(Cur2,
&(mode->interconnect[i].annotations[k]), nullptr, loc_data);
/* get next iteration */
k++;
Cur2 = Cur2.next_sibling(Cur2.name());
}
}
VTR_ASSERT(k == num_annotations);
/* Power */
mode->interconnect[i].interconnect_power = (t_interconnect_power*)vtr::calloc(1,
sizeof(t_interconnect_power));
mode->interconnect[i].interconnect_power->port_info_initialized = false;
/* get next iteration */
Cur = Cur.next_sibling(Cur.name());
i++;
}
}
interc_names.clear();
VTR_ASSERT(i == num_interconnect);
}
static void ProcessMode(vtr::string_internment* strings, pugi::xml_node Parent, t_mode* mode, const bool timing_enabled, const t_arch& arch, const pugiutil::loc_data& loc_data) {
int i;
const char* Prop;
pugi::xml_node Cur;
std::map<std::string, int> pb_type_names;
std::pair<std::map<std::string, int>::iterator, bool> ret_pb_types;
bool implied_mode = 0 == strcmp(Parent.name(), "pb_type");
if (implied_mode) {
mode->name = vtr::strdup("default");
} else {
Prop = get_attribute(Parent, "name", loc_data).value();
mode->name = vtr::strdup(Prop);
}
mode->num_pb_type_children = count_children(Parent, "pb_type", loc_data, ReqOpt::OPTIONAL);
if (mode->num_pb_type_children > 0) {
mode->pb_type_children = new t_pb_type[mode->num_pb_type_children];
i = 0;
Cur = get_first_child(Parent, "pb_type", loc_data);
while (Cur != nullptr) {
if (0 == strcmp(Cur.name(), "pb_type")) {
ProcessPb_Type(strings, Cur, &mode->pb_type_children[i], mode, timing_enabled, arch, loc_data);
ret_pb_types = pb_type_names.insert(
std::pair<std::string, int>(mode->pb_type_children[i].name, 0));
if (!ret_pb_types.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Duplicate pb_type name: '%s' in mode: '%s'.\n",
mode->pb_type_children[i].name, mode->name);
}
/* get next iteration */
i++;
Cur = Cur.next_sibling(Cur.name());
}
}
} else {
mode->pb_type_children = nullptr;
}
/* Allocate power structure */
mode->mode_power = (t_mode_power*)vtr::calloc(1, sizeof(t_mode_power));
if (!implied_mode) {
// Implied mode metadata is attached to the pb_type, rather than
// the t_mode object.
mode->meta = ProcessMetadata(strings, Parent, loc_data);
}
/* Clear STL map used for duplicate checks */
pb_type_names.clear();
Cur = get_single_child(Parent, "interconnect", loc_data);
ProcessInterconnect(strings, Cur, mode, loc_data);
}
static t_metadata_dict ProcessMetadata(vtr::string_internment* strings, pugi::xml_node Parent, const pugiutil::loc_data& loc_data) {
// <metadata>
// <meta>CLBLL_L_</meta>
// </metadata>
t_metadata_dict data;
auto metadata = get_single_child(Parent, "metadata", loc_data, ReqOpt::OPTIONAL);
if (metadata) {
auto meta_tag = get_first_child(metadata, "meta", loc_data);
while (meta_tag) {
auto key = get_attribute(meta_tag, "name", loc_data).as_string();
auto value = meta_tag.child_value();
data.add(strings->intern_string(vtr::string_view(key)),
strings->intern_string(vtr::string_view(value)));
meta_tag = meta_tag.next_sibling(meta_tag.name());
}
}
return data;
}
static void Process_Fc_Values(pugi::xml_node Node, t_default_fc_spec& spec, const pugiutil::loc_data& loc_data) {
spec.specified = true;
/* Load the default fc_in */
auto default_fc_in_attrib = get_attribute(Node, "in_type", loc_data);
spec.in_value_type = string_to_fc_value_type(default_fc_in_attrib.value(), Node, loc_data);
auto in_val_attrib = get_attribute(Node, "in_val", loc_data);
spec.in_value = vtr::atof(in_val_attrib.value());
/* Load the default fc_out */
auto default_fc_out_attrib = get_attribute(Node, "out_type", loc_data);
spec.out_value_type = string_to_fc_value_type(default_fc_out_attrib.value(), Node, loc_data);
auto out_val_attrib = get_attribute(Node, "out_val", loc_data);
spec.out_value = vtr::atof(out_val_attrib.value());
}
/* Takes in the node ptr for the 'fc' elements and initializes
* the appropriate fields of type. */
static void Process_Fc(pugi::xml_node Node,
t_physical_tile_type* PhysicalTileType,
t_sub_tile* SubTile,
t_pin_counts pin_counts,
std::vector<t_segment_inf>& segments,
const t_default_fc_spec& arch_def_fc,
const pugiutil::loc_data& loc_data) {
std::vector<t_fc_override> fc_overrides;
t_default_fc_spec def_fc_spec;
if (Node) {
/* Load the default Fc values from the node */
Process_Fc_Values(Node, def_fc_spec, loc_data);
/* Load any <fc_override/> tags */
for (auto child_node : Node.children()) {
t_fc_override fc_override = Process_Fc_override(child_node, loc_data);
fc_overrides.push_back(fc_override);
}
} else {
/* Use the default value, if available */
if (!arch_def_fc.specified) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"<sub_tile> is missing child <fc>, and no <default_fc> specified in architecture\n");
}
def_fc_spec = arch_def_fc;
}
/* Go through all the port/segment combinations and create the (potentially
* overriden) pin/seg Fc specifications */
for (size_t iseg = 0; iseg < segments.size(); ++iseg) {
for (int icapacity = 0; icapacity < SubTile->capacity.total(); ++icapacity) {
//If capacity > 0, we need t offset the block index by the number of pins per instance
//this ensures that all pins have an Fc specification
int iblk_pin = icapacity * pin_counts.total();
for (const auto& port : SubTile->ports) {
t_fc_specification fc_spec;
fc_spec.seg_index = iseg;
//Apply type and defaults
if (port.type == IN_PORT) {
fc_spec.fc_type = e_fc_type::IN;
fc_spec.fc_value_type = def_fc_spec.in_value_type;
fc_spec.fc_value = def_fc_spec.in_value;
} else {
VTR_ASSERT(port.type == OUT_PORT);
fc_spec.fc_type = e_fc_type::OUT;
fc_spec.fc_value_type = def_fc_spec.out_value_type;
fc_spec.fc_value = def_fc_spec.out_value;
}
//Apply any matching overrides
bool default_overriden = false;
for (const auto& fc_override : fc_overrides) {
bool apply_override = false;
if (!fc_override.port_name.empty() && !fc_override.seg_name.empty()) {
//Both port and seg names are specified require exact match on both
if (fc_override.port_name == port.name && fc_override.seg_name == segments[iseg].name) {
apply_override = true;
}
} else if (!fc_override.port_name.empty()) {
VTR_ASSERT(fc_override.seg_name.empty());
//Only the port name specified, require it to match
if (fc_override.port_name == port.name) {
apply_override = true;
}
} else {
VTR_ASSERT(!fc_override.seg_name.empty());
VTR_ASSERT(fc_override.port_name.empty());
//Only the seg name specified, require it to match
if (fc_override.seg_name == segments[iseg].name) {
apply_override = true;
}
}
if (apply_override) {
//Exact match, or partial match to either port or seg name
// Note that we continue searching, this ensures that the last matching override (in file order)
// is applied last
if (default_overriden) {
//Warn if multiple overrides match
VTR_LOGF_WARN(loc_data.filename_c_str(), loc_data.line(Node), "Multiple matching Fc overrides found; the last will be applied\n");
}
fc_spec.fc_value_type = fc_override.fc_value_type;
fc_spec.fc_value = fc_override.fc_value;
default_overriden = true;
}
}
//Add all the pins from this port
for (int iport_pin = 0; iport_pin < port.num_pins; ++iport_pin) {
//XXX: this assumes that iterating through the tile ports
// in order yields the block pin order
int true_physical_blk_pin = SubTile->sub_tile_to_tile_pin_indices[iblk_pin];
fc_spec.pins.push_back(true_physical_blk_pin);
++iblk_pin;
}
PhysicalTileType->fc_specs.push_back(fc_spec);
}
}
}
}
static t_fc_override Process_Fc_override(pugi::xml_node node, const pugiutil::loc_data& loc_data) {
if (node.name() != std::string("fc_override")) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(node),
"Unexpeted node of type '%s' (expected optional 'fc_override')",
node.name());
}
t_fc_override fc_override;
expect_child_node_count(node, 0, loc_data);
bool seen_fc_type = false;
bool seen_fc_value = false;
bool seen_port_or_seg = false;
for (auto attrib : node.attributes()) {
if (attrib.name() == std::string("port_name")) {
fc_override.port_name = attrib.value();
seen_port_or_seg |= true;
} else if (attrib.name() == std::string("segment_name")) {
fc_override.seg_name = attrib.value();
seen_port_or_seg |= true;
} else if (attrib.name() == std::string("fc_type")) {
fc_override.fc_value_type = string_to_fc_value_type(attrib.value(), node, loc_data);
seen_fc_type = true;
} else if (attrib.name() == std::string("fc_val")) {
fc_override.fc_value = vtr::atof(attrib.value());
seen_fc_value = true;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(node),
"Unexpected attribute '%s'", attrib.name());
}
}
if (!seen_fc_type) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(node),
"Missing expected attribute 'fc_type'");
}
if (!seen_fc_value) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(node),
"Missing expected attribute 'fc_value'");
}
if (!seen_port_or_seg) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(node),
"Missing expected attribute(s) 'port_name' and/or 'segment_name'");
}
return fc_override;
}
static e_fc_value_type string_to_fc_value_type(const std::string& str, pugi::xml_node node, const pugiutil::loc_data& loc_data) {
e_fc_value_type fc_value_type = e_fc_value_type::FRACTIONAL;
if (str == "frac") {
fc_value_type = e_fc_value_type::FRACTIONAL;
} else if (str == "abs") {
fc_value_type = e_fc_value_type::ABSOLUTE;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(node),
"Invalid fc_type '%s'. Must be 'abs' or 'frac'.\n",
str.c_str());
}
return fc_value_type;
}
//Process any custom switchblock locations
static void ProcessSwitchblockLocations(pugi::xml_node switchblock_locations,
t_physical_tile_type* type,
const t_arch& arch,
const pugiutil::loc_data& loc_data) {
VTR_ASSERT(type);
expect_only_attributes(switchblock_locations, {"pattern", "internal_switch"}, loc_data);
std::string pattern = get_attribute(switchblock_locations, "pattern", loc_data, ReqOpt::OPTIONAL).as_string("external_full_internal_straight");
//Initialize the location specs
size_t width = type->width;
size_t height = type->height;
type->switchblock_locations = vtr::Matrix<e_sb_type>({{width, height}}, e_sb_type::NONE);
type->switchblock_switch_overrides = vtr::Matrix<int>({{width, height}}, DEFAULT_SWITCH);
if (pattern == "custom") {
expect_only_attributes(switchblock_locations, {"pattern"}, loc_data);
//Load a custom pattern specified with <sb_loc> tags
expect_only_children(switchblock_locations, {"sb_loc"}, loc_data); //Only sb_loc child tags
//Default to no SBs unless specified
type->switchblock_locations.fill(e_sb_type::NONE);
//Track which locations have been assigned to detect overlaps
auto assigned_locs = vtr::Matrix<bool>({{width, height}}, false);
for (pugi::xml_node sb_loc : switchblock_locations.children("sb_loc")) {
expect_only_attributes(sb_loc, {"type", "xoffset", "yoffset", "switch_override"}, loc_data);
//Determine the type
std::string sb_type_str = get_attribute(sb_loc, "type", loc_data, ReqOpt::OPTIONAL).as_string("full");
e_sb_type sb_type = e_sb_type::FULL;
if (sb_type_str == "none") {
sb_type = e_sb_type::NONE;
} else if (sb_type_str == "horizontal") {
sb_type = e_sb_type::HORIZONTAL;
} else if (sb_type_str == "vertical") {
sb_type = e_sb_type::VERTICAL;
} else if (sb_type_str == "turns") {
sb_type = e_sb_type::TURNS;
} else if (sb_type_str == "straight") {
sb_type = e_sb_type::STRAIGHT;
} else if (sb_type_str == "full") {
sb_type = e_sb_type::FULL;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(sb_loc),
"Invalid <sb_loc> 'type' attribute '%s'\n",
sb_type_str.c_str());
}
//Determine the switch type
int sb_switch_override = DEFAULT_SWITCH;
auto sb_switch_override_attr = get_attribute(sb_loc, "switch_override", loc_data, ReqOpt::OPTIONAL);
if (sb_switch_override_attr) {
std::string sb_switch_override_str = sb_switch_override_attr.as_string();
//Use the specified switch
sb_switch_override = find_switch_by_name(arch, sb_switch_override_str);
if (sb_switch_override == OPEN) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(switchblock_locations),
"Invalid <sb_loc> 'switch_override' attribute '%s' (no matching switch named '%s' found)\n",
sb_switch_override_str.c_str(), sb_switch_override_str.c_str());
}
}
//Get the horizontal offset
size_t xoffset = get_attribute(sb_loc, "xoffset", loc_data, ReqOpt::OPTIONAL).as_uint(0);
if (xoffset > width - 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(sb_loc),
"Invalid <sb_loc> 'xoffset' attribute '%zu' (must be in range [%d,%d])\n",
xoffset, 0, width - 1);
}
//Get the vertical offset
size_t yoffset = get_attribute(sb_loc, "yoffset", loc_data, ReqOpt::OPTIONAL).as_uint(0);
if (yoffset > height - 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(sb_loc),
"Invalid <sb_loc> 'yoffset' attribute '%zu' (must be in range [%d,%d])\n",
yoffset, 0, height - 1);
}
//Check if this location has already been set
if (assigned_locs[xoffset][yoffset]) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(sb_loc),
"Duplicate <sb_loc> specifications at xoffset=%zu yoffset=%zu\n",
xoffset, yoffset);
}
//Set the custom sb location and type
type->switchblock_locations[xoffset][yoffset] = sb_type;
type->switchblock_switch_overrides[xoffset][yoffset] = sb_switch_override;
assigned_locs[xoffset][yoffset] = true; //Mark the location as set for error detection
}
} else { //Non-custom patterns
//Initialize defaults
int internal_switch = DEFAULT_SWITCH;
int external_switch = DEFAULT_SWITCH;
e_sb_type internal_type = e_sb_type::FULL;
e_sb_type external_type = e_sb_type::FULL;
//Determine any internal switch override
auto internal_switch_attr = get_attribute(switchblock_locations, "internal_switch", loc_data, ReqOpt::OPTIONAL);
if (internal_switch_attr) {
std::string internal_switch_name = internal_switch_attr.as_string();
//Use the specified switch
internal_switch = find_switch_by_name(arch, internal_switch_name);
if (internal_switch == OPEN) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(switchblock_locations),
"Invalid <switchblock_locations> 'internal_switch' attribute '%s' (no matching switch named '%s' found)\n",
internal_switch_name.c_str(), internal_switch_name.c_str());
}
}
//Identify switch block types
if (pattern == "all") {
internal_type = e_sb_type::FULL;
external_type = e_sb_type::FULL;
} else if (pattern == "external") {
internal_type = e_sb_type::NONE;
external_type = e_sb_type::FULL;
} else if (pattern == "internal") {
internal_type = e_sb_type::FULL;
external_type = e_sb_type::NONE;
} else if (pattern == "external_full_internal_straight") {
internal_type = e_sb_type::STRAIGHT;
external_type = e_sb_type::FULL;
} else if (pattern == "none") {
internal_type = e_sb_type::NONE;
external_type = e_sb_type::NONE;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(switchblock_locations),
"Invalid <switchblock_locations> 'pattern' attribute '%s'\n",
pattern.c_str());
}
//Fill in all locations (sets internal)
type->switchblock_locations.fill(internal_type);
type->switchblock_switch_overrides.fill(internal_switch);
//Fill in top edge external
size_t yoffset = height - 1;
for (size_t xoffset = 0; xoffset < width; ++xoffset) {
type->switchblock_locations[xoffset][yoffset] = external_type;
type->switchblock_switch_overrides[xoffset][yoffset] = external_switch;
}
//Fill in right edge external
size_t xoffset = width - 1;
for (yoffset = 0; yoffset < height; ++yoffset) {
type->switchblock_locations[xoffset][yoffset] = external_type;
type->switchblock_switch_overrides[xoffset][yoffset] = external_switch;
}
}
}
/* Takes in node pointing to <models> and loads all the
* child type objects. */
static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data) {
pugi::xml_node p;
t_model* temp = nullptr;
int L_index;
/* std::maps for checking duplicates */
std::map<std::string, int> model_name_map;
std::pair<std::map<std::string, int>::iterator, bool> ret_map_name;
L_index = NUM_MODELS_IN_LIBRARY;
arch->models = nullptr;
for (pugi::xml_node model : Node.children()) {
//Process each model
if (model.name() != std::string("model")) {
bad_tag(model, loc_data, Node, {"model"});
}
try {
temp = new t_model;
temp->index = L_index;
L_index++;
//Process the <model> tag attributes
for (pugi::xml_attribute attr : model.attributes()) {
if (attr.name() != std::string("name")) {
bad_attribute(attr, model, loc_data);
} else {
VTR_ASSERT(attr.name() == std::string("name"));
if (!temp->name) {
//First name attr. seen
temp->name = vtr::strdup(attr.value());
} else {
//Duplicate name
archfpga_throw(loc_data.filename_c_str(), loc_data.line(model),
"Duplicate 'name' attribute on <model> tag.");
}
}
}
/* Try insert new model, check if already exist at the same time */
ret_map_name = model_name_map.insert(std::pair<std::string, int>(temp->name, 0));
if (!ret_map_name.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(model),
"Duplicate model name: '%s'.\n", temp->name);
}
//Process the ports
std::set<std::string> port_names;
for (pugi::xml_node port_group : model.children()) {
if (port_group.name() == std::string("input_ports")) {
ProcessModelPorts(port_group, temp, port_names, loc_data);
} else if (port_group.name() == std::string("output_ports")) {
ProcessModelPorts(port_group, temp, port_names, loc_data);
} else {
bad_tag(port_group, loc_data, model, {"input_ports", "output_ports"});
}
}
//Sanity check the model
check_model_clocks(model, loc_data, temp);
check_model_combinational_sinks(model, loc_data, temp);
warn_model_missing_timing(model, loc_data, temp);
} catch (ArchFpgaError& e) {
free_arch_model(temp);
throw;
}
//Add the model
temp->next = arch->models;
arch->models = temp;
}
return;
}
static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::set<std::string>& port_names, const pugiutil::loc_data& loc_data) {
for (pugi::xml_attribute attr : port_group.attributes()) {
bad_attribute(attr, port_group, loc_data);
}
enum PORTS dir = ERR_PORT;
if (port_group.name() == std::string("input_ports")) {
dir = IN_PORT;
} else {
VTR_ASSERT(port_group.name() == std::string("output_ports"));
dir = OUT_PORT;
}
//Process each port
for (pugi::xml_node port : port_group.children()) {
//Should only be ports
if (port.name() != std::string("port")) {
bad_tag(port, loc_data, port_group, {"port"});
}
//Ports should have no children
for (pugi::xml_node port_child : port.children()) {
bad_tag(port_child, loc_data, port);
}
t_model_ports* model_port = new t_model_ports;
model_port->dir = dir;
//Process the attributes of each port
for (pugi::xml_attribute attr : port.attributes()) {
if (attr.name() == std::string("name")) {
model_port->name = vtr::strdup(attr.value());
} else if (attr.name() == std::string("is_clock")) {
model_port->is_clock = attribute_to_bool(port, attr, loc_data);
} else if (attr.name() == std::string("is_non_clock_global")) {
model_port->is_non_clock_global = attribute_to_bool(port, attr, loc_data);
} else if (attr.name() == std::string("clock")) {
model_port->clock = std::string(attr.value());
} else if (attr.name() == std::string("combinational_sink_ports")) {
model_port->combinational_sink_ports = vtr::split(attr.value());
} else {
bad_attribute(attr, port, loc_data);
}
}
//Sanity checks
if (model_port->is_clock == true && model_port->is_non_clock_global == true) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(port),
"Model port '%s' cannot be both a clock and a non-clock signal simultaneously", model_port->name);
}
if (model_port->name == nullptr) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(port),
"Model port is missing a name");
}
if (port_names.count(model_port->name)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(port),
"Duplicate model port named '%s'", model_port->name);
}
if (dir == OUT_PORT && !model_port->combinational_sink_ports.empty()) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(port),
"Model output ports can not have combinational sink ports");
}
//Add the port
if (dir == IN_PORT) {
model_port->next = model->inputs;
model->inputs = model_port;
} else {
VTR_ASSERT(dir == OUT_PORT);
model_port->next = model->outputs;
model->outputs = model_port;
}
}
}
static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiutil::loc_data& loc_data) {
VTR_ASSERT(layout_tag.name() == std::string("layout"));
//Expect no attributes on <layout>
expect_only_attributes(layout_tag, {}, loc_data);
//Count the number of <auto_layout> or <fixed_layout> tags
size_t auto_layout_cnt = 0;
size_t fixed_layout_cnt = 0;
for (auto layout_type_tag : layout_tag.children()) {
if (layout_type_tag.name() == std::string("auto_layout")) {
++auto_layout_cnt;
} else if (layout_type_tag.name() == std::string("fixed_layout")) {
++fixed_layout_cnt;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag),
"Unexpected tag type '<%s>', expected '<auto_layout>' or '<fixed_layout>'", layout_type_tag.name());
}
}
if (auto_layout_cnt == 0 && fixed_layout_cnt == 0) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_tag),
"Expected either an <auto_layout> or <fixed_layout> tag");
}
if (auto_layout_cnt > 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_tag),
"Expected at most one <auto_layout> tag");
}
VTR_ASSERT_MSG(auto_layout_cnt == 0 || auto_layout_cnt == 1, "<auto_layout> may appear at most once");
for (auto layout_type_tag : layout_tag.children()) {
t_grid_def grid_def = ProcessGridLayout(&arch->strings, layout_type_tag, loc_data);
arch->grid_layouts.emplace_back(std::move(grid_def));
}
}
static t_grid_def ProcessGridLayout(vtr::string_internment* strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data) {
t_grid_def grid_def;
//Determine the grid specification type
if (layout_type_tag.name() == std::string("auto_layout")) {
expect_only_attributes(layout_type_tag, {"aspect_ratio"}, loc_data);
grid_def.grid_type = GridDefType::AUTO;
grid_def.aspect_ratio = get_attribute(layout_type_tag, "aspect_ratio", loc_data, ReqOpt::OPTIONAL).as_float(1.);
grid_def.name = "auto";
} else if (layout_type_tag.name() == std::string("fixed_layout")) {
expect_only_attributes(layout_type_tag, {"width", "height", "name"}, loc_data);
grid_def.grid_type = GridDefType::FIXED;
grid_def.width = get_attribute(layout_type_tag, "width", loc_data).as_int();
grid_def.height = get_attribute(layout_type_tag, "height", loc_data).as_int();
std::string name = get_attribute(layout_type_tag, "name", loc_data).value();
if (name == "auto") {
//We name <auto_layout> as 'auto', so don't allow a user to specify it
archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag),
"The name '%s' is reserved for auto-sized layouts; please choose another name");
}
grid_def.name = name;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag),
"Unexpected tag '<%s>'. Expected '<auto_layout>' or '<fixed_layout>'.",
layout_type_tag.name());
}
//Process all the block location specifications
for (auto loc_spec_tag : layout_type_tag.children()) {
auto loc_type = loc_spec_tag.name();
auto type_name = get_attribute(loc_spec_tag, "type", loc_data).value();
int priority = get_attribute(loc_spec_tag, "priority", loc_data).as_int();
t_metadata_dict meta = ProcessMetadata(strings, loc_spec_tag, loc_data);
if (loc_type == std::string("perimeter")) {
expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data);
//The edges
t_grid_loc_def left_edge(type_name, priority); //Including corners
left_edge.x.start_expr = "0";
left_edge.x.end_expr = "0";
left_edge.y.start_expr = "0";
left_edge.y.end_expr = "H - 1";
t_grid_loc_def right_edge(type_name, priority); //Including corners
right_edge.x.start_expr = "W - 1";
right_edge.x.end_expr = "W - 1";
right_edge.y.start_expr = "0";
right_edge.y.end_expr = "H - 1";
t_grid_loc_def bottom_edge(type_name, priority); //Exclucing corners
bottom_edge.x.start_expr = "1";
bottom_edge.x.end_expr = "W - 2";
bottom_edge.y.start_expr = "0";
bottom_edge.y.end_expr = "0";
t_grid_loc_def top_edge(type_name, priority); //Excluding corners
top_edge.x.start_expr = "1";
top_edge.x.end_expr = "W - 2";
top_edge.y.start_expr = "H - 1";
top_edge.y.end_expr = "H - 1";
left_edge.owned_meta = std::make_unique<t_metadata_dict>(meta);
left_edge.meta = left_edge.owned_meta.get();
right_edge.meta = left_edge.owned_meta.get();
top_edge.meta = left_edge.owned_meta.get();
bottom_edge.meta = left_edge.owned_meta.get();
grid_def.loc_defs.emplace_back(std::move(left_edge));
grid_def.loc_defs.emplace_back(std::move(right_edge));
grid_def.loc_defs.emplace_back(std::move(top_edge));
grid_def.loc_defs.emplace_back(std::move(bottom_edge));
} else if (loc_type == std::string("corners")) {
expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data);
//The corners
t_grid_loc_def bottom_left(type_name, priority);
bottom_left.x.start_expr = "0";
bottom_left.x.end_expr = "0";
bottom_left.y.start_expr = "0";
bottom_left.y.end_expr = "0";
t_grid_loc_def top_left(type_name, priority);
top_left.x.start_expr = "0";
top_left.x.end_expr = "0";
top_left.y.start_expr = "H-1";
top_left.y.end_expr = "H-1";
t_grid_loc_def bottom_right(type_name, priority);
bottom_right.x.start_expr = "W-1";
bottom_right.x.end_expr = "W-1";
bottom_right.y.start_expr = "0";
bottom_right.y.end_expr = "0";
t_grid_loc_def top_right(type_name, priority);
top_right.x.start_expr = "W-1";
top_right.x.end_expr = "W-1";
top_right.y.start_expr = "H-1";
top_right.y.end_expr = "H-1";
bottom_left.owned_meta = std::make_unique<t_metadata_dict>(meta);
bottom_left.meta = bottom_left.owned_meta.get();
top_left.meta = bottom_left.owned_meta.get();
bottom_right.meta = bottom_left.owned_meta.get();
top_right.meta = bottom_left.owned_meta.get();
grid_def.loc_defs.emplace_back(std::move(bottom_left));
grid_def.loc_defs.emplace_back(std::move(top_left));
grid_def.loc_defs.emplace_back(std::move(bottom_right));
grid_def.loc_defs.emplace_back(std::move(top_right));
} else if (loc_type == std::string("fill")) {
expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data);
t_grid_loc_def fill(type_name, priority);
fill.x.start_expr = "0";
fill.x.end_expr = "W - 1";
fill.y.start_expr = "0";
fill.y.end_expr = "H - 1";
fill.owned_meta = std::make_unique<t_metadata_dict>(meta);
fill.meta = fill.owned_meta.get();
grid_def.loc_defs.emplace_back(std::move(fill));
} else if (loc_type == std::string("single")) {
expect_only_attributes(loc_spec_tag, {"type", "priority", "x", "y"}, loc_data);
t_grid_loc_def single(type_name, priority);
single.x.start_expr = get_attribute(loc_spec_tag, "x", loc_data).value();
single.y.start_expr = get_attribute(loc_spec_tag, "y", loc_data).value();
single.x.end_expr = single.x.start_expr + " + w - 1";
single.y.end_expr = single.y.start_expr + " + h - 1";
single.owned_meta = std::make_unique<t_metadata_dict>(meta);
single.meta = single.owned_meta.get();
grid_def.loc_defs.emplace_back(std::move(single));
} else if (loc_type == std::string("col")) {
expect_only_attributes(loc_spec_tag, {"type", "priority", "startx", "repeatx", "starty", "incry"}, loc_data);
t_grid_loc_def col(type_name, priority);
auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data);
col.x.start_expr = startx_attr.value();
col.x.end_expr = startx_attr.value() + std::string(" + w - 1"); //end is inclusive so need to include block width
auto repeat_attr = get_attribute(loc_spec_tag, "repeatx", loc_data, ReqOpt::OPTIONAL);
if (repeat_attr) {
col.x.repeat_expr = repeat_attr.value();
}
auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data, ReqOpt::OPTIONAL);
if (starty_attr) {
col.y.start_expr = starty_attr.value();
}
auto incry_attr = get_attribute(loc_spec_tag, "incry", loc_data, ReqOpt::OPTIONAL);
if (incry_attr) {
col.y.incr_expr = incry_attr.value();
}
col.owned_meta = std::make_unique<t_metadata_dict>(meta);
col.meta = col.owned_meta.get();
grid_def.loc_defs.emplace_back(std::move(col));
} else if (loc_type == std::string("row")) {
expect_only_attributes(loc_spec_tag, {"type", "priority", "starty", "repeaty", "startx", "incrx"}, loc_data);
t_grid_loc_def row(type_name, priority);
auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data);
row.y.start_expr = starty_attr.value();
row.y.end_expr = starty_attr.value() + std::string(" + h - 1"); //end is inclusive so need to include block height
auto repeat_attr = get_attribute(loc_spec_tag, "repeaty", loc_data, ReqOpt::OPTIONAL);
if (repeat_attr) {
row.y.repeat_expr = repeat_attr.value();
}
auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data, ReqOpt::OPTIONAL);
if (startx_attr) {
row.x.start_expr = startx_attr.value();
}
auto incrx_attr = get_attribute(loc_spec_tag, "incrx", loc_data, ReqOpt::OPTIONAL);
if (incrx_attr) {
row.x.incr_expr = incrx_attr.value();
}
row.owned_meta = std::make_unique<t_metadata_dict>(meta);
row.meta = row.owned_meta.get();
grid_def.loc_defs.emplace_back(std::move(row));
} else if (loc_type == std::string("region")) {
expect_only_attributes(loc_spec_tag,
{"type", "priority",
"startx", "endx", "repeatx", "incrx",
"starty", "endy", "repeaty", "incry"},
loc_data);
t_grid_loc_def region(type_name, priority);
auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data, ReqOpt::OPTIONAL);
if (startx_attr) {
region.x.start_expr = startx_attr.value();
}
auto endx_attr = get_attribute(loc_spec_tag, "endx", loc_data, ReqOpt::OPTIONAL);
if (endx_attr) {
region.x.end_expr = endx_attr.value();
}
auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data, ReqOpt::OPTIONAL);
if (starty_attr) {
region.y.start_expr = starty_attr.value();
}
auto endy_attr = get_attribute(loc_spec_tag, "endy", loc_data, ReqOpt::OPTIONAL);
if (endy_attr) {
region.y.end_expr = endy_attr.value();
}
auto repeatx_attr = get_attribute(loc_spec_tag, "repeatx", loc_data, ReqOpt::OPTIONAL);
if (repeatx_attr) {
region.x.repeat_expr = repeatx_attr.value();
}
auto repeaty_attr = get_attribute(loc_spec_tag, "repeaty", loc_data, ReqOpt::OPTIONAL);
if (repeaty_attr) {
region.y.repeat_expr = repeaty_attr.value();
}
auto incrx_attr = get_attribute(loc_spec_tag, "incrx", loc_data, ReqOpt::OPTIONAL);
if (incrx_attr) {
region.x.incr_expr = incrx_attr.value();
}
auto incry_attr = get_attribute(loc_spec_tag, "incry", loc_data, ReqOpt::OPTIONAL);
if (incry_attr) {
region.y.incr_expr = incry_attr.value();
}
region.owned_meta = std::make_unique<t_metadata_dict>(meta);
region.meta = region.owned_meta.get();
grid_def.loc_defs.emplace_back(std::move(region));
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(loc_spec_tag),
"Unrecognized grid location specification type '%s'\n", loc_type);
}
}
//Warn if any type has no grid location specifed
return grid_def;
}
/* Takes in node pointing to <device> and loads all the
* child type objects. */
static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data) {
const char* Prop;
pugi::xml_node Cur;
bool custom_switch_block = false;
//Warn that <timing> is no longer supported
//TODO: eventually remove
try {
expect_child_node_count(Node, "timing", 0, loc_data);
} catch (pugiutil::XmlError& e) {
std::string msg = e.what();
msg += ". <timing> has been replaced with the <switch_block> tag.";
msg += " Please upgrade your architecture file.";
archfpga_throw(e.filename().c_str(), e.line(), msg.c_str());
}
expect_only_children(Node, {"sizing", "area", "chan_width_distr", "switch_block", "connection_block", "default_fc"}, loc_data);
//<sizing> tag
Cur = get_single_child(Node, "sizing", loc_data);
expect_only_attributes(Cur, {"R_minW_nmos", "R_minW_pmos"}, loc_data);
arch->R_minW_nmos = get_attribute(Cur, "R_minW_nmos", loc_data).as_float();
arch->R_minW_pmos = get_attribute(Cur, "R_minW_pmos", loc_data).as_float();
//<area> tag
Cur = get_single_child(Node, "area", loc_data);
expect_only_attributes(Cur, {"grid_logic_tile_area"}, loc_data);
arch->grid_logic_tile_area = get_attribute(Cur, "grid_logic_tile_area",
loc_data, ReqOpt::OPTIONAL)
.as_float(0);
//<chan_width_distr> tag
Cur = get_single_child(Node, "chan_width_distr", loc_data, ReqOpt::OPTIONAL);
expect_only_attributes(Cur, {}, loc_data);
if (Cur != nullptr) {
ProcessChanWidthDistr(Cur, arch, loc_data);
}
//<connection_block> tag
Cur = get_single_child(Node, "connection_block", loc_data);
expect_only_attributes(Cur, {"input_switch_name"}, loc_data);
arch->ipin_cblock_switch_name = get_attribute(Cur, "input_switch_name", loc_data).as_string();
//<switch_block> tag
Cur = get_single_child(Node, "switch_block", loc_data);
expect_only_attributes(Cur, {"type", "fs"}, loc_data);
Prop = get_attribute(Cur, "type", loc_data).value();
if (strcmp(Prop, "wilton") == 0) {
arch->SBType = WILTON;
} else if (strcmp(Prop, "universal") == 0) {
arch->SBType = UNIVERSAL;
} else if (strcmp(Prop, "subset") == 0) {
arch->SBType = SUBSET;
} else if (strcmp(Prop, "custom") == 0) {
arch->SBType = CUSTOM;
custom_switch_block = true;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Unknown property %s for switch block type x\n", Prop);
}
ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block);
arch->Fs = get_attribute(Cur, "fs", loc_data, CUSTOM_SWITCHBLOCK_REQD).as_int(3);
Cur = get_single_child(Node, "default_fc", loc_data, ReqOpt::OPTIONAL);
if (Cur) {
arch_def_fc.specified = true;
expect_only_attributes(Cur, {"in_type", "in_val", "out_type", "out_val"}, loc_data);
Process_Fc_Values(Cur, arch_def_fc, loc_data);
} else {
arch_def_fc.specified = false;
}
}
/* Takes in node pointing to <chan_width_distr> and loads all the
* child type objects. */
static void ProcessChanWidthDistr(pugi::xml_node Node,
t_arch* arch,
const pugiutil::loc_data& loc_data) {
pugi::xml_node Cur;
expect_only_children(Node, {"x", "y"}, loc_data);
Cur = get_single_child(Node, "x", loc_data);
ProcessChanWidthDistrDir(Cur, &arch->Chans.chan_x_dist, loc_data);
Cur = get_single_child(Node, "y", loc_data);
ProcessChanWidthDistrDir(Cur, &arch->Chans.chan_y_dist, loc_data);
}
/* Takes in node within <chan_width_distr> and loads all the
* child type objects. */
static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pugiutil::loc_data& loc_data) {
const char* Prop;
ReqOpt hasXpeak, hasWidth, hasDc;
hasXpeak = hasWidth = hasDc = ReqOpt::OPTIONAL;
Prop = get_attribute(Node, "distr", loc_data).value();
if (strcmp(Prop, "uniform") == 0) {
chan->type = UNIFORM;
} else if (strcmp(Prop, "gaussian") == 0) {
chan->type = GAUSSIAN;
hasXpeak = hasWidth = hasDc = ReqOpt::REQUIRED;
} else if (strcmp(Prop, "pulse") == 0) {
chan->type = PULSE;
hasXpeak = hasWidth = hasDc = ReqOpt::REQUIRED;
} else if (strcmp(Prop, "delta") == 0) {
hasXpeak = hasDc = ReqOpt::REQUIRED;
chan->type = DELTA;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Unknown property %s for chan_width_distr x\n", Prop);
}
chan->peak = get_attribute(Node, "peak", loc_data).as_float(UNDEFINED);
chan->width = get_attribute(Node, "width", loc_data, hasWidth).as_float(0);
chan->xpeak = get_attribute(Node, "xpeak", loc_data, hasXpeak).as_float(0);
chan->dc = get_attribute(Node, "dc", loc_data, hasDc).as_float(0);
}
static void ProcessTiles(pugi::xml_node Node,
std::vector<t_physical_tile_type>& PhysicalTileTypes,
std::vector<t_logical_block_type>& LogicalBlockTypes,
const t_default_fc_spec& arch_def_fc,
t_arch& arch,
const pugiutil::loc_data& loc_data) {
pugi::xml_node CurTileType;
pugi::xml_node Cur;
std::map<std::string, int> tile_type_descriptors;
/* Alloc the type list. Need one additional t_type_desctiptors:
* 1: empty psuedo-type
*/
t_physical_tile_type EMPTY_PHYSICAL_TILE_TYPE = SetupEmptyPhysicalType();
EMPTY_PHYSICAL_TILE_TYPE.index = 0;
PhysicalTileTypes.push_back(EMPTY_PHYSICAL_TILE_TYPE);
/* Process the types */
int index = 1; /* Skip over 'empty' type */
CurTileType = Node.first_child();
while (CurTileType) {
check_node(CurTileType, "tile", loc_data);
t_physical_tile_type PhysicalTileType;
PhysicalTileType.index = index;
/* Parses the properties fields of the type */
ProcessTileProps(CurTileType, &PhysicalTileType, loc_data);
auto result = tile_type_descriptors.insert(std::pair<std::string, int>(PhysicalTileType.name, 0));
if (!result.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(CurTileType),
"Duplicate tile descriptor name: '%s'.\n", PhysicalTileType.name);
}
//Warn that gridlocations is no longer supported
//TODO: eventually remove
try {
expect_child_node_count(CurTileType, "gridlocations", 0, loc_data);
} catch (pugiutil::XmlError& e) {
std::string msg = e.what();
msg += ". <gridlocations> has been replaced by the <auto_layout> and <device_layout> tags in the <layout> section.";
msg += " Please upgrade your architecture file.";
archfpga_throw(e.filename().c_str(), e.line(), msg.c_str());
}
//Load switchblock type and location overrides
Cur = get_single_child(CurTileType, "switchblock_locations", loc_data, ReqOpt::OPTIONAL);
ProcessSwitchblockLocations(Cur, &PhysicalTileType, arch, loc_data);
ProcessSubTiles(CurTileType, &PhysicalTileType, LogicalBlockTypes, arch.Segments, arch_def_fc, loc_data);
/* Type fully read */
++index;
/* Push newly created Types to corresponding vectors */
PhysicalTileTypes.push_back(PhysicalTileType);
/* Free this node and get its next sibling node */
CurTileType = CurTileType.next_sibling(CurTileType.name());
}
tile_type_descriptors.clear();
}
static void MarkIoTypes(std::vector<t_physical_tile_type>& PhysicalTileTypes) {
for (auto& type : PhysicalTileTypes) {
type.is_input_type = false;
type.is_output_type = false;
auto equivalent_sites = get_equivalent_sites_set(&type);
for (const auto& equivalent_site : equivalent_sites) {
if (block_type_contains_blif_model(equivalent_site, MODEL_INPUT)) {
type.is_input_type = true;
break;
}
}
for (const auto& equivalent_site : equivalent_sites) {
if (block_type_contains_blif_model(equivalent_site, MODEL_OUTPUT)) {
type.is_output_type = true;
break;
}
}
}
}
static void ProcessTileProps(pugi::xml_node Node,
t_physical_tile_type* PhysicalTileType,
const pugiutil::loc_data& loc_data) {
expect_only_attributes(Node, {"name", "width", "height", "area"}, loc_data);
/* Load type name */
auto Prop = get_attribute(Node, "name", loc_data).value();
PhysicalTileType->name = vtr::strdup(Prop);
/* Load properties */
PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1);
PhysicalTileType->height = get_attribute(Node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1);
PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED);
if (atof(Prop) < 0) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Area for type %s must be non-negative\n", PhysicalTileType->name);
}
}
static t_pin_counts ProcessSubTilePorts(pugi::xml_node Parent,
t_sub_tile* SubTile,
std::unordered_map<std::string, t_physical_tile_port>& tile_port_names,
const pugiutil::loc_data& loc_data) {
pugi::xml_node Cur;
std::map<std::string, int> sub_tile_port_names;
int num_ports, num_in_ports, num_out_ports, num_clock_ports;
num_ports = num_in_ports = num_out_ports = num_clock_ports = 0;
num_in_ports = count_children(Parent, "input", loc_data, ReqOpt::OPTIONAL);
num_out_ports = count_children(Parent, "output", loc_data, ReqOpt::OPTIONAL);
num_clock_ports = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL);
num_ports = num_in_ports + num_out_ports + num_clock_ports;
int port_index_by_type;
int port_index = 0;
int absolute_first_pin_index = 0;
std::vector<const char*> port_types = {"input", "output", "clock"};
for (auto port_type : port_types) {
port_index_by_type = 0;
Cur = get_first_child(Parent, port_type, loc_data, ReqOpt::OPTIONAL);
while (Cur) {
t_physical_tile_port port;
port.index = port_index;
port.absolute_first_pin_index = absolute_first_pin_index;
port.port_index_by_type = port_index_by_type;
ProcessTilePort(Cur, &port, loc_data);
//Check port name duplicates
auto sub_tile_port_result = sub_tile_port_names.insert(std::pair<std::string, int>(port.name, 0));
if (!sub_tile_port_result.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Duplicate port names in tile '%s': port '%s'\n",
SubTile->name, port.name);
}
//Check port name duplicates
auto tile_port_result = tile_port_names.insert(std::pair<std::string, t_physical_tile_port>(port.name, port));
if (!tile_port_result.second) {
if (tile_port_result.first->second.num_pins != port.num_pins || tile_port_result.first->second.equivalent != port.equivalent) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Another port found with the same name in other sub tiles "
"that did not match the current port settings. '%s': port '%s'\n",
SubTile->name, port.name);
}
}
//Push port
SubTile->ports.push_back(port);
/* get next iteration */
port_index++;
port_index_by_type++;
absolute_first_pin_index += port.num_pins;
Cur = Cur.next_sibling(Cur.name());
}
}
VTR_ASSERT(port_index == num_ports);
t_pin_counts pin_counts;
/* Count stats on the number of each type of pin */
for (const auto& port : SubTile->ports) {
if (port.type == IN_PORT && port.is_clock == false) {
pin_counts.input += port.num_pins;
} else if (port.type == OUT_PORT) {
pin_counts.output += port.num_pins;
} else {
VTR_ASSERT(port.is_clock && port.type == IN_PORT);
pin_counts.clock += port.num_pins;
}
}
return pin_counts;
}
static void ProcessTilePort(pugi::xml_node Node,
t_physical_tile_port* port,
const pugiutil::loc_data& loc_data) {
std::vector<std::string> expected_attributes = {"name", "num_pins", "equivalent"};
if (Node.name() == "input"s || Node.name() == "clock"s) {
expected_attributes.push_back("is_non_clock_global");
}
expect_only_attributes(Node, expected_attributes, loc_data);
const char* Prop;
Prop = get_attribute(Node, "name", loc_data).value();
port->name = vtr::strdup(Prop);
Prop = get_attribute(Node, "equivalent", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (Prop) {
if (Prop == "none"s) {
port->equivalent = PortEquivalence::NONE;
} else if (Prop == "full"s) {
port->equivalent = PortEquivalence::FULL;
} else if (Prop == "instance"s) {
if (Node.name() == "output"s) {
port->equivalent = PortEquivalence::INSTANCE;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Invalid pin equivalence '%s' for %s port.", Prop, Node.name());
}
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Invalid pin equivalence '%s'.", Prop);
}
}
port->num_pins = get_attribute(Node, "num_pins", loc_data).as_int(0);
port->is_non_clock_global = get_attribute(Node,
"is_non_clock_global", loc_data, ReqOpt::OPTIONAL)
.as_bool(false);
if (port->num_pins <= 0) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Invalid number of pins %d for %s port.", port->num_pins, Node.name());
}
if (0 == strcmp(Node.name(), "input")) {
port->type = IN_PORT;
port->is_clock = false;
} else if (0 == strcmp(Node.name(), "output")) {
port->type = OUT_PORT;
port->is_clock = false;
} else if (0 == strcmp(Node.name(), "clock")) {
port->type = IN_PORT;
port->is_clock = true;
if (port->is_non_clock_global == true) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Port %s cannot be both a clock and a non-clock simultaneously\n",
Node.name());
}
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Unknown port type %s", Node.name());
}
}
static void ProcessTileEquivalentSites(pugi::xml_node Parent,
t_sub_tile* SubTile,
t_physical_tile_type* PhysicalTileType,
std::vector<t_logical_block_type>& LogicalBlockTypes,
const pugiutil::loc_data& loc_data) {
pugi::xml_node CurSite;
expect_only_children(Parent, {"site"}, loc_data);
if (count_children(Parent, "site", loc_data) < 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"There are no sites corresponding to this tile: %s.\n", SubTile->name);
}
CurSite = Parent.first_child();
while (CurSite) {
check_node(CurSite, "site", loc_data);
expect_only_attributes(CurSite, {"pb_type", "pin_mapping"}, loc_data);
/* Load equivalent site name */
auto Prop = std::string(get_attribute(CurSite, "pb_type", loc_data).value());
auto LogicalBlockType = get_type_by_name<t_logical_block_type>(Prop.c_str(), LogicalBlockTypes);
auto pin_mapping = get_attribute(CurSite, "pin_mapping", loc_data, ReqOpt::OPTIONAL).as_string("direct");
if (0 == strcmp(pin_mapping, "custom")) {
// Pin mapping between Tile and Pb Type is user-defined
ProcessEquivalentSiteCustomConnection(CurSite, SubTile, PhysicalTileType, LogicalBlockType, Prop, loc_data);
} else if (0 == strcmp(pin_mapping, "direct")) {
ProcessEquivalentSiteDirectConnection(CurSite, SubTile, PhysicalTileType, LogicalBlockType, loc_data);
}
if (0 == strcmp(LogicalBlockType->pb_type->name, Prop.c_str())) {
SubTile->equivalent_sites.push_back(LogicalBlockType);
check_port_direct_mappings(PhysicalTileType, SubTile, LogicalBlockType);
}
CurSite = CurSite.next_sibling(CurSite.name());
}
}
static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent,
t_sub_tile* SubTile,
t_physical_tile_type* PhysicalTileType,
t_logical_block_type* LogicalBlockType,
const pugiutil::loc_data& loc_data) {
int num_pins = (int)SubTile->sub_tile_to_tile_pin_indices.size() / SubTile->capacity.total();
if (num_pins != LogicalBlockType->pb_type->num_pins) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", LogicalBlockType->pb_type->name, SubTile->name);
}
vtr::bimap<t_logical_pin, t_physical_pin> directs_map;
for (int npin = 0; npin < num_pins; npin++) {
t_physical_pin physical_pin(npin);
t_logical_pin logical_pin(npin);
directs_map.insert(logical_pin, physical_pin);
}
PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index][SubTile->index] = directs_map;
}
static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent,
t_sub_tile* SubTile,
t_physical_tile_type* PhysicalTileType,
t_logical_block_type* LogicalBlockType,
std::string site_name,
const pugiutil::loc_data& loc_data) {
pugi::xml_node CurDirect;
expect_only_children(Parent, {"direct"}, loc_data);
if (count_children(Parent, "direct", loc_data) < 1) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"There are no direct pin mappings between site %s and tile %s.\n", site_name.c_str(), SubTile->name);
}
vtr::bimap<t_logical_pin, t_physical_pin> directs_map;
CurDirect = Parent.first_child();
while (CurDirect) {
check_node(CurDirect, "direct", loc_data);
expect_only_attributes(CurDirect, {"from", "to"}, loc_data);
std::string from, to;
// `from` attribute is relative to the physical tile pins
from = std::string(get_attribute(CurDirect, "from", loc_data).value());
// `to` attribute is relative to the logical block pins
to = std::string(get_attribute(CurDirect, "to", loc_data).value());
auto from_pins = ProcessPinString<t_sub_tile*>(CurDirect, SubTile, from.c_str(), loc_data);
auto to_pins = ProcessPinString<t_logical_block_type_ptr>(CurDirect, LogicalBlockType, to.c_str(), loc_data);
// Checking that the number of pins is exactly the same
if (from_pins.second - from_pins.first != to_pins.second - to_pins.first) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"The number of pins specified in the direct pin mapping is "
"not equivalent for Physical Tile %s and Logical Block %s.\n",
SubTile->name, LogicalBlockType->name);
}
int num_pins = from_pins.second - from_pins.first;
for (int i = 0; i < num_pins; i++) {
t_physical_pin physical_pin(from_pins.first + i);
t_logical_pin logical_pin(to_pins.first + i);
auto result = directs_map.insert(logical_pin, physical_pin);
if (!result.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent),
"Duplicate logical pin (%d) to physical pin (%d) mappings found for "
"Physical Tile %s and Logical Block %s.\n",
logical_pin.pin, physical_pin.pin, SubTile->name, LogicalBlockType->name);
}
}
CurDirect = CurDirect.next_sibling(CurDirect.name());
}
PhysicalTileType->tile_block_pin_directs_map[LogicalBlockType->index][SubTile->index] = directs_map;
}
static void ProcessPinLocations(pugi::xml_node Locations,
t_physical_tile_type* PhysicalTileType,
t_sub_tile* SubTile,
t_pin_locs* pin_locs,
const pugiutil::loc_data& loc_data) {
pugi::xml_node Cur;
const char* Prop;
enum e_pin_location_distr distribution;
if (Locations) {
expect_only_attributes(Locations, {"pattern"}, loc_data);
Prop = get_attribute(Locations, "pattern", loc_data).value();
if (strcmp(Prop, "spread") == 0) {
distribution = E_SPREAD_PIN_DISTR;
} else if (strcmp(Prop, "perimeter") == 0) {
distribution = E_PERIMETER_PIN_DISTR;
} else if (strcmp(Prop, "spread_inputs_perimeter_outputs") == 0) {
distribution = E_SPREAD_INPUTS_PERIMETER_OUTPUTS_PIN_DISTR;
} else if (strcmp(Prop, "custom") == 0) {
distribution = E_CUSTOM_PIN_DISTR;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"%s is an invalid pin location pattern.\n", Prop);
}
} else {
distribution = E_SPREAD_PIN_DISTR;
Prop = "spread";
}
if (pin_locs->is_distribution_set()) {
if (pin_locs->distribution != distribution) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"Sub Tile %s has a different pin location pattern (%s) with respect "
"to the sibling sub tiles",
SubTile->name, Prop);
}
} else {
pin_locs->distribution = distribution;
pin_locs->set_distribution();
}
int sub_tile_index = SubTile->index;
/* Load the pin locations */
if (distribution == E_CUSTOM_PIN_DISTR) {
expect_only_children(Locations, {"loc"}, loc_data);
Cur = Locations.first_child();
std::set<std::tuple<e_side, int, int>> seen_sides;
while (Cur) {
check_node(Cur, "loc", loc_data);
expect_only_attributes(Cur, {"side", "xoffset", "yoffset"}, loc_data);
/* Get offset (ie. height) */
int x_offset = get_attribute(Cur, "xoffset", loc_data, ReqOpt::OPTIONAL).as_int(0);
int y_offset = get_attribute(Cur, "yoffset", loc_data, ReqOpt::OPTIONAL).as_int(0);
/* Get side */
e_side side = TOP;
Prop = get_attribute(Cur, "side", loc_data).value();
if (0 == strcmp(Prop, "left")) {
side = LEFT;
} else if (0 == strcmp(Prop, "top")) {
side = TOP;
} else if (0 == strcmp(Prop, "right")) {
side = RIGHT;
} else if (0 == strcmp(Prop, "bottom")) {
side = BOTTOM;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"'%s' is not a valid side.\n", Prop);
}
if ((x_offset < 0) || (x_offset >= PhysicalTileType->width)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"'%d' is an invalid horizontal offset for type '%s' (must be within [0, %d]).\n",
x_offset, PhysicalTileType->name, PhysicalTileType->width - 1);
}
if ((y_offset < 0) || (y_offset >= PhysicalTileType->height)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"'%d' is an invalid vertical offset for type '%s' (must be within [0, %d]).\n",
y_offset, PhysicalTileType->name, PhysicalTileType->height - 1);
}
//Check for duplicate side specifications, since the code below silently overwrites if there are duplicates
auto side_offset = std::make_tuple(side, x_offset, y_offset);
if (seen_sides.count(side_offset)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Duplicate pin location side/offset specification."
" Only a single <loc> per side/xoffset/yoffset is permitted.\n");
}
seen_sides.insert(side_offset);
/* Go through lists of pins */
const std::vector<std::string> Tokens = vtr::split(Cur.child_value());
int Count = (int)Tokens.size();
if (Count > 0) {
for (int pin = 0; pin < Count; ++pin) {
/* Store location assignment */
pin_locs->assignments[sub_tile_index][x_offset][y_offset][side].push_back(std::string(Tokens[pin].c_str()));
/* Advance through list of pins in this location */
}
}
Cur = Cur.next_sibling(Cur.name());
}
//Verify that all top-level pins have had their locations specified
//Record all the specified pins
std::map<std::string, std::set<int>> port_pins_with_specified_locations;
for (int w = 0; w < PhysicalTileType->width; ++w) {
for (int h = 0; h < PhysicalTileType->height; ++h) {
for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
for (auto token : pin_locs->assignments[sub_tile_index][w][h][side]) {
InstPort inst_port(token.c_str());
//A pin specification should contain only the block name, and not any instace count information
if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"Pin location specification '%s' should not contain an instance range (should only be the block name)",
token.c_str());
}
//Check that the block name matches
if (inst_port.instance_name() != SubTile->name) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"Mismatched sub tile name in pin location specification (expected '%s' was '%s')",
SubTile->name, inst_port.instance_name().c_str());
}
int pin_low_idx = inst_port.port_low_index();
int pin_high_idx = inst_port.port_high_index();
if (pin_low_idx == InstPort::UNSPECIFIED && pin_high_idx == InstPort::UNSPECIFIED) {
//Empty range, so full port
//Find the matching pb type to get the total number of pins
const t_physical_tile_port* port = nullptr;
for (const auto& tmp_port : SubTile->ports) {
if (tmp_port.name == inst_port.port_name()) {
port = &tmp_port;
break;
}
}
if (port) {
pin_low_idx = 0;
pin_high_idx = port->num_pins - 1;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"Failed to find port named '%s' on block '%s'",
inst_port.port_name().c_str(), SubTile->name);
}
}
VTR_ASSERT(pin_low_idx >= 0);
VTR_ASSERT(pin_high_idx >= 0);
for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) {
//Record that the pin has it's location specified
port_pins_with_specified_locations[inst_port.port_name()].insert(ipin);
}
}
}
}
}
//Check for any pins missing location specs
for (const auto& port : SubTile->ports) {
for (int ipin = 0; ipin < port.num_pins; ++ipin) {
if (!port_pins_with_specified_locations[port.name].count(ipin)) {
//Missing
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations),
"Pin '%s.%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")",
SubTile->name, port.name, ipin);
}
}
}
} else if (Locations) {
//Non-custom pin locations. There should be no child tags
expect_child_node_count(Locations, 0, loc_data);
}
}
static void ProcessSubTiles(pugi::xml_node Node,
t_physical_tile_type* PhysicalTileType,
std::vector<t_logical_block_type>& LogicalBlockTypes,
std::vector<t_segment_inf>& segments,
const t_default_fc_spec& arch_def_fc,
const pugiutil::loc_data& loc_data) {
pugi::xml_node CurSubTile;
pugi::xml_node Cur;
int index = 0;
unsigned long int num_sub_tiles = count_children(Node, "sub_tile", loc_data);
unsigned long int width = PhysicalTileType->width;
unsigned long int height = PhysicalTileType->height;
unsigned long int num_sides = 4;
std::map<std::string, int> sub_tile_names;
t_pin_locs pin_locs;
pin_locs.assignments.resize({num_sub_tiles, width, height, num_sides});
if (num_sub_tiles == 0) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"No sub tile found for the Physical Tile %s.\n"
"At least one sub tile is needed to correctly describe the Physical Tile.\n",
PhysicalTileType->name);
}
CurSubTile = get_first_child(Node, "sub_tile", loc_data);
while (CurSubTile) {
t_sub_tile SubTile;
SubTile.index = index;
expect_only_attributes(CurSubTile, {"name", "capacity"}, loc_data);
/* Load type name */
auto name = vtr::strdup(get_attribute(CurSubTile, "name", loc_data).value());
//Check Sub Tile name duplicates
auto result = sub_tile_names.insert(std::pair<std::string, int>(std::string(name), 0));
if (!result.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
"Duplicate Sub Tile names in tile '%s': Sub Tile'%s'\n",
PhysicalTileType->name, name);
}
SubTile.name = name;
/* Load properties */
int capacity = get_attribute(CurSubTile, "capacity", loc_data, ReqOpt::OPTIONAL).as_int(1);
SubTile.capacity.set(PhysicalTileType->capacity, PhysicalTileType->capacity + capacity - 1);
PhysicalTileType->capacity += capacity;
/* Process sub tile port definitions */
std::unordered_map<std::string, t_physical_tile_port> tile_port_names;
auto pin_counts = ProcessSubTilePorts(CurSubTile, &SubTile, tile_port_names, loc_data);
/* Map Sub Tile physical pins with the Physical Tile Type physical pins.
* This takes into account the capacity of each sub tiles to add the correct offset.
*/
for (int ipin = 0; ipin < capacity * pin_counts.total(); ipin++) {
SubTile.sub_tile_to_tile_pin_indices.push_back(PhysicalTileType->num_pins + ipin);
}
SubTile.num_phy_pins = pin_counts.total() * capacity;
/* Assign pin counts to the Physical Tile Type */
PhysicalTileType->num_input_pins += pin_counts.input;
PhysicalTileType->num_output_pins += pin_counts.output;
PhysicalTileType->num_clock_pins += pin_counts.clock;
PhysicalTileType->num_pins += capacity * pin_counts.total();
PhysicalTileType->num_inst_pins += pin_counts.total();
/* Assign drivers and receivers count to Physical Tile Type */
PhysicalTileType->num_receivers += capacity * pin_counts.input;
PhysicalTileType->num_drivers += capacity * pin_counts.output;
Cur = get_single_child(CurSubTile, "pinlocations", loc_data, ReqOpt::OPTIONAL);
ProcessPinLocations(Cur, PhysicalTileType, &SubTile, &pin_locs, loc_data);
/* Load Fc */
Cur = get_single_child(CurSubTile, "fc", loc_data, ReqOpt::OPTIONAL);
Process_Fc(Cur, PhysicalTileType, &SubTile, pin_counts, segments, arch_def_fc, loc_data);
//Load equivalent sites infromation
Cur = get_single_child(CurSubTile, "equivalent_sites", loc_data, ReqOpt::REQUIRED);
ProcessTileEquivalentSites(Cur, &SubTile, PhysicalTileType, LogicalBlockTypes, loc_data);
PhysicalTileType->sub_tiles.push_back(SubTile);
index++;
CurSubTile = CurSubTile.next_sibling(CurSubTile.name());
}
// Initialize pinloc data structure.
int num_pins = PhysicalTileType->num_pins;
PhysicalTileType->pinloc.resize({width, height, num_sides}, std::vector<bool>(num_pins, false));
SetupPinClasses(PhysicalTileType);
LoadPinLoc(Cur, PhysicalTileType, &pin_locs, loc_data);
}
/* Takes in node pointing to <typelist> and loads all the
* child type objects. */
static void ProcessComplexBlocks(vtr::string_internment* strings, pugi::xml_node Node, std::vector<t_logical_block_type>& LogicalBlockTypes, t_arch& arch, const bool timing_enabled, const pugiutil::loc_data& loc_data) {
pugi::xml_node CurBlockType;
pugi::xml_node Cur;
std::map<std::string, int> pb_type_descriptors;
/* Alloc the type list. Need one additional t_type_desctiptors:
* 1: empty psuedo-type
*/
t_logical_block_type EMPTY_LOGICAL_BLOCK_TYPE = SetupEmptyLogicalType();
EMPTY_LOGICAL_BLOCK_TYPE.index = 0;
LogicalBlockTypes.push_back(EMPTY_LOGICAL_BLOCK_TYPE);
/* Process the types */
int index = 1; /* Skip over 'empty' type */
CurBlockType = Node.first_child();
while (CurBlockType) {
check_node(CurBlockType, "pb_type", loc_data);
t_logical_block_type LogicalBlockType;
expect_only_attributes(CurBlockType, {"name"}, loc_data);
/* Load type name */
auto Prop = get_attribute(CurBlockType, "name", loc_data).value();
LogicalBlockType.name = vtr::strdup(Prop);
auto result = pb_type_descriptors.insert(std::pair<std::string, int>(LogicalBlockType.name, 0));
if (!result.second) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(CurBlockType),
"Duplicate pb_type descriptor name: '%s'.\n", LogicalBlockType.name);
}
/* Load pb_type info to assign to the Logical Block Type */
LogicalBlockType.pb_type = new t_pb_type;
LogicalBlockType.pb_type->name = vtr::strdup(LogicalBlockType.name);
ProcessPb_Type(strings, CurBlockType, LogicalBlockType.pb_type, nullptr, timing_enabled, arch, loc_data);
LogicalBlockType.index = index;
/* Type fully read */
++index;
/* Push newly created Types to corresponding vectors */
LogicalBlockTypes.push_back(LogicalBlockType);
/* Free this node and get its next sibling node */
CurBlockType = CurBlockType.next_sibling(CurBlockType.name());
}
pb_type_descriptors.clear();
}
static void ProcessSegments(pugi::xml_node Parent,
std::vector<t_segment_inf>& Segs,
const t_arch_switch_inf* Switches,
const int NumSwitches,
const bool timing_enabled,
const bool switchblocklist_required,
const pugiutil::loc_data& loc_data) {
int i, j, length;
const char* tmp;
pugi::xml_node SubElem;
pugi::xml_node Node;
/* Count the number of segs and check they are in fact
* of segment elements. */
int NumSegs = count_children(Parent, "segment", loc_data);
/* Alloc segment list */
if (NumSegs > 0) {
Segs.resize(NumSegs);
}
/* Load the segments. */
Node = get_first_child(Parent, "segment", loc_data);
for (i = 0; i < NumSegs; ++i) {
/* Get segment name */
tmp = get_attribute(Node, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (tmp) {
Segs[i].name = std::string(tmp);
} else {
/* if swich block is "custom", then you have to provide a name for segment */
if (switchblocklist_required) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"No name specified for the segment #%d.\n", i);
}
/* set name to default: "unnamed_segment_<segment_index>" */
std::stringstream ss;
ss << "unnamed_segment_" << i;
std::string dummy = ss.str();
tmp = dummy.c_str();
Segs[i].name = std::string(tmp);
}
/* Get segment length */
length = 1; /* DEFAULT */
tmp = get_attribute(Node, "length", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (tmp) {
if (strcmp(tmp, "longline") == 0) {
Segs[i].longline = true;
} else {
length = vtr::atoi(tmp);
}
}
Segs[i].length = length;
/* Get the frequency */
Segs[i].frequency = 1; /* DEFAULT */
tmp = get_attribute(Node, "freq", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (tmp) {
Segs[i].frequency = (int)(atof(tmp) * MAX_CHANNEL_WIDTH);
}
/* Get timing info */
ReqOpt TIMING_ENABLE_REQD = BoolToReqOpt(timing_enabled);
Segs[i].Rmetal = get_attribute(Node, "Rmetal", loc_data, TIMING_ENABLE_REQD).as_float(0);
Segs[i].Cmetal = get_attribute(Node, "Cmetal", loc_data, TIMING_ENABLE_REQD).as_float(0);
/* Get Power info */
/*
* (*Segs)[i].Cmetal_per_m = get_attribute(Node, "Cmetal_per_m", false,
* 0.);*/
//Set of expected subtags (exact subtags are dependant on parameters)
std::vector<std::string> expected_subtags;
if (!Segs[i].longline) {
//Long line doesn't accpet <sb> or <cb> since it assumes full population
expected_subtags.push_back("sb");
expected_subtags.push_back("cb");
}
/* Get the type */
tmp = get_attribute(Node, "type", loc_data).value();
if (0 == strcmp(tmp, "bidir")) {
Segs[i].directionality = BI_DIRECTIONAL;
//Bidir requires the following tags
expected_subtags.push_back("wire_switch");
expected_subtags.push_back("opin_switch");
}
else if (0 == strcmp(tmp, "unidir")) {
Segs[i].directionality = UNI_DIRECTIONAL;
//Unidir requires the following tags
expected_subtags.push_back("mux");
}
else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Invalid switch type '%s'.\n", tmp);
}
//Verify only expected sub-tags are found
expect_only_children(Node, expected_subtags, loc_data);
/* Get the wire and opin switches, or mux switch if unidir */
if (UNI_DIRECTIONAL == Segs[i].directionality) {
SubElem = get_single_child(Node, "mux", loc_data);
tmp = get_attribute(SubElem, "name", loc_data).value();
/* Match names */
for (j = 0; j < NumSwitches; ++j) {
if (0 == strcmp(tmp, Switches[j].name)) {
break; /* End loop so j is where we want it */
}
}
if (j >= NumSwitches) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
"'%s' is not a valid mux name.\n", tmp);
}
/* Unidir muxes must have the same switch
* for wire and opin fanin since there is
* really only the mux in unidir. */
Segs[i].arch_wire_switch = j;
Segs[i].arch_opin_switch = j;
}
else {
VTR_ASSERT(BI_DIRECTIONAL == Segs[i].directionality);
SubElem = get_single_child(Node, "wire_switch", loc_data);
tmp = get_attribute(SubElem, "name", loc_data).value();
/* Match names */
for (j = 0; j < NumSwitches; ++j) {
if (0 == strcmp(tmp, Switches[j].name)) {
break; /* End loop so j is where we want it */
}
}
if (j >= NumSwitches) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
"'%s' is not a valid wire_switch name.\n", tmp);
}
Segs[i].arch_wire_switch = j;
SubElem = get_single_child(Node, "opin_switch", loc_data);
tmp = get_attribute(SubElem, "name", loc_data).value();
/* Match names */
for (j = 0; j < NumSwitches; ++j) {
if (0 == strcmp(tmp, Switches[j].name)) {
break; /* End loop so j is where we want it */
}
}
if (j >= NumSwitches) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem),
"'%s' is not a valid opin_switch name.\n", tmp);
}
Segs[i].arch_opin_switch = j;
}
/* Setup the CB list if they give one, otherwise use full */
Segs[i].cb.resize(length);
for (j = 0; j < length; ++j) {
Segs[i].cb[j] = true;
}
SubElem = get_single_child(Node, "cb", loc_data, ReqOpt::OPTIONAL);
if (SubElem) {
ProcessCB_SB(SubElem, Segs[i].cb, loc_data);
}
/* Setup the SB list if they give one, otherwise use full */
Segs[i].sb.resize(length + 1);
for (j = 0; j < (length + 1); ++j) {
Segs[i].sb[j] = true;
}
SubElem = get_single_child(Node, "sb", loc_data, ReqOpt::OPTIONAL);
if (SubElem) {
ProcessCB_SB(SubElem, Segs[i].sb, loc_data);
}
/* Get next Node */
Node = Node.next_sibling(Node.name());
}
}
/* Processes the switchblocklist section from the xml architecture file.
* See vpr/SRC/route/build_switchblocks.c for a detailed description of this
* switch block format */
static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiutil::loc_data& loc_data) {
pugi::xml_node Node;
pugi::xml_node SubElem;
const char* tmp;
/* get the number of switchblocks */
int num_switchblocks = count_children(Parent, "switchblock", loc_data);
arch->switchblocks.reserve(num_switchblocks);
/* read-in all switchblock data */
Node = get_first_child(Parent, "switchblock", loc_data);
for (int i_sb = 0; i_sb < num_switchblocks; i_sb++) {
/* use a temp variable which will be assigned to switchblocks later */
t_switchblock_inf sb;
/* get name */
tmp = get_attribute(Node, "name", loc_data).as_string(nullptr);
if (tmp) {
sb.name = tmp;
}
/* get type */
tmp = get_attribute(Node, "type", loc_data).as_string(nullptr);
if (tmp) {
if (0 == strcmp(tmp, "bidir")) {
sb.directionality = BI_DIRECTIONAL;
} else if (0 == strcmp(tmp, "unidir")) {
sb.directionality = UNI_DIRECTIONAL;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "Unsopported switchblock type: %s\n", tmp);
}
}
/* get the switchblock location */
SubElem = get_single_child(Node, "switchblock_location", loc_data);
tmp = get_attribute(SubElem, "type", loc_data).as_string(nullptr);
if (tmp) {
if (strcmp(tmp, "EVERYWHERE") == 0) {
sb.location = E_EVERYWHERE;
} else if (strcmp(tmp, "PERIMETER") == 0) {
sb.location = E_PERIMETER;
} else if (strcmp(tmp, "CORE") == 0) {
sb.location = E_CORE;
} else if (strcmp(tmp, "CORNER") == 0) {
sb.location = E_CORNER;
} else if (strcmp(tmp, "FRINGE") == 0) {
sb.location = E_FRINGE;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), "unrecognized switchblock location: %s\n", tmp);
}
}
/* get switchblock permutation functions */
SubElem = get_first_child(Node, "switchfuncs", loc_data);
read_sb_switchfuncs(SubElem, &sb, loc_data);
read_sb_wireconns(arch->Switches, arch->num_switches, Node, &sb, loc_data);
/* run error checks on switch blocks */
check_switchblock(&sb, arch);
/* assign the sb to the switchblocks vector */
arch->switchblocks.push_back(sb);
Node = Node.next_sibling(Node.name());
}
return;
}
static void ProcessCB_SB(pugi::xml_node Node, std::vector<bool>& list, const pugiutil::loc_data& loc_data) {
const char* tmp = nullptr;
int i;
int len = list.size();
/* Check the type. We only support 'pattern' for now.
* Should add frac back eventually. */
tmp = get_attribute(Node, "type", loc_data).value();
if (0 == strcmp(tmp, "pattern")) {
i = 0;
/* Get the content string */
tmp = Node.child_value();
while (*tmp) {
switch (*tmp) {
case ' ':
case '\t':
case '\n':
break;
case 'T':
case '1':
if (i >= len) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"CB or SB depopulation is too long (%d). It should be %d symbols for CBs and %d symbols for SBs.\n",
i, len - 1, len);
}
list[i] = true;
++i;
break;
case 'F':
case '0':
if (i >= len) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"CB or SB depopulation is too long (%d). It should be %d symbols for CBs and %d symbols for SBs.\n",
i, len - 1, len);
}
list[i] = false;
++i;
break;
default:
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Invalid character %c in CB or SB depopulation list.\n",
*tmp);
}
++tmp;
}
if (i < len) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"CB or SB depopulation is too short (%d). It should be %d symbols for CBs and %d symbols for SBs.\n",
i, len - 1, len);
}
}
else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"'%s' is not a valid type for specifying cb and sb depopulation.\n",
tmp);
}
}
static void ProcessSwitches(pugi::xml_node Parent,
t_arch_switch_inf** Switches,
int* NumSwitches,
const bool timing_enabled,
const pugiutil::loc_data& loc_data) {
int i, j;
const char* type_name;
const char* switch_name;
ReqOpt TIMING_ENABLE_REQD = BoolToReqOpt(timing_enabled);
pugi::xml_node Node;
/* Count the children and check they are switches */
*NumSwitches = count_children(Parent, "switch", loc_data);
/* Alloc switch list */
*Switches = nullptr;
if (*NumSwitches > 0) {
(*Switches) = new t_arch_switch_inf[(*NumSwitches)];
}
/* Load the switches. */
Node = get_first_child(Parent, "switch", loc_data);
for (i = 0; i < *NumSwitches; ++i) {
t_arch_switch_inf& arch_switch = (*Switches)[i];
switch_name = get_attribute(Node, "name", loc_data).value();
/* Check if the switch has conflicts with any reserved names */
if (0 == strcmp(switch_name, VPR_DELAYLESS_SWITCH_NAME)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Switch name '%s' is a reserved name for VPR internal usage! Please use another name.\n",
switch_name);
}
type_name = get_attribute(Node, "type", loc_data).value();
/* Check for switch name collisions */
for (j = 0; j < i; ++j) {
if (0 == strcmp((*Switches)[j].name, switch_name)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Two switches with the same name '%s' were found.\n",
switch_name);
}
}
arch_switch.name = vtr::strdup(switch_name);
/* Figure out the type of switch */
/* As noted above, due to their configuration of pass transistors feeding into a buffer,
* only multiplexers and tristate buffers have an internal capacitance element. */
SwitchType type = SwitchType::MUX;
if (0 == strcmp(type_name, "mux")) {
type = SwitchType::MUX;
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "penalty_cost", "buf_size", "power_buf_size", "mux_trans_size"}, " with type '"s + type_name + "'"s, loc_data);
} else if (0 == strcmp(type_name, "tristate")) {
type = SwitchType::TRISTATE;
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "penalty_cost", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
} else if (0 == strcmp(type_name, "buffer")) {
type = SwitchType::BUFFER;
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
} else if (0 == strcmp(type_name, "pass_gate")) {
type = SwitchType::PASS_GATE;
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost"}, " with type '"s + type_name + "'"s, loc_data);
} else if (0 == strcmp(type_name, "short")) {
type = SwitchType::SHORT;
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost"}, " with type "s + type_name + "'"s, loc_data);
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Invalid switch type '%s'.\n", type_name);
}
arch_switch.set_type(type);
arch_switch.R = get_attribute(Node, "R", loc_data, TIMING_ENABLE_REQD).as_float(0);
ReqOpt COUT_REQD = TIMING_ENABLE_REQD;
ReqOpt CIN_REQD = TIMING_ENABLE_REQD;
// We have defined the Cinternal parameter as optional, so that the user may specify an
// architecture without Cinternal without breaking the program flow.
ReqOpt CINTERNAL_REQD = ReqOpt::OPTIONAL;
if (arch_switch.type() == SwitchType::SHORT) {
//Cin/Cout are optional on shorts, since they really only have one capacitance
CIN_REQD = ReqOpt::OPTIONAL;
COUT_REQD = ReqOpt::OPTIONAL;
}
arch_switch.Cin = get_attribute(Node, "Cin", loc_data, CIN_REQD).as_float(0);
arch_switch.Cout = get_attribute(Node, "Cout", loc_data, COUT_REQD).as_float(0);
arch_switch.Cinternal = get_attribute(Node, "Cinternal", loc_data, CINTERNAL_REQD).as_float(0);
arch_switch.penalty_cost = get_attribute(Node, "penalty_cost", loc_data, ReqOpt::OPTIONAL).as_float(0);
if (arch_switch.type() == SwitchType::MUX) {
//Only muxes have mux transistors
arch_switch.mux_trans_size = get_attribute(Node, "mux_trans_size", loc_data, ReqOpt::OPTIONAL).as_float(1);
} else {
arch_switch.mux_trans_size = 0.;
}
if (arch_switch.type() == SwitchType::SHORT
|| arch_switch.type() == SwitchType::PASS_GATE) {
//No buffers
arch_switch.buf_size_type = BufferSize::ABSOLUTE;
arch_switch.buf_size = 0.;
arch_switch.power_buffer_type = POWER_BUFFER_TYPE_ABSOLUTE_SIZE;
arch_switch.power_buffer_size = 0.;
} else {
auto buf_size_attrib = get_attribute(Node, "buf_size", loc_data, ReqOpt::OPTIONAL);
if (!buf_size_attrib || buf_size_attrib.as_string() == std::string("auto")) {
arch_switch.buf_size_type = BufferSize::AUTO;
arch_switch.buf_size = 0.;
} else {
arch_switch.buf_size_type = BufferSize::ABSOLUTE;
arch_switch.buf_size = buf_size_attrib.as_float();
}
auto power_buf_size = get_attribute(Node, "power_buf_size", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (power_buf_size == nullptr) {
arch_switch.power_buffer_type = POWER_BUFFER_TYPE_AUTO;
} else if (strcmp(power_buf_size, "auto") == 0) {
arch_switch.power_buffer_type = POWER_BUFFER_TYPE_AUTO;
} else {
arch_switch.power_buffer_type = POWER_BUFFER_TYPE_ABSOLUTE_SIZE;
arch_switch.power_buffer_size = (float)vtr::atof(power_buf_size);
}
}
//Load the Tdel (which may be specfied with sub-tags)
ProcessSwitchTdel(Node, timing_enabled, i, (*Switches), loc_data);
/* Get next switch element */
Node = Node.next_sibling(Node.name());
}
}
/* Processes the switch delay. Switch delay can be specified in two ways.
* First way: switch delay is specified as a constant via the property Tdel in the switch node.
* Second way: switch delay is specified as a function of the switch fan-in. In this
* case, multiple nodes in the form
*
* <Tdel num_inputs="1" delay="3e-11"/>
*
* are specified as children of the switch node. In this case, Tdel
* is not included as a property of the switch node (first way). */
static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, const int switch_index, t_arch_switch_inf* Switches, const pugiutil::loc_data& loc_data) {
float Tdel_prop_value;
int num_Tdel_children;
/* check if switch node has the Tdel property */
bool has_Tdel_prop = false;
Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED);
if (Tdel_prop_value != UNDEFINED) {
has_Tdel_prop = true;
}
/* check if switch node has Tdel children */
bool has_Tdel_children = false;
num_Tdel_children = count_children(Node, "Tdel", loc_data, ReqOpt::OPTIONAL);
if (num_Tdel_children != 0) {
has_Tdel_children = true;
}
/* delay should not be specified as a Tdel property AND a Tdel child */
if (has_Tdel_prop && has_Tdel_children) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Switch delay should be specified as EITHER a Tdel property OR as a child of the switch node, not both");
}
/* get pointer to the switch's Tdel map, then read-in delay data into this map */
if (has_Tdel_prop) {
/* delay specified as a constant */
Switches[switch_index].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, Tdel_prop_value);
} else if (has_Tdel_children) {
/* Delay specified as a function of switch fan-in.
* Go through each Tdel child, read-in num_inputs and the delay value.
* Insert this info into the switch delay map */
pugi::xml_node Tdel_child = get_first_child(Node, "Tdel", loc_data);
std::set<int> seen_fanins;
for (int ichild = 0; ichild < num_Tdel_children; ichild++) {
int num_inputs = get_attribute(Tdel_child, "num_inputs", loc_data).as_int(0);
float Tdel_value = get_attribute(Tdel_child, "delay", loc_data).as_float(0.);
if (seen_fanins.count(num_inputs)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Tdel_child),
"Tdel node specified num_inputs (%d) that has already been specified by another Tdel node", num_inputs);
} else {
Switches[switch_index].set_Tdel(num_inputs, Tdel_value);
seen_fanins.insert(num_inputs);
}
Tdel_child = Tdel_child.next_sibling(Tdel_child.name());
}
} else {
/* No delay info specified for switch */
if (timing_enabled) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Switch should contain intrinsic delay information if timing is enabled");
} else {
/* set a default value */
Switches[switch_index].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.);
}
}
}
static void ProcessDirects(pugi::xml_node Parent, t_direct_inf** Directs, int* NumDirects, const t_arch_switch_inf* Switches, const int NumSwitches, const pugiutil::loc_data& loc_data) {
int i, j;
const char* direct_name;
const char* from_pin_name;
const char* to_pin_name;
const char* switch_name;
pugi::xml_node Node;
/* Count the children and check they are direct connections */
expect_only_children(Parent, {"direct"}, loc_data);
*NumDirects = count_children(Parent, "direct", loc_data);
/* Alloc direct list */
*Directs = nullptr;
if (*NumDirects > 0) {
*Directs = (t_direct_inf*)vtr::malloc(*NumDirects * sizeof(t_direct_inf));
memset(*Directs, 0, (*NumDirects * sizeof(t_direct_inf)));
}
/* Load the directs. */
Node = get_first_child(Parent, "direct", loc_data);
for (i = 0; i < *NumDirects; ++i) {
expect_only_attributes(Node, {"name", "from_pin", "to_pin", "x_offset", "y_offset", "z_offset", "switch_name", "from_side", "to_side"}, loc_data);
direct_name = get_attribute(Node, "name", loc_data).value();
/* Check for direct name collisions */
for (j = 0; j < i; ++j) {
if (0 == strcmp((*Directs)[j].name, direct_name)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Two directs with the same name '%s' were found.\n",
direct_name);
}
}
(*Directs)[i].name = vtr::strdup(direct_name);
/* Figure out the source pin and sink pin name */
from_pin_name = get_attribute(Node, "from_pin", loc_data).value();
to_pin_name = get_attribute(Node, "to_pin", loc_data).value();
/* Check that to_pin and the from_pin are not the same */
if (0 == strcmp(to_pin_name, from_pin_name)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"The source pin and sink pin are the same: %s.\n",
to_pin_name);
}
(*Directs)[i].from_pin = vtr::strdup(from_pin_name);
(*Directs)[i].to_pin = vtr::strdup(to_pin_name);
(*Directs)[i].x_offset = get_attribute(Node, "x_offset", loc_data).as_int(0);
(*Directs)[i].y_offset = get_attribute(Node, "y_offset", loc_data).as_int(0);
(*Directs)[i].sub_tile_offset = get_attribute(Node, "z_offset", loc_data).as_int(0);
std::string from_side_str = get_attribute(Node, "from_side", loc_data, ReqOpt::OPTIONAL).value();
(*Directs)[i].from_side = string_to_side(from_side_str);
std::string to_side_str = get_attribute(Node, "to_side", loc_data, ReqOpt::OPTIONAL).value();
(*Directs)[i].to_side = string_to_side(to_side_str);
//Set the optional switch type
switch_name = get_attribute(Node, "switch_name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr);
if (switch_name != nullptr) {
//Look-up the user defined switch
for (j = 0; j < NumSwitches; j++) {
if (0 == strcmp(switch_name, Switches[j].name)) {
break; //Found the switch
}
}
if (j >= NumSwitches) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"Could not find switch named '%s' in switch list.\n", switch_name);
}
(*Directs)[i].switch_type = j; //Save the correct switch index
} else {
//If not defined, use the delayless switch by default
//TODO: find a better way of indicating this. Ideally, we would
//specify the delayless switch index here, but it does not appear
//to be defined at this point.
(*Directs)[i].switch_type = -1;
}
/* Check that the direct chain connection is not zero in both direction */
if ((*Directs)[i].x_offset == 0 && (*Directs)[i].y_offset == 0) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
"The x_offset and y_offset are both zero, this is a length 0 direct chain connection.\n");
}
(*Directs)[i].line = loc_data.line(Node);
/* Should I check that the direct chain offset is not greater than the chip? How? */
/* Get next direct element */
Node = Node.next_sibling(Node.name());
}
}
static void ProcessClockMetalLayers(pugi::xml_node parent,
std::unordered_map<std::string, t_metal_layer>& metal_layers,
pugiutil::loc_data& loc_data) {
std::vector<std::string> expected_attributes = {"name", "Rmetal", "Cmetal"};
std::vector<std::string> expected_children = {"metal_layer"};
pugi::xml_node metal_layers_parent = get_single_child(parent, "metal_layers", loc_data);
int num_metal_layers = count_children(metal_layers_parent, "metal_layer", loc_data);
pugi::xml_node curr_layer = get_first_child(metal_layers_parent, "metal_layer", loc_data);
for (int i = 0; i < num_metal_layers; i++) {
expect_only_children(metal_layers_parent, expected_children, loc_data);
expect_only_attributes(curr_layer, expected_attributes, loc_data);
// Get metal layer values: name, r_metal, and c_metal
std::string name(get_attribute(curr_layer, "name", loc_data).value());
t_metal_layer metal_layer;
metal_layer.r_metal = get_attribute(curr_layer, "Rmetal", loc_data).as_float(0.);
metal_layer.c_metal = get_attribute(curr_layer, "Cmetal", loc_data).as_float(0.);
// Insert metal layer into map
auto itter = metal_layers.find(name);
if (itter != metal_layers.end()) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(curr_layer),
"Two metal layers with the same name '%s' were found.\n",
name.c_str());
}
metal_layers.insert({name, metal_layer});
curr_layer = curr_layer.next_sibling(curr_layer.name());
}
}
static void ProcessClockNetworks(pugi::xml_node parent,
std::vector<t_clock_network_arch>& clock_networks,
const t_arch_switch_inf* switches,
const int num_switches,
pugiutil::loc_data& loc_data) {
std::vector<std::string> expected_spine_attributes = {"name", "num_inst", "metal_layer", "starty", "endy", "x", "repeatx", "repeaty"};
std::vector<std::string> expected_rib_attributes = {"name", "num_inst", "metal_layer", "startx", "endx", "y", "repeatx", "repeaty"};
std::vector<std::string> expected_children = {"rib", "spine"};
int num_clock_networks = count_children(parent, "clock_network", loc_data);
pugi::xml_node curr_network = get_first_child(parent, "clock_network", loc_data);
for (int i = 0; i < num_clock_networks; i++) {
expect_only_children(curr_network, expected_children, loc_data);
t_clock_network_arch clock_network;
std::string name(get_attribute(curr_network, "name", loc_data).value());
clock_network.name = name;
clock_network.num_inst = get_attribute(curr_network, "num_inst", loc_data).as_int(0);
bool is_supported_clock_type = false;
pugi::xml_node curr_type;
// Parse spine
curr_type = get_single_child(curr_network, "spine", loc_data, ReqOpt::OPTIONAL);
if (curr_type) {
expect_only_attributes(curr_network, expected_spine_attributes, loc_data);
is_supported_clock_type = true;
clock_network.type = e_clock_type::SPINE;
std::string metal_layer(get_attribute(curr_type, "metal_layer", loc_data).value());
std::string starty(get_attribute(curr_type, "starty", loc_data).value());
std::string endy(get_attribute(curr_type, "endy", loc_data).value());
std::string x(get_attribute(curr_type, "x", loc_data).value());
std::string repeatx;
auto repeatx_attr = get_attribute(curr_type, "repeatx", loc_data, ReqOpt::OPTIONAL);
if (repeatx_attr) {
repeatx = repeatx_attr.value();
} else {
repeatx = "W";
}
std::string repeaty;
auto repeaty_attr = get_attribute(curr_type, "repeaty", loc_data, ReqOpt::OPTIONAL);
if (repeaty_attr) {
repeaty = repeaty_attr.value();
} else {
repeaty = "H";
}
clock_network.metal_layer = metal_layer;
clock_network.wire.start = starty;
clock_network.wire.end = endy;
clock_network.wire.position = x;
clock_network.repeat.x = repeatx;
clock_network.repeat.y = repeaty;
ProcessClockSwitchPoints(curr_type, clock_network, switches, num_switches, loc_data);
}
// Parse rib
curr_type = get_single_child(curr_network, "rib", loc_data, ReqOpt::OPTIONAL);
if (curr_type) {
expect_only_attributes(curr_network, expected_spine_attributes, loc_data);
is_supported_clock_type = true;
clock_network.type = e_clock_type::RIB;
std::string metal_layer(get_attribute(curr_type, "metal_layer", loc_data).value());
std::string startx(get_attribute(curr_type, "startx", loc_data).value());
std::string endx(get_attribute(curr_type, "endx", loc_data).value());
std::string y(get_attribute(curr_type, "y", loc_data).value());
std::string repeatx;
auto repeatx_attr = get_attribute(curr_type, "repeatx", loc_data, ReqOpt::OPTIONAL);
if (repeatx_attr) {
repeatx = repeatx_attr.value();
} else {
repeatx = "W";
}
std::string repeaty;
auto repeaty_attr = get_attribute(curr_type, "repeaty", loc_data, ReqOpt::OPTIONAL);
if (repeaty_attr) {
repeaty = repeaty_attr.value();
} else {
repeaty = "H";
}
clock_network.metal_layer = metal_layer;
clock_network.wire.start = startx;
clock_network.wire.end = endx;
clock_network.wire.position = y;
clock_network.repeat.x = repeatx;
clock_network.repeat.y = repeaty;
ProcessClockSwitchPoints(curr_type, clock_network, switches, num_switches, loc_data);
}
// Currently their is only support for ribs and spines
if (!is_supported_clock_type) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(curr_type),
"Found no supported clock network type for '%s' clock network.\n"
"Currently there is only support for rib and spine networks.\n",
name.c_str());
}
clock_networks.push_back(clock_network);
curr_network = curr_network.next_sibling(curr_network.name());
}
}
static void ProcessClockSwitchPoints(pugi::xml_node parent,
t_clock_network_arch& clock_network,
const t_arch_switch_inf* switches,
const int num_switches,
pugiutil::loc_data& loc_data) {
std::vector<std::string> expected_spine_drive_attributes = {"name", "type", "yoffset", "switch_name"};
std::vector<std::string> expected_rib_drive_attributes = {"name", "type", "xoffset", "switch_name"};
std::vector<std::string> expected_spine_tap_attributes = {"name", "type", "yoffset", "yincr"};
std::vector<std::string> expected_rib_tap_attributes = {"name", "type", "xoffset", "xincr"};
std::vector<std::string> expected_children = {"switch_point"};
int num_clock_switches = count_children(parent, "switch_point", loc_data);
pugi::xml_node curr_switch = get_first_child(parent, "switch_point", loc_data);
//TODO: currently only supporting one drive and one tap. Should change to support
// multiple taps
VTR_ASSERT(num_switches != 2);
//TODO: ensure switch name is unique for every switch of this clock network
for (int i = 0; i < num_clock_switches; i++) {
expect_only_children(curr_switch, expected_children, loc_data);
std::string switch_type(get_attribute(curr_switch, "type", loc_data).value());
if (switch_type == "drive") {
t_clock_drive drive;
std::string name(get_attribute(curr_switch, "name", loc_data).value());
const char* offset;
if (clock_network.type == e_clock_type::SPINE) {
expect_only_attributes(curr_switch, expected_spine_drive_attributes, loc_data);
offset = get_attribute(curr_switch, "yoffset", loc_data).value();
} else {
VTR_ASSERT(clock_network.type == e_clock_type::RIB);
expect_only_attributes(curr_switch, expected_rib_drive_attributes, loc_data);
offset = get_attribute(curr_switch, "xoffset", loc_data).value();
}
// get switch index
const char* switch_name = get_attribute(curr_switch, "switch_name", loc_data).value();
int switch_idx;
for (switch_idx = 0; switch_idx < num_switches; switch_idx++) {
if (0 == strcmp(switch_name, switches[switch_idx].name)) {
break; // switch_idx has been found
}
}
if (switch_idx >= num_switches) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(curr_switch),
"'%s' is not a valid switch name.\n", switch_name);
}
drive.name = name;
drive.offset = offset;
drive.arch_switch_idx = switch_idx;
clock_network.drive = drive;
} else if (switch_type == "tap") {
t_clock_taps tap;
std::string name(get_attribute(curr_switch, "name", loc_data).value());
const char* offset;
const char* increment;
if (clock_network.type == e_clock_type::SPINE) {
expect_only_attributes(curr_switch, expected_spine_tap_attributes, loc_data);
offset = get_attribute(curr_switch, "yoffset", loc_data).value();
increment = get_attribute(curr_switch, "yincr", loc_data).value();
} else {
VTR_ASSERT(clock_network.type == e_clock_type::RIB);
expect_only_attributes(curr_switch, expected_rib_tap_attributes, loc_data);
offset = get_attribute(curr_switch, "xoffset", loc_data).value();
increment = get_attribute(curr_switch, "xincr", loc_data).value();
}
tap.name = name;
tap.offset = offset;
tap.increment = increment;
clock_network.tap = tap;
} else {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(curr_switch),
"Found unsupported switch type for '%s' clock network.\n"
"Currently there is only support for drive and tap switch types.\n",
clock_network.name.c_str());
}
curr_switch = curr_switch.next_sibling(curr_switch.name());
}
}
static void ProcessClockRouting(pugi::xml_node parent,
std::vector<t_clock_connection_arch>& clock_connections,
const t_arch_switch_inf* switches,
const int num_switches,
pugiutil::loc_data& loc_data) {
std::vector<std::string> expected_attributes = {"from", "to", "switch", "fc_val", "locationx", "locationy"};
pugi::xml_node clock_routing_parent = get_single_child(parent, "clock_routing", loc_data);
int num_routing_connections = count_children(clock_routing_parent, "tap", loc_data);
pugi::xml_node curr_connection = get_first_child(clock_routing_parent, "tap", loc_data);
for (int i = 0; i < num_routing_connections; i++) {
expect_only_attributes(curr_connection, expected_attributes, loc_data);
t_clock_connection_arch clock_connection;
const char* from = get_attribute(curr_connection, "from", loc_data).value();
const char* to = get_attribute(curr_connection, "to", loc_data).value();
const char* switch_name = get_attribute(curr_connection, "switch", loc_data).value();
const char* locationx = get_attribute(curr_connection, "locationx", loc_data, ReqOpt::OPTIONAL).value();
const char* locationy = get_attribute(curr_connection, "locationy", loc_data, ReqOpt::OPTIONAL).value();
float fc = get_attribute(curr_connection, "fc_val", loc_data).as_float(0.);
int switch_idx;
for (switch_idx = 0; switch_idx < num_switches; switch_idx++) {
if (0 == strcmp(switch_name, switches[switch_idx].name)) {
break; // switch_idx has been found
}
}
if (switch_idx >= num_switches) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(curr_connection),
"'%s' is not a valid switch name.\n", switch_name);
}
clock_connection.from = from;
clock_connection.to = to;
clock_connection.arch_switch_idx = switch_idx;
clock_connection.locationx = locationx;
clock_connection.locationy = locationy;
clock_connection.fc = fc;
clock_connections.push_back(clock_connection);
curr_connection = curr_connection.next_sibling(curr_connection.name());
}
}
static void ProcessPower(pugi::xml_node parent,
t_power_arch* power_arch,
const pugiutil::loc_data& loc_data) {
pugi::xml_node Cur;
/* Get the local interconnect capacitances */
power_arch->local_interc_factor = 0.5;
Cur = get_single_child(parent, "local_interconnect", loc_data, ReqOpt::OPTIONAL);
if (Cur) {
power_arch->C_wire_local = get_attribute(Cur, "C_wire", loc_data, ReqOpt::OPTIONAL).as_float(0.);
power_arch->local_interc_factor = get_attribute(Cur, "factor", loc_data, ReqOpt::OPTIONAL).as_float(0.5);
}
/* Get logical effort factor */
power_arch->logical_effort_factor = 4.0;
Cur = get_single_child(parent, "buffers", loc_data, ReqOpt::OPTIONAL);
if (Cur) {
power_arch->logical_effort_factor = get_attribute(Cur,
"logical_effort_factor", loc_data)
.as_float(0);
;
}
/* Get SRAM Size */
power_arch->transistors_per_SRAM_bit = 6.0;
Cur = get_single_child(parent, "sram", loc_data, ReqOpt::OPTIONAL);
if (Cur) {
power_arch->transistors_per_SRAM_bit = get_attribute(Cur,
"transistors_per_bit", loc_data)
.as_float(0);
}
/* Get Mux transistor size */
power_arch->mux_transistor_size = 1.0;
Cur = get_single_child(parent, "mux_transistor_size", loc_data, ReqOpt::OPTIONAL);
if (Cur) {
power_arch->mux_transistor_size = get_attribute(Cur,
"mux_transistor_size", loc_data)
.as_float(0);
}
/* Get FF size */
power_arch->FF_size = 1.0;
Cur = get_single_child(parent, "FF_size", loc_data, ReqOpt::OPTIONAL);
if (Cur) {
power_arch->FF_size = get_attribute(Cur, "FF_size", loc_data).as_float(0);
}
/* Get LUT transistor size */
power_arch->LUT_transistor_size = 1.0;
Cur = get_single_child(parent, "LUT_transistor_size", loc_data, ReqOpt::OPTIONAL);
if (Cur) {
power_arch->LUT_transistor_size = get_attribute(Cur,
"LUT_transistor_size", loc_data)
.as_float(0);
}
}
/* Get the clock architcture */
static void ProcessClocks(pugi::xml_node Parent, t_clock_arch* clocks, const pugiutil::loc_data& loc_data) {
pugi::xml_node Node;
int i;
const char* tmp;
clocks->num_global_clocks = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL);
/* Alloc the clockdetails */
clocks->clock_inf = nullptr;
if (clocks->num_global_clocks > 0) {
clocks->clock_inf = (t_clock_network*)vtr::malloc(clocks->num_global_clocks * sizeof(t_clock_network));
memset(clocks->clock_inf, 0,
clocks->num_global_clocks * sizeof(t_clock_network));
}
/* Load the clock info. */
Node = get_first_child(Parent, "clock", loc_data);
for (i = 0; i < clocks->num_global_clocks; ++i) {
tmp = get_attribute(Node, "buffer_size", loc_data).value();
if (strcmp(tmp, "auto") == 0) {
clocks->clock_inf[i].autosize_buffer = true;
} else {
clocks->clock_inf[i].autosize_buffer = false;
clocks->clock_inf[i].buffer_size = (float)atof(tmp);
}
clocks->clock_inf[i].C_wire = get_attribute(Node, "C_wire", loc_data).as_float(0);
/* get the next clock item */
Node = Node.next_sibling(Node.name());
}
}
/* Used by functions outside read_xml_util.c to gain access to arch filename */
const char* get_arch_file_name() {
return arch_file_name;
}
bool check_model_clocks(pugi::xml_node model_tag, const pugiutil::loc_data& loc_data, const t_model* model) {
//Collect the ports identified as clocks
std::set<std::string> clocks;
for (t_model_ports* ports : {model->inputs, model->outputs}) {
for (t_model_ports* port = ports; port != nullptr; port = port->next) {
if (port->is_clock) {
clocks.insert(port->name);
}
}
}
//Check that any clock references on the ports are to identified clock ports
for (t_model_ports* ports : {model->inputs, model->outputs}) {
for (t_model_ports* port = ports; port != nullptr; port = port->next) {
if (!port->clock.empty() && !clocks.count(port->clock)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(model_tag),
"No matching clock port '%s' on model '%s', required for port '%s'",
port->clock.c_str(), model->name, port->name);
}
}
}
return true;
}
bool check_model_combinational_sinks(pugi::xml_node model_tag, const pugiutil::loc_data& loc_data, const t_model* model) {
//Outputs should have no combinational sinks
for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) {
if (port->combinational_sink_ports.size() != 0) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(model_tag),
"Model '%s' output port '%s' can not have combinational sink ports",
model->name, port->name);
}
}
//Record the output ports
std::map<std::string, t_model_ports*> output_ports;
for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) {
output_ports.insert({port->name, port});
}
for (t_model_ports* port = model->inputs; port != nullptr; port = port->next) {
for (const std::string& sink_port_name : port->combinational_sink_ports) {
//Check that the input port combinational sinks are all outputs
if (!output_ports.count(sink_port_name)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(model_tag),
"Model '%s' input port '%s' can not be combinationally connected to '%s' (not an output port of the model)",
model->name, port->name, sink_port_name.c_str());
}
//Check that any output combinational sinks are not clocks
t_model_ports* sink_port = output_ports[sink_port_name];
VTR_ASSERT(sink_port);
if (sink_port->is_clock) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(model_tag),
"Model '%s' output port '%s' can not be both: a clock source (is_clock=\"%d\"),"
" and combinationally connected to input port '%s' (acting as a clock buffer).",
model->name, sink_port->name, sink_port->is_clock, port->name);
}
}
}
return true;
}
void warn_model_missing_timing(pugi::xml_node model_tag, const pugiutil::loc_data& loc_data, const t_model* model) {
//Check whether there are missing edges and warn the user
std::set<std::string> comb_connected_outputs;
for (t_model_ports* port = model->inputs; port != nullptr; port = port->next) {
if (port->clock.empty() //Not sequential
&& port->combinational_sink_ports.empty() //Doesn't drive any combinational outputs
&& !port->is_clock //Not an input clock
) {
VTR_LOGF_WARN(loc_data.filename_c_str(), loc_data.line(model_tag),
"Model '%s' input port '%s' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)\n", model->name, port->name);
}
comb_connected_outputs.insert(port->combinational_sink_ports.begin(), port->combinational_sink_ports.end());
}
for (t_model_ports* port = model->outputs; port != nullptr; port = port->next) {
if (port->clock.empty() //Not sequential
&& !comb_connected_outputs.count(port->name) //Not combinationally drivven
&& !port->is_clock //Not an output clock
) {
VTR_LOGF_WARN(loc_data.filename_c_str(), loc_data.line(model_tag),
"Model '%s' output port '%s' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)\n", model->name, port->name);
}
}
}
bool check_leaf_pb_model_timing_consistency(const t_pb_type* pb_type, const t_arch& arch) {
//Normalize the blif model name to match the model name
// by removing the leading '.' (.latch, .inputs, .names etc.)
// by removing the leading '.subckt'
VTR_ASSERT(pb_type->blif_model);
std::string blif_model = pb_type->blif_model;
std::string subckt = ".subckt ";
auto pos = blif_model.find(subckt);
if (pos != std::string::npos) {
blif_model = blif_model.substr(pos + subckt.size());
}
//Find the matching model
const t_model* model = nullptr;
for (const t_model* models : {arch.models, arch.model_library}) {
for (model = models; model != nullptr; model = model->next) {
if (std::string(model->name) == blif_model) {
break;
}
}
if (model != nullptr) {
break;
}
}
if (model == nullptr) {
archfpga_throw(get_arch_file_name(), -1,
"Unable to find model for blif_model '%s' found on pb_type '%s'",
blif_model.c_str(), pb_type->name);
}
//Now that we have the model we can compare the timing annotations
//Check from the pb_type's delay annotations match the model
//
// This ensures that the pb_types' delay annotations are consistent with the model
for (int i = 0; i < pb_type->num_annotations; ++i) {
const t_pin_to_pin_annotation* annot = &pb_type->annotations[i];
if (annot->type == E_ANNOT_PIN_TO_PIN_DELAY) {
//Check that any combinational delays specified match the 'combinational_sinks_ports' in the model
if (annot->clock) {
//Sequential annotation, check that the clock on the specified port matches the model
//Annotations always put the pin in the input_pins field
VTR_ASSERT(annot->input_pins);
for (const std::string& input_pin : vtr::split(annot->input_pins)) {
InstPort annot_port(input_pin);
for (const std::string& clock : vtr::split(annot->clock)) {
InstPort annot_clock(clock);
//Find the model port
const t_model_ports* model_port = nullptr;
for (const t_model_ports* ports : {model->inputs, model->outputs}) {
for (const t_model_ports* port = ports; port != nullptr; port = port->next) {
if (port->name == annot_port.port_name()) {
model_port = port;
break;
}
}
if (model_port != nullptr) break;
}
if (model_port == nullptr) {
archfpga_throw(get_arch_file_name(), annot->line_num,
"Failed to find port '%s' on '%s' for sequential delay annotation",
annot_port.port_name().c_str(), annot_port.instance_name().c_str());
}
//Check that the clock matches the model definition
std::string model_clock = model_port->clock;
if (model_clock.empty()) {
archfpga_throw(get_arch_file_name(), annot->line_num,
"<pb_type> timing-annotation/<model> mismatch on port '%s' of model '%s', model specifies"
" no clock but timing annotation specifies '%s'",
annot_port.port_name().c_str(), model->name, annot_clock.port_name().c_str());
}
if (model_port->clock != annot_clock.port_name()) {
archfpga_throw(get_arch_file_name(), annot->line_num,
"<pb_type> timing-annotation/<model> mismatch on port '%s' of model '%s', model specifies"
" clock as '%s' but timing annotation specifies '%s'",
annot_port.port_name().c_str(), model->name, model_clock.c_str(), annot_clock.port_name().c_str());
}
}
}
} else if (annot->input_pins && annot->output_pins) {
//Combinational annotation
VTR_ASSERT_MSG(!annot->clock, "Combinational annotations should have no clock");
for (const std::string& input_pin : vtr::split(annot->input_pins)) {
InstPort annot_in(input_pin);
for (const std::string& output_pin : vtr::split(annot->output_pins)) {
InstPort annot_out(output_pin);
//Find the input model port
const t_model_ports* model_port = nullptr;
for (const t_model_ports* port = model->inputs; port != nullptr; port = port->next) {
if (port->name == annot_in.port_name()) {
model_port = port;
break;
}
}
if (model_port == nullptr) {
archfpga_throw(get_arch_file_name(), annot->line_num,
"Failed to find port '%s' on '%s' for combinational delay annotation",
annot_in.port_name().c_str(), annot_in.instance_name().c_str());
}
//Check that the output port is listed in the model's combinational sinks
auto b = model_port->combinational_sink_ports.begin();
auto e = model_port->combinational_sink_ports.end();
auto iter = std::find(b, e, annot_out.port_name());
if (iter == e) {
archfpga_throw(get_arch_file_name(), annot->line_num,
"<pb_type> timing-annotation/<model> mismatch on port '%s' of model '%s', timing annotation"
" specifies combinational connection to port '%s' but the connection does not exist in the model",
model_port->name, model->name, annot_out.port_name().c_str());
}
}
}
} else {
throw ArchFpgaError("Unrecognized delay annotation");
}
}
}
//Build a list of combinationally connected sinks
std::set<std::string> comb_connected_outputs;
for (t_model_ports* model_ports : {model->inputs, model->outputs}) {
for (t_model_ports* model_port = model_ports; model_port != nullptr; model_port = model_port->next) {
comb_connected_outputs.insert(model_port->combinational_sink_ports.begin(), model_port->combinational_sink_ports.end());
}
}
//Check from the model to pb_type's delay annotations
//
// This ensures that the pb_type has annotations for all delays/values
// required by the model
for (t_model_ports* model_ports : {model->inputs, model->outputs}) {
for (t_model_ports* model_port = model_ports; model_port != nullptr; model_port = model_port->next) {
//If the model port has no timing specification don't check anything (e.g. architectures with no timing info)
if (model_port->clock.empty()
&& model_port->combinational_sink_ports.empty()
&& !comb_connected_outputs.count(model_port->name)) {
continue;
}
if (!model_port->clock.empty()) {
//Sequential port
if (model_port->dir == IN_PORT) {
//Sequential inputs must have a T_setup or T_hold
if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) == nullptr
&& find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) {
std::stringstream msg;
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
msg << " port '" << model_port->name << "' of model '" << model->name << "',";
msg << " port is a sequential input but has neither T_setup nor T_hold specified";
if (is_library_model(model)) {
//Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture)
VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str());
} else {
archfpga_throw(get_arch_file_name(), -1, msg.str().c_str());
}
}
if (!model_port->combinational_sink_ports.empty()) {
//Sequential input with internal combinational connectsion it must also have T_clock_to_Q
if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) == nullptr
&& find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) {
std::stringstream msg;
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
msg << " port '" << model_port->name << "' of model '" << model->name << "',";
msg << " port is a sequential input with internal combinational connects but has neither";
msg << " min nor max T_clock_to_Q specified";
if (is_library_model(model)) {
//Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture)
VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str());
} else {
archfpga_throw(get_arch_file_name(), -1, msg.str().c_str());
}
}
}
} else {
VTR_ASSERT(model_port->dir == OUT_PORT);
//Sequential outputs must have T_clock_to_Q
if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) == nullptr
&& find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN) == nullptr) {
std::stringstream msg;
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
msg << " port '" << model_port->name << "' of model '" << model->name << "',";
msg << " port is a sequential output but has neither min nor max T_clock_to_Q specified";
if (is_library_model(model)) {
//Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture)
VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str());
} else {
archfpga_throw(get_arch_file_name(), -1, msg.str().c_str());
}
}
if (comb_connected_outputs.count(model_port->name)) {
//Sequential output with internal combinational connectison must have T_setup/T_hold
if (find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) == nullptr
&& find_sequential_annotation(pb_type, model_port, E_ANNOT_PIN_TO_PIN_DELAY_THOLD) == nullptr) {
std::stringstream msg;
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
msg << " port '" << model_port->name << "' of model '" << model->name << "',";
msg << " port is a sequential output with internal combinational connections but has";
msg << " neither T_setup nor T_hold specified";
if (is_library_model(model)) {
//Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture)
VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str());
} else {
archfpga_throw(get_arch_file_name(), -1, msg.str().c_str());
}
}
}
}
}
//Check that combinationally connected inputs/outputs have combinational delays between them
if (model_port->dir == IN_PORT) {
for (const auto& sink_port : model_port->combinational_sink_ports) {
if (find_combinational_annotation(pb_type, model_port->name, sink_port) == nullptr) {
std::stringstream msg;
msg << "<pb_type> '" << pb_type->name << "' timing-annotation/<model> mismatch on";
msg << " port '" << model_port->name << "' of model '" << model->name << "',";
msg << " input port '" << model_port->name << "' has combinational connections to";
msg << " port '" << sink_port.c_str() << "'; specified in model, but no combinational delays found on pb_type";
if (is_library_model(model)) {
//Only warn if timing info is missing from a library model (e.g. .names/.latch on a non-timing architecture)
VTR_LOGF_WARN(get_arch_file_name(), -1, "%s\n", msg.str().c_str());
} else {
archfpga_throw(get_arch_file_name(), -1, msg.str().c_str());
}
}
}
}
}
}
return true;
}
const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* port, enum e_pin_to_pin_delay_annotations annot_type) {
VTR_ASSERT(annot_type == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP
|| annot_type == E_ANNOT_PIN_TO_PIN_DELAY_THOLD
|| annot_type == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX
|| annot_type == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN);
for (int iannot = 0; iannot < pb_type->num_annotations; ++iannot) {
const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot];
InstPort annot_in(annot->input_pins);
if (annot_in.port_name() == port->name) {
for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) {
if (annot->prop[iprop] == annot_type) {
return annot;
}
}
}
}
return nullptr;
}
const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string in_port, std::string out_port) {
for (int iannot = 0; iannot < pb_type->num_annotations; ++iannot) {
const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot];
for (const auto& annot_in_str : vtr::split(annot->input_pins)) {
InstPort in_pins(annot_in_str);
for (const auto& annot_out_str : vtr::split(annot->output_pins)) {
InstPort out_pins(annot_out_str);
if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
for (int iprop = 0; iprop < annot->num_value_prop_pairs; ++iprop) {
if (annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MAX
|| annot->prop[iprop] == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
return annot;
}
}
}
}
}
}
return nullptr;
}
std::string inst_port_to_port_name(std::string inst_port) {
auto pos = inst_port.find('.');
if (pos != std::string::npos) {
return inst_port.substr(pos + 1);
}
return inst_port;
}
static bool attribute_to_bool(const pugi::xml_node node,
const pugi::xml_attribute attr,
const pugiutil::loc_data& loc_data) {
if (attr.value() == std::string("1")) {
return true;
} else if (attr.value() == std::string("0")) {
return false;
} else {
bad_attribute_value(attr, node, loc_data, {"0", "1"});
}
return false;
}
int find_switch_by_name(const t_arch& arch, std::string switch_name) {
for (int iswitch = 0; iswitch < arch.num_switches; ++iswitch) {
const t_arch_switch_inf& arch_switch = arch.Switches[iswitch];
if (arch_switch.name == switch_name) {
return iswitch;
}
}
return OPEN;
}
e_side string_to_side(std::string side_str) {
e_side side = NUM_SIDES;
if (side_str.empty()) {
side = NUM_SIDES;
} else if (side_str == "left") {
side = LEFT;
} else if (side_str == "right") {
side = RIGHT;
} else if (side_str == "top") {
side = TOP;
} else if (side_str == "bottom") {
side = BOTTOM;
} else {
archfpga_throw(__FILE__, __LINE__,
"Invalid side specification");
}
return side;
}
static void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTileTypes,
std::vector<t_logical_block_type>& LogicalBlockTypes) {
for (auto& physical_tile : PhysicalTileTypes) {
if (physical_tile.index == EMPTY_TYPE_INDEX) continue;
auto eq_sites_set = get_equivalent_sites_set(&physical_tile);
auto equivalent_sites = std::vector<t_logical_block_type_ptr>(eq_sites_set.begin(), eq_sites_set.end());
auto criteria = [&physical_tile](const t_logical_block_type* lhs, const t_logical_block_type* rhs) {
int num_pins = physical_tile.num_inst_pins;
int lhs_num_logical_pins = lhs->pb_type->num_pins;
int rhs_num_logical_pins = rhs->pb_type->num_pins;
int lhs_diff_num_pins = num_pins - lhs_num_logical_pins;
int rhs_diff_num_pins = num_pins - rhs_num_logical_pins;
return lhs_diff_num_pins < rhs_diff_num_pins;
};
std::sort(equivalent_sites.begin(), equivalent_sites.end(), criteria);
for (auto& logical_block : LogicalBlockTypes) {
for (auto site : equivalent_sites) {
if (0 == strcmp(logical_block.name, site->pb_type->name)) {
logical_block.equivalent_tiles.push_back(&physical_tile);
break;
}
}
}
}
for (auto& logical_block : LogicalBlockTypes) {
if (logical_block.index == EMPTY_TYPE_INDEX) continue;
auto& equivalent_tiles = logical_block.equivalent_tiles;
if ((int)equivalent_tiles.size() <= 0) {
archfpga_throw(__FILE__, __LINE__,
"Logical Block %s does not have any equivalent tiles.\n", logical_block.name);
}
std::unordered_map<int, bool> ignored_pins_check_map;
std::unordered_map<int, bool> global_pins_check_map;
auto criteria = [&logical_block](const t_physical_tile_type* lhs, const t_physical_tile_type* rhs) {
int num_logical_pins = logical_block.pb_type->num_pins;
int lhs_num_pins = lhs->num_inst_pins;
int rhs_num_pins = rhs->num_inst_pins;
int lhs_diff_num_pins = lhs_num_pins - num_logical_pins;
int rhs_diff_num_pins = rhs_num_pins - num_logical_pins;
return lhs_diff_num_pins < rhs_diff_num_pins;
};
std::sort(equivalent_tiles.begin(), equivalent_tiles.end(), criteria);
for (int pin = 0; pin < logical_block.pb_type->num_pins; pin++) {
for (auto& tile : equivalent_tiles) {
auto direct_maps = tile->tile_block_pin_directs_map.at(logical_block.index);
for (auto& sub_tile : tile->sub_tiles) {
auto equiv_sites = sub_tile.equivalent_sites;
if (std::find(equiv_sites.begin(), equiv_sites.end(), &logical_block) == equiv_sites.end()) {
continue;
}
auto direct_map = direct_maps.at(sub_tile.index);
auto result = direct_map.find(t_logical_pin(pin));
if (result == direct_map.end()) {
archfpga_throw(__FILE__, __LINE__,
"Logical pin %d not present in pin mapping between Tile %s and Block %s.\n",
pin, tile->name, logical_block.name);
}
int sub_tile_pin_index = result->second.pin;
int phy_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index];
bool is_ignored = tile->is_ignored_pin[phy_index];
bool is_global = tile->is_pin_global[phy_index];
auto ignored_result = ignored_pins_check_map.insert(std::pair<int, bool>(pin, is_ignored));
if (!ignored_result.second && ignored_result.first->second != is_ignored) {
archfpga_throw(__FILE__, __LINE__,
"Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) "
"different from the corresponding pins of the other equivalent site %s\n.",
tile->name, phy_index, pin, logical_block.name);
}
auto global_result = global_pins_check_map.insert(std::pair<int, bool>(pin, is_global));
if (!global_result.second && global_result.first->second != is_global) {
archfpga_throw(__FILE__, __LINE__,
"Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) "
"different from the corresponding pins of the other equivalent sites\n.",
tile->name, phy_index, pin);
}
}
}
}
}
}
static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_tile* sub_tile, t_logical_block_type_ptr logical_block) {
auto pb_type = logical_block->pb_type;
if (pb_type->num_pins > (sub_tile->num_phy_pins / sub_tile->capacity.total())) {
archfpga_throw(__FILE__, __LINE__,
"Logical Block (%s) has more pins than the Sub Tile (%s).\n",
logical_block->name, sub_tile->name);
}
auto& pin_direct_maps = physical_tile->tile_block_pin_directs_map.at(logical_block->index);
auto pin_direct_map = pin_direct_maps.at(sub_tile->index);
if (pb_type->num_pins != (int)pin_direct_map.size()) {
archfpga_throw(__FILE__, __LINE__,
"Logical block (%s) and Sub tile (%s) have a different number of ports.\n",
logical_block->name, physical_tile->name);
}
for (auto pin_map : pin_direct_map) {
auto block_port = get_port_by_pin(logical_block, pin_map.first.pin);
auto sub_tile_port = get_port_by_pin(sub_tile, pin_map.second.pin);
VTR_ASSERT(block_port != nullptr);
VTR_ASSERT(sub_tile_port != nullptr);
if (sub_tile_port->type != block_port->type
|| sub_tile_port->num_pins != block_port->num_pins
|| sub_tile_port->equivalent != block_port->equivalent) {
archfpga_throw(__FILE__, __LINE__,
"Logical block (%s) and Physical tile (%s) do not have equivalent port specifications. Sub tile port %s, logical block port %s\n",
logical_block->name, sub_tile->name, sub_tile_port->name, block_port->name);
}
}
}
static const t_physical_tile_port* get_port_by_name(t_sub_tile* sub_tile, const char* port_name) {
for (auto port : sub_tile->ports) {
if (0 == strcmp(port.name, port_name)) {
return &sub_tile->ports[port.index];
}
}
return nullptr;
}
static const t_port* get_port_by_name(t_logical_block_type_ptr type, const char* port_name) {
auto pb_type = type->pb_type;
for (int i = 0; i < pb_type->num_ports; i++) {
auto port = pb_type->ports[i];
if (0 == strcmp(port.name, port_name)) {
return &pb_type->ports[port.index];
}
}
return nullptr;
}
static const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin) {
for (auto port : sub_tile->ports) {
if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) {
return &sub_tile->ports[port.index];
}
}
return nullptr;
}
static const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin) {
auto pb_type = type->pb_type;
for (int i = 0; i < pb_type->num_ports; i++) {
auto port = pb_type->ports[i];
if (pin >= port.absolute_first_pin_index && pin < port.absolute_first_pin_index + port.num_pins) {
return &pb_type->ports[port.index];
}
}
return nullptr;
}
template<typename T>
static T* get_type_by_name(const char* type_name, std::vector<T>& types) {
for (auto& type : types) {
if (0 == strcmp(type.name, type_name)) {
return &type;
}
}
archfpga_throw(__FILE__, __LINE__,
"Could not find type: %s\n", type_name);
}
|
if not defined @FSQRT
; Square root of floating-point number
; In: HL
; Out: HL = abs(HL)^0.5, reset carry
; Pollutes: AF
; Mantissas of square roots
; exp = 2*e
; (2^exp * mantisa)^0.5 = 2^e * mantisa^0.5
; exp = 2*e+1
; (2^exp * mantisa)^0.5 = 2^e * mantisa^0.5 * 2^0.5
; (2^-3 * mantisa)^0.5 = 2^-1 * 2^-0.5 * mantisa^0.5 = 2^-2 * 2^+0.5 ...
; (2^-2 * mantisa)^0.5 = 2^-1 * mantisa^0.5 = 2^-1 * ...
; (2^-1 * mantisa)^0.5 = 2^+0 * 2^-0.5 * mantisa^0.5 = 2^-1 * 2^+0.5 ...
; (2^+0 * mantisa)^0.5 = 2^+0 * mantisa^0.5 = 2^+0 * ...
; (2^+1 * mantisa)^0.5 = 2^+0 * 2^+0.5 * mantisa^0.5 = 2^+0 * 2^+0.5 ...
; (2^+2 * mantisa)^0.5 = 2^+1 * mantisa^0.5 = 2^+1 * ...
; (2^+3 * mantisa)^0.5 = 2^+1 * 2^+0.5 * mantisa^0.5 = 2^+1 * 2^+0.5 ...
@FSQRT:
if not defined FSQRT
; *****************************************
FSQRT ; *
; *****************************************
endif
SLA L ; 2:8 ABS(HL)
LD A, H ; 1:4
ADD A, BIAS ; 2:7
RRA ; 1:4 A = (exp-bias)/2 + bias = (exp+bias)/2
; carry => out = out * 2^0.5
RR L ; 2:8 RET with reset carry
LD H, SQR_TAB/256 ; 2:7
LD L, (HL) ; 1:7
LD H, A ; 1:4
RET ; 1:10
endif
|
//===- SymbolTable.cpp ----------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "SymbolTable.h"
#include "ConcatOutputSection.h"
#include "Config.h"
#include "InputFiles.h"
#include "InputSection.h"
#include "Symbols.h"
#include "SyntheticSections.h"
#include "lld/Common/ErrorHandler.h"
#include "lld/Common/Memory.h"
using namespace llvm;
using namespace lld;
using namespace lld::macho;
Symbol *SymbolTable::find(CachedHashStringRef cachedName) {
auto it = symMap.find(cachedName);
if (it == symMap.end())
return nullptr;
return symVector[it->second];
}
std::pair<Symbol *, bool> SymbolTable::insert(StringRef name,
const InputFile *file) {
auto p = symMap.insert({CachedHashStringRef(name), (int)symVector.size()});
Symbol *sym;
if (!p.second) {
// Name already present in the symbol table.
sym = symVector[p.first->second];
} else {
// Name is a new symbol.
sym = reinterpret_cast<Symbol *>(make<SymbolUnion>());
symVector.push_back(sym);
}
sym->isUsedInRegularObj |= !file || isa<ObjFile>(file);
return {sym, p.second};
}
Defined *SymbolTable::addDefined(StringRef name, InputFile *file,
InputSection *isec, uint64_t value,
uint64_t size, bool isWeakDef,
bool isPrivateExtern, bool isThumb,
bool isReferencedDynamically, bool noDeadStrip,
bool isWeakDefCanBeHidden) {
Symbol *s;
bool wasInserted;
bool overridesWeakDef = false;
std::tie(s, wasInserted) = insert(name, file);
assert(!isWeakDef || (isa<BitcodeFile>(file) && !isec) ||
(isa<ObjFile>(file) && file == isec->getFile()));
if (!wasInserted) {
if (auto *defined = dyn_cast<Defined>(s)) {
if (isWeakDef) {
// See further comment in createDefined() in InputFiles.cpp
if (defined->isWeakDef()) {
defined->privateExtern &= isPrivateExtern;
defined->weakDefCanBeHidden &= isWeakDefCanBeHidden;
defined->referencedDynamically |= isReferencedDynamically;
defined->noDeadStrip |= noDeadStrip;
}
// FIXME: Handle this for bitcode files.
if (auto concatIsec = dyn_cast_or_null<ConcatInputSection>(isec))
concatIsec->wasCoalesced = true;
return defined;
}
if (defined->isWeakDef()) {
// FIXME: Handle this for bitcode files.
if (auto concatIsec =
dyn_cast_or_null<ConcatInputSection>(defined->isec)) {
concatIsec->wasCoalesced = true;
concatIsec->symbols.erase(llvm::find(concatIsec->symbols, defined));
}
} else {
error("duplicate symbol: " + name + "\n>>> defined in " +
toString(defined->getFile()) + "\n>>> defined in " +
toString(file));
}
} else if (auto *dysym = dyn_cast<DylibSymbol>(s)) {
overridesWeakDef = !isWeakDef && dysym->isWeakDef();
dysym->unreference();
}
// Defined symbols take priority over other types of symbols, so in case
// of a name conflict, we fall through to the replaceSymbol() call below.
}
Defined *defined = replaceSymbol<Defined>(
s, name, file, isec, value, size, isWeakDef, /*isExternal=*/true,
isPrivateExtern, isThumb, isReferencedDynamically, noDeadStrip,
overridesWeakDef, isWeakDefCanBeHidden);
return defined;
}
Symbol *SymbolTable::addUndefined(StringRef name, InputFile *file,
bool isWeakRef) {
Symbol *s;
bool wasInserted;
std::tie(s, wasInserted) = insert(name, file);
RefState refState = isWeakRef ? RefState::Weak : RefState::Strong;
if (wasInserted)
replaceSymbol<Undefined>(s, name, file, refState);
else if (auto *lazy = dyn_cast<LazyArchive>(s))
lazy->fetchArchiveMember();
else if (auto *dynsym = dyn_cast<DylibSymbol>(s))
dynsym->reference(refState);
else if (auto *undefined = dyn_cast<Undefined>(s))
undefined->refState = std::max(undefined->refState, refState);
return s;
}
Symbol *SymbolTable::addCommon(StringRef name, InputFile *file, uint64_t size,
uint32_t align, bool isPrivateExtern) {
Symbol *s;
bool wasInserted;
std::tie(s, wasInserted) = insert(name, file);
if (!wasInserted) {
if (auto *common = dyn_cast<CommonSymbol>(s)) {
if (size < common->size)
return s;
} else if (isa<Defined>(s)) {
return s;
}
// Common symbols take priority over all non-Defined symbols, so in case of
// a name conflict, we fall through to the replaceSymbol() call below.
}
replaceSymbol<CommonSymbol>(s, name, file, size, align, isPrivateExtern);
return s;
}
Symbol *SymbolTable::addDylib(StringRef name, DylibFile *file, bool isWeakDef,
bool isTlv) {
Symbol *s;
bool wasInserted;
std::tie(s, wasInserted) = insert(name, file);
RefState refState = RefState::Unreferenced;
if (!wasInserted) {
if (auto *defined = dyn_cast<Defined>(s)) {
if (isWeakDef && !defined->isWeakDef())
defined->overridesWeakDef = true;
} else if (auto *undefined = dyn_cast<Undefined>(s)) {
refState = undefined->refState;
} else if (auto *dysym = dyn_cast<DylibSymbol>(s)) {
refState = dysym->getRefState();
}
}
bool isDynamicLookup = file == nullptr;
if (wasInserted || isa<Undefined>(s) ||
(isa<DylibSymbol>(s) &&
((!isWeakDef && s->isWeakDef()) ||
(!isDynamicLookup && cast<DylibSymbol>(s)->isDynamicLookup())))) {
if (auto *dynsym = dyn_cast<DylibSymbol>(s))
dynsym->unreference();
replaceSymbol<DylibSymbol>(s, file, name, isWeakDef, refState, isTlv);
}
return s;
}
Symbol *SymbolTable::addDynamicLookup(StringRef name) {
return addDylib(name, /*file=*/nullptr, /*isWeakDef=*/false, /*isTlv=*/false);
}
Symbol *SymbolTable::addLazyArchive(StringRef name, ArchiveFile *file,
const object::Archive::Symbol &sym) {
Symbol *s;
bool wasInserted;
std::tie(s, wasInserted) = insert(name, file);
if (wasInserted) {
replaceSymbol<LazyArchive>(s, file, sym);
} else if (isa<Undefined>(s)) {
file->fetch(sym);
} else if (auto *dysym = dyn_cast<DylibSymbol>(s)) {
if (dysym->isWeakDef()) {
if (dysym->getRefState() != RefState::Unreferenced)
file->fetch(sym);
else
replaceSymbol<LazyArchive>(s, file, sym);
}
}
return s;
}
Defined *SymbolTable::addSynthetic(StringRef name, InputSection *isec,
uint64_t value, bool isPrivateExtern,
bool includeInSymtab,
bool referencedDynamically) {
Defined *s =
addDefined(name, nullptr, isec, value, /*size=*/0,
/*isWeakDef=*/false, isPrivateExtern,
/*isThumb=*/false, referencedDynamically,
/*noDeadStrip=*/false, /*isWeakDefCanBeHidden=*/false);
s->includeInSymtab = includeInSymtab;
return s;
}
enum class Boundary {
Start,
End,
};
static Defined *createBoundarySymbol(const Undefined &sym) {
return symtab->addSynthetic(
sym.getName(), /*isec=*/nullptr, /*value=*/-1, /*isPrivateExtern=*/true,
/*includeInSymtab=*/false, /*referencedDynamically=*/false);
}
static void handleSectionBoundarySymbol(const Undefined &sym, StringRef segSect,
Boundary which) {
StringRef segName, sectName;
std::tie(segName, sectName) = segSect.split('$');
// Attach the symbol to any InputSection that will end up in the right
// OutputSection -- it doesn't matter which one we pick.
// Don't bother looking through inputSections for a matching
// ConcatInputSection -- we need to create ConcatInputSection for
// non-existing sections anyways, and that codepath works even if we should
// already have a ConcatInputSection with the right name.
OutputSection *osec = nullptr;
// This looks for __TEXT,__cstring etc.
for (SyntheticSection *ssec : syntheticSections)
if (ssec->segname == segName && ssec->name == sectName) {
osec = ssec->isec->parent;
break;
}
if (!osec) {
ConcatInputSection *isec = make<ConcatInputSection>(segName, sectName);
// This runs after markLive() and is only called for Undefineds that are
// live. Marking the isec live ensures an OutputSection is created that the
// start/end symbol can refer to.
assert(sym.isLive());
isec->live = true;
// This runs after gatherInputSections(), so need to explicitly set parent
// and add to inputSections.
osec = isec->parent = ConcatOutputSection::getOrCreateForInput(isec);
inputSections.push_back(isec);
}
if (which == Boundary::Start)
osec->sectionStartSymbols.push_back(createBoundarySymbol(sym));
else
osec->sectionEndSymbols.push_back(createBoundarySymbol(sym));
}
static void handleSegmentBoundarySymbol(const Undefined &sym, StringRef segName,
Boundary which) {
OutputSegment *seg = getOrCreateOutputSegment(segName);
if (which == Boundary::Start)
seg->segmentStartSymbols.push_back(createBoundarySymbol(sym));
else
seg->segmentEndSymbols.push_back(createBoundarySymbol(sym));
}
void lld::macho::treatUndefinedSymbol(const Undefined &sym, StringRef source) {
// Handle start/end symbols.
StringRef name = sym.getName();
if (name.consume_front("section$start$"))
return handleSectionBoundarySymbol(sym, name, Boundary::Start);
if (name.consume_front("section$end$"))
return handleSectionBoundarySymbol(sym, name, Boundary::End);
if (name.consume_front("segment$start$"))
return handleSegmentBoundarySymbol(sym, name, Boundary::Start);
if (name.consume_front("segment$end$"))
return handleSegmentBoundarySymbol(sym, name, Boundary::End);
// Handle -U.
if (config->explicitDynamicLookups.count(sym.getName())) {
symtab->addDynamicLookup(sym.getName());
return;
}
// Handle -undefined.
auto message = [source, &sym]() {
std::string message = "undefined symbol";
if (config->archMultiple)
message += (" for arch " + getArchitectureName(config->arch())).str();
message += ": " + toString(sym);
if (!source.empty())
message += "\n>>> referenced by " + source.str();
else
message += "\n>>> referenced by " + toString(sym.getFile());
return message;
};
switch (config->undefinedSymbolTreatment) {
case UndefinedSymbolTreatment::error:
error(message());
break;
case UndefinedSymbolTreatment::warning:
warn(message());
LLVM_FALLTHROUGH;
case UndefinedSymbolTreatment::dynamic_lookup:
case UndefinedSymbolTreatment::suppress:
symtab->addDynamicLookup(sym.getName());
break;
case UndefinedSymbolTreatment::unknown:
llvm_unreachable("unknown -undefined TREATMENT");
}
}
std::unique_ptr<SymbolTable> macho::symtab;
|
; A304376: a(n) = 60*2^n - 48 (n>=1).
; 72,192,432,912,1872,3792,7632,15312,30672,61392,122832,245712,491472,982992,1966032,3932112,7864272,15728592,31457232,62914512,125829072,251658192,503316432,1006632912,2013265872,4026531792,8053063632,16106127312,32212254672,64424509392,128849018832,257698037712,515396075472,1030792150992,2061584302032,4123168604112,8246337208272,16492674416592,32985348833232,65970697666512,131941395333072,263882790666192,527765581332432,1055531162664912,2111062325329872,4222124650659792,8444249301319632,16888498602639312,33776997205278672,67553994410557392,135107988821114832,270215977642229712,540431955284459472,1080863910568918992,2161727821137838032,4323455642275676112,8646911284551352272,17293822569102704592,34587645138205409232,69175290276410818512,138350580552821637072,276701161105643274192,553402322211286548432,1106804644422573096912,2213609288845146193872,4427218577690292387792,8854437155380584775632,17708874310761169551312,35417748621522339102672,70835497243044678205392,141670994486089356410832,283341988972178712821712,566683977944357425643472,1133367955888714851286992,2266735911777429702574032,4533471823554859405148112,9066943647109718810296272,18133887294219437620592592,36267774588438875241185232,72535549176877750482370512,145071098353755500964741072,290142196707511001929482192,580284393415022003858964432,1160568786830044007717928912,2321137573660088015435857872,4642275147320176030871715792,9284550294640352061743431632,18569100589280704123486863312,37138201178561408246973726672,74276402357122816493947453392,148552804714245632987894906832,297105609428491265975789813712,594211218856982531951579627472,1188422437713965063903159254992,2376844875427930127806318510032,4753689750855860255612637020112,9507379501711720511225274040272,19014759003423441022450548080592,38029518006846882044901096161232,76059036013693764089802192322512
mov $1,2
pow $1,$0
sub $1,1
mul $1,120
add $1,72
mov $0,$1
|
// Copyright (c) 2011-2018 The Worldcoin Core developers
// Distributed under the MIT software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
#include <test/data/base58_encode_decode.json.h>
#include <base58.h>
#include <test/test_worldcoin.h>
#include <utilstrencodings.h>
#include <univalue.h>
#include <boost/test/unit_test.hpp>
extern UniValue read_json(const std::string& jsondata);
BOOST_FIXTURE_TEST_SUITE(base58_tests, BasicTestingSetup)
// Goal: test low-level base58 encoding functionality
BOOST_AUTO_TEST_CASE(base58_EncodeBase58)
{
UniValue tests = read_json(std::string(json_tests::base58_encode_decode, json_tests::base58_encode_decode + sizeof(json_tests::base58_encode_decode)));
for (unsigned int idx = 0; idx < tests.size(); idx++) {
UniValue test = tests[idx];
std::string strTest = test.write();
if (test.size() < 2) // Allow for extra stuff (useful for comments)
{
BOOST_ERROR("Bad test: " << strTest);
continue;
}
std::vector<unsigned char> sourcedata = ParseHex(test[0].get_str());
std::string base58string = test[1].get_str();
BOOST_CHECK_MESSAGE(
EncodeBase58(sourcedata.data(), sourcedata.data() + sourcedata.size()) == base58string,
strTest);
}
}
// Goal: test low-level base58 decoding functionality
BOOST_AUTO_TEST_CASE(base58_DecodeBase58)
{
UniValue tests = read_json(std::string(json_tests::base58_encode_decode, json_tests::base58_encode_decode + sizeof(json_tests::base58_encode_decode)));
std::vector<unsigned char> result;
for (unsigned int idx = 0; idx < tests.size(); idx++) {
UniValue test = tests[idx];
std::string strTest = test.write();
if (test.size() < 2) // Allow for extra stuff (useful for comments)
{
BOOST_ERROR("Bad test: " << strTest);
continue;
}
std::vector<unsigned char> expected = ParseHex(test[0].get_str());
std::string base58string = test[1].get_str();
BOOST_CHECK_MESSAGE(DecodeBase58(base58string, result), strTest);
BOOST_CHECK_MESSAGE(result.size() == expected.size() && std::equal(result.begin(), result.end(), expected.begin()), strTest);
}
BOOST_CHECK(!DecodeBase58("invalid", result));
// check that DecodeBase58 skips whitespace, but still fails with unexpected non-whitespace at the end.
BOOST_CHECK(!DecodeBase58(" \t\n\v\f\r skip \r\f\v\n\t a", result));
BOOST_CHECK( DecodeBase58(" \t\n\v\f\r skip \r\f\v\n\t ", result));
std::vector<unsigned char> expected = ParseHex("971a55");
BOOST_CHECK_EQUAL_COLLECTIONS(result.begin(), result.end(), expected.begin(), expected.end());
}
BOOST_AUTO_TEST_SUITE_END()
|
; A060469: Smallest positive a(n) such that number of solutions to a(n) = a(j)+a(k) j<k<n is one or less.
; 1,2,3,4,6,8,11,13,16,18,23,25,28,30,35,37,40,42,47,49,52,54,59,61,64,66,71,73,76,78,83,85,88,90,95,97,100,102,107,109,112,114,119,121,124,126,131,133,136,138,143,145,148,150,155,157,160,162,167,169,172,174,179,181,184,186,191,193,196,198,203,205,208,210,215,217,220,222,227,229,232,234,239,241,244,246,251,253,256,258,263,265,268,270,275,277,280,282,287,289,292,294,299,301,304,306,311,313,316,318,323,325,328,330,335,337,340,342,347,349,352,354,359,361,364,366,371,373,376,378,383,385,388,390,395,397,400,402,407,409,412,414,419,421,424,426,431,433,436,438,443,445,448,450,455,457,460,462,467,469,472,474,479,481,484,486,491,493,496,498,503,505,508,510,515,517,520,522,527,529,532,534,539,541,544,546,551,553,556,558,563,565,568,570,575,577,580,582,587,589,592,594,599,601,604,606,611,613,616,618,623,625,628,630,635,637,640,642,647,649,652,654,659,661,664,666,671,673,676,678,683,685,688,690,695,697,700,702,707,709,712,714,719,721,724,726,731,733,736,738
mov $2,$0
add $2,1
mov $7,$0
lpb $2
mov $0,$7
sub $2,1
sub $0,$2
mov $4,$3
mov $5,$0
trn $5,5
trn $9,3
add $9,$5
lpb $0
add $4,$0
mov $0,4
sub $0,$9
trn $0,1
mov $3,5
mov $9,$4
gcd $9,4
mov $8,$9
mul $8,2
lpe
add $3,1
mov $6,$8
div $6,2
add $6,1
add $1,$6
lpe
|
; A039969: An example of a d-perfect sequence: a(n) = Catalan(n) mod 3.
; 1,1,2,2,2,0,0,0,2,2,2,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,1,1,1,0,0,0,1,1,1,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,1,1,1,0,0,0,1,1,1,2,2,2,0,0,0,0,0
add $0,1
seq $0,132328 ; a(n) = Product_{k>0} (1+floor(n/3^k)).
mod $0,3
|
; A074516: a(n) = 1^n + 5^n + 6^n.
; 3,12,62,342,1922,10902,62282,358062,2070242,12030822,70231802,411625182,2420922962,14281397142,84467679722,500702562702,2973697798082,17689598897862,105374653934042,628433226338622,3751525871703602,22413787798580982,134005889633282762,801651152008680942,4797985983097007522,28728311253806654502,172071844298962973882,1030940949674393077662,6178195117449434637842,37031917801711988686422,222005242295348836415402,1331100131197477539976782,7981944174311787847282562,47868381981505340120804742,287093876567205105910375322,1721981182794095961389986302,10328976713718902397978589682,61959308367085047536064897462,371683090626368450957356181642,2229734745877501534448971074222,13376589485861463350217996367202,80250441968151050818928827812582,481457177073817658501677214922362,2888515688767462718950584529768542,17329957264227560153406113379783122,103974059243479280118949711284558102,623815933751445276706263422736645482
mov $2,5
pow $2,$0
mov $1,$2
add $1,6
mov $3,6
pow $3,$0
add $1,$3
sub $1,5
mov $0,$1
|
extern real_routine
global disk_load_sector
global disk_write_sector
global read_drive_parameters
section .data
%define disk_load_sector_size disk_load_sector_end - disk_load_sector_bin
disk_load_sector_bin: incbin "blobs/disk_load_sector.bin"
disk_load_sector_end:
%define disk_write_sector_size disk_write_sector_end - disk_write_sector_bin
disk_write_sector_bin: incbin "blobs/disk_write_sector.bin"
disk_write_sector_end:
%define read_drive_parameters_size read_drive_parameters_end - read_drive_parameters_bin
read_drive_parameters_bin: incbin "blobs/read_drive_parameters.bin"
read_drive_parameters_end:
function_struct:
.source_sector_low dd 0
.source_sector_high dd 0
.target_address dd 0
.drive db 0
section .text
bits 32
disk_load_sector:
; void disk_load_sector(uint8_t drive, uint8_t* target_address, uint64_t source_sector);
push ebx
push esi
push edi
push ebp
; Prepare the struct
mov eax, dword [esp+32]
mov dword [function_struct.source_sector_high], eax
mov eax, dword [esp+28]
mov dword [function_struct.source_sector_low], eax
mov eax, dword [esp+24]
mov dword [function_struct.target_address], eax
mov eax, dword [esp+20]
mov byte [function_struct.drive], al
; Call real mode routine
mov ebx, function_struct
mov esi, disk_load_sector_bin
mov ecx, disk_load_sector_size
call real_routine
pop ebp
pop edi
pop esi
pop ebx
ret
disk_write_sector:
; void disk_load_sector(uint8_t drive, uint8_t* target_address, uint64_t source_sector);
push ebx
push esi
push edi
push ebp
; Prepare the struct
mov eax, dword [esp+32]
mov dword [function_struct.source_sector_high], eax
mov eax, dword [esp+28]
mov dword [function_struct.source_sector_low], eax
mov eax, dword [esp+24]
mov dword [function_struct.target_address], eax
mov eax, dword [esp+20]
mov byte [function_struct.drive], al
; Call real mode routine
mov ebx, function_struct
mov esi, disk_write_sector_bin
mov ecx, disk_write_sector_size
call real_routine
pop ebp
pop edi
pop esi
pop ebx
ret
read_drive_parameters:
; void read_drive_parameters(drive_parameters_t* struct);
push ebx
push esi
push edi
push ebp
; Call real mode routine
mov ebx, dword [esp+20]
mov esi, read_drive_parameters_bin
mov ecx, read_drive_parameters_size
call real_routine
pop ebp
pop edi
pop esi
pop ebx
ret
|
BITS 64
;TEST_FILE_META_BEGIN
;TEST_TYPE=TEST_F
;TEST_IGNOREFLAGS=
;TEST_FILE_META_END
; convert 1 to a double precision float and store in xmm0
mov ecx, 1
cvtsi2sd xmm0, ecx
;TEST_BEGIN_RECORDING
; load 2.5 (in double precision float form)
lea rcx, [rsp-8]
mov DWORD [rcx], 0
mov DWORD [rcx+4], 0x40040000
addsd xmm0, [rcx]
mov ecx, [rcx]
;TEST_END_RECORDING
xor ecx, ecx
cvtsi2sd xmm0, ecx
|
@ Allocate 2k buffer in OR[287]
0x0000 (0x000000) 0x101A- f:00010 d: 26 | A = 26 (0x001A)
0x0001 (0x000002) 0x292D- f:00024 d: 301 | OR[301] = A
0x0002 (0x000004) 0x111F- f:00010 d: 287 | A = 287 (0x011F)
0x0003 (0x000006) 0x292E- f:00024 d: 302 | OR[302] = A
0x0004 (0x000008) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x0005 (0x00000A) 0x5800- f:00054 d: 0 | B = A
0x0006 (0x00000C) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0007 (0x00000E) 0x7C09- f:00076 d: 9 | R = OR[9]
0x0008 (0x000010) 0x87AD- f:00103 d: 429 | P = P + 429 (0x01B5), A # 0
@ Allocate 24+42 WORDs of memory in OR[299]
0x0009 (0x000012) 0x1018- f:00010 d: 24 | A = 24 (0x0018)
0x000A (0x000014) 0x292D- f:00024 d: 301 | OR[301] = A
0x000B (0x000016) 0x1018- f:00010 d: 24 | A = 24 (0x0018)
0x000C (0x000018) 0x142A- f:00012 d: 42 | A = A + 42 (0x002A)
0x000D (0x00001A) 0x292E- f:00024 d: 302 | OR[302] = A
0x000E (0x00001C) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x000F (0x00001E) 0x292F- f:00024 d: 303 | OR[303] = A
0x0010 (0x000020) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0011 (0x000022) 0x2930- f:00024 d: 304 | OR[304] = A
0x0012 (0x000024) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0013 (0x000026) 0x2931- f:00024 d: 305 | OR[305] = A
0x0014 (0x000028) 0x112B- f:00010 d: 299 | A = 299 (0x012B)
0x0015 (0x00002A) 0x2932- f:00024 d: 306 | OR[306] = A
0x0016 (0x00002C) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x0017 (0x00002E) 0x5800- f:00054 d: 0 | B = A
0x0018 (0x000030) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0019 (0x000032) 0x7C09- f:00076 d: 9 | R = OR[9]
0x001A (0x000034) 0x8793- f:00103 d: 403 | P = P + 403 (0x01AD), A # 0
0x001B (0x000036) 0x212B- f:00020 d: 299 | A = OR[299]
0x001C (0x000038) 0x1418- f:00012 d: 24 | A = A + 24 (0x0018)
0x001D (0x00003A) 0x291E- f:00024 d: 286 | OR[286] = A
0x001E (0x00003C) 0x212B- f:00020 d: 299 | A = OR[299]
0x001F (0x00003E) 0x290E- f:00024 d: 270 | OR[270] = A
0x0020 (0x000040) 0x1018- f:00010 d: 24 | A = 24 (0x0018)
0x0021 (0x000042) 0x290D- f:00024 d: 269 | OR[269] = A
0x0022 (0x000044) 0x210D- f:00020 d: 269 | A = OR[269]
0x0023 (0x000046) 0x8406- f:00102 d: 6 | P = P + 6 (0x0029), A = 0
0x0024 (0x000048) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0025 (0x00004A) 0x390E- f:00034 d: 270 | (OR[270]) = A
0x0026 (0x00004C) 0x2F0D- f:00027 d: 269 | OR[269] = OR[269] - 1
0x0027 (0x00004E) 0x2D0E- f:00026 d: 270 | OR[270] = OR[270] + 1
0x0028 (0x000050) 0x7206- f:00071 d: 6 | P = P - 6 (0x0022)
0x0029 (0x000052) 0x2118- f:00020 d: 280 | A = OR[280]
0x002A (0x000054) 0x8402- f:00102 d: 2 | P = P + 2 (0x002C), A = 0
0x002B (0x000056) 0x7004- f:00070 d: 4 | P = P + 4 (0x002F)
0x002C (0x000058) 0x2047- f:00020 d: 71 | A = OR[71]
0x002D (0x00005A) 0x2918- f:00024 d: 280 | OR[280] = A
0x002E (0x00005C) 0x7012- f:00070 d: 18 | P = P + 18 (0x0040)
0x002F (0x00005E) 0x2118- f:00020 d: 280 | A = OR[280]
0x0030 (0x000060) 0x0808- f:00004 d: 8 | A = A > 8 (0x0008)
0x0031 (0x000062) 0x1630- f:00013 d: 48 | A = A - 48 (0x0030)
0x0032 (0x000064) 0x2918- f:00024 d: 280 | OR[280] = A
0x0033 (0x000066) 0x2118- f:00020 d: 280 | A = OR[280]
0x0034 (0x000068) 0x1603- f:00013 d: 3 | A = A - 3 (0x0003)
0x0035 (0x00006A) 0x8003- f:00100 d: 3 | P = P + 3 (0x0038), C = 0
0x0036 (0x00006C) 0x8402- f:00102 d: 2 | P = P + 2 (0x0038), A = 0
0x0037 (0x00006E) 0x7002- f:00070 d: 2 | P = P + 2 (0x0039)
0x0038 (0x000070) 0x7008- f:00070 d: 8 | P = P + 8 (0x0040)
0x0039 (0x000072) 0x7582- f:00072 d: 386 | R = P + 386 (0x01BB)
0x003A (0x000074) 0x1800-0x0285 f:00014 d: 0 | A = 645 (0x0285) @ String: 'IOP NOT CONFIGURED'
0x003C (0x000078) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x003D (0x00007A) 0x291A- f:00024 d: 282 | OR[282] = A
0x003E (0x00007C) 0x758B- f:00072 d: 395 | R = P + 395 (0x01C9)
0x003F (0x00007E) 0x7166- f:00070 d: 358 | P = P + 358 (0x01A5)
@ Call kernel function 43 - maybe load data overlay info (AMAP in this case)
0x0040 (0x000080) 0x102B- f:00010 d: 43 | A = 43 (0x002B)
0x0041 (0x000082) 0x292D- f:00024 d: 301 | OR[301] = A
0x0042 (0x000084) 0x1800-0x000B f:00014 d: 0 | A = 11 (0x000B)
0x0044 (0x000088) 0x292E- f:00024 d: 302 | OR[302] = A
0x0045 (0x00008A) 0x1126- f:00010 d: 294 | A = 294 (0x0126)
0x0046 (0x00008C) 0x292F- f:00024 d: 303 | OR[303] = A
0x0047 (0x00008E) 0x1127- f:00010 d: 295 | A = 295 (0x0127)
0x0048 (0x000090) 0x2930- f:00024 d: 304 | OR[304] = A
0x0049 (0x000092) 0x1125- f:00010 d: 293 | A = 293 (0x0125)
0x004A (0x000094) 0x2931- f:00024 d: 305 | OR[305] = A
0x004B (0x000096) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x004C (0x000098) 0x5800- f:00054 d: 0 | B = A
0x004D (0x00009A) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x004E (0x00009C) 0x7C09- f:00076 d: 9 | R = OR[9]
0x004F (0x00009E) 0x8756- f:00103 d: 342 | P = P + 342 (0x01A5), A # 0
@ Call kernel function 38 - maybe load from MOS
0x0050 (0x0000A0) 0x1026- f:00010 d: 38 | A = 38 (0x0026)
0x0051 (0x0000A2) 0x292D- f:00024 d: 301 | OR[301] = A
0x0052 (0x0000A4) 0x2126- f:00020 d: 294 | A = OR[294]
0x0053 (0x0000A6) 0x292E- f:00024 d: 302 | OR[302] = A
0x0054 (0x0000A8) 0x2127- f:00020 d: 295 | A = OR[295]
0x0055 (0x0000AA) 0x292F- f:00024 d: 303 | OR[303] = A
0x0056 (0x0000AC) 0x211F- f:00020 d: 287 | A = OR[287]
0x0057 (0x0000AE) 0x2930- f:00024 d: 304 | OR[304] = A
0x0058 (0x0000B0) 0x2125- f:00020 d: 293 | A = OR[293]
0x0059 (0x0000B2) 0x2931- f:00024 d: 305 | OR[305] = A
0x005A (0x0000B4) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x005B (0x0000B6) 0x2932- f:00024 d: 306 | OR[306] = A
0x005C (0x0000B8) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x005D (0x0000BA) 0x5800- f:00054 d: 0 | B = A
0x005E (0x0000BC) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x005F (0x0000BE) 0x7C09- f:00076 d: 9 | R = OR[9]
@ Call overlay STATS - statistics collection
0x0060 (0x0000C0) 0x1028- f:00010 d: 40 | A = 40 (0x0028)
0x0061 (0x0000C2) 0x292D- f:00024 d: 301 | OR[301] = A
0x0062 (0x0000C4) 0x1800-0x0039 f:00014 d: 0 | A = 57 (0x0039)
0x0064 (0x0000C8) 0x292E- f:00024 d: 302 | OR[302] = A
0x0065 (0x0000CA) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0066 (0x0000CC) 0x292F- f:00024 d: 303 | OR[303] = A
0x0067 (0x0000CE) 0x2118- f:00020 d: 280 | A = OR[280]
0x0068 (0x0000D0) 0x2930- f:00024 d: 304 | OR[304] = A
0x0069 (0x0000D2) 0x212B- f:00020 d: 299 | A = OR[299]
0x006A (0x0000D4) 0x2931- f:00024 d: 305 | OR[305] = A
0x006B (0x0000D6) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x006C (0x0000D8) 0x2932- f:00024 d: 306 | OR[306] = A
0x006D (0x0000DA) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x006E (0x0000DC) 0x2933- f:00024 d: 307 | OR[307] = A
0x006F (0x0000DE) 0x1006- f:00010 d: 6 | A = 6 (0x0006)
0x0070 (0x0000E0) 0x2934- f:00024 d: 308 | OR[308] = A
0x0071 (0x0000E2) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0072 (0x0000E4) 0x2935- f:00024 d: 309 | OR[309] = A
0x0073 (0x0000E6) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x0074 (0x0000E8) 0x5800- f:00054 d: 0 | B = A
0x0075 (0x0000EA) 0x1800-0x2B18 f:00014 d: 0 | A = 11032 (0x2B18)
0x0077 (0x0000EE) 0x7C09- f:00076 d: 9 | R = OR[9]
0x0078 (0x0000F0) 0x1800-0x0007 f:00014 d: 0 | A = 7 (0x0007)
0x007A (0x0000F4) 0x1404- f:00012 d: 4 | A = A + 4 (0x0004)
0x007B (0x0000F6) 0x251F- f:00022 d: 287 | A = A + OR[287] @ OR[287] is the 2k buffer
0x007C (0x0000F8) 0x2518- f:00022 d: 280 | A = A + OR[280]
0x007D (0x0000FA) 0x2921- f:00024 d: 289 | OR[289] = A
0x007E (0x0000FC) 0x3121- f:00030 d: 289 | A = (OR[289])
0x007F (0x0000FE) 0x2921- f:00024 d: 289 | OR[289] = A
0x0080 (0x000100) 0x8402- f:00102 d: 2 | P = P + 2 (0x0082), A = 0
0x0081 (0x000102) 0x700A- f:00070 d: 10 | P = P + 10 (0x008B)
0x0082 (0x000104) 0x7539- f:00072 d: 313 | R = P + 313 (0x01BB)
0x0083 (0x000106) 0x1800-0x0285 f:00014 d: 0 | A = 645 (0x0285)
0x0085 (0x00010A) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x0086 (0x00010C) 0x291A- f:00024 d: 282 | OR[282] = A
0x0087 (0x00010E) 0x1018- f:00010 d: 24 | A = 24 (0x0018)
0x0088 (0x000110) 0x291B- f:00024 d: 283 | OR[283] = A
0x0089 (0x000112) 0x7540- f:00072 d: 320 | R = P + 320 (0x01C9)
0x008A (0x000114) 0x711B- f:00070 d: 283 | P = P + 283 (0x01A5)
0x008B (0x000116) 0x2121- f:00020 d: 289 | A = OR[289]
0x008C (0x000118) 0x251F- f:00022 d: 287 | A = A + OR[287]
0x008D (0x00011A) 0x2921- f:00024 d: 289 | OR[289] = A
0x008E (0x00011C) 0x2118- f:00020 d: 280 | A = OR[280]
0x008F (0x00011E) 0x1430- f:00012 d: 48 | A = A + 48 (0x0030)
0x0090 (0x000120) 0x2928- f:00024 d: 296 | OR[296] = A
0x0091 (0x000122) 0x1004- f:00010 d: 4 | A = 4 (0x0004)
0x0092 (0x000124) 0x291B- f:00024 d: 283 | OR[283] = A
0x0093 (0x000126) 0x1800-0x0238 f:00014 d: 0 | A = 568 (0x0238)
0x0095 (0x00012A) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x0096 (0x00012C) 0x291D- f:00024 d: 285 | OR[285] = A
0x0097 (0x00012E) 0x755D- f:00072 d: 349 | R = P + 349 (0x01F4)
0x0098 (0x000130) 0x7523- f:00072 d: 291 | R = P + 291 (0x01BB)
0x0099 (0x000132) 0x1800-0x0238 f:00014 d: 0 | A = 568 (0x0238)
0x009B (0x000136) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x009C (0x000138) 0x291A- f:00024 d: 282 | OR[282] = A
0x009D (0x00013A) 0x1018- f:00010 d: 24 | A = 24 (0x0018)
0x009E (0x00013C) 0x291B- f:00024 d: 283 | OR[283] = A
0x009F (0x00013E) 0x752A- f:00072 d: 298 | R = P + 298 (0x01C9)
0x00A0 (0x000140) 0x751B- f:00072 d: 283 | R = P + 283 (0x01BB)
0x00A1 (0x000142) 0x7532- f:00072 d: 306 | R = P + 306 (0x01D3)
0x00A2 (0x000144) 0x1800-0x0243 f:00014 d: 0 | A = 579 (0x0243)
0x00A4 (0x000148) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x00A5 (0x00014A) 0x291A- f:00024 d: 282 | OR[282] = A
0x00A6 (0x00014C) 0x1005- f:00010 d: 5 | A = 5 (0x0005)
0x00A7 (0x00014E) 0x291B- f:00024 d: 283 | OR[283] = A
0x00A8 (0x000150) 0x7521- f:00072 d: 289 | R = P + 289 (0x01C9)
0x00A9 (0x000152) 0x7512- f:00072 d: 274 | R = P + 274 (0x01BB)
0x00AA (0x000154) 0x1800-0x0264 f:00014 d: 0 | A = 612 (0x0264)
0x00AC (0x000158) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x00AD (0x00015A) 0x291A- f:00024 d: 282 | OR[282] = A
0x00AE (0x00015C) 0x1005- f:00010 d: 5 | A = 5 (0x0005)
0x00AF (0x00015E) 0x291B- f:00024 d: 283 | OR[283] = A
0x00B0 (0x000160) 0x7519- f:00072 d: 281 | R = P + 281 (0x01C9)
0x00B1 (0x000162) 0x750A- f:00072 d: 266 | R = P + 266 (0x01BB)
0x00B2 (0x000164) 0x7521- f:00072 d: 289 | R = P + 289 (0x01D3)
0x00B3 (0x000166) 0x1006- f:00010 d: 6 | A = 6 (0x0006)
0x00B4 (0x000168) 0x2923- f:00024 d: 291 | OR[291] = A
0x00B5 (0x00016A) 0x2121- f:00020 d: 289 | A = OR[289]
0x00B6 (0x00016C) 0x1406- f:00012 d: 6 | A = A + 6 (0x0006)
0x00B7 (0x00016E) 0x2908- f:00024 d: 264 | OR[264] = A
0x00B8 (0x000170) 0x3108- f:00030 d: 264 | A = (OR[264])
0x00B9 (0x000172) 0x1401- f:00012 d: 1 | A = A + 1 (0x0001)
0x00BA (0x000174) 0x2924- f:00024 d: 292 | OR[292] = A
0x00BB (0x000176) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x00BC (0x000178) 0x2922- f:00024 d: 290 | OR[290] = A
0x00BD (0x00017A) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x00BE (0x00017C) 0x2929- f:00024 d: 297 | OR[297] = A
@ We have a large loop here
0x00BF (0x00017E) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x00C0 (0x000180) 0x292A- f:00024 d: 298 | OR[298] = A
0x00C1 (0x000182) 0x2124- f:00020 d: 292 | A = OR[292]
0x00C2 (0x000184) 0x251F- f:00022 d: 287 | A = A + OR[287] @ OR[287] is the 2k buffer
0x00C3 (0x000186) 0x2919- f:00024 d: 281 | OR[281] = A
0x00C4 (0x000188) 0x3119- f:00030 d: 281 | A = (OR[281])
0x00C5 (0x00018A) 0x2919- f:00024 d: 281 | OR[281] = A
0x00C6 (0x00018C) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x00C7 (0x00018E) 0x2920- f:00024 d: 288 | OR[288] = A
0x00C8 (0x000190) 0x2119- f:00020 d: 281 | A = OR[281]
0x00C9 (0x000192) 0x841F- f:00102 d: 31 | P = P + 31 (0x00E8), A = 0
0x00CA (0x000194) 0x2119- f:00020 d: 281 | A = OR[281]
0x00CB (0x000196) 0x0A01- f:00005 d: 1 | A = A < 1 (0x0001)
0x00CC (0x000198) 0x8002- f:00100 d: 2 | P = P + 2 (0x00CE), C = 0
0x00CD (0x00019A) 0x700A- f:00070 d: 10 | P = P + 10 (0x00D7)
0x00CE (0x00019C) 0x2119- f:00020 d: 281 | A = OR[281]
0x00CF (0x00019E) 0x1A00-0x3FFF f:00015 d: 0 | A = A & 16383 (0x3FFF)
0x00D1 (0x0001A2) 0x251F- f:00022 d: 287 | A = A + OR[287]
0x00D2 (0x0001A4) 0x2920- f:00024 d: 288 | OR[288] = A
0x00D3 (0x0001A6) 0x3120- f:00030 d: 288 | A = (OR[288])
0x00D4 (0x0001A8) 0x13FF- f:00011 d: 511 | A = A & 511 (0x01FF)
0x00D5 (0x0001AA) 0x2920- f:00024 d: 288 | OR[288] = A
0x00D6 (0x0001AC) 0x7012- f:00070 d: 18 | P = P + 18 (0x00E8)
0x00D7 (0x0001AE) 0x2119- f:00020 d: 281 | A = OR[281]
0x00D8 (0x0001B0) 0x13FF- f:00011 d: 511 | A = A & 511 (0x01FF)
0x00D9 (0x0001B2) 0x2920- f:00024 d: 288 | OR[288] = A
0x00DA (0x0001B4) 0x2119- f:00020 d: 281 | A = OR[281]
0x00DB (0x0001B6) 0x0809- f:00004 d: 9 | A = A > 9 (0x0009)
0x00DC (0x0001B8) 0x121F- f:00011 d: 31 | A = A & 31 (0x001F)
0x00DD (0x0001BA) 0x292A- f:00024 d: 298 | OR[298] = A
0x00DE (0x0001BC) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x00DF (0x0001BE) 0x292C- f:00024 d: 300 | OR[300] = A
0x00E0 (0x0001C0) 0x212A- f:00020 d: 298 | A = OR[298]
0x00E1 (0x0001C2) 0x160A- f:00013 d: 10 | A = A - 10 (0x000A)
0x00E2 (0x0001C4) 0x8006- f:00100 d: 6 | P = P + 6 (0x00E8), C = 0
0x00E3 (0x0001C6) 0x212A- f:00020 d: 298 | A = OR[298]
0x00E4 (0x0001C8) 0x160A- f:00013 d: 10 | A = A - 10 (0x000A)
0x00E5 (0x0001CA) 0x292A- f:00024 d: 298 | OR[298] = A
0x00E6 (0x0001CC) 0x2D2C- f:00026 d: 300 | OR[300] = OR[300] + 1
0x00E7 (0x0001CE) 0x7207- f:00071 d: 7 | P = P - 7 (0x00E0)
0x00E8 (0x0001D0) 0x2123- f:00020 d: 291 | A = OR[291]
0x00E9 (0x0001D2) 0x291A- f:00024 d: 282 | OR[282] = A
0x00EA (0x0001D4) 0x1005- f:00010 d: 5 | A = 5 (0x0005)
0x00EB (0x0001D6) 0x291B- f:00024 d: 283 | OR[283] = A
0x00EC (0x0001D8) 0x2129- f:00020 d: 297 | A = OR[297]
0x00ED (0x0001DA) 0x1601- f:00013 d: 1 | A = A - 1 (0x0001)
0x00EE (0x0001DC) 0x8603- f:00103 d: 3 | P = P + 3 (0x00F1), A # 0
0x00EF (0x0001DE) 0x1020- f:00010 d: 32 | A = 32 (0x0020)
0x00F0 (0x0001E0) 0x291B- f:00024 d: 283 | OR[283] = A
0x00F1 (0x0001E2) 0x7E03-0x021D f:00077 d: 3 | R = OR[3]+541 (0x021D)
0x00F3 (0x0001E6) 0x2120- f:00020 d: 288 | A = OR[288]
0x00F4 (0x0001E8) 0x8460- f:00102 d: 96 | P = P + 96 (0x0154), A = 0
0x00F5 (0x0001EA) 0x1002- f:00010 d: 2 | A = 2 (0x0002)
0x00F6 (0x0001EC) 0x2B1B- f:00025 d: 283 | OR[283] = A + OR[283]
0x00F7 (0x0001EE) 0x2123- f:00020 d: 291 | A = OR[291]
0x00F8 (0x0001F0) 0x1608- f:00013 d: 8 | A = A - 8 (0x0008)
0x00F9 (0x0001F2) 0x8202- f:00101 d: 2 | P = P + 2 (0x00FB), C = 1
0x00FA (0x0001F4) 0x2D1B- f:00026 d: 283 | OR[283] = OR[283] + 1
@ Load into OR[282] the address of the channel name string
0x00FB (0x0001F6) 0x1800-0x034E f:00014 d: 0 | A = 846 (0x034E) @ Pointer to peripheral name string pointer table
0x00FD (0x0001FA) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x00FE (0x0001FC) 0x2520- f:00022 d: 288 | A = A + OR[288]
0x00FF (0x0001FE) 0x2919- f:00024 d: 281 | OR[281] = A
0x0100 (0x000200) 0x3119- f:00030 d: 281 | A = (OR[281])
0x0101 (0x000202) 0x291A- f:00024 d: 282 | OR[282] = A
0x0102 (0x000204) 0x211A- f:00020 d: 282 | A = OR[282]
0x0103 (0x000206) 0x8402- f:00102 d: 2 | P = P + 2 (0x0105), A = 0
0x0104 (0x000208) 0x7005- f:00070 d: 5 | P = P + 5 (0x0109)
0x0105 (0x00020A) 0x103F- f:00010 d: 63 | A = 63 (0x003F)
0x0106 (0x00020C) 0x2928- f:00024 d: 296 | OR[296] = A
0x0107 (0x00020E) 0x74ED- f:00072 d: 237 | R = P + 237 (0x01F4)
0x0108 (0x000210) 0x7006- f:00070 d: 6 | P = P + 6 (0x010E)
0x0109 (0x000212) 0x211A- f:00020 d: 282 | A = OR[282]
0x010A (0x000214) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x010B (0x000216) 0x291A- f:00024 d: 282 | OR[282] = A
0x010C (0x000218) 0x7E03-0x0215 f:00077 d: 3 | R = OR[3]+533 (0x0215)
0x010E (0x00021C) 0x2120- f:00020 d: 288 | A = OR[288]
0x010F (0x00021E) 0x161F- f:00013 d: 31 | A = A - 31 (0x001F)
0x0110 (0x000220) 0x8405- f:00102 d: 5 | P = P + 5 (0x0115), A = 0
0x0111 (0x000222) 0x2120- f:00020 d: 288 | A = OR[288]
0x0112 (0x000224) 0x1620- f:00013 d: 32 | A = A - 32 (0x0020)
0x0113 (0x000226) 0x8402- f:00102 d: 2 | P = P + 2 (0x0115), A = 0
0x0114 (0x000228) 0x7004- f:00070 d: 4 | P = P + 4 (0x0118)
0x0115 (0x00022A) 0x1001- f:00010 d: 1 | A = 1 (0x0001)
0x0116 (0x00022C) 0x2913- f:00024 d: 275 | OR[275] = A
0x0117 (0x00022E) 0x7014- f:00070 d: 20 | P = P + 20 (0x012B)
0x0118 (0x000230) 0x2120- f:00020 d: 288 | A = OR[288]
0x0119 (0x000232) 0x161E- f:00013 d: 30 | A = A - 30 (0x001E)
0x011A (0x000234) 0x8405- f:00102 d: 5 | P = P + 5 (0x011F), A = 0
0x011B (0x000236) 0x2120- f:00020 d: 288 | A = OR[288]
0x011C (0x000238) 0x1622- f:00013 d: 34 | A = A - 34 (0x0022)
0x011D (0x00023A) 0x8402- f:00102 d: 2 | P = P + 2 (0x011F), A = 0
0x011E (0x00023C) 0x7004- f:00070 d: 4 | P = P + 4 (0x0122)
0x011F (0x00023E) 0x1001- f:00010 d: 1 | A = 1 (0x0001)
0x0120 (0x000240) 0x2913- f:00024 d: 275 | OR[275] = A
0x0121 (0x000242) 0x700A- f:00070 d: 10 | P = P + 10 (0x012B)
0x0122 (0x000244) 0x2120- f:00020 d: 288 | A = OR[288]
0x0123 (0x000246) 0x1625- f:00013 d: 37 | A = A - 37 (0x0025)
0x0124 (0x000248) 0x8402- f:00102 d: 2 | P = P + 2 (0x0126), A = 0
0x0125 (0x00024A) 0x7004- f:00070 d: 4 | P = P + 4 (0x0129)
0x0126 (0x00024C) 0x1001- f:00010 d: 1 | A = 1 (0x0001)
0x0127 (0x00024E) 0x2913- f:00024 d: 275 | OR[275] = A
0x0128 (0x000250) 0x7003- f:00070 d: 3 | P = P + 3 (0x012B)
0x0129 (0x000252) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x012A (0x000254) 0x2913- f:00024 d: 275 | OR[275] = A
0x012B (0x000256) 0x2113- f:00020 d: 275 | A = OR[275]
0x012C (0x000258) 0x1601- f:00013 d: 1 | A = A - 1 (0x0001)
0x012D (0x00025A) 0x8402- f:00102 d: 2 | P = P + 2 (0x012F), A = 0
0x012E (0x00025C) 0x7013- f:00070 d: 19 | P = P + 19 (0x0141)
0x012F (0x00025E) 0x212C- f:00020 d: 300 | A = OR[300]
0x0130 (0x000260) 0x8602- f:00103 d: 2 | P = P + 2 (0x0132), A # 0
0x0131 (0x000262) 0x7009- f:00070 d: 9 | P = P + 9 (0x013A)
0x0132 (0x000264) 0x211B- f:00020 d: 283 | A = OR[283]
0x0133 (0x000266) 0x1604- f:00013 d: 4 | A = A - 4 (0x0004)
0x0134 (0x000268) 0x291B- f:00024 d: 283 | OR[283] = A
0x0135 (0x00026A) 0x212C- f:00020 d: 300 | A = OR[300]
0x0136 (0x00026C) 0x1430- f:00012 d: 48 | A = A + 48 (0x0030)
0x0137 (0x00026E) 0x2928- f:00024 d: 296 | OR[296] = A
0x0138 (0x000270) 0x74BC- f:00072 d: 188 | R = P + 188 (0x01F4)
0x0139 (0x000272) 0x7004- f:00070 d: 4 | P = P + 4 (0x013D)
0x013A (0x000274) 0x211B- f:00020 d: 283 | A = OR[283]
0x013B (0x000276) 0x1603- f:00013 d: 3 | A = A - 3 (0x0003)
0x013C (0x000278) 0x291B- f:00024 d: 283 | OR[283] = A
0x013D (0x00027A) 0x212A- f:00020 d: 298 | A = OR[298]
0x013E (0x00027C) 0x1430- f:00012 d: 48 | A = A + 48 (0x0030)
0x013F (0x00027E) 0x2928- f:00024 d: 296 | OR[296] = A
0x0140 (0x000280) 0x74B4- f:00072 d: 180 | R = P + 180 (0x01F4)
0x0141 (0x000282) 0x1800-0x0CB9 f:00014 d: 0 | A = 3257 (0x0CB9)
0x0143 (0x000286) 0x2908- f:00024 d: 264 | OR[264] = A
0x0144 (0x000288) 0x2123- f:00020 d: 291 | A = OR[291]
0x0145 (0x00028A) 0x3708- f:00033 d: 264 | A = A - (OR[264])
0x0146 (0x00028C) 0x8402- f:00102 d: 2 | P = P + 2 (0x0148), A = 0
0x0147 (0x00028E) 0x700B- f:00070 d: 11 | P = P + 11 (0x0152)
0x0148 (0x000290) 0x2118- f:00020 d: 280 | A = OR[280]
0x0149 (0x000292) 0x2647- f:00023 d: 71 | A = A - OR[71]
0x014A (0x000294) 0x8402- f:00102 d: 2 | P = P + 2 (0x014C), A = 0
0x014B (0x000296) 0x7007- f:00070 d: 7 | P = P + 7 (0x0152)
0x014C (0x000298) 0x1020- f:00010 d: 32 | A = 32 (0x0020)
0x014D (0x00029A) 0x1601- f:00013 d: 1 | A = A - 1 (0x0001)
0x014E (0x00029C) 0x291B- f:00024 d: 283 | OR[283] = A
0x014F (0x00029E) 0x102A- f:00010 d: 42 | A = 42 (0x002A)
0x0150 (0x0002A0) 0x2928- f:00024 d: 296 | OR[296] = A
0x0151 (0x0002A2) 0x74A3- f:00072 d: 163 | R = P + 163 (0x01F4)
0x0152 (0x0002A4) 0x103B- f:00010 d: 59 | A = 59 (0x003B)
0x0153 (0x0002A6) 0x291B- f:00024 d: 283 | OR[283] = A
0x0154 (0x0002A8) 0x2129- f:00020 d: 297 | A = OR[297]
0x0155 (0x0002AA) 0x8402- f:00102 d: 2 | P = P + 2 (0x0157), A = 0
0x0156 (0x0002AC) 0x7009- f:00070 d: 9 | P = P + 9 (0x015F)
0x0157 (0x0002AE) 0x1001- f:00010 d: 1 | A = 1 (0x0001)
0x0158 (0x0002B0) 0x2929- f:00024 d: 297 | OR[297] = A
0x0159 (0x0002B2) 0x1012- f:00010 d: 18 | A = 18 (0x0012)
0x015A (0x0002B4) 0x2B23- f:00025 d: 291 | OR[291] = A + OR[291]
0x015B (0x0002B6) 0x1012- f:00010 d: 18 | A = 18 (0x0012)
0x015C (0x0002B8) 0x2B24- f:00025 d: 292 | OR[292] = A + OR[292]
0x015D (0x0002BA) 0x729E- f:00071 d: 158 | P = P - 158 (0x00BF)
0x015E (0x0002BC) 0x7003- f:00070 d: 3 | P = P + 3 (0x0161)
0x015F (0x0002BE) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0160 (0x0002C0) 0x2929- f:00024 d: 297 | OR[297] = A
0x0161 (0x0002C2) 0x1800-0x02B2 f:00014 d: 0 | A = 690 (0x02B2) @ Base address of resources name string pointer table)
0x0163 (0x0002C6) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x0164 (0x0002C8) 0x2522- f:00022 d: 290 | A = A + OR[290]
0x0165 (0x0002CA) 0x2913- f:00024 d: 275 | OR[275] = A
0x0166 (0x0002CC) 0x1800-0x02B8 f:00014 d: 0 | A = 696 (0x02B8) @ Base address of peripheral name table
0x0168 (0x0002D0) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x0169 (0x0002D2) 0x2908- f:00024 d: 264 | OR[264] = A
0x016A (0x0002D4) 0x2113- f:00020 d: 275 | A = OR[275]
0x016B (0x0002D6) 0x2708- f:00023 d: 264 | A = A - OR[264]
0x016C (0x0002D8) 0x822D- f:00101 d: 45 | P = P + 45 (0x0199), C = 1
0x016D (0x0002DA) 0x3113- f:00030 d: 275 | A = (OR[275])
0x016E (0x0002DC) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x016F (0x0002DE) 0x291A- f:00024 d: 282 | OR[282] = A
0x0170 (0x0002E0) 0x103B- f:00010 d: 59 | A = 59 (0x003B)
0x0171 (0x0002E2) 0x291B- f:00024 d: 283 | OR[283] = A
0x0172 (0x0002E4) 0x7E03-0x0215 f:00077 d: 3 | R = OR[3]+533 (0x0215)
0x0174 (0x0002E8) 0x1800-0x02B7 f:00014 d: 0 | A = 695 (0x02B7)
0x0176 (0x0002EC) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x0177 (0x0002EE) 0x2908- f:00024 d: 264 | OR[264] = A
0x0178 (0x0002F0) 0x2113- f:00020 d: 275 | A = OR[275]
0x0179 (0x0002F2) 0x2708- f:00023 d: 264 | A = A - OR[264]
0x017A (0x0002F4) 0x8002- f:00100 d: 2 | P = P + 2 (0x017C), C = 0
0x017B (0x0002F6) 0x7005- f:00070 d: 5 | P = P + 5 (0x0180)
0x017C (0x0002F8) 0x2121- f:00020 d: 289 | A = OR[289]
0x017D (0x0002FA) 0x2522- f:00022 d: 290 | A = A + OR[290]
0x017E (0x0002FC) 0x291A- f:00024 d: 282 | OR[282] = A
0x017F (0x0002FE) 0x700E- f:00070 d: 14 | P = P + 14 (0x018D)
0x0180 (0x000300) 0x1800-0x02B7 f:00014 d: 0 | A = 695 (0x02B7)
0x0182 (0x000304) 0x2403- f:00022 d: 3 | A = A + OR[3]
0x0183 (0x000306) 0x2908- f:00024 d: 264 | OR[264] = A
0x0184 (0x000308) 0x2113- f:00020 d: 275 | A = OR[275]
0x0185 (0x00030A) 0x2708- f:00023 d: 264 | A = A - OR[264]
0x0186 (0x00030C) 0x8402- f:00102 d: 2 | P = P + 2 (0x0188), A = 0
0x0187 (0x00030E) 0x7006- f:00070 d: 6 | P = P + 6 (0x018D)
0x0188 (0x000310) 0x212B- f:00020 d: 299 | A = OR[299]
0x0189 (0x000312) 0x1404- f:00012 d: 4 | A = A + 4 (0x0004)
0x018A (0x000314) 0x291A- f:00024 d: 282 | OR[282] = A
0x018B (0x000316) 0x1003- f:00010 d: 3 | A = 3 (0x0003)
0x018C (0x000318) 0x2B1A- f:00025 d: 282 | OR[282] = A + OR[282]
0x018D (0x00031A) 0x311A- f:00030 d: 282 | A = (OR[282])
0x018E (0x00031C) 0x291A- f:00024 d: 282 | OR[282] = A
0x018F (0x00031E) 0x1002- f:00010 d: 2 | A = 2 (0x0002)
0x0190 (0x000320) 0x2B1B- f:00025 d: 283 | OR[283] = A + OR[283]
0x0191 (0x000322) 0x7E03-0x021D f:00077 d: 3 | R = OR[3]+541 (0x021D)
0x0193 (0x000326) 0x2122- f:00020 d: 290 | A = OR[290]
0x0194 (0x000328) 0x8402- f:00102 d: 2 | P = P + 2 (0x0196), A = 0
0x0195 (0x00032A) 0x7004- f:00070 d: 4 | P = P + 4 (0x0199)
0x0196 (0x00032C) 0x104B- f:00010 d: 75 | A = 75 (0x004B)
0x0197 (0x00032E) 0x2928- f:00024 d: 296 | OR[296] = A
0x0198 (0x000330) 0x745C- f:00072 d: 92 | R = P + 92 (0x01F4)
0x0199 (0x000332) 0x743A- f:00072 d: 58 | R = P + 58 (0x01D3)
0x019A (0x000334) 0x2D22- f:00026 d: 290 | OR[290] = OR[290] + 1
0x019B (0x000336) 0x2123- f:00020 d: 291 | A = OR[291]
0x019C (0x000338) 0x1611- f:00013 d: 17 | A = A - 17 (0x0011)
0x019D (0x00033A) 0x2923- f:00024 d: 291 | OR[291] = A
0x019E (0x00033C) 0x2124- f:00020 d: 292 | A = OR[292]
0x019F (0x00033E) 0x1611- f:00013 d: 17 | A = A - 17 (0x0011)
0x01A0 (0x000340) 0x2924- f:00024 d: 292 | OR[292] = A
0x01A1 (0x000342) 0x741A- f:00072 d: 26 | R = P + 26 (0x01BB)
0x01A2 (0x000344) 0x2123- f:00020 d: 291 | A = OR[291]
0x01A3 (0x000346) 0x1618- f:00013 d: 24 | A = A - 24 (0x0018)
0x01A4 (0x000348) 0x8EE5- f:00107 d: 229 | P = P - 229 (0x00BF), A # 0
0x01A5 (0x00034A) 0x1019- f:00010 d: 25 | A = 25 (0x0019)
0x01A6 (0x00034C) 0x292D- f:00024 d: 301 | OR[301] = A
0x01A7 (0x00034E) 0x212B- f:00020 d: 299 | A = OR[299]
0x01A8 (0x000350) 0x292E- f:00024 d: 302 | OR[302] = A
0x01A9 (0x000352) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x01AA (0x000354) 0x5800- f:00054 d: 0 | B = A
0x01AB (0x000356) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x01AC (0x000358) 0x7C09- f:00076 d: 9 | R = OR[9]
@ Free buffer
0x01AD (0x00035A) 0x101B- f:00010 d: 27 | A = 27 (0x001B)
0x01AE (0x00035C) 0x292D- f:00024 d: 301 | OR[301] = A
0x01AF (0x00035E) 0x211F- f:00020 d: 287 | A = OR[287]
0x01B0 (0x000360) 0x292E- f:00024 d: 302 | OR[302] = A
0x01B1 (0x000362) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x01B2 (0x000364) 0x5800- f:00054 d: 0 | B = A
0x01B3 (0x000366) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x01B4 (0x000368) 0x7C09- f:00076 d: 9 | R = OR[9]
@ Return from overlay
0x01B5 (0x00036A) 0x102A- f:00010 d: 42 | A = 42 (0x002A)
0x01B6 (0x00036C) 0x292D- f:00024 d: 301 | OR[301] = A
0x01B7 (0x00036E) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x01B8 (0x000370) 0x5800- f:00054 d: 0 | B = A
0x01B9 (0x000372) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x01BA (0x000374) 0x7C09- f:00076 d: 9 | R = OR[9]
0x01BB (0x000376) 0x211E- f:00020 d: 286 | A = OR[286]
0x01BC (0x000378) 0x2919- f:00024 d: 281 | OR[281] = A
0x01BD (0x00037A) 0x211E- f:00020 d: 286 | A = OR[286]
0x01BE (0x00037C) 0x142A- f:00012 d: 42 | A = A + 42 (0x002A)
0x01BF (0x00037E) 0x2908- f:00024 d: 264 | OR[264] = A
0x01C0 (0x000380) 0x2119- f:00020 d: 281 | A = OR[281]
0x01C1 (0x000382) 0x2708- f:00023 d: 264 | A = A - OR[264]
0x01C2 (0x000384) 0x8406- f:00102 d: 6 | P = P + 6 (0x01C8), A = 0
0x01C3 (0x000386) 0x1800-0x2020 f:00014 d: 0 | A = 8224 (0x2020)
0x01C5 (0x00038A) 0x3919- f:00034 d: 281 | (OR[281]) = A
0x01C6 (0x00038C) 0x2D19- f:00026 d: 281 | OR[281] = OR[281] + 1
0x01C7 (0x00038E) 0x720A- f:00071 d: 10 | P = P - 10 (0x01BD)
0x01C8 (0x000390) 0x0200- f:00001 d: 0 | EXIT
0x01C9 (0x000392) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x01CA (0x000394) 0x291C- f:00024 d: 284 | OR[284] = A
0x01CB (0x000396) 0x211E- f:00020 d: 286 | A = OR[286]
0x01CC (0x000398) 0x291D- f:00024 d: 285 | OR[285] = A
0x01CD (0x00039A) 0x7413- f:00072 d: 19 | R = P + 19 (0x01E0)
0x01CE (0x00039C) 0x7426- f:00072 d: 38 | R = P + 38 (0x01F4)
0x01CF (0x00039E) 0x2128- f:00020 d: 296 | A = OR[296]
0x01D0 (0x0003A0) 0x8E03- f:00107 d: 3 | P = P - 3 (0x01CD), A # 0
0x01D1 (0x0003A2) 0x7402- f:00072 d: 2 | R = P + 2 (0x01D3)
0x01D2 (0x0003A4) 0x0200- f:00001 d: 0 | EXIT
0x01D3 (0x0003A6) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x01D4 (0x0003A8) 0x2928- f:00024 d: 296 | OR[296] = A
0x01D5 (0x0003AA) 0x741F- f:00072 d: 31 | R = P + 31 (0x01F4)
0x01D6 (0x0003AC) 0x1010- f:00010 d: 16 | A = 16 (0x0010)
0x01D7 (0x0003AE) 0x292D- f:00024 d: 301 | OR[301] = A
0x01D8 (0x0003B0) 0x211E- f:00020 d: 286 | A = OR[286]
0x01D9 (0x0003B2) 0x292E- f:00024 d: 302 | OR[302] = A
0x01DA (0x0003B4) 0x112D- f:00010 d: 301 | A = 301 (0x012D)
0x01DB (0x0003B6) 0x5800- f:00054 d: 0 | B = A
0x01DC (0x0003B8) 0x1800-0x2B18 f:00014 d: 0 | A = 11032 (0x2B18)
0x01DE (0x0003BC) 0x7C09- f:00076 d: 9 | R = OR[9]
0x01DF (0x0003BE) 0x0200- f:00001 d: 0 | EXIT
0x01E0 (0x0003C0) 0x211C- f:00020 d: 284 | A = OR[284]
0x01E1 (0x0003C2) 0x0801- f:00004 d: 1 | A = A > 1 (0x0001)
0x01E2 (0x0003C4) 0x251A- f:00022 d: 282 | A = A + OR[282]
0x01E3 (0x0003C6) 0x290D- f:00024 d: 269 | OR[269] = A
0x01E4 (0x0003C8) 0x310D- f:00030 d: 269 | A = (OR[269])
0x01E5 (0x0003CA) 0x290D- f:00024 d: 269 | OR[269] = A
0x01E6 (0x0003CC) 0x211C- f:00020 d: 284 | A = OR[284]
0x01E7 (0x0003CE) 0x1201- f:00011 d: 1 | A = A & 1 (0x0001)
0x01E8 (0x0003D0) 0x2908- f:00024 d: 264 | OR[264] = A
0x01E9 (0x0003D2) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x01EA (0x0003D4) 0x2708- f:00023 d: 264 | A = A - OR[264]
0x01EB (0x0003D6) 0x8604- f:00103 d: 4 | P = P + 4 (0x01EF), A # 0
0x01EC (0x0003D8) 0x210D- f:00020 d: 269 | A = OR[269]
0x01ED (0x0003DA) 0x0808- f:00004 d: 8 | A = A > 8 (0x0008)
0x01EE (0x0003DC) 0x290D- f:00024 d: 269 | OR[269] = A
0x01EF (0x0003DE) 0x210D- f:00020 d: 269 | A = OR[269]
0x01F0 (0x0003E0) 0x12FF- f:00011 d: 255 | A = A & 255 (0x00FF)
0x01F1 (0x0003E2) 0x2928- f:00024 d: 296 | OR[296] = A
0x01F2 (0x0003E4) 0x2D1C- f:00026 d: 284 | OR[284] = OR[284] + 1
0x01F3 (0x0003E6) 0x0200- f:00001 d: 0 | EXIT
0x01F4 (0x0003E8) 0x2128- f:00020 d: 296 | A = OR[296]
0x01F5 (0x0003EA) 0x12FF- f:00011 d: 255 | A = A & 255 (0x00FF)
0x01F6 (0x0003EC) 0x290D- f:00024 d: 269 | OR[269] = A
0x01F7 (0x0003EE) 0x211B- f:00020 d: 283 | A = OR[283]
0x01F8 (0x0003F0) 0x0801- f:00004 d: 1 | A = A > 1 (0x0001)
0x01F9 (0x0003F2) 0x251D- f:00022 d: 285 | A = A + OR[285]
0x01FA (0x0003F4) 0x290E- f:00024 d: 270 | OR[270] = A
0x01FB (0x0003F6) 0x211B- f:00020 d: 283 | A = OR[283]
0x01FC (0x0003F8) 0x1201- f:00011 d: 1 | A = A & 1 (0x0001)
0x01FD (0x0003FA) 0x2908- f:00024 d: 264 | OR[264] = A
0x01FE (0x0003FC) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x01FF (0x0003FE) 0x2708- f:00023 d: 264 | A = A - OR[264]
0x0200 (0x000400) 0xAE03-0x020E f:00127 d: 3 | P = OR[3]+526 (0x020E), A # 0
0x0202 (0x000404) 0x310E- f:00030 d: 270 | A = (OR[270])
0x0203 (0x000406) 0x0A09- f:00005 d: 9 | A = A < 9 (0x0009)
0x0204 (0x000408) 0x250D- f:00022 d: 269 | A = A + OR[269]
0x0205 (0x00040A) 0x0C09- f:00006 d: 9 | A = A >> 9 (0x0009)
0x0206 (0x00040C) 0x390E- f:00034 d: 270 | (OR[270]) = A
0x0207 (0x00040E) 0x7006- f:00070 d: 6 | P = P + 6 (0x020D)
0x0208 (0x000410) 0x310E- f:00030 d: 270 | A = (OR[270])
0x0209 (0x000412) 0x1A00-0xFF00 f:00015 d: 0 | A = A & 65280 (0xFF00)
0x020B (0x000416) 0x250D- f:00022 d: 269 | A = A + OR[269]
0x020C (0x000418) 0x390E- f:00034 d: 270 | (OR[270]) = A
0x020D (0x00041A) 0x2D1B- f:00026 d: 283 | OR[283] = OR[283] + 1
0x020E (0x00041C) 0x0200- f:00001 d: 0 | EXIT
0x020F (0x00041E) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0210 (0x000420) 0x291C- f:00024 d: 284 | OR[284] = A
0x0211 (0x000422) 0x7631- f:00073 d: 49 | R = P - 49 (0x01E0)
0x0212 (0x000424) 0x2128- f:00020 d: 296 | A = OR[296]
0x0213 (0x000426) 0x8602- f:00103 d: 2 | P = P + 2 (0x0215), A # 0
0x0214 (0x000428) 0x0200- f:00001 d: 0 | EXIT
0x0215 (0x00042A) 0x7621- f:00073 d: 33 | R = P - 33 (0x01F4)
0x0216 (0x00042C) 0x7205- f:00071 d: 5 | P = P - 5 (0x0211)
0x0217 (0x00042E) 0x1000- f:00010 d: 0 | A = 0 (0x0000)
0x0218 (0x000430) 0x2919- f:00024 d: 281 | OR[281] = A
0x0219 (0x000432) 0x1012- f:00010 d: 18 | A = 18 (0x0012)
0x021A (0x000434) 0x5800- f:00054 d: 0 | B = A
0x021B (0x000436) 0x5000- f:00050 d: 0 | A = B
0x021C (0x000438) 0x1603- f:00013 d: 3 | A = A - 3 (0x0003)
0x021D (0x00043A) 0x5800- f:00054 d: 0 | B = A
0x021E (0x00043C) 0x211A- f:00020 d: 282 | A = OR[282]
0x021F (0x00043E) 0x4800- f:00044 d: 0 | A = A > B
0x0220 (0x000440) 0x1207- f:00011 d: 7 | A = A & 7 (0x0007)
0x0221 (0x000442) 0x1430- f:00012 d: 48 | A = A + 48 (0x0030)
0x0222 (0x000444) 0x2928- f:00024 d: 296 | OR[296] = A
0x0223 (0x000446) 0x2119- f:00020 d: 281 | A = OR[281]
0x0224 (0x000448) 0x8402- f:00102 d: 2 | P = P + 2 (0x0226), A = 0
0x0225 (0x00044A) 0x7007- f:00070 d: 7 | P = P + 7 (0x022C)
0x0226 (0x00044C) 0x2128- f:00020 d: 296 | A = OR[296]
0x0227 (0x00044E) 0x1630- f:00013 d: 48 | A = A - 48 (0x0030)
0x0228 (0x000450) 0x8402- f:00102 d: 2 | P = P + 2 (0x022A), A = 0
0x0229 (0x000452) 0x7003- f:00070 d: 3 | P = P + 3 (0x022C)
0x022A (0x000454) 0x5000- f:00050 d: 0 | A = B
0x022B (0x000456) 0x8E10- f:00107 d: 16 | P = P - 16 (0x021B), A # 0
0x022C (0x000458) 0x1001- f:00010 d: 1 | A = 1 (0x0001)
0x022D (0x00045A) 0x2919- f:00024 d: 281 | OR[281] = A
0x022E (0x00045C) 0x763A- f:00073 d: 58 | R = P - 58 (0x01F4)
0x022F (0x00045E) 0x5000- f:00050 d: 0 | A = B
0x0230 (0x000460) 0x8E15- f:00107 d: 21 | P = P - 21 (0x021B), A # 0
0x0231 (0x000462) 0x0200- f:00001 d: 0 | EXIT
0x0232 (0x000464) 0x494F - string 'IOP-0 CONFIGURATION'
0x0233 (0x000466) 0x502D
0x0234 (0x000468) 0x3020
0x0235 (0x00046A) 0x434F
0x0236 (0x00046C) 0x4E46
0x0237 (0x00046E) 0x4947
0x0238 (0x000470) 0x5552
0x0239 (0x000472) 0x4154
0x023A (0x000474) 0x494F
0x023B (0x000476) 0x4E20
0x023C (0x000478) 0x0000
0x023D (0x00047A) 0x4348 - string 'CHANNEL (ORD)'
0x023E (0x00047C) 0x414E
0x023F (0x00047E) 0x4E45
0x0240 (0x000480) 0x4C20
0x0241 (0x000482) 0x284F
0x0242 (0x000484) 0x5244
0x0243 (0x000486) 0x2920
0x0244 (0x000488) 0x2020
0x0245 (0x00048A) 0x2020
0x0246 (0x00048C) 0x2020
0x0247 (0x00048E) 0x2020
0x0248 (0x000490) 0x2020
0x0249 (0x000492) 0x2020
0x024A (0x000494) 0x2043
0x024B (0x000496) 0x4841
0x024C (0x000498) 0x4E4E
0x024D (0x00049A) 0x454C
0x024E (0x00049C) 0x2028
0x024F (0x00049E) 0x4F52
0x0250 (0x0004A0) 0x4429
0x0251 (0x0004A2) 0x2020
0x0252 (0x0004A4) 0x2020
0x0253 (0x0004A6) 0x2020
0x0254 (0x0004A8) 0x2020
0x0255 (0x0004AA) 0x2020
0x0256 (0x0004AC) 0x2020
0x0257 (0x0004AE) 0x2020
0x0258 (0x0004B0) 0x5245
0x0259 (0x0004B2) 0x534F
0x025A (0x0004B4) 0x5552
0x025B (0x0004B6) 0x4345
0x025C (0x0004B8) 0x5320
0x025D (0x0004BA) 0x0000
0x025E (0x0004BC) 0x2D2D
0x025F (0x0004BE) 0x2D2D
0x0260 (0x0004C0) 0x2D2D
0x0261 (0x0004C2) 0x2D2D
0x0262 (0x0004C4) 0x2D2D
0x0263 (0x0004C6) 0x2D2D
0x0264 (0x0004C8) 0x2D20
0x0265 (0x0004CA) 0x2020
0x0266 (0x0004CC) 0x2020
0x0267 (0x0004CE) 0x2020
0x0268 (0x0004D0) 0x2020
0x0269 (0x0004D2) 0x2020
0x026A (0x0004D4) 0x2020
0x026B (0x0004D6) 0x202D
0x026C (0x0004D8) 0x2D2D
0x026D (0x0004DA) 0x2D2D
0x026E (0x0004DC) 0x2D2D
0x026F (0x0004DE) 0x2D2D
0x0270 (0x0004E0) 0x2D2D
0x0271 (0x0004E2) 0x2D2D
0x0272 (0x0004E4) 0x2020
0x0273 (0x0004E6) 0x2020
0x0274 (0x0004E8) 0x2020
0x0275 (0x0004EA) 0x2020
0x0276 (0x0004EC) 0x2020
0x0277 (0x0004EE) 0x2020
0x0278 (0x0004F0) 0x2020
0x0279 (0x0004F2) 0x2D2D
0x027A (0x0004F4) 0x2D2D
0x027B (0x0004F6) 0x2D2D
0x027C (0x0004F8) 0x2D2D
0x027D (0x0004FA) 0x2D20
0x027E (0x0004FC) 0x0000
0x027F (0x0004FE) 0x494F - string 'IOP NOT CONFIGURED'
0x0280 (0x000500) 0x5020
0x0281 (0x000502) 0x4E4F
0x0282 (0x000504) 0x5420
0x0283 (0x000506) 0x434F
0x0284 (0x000508) 0x4E46
0x0285 (0x00050A) 0x4947
0x0286 (0x00050C) 0x5552
0x0287 (0x00050E) 0x4544
0x0288 (0x000510) 0x0000
0x0289 (0x000512) 0x4D4F - string 'MOS SIZE'
0x028A (0x000514) 0x5320
0x028B (0x000516) 0x5349
0x028C (0x000518) 0x5A45
0x028D (0x00051A) 0x0000
0x028E (0x00051C) 0x4449 - string 'DISK BUFFERS'
0x028F (0x00051E) 0x534B
0x0290 (0x000520) 0x2042
0x0291 (0x000522) 0x5546
0x0292 (0x000524) 0x4645
0x0293 (0x000526) 0x5253
0x0294 (0x000528) 0x0000
0x0295 (0x00052A) 0x534D - string 'SMODS'
0x0296 (0x00052C) 0x4F44
0x0297 (0x00052E) 0x5320
0x0298 (0x000530) 0x0000
0x0299 (0x000532) 0x4F56 - string 'OVL SPACE'
0x029A (0x000534) 0x4C20
0x029B (0x000536) 0x5350
0x029C (0x000538) 0x4143
0x029D (0x00053A) 0x4520
0x029E (0x00053C) 0x0000
0x029F (0x00053E) 0x4441 - string 'DAL COUNT'
0x02A0 (0x000540) 0x4C20
0x02A1 (0x000542) 0x434F
0x02A2 (0x000544) 0x554E
0x02A3 (0x000546) 0x5420
0x02A4 (0x000548) 0x0000
0x02A5 (0x00054A) 0x4652 - string 'FREE MEMORY'
0x02A6 (0x00054C) 0x4545
0x02A7 (0x00054E) 0x204D
0x02A8 (0x000550) 0x454D
0x02A9 (0x000552) 0x4F52
0x02AA (0x000554) 0x5920
0x02AB (0x000556) 0x0000
0x02AC (0x000558) 0x028F - pointer to string 'MOS SIZE'
0x02AD (0x00055A) 0x0294 - pointer to string 'DISK BUFFERS'
0x02AE (0x00055C) 0x029B - pointer to string 'SMODS'
0x02AF (0x00055E) 0x029F - pointer to string 'OVL SPACE'
0x02B0 (0x000560) 0x02A5 - pointer to string 'DAL COUNT'
0x02B1 (0x000562) 0x02AB - pointer to string 'FREE MEMORY'
0x02B2 (0x000564) 0x4444 - string 'DD-19'
0x02B3 (0x000566) 0x2D31
0x02B4 (0x000568) 0x3920
0x02B5 (0x00056A) 0x0000
0x02B6 (0x00056C) 0x4444 - string 'DD-29'
0x02B7 (0x00056E) 0x2D32
0x02B8 (0x000570) 0x3920
0x02B9 (0x000572) 0x0000
0x02BA (0x000574) 0x4558
0x02BB (0x000576) 0x5041
0x02BC (0x000578) 0x4E44
0x02BD (0x00057A) 0x4552
0x02BE (0x00057C) 0x0000
0x02BF (0x00057E) 0x5445
0x02C0 (0x000580) 0x4320
0x02C1 (0x000582) 0x3435
0x02C2 (0x000584) 0x3520
0x02C3 (0x000586) 0x0000
0x02C4 (0x000588) 0x5445
0x02C5 (0x00058A) 0x4320
0x02C6 (0x00058C) 0x3134
0x02C7 (0x00058E) 0x3430
0x02C8 (0x000590) 0x0000
0x02C9 (0x000592) 0x534F
0x02CA (0x000594) 0x524F
0x02CB (0x000596) 0x4320
0x02CC (0x000598) 0x0000
0x02CD (0x00059A) 0x494F
0x02CE (0x00059C) 0x5030
0x02CF (0x00059E) 0x2041
0x02D0 (0x0005A0) 0x2D3E
0x02D1 (0x0005A2) 0x4120
0x02D2 (0x0005A4) 0x0000
0x02D3 (0x0005A6) 0x494F
0x02D4 (0x0005A8) 0x5031
0x02D5 (0x0005AA) 0x2041
0x02D6 (0x0005AC) 0x2D3E
0x02D7 (0x0005AE) 0x4120
0x02D8 (0x0005B0) 0x0000
0x02D9 (0x0005B2) 0x494F
0x02DA (0x0005B4) 0x5032
0x02DB (0x0005B6) 0x2041
0x02DC (0x0005B8) 0x2D3E
0x02DD (0x0005BA) 0x4120
0x02DE (0x0005BC) 0x0000
0x02DF (0x0005BE) 0x494F
0x02E0 (0x0005C0) 0x5033
0x02E1 (0x0005C2) 0x2041
0x02E2 (0x0005C4) 0x2D3E
0x02E3 (0x0005C6) 0x4120
0x02E4 (0x0005C8) 0x0000
0x02E5 (0x0005CA) 0x4352
0x02E6 (0x0005CC) 0x4159
0x02E7 (0x0005CE) 0x2035
0x02E8 (0x0005D0) 0x304D
0x02E9 (0x0005D2) 0x4220
0x02EA (0x0005D4) 0x0000
0x02EB (0x0005D6) 0x4352
0x02EC (0x0005D8) 0x4159
0x02ED (0x0005DA) 0x2038
0x02EE (0x0005DC) 0x3530
0x02EF (0x0005DE) 0x4D42
0x02F0 (0x0005E0) 0x0000
0x02F1 (0x0005E2) 0x4853
0x02F2 (0x0005E4) 0x5820
0x02F3 (0x0005E6) 0x0000
0x02F4 (0x0005E8) 0x434F
0x02F5 (0x0005EA) 0x4E43
0x02F6 (0x0005EC) 0x2028
0x02F7 (0x0005EE) 0x2020
0x02F8 (0x0005F0) 0x2920
0x02F9 (0x0005F2) 0x0000
0x02FA (0x0005F4) 0x4552
0x02FB (0x0005F6) 0x524F
0x02FC (0x0005F8) 0x5220
0x02FD (0x0005FA) 0x4C4F
0x02FE (0x0005FC) 0x4720
0x02FF (0x0005FE) 0x0000
0x0300 (0x000600) 0x414D
0x0301 (0x000602) 0x5045
0x0302 (0x000604) 0x5820
0x0303 (0x000606) 0x3830
0x0304 (0x000608) 0x0000
0x0305 (0x00060A) 0x4E53
0x0306 (0x00060C) 0x4320
0x0307 (0x00060E) 0x2028
0x0308 (0x000610) 0x2020
0x0309 (0x000612) 0x2920
0x030A (0x000614) 0x0000
0x030B (0x000616) 0x4444
0x030C (0x000618) 0x2D34
0x030D (0x00061A) 0x3920
0x030E (0x00061C) 0x0000
0x030F (0x00061E) 0x5543
0x0310 (0x000620) 0x484E
0x0311 (0x000622) 0x0000
0x0312 (0x000624) 0x4444
0x0313 (0x000626) 0x2D33
0x0314 (0x000628) 0x3920
0x0315 (0x00062A) 0x0000
0x0316 (0x00062C) 0x4444
0x0317 (0x00062E) 0x2D35
0x0318 (0x000630) 0x3020
0x0319 (0x000632) 0x0000
0x031A (0x000634) 0x4645
0x031B (0x000636) 0x492D
0x031C (0x000638) 0x4C50
0x031D (0x00063A) 0x0000
0x031E (0x00063C) 0x564D
0x031F (0x00063E) 0x4520
0x0320 (0x000640) 0x2028
0x0321 (0x000642) 0x2020
0x0322 (0x000644) 0x2920
0x0323 (0x000646) 0x0000
0x0324 (0x000648) 0x4444
0x0325 (0x00064A) 0x2D34
0x0326 (0x00064C) 0x3020
0x0327 (0x00064E) 0x0000
0x0328 (0x000650) 0x4444
0x0329 (0x000652) 0x2D31
0x032A (0x000654) 0x3953
0x032B (0x000656) 0x0000
0x032C (0x000658) 0x4444
0x032D (0x00065A) 0x2D32
0x032E (0x00065C) 0x3953
0x032F (0x00065E) 0x0000
0x0330 (0x000660) 0x4444
0x0331 (0x000662) 0x2D33
0x0332 (0x000664) 0x3953
0x0333 (0x000666) 0x0000
0x0334 (0x000668) 0x4444
0x0335 (0x00066A) 0x2D34
0x0336 (0x00066C) 0x3953
0x0337 (0x00066E) 0x0000
0x0338 (0x000670) 0x4444
0x0339 (0x000672) 0x2D35
0x033A (0x000674) 0x3053
0x033B (0x000676) 0x0000
0x033C (0x000678) 0x4444
0x033D (0x00067A) 0x2D34
0x033E (0x00067C) 0x3053
0x033F (0x00067E) 0x0000
0x0340 (0x000680) 0x4444
0x0341 (0x000682) 0x2D31
0x0342 (0x000684) 0x3020
0x0343 (0x000686) 0x0000
0x0344 (0x000688) 0x4444
0x0345 (0x00068A) 0x2D31
0x0346 (0x00068C) 0x3053
0x0347 (0x00068E) 0x0000
0x0348 (0x000690) 0x0000 @ Srting pointer for peripheral number 0x00
0x0349 (0x000692) 0x02B8 @ String pointer for peripheral number 0x01 - DD-19
0x034A (0x000694) 0x02BC @ String pointer for peripheral number 0x02 - DD-29
0x034B (0x000696) 0x0311 @ String pointer for peripheral number 0x03 - DD-49
0x034C (0x000698) 0x0318 @ String pointer for peripheral number 0x04 - DD-39
0x034D (0x00069A) 0x0346 @ String pointer for peripheral number 0x05 - DD-10
0x034E (0x00069C) 0x032A @ String pointer for peripheral number 0x06 - DD-40
0x034F (0x00069E) 0x031C @ String pointer for peripheral number 0x07 - DD-50
0x0350 (0x0006A0) 0x02C0 @ String pointer for peripheral number 0x08 - EXPANDER
0x0351 (0x0006A2) 0x0300 @ String pointer for peripheral number 0x09 - ERROR LOG
0x0352 (0x0006A4) 0x02F7 @ String pointer for peripheral number 0x0a - HSX
0x0353 (0x0006A6) 0x0000 @ String pointer for peripheral number 0x0b
0x0354 (0x0006A8) 0x0000 @ String pointer for peripheral number 0x0c
0x0355 (0x0006AA) 0x0000 @ String pointer for peripheral number 0x0d
0x0356 (0x0006AC) 0x0000 @ String pointer for peripheral number 0x0e
0x0357 (0x0006AE) 0x0000 @ String pointer for peripheral number 0x0f
0x0358 (0x0006B0) 0x02C5 @ String pointer for peripheral number 0x10 - TEC 455
0x0359 (0x0006B2) 0x02CA @ String pointer for peripheral number 0x11 - TEC 1440
0x035A (0x0006B4) 0x02CF @ String pointer for peripheral number 0x12 - SOROC
0x035B (0x0006B6) 0x0306 @ String pointer for peripheral number 0x13 - AMPEX 80
0x035C (0x0006B8) 0x0000 @ String pointer for peripheral number 0x14
0x035D (0x0006BA) 0x0000 @ String pointer for peripheral number 0x15
0x035E (0x0006BC) 0x0000 @ String pointer for peripheral number 0x16
0x035F (0x0006BE) 0x0000 @ String pointer for peripheral number 0x17
0x0360 (0x0006C0) 0x02D3 @ String pointer for peripheral number 0x18 - IOP0 A->A
0x0361 (0x0006C2) 0x02D9 @ String pointer for peripheral number 0x19 - IOP1 A->A
0x0362 (0x0006C4) 0x02DF @ String pointer for peripheral number 0x1a - IOP2 A->A
0x0363 (0x0006C6) 0x02E5 @ String pointer for peripheral number 0x1b - IOP3 A->A
0x0364 (0x0006C8) 0x02EB @ String pointer for peripheral number 0x1c - CRAY 50MB
0x0365 (0x0006CA) 0x02F1 @ String pointer for peripheral number 0x1d - CRAY 850MB
0x0366 (0x0006CC) 0x02FA @ String pointer for peripheral number 0x1e - CONC ( )
0x0367 (0x0006CE) 0x02FA @ String pointer for peripheral number 0x1f - CONC ( )
0x0368 (0x0006D0) 0x02FA @ String pointer for peripheral number 0x20 - CONC ( )
0x0369 (0x0006D2) 0x0000 @ String pointer for peripheral number 0x21
0x036A (0x0006D4) 0x030B @ String pointer for peripheral number 0x22 - NSC ( )
0x036B (0x0006D6) 0x0315 @ String pointer for peripheral number 0x23 - UCHN
0x036C (0x0006D8) 0x0320 @ String pointer for peripheral number 0x24 - FEI-LP
0x036D (0x0006DA) 0x0324 @ String pointer for peripheral number 0x25 - VME ( )
0x036E (0x0006DC) 0x0000 @ String pointer for peripheral number 0x26
0x036F (0x0006DE) 0x0000 @ String pointer for peripheral number 0x27
0x0370 (0x0006E0) 0x0000 @ String pointer for peripheral number 0x28
0x0371 (0x0006E2) 0x032E @ String pointer for peripheral number 0x29 - DD-19S
0x0372 (0x0006E4) 0x0332 @ String pointer for peripheral number 0x2a - DD-29S
0x0373 (0x0006E6) 0x033A @ String pointer for peripheral number 0x2b - DD-49S
0x0374 (0x0006E8) 0x0336 @ String pointer for peripheral number 0x2c - DD-39S
0x0375 (0x0006EA) 0x034A @ String pointer for peripheral number 0x2d - DD-10S
0x0376 (0x0006EC) 0x0342 @ String pointer for peripheral number 0x2e - DD-40S
0x0377 (0x0006EE) 0x033E @ String pointer for peripheral number 0x2f - DD-50S
0x0378 (0x0006F0) 0x0000 @ String pointer for peripheral number 0x30
0x0379 (0x0006F2) 0x0000 @ String pointer for peripheral number 0x31
0x037A (0x0006F4) 0x0000 @ String pointer for peripheral number 0x32
0x037B (0x0006F6) 0x0000 @ String pointer for peripheral number 0x33
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r13
push %r15
push %rbp
push %rbx
push %rcx
push %rdi
push %rsi
lea addresses_A_ht+0x3e5e, %rsi
lea addresses_normal_ht+0x1eb3f, %rdi
nop
nop
nop
nop
xor %rbp, %rbp
mov $70, %rcx
rep movsq
xor %r15, %r15
lea addresses_normal_ht+0x15203, %rsi
lea addresses_D_ht+0x11cf7, %rdi
nop
nop
nop
xor %r13, %r13
mov $98, %rcx
rep movsl
nop
nop
nop
nop
add $55482, %rdi
lea addresses_normal_ht+0xbea3, %r15
clflush (%r15)
nop
cmp $23788, %rcx
mov (%r15), %r13w
nop
and %r15, %r15
lea addresses_normal_ht+0x1c3, %rsi
nop
nop
nop
nop
nop
add $46366, %rbx
mov $0x6162636465666768, %rcx
movq %rcx, %xmm6
movups %xmm6, (%rsi)
nop
nop
nop
nop
nop
inc %rsi
lea addresses_WT_ht+0x18b4b, %r15
nop
nop
sub $34800, %rcx
movl $0x61626364, (%r15)
nop
nop
dec %rcx
lea addresses_WT_ht+0x6552, %rsi
nop
nop
nop
nop
add $3335, %r13
mov (%rsi), %edi
nop
inc %rbx
lea addresses_A_ht+0x1224c, %rsi
lea addresses_UC_ht+0x2843, %rdi
nop
nop
add %r10, %r10
mov $79, %rcx
rep movsq
nop
cmp %rbp, %rbp
lea addresses_WT_ht+0x18325, %r15
xor %rbx, %rbx
mov $0x6162636465666768, %r13
movq %r13, %xmm5
vmovups %ymm5, (%r15)
cmp %rbx, %rbx
lea addresses_UC_ht+0xcb73, %rdi
clflush (%rdi)
nop
nop
nop
nop
nop
cmp $33725, %rbx
movw $0x6162, (%rdi)
nop
add $2253, %rcx
lea addresses_A_ht+0xbdc3, %rsi
lea addresses_UC_ht+0x61c3, %rdi
nop
nop
nop
nop
and %r15, %r15
mov $63, %rcx
rep movsb
nop
nop
xor $61885, %rsi
lea addresses_WC_ht+0x32a9, %rsi
nop
nop
nop
add $38292, %rdi
movb $0x61, (%rsi)
nop
nop
add $58832, %rdi
lea addresses_UC_ht+0x1d5c3, %r13
clflush (%r13)
sub %rbx, %rbx
movl $0x61626364, (%r13)
nop
and %r15, %r15
pop %rsi
pop %rdi
pop %rcx
pop %rbx
pop %rbp
pop %r15
pop %r13
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r10
push %r13
push %r15
push %r8
push %r9
push %rbp
push %rsi
// Load
lea addresses_WC+0x85c3, %rsi
nop
nop
nop
nop
nop
sub $25792, %r8
mov (%rsi), %r10d
nop
nop
nop
nop
nop
and $54204, %r10
// Store
lea addresses_UC+0x165c3, %rsi
nop
inc %r13
movw $0x5152, (%rsi)
sub $40097, %r10
// Faulty Load
lea addresses_D+0x31c3, %rsi
nop
nop
add %r10, %r10
movb (%rsi), %r8b
lea oracles, %rbp
and $0xff, %r8
shlq $12, %r8
mov (%rbp,%r8,1), %r8
pop %rsi
pop %rbp
pop %r9
pop %r8
pop %r15
pop %r13
pop %r10
ret
/*
<gen_faulty_load>
[REF]
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0, 'same': False, 'type': 'addresses_D'}, 'OP': 'LOAD'}
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 10, 'same': False, 'type': 'addresses_WC'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 9, 'same': False, 'type': 'addresses_UC'}, 'OP': 'STOR'}
[Faulty Load]
{'src': {'NT': False, 'AVXalign': True, 'size': 1, 'congruent': 0, 'same': True, 'type': 'addresses_D'}, 'OP': 'LOAD'}
<gen_prepare_buffer>
{'src': {'congruent': 0, 'same': False, 'type': 'addresses_A_ht'}, 'dst': {'congruent': 2, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'REPM'}
{'src': {'congruent': 6, 'same': False, 'type': 'addresses_normal_ht'}, 'dst': {'congruent': 1, 'same': False, 'type': 'addresses_D_ht'}, 'OP': 'REPM'}
{'src': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 5, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'LOAD'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 16, 'congruent': 11, 'same': False, 'type': 'addresses_normal_ht'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 3, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'STOR'}
{'src': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 0, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'LOAD'}
{'src': {'congruent': 0, 'same': False, 'type': 'addresses_A_ht'}, 'dst': {'congruent': 6, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'REPM'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 32, 'congruent': 1, 'same': False, 'type': 'addresses_WT_ht'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 2, 'congruent': 4, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'STOR'}
{'src': {'congruent': 10, 'same': False, 'type': 'addresses_A_ht'}, 'dst': {'congruent': 10, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'REPM'}
{'dst': {'NT': True, 'AVXalign': False, 'size': 1, 'congruent': 0, 'same': False, 'type': 'addresses_WC_ht'}, 'OP': 'STOR'}
{'dst': {'NT': False, 'AVXalign': False, 'size': 4, 'congruent': 6, 'same': False, 'type': 'addresses_UC_ht'}, 'OP': 'STOR'}
{'36': 21829}
36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
*/
|
; A337499: a(n) is the number of ballot sequences of length n tied or won by at most 2 votes.
; Submitted by Christian Krause
; 1,2,4,6,14,20,50,70,182,252,672,924,2508,3432,9438,12870,35750,48620,136136,184756,520676,705432,1998724,2704156,7696444,10400600,29716000,40116600,115000920,155117520,445962870,601080390,1732525830,2333606220,6741529080,9075135300,26270128500,35345263800,102501265020,137846528820,400411345620,538257874440,1565841089280,2104098963720,6129331763880,8233430727600,24014172955500,32247603683100,94163002754652,126410606437752,369507926510352,495918532948104,1451020892700008,1946939425648112
mov $1,$0
div $0,2
mov $2,1
add $2,$0
add $0,$2
bin $0,$2
bin $1,$2
add $0,$1
|
.repeat 16
.byte 27
.endrepeat |
;
; Small C z88 File functions
; Written by Dominic Morris <djm@jb.man.ac.uk>
;
; 11/3/99 djm ***UNTESTED***
;
; *** THIS IS A Z88 SPECIFIC ROUTINE!!! ***
;
;
; $Id: fdtell.asm,v 1.5 2015/01/19 01:32:44 pauloscustodio Exp $
;
INCLUDE "fileio.def"
PUBLIC fdtell
;long fdtell(int fd)
.fdtell
pop bc ;ret
pop ix ;fd
push ix
push bc
ld a,FA_PTR
call_oz(os_frm)
push bc ;get the var into our preferred regs
pop hl
ret nc
;Error, return with -1
ld hl,65535
ld d,h
ld e,l
ret
|
.macosx_version_min 10, 12
.section __TEXT,__text,regular,pure_instructions
.align 4, 0x90
.globl _pari_init_evaluator
_pari_init_evaluator:
pushq %rbp
Ltmp0:
pushq %r14
Ltmp1:
pushq %rbx
Ltmp2:
Ltmp3:
Ltmp4:
Ltmp5:
movq $0, _sp(%rip)
leaq _s_st(%rip), %rax
leaq _st(%rip), %rcx
subq %rax, %rcx
movq %rcx, _s_st(%rip)
movq $0, _st(%rip)
movq $0, _s_st+8(%rip)
movq $8, _s_st+24(%rip)
movq $32, _s_st+16(%rip)
movq _st(%rip), %rdi
movq _PARI_SIGINT_block@GOTPCREL(%rip), %r14
movl (%r14), %ebp
movl $1, (%r14)
testq %rdi, %rdi
je LBB0_1
movl $256, %esi
call _realloc
jmp LBB0_3
LBB0_1:
movl $256, %edi
call _malloc
LBB0_3:
movq %rax, %rbx
movl %ebp, (%r14)
testl %ebp, %ebp
jne LBB0_6
movq _PARI_SIGINT_pending@GOTPCREL(%rip), %rax
cmpl $0, (%rax)
je LBB0_6
movl (%rax), %edi
movl $0, (%rax)
call _raise
LBB0_6:
testq %rbx, %rbx
jne LBB0_8
movl $28, %edi
xorl %eax, %eax
call _pari_err
LBB0_8:
movq %rbx, _st(%rip)
movq _s_st+16(%rip), %rax
movq %rax, _s_st+8(%rip)
movq $0, _rp(%rip)
leaq _s_ptrs(%rip), %rax
leaq _ptrs(%rip), %rcx
subq %rax, %rcx
movq %rcx, _s_ptrs(%rip)
movq $0, _ptrs(%rip)
movq $0, _s_ptrs+8(%rip)
movq $56, _s_ptrs+24(%rip)
movq $16, _s_ptrs+16(%rip)
movq _ptrs(%rip), %rdi
movl (%r14), %ebp
movl $1, (%r14)
testq %rdi, %rdi
je LBB0_9
movl $896, %esi
call _realloc
jmp LBB0_11
LBB0_9:
movl $896, %edi
call _malloc
LBB0_11:
movq %rax, %rbx
movl %ebp, (%r14)
testl %ebp, %ebp
jne LBB0_14
movq _PARI_SIGINT_pending@GOTPCREL(%rip), %rax
cmpl $0, (%rax)
je LBB0_14
movl (%rax), %edi
movl $0, (%rax)
call _raise
LBB0_14:
testq %rbx, %rbx
jne LBB0_16
movl $28, %edi
xorl %eax, %eax
call _pari_err
LBB0_16:
movq %rbx, _ptrs(%rip)
movq _s_ptrs+16(%rip), %rax
movq %rax, _s_ptrs+8(%rip)
leaq _s_var(%rip), %rax
leaq _var(%rip), %rcx
subq %rax, %rcx
movq %rcx, _s_var(%rip)
movq $0, _var(%rip)
movq $0, _s_var+16(%rip)
movq $0, _s_var+8(%rip)
movq $16, _s_var+24(%rip)
leaq _s_lvars(%rip), %rax
leaq _lvars(%rip), %rcx
subq %rax, %rcx
movq %rcx, _s_lvars(%rip)
movq $0, _lvars(%rip)
movq $0, _s_lvars+16(%rip)
movq $0, _s_lvars+8(%rip)
movq $8, _s_lvars+24(%rip)
leaq _s_trace(%rip), %rax
leaq _trace(%rip), %rcx
subq %rax, %rcx
movq %rcx, _s_trace(%rip)
movq $0, _trace(%rip)
movq $0, _s_trace+16(%rip)
movq $0, _s_trace+8(%rip)
movq $16, _s_trace+24(%rip)
popq %rbx
popq %r14
popq %rbp
ret
# ----------------------
.align 4, 0x90
.globl _pari_close_evaluator
_pari_close_evaluator:
pushq %rax
Ltmp6:
leaq _s_st(%rip), %rax
movq _s_st(%rip), %rcx
movq (%rcx,%rax), %rdi
testq %rdi, %rdi
je LBB1_2
call _free
LBB1_2:
leaq _s_ptrs(%rip), %rax
movq _s_ptrs(%rip), %rcx
movq (%rcx,%rax), %rdi
testq %rdi, %rdi
je LBB1_4
call _free
LBB1_4:
leaq _s_var(%rip), %rax
movq _s_var(%rip), %rcx
movq (%rcx,%rax), %rdi
testq %rdi, %rdi
je LBB1_6
call _free
LBB1_6:
leaq _s_lvars(%rip), %rax
movq _s_lvars(%rip), %rcx
movq (%rcx,%rax), %rdi
testq %rdi, %rdi
je LBB1_8
call _free
LBB1_8:
leaq _s_trace(%rip), %rax
movq _s_trace(%rip), %rcx
movq (%rcx,%rax), %rdi
testq %rdi, %rdi
je LBB1_9
popq %rax
jmp _free
LBB1_9:
popq %rax
ret
# ----------------------
.align 4, 0x90
.globl _closure_evalvoid
_closure_evalvoid:
pushq %r14
Ltmp7:
pushq %rbx
Ltmp8:
pushq %rax
Ltmp9:
Ltmp10:
Ltmp11:
movq _avma@GOTPCREL(%rip), %r14
movq (%r14), %rbx
call _closure_eval
movq %rbx, (%r14)
addq $8, %rsp
popq %rbx
popq %r14
ret
.align 4, 0x90
_closure_eval:
pushq %rbp
Ltmp12:
pushq %r15
Ltmp13:
pushq %r14
Ltmp14:
pushq %r13
Ltmp15:
pushq %r12
Ltmp16:
pushq %rbx
Ltmp17:
subq $296, %rsp
Ltmp18:
Ltmp19:
Ltmp20:
Ltmp21:
Ltmp22:
Ltmp23:
Ltmp24:
movq %rdi, %rcx
movq %rcx, 264(%rsp)
movq $72057594037927935, %r13
movq 16(%rcx), %rax
movq %rax, 240(%rsp)
movq 24(%rcx), %r14
movq %r14, 224(%rsp)
movq 32(%rcx), %rax
movq %rax, 192(%rsp)
movq (%r14), %r12
andq %r13, %r12
movq %r12, 256(%rsp)
movq _sp(%rip), %rax
subq 8(%rcx), %rax
movq %rax, 184(%rsp)
movq _rp(%rip), %rax
movq %rax, 176(%rsp)
movq $0, 288(%rsp)
leaq 1(%r13), %rax
movq %rax, 216(%rsp)
testq (%rcx), %rax
je LBB3_2
incq -32(%rcx)
LBB3_2:
xorl %ebx, %ebx
leaq 288(%rsp), %rdi
xorl %eax, %eax
movq %rcx, %rsi
movq %rcx, %rbp
call _trace_push
movq %rbp, %r8
movq (%r8), %rax
andq %r13, %rax
cmpq $8, %rax
jne LBB3_3
movq 56(%r8), %r12
movq (%r12), %r15
andq %r13, %r15
leaq -1(%r15), %rbx
movq _s_var+8(%rip), %rcx
leaq -1(%rcx,%r15), %rax
movq _s_var+16(%rip), %rdx
cmpq %rdx, %rax
jle LBB3_18
movq %rbx, %rcx
movq %rcx, 248(%rsp)
movq _s_var(%rip), %rbp
testq %rdx, %rdx
movq %rcx, %rsi
je LBB3_9
movq %rdx, %rsi
.align 4, 0x90
LBB3_8:
addq %rsi, %rsi
cmpq %rsi, %rax
jg LBB3_8
LBB3_9:
movq %rsi, _s_var+16(%rip)
leaq _s_var(%rip), %rax
movq (%rbp,%rax), %rdi
movq %rbp, 232(%rsp)
imulq _s_var+24(%rip), %rsi
movq _PARI_SIGINT_block@GOTPCREL(%rip), %rbp
movl (%rbp), %r13d
movl $1, (%rbp)
testq %rdi, %rdi
je LBB3_10
call _realloc
jmp LBB3_12
LBB3_10:
movq %rsi, %rdi
call _malloc
LBB3_12:
movq %rax, %rbx
movl %r13d, (%rbp)
testl %r13d, %r13d
jne LBB3_15
movq _PARI_SIGINT_pending@GOTPCREL(%rip), %rax
cmpl $0, (%rax)
je LBB3_15
movl (%rax), %edi
movl $0, (%rax)
call _raise
LBB3_15:
testq %rbx, %rbx
movq 264(%rsp), %r8
movq 224(%rsp), %r14
jne LBB3_17
movl $28, %edi
xorl %eax, %eax
movq %r8, %rbp
call _pari_err
movq %rbp, %r8
LBB3_17:
movq 232(%rsp), %rax
leaq _s_var(%rip), %rcx
movq %rbx, (%rax,%rcx)
movq _s_var+8(%rip), %rcx
movq 248(%rsp), %rbx
LBB3_18:
addq %rbx, %rcx
movq %rcx, _s_var+8(%rip)
cmpq $2, %r15
jae LBB3_20
movq 256(%rsp), %r12
jmp LBB3_3
LBB3_20:
shlq $4, %rcx
movq _var(%rip), %rax
movq $0, -16(%rcx,%rax)
movq 8(%r12), %rax
movq _s_var+8(%rip), %rcx
shlq $4, %rcx
movq _var(%rip), %rdx
movq %rax, -8(%rcx,%rdx)
cmpq $2, %rbx
jl LBB3_21
movq $-2, %rax
movl $1, %ecx
.align 4, 0x90
LBB3_23:
movq _var(%rip), %rdx
movq _s_var+8(%rip), %rsi
addq %rax, %rsi
shlq $4, %rsi
movq $0, (%rdx,%rsi)
movq 8(%r12,%rcx,8), %rdx
incq %rcx
movq _var(%rip), %rsi
movq _s_var+8(%rip), %rdi
addq %rax, %rdi
shlq $4, %rdi
movq %rdx, 8(%rsi,%rdi)
decq %rax
cmpq %rbx, %rcx
jl LBB3_23
movq 256(%rsp), %r12
jmp LBB3_3
LBB3_21:
movq 256(%rsp), %r12
LBB3_3:
movq %r8, 264(%rsp)
movq %rbx, 248(%rsp)
movq $1, 288(%rsp)
cmpq $2, %r12
movq %r14, %r13
jb LBB3_4
movl $1, %eax
xorl %ecx, %ecx
movq %rcx, 232(%rsp)
movq 240(%rsp), %r14
jmp LBB3_26
LBB3_4:
xorl %eax, %eax
movq %rax, 232(%rsp)
jmp LBB3_448
LBB3_326:
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rdi
xorl %eax, %eax
call *16(%r15)
jmp LBB3_446
LBB3_327:
movq _sp(%rip), %rax
leaq -2(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %rdi
movq -8(%rcx,%rax,8), %rsi
xorl %eax, %eax
call *16(%r15)
jmp LBB3_446
LBB3_328:
movq _sp(%rip), %rax
leaq -3(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -24(%rcx,%rax,8), %rdi
movq -16(%rcx,%rax,8), %rsi
movq -8(%rcx,%rax,8), %rdx
xorl %eax, %eax
call *16(%r15)
jmp LBB3_446
LBB3_329:
movq _sp(%rip), %rax
leaq -4(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -32(%rcx,%rax,8), %rdi
movq -24(%rcx,%rax,8), %rsi
movq -16(%rcx,%rax,8), %rdx
movq -8(%rcx,%rax,8), %rcx
xorl %eax, %eax
call *16(%r15)
jmp LBB3_446
LBB3_330:
movq _sp(%rip), %rax
leaq -5(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %r8
xorl %eax, %eax
call *16(%r15)
jmp LBB3_446
LBB3_331:
movq _sp(%rip), %rax
leaq -6(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -48(%rbp,%rax,8), %rdi
movq -40(%rbp,%rax,8), %rsi
movq -32(%rbp,%rax,8), %rdx
movq -24(%rbp,%rax,8), %rcx
movq -16(%rbp,%rax,8), %r8
movq -8(%rbp,%rax,8), %r9
jmp LBB3_336
LBB3_332:
movq _sp(%rip), %rax
leaq -7(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -56(%rbp,%rax,8), %rdi
movq -48(%rbp,%rax,8), %rsi
movq -40(%rbp,%rax,8), %rdx
movq -32(%rbp,%rax,8), %rcx
movq -24(%rbp,%rax,8), %r8
movq -16(%rbp,%rax,8), %r9
movq -8(%rbp,%rax,8), %rax
movq %rax, (%rsp)
jmp LBB3_336
LBB3_333:
movq _sp(%rip), %rax
leaq -8(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -64(%rbp,%rax,8), %rdi
movq -56(%rbp,%rax,8), %rsi
movq -48(%rbp,%rax,8), %rdx
movq -40(%rbp,%rax,8), %rcx
movq -32(%rbp,%rax,8), %r8
movq -24(%rbp,%rax,8), %r9
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 8(%rsp)
movq %rbx, (%rsp)
jmp LBB3_336
LBB3_334:
movq _sp(%rip), %rax
leaq -9(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -72(%rbp,%rax,8), %rdi
movq -64(%rbp,%rax,8), %rsi
movq -56(%rbp,%rax,8), %rdx
movq -48(%rbp,%rax,8), %rcx
movq -40(%rbp,%rax,8), %r8
movq -32(%rbp,%rax,8), %r9
movq -24(%rbp,%rax,8), %r10
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 16(%rsp)
movq %rbx, 8(%rsp)
jmp LBB3_335
LBB3_337:
movq _sp(%rip), %rax
leaq -10(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -80(%rbp,%rax,8), %rdi
movq -72(%rbp,%rax,8), %rsi
movq -64(%rbp,%rax,8), %rdx
movq -56(%rbp,%rax,8), %rcx
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %r9
movq -32(%rbp,%rax,8), %r10
movq -24(%rbp,%rax,8), %r11
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 24(%rsp)
movq %rbx, 16(%rsp)
movq %r11, 8(%rsp)
LBB3_335:
movq %r10, (%rsp)
LBB3_336:
xorl %eax, %eax
call *16(%r15)
jmp LBB3_446
LBB3_338:
movq _sp(%rip), %rax
leaq -11(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -88(%rbp,%rax,8), %rdi
movq -80(%rbp,%rax,8), %rsi
movq -72(%rbp,%rax,8), %rdx
movq -64(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -56(%rbp,%rax,8), %r8
movq -48(%rbp,%rax,8), %r9
movq -40(%rbp,%rax,8), %r10
movq -32(%rbp,%rax,8), %r11
movq %r12, %rcx
movq %r14, %r12
movq -24(%rbp,%rax,8), %r14
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 32(%rsp)
movq %rbx, 24(%rsp)
movq %r14, 16(%rsp)
movq %r12, %r14
movq %rcx, %r12
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
jmp LBB3_339
LBB3_340:
movq _sp(%rip), %rax
leaq -12(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -96(%rbp,%rax,8), %rdi
movq -88(%rbp,%rax,8), %rsi
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -72(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -64(%rbp,%rax,8), %r8
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r10
movq -40(%rbp,%rax,8), %r11
movq %r13, %rdx
movq %r14, %r13
movq -32(%rbp,%rax,8), %r14
movq %r12, %rcx
movq -24(%rbp,%rax,8), %r12
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 40(%rsp)
movq %rbx, 32(%rsp)
movq %r12, 24(%rsp)
movq %rcx, %r12
movq %r14, 16(%rsp)
movq %r13, %r14
movq %rdx, %r13
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq 200(%rsp), %rdx
LBB3_339:
movq 208(%rsp), %rcx
call *16(%r15)
jmp LBB3_446
LBB3_341:
movq _sp(%rip), %rax
leaq -13(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -104(%rbp,%rax,8), %rdx
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -72(%rbp,%rax,8), %r8
movq -64(%rbp,%rax,8), %r9
movq -56(%rbp,%rax,8), %r10
movq -48(%rbp,%rax,8), %r11
movq %r14, %rdi
movq -40(%rbp,%rax,8), %r14
movq %r12, %rsi
movq -32(%rbp,%rax,8), %r12
movq %r13, %rcx
movq -24(%rbp,%rax,8), %r13
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rcx, %r13
movq %r12, 24(%rsp)
movq %rsi, %r12
movq %r14, 16(%rsp)
movq %rdi, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq %rdx, %rdi
movq 208(%rsp), %rsi
movq 168(%rsp), %rdx
jmp LBB3_342
LBB3_343:
movq _sp(%rip), %rax
leaq -14(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -112(%rbp,%rax,8), %rsi
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -72(%rbp,%rax,8), %r9
movq -64(%rbp,%rax,8), %r10
movq -56(%rbp,%rax,8), %r11
movq %r14, %r8
movq -48(%rbp,%rax,8), %r14
movq %r12, %rdi
movq -40(%rbp,%rax,8), %r12
movq %r13, %rdx
movq -32(%rbp,%rax,8), %r13
movq -24(%rbp,%rax,8), %rbx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rdx, %r13
movq %r12, 24(%rsp)
movq %rdi, %r12
movq %r14, 16(%rsp)
movq %r8, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq %rsi, %rdi
movq 208(%rsp), %rsi
movq 168(%rsp), %rdx
movq 160(%rsp), %r8
LBB3_342:
movq 200(%rsp), %rcx
call *16(%r15)
jmp LBB3_446
LBB3_344:
movq _sp(%rip), %rax
leaq -15(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -120(%rbp,%rax,8), %rdi
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -72(%rbp,%rax,8), %r10
movq -64(%rbp,%rax,8), %r11
movq %r14, %r9
movq -56(%rbp,%rax,8), %r14
movq %r12, %r8
movq -48(%rbp,%rax,8), %r12
movq %r13, %rsi
movq -40(%rbp,%rax,8), %r13
movq -32(%rbp,%rax,8), %rbx
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rsi, %r13
movq %r12, 24(%rsp)
movq %r8, %r12
movq %r14, 16(%rsp)
movq %r9, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
jmp LBB3_345
LBB3_346:
movq _sp(%rip), %rax
leaq -16(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -128(%rbp,%rax,8), %r8
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -72(%rbp,%rax,8), %r11
movq %r14, %r10
movq -64(%rbp,%rax,8), %r14
movq %r12, %r9
movq -56(%rbp,%rax,8), %r12
movq %r13, %rdi
movq -48(%rbp,%rax,8), %r13
movq -40(%rbp,%rax,8), %rbx
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rdi, %r13
movq %r12, 24(%rsp)
movq %r9, %r12
movq %r14, 16(%rsp)
movq %r10, %r14
movq %r11, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r8, %rdi
jmp LBB3_345
LBB3_347:
movq _sp(%rip), %rax
leaq -17(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -136(%rbp,%rax,8), %r9
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq %r14, %r11
movq -72(%rbp,%rax,8), %r14
movq %r12, %r10
movq -64(%rbp,%rax,8), %r12
movq %r13, %r8
movq -56(%rbp,%rax,8), %r13
movq -48(%rbp,%rax,8), %rbx
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rsi, 56(%rsp)
movq %rdi, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r8, %r13
movq %r12, 24(%rsp)
movq %r10, %r12
movq %r14, 16(%rsp)
movq %r11, %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r9, %rdi
jmp LBB3_345
LBB3_348:
movq _sp(%rip), %rax
leaq -18(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -144(%rbp,%rax,8), %r10
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -80(%rbp,%rax,8), %r14
movq %r12, %r11
movq -72(%rbp,%rax,8), %r12
movq %r13, %r9
movq -64(%rbp,%rax,8), %r13
movq -56(%rbp,%rax,8), %rbx
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdi, 56(%rsp)
movq %r8, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r9, %r13
movq %r12, 24(%rsp)
movq %r11, %r12
movq %r14, 16(%rsp)
movq 240(%rsp), %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r10, %rdi
jmp LBB3_345
LBB3_349:
movq _sp(%rip), %rax
leaq -19(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -152(%rbp,%rax,8), %r11
movq -144(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 128(%rsp)
movq %r12, %r14
movq -80(%rbp,%rax,8), %r12
movq %r13, %r10
movq -72(%rbp,%rax,8), %r13
movq -64(%rbp,%rax,8), %rbx
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rsi, 72(%rsp)
movq %rdi, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r10, %r13
movq %r12, 24(%rsp)
movq %r14, %r12
movq 128(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r11, %rdi
LBB3_345:
movq 200(%rsp), %rsi
movq 160(%rsp), %r8
movq 152(%rsp), %r9
movq 208(%rsp), %rdx
movq 168(%rsp), %rcx
call *16(%r15)
jmp LBB3_446
LBB3_350:
movq _sp(%rip), %rax
leaq -20(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -160(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -152(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -144(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 128(%rsp)
movq -96(%rbp,%rax,8), %r14
movq -88(%rbp,%rax,8), %r12
movq %r13, %r11
movq -80(%rbp,%rax,8), %r13
movq -72(%rbp,%rax,8), %rbx
movq -64(%rbp,%rax,8), %r10
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdi, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movq %r10, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r11, %r13
movq %r12, 24(%rsp)
movq 256(%rsp), %r12
movq %r14, 16(%rsp)
movq 240(%rsp), %r14
movq 128(%rsp), %rax
movq %rax, 8(%rsp)
movq 136(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq 208(%rsp), %rdi
movq 168(%rsp), %rsi
movq 152(%rsp), %r8
movq 144(%rsp), %r9
movq 200(%rsp), %rdx
movq 160(%rsp), %rcx
call *16(%r15)
jmp LBB3_446
LBB3_135:
cmpq $1, %rax
movq $72057594037927935, %r12
jne LBB3_161
movq 8(%rbx), %r10
movq %r10, %rdx
andq %r12, %rdx
leaq 0(,%rdx,8), %rax
movq %rbp, %r15
subq %rax, %r15
cmpq $2, %rdx
jb LBB3_147
movq %r10, %rsi
andq %r12, %rsi
movq %rsi, %rdi
negq %rdi
cmpq $-3, %rdi
movq $-2, %r11
movq $-2, %rax
cmovg %rdi, %rax
leaq (%rax,%rsi), %rcx
cmpq $-1, %rcx
movq %rdx, %rcx
je LBB3_145
leaq 1(%rax,%rsi), %r8
incq %rax
addl %r10d, %eax
andq $3, %rax
cmpq $-3, %rdi
cmovg %rdi, %r11
xorl %r14d, %r14d
movq %r8, %r9
subq %rax, %r9
movq %rdx, %rcx
je LBB3_144
movq %r11, %rax
notq %rax
leaq (%rbx,%rax,8), %rax
leaq -8(%rbp), %rcx
xorl %r14d, %r14d
cmpq %rax, %rcx
ja LBB3_141
leaq -8(%rbx,%rsi,8), %rax
addq %rsi, %r11
notq %r11
leaq (%rbp,%r11,8), %rcx
cmpq %rcx, %rax
movq %rdx, %rcx
jbe LBB3_144
LBB3_141:
movq %rdx, %rcx
subq %r9, %rcx
cmpq $-3, %rdi
movq $-2, %r11
cmovg %rdi, %r11
cmpq $-2, %rdi
movl $-2, %eax
cmovg %edi, %eax
leal 1(%r10,%rax), %edi
andq $3, %rdi
subq %r11, %rdi
decq %rdi
LBB3_142:
movd %rsi, %xmm0
pshufd $68, %xmm0, %xmm0
paddq LCPI3_0(%rip), %xmm0
movd %xmm0, %rax
movups -8(%rbx,%rax,8), %xmm0
movups -24(%rbx,%rax,8), %xmm1
subq %rdx, %rax
movups %xmm0, -8(%rbp,%rax,8)
movups %xmm1, -24(%rbp,%rax,8)
addq $-4, %rsi
cmpq %rsi, %rdi
jne LBB3_142
movq %r9, %r14
LBB3_144:
cmpq %r14, %r8
movq 240(%rsp), %r14
je LBB3_147
LBB3_145:
andq %r12, %r10
shlq $3, %r10
subq %r10, %rbp
addq $-8, %rbp
LBB3_146:
movq -8(%rbx,%rcx,8), %rax
movq %rax, (%rbp,%rcx,8)
leaq -1(%rcx), %rcx
cmpq $1, %rcx
jg LBB3_146
LBB3_147:
movq $144115188075855875, %rax
leaq -3(%rax), %rax
orq %rax, %rdx
movq %rdx, (%r15)
movq _avma@GOTPCREL(%rip), %rax
movq %r15, (%rax)
movq %r15, %rbx
jmp LBB3_162
LBB3_95:
andq %rax, %r8
leaq (%rcx,%r8,8), %rsi
movq %rcx, %rdx
call _gerepile
movq %rax, %rcx
jmp LBB3_96
LBB3_161:
andq %r12, %r8
leaq (%rbx,%r8,8), %rsi
movq %rbp, %rdi
movq %rbx, %rdx
call _gerepile
movq %rax, %rbx
LBB3_162:
movq 256(%rsp), %r12
LBB3_163:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq %rbx, -8(%rcx,%rax,8)
jmp LBB3_446
.align 4, 0x90
LBB3_26:
movsbl 7(%r14,%rax), %ebp
movq (%r13,%rax,8), %r15
cmpq $0, _sp(%rip)
jns LBB3_28
movl $2, %edi
xorl %eax, %eax
leaq L_.str(%rip), %rsi
call _pari_err
LBB3_28:
movl $16, %edi
xorl %eax, %eax
call _st_alloc
addl $-65, %ebp
cmpl $56, %ebp
ja LBB3_446
movq %r15, %rbx
negq %rbx
leaq LJTI3_0(%rip), %rax
movq %rax, %rcx
movslq (%rcx,%rbp,4), %rax
addq %rcx, %rax
jmp *%rax
LBB3_34:
movq _gnil@GOTPCREL(%rip), %rax
movq (%rax), %rax
jmp LBB3_273
LBB3_272:
movq 192(%rsp), %rax
movq (%rax,%r15,8), %rax
jmp LBB3_273
LBB3_36:
movq 192(%rsp), %rax
movq (%rax,%r15,8), %rdi
addq $8, %rdi
movq _precreal@GOTPCREL(%rip), %rax
movq (%rax), %rsi
call _strtor
jmp LBB3_273
LBB3_37:
movq %r14, %r12
testq %r15, %r15
je LBB3_38
movq _avma@GOTPCREL(%rip), %rdx
movq (%rdx), %rbp
leaq -24(%rbp), %r14
movq _bot@GOTPCREL(%rip), %rcx
movq %rbp, %rax
subq (%rcx), %rax
testq %r15, %r15
jle LBB3_43
cmpq $23, %rax
ja LBB3_42
movl $14, %edi
xorl %eax, %eax
movq %rdx, %rbx
call _pari_err
movq %rbx, %rdx
LBB3_42:
movq %r14, (%rdx)
movq $144115188075855875, %rax
movq %rax, -24(%rbp)
movq $4611686018427387907, %rax
movq %rax, -16(%rbp)
movq %r15, -8(%rbp)
jmp LBB3_46
LBB3_47:
movq %r15, %rdi
call _pari_var_create
addq $72, %r15
LBB3_48:
movq _sp(%rip), %rax
leaq 1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq %r15, (%rcx,%rax,8)
jmp LBB3_446
LBB3_445:
subq %r15, _sp(%rip)
jmp LBB3_446
LBB3_102:
movq %r12, %r15
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rbx
movq %r14, %r12
testq %rbx, %rbx
je LBB3_103
jle LBB3_108
movq _avma@GOTPCREL(%rip), %rdx
movq (%rdx), %rbp
leaq -24(%rbp), %r14
movq _bot@GOTPCREL(%rip), %rax
movq %rbp, %rcx
subq (%rax), %rcx
cmpq $23, %rcx
ja LBB3_107
movl $14, %edi
xorl %eax, %eax
call _pari_err
movq _avma@GOTPCREL(%rip), %rdx
LBB3_107:
movq %r14, (%rdx)
movq $144115188075855875, %rax
movq %rax, -24(%rbp)
movq $4611686018427387907, %rax
jmp LBB3_111
LBB3_113:
movq _sp(%rip), %rax
addq %r15, %rax
movq _st(%rip), %rcx
movq (%rcx,%rax,8), %rbp
jmp LBB3_114
LBB3_122:
movq _sp(%rip), %rcx
leaq (%rcx,%r15), %rax
movq _st(%rip), %rdx
movq (%rdx,%rax,8), %rax
movq (%rax), %rsi
movq $-144115188075855872, %rdi
andq %rdi, %rsi
movq $3026418949592973312, %rdi
cmpq %rdi, %rsi
je LBB3_124
movq %rax, %rdi
call _GENtoGENstr
movq _sp(%rip), %rcx
movq _st(%rip), %rdx
LBB3_124:
addq $8, %rax
addq %r15, %rcx
movq %rax, (%rdx,%rcx,8)
jmp LBB3_446
LBB3_125:
movq _sp(%rip), %rax
addq %r15, %rax
movq _st(%rip), %rcx
movq (%rcx,%rax,8), %rdi
xorl %eax, %eax
call _closure_varn
cltq
jmp LBB3_121
LBB3_165:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rdi
jmp LBB3_166
LBB3_164:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rdi
movq 216(%rsp), %rax
testq (%rdi), %rax
je LBB3_446
LBB3_166:
call _gcopy
movq _sp(%rip), %rcx
movq _st(%rip), %rdx
movq %rax, -8(%rdx,%rcx,8)
jmp LBB3_446
LBB3_97:
movq _precreal@GOTPCREL(%rip), %rax
movq (%rax), %rax
jmp LBB3_273
LBB3_98:
movq _precdl@GOTPCREL(%rip), %rax
movq (%rax), %rax
jmp LBB3_273
LBB3_421:
movq _avma@GOTPCREL(%rip), %rbp
movq (%rbp), %rax
leaq (%rax,%rbx,8), %rbx
movq _bot@GOTPCREL(%rip), %rcx
subq (%rcx), %rax
shrq $3, %rax
cmpq %r15, %rax
jae LBB3_423
movl $14, %edi
xorl %eax, %eax
call _pari_err
LBB3_423:
movq %rbx, (%rbp)
movq $72057594037927935, %rax
cmpq %rax, %r15
jbe LBB3_425
leaq L_.str12(%rip), %rsi
movl $15, %edi
xorl %eax, %eax
call _pari_err
LBB3_425:
movq $2449958197289549824, %rax
jmp LBB3_426
LBB3_432:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %r14
movq _avma@GOTPCREL(%rip), %rdx
movq (%rdx), %rax
movq %rax, 208(%rsp)
leaq (%rax,%rbx,8), %rbp
movq _bot@GOTPCREL(%rip), %rcx
subq (%rcx), %rax
shrq $3, %rax
cmpq %r15, %rax
jae LBB3_434
movl $14, %edi
xorl %eax, %eax
movq %rdx, %rbx
call _pari_err
movq %rbx, %rdx
LBB3_434:
movq %rbp, (%rdx)
movq $72057594037927935, %rax
cmpq %rax, %r15
jbe LBB3_436
leaq L_.str12(%rip), %rsi
movl $15, %edi
xorl %eax, %eax
movq %rdx, %rbx
call _pari_err
movq %rbx, %rdx
LBB3_436:
movq %r15, %rax
movq $2738188573441261568, %rcx
orq %rcx, %rax
movq %rax, (%rbp)
movq %rbp, 168(%rsp)
cmpq $2, %r15
jl LBB3_444
movq %r14, 200(%rsp)
movq %r14, %r12
negq %r12
movq %r14, %r13
movq $2594073385365405696, %rax
orq %rax, %r13
movq $72057594037927935, %rax
movl $1, %ebx
subq %r15, %rbx
cmpq %rax, %r14
jbe LBB3_438
.align 4, 0x90
LBB3_441:
movq (%rdx), %rax
leaq (%rax,%r12,8), %r14
movq _bot@GOTPCREL(%rip), %rcx
subq (%rcx), %rax
shrq $3, %rax
cmpq 200(%rsp), %rax
jae LBB3_443
movl $14, %edi
xorl %eax, %eax
movq %rdx, %r15
call _pari_err
movq %r15, %rdx
LBB3_443:
movq %r14, (%rdx)
leaq L_.str12(%rip), %rsi
movl $15, %edi
xorl %eax, %eax
movq %rdx, %rbp
call _pari_err
movq %rbp, %rdx
movq %r13, (%r14)
movq 208(%rsp), %rax
movq %r14, (%rax,%rbx,8)
incq %rbx
jne LBB3_441
jmp LBB3_444
.align 4, 0x90
LBB3_438:
movq (%rdx), %rax
leaq (%rax,%r12,8), %rbp
movq _bot@GOTPCREL(%rip), %rcx
subq (%rcx), %rax
shrq $3, %rax
cmpq 200(%rsp), %rax
jae LBB3_440
movl $14, %edi
xorl %eax, %eax
movq %rdx, %r15
call _pari_err
movq %r15, %rdx
LBB3_440:
movq %rbp, (%rdx)
movq %r13, (%rbp)
movq 208(%rsp), %rax
movq %rbp, (%rax,%rbx,8)
incq %rbx
jne LBB3_438
LBB3_444:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq 168(%rsp), %rsi
movq %rsi, -8(%rcx,%rax,8)
movq (%rdx), %rax
movq _sp(%rip), %rcx
leaq 1(%rcx), %rdx
movq %rdx, _sp(%rip)
movq _st(%rip), %rdx
movq %rax, (%rdx,%rcx,8)
jmp LBB3_230
LBB3_427:
movq _avma@GOTPCREL(%rip), %rbp
movq (%rbp), %rax
leaq (%rax,%rbx,8), %rbx
movq _bot@GOTPCREL(%rip), %rcx
subq (%rcx), %rax
shrq $3, %rax
cmpq %r15, %rax
jae LBB3_429
movl $14, %edi
xorl %eax, %eax
call _pari_err
LBB3_429:
movq %rbx, (%rbp)
movq $72057594037927935, %rax
cmpq %rax, %r15
jbe LBB3_431
leaq L_.str12(%rip), %rsi
movl $15, %edi
xorl %eax, %eax
call _pari_err
LBB3_431:
movq $2594073385365405696, %rax
LBB3_426:
orq %rax, %r15
movq %r15, (%rbx)
movq _sp(%rip), %rax
leaq 1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq %rbx, (%rcx,%rax,8)
movq (%rbp), %rax
jmp LBB3_273
LBB3_62:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %rdi
movq -8(%rcx,%rax,8), %rcx
movq _bot@GOTPCREL(%rip), %rax
cmpq (%rax), %rcx
jb LBB3_65
cmpq %rcx, %rdi
jbe LBB3_65
movq _top@GOTPCREL(%rip), %rax
cmpq (%rax), %rcx
jae LBB3_65
movq (%rcx), %r8
movq %r8, %rax
shrq $57, %rax
leaq -21(%rax), %rsi
cmpq $2, %rsi
jb LBB3_81
cmpq $2, %rax
jne LBB3_68
LBB3_81:
movq %r8, %rax
movq $72057594037927935, %rbx
andq %rbx, %rax
shlq $3, %rax
movq %rdi, %r11
subq %rax, %r11
movq %r8, %rsi
andq %rbx, %rsi
movq _avma@GOTPCREL(%rip), %rax
movq %r11, (%rax)
je LBB3_82
movq %r8, %rax
movq $-72057594037927936, %rdx
orq %rdx, %rax
movq %rax, %rbp
xorq %rbx, %rbp
cmpq %rdx, %rax
movq $-2, %r14
movq $-2, %r12
cmove %rbp, %r12
leaq (%r12,%rsi), %rbx
cmpq $-2, %rbx
je LBB3_92
leaq 2(%r12), %rbx
leaq 2(%r12,%rsi), %r9
addl %r8d, %ebx
andq $3, %rbx
cmpq %rdx, %rax
movq %r9, %rdx
cmove %rbp, %r14
xorl %r10d, %r10d
subq %rbx, %r9
je LBB3_90
movq $-2, %rax
movq $-2, %rbp
subq %r14, %rbp
leaq (%rcx,%rbp,8), %rbx
leaq -8(%rdi), %rbp
xorl %r10d, %r10d
cmpq %rbx, %rbp
ja LBB3_87
leaq -8(%rcx,%rsi,8), %rbx
addq %rsi, %r14
subq %r14, %rax
leaq (%rdi,%rax,8), %rax
cmpq %rax, %rbx
jbe LBB3_90
LBB3_87:
movq %rsi, %r10
subq %r9, %r10
leal 2(%r12,%r8), %ebp
andq $3, %rbp
subq %r12, %rbp
addq $-2, %rbp
movq %rsi, %rax
LBB3_88:
movd %rax, %xmm0
pshufd $68, %xmm0, %xmm0
paddq LCPI3_0(%rip), %xmm0
movd %xmm0, %rbx
movups -8(%rcx,%rbx,8), %xmm0
movups -24(%rcx,%rbx,8), %xmm1
subq %rsi, %rbx
movups %xmm0, -8(%rdi,%rbx,8)
movups %xmm1, -24(%rdi,%rbx,8)
addq $-4, %rax
cmpq %rax, %rbp
jne LBB3_88
movq %r10, %rsi
movq %r9, %r10
LBB3_90:
cmpq %r10, %rdx
jne LBB3_92
movq %r11, %rcx
movq 240(%rsp), %r14
movq 256(%rsp), %r12
jmp LBB3_96
LBB3_167:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %rbx
movq -8(%rcx,%rax,8), %rbp
leaq -2(%rax), %rax
movq %rax, _sp(%rip)
movq (%rbx), %rsi
movq %rsi, %rax
shrq $57, %rax
cmpq $22, %rax
je LBB3_175
cmpq $20, %rax
movq $72057594037927935, %rcx
je LBB3_171
addq $-17, %rax
cmpq $1, %rax
jbe LBB3_173
leaq L_.str2(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
jmp LBB3_446
LBB3_197:
movq %r14, %r13
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -24(%rcx,%rax,8), %rbx
movq -16(%rcx,%rax,8), %r14
movq -8(%rcx,%rax,8), %r12
movq (%rbx), %rsi
movq %rsi, %rax
movq $-144115188075855872, %rcx
andq %rcx, %rax
movq $2738188573441261568, %rcx
cmpq %rcx, %rax
je LBB3_199
leaq L_.str3(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
movq (%rbx), %rsi
LBB3_199:
movq $72057594037927935, %rax
movq %rax, %rbp
andq %rbp, %rsi
xorl %eax, %eax
movq %r12, %rdi
call _check_array_index
movq (%rbx,%r12,8), %rax
movq (%rax), %rsi
andq %rbp, %rsi
xorl %eax, %eax
movq %r14, %rdi
call _check_array_index
addq $-3, _sp(%rip)
movq (%rbx,%r12,8), %rax
movq (%rax,%r14,8), %rdi
xorl %eax, %eax
movq %r15, %rsi
call _closure_castgen
movq %r13, %r14
jmp LBB3_231
LBB3_203:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %rbp
movq -8(%rcx,%rax,8), %rbx
movq (%rbp), %rsi
movq %rsi, %rax
movq $-144115188075855872, %rcx
andq %rcx, %rax
movq $2738188573441261568, %rcx
cmpq %rcx, %rax
je LBB3_205
leaq L_.str4(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
movq (%rbp), %rsi
LBB3_205:
movq $72057594037927935, %rax
andq %rax, %rsi
xorl %eax, %eax
movq %rbx, %rdi
call _check_array_index
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
movq (%rbp,%rbx,8), %rcx
movq _st(%rip), %rdx
movq %rcx, -16(%rdx,%rax,8)
jmp LBB3_446
LBB3_209:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %r15
movq -8(%rcx,%rax,8), %r14
decq %rax
movq %rax, _sp(%rip)
movq (%r15), %rax
movq %rax, %rcx
movq $-144115188075855872, %rdx
andq %rdx, %rcx
movq $2738188573441261568, %rdx
cmpq %rdx, %rcx
je LBB3_211
leaq L_.str5(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
movq (%r15), %rax
LBB3_211:
movq $72057594037927935, %rbp
andq %rbp, %rax
cmpq $1, %rax
jne LBB3_213
leaq L_.str6(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
LBB3_213:
movq 8(%r15), %rax
movq (%rax), %rsi
andq %rbp, %rsi
xorl %eax, %eax
movq %r14, %rdi
call _check_array_index
movq (%r15), %rbx
andq %rbp, %rbx
movq _avma@GOTPCREL(%rip), %r12
movq (%r12), %rax
leaq 0(,%rbx,8), %rcx
movq %rax, %rbp
subq %rcx, %rbp
movq _bot@GOTPCREL(%rip), %rcx
subq (%rcx), %rax
shrq $3, %rax
cmpq %rbx, %rax
jae LBB3_215
movl $14, %edi
xorl %eax, %eax
call _pari_err
LBB3_215:
movq %rbp, (%r12)
movq %rbx, %rax
movq $2449958197289549824, %rcx
orq %rcx, %rax
movq %rax, (%rbp)
cmpq $2, %rbx
jb LBB3_218
movl $1, %eax
.align 4, 0x90
LBB3_217:
movq (%r15,%rax,8), %rcx
movq (%rcx,%r14,8), %rcx
movq %rcx, (%rbp,%rax,8)
incq %rax
cmpq %rbx, %rax
jl LBB3_217
LBB3_218:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq %rbp, -8(%rcx,%rax,8)
movq 240(%rsp), %r14
movq 256(%rsp), %r12
jmp LBB3_446
LBB3_56:
imulq $56, _rp(%rip), %rax
movq _ptrs(%rip), %rcx
movq _sp(%rip), %rdx
movq %rdx, -8(%rax,%rcx)
leaq -32(%rax,%rcx), %rax
jmp LBB3_273
LBB3_30:
testq %r15, %r15
jle LBB3_446
.align 4, 0x90
LBB3_31:
movq _rp(%rip), %rcx
decq %rcx
movq %rcx, _rp(%rip)
movq _ptrs(%rip), %rax
imulq $56, %rcx, %rcx
movq 32(%rax,%rcx), %rdi
testq %rdi, %rdi
je LBB3_58
movq 24(%rax,%rcx), %rsi
movq 40(%rax,%rcx), %rcx
testq %rcx, %rcx
je LBB3_57
xorl %eax, %eax
movq %rcx, %rdi
call _changelex
jmp LBB3_59
.align 4, 0x90
LBB3_58:
leaq (%rax,%rcx), %rdi
movq 24(%rax,%rcx), %rsi
xorl %eax, %eax
call _change_compo
jmp LBB3_59
.align 4, 0x90
LBB3_57:
call _changevalue
LBB3_59:
decq %r15
jne LBB3_31
jmp LBB3_446
LBB3_176:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rbx
decq %rax
movq _rp(%rip), %rcx
decq %rcx
movq _ptrs(%rip), %r15
imulq $56, %rcx, %r12
leaq (%r15,%r12), %r14
leaq 24(%r15,%r12), %rcx
movq %rcx, 208(%rsp)
movq 24(%r15,%r12), %rbp
movq %rax, _sp(%rip)
movq (%rbp), %rsi
movq %rsi, %rax
shrq $57, %rax
cmpq $22, %rax
je LBB3_182
cmpq $20, %rax
je LBB3_193
addq $-17, %rax
cmpq $1, %rax
jbe LBB3_195
leaq L_.str2(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
jmp LBB3_180
LBB3_200:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %r14
movq -8(%rcx,%rax,8), %r12
leaq -2(%rax), %rax
movq _rp(%rip), %rcx
decq %rcx
movq _ptrs(%rip), %r13
imulq $56, %rcx, %rbp
leaq 24(%r13,%rbp), %rcx
movq %rcx, 208(%rsp)
movq 24(%r13,%rbp), %rbx
movq %rax, _sp(%rip)
movq (%rbx), %rsi
movq %rsi, %rax
movq $-144115188075855872, %rcx
andq %rcx, %rax
movq $2738188573441261568, %rcx
cmpq %rcx, %rax
je LBB3_202
leaq L_.str3(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
movq (%rbx), %rsi
LBB3_202:
movq $72057594037927935, %r15
andq %r15, %rsi
xorl %eax, %eax
movq %r12, %rdi
call _check_array_index
movq (%rbx,%r12,8), %rax
movq (%rax), %rsi
andq %r15, %rsi
xorl %eax, %eax
movq %r14, %rdi
call _check_array_index
movq (%rbx,%r12,8), %rax
leaq (%rax,%r14,8), %rcx
movq %rcx, (%r13,%rbp)
movq %rbx, 8(%r13,%rbp)
movq (%rax,%r14,8), %rax
movq 208(%rsp), %rcx
jmp LBB3_229
LBB3_206:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %r15
decq %rax
movq _rp(%rip), %rcx
decq %rcx
movq _ptrs(%rip), %rbp
imulq $56, %rcx, %rbx
leaq (%rbp,%rbx), %r13
leaq 24(%rbp,%rbx), %r14
movq 24(%rbp,%rbx), %r12
movq %rax, _sp(%rip)
movq (%r12), %rsi
movq %rsi, %rax
movq $-144115188075855872, %rcx
andq %rcx, %rax
movq $2738188573441261568, %rcx
cmpq %rcx, %rax
je LBB3_208
leaq L_.str4(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
movq (%r12), %rsi
LBB3_208:
movq $72057594037927935, %rax
andq %rax, %rsi
xorl %eax, %eax
movq %r15, %rdi
call _check_array_index
leaq (%r12,%r15,8), %rax
movq %rax, (%r13)
movl %r15d, 16(%rbp,%rbx)
movq %r12, 8(%rbp,%rbx)
movq (%r12,%r15,8), %rax
movq %rax, (%r14)
jmp LBB3_230
LBB3_219:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %r12
decq %rax
movq _rp(%rip), %rcx
decq %rcx
movq _ptrs(%rip), %r14
imulq $56, %rcx, %r15
movq 24(%r14,%r15), %r13
movq %rax, _sp(%rip)
movq (%r13), %rax
movq %rax, %rcx
movq $-144115188075855872, %rdx
andq %rdx, %rcx
movq $2738188573441261568, %rdx
cmpq %rdx, %rcx
je LBB3_221
leaq L_.str5(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
movq (%r13), %rax
LBB3_221:
movq $72057594037927935, %rcx
andq %rcx, %rax
cmpq $1, %rax
jne LBB3_223
leaq L_.str6(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
LBB3_223:
movq 8(%r13), %rax
movq (%rax), %rsi
movq $72057594037927935, %rax
movq %rax, %rbp
andq %rbp, %rsi
xorl %eax, %eax
movq %r12, %rdi
call _check_array_index
movq (%r13), %rbx
andq %rbp, %rbx
movq _avma@GOTPCREL(%rip), %rdx
movq (%rdx), %rax
leaq 0(,%rbx,8), %rcx
movq %rax, %rbp
subq %rcx, %rbp
movq _bot@GOTPCREL(%rip), %rcx
subq (%rcx), %rax
shrq $3, %rax
cmpq %rbx, %rax
jae LBB3_225
movl $14, %edi
xorl %eax, %eax
movq %r14, 208(%rsp)
movq %rdx, %r14
call _pari_err
movq %r14, %rdx
movq 208(%rsp), %r14
LBB3_225:
leaq 24(%r14,%r15), %rax
movq %rax, 200(%rsp)
movq %r14, 208(%rsp)
movq %rbp, (%rdx)
movq %rbx, %rax
movq $2449958197289549824, %rcx
orq %rcx, %rax
movq %rax, (%rbp)
cmpq $2, %rbx
jb LBB3_228
movl $1, %r14d
.align 4, 0x90
LBB3_227:
movq (%r13,%r14,8), %rax
movq (%rax,%r12,8), %rdi
call _gcopy
movq %rax, (%rbp,%r14,8)
incq %r14
cmpq %rbx, %r14
jl LBB3_227
LBB3_228:
movq %rbp, 280(%rsp)
movq 208(%rsp), %rcx
movl %r12d, 20(%rcx,%r15)
leaq 280(%rsp), %rax
movq %rax, (%rcx,%r15)
movq %r13, 8(%rcx,%r15)
movq 280(%rsp), %rax
movq 200(%rsp), %rcx
LBB3_229:
movq %rax, (%rcx)
jmp LBB3_230
LBB3_275:
movq 56(%r15), %rax
cmpq $20, %rax
ja LBB3_447
leaq LJTI3_3(%rip), %rcx
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmp *%rax
LBB3_261:
movq 56(%r15), %rax
cmpq $20, %rax
ja LBB3_447
leaq LJTI3_4(%rip), %rcx
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmp *%rax
LBB3_293:
xorl %eax, %eax
call *16(%r15)
jmp LBB3_273
LBB3_274:
movq _sp(%rip), %rax
leaq -2(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %rdi
movq -8(%rcx,%rax,8), %rsi
call *16(%r15)
jmp LBB3_273
LBB3_294:
movq 56(%r15), %rax
cmpq $20, %rax
ja LBB3_447
leaq LJTI3_2(%rip), %rcx
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmp *%rax
LBB3_321:
xorl %eax, %eax
call *16(%r15)
cltq
jmp LBB3_273
LBB3_323:
movq 56(%r15), %rax
cmpq $20, %rax
ja LBB3_447
leaq LJTI3_1(%rip), %rcx
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmp *%rax
LBB3_325:
xorl %eax, %eax
call *16(%r15)
jmp LBB3_446
LBB3_351:
movq %r15, %rax
notq %rax
addq _sp(%rip), %rax
movq _st(%rip), %rcx
movq (%rcx,%rax,8), %r12
movq (%r12), %rax
movq $-144115188075855872, %rcx
andq %rcx, %rax
movq $3314649325744685056, %rcx
cmpq %rcx, %rax
je LBB3_353
movl $9, %edi
xorl %eax, %eax
movq %r12, %rsi
call _pari_err
LBB3_353:
movq 8(%r12), %rbx
movq %rbx, %rbp
subq %r15, %rbp
je LBB3_358
jge LBB3_356
leaq L_.str8(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
LBB3_356:
xorl %eax, %eax
movq %rbp, %rdi
call _st_alloc
subq %r15, %rbx
jle LBB3_358
.align 4, 0x90
LBB3_357:
movq _sp(%rip), %rax
leaq 1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq $0, (%rcx,%rax,8)
decq %rbx
jne LBB3_357
LBB3_358:
movq _PARI_stack_limit@GOTPCREL(%rip), %rax
movq (%rax), %rax
testq %rax, %rax
je LBB3_361
leaq 272(%rsp), %rcx
cmpq %rax, %rcx
ja LBB3_361
leaq L_.str9(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
LBB3_361:
xorl %eax, %eax
movq %r12, %rdi
call _closure_return
cltq
movq %rax, 272(%rsp)
movq _sp(%rip), %rcx
movq _st(%rip), %rdx
movq %rax, -8(%rdx,%rcx,8)
movq 256(%rsp), %r12
jmp LBB3_446
LBB3_362:
movq _s_var+8(%rip), %rcx
leaq (%rcx,%r15), %rax
movq _s_var+16(%rip), %rdx
cmpq %rdx, %rax
jle LBB3_374
movq _s_var(%rip), %r12
testq %rdx, %rdx
movq %r15, %rsi
je LBB3_365
.align 4, 0x90
LBB3_364:
addq %rdx, %rdx
cmpq %rdx, %rax
movq %rdx, %rsi
jg LBB3_364
LBB3_365:
movq %rsi, _s_var+16(%rip)
leaq _s_var(%rip), %r14
movq (%r12,%r14), %rdi
imulq _s_var+24(%rip), %rsi
movq _PARI_SIGINT_block@GOTPCREL(%rip), %r13
movl (%r13), %ebx
movl $1, (%r13)
testq %rdi, %rdi
je LBB3_366
call _realloc
jmp LBB3_368
LBB3_377:
testq %r15, %r15
leaq _shallowcopy(%rip), %rcx
cmovne _gcopy@GOTPCREL(%rip), %rcx
movq _sp(%rip), %rax
movq _st(%rip), %rdx
movq -8(%rdx,%rax,8), %rdi
call *%rcx
movq %rax, %r14
movq 56(%r14), %rax
movq (%rax), %r13
movq $72057594037927935, %rax
andq %rax, %r13
movq _avma@GOTPCREL(%rip), %rbx
movq (%rbx), %rax
leaq 0(,%r13,8), %rcx
movq %rax, %r12
subq %rcx, %r12
movq _bot@GOTPCREL(%rip), %rcx
subq (%rcx), %rax
shrq $3, %rax
cmpq %r13, %rax
jae LBB3_379
movl $14, %edi
xorl %eax, %eax
call _pari_err
LBB3_379:
movq %r12, (%rbx)
movq %r13, %rax
movq $2449958197289549824, %rcx
orq %rcx, %rax
movq %rax, (%r12)
cmpq $2, %r13
jb LBB3_385
testq %r15, %r15
je LBB3_381
movq $-1, %rbp
movl $1, %ebx
.align 4, 0x90
LBB3_384:
movq _var(%rip), %rax
movq _s_var+8(%rip), %rcx
addq %rbp, %rcx
shlq $4, %rcx
movq 8(%rax,%rcx), %rdi
call _gcopy
movq %rax, (%r12,%rbx,8)
incq %rbx
decq %rbp
cmpq %r13, %rbx
jl LBB3_384
jmp LBB3_385
LBB3_49:
xorl %eax, %eax
movq %r15, %rdi
call _checkvalue
movq 16(%r15), %rax
jmp LBB3_273
LBB3_60:
xorl %eax, %eax
movq %r15, %rdi
call _checkvalue
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rsi
movq %r15, %rdi
call _changevalue
jmp LBB3_446
LBB3_53:
xorl %eax, %eax
call _new_ptr
movslq %eax, %rbx
xorl %eax, %eax
movq %r15, %rdi
call _checkvalue
movq $-1, 48(%rbx)
xorl %eax, %eax
movq %r15, %rdi
call _copyvalue
jmp LBB3_55
LBB3_51:
xorl %eax, %eax
call _new_ptr
movslq %eax, %rbx
movq $0, 40(%rbx)
movq %r15, 32(%rbx)
xorl %eax, %eax
movq %r15, %rdi
call _checkvalue
movq 32(%rbx), %rax
movq 16(%rax), %rax
movq %rax, 24(%rbx)
movq _sp(%rip), %rax
movq %rax, 48(%rbx)
leaq 24(%rbx), %rax
jmp LBB3_273
LBB3_50:
addq _s_var+8(%rip), %r15
movq _var(%rip), %rax
shlq $4, %r15
movq 8(%rax,%r15), %rax
jmp LBB3_273
LBB3_61:
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rsi
xorl %eax, %eax
movq %r15, %rdi
call _changelex
jmp LBB3_446
LBB3_54:
xorl %eax, %eax
call _new_ptr
movslq %eax, %rbx
movq $-1, 48(%rbx)
xorl %eax, %eax
movq %r15, %rdi
call _copylex
LBB3_55:
cltq
leaq 24(%rbx), %rcx
movq %rax, 24(%rbx)
movq $0, 16(%rbx)
movq $0, 40(%rbx)
movq $0, 32(%rbx)
movq %rax, 8(%rbx)
movq %rcx, (%rbx)
jmp LBB3_446
LBB3_52:
xorl %eax, %eax
call _new_ptr
cltq
movq %r15, 40(%rax)
movq $1, 32(%rax)
addq _s_var+8(%rip), %r15
movq _var(%rip), %rcx
shlq $4, %r15
movq 8(%rcx,%r15), %rcx
movq %rcx, 24(%rax)
movq _sp(%rip), %rcx
movq %rcx, 48(%rax)
leaq 24(%rax), %rax
jmp LBB3_273
LBB3_386:
movq _s_var+8(%rip), %rdx
leaq (%rdx,%r15), %rax
movq _s_var+16(%rip), %rcx
cmpq %rcx, %rax
jle LBB3_398
movq _s_var(%rip), %r14
testq %rcx, %rcx
movq %r15, %rsi
je LBB3_389
.align 4, 0x90
LBB3_388:
addq %rcx, %rcx
cmpq %rcx, %rax
movq %rcx, %rsi
jg LBB3_388
LBB3_389:
movq %rsi, _s_var+16(%rip)
leaq _s_var(%rip), %rax
movq (%r14,%rax), %rdi
imulq _s_var+24(%rip), %rsi
movq _PARI_SIGINT_block@GOTPCREL(%rip), %r12
movl (%r12), %ebp
movl $1, (%r12)
testq %rdi, %rdi
je LBB3_390
call _realloc
jmp LBB3_392
LBB3_232:
movq _s_var+8(%rip), %rax
addq %r15, %rax
movq _var(%rip), %rcx
shlq $4, %rax
cmpq $2, (%rcx,%rax)
jne LBB3_234
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rdi
call _closure_evalnobrk
movq %rax, %rcx
xorl %eax, %eax
movq %r15, %rdi
movq %rcx, %rsi
call _pushlex
LBB3_234:
decq _sp(%rip)
jmp LBB3_446
LBB3_235:
movq _s_lvars+8(%rip), %rbp
movq _s_lvars+16(%rip), %rax
cmpq %rax, %rbp
jl LBB3_247
movq 264(%rsp), %r14
movq _s_lvars(%rip), %r12
movl $1, %esi
testq %rax, %rax
je LBB3_238
.align 4, 0x90
LBB3_237:
addq %rax, %rax
cmpq %rax, %rbp
movq %rax, %rsi
jge LBB3_237
LBB3_238:
movq %rsi, _s_lvars+16(%rip)
leaq _s_lvars(%rip), %rax
movq (%r12,%rax), %rdi
imulq _s_lvars+24(%rip), %rsi
movq _PARI_SIGINT_block@GOTPCREL(%rip), %r13
movl (%r13), %ebx
movl $1, (%r13)
testq %rdi, %rdi
je LBB3_239
call _realloc
jmp LBB3_241
LBB3_248:
movq _s_lvars+8(%rip), %rbp
movq _s_lvars+16(%rip), %rax
cmpq %rax, %rbp
jl LBB3_260
movq 264(%rsp), %r14
movq _s_lvars(%rip), %r12
movl $1, %esi
testq %rax, %rax
je LBB3_251
.align 4, 0x90
LBB3_250:
addq %rax, %rax
cmpq %rax, %rbp
movq %rax, %rsi
jge LBB3_250
LBB3_251:
movq %rsi, _s_lvars+16(%rip)
leaq _s_lvars(%rip), %rax
movq (%r12,%rax), %rdi
imulq _s_lvars+24(%rip), %rsi
movq _PARI_SIGINT_block@GOTPCREL(%rip), %r13
movl (%r13), %ebx
movl $1, (%r13)
testq %rdi, %rdi
je LBB3_252
call _realloc
jmp LBB3_254
LBB3_406:
testq %r15, %r15
je LBB3_446
movq _sp(%rip), %rax
leaq -8(,%rax,8), %rbx
.align 4, 0x90
LBB3_408:
testb $1, %r15b
je LBB3_411
movq _st(%rip), %rax
cmpq $0, (%rax,%rbx)
jne LBB3_411
leaq L_.str10(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
.align 4, 0x90
LBB3_411:
sarq $1, %r15
addq $-8, %rbx
testq %r15, %r15
jne LBB3_408
jmp LBB3_446
LBB3_412:
testq %r15, %r15
je LBB3_446
movq _sp(%rip), %rax
leaq -8(,%rax,8), %rbx
.align 4, 0x90
LBB3_414:
testb $1, %r15b
je LBB3_417
movq _st(%rip), %rax
cmpq $0, (%rax,%rbx)
je LBB3_417
leaq L_.str11(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
call _pari_err
LBB3_417:
sarq $1, %r15
addq $-8, %rbx
testq %r15, %r15
jne LBB3_414
jmp LBB3_446
LBB3_419:
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
leaq -1(%rax,%r15), %rcx
movq _st(%rip), %rdx
cmpq $0, (%rdx,%rcx,8)
jne LBB3_446
jmp LBB3_420
LBB3_418:
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
leaq -1(%rax,%r15), %rcx
movq _st(%rip), %rdx
movq (%rdx,%rcx,8), %rbp
testq %rbp, %rbp
je LBB3_420
LBB3_114:
movq (%rbp), %rax
movq $-144115188075855872, %rcx
andq %rcx, %rax
movq $144115188075855875, %rcx
leaq -3(%rcx), %rcx
cmpq %rcx, %rax
je LBB3_116
leaq L_.str13(%rip), %rsi
movl $5, %edi
xorl %eax, %eax
movq %rbp, %rdx
call _pari_err
LBB3_116:
movq 8(%rbp), %rcx
xorl %eax, %eax
movq %rcx, %rbx
sarq $62, %rbx
movq $72057594037927935, %rdx
je LBB3_121
movq 16(%rbp), %rbp
leaq -3(%rdx), %rax
andq %rax, %rcx
cmpq $3, %rcx
ja LBB3_119
testq %rbp, %rbp
jns LBB3_120
LBB3_119:
leaq L_.str14(%rip), %rsi
movl $15, %edi
xorl %eax, %eax
call _pari_err
LBB3_120:
movq %rbp, %rax
negq %rax
testq %rbx, %rbx
cmovg %rbp, %rax
LBB3_121:
addq _sp(%rip), %r15
movq _st(%rip), %rcx
movq %rax, (%rcx,%r15,8)
jmp LBB3_446
LBB3_99:
movq _avma@GOTPCREL(%rip), %rax
movq (%rax), %rax
jmp LBB3_273
LBB3_126:
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %rbp
movq -8(%rcx,%rax,8), %rbx
movq (%rbx), %rax
movq $72057594037927935, %rcx
andq %rcx, %rax
leaq (%rbx,%rax,8), %rax
movq %rbp, %rdx
subq %rax, %rdx
cmpq $1000001, %rdx
jb LBB3_163
movq _DEBUGMEM@GOTPCREL(%rip), %rax
cmpq $2, (%rax)
jb LBB3_129
leaq L_.str1(%rip), %rsi
movl $3, %edi
xorl %eax, %eax
call _pari_warn
LBB3_129:
movq _bot@GOTPCREL(%rip), %rax
cmpq (%rax), %rbx
jb LBB3_132
cmpq %rbx, %rbp
jbe LBB3_132
movq _top@GOTPCREL(%rip), %rax
cmpq (%rax), %rbx
jae LBB3_132
movq (%rbx), %r8
movq %r8, %rax
shrq $57, %rax
leaq -21(%rax), %rdx
cmpq $2, %rdx
jb LBB3_148
cmpq $2, %rax
jne LBB3_135
LBB3_148:
movq %r8, %rax
movq $72057594037927935, %r12
andq %r12, %rax
shlq $3, %rax
movq %rbp, %r11
subq %rax, %r11
movq %r8, %rdx
andq %r12, %rdx
movq _avma@GOTPCREL(%rip), %rax
movq %r11, (%rax)
je LBB3_149
movq %r8, %rax
movq $-72057594037927936, %rcx
orq %rcx, %rax
movq %rax, %rdi
xorq %r12, %rdi
cmpq %rcx, %rax
movq $-2, %r14
movq $-2, %r15
cmove %rdi, %r15
leaq (%r15,%rdx), %rsi
cmpq $-2, %rsi
je LBB3_159
leaq 2(%r15), %rsi
leaq 2(%r15,%rdx), %r9
addl %r8d, %esi
andq $3, %rsi
cmpq %rcx, %rax
movq %r9, %rcx
cmove %rdi, %r14
xorl %r10d, %r10d
subq %rsi, %r9
je LBB3_157
movq $-2, %rax
movq $-2, %rsi
subq %r14, %rsi
leaq (%rbx,%rsi,8), %rsi
leaq -8(%rbp), %rdi
xorl %r10d, %r10d
cmpq %rsi, %rdi
ja LBB3_154
leaq -8(%rbx,%rdx,8), %rsi
addq %rdx, %r14
subq %r14, %rax
leaq (%rbp,%rax,8), %rax
cmpq %rax, %rsi
jbe LBB3_157
LBB3_154:
movq %rdx, %r10
subq %r9, %r10
leal 2(%r15,%r8), %edi
andq $3, %rdi
subq %r15, %rdi
addq $-2, %rdi
movq %rdx, %rax
LBB3_155:
movd %rax, %xmm0
pshufd $68, %xmm0, %xmm0
paddq LCPI3_0(%rip), %xmm0
movd %xmm0, %rsi
movups -8(%rbx,%rsi,8), %xmm0
movups -24(%rbx,%rsi,8), %xmm1
subq %rdx, %rsi
movups %xmm0, -8(%rbp,%rsi,8)
movups %xmm1, -24(%rbp,%rsi,8)
addq $-4, %rax
cmpq %rax, %rdi
jne LBB3_155
movq %r10, %rdx
movq %r9, %r10
LBB3_157:
cmpq %r10, %rcx
jne LBB3_159
movq %r11, %rbx
movq 240(%rsp), %r14
jmp LBB3_162
LBB3_100:
xorl %eax, %eax
movq %r15, %rdi
call _checkvalue
xorl %eax, %eax
movq %r15, %rdi
call _copyvalue
jmp LBB3_446
LBB3_101:
xorl %eax, %eax
movq %r15, %rdi
call _copylex
jmp LBB3_446
LBB3_65:
movq _avma@GOTPCREL(%rip), %rax
movq %rdi, (%rax)
LBB3_96:
movq _sp(%rip), %rax
movq _st(%rip), %rdx
movq -16(%rdx,%rax,8), %rsi
xorl %eax, %eax
movq %rcx, %rdi
call _copyupto
cltq
movq _sp(%rip), %rcx
movq _st(%rip), %rdx
movq -24(%rdx,%rcx,8), %rcx
movq %rax, (%rcx,%r15,8)
movq _avma@GOTPCREL(%rip), %rax
movq (%rax), %rax
movq _sp(%rip), %rcx
movq _st(%rip), %rdx
movq %rax, -16(%rdx,%rcx,8)
decq _sp(%rip)
jmp LBB3_446
LBB3_420:
movq -8(%rdx,%rax,8), %rax
movq %rax, (%rdx,%rcx,8)
jmp LBB3_446
LBB3_38:
movq _gen_0@GOTPCREL(%rip), %rax
movq (%rax), %r14
jmp LBB3_46
LBB3_103:
movq _gen_0@GOTPCREL(%rip), %rax
movq (%rax), %r14
jmp LBB3_112
LBB3_132:
movq _avma@GOTPCREL(%rip), %rax
movq %rbp, (%rax)
jmp LBB3_163
LBB3_175:
movq $72057594037927935, %rax
andq %rax, %rsi
xorl %eax, %eax
movq %rbp, %rdi
call _check_array_index
movq (%rbx,%rbp,8), %rdi
xorl %eax, %eax
movq %r15, %rsi
call _closure_castlong
jmp LBB3_446
LBB3_171:
movq 16(%rbx), %rbx
movl $1, %esi
testq %rbx, %rbx
je LBB3_174
movq (%rbx), %rsi
LBB3_173:
andq %rcx, %rsi
LBB3_174:
xorl %eax, %eax
movq %rbp, %rdi
call _check_array_index
movq (%rbx,%rbp,8), %rdi
xorl %eax, %eax
movq %r15, %rsi
call _closure_castgen
jmp LBB3_446
LBB3_182:
movq $72057594037927935, %rax
andq %rax, %rsi
xorl %eax, %eax
movq %rbx, %rdi
call _check_array_index
leaq (%rbp,%rbx,8), %rax
movq %rax, (%r14)
movq (%rbp,%rbx,8), %r14
testq %r14, %r14
je LBB3_183
jle LBB3_190
movq _avma@GOTPCREL(%rip), %rdx
movq (%rdx), %rbx
leaq -24(%rbx), %r13
movq _bot@GOTPCREL(%rip), %rax
movq %rbx, %rcx
subq (%rax), %rcx
cmpq $23, %rcx
ja LBB3_188
movl $14, %edi
xorl %eax, %eax
call _pari_err
movq _avma@GOTPCREL(%rip), %rdx
LBB3_188:
movq %r13, (%rdx)
movq $144115188075855875, %rax
movq %rax, -24(%rbx)
movq $4611686018427387907, %rax
jmp LBB3_189
LBB3_193:
movq 16(%rbp), %rbp
movl $1, %esi
testq %rbp, %rbp
je LBB3_196
movq (%rbp), %rsi
LBB3_195:
movq $72057594037927935, %rax
andq %rax, %rsi
LBB3_196:
xorl %eax, %eax
movq %rbx, %rdi
call _check_array_index
leaq (%rbp,%rbx,8), %rax
movq %rax, (%r14)
movq (%rbp,%rbx,8), %rax
LBB3_184:
movq 208(%rsp), %rcx
movq %rax, (%rcx)
LBB3_180:
movq 240(%rsp), %r14
LBB3_181:
movq %rbp, 8(%r15,%r12)
movq 256(%rsp), %r12
jmp LBB3_446
LBB3_43:
cmpq $23, %rax
ja LBB3_45
movl $14, %edi
xorl %eax, %eax
movq %rdx, %r15
call _pari_err
movq %r15, %rdx
LBB3_45:
movq %r14, (%rdx)
movq $144115188075855875, %rax
movq %rax, -24(%rbp)
movq $-4611686018427387901, %rax
movq %rax, -16(%rbp)
movq %rbx, -8(%rbp)
LBB3_46:
movq _sp(%rip), %rax
leaq 1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq %r14, (%rcx,%rax,8)
movq %r12, %r14
movq 256(%rsp), %r12
jmp LBB3_446
LBB3_108:
negq %rbx
movq _avma@GOTPCREL(%rip), %rdx
movq (%rdx), %rbp
leaq -24(%rbp), %r14
movq _bot@GOTPCREL(%rip), %rax
movq %rbp, %rcx
subq (%rax), %rcx
cmpq $23, %rcx
ja LBB3_110
movl $14, %edi
xorl %eax, %eax
call _pari_err
movq _avma@GOTPCREL(%rip), %rdx
LBB3_110:
movq %r14, (%rdx)
movq $144115188075855875, %rax
movq %rax, -24(%rbp)
movq $-4611686018427387901, %rax
LBB3_111:
movq %rax, -16(%rbp)
movq %rbx, -8(%rbp)
LBB3_112:
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq %r14, -8(%rcx,%rax,8)
movq %r12, %r14
movq %r15, %r12
jmp LBB3_446
LBB3_366:
movq %rsi, %rdi
call _malloc
LBB3_368:
movq %rax, %rbp
movl %ebx, (%r13)
testl %ebx, %ebx
jne LBB3_371
movq _PARI_SIGINT_pending@GOTPCREL(%rip), %rax
cmpl $0, (%rax)
je LBB3_371
movl (%rax), %edi
movl $0, (%rax)
call _raise
LBB3_371:
testq %rbp, %rbp
movq 224(%rsp), %r13
jne LBB3_373
movl $28, %edi
xorl %eax, %eax
call _pari_err
LBB3_373:
movq %rbp, (%r12,%r14)
movq _s_var+8(%rip), %rcx
movq 240(%rsp), %r14
movq 256(%rsp), %r12
LBB3_374:
addq %r15, %rcx
movq %rcx, _s_var+8(%rip)
addq %r15, 248(%rsp)
testq %r15, %r15
jle LBB3_446
shlq $4, %rcx
movq _var(%rip), %rax
movq $0, -16(%rcx,%rax)
movq _gen_0@GOTPCREL(%rip), %rax
movq (%rax), %rcx
movq _s_var+8(%rip), %rdx
shlq $4, %rdx
movq _var(%rip), %rsi
movq %rcx, -8(%rdx,%rsi)
movq $-2, %rcx
cmpq $1, %r15
je LBB3_446
.align 4, 0x90
LBB3_376:
movq _var(%rip), %rdx
movq _s_var+8(%rip), %rsi
addq %rcx, %rsi
shlq $4, %rsi
movq $0, (%rdx,%rsi)
movq (%rax), %rdx
movq _var(%rip), %rsi
movq _s_var+8(%rip), %rdi
addq %rcx, %rdi
shlq $4, %rdi
movq %rdx, 8(%rsi,%rdi)
leaq -1(%r15,%rcx), %rdx
decq %rcx
cmpq $-1, %rdx
jne LBB3_376
jmp LBB3_446
LBB3_381:
movq $-1, %rax
movl $1, %ecx
.align 4, 0x90
LBB3_382:
movq _var(%rip), %rdx
movq _s_var+8(%rip), %rsi
addq %rax, %rsi
shlq $4, %rsi
movq 8(%rdx,%rsi), %rdx
movq %rdx, (%r12,%rcx,8)
incq %rcx
decq %rax
cmpq %r13, %rcx
jl LBB3_382
LBB3_385:
movq %r12, 56(%r14)
movq _sp(%rip), %rax
movq _st(%rip), %rcx
movq %r14, -8(%rcx,%rax,8)
LBB3_230:
movq 240(%rsp), %r14
LBB3_231:
movq 224(%rsp), %r13
movq 256(%rsp), %r12
jmp LBB3_446
LBB3_390:
movq %rsi, %rdi
call _malloc
LBB3_392:
movq %rax, %r13
movl %ebp, (%r12)
testl %ebp, %ebp
jne LBB3_395
movq _PARI_SIGINT_pending@GOTPCREL(%rip), %rax
cmpl $0, (%rax)
je LBB3_395
movl (%rax), %edi
movl $0, (%rax)
call _raise
LBB3_395:
testq %r13, %r13
movq 256(%rsp), %r12
jne LBB3_397
movl $28, %edi
xorl %eax, %eax
call _pari_err
LBB3_397:
leaq _s_var(%rip), %rax
movq %r13, (%r14,%rax)
movq _s_var+8(%rip), %rdx
movq 240(%rsp), %r14
movq 224(%rsp), %r13
LBB3_398:
addq %r15, %rdx
movq %rdx, _s_var+8(%rip)
addq %r15, 248(%rsp)
movq _sp(%rip), %rax
subq %r15, %rax
movq %rax, _sp(%rip)
testq %r15, %r15
jle LBB3_446
movq %r14, %r15
xorl %ebp, %ebp
jmp LBB3_400
.align 4, 0x90
LBB3_405:
incq %rbp
movq _sp(%rip), %rax
LBB3_400:
leaq 1(%rbx,%rbp), %r14
movq _st(%rip), %rcx
addq %rbp, %rax
movq (%rcx,%rax,8), %rsi
testq %rsi, %rsi
je LBB3_402
leaq (%rbx,%rbp), %rdi
xorl %eax, %eax
call _pushlex
jmp LBB3_403
.align 4, 0x90
LBB3_402:
movq _var(%rip), %rax
leaq (%rbx,%rbp), %rcx
movq _s_var+8(%rip), %rdx
addq %rcx, %rdx
shlq $4, %rdx
movq $2, (%rax,%rdx)
movq _gen_0@GOTPCREL(%rip), %rax
movq (%rax), %rax
movq _var(%rip), %rdx
addq _s_var+8(%rip), %rcx
shlq $4, %rcx
movq %rax, 8(%rdx,%rcx)
LBB3_403:
testq %r14, %r14
jne LBB3_405
movq %r15, %r14
jmp LBB3_446
LBB3_239:
movq %rsi, %rdi
call _malloc
LBB3_241:
movq %rax, %rbp
movl %ebx, (%r13)
testl %ebx, %ebx
jne LBB3_244
movq _PARI_SIGINT_pending@GOTPCREL(%rip), %rax
cmpl $0, (%rax)
je LBB3_244
movl (%rax), %edi
movl $0, (%rax)
call _raise
LBB3_244:
testq %rbp, %rbp
movq 224(%rsp), %r13
jne LBB3_246
movl $28, %edi
xorl %eax, %eax
call _pari_err
LBB3_246:
movq %r14, 264(%rsp)
leaq _s_lvars(%rip), %rax
movq %rbp, (%r12,%rax)
movq _s_lvars+8(%rip), %rbp
movq 240(%rsp), %r14
movq 256(%rsp), %r12
LBB3_247:
leaq 1(%rbp), %rax
movq %rax, _s_lvars+8(%rip)
xorl %eax, %eax
movq %r15, %rdi
call _checkvalue
movq _lvars(%rip), %rax
movq %r15, (%rax,%rbp,8)
incq 232(%rsp)
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rsi
xorl %eax, %eax
movq %r15, %rdi
call _pushvalue
jmp LBB3_446
LBB3_252:
movq %rsi, %rdi
call _malloc
LBB3_254:
movq %rax, %rbp
movl %ebx, (%r13)
testl %ebx, %ebx
jne LBB3_257
movq _PARI_SIGINT_pending@GOTPCREL(%rip), %rax
cmpl $0, (%rax)
je LBB3_257
movl (%rax), %edi
movl $0, (%rax)
call _raise
LBB3_257:
testq %rbp, %rbp
movq 224(%rsp), %r13
jne LBB3_259
movl $28, %edi
xorl %eax, %eax
call _pari_err
LBB3_259:
movq %r14, 264(%rsp)
leaq _s_lvars(%rip), %rax
movq %rbp, (%r12,%rax)
movq _s_lvars+8(%rip), %rbp
movq 240(%rsp), %r14
movq 256(%rsp), %r12
LBB3_260:
leaq 1(%rbp), %rax
movq %rax, _s_lvars+8(%rip)
xorl %eax, %eax
movq %r15, %rdi
call _checkvalue
movq _lvars(%rip), %rax
movq %r15, (%rax,%rbp,8)
incq 232(%rsp)
xorl %eax, %eax
movq %r15, %rdi
call _zerovalue
jmp LBB3_446
LBB3_183:
movq _gen_0@GOTPCREL(%rip), %rax
movq (%rax), %rax
jmp LBB3_184
LBB3_92:
incq %rsi
movq $72057594037927935, %rax
andq %rax, %r8
shlq $3, %r8
subq %r8, %rdi
movq 240(%rsp), %r14
movq 256(%rsp), %r12
.align 4, 0x90
LBB3_93:
movq -16(%rcx,%rsi,8), %rax
movq %rax, -16(%rdi,%rsi,8)
decq %rsi
cmpq $1, %rsi
jg LBB3_93
movq %r11, %rcx
jmp LBB3_96
LBB3_277:
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rdi
xorl %eax, %eax
call *16(%r15)
jmp LBB3_273
LBB3_278:
movq _sp(%rip), %rax
leaq -2(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %rdi
movq -8(%rcx,%rax,8), %rsi
xorl %eax, %eax
call *16(%r15)
jmp LBB3_273
LBB3_279:
movq _sp(%rip), %rax
leaq -3(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -24(%rcx,%rax,8), %rdi
movq -16(%rcx,%rax,8), %rsi
movq -8(%rcx,%rax,8), %rdx
xorl %eax, %eax
call *16(%r15)
jmp LBB3_273
LBB3_280:
movq _sp(%rip), %rax
leaq -4(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -32(%rcx,%rax,8), %rdi
movq -24(%rcx,%rax,8), %rsi
movq -16(%rcx,%rax,8), %rdx
movq -8(%rcx,%rax,8), %rcx
xorl %eax, %eax
call *16(%r15)
jmp LBB3_273
LBB3_281:
movq _sp(%rip), %rax
leaq -5(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %r8
xorl %eax, %eax
call *16(%r15)
jmp LBB3_273
LBB3_282:
movq _sp(%rip), %rax
leaq -6(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -48(%rbp,%rax,8), %rdi
movq -40(%rbp,%rax,8), %rsi
movq -32(%rbp,%rax,8), %rdx
movq -24(%rbp,%rax,8), %rcx
movq -16(%rbp,%rax,8), %r8
movq -8(%rbp,%rax,8), %r9
jmp LBB3_265
LBB3_283:
movq _sp(%rip), %rax
leaq -7(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -56(%rbp,%rax,8), %rdi
movq -48(%rbp,%rax,8), %rsi
movq -40(%rbp,%rax,8), %rdx
movq -32(%rbp,%rax,8), %rcx
movq -24(%rbp,%rax,8), %r8
movq -16(%rbp,%rax,8), %r9
movq -8(%rbp,%rax,8), %rax
movq %rax, (%rsp)
jmp LBB3_265
LBB3_284:
movq _sp(%rip), %rax
leaq -8(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -64(%rbp,%rax,8), %rdi
movq -56(%rbp,%rax,8), %rsi
movq -48(%rbp,%rax,8), %rdx
movq -40(%rbp,%rax,8), %rcx
movq -32(%rbp,%rax,8), %r8
movq -24(%rbp,%rax,8), %r9
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 8(%rsp)
movq %rbx, (%rsp)
jmp LBB3_265
LBB3_263:
movq _sp(%rip), %rax
leaq -9(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -72(%rbp,%rax,8), %rdi
movq -64(%rbp,%rax,8), %rsi
movq -56(%rbp,%rax,8), %rdx
movq -48(%rbp,%rax,8), %rcx
movq -40(%rbp,%rax,8), %r8
movq -32(%rbp,%rax,8), %r9
movq -24(%rbp,%rax,8), %r10
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 16(%rsp)
movq %rbx, 8(%rsp)
jmp LBB3_264
LBB3_285:
movq _sp(%rip), %rax
leaq -10(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -80(%rbp,%rax,8), %rdi
movq -72(%rbp,%rax,8), %rsi
movq -64(%rbp,%rax,8), %rdx
movq -56(%rbp,%rax,8), %rcx
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %r9
movq -32(%rbp,%rax,8), %r10
movq -24(%rbp,%rax,8), %r11
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 24(%rsp)
movq %rbx, 16(%rsp)
movq %r11, 8(%rsp)
LBB3_264:
movq %r10, (%rsp)
LBB3_265:
xorl %eax, %eax
call *16(%r15)
jmp LBB3_273
LBB3_266:
movq _sp(%rip), %rax
leaq -11(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -88(%rbp,%rax,8), %rdi
movq -80(%rbp,%rax,8), %rsi
movq -72(%rbp,%rax,8), %rdx
movq -64(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -56(%rbp,%rax,8), %r8
movq -48(%rbp,%rax,8), %r9
movq -40(%rbp,%rax,8), %r10
movq -32(%rbp,%rax,8), %r11
movq %r12, %rcx
movq %r14, %r12
movq -24(%rbp,%rax,8), %r14
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 32(%rsp)
movq %rbx, 24(%rsp)
movq %r14, 16(%rsp)
movq %r12, %r14
movq %rcx, %r12
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
jmp LBB3_267
LBB3_286:
movq _sp(%rip), %rax
leaq -12(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -96(%rbp,%rax,8), %rdi
movq -88(%rbp,%rax,8), %rsi
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -72(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -64(%rbp,%rax,8), %r8
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r10
movq -40(%rbp,%rax,8), %r11
movq %r13, %rdx
movq %r14, %r13
movq -32(%rbp,%rax,8), %r14
movq %r12, %rcx
movq -24(%rbp,%rax,8), %r12
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 40(%rsp)
movq %rbx, 32(%rsp)
movq %r12, 24(%rsp)
movq %rcx, %r12
movq %r14, 16(%rsp)
movq %r13, %r14
movq %rdx, %r13
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq 200(%rsp), %rdx
LBB3_267:
movq 208(%rsp), %rcx
call *16(%r15)
jmp LBB3_273
LBB3_268:
movq _sp(%rip), %rax
leaq -13(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -104(%rbp,%rax,8), %rdx
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -72(%rbp,%rax,8), %r8
movq -64(%rbp,%rax,8), %r9
movq -56(%rbp,%rax,8), %r10
movq -48(%rbp,%rax,8), %r11
movq %r14, %rdi
movq -40(%rbp,%rax,8), %r14
movq %r12, %rsi
movq -32(%rbp,%rax,8), %r12
movq %r13, %rcx
movq -24(%rbp,%rax,8), %r13
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rcx, %r13
movq %r12, 24(%rsp)
movq %rsi, %r12
movq %r14, 16(%rsp)
movq %rdi, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq %rdx, %rdi
movq 208(%rsp), %rsi
movq 168(%rsp), %rdx
jmp LBB3_269
LBB3_287:
movq _sp(%rip), %rax
leaq -14(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -112(%rbp,%rax,8), %rsi
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -72(%rbp,%rax,8), %r9
movq -64(%rbp,%rax,8), %r10
movq -56(%rbp,%rax,8), %r11
movq %r14, %r8
movq -48(%rbp,%rax,8), %r14
movq %r12, %rdi
movq -40(%rbp,%rax,8), %r12
movq %r13, %rdx
movq -32(%rbp,%rax,8), %r13
movq -24(%rbp,%rax,8), %rbx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rdx, %r13
movq %r12, 24(%rsp)
movq %rdi, %r12
movq %r14, 16(%rsp)
movq %r8, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq %rsi, %rdi
movq 208(%rsp), %rsi
movq 168(%rsp), %rdx
movq 160(%rsp), %r8
LBB3_269:
movq 200(%rsp), %rcx
call *16(%r15)
jmp LBB3_273
LBB3_270:
movq _sp(%rip), %rax
leaq -15(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -120(%rbp,%rax,8), %rdi
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -72(%rbp,%rax,8), %r10
movq -64(%rbp,%rax,8), %r11
movq %r14, %r9
movq -56(%rbp,%rax,8), %r14
movq %r12, %r8
movq -48(%rbp,%rax,8), %r12
movq %r13, %rsi
movq -40(%rbp,%rax,8), %r13
movq -32(%rbp,%rax,8), %rbx
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rsi, %r13
movq %r12, 24(%rsp)
movq %r8, %r12
movq %r14, 16(%rsp)
movq %r9, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
jmp LBB3_271
LBB3_288:
movq _sp(%rip), %rax
leaq -16(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -128(%rbp,%rax,8), %r8
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -72(%rbp,%rax,8), %r11
movq %r14, %r10
movq -64(%rbp,%rax,8), %r14
movq %r12, %r9
movq -56(%rbp,%rax,8), %r12
movq %r13, %rdi
movq -48(%rbp,%rax,8), %r13
movq -40(%rbp,%rax,8), %rbx
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rdi, %r13
movq %r12, 24(%rsp)
movq %r9, %r12
movq %r14, 16(%rsp)
movq %r10, %r14
movq %r11, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r8, %rdi
jmp LBB3_271
LBB3_289:
movq _sp(%rip), %rax
leaq -17(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -136(%rbp,%rax,8), %r9
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq %r14, %r11
movq -72(%rbp,%rax,8), %r14
movq %r12, %r10
movq -64(%rbp,%rax,8), %r12
movq %r13, %r8
movq -56(%rbp,%rax,8), %r13
movq -48(%rbp,%rax,8), %rbx
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rsi, 56(%rsp)
movq %rdi, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r8, %r13
movq %r12, 24(%rsp)
movq %r10, %r12
movq %r14, 16(%rsp)
movq %r11, %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r9, %rdi
jmp LBB3_271
LBB3_290:
movq _sp(%rip), %rax
leaq -18(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -144(%rbp,%rax,8), %r10
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -80(%rbp,%rax,8), %r14
movq %r12, %r11
movq -72(%rbp,%rax,8), %r12
movq %r13, %r9
movq -64(%rbp,%rax,8), %r13
movq -56(%rbp,%rax,8), %rbx
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdi, 56(%rsp)
movq %r8, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r9, %r13
movq %r12, 24(%rsp)
movq %r11, %r12
movq %r14, 16(%rsp)
movq 240(%rsp), %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r10, %rdi
jmp LBB3_271
LBB3_291:
movq _sp(%rip), %rax
leaq -19(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -152(%rbp,%rax,8), %r11
movq -144(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 128(%rsp)
movq %r12, %r14
movq -80(%rbp,%rax,8), %r12
movq %r13, %r10
movq -72(%rbp,%rax,8), %r13
movq -64(%rbp,%rax,8), %rbx
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rsi, 72(%rsp)
movq %rdi, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r10, %r13
movq %r12, 24(%rsp)
movq %r14, %r12
movq 128(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r11, %rdi
LBB3_271:
movq 200(%rsp), %rsi
movq 160(%rsp), %r8
movq 152(%rsp), %r9
movq 208(%rsp), %rdx
movq 168(%rsp), %rcx
call *16(%r15)
jmp LBB3_273
LBB3_292:
movq _sp(%rip), %rax
leaq -20(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -160(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -152(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -144(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 128(%rsp)
movq -96(%rbp,%rax,8), %r14
movq -88(%rbp,%rax,8), %r12
movq %r13, %r11
movq -80(%rbp,%rax,8), %r13
movq -72(%rbp,%rax,8), %rbx
movq -64(%rbp,%rax,8), %r10
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdi, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movq %r10, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r11, %r13
movq %r12, 24(%rsp)
movq 256(%rsp), %r12
movq %r14, 16(%rsp)
movq 240(%rsp), %r14
movq 128(%rsp), %rax
movq %rax, 8(%rsp)
movq 136(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq 208(%rsp), %rdi
movq 168(%rsp), %rsi
movq 152(%rsp), %r8
movq 144(%rsp), %r9
movq 200(%rsp), %rdx
movq 160(%rsp), %rcx
call *16(%r15)
jmp LBB3_273
LBB3_82:
movq %r11, %rcx
jmp LBB3_96
LBB3_68:
cmpq $1, %rax
movq $72057594037927935, %rax
jne LBB3_95
movq %r12, %r8
movq 8(%rcx), %r10
movq %r10, %rbp
andq %rax, %rbp
leaq 0(,%rbp,8), %rax
movq %rdi, %r12
subq %rax, %r12
cmpq $2, %rbp
jb LBB3_80
movq %r10, %rsi
movq $72057594037927935, %rax
andq %rax, %rsi
movq %rsi, %rbx
negq %rbx
cmpq $-3, %rbx
movq $-2, %r11
movq $-2, %rax
cmovg %rbx, %rax
leaq (%rax,%rsi), %rdx
cmpq $-1, %rdx
movq %rbp, %rdx
je LBB3_78
leaq 1(%rax,%rsi), %r9
movq %r9, 208(%rsp)
incq %rax
addl %r10d, %eax
andq $3, %rax
cmpq $-3, %rbx
cmovg %rbx, %r11
xorl %r14d, %r14d
subq %rax, %r9
movq %rbp, %rdx
je LBB3_77
movq %r11, %rax
notq %rax
leaq (%rcx,%rax,8), %rax
leaq -8(%rdi), %rdx
xorl %r14d, %r14d
cmpq %rax, %rdx
ja LBB3_74
leaq -8(%rcx,%rsi,8), %rax
addq %rsi, %r11
notq %r11
leaq (%rdi,%r11,8), %rdx
cmpq %rdx, %rax
movq %rbp, %rdx
jbe LBB3_77
LBB3_74:
movq %rbp, %rdx
subq %r9, %rdx
cmpq $-3, %rbx
movq $-2, %r11
cmovg %rbx, %r11
cmpq $-2, %rbx
movl $-2, %eax
cmovg %ebx, %eax
leal 1(%r10,%rax), %ebx
andq $3, %rbx
subq %r11, %rbx
decq %rbx
LBB3_75:
movd %rsi, %xmm0
pshufd $68, %xmm0, %xmm0
paddq LCPI3_0(%rip), %xmm0
movd %xmm0, %rax
movups -8(%rcx,%rax,8), %xmm0
movups -24(%rcx,%rax,8), %xmm1
subq %rbp, %rax
movups %xmm0, -8(%rdi,%rax,8)
movups %xmm1, -24(%rdi,%rax,8)
addq $-4, %rsi
cmpq %rsi, %rbx
jne LBB3_75
movq %r9, %r14
LBB3_77:
cmpq %r14, 208(%rsp)
movq 240(%rsp), %r14
je LBB3_80
LBB3_78:
movq $72057594037927935, %rax
andq %rax, %r10
shlq $3, %r10
subq %r10, %rdi
addq $-8, %rdi
LBB3_79:
movq -8(%rcx,%rdx,8), %rax
movq %rax, (%rdi,%rdx,8)
leaq -1(%rdx), %rdx
cmpq $1, %rdx
jg LBB3_79
LBB3_80:
movq $144115188075855875, %rax
leaq -3(%rax), %rax
orq %rax, %rbp
movq %rbp, (%r12)
movq _avma@GOTPCREL(%rip), %rax
movq %r12, (%rax)
movq %r12, %rcx
movq %r8, %r12
jmp LBB3_96
LBB3_190:
negq %r14
movq _avma@GOTPCREL(%rip), %rdx
movq (%rdx), %rbx
leaq -24(%rbx), %r13
movq _bot@GOTPCREL(%rip), %rax
movq %rbx, %rcx
subq (%rax), %rcx
cmpq $23, %rcx
ja LBB3_192
movl $14, %edi
xorl %eax, %eax
call _pari_err
movq _avma@GOTPCREL(%rip), %rdx
LBB3_192:
movq %r13, (%rdx)
movq $144115188075855875, %rax
movq %rax, -24(%rbx)
movq $-4611686018427387901, %rax
LBB3_189:
movq %rax, -16(%rbx)
movq %r14, -8(%rbx)
movq 208(%rsp), %rax
movq %r13, (%rax)
movq 240(%rsp), %r14
movq 224(%rsp), %r13
jmp LBB3_181
LBB3_159:
incq %rdx
andq %r12, %r8
shlq $3, %r8
subq %r8, %rbp
movq 240(%rsp), %r14
LBB3_160:
movq -16(%rbx,%rdx,8), %rax
movq %rax, -16(%rbp,%rdx,8)
decq %rdx
cmpq $1, %rdx
jg LBB3_160
LBB3_149:
movq %r11, %rbx
jmp LBB3_162
LBB3_296:
movq _sp(%rip), %rax
leaq -1(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -8(%rcx,%rax,8), %rdi
xorl %eax, %eax
call *16(%r15)
cltq
jmp LBB3_273
LBB3_297:
movq _sp(%rip), %rax
leaq -2(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -16(%rcx,%rax,8), %rdi
movq -8(%rcx,%rax,8), %rsi
xorl %eax, %eax
call *16(%r15)
cltq
jmp LBB3_273
LBB3_298:
movq _sp(%rip), %rax
leaq -3(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -24(%rcx,%rax,8), %rdi
movq -16(%rcx,%rax,8), %rsi
movq -8(%rcx,%rax,8), %rdx
xorl %eax, %eax
call *16(%r15)
cltq
jmp LBB3_273
LBB3_299:
movq _sp(%rip), %rax
leaq -4(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rcx
movq -32(%rcx,%rax,8), %rdi
movq -24(%rcx,%rax,8), %rsi
movq -16(%rcx,%rax,8), %rdx
movq -8(%rcx,%rax,8), %rcx
xorl %eax, %eax
call *16(%r15)
cltq
jmp LBB3_273
LBB3_300:
movq _sp(%rip), %rax
leaq -5(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %r8
xorl %eax, %eax
call *16(%r15)
cltq
jmp LBB3_273
LBB3_301:
movq _sp(%rip), %rax
leaq -6(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -48(%rbp,%rax,8), %rdi
movq -40(%rbp,%rax,8), %rsi
movq -32(%rbp,%rax,8), %rdx
movq -24(%rbp,%rax,8), %rcx
movq -16(%rbp,%rax,8), %r8
movq -8(%rbp,%rax,8), %r9
jmp LBB3_306
LBB3_302:
movq _sp(%rip), %rax
leaq -7(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -56(%rbp,%rax,8), %rdi
movq -48(%rbp,%rax,8), %rsi
movq -40(%rbp,%rax,8), %rdx
movq -32(%rbp,%rax,8), %rcx
movq -24(%rbp,%rax,8), %r8
movq -16(%rbp,%rax,8), %r9
movq -8(%rbp,%rax,8), %rax
movq %rax, (%rsp)
jmp LBB3_306
LBB3_303:
movq _sp(%rip), %rax
leaq -8(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -64(%rbp,%rax,8), %rdi
movq -56(%rbp,%rax,8), %rsi
movq -48(%rbp,%rax,8), %rdx
movq -40(%rbp,%rax,8), %rcx
movq -32(%rbp,%rax,8), %r8
movq -24(%rbp,%rax,8), %r9
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 8(%rsp)
movq %rbx, (%rsp)
jmp LBB3_306
LBB3_304:
movq _sp(%rip), %rax
leaq -9(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -72(%rbp,%rax,8), %rdi
movq -64(%rbp,%rax,8), %rsi
movq -56(%rbp,%rax,8), %rdx
movq -48(%rbp,%rax,8), %rcx
movq -40(%rbp,%rax,8), %r8
movq -32(%rbp,%rax,8), %r9
movq -24(%rbp,%rax,8), %r10
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 16(%rsp)
movq %rbx, 8(%rsp)
jmp LBB3_305
LBB3_307:
movq _sp(%rip), %rax
leaq -10(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -80(%rbp,%rax,8), %rdi
movq -72(%rbp,%rax,8), %rsi
movq -64(%rbp,%rax,8), %rdx
movq -56(%rbp,%rax,8), %rcx
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %r9
movq -32(%rbp,%rax,8), %r10
movq -24(%rbp,%rax,8), %r11
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 24(%rsp)
movq %rbx, 16(%rsp)
movq %r11, 8(%rsp)
LBB3_305:
movq %r10, (%rsp)
LBB3_306:
xorl %eax, %eax
call *16(%r15)
cltq
jmp LBB3_273
LBB3_308:
movq _sp(%rip), %rax
leaq -11(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -88(%rbp,%rax,8), %rdi
movq -80(%rbp,%rax,8), %rsi
movq -72(%rbp,%rax,8), %rdx
movq -64(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -56(%rbp,%rax,8), %r8
movq -48(%rbp,%rax,8), %r9
movq -40(%rbp,%rax,8), %r10
movq -32(%rbp,%rax,8), %r11
movq %r12, %rcx
movq %r14, %r12
movq -24(%rbp,%rax,8), %r14
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 32(%rsp)
movq %rbx, 24(%rsp)
movq %r14, 16(%rsp)
movq %r12, %r14
movq %rcx, %r12
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
jmp LBB3_309
LBB3_310:
movq _sp(%rip), %rax
leaq -12(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -96(%rbp,%rax,8), %rdi
movq -88(%rbp,%rax,8), %rsi
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -72(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -64(%rbp,%rax,8), %r8
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r10
movq -40(%rbp,%rax,8), %r11
movq %r13, %rdx
movq %r14, %r13
movq -32(%rbp,%rax,8), %r14
movq %r12, %rcx
movq -24(%rbp,%rax,8), %r12
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 40(%rsp)
movq %rbx, 32(%rsp)
movq %r12, 24(%rsp)
movq %rcx, %r12
movq %r14, 16(%rsp)
movq %r13, %r14
movq %rdx, %r13
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq 200(%rsp), %rdx
LBB3_309:
movq 208(%rsp), %rcx
call *16(%r15)
cltq
jmp LBB3_273
LBB3_311:
movq _sp(%rip), %rax
leaq -13(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -104(%rbp,%rax,8), %rdx
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -72(%rbp,%rax,8), %r8
movq -64(%rbp,%rax,8), %r9
movq -56(%rbp,%rax,8), %r10
movq -48(%rbp,%rax,8), %r11
movq %r14, %rdi
movq -40(%rbp,%rax,8), %r14
movq %r12, %rsi
movq -32(%rbp,%rax,8), %r12
movq %r13, %rcx
movq -24(%rbp,%rax,8), %r13
movq -16(%rbp,%rax,8), %rbx
movq -8(%rbp,%rax,8), %rax
movq %rax, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rcx, %r13
movq %r12, 24(%rsp)
movq %rsi, %r12
movq %r14, 16(%rsp)
movq %rdi, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq %rdx, %rdi
movq 208(%rsp), %rsi
movq 168(%rsp), %rdx
jmp LBB3_312
LBB3_313:
movq _sp(%rip), %rax
leaq -14(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -112(%rbp,%rax,8), %rsi
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -72(%rbp,%rax,8), %r9
movq -64(%rbp,%rax,8), %r10
movq -56(%rbp,%rax,8), %r11
movq %r14, %r8
movq -48(%rbp,%rax,8), %r14
movq %r12, %rdi
movq -40(%rbp,%rax,8), %r12
movq %r13, %rdx
movq -32(%rbp,%rax,8), %r13
movq -24(%rbp,%rax,8), %rbx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rdx, %r13
movq %r12, 24(%rsp)
movq %rdi, %r12
movq %r14, 16(%rsp)
movq %r8, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
movq %rsi, %rdi
movq 208(%rsp), %rsi
movq 168(%rsp), %rdx
movq 160(%rsp), %r8
LBB3_312:
movq 200(%rsp), %rcx
call *16(%r15)
cltq
jmp LBB3_273
LBB3_314:
movq _sp(%rip), %rax
leaq -15(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -120(%rbp,%rax,8), %rdi
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -72(%rbp,%rax,8), %r10
movq -64(%rbp,%rax,8), %r11
movq %r14, %r9
movq -56(%rbp,%rax,8), %r14
movq %r12, %r8
movq -48(%rbp,%rax,8), %r12
movq %r13, %rsi
movq -40(%rbp,%rax,8), %r13
movq -32(%rbp,%rax,8), %rbx
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rsi, %r13
movq %r12, 24(%rsp)
movq %r8, %r12
movq %r14, 16(%rsp)
movq %r9, %r14
movq %r11, 8(%rsp)
movq %r10, (%rsp)
xorl %eax, %eax
jmp LBB3_315
LBB3_316:
movq _sp(%rip), %rax
leaq -16(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -128(%rbp,%rax,8), %r8
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -72(%rbp,%rax,8), %r11
movq %r14, %r10
movq -64(%rbp,%rax,8), %r14
movq %r12, %r9
movq -56(%rbp,%rax,8), %r12
movq %r13, %rdi
movq -48(%rbp,%rax,8), %r13
movq -40(%rbp,%rax,8), %rbx
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %rdi, %r13
movq %r12, 24(%rsp)
movq %r9, %r12
movq %r14, 16(%rsp)
movq %r10, %r14
movq %r11, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r8, %rdi
jmp LBB3_315
LBB3_317:
movq _sp(%rip), %rax
leaq -17(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -136(%rbp,%rax,8), %r9
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -80(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq %r14, %r11
movq -72(%rbp,%rax,8), %r14
movq %r12, %r10
movq -64(%rbp,%rax,8), %r12
movq %r13, %r8
movq -56(%rbp,%rax,8), %r13
movq -48(%rbp,%rax,8), %rbx
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rsi, 56(%rsp)
movq %rdi, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r8, %r13
movq %r12, 24(%rsp)
movq %r10, %r12
movq %r14, 16(%rsp)
movq %r11, %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r9, %rdi
jmp LBB3_315
LBB3_318:
movq _sp(%rip), %rax
leaq -18(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -144(%rbp,%rax,8), %r10
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -80(%rbp,%rax,8), %r14
movq %r12, %r11
movq -72(%rbp,%rax,8), %r12
movq %r13, %r9
movq -64(%rbp,%rax,8), %r13
movq -56(%rbp,%rax,8), %rbx
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdi, 56(%rsp)
movq %r8, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r9, %r13
movq %r12, 24(%rsp)
movq %r11, %r12
movq %r14, 16(%rsp)
movq 240(%rsp), %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r10, %rdi
jmp LBB3_315
LBB3_319:
movq _sp(%rip), %rax
leaq -19(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -152(%rbp,%rax,8), %r11
movq -144(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -96(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -88(%rbp,%rax,8), %rcx
movq %rcx, 128(%rsp)
movq %r12, %r14
movq -80(%rbp,%rax,8), %r12
movq %r13, %r10
movq -72(%rbp,%rax,8), %r13
movq -64(%rbp,%rax,8), %rbx
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rsi, 72(%rsp)
movq %rdi, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r10, %r13
movq %r12, 24(%rsp)
movq %r14, %r12
movq 128(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %r14
movq 136(%rsp), %rax
movq %rax, 8(%rsp)
movq 144(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq %r11, %rdi
LBB3_315:
movq 200(%rsp), %rsi
movq 160(%rsp), %r8
movq 152(%rsp), %r9
movq 208(%rsp), %rdx
movq 168(%rsp), %rcx
call *16(%r15)
cltq
jmp LBB3_273
LBB3_320:
movq _sp(%rip), %rax
leaq -20(%rax), %rcx
movq %rcx, _sp(%rip)
movq _st(%rip), %rbp
movq -160(%rbp,%rax,8), %rcx
movq %rcx, 208(%rsp)
movq -152(%rbp,%rax,8), %rcx
movq %rcx, 168(%rsp)
movq -144(%rbp,%rax,8), %rcx
movq %rcx, 200(%rsp)
movq -136(%rbp,%rax,8), %rcx
movq %rcx, 160(%rsp)
movq -128(%rbp,%rax,8), %rcx
movq %rcx, 152(%rsp)
movq -120(%rbp,%rax,8), %rcx
movq %rcx, 144(%rsp)
movq -112(%rbp,%rax,8), %rcx
movq %rcx, 136(%rsp)
movq -104(%rbp,%rax,8), %rcx
movq %rcx, 128(%rsp)
movq -96(%rbp,%rax,8), %r14
movq -88(%rbp,%rax,8), %r12
movq %r13, %r11
movq -80(%rbp,%rax,8), %r13
movq -72(%rbp,%rax,8), %rbx
movq -64(%rbp,%rax,8), %r10
movq -56(%rbp,%rax,8), %r9
movq -48(%rbp,%rax,8), %r8
movq -40(%rbp,%rax,8), %rdi
movq -32(%rbp,%rax,8), %rsi
movq -24(%rbp,%rax,8), %rdx
movq -16(%rbp,%rax,8), %rcx
movq -8(%rbp,%rax,8), %rax
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdi, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movq %r10, 48(%rsp)
movq %rbx, 40(%rsp)
movq %r13, 32(%rsp)
movq %r11, %r13
movq %r12, 24(%rsp)
movq 256(%rsp), %r12
movq %r14, 16(%rsp)
movq 240(%rsp), %r14
movq 128(%rsp), %rax
movq %rax, 8(%rsp)
movq 136(%rsp), %rax
movq %rax, (%rsp)
xorl %eax, %eax
movq 208(%rsp), %rdi
movq 168(%rsp), %rsi
movq 152(%rsp), %r8
movq 144(%rsp), %r9
movq 200(%rsp), %rdx
movq 160(%rsp), %rcx
call *16(%r15)
cltq
LBB3_273:
movq _sp(%rip), %rcx
leaq 1(%rcx), %rdx
movq %rdx, _sp(%rip)
movq _st(%rip), %rdx
movq %rax, (%rdx,%rcx,8)
.align 4, 0x90
LBB3_446:
movq 288(%rsp), %rax
incq %rax
movq %rax, 288(%rsp)
cmpq %r12, %rax
jl LBB3_26
jmp LBB3_448
LBB3_447:
leaq L_.str7(%rip), %rsi
movl $7, %edi
xorl %eax, %eax
call _pari_err
movq 176(%rsp), %rcx
movq 184(%rsp), %rax
movq %rax, _sp(%rip)
movq %rcx, _rp(%rip)
LBB3_448:
decq _s_trace+8(%rip)
xorl %eax, %eax
movq 248(%rsp), %rdi
movq 232(%rsp), %rsi
call _restore_vars
movq 216(%rsp), %rax
movq 264(%rsp), %rdi
testq (%rdi), %rax
je LBB3_450
call _gunclone
LBB3_450:
addq $296, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
ret
.align 2, 0x90
LJTI3_0:
.long L3_0_set_48
.long L3_0_set_34
.long L3_0_set_272
.long L3_0_set_36
.long L3_0_set_37
.long L3_0_set_47
.long L3_0_set_445
.long L3_0_set_102
.long L3_0_set_113
.long L3_0_set_122
.long L3_0_set_125
.long L3_0_set_165
.long L3_0_set_164
.long L3_0_set_97
.long L3_0_set_98
.long L3_0_set_421
.long L3_0_set_432
.long L3_0_set_427
.long L3_0_set_62
.long L3_0_set_167
.long L3_0_set_197
.long L3_0_set_203
.long L3_0_set_209
.long L3_0_set_56
.long L3_0_set_30
.long L3_0_set_176
.long L3_0_set_200
.long L3_0_set_206
.long L3_0_set_219
.long L3_0_set_275
.long L3_0_set_261
.long L3_0_set_274
.long L3_0_set_294
.long L3_0_set_323
.long L3_0_set_351
.long L3_0_set_362
.long L3_0_set_377
.long L3_0_set_49
.long L3_0_set_60
.long L3_0_set_53
.long L3_0_set_51
.long L3_0_set_50
.long L3_0_set_61
.long L3_0_set_54
.long L3_0_set_52
.long L3_0_set_386
.long L3_0_set_232
.long L3_0_set_235
.long L3_0_set_248
.long L3_0_set_406
.long L3_0_set_412
.long L3_0_set_419
.long L3_0_set_418
.long L3_0_set_99
.long L3_0_set_126
.long L3_0_set_100
.long L3_0_set_101
LJTI3_1:
.long L3_1_set_325
.long L3_1_set_326
.long L3_1_set_327
.long L3_1_set_328
.long L3_1_set_329
.long L3_1_set_330
.long L3_1_set_331
.long L3_1_set_332
.long L3_1_set_333
.long L3_1_set_334
.long L3_1_set_337
.long L3_1_set_338
.long L3_1_set_340
.long L3_1_set_341
.long L3_1_set_343
.long L3_1_set_344
.long L3_1_set_346
.long L3_1_set_347
.long L3_1_set_348
.long L3_1_set_349
.long L3_1_set_350
LJTI3_2:
.long L3_2_set_321
.long L3_2_set_296
.long L3_2_set_297
.long L3_2_set_298
.long L3_2_set_299
.long L3_2_set_300
.long L3_2_set_301
.long L3_2_set_302
.long L3_2_set_303
.long L3_2_set_304
.long L3_2_set_307
.long L3_2_set_308
.long L3_2_set_310
.long L3_2_set_311
.long L3_2_set_313
.long L3_2_set_314
.long L3_2_set_316
.long L3_2_set_317
.long L3_2_set_318
.long L3_2_set_319
.long L3_2_set_320
LJTI3_3:
.long L3_3_set_293
.long L3_3_set_277
.long L3_3_set_278
.long L3_3_set_279
.long L3_3_set_280
.long L3_3_set_281
.long L3_3_set_282
.long L3_3_set_283
.long L3_3_set_284
.long L3_3_set_263
.long L3_3_set_285
.long L3_3_set_266
.long L3_3_set_286
.long L3_3_set_268
.long L3_3_set_287
.long L3_3_set_270
.long L3_3_set_288
.long L3_3_set_289
.long L3_3_set_290
.long L3_3_set_291
.long L3_3_set_292
LJTI3_4:
.long L3_4_set_293
.long L3_4_set_277
.long L3_4_set_278
.long L3_4_set_279
.long L3_4_set_280
.long L3_4_set_281
.long L3_4_set_282
.long L3_4_set_283
.long L3_4_set_284
.long L3_4_set_263
.long L3_4_set_285
.long L3_4_set_266
.long L3_4_set_286
.long L3_4_set_268
.long L3_4_set_287
.long L3_4_set_270
.long L3_4_set_288
.long L3_4_set_289
.long L3_4_set_290
.long L3_4_set_291
.long L3_4_set_292
.align 4, 0x90
_shallowcopy:
pushq %rbp
Ltmp25:
pushq %r15
Ltmp26:
pushq %r14
Ltmp27:
pushq %r13
Ltmp28:
pushq %r12
Ltmp29:
pushq %rbx
Ltmp30:
subq $56, %rsp
Ltmp31:
Ltmp32:
Ltmp33:
Ltmp34:
Ltmp35:
Ltmp36:
Ltmp37:
movq %rdi, 48(%rsp)
movq $72057594037927935, %r13
movq (%rdi), %rbx
movq %rbx, %r14
andq %r13, %r14
movq %r14, 16(%rsp)
movq _avma@GOTPCREL(%rip), %r15
movq (%r15), %rcx
movq %rcx, 24(%rsp)
leaq 0(,%r14,8), %rax
movq %rcx, %rbp
subq %rax, %rbp
movq _bot@GOTPCREL(%rip), %r9
movq %rcx, %rax
subq (%r9), %rax
shrq $3, %rax
movq %rbx, %rcx
shrq $57, %rcx
cmpq $19, %rcx
jne LBB4_22
cmpq %r14, %rax
jae LBB4_3
movl $14, %edi
xorl %eax, %eax
call _pari_err
movq _bot@GOTPCREL(%rip), %r9
LBB4_3:
movq %r15, %r8
movq %rbp, (%r8)
movq 48(%rsp), %rax
movq (%rax), %rax
movq $-72057594037927937, %rcx
andq %rcx, %rax
movq %rax, (%rbp)
movq %rbp, 8(%rsp)
cmpq $2, %r14
jb LBB4_35
movdqa LCPI4_0(%rip), %xmm2
movq %r14, %rdi
.align 4, 0x90
LBB4_5:
movq 48(%rsp), %rax
movq -8(%rax,%rdi,8), %r12
movq (%r12), %rdx
movq %rdx, %r15
andq %r13, %r15
movq (%r8), %rbp
leaq 0(,%r15,8), %rax
movq %rbp, %rsi
subq %rax, %rsi
movq %rbp, %rax
subq (%r9), %rax
shrq $3, %rax
cmpq %r15, %rax
jae LBB4_7
movq %rdi, 32(%rsp)
movl $14, %edi
xorl %eax, %eax
movq %r9, %rbx
movq %rsi, 40(%rsp)
movq %rdx, %r13
call _pari_err
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
movdqa LCPI4_0(%rip), %xmm2
movq %rbx, %r9
movq $72057594037927935, %r13
movq 16(%rsp), %r14
movq _avma@GOTPCREL(%rip), %r8
LBB4_7:
decq %rdi
movq %rsi, (%r8)
movq (%r12), %rax
movq $-72057594037927937, %rcx
andq %rcx, %rax
movq %rax, (%rsi)
cmpq $2, %r15
jb LBB4_21
movq %rdx, %rcx
andq %r13, %rcx
movq %rdx, %rbx
movq %rcx, %r11
negq %r11
cmpq $-3, %r11
movq $-2, %rax
cmovg %r11, %rax
leaq (%rax,%rcx), %rdx
cmpq $-1, %rdx
je LBB4_19
movq %rsi, 40(%rsp)
movq %rdi, 32(%rsp)
leaq 1(%rax,%rcx), %rdx
incq %rax
addl %ebx, %eax
movq %rbx, %rsi
andq $3, %rax
cmpq $-3, %r11
movq $-2, %rdi
cmovg %r11, %rdi
movq %rdx, %r10
subq %rax, %r10
jne LBB4_12
xorl %r10d, %r10d
jmp LBB4_11
LBB4_12:
movq %rdi, %rax
notq %rax
leaq (%r12,%rax,8), %r9
leaq -8(%rbp), %rax
cmpq %r9, %rax
ja LBB4_15
leaq -8(%r12,%rcx,8), %rax
addq %rcx, %rdi
notq %rdi
leaq (%rbp,%rdi,8), %rdi
cmpq %rdi, %rax
ja LBB4_15
xorl %r10d, %r10d
movq _bot@GOTPCREL(%rip), %r9
LBB4_11:
movq 32(%rsp), %rdi
movq %rsi, %rbx
jmp LBB4_18
LBB4_15:
movq %r15, %rax
subq %r10, %rax
movq %rax, (%rsp)
cmpq $-3, %r11
movq $-2, %rax
cmovg %r11, %rax
cmpq $-2, %r11
movl $-2, %edi
cmovle %edi, %r11d
movq %rsi, %rdi
leal 1(%rdi,%r11), %esi
movq %rdi, %rbx
andq $3, %rsi
subq %rax, %rsi
decq %rsi
movq _bot@GOTPCREL(%rip), %r9
.align 4, 0x90
LBB4_16:
movd %rcx, %xmm0
pshufd $68, %xmm0, %xmm0
paddq %xmm2, %xmm0
movd %xmm0, %rax
movdqu -8(%r12,%rax,8), %xmm0
movups -24(%r12,%rax,8), %xmm1
subq %r15, %rax
movdqu %xmm0, -8(%rbp,%rax,8)
movups %xmm1, -24(%rbp,%rax,8)
addq $-4, %rcx
cmpq %rcx, %rsi
jne LBB4_16
movq (%rsp), %r15
movq 32(%rsp), %rdi
LBB4_18:
cmpq %r10, %rdx
movq 40(%rsp), %rsi
je LBB4_21
LBB4_19:
andq %r13, %rbx
shlq $3, %rbx
subq %rbx, %rbp
addq $-8, %rbp
.align 4, 0x90
LBB4_20:
movq -8(%r12,%r15,8), %rax
movq %rax, (%rbp,%r15,8)
leaq -1(%r15), %r15
cmpq $1, %r15
jg LBB4_20
LBB4_21:
movq %rdi, %rax
subq %r14, %rax
movq 24(%rsp), %rcx
movq %rsi, (%rcx,%rax,8)
cmpq $1, %rdi
jg LBB4_5
jmp LBB4_35
LBB4_22:
cmpq %r14, %rax
jae LBB4_24
movl $14, %edi
xorl %eax, %eax
call _pari_err
LBB4_24:
movq %rbp, (%r15)
movq $-72057594037927937, %rax
movq 48(%rsp), %rcx
andq (%rcx), %rax
movq %rax, (%rbp)
movq %rbp, 8(%rsp)
cmpq $2, %r14
jb LBB4_35
andq %rbx, %r13
movq %r13, %rdx
negq %rdx
cmpq $-3, %rdx
movq $-2, %rsi
movq $-2, %rax
cmovg %rdx, %rax
addq %r13, %rax
cmpq $-1, %rax
je LBB4_33
incq %rax
cmpq $-3, %rdx
cmovg %rdx, %rsi
xorl %edi, %edi
movq %rax, %r9
andq $-4, %r9
je LBB4_32
movq %rsi, %rdi
notq %rdi
movq 48(%rsp), %rcx
leaq (%rcx,%rdi,8), %rbp
movq 24(%rsp), %rcx
leaq -8(%rcx), %rcx
xorl %edi, %edi
cmpq %rbp, %rcx
ja LBB4_29
movq 48(%rsp), %rcx
leaq -8(%rcx,%r13,8), %rcx
addq %r13, %rsi
notq %rsi
movq 24(%rsp), %rbp
leaq (%rbp,%rsi,8), %rsi
cmpq %rsi, %rcx
jbe LBB4_32
LBB4_29:
movq %r14, %rsi
subq %r9, %rsi
cmpq $-3, %rdx
movq $-2, %rcx
cmovg %rdx, %rcx
leaq 1(%rcx,%r13), %rdx
andq $-4, %rdx
movdqa LCPI4_0(%rip), %xmm0
.align 4, 0x90
LBB4_30:
movd %r13, %xmm1
pshufd $68, %xmm1, %xmm1
paddq %xmm0, %xmm1
movd %xmm1, %rcx
movq 48(%rsp), %rdi
movups -8(%rdi,%rcx,8), %xmm1
movdqu -24(%rdi,%rcx,8), %xmm2
subq %r14, %rcx
movq 24(%rsp), %rdi
movups %xmm1, -8(%rdi,%rcx,8)
movdqu %xmm2, -24(%rdi,%rcx,8)
addq $-4, %r13
addq $-4, %rdx
jne LBB4_30
movq %rsi, %r14
movq %r9, %rdi
LBB4_32:
cmpq %rdi, %rax
je LBB4_35
LBB4_33:
notq %rbx
movq $2233785415175766016, %rax
orq %rbx, %rax
movq 24(%rsp), %rcx
leaq (%rcx,%rax,8), %rax
.align 4, 0x90
LBB4_34:
movq 48(%rsp), %rcx
movq -8(%rcx,%r14,8), %rcx
movq %rcx, (%rax,%r14,8)
leaq -1(%r14), %r14
cmpq $1, %r14
jg LBB4_34
LBB4_35:
movq 8(%rsp), %rax
addq $56, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
ret
# ----------------------
.section __TEXT,__literal16,16byte_literals
.align 4
LCPI3_0:
.quad -1
.quad -2
.align 4
LCPI4_0:
.quad -1
.quad -2
# ----------------------
.zerofill __DATA,__bss,_sp,8,3
# ----------------------
.zerofill __DATA,__bss,_s_st,32,3
# ----------------------
.zerofill __DATA,__bss,_st,8,3
# ----------------------
.zerofill __DATA,__bss,_rp,8,3
# ----------------------
.zerofill __DATA,__bss,_s_ptrs,32,3
# ----------------------
.zerofill __DATA,__bss,_ptrs,8,3
# ----------------------
.zerofill __DATA,__bss,_s_var,32,3
# ----------------------
.zerofill __DATA,__bss,_var,8,3
# ----------------------
.zerofill __DATA,__bss,_s_lvars,32,3
# ----------------------
.zerofill __DATA,__bss,_lvars,8,3
# ----------------------
.zerofill __DATA,__bss,_s_trace,32,3
# ----------------------
.zerofill __DATA,__bss,_trace,8,3
# ----------------------
.section __TEXT,__cstring,cstring_literals
L_.str:
.asciz "closure_eval, stack underflow"
L_.str1:
.asciz "eval: recovering %ld bytes"
L_.str2:
.asciz "_[_]: not a vector"
L_.str3:
.asciz "_[_,_]: not a matrix"
L_.str4:
.asciz "_[,_]: not a matrix"
L_.str5:
.asciz "_[_,]: not a matrix"
L_.str6:
.asciz "a 0x0 matrix has no elements"
L_.str7:
.asciz "functions with more than 20 parameters"
L_.str8:
.asciz "too many parameters in user-defined function call"
L_.str9:
.asciz "deep recursion"
L_.str10:
.asciz "missing mandatory argument"
L_.str11:
.asciz "argument type not implemented"
L_.str12:
.asciz "lg()"
L_.str13:
.asciz "gtos expected an integer, got '%Ps'"
L_.str14:
.asciz "t_INT-->long assignment"
# ----------------------
.set L3_0_set_48,LBB3_48-LJTI3_0
.set L3_0_set_34,LBB3_34-LJTI3_0
.set L3_0_set_272,LBB3_272-LJTI3_0
.set L3_0_set_36,LBB3_36-LJTI3_0
.set L3_0_set_37,LBB3_37-LJTI3_0
.set L3_0_set_47,LBB3_47-LJTI3_0
.set L3_0_set_445,LBB3_445-LJTI3_0
.set L3_0_set_102,LBB3_102-LJTI3_0
.set L3_0_set_113,LBB3_113-LJTI3_0
.set L3_0_set_122,LBB3_122-LJTI3_0
.set L3_0_set_125,LBB3_125-LJTI3_0
.set L3_0_set_165,LBB3_165-LJTI3_0
.set L3_0_set_164,LBB3_164-LJTI3_0
.set L3_0_set_97,LBB3_97-LJTI3_0
.set L3_0_set_98,LBB3_98-LJTI3_0
.set L3_0_set_421,LBB3_421-LJTI3_0
.set L3_0_set_432,LBB3_432-LJTI3_0
.set L3_0_set_427,LBB3_427-LJTI3_0
.set L3_0_set_62,LBB3_62-LJTI3_0
.set L3_0_set_167,LBB3_167-LJTI3_0
.set L3_0_set_197,LBB3_197-LJTI3_0
.set L3_0_set_203,LBB3_203-LJTI3_0
.set L3_0_set_209,LBB3_209-LJTI3_0
.set L3_0_set_56,LBB3_56-LJTI3_0
.set L3_0_set_30,LBB3_30-LJTI3_0
.set L3_0_set_176,LBB3_176-LJTI3_0
.set L3_0_set_200,LBB3_200-LJTI3_0
.set L3_0_set_206,LBB3_206-LJTI3_0
.set L3_0_set_219,LBB3_219-LJTI3_0
.set L3_0_set_275,LBB3_275-LJTI3_0
.set L3_0_set_261,LBB3_261-LJTI3_0
.set L3_0_set_274,LBB3_274-LJTI3_0
.set L3_0_set_294,LBB3_294-LJTI3_0
.set L3_0_set_323,LBB3_323-LJTI3_0
.set L3_0_set_351,LBB3_351-LJTI3_0
.set L3_0_set_362,LBB3_362-LJTI3_0
.set L3_0_set_377,LBB3_377-LJTI3_0
.set L3_0_set_49,LBB3_49-LJTI3_0
.set L3_0_set_60,LBB3_60-LJTI3_0
.set L3_0_set_53,LBB3_53-LJTI3_0
.set L3_0_set_51,LBB3_51-LJTI3_0
.set L3_0_set_50,LBB3_50-LJTI3_0
.set L3_0_set_61,LBB3_61-LJTI3_0
.set L3_0_set_54,LBB3_54-LJTI3_0
.set L3_0_set_52,LBB3_52-LJTI3_0
.set L3_0_set_386,LBB3_386-LJTI3_0
.set L3_0_set_232,LBB3_232-LJTI3_0
.set L3_0_set_235,LBB3_235-LJTI3_0
.set L3_0_set_248,LBB3_248-LJTI3_0
.set L3_0_set_406,LBB3_406-LJTI3_0
.set L3_0_set_412,LBB3_412-LJTI3_0
.set L3_0_set_419,LBB3_419-LJTI3_0
.set L3_0_set_418,LBB3_418-LJTI3_0
.set L3_0_set_99,LBB3_99-LJTI3_0
.set L3_0_set_126,LBB3_126-LJTI3_0
.set L3_0_set_100,LBB3_100-LJTI3_0
.set L3_0_set_101,LBB3_101-LJTI3_0
.set L3_1_set_325,LBB3_325-LJTI3_1
.set L3_1_set_326,LBB3_326-LJTI3_1
.set L3_1_set_327,LBB3_327-LJTI3_1
.set L3_1_set_328,LBB3_328-LJTI3_1
.set L3_1_set_329,LBB3_329-LJTI3_1
.set L3_1_set_330,LBB3_330-LJTI3_1
.set L3_1_set_331,LBB3_331-LJTI3_1
.set L3_1_set_332,LBB3_332-LJTI3_1
.set L3_1_set_333,LBB3_333-LJTI3_1
.set L3_1_set_334,LBB3_334-LJTI3_1
.set L3_1_set_337,LBB3_337-LJTI3_1
.set L3_1_set_338,LBB3_338-LJTI3_1
.set L3_1_set_340,LBB3_340-LJTI3_1
.set L3_1_set_341,LBB3_341-LJTI3_1
.set L3_1_set_343,LBB3_343-LJTI3_1
.set L3_1_set_344,LBB3_344-LJTI3_1
.set L3_1_set_346,LBB3_346-LJTI3_1
.set L3_1_set_347,LBB3_347-LJTI3_1
.set L3_1_set_348,LBB3_348-LJTI3_1
.set L3_1_set_349,LBB3_349-LJTI3_1
.set L3_1_set_350,LBB3_350-LJTI3_1
.set L3_2_set_321,LBB3_321-LJTI3_2
.set L3_2_set_296,LBB3_296-LJTI3_2
.set L3_2_set_297,LBB3_297-LJTI3_2
.set L3_2_set_298,LBB3_298-LJTI3_2
.set L3_2_set_299,LBB3_299-LJTI3_2
.set L3_2_set_300,LBB3_300-LJTI3_2
.set L3_2_set_301,LBB3_301-LJTI3_2
.set L3_2_set_302,LBB3_302-LJTI3_2
.set L3_2_set_303,LBB3_303-LJTI3_2
.set L3_2_set_304,LBB3_304-LJTI3_2
.set L3_2_set_307,LBB3_307-LJTI3_2
.set L3_2_set_308,LBB3_308-LJTI3_2
.set L3_2_set_310,LBB3_310-LJTI3_2
.set L3_2_set_311,LBB3_311-LJTI3_2
.set L3_2_set_313,LBB3_313-LJTI3_2
.set L3_2_set_314,LBB3_314-LJTI3_2
.set L3_2_set_316,LBB3_316-LJTI3_2
.set L3_2_set_317,LBB3_317-LJTI3_2
.set L3_2_set_318,LBB3_318-LJTI3_2
.set L3_2_set_319,LBB3_319-LJTI3_2
.set L3_2_set_320,LBB3_320-LJTI3_2
.set L3_3_set_293,LBB3_293-LJTI3_3
.set L3_3_set_277,LBB3_277-LJTI3_3
.set L3_3_set_278,LBB3_278-LJTI3_3
.set L3_3_set_279,LBB3_279-LJTI3_3
.set L3_3_set_280,LBB3_280-LJTI3_3
.set L3_3_set_281,LBB3_281-LJTI3_3
.set L3_3_set_282,LBB3_282-LJTI3_3
.set L3_3_set_283,LBB3_283-LJTI3_3
.set L3_3_set_284,LBB3_284-LJTI3_3
.set L3_3_set_263,LBB3_263-LJTI3_3
.set L3_3_set_285,LBB3_285-LJTI3_3
.set L3_3_set_266,LBB3_266-LJTI3_3
.set L3_3_set_286,LBB3_286-LJTI3_3
.set L3_3_set_268,LBB3_268-LJTI3_3
.set L3_3_set_287,LBB3_287-LJTI3_3
.set L3_3_set_270,LBB3_270-LJTI3_3
.set L3_3_set_288,LBB3_288-LJTI3_3
.set L3_3_set_289,LBB3_289-LJTI3_3
.set L3_3_set_290,LBB3_290-LJTI3_3
.set L3_3_set_291,LBB3_291-LJTI3_3
.set L3_3_set_292,LBB3_292-LJTI3_3
.set L3_4_set_293,LBB3_293-LJTI3_4
.set L3_4_set_277,LBB3_277-LJTI3_4
.set L3_4_set_278,LBB3_278-LJTI3_4
.set L3_4_set_279,LBB3_279-LJTI3_4
.set L3_4_set_280,LBB3_280-LJTI3_4
.set L3_4_set_281,LBB3_281-LJTI3_4
.set L3_4_set_282,LBB3_282-LJTI3_4
.set L3_4_set_283,LBB3_283-LJTI3_4
.set L3_4_set_284,LBB3_284-LJTI3_4
.set L3_4_set_263,LBB3_263-LJTI3_4
.set L3_4_set_285,LBB3_285-LJTI3_4
.set L3_4_set_266,LBB3_266-LJTI3_4
.set L3_4_set_286,LBB3_286-LJTI3_4
.set L3_4_set_268,LBB3_268-LJTI3_4
.set L3_4_set_287,LBB3_287-LJTI3_4
.set L3_4_set_270,LBB3_270-LJTI3_4
.set L3_4_set_288,LBB3_288-LJTI3_4
.set L3_4_set_289,LBB3_289-LJTI3_4
.set L3_4_set_290,LBB3_290-LJTI3_4
.set L3_4_set_291,LBB3_291-LJTI3_4
.set L3_4_set_292,LBB3_292-LJTI3_4
.subsections_via_symbols
|
Name: mn_hp_smram.asm
Type: file
Size: 60691
Last-Modified: '1993-08-25T02:45:12Z'
SHA-1: BCD251515AA1ED6D46A342E9F1F647CAD2C6D8AD
Description: null
|
/*
* RateGroupDriverImplTester.hpp
*
* Created on: June 19, 2015
* Author: tcanham
*/
#ifndef RATEGROUPDRIVER_TEST_UT_RATEGROUPDRIVERIMPLTESTER_HPP_
#define RATEGROUPDRIVER_TEST_UT_RATEGROUPDRIVERIMPLTESTER_HPP_
#include <GTestBase.hpp>
#include <Svc/RateGroupDriver/RateGroupDriverImpl.hpp>
namespace Svc {
class RateGroupDriverImplTester: public RateGroupDriverGTestBase {
public:
RateGroupDriverImplTester(Svc::RateGroupDriverImpl& inst);
virtual ~RateGroupDriverImplTester();
void init(NATIVE_INT_TYPE instance = 0);
void runSchedNominal(NATIVE_INT_TYPE dividers[], NATIVE_INT_TYPE numDividers);
private:
void from_CycleOut_handler(NATIVE_INT_TYPE portNum, Svc::TimerVal& cycleStart);
Svc::RateGroupDriverImpl& m_impl;
void clearPortCalls(void);
bool m_portCalls[3];
};
} /* namespace Svc */
#endif /* RATEGROUPDRIVER_TEST_UT_ACTIVELOGGERIMPLTESTER_HPP_ */
|
; A090443: a(n) = (n+2)! * (n+1)! * n! / 2.
; Submitted by Jon Maiga
; 1,6,144,8640,1036800,217728000,73156608000,36870930432000,26547069911040000,26281599211929600000,34691710959747072000000,59530976006925975552000000,130015651599126330605568000000,354942728865614882553200640000000,1192607568988466005378754150400000000,4865838881472941301945316933632000000000,23823147163691520614324271707062272000000000,138507777609702500851681315704860049408000000000,947393198850365105825500199421242737950720000000000,7560197726825913544487491591381517048846745600000000000
mov $1,1
mov $2,2
lpb $0
mul $1,$0
sub $0,1
mul $1,$2
add $2,1
mul $1,$2
lpe
mov $0,$1
|
; A083878: a(0)=1, a(1)=3, a(n)=6a(n-1)-7a(n-2), n>=2.
; 1,3,11,45,193,843,3707,16341,72097,318195,1404491,6199581,27366049,120799227,533233019,2353803525,10390190017,45864515427,202455762443,893682966669,3944907462913,17413664010795,76867631824379
lpb $0
sub $0,1
mov $2,$0
max $2,0
seq $2,86351 ; T(n,3) of A086350.
add $1,$2
lpe
mul $1,2
add $1,1
mov $0,$1
|
#if ((defined(_MSC_VER) && _MSC_VER >= 1700) || (__cplusplus >= 201103L))
#include "../test.h"
#ifdef _MSC_VER
#define noexcept
#define snprintf _snprintf
#endif
#include "dropbox-json11/json11.cpp"
using namespace json11;
static void GenStat(Stat& stat, const Json& v) {
switch (v.type()) {
case Json::ARRAY:
for (auto const& i : v.array_items())
GenStat(stat, i);
stat.arrayCount++;
stat.elementCount += v.array_items().size();
break;
case Json::OBJECT:
for (auto const& i : v.object_items()) {
GenStat(stat, i.second);
stat.stringLength += i.first.size();
}
stat.objectCount++;
stat.memberCount += v.object_items().size();
stat.stringCount += v.object_items().size();
break;
case Json::STRING:
stat.stringCount++;
stat.stringLength += v.string_value().size();
break;
case Json::NUMBER:
stat.numberCount++;
break;
case Json::BOOL:
if (v.bool_value())
stat.trueCount++;
else
stat.falseCount++;
break;
case Json::NUL:
stat.nullCount++;
break;
}
}
class Dropboxjson11ParseResult : public ParseResultBase {
public:
Json root;
};
class Dropboxjson11StringResult : public StringResultBase {
public:
virtual const char* c_str() const { return s.c_str(); }
std::string s;
};
class Dropboxjson11Test : public TestBase {
public:
#if TEST_INFO
virtual const char* GetName() const { return "dropbox/json11 (C++11)"; }
virtual const char* GetFilename() const { return __FILE__; }
#endif
#if TEST_PARSE
virtual ParseResultBase* Parse(const char* json, size_t length) const {
(void)length;
Dropboxjson11ParseResult* pr = new Dropboxjson11ParseResult;
std::string err;
pr->root = Json::parse(json, err);
if (!err.empty()) {
delete pr;
return 0;
}
return pr;
}
#endif
#if TEST_STRINGIFY
virtual StringResultBase* Stringify(const ParseResultBase* parseResult) const {
const Dropboxjson11ParseResult* pr = static_cast<const Dropboxjson11ParseResult*>(parseResult);
Dropboxjson11StringResult* sr = new Dropboxjson11StringResult;
pr->root.dump(sr->s);
return sr;
}
#endif
#if TEST_STATISTICS
virtual bool Statistics(const ParseResultBase* parseResult, Stat* stat) const {
const Dropboxjson11ParseResult* pr = static_cast<const Dropboxjson11ParseResult*>(parseResult);
memset(stat, 0, sizeof(Stat));
GenStat(*stat, pr->root);
return true;
}
#endif
#if TEST_CONFORMANCE
virtual bool ParseDouble(const char* json, double* d) const {
Json root;
std::string err;
root = Json::parse(json, err);
if (err.empty() && root.is_array() && root.array_items().size() == 1 && root.array_items()[0].is_number()) {
*d = root.array_items()[0].number_value();
return true;
}
else
return false;
}
virtual bool ParseString(const char* json, std::string& s) const {
Json root;
std::string err;
root = Json::parse(json, err);
if (err.empty() && root.is_array() && root.array_items().size() == 1 && root.array_items()[0].is_string()) {
s = root.array_items()[0].string_value();
return true;
}
else
return false;
}
#endif
};
REGISTER_TEST(Dropboxjson11Test);
#endif
|
; battle commands are defined in engine/battle/effect_commands.asm
dw 0 ; padding
BattleCommandPointers:
; entries correspond to macros/scripts/battle_commands.asm
dw BattleCommand_CheckTurn
dw BattleCommand_CheckObedience
dw BattleCommand_UsedMoveText
dw BattleCommand_DoTurn
dw BattleCommand_Critical
dw BattleCommand_DamageStats
dw BattleCommand_Stab
dw BattleCommand_DamageVariation
dw BattleCommand_CheckHit
dw BattleCommand_LowerSub
dw BattleCommand_MoveAnimNoSub
dw BattleCommand_RaiseSub
dw BattleCommand_FailureText
dw BattleCommand_ApplyDamage
dw BattleCommand_CriticalText
dw BattleCommand_SuperEffectiveText
dw BattleCommand_CheckFaint
dw BattleCommand_BuildOpponentRage
dw BattleCommand_PoisonTarget
dw BattleCommand_SleepTarget
dw BattleCommand_DrainTarget
dw BattleCommand_EatDream
dw BattleCommand_BurnTarget
dw BattleCommand_FreezeTarget
dw BattleCommand_ParalyzeTarget
dw BattleCommand_Selfdestruct
dw BattleCommand_MirrorMove
dw BattleCommand_StatUp
dw BattleCommand_StatDown
dw BattleCommand_PayDay
dw BattleCommand_Conversion
dw BattleCommand_ResetStats
dw BattleCommand_StoreEnergy
dw BattleCommand_UnleashEnergy
dw BattleCommand_ForceSwitch
dw BattleCommand_EndLoop
dw BattleCommand_FlinchTarget
dw BattleCommand_OHKO
dw BattleCommand_Recoil
dw BattleCommand_Mist
dw BattleCommand_FocusEnergy
dw BattleCommand_Confuse
dw BattleCommand_ConfuseTarget
dw BattleCommand_Heal
dw BattleCommand_Transform
dw BattleCommand_Screen
dw BattleCommand_Poison
dw BattleCommand_Paralyze
dw BattleCommand_Substitute
dw BattleCommand_RechargeNextTurn
dw BattleCommand_Mimic
dw BattleCommand_Metronome
dw BattleCommand_LeechSeed
dw BattleCommand_Splash
dw BattleCommand_Disable
dw BattleCommand_ClearText
dw BattleCommand_Charge
dw BattleCommand_CheckCharge
dw BattleCommand_TrapTarget
dw BattleCommand3c
dw BattleCommand_Rampage
dw BattleCommand_CheckRampage
dw BattleCommand_ConstantDamage
dw BattleCommand_Counter
dw BattleCommand_Encore
dw BattleCommand_PainSplit
dw BattleCommand_Snore
dw BattleCommand_Conversion2
dw BattleCommand_LockOn
dw BattleCommand_Sketch
dw BattleCommand_DefrostOpponent
dw BattleCommand_SleepTalk
dw BattleCommand_DestinyBond
dw BattleCommand_Spite
dw BattleCommand_FalseSwipe
dw BattleCommand_HealBell
dw BattleCommand_HeldFlinch
dw BattleCommand_TripleKick
dw BattleCommand_KickCounter
dw BattleCommand_Thief
dw BattleCommand_ArenaTrap
dw BattleCommand_Nightmare
dw BattleCommand_Defrost
dw BattleCommand_Curse
dw BattleCommand_Protect
dw BattleCommand_Spikes
dw BattleCommand_Foresight
dw BattleCommand_PerishSong
dw BattleCommand_StartSandstorm
dw BattleCommand_Endure
dw BattleCommand_CheckCurl
dw BattleCommand_RolloutPower
dw BattleCommand5d
dw BattleCommand_FuryCutter
dw BattleCommand_Attract
dw BattleCommand_HappinessPower
dw BattleCommand_Present
dw BattleCommand_DamageCalc
dw BattleCommand_FrustrationPower
dw BattleCommand_Safeguard
dw BattleCommand_CheckSafeguard
dw BattleCommand_GetMagnitude
dw BattleCommand_BatonPass
dw BattleCommand_Pursuit
dw BattleCommand_ClearHazards
dw BattleCommand_HealMorn
dw BattleCommand_HealDay
dw BattleCommand_HealNite
dw BattleCommand_HiddenPower
dw BattleCommand_StartRain
dw BattleCommand_StartSun
dw BattleCommand_AttackUp
dw BattleCommand_DefenseUp
dw BattleCommand_SpeedUp
dw BattleCommand_SpecialAttackUp
dw BattleCommand_SpecialDefenseUp
dw BattleCommand_AccuracyUp
dw BattleCommand_EvasionUp
dw BattleCommand_AttackUp2
dw BattleCommand_DefenseUp2
dw BattleCommand_SpeedUp2
dw BattleCommand_SpecialAttackUp2
dw BattleCommand_SpecialDefenseUp2
dw BattleCommand_AccuracyUp2
dw BattleCommand_EvasionUp2
dw BattleCommand_AttackDown
dw BattleCommand_DefenseDown
dw BattleCommand_SpeedDown
dw BattleCommand_SpecialAttackDown
dw BattleCommand_SpecialDefenseDown
dw BattleCommand_AccuracyDown
dw BattleCommand_EvasionDown
dw BattleCommand_AttackDown2
dw BattleCommand_DefenseDown2
dw BattleCommand_SpeedDown2
dw BattleCommand_SpecialAttackDown2
dw BattleCommand_SpecialDefenseDown2
dw BattleCommand_AccuracyDown2
dw BattleCommand_EvasionDown2
dw BattleCommand_StatUpMessage
dw BattleCommand_StatDownMessage
dw BattleCommand_StatUpFailText
dw BattleCommand_StatDownFailText
dw BattleCommand_EffectChance
dw BattleCommand_StatDownAnim
dw BattleCommand_StatUpAnim
dw BattleCommand_SwitchTurn
dw BattleCommand_FakeOut
dw BattleCommand_BellyDrum
dw BattleCommand_PsychUp
dw BattleCommand_Rage
dw BattleCommand_DoubleFlyingDamage
dw BattleCommand_DoubleUndergroundDamage
dw BattleCommand_MirrorCoat
dw BattleCommand_CheckFutureSight
dw BattleCommand_FutureSight
dw BattleCommand_DoubleMinimizeDamage
dw BattleCommand_SkipSunCharge
dw BattleCommand_ThunderAccuracy
dw BattleCommand_Teleport
dw BattleCommand_BeatUp
dw BattleCommand_RageDamage
dw BattleCommand_ResetTypeMatchup
dw BattleCommand_AllStatsUp
dw BattleCommand_BideFailText
dw BattleCommand_RaiseSubNoAnim
dw BattleCommand_LowerSubNoAnim
dw BattleCommand_BeatUpFailText
dw BattleCommand_ClearMissDamage
dw BattleCommand_MoveDelay
dw BattleCommand_MoveAnim
dw BattleCommand_TriStatusChance
dw BattleCommand_SuperEffectiveLoopText
dw BattleCommand_StartLoop
dw BattleCommand_Curl
|
; A021653: Decimal expansion of 1/649.
; Submitted by Christian Krause
; 0,0,1,5,4,0,8,3,2,0,4,9,3,0,6,6,2,5,5,7,7,8,1,2,0,1,8,4,8,9,9,8,4,5,9,1,6,7,9,5,0,6,9,3,3,7,4,4,2,2,1,8,7,9,8,1,5,1,0,0,1,5,4,0,8,3,2,0,4,9,3,0,6,6,2,5,5,7,7,8,1,2,0,1,8,4,8,9,9,8,4,5,9,1,6,7,9,5,0
seq $0,42 ; Unary representation of natural numbers.
div $0,11
mul $0,9
div $0,59
mod $0,10
|
_stressfs: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
#include "fs.h"
#include "fcntl.h"
int
main(int argc, char *argv[])
{
0: 8d 4c 24 04 lea 0x4(%esp),%ecx
4: 83 e4 f0 and $0xfffffff0,%esp
int fd, i;
char path[] = "stressfs0";
7: b8 30 00 00 00 mov $0x30,%eax
{
c: ff 71 fc pushl -0x4(%ecx)
f: 55 push %ebp
10: 89 e5 mov %esp,%ebp
12: 57 push %edi
13: 56 push %esi
14: 53 push %ebx
15: 51 push %ecx
char data[512];
printf(1, "stressfs starting\n");
memset(data, 'a', sizeof(data));
16: 8d b5 e8 fd ff ff lea -0x218(%ebp),%esi
for(i = 0; i < 4; i++)
1c: 31 db xor %ebx,%ebx
{
1e: 81 ec 20 02 00 00 sub $0x220,%esp
char path[] = "stressfs0";
24: 66 89 85 e6 fd ff ff mov %ax,-0x21a(%ebp)
2b: c7 85 de fd ff ff 73 movl $0x65727473,-0x222(%ebp)
32: 74 72 65
printf(1, "stressfs starting\n");
35: 68 38 08 00 00 push $0x838
3a: 6a 01 push $0x1
char path[] = "stressfs0";
3c: c7 85 e2 fd ff ff 73 movl $0x73667373,-0x21e(%ebp)
43: 73 66 73
printf(1, "stressfs starting\n");
46: e8 95 04 00 00 call 4e0 <printf>
memset(data, 'a', sizeof(data));
4b: 83 c4 0c add $0xc,%esp
4e: 68 00 02 00 00 push $0x200
53: 6a 61 push $0x61
55: 56 push %esi
56: e8 95 01 00 00 call 1f0 <memset>
5b: 83 c4 10 add $0x10,%esp
if(fork() > 0)
5e: e8 27 03 00 00 call 38a <fork>
63: 85 c0 test %eax,%eax
65: 0f 8f bf 00 00 00 jg 12a <main+0x12a>
for(i = 0; i < 4; i++)
6b: 83 c3 01 add $0x1,%ebx
6e: 83 fb 04 cmp $0x4,%ebx
71: 75 eb jne 5e <main+0x5e>
73: bf 04 00 00 00 mov $0x4,%edi
break;
printf(1, "write %d\n", i);
78: 83 ec 04 sub $0x4,%esp
7b: 53 push %ebx
7c: 68 4b 08 00 00 push $0x84b
path[8] += i;
fd = open(path, O_CREATE | O_RDWR);
81: bb 14 00 00 00 mov $0x14,%ebx
printf(1, "write %d\n", i);
86: 6a 01 push $0x1
88: e8 53 04 00 00 call 4e0 <printf>
path[8] += i;
8d: 89 f8 mov %edi,%eax
8f: 00 85 e6 fd ff ff add %al,-0x21a(%ebp)
fd = open(path, O_CREATE | O_RDWR);
95: 5f pop %edi
96: 58 pop %eax
97: 8d 85 de fd ff ff lea -0x222(%ebp),%eax
9d: 68 02 02 00 00 push $0x202
a2: 50 push %eax
a3: e8 2a 03 00 00 call 3d2 <open>
a8: 83 c4 10 add $0x10,%esp
ab: 89 c7 mov %eax,%edi
ad: 8d 76 00 lea 0x0(%esi),%esi
for(i = 0; i < 20; i++)
// printf(fd, "%d\n", i);
write(fd, data, sizeof(data));
b0: 83 ec 04 sub $0x4,%esp
b3: 68 00 02 00 00 push $0x200
b8: 56 push %esi
b9: 57 push %edi
ba: e8 f3 02 00 00 call 3b2 <write>
for(i = 0; i < 20; i++)
bf: 83 c4 10 add $0x10,%esp
c2: 83 eb 01 sub $0x1,%ebx
c5: 75 e9 jne b0 <main+0xb0>
close(fd);
c7: 83 ec 0c sub $0xc,%esp
ca: 57 push %edi
cb: e8 ea 02 00 00 call 3ba <close>
printf(1, "read\n");
d0: 58 pop %eax
d1: 5a pop %edx
d2: 68 55 08 00 00 push $0x855
d7: 6a 01 push $0x1
d9: e8 02 04 00 00 call 4e0 <printf>
fd = open(path, O_RDONLY);
de: 59 pop %ecx
df: 8d 85 de fd ff ff lea -0x222(%ebp),%eax
e5: 5b pop %ebx
e6: 6a 00 push $0x0
e8: 50 push %eax
e9: bb 14 00 00 00 mov $0x14,%ebx
ee: e8 df 02 00 00 call 3d2 <open>
f3: 83 c4 10 add $0x10,%esp
f6: 89 c7 mov %eax,%edi
f8: 90 nop
f9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
for (i = 0; i < 20; i++)
read(fd, data, sizeof(data));
100: 83 ec 04 sub $0x4,%esp
103: 68 00 02 00 00 push $0x200
108: 56 push %esi
109: 57 push %edi
10a: e8 9b 02 00 00 call 3aa <read>
for (i = 0; i < 20; i++)
10f: 83 c4 10 add $0x10,%esp
112: 83 eb 01 sub $0x1,%ebx
115: 75 e9 jne 100 <main+0x100>
close(fd);
117: 83 ec 0c sub $0xc,%esp
11a: 57 push %edi
11b: e8 9a 02 00 00 call 3ba <close>
wait();
120: e8 75 02 00 00 call 39a <wait>
exit();
125: e8 68 02 00 00 call 392 <exit>
12a: 89 df mov %ebx,%edi
12c: e9 47 ff ff ff jmp 78 <main+0x78>
131: 66 90 xchg %ax,%ax
133: 66 90 xchg %ax,%ax
135: 66 90 xchg %ax,%ax
137: 66 90 xchg %ax,%ax
139: 66 90 xchg %ax,%ax
13b: 66 90 xchg %ax,%ax
13d: 66 90 xchg %ax,%ax
13f: 90 nop
00000140 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, const char *t)
{
140: 55 push %ebp
141: 89 e5 mov %esp,%ebp
143: 53 push %ebx
144: 8b 45 08 mov 0x8(%ebp),%eax
147: 8b 4d 0c mov 0xc(%ebp),%ecx
char *os;
os = s;
while((*s++ = *t++) != 0)
14a: 89 c2 mov %eax,%edx
14c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
150: 83 c1 01 add $0x1,%ecx
153: 0f b6 59 ff movzbl -0x1(%ecx),%ebx
157: 83 c2 01 add $0x1,%edx
15a: 84 db test %bl,%bl
15c: 88 5a ff mov %bl,-0x1(%edx)
15f: 75 ef jne 150 <strcpy+0x10>
;
return os;
}
161: 5b pop %ebx
162: 5d pop %ebp
163: c3 ret
164: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
16a: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
00000170 <strcmp>:
int
strcmp(const char *p, const char *q)
{
170: 55 push %ebp
171: 89 e5 mov %esp,%ebp
173: 53 push %ebx
174: 8b 55 08 mov 0x8(%ebp),%edx
177: 8b 4d 0c mov 0xc(%ebp),%ecx
while(*p && *p == *q)
17a: 0f b6 02 movzbl (%edx),%eax
17d: 0f b6 19 movzbl (%ecx),%ebx
180: 84 c0 test %al,%al
182: 75 1c jne 1a0 <strcmp+0x30>
184: eb 2a jmp 1b0 <strcmp+0x40>
186: 8d 76 00 lea 0x0(%esi),%esi
189: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
p++, q++;
190: 83 c2 01 add $0x1,%edx
while(*p && *p == *q)
193: 0f b6 02 movzbl (%edx),%eax
p++, q++;
196: 83 c1 01 add $0x1,%ecx
199: 0f b6 19 movzbl (%ecx),%ebx
while(*p && *p == *q)
19c: 84 c0 test %al,%al
19e: 74 10 je 1b0 <strcmp+0x40>
1a0: 38 d8 cmp %bl,%al
1a2: 74 ec je 190 <strcmp+0x20>
return (uchar)*p - (uchar)*q;
1a4: 29 d8 sub %ebx,%eax
}
1a6: 5b pop %ebx
1a7: 5d pop %ebp
1a8: c3 ret
1a9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
1b0: 31 c0 xor %eax,%eax
return (uchar)*p - (uchar)*q;
1b2: 29 d8 sub %ebx,%eax
}
1b4: 5b pop %ebx
1b5: 5d pop %ebp
1b6: c3 ret
1b7: 89 f6 mov %esi,%esi
1b9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
000001c0 <strlen>:
uint
strlen(const char *s)
{
1c0: 55 push %ebp
1c1: 89 e5 mov %esp,%ebp
1c3: 8b 4d 08 mov 0x8(%ebp),%ecx
int n;
for(n = 0; s[n]; n++)
1c6: 80 39 00 cmpb $0x0,(%ecx)
1c9: 74 15 je 1e0 <strlen+0x20>
1cb: 31 d2 xor %edx,%edx
1cd: 8d 76 00 lea 0x0(%esi),%esi
1d0: 83 c2 01 add $0x1,%edx
1d3: 80 3c 11 00 cmpb $0x0,(%ecx,%edx,1)
1d7: 89 d0 mov %edx,%eax
1d9: 75 f5 jne 1d0 <strlen+0x10>
;
return n;
}
1db: 5d pop %ebp
1dc: c3 ret
1dd: 8d 76 00 lea 0x0(%esi),%esi
for(n = 0; s[n]; n++)
1e0: 31 c0 xor %eax,%eax
}
1e2: 5d pop %ebp
1e3: c3 ret
1e4: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
1ea: 8d bf 00 00 00 00 lea 0x0(%edi),%edi
000001f0 <memset>:
void*
memset(void *dst, int c, uint n)
{
1f0: 55 push %ebp
1f1: 89 e5 mov %esp,%ebp
1f3: 57 push %edi
1f4: 8b 55 08 mov 0x8(%ebp),%edx
}
static inline void
stosb(void *addr, int data, int cnt)
{
asm volatile("cld; rep stosb" :
1f7: 8b 4d 10 mov 0x10(%ebp),%ecx
1fa: 8b 45 0c mov 0xc(%ebp),%eax
1fd: 89 d7 mov %edx,%edi
1ff: fc cld
200: f3 aa rep stos %al,%es:(%edi)
stosb(dst, c, n);
return dst;
}
202: 89 d0 mov %edx,%eax
204: 5f pop %edi
205: 5d pop %ebp
206: c3 ret
207: 89 f6 mov %esi,%esi
209: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000210 <strchr>:
char*
strchr(const char *s, char c)
{
210: 55 push %ebp
211: 89 e5 mov %esp,%ebp
213: 53 push %ebx
214: 8b 45 08 mov 0x8(%ebp),%eax
217: 8b 5d 0c mov 0xc(%ebp),%ebx
for(; *s; s++)
21a: 0f b6 10 movzbl (%eax),%edx
21d: 84 d2 test %dl,%dl
21f: 74 1d je 23e <strchr+0x2e>
if(*s == c)
221: 38 d3 cmp %dl,%bl
223: 89 d9 mov %ebx,%ecx
225: 75 0d jne 234 <strchr+0x24>
227: eb 17 jmp 240 <strchr+0x30>
229: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
230: 38 ca cmp %cl,%dl
232: 74 0c je 240 <strchr+0x30>
for(; *s; s++)
234: 83 c0 01 add $0x1,%eax
237: 0f b6 10 movzbl (%eax),%edx
23a: 84 d2 test %dl,%dl
23c: 75 f2 jne 230 <strchr+0x20>
return (char*)s;
return 0;
23e: 31 c0 xor %eax,%eax
}
240: 5b pop %ebx
241: 5d pop %ebp
242: c3 ret
243: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
249: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000250 <gets>:
char*
gets(char *buf, int max)
{
250: 55 push %ebp
251: 89 e5 mov %esp,%ebp
253: 57 push %edi
254: 56 push %esi
255: 53 push %ebx
int i, cc;
char c;
for(i=0; i+1 < max; ){
256: 31 f6 xor %esi,%esi
258: 89 f3 mov %esi,%ebx
{
25a: 83 ec 1c sub $0x1c,%esp
25d: 8b 7d 08 mov 0x8(%ebp),%edi
for(i=0; i+1 < max; ){
260: eb 2f jmp 291 <gets+0x41>
262: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
cc = read(0, &c, 1);
268: 8d 45 e7 lea -0x19(%ebp),%eax
26b: 83 ec 04 sub $0x4,%esp
26e: 6a 01 push $0x1
270: 50 push %eax
271: 6a 00 push $0x0
273: e8 32 01 00 00 call 3aa <read>
if(cc < 1)
278: 83 c4 10 add $0x10,%esp
27b: 85 c0 test %eax,%eax
27d: 7e 1c jle 29b <gets+0x4b>
break;
buf[i++] = c;
27f: 0f b6 45 e7 movzbl -0x19(%ebp),%eax
283: 83 c7 01 add $0x1,%edi
286: 88 47 ff mov %al,-0x1(%edi)
if(c == '\n' || c == '\r')
289: 3c 0a cmp $0xa,%al
28b: 74 23 je 2b0 <gets+0x60>
28d: 3c 0d cmp $0xd,%al
28f: 74 1f je 2b0 <gets+0x60>
for(i=0; i+1 < max; ){
291: 83 c3 01 add $0x1,%ebx
294: 3b 5d 0c cmp 0xc(%ebp),%ebx
297: 89 fe mov %edi,%esi
299: 7c cd jl 268 <gets+0x18>
29b: 89 f3 mov %esi,%ebx
break;
}
buf[i] = '\0';
return buf;
}
29d: 8b 45 08 mov 0x8(%ebp),%eax
buf[i] = '\0';
2a0: c6 03 00 movb $0x0,(%ebx)
}
2a3: 8d 65 f4 lea -0xc(%ebp),%esp
2a6: 5b pop %ebx
2a7: 5e pop %esi
2a8: 5f pop %edi
2a9: 5d pop %ebp
2aa: c3 ret
2ab: 90 nop
2ac: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
2b0: 8b 75 08 mov 0x8(%ebp),%esi
2b3: 8b 45 08 mov 0x8(%ebp),%eax
2b6: 01 de add %ebx,%esi
2b8: 89 f3 mov %esi,%ebx
buf[i] = '\0';
2ba: c6 03 00 movb $0x0,(%ebx)
}
2bd: 8d 65 f4 lea -0xc(%ebp),%esp
2c0: 5b pop %ebx
2c1: 5e pop %esi
2c2: 5f pop %edi
2c3: 5d pop %ebp
2c4: c3 ret
2c5: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
2c9: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
000002d0 <stat>:
int
stat(const char *n, struct stat *st)
{
2d0: 55 push %ebp
2d1: 89 e5 mov %esp,%ebp
2d3: 56 push %esi
2d4: 53 push %ebx
int fd;
int r;
fd = open(n, O_RDONLY);
2d5: 83 ec 08 sub $0x8,%esp
2d8: 6a 00 push $0x0
2da: ff 75 08 pushl 0x8(%ebp)
2dd: e8 f0 00 00 00 call 3d2 <open>
if(fd < 0)
2e2: 83 c4 10 add $0x10,%esp
2e5: 85 c0 test %eax,%eax
2e7: 78 27 js 310 <stat+0x40>
return -1;
r = fstat(fd, st);
2e9: 83 ec 08 sub $0x8,%esp
2ec: ff 75 0c pushl 0xc(%ebp)
2ef: 89 c3 mov %eax,%ebx
2f1: 50 push %eax
2f2: e8 f3 00 00 00 call 3ea <fstat>
close(fd);
2f7: 89 1c 24 mov %ebx,(%esp)
r = fstat(fd, st);
2fa: 89 c6 mov %eax,%esi
close(fd);
2fc: e8 b9 00 00 00 call 3ba <close>
return r;
301: 83 c4 10 add $0x10,%esp
}
304: 8d 65 f8 lea -0x8(%ebp),%esp
307: 89 f0 mov %esi,%eax
309: 5b pop %ebx
30a: 5e pop %esi
30b: 5d pop %ebp
30c: c3 ret
30d: 8d 76 00 lea 0x0(%esi),%esi
return -1;
310: be ff ff ff ff mov $0xffffffff,%esi
315: eb ed jmp 304 <stat+0x34>
317: 89 f6 mov %esi,%esi
319: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
00000320 <atoi>:
int
atoi(const char *s)
{
320: 55 push %ebp
321: 89 e5 mov %esp,%ebp
323: 53 push %ebx
324: 8b 4d 08 mov 0x8(%ebp),%ecx
int n;
n = 0;
while('0' <= *s && *s <= '9')
327: 0f be 11 movsbl (%ecx),%edx
32a: 8d 42 d0 lea -0x30(%edx),%eax
32d: 3c 09 cmp $0x9,%al
n = 0;
32f: b8 00 00 00 00 mov $0x0,%eax
while('0' <= *s && *s <= '9')
334: 77 1f ja 355 <atoi+0x35>
336: 8d 76 00 lea 0x0(%esi),%esi
339: 8d bc 27 00 00 00 00 lea 0x0(%edi,%eiz,1),%edi
n = n*10 + *s++ - '0';
340: 8d 04 80 lea (%eax,%eax,4),%eax
343: 83 c1 01 add $0x1,%ecx
346: 8d 44 42 d0 lea -0x30(%edx,%eax,2),%eax
while('0' <= *s && *s <= '9')
34a: 0f be 11 movsbl (%ecx),%edx
34d: 8d 5a d0 lea -0x30(%edx),%ebx
350: 80 fb 09 cmp $0x9,%bl
353: 76 eb jbe 340 <atoi+0x20>
return n;
}
355: 5b pop %ebx
356: 5d pop %ebp
357: c3 ret
358: 90 nop
359: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
00000360 <memmove>:
void*
memmove(void *vdst, const void *vsrc, int n)
{
360: 55 push %ebp
361: 89 e5 mov %esp,%ebp
363: 56 push %esi
364: 53 push %ebx
365: 8b 5d 10 mov 0x10(%ebp),%ebx
368: 8b 45 08 mov 0x8(%ebp),%eax
36b: 8b 75 0c mov 0xc(%ebp),%esi
char *dst;
const char *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
36e: 85 db test %ebx,%ebx
370: 7e 14 jle 386 <memmove+0x26>
372: 31 d2 xor %edx,%edx
374: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
*dst++ = *src++;
378: 0f b6 0c 16 movzbl (%esi,%edx,1),%ecx
37c: 88 0c 10 mov %cl,(%eax,%edx,1)
37f: 83 c2 01 add $0x1,%edx
while(n-- > 0)
382: 39 d3 cmp %edx,%ebx
384: 75 f2 jne 378 <memmove+0x18>
return vdst;
}
386: 5b pop %ebx
387: 5e pop %esi
388: 5d pop %ebp
389: c3 ret
0000038a <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
38a: b8 01 00 00 00 mov $0x1,%eax
38f: cd 40 int $0x40
391: c3 ret
00000392 <exit>:
SYSCALL(exit)
392: b8 02 00 00 00 mov $0x2,%eax
397: cd 40 int $0x40
399: c3 ret
0000039a <wait>:
SYSCALL(wait)
39a: b8 03 00 00 00 mov $0x3,%eax
39f: cd 40 int $0x40
3a1: c3 ret
000003a2 <pipe>:
SYSCALL(pipe)
3a2: b8 04 00 00 00 mov $0x4,%eax
3a7: cd 40 int $0x40
3a9: c3 ret
000003aa <read>:
SYSCALL(read)
3aa: b8 05 00 00 00 mov $0x5,%eax
3af: cd 40 int $0x40
3b1: c3 ret
000003b2 <write>:
SYSCALL(write)
3b2: b8 10 00 00 00 mov $0x10,%eax
3b7: cd 40 int $0x40
3b9: c3 ret
000003ba <close>:
SYSCALL(close)
3ba: b8 15 00 00 00 mov $0x15,%eax
3bf: cd 40 int $0x40
3c1: c3 ret
000003c2 <kill>:
SYSCALL(kill)
3c2: b8 06 00 00 00 mov $0x6,%eax
3c7: cd 40 int $0x40
3c9: c3 ret
000003ca <exec>:
SYSCALL(exec)
3ca: b8 07 00 00 00 mov $0x7,%eax
3cf: cd 40 int $0x40
3d1: c3 ret
000003d2 <open>:
SYSCALL(open)
3d2: b8 0f 00 00 00 mov $0xf,%eax
3d7: cd 40 int $0x40
3d9: c3 ret
000003da <mknod>:
SYSCALL(mknod)
3da: b8 11 00 00 00 mov $0x11,%eax
3df: cd 40 int $0x40
3e1: c3 ret
000003e2 <unlink>:
SYSCALL(unlink)
3e2: b8 12 00 00 00 mov $0x12,%eax
3e7: cd 40 int $0x40
3e9: c3 ret
000003ea <fstat>:
SYSCALL(fstat)
3ea: b8 08 00 00 00 mov $0x8,%eax
3ef: cd 40 int $0x40
3f1: c3 ret
000003f2 <link>:
SYSCALL(link)
3f2: b8 13 00 00 00 mov $0x13,%eax
3f7: cd 40 int $0x40
3f9: c3 ret
000003fa <mkdir>:
SYSCALL(mkdir)
3fa: b8 14 00 00 00 mov $0x14,%eax
3ff: cd 40 int $0x40
401: c3 ret
00000402 <chdir>:
SYSCALL(chdir)
402: b8 09 00 00 00 mov $0x9,%eax
407: cd 40 int $0x40
409: c3 ret
0000040a <dup>:
SYSCALL(dup)
40a: b8 0a 00 00 00 mov $0xa,%eax
40f: cd 40 int $0x40
411: c3 ret
00000412 <getpid>:
SYSCALL(getpid)
412: b8 0b 00 00 00 mov $0xb,%eax
417: cd 40 int $0x40
419: c3 ret
0000041a <sbrk>:
SYSCALL(sbrk)
41a: b8 0c 00 00 00 mov $0xc,%eax
41f: cd 40 int $0x40
421: c3 ret
00000422 <sleep>:
SYSCALL(sleep)
422: b8 0d 00 00 00 mov $0xd,%eax
427: cd 40 int $0x40
429: c3 ret
0000042a <uptime>:
SYSCALL(uptime)
42a: b8 0e 00 00 00 mov $0xe,%eax
42f: cd 40 int $0x40
431: c3 ret
00000432 <getreadcount>:
SYSCALL(getreadcount)
432: b8 16 00 00 00 mov $0x16,%eax
437: cd 40 int $0x40
439: c3 ret
43a: 66 90 xchg %ax,%ax
43c: 66 90 xchg %ax,%ax
43e: 66 90 xchg %ax,%ax
00000440 <printint>:
write(fd, &c, 1);
}
static void
printint(int fd, int xx, int base, int sgn)
{
440: 55 push %ebp
441: 89 e5 mov %esp,%ebp
443: 57 push %edi
444: 56 push %esi
445: 53 push %ebx
446: 83 ec 3c sub $0x3c,%esp
char buf[16];
int i, neg;
uint x;
neg = 0;
if(sgn && xx < 0){
449: 85 d2 test %edx,%edx
{
44b: 89 45 c0 mov %eax,-0x40(%ebp)
neg = 1;
x = -xx;
44e: 89 d0 mov %edx,%eax
if(sgn && xx < 0){
450: 79 76 jns 4c8 <printint+0x88>
452: f6 45 08 01 testb $0x1,0x8(%ebp)
456: 74 70 je 4c8 <printint+0x88>
x = -xx;
458: f7 d8 neg %eax
neg = 1;
45a: c7 45 c4 01 00 00 00 movl $0x1,-0x3c(%ebp)
} else {
x = xx;
}
i = 0;
461: 31 f6 xor %esi,%esi
463: 8d 5d d7 lea -0x29(%ebp),%ebx
466: eb 0a jmp 472 <printint+0x32>
468: 90 nop
469: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
do{
buf[i++] = digits[x % base];
470: 89 fe mov %edi,%esi
472: 31 d2 xor %edx,%edx
474: 8d 7e 01 lea 0x1(%esi),%edi
477: f7 f1 div %ecx
479: 0f b6 92 64 08 00 00 movzbl 0x864(%edx),%edx
}while((x /= base) != 0);
480: 85 c0 test %eax,%eax
buf[i++] = digits[x % base];
482: 88 14 3b mov %dl,(%ebx,%edi,1)
}while((x /= base) != 0);
485: 75 e9 jne 470 <printint+0x30>
if(neg)
487: 8b 45 c4 mov -0x3c(%ebp),%eax
48a: 85 c0 test %eax,%eax
48c: 74 08 je 496 <printint+0x56>
buf[i++] = '-';
48e: c6 44 3d d8 2d movb $0x2d,-0x28(%ebp,%edi,1)
493: 8d 7e 02 lea 0x2(%esi),%edi
496: 8d 74 3d d7 lea -0x29(%ebp,%edi,1),%esi
49a: 8b 7d c0 mov -0x40(%ebp),%edi
49d: 8d 76 00 lea 0x0(%esi),%esi
4a0: 0f b6 06 movzbl (%esi),%eax
write(fd, &c, 1);
4a3: 83 ec 04 sub $0x4,%esp
4a6: 83 ee 01 sub $0x1,%esi
4a9: 6a 01 push $0x1
4ab: 53 push %ebx
4ac: 57 push %edi
4ad: 88 45 d7 mov %al,-0x29(%ebp)
4b0: e8 fd fe ff ff call 3b2 <write>
while(--i >= 0)
4b5: 83 c4 10 add $0x10,%esp
4b8: 39 de cmp %ebx,%esi
4ba: 75 e4 jne 4a0 <printint+0x60>
putc(fd, buf[i]);
}
4bc: 8d 65 f4 lea -0xc(%ebp),%esp
4bf: 5b pop %ebx
4c0: 5e pop %esi
4c1: 5f pop %edi
4c2: 5d pop %ebp
4c3: c3 ret
4c4: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
neg = 0;
4c8: c7 45 c4 00 00 00 00 movl $0x0,-0x3c(%ebp)
4cf: eb 90 jmp 461 <printint+0x21>
4d1: eb 0d jmp 4e0 <printf>
4d3: 90 nop
4d4: 90 nop
4d5: 90 nop
4d6: 90 nop
4d7: 90 nop
4d8: 90 nop
4d9: 90 nop
4da: 90 nop
4db: 90 nop
4dc: 90 nop
4dd: 90 nop
4de: 90 nop
4df: 90 nop
000004e0 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, const char *fmt, ...)
{
4e0: 55 push %ebp
4e1: 89 e5 mov %esp,%ebp
4e3: 57 push %edi
4e4: 56 push %esi
4e5: 53 push %ebx
4e6: 83 ec 2c sub $0x2c,%esp
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
4e9: 8b 75 0c mov 0xc(%ebp),%esi
4ec: 0f b6 1e movzbl (%esi),%ebx
4ef: 84 db test %bl,%bl
4f1: 0f 84 b3 00 00 00 je 5aa <printf+0xca>
ap = (uint*)(void*)&fmt + 1;
4f7: 8d 45 10 lea 0x10(%ebp),%eax
4fa: 83 c6 01 add $0x1,%esi
state = 0;
4fd: 31 ff xor %edi,%edi
ap = (uint*)(void*)&fmt + 1;
4ff: 89 45 d4 mov %eax,-0x2c(%ebp)
502: eb 2f jmp 533 <printf+0x53>
504: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
c = fmt[i] & 0xff;
if(state == 0){
if(c == '%'){
508: 83 f8 25 cmp $0x25,%eax
50b: 0f 84 a7 00 00 00 je 5b8 <printf+0xd8>
write(fd, &c, 1);
511: 8d 45 e2 lea -0x1e(%ebp),%eax
514: 83 ec 04 sub $0x4,%esp
517: 88 5d e2 mov %bl,-0x1e(%ebp)
51a: 6a 01 push $0x1
51c: 50 push %eax
51d: ff 75 08 pushl 0x8(%ebp)
520: e8 8d fe ff ff call 3b2 <write>
525: 83 c4 10 add $0x10,%esp
528: 83 c6 01 add $0x1,%esi
for(i = 0; fmt[i]; i++){
52b: 0f b6 5e ff movzbl -0x1(%esi),%ebx
52f: 84 db test %bl,%bl
531: 74 77 je 5aa <printf+0xca>
if(state == 0){
533: 85 ff test %edi,%edi
c = fmt[i] & 0xff;
535: 0f be cb movsbl %bl,%ecx
538: 0f b6 c3 movzbl %bl,%eax
if(state == 0){
53b: 74 cb je 508 <printf+0x28>
state = '%';
} else {
putc(fd, c);
}
} else if(state == '%'){
53d: 83 ff 25 cmp $0x25,%edi
540: 75 e6 jne 528 <printf+0x48>
if(c == 'd'){
542: 83 f8 64 cmp $0x64,%eax
545: 0f 84 05 01 00 00 je 650 <printf+0x170>
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
54b: 81 e1 f7 00 00 00 and $0xf7,%ecx
551: 83 f9 70 cmp $0x70,%ecx
554: 74 72 je 5c8 <printf+0xe8>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
556: 83 f8 73 cmp $0x73,%eax
559: 0f 84 99 00 00 00 je 5f8 <printf+0x118>
s = "(null)";
while(*s != 0){
putc(fd, *s);
s++;
}
} else if(c == 'c'){
55f: 83 f8 63 cmp $0x63,%eax
562: 0f 84 08 01 00 00 je 670 <printf+0x190>
putc(fd, *ap);
ap++;
} else if(c == '%'){
568: 83 f8 25 cmp $0x25,%eax
56b: 0f 84 ef 00 00 00 je 660 <printf+0x180>
write(fd, &c, 1);
571: 8d 45 e7 lea -0x19(%ebp),%eax
574: 83 ec 04 sub $0x4,%esp
577: c6 45 e7 25 movb $0x25,-0x19(%ebp)
57b: 6a 01 push $0x1
57d: 50 push %eax
57e: ff 75 08 pushl 0x8(%ebp)
581: e8 2c fe ff ff call 3b2 <write>
586: 83 c4 0c add $0xc,%esp
589: 8d 45 e6 lea -0x1a(%ebp),%eax
58c: 88 5d e6 mov %bl,-0x1a(%ebp)
58f: 6a 01 push $0x1
591: 50 push %eax
592: ff 75 08 pushl 0x8(%ebp)
595: 83 c6 01 add $0x1,%esi
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
putc(fd, c);
}
state = 0;
598: 31 ff xor %edi,%edi
write(fd, &c, 1);
59a: e8 13 fe ff ff call 3b2 <write>
for(i = 0; fmt[i]; i++){
59f: 0f b6 5e ff movzbl -0x1(%esi),%ebx
write(fd, &c, 1);
5a3: 83 c4 10 add $0x10,%esp
for(i = 0; fmt[i]; i++){
5a6: 84 db test %bl,%bl
5a8: 75 89 jne 533 <printf+0x53>
}
}
}
5aa: 8d 65 f4 lea -0xc(%ebp),%esp
5ad: 5b pop %ebx
5ae: 5e pop %esi
5af: 5f pop %edi
5b0: 5d pop %ebp
5b1: c3 ret
5b2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
state = '%';
5b8: bf 25 00 00 00 mov $0x25,%edi
5bd: e9 66 ff ff ff jmp 528 <printf+0x48>
5c2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
printint(fd, *ap, 16, 0);
5c8: 83 ec 0c sub $0xc,%esp
5cb: b9 10 00 00 00 mov $0x10,%ecx
5d0: 6a 00 push $0x0
5d2: 8b 7d d4 mov -0x2c(%ebp),%edi
5d5: 8b 45 08 mov 0x8(%ebp),%eax
5d8: 8b 17 mov (%edi),%edx
5da: e8 61 fe ff ff call 440 <printint>
ap++;
5df: 89 f8 mov %edi,%eax
5e1: 83 c4 10 add $0x10,%esp
state = 0;
5e4: 31 ff xor %edi,%edi
ap++;
5e6: 83 c0 04 add $0x4,%eax
5e9: 89 45 d4 mov %eax,-0x2c(%ebp)
5ec: e9 37 ff ff ff jmp 528 <printf+0x48>
5f1: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
s = (char*)*ap;
5f8: 8b 45 d4 mov -0x2c(%ebp),%eax
5fb: 8b 08 mov (%eax),%ecx
ap++;
5fd: 83 c0 04 add $0x4,%eax
600: 89 45 d4 mov %eax,-0x2c(%ebp)
if(s == 0)
603: 85 c9 test %ecx,%ecx
605: 0f 84 8e 00 00 00 je 699 <printf+0x1b9>
while(*s != 0){
60b: 0f b6 01 movzbl (%ecx),%eax
state = 0;
60e: 31 ff xor %edi,%edi
s = (char*)*ap;
610: 89 cb mov %ecx,%ebx
while(*s != 0){
612: 84 c0 test %al,%al
614: 0f 84 0e ff ff ff je 528 <printf+0x48>
61a: 89 75 d0 mov %esi,-0x30(%ebp)
61d: 89 de mov %ebx,%esi
61f: 8b 5d 08 mov 0x8(%ebp),%ebx
622: 8d 7d e3 lea -0x1d(%ebp),%edi
625: 8d 76 00 lea 0x0(%esi),%esi
write(fd, &c, 1);
628: 83 ec 04 sub $0x4,%esp
s++;
62b: 83 c6 01 add $0x1,%esi
62e: 88 45 e3 mov %al,-0x1d(%ebp)
write(fd, &c, 1);
631: 6a 01 push $0x1
633: 57 push %edi
634: 53 push %ebx
635: e8 78 fd ff ff call 3b2 <write>
while(*s != 0){
63a: 0f b6 06 movzbl (%esi),%eax
63d: 83 c4 10 add $0x10,%esp
640: 84 c0 test %al,%al
642: 75 e4 jne 628 <printf+0x148>
644: 8b 75 d0 mov -0x30(%ebp),%esi
state = 0;
647: 31 ff xor %edi,%edi
649: e9 da fe ff ff jmp 528 <printf+0x48>
64e: 66 90 xchg %ax,%ax
printint(fd, *ap, 10, 1);
650: 83 ec 0c sub $0xc,%esp
653: b9 0a 00 00 00 mov $0xa,%ecx
658: 6a 01 push $0x1
65a: e9 73 ff ff ff jmp 5d2 <printf+0xf2>
65f: 90 nop
write(fd, &c, 1);
660: 83 ec 04 sub $0x4,%esp
663: 88 5d e5 mov %bl,-0x1b(%ebp)
666: 8d 45 e5 lea -0x1b(%ebp),%eax
669: 6a 01 push $0x1
66b: e9 21 ff ff ff jmp 591 <printf+0xb1>
putc(fd, *ap);
670: 8b 7d d4 mov -0x2c(%ebp),%edi
write(fd, &c, 1);
673: 83 ec 04 sub $0x4,%esp
putc(fd, *ap);
676: 8b 07 mov (%edi),%eax
write(fd, &c, 1);
678: 6a 01 push $0x1
ap++;
67a: 83 c7 04 add $0x4,%edi
putc(fd, *ap);
67d: 88 45 e4 mov %al,-0x1c(%ebp)
write(fd, &c, 1);
680: 8d 45 e4 lea -0x1c(%ebp),%eax
683: 50 push %eax
684: ff 75 08 pushl 0x8(%ebp)
687: e8 26 fd ff ff call 3b2 <write>
ap++;
68c: 89 7d d4 mov %edi,-0x2c(%ebp)
68f: 83 c4 10 add $0x10,%esp
state = 0;
692: 31 ff xor %edi,%edi
694: e9 8f fe ff ff jmp 528 <printf+0x48>
s = "(null)";
699: bb 5b 08 00 00 mov $0x85b,%ebx
while(*s != 0){
69e: b8 28 00 00 00 mov $0x28,%eax
6a3: e9 72 ff ff ff jmp 61a <printf+0x13a>
6a8: 66 90 xchg %ax,%ax
6aa: 66 90 xchg %ax,%ax
6ac: 66 90 xchg %ax,%ax
6ae: 66 90 xchg %ax,%ax
000006b0 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
6b0: 55 push %ebp
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
6b1: a1 14 0b 00 00 mov 0xb14,%eax
{
6b6: 89 e5 mov %esp,%ebp
6b8: 57 push %edi
6b9: 56 push %esi
6ba: 53 push %ebx
6bb: 8b 5d 08 mov 0x8(%ebp),%ebx
bp = (Header*)ap - 1;
6be: 8d 4b f8 lea -0x8(%ebx),%ecx
6c1: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
6c8: 39 c8 cmp %ecx,%eax
6ca: 8b 10 mov (%eax),%edx
6cc: 73 32 jae 700 <free+0x50>
6ce: 39 d1 cmp %edx,%ecx
6d0: 72 04 jb 6d6 <free+0x26>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
6d2: 39 d0 cmp %edx,%eax
6d4: 72 32 jb 708 <free+0x58>
break;
if(bp + bp->s.size == p->s.ptr){
6d6: 8b 73 fc mov -0x4(%ebx),%esi
6d9: 8d 3c f1 lea (%ecx,%esi,8),%edi
6dc: 39 fa cmp %edi,%edx
6de: 74 30 je 710 <free+0x60>
bp->s.size += p->s.ptr->s.size;
bp->s.ptr = p->s.ptr->s.ptr;
} else
bp->s.ptr = p->s.ptr;
6e0: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
6e3: 8b 50 04 mov 0x4(%eax),%edx
6e6: 8d 34 d0 lea (%eax,%edx,8),%esi
6e9: 39 f1 cmp %esi,%ecx
6eb: 74 3a je 727 <free+0x77>
p->s.size += bp->s.size;
p->s.ptr = bp->s.ptr;
} else
p->s.ptr = bp;
6ed: 89 08 mov %ecx,(%eax)
freep = p;
6ef: a3 14 0b 00 00 mov %eax,0xb14
}
6f4: 5b pop %ebx
6f5: 5e pop %esi
6f6: 5f pop %edi
6f7: 5d pop %ebp
6f8: c3 ret
6f9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
700: 39 d0 cmp %edx,%eax
702: 72 04 jb 708 <free+0x58>
704: 39 d1 cmp %edx,%ecx
706: 72 ce jb 6d6 <free+0x26>
{
708: 89 d0 mov %edx,%eax
70a: eb bc jmp 6c8 <free+0x18>
70c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
bp->s.size += p->s.ptr->s.size;
710: 03 72 04 add 0x4(%edx),%esi
713: 89 73 fc mov %esi,-0x4(%ebx)
bp->s.ptr = p->s.ptr->s.ptr;
716: 8b 10 mov (%eax),%edx
718: 8b 12 mov (%edx),%edx
71a: 89 53 f8 mov %edx,-0x8(%ebx)
if(p + p->s.size == bp){
71d: 8b 50 04 mov 0x4(%eax),%edx
720: 8d 34 d0 lea (%eax,%edx,8),%esi
723: 39 f1 cmp %esi,%ecx
725: 75 c6 jne 6ed <free+0x3d>
p->s.size += bp->s.size;
727: 03 53 fc add -0x4(%ebx),%edx
freep = p;
72a: a3 14 0b 00 00 mov %eax,0xb14
p->s.size += bp->s.size;
72f: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
732: 8b 53 f8 mov -0x8(%ebx),%edx
735: 89 10 mov %edx,(%eax)
}
737: 5b pop %ebx
738: 5e pop %esi
739: 5f pop %edi
73a: 5d pop %ebp
73b: c3 ret
73c: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
00000740 <malloc>:
return freep;
}
void*
malloc(uint nbytes)
{
740: 55 push %ebp
741: 89 e5 mov %esp,%ebp
743: 57 push %edi
744: 56 push %esi
745: 53 push %ebx
746: 83 ec 0c sub $0xc,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
749: 8b 45 08 mov 0x8(%ebp),%eax
if((prevp = freep) == 0){
74c: 8b 15 14 0b 00 00 mov 0xb14,%edx
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
752: 8d 78 07 lea 0x7(%eax),%edi
755: c1 ef 03 shr $0x3,%edi
758: 83 c7 01 add $0x1,%edi
if((prevp = freep) == 0){
75b: 85 d2 test %edx,%edx
75d: 0f 84 9d 00 00 00 je 800 <malloc+0xc0>
763: 8b 02 mov (%edx),%eax
765: 8b 48 04 mov 0x4(%eax),%ecx
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
if(p->s.size >= nunits){
768: 39 cf cmp %ecx,%edi
76a: 76 6c jbe 7d8 <malloc+0x98>
76c: 81 ff 00 10 00 00 cmp $0x1000,%edi
772: bb 00 10 00 00 mov $0x1000,%ebx
777: 0f 43 df cmovae %edi,%ebx
p = sbrk(nu * sizeof(Header));
77a: 8d 34 dd 00 00 00 00 lea 0x0(,%ebx,8),%esi
781: eb 0e jmp 791 <malloc+0x51>
783: 90 nop
784: 8d 74 26 00 lea 0x0(%esi,%eiz,1),%esi
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
788: 8b 02 mov (%edx),%eax
if(p->s.size >= nunits){
78a: 8b 48 04 mov 0x4(%eax),%ecx
78d: 39 f9 cmp %edi,%ecx
78f: 73 47 jae 7d8 <malloc+0x98>
p->s.size = nunits;
}
freep = prevp;
return (void*)(p + 1);
}
if(p == freep)
791: 39 05 14 0b 00 00 cmp %eax,0xb14
797: 89 c2 mov %eax,%edx
799: 75 ed jne 788 <malloc+0x48>
p = sbrk(nu * sizeof(Header));
79b: 83 ec 0c sub $0xc,%esp
79e: 56 push %esi
79f: e8 76 fc ff ff call 41a <sbrk>
if(p == (char*)-1)
7a4: 83 c4 10 add $0x10,%esp
7a7: 83 f8 ff cmp $0xffffffff,%eax
7aa: 74 1c je 7c8 <malloc+0x88>
hp->s.size = nu;
7ac: 89 58 04 mov %ebx,0x4(%eax)
free((void*)(hp + 1));
7af: 83 ec 0c sub $0xc,%esp
7b2: 83 c0 08 add $0x8,%eax
7b5: 50 push %eax
7b6: e8 f5 fe ff ff call 6b0 <free>
return freep;
7bb: 8b 15 14 0b 00 00 mov 0xb14,%edx
if((p = morecore(nunits)) == 0)
7c1: 83 c4 10 add $0x10,%esp
7c4: 85 d2 test %edx,%edx
7c6: 75 c0 jne 788 <malloc+0x48>
return 0;
}
}
7c8: 8d 65 f4 lea -0xc(%ebp),%esp
return 0;
7cb: 31 c0 xor %eax,%eax
}
7cd: 5b pop %ebx
7ce: 5e pop %esi
7cf: 5f pop %edi
7d0: 5d pop %ebp
7d1: c3 ret
7d2: 8d b6 00 00 00 00 lea 0x0(%esi),%esi
if(p->s.size == nunits)
7d8: 39 cf cmp %ecx,%edi
7da: 74 54 je 830 <malloc+0xf0>
p->s.size -= nunits;
7dc: 29 f9 sub %edi,%ecx
7de: 89 48 04 mov %ecx,0x4(%eax)
p += p->s.size;
7e1: 8d 04 c8 lea (%eax,%ecx,8),%eax
p->s.size = nunits;
7e4: 89 78 04 mov %edi,0x4(%eax)
freep = prevp;
7e7: 89 15 14 0b 00 00 mov %edx,0xb14
}
7ed: 8d 65 f4 lea -0xc(%ebp),%esp
return (void*)(p + 1);
7f0: 83 c0 08 add $0x8,%eax
}
7f3: 5b pop %ebx
7f4: 5e pop %esi
7f5: 5f pop %edi
7f6: 5d pop %ebp
7f7: c3 ret
7f8: 90 nop
7f9: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
base.s.ptr = freep = prevp = &base;
800: c7 05 14 0b 00 00 18 movl $0xb18,0xb14
807: 0b 00 00
80a: c7 05 18 0b 00 00 18 movl $0xb18,0xb18
811: 0b 00 00
base.s.size = 0;
814: b8 18 0b 00 00 mov $0xb18,%eax
819: c7 05 1c 0b 00 00 00 movl $0x0,0xb1c
820: 00 00 00
823: e9 44 ff ff ff jmp 76c <malloc+0x2c>
828: 90 nop
829: 8d b4 26 00 00 00 00 lea 0x0(%esi,%eiz,1),%esi
prevp->s.ptr = p->s.ptr;
830: 8b 08 mov (%eax),%ecx
832: 89 0a mov %ecx,(%edx)
834: eb b1 jmp 7e7 <malloc+0xa7>
|
; A135405: Sequence where the sum of each pair of consecutive elements is a square.
; 0,1,8,8,17,19,30,34,47,53,68,76,93,103,122,134,155,169,192,208,233,251,278,298,327,349,380,404,437,463,498,526,563,593,632,664,705,739,782,818,863,901,948,988,1037,1079,1130,1174,1227,1273,1328,1376,1433,1483,1542,1594,1655,1709,1772,1828,1893,1951,2018,2078,2147,2209,2280,2344,2417,2483,2558,2626,2703,2773,2852,2924,3005,3079,3162,3238,3323,3401,3488,3568,3657,3739,3830,3914,4007,4093,4188,4276,4373,4463,4562,4654,4755,4849,4952,5048,5153,5251,5358,5458,5567,5669,5780,5884,5997,6103,6218,6326,6443,6553,6672,6784,6905,7019,7142,7258,7383,7501,7628,7748,7877,7999,8130,8254,8387,8513,8648,8776,8913,9043,9182,9314,9455,9589,9732,9868,10013,10151,10298,10438,10587,10729,10880,11024,11177,11323,11478,11626,11783,11933,12092,12244,12405,12559,12722,12878,13043,13201,13368,13528,13697,13859,14030,14194,14367,14533,14708,14876,15053,15223,15402,15574,15755,15929,16112,16288,16473,16651,16838,17018,17207,17389,17580,17764,17957,18143,18338,18526,18723,18913,19112,19304,19505,19699,19902,20098,20303,20501,20708,20908,21117,21319,21530,21734,21947,22153,22368,22576,22793,23003,23222,23434,23655,23869,24092,24308,24533,24751,24978,25198,25427,25649,25880,26104,26337,26563,26798,27026,27263,27493,27732,27964,28205,28439,28682,28918,29163,29401,29648,29888,30137,30379,30630,30874,31127,31373
mov $2,$0
mov $4,3
lpb $2
mov $1,1
add $1,$2
mov $3,$4
add $3,$2
add $3,$1
mov $4,$0
mov $0,$3
mov $1,$4
sub $2,1
lpe
|
#ifndef Plate_H
#include "Plate.h"
#endif
Plate::Plate(int pin,int maxPWM){
_numPin=pin;
pinMode(_numPin,OUTPUT);
_maxPWM = maxPWM;
analogWrite(_numPin,0);
}
void Plate::set(int pwm){
if(pwm>=_maxPWM)
analogWrite(_numPin,_maxPWM);
else if (pwm<0)
analogWrite(_numPin,0);
else
analogWrite(_numPin,pwm);
}
|
/*=============================================================================
Library: CppMicroServices
Copyright (c) The CppMicroServices developers. See the COPYRIGHT
file at the top-level directory of this distribution and at
https://github.com/CppMicroServices/CppMicroServices/COPYRIGHT .
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
=============================================================================*/
#include "gtest/gtest.h"
#include "cppmicroservices/Constants.h"
#include "cppmicroservices/ServiceEvent.h"
#include "TestFixture.hpp"
#include "TestUtils.hpp"
#include "IDictionaryService/IDictionaryService.hpp"
#include "ISpellCheckService/ISpellCheckService.hpp"
namespace test
{
/**
* Verify Spellcheck service works as expected with a Dictionary service from a
* DS bundle and a non-DS bundle
*/
TEST_F(tServiceComponent, DISABLED_testDictionaryExample) //DS_TOI_50
{
auto ctxt = framework.GetBundleContext();
// try DS spellchecker with DS dictionary
EXPECT_TRUE(ctxt.GetServiceReferences<test::IDictionaryService>().empty());
auto frenchDictDSBundle = StartTestBundle("DSFrenchDictionary");
EXPECT_EQ(ctxt.GetServiceReferences<test::IDictionaryService>().size(), 1ul);
EXPECT_TRUE(ctxt.GetServiceReferences<test::ISpellCheckService>().empty());
auto spellcheckerBundle = StartTestBundle("DSSpellChecker");
EXPECT_FALSE(ctxt.GetServiceReferences<test::ISpellCheckService>().empty());
auto spellCheckRef = ctxt.GetServiceReference<test::ISpellCheckService>();
auto service = ctxt.GetService<test::ISpellCheckService>(spellCheckRef);
ASSERT_NE(service, nullptr);
auto spellCheckServiceId = GetServiceId(spellCheckRef);
EXPECT_TRUE(service->Check("bienvenue au tutoriel micro services").empty());
EXPECT_FALSE(service->Check("bienvenue au tutoriel microservices").empty());
EXPECT_TRUE(service->Check("bienvenue au").empty()); // verify partial string
// register service listener and wait for SERVICE_UNREGISTERING event for SpellCheck service
std::mutex mtx;
std::condition_variable cv;
auto token = ctxt.AddServiceListener([&](const cppmicroservices::ServiceEvent& evt) {
if((evt.GetType() == cppmicroservices::ServiceEvent::SERVICE_UNREGISTERING) &&
(spellCheckServiceId == GetServiceId(evt.GetServiceReference())))
{
std::unique_lock<std::mutex> lk(mtx);
cv.notify_all();
}
});
frenchDictDSBundle.Stop(); // remove the dependency for spellchecker
{
std::unique_lock<std::mutex> lk(mtx);
bool result = cv.wait_for(lk, std::chrono::milliseconds(30000), [&ctxt]() -> bool {
return static_cast<bool>(ctxt.GetServiceReference<test::ISpellCheckService>()) == false;
});
ctxt.RemoveListener(std::move(token));
ASSERT_TRUE(result);
EXPECT_TRUE(ctxt.GetServiceReferences<test::ISpellCheckService>().empty());
spellCheckRef = ctxt.GetServiceReference<test::ISpellCheckService>();
EXPECT_FALSE(static_cast<bool>(spellCheckRef));
}
spellcheckerBundle.Stop();
// try the DS spell checker with a non-DS dictionary
spellcheckerBundle.Start(); // restart the bundle to re-use it, since the
// default binding policy is static reluctant.
EXPECT_TRUE(ctxt.GetServiceReferences<test::ISpellCheckService>().empty());
EXPECT_TRUE(ctxt.GetServiceReferences<test::IDictionaryService>().empty());
// register service listener and wait for SERVICE_REGISTERED event for SpellCheck service
std::mutex mtx1;
std::condition_variable cv1;
auto token1 = ctxt.AddServiceListener([&](const cppmicroservices::ServiceEvent& evt) {
if(evt.GetType() == cppmicroservices::ServiceEvent::SERVICE_REGISTERED &&
evt.GetServiceReference().GetBundle() == spellcheckerBundle)
{
{
std::unique_lock<std::mutex> lk(mtx1);
}
cv1.notify_all();
}
});
auto englishDictDSBundle = StartTestBundle("EnglishDictionary");
EXPECT_EQ(ctxt.GetServiceReferences<test::IDictionaryService>().size(), 1ul);
{
std::unique_lock<std::mutex> lk(mtx1);
auto result = cv1.wait_for(lk, std::chrono::milliseconds(30000), [&ctxt]() -> bool {
return static_cast<bool>(ctxt.GetServiceReference<test::ISpellCheckService>());
});
ctxt.RemoveListener(std::move(token1));
ASSERT_TRUE(result);
spellCheckRef = ctxt.GetServiceReference<test::ISpellCheckService>();
ASSERT_TRUE(static_cast<bool>(spellCheckRef));
service = ctxt.GetService<test::ISpellCheckService>(spellCheckRef);
}
ASSERT_NE(service, nullptr);
EXPECT_TRUE(service->Check("welcome to micro services tutorial").empty());
auto misspelledWords = service->Check("welcome to microservices tutorial page");
EXPECT_FALSE(misspelledWords.empty());
auto expectedWords = { "microservices", "page" };
EXPECT_TRUE(std::equal(misspelledWords.begin(), misspelledWords.end(), expectedWords.begin()));
EXPECT_TRUE(service->Check("welcome micro").empty()); // verify partial string
}
}
|
/*************************************************************************
* Copyright (C) [2020] by Cambricon, Inc. All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*************************************************************************/
#include "cnfont.hpp"
#ifdef HAVE_OPENCV
#include "opencv2/highgui/highgui.hpp"
#include "opencv2/imgproc/imgproc.hpp"
#if (CV_MAJOR_VERSION >= 3)
#include "opencv2/imgcodecs/imgcodecs.hpp"
#endif
#else
#error OpenCV required
#endif
#include <string>
#include "glog/logging.h"
namespace cnstream {
#ifdef HAVE_FREETYPE
bool CnFont::Init(const std::string &font_path) {
if (FT_Init_FreeType(&m_library)) {
LOG(ERROR) << "FreeType init errors";
return false;
}
if (FT_New_Face(m_library, font_path.c_str(), 0, &m_face)) {
FT_Done_FreeType(m_library);
LOG(ERROR) << "Can not create a font, please checkout the font path: " << m_library;
return false;
}
// Set font args
restoreFont();
// Set font env
setlocale(LC_ALL, "");
is_initialized_ = true;
return true;
}
CnFont::~CnFont() {
if (is_initialized_) {
FT_Done_Face(m_face);
FT_Done_FreeType(m_library);
}
}
// Restore the original font Settings
void CnFont::restoreFont() {
if (!is_initialized_) {
LOG(ERROR) << " [Osd] Please init CnFont first.";
return;
}
m_fontType = 0;
m_fontSize.val[0] = 20;
m_fontSize.val[1] = 0.5;
m_fontSize.val[2] = 0.1;
m_fontSize.val[3] = 0;
m_fontUnderline = false;
m_fontDiaphaneity = 1.0;
// Set character size
FT_Set_Pixel_Sizes(m_face, static_cast<int>(m_fontSize.val[0]), 0);
}
int CnFont::ToWchar(char*& src, wchar_t*& dest, const char* locale) {
if (src == NULL) {
dest = NULL;
return 0;
}
// Set the locale according to the environment variable
setlocale(LC_CTYPE, locale);
// Gets the required wide character size to convert to
int w_size = mbstowcs(NULL, src, 0) + 1;
if (w_size == 0) {
dest = NULL;
return -1;
}
dest = new (std::nothrow) wchar_t[w_size];
if (!dest) {
return -1;
}
int ret = mbstowcs(dest, src, strlen(src) + 1);
if (ret <= 0) {
return -1;
}
return 0;
}
int CnFont::putText(cv::Mat& img, char* text, cv::Point pos, cv::Scalar color) {
if (img.data == nullptr) return -1;
if (text == nullptr) return -1;
if (!is_initialized_) {
LOG(ERROR) << " [Osd] Please init CnFont first.";
return -1;
}
wchar_t* w_str;
ToWchar(text, w_str);
for (int i = 0; w_str[i] != '\0'; ++i) {
putWChar(img, w_str[i], pos, color);
}
return 0;
}
// Output the current character and update the m pos position
void CnFont::putWChar(cv::Mat& img, wchar_t wc, cv::Point& pos, cv::Scalar color) {
// Generate a binary bitmap of a font based on unicode
FT_UInt glyph_index = FT_Get_Char_Index(m_face, wc);
FT_Load_Glyph(m_face, glyph_index, FT_LOAD_DEFAULT);
FT_Render_Glyph(m_face->glyph, FT_RENDER_MODE_MONO);
FT_GlyphSlot slot = m_face->glyph;
// Cols and rows
int rows = slot->bitmap.rows;
int cols = slot->bitmap.width;
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
int off = i * slot->bitmap.pitch + j / 8;
if (slot->bitmap.buffer[off] & (0xC0 >> (j % 8))) {
int r = pos.y - (rows - 1 - i);
int c = pos.x + j;
if (r >= 0 && r < img.rows && c >= 0 && c < img.cols) {
cv::Vec3b pixel = img.at<cv::Vec3b>(cv::Point(c, r));
cv::Scalar scalar = cv::Scalar(pixel.val[0], pixel.val[1], pixel.val[2]);
// Color fusion
float p = m_fontDiaphaneity;
for (int k = 0; k < 4; ++k) {
scalar.val[k] = scalar.val[k] * (1 - p) + color.val[k] * p;
}
img.at<cv::Vec3b>(cv::Point(c, r))[0] = (unsigned char)(scalar.val[0]);
img.at<cv::Vec3b>(cv::Point(c, r))[1] = (unsigned char)(scalar.val[1]);
img.at<cv::Vec3b>(cv::Point(c, r))[2] = (unsigned char)(scalar.val[2]);
}
}
}
}
// Modify the output position of the next word
double space = m_fontSize.val[0] * m_fontSize.val[1];
double sep = m_fontSize.val[0] * m_fontSize.val[2];
pos.x += static_cast<int>((cols ? cols : space) + sep);
}
#endif
} // namespace cnstream
|
; A041188: Numerators of continued fraction convergents to sqrt(105).
; Submitted by Christian Krause
; 10,41,830,3361,68050,275561,5579270,22592641,457432090,1852321001,37503852110,151867729441,3074858440930,12451301493161,252100888304150,1020854854709761,20669197982499370,83697646784707241,1694622133676644190,6862186181491284001,138938345763502324210,562615569235500580841,11391249730473513941030,46127614491129556344961,933943539553064640840250,3781901772703388119705961,76571978993620827034959470,310069817747186696259543841,6277968333937354752225836290,25421943153496605705162889001
add $0,1
mov $3,1
lpb $0
sub $0,1
add $3,$2
add $2,$3
mov $3,$1
mov $1,$2
dif $2,5
mul $2,10
lpe
add $3,$2
mov $0,$3
|
; A055631: Sum of Euler's totient function phi of distinct primes dividing n.
; 0,1,2,1,4,3,6,1,2,5,10,3,12,7,6,1,16,3,18,5,8,11,22,3,4,13,2,7,28,7,30,1,12,17,10,3,36,19,14,5,40,9,42,11,6,23,46,3,6,5,18,13,52,3,14,7,20,29,58,7,60,31,8,1,16,13,66,17,24,11,70,3,72,37,6,19,16,15,78,5,2,41,82,9,20,43,30,11,88,7,18,23,32,47,22,3,96,7,12,5
add $0,1
mov $2,1
mov $3,$0
mov $4,$0
lpb $3
mov $5,$4
lpb $0
lpb $5
mov $7,$0
div $0,$2
mod $7,$2
cmp $7,0
sub $5,$7
lpe
cmp $6,0
lpe
cmp $6,0
mov $7,$2
pow $7,$6
add $1,$7
add $2,1
mov $7,$0
cmp $7,1
cmp $7,0
sub $3,$7
mov $6,1
lpe
mov $0,$1
|
.size 8000
.text@48
jp lstatint
.text@100
jp lbegin
.data@143
80
.text@150
lbegin:
ld c, 41
ld b, 02
ld d, 03
lbegin_waitm2:
ldff a, (c)
and a, d
cmp a, b
jrnz lbegin_waitm2
ld a, 08
ldff(c), a
xor a, a
ldff(0f), a
ld a, 02
ldff(ff), a
ei
ld c, 0f
.text@1000
lstatint:
ld a, 48
ldff(41), a
ldff a, (44)
inc a
ldff(45), a
ld a, 02
ldff(43), a
.text@1058
xor a, a
ldff(c), a
nop
nop
nop
nop
nop
ld a, 08
ldff(41), a
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
ldff a, (c)
and a, 03
jp lprint_a
.text@7000
lprint_a:
push af
ld b, 91
call lwaitly_b
xor a, a
ldff(40), a
pop af
ld(9800), a
ld bc, 7a00
ld hl, 8000
ld d, a0
lprint_copytiles:
ld a, (bc)
inc bc
ld(hl++), a
dec d
jrnz lprint_copytiles
ld a, c0
ldff(47), a
ld a, 80
ldff(68), a
ld a, ff
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
xor a, a
ldff(69), a
ldff(69), a
ldff(43), a
ld a, 91
ldff(40), a
lprint_limbo:
jr lprint_limbo
.text@7400
lwaitly_b:
ld c, 44
lwaitly_b_loop:
ldff a, (c)
cmp a, b
jrnz lwaitly_b_loop
ret
.data@7a00
00 00 7f 7f 41 41 41 41
41 41 41 41 41 41 7f 7f
00 00 08 08 08 08 08 08
08 08 08 08 08 08 08 08
00 00 7f 7f 01 01 01 01
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 01 01 01 01
3f 3f 01 01 01 01 7f 7f
00 00 41 41 41 41 41 41
7f 7f 01 01 01 01 01 01
00 00 7f 7f 40 40 40 40
7e 7e 01 01 01 01 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 41 41 41 41 7f 7f
00 00 7f 7f 01 01 02 02
04 04 08 08 10 10 10 10
00 00 3e 3e 41 41 41 41
3e 3e 41 41 41 41 3e 3e
00 00 7f 7f 41 41 41 41
7f 7f 01 01 01 01 7f 7f
|
BITS 32
org 0x7c00
mov edx, 0x03f8
in al, dx
jmp 0
|
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
;
; LRotU64.nasm
;
; Abstract:
;
; 64-bit left rotation for Ia32
;
;------------------------------------------------------------------------------
SECTION .text
;------------------------------------------------------------------------------
; UINT64
; EFIAPI
; InternalMathLRotU64 (
; IN UINT64 Operand,
; IN UINTN Count
; );
;------------------------------------------------------------------------------
global ASM_PFX(InternalMathLRotU64)
ASM_PFX(InternalMathLRotU64):
push ebx
mov cl, [esp + 16]
mov edx, [esp + 12]
mov eax, [esp + 8]
shld ebx, edx, cl
shld edx, eax, cl
ror ebx, cl
shld eax, ebx, cl
test cl, 32 ; Count >= 32?
jz .0
mov ecx, eax
mov eax, edx
mov edx, ecx
.0:
pop ebx
ret
|
/*
* Copyright 2016 The Cartographer Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string>
#include <vector>
#include "cartographer_ros/node_options.h"
#include "gtest/gtest.h"
#include "ros/package.h"
namespace cartographer_ros {
namespace {
class ConfigurationFilesTest : public ::testing::TestWithParam<const char*> {};
TEST_P(ConfigurationFilesTest, ValidateNodeOptions) {
EXPECT_NO_FATAL_FAILURE({
LoadOptions(::ros::package::getPath("cartographer_toyota_hsr") +
"/configuration_files",
GetParam());
});
}
INSTANTIATE_TEST_CASE_P(ValidateAllNodeOptions, ConfigurationFilesTest,
::testing::Values("toyota_hsr_2d.lua",
"toyota_hsr_3d.lua"));
} // namespace
} // namespace cartographer_ros
|
; A164464: Number of binary strings of length n with no substrings equal to 0001, 0100, or 0111.
; 13,20,31,47,70,104,154,227,334,491,721,1058,1552,2276,3337,4892,7171,10511,15406,22580,33094,48503,71086,104183,152689,223778,327964,480656,704437,1032404,1513063,2217503,3249910,4762976,6980482,10230395,14993374,21973859,32204257,47197634,69171496,101375756,148573393,217744892,319120651,467694047,685438942,1004559596,1472253646,2157692591,3162252190,4634505839,6792198433,9954450626,14588956468,21381154904,31335605533,45924562004,67305716911,98641322447,144565884454,211871601368,310512923818
mul $0,2
mov $1,2
mov $4,9
add $4,$0
mov $0,$4
mov $2,1
mov $3,1
mov $4,2
lpb $0
trn $0,2
sub $4,1
mov $5,$1
add $1,$3
add $1,$4
mov $4,$2
mov $2,$5
lpe
sub $1,3
mov $0,$1
|
; A061085: a(n) = A019550(n) / 3.
; 4,8,12,16,170,204,238,272,306,340,374,408,442,476,510,544,578,612,646,680,714,748,782,816,850,884,918,952,986,1020,1054,1088,1122,1156,1190,1224,1258,1292,1326,1360,1394,1428,1462,1496,1530,1564,1598,1632,1666
seq $0,309809 ; a(n) is the concatenation of n and 2n+1.
div $0,3
|
; Internal routine to read increment local address HL with far pointer EBC
; 31/3/00 GWL
; Corrupts D via farseg1, but preserves A
;
; $Id: incfar.asm,v 1.3 2015/01/19 01:32:43 pauloscustodio Exp $
;
PUBLIC incfar
EXTERN farseg1
.incfar
inc hl
inc c
ret nz
inc b
jr nz,skiphigh
inc e
.skiphigh
push af
call farseg1
pop af
ret
|
; A192033: Expansion of x*(3*x^2+x+1)/((x-1)*(2*x-1)*(x+1)).
; 0,1,3,10,21,46,93,190,381,766,1533,3070,6141,12286,24573,49150,98301,196606,393213,786430,1572861,3145726,6291453,12582910,25165821,50331646,100663293,201326590,402653181,805306366,1610612733,3221225470,6442450941,12884901886,25769803773,51539607550,103079215101,206158430206,412316860413,824633720830,1649267441661,3298534883326,6597069766653,13194139533310,26388279066621,52776558133246,105553116266493,211106232532990,422212465065981,844424930131966,1688849860263933,3377699720527870,6755399441055741,13510798882111486,27021597764222973,54043195528445950,108086391056891901,216172782113783806,432345564227567613,864691128455135230,1729382256910270461,3458764513820540926,6917529027641081853,13835058055282163710,27670116110564327421,55340232221128654846,110680464442257309693,221360928884514619390,442721857769029238781,885443715538058477566,1770887431076116955133,3541774862152233910270,7083549724304467820541,14167099448608935641086,28334198897217871282173,56668397794435742564350,113336795588871485128701,226673591177742970257406,453347182355485940514813,906694364710971881029630,1813388729421943762059261,3626777458843887524118526,7253554917687775048237053,14507109835375550096474110,29014219670751100192948221,58028439341502200385896446,116056878683004400771792893,232113757366008801543585790,464227514732017603087171581,928455029464035206174343166,1856910058928070412348686333,3713820117856140824697372670,7427640235712281649394745341,14855280471424563298789490686,29710560942849126597578981373,59421121885698253195157962750,118842243771396506390315925501,237684487542793012780631851006,475368975085586025561263702013,950737950171172051122527404030
lpb $0
sub $0,1
add $1,1
mov $3,$1
add $4,1
mov $1,$4
mul $3,2
add $2,$3
mov $4,$2
add $2,3
lpe
mov $0,$1
|
.model small
.stack 100h
.code
main proc
mov ah,1
int 21h
mov bl,al
mov ah,02h
mov ah,1
int 21h
mov ah,02h
mov bh,al
mov ah,02h
mov cl,al
mov ah,02h
mov dl,0Ah
int 21h
mov dl,0Dh
int 21h
mov ah,2
mov dl,bl
int 21h
mov ah,2
mov dl,bh
int 21h
mov ah,4ch
int 21h
main endp
end main |
; Copyright 2019 by Sven Fabricius, see LICENSE.txt
;
; @file SSD1289_WriteReg.asm
;
; @brief Writes data to a specified SSD1289 register
;
; @author Sven Fabricius
; Contact: Sven.Fabricius@livediesel.de
;typedef struct _SSD1289_Config
;{
; volatile uint16_t * dataOut; + 0
; volatile uint16_t * dataIn; + 4
; volatile uint16_t * dataDir; + 8
; volatile uint16_t * ctrlOut; + 12
; uint16_t csPin; + 16
; uint16_t rsPin; + 18
; uint16_t rdPin; + 20
; uint16_t wrPin; + 22
;} SSD1289_Config;
DATA_OUT_OFF .set 0x00
DATA_IN_OFF .set 0x04
DATA_DIR_OFF .set 0x08
CTRL_OUT_OFF .set 0x0C
CS_PIN_OFF .set 0x10
RS_PIN_OFF .set 0x12
RD_PIN_OFF .set 0x14
WR_PIN_OFF .set 0x16
;############################################################################################
; extern void SSD1289_WriteReg(SSD1289_Config * config, uint16_t command, uint16_t data);
.global SSD1289_WriteReg
SSD1289_WriteReg: .asmfunc
config .set r0
command .set r1
data .set r2
ctrlOut .set r3
dataOut .set r4
w0 .set r5
w1 .set r6
buffer .set r7
PUSH {r4-r7,lr} ; 5 regs are pushed, SP is decremented by 5*4 = 20 bytes
LDR ctrlOut, [config, #CTRL_OUT_OFF] ; load pointer to Ctrl out
LDR dataOut, [config, #DATA_OUT_OFF] ; load pointer to Data out
LDRH w1, [ctrlOut] ; load Ctrl data
LDRH buffer, [config, #WR_PIN_OFF] ; load WR pin
BIC w0, w1, buffer ; disable WR pin
LDRH buffer, [config, #RS_PIN_OFF] ; load RS pin
BIC w0, w0, buffer ; disable RS pin
STRH w0, [ctrlOut] ; set Ctrl out ; WR Low, RS Low
STRH command, [dataOut] ; set Data out
STRH w1, [ctrlOut] ; set Ctrl out ; WR High, RS High
ORR w0, w0, buffer ; enable RS pin
STRH w0, [ctrlOut] ; set Ctrl out ; WR Low, RS High
STRH data, [dataOut] ; set Data out
STRH w1, [ctrlOut] ; set Ctrl out ; WR High, RS High
POP {r4-r7,lr}
BX lr
.endasmfunc
|
.TITEL HELLO WORLED
.MODEL SMALL
.STACK 100H
.DATA
MESSAGE DB "HELLO,WORLED$"
.CODE
MAIN PROC
MOV AX,@DATA
MOV DS,AX
LEA DX,MESSAGE
MOV AH,09H
INT 21H
MOV AH,4CH
INT 21H
MAIN ENDP
END MAIN
|
; A093964: a(n) = Sum_{k=1..n} k*k!*C(n,k).
; 0,1,6,33,196,1305,9786,82201,767208,7891281,88776910,1085051121,14322674796,203121569833,3080677142466,49764784609065,853110593298256,15469738758475041
lpb $0,1
add $3,$0
sub $0,1
add $2,1
mul $3,$2
lpe
mov $1,$3
|
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Interval and RefPosition Building XX
XX XX
XX This contains the logic for constructing Intervals and RefPositions that XX
XX is common across architectures. See lsra{arch}.cpp for the architecture- XX
XX specific methods for building. XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#ifndef LEGACY_BACKEND // This file is ONLY used for the RyuJIT backend that uses the linear scan register allocator
#include "lsra.h"
//------------------------------------------------------------------------
// LocationInfoListNodePool::LocationInfoListNodePool:
// Creates a pool of `LocationInfoListNode` values.
//
// Arguments:
// compiler - The compiler context.
// preallocate - The number of nodes to preallocate.
//
LocationInfoListNodePool::LocationInfoListNodePool(Compiler* compiler, unsigned preallocate) : m_compiler(compiler)
{
if (preallocate > 0)
{
size_t preallocateSize = sizeof(LocationInfoListNode) * preallocate;
LocationInfoListNode* preallocatedNodes =
reinterpret_cast<LocationInfoListNode*>(compiler->compGetMem(preallocateSize, CMK_LSRA));
LocationInfoListNode* head = preallocatedNodes;
head->m_next = nullptr;
for (unsigned i = 1; i < preallocate; i++)
{
LocationInfoListNode* node = &preallocatedNodes[i];
node->m_next = head;
head = node;
}
m_freeList = head;
}
}
//------------------------------------------------------------------------
// LocationInfoListNodePool::GetNode: Fetches an unused node from the
// pool.
//
// Arguments:
// l - - The `LsraLocation` for the `LocationInfo` value.
// i - The interval for the `LocationInfo` value.
// t - The IR node for the `LocationInfo` value
// regIdx - The register index for the `LocationInfo` value.
//
// Returns:
// A pooled or newly-allocated `LocationInfoListNode`, depending on the
// contents of the pool.
LocationInfoListNode* LocationInfoListNodePool::GetNode(LsraLocation l, Interval* i, GenTree* t, unsigned regIdx)
{
LocationInfoListNode* head = m_freeList;
if (head == nullptr)
{
head = reinterpret_cast<LocationInfoListNode*>(m_compiler->compGetMem(sizeof(LocationInfoListNode)));
}
else
{
m_freeList = head->m_next;
}
head->loc = l;
head->interval = i;
head->treeNode = t;
head->m_next = nullptr;
return head;
}
//------------------------------------------------------------------------
// LocationInfoListNodePool::ReturnNodes: Returns a list of nodes to the node
// pool and clears the given list.
//
// Arguments:
// list - The list to return.
//
void LocationInfoListNodePool::ReturnNodes(LocationInfoList& list)
{
assert(list.m_head != nullptr);
assert(list.m_tail != nullptr);
LocationInfoListNode* head = m_freeList;
list.m_tail->m_next = head;
m_freeList = list.m_head;
list.m_head = nullptr;
list.m_tail = nullptr;
}
//------------------------------------------------------------------------
// newInterval: Create a new Interval of the given RegisterType.
//
// Arguments:
// theRegisterType - The type of Interval to create.
//
// TODO-Cleanup: Consider adding an overload that takes a varDsc, and can appropriately
// set such fields as isStructField
//
Interval* LinearScan::newInterval(RegisterType theRegisterType)
{
intervals.emplace_back(theRegisterType, allRegs(theRegisterType));
Interval* newInt = &intervals.back();
#ifdef DEBUG
newInt->intervalIndex = static_cast<unsigned>(intervals.size() - 1);
#endif // DEBUG
DBEXEC(VERBOSE, newInt->dump());
return newInt;
}
//------------------------------------------------------------------------
// newRefPositionRaw: Create a new RefPosition
//
// Arguments:
// nodeLocation - The location of the reference.
// treeNode - The GenTree of the reference.
// refType - The type of reference
//
// Notes:
// This is used to create RefPositions for both RegRecords and Intervals,
// so it does only the common initialization.
//
RefPosition* LinearScan::newRefPositionRaw(LsraLocation nodeLocation, GenTree* treeNode, RefType refType)
{
refPositions.emplace_back(curBBNum, nodeLocation, treeNode, refType);
RefPosition* newRP = &refPositions.back();
#ifdef DEBUG
newRP->rpNum = static_cast<unsigned>(refPositions.size() - 1);
#endif // DEBUG
return newRP;
}
//------------------------------------------------------------------------
// resolveConflictingDefAndUse: Resolve the situation where we have conflicting def and use
// register requirements on a single-def, single-use interval.
//
// Arguments:
// defRefPosition - The interval definition
// useRefPosition - The (sole) interval use
//
// Return Value:
// None.
//
// Assumptions:
// The two RefPositions are for the same interval, which is a tree-temp.
//
// Notes:
// We require some special handling for the case where the use is a "delayRegFree" case of a fixedReg.
// In that case, if we change the registerAssignment on the useRefPosition, we will lose the fact that,
// even if we assign a different register (and rely on codegen to do the copy), that fixedReg also needs
// to remain busy until the Def register has been allocated. In that case, we don't allow Case 1 or Case 4
// below.
// Here are the cases we consider (in this order):
// 1. If The defRefPosition specifies a single register, and there are no conflicting
// FixedReg uses of it between the def and use, we use that register, and the code generator
// will insert the copy. Note that it cannot be in use because there is a FixedRegRef for the def.
// 2. If the useRefPosition specifies a single register, and it is not in use, and there are no
// conflicting FixedReg uses of it between the def and use, we use that register, and the code generator
// will insert the copy.
// 3. If the defRefPosition specifies a single register (but there are conflicts, as determined
// in 1.), and there are no conflicts with the useRefPosition register (if it's a single register),
/// we set the register requirements on the defRefPosition to the use registers, and the
// code generator will insert a copy on the def. We can't rely on the code generator to put a copy
// on the use if it has multiple possible candidates, as it won't know which one has been allocated.
// 4. If the useRefPosition specifies a single register, and there are no conflicts with the register
// on the defRefPosition, we leave the register requirements on the defRefPosition as-is, and set
// the useRefPosition to the def registers, for similar reasons to case #3.
// 5. If both the defRefPosition and the useRefPosition specify single registers, but both have conflicts,
// We set the candiates on defRefPosition to be all regs of the appropriate type, and since they are
// single registers, codegen can insert the copy.
// 6. Finally, if the RefPositions specify disjoint subsets of the registers (or the use is fixed but
// has a conflict), we must insert a copy. The copy will be inserted before the use if the
// use is not fixed (in the fixed case, the code generator will insert the use).
//
// TODO-CQ: We get bad register allocation in case #3 in the situation where no register is
// available for the lifetime. We end up allocating a register that must be spilled, and it probably
// won't be the register that is actually defined by the target instruction. So, we have to copy it
// and THEN spill it. In this case, we should be using the def requirement. But we need to change
// the interface to this method a bit to make that work (e.g. returning a candidate set to use, but
// leaving the registerAssignment as-is on the def, so that if we find that we need to spill anyway
// we can use the fixed-reg on the def.
//
void LinearScan::resolveConflictingDefAndUse(Interval* interval, RefPosition* defRefPosition)
{
assert(!interval->isLocalVar);
RefPosition* useRefPosition = defRefPosition->nextRefPosition;
regMaskTP defRegAssignment = defRefPosition->registerAssignment;
regMaskTP useRegAssignment = useRefPosition->registerAssignment;
RegRecord* defRegRecord = nullptr;
RegRecord* useRegRecord = nullptr;
regNumber defReg = REG_NA;
regNumber useReg = REG_NA;
bool defRegConflict = false;
bool useRegConflict = false;
// If the useRefPosition is a "delayRegFree", we can't change the registerAssignment
// on it, or we will fail to ensure that the fixedReg is busy at the time the target
// (of the node that uses this interval) is allocated.
bool canChangeUseAssignment = !useRefPosition->isFixedRegRef || !useRefPosition->delayRegFree;
INDEBUG(dumpLsraAllocationEvent(LSRA_EVENT_DEFUSE_CONFLICT));
if (!canChangeUseAssignment)
{
INDEBUG(dumpLsraAllocationEvent(LSRA_EVENT_DEFUSE_FIXED_DELAY_USE));
}
if (defRefPosition->isFixedRegRef)
{
defReg = defRefPosition->assignedReg();
defRegRecord = getRegisterRecord(defReg);
if (canChangeUseAssignment)
{
RefPosition* currFixedRegRefPosition = defRegRecord->recentRefPosition;
assert(currFixedRegRefPosition != nullptr &&
currFixedRegRefPosition->nodeLocation == defRefPosition->nodeLocation);
if (currFixedRegRefPosition->nextRefPosition == nullptr ||
currFixedRegRefPosition->nextRefPosition->nodeLocation > useRefPosition->getRefEndLocation())
{
// This is case #1. Use the defRegAssignment
INDEBUG(dumpLsraAllocationEvent(LSRA_EVENT_DEFUSE_CASE1));
useRefPosition->registerAssignment = defRegAssignment;
return;
}
else
{
defRegConflict = true;
}
}
}
if (useRefPosition->isFixedRegRef)
{
useReg = useRefPosition->assignedReg();
useRegRecord = getRegisterRecord(useReg);
RefPosition* currFixedRegRefPosition = useRegRecord->recentRefPosition;
// We know that useRefPosition is a fixed use, so the nextRefPosition must not be null.
RefPosition* nextFixedRegRefPosition = useRegRecord->getNextRefPosition();
assert(nextFixedRegRefPosition != nullptr &&
nextFixedRegRefPosition->nodeLocation <= useRefPosition->nodeLocation);
// First, check to see if there are any conflicting FixedReg references between the def and use.
if (nextFixedRegRefPosition->nodeLocation == useRefPosition->nodeLocation)
{
// OK, no conflicting FixedReg references.
// Now, check to see whether it is currently in use.
if (useRegRecord->assignedInterval != nullptr)
{
RefPosition* possiblyConflictingRef = useRegRecord->assignedInterval->recentRefPosition;
LsraLocation possiblyConflictingRefLocation = possiblyConflictingRef->getRefEndLocation();
if (possiblyConflictingRefLocation >= defRefPosition->nodeLocation)
{
useRegConflict = true;
}
}
if (!useRegConflict)
{
// This is case #2. Use the useRegAssignment
INDEBUG(dumpLsraAllocationEvent(LSRA_EVENT_DEFUSE_CASE2));
defRefPosition->registerAssignment = useRegAssignment;
return;
}
}
else
{
useRegConflict = true;
}
}
if (defRegRecord != nullptr && !useRegConflict)
{
// This is case #3.
INDEBUG(dumpLsraAllocationEvent(LSRA_EVENT_DEFUSE_CASE3));
defRefPosition->registerAssignment = useRegAssignment;
return;
}
if (useRegRecord != nullptr && !defRegConflict && canChangeUseAssignment)
{
// This is case #4.
INDEBUG(dumpLsraAllocationEvent(LSRA_EVENT_DEFUSE_CASE4));
useRefPosition->registerAssignment = defRegAssignment;
return;
}
if (defRegRecord != nullptr && useRegRecord != nullptr)
{
// This is case #5.
INDEBUG(dumpLsraAllocationEvent(LSRA_EVENT_DEFUSE_CASE5));
RegisterType regType = interval->registerType;
assert((getRegisterType(interval, defRefPosition) == regType) &&
(getRegisterType(interval, useRefPosition) == regType));
regMaskTP candidates = allRegs(regType);
defRefPosition->registerAssignment = candidates;
return;
}
INDEBUG(dumpLsraAllocationEvent(LSRA_EVENT_DEFUSE_CASE6));
return;
}
//------------------------------------------------------------------------
// applyCalleeSaveHeuristics: Set register preferences for an interval based on the given RefPosition
//
// Arguments:
// rp - The RefPosition of interest
//
// Notes:
// This is slightly more general than its name applies, and updates preferences not just
// for callee-save registers.
//
void LinearScan::applyCalleeSaveHeuristics(RefPosition* rp)
{
#ifdef _TARGET_AMD64_
if (compiler->opts.compDbgEnC)
{
// We only use RSI and RDI for EnC code, so we don't want to favor callee-save regs.
return;
}
#endif // _TARGET_AMD64_
Interval* theInterval = rp->getInterval();
#ifdef DEBUG
if (!doReverseCallerCallee())
#endif // DEBUG
{
// Set preferences so that this register set will be preferred for earlier refs
theInterval->updateRegisterPreferences(rp->registerAssignment);
}
}
//------------------------------------------------------------------------
// checkConflictingDefUse: Ensure that we have consistent def/use on SDSU temps.
//
// Arguments:
// useRP - The use RefPosition of a tree temp (SDSU Interval)
//
// Notes:
// There are a couple of cases where this may over-constrain allocation:
// 1. In the case of a non-commutative rmw def (in which the rmw source must be delay-free), or
// 2. In the case where the defining node requires a temp distinct from the target (also a
// delay-free case).
// In those cases, if we propagate a single-register restriction from the consumer to the producer
// the delayed uses will not see a fixed reference in the PhysReg at that position, and may
// incorrectly allocate that register.
// TODO-CQ: This means that we may often require a copy at the use of this node's result.
// This case could be moved to BuildRefPositionsForNode, at the point where the def RefPosition is
// created, causing a RefTypeFixedRef to be added at that location. This, however, results in
// more PhysReg RefPositions (a throughput impact), and a large number of diffs that require
// further analysis to determine benefit.
// See Issue #11274.
//
void LinearScan::checkConflictingDefUse(RefPosition* useRP)
{
assert(useRP->refType == RefTypeUse);
Interval* theInterval = useRP->getInterval();
assert(!theInterval->isLocalVar);
RefPosition* defRP = theInterval->firstRefPosition;
// All defs must have a valid treeNode, but we check it below to be conservative.
assert(defRP->treeNode != nullptr);
regMaskTP prevAssignment = defRP->registerAssignment;
regMaskTP newAssignment = (prevAssignment & useRP->registerAssignment);
if (newAssignment != RBM_NONE)
{
if (!isSingleRegister(newAssignment) || !theInterval->hasInterferingUses)
{
defRP->registerAssignment = newAssignment;
}
}
else
{
theInterval->hasConflictingDefUse = true;
}
}
//------------------------------------------------------------------------
// associateRefPosWithInterval: Update the Interval based on the given RefPosition.
//
// Arguments:
// rp - The RefPosition of interest
//
// Notes:
// This is called at the time when 'rp' has just been created, so it becomes
// the nextRefPosition of the recentRefPosition, and both the recentRefPosition
// and lastRefPosition of its referent.
//
void LinearScan::associateRefPosWithInterval(RefPosition* rp)
{
Referenceable* theReferent = rp->referent;
if (theReferent != nullptr)
{
// All RefPositions except the dummy ones at the beginning of blocks
if (rp->isIntervalRef())
{
Interval* theInterval = rp->getInterval();
applyCalleeSaveHeuristics(rp);
if (theInterval->isLocalVar)
{
if (RefTypeIsUse(rp->refType))
{
RefPosition* const prevRP = theInterval->recentRefPosition;
if ((prevRP != nullptr) && (prevRP->bbNum == rp->bbNum))
{
prevRP->lastUse = false;
}
}
rp->lastUse = (rp->refType != RefTypeExpUse) && (rp->refType != RefTypeParamDef) &&
(rp->refType != RefTypeZeroInit) && !extendLifetimes();
}
else if (rp->refType == RefTypeUse)
{
checkConflictingDefUse(rp);
rp->lastUse = true;
}
}
RefPosition* prevRP = theReferent->recentRefPosition;
if (prevRP != nullptr)
{
prevRP->nextRefPosition = rp;
}
else
{
theReferent->firstRefPosition = rp;
}
theReferent->recentRefPosition = rp;
theReferent->lastRefPosition = rp;
}
else
{
assert((rp->refType == RefTypeBB) || (rp->refType == RefTypeKillGCRefs));
}
}
//---------------------------------------------------------------------------
// newRefPosition: allocate and initialize a new RefPosition.
//
// Arguments:
// reg - reg number that identifies RegRecord to be associated
// with this RefPosition
// theLocation - LSRA location of RefPosition
// theRefType - RefPosition type
// theTreeNode - GenTree node for which this RefPosition is created
// mask - Set of valid registers for this RefPosition
// multiRegIdx - register position if this RefPosition corresponds to a
// multi-reg call node.
//
// Return Value:
// a new RefPosition
//
RefPosition* LinearScan::newRefPosition(
regNumber reg, LsraLocation theLocation, RefType theRefType, GenTree* theTreeNode, regMaskTP mask)
{
RefPosition* newRP = newRefPositionRaw(theLocation, theTreeNode, theRefType);
newRP->setReg(getRegisterRecord(reg));
newRP->registerAssignment = mask;
newRP->setMultiRegIdx(0);
newRP->setAllocateIfProfitable(false);
associateRefPosWithInterval(newRP);
DBEXEC(VERBOSE, newRP->dump());
return newRP;
}
//---------------------------------------------------------------------------
// newRefPosition: allocate and initialize a new RefPosition.
//
// Arguments:
// theInterval - interval to which RefPosition is associated with.
// theLocation - LSRA location of RefPosition
// theRefType - RefPosition type
// theTreeNode - GenTree node for which this RefPosition is created
// mask - Set of valid registers for this RefPosition
// multiRegIdx - register position if this RefPosition corresponds to a
// multi-reg call node.
//
// Return Value:
// a new RefPosition
//
RefPosition* LinearScan::newRefPosition(Interval* theInterval,
LsraLocation theLocation,
RefType theRefType,
GenTree* theTreeNode,
regMaskTP mask,
unsigned multiRegIdx /* = 0 */)
{
#ifdef DEBUG
if (theInterval != nullptr && regType(theInterval->registerType) == FloatRegisterType)
{
// In the case we're using floating point registers we must make sure
// this flag was set previously in the compiler since this will mandate
// whether LSRA will take into consideration FP reg killsets.
assert(compiler->compFloatingPointUsed || ((mask & RBM_FLT_CALLEE_SAVED) == 0));
}
#endif // DEBUG
// If this reference is constrained to a single register (and it's not a dummy
// or Kill reftype already), add a RefTypeFixedReg at this location so that its
// availability can be more accurately determined
bool isFixedRegister = isSingleRegister(mask);
bool insertFixedRef = false;
if (isFixedRegister)
{
// Insert a RefTypeFixedReg for any normal def or use (not ParamDef or BB)
if (theRefType == RefTypeUse || theRefType == RefTypeDef)
{
insertFixedRef = true;
}
}
if (insertFixedRef)
{
regNumber physicalReg = genRegNumFromMask(mask);
RefPosition* pos = newRefPosition(physicalReg, theLocation, RefTypeFixedReg, nullptr, mask);
assert(theInterval != nullptr);
assert((allRegs(theInterval->registerType) & mask) != 0);
}
RefPosition* newRP = newRefPositionRaw(theLocation, theTreeNode, theRefType);
newRP->setInterval(theInterval);
// Spill info
newRP->isFixedRegRef = isFixedRegister;
#ifndef _TARGET_AMD64_
// We don't need this for AMD because the PInvoke method epilog code is explicit
// at register allocation time.
if (theInterval != nullptr && theInterval->isLocalVar && compiler->info.compCallUnmanaged &&
theInterval->varNum == compiler->genReturnLocal)
{
mask &= ~(RBM_PINVOKE_TCB | RBM_PINVOKE_FRAME);
noway_assert(mask != RBM_NONE);
}
#endif // !_TARGET_AMD64_
newRP->registerAssignment = mask;
newRP->setMultiRegIdx(multiRegIdx);
newRP->setAllocateIfProfitable(false);
associateRefPosWithInterval(newRP);
DBEXEC(VERBOSE, newRP->dump());
return newRP;
}
//------------------------------------------------------------------------
// IsContainableMemoryOp: Checks whether this is a memory op that can be contained.
//
// Arguments:
// node - the node of interest.
//
// Return value:
// True if this will definitely be a memory reference that could be contained.
//
// Notes:
// This differs from the isMemoryOp() method on GenTree because it checks for
// the case of doNotEnregister local. This won't include locals that
// for some other reason do not become register candidates, nor those that get
// spilled.
// Also, because we usually call this before we redo dataflow, any new lclVars
// introduced after the last dataflow analysis will not yet be marked lvTracked,
// so we don't use that.
//
bool LinearScan::isContainableMemoryOp(GenTree* node)
{
if (node->isMemoryOp())
{
return true;
}
if (node->IsLocal())
{
if (!enregisterLocalVars)
{
return true;
}
LclVarDsc* varDsc = &compiler->lvaTable[node->AsLclVar()->gtLclNum];
return varDsc->lvDoNotEnregister;
}
return false;
}
//------------------------------------------------------------------------
// addRefsForPhysRegMask: Adds RefPositions of the given type for all the registers in 'mask'.
//
// Arguments:
// mask - the mask (set) of registers.
// currentLoc - the location at which they should be added
// refType - the type of refposition
// isLastUse - true IFF this is a last use of the register
//
void LinearScan::addRefsForPhysRegMask(regMaskTP mask, LsraLocation currentLoc, RefType refType, bool isLastUse)
{
for (regNumber reg = REG_FIRST; mask; reg = REG_NEXT(reg), mask >>= 1)
{
if (mask & 1)
{
// This assumes that these are all "special" RefTypes that
// don't need to be recorded on the tree (hence treeNode is nullptr)
RefPosition* pos = newRefPosition(reg, currentLoc, refType, nullptr,
genRegMask(reg)); // This MUST occupy the physical register (obviously)
if (isLastUse)
{
pos->lastUse = true;
}
}
}
}
//------------------------------------------------------------------------
// getKillSetForStoreInd: Determine the liveness kill set for a GT_STOREIND node.
// If the GT_STOREIND will generate a write barrier, determine the specific kill
// set required by the case-specific, platform-specific write barrier. If no
// write barrier is required, the kill set will be RBM_NONE.
//
// Arguments:
// tree - the GT_STOREIND node
//
// Return Value: a register mask of the registers killed
//
regMaskTP LinearScan::getKillSetForStoreInd(GenTreeStoreInd* tree)
{
assert(tree->OperIs(GT_STOREIND));
regMaskTP killMask = RBM_NONE;
GenTree* data = tree->Data();
GCInfo::WriteBarrierForm writeBarrierForm = compiler->codeGen->gcInfo.gcIsWriteBarrierCandidate(tree, data);
if (writeBarrierForm != GCInfo::WBF_NoBarrier)
{
if (compiler->codeGen->genUseOptimizedWriteBarriers(writeBarrierForm))
{
// We can't determine the exact helper to be used at this point, because it depends on
// the allocated register for the `data` operand. However, all the (x86) optimized
// helpers have the same kill set: EDX. And note that currently, only x86 can return
// `true` for genUseOptimizedWriteBarriers().
killMask = RBM_CALLEE_TRASH_NOGC;
}
else
{
// Figure out which helper we're going to use, and then get the kill set for that helper.
CorInfoHelpFunc helper =
compiler->codeGen->genWriteBarrierHelperForWriteBarrierForm(tree, writeBarrierForm);
killMask = compiler->compHelperCallKillSet(helper);
}
}
return killMask;
}
#ifdef FEATURE_HW_INTRINSICS
//------------------------------------------------------------------------
// getKillSetForHWIntrinsic: Determine the liveness kill set for a GT_STOREIND node.
// If the GT_STOREIND will generate a write barrier, determine the specific kill
// set required by the case-specific, platform-specific write barrier. If no
// write barrier is required, the kill set will be RBM_NONE.
//
// Arguments:
// tree - the GT_STOREIND node
//
// Return Value: a register mask of the registers killed
//
regMaskTP LinearScan::getKillSetForHWIntrinsic(GenTreeHWIntrinsic* node)
{
regMaskTP killMask = RBM_NONE;
#ifdef _TARGET_XARCH_
switch (node->gtHWIntrinsicId)
{
case NI_SSE2_MaskMove:
// maskmovdqu uses edi as the implicit address register.
// Although it is set as the srcCandidate on the address, if there is also a fixed
// assignment for the definition of the address, resolveConflictingDefAndUse() may
// change the register assignment on the def or use of a tree temp (SDSU) when there
// is a conflict, and the FixedRef on edi won't be sufficient to ensure that another
// Interval will not be allocated there.
// Issue #17674 tracks this.
killMask = RBM_EDI;
break;
default:
// Leave killMask as RBM_NONE
break;
}
#endif // _TARGET_XARCH_
return killMask;
}
#endif // FEATURE_HW_INTRINSICS
//------------------------------------------------------------------------
// getKillSetForNode: Return the registers killed by the given tree node.
//
// Arguments:
// compiler - the compiler context to use
// tree - the tree for which the kill set is needed.
//
// Return Value: a register mask of the registers killed
//
regMaskTP LinearScan::getKillSetForNode(GenTree* tree)
{
regMaskTP killMask = RBM_NONE;
switch (tree->OperGet())
{
#ifdef _TARGET_XARCH_
case GT_MUL:
// We use the 128-bit multiply when performing an overflow checking unsigned multiply
//
if (((tree->gtFlags & GTF_UNSIGNED) != 0) && tree->gtOverflowEx())
{
// Both RAX and RDX are killed by the operation
killMask = RBM_RAX | RBM_RDX;
}
break;
case GT_MULHI:
#if defined(_TARGET_X86_) && !defined(LEGACY_BACKEND)
case GT_MUL_LONG:
#endif
killMask = RBM_RAX | RBM_RDX;
break;
case GT_MOD:
case GT_DIV:
case GT_UMOD:
case GT_UDIV:
if (!varTypeIsFloating(tree->TypeGet()))
{
// Both RAX and RDX are killed by the operation
killMask = RBM_RAX | RBM_RDX;
}
break;
#endif // _TARGET_XARCH_
case GT_STORE_OBJ:
if (tree->OperIsCopyBlkOp())
{
assert(tree->AsObj()->gtGcPtrCount != 0);
killMask = compiler->compHelperCallKillSet(CORINFO_HELP_ASSIGN_BYREF);
break;
}
__fallthrough;
case GT_STORE_BLK:
case GT_STORE_DYN_BLK:
{
GenTreeBlk* blkNode = tree->AsBlk();
bool isCopyBlk = varTypeIsStruct(blkNode->Data());
switch (blkNode->gtBlkOpKind)
{
case GenTreeBlk::BlkOpKindHelper:
if (isCopyBlk)
{
killMask = compiler->compHelperCallKillSet(CORINFO_HELP_MEMCPY);
}
else
{
killMask = compiler->compHelperCallKillSet(CORINFO_HELP_MEMSET);
}
break;
#ifdef _TARGET_XARCH_
case GenTreeBlk::BlkOpKindRepInstr:
if (isCopyBlk)
{
// rep movs kills RCX, RDI and RSI
killMask = RBM_RCX | RBM_RDI | RBM_RSI;
}
else
{
// rep stos kills RCX and RDI.
// (Note that the Data() node, if not constant, will be assigned to
// RCX, but it's find that this kills it, as the value is not available
// after this node in any case.)
killMask = RBM_RDI | RBM_RCX;
}
break;
#else
case GenTreeBlk::BlkOpKindRepInstr:
#endif
case GenTreeBlk::BlkOpKindUnroll:
case GenTreeBlk::BlkOpKindInvalid:
// for these 'gtBlkOpKind' kinds, we leave 'killMask' = RBM_NONE
break;
}
}
break;
case GT_RETURNTRAP:
killMask = compiler->compHelperCallKillSet(CORINFO_HELP_STOP_FOR_GC);
break;
case GT_CALL:
#ifdef _TARGET_X86_
if (compiler->compFloatingPointUsed)
{
if (tree->TypeGet() == TYP_DOUBLE)
{
needDoubleTmpForFPCall = true;
}
else if (tree->TypeGet() == TYP_FLOAT)
{
needFloatTmpForFPCall = true;
}
}
#endif // _TARGET_X86_
#if defined(_TARGET_X86_) || defined(_TARGET_ARM_)
if (tree->IsHelperCall())
{
GenTreeCall* call = tree->AsCall();
CorInfoHelpFunc helpFunc = compiler->eeGetHelperNum(call->gtCallMethHnd);
killMask = compiler->compHelperCallKillSet(helpFunc);
}
else
#endif // defined(_TARGET_X86_) || defined(_TARGET_ARM_)
{
// if there is no FP used, we can ignore the FP kills
if (compiler->compFloatingPointUsed)
{
killMask = RBM_CALLEE_TRASH;
}
else
{
killMask = RBM_INT_CALLEE_TRASH;
}
#ifdef _TARGET_ARM_
if (tree->AsCall()->IsVirtualStub())
{
killMask |= compiler->virtualStubParamInfo->GetRegMask();
}
#else // !_TARGET_ARM_
// Verify that the special virtual stub call registers are in the kill mask.
// We don't just add them unconditionally to the killMask because for most architectures
// they are already in the RBM_CALLEE_TRASH set,
// and we don't want to introduce extra checks and calls in this hot function.
assert(!tree->AsCall()->IsVirtualStub() || ((killMask & compiler->virtualStubParamInfo->GetRegMask()) ==
compiler->virtualStubParamInfo->GetRegMask()));
#endif
}
break;
case GT_STOREIND:
killMask = getKillSetForStoreInd(tree->AsStoreInd());
break;
#if defined(PROFILING_SUPPORTED)
// If this method requires profiler ELT hook then mark these nodes as killing
// callee trash registers (excluding RAX and XMM0). The reason for this is that
// profiler callback would trash these registers. See vm\amd64\asmhelpers.asm for
// more details.
case GT_RETURN:
if (compiler->compIsProfilerHookNeeded())
{
killMask = compiler->compHelperCallKillSet(CORINFO_HELP_PROF_FCN_LEAVE);
}
break;
case GT_PROF_HOOK:
if (compiler->compIsProfilerHookNeeded())
{
killMask = compiler->compHelperCallKillSet(CORINFO_HELP_PROF_FCN_TAILCALL);
}
break;
#endif // PROFILING_SUPPORTED
#ifdef FEATURE_HW_INTRINSICS
case GT_HWIntrinsic:
killMask = getKillSetForHWIntrinsic(tree->AsHWIntrinsic());
break;
#endif // FEATURE_HW_INTRINSICS
default:
// for all other 'tree->OperGet()' kinds, leave 'killMask' = RBM_NONE
break;
}
return killMask;
}
//------------------------------------------------------------------------
// buildKillPositionsForNode:
// Given some tree node add refpositions for all the registers this node kills
//
// Arguments:
// tree - the tree for which kill positions should be generated
// currentLoc - the location at which the kills should be added
//
// Return Value:
// true - kills were inserted
// false - no kills were inserted
//
// Notes:
// The return value is needed because if we have any kills, we need to make sure that
// all defs are located AFTER the kills. On the other hand, if there aren't kills,
// the multiple defs for a regPair are in different locations.
// If we generate any kills, we will mark all currentLiveVars as being preferenced
// to avoid the killed registers. This is somewhat conservative.
bool LinearScan::buildKillPositionsForNode(GenTree* tree, LsraLocation currentLoc)
{
regMaskTP killMask = getKillSetForNode(tree);
bool isCallKill = ((killMask == RBM_INT_CALLEE_TRASH) || (killMask == RBM_CALLEE_TRASH));
if (killMask != RBM_NONE)
{
// The killMask identifies a set of registers that will be used during codegen.
// Mark these as modified here, so when we do final frame layout, we'll know about
// all these registers. This is especially important if killMask contains
// callee-saved registers, which affect the frame size since we need to save/restore them.
// In the case where we have a copyBlk with GC pointers, can need to call the
// CORINFO_HELP_ASSIGN_BYREF helper, which kills callee-saved RSI and RDI, if
// LSRA doesn't assign RSI/RDI, they wouldn't get marked as modified until codegen,
// which is too late.
compiler->codeGen->regSet.rsSetRegsModified(killMask DEBUGARG(true));
addRefsForPhysRegMask(killMask, currentLoc, RefTypeKill, true);
// TODO-CQ: It appears to be valuable for both fp and int registers to avoid killing the callee
// save regs on infrequently exectued paths. However, it results in a large number of asmDiffs,
// many of which appear to be regressions (because there is more spill on the infrequently path),
// but are not really because the frequent path becomes smaller. Validating these diffs will need
// to be done before making this change.
// if (!blockSequence[curBBSeqNum]->isRunRarely())
if (enregisterLocalVars)
{
VarSetOps::Iter iter(compiler, currentLiveVars);
unsigned varIndex = 0;
while (iter.NextElem(&varIndex))
{
unsigned varNum = compiler->lvaTrackedToVarNum[varIndex];
LclVarDsc* varDsc = compiler->lvaTable + varNum;
#if FEATURE_PARTIAL_SIMD_CALLEE_SAVE
if (varTypeNeedsPartialCalleeSave(varDsc->lvType))
{
if (!VarSetOps::IsMember(compiler, largeVectorCalleeSaveCandidateVars, varIndex))
{
continue;
}
}
else
#endif // FEATURE_PARTIAL_SIMD_CALLEE_SAVE
if (varTypeIsFloating(varDsc) &&
!VarSetOps::IsMember(compiler, fpCalleeSaveCandidateVars, varIndex))
{
continue;
}
Interval* interval = getIntervalForLocalVar(varIndex);
if (isCallKill)
{
interval->preferCalleeSave = true;
}
regMaskTP newPreferences = allRegs(interval->registerType) & (~killMask);
if (newPreferences != RBM_NONE)
{
interval->updateRegisterPreferences(newPreferences);
}
else
{
// If there are no callee-saved registers, the call could kill all the registers.
// This is a valid state, so in that case assert should not trigger. The RA will spill in order to
// free a register later.
assert(compiler->opts.compDbgEnC || (calleeSaveRegs(varDsc->lvType)) == RBM_NONE);
}
}
}
if (compiler->killGCRefs(tree))
{
RefPosition* pos = newRefPosition((Interval*)nullptr, currentLoc, RefTypeKillGCRefs, tree,
(allRegs(TYP_REF) & ~RBM_ARG_REGS));
}
return true;
}
return false;
}
//----------------------------------------------------------------------------
// defineNewInternalTemp: Defines a ref position for an internal temp.
//
// Arguments:
// tree - Gentree node requiring an internal register
// regType - Register type
// currentLoc - Location of the temp Def position
// regMask - register mask of candidates for temp
//
RefPosition* LinearScan::defineNewInternalTemp(GenTree* tree, RegisterType regType, regMaskTP regMask)
{
Interval* current = newInterval(regType);
current->isInternal = true;
return newRefPosition(current, currentLoc, RefTypeDef, tree, regMask, 0);
}
//------------------------------------------------------------------------
// buildInternalRegisterDefsForNode - build Def positions for internal
// registers required for tree node.
//
// Arguments:
// tree - Gentree node that needs internal registers
// temps - in-out array which is populated with ref positions
// created for Def of internal registers
//
// Returns:
// The total number of Def positions created for internal registers of tree no.
int LinearScan::buildInternalRegisterDefsForNode(GenTree* tree, TreeNodeInfo* info, RefPosition* temps[])
{
int count;
int internalIntCount = info->internalIntCount;
regMaskTP internalCands = info->getInternalCandidates(this);
// If the number of internal integer registers required is the same as the number of candidate integer registers in
// the candidate set, then they must be handled as fixed registers.
// (E.g. for the integer registers that floating point arguments must be copied into for a varargs call.)
bool fixedRegs = false;
regMaskTP internalIntCandidates = (internalCands & allRegs(TYP_INT));
if (((int)genCountBits(internalIntCandidates)) == internalIntCount)
{
fixedRegs = true;
}
for (count = 0; count < internalIntCount; count++)
{
regMaskTP internalIntCands = (internalCands & allRegs(TYP_INT));
if (fixedRegs)
{
internalIntCands = genFindLowestBit(internalIntCands);
internalCands &= ~internalIntCands;
}
temps[count] = defineNewInternalTemp(tree, IntRegisterType, internalIntCands);
}
int internalFloatCount = info->internalFloatCount;
for (int i = 0; i < internalFloatCount; i++)
{
regMaskTP internalFPCands = (internalCands & internalFloatRegCandidates());
temps[count++] = defineNewInternalTemp(tree, FloatRegisterType, internalFPCands);
}
assert(count < MaxInternalRegisters);
assert(count == (internalIntCount + internalFloatCount));
return count;
}
//------------------------------------------------------------------------
// buildInternalRegisterUsesForNode - adds Use positions for internal
// registers required for tree node.
//
// Arguments:
// tree - Gentree node that needs internal registers
// defs - int array containing Def positions of internal
// registers.
// total - Total number of Def positions in 'defs' array.
//
// Returns:
// Void.
void LinearScan::buildInternalRegisterUsesForNode(GenTree* tree, TreeNodeInfo* info, RefPosition* defs[], int total)
{
assert(total < MaxInternalRegisters);
// defs[] has been populated by buildInternalRegisterDefsForNode
// now just add uses to the defs previously added.
for (int i = 0; i < total; i++)
{
RefPosition* prevRefPosition = defs[i];
assert(prevRefPosition != nullptr);
regMaskTP mask = prevRefPosition->registerAssignment;
if (prevRefPosition->isPhysRegRef)
{
newRefPosition(defs[i]->getReg()->regNum, currentLoc, RefTypeUse, tree, mask);
}
else
{
RefPosition* newest = newRefPosition(defs[i]->getInterval(), currentLoc, RefTypeUse, tree, mask, 0);
if (info->isInternalRegDelayFree)
{
newest->delayRegFree = true;
}
}
}
}
#if FEATURE_PARTIAL_SIMD_CALLEE_SAVE
//------------------------------------------------------------------------
// buildUpperVectorSaveRefPositions - Create special RefPositions for saving
// the upper half of a set of large vector.
//
// Arguments:
// tree - The current node being handled
// currentLoc - The location of the current node
//
// Return Value: Returns the set of lclVars that are killed by this node, and therefore
// required RefTypeUpperVectorSaveDef RefPositions.
//
// Notes: The returned set is used by buildUpperVectorRestoreRefPositions.
//
VARSET_VALRET_TP
LinearScan::buildUpperVectorSaveRefPositions(GenTree* tree, LsraLocation currentLoc)
{
assert(enregisterLocalVars);
VARSET_TP liveLargeVectors(VarSetOps::MakeEmpty(compiler));
regMaskTP fpCalleeKillSet = RBM_NONE;
if (!VarSetOps::IsEmpty(compiler, largeVectorVars))
{
// We actually need to find any calls that kill the upper-half of the callee-save vector registers.
// But we will use as a proxy any node that kills floating point registers.
// (Note that some calls are masquerading as other nodes at this point so we can't just check for calls.)
fpCalleeKillSet = getKillSetForNode(tree);
if ((fpCalleeKillSet & RBM_FLT_CALLEE_TRASH) != RBM_NONE)
{
VarSetOps::AssignNoCopy(compiler, liveLargeVectors,
VarSetOps::Intersection(compiler, currentLiveVars, largeVectorVars));
VarSetOps::Iter iter(compiler, liveLargeVectors);
unsigned varIndex = 0;
while (iter.NextElem(&varIndex))
{
Interval* varInterval = getIntervalForLocalVar(varIndex);
Interval* tempInterval = newInterval(varInterval->registerType);
tempInterval->isInternal = true;
RefPosition* pos =
newRefPosition(tempInterval, currentLoc, RefTypeUpperVectorSaveDef, tree, RBM_FLT_CALLEE_SAVED);
// We are going to save the existing relatedInterval of varInterval on tempInterval, so that we can set
// the tempInterval as the relatedInterval of varInterval, so that we can build the corresponding
// RefTypeUpperVectorSaveUse RefPosition. We will then restore the relatedInterval onto varInterval,
// and set varInterval as the relatedInterval of tempInterval.
tempInterval->relatedInterval = varInterval->relatedInterval;
varInterval->relatedInterval = tempInterval;
}
}
}
return liveLargeVectors;
}
// buildUpperVectorRestoreRefPositions - Create special RefPositions for restoring
// the upper half of a set of large vectors.
//
// Arguments:
// tree - The current node being handled
// currentLoc - The location of the current node
// liveLargeVectors - The set of lclVars needing restores (returned by buildUpperVectorSaveRefPositions)
//
void LinearScan::buildUpperVectorRestoreRefPositions(GenTree* tree,
LsraLocation currentLoc,
VARSET_VALARG_TP liveLargeVectors)
{
assert(enregisterLocalVars);
if (!VarSetOps::IsEmpty(compiler, liveLargeVectors))
{
VarSetOps::Iter iter(compiler, liveLargeVectors);
unsigned varIndex = 0;
while (iter.NextElem(&varIndex))
{
Interval* varInterval = getIntervalForLocalVar(varIndex);
Interval* tempInterval = varInterval->relatedInterval;
assert(tempInterval->isInternal == true);
RefPosition* pos =
newRefPosition(tempInterval, currentLoc, RefTypeUpperVectorSaveUse, tree, RBM_FLT_CALLEE_SAVED);
// Restore the relatedInterval onto varInterval, and set varInterval as the relatedInterval
// of tempInterval.
varInterval->relatedInterval = tempInterval->relatedInterval;
tempInterval->relatedInterval = varInterval;
}
}
}
#endif // FEATURE_PARTIAL_SIMD_CALLEE_SAVE
#ifdef DEBUG
//------------------------------------------------------------------------
// ComputeOperandDstCount: computes the number of registers defined by a
// node.
//
// For most nodes, this is simple:
// - Nodes that do not produce values (e.g. stores and other void-typed
// nodes) and nodes that immediately use the registers they define
// produce no registers
// - Nodes that are marked as defining N registers define N registers.
//
// For contained nodes, however, things are more complicated: for purposes
// of bookkeeping, a contained node is treated as producing the transitive
// closure of the registers produced by its sources.
//
// Arguments:
// operand - The operand for which to compute a register count.
//
// Returns:
// The number of registers defined by `operand`.
//
// static
int LinearScan::ComputeOperandDstCount(GenTree* operand)
{
// GT_ARGPLACE is the only non-LIR node that is currently in the trees at this stage, though
// note that it is not in the linear order. It seems best to check for !IsLIR() rather than
// GT_ARGPLACE directly, since it's that characteristic that makes it irrelevant for this method.
if (!operand->IsLIR())
{
return 0;
}
if (operand->isContained())
{
int dstCount = 0;
for (GenTree* op : operand->Operands())
{
dstCount += ComputeOperandDstCount(op);
}
return dstCount;
}
if (operand->IsUnusedValue())
{
// Operands that define an unused value do not produce any registers.
return 0;
}
if (operand->IsValue())
{
// Operands that are values and are not contained consume all of their operands
// and produce one or more registers.
return operand->GetRegisterDstCount();
}
else
{
// This must be one of the operand types that are neither contained nor produce a value.
// Stores and void-typed operands may be encountered when processing call nodes, which contain
// pointers to argument setup stores.
assert(operand->OperIsStore() || operand->OperIsBlkOp() || operand->OperIsPutArgStk() ||
operand->OperIsCompare() || operand->OperIs(GT_CMP) || operand->IsSIMDEqualityOrInequality() ||
operand->TypeGet() == TYP_VOID);
return 0;
}
}
//------------------------------------------------------------------------
// ComputeAvailableSrcCount: computes the number of registers available as
// sources for a node.
//
// This is simply the sum of the number of registers produced by each
// operand to the node.
//
// Arguments:
// node - The node for which to compute a source count.
//
// Return Value:
// The number of registers available as sources for `node`.
//
// static
int LinearScan::ComputeAvailableSrcCount(GenTree* node)
{
int numSources = 0;
for (GenTree* operand : node->Operands())
{
numSources += ComputeOperandDstCount(operand);
}
return numSources;
}
#endif // DEBUG
//------------------------------------------------------------------------
// buildRefPositionsForNode: The main entry point for building the RefPositions
// and "tree temp" Intervals for a given node.
//
// Arguments:
// tree - The node for which we are building RefPositions
// block - The BasicBlock in which the node resides
// currentLoc - The LsraLocation of the given node
//
void LinearScan::buildRefPositionsForNode(GenTree* tree, BasicBlock* block, LsraLocation currentLoc)
{
#ifdef _TARGET_ARM_
assert(!isRegPairType(tree->TypeGet()));
#endif // _TARGET_ARM_
// The LIR traversal doesn't visit GT_LIST or GT_ARGPLACE nodes.
// GT_CLS_VAR nodes should have been eliminated by rationalizer.
assert(tree->OperGet() != GT_ARGPLACE);
assert(tree->OperGet() != GT_LIST);
assert(tree->OperGet() != GT_CLS_VAR);
// The LIR traversal visits only the first node in a GT_FIELD_LIST.
assert((tree->OperGet() != GT_FIELD_LIST) || tree->AsFieldList()->IsFieldListHead());
// The set of internal temporary registers used by this node are stored in the
// gtRsvdRegs register mask. Clear it out.
tree->gtRsvdRegs = RBM_NONE;
#ifdef DEBUG
if (VERBOSE)
{
dumpDefList();
compiler->gtDispTree(tree, nullptr, nullptr, true);
}
#endif // DEBUG
// If the node produces a value that will be consumed by a parent node, its TreeNodeInfo will
// be allocated in the LocationInfoListNode. Otherwise, we'll just use a local value that will
// be thrown away when we're done.
LocationInfoListNode* locationInfo = nullptr;
TreeNodeInfo tempInfo;
TreeNodeInfo* info = nullptr;
int consume = 0;
int produce = 0;
if (!tree->isContained())
{
if (tree->IsValue())
{
locationInfo = listNodePool.GetNode(currentLoc, nullptr, tree);
currentNodeInfo = &locationInfo->info;
}
else
{
currentNodeInfo = &tempInfo;
}
info = currentNodeInfo;
info->Initialize(this, tree);
BuildNode(tree);
assert(info->IsValid(this));
consume = info->srcCount;
produce = info->dstCount;
#ifdef DEBUG
if (VERBOSE)
{
printf(" +");
info->dump(this);
tree->dumpLIRFlags();
printf("\n");
}
#endif // DEBUG
}
#ifdef DEBUG
if (VERBOSE)
{
if (tree->isContained())
{
JITDUMP("Contained\n");
}
else if (tree->OperIs(GT_LCL_VAR, GT_LCL_FLD) && tree->IsUnusedValue())
{
JITDUMP("Unused\n");
}
else
{
JITDUMP(" consume=%d produce=%d\n", consume, produce);
}
}
#endif // DEBUG
assert(((consume == 0) && (produce == 0)) || (ComputeAvailableSrcCount(tree) == consume));
if (tree->OperIs(GT_LCL_VAR, GT_LCL_FLD))
{
LclVarDsc* const varDsc = &compiler->lvaTable[tree->AsLclVarCommon()->gtLclNum];
if (isCandidateVar(varDsc))
{
assert(consume == 0);
// We handle tracked variables differently from non-tracked ones. If it is tracked,
// we simply add a use or def of the tracked variable. Otherwise, for a use we need
// to actually add the appropriate references for loading or storing the variable.
//
// It won't actually get used or defined until the appropriate ancestor tree node
// is processed, unless this is marked "isLocalDefUse" because it is a stack-based argument
// to a call
assert(varDsc->lvTracked);
unsigned varIndex = varDsc->lvVarIndex;
if (!tree->IsUnusedValue() && !tree->isContained())
{
assert(produce != 0);
locationInfo->interval = getIntervalForLocalVar(varIndex);
defList.Append(locationInfo);
}
return;
}
}
if (tree->isContained())
{
return;
}
// Handle the case of local variable assignment
Interval* varDefInterval = nullptr;
GenTree* defNode = tree;
// noAdd means the node creates a def but for purposes of map
// management do not add it because data is not flowing up the
// tree
bool noAdd = info->isLocalDefUse;
RefPosition* prevPos = nullptr;
bool isSpecialPutArg = false;
assert(!tree->OperIsAssignment());
if (tree->OperIsLocalStore())
{
GenTreeLclVarCommon* const store = tree->AsLclVarCommon();
assert((consume > 1) || (regType(store->gtOp1->TypeGet()) == regType(store->TypeGet())));
LclVarDsc* varDsc = &compiler->lvaTable[store->gtLclNum];
if (isCandidateVar(varDsc))
{
// We always push the tracked lclVar intervals
assert(varDsc->lvTracked);
unsigned varIndex = varDsc->lvVarIndex;
varDefInterval = getIntervalForLocalVar(varIndex);
assert((store->gtFlags & GTF_VAR_DEF) != 0);
defNode = tree;
if (produce == 0)
{
produce = 1;
noAdd = true;
}
assert(consume <= MAX_RET_REG_COUNT);
if (consume == 1)
{
// Get the location info for the register defined by the first operand.
LocationInfoListNode& operandInfo = *(useList.Begin());
assert(operandInfo.treeNode == tree->gtGetOp1());
Interval* srcInterval = operandInfo.interval;
if (srcInterval->relatedInterval == nullptr)
{
// Preference the source to the dest, unless this is a non-last-use localVar.
// Note that the last-use info is not correct, but it is a better approximation than preferencing
// the source to the dest, if the source's lifetime extends beyond the dest.
if (!srcInterval->isLocalVar || (operandInfo.treeNode->gtFlags & GTF_VAR_DEATH) != 0)
{
srcInterval->assignRelatedInterval(varDefInterval);
}
}
else if (!srcInterval->isLocalVar)
{
// Preference the source to dest, if src is not a local var.
srcInterval->assignRelatedInterval(varDefInterval);
}
}
}
else if (store->gtOp1->OperIs(GT_BITCAST))
{
store->gtType = store->gtOp1->gtType = store->gtOp1->AsUnOp()->gtOp1->TypeGet();
// Get the location info for the register defined by the first operand.
LocationInfoListNode& operandInfo = *(useList.Begin());
assert(operandInfo.treeNode == tree->gtGetOp1());
Interval* srcInterval = operandInfo.interval;
srcInterval->registerType = regType(store->TypeGet());
RefPosition* srcDefPosition = srcInterval->firstRefPosition;
assert(srcDefPosition != nullptr);
assert(srcDefPosition->refType == RefTypeDef);
assert(srcDefPosition->treeNode == store->gtOp1);
srcDefPosition->registerAssignment = allRegs(store->TypeGet());
operandInfo.info.setSrcCandidates(this, allRegs(store->TypeGet()));
}
}
else if (noAdd && produce == 0)
{
// Dead nodes may remain after tree rationalization, decomposition or lowering.
// They should be marked as UnusedValue.
// TODO-Cleanup: Identify and remove these dead nodes prior to register allocation.
assert(!noAdd || (produce != 0));
}
Interval* prefSrcInterval = nullptr;
// If this is a binary operator that will be encoded with 2 operand fields
// (i.e. the target is read-modify-write), preference the dst to op1.
bool hasDelayFreeSrc = info->hasDelayFreeSrc;
#if defined(DEBUG) && defined(_TARGET_X86_)
// On x86, `LSRA_LIMIT_CALLER` is too restrictive to allow the use of special put args: this stress mode
// leaves only three registers allocatable--eax, ecx, and edx--of which the latter two are also used for the
// first two integral arguments to a call. This can leave us with too few registers to succesfully allocate in
// situations like the following:
//
// t1026 = lclVar ref V52 tmp35 u:3 REG NA <l:$3a1, c:$98d>
//
// /--* t1026 ref
// t1352 = * putarg_reg ref REG NA
//
// t342 = lclVar int V14 loc6 u:4 REG NA $50c
//
// t343 = const int 1 REG NA $41
//
// /--* t342 int
// +--* t343 int
// t344 = * + int REG NA $495
//
// t345 = lclVar int V04 arg4 u:2 REG NA $100
//
// /--* t344 int
// +--* t345 int
// t346 = * % int REG NA $496
//
// /--* t346 int
// t1353 = * putarg_reg int REG NA
//
// t1354 = lclVar ref V52 tmp35 (last use) REG NA
//
// /--* t1354 ref
// t1355 = * lea(b+0) byref REG NA
//
// Here, the first `putarg_reg` would normally be considered a special put arg, which would remove `ecx` from the
// set of allocatable registers, leaving only `eax` and `edx`. The allocator will then fail to allocate a register
// for the def of `t345` if arg4 is not a register candidate: the corresponding ref position will be constrained to
// { `ecx`, `ebx`, `esi`, `edi` }, which `LSRA_LIMIT_CALLER` will further constrain to `ecx`, which will not be
// available due to the special put arg.
const bool supportsSpecialPutArg = getStressLimitRegs() != LSRA_LIMIT_CALLER;
#else
const bool supportsSpecialPutArg = true;
#endif
if (supportsSpecialPutArg)
{
if ((tree->OperGet() == GT_PUTARG_REG) && isCandidateLocalRef(tree->gtGetOp1()) &&
(tree->gtGetOp1()->gtFlags & GTF_VAR_DEATH) == 0)
{
// This is the case for a "pass-through" copy of a lclVar. In the case where it is a non-last-use,
// we don't want the def of the copy to kill the lclVar register, if it is assigned the same register
// (which is actually what we hope will happen).
JITDUMP("Setting putarg_reg as a pass-through of a non-last use lclVar\n");
// Get the register information for the first operand of the node.
LocationInfoListNode* operandDef = useList.Begin();
assert(operandDef->treeNode == tree->gtGetOp1());
// Preference the destination to the interval of the first register defined by the first operand.
Interval* srcInterval = operandDef->interval;
assert(srcInterval->isLocalVar);
prefSrcInterval = srcInterval;
isSpecialPutArg = true;
INDEBUG(specialPutArgCount++);
}
else if (tree->IsCall())
{
INDEBUG(specialPutArgCount = 0);
}
}
RefPosition* internalRefs[MaxInternalRegisters];
#ifdef DEBUG
// If we are constraining the registers for allocation, we will modify all the RefPositions
// we've built for this node after we've created them. In order to do that, we'll remember
// the last RefPosition prior to those created for this node.
RefPositionIterator refPositionMark = refPositions.backPosition();
#endif // DEBUG
// Make intervals for all the 'internal' register requirements for this node,
// where internal means additional registers required temporarily.
// Create a RefTypeDef RefPosition for each such interval.
int internalCount = buildInternalRegisterDefsForNode(tree, info, internalRefs);
// Make use RefPositions for all used values.
int consumed = 0;
for (LocationInfoListNode *listNode = useList.Begin(), *end = useList.End(); listNode != end;
listNode = listNode->Next())
{
LocationInfo& locInfo = *static_cast<LocationInfo*>(listNode);
// For tree temps, a use is always a last use and the end of the range;
// this is set by default in newRefPosition
GenTree* const useNode = locInfo.treeNode;
assert(useNode != nullptr);
Interval* srcInterval = locInfo.interval;
TreeNodeInfo& useNodeInfo = locInfo.info;
if (useNodeInfo.isTgtPref)
{
prefSrcInterval = srcInterval;
}
const bool delayRegFree = (hasDelayFreeSrc && useNodeInfo.isDelayFree);
regMaskTP candidates = useNodeInfo.getSrcCandidates(this);
#ifdef _TARGET_ARM_
regMaskTP allCandidates = candidates;
if (useNode->OperIsPutArgSplit() || useNode->OperIsMultiRegOp())
{
// get i-th candidate, set bits in useCandidates must be in sequential order.
candidates = genFindLowestReg(allCandidates);
allCandidates &= ~candidates;
}
#endif // _TARGET_ARM_
assert((candidates & allRegs(srcInterval->registerType)) != 0);
GenTree* refPosNode;
if (srcInterval->isLocalVar)
{
// We have only approximate last-use information at this point. This is because the
// execution order doesn't actually reflect the true order in which the localVars
// are referenced - but the order of the RefPositions will, so we recompute it after
// RefPositions are built.
// Use the old value for setting currentLiveVars - note that we do this with the
// not-quite-correct setting of lastUse. However, this is OK because
// 1) this is only for preferencing, which doesn't require strict correctness, and
// for determing which largeVectors require having their upper-half saved & restored.
// (Issue #17481 tracks the issue that this system results in excessive spills and
// should be changed.)
// 2) the cases where these out-of-order uses occur should not overlap a kill (they are
// only known to occur within a single expression).
if ((useNode->gtFlags & GTF_VAR_DEATH) != 0)
{
VarSetOps::RemoveElemD(compiler, currentLiveVars, srcInterval->getVarIndex(compiler));
}
refPosNode = useNode;
}
else
{
// For non-localVar uses we record nothing, as nothing needs to be written back to the tree.
refPosNode = nullptr;
}
RefPosition* pos = newRefPosition(srcInterval, currentLoc, RefTypeUse, refPosNode, candidates, 0);
if (delayRegFree)
{
pos->delayRegFree = true;
}
if (useNode->IsRegOptional())
{
pos->setAllocateIfProfitable(true);
}
consumed++;
// Create additional use RefPositions for multi-reg nodes.
for (int idx = 1; idx < locInfo.info.dstCount; idx++)
{
noway_assert(srcInterval->relatedInterval != nullptr);
srcInterval = srcInterval->relatedInterval;
#ifdef _TARGET_ARM_
if (useNode->OperIsPutArgSplit() ||
(compiler->opts.compUseSoftFP && (useNode->OperIsPutArgReg() || useNode->OperGet() == GT_BITCAST)))
{
// get first candidate, set bits in useCandidates must be in sequential order.
candidates = genFindLowestReg(allCandidates);
allCandidates &= ~candidates;
}
#endif // _TARGET_ARM_
RefPosition* pos = newRefPosition(srcInterval, currentLoc, RefTypeUse, refPosNode, candidates, idx);
consumed++;
}
}
assert(consumed == consume);
if (consume != 0)
{
listNodePool.ReturnNodes(useList);
}
buildInternalRegisterUsesForNode(tree, info, internalRefs, internalCount);
RegisterType registerType = getDefType(tree);
regMaskTP candidates = info->getDstCandidates(this);
regMaskTP useCandidates = info->getSrcCandidates(this);
#ifdef DEBUG
if (VERBOSE && produce)
{
printf("Def candidates ");
dumpRegMask(candidates);
printf(", Use candidates ");
dumpRegMask(useCandidates);
printf("\n");
}
#endif // DEBUG
#if defined(_TARGET_AMD64_)
// Multi-reg call node is the only node that could produce multi-reg value
assert(produce <= 1 || (tree->IsMultiRegCall() && produce == MAX_RET_REG_COUNT));
#endif // _TARGET_xxx_
// Add kill positions before adding def positions
buildKillPositionsForNode(tree, currentLoc + 1);
#if FEATURE_PARTIAL_SIMD_CALLEE_SAVE
VARSET_TP liveLargeVectors(VarSetOps::UninitVal());
if (enregisterLocalVars && (RBM_FLT_CALLEE_SAVED != RBM_NONE))
{
// Build RefPositions for saving any live large vectors.
// This must be done after the kills, so that we know which large vectors are still live.
VarSetOps::AssignNoCopy(compiler, liveLargeVectors, buildUpperVectorSaveRefPositions(tree, currentLoc + 1));
}
#endif // FEATURE_PARTIAL_SIMD_CALLEE_SAVE
ReturnTypeDesc* retTypeDesc = nullptr;
bool isMultiRegCall = tree->IsMultiRegCall();
if (isMultiRegCall)
{
retTypeDesc = tree->AsCall()->GetReturnTypeDesc();
assert((int)genCountBits(candidates) == produce);
assert(candidates == retTypeDesc->GetABIReturnRegs());
}
// push defs
LocationInfoList locationInfoList;
LsraLocation defLocation = currentLoc + 1;
Interval* interval = varDefInterval;
// For nodes that define multiple registers, subsequent intervals will be linked using the 'relatedInterval' field.
// Keep track of the previous interval allocated, for that purpose.
Interval* prevInterval = nullptr;
for (int i = 0; i < produce; i++)
{
regMaskTP currCandidates = candidates;
// In case of multi-reg call node, registerType is given by
// the type of ith position return register.
if (isMultiRegCall)
{
registerType = retTypeDesc->GetReturnRegType((unsigned)i);
currCandidates = genRegMask(retTypeDesc->GetABIReturnReg(i));
useCandidates = allRegs(registerType);
}
#ifdef _TARGET_ARM_
// If oper is GT_PUTARG_REG, set bits in useCandidates must be in sequential order.
if (tree->OperIsPutArgSplit() || tree->OperIsMultiRegOp())
{
// get i-th candidate
currCandidates = genFindLowestReg(candidates);
candidates &= ~currCandidates;
}
#endif // _TARGET_ARM_
if (interval == nullptr)
{
// Make a new interval
interval = newInterval(registerType);
if (hasDelayFreeSrc || info->isInternalRegDelayFree)
{
interval->hasInterferingUses = true;
}
else if (tree->OperIsConst())
{
assert(!tree->IsReuseRegVal());
interval->isConstant = true;
}
if ((currCandidates & useCandidates) != RBM_NONE)
{
interval->updateRegisterPreferences(currCandidates & useCandidates);
}
if (isSpecialPutArg)
{
interval->isSpecialPutArg = true;
}
}
else
{
assert(registerTypesEquivalent(interval->registerType, registerType));
assert(interval->isLocalVar);
if ((tree->gtFlags & GTF_VAR_DEATH) == 0)
{
VarSetOps::AddElemD(compiler, currentLiveVars, interval->getVarIndex(compiler));
}
}
if (prefSrcInterval != nullptr)
{
interval->assignRelatedIntervalIfUnassigned(prefSrcInterval);
}
// for assignments, we want to create a refposition for the def
// but not push it
if (!noAdd)
{
if (i == 0)
{
locationInfo->interval = interval;
prevInterval = interval;
defList.Append(locationInfo);
}
else
{
// This is the 2nd or subsequent register defined by a multi-reg node.
// Connect them using 'relatedInterval'.
noway_assert(prevInterval != nullptr);
prevInterval->relatedInterval = interval;
prevInterval = interval;
prevInterval->isMultiReg = true;
interval->isMultiReg = true;
}
}
RefPosition* pos = newRefPosition(interval, defLocation, RefTypeDef, defNode, currCandidates, (unsigned)i);
if (info->isLocalDefUse)
{
// This must be an unused value, OR it is a special node for which we allocate
// a target register even though it produces no value.
assert(defNode->IsUnusedValue() || (defNode->gtOper == GT_LOCKADD));
pos->isLocalDefUse = true;
pos->lastUse = true;
}
interval->updateRegisterPreferences(currCandidates);
interval->updateRegisterPreferences(useCandidates);
interval = nullptr;
}
#if FEATURE_PARTIAL_SIMD_CALLEE_SAVE
// SaveDef position must be at the same location as Def position of call node.
if (enregisterLocalVars)
{
buildUpperVectorRestoreRefPositions(tree, defLocation, liveLargeVectors);
}
#endif // FEATURE_PARTIAL_SIMD_CALLEE_SAVE
#ifdef DEBUG
// If we are constraining registers, modify all the RefPositions we've just built to specify the
// minimum reg count required.
if ((getStressLimitRegs() != LSRA_LIMIT_NONE) || (getSelectionHeuristics() != LSRA_SELECT_DEFAULT))
{
// The number of registers required for a tree node is the sum of
// consume + produce + internalCount + specialPutArgCount.
// This is the minimum set of registers that needs to be ensured in the candidate set of ref positions created.
//
unsigned minRegCount =
consume + produce + info->internalIntCount + info->internalFloatCount + specialPutArgCount;
for (refPositionMark++; refPositionMark != refPositions.end(); refPositionMark++)
{
RefPosition* newRefPosition = &(*refPositionMark);
unsigned minRegCountForRef = minRegCount;
if (RefTypeIsUse(newRefPosition->refType) && newRefPosition->delayRegFree)
{
// If delayRegFree, then Use will interfere with the destination of the consuming node.
// Therefore, we also need add the kill set of the consuming node to minRegCount.
//
// For example consider the following IR on x86, where v01 and v02
// are method args coming in ecx and edx respectively.
// GT_DIV(v01, v02)
//
// For GT_DIV, the minRegCount will be 3 without adding kill set of GT_DIV node.
//
// Assume further JitStressRegs=2, which would constrain candidates to callee trashable
// regs { eax, ecx, edx } on use positions of v01 and v02. LSRA allocates ecx for v01.
// The use position of v02 cannot be allocated a reg since it is marked delay-reg free and
// {eax,edx} are getting killed before the def of GT_DIV. For this reason, minRegCount for
// the use position of v02 also needs to take into account the kill set of its consuming node.
regMaskTP killMask = getKillSetForNode(tree);
if (killMask != RBM_NONE)
{
minRegCountForRef += genCountBits(killMask);
}
}
newRefPosition->minRegCandidateCount = minRegCountForRef;
if (newRefPosition->IsActualRef() && doReverseCallerCallee())
{
Interval* interval = newRefPosition->getInterval();
regMaskTP oldAssignment = newRefPosition->registerAssignment;
regMaskTP calleeSaveMask = calleeSaveRegs(interval->registerType);
newRefPosition->registerAssignment =
getConstrainedRegMask(oldAssignment, calleeSaveMask, minRegCountForRef);
if ((newRefPosition->registerAssignment != oldAssignment) && (newRefPosition->refType == RefTypeUse) &&
!interval->isLocalVar)
{
checkConflictingDefUse(newRefPosition);
}
}
}
}
#endif // DEBUG
JITDUMP("\n");
}
//------------------------------------------------------------------------
// buildPhysRegRecords: Make an interval for each physical register
//
void LinearScan::buildPhysRegRecords()
{
RegisterType regType = IntRegisterType;
for (regNumber reg = REG_FIRST; reg < ACTUAL_REG_COUNT; reg = REG_NEXT(reg))
{
RegRecord* curr = &physRegs[reg];
curr->init(reg);
}
}
//------------------------------------------------------------------------
// getNonEmptyBlock: Return the first non-empty block starting with 'block'
//
// Arguments:
// block - the BasicBlock from which we start looking
//
// Return Value:
// The first non-empty BasicBlock we find.
//
BasicBlock* getNonEmptyBlock(BasicBlock* block)
{
while (block != nullptr && block->bbTreeList == nullptr)
{
BasicBlock* nextBlock = block->bbNext;
// Note that here we use the version of NumSucc that does not take a compiler.
// That way this doesn't have to take a compiler, or be an instance method, e.g. of LinearScan.
// If we have an empty block, it must have jump type BBJ_NONE or BBJ_ALWAYS, in which
// case we don't need the version that takes a compiler.
assert(block->NumSucc() == 1 && ((block->bbJumpKind == BBJ_ALWAYS) || (block->bbJumpKind == BBJ_NONE)));
// sometimes the first block is empty and ends with an uncond branch
// assert( block->GetSucc(0) == nextBlock);
block = nextBlock;
}
assert(block != nullptr && block->bbTreeList != nullptr);
return block;
}
//------------------------------------------------------------------------
// insertZeroInitRefPositions: Handle lclVars that are live-in to the first block
//
// Notes:
// Prior to calling this method, 'currentLiveVars' must be set to the set of register
// candidate variables that are liveIn to the first block.
// For each register candidate that is live-in to the first block:
// - If it is a GC ref, or if compInitMem is set, a ZeroInit RefPosition will be created.
// - Otherwise, it will be marked as spilled, since it will not be assigned a register
// on entry and will be loaded from memory on the undefined path.
// Note that, when the compInitMem option is not set, we may encounter these on
// paths that are protected by the same condition as an earlier def. However, since
// we don't do the analysis to determine this - and couldn't rely on always identifying
// such cases even if we tried - we must conservatively treat the undefined path as
// being possible. This is a relatively rare case, so the introduced conservatism is
// not expected to warrant the analysis required to determine the best placement of
// an initialization.
//
void LinearScan::insertZeroInitRefPositions()
{
assert(enregisterLocalVars);
#ifdef DEBUG
VARSET_TP expectedLiveVars(VarSetOps::Intersection(compiler, registerCandidateVars, compiler->fgFirstBB->bbLiveIn));
assert(VarSetOps::Equal(compiler, currentLiveVars, expectedLiveVars));
#endif // DEBUG
// insert defs for this, then a block boundary
VarSetOps::Iter iter(compiler, currentLiveVars);
unsigned varIndex = 0;
while (iter.NextElem(&varIndex))
{
unsigned varNum = compiler->lvaTrackedToVarNum[varIndex];
LclVarDsc* varDsc = compiler->lvaTable + varNum;
if (!varDsc->lvIsParam && isCandidateVar(varDsc))
{
JITDUMP("V%02u was live in to first block:", varNum);
Interval* interval = getIntervalForLocalVar(varIndex);
if (compiler->info.compInitMem || varTypeIsGC(varDsc->TypeGet()))
{
JITDUMP(" creating ZeroInit\n");
GenTree* firstNode = getNonEmptyBlock(compiler->fgFirstBB)->firstNode();
RefPosition* pos =
newRefPosition(interval, MinLocation, RefTypeZeroInit, firstNode, allRegs(interval->registerType));
varDsc->lvMustInit = true;
}
else
{
setIntervalAsSpilled(interval);
JITDUMP(" marking as spilled\n");
}
}
}
}
#if defined(UNIX_AMD64_ABI)
//------------------------------------------------------------------------
// unixAmd64UpdateRegStateForArg: Sets the register state for an argument of type STRUCT for System V systems.
//
// Arguments:
// argDsc - the LclVarDsc for the argument of interest
//
// Notes:
// See Compiler::raUpdateRegStateForArg(RegState *regState, LclVarDsc *argDsc) in regalloc.cpp
// for how state for argument is updated for unix non-structs and Windows AMD64 structs.
//
void LinearScan::unixAmd64UpdateRegStateForArg(LclVarDsc* argDsc)
{
assert(varTypeIsStruct(argDsc));
RegState* intRegState = &compiler->codeGen->intRegState;
RegState* floatRegState = &compiler->codeGen->floatRegState;
if ((argDsc->lvArgReg != REG_STK) && (argDsc->lvArgReg != REG_NA))
{
if (genRegMask(argDsc->lvArgReg) & (RBM_ALLFLOAT))
{
assert(genRegMask(argDsc->lvArgReg) & (RBM_FLTARG_REGS));
floatRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->lvArgReg);
}
else
{
assert(genRegMask(argDsc->lvArgReg) & (RBM_ARG_REGS));
intRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->lvArgReg);
}
}
if ((argDsc->lvOtherArgReg != REG_STK) && (argDsc->lvOtherArgReg != REG_NA))
{
if (genRegMask(argDsc->lvOtherArgReg) & (RBM_ALLFLOAT))
{
assert(genRegMask(argDsc->lvOtherArgReg) & (RBM_FLTARG_REGS));
floatRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->lvOtherArgReg);
}
else
{
assert(genRegMask(argDsc->lvOtherArgReg) & (RBM_ARG_REGS));
intRegState->rsCalleeRegArgMaskLiveIn |= genRegMask(argDsc->lvOtherArgReg);
}
}
}
#endif // defined(UNIX_AMD64_ABI)
//------------------------------------------------------------------------
// updateRegStateForArg: Updates rsCalleeRegArgMaskLiveIn for the appropriate
// regState (either compiler->intRegState or compiler->floatRegState),
// with the lvArgReg on "argDsc"
//
// Arguments:
// argDsc - the argument for which the state is to be updated.
//
// Return Value: None
//
// Assumptions:
// The argument is live on entry to the function
// (or is untracked and therefore assumed live)
//
// Notes:
// This relies on a method in regAlloc.cpp that is shared between LSRA
// and regAlloc. It is further abstracted here because regState is updated
// separately for tracked and untracked variables in LSRA.
//
void LinearScan::updateRegStateForArg(LclVarDsc* argDsc)
{
#if defined(UNIX_AMD64_ABI)
// For System V AMD64 calls the argDsc can have 2 registers (for structs.)
// Handle them here.
if (varTypeIsStruct(argDsc))
{
unixAmd64UpdateRegStateForArg(argDsc);
}
else
#endif // defined(UNIX_AMD64_ABI)
{
RegState* intRegState = &compiler->codeGen->intRegState;
RegState* floatRegState = &compiler->codeGen->floatRegState;
// In the case of AMD64 we'll still use the floating point registers
// to model the register usage for argument on vararg calls, so
// we will ignore the varargs condition to determine whether we use
// XMM registers or not for setting up the call.
bool isFloat = (isFloatRegType(argDsc->lvType)
#ifndef _TARGET_AMD64_
&& !compiler->info.compIsVarArgs
#endif
&& !compiler->opts.compUseSoftFP);
if (argDsc->lvIsHfaRegArg())
{
isFloat = true;
}
if (isFloat)
{
JITDUMP("Float arg V%02u in reg %s\n", (argDsc - compiler->lvaTable), getRegName(argDsc->lvArgReg));
compiler->raUpdateRegStateForArg(floatRegState, argDsc);
}
else
{
JITDUMP("Int arg V%02u in reg %s\n", (argDsc - compiler->lvaTable), getRegName(argDsc->lvArgReg));
#if FEATURE_MULTIREG_ARGS
if (argDsc->lvOtherArgReg != REG_NA)
{
JITDUMP("(second half) in reg %s\n", getRegName(argDsc->lvOtherArgReg));
}
#endif // FEATURE_MULTIREG_ARGS
compiler->raUpdateRegStateForArg(intRegState, argDsc);
}
}
}
//------------------------------------------------------------------------
// buildIntervals: The main entry point for building the data structures over
// which we will do register allocation.
//
void LinearScan::buildIntervals()
{
BasicBlock* block;
JITDUMP("\nbuildIntervals ========\n");
// Build (empty) records for all of the physical registers
buildPhysRegRecords();
#ifdef DEBUG
if (VERBOSE)
{
printf("\n-----------------\n");
printf("LIVENESS:\n");
printf("-----------------\n");
foreach_block(compiler, block)
{
printf("BB%02u use def in out\n", block->bbNum);
dumpConvertedVarSet(compiler, block->bbVarUse);
printf("\n");
dumpConvertedVarSet(compiler, block->bbVarDef);
printf("\n");
dumpConvertedVarSet(compiler, block->bbLiveIn);
printf("\n");
dumpConvertedVarSet(compiler, block->bbLiveOut);
printf("\n");
}
}
#endif // DEBUG
#if DOUBLE_ALIGN
// We will determine whether we should double align the frame during
// identifyCandidates(), but we initially assume that we will not.
doDoubleAlign = false;
#endif
identifyCandidates();
// Figure out if we're going to use a frame pointer. We need to do this before building
// the ref positions, because those objects will embed the frame register in various register masks
// if the frame pointer is not reserved. If we decide to have a frame pointer, setFrameType() will
// remove the frame pointer from the masks.
setFrameType();
DBEXEC(VERBOSE, TupleStyleDump(LSRA_DUMP_PRE));
// second part:
JITDUMP("\nbuildIntervals second part ========\n");
currentLoc = 0;
// TODO-Cleanup: This duplicates prior behavior where entry (ParamDef) RefPositions were
// being assigned the bbNum of the last block traversed in the 2nd phase of Lowering.
// Previously, the block sequencing was done for the (formerly separate) Build pass,
// and the curBBNum was left as the last block sequenced. This block was then used to set the
// weight for the entry (ParamDef) RefPositions. It would be logical to set this to the
// normalized entry weight (compiler->fgCalledCount), but that results in a net regression.
if (!blockSequencingDone)
{
setBlockSequence();
}
curBBNum = blockSequence[bbSeqCount - 1]->bbNum;
// Next, create ParamDef RefPositions for all the tracked parameters, in order of their varIndex.
// Assign these RefPositions to the (nonexistent) BB0.
curBBNum = 0;
LclVarDsc* argDsc;
unsigned int lclNum;
RegState* intRegState = &compiler->codeGen->intRegState;
RegState* floatRegState = &compiler->codeGen->floatRegState;
intRegState->rsCalleeRegArgMaskLiveIn = RBM_NONE;
floatRegState->rsCalleeRegArgMaskLiveIn = RBM_NONE;
for (unsigned int varIndex = 0; varIndex < compiler->lvaTrackedCount; varIndex++)
{
lclNum = compiler->lvaTrackedToVarNum[varIndex];
argDsc = &(compiler->lvaTable[lclNum]);
if (!argDsc->lvIsParam)
{
continue;
}
// Only reserve a register if the argument is actually used.
// Is it dead on entry? If compJmpOpUsed is true, then the arguments
// have to be kept alive, so we have to consider it as live on entry.
// Use lvRefCnt instead of checking bbLiveIn because if it's volatile we
// won't have done dataflow on it, but it needs to be marked as live-in so
// it will get saved in the prolog.
if (!compiler->compJmpOpUsed && argDsc->lvRefCnt == 0 && !compiler->opts.compDbgCode)
{
continue;
}
if (argDsc->lvIsRegArg)
{
updateRegStateForArg(argDsc);
}
if (isCandidateVar(argDsc))
{
Interval* interval = getIntervalForLocalVar(varIndex);
regMaskTP mask = allRegs(TypeGet(argDsc));
if (argDsc->lvIsRegArg)
{
// Set this interval as currently assigned to that register
regNumber inArgReg = argDsc->lvArgReg;
assert(inArgReg < REG_COUNT);
mask = genRegMask(inArgReg);
assignPhysReg(inArgReg, interval);
}
RefPosition* pos = newRefPosition(interval, MinLocation, RefTypeParamDef, nullptr, mask);
}
else if (varTypeIsStruct(argDsc->lvType))
{
for (unsigned fieldVarNum = argDsc->lvFieldLclStart;
fieldVarNum < argDsc->lvFieldLclStart + argDsc->lvFieldCnt; ++fieldVarNum)
{
LclVarDsc* fieldVarDsc = &(compiler->lvaTable[fieldVarNum]);
if (fieldVarDsc->lvLRACandidate)
{
assert(fieldVarDsc->lvTracked);
Interval* interval = getIntervalForLocalVar(fieldVarDsc->lvVarIndex);
RefPosition* pos =
newRefPosition(interval, MinLocation, RefTypeParamDef, nullptr, allRegs(TypeGet(fieldVarDsc)));
}
}
}
else
{
// We can overwrite the register (i.e. codegen saves it on entry)
assert(argDsc->lvRefCnt == 0 || !argDsc->lvIsRegArg || argDsc->lvDoNotEnregister ||
!argDsc->lvLRACandidate || (varTypeIsFloating(argDsc->TypeGet()) && compiler->opts.compDbgCode));
}
}
// Now set up the reg state for the non-tracked args
// (We do this here because we want to generate the ParamDef RefPositions in tracked
// order, so that loop doesn't hit the non-tracked args)
for (unsigned argNum = 0; argNum < compiler->info.compArgsCount; argNum++, argDsc++)
{
argDsc = &(compiler->lvaTable[argNum]);
if (argDsc->lvPromotedStruct())
{
noway_assert(argDsc->lvFieldCnt == 1); // We only handle one field here
unsigned fieldVarNum = argDsc->lvFieldLclStart;
argDsc = &(compiler->lvaTable[fieldVarNum]);
}
noway_assert(argDsc->lvIsParam);
if (!argDsc->lvTracked && argDsc->lvIsRegArg)
{
updateRegStateForArg(argDsc);
}
}
// If there is a secret stub param, it is also live in
if (compiler->info.compPublishStubParam)
{
intRegState->rsCalleeRegArgMaskLiveIn |= RBM_SECRET_STUB_PARAM;
}
BasicBlock* predBlock = nullptr;
BasicBlock* prevBlock = nullptr;
// Initialize currentLiveVars to the empty set. We will set it to the current
// live-in at the entry to each block (this will include the incoming args on
// the first block).
VarSetOps::AssignNoCopy(compiler, currentLiveVars, VarSetOps::MakeEmpty(compiler));
for (block = startBlockSequence(); block != nullptr; block = moveToNextBlock())
{
JITDUMP("\nNEW BLOCK BB%02u\n", block->bbNum);
bool predBlockIsAllocated = false;
predBlock = findPredBlockForLiveIn(block, prevBlock DEBUGARG(&predBlockIsAllocated));
if (predBlock)
{
JITDUMP("\n\nSetting BB%02u as the predecessor for determining incoming variable registers of BB%02u\n",
block->bbNum, predBlock->bbNum);
assert(predBlock->bbNum <= bbNumMaxBeforeResolution);
blockInfo[block->bbNum].predBBNum = predBlock->bbNum;
}
if (enregisterLocalVars)
{
VarSetOps::AssignNoCopy(compiler, currentLiveVars,
VarSetOps::Intersection(compiler, registerCandidateVars, block->bbLiveIn));
if (block == compiler->fgFirstBB)
{
insertZeroInitRefPositions();
// The first real location is at 1; 0 is for the entry.
currentLoc = 1;
}
// Any lclVars live-in to a block are resolution candidates.
VarSetOps::UnionD(compiler, resolutionCandidateVars, currentLiveVars);
// Determine if we need any DummyDefs.
// We need DummyDefs for cases where "predBlock" isn't really a predecessor.
// Note that it's possible to have uses of unitialized variables, in which case even the first
// block may require DummyDefs, which we are not currently adding - this means that these variables
// will always be considered to be in memory on entry (and reloaded when the use is encountered).
// TODO-CQ: Consider how best to tune this. Currently, if we create DummyDefs for uninitialized
// variables (which may actually be initialized along the dynamically executed paths, but not
// on all static paths), we wind up with excessive liveranges for some of these variables.
VARSET_TP newLiveIn(VarSetOps::MakeCopy(compiler, currentLiveVars));
if (predBlock)
{
// Compute set difference: newLiveIn = currentLiveVars - predBlock->bbLiveOut
VarSetOps::DiffD(compiler, newLiveIn, predBlock->bbLiveOut);
}
bool needsDummyDefs = (!VarSetOps::IsEmpty(compiler, newLiveIn) && block != compiler->fgFirstBB);
// Create dummy def RefPositions
if (needsDummyDefs)
{
// If we are using locations from a predecessor, we should never require DummyDefs.
assert(!predBlockIsAllocated);
JITDUMP("Creating dummy definitions\n");
VarSetOps::Iter iter(compiler, newLiveIn);
unsigned varIndex = 0;
while (iter.NextElem(&varIndex))
{
unsigned varNum = compiler->lvaTrackedToVarNum[varIndex];
LclVarDsc* varDsc = compiler->lvaTable + varNum;
// Add a dummyDef for any candidate vars that are in the "newLiveIn" set.
// If this is the entry block, don't add any incoming parameters (they're handled with ParamDefs).
if (isCandidateVar(varDsc) && (predBlock != nullptr || !varDsc->lvIsParam))
{
Interval* interval = getIntervalForLocalVar(varIndex);
RefPosition* pos = newRefPosition(interval, currentLoc, RefTypeDummyDef, nullptr,
allRegs(interval->registerType));
}
}
JITDUMP("Finished creating dummy definitions\n\n");
}
}
// Add a dummy RefPosition to mark the block boundary.
// Note that we do this AFTER adding the exposed uses above, because the
// register positions for those exposed uses need to be recorded at
// this point.
RefPosition* pos = newRefPosition((Interval*)nullptr, currentLoc, RefTypeBB, nullptr, RBM_NONE);
currentLoc += 2;
JITDUMP("\n");
LIR::Range& blockRange = LIR::AsRange(block);
for (GenTree* node : blockRange.NonPhiNodes())
{
// We increment the number position of each tree node by 2 to simplify the logic when there's the case of
// a tree that implicitly does a dual-definition of temps (the long case). In this case it is easier to
// already have an idle spot to handle a dual-def instead of making some messy adjustments if we only
// increment the number position by one.
CLANG_FORMAT_COMMENT_ANCHOR;
#ifdef DEBUG
node->gtSeqNum = currentLoc;
// In DEBUG, we want to set the gtRegTag to GT_REGTAG_REG, so that subsequent dumps will so the register
// value.
// Although this looks like a no-op it sets the tag.
node->gtRegNum = node->gtRegNum;
#endif
buildRefPositionsForNode(node, block, currentLoc);
#ifdef DEBUG
if (currentLoc > maxNodeLocation)
{
maxNodeLocation = currentLoc;
}
#endif // DEBUG
currentLoc += 2;
}
// Note: the visited set is cleared in LinearScan::doLinearScan()
markBlockVisited(block);
assert(defList.IsEmpty());
if (enregisterLocalVars)
{
// Insert exposed uses for a lclVar that is live-out of 'block' but not live-in to the
// next block, or any unvisited successors.
// This will address lclVars that are live on a backedge, as well as those that are kept
// live at a GT_JMP.
//
// Blocks ending with "jmp method" are marked as BBJ_HAS_JMP,
// and jmp call is represented using GT_JMP node which is a leaf node.
// Liveness phase keeps all the arguments of the method live till the end of
// block by adding them to liveout set of the block containing GT_JMP.
//
// The target of a GT_JMP implicitly uses all the current method arguments, however
// there are no actual references to them. This can cause LSRA to assert, because
// the variables are live but it sees no references. In order to correctly model the
// liveness of these arguments, we add dummy exposed uses, in the same manner as for
// backward branches. This will happen automatically via expUseSet.
//
// Note that a block ending with GT_JMP has no successors and hence the variables
// for which dummy use ref positions are added are arguments of the method.
VARSET_TP expUseSet(VarSetOps::MakeCopy(compiler, block->bbLiveOut));
VarSetOps::IntersectionD(compiler, expUseSet, registerCandidateVars);
BasicBlock* nextBlock = getNextBlock();
if (nextBlock != nullptr)
{
VarSetOps::DiffD(compiler, expUseSet, nextBlock->bbLiveIn);
}
for (BasicBlock* succ : block->GetAllSuccs(compiler))
{
if (VarSetOps::IsEmpty(compiler, expUseSet))
{
break;
}
if (isBlockVisited(succ))
{
continue;
}
VarSetOps::DiffD(compiler, expUseSet, succ->bbLiveIn);
}
if (!VarSetOps::IsEmpty(compiler, expUseSet))
{
JITDUMP("Exposed uses:");
VarSetOps::Iter iter(compiler, expUseSet);
unsigned varIndex = 0;
while (iter.NextElem(&varIndex))
{
unsigned varNum = compiler->lvaTrackedToVarNum[varIndex];
LclVarDsc* varDsc = compiler->lvaTable + varNum;
assert(isCandidateVar(varDsc));
Interval* interval = getIntervalForLocalVar(varIndex);
RefPosition* pos =
newRefPosition(interval, currentLoc, RefTypeExpUse, nullptr, allRegs(interval->registerType));
JITDUMP(" V%02u", varNum);
}
JITDUMP("\n");
}
// Clear the "last use" flag on any vars that are live-out from this block.
{
VarSetOps::Iter iter(compiler, block->bbLiveOut);
unsigned varIndex = 0;
while (iter.NextElem(&varIndex))
{
unsigned varNum = compiler->lvaTrackedToVarNum[varIndex];
LclVarDsc* const varDsc = &compiler->lvaTable[varNum];
if (isCandidateVar(varDsc))
{
RefPosition* const lastRP = getIntervalForLocalVar(varIndex)->lastRefPosition;
if ((lastRP != nullptr) && (lastRP->bbNum == block->bbNum))
{
lastRP->lastUse = false;
}
}
}
}
#ifdef DEBUG
checkLastUses(block);
if (VERBOSE)
{
printf("use: ");
dumpConvertedVarSet(compiler, block->bbVarUse);
printf("\ndef: ");
dumpConvertedVarSet(compiler, block->bbVarDef);
printf("\n");
}
#endif // DEBUG
}
prevBlock = block;
}
if (enregisterLocalVars)
{
if (compiler->lvaKeepAliveAndReportThis())
{
// If we need to KeepAliveAndReportThis, add a dummy exposed use of it at the end
unsigned keepAliveVarNum = compiler->info.compThisArg;
assert(compiler->info.compIsStatic == false);
LclVarDsc* varDsc = compiler->lvaTable + keepAliveVarNum;
if (isCandidateVar(varDsc))
{
JITDUMP("Adding exposed use of this, for lvaKeepAliveAndReportThis\n");
Interval* interval = getIntervalForLocalVar(varDsc->lvVarIndex);
RefPosition* pos =
newRefPosition(interval, currentLoc, RefTypeExpUse, nullptr, allRegs(interval->registerType));
}
}
#ifdef DEBUG
if (getLsraExtendLifeTimes())
{
LclVarDsc* varDsc;
for (lclNum = 0, varDsc = compiler->lvaTable; lclNum < compiler->lvaCount; lclNum++, varDsc++)
{
if (varDsc->lvLRACandidate)
{
JITDUMP("Adding exposed use of V%02u for LsraExtendLifetimes\n", lclNum);
Interval* interval = getIntervalForLocalVar(varDsc->lvVarIndex);
RefPosition* pos =
newRefPosition(interval, currentLoc, RefTypeExpUse, nullptr, allRegs(interval->registerType));
}
}
}
#endif // DEBUG
}
// If the last block has successors, create a RefTypeBB to record
// what's live
if (prevBlock->NumSucc(compiler) > 0)
{
RefPosition* pos = newRefPosition((Interval*)nullptr, currentLoc, RefTypeBB, nullptr, RBM_NONE);
}
#ifdef DEBUG
// Make sure we don't have any blocks that were not visited
foreach_block(compiler, block)
{
assert(isBlockVisited(block));
}
if (VERBOSE)
{
lsraDumpIntervals("BEFORE VALIDATING INTERVALS");
dumpRefPositions("BEFORE VALIDATING INTERVALS");
validateIntervals();
}
#endif // DEBUG
}
#ifdef DEBUG
//------------------------------------------------------------------------
// validateIntervals: A DEBUG-only method that checks that the lclVar RefPositions
// do not reflect uses of undefined values
//
// Notes: If an undefined use is encountered, it merely prints a message.
//
// TODO-Cleanup: This should probably assert, or at least print the message only
// when doing a JITDUMP.
//
void LinearScan::validateIntervals()
{
if (enregisterLocalVars)
{
for (unsigned i = 0; i < compiler->lvaTrackedCount; i++)
{
if (!compiler->lvaTable[compiler->lvaTrackedToVarNum[i]].lvLRACandidate)
{
continue;
}
Interval* interval = getIntervalForLocalVar(i);
bool defined = false;
printf("-----------------\n");
for (RefPosition* ref = interval->firstRefPosition; ref != nullptr; ref = ref->nextRefPosition)
{
ref->dump();
RefType refType = ref->refType;
if (!defined && RefTypeIsUse(refType))
{
if (compiler->info.compMethodName != nullptr)
{
printf("%s: ", compiler->info.compMethodName);
}
printf("LocalVar V%02u: undefined use at %u\n", interval->varNum, ref->nodeLocation);
}
// Note that there can be multiple last uses if they are on disjoint paths,
// so we can't really check the lastUse flag
if (ref->lastUse)
{
defined = false;
}
if (RefTypeIsDef(refType))
{
defined = true;
}
}
}
}
}
#endif // DEBUG
//------------------------------------------------------------------------
// GetIndirInfo: Get the source registers for an indirection that might be contained.
//
// Arguments:
// node - The node of interest
//
// Return Value:
// The number of source registers used by the *parent* of this node.
//
// Notes:
// Adds the defining node for each register to the useList.
//
int LinearScan::GetIndirInfo(GenTreeIndir* indirTree)
{
GenTree* const addr = indirTree->gtOp1;
if (!addr->isContained())
{
appendLocationInfoToList(addr);
return 1;
}
if (!addr->OperIs(GT_LEA))
{
return 0;
}
GenTreeAddrMode* const addrMode = addr->AsAddrMode();
unsigned srcCount = 0;
if ((addrMode->Base() != nullptr) && !addrMode->Base()->isContained())
{
appendLocationInfoToList(addrMode->Base());
srcCount++;
}
if ((addrMode->Index() != nullptr) && !addrMode->Index()->isContained())
{
appendLocationInfoToList(addrMode->Index());
srcCount++;
}
return srcCount;
}
//------------------------------------------------------------------------
// GetOperandInfo: Get the source registers for an operand that might be contained.
//
// Arguments:
// node - The node of interest
// useList - The list of uses for the node that we're currently processing
//
// Return Value:
// The number of source registers used by the *parent* of this node.
//
// Notes:
// Adds the defining node for each register to the given useList.
//
int LinearScan::GetOperandInfo(GenTree* node)
{
if (!node->isContained())
{
appendLocationInfoToList(node);
return 1;
}
#if !defined(_TARGET_64BIT_)
if (node->OperIs(GT_LONG))
{
return appendBinaryLocationInfoToList(node->AsOp());
}
#endif // !defined(_TARGET_64BIT_)
if (node->OperIsIndir())
{
const unsigned srcCount = GetIndirInfo(node->AsIndir());
return srcCount;
}
if (node->OperIsHWIntrinsic())
{
appendLocationInfoToList(node->gtGetOp1());
return 1;
}
return 0;
}
//------------------------------------------------------------------------
// GetOperandInfo: Get the source registers for an operand that might be contained.
//
// Arguments:
// node - The node of interest
// useList - The list of uses for the node that we're currently processing
//
// Return Value:
// The number of source registers used by the *parent* of this node.
//
// Notes:
// Adds the defining node for each register to the useList.
//
int LinearScan::GetOperandInfo(GenTree* node, LocationInfoListNode** pFirstInfo)
{
LocationInfoListNode* prevLast = useList.Last();
int srcCount = GetOperandInfo(node);
if (prevLast == nullptr)
{
*pFirstInfo = useList.Begin();
}
else
{
*pFirstInfo = prevLast->Next();
}
return srcCount;
}
void TreeNodeInfo::Initialize(LinearScan* lsra, GenTree* node)
{
_dstCount = 0;
_srcCount = 0;
_internalIntCount = 0;
_internalFloatCount = 0;
isLocalDefUse = false;
isDelayFree = false;
hasDelayFreeSrc = false;
isTgtPref = false;
isInternalRegDelayFree = false;
regMaskTP dstCandidates;
// if there is a reg indicated on the tree node, use that for dstCandidates
// the exception is the NOP, which sometimes show up around late args.
// TODO-Cleanup: get rid of those NOPs.
if (node->gtRegNum == REG_STK)
{
dstCandidates = RBM_NONE;
}
else if (node->gtRegNum == REG_NA || node->gtOper == GT_NOP)
{
#ifdef ARM_SOFTFP
if (node->OperGet() == GT_PUTARG_REG)
{
dstCandidates = lsra->allRegs(TYP_INT);
}
else
#endif
{
dstCandidates = lsra->allRegs(node->TypeGet());
}
}
else
{
dstCandidates = genRegMask(node->gtRegNum);
}
setDstCandidates(lsra, dstCandidates);
srcCandsIndex = dstCandsIndex;
setInternalCandidates(lsra, lsra->allRegs(TYP_INT));
#ifdef DEBUG
isInitialized = true;
#endif
assert(IsValid(lsra));
}
//------------------------------------------------------------------------
// getSrcCandidates: Get the source candidates (candidates for the consumer
// of the node) from the TreeNodeInfo
//
// Arguments:
// lsra - the LinearScan object
//
// Return Value:
// The set of registers (as a register mask) that are candidates for the
// consumer of the node
//
// Notes:
// The LinearScan object maintains the mapping from the indices kept in the
// TreeNodeInfo to the actual register masks.
//
regMaskTP TreeNodeInfo::getSrcCandidates(LinearScan* lsra)
{
return lsra->GetRegMaskForIndex(srcCandsIndex);
}
//------------------------------------------------------------------------
// setSrcCandidates: Set the source candidates (candidates for the consumer
// of the node) on the TreeNodeInfo
//
// Arguments:
// lsra - the LinearScan object
//
// Notes: see getSrcCandidates
//
void TreeNodeInfo::setSrcCandidates(LinearScan* lsra, regMaskTP mask)
{
LinearScan::RegMaskIndex i = lsra->GetIndexForRegMask(mask);
assert(FitsIn<unsigned char>(i));
srcCandsIndex = (unsigned char)i;
}
//------------------------------------------------------------------------
// getDstCandidates: Get the dest candidates (candidates for the definition
// of the node) from the TreeNodeInfo
//
// Arguments:
// lsra - the LinearScan object
//
// Return Value:
// The set of registers (as a register mask) that are candidates for the
// node itself
//
// Notes: see getSrcCandidates
//
regMaskTP TreeNodeInfo::getDstCandidates(LinearScan* lsra)
{
return lsra->GetRegMaskForIndex(dstCandsIndex);
}
//------------------------------------------------------------------------
// setDstCandidates: Set the dest candidates (candidates for the definition
// of the node) on the TreeNodeInfo
//
// Arguments:
// lsra - the LinearScan object
//
// Notes: see getSrcCandidates
//
void TreeNodeInfo::setDstCandidates(LinearScan* lsra, regMaskTP mask)
{
LinearScan::RegMaskIndex i = lsra->GetIndexForRegMask(mask);
assert(FitsIn<unsigned char>(i));
dstCandsIndex = (unsigned char)i;
}
//------------------------------------------------------------------------
// getInternalCandidates: Get the internal candidates (candidates for the internal
// temporary registers used by a node) from the TreeNodeInfo
//
// Arguments:
// lsra - the LinearScan object
//
// Return Value:
// The set of registers (as a register mask) that are candidates for the
// internal temporary registers.
//
// Notes: see getSrcCandidates
//
regMaskTP TreeNodeInfo::getInternalCandidates(LinearScan* lsra)
{
return lsra->GetRegMaskForIndex(internalCandsIndex);
}
//------------------------------------------------------------------------
// getInternalCandidates: Set the internal candidates (candidates for the internal
// temporary registers used by a node) on the TreeNodeInfo
//
// Arguments:
// lsra - the LinearScan object
//
// Notes: see getSrcCandidates
//
void TreeNodeInfo::setInternalCandidates(LinearScan* lsra, regMaskTP mask)
{
LinearScan::RegMaskIndex i = lsra->GetIndexForRegMask(mask);
assert(FitsIn<unsigned char>(i));
internalCandsIndex = (unsigned char)i;
}
//------------------------------------------------------------------------
// addInternalCandidates: Add internal candidates (candidates for the internal
// temporary registers used by a node) on the TreeNodeInfo
//
// Arguments:
// lsra - the LinearScan object
//
// Notes: see getSrcCandidates
//
void TreeNodeInfo::addInternalCandidates(LinearScan* lsra, regMaskTP mask)
{
LinearScan::RegMaskIndex i = lsra->GetIndexForRegMask(lsra->GetRegMaskForIndex(internalCandsIndex) | mask);
assert(FitsIn<unsigned char>(i));
internalCandsIndex = (unsigned char)i;
}
//------------------------------------------------------------------------
// BuildStoreLoc: Set register requirements for a store of a lclVar
//
// Arguments:
// storeLoc - the local store (GT_STORE_LCL_FLD or GT_STORE_LCL_VAR)
//
// Notes:
// This involves:
// - Setting the appropriate candidates for a store of a multi-reg call return value.
// - Handling of contained immediates.
// - Requesting an internal register for SIMD12 stores.
//
void LinearScan::BuildStoreLoc(GenTreeLclVarCommon* storeLoc)
{
TreeNodeInfo* info = currentNodeInfo;
GenTree* op1 = storeLoc->gtGetOp1();
assert(info->dstCount == 0);
if (op1->IsMultiRegCall())
{
// This is the case of var = call where call is returning
// a value in multiple return registers.
// Must be a store lclvar.
assert(storeLoc->OperGet() == GT_STORE_LCL_VAR);
// srcCount = number of registers in which the value is returned by call
GenTreeCall* call = op1->AsCall();
ReturnTypeDesc* retTypeDesc = call->GetReturnTypeDesc();
unsigned regCount = retTypeDesc->GetReturnRegCount();
info->srcCount = regCount;
// Call node srcCandidates = Bitwise-OR(allregs(GetReturnRegType(i))) for all i=0..RetRegCount-1
regMaskTP srcCandidates = allMultiRegCallNodeRegs(call);
LocationInfoListNode* locInfo = getLocationInfo(op1);
locInfo->info.setSrcCandidates(this, srcCandidates);
useList.Append(locInfo);
}
#ifndef _TARGET_64BIT_
else if (varTypeIsLong(op1))
{
if (op1->OperIs(GT_MUL_LONG))
{
#ifdef _TARGET_X86_
// This is actually a bug. A GT_MUL_LONG produces two registers, but is modeled as only producing
// eax (and killing edx). This only works because it always occurs as var = GT_MUL_LONG (ensured by
// DecomposeMul), and therefore edx won't be reused before the store.
// TODO-X86-Cleanup: GT_MUL_LONG should be a multireg node on x86, just as on ARM.
info->srcCount = 1;
#else
info->srcCount = 2;
#endif
appendLocationInfoToList(op1);
}
else
{
assert(op1->OperIs(GT_LONG));
assert(op1->isContained() && !op1->gtOp.gtOp1->isContained() && !op1->gtOp.gtOp2->isContained());
info->srcCount = appendBinaryLocationInfoToList(op1->AsOp());
assert(info->srcCount == 2);
}
}
#endif // !_TARGET_64BIT_
else if (op1->isContained())
{
info->srcCount = 0;
}
else
{
info->srcCount = 1;
appendLocationInfoToList(op1);
}
#ifdef FEATURE_SIMD
if (varTypeIsSIMD(storeLoc))
{
if (!op1->isContained() && (storeLoc->TypeGet() == TYP_SIMD12))
{
// Need an additional register to extract upper 4 bytes of Vector3.
#ifdef _TARGET_XARCH_
info->internalFloatCount = 1;
info->setInternalCandidates(this, allSIMDRegs());
#elif defined(_TARGET_ARM64_)
info->internalIntCount = 1;
#else
#error "Unknown target architecture for STORE_LCL_VAR of SIMD12"
#endif
}
}
#endif // FEATURE_SIMD
}
//------------------------------------------------------------------------
// BuildSimple: Sets the srcCount for all the trees
// without special handling based on the tree node type.
//
// Arguments:
// tree - The node of interest
//
// Return Value:
// None.
//
void LinearScan::BuildSimple(GenTree* tree)
{
TreeNodeInfo* info = currentNodeInfo;
unsigned kind = tree->OperKind();
assert(info->dstCount == (tree->IsValue() ? 1 : 0));
if (kind & (GTK_CONST | GTK_LEAF))
{
info->srcCount = 0;
}
else if (kind & (GTK_SMPOP))
{
info->srcCount = appendBinaryLocationInfoToList(tree->AsOp());
}
else
{
unreached();
}
}
//------------------------------------------------------------------------
// BuildReturn: Set the NodeInfo for a GT_RETURN.
//
// Arguments:
// tree - The node of interest
//
// Return Value:
// None.
//
void LinearScan::BuildReturn(GenTree* tree)
{
TreeNodeInfo* info = currentNodeInfo;
assert(info->dstCount == 0);
GenTree* op1 = tree->gtGetOp1();
#if !defined(_TARGET_64BIT_)
if (tree->TypeGet() == TYP_LONG)
{
assert((op1->OperGet() == GT_LONG) && op1->isContained());
GenTree* loVal = op1->gtGetOp1();
GenTree* hiVal = op1->gtGetOp2();
info->srcCount = 2;
LocationInfoListNode* loValInfo = getLocationInfo(loVal);
LocationInfoListNode* hiValInfo = getLocationInfo(hiVal);
loValInfo->info.setSrcCandidates(this, RBM_LNGRET_LO);
hiValInfo->info.setSrcCandidates(this, RBM_LNGRET_HI);
useList.Append(loValInfo);
useList.Append(hiValInfo);
}
else
#endif // !defined(_TARGET_64BIT_)
if ((tree->TypeGet() != TYP_VOID) && !op1->isContained())
{
regMaskTP useCandidates = RBM_NONE;
info->srcCount = 1;
#if FEATURE_MULTIREG_RET
if (varTypeIsStruct(tree))
{
// op1 has to be either an lclvar or a multi-reg returning call
if (op1->OperGet() != GT_LCL_VAR)
{
noway_assert(op1->IsMultiRegCall());
ReturnTypeDesc* retTypeDesc = op1->AsCall()->GetReturnTypeDesc();
info->srcCount = retTypeDesc->GetReturnRegCount();
useCandidates = retTypeDesc->GetABIReturnRegs();
}
}
else
#endif // FEATURE_MULTIREG_RET
{
// Non-struct type return - determine useCandidates
switch (tree->TypeGet())
{
case TYP_VOID:
useCandidates = RBM_NONE;
break;
case TYP_FLOAT:
useCandidates = RBM_FLOATRET;
break;
case TYP_DOUBLE:
// We ONLY want the valid double register in the RBM_DOUBLERET mask.
useCandidates = (RBM_DOUBLERET & RBM_ALLDOUBLE);
break;
case TYP_LONG:
useCandidates = RBM_LNGRET;
break;
default:
useCandidates = RBM_INTRET;
break;
}
}
LocationInfoListNode* locationInfo = getLocationInfo(op1);
if (useCandidates != RBM_NONE)
{
locationInfo->info.setSrcCandidates(this, useCandidates);
}
useList.Append(locationInfo);
}
}
//------------------------------------------------------------------------
// BuildPutArgReg: Set the NodeInfo for a PUTARG_REG.
//
// Arguments:
// node - The PUTARG_REG node.
// argReg - The register in which to pass the argument.
// info - The info for the node's using call.
// isVarArgs - True if the call uses a varargs calling convention.
// callHasFloatRegArgs - Set to true if this PUTARG_REG uses an FP register.
//
// Return Value:
// None.
//
void LinearScan::BuildPutArgReg(GenTreeUnOp* node)
{
TreeNodeInfo* info = currentNodeInfo;
assert(node != nullptr);
assert(node->OperIsPutArgReg());
info->srcCount = 1;
regNumber argReg = node->gtRegNum;
assert(argReg != REG_NA);
// Set the register requirements for the node.
regMaskTP argMask = genRegMask(argReg);
#ifdef _TARGET_ARM_
// If type of node is `long` then it is actually `double`.
// The actual `long` types must have been transformed as a field list with two fields.
if (node->TypeGet() == TYP_LONG)
{
info->srcCount++;
info->dstCount = info->srcCount;
assert(genRegArgNext(argReg) == REG_NEXT(argReg));
argMask |= genRegMask(REG_NEXT(argReg));
}
#endif // _TARGET_ARM_
info->setDstCandidates(this, argMask);
info->setSrcCandidates(this, argMask);
// To avoid redundant moves, have the argument operand computed in the
// register in which the argument is passed to the call.
LocationInfoListNode* op1Info = getLocationInfo(node->gtOp.gtOp1);
op1Info->info.setSrcCandidates(this, info->getSrcCandidates(this));
op1Info->info.isDelayFree = true;
useList.Append(op1Info);
}
//------------------------------------------------------------------------
// HandleFloatVarArgs: Handle additional register requirements for a varargs call
//
// Arguments:
// call - The call node of interest
// argNode - The current argument
//
// Return Value:
// None.
//
// Notes:
// In the case of a varargs call, the ABI dictates that if we have floating point args,
// we must pass the enregistered arguments in both the integer and floating point registers.
// Since the integer register is not associated with the arg node, we will reserve it as
// an internal register on the call so that it is not used during the evaluation of the call node
// (e.g. for the target).
void LinearScan::HandleFloatVarArgs(GenTreeCall* call, GenTree* argNode, bool* callHasFloatRegArgs)
{
#if FEATURE_VARARG
TreeNodeInfo* info = currentNodeInfo;
if (call->IsVarargs() && varTypeIsFloating(argNode))
{
*callHasFloatRegArgs = true;
regNumber argReg = argNode->gtRegNum;
regNumber targetReg = compiler->getCallArgIntRegister(argReg);
info->setInternalIntCount(info->internalIntCount + 1);
info->addInternalCandidates(this, genRegMask(targetReg));
}
#endif // FEATURE_VARARG
}
//------------------------------------------------------------------------
// BuildGCWriteBarrier: Handle additional register requirements for a GC write barrier
//
// Arguments:
// tree - The STORE_IND for which a write barrier is required
//
void LinearScan::BuildGCWriteBarrier(GenTree* tree)
{
TreeNodeInfo* info = currentNodeInfo;
GenTree* dst = tree;
GenTree* addr = tree->gtOp.gtOp1;
GenTree* src = tree->gtOp.gtOp2;
LocationInfoListNode* addrInfo = getLocationInfo(addr);
LocationInfoListNode* srcInfo = getLocationInfo(src);
// In the case where we are doing a helper assignment, even if the dst
// is an indir through an lea, we need to actually instantiate the
// lea in a register
assert(!addr->isContained() && !src->isContained());
useList.Append(addrInfo);
useList.Append(srcInfo);
info->srcCount = 2;
assert(info->dstCount == 0);
bool customSourceRegs = false;
#if defined(_TARGET_ARM64_)
// the 'addr' goes into x14 (REG_WRITE_BARRIER_DST)
// the 'src' goes into x15 (REG_WRITE_BARRIER_SRC)
//
addrInfo->info.setSrcCandidates(this, RBM_WRITE_BARRIER_DST);
srcInfo->info.setSrcCandidates(this, RBM_WRITE_BARRIER_SRC);
customSourceRegs = true;
#elif defined(_TARGET_X86_) && NOGC_WRITE_BARRIERS
bool useOptimizedWriteBarrierHelper = compiler->codeGen->genUseOptimizedWriteBarriers(tree, src);
if (useOptimizedWriteBarrierHelper)
{
// Special write barrier:
// op1 (addr) goes into REG_WRITE_BARRIER (rdx) and
// op2 (src) goes into any int register.
addrInfo->info.setSrcCandidates(this, RBM_WRITE_BARRIER);
srcInfo->info.setSrcCandidates(this, RBM_WRITE_BARRIER_SRC);
customSourceRegs = true;
}
#endif // defined(_TARGET_X86_) && NOGC_WRITE_BARRIERS
if (!customSourceRegs)
{
// For the standard JIT Helper calls:
// op1 (addr) goes into REG_ARG_0 and
// op2 (src) goes into REG_ARG_1
addrInfo->info.setSrcCandidates(this, RBM_ARG_0);
srcInfo->info.setSrcCandidates(this, RBM_ARG_1);
}
// Both src and dst must reside in a register, which they should since we haven't set
// either of them as contained.
assert(addrInfo->info.dstCount == 1);
assert(srcInfo->info.dstCount == 1);
}
//------------------------------------------------------------------------
// BuildCmp: Set the register requirements for a compare.
//
// Arguments:
// tree - The node of interest
//
// Return Value:
// None.
//
void LinearScan::BuildCmp(GenTree* tree)
{
TreeNodeInfo* info = currentNodeInfo;
assert(tree->OperIsCompare() || tree->OperIs(GT_CMP) || tree->OperIs(GT_JCMP));
info->srcCount = 0;
assert((info->dstCount == 1) || (tree->TypeGet() == TYP_VOID));
#ifdef _TARGET_X86_
// If the compare is used by a jump, we just need to set the condition codes. If not, then we need
// to store the result into the low byte of a register, which requires the dst be a byteable register.
// We always set the dst candidates, though, because if this is compare is consumed by a jump, they
// won't be used. We might be able to use GTF_RELOP_JMP_USED to determine this case, but it's not clear
// that flag is maintained until this location (especially for decomposed long compares).
info->setDstCandidates(this, RBM_BYTE_REGS);
#endif // _TARGET_X86_
info->srcCount = appendBinaryLocationInfoToList(tree->AsOp());
}
#endif // !LEGACY_BACKEND
|
; A270684: First differences of number of active (ON,black) cells in n-th stage of growth of two-dimensional cellular automaton defined by "Rule 190", based on the 5-celled von Neumann neighborhood.
; 4,7,12,8,20,8,28,8,36,8,44,8,52,8,60,8,68,8,76,8,84,8,92,8,100,8,108,8,116,8,124,8,132,8,140,8,148,8,156,8,164,8,172,8,180,8,188,8,196,8,204,8,212,8,220,8,228,8,236,8,244,8,252,8,260,8,268,8,276,8,284,8,292,8,300,8,308,8,316,8,324,8,332,8,340,8,348,8,356,8,364,8,372,8,380,8,388,8,396,8,404,8,412,8,420,8,428,8,436,8,444,8,452,8,460,8,468,8,476,8,484,8,492,8,500,8,508,8
mov $2,$0
mov $3,2
lpb $3,1
mov $0,$2
sub $3,1
add $0,$3
sub $0,1
mov $6,$0
lpb $0,1
sub $0,1
mov $4,$0
mul $4,2
add $4,3
mov $7,$0
trn $0,1
mov $9,$6
add $9,$4
mov $5,$9
lpe
mul $5,$6
sub $5,$7
add $5,$6
mov $8,$3
lpb $8,1
mov $1,$5
sub $8,1
lpe
lpe
lpb $2,1
sub $1,$5
mov $2,0
lpe
trn $1,2
add $1,4
|
; A082694: Partial sums of A082693.
; 1,3,4,6,10,12,13,15,19,27,31,33,34,36,40,48,64,72,76,78,79,81,85,93,109,141,157,165,169,171,172,174,178,186,202,234,298,330,346,354,358,360,361,363,367,375,391,423,487,615,679,711,727,735,739,741,742,744
mov $5,$0
mov $7,$0
add $7,1
lpb $7,1
clr $0,5
mov $0,$5
sub $7,1
sub $0,$7
cal $0,4738 ; Concatenation of sequences (1,2,...,n-1,n,n-1,...,2) for n >= 2.
add $1,$0
mov $3,$1
cal $3,53208 ; Row sums of A053207.
mov $1,$3
div $1,7
add $1,1
add $6,$1
lpe
mov $1,$6
|
// Copyright 2021 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "google/cloud/bigtable/internal/defaults.h"
#include "google/cloud/bigtable/internal/client_options_defaults.h"
#include "google/cloud/bigtable/options.h"
#include "google/cloud/common_options.h"
#include "google/cloud/connection_options.h"
#include "google/cloud/grpc_options.h"
#include "google/cloud/internal/getenv.h"
#include "google/cloud/internal/user_agent_prefix.h"
#include "google/cloud/options.h"
#include <chrono>
#include <string>
namespace google {
namespace cloud {
namespace bigtable {
GOOGLE_CLOUD_CPP_INLINE_NAMESPACE_BEGIN
namespace internal {
namespace {
// As learned from experiments, idle gRPC connections enter IDLE state after 4m.
auto constexpr kDefaultMaxRefreshPeriod =
std::chrono::milliseconds(std::chrono::minutes(3));
// Applications with hundreds of clients seem to work better with a longer
// delay for the initial refresh. As there is no particular rush, start with 1m.
auto constexpr kDefaultMinRefreshPeriod =
std::chrono::milliseconds(std::chrono::minutes(1));
static_assert(kDefaultMinRefreshPeriod <= kDefaultMaxRefreshPeriod,
"The default period range must be valid");
// For background information on gRPC keepalive pings, see
// https://github.com/grpc/grpc/blob/master/doc/keepalive.md
// The default value for GRPC_KEEPALIVE_TIME_MS, how long before a keepalive
// ping is sent. A better name may have been "period", but consistency with the
// gRPC naming seems valuable.
auto constexpr kDefaultKeepaliveTime = std::chrono::seconds(30);
// The default value for GRPC_KEEPALIVE_TIMEOUT_MS, how long the sender (in
// this case the Cloud Bigtable C++ client library) waits for an acknowledgement
// for a keepalive ping.
auto constexpr kDefaultKeepaliveTimeout = std::chrono::seconds(10);
} // namespace
int DefaultConnectionPoolSize() {
// For better resource utilization and greater throughput, it is recommended
// to calculate the default pool size based on cores(CPU) available. However,
// as per C++11 documentation `std::thread::hardware_concurrency()` cannot be
// fully relied upon. It is only a hint and the value can be 0 if it is not
// well defined or not computable. Apart from CPU count, multiple channels
// can be opened for each CPU to increase throughput. The pool size is also
// capped so that servers with many cores do not create too many channels.
int cpu_count = std::thread::hardware_concurrency();
if (cpu_count == 0) return BIGTABLE_CLIENT_DEFAULT_CONNECTION_POOL_SIZE;
return (std::min)(BIGTABLE_CLIENT_DEFAULT_CONNECTION_POOL_SIZE_MAX,
cpu_count * BIGTABLE_CLIENT_DEFAULT_CHANNELS_PER_CPU);
}
Options DefaultOptions(Options opts) {
using ::google::cloud::internal::GetEnv;
auto emulator = GetEnv("BIGTABLE_EMULATOR_HOST");
if (emulator) {
opts.set<DataEndpointOption>(*emulator);
opts.set<AdminEndpointOption>(*emulator);
opts.set<InstanceAdminEndpointOption>(*emulator);
}
auto instance_admin_emulator =
GetEnv("BIGTABLE_INSTANCE_ADMIN_EMULATOR_HOST");
if (instance_admin_emulator) {
opts.set<InstanceAdminEndpointOption>(*std::move(instance_admin_emulator));
}
if (!opts.has<DataEndpointOption>()) {
opts.set<DataEndpointOption>("bigtable.googleapis.com");
}
if (!opts.has<AdminEndpointOption>()) {
opts.set<AdminEndpointOption>("bigtableadmin.googleapis.com");
}
if (!opts.has<InstanceAdminEndpointOption>()) {
opts.set<InstanceAdminEndpointOption>("bigtableadmin.googleapis.com");
}
if (!opts.has<GrpcCredentialOption>()) {
opts.set<GrpcCredentialOption>(emulator ? grpc::InsecureChannelCredentials()
: grpc::GoogleDefaultCredentials());
}
if (!opts.has<TracingComponentsOption>()) {
opts.set<TracingComponentsOption>(
::google::cloud::internal::DefaultTracingComponents());
}
if (!opts.has<GrpcTracingOptionsOption>()) {
opts.set<GrpcTracingOptionsOption>(
::google::cloud::internal::DefaultTracingOptions());
}
if (!opts.has<GrpcNumChannelsOption>()) {
opts.set<GrpcNumChannelsOption>(DefaultConnectionPoolSize());
}
auto const has_min = opts.has<MinConnectionRefreshOption>();
auto const has_max = opts.has<MaxConnectionRefreshOption>();
if (!has_min && !has_max) {
opts.set<MinConnectionRefreshOption>(kDefaultMinRefreshPeriod);
opts.set<MaxConnectionRefreshOption>(kDefaultMaxRefreshPeriod);
} else if (has_min && !has_max) {
opts.set<MaxConnectionRefreshOption>((std::max)(
opts.get<MinConnectionRefreshOption>(), kDefaultMaxRefreshPeriod));
} else if (!has_min && has_max) {
opts.set<MinConnectionRefreshOption>((std::min)(
opts.get<MaxConnectionRefreshOption>(), kDefaultMinRefreshPeriod));
} else {
// If the range is invalid, use the greater value as both the min and max
auto const p = opts.get<MinConnectionRefreshOption>();
if (p > opts.get<MaxConnectionRefreshOption>()) {
opts.set<MaxConnectionRefreshOption>(std::move(p));
}
}
using ::google::cloud::internal::GetIntChannelArgument;
auto c_arg = [](std::chrono::milliseconds ms) {
return static_cast<int>(ms.count());
};
auto& args = opts.lookup<GrpcChannelArgumentsNativeOption>();
if (!GetIntChannelArgument(args, GRPC_ARG_MAX_SEND_MESSAGE_LENGTH)) {
args.SetMaxSendMessageSize(BIGTABLE_CLIENT_DEFAULT_MAX_MESSAGE_LENGTH);
}
if (!GetIntChannelArgument(args, GRPC_ARG_MAX_RECEIVE_MESSAGE_LENGTH)) {
args.SetMaxReceiveMessageSize(BIGTABLE_CLIENT_DEFAULT_MAX_MESSAGE_LENGTH);
}
if (!GetIntChannelArgument(args, GRPC_ARG_KEEPALIVE_TIME_MS)) {
args.SetInt(GRPC_ARG_KEEPALIVE_TIME_MS, c_arg(kDefaultKeepaliveTime));
}
if (!GetIntChannelArgument(args, GRPC_ARG_KEEPALIVE_TIMEOUT_MS)) {
args.SetInt(GRPC_ARG_KEEPALIVE_TIMEOUT_MS, c_arg(kDefaultKeepaliveTimeout));
}
// Inserts our user-agent string at the front.
auto& products = opts.lookup<UserAgentProductsOption>();
products.insert(products.begin(),
::google::cloud::internal::UserAgentPrefix());
return opts;
}
Options DefaultDataOptions(Options opts) {
using ::google::cloud::internal::GetEnv;
auto user_project = GetEnv("GOOGLE_CLOUD_CPP_USER_PROJECT");
if (user_project && !user_project->empty()) {
opts.set<UserProjectOption>(*std::move(user_project));
}
if (!opts.has<AuthorityOption>()) {
opts.set<AuthorityOption>("bigtable.googleapis.com");
}
opts = DefaultOptions(std::move(opts));
return opts.set<EndpointOption>(opts.get<DataEndpointOption>());
}
Options DefaultInstanceAdminOptions(Options opts) {
opts = DefaultOptions(std::move(opts));
return opts.set<EndpointOption>(opts.get<InstanceAdminEndpointOption>());
}
Options DefaultTableAdminOptions(Options opts) {
opts = DefaultOptions(std::move(opts));
return opts.set<EndpointOption>(opts.get<AdminEndpointOption>());
}
} // namespace internal
GOOGLE_CLOUD_CPP_INLINE_NAMESPACE_END
} // namespace bigtable
} // namespace cloud
} // namespace google
|
.size 8000
.text@50
jp ltimaint
.text@100
jp lbegin
.data@143
c0
.text@150
lbegin:
xor a, a
ldff(0f), a
ldff(ff), a
ld a, f0
ldff(05), a
ldff(06), a
ld a, 04
ldff(ff), a
ld a, 05
ldff(07), a
ei
nop
halt
.text@1000
ltimaint:
nop
.text@1031
ld c, 05
ld a, 10
ldff(06), a
nop
ldff a, (c)
.text@104a
jp lprint_a
.text@7000
lprint_a:
push af
ld b, 91
call lwaitly_b
xor a, a
ldff(40), a
ld bc, 7a00
ld hl, 8000
ld d, 00
lprint_copytiles:
ld a, (bc)
inc bc
ld(hl++), a
dec d
jrnz lprint_copytiles
pop af
ld b, a
srl a
srl a
srl a
srl a
ld(9800), a
ld a, b
and a, 0f
ld(9801), a
ld a, c0
ldff(47), a
ld a, 80
ldff(68), a
ld a, ff
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
xor a, a
ldff(69), a
ldff(69), a
ldff(43), a
ld a, 91
ldff(40), a
lprint_limbo:
jr lprint_limbo
.text@7400
lwaitly_b:
ld c, 44
lwaitly_b_loop:
ldff a, (c)
cmp a, b
jrnz lwaitly_b_loop
ret
.data@7a00
00 00 7f 7f 41 41 41 41
41 41 41 41 41 41 7f 7f
00 00 08 08 08 08 08 08
08 08 08 08 08 08 08 08
00 00 7f 7f 01 01 01 01
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 01 01 01 01
3f 3f 01 01 01 01 7f 7f
00 00 41 41 41 41 41 41
7f 7f 01 01 01 01 01 01
00 00 7f 7f 40 40 40 40
7e 7e 01 01 01 01 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 41 41 41 41 7f 7f
00 00 7f 7f 01 01 02 02
04 04 08 08 10 10 10 10
00 00 3e 3e 41 41 41 41
3e 3e 41 41 41 41 3e 3e
00 00 7f 7f 41 41 41 41
7f 7f 01 01 01 01 7f 7f
00 00 08 08 22 22 41 41
7f 7f 41 41 41 41 41 41
00 00 7e 7e 41 41 41 41
7e 7e 41 41 41 41 7e 7e
00 00 3e 3e 41 41 40 40
40 40 40 40 41 41 3e 3e
00 00 7e 7e 41 41 41 41
41 41 41 41 41 41 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 40 40 40 40
7f 7f 40 40 40 40 40 40
|
CGAHeart2 label byte
word C_BLACK
Bitmap <67,41,BMC_PACKBITS,BMF_MONO>
db 0xf8, 0x00
db 0xf8, 0x00
db 0x08, 0x0f, 0xe0, 0x00, 0x1f, 0x1f, 0x00, 0x00,
0xee, 0x00
db 0x08, 0x18, 0x30, 0x00, 0x2a, 0xaa, 0x80, 0x01,
0x55, 0x00
db 0x08, 0x00, 0x70, 0x00, 0x35, 0x55, 0x80, 0x01,
0xab, 0x00
db 0x08, 0x01, 0xc0, 0x00, 0x1a, 0xab, 0x00, 0x00,
0xd6, 0x00
db 0x08, 0x07, 0x00, 0x00, 0x07, 0x5c, 0x00, 0x00,
0x6c, 0x00
db 0x08, 0x1c, 0x30, 0x00, 0x01, 0xb0, 0x00, 0x00,
0x10, 0x00
db 0x04, 0x1f, 0xf0, 0x00, 0x00, 0x40, 0xfd, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
db 0xfd, 0x00, 0x04, 0x40, 0x00, 0x01, 0xff, 0x00
db 0x08, 0x01, 0x00, 0x00, 0x01, 0xb0, 0x00, 0x01,
0x87, 0x00
db 0x08, 0x06, 0xc0, 0x00, 0x07, 0x5c, 0x00, 0x00,
0x1c, 0x00
db 0x08, 0x0d, 0x60, 0x00, 0x1a, 0xab, 0x00, 0x00,
0x70, 0x00
db 0x08, 0x1a, 0xb0, 0x00, 0x35, 0x55, 0x80, 0x01,
0xc0, 0x00
db 0x08, 0x15, 0x50, 0x00, 0x2a, 0xaa, 0x80, 0x01,
0x83, 0x00
db 0x08, 0x0e, 0xe0, 0x00, 0x1f, 0x1f, 0x00, 0x00,
0xfe, 0x00
db 0xf8, 0x00
db 0xf8, 0x00
|
; A284395: Positions of 1 in A284394.
; 2,8,17,23,32,41,47,56,62,71,80,86,95,104,110,119,125,134,143,149,158,164,173,182,188,197,206,212,221,227,236,245,251,260,269,275,284,290,299,308,314,323,329,338,347,353,362,371,377,386,392,401,410,416,425,431,440,449,455,464,473,479,488,494,503,512,518,527,536,542,551,557,566,575,581,590,596,605,614,620,629,638,644,653,659,668,677,683,692,701,707,716,722,731,740,746,755,761,770,779,785,794,803,809,818,824,833,842,848,857,863,872,881,887,896,905,911,920,926,935,944,950,959,968,974,983,989,998,1007,1013,1022,1028,1037,1046,1052,1061,1070,1076,1085,1091,1100,1109,1115,1124,1130,1139,1148,1154,1163,1172,1178,1187,1193,1202,1211,1217,1226,1235,1241,1250,1256,1265,1274,1280,1289,1295,1304,1313,1319,1328,1337,1343,1352,1358,1367,1376,1382,1391,1400,1406,1415,1421,1430,1439,1445,1454,1460,1469,1478,1484,1493,1502,1508,1517,1523,1532,1541,1547,1556,1562,1571,1580,1586,1595,1604,1610,1619,1625,1634,1643,1649,1658,1667,1673,1682,1688,1697,1706,1712,1721,1727,1736,1745,1751,1760,1769,1775,1784,1790,1799,1808,1814,1823,1832,1838,1847,1853,1862,1871,1877,1886,1892,1901,1910,1916,1925,1934,1940,1949,1955
mov $7,$0
mov $9,$0
add $9,1
mov $10,$0
lpb $9,1
mov $0,$7
sub $9,1
sub $0,$9
mov $3,$0
mov $5,2
lpb $5,1
mov $0,$3
sub $5,1
add $0,$5
sub $0,1
mov $1,$0
pow $0,2
lpb $0,1
sub $0,$1
trn $0,1
add $1,2
lpe
mul $1,32
mov $6,$5
lpb $6,1
mov $4,$1
sub $6,1
lpe
lpe
lpb $3,1
mov $3,0
sub $4,$1
lpe
mov $1,$4
sub $1,16
div $1,32
mul $1,3
add $1,3
add $8,$1
lpe
mov $1,$8
sub $1,5
div $1,3
add $1,2
mov $2,$10
mul $2,3
add $1,$2
sub $1,3
div $1,2
mul $1,3
add $1,2
|
; A099425: Expansion of (1+x^2)/(1-2*x-x^2).
; 1,2,6,14,34,82,198,478,1154,2786,6726,16238,39202,94642,228486,551614,1331714,3215042,7761798,18738638,45239074,109216786,263672646,636562078,1536796802,3710155682,8957108166,21624372014,52205852194,126036076402,304278004998,734592086398,1773462177794,4281516441986,10336495061766,24954506565518,60245508192802,145445522951122,351136554095046,847718631141214,2046573816377474,4940866263896162
mov $2,1
lpb $0
sub $0,1
add $3,$2
mov $1,$3
add $3,$2
mov $2,$1
lpe
add $1,$2
|
; A131783: A000012 * (A004736 + A002260 - I).
; Submitted by Christian Krause
; 1,4,2,8,6,3,13,11,8,4,19,17,14,10,5,26,24,21,17,12,6,34,32,29,25,20,14,7,43,41,38,34,29,23,16,8,53,51,48,44,39,33,26,18,9,64,62,59,55,50,44,37,29,20,10
lpb $0
add $1,1
sub $0,$1
lpe
sub $1,$0
add $0,2
mul $0,2
add $0,$1
add $1,1
mul $1,$0
mov $0,$1
div $0,2
sub $0,1
|
// NES DXYCP using sprites
/// @file
/// Nintendo Entertainment System (NES
///
/// https://en.wikipedia.org/wiki/Nintendo_Entertainment_System_(Model_NES-101)
/// https://github.com/gregkrsak/first_nes
/// @file
/// Ricoh 2C02 - NES Picture Processing Unit (PPU)
///
/// Ricoh RP2C02 (NTSC version) / RP2C07 (PAL version),
/// https://en.wikipedia.org/wiki/Picture_Processing_Unit
/// https://wiki.nesdev.com/w/index.php/PPU_registers
/// http://nesdev.com/2C02%20technical%20reference.TXT
/// Based on: https://github.com/gregkrsak/first_nes written by Greg M. Krsak, 2018.
.cpu _6502
// Nintendo Entertainment System (NES) ROM (Mapper 0 NROM, Vertical Mirroring)
// https://sadistech.com/nesromtool/romdoc.html
// https://forums.nesdev.com/viewtopic.php?f=2&t=9896
// https://github.com/gregkrsak/first_nes
.file [name="nes-dxycp.nes", type="bin", segments="NesRom"]
.file [name="nes-dxycp.nes_hdr", type="bin", segments="Header"]
.file [name="nes-dxycp.nes_prg", type="bin", segments="ProgramRom"]
.file [name="nes-dxycp.nes_chr", type="bin", segments="CharacterRom"]
.segmentdef Header [ start=$0000, min=$0000, max=$000f, fill ]
.segmentdef Tiles [ start=$0000, min=$0000, max=$1fff, fill ]
.segmentdef Code [ start=$c000, min=$c000, max=$fff9 ]
.segmentdef Data [ startAfter="Code", min=$c000, max=$fff9 ]
.segmentdef Vectors [ start=$fffa, min=$fffa, max=$ffff ]
.segmentdef GameRam [start=$200,max=$7ff, virtual]
.segmentdef ProgramRom [ segments="Code, Data, Vectors" ]
.segmentdef CharacterRom [ segments="Tiles" ]
.segmentdef NesRom
.segment NesRom
.segmentout [ segments="Header" ]
.segmentout [ segments="ProgramRom" ]
.segmentout [ segments="CharacterRom" ]
.segment Header
.text @"NES\$1a"
.byte $01 // 1x 16KB ROM (PRG)
.byte $01 // 1x 8KB VROM (CHR)
.byte %00000001 // Mapper nibble 0000 == No mapping (a simple 16KB PRG + 8KB CHR game)
// Mirroring nibble 0001 == Vertical mirroring only
.const OFFSET_STRUCT_SPRITEDATA_TILE = 1
.const OFFSET_STRUCT_SPRITEDATA_ATTRIBUTES = 2
.const OFFSET_STRUCT_SPRITEDATA_X = 3
.const OFFSET_STRUCT_RICOH_2C02_OAMADDR = 3
.const OFFSET_STRUCT_RICOH_2A03_OAMDMA = $14
.const OFFSET_STRUCT_RICOH_2A03_DMC_FREQ = $10
.const OFFSET_STRUCT_RICOH_2C02_PPUMASK = 1
.const OFFSET_STRUCT_RICOH_2C02_PPUSTATUS = 2
.const OFFSET_STRUCT_RICOH_2A03_JOY1 = $16
.const OFFSET_STRUCT_RICOH_2C02_PPUADDR = 6
.const OFFSET_STRUCT_RICOH_2C02_PPUDATA = 7
.const OFFSET_STRUCT_RICOH_2C02_PPUSCROLL = 5
.const SIZEOF_CHAR = 1
/// $2000-$23bf $03c0 Name table 0
.label PPU_NAME_TABLE_0 = $2000
/// $23c0-$23ff $0040 Attribute table 0
.label PPU_ATTRIBUTE_TABLE_0 = $23c0
/// $3000-$3eff $0f00 Mirrors of $2000-$2eff
/// $3f00-$3f1f $0020 Palette RAM indexes
.label PPU_PALETTE = $3f00
/// PPU Status Register for reading in ASM
.label PPU_PPUSTATUS = $2002
/// APU Frame Counter
/// generates low-frequency clocks for the channels and an optional 60 Hz interrupt.
/// https://wiki.nesdev.com/w/index.php/APU_Frame_Counter
/// ------+-----+---------------------------------------------------------------
/// $4017 | W | FR_COUNTER Frame Counter Set mode and interrupt
/// ------+-----+---------------------------------------------------------------
/// | 7 | Sequencer mode: 0 selects 4-step sequence, 1 selects 5-step sequence
/// | 6 | Interrupt inhibit flag. If set, the frame interrupt flag is cleared, otherwise it is unaffected.
/// ------+-----+---------------------------------------------------------------
/// Side effects After 3 or 4 CPU clock cycles*, the timer is reset.
/// If the mode flag is set, then both "quarter frame" and "half frame" signals are also generated.
.label FR_COUNTER = $4017
/// Pointer to the start of RAM memory
.label MEMORY = 0
/// NES Picture Processing Unit (PPU)
.label PPU = $2000
/// NES CPU and audion processing unit (APU)
.label APU = $4000
// Index into the Y sine
.label y_sin_idx = $e
// Index into the X sine
.label x_sin_idx = $f
// Index into the small X sine
.label x_sin_idx_2 = $10
.segment Code
__start: {
// volatile char y_sin_idx = 0
lda #0
sta.z y_sin_idx
// volatile char x_sin_idx = 73
lda #$49
sta.z x_sin_idx
// volatile char x_sin_idx_2 = 82
lda #$52
sta.z x_sin_idx_2
jsr main
rts
}
// NMI Called when the PPU refreshes the screen (also known as the V-Blank period)
vblank: {
.label __17 = $a
.label __19 = $a
.label __23 = 9
.label __25 = 9
.label __28 = $d
.label y_idx = $c
.label x_idx = $a
.label x_idx_2 = 9
.label s = $b
pha
txa
pha
tya
pha
// PPU->PPUSCROLL = 0
// Set scroll
lda #0
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUSCROLL
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUSCROLL
// PPU->OAMADDR = 0
sta PPU+OFFSET_STRUCT_RICOH_2C02_OAMADDR
// APU->OAMDMA = BYTE1(spriteBuffer)
lda #>SPRITE_BUFFER
sta APU+OFFSET_STRUCT_RICOH_2A03_OAMDMA
// char joy = readJoy1()
// Read controller 1
jsr readJoy1
// if(joy)
cmp #0
beq __b1
__breturn:
// }
pla
tay
pla
tax
pla
rti
__b1:
// char y_idx = y_sin_idx++
// Update sprite positions
lda.z y_sin_idx
sta.z y_idx
inc.z y_sin_idx
// (x_sin_idx==238) ? 0 : x_sin_idx+1
lda #$ee
cmp.z x_sin_idx
beq __b2
ldx.z x_sin_idx
inx
jmp __b3
__b2:
ldx #0
__b3:
// x_sin_idx = (x_sin_idx==238) ? 0 : x_sin_idx+1
stx.z x_sin_idx
// char x_idx = x_sin_idx
txa
sta.z x_idx
// (x_sin_idx_2==88) ? 0 : x_sin_idx_2+1
lda #$58
cmp.z x_sin_idx_2
beq __b4
ldx.z x_sin_idx_2
inx
jmp __b5
__b4:
ldx #0
__b5:
// x_sin_idx_2 = (x_sin_idx_2==88) ? 0 : x_sin_idx_2+1
stx.z x_sin_idx_2
// char x_idx_2 = x_sin_idx_2
txa
sta.z x_idx_2
lda #0
sta.z s
__b6:
// for(char s=0;s<0x40;s++)
lda.z s
cmp #$40
bcc __b7
jmp __breturn
__b7:
// SPRITE_BUFFER[s].y = SINTABLE_240[y_idx]
lda.z s
asl
asl
sta.z __28
ldy.z y_idx
lda SINTABLE_240,y
ldy.z __28
sta SPRITE_BUFFER,y
// y_idx -= 4
lax.z y_idx
axs #4
stx.z y_idx
// SINTABLE_184[x_idx] + SINTABLE_64[x_idx_2]
ldy.z x_idx
lda SINTABLE_184,y
ldy.z x_idx_2
clc
adc SINTABLE_64,y
// SPRITE_BUFFER[s].x = SINTABLE_184[x_idx] + SINTABLE_64[x_idx_2]
ldy.z __28
sta SPRITE_BUFFER+OFFSET_STRUCT_SPRITEDATA_X,y
// (x_idx<3) ? x_idx+236 : x_idx-3
lda.z x_idx
cmp #3
bcc __b8
lax.z __17
axs #3
stx.z __17
__b10:
// (x_idx_2>=86) ? x_idx_2-86 : x_idx_2+3
lda.z x_idx_2
cmp #$56
bcs __b11
lax.z __23
axs #-[3]
stx.z __23
__b13:
// for(char s=0;s<0x40;s++)
inc.z s
jmp __b6
__b11:
// (x_idx_2>=86) ? x_idx_2-86 : x_idx_2+3
lax.z __25
axs #$56
stx.z __25
jmp __b13
__b8:
// (x_idx<3) ? x_idx+236 : x_idx-3
lax.z __19
axs #-[$ec]
stx.z __19
jmp __b10
}
// RESET Called when the NES is reset, including when it is turned on.
main: {
// asm
cld
ldx #$ff
txs
// PPU->PPUCTRL = 0
lda #0
sta PPU
// PPU->PPUMASK = 0
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUMASK
// *FR_COUNTER = 0b01000000
lda #$40
sta FR_COUNTER
// APU->DMC_FREQ = 0b01000000
sta APU+OFFSET_STRUCT_RICOH_2A03_DMC_FREQ
// asm
lda PPU_PPUSTATUS
initNES1_waitForVBlank1:
// PPU->PPUSTATUS&0x80
lda #$80
and PPU+OFFSET_STRUCT_RICOH_2C02_PPUSTATUS
// while(!(PPU->PPUSTATUS&0x80))
cmp #0
beq initNES1_waitForVBlank1
ldx #0
initNES1___b1:
// (MEMORY+0x000)[i] = 0
lda #0
sta.z MEMORY,x
// (MEMORY+0x100)[i] = 0
sta MEMORY+$100,x
// (MEMORY+0x200)[i] = 0
sta MEMORY+$200,x
// (MEMORY+0x300)[i] = 0
sta MEMORY+$300,x
// (MEMORY+0x400)[i] = 0
sta MEMORY+$400,x
// (MEMORY+0x500)[i] = 0
sta MEMORY+$500,x
// (MEMORY+0x600)[i] = 0
sta MEMORY+$600,x
// (MEMORY+0x700)[i] = 0
sta MEMORY+$700,x
// while (++i)
inx
cpx #0
bne initNES1___b1
initNES1_waitForVBlank2:
// PPU->PPUSTATUS&0x80
lda #$80
and PPU+OFFSET_STRUCT_RICOH_2C02_PPUSTATUS
// while(!(PPU->PPUSTATUS&0x80))
cmp #0
beq initNES1_waitForVBlank2
// asm
lda PPU_PPUSTATUS
// ppuDataTransfer(PPU_PALETTE, PALETTE, sizeof(PALETTE))
// Transfer the palette
jsr ppuDataTransfer
// ppuDataFill(PPU_NAME_TABLE_0, '*', 32*30)
// Fill the PPU attribute table
ldx #'*'
lda #<$20*$1e
sta.z ppuDataFill.size
lda #>$20*$1e
sta.z ppuDataFill.size+1
lda #<PPU_NAME_TABLE_0
sta.z ppuDataFill.ppuDataPrepare1_ppuData
lda #>PPU_NAME_TABLE_0
sta.z ppuDataFill.ppuDataPrepare1_ppuData+1
jsr ppuDataFill
// ppuDataFill(PPU_ATTRIBUTE_TABLE_0, 0, 0x40)
ldx #0
lda #<$40
sta.z ppuDataFill.size
lda #>$40
sta.z ppuDataFill.size+1
lda #<PPU_ATTRIBUTE_TABLE_0
sta.z ppuDataFill.ppuDataPrepare1_ppuData
lda #>PPU_ATTRIBUTE_TABLE_0
sta.z ppuDataFill.ppuDataPrepare1_ppuData+1
jsr ppuDataFill
ldx #0
// Initialize Sprite Buffer with the SPRITE data
__b1:
// for(char s=0;s<0x40;s++)
cpx #$40
bcc __b2
// PPU->PPUCTRL = 0b10000000
lda #$80
sta PPU
// PPU->PPUMASK = 0b00011110
lda #$1e
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUMASK
__b3:
// Infinite loop
jmp __b3
__b2:
// SPRITE_BUFFER[s] = { 0, MESSAGE[s], 0b00000010, 0 }
txa
asl
asl
tay
lda #0
sta SPRITE_BUFFER,y
lda MESSAGE,x
sta SPRITE_BUFFER+OFFSET_STRUCT_SPRITEDATA_TILE,y
lda #2
sta SPRITE_BUFFER+OFFSET_STRUCT_SPRITEDATA_ATTRIBUTES,y
lda #0
sta SPRITE_BUFFER+OFFSET_STRUCT_SPRITEDATA_X,y
// for(char s=0;s<0x40;s++)
inx
jmp __b1
}
// Read Standard Controller #1
// Returns a byte representing the pushed buttons
// - bit 0: right
// - bit 1: left
// - bit 2: down
// - bit 3: up
// - bit 4: start
// - bit 5: select
// - bit 6: B
// - bit 7: A
readJoy1: {
.label __1 = 8
// APU->JOY1 = 1
// Latch the controller buttons
lda #1
sta APU+OFFSET_STRUCT_RICOH_2A03_JOY1
// APU->JOY1 = 0
lda #0
sta APU+OFFSET_STRUCT_RICOH_2A03_JOY1
tax
__b1:
// for(char i=0;i<8;i++)
cpx #8
bcc __b2
// }
rts
__b2:
// joy<<1
asl
sta.z __1
// APU->JOY1&1
lda #1
and APU+OFFSET_STRUCT_RICOH_2A03_JOY1
// joy = joy<<1 | APU->JOY1&1
ora.z __1
// for(char i=0;i<8;i++)
inx
jmp __b1
}
// Transfer a number of bytes from the CPU memory to the PPU memory
// - ppuData : Pointer in the PPU memory
// - cpuData : Pointer to the CPU memory (RAM of ROM)
// - size : The number of bytes to transfer
// void ppuDataTransfer(void * const ppuData, void * const cpuData, unsigned int size)
ppuDataTransfer: {
.const size = $20*SIZEOF_CHAR
.label ppuData = PPU_PALETTE
.label cpuData = PALETTE
// Transfer to PPU
.label cpuSrc = 6
.label i = 4
// PPU->PPUADDR = BYTE1(ppuData)
lda #>ppuData
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUADDR
// PPU->PPUADDR = BYTE0(ppuData)
lda #0
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUADDR
lda #<cpuData
sta.z cpuSrc
lda #>cpuData
sta.z cpuSrc+1
lda #<0
sta.z i
sta.z i+1
__b1:
// for(unsigned int i=0;i<size;i++)
lda.z i+1
cmp #>size
bcc __b2
bne !+
lda.z i
cmp #<size
bcc __b2
!:
// }
rts
__b2:
// ppuDataPut(*cpuSrc++)
ldy #0
lda (cpuSrc),y
// PPU->PPUDATA = val
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUDATA
// ppuDataPut(*cpuSrc++);
inc.z cpuSrc
bne !+
inc.z cpuSrc+1
!:
// for(unsigned int i=0;i<size;i++)
inc.z i
bne !+
inc.z i+1
!:
jmp __b1
}
// Fill a number of bytes in the PPU memory
// - ppuData : Pointer in the PPU memory
// - size : The number of bytes to transfer
// void ppuDataFill(void * const ppuData, __register(X) char val, __zp(6) unsigned int size)
ppuDataFill: {
.label ppuDataPrepare1_ppuData = 4
.label i = 2
.label size = 6
// BYTE1(ppuData)
lda.z ppuDataPrepare1_ppuData+1
// PPU->PPUADDR = BYTE1(ppuData)
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUADDR
// BYTE0(ppuData)
lda.z ppuDataPrepare1_ppuData
// PPU->PPUADDR = BYTE0(ppuData)
sta PPU+OFFSET_STRUCT_RICOH_2C02_PPUADDR
lda #<0
sta.z i
sta.z i+1
// Transfer to PPU
__b1:
// for(unsigned int i=0;i<size;i++)
lda.z i+1
cmp.z size+1
bcc ppuDataPut1
bne !+
lda.z i
cmp.z size
bcc ppuDataPut1
!:
// }
rts
ppuDataPut1:
// PPU->PPUDATA = val
stx PPU+OFFSET_STRUCT_RICOH_2C02_PPUDATA
// for(unsigned int i=0;i<size;i++)
inc.z i
bne !+
inc.z i+1
!:
jmp __b1
}
.segment Data
// The DXYCP message 0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef
MESSAGE: .text "rex-of-camelot-presents-a-dxycp-on-nintendo-entertainment-system"
// Color Palette
PALETTE: .byte 1, $21, $f, $30, 1, $21, $f, $30, 1, $21, $f, $30, 1, $21, $f, $30, 1, $f, $30, 8, 1, $f, $18, 8, 1, $30, $37, $1a, $f, $f, $f, $f
// Sine Table (0-239)
SINTABLE_240:
.fill $100, round(115.5+107.5*sin(2*PI*i/256))
// Sine Table (0-63)
SINTABLE_64:
.fill 89, round(52.5+52.5*sin(2*PI*i/89))
// Sine Table (0-183)
SINTABLE_184:
.fill 239, round(71.5+71.5*sin(2*PI*i/239))
.segment Tiles
TILES:
.var filechargen = LoadBinary("characters.901225-01.bin")
.for(var c=0; c<256; c++) {
// Plane 0
.fill 8, filechargen.get(c*8+i)
// Plane 1
.fill 8, 0
}
.segment GameRam
.align $100
SPRITE_BUFFER: .fill 4*$100, 0
.segment Vectors
VECTORS: .word vblank, main, 0
|
start:
ldx #0
c:lda bottombar,x
cmp #$ff
beq init
sta $4e0,x
sta $5e0,x
inx
jmp c
init:
jsr initDraw
lda #0
sta $10 ; scrptr
sta $11 ; txtptr
loop:
jsr drawMain
jsr putfont
jsr scrollarea
jmp loop
scrollarea:
ldx #0
g:lda $521,x
sta $520,x
lda $541,x
sta $540,x
lda $561,x
sta $560,x
lda $581,x
sta $580,x
lda $5a1,x
sta $5a0,x
inx
cpx #31
bne g
rts
putfont:
lda $10 ; scrptr
cmp #0
bne noNext
inc $11
ldx $11
lda scrolltext,x
tax
lda fontSize,x
sta $10
noNext:
dec $10
ldx $11
lda scrolltext,x
cmp #$ff
bne notResetText
lda #0
sta $10
sta $11
rts
notResetText:
asl
tax
lda fontlookup,x
sta $2
inx
lda fontlookup,x
sta $3
lda #<fonts
clc
adc $2
sta $0
lda #>fonts
adc $3
sta $1
ldy $10
lda ($00),y
sta $53f
tya
clc
adc #6
tay
lda ($00),y
sta $55f
tya
clc
adc #6
tay
lda ($00),y
sta $57f
tya
clc
adc #6
tay
lda ($00),y
sta $59f
tya
clc
adc #6
tay
lda ($00),y
sta $5bf
rts
initDraw:
lda #<picture
sta $20
lda #>picture
sta $21
lda #$00
sta $22
lda #$02
sta $23
ldx #$0
rts
drawMain:
ldx #0
lda ($20,x)
cmp #$ff
beq done
sta ($22,x)
inc $20
lda $20
cmp #$00
bne n1
inc $21
n1:
inc $22
lda $22
cmp #$00
bne done
lda $23
cmp #$05
beq done
inc $23
done:
rts
picture:
dcb 0,0,0,0,0,0,0,0,0,$b,$b,$c,$f,$f,$f,$f
dcb $f,$b,0,0,0,$b,$b,$c,$c,$f,$f,$b,0,0,0,0
dcb 0,0,0,0,0,0,0,0,0,$b,$c,$c,$f,$c,$f,$f
dcb $b,$b,$b,$b,$b,0,$b,$b,$c,$f,$f,$c,0,0,0,0
dcb 0,0,0,0,0,0,0,$b,0,$c,$b,$f,$c,$f,$f,$c
dcb $c,$b,0,$b,$c,$c,$c,$f,$f,1,$f,$c,$b,0,0,0
dcb 0,0,0,0,0,0,0,0,$b,$b,$c,$c,$c,$f,$f,$f
dcb $c,$c,$c,$c,$c,$c,$f,$c,$f,$f,$f,$f,$b,0,0,0
dcb 0,0,0,0,0,0,0,$b,0,0,$b,$c,$c,$f,$f,$f
dcb $f,$c,$f,$f,$f,$f,$f,$f,$f,1,$f,$f,$c,0,0,0
dcb 0,0,0,0,0,0,0,0,0,$b,$b,$b,$c,$f,$f,1
dcb $f,$f,$c,$f,$f,$f,1,$f,$f,$f,$f,$f,$f,0,0,0
dcb 0,0,0,0,0,0,0,0,0,$b,$b,$b,$b,$c,$f,1
dcb $f,$f,$f,$f,$f,$f,$f,$f,1,$f,$f,$f,$f,$b,0,0
dcb 0,0,0,0,0,0,0,0,$b,0,$b,$c,$b,$c,$c,1
dcb 1,$f,1,$f,1,$f,1,$f,$f,1,$f,$f,1,$b,0,0
dcb 0,0,0,0,0,0,0,$b,$b,$b,$c,$c,$b,$c,$f,1
dcb 1,1,$f,$f,1,$f,$f,1,$f,$f,$f,$f,1,$c,0,0
dcb 0,0,0,0,0,0,0,$b,$b,$c,$c,$c,$b,$c,$c,$f
dcb 1,1,1,$f,$f,1,$f,1,$f,1,$f,$f,1,$c,0,0
dcb 0,0,0,0,0,$b,$b,$b,$c,$c,$c,$f,$c,$c,$f,$f
dcb 1,1,1,1,$f,$f,$f,1,$f,1,$f,$f,$f,$f,0,0
dcb 0,0,0,0,0,0,$b,$c,$c,$c,$f,$c,$f,$c,$f,$f
dcb 1,1,1,1,1,$f,$f,1,$f,$f,$f,$f,1,$f,$b,0
dcb 0,0,0,0,$b,$b,$b,$c,$c,$f,$c,$f,$f,$c,$f,$f
dcb 1,1,1,1,1,$f,$f,$f,1,$f,$f,$f,1,$c,$b,$b
dcb 0,0,0,0,$b,$b,$c,$f,$c,$f,$f,$f,$f,$f,$c,$f
dcb 1,1,1,1,1,$f,$f,$f,1,$f,$f,$f,$f,$f,$b,$b
dcb 0,0,0,0,$b,$c,$c,$c,$f,$f,$f,$f,$f,$f,$f,$f
dcb $f,1,1,1,$f,$b,$f,$f,$f,1,$f,$f,$f,$f,$b,$b
dcb 0,0,0,0,$b,$c,$c,$f,$c,$f,$f,$f,$f,$f,$f,$f
dcb $f,$f,$f,$c,$b,$f,$f,1,$f,$f,$f,$f,$f,$f,$c,$b
dcb 0,0,0,0,$b,$b,$c,$c,$f,$c,$f,$f,$f,$f,$f,$f
dcb $c,$c,$b,$c,$c,$f,$f,1,$c,$c,$f,$f,$f,$f,$c,$b
dcb 0,0,0,0,$b,$b,$c,$c,$c,$f,$f,$f,$f,$f,$f,$f
dcb $f,$f,$f,$f,$f,1,$f,$c,$b,$f,$c,$f,$c,$f,$c,$b
dcb 0,0,0,0,0,$b,$c,$c,$c,$c,$f,$f,$f,$f,$f,$f
dcb $f,$f,$f,$f,$f,$c,$b,$c,$c,$c,$f,$f,$c,$f,$c,$c
dcb 0,0,0,0,0,$b,$b,$c,$c,$c,$c,$c,$f,$f,$f,$f
dcb $f,$f,$f,$c,$b,$b,$c,$c,$c,$f,$c,$f,$f,$f,$c,$b
dcb 0,0,0,0,0,$b,$b,$b,$b,$c,$c,$f,$c,$f,$f,$f
dcb $c,$c,$b,$b,$b,$c,$b,$b,$c,$c,$f,$c,$c,$f,$c,$c
dcb 0,0,0,0,0,0,$b,$b,$c,$b,$c,$c,$c,$c,$c,$c
dcb $b,$b,$b,$b,$c,$b,$b,$c,$c,$f,$f,$f,$c,$c,$c,$b
dcb 0,0,0,0,0,0,0,0,$b,$b,$b,$c,$c,$c,$c,$c
dcb $c,$c,$b,$b,$b,$b,$c,$c,$f,$f,$f,$c,$c,$c,$c,$c
dcb $ff
fontSize:
dcb 5,5,5,5,5,5,5,5 ;abcdefgh
dcb 2,5,5,5,6,6,5,5 ;ijklmnop
dcb 6,5,5,4,5,6,6,6 ;qrstuvwx
dcb 6,5,2,3 ;yz.[SPACE]
;
; a=0, b=1, c=2, d=3....
;
scrolltext:
dcb 0
dcb 14,13,11,24,27 ; "only "
dcb 03,04,15,19,07,27 ; "depth "
dcb 12,0,10,4,18,27 ; "makes "
dcb 8,19,27 ; "it "
dcb 15,14,18,18,8,1,11,4 ; "possible"
dcb 26,26,26 ; "..."
dcb 19,7,8,18,27 ; "this "
dcb 8,18,27 ; "is "
dcb 19,7,4,27 ; "the "
dcb 5,8,17,18,19,27 ; "first "
dcb 3,4,12,14,27 ; "demo "
dcb 12,0,3,4,27 ; "made "
dcb 8,13,27 ; "in "
dcb 19,7,8,18,27 ; "this "
dcb 4,13,21,26,26,26,26,27 ; "env.... "
dcb 7,14,15,4,27 ; "hope "
dcb 24,14,20,27 ; "you "
dcb 11,8,10,4,27 ; "like "
dcb 8,19,26,26,26,27,27 ; "it... "
dcb 22,22,22,26 ; "www."
dcb 3,4,15,19,7,26 ; "depth."
dcb 14,17,6,27,27,27,27,27 ; "org "
dcb $ff ; end of text
fontlookup:
dcb $00,$00 ;a
dcb $20,$00 ;b
dcb $40,$00 ;c
dcb $60,$00 ;d
dcb $80,$00 ;e
dcb $a0,$00 ;f
dcb $c0,$00 ;g
dcb $e0,$00 ;h
dcb $00,$01 ;i
dcb $20,$01 ;j
dcb $40,$01 ;k
dcb $60,$01 ;l
dcb $80,$01 ;m
dcb $a0,$01 ;n
dcb $c0,$01 ;o
dcb $e0,$01 ;p
dcb $00,$02 ;q
dcb $20,$02 ;r
dcb $40,$02 ;s
dcb $60,$02 ;t
dcb $80,$02 ;u
dcb $a0,$02 ;v
dcb $c0,$02 ;w
dcb $e0,$02 ;x
dcb $00,$03 ;y
dcb $20,$03 ;z
dcb $40,$03 ;.
dcb $60,$03 ;" "
fonts:
dcb 0,1,1,0,0,0
dcb 1,0,0,1,0,0
dcb 1,1,1,1,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 0,0
dcb 0,1,1,1,0,0
dcb 1,0,0,1,0,0
dcb 0,1,1,1,0,0
dcb 1,0,0,1,0,0
dcb 0,1,1,1,0,0
dcb 0,0
dcb 0,1,1,0,0,0
dcb 1,0,0,1,0,0
dcb 0,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 0,1,1,0,0,0
dcb 0,0
dcb 0,1,1,1,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 0,1,1,1,0,0
dcb 0,0
dcb 1,1,1,1,0,0
dcb 0,0,0,1,0,0
dcb 0,1,1,1,0,0
dcb 0,0,0,1,0,0
dcb 1,1,1,1,0,0
dcb 0,0
dcb 1,1,1,1,0,0
dcb 0,0,0,1,0,0
dcb 0,1,1,1,0,0
dcb 0,0,0,1,0,0
dcb 0,0,0,1,0,0
dcb 0,0
dcb 1,1,1,0,0,0
dcb 0,0,0,1,0,0
dcb 1,1,0,1,0,0
dcb 1,0,0,1,0,0
dcb 1,1,1,0,0,0
dcb 0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 1,1,1,1,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 0,0
dcb 1,0,0,0,0,0
dcb 1,0,0,0,0,0
dcb 1,0,0,0,0,0
dcb 1,0,0,0,0,0
dcb 1,0,0,0,0,0
dcb 0,0
dcb 1,0,0,0,0,0
dcb 1,0,0,0,0,0
dcb 1,0,0,0,0,0
dcb 1,0,0,1,0,0
dcb 0,1,1,0,0,0
dcb 0,0
dcb 1,0,0,1,0,0
dcb 0,1,0,1,0,0
dcb 0,0,1,1,0,0
dcb 0,1,0,1,0,0
dcb 1,0,0,1,0,0
dcb 0,0
dcb 0,0,0,1,0,0
dcb 0,0,0,1,0,0
dcb 0,0,0,1,0,0
dcb 0,0,0,1,0,0
dcb 1,1,1,1,0,0
dcb 0,0
dcb 1,0,0,0,1,0
dcb 1,1,0,1,1,0
dcb 1,0,1,0,1,0
dcb 1,0,0,0,1,0
dcb 1,0,0,0,1,0
dcb 0,0
dcb 1,0,0,0,1,0
dcb 1,0,0,1,1,0
dcb 1,0,1,0,1,0
dcb 1,1,0,0,1,0
dcb 1,0,0,0,1,0
dcb 0,0
dcb 0,1,1,0,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 0,1,1,0,0,0
dcb 0,0
dcb 0,1,1,1,0,0
dcb 1,0,0,1,0,0
dcb 0,1,1,1,0,0
dcb 0,0,0,1,0,0
dcb 0,0,0,1,0,0
dcb 0,0
dcb 0,1,1,0,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 0,1,0,1,0,0
dcb 1,0,1,0,0,0
dcb 0,0
dcb 0,1,1,1,0,0
dcb 1,0,0,1,0,0
dcb 0,1,1,1,0,0
dcb 0,1,0,1,0,0
dcb 1,0,0,1,0,0
dcb 0,0
dcb 1,1,1,0,0,0
dcb 0,0,0,1,0,0
dcb 0,1,1,0,0,0
dcb 1,0,0,0,0,0
dcb 0,1,1,1,0,0
dcb 0,0
dcb 1,1,1,0,0,0
dcb 0,1,0,0,0,0
dcb 0,1,0,0,0,0
dcb 0,1,0,0,0,0
dcb 0,1,0,0,0,0
dcb 0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 1,0,0,1,0,0
dcb 1,1,1,0,0,0
dcb 0,0
dcb 1,0,0,0,1,0
dcb 1,0,0,0,1,0
dcb 1,0,0,0,1,0
dcb 0,1,0,1,0,0
dcb 0,0,1,0,0,0
dcb 0,0
dcb 1,0,0,0,1,0
dcb 1,0,0,0,1,0
dcb 1,0,1,0,1,0
dcb 1,1,0,1,1,0
dcb 1,0,0,0,1,0
dcb 0,0
dcb 1,0,0,0,1,0
dcb 0,1,0,1,0,0
dcb 0,0,1,0,0,0
dcb 0,1,0,1,0,0
dcb 1,0,0,0,1,0
dcb 0,0
dcb 1,0,0,0,1,0
dcb 0,1,0,1,0,0
dcb 0,0,1,0,0,0
dcb 0,0,1,0,0,0
dcb 0,0,1,0,0,0
dcb 0,0
dcb 1,1,1,1,0,0 ; z
dcb 1,0,0,0,0,0
dcb 0,1,1,0,0,0
dcb 0,0,0,1,0,0
dcb 1,1,1,1,0,0
dcb 0,0
dcb 0,0,0,0,0,0 ; .
dcb 0,0,0,0,0,0
dcb 0,0,0,0,0,0
dcb 0,0,0,0,0,0
dcb 1,0,0,0,0,0
dcb 0,0
dcb 0,0,0,0,0,0 ; " "
dcb 0,0,0,0,0,0
dcb 0,0,0,0,0,0
dcb 0,0,0,0,0,0
dcb 0,0,0,0,0,0
dcb 0,0
bottombar:
dcb $b,$9,$b,9,8,9,8,$a,8,$a,7,$a,7,1,7,1,1
dcb 7,1,7,$a,7,$a,8,$a,8,9,8,9,$b,9,$b
dcb $ff
|
;*****************************************************
;
; Video Technology library for small C compiler
;
; Juergen Buchmueller
;
;*****************************************************
; ----- void __FASTCALL__ vz_setbase(void *start)
PUBLIC vz_setbase
PUBLIC scrbase
.vz_setbase
ld (scrbase),hl
ret
.scrbase
defw $7000
|
; A208995: Number of 4-bead necklaces labeled with numbers -n..n not allowing reversal, with sum zero and first differences in -n..n.
; 2,7,16,33,58,95,144,209,290,391,512,657,826,1023,1248,1505,1794,2119,2480,2881,3322,3807,4336,4913,5538,6215,6944,7729,8570,9471,10432,11457,12546,13703,14928,16225,17594,19039,20560,22161,23842,25607,27456,29393
mov $2,$0
mov $3,$0
lpb $0
lpb $0
sub $0,1
add $4,$2
lpe
lpb $4
add $1,2
sub $4,1
lpe
sub $2,1
add $0,$2
sub $2,1
lpe
add $1,2
lpb $3
add $1,3
sub $3,1
lpe
|
; A146205: Number of paths of the simple random walk on condition that the median applied to the partial sums S_0=0, S_1,...,S_n, n odd (n=15 in this example), is equal to half-integer values k+1/2, -[n/2]-1<=k<=[n/2].
; 35,35,245,245,735,735,1225,1225,1225,1225,735,735,245,245,35,35
div $0,2
mov $1,7
bin $1,$0
mul $1,35
mov $0,$1
|
; Startup for VZ200/300
;
; Stefano Bodrato - Apr. 2000
;
; If an error occurs eg break we just drop back to BASIC
;
; $Id: vz_crt0.asm,v 1.27 2016-07-15 21:03:25 dom Exp $
;
MODULE vz_crt0
;--------
; Include zcc_opt.def to find out some info
;--------
defc crt0 = 1
INCLUDE "zcc_opt.def"
;--------
; Some scope definitions
;--------
EXTERN _main ;main() is always external to crt0 code
PUBLIC cleanup ;jp'd to by exit()
PUBLIC l_dcal ;jp(hl)
IF !DEFINED_CRT_ORG_CODE
IF (startup=3)
defc CRT_ORG_CODE = 32768 ; clean binary block
ELSE
IF (startup=2)
defc CRT_ORG_CODE = $7ae9 ; BASIC startup mode
ELSE
defc CRT_ORG_CODE = $7b00 ; Direct M/C mode
ENDIF
ENDIF
ENDIF
defc CONSOLE_ROWS = 16
defc CONSOLE_COLUMNS = 32
; Now, getting to the real stuff now!
defc TAR__no_ansifont = 1
defc TAR__clib_exit_stack_size = 32
defc TAR__register_sp = -1
defc __CPU_CLOCK = 3800000
INCLUDE "crt/classic/crt_rules.inc"
org CRT_ORG_CODE-24
IF (startup=3)
; STARTUP=3 -> plain binary block
ELSE
defb $20,$20,0,0
defm "z80.mc"
defb 0,0,0,0,0,0,0,0,0,0,0
IF (startup=2)
; BASIC startup mode
defb $f0
ELSE
; native M/C startup mode
defb $f1
ENDIF
defw CRT_ORG_CODE
IF (startup=2)
defw $7b04
defw 1
defb $B1 ;POKE
defm " 30862,18:"
defb $B1 ;POKE
defm " 30863,123"
defb 0 ; this block is 27 bytes long
defw $7b0f
defw 2
defb $b2 ; PRINT
defb ' '
defb $c1 ; USR
defm "(0)"
defb 0 ; this block is 11 bytes long
defw 0
defb 4
; Header ends here: 65 bytes
ENDIF
ENDIF
start:
ld (start1+1),sp
INCLUDE "crt/classic/crt_init_sp.asm"
INCLUDE "crt/classic/crt_init_atexit.asm"
call crt0_init_bss
ld (exitsp),sp
; Optional definition for auto MALLOC init
; it assumes we have free space between the end of
; the compiled program and the stack pointer
IF DEFINED_USING_amalloc
INCLUDE "crt/classic/crt_init_amalloc.asm"
ENDIF
call _main
cleanup:
push hl
call crt0_exit
pop bc
start1:
ld sp,0
jp 1A19h
l_dcal:
jp (hl)
INCLUDE "crt/classic/crt_runtime_selection.asm"
INCLUDE "crt/classic/crt_section.asm"
SECTION code_crt_init
ld hl,$7000
ld (base_graphics),hl
|
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.
// ===========================================================================
// File: MDInternalDisp.CPP
//
// Notes:
//
//
// ===========================================================================
#include "stdafx.h"
#include "mdinternaldisp.h"
#include "mdinternalro.h"
#include "posterror.h"
#include "corpriv.h"
#include "assemblymdinternaldisp.h"
#include "pedecoder.h"
#include "winmdinterfaces.h"
#ifdef FEATURE_METADATA_INTERNAL_APIS
// forward declaration
HRESULT GetInternalWithRWFormat(
LPVOID pData,
ULONG cbData,
DWORD flags, // [IN] MDInternal_OpenForRead or MDInternal_OpenForENC
REFIID riid, // [in] The interface desired.
void **ppIUnk); // [out] Return interface on success.
//*****************************************************************************
// CheckFileFormat
// This function will determine if the in-memory image is a readonly, readwrite,
// or ICR format.
//*****************************************************************************
HRESULT
CheckFileFormat(
LPVOID pData,
ULONG cbData,
MDFileFormat *pFormat) // [OUT] the file format
{
HRESULT hr = NOERROR;
STORAGEHEADER sHdr; // Header for the storage.
PSTORAGESTREAM pStream; // Pointer to each stream.
int i;
ULONG cbStreamBuffer;
_ASSERTE(pFormat != NULL);
*pFormat = MDFormat_Invalid;
// Validate the signature of the format, or it isn't ours.
if (FAILED(hr = MDFormat::VerifySignature((PSTORAGESIGNATURE) pData, cbData)))
goto ErrExit;
// Remaining buffer size behind the stream header (pStream).
cbStreamBuffer = cbData;
// Get back the first stream.
pStream = MDFormat::GetFirstStream_Verify(&sHdr, pData, &cbStreamBuffer);
if (pStream == NULL)
{
Debug_ReportError("Invalid MetaData storage signature - cannot get the first stream header.");
IfFailGo(CLDB_E_FILE_CORRUPT);
}
// Loop through each stream and pick off the ones we need.
for (i = 0; i < sHdr.GetiStreams(); i++)
{
// Do we have enough buffer to read stream header?
if (cbStreamBuffer < sizeof(*pStream))
{
Debug_ReportError("Stream header is not within MetaData block.");
IfFailGo(CLDB_E_FILE_CORRUPT);
}
// Get next stream.
PSTORAGESTREAM pNext = pStream->NextStream_Verify();
if (pNext == NULL)
{ // Stream header is corrupted.
Debug_ReportError("Invalid stream header - cannot get next stream header.");
IfFailGo(CLDB_E_FILE_CORRUPT);
}
// Check that stream header is within the buffer.
if (((LPBYTE)pStream >= ((LPBYTE)pData + cbData)) ||
((LPBYTE)pNext > ((LPBYTE)pData + cbData)))
{
Debug_ReportError("Stream header is not within MetaData block.");
hr = CLDB_E_FILE_CORRUPT;
goto ErrExit;
}
// Check that the stream data starts and fits within the buffer.
// need two checks on size because of wraparound.
if ((pStream->GetOffset() > cbData) ||
(pStream->GetSize() > cbData) ||
((pStream->GetSize() + pStream->GetOffset()) < pStream->GetOffset()) ||
((pStream->GetSize() + pStream->GetOffset()) > cbData))
{
Debug_ReportError("Stream data are not within MetaData block.");
hr = CLDB_E_FILE_CORRUPT;
goto ErrExit;
}
// Pick off the location and size of the data.
if (strcmp(pStream->GetName(), COMPRESSED_MODEL_STREAM_A) == 0)
{
// Validate that only one of compressed/uncompressed is present.
if (*pFormat != MDFormat_Invalid)
{ // Already found a good stream.
Debug_ReportError("Compressed model stream #~ is second important stream.");
hr = CLDB_E_FILE_CORRUPT;
goto ErrExit;
}
// Found the compressed meta data stream.
*pFormat = MDFormat_ReadOnly;
}
else if (strcmp(pStream->GetName(), ENC_MODEL_STREAM_A) == 0)
{
// Validate that only one of compressed/uncompressed is present.
if (*pFormat != MDFormat_Invalid)
{ // Already found a good stream.
Debug_ReportError("ENC model stream #- is second important stream.");
hr = CLDB_E_FILE_CORRUPT;
goto ErrExit;
}
// Found the ENC meta data stream.
*pFormat = MDFormat_ReadWrite;
}
else if (strcmp(pStream->GetName(), SCHEMA_STREAM_A) == 0)
{
// Found the uncompressed format
*pFormat = MDFormat_ICR;
// keep going. We may find the compressed format later.
// If so, we want to use the compressed format.
}
// Pick off the next stream if there is one.
pStream = pNext;
cbStreamBuffer = (ULONG)((LPBYTE)pData + cbData - (LPBYTE)pNext);
}
if (*pFormat == MDFormat_Invalid)
{ // Didn't find a good stream.
Debug_ReportError("Cannot find MetaData stream.");
hr = CLDB_E_FILE_CORRUPT;
}
ErrExit:
return hr;
} // CheckFileFormat
//*****************************************************************************
// GetMDInternalInterface.
// This function will check the metadata section and determine if it should
// return an interface which implements ReadOnly or ReadWrite.
//*****************************************************************************
STDAPI GetMDInternalInterface(
LPVOID pData,
ULONG cbData,
DWORD flags, // [IN] ofRead or ofWrite.
REFIID riid, // [in] The interface desired.
void **ppIUnk) // [out] Return interface on success.
{
HRESULT hr = NOERROR;
MDInternalRO *pInternalRO = NULL;
IMDCommon *pInternalROMDCommon = NULL;
MDFileFormat format;
if (ppIUnk == NULL)
IfFailGo(E_INVALIDARG);
// Determine the file format we're trying to read.
IfFailGo( CheckFileFormat(pData, cbData, &format) );
// Found a fully-compressed, read-only format.
if ( format == MDFormat_ReadOnly )
{
pInternalRO = new (nothrow) MDInternalRO;
IfNullGo( pInternalRO );
IfFailGo( pInternalRO->Init(const_cast<void*>(pData), cbData) );
#ifdef FEATURE_COMINTEROP
IfFailGo(pInternalRO->QueryInterface(IID_IMDCommon, (void**)&pInternalROMDCommon));
IfFailGo( (flags & ofNoTransform) ? S_FALSE : CheckIfWinMDAdapterNeeded(pInternalROMDCommon));
if (hr == S_OK)
{
IfFailGo(CreateWinMDInternalImportRO(pInternalROMDCommon, riid, (void**)ppIUnk));
}
else
#endif // FEATURE_COMINTEROP
{
IfFailGo(pInternalRO->QueryInterface(riid, ppIUnk));
}
}
else
{
// Found a not-fully-compressed, ENC format.
_ASSERTE( format == MDFormat_ReadWrite );
IfFailGo( GetInternalWithRWFormat( pData, cbData, flags, riid, ppIUnk ) );
}
ErrExit:
// clean up
if ( pInternalRO )
pInternalRO->Release();
if ( pInternalROMDCommon )
pInternalROMDCommon->Release();
return hr;
} // GetMDInternalInterface
#endif //FEATURE_METADATA_INTERNAL_APIS
|
<%
import collections
import pwnlib.abi
import pwnlib.constants
import pwnlib.shellcraft
import six
%>
<%docstring>vserver(vararg_0, vararg_1, vararg_2, vararg_3, vararg_4) -> str
Invokes the syscall vserver.
See 'man 2 vserver' for more information.
Arguments:
vararg(int): vararg
Returns:
long
</%docstring>
<%page args="vararg_0=None, vararg_1=None, vararg_2=None, vararg_3=None, vararg_4=None"/>
<%
abi = pwnlib.abi.ABI.syscall()
stack = abi.stack
regs = abi.register_arguments[1:]
allregs = pwnlib.shellcraft.registers.current()
can_pushstr = []
can_pushstr_array = []
argument_names = ['vararg_0', 'vararg_1', 'vararg_2', 'vararg_3', 'vararg_4']
argument_values = [vararg_0, vararg_1, vararg_2, vararg_3, vararg_4]
# Load all of the arguments into their destination registers / stack slots.
register_arguments = dict()
stack_arguments = collections.OrderedDict()
string_arguments = dict()
dict_arguments = dict()
array_arguments = dict()
syscall_repr = []
for name, arg in zip(argument_names, argument_values):
if arg is not None:
syscall_repr.append('%s=%s' % (name, pwnlib.shellcraft.pretty(arg, False)))
# If the argument itself (input) is a register...
if arg in allregs:
index = argument_names.index(name)
if index < len(regs):
target = regs[index]
register_arguments[target] = arg
elif arg is not None:
stack_arguments[index] = arg
# The argument is not a register. It is a string value, and we
# are expecting a string value
elif name in can_pushstr and isinstance(arg, (six.binary_type, six.text_type)):
if isinstance(arg, six.text_type):
arg = arg.encode('utf-8')
string_arguments[name] = arg
# The argument is not a register. It is a dictionary, and we are
# expecting K:V paris.
elif name in can_pushstr_array and isinstance(arg, dict):
array_arguments[name] = ['%s=%s' % (k,v) for (k,v) in arg.items()]
# The arguent is not a register. It is a list, and we are expecting
# a list of arguments.
elif name in can_pushstr_array and isinstance(arg, (list, tuple)):
array_arguments[name] = arg
# The argument is not a register, string, dict, or list.
# It could be a constant string ('O_RDONLY') for an integer argument,
# an actual integer value, or a constant.
else:
index = argument_names.index(name)
if index < len(regs):
target = regs[index]
register_arguments[target] = arg
elif arg is not None:
stack_arguments[target] = arg
# Some syscalls have different names on various architectures.
# Determine which syscall number to use for the current architecture.
for syscall in ['SYS_vserver']:
if hasattr(pwnlib.constants, syscall):
break
else:
raise Exception("Could not locate any syscalls: %r" % syscalls)
%>
/* vserver(${', '.join(syscall_repr)}) */
%for name, arg in string_arguments.items():
${pwnlib.shellcraft.pushstr(arg, append_null=(b'\x00' not in arg))}
${pwnlib.shellcraft.mov(regs[argument_names.index(name)], abi.stack)}
%endfor
%for name, arg in array_arguments.items():
${pwnlib.shellcraft.pushstr_array(regs[argument_names.index(name)], arg)}
%endfor
%for name, arg in stack_arguments.items():
${pwnlib.shellcraft.push(arg)}
%endfor
${pwnlib.shellcraft.setregs(register_arguments)}
${pwnlib.shellcraft.syscall(syscall)}
|
<%
from pwnlib.shellcraft.powerpc.linux import syscall
%>
<%page args="fildes"/>
<%docstring>
Invokes the syscall fdatasync. See 'man 2 fdatasync' for more information.
Arguments:
fildes(int): fildes
</%docstring>
${syscall('SYS_fdatasync', fildes)}
|
; A262493: Centered 13-gonal (or tridecagonal) primes.
; Submitted by Jon Maiga
; 79,131,859,2731,5279,6449,8191,10141,15289,17239,20021,20749,23011,26209,38039,41081,45319,46411,50909,54419,59281,65651,70981,76519,80809,86711,92821,99139,126491,128311,135721,159199,167441,175891,200201,209431,221261,230959
mov $2,332202
lpb $2
mov $3,$5
seq $3,10051 ; Characteristic function of primes: 1 if n is prime, else 0.
sub $0,$3
add $1,13
mov $4,$0
max $4,0
cmp $4,$0
mul $2,$4
sub $2,18
add $5,$1
lpe
mov $0,$5
add $0,1
|
;;;; processor ;;;;
PROCESSOR 6502
;;;; assembly includes ;;;;
INCLUDE "macro.h"
INCLUDE "vcs.h"
;;;; ram ;;;;
SEG.U VARIABLES
ORG $80
;;;; variables ;;;;
Var .byte ; RAM variable
;;;; move to rom start ;;;;
SEG ROM
ORG $F000
;;;; reset vcs REGS, RAM, TIA ;;;;
Reset:
CLEAN_START
;;;; init variables ;;;;
LDX #0
STA Var
;;;; Define rom end ;;;;
ORG $FFFC
.word Reset ; FFFC,FFFE
.word Reset ; FFFE,FFFF rom launch endpoint
; at FFFF
|
#include <scene.h>
#include <accel.h>
/**
* Scene class
*/
Scene::Scene() : light(nullptr), accel(), hasAccel() {}
Scene::Scene(std::shared_ptr<Light> light) : light(light) {}
void Scene::addGeometry(std::shared_ptr<Geometry> geom) {
geometries.push_back(geom);
}
int Scene::countGeometries() const {
return static_cast<int>(geometries.size());
}
void Scene::setLight(std::shared_ptr<Light> newLight) { light = newLight; }
std::shared_ptr<Light> Scene::getLight() const { return light; }
bool Scene::intersect(const Ray &ray, Interaction &interaction) const {
Interaction surfaceInteraction;
light->intersect(surfaceInteraction, ray);
if (hasAccel) {
Interaction curInteraction;
if (accel->intersect(curInteraction, ray)) {
if (surfaceInteraction.entryDist == -1 ||
curInteraction.entryDist < surfaceInteraction.entryDist) {
surfaceInteraction = curInteraction;
}
}
} else {
for (auto &geom : geometries) {
Interaction curInteraction;
if (geom->intersect(curInteraction, ray)) {
if (surfaceInteraction.entryDist == -1 ||
curInteraction.entryDist < surfaceInteraction.entryDist) {
surfaceInteraction = curInteraction;
}
}
}
}
interaction = surfaceInteraction;
if (surfaceInteraction.entryDist != -1 &&
surfaceInteraction.entryDist >= ray.tMin &&
surfaceInteraction.entryDist <= ray.tMax) {
return true;
}
return false;
}
bool Scene::isShadowed(const Ray &ray) const {
Interaction in;
return intersect(ray, in) && in.type == Interaction::Type::GEOMETRY;
}
void Scene::addGeometry(const std::vector<std::shared_ptr<Geometry>> &geoms) {
for (auto &i : geoms) addGeometry(i);
}
void Scene::buildAccel() {
if (geometries.empty()) return;
accel = std::make_shared<KdTreeAccel>(
*(reinterpret_cast<std::vector<std::shared_ptr<Triangle>> *>(&geometries)));
hasAccel = true;
}
|
; void __CALLEE__ sp1_ClearRectInv_callee(struct sp1_Rect *r, uchar tile, uchar rflag)
; 01.2008 aralbrec, Sprite Pack v3.0
; ts2068 hi-res version
PUBLIC sp1_ClearRectInv_callee
PUBLIC ASMDISP_SP1_CLEARRECTINV_CALLEE
EXTERN sp1_GetUpdateStruct_callee, sp1_ClearRect_callee, l_jpix
EXTERN ASMDISP_SP1_GETUPDATESTRUCT_CALLEE, ASMDISP_SP1CRSELECT
EXTERN SP1V_DISPWIDTH, SP1V_UPDATELISTT
.sp1_ClearRectInv_callee
pop af
pop bc
pop hl
pop de
push af
ld a,c
push hl
ex de,hl
ld d,(hl)
inc hl
ld e,(hl)
inc hl
ld b,(hl)
inc hl
ld c,(hl)
pop hl
.asmentry
; Clear a rectangular area on screen, erasing sprites,
; changing tile and changing colour depending on flags.
; Invalidate the area so that it is drawn in the next update.
;
; enter : d = row coord
; e = col coord
; b = width
; c = height
; l = tile
; a = bit 0 set for tiles, bit 1 set for tile colours, bit 2 set for sprites
; uses : af, bc, de, hl, af', ix, iy
.SP1ClearRectInv
and $07
ret z ; ret if all flags reset
push hl
call sp1_ClearRect_callee + ASMDISP_SP1CRSELECT ; ix = address of operation code (depending on flags passed in)
call sp1_GetUpdateStruct_callee + ASMDISP_SP1_GETUPDATESTRUCT_CALLEE ; hl = & struct update
pop de ; d = attr, e = tile
ld iy,(SP1V_UPDATELISTT) ; iy = last struct sp1_update in draw queue
.rowloop
push bc ; save b = width
push hl ; save update position
.colloop
ld a,$80
xor (hl)
jp p, alreadyinv ; if this update struct already invalidated, skip ahead
ld (hl),a
ld (iy+5),h ; store link in last invalidated update struct to this struct update
ld (iy+6),l
ld a,l ; make this update struct the last one in invalidated list
ld iyl,a ; "ld iyl,l" is likely taken as "ld iyl,iyl"
ld a,h
ld iyh,a
.alreadyinv
call l_jpix ; apply operation on hl, advance hl to next struct sp1_update to the right
djnz colloop
pop hl
ld bc,9*SP1V_DISPWIDTH
add hl,bc
pop bc
dec c
jp nz, rowloop
ld (iy+5),0
ld (SP1V_UPDATELISTT),iy
ret
DEFC ASMDISP_SP1_CLEARRECTINV_CALLEE = # asmentry - sp1_ClearRectInv_callee
|
sta {m1}+1
sty {m1}
|
lda {m2}
sta $fe
lda {m2}+1
sta $ff
lda ($fe),y
cmp {m1}
beq {la1} |
; A084171: Binomial transform of generalized Jacobsthal numbers A084170.
; 1,3,11,37,119,373,1151,3517,10679,32293,97391,293197,881639,2649013,7955231,23882077,71678999,215102533,645438671,1936578157,5810258759,17431824853,52297571711,156896909437,470699116919,1412114127973,4236375938351,12709194923917,38127718989479,114383425403893,343150813082591,1029453512989597,3088362686452439
mov $1,1
mov $3,1
lpb $0
sub $0,1
add $2,$1
mul $2,2
add $1,$2
mov $2,$3
mul $3,2
lpe
|
Name: ys_w51.asm
Type: file
Size: 19867
Last-Modified: '2016-05-13T04:50:38Z'
SHA-1: 5CF4C2E21C91A94AA098CBF36C4E486A1A78FE46
Description: null
|
; A202206: a(n) = 3*a(n-1)+3*a(n-2) with a(0)=1 and a(1)=2.
; 1,2,9,33,126,477,1809,6858,26001,98577,373734,1416933,5372001,20366802,77216409,292749633,1109898126,4207943277,15953524209,60484402458,229313780001,869394547377,3296124982134
mov $22,$0
mov $24,$0
add $24,1
lpb $24
clr $0,22
mov $0,$22
sub $24,1
sub $0,$24
mov $19,$0
mov $21,$0
add $21,1
lpb $21
mov $0,$19
sub $21,1
sub $0,$21
mov $15,$0
mov $17,2
lpb $17
mov $0,$15
sub $17,1
add $0,$17
sub $0,1
mov $11,$0
mov $13,2
lpb $13
mov $0,$11
sub $13,1
add $0,$13
sub $0,1
mov $7,$0
mov $9,2
lpb $9
mov $0,$7
sub $9,1
add $0,$9
sub $0,1
sub $2,$2
mov $3,90
lpb $0
sub $0,1
mov $6,$2
mov $2,$3
add $3,$6
mul $3,3
lpe
add $3,2
mul $3,37
mov $1,$3
sub $1,3403
div $1,3330
mul $1,12
add $1,12
mov $10,$9
lpb $10
mov $8,$1
sub $10,1
lpe
lpe
lpb $7
mov $7,0
sub $8,$1
lpe
mov $1,$8
mov $14,$13
lpb $14
mov $12,$1
sub $14,1
lpe
lpe
lpb $11
mov $11,0
sub $12,$1
lpe
mov $1,$12
mov $18,$17
lpb $18
mov $16,$1
sub $18,1
lpe
lpe
lpb $15
mov $15,0
sub $16,$1
lpe
mov $1,$16
div $1,12
add $20,$1
lpe
add $23,$20
lpe
mov $1,$23
|
////////////////////////////////////////////////////////////
//
// SFML - Simple and Fast Multimedia Library
// Copyright (C) 2007-2020 Laurent Gomila (laurent@sfml-dev.org)
//
// This software is provided 'as-is', without any express or implied warranty.
// In no event will the authors be held liable for any damages arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it freely,
// subject to the following restrictions:
//
// 1. The origin of this software must not be misrepresented;
// you must not claim that you wrote the original software.
// If you use this software in a product, an acknowledgment
// in the product documentation would be appreciated but is not required.
//
// 2. Altered source versions must be plainly marked as such,
// and must not be misrepresented as being the original software.
//
// 3. This notice may not be removed or altered from any source distribution.
//
////////////////////////////////////////////////////////////
#ifndef SFML_VECTOR3_HPP
#define SFML_VECTOR3_HPP
namespace sf
{
////////////////////////////////////////////////////////////
/// \brief Utility template class for manipulating
/// 3-dimensional vectors
///
////////////////////////////////////////////////////////////
template <typename T>
class Vector3
{
public:
////////////////////////////////////////////////////////////
/// \brief Default constructor
///
/// Creates a Vector3(0, 0, 0).
///
////////////////////////////////////////////////////////////
Vector3();
////////////////////////////////////////////////////////////
/// \brief Construct the vector from its coordinates
///
/// \param X X coordinate
/// \param Y Y coordinate
/// \param Z Z coordinate
///
////////////////////////////////////////////////////////////
Vector3(T X, T Y, T Z);
////////////////////////////////////////////////////////////
/// \brief Construct the vector from another type of vector
///
/// This constructor doesn't replace the copy constructor,
/// it's called only when U != T.
/// A call to this constructor will fail to compile if U
/// is not convertible to T.
///
/// \param vector Vector to convert
///
////////////////////////////////////////////////////////////
template <typename U>
explicit Vector3(const Vector3<U>& vector);
////////////////////////////////////////////////////////////
// Member data
////////////////////////////////////////////////////////////
T x; //!< X coordinate of the vector
T y; //!< Y coordinate of the vector
T z; //!< Z coordinate of the vector
};
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of unary operator -
///
/// \param left Vector to negate
///
/// \return Memberwise opposite of the vector
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T> operator -(const Vector3<T>& left);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator +=
///
/// This operator performs a memberwise addition of both vectors,
/// and assigns the result to \a left.
///
/// \param left Left operand (a vector)
/// \param right Right operand (a vector)
///
/// \return Reference to \a left
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T>& operator +=(Vector3<T>& left, const Vector3<T>& right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator -=
///
/// This operator performs a memberwise subtraction of both vectors,
/// and assigns the result to \a left.
///
/// \param left Left operand (a vector)
/// \param right Right operand (a vector)
///
/// \return Reference to \a left
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T>& operator -=(Vector3<T>& left, const Vector3<T>& right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator +
///
/// \param left Left operand (a vector)
/// \param right Right operand (a vector)
///
/// \return Memberwise addition of both vectors
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T> operator +(const Vector3<T>& left, const Vector3<T>& right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator -
///
/// \param left Left operand (a vector)
/// \param right Right operand (a vector)
///
/// \return Memberwise subtraction of both vectors
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T> operator -(const Vector3<T>& left, const Vector3<T>& right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator *
///
/// \param left Left operand (a vector)
/// \param right Right operand (a scalar value)
///
/// \return Memberwise multiplication by \a right
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T> operator *(const Vector3<T>& left, T right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator *
///
/// \param left Left operand (a scalar value)
/// \param right Right operand (a vector)
///
/// \return Memberwise multiplication by \a left
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T> operator *(T left, const Vector3<T>& right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator *=
///
/// This operator performs a memberwise multiplication by \a right,
/// and assigns the result to \a left.
///
/// \param left Left operand (a vector)
/// \param right Right operand (a scalar value)
///
/// \return Reference to \a left
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T>& operator *=(Vector3<T>& left, T right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator /
///
/// \param left Left operand (a vector)
/// \param right Right operand (a scalar value)
///
/// \return Memberwise division by \a right
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T> operator /(const Vector3<T>& left, T right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator /=
///
/// This operator performs a memberwise division by \a right,
/// and assigns the result to \a left.
///
/// \param left Left operand (a vector)
/// \param right Right operand (a scalar value)
///
/// \return Reference to \a left
///
////////////////////////////////////////////////////////////
template <typename T>
Vector3<T>& operator /=(Vector3<T>& left, T right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator ==
///
/// This operator compares strict equality between two vectors.
///
/// \param left Left operand (a vector)
/// \param right Right operand (a vector)
///
/// \return True if \a left is equal to \a right
///
////////////////////////////////////////////////////////////
template <typename T>
bool operator ==(const Vector3<T>& left, const Vector3<T>& right);
////////////////////////////////////////////////////////////
/// \relates Vector3
/// \brief Overload of binary operator !=
///
/// This operator compares strict difference between two vectors.
///
/// \param left Left operand (a vector)
/// \param right Right operand (a vector)
///
/// \return True if \a left is not equal to \a right
///
////////////////////////////////////////////////////////////
template <typename T>
bool operator !=(const Vector3<T>& left, const Vector3<T>& right);
#include <SFML/System/Vector3.inl>
// Define the most common types
typedef Vector3<int> Vector3i;
typedef Vector3<float> Vector3f;
} // namespace sf
#endif // SFML_VECTOR3_HPP
////////////////////////////////////////////////////////////
/// \class sf::Vector3
/// \ingroup system
///
/// sf::Vector3 is a simple class that defines a mathematical
/// vector with three coordinates (x, y and z). It can be used to
/// represent anything that has three dimensions: a size, a point,
/// a velocity, etc.
///
/// The template parameter T is the type of the coordinates. It
/// can be any type that supports arithmetic operations (+, -, /, *)
/// and comparisons (==, !=), for example int or float.
///
/// You generally don't have to care about the templated form (sf::Vector3<T>),
/// the most common specializations have special typedefs:
/// \li sf::Vector3<float> is sf::Vector3f
/// \li sf::Vector3<int> is sf::Vector3i
///
/// The sf::Vector3 class has a small and simple interface, its x and y members
/// can be accessed directly (there are no accessors like setX(), getX()) and it
/// contains no mathematical function like dot product, cross product, length, etc.
///
/// Usage example:
/// \code
/// sf::Vector3f v1(16.5f, 24.f, -8.2f);
/// v1.x = 18.2f;
/// float y = v1.y;
/// float z = v1.z;
///
/// sf::Vector3f v2 = v1 * 5.f;
/// sf::Vector3f v3;
/// v3 = v1 + v2;
///
/// bool different = (v2 != v3);
/// \endcode
///
/// Note: for 2-dimensional vectors, see sf::Vector2.
///
////////////////////////////////////////////////////////////
|
.global s_prepare_buffers
s_prepare_buffers:
push %r10
push %r13
push %r9
push %rbp
push %rcx
push %rdi
push %rsi
lea addresses_WC_ht+0x7f58, %rsi
lea addresses_normal_ht+0x15970, %rdi
nop
nop
inc %r13
mov $6, %rcx
rep movsl
nop
nop
nop
nop
nop
and $12518, %rbp
lea addresses_WC_ht+0x5958, %r13
nop
add $60420, %r9
mov $0x6162636465666768, %rdi
movq %rdi, (%r13)
nop
nop
nop
nop
inc %rdi
lea addresses_D_ht+0x13080, %r9
nop
nop
nop
nop
nop
and $55967, %rcx
mov (%r9), %di
nop
nop
nop
nop
nop
add $19692, %rbp
lea addresses_A_ht+0x1a158, %rcx
nop
nop
nop
nop
nop
and %r10, %r10
mov (%rcx), %edi
nop
inc %r13
lea addresses_A_ht+0x658, %rbp
clflush (%rbp)
nop
nop
nop
nop
add %rsi, %rsi
movb (%rbp), %r9b
add %rbp, %rbp
pop %rsi
pop %rdi
pop %rcx
pop %rbp
pop %r9
pop %r13
pop %r10
ret
.global s_faulty_load
s_faulty_load:
push %r14
push %rax
push %rbx
push %rcx
push %rdi
push %rdx
push %rsi
// REPMOV
lea addresses_A+0x3a74, %rsi
lea addresses_WT+0x136ac, %rdi
nop
nop
xor %r14, %r14
mov $80, %rcx
rep movsw
nop
nop
nop
xor %rsi, %rsi
// Store
lea addresses_RW+0x1dd58, %rax
dec %rcx
mov $0x5152535455565758, %r14
movq %r14, %xmm3
movups %xmm3, (%rax)
nop
nop
nop
nop
sub $44846, %rdi
// Store
mov $0xb752a0000000898, %rdi
nop
and $28711, %rdx
mov $0x5152535455565758, %rax
movq %rax, %xmm6
vmovups %ymm6, (%rdi)
add %rax, %rax
// Faulty Load
lea addresses_A+0x1b958, %rsi
nop
nop
xor %rcx, %rcx
mov (%rsi), %ax
lea oracles, %rsi
and $0xff, %rax
shlq $12, %rax
mov (%rsi,%rax,1), %rax
pop %rsi
pop %rdx
pop %rdi
pop %rcx
pop %rbx
pop %rax
pop %r14
ret
/*
<gen_faulty_load>
[REF]
{'OP': 'LOAD', 'src': {'type': 'addresses_A', 'size': 8, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': False}}
{'OP': 'REPM', 'src': {'type': 'addresses_A', 'congruent': 2, 'same': False}, 'dst': {'type': 'addresses_WT', 'congruent': 2, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_RW', 'size': 16, 'AVXalign': False, 'NT': False, 'congruent': 10, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_NC', 'size': 32, 'AVXalign': False, 'NT': False, 'congruent': 6, 'same': False}}
[Faulty Load]
{'OP': 'LOAD', 'src': {'type': 'addresses_A', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 0, 'same': True}}
<gen_prepare_buffer>
{'OP': 'REPM', 'src': {'type': 'addresses_WC_ht', 'congruent': 9, 'same': True}, 'dst': {'type': 'addresses_normal_ht', 'congruent': 3, 'same': False}}
{'OP': 'STOR', 'dst': {'type': 'addresses_WC_ht', 'size': 8, 'AVXalign': True, 'NT': False, 'congruent': 11, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_D_ht', 'size': 2, 'AVXalign': False, 'NT': False, 'congruent': 3, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_A_ht', 'size': 4, 'AVXalign': False, 'NT': True, 'congruent': 11, 'same': False}}
{'OP': 'LOAD', 'src': {'type': 'addresses_A_ht', 'size': 1, 'AVXalign': False, 'NT': False, 'congruent': 7, 'same': True}}
{'00': 4}
00 00 00 00
*/
|
; A140811: a(n) = 6*n^2 - 1.
; -1,5,23,53,95,149,215,293,383,485,599,725,863,1013,1175,1349,1535,1733,1943,2165,2399,2645,2903,3173,3455,3749,4055,4373,4703,5045,5399,5765,6143,6533,6935,7349,7775,8213,8663,9125,9599,10085,10583,11093,11615,12149,12695,13253,13823,14405,14999,15605,16223,16853,17495,18149,18815,19493,20183,20885,21599,22325,23063,23813,24575,25349,26135,26933,27743,28565,29399,30245,31103,31973,32855,33749,34655,35573,36503,37445,38399,39365,40343,41333,42335,43349,44375,45413,46463,47525,48599,49685,50783
pow $0,2
mul $0,6
sub $0,1
|
;
; Grundy Newbrain Specific libraries
;
; Stefano Bodrato - 19/05/2007
;
;
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;
; This function is linked only in the CP/M extension version
; it calls the ROM functions via the CP/M facility
;
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;
; Used internally only
;
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;
;
; $Id: cpmzcall.asm,v 1.3 2016-06-19 20:33:40 dom Exp $
;
SECTION code_clib
PUBLIC ZCALL
.ZCALL
jp $f4fb ; CPMZCALL
|
/*
* Copyright (C) 2015 BMW Car IT GmbH
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "capu/util/Iterator.h"
#include "capu/container/vector.h"
#include "capu/Config.h"
#include "BidirectionalTestContainer.h"
#include "gmock/gmock.h"
namespace capu
{
TEST(IteratorTest, DistanceOnPointer)
{
uint_t a[4] = { 1, 2, 3, 4 };
int_t result = distance(a, a + 4);
EXPECT_EQ(4, result);
}
TEST(IteratorTest, DistanceOnSamePointer)
{
uint_t a[1] = { 1 };
int_t result = distance(a, a);
EXPECT_EQ(0, result);
}
TEST(IteratorTest, DistanceOnPointerNegative)
{
uint_t a[4] = { 1, 2, 3, 4 };
int_t result = distance(a + 4, a);
EXPECT_EQ(-4, result);
}
TEST(IteratorTest, DistanceOnVector)
{
vector<uint_t> v(3, 0);
int_t result = distance(v.begin(), v.end());
EXPECT_EQ(3, result);
}
TEST(IteratorTest, DistanceOnVectorSameIterator)
{
vector<uint_t> v(3, 0);
int_t result = distance(v.begin(), v.begin());
EXPECT_EQ(0, result);
}
TEST(IteratorTest, DistanceOnVectorNegative)
{
vector<uint_t> v(3, 0);
int_t result = distance(vector<uint_t>::Iterator(v.begin() + 2u), v.begin());
EXPECT_EQ(-2, result);
}
TEST(IteratorTest, DistanceOnBidirectionalIterator)
{
BidirectionalTestContainer<uint_t> c(5);
int_t result = distance(c.begin(), c.end());
EXPECT_EQ(5, result);
}
TEST(IteratorTest, DistanceOnBidirectionalIteratorSameIterator)
{
BidirectionalTestContainer<uint_t> c(5);
int_t result = distance(c.end(), c.end());
EXPECT_EQ(0, result);
}
TEST(IteratorTest, AdvanceOnPointer)
{
uint_t a[4] = { 1, 2, 3, 4 };
uint_t *p = a;
advance(p, 2);
EXPECT_EQ(3u, *p);
}
TEST(IteratorTest, AdvanceZeroOnPointer)
{
uint_t a[2] = { 1, 2 };
uint_t *p = a;
advance(p, 0);
EXPECT_EQ(1u, *p);
}
TEST(IteratorTest, AdvanceNegativeOnPointer)
{
uint_t a[4] = { 1, 2, 3, 4 };
uint_t *p = &a[3];
advance(p, -3);
EXPECT_EQ(1u, *p);
}
TEST(IteratorTest, AdvanceOnVector)
{
vector<uint_t> v(4, 0);
v[0] = 1;
v[1] = 2;
v[2] = 3;
v[3] = 4;
vector<uint_t>::Iterator it = v.begin();
advance(it, 2);
EXPECT_EQ(3u, *it);
}
TEST(IteratorTest, AdvanceZeroOnVector)
{
vector<uint_t> v(2, 0);
v[0] = 1;
v[1] = 2;
vector<uint_t>::Iterator it = v.begin();
advance(it, 0);
EXPECT_EQ(1u, *it);
}
TEST(IteratorTest, AdvanceNegativeOnVector)
{
vector<uint_t> v(4, 0);
v[0] = 1;
v[1] = 2;
v[2] = 3;
v[3] = 4;
vector<uint_t>::Iterator it = v.begin() + 3u;
advance(it, -3);
EXPECT_EQ(1u, *it);
}
TEST(IteratorTest, AdvanceOnBidirectionalContainer)
{
BidirectionalTestContainer<uint_t> c(4);
c[0] = 1;
c[1] = 2;
c[2] = 3;
c[3] = 4;
BidirectionalTestContainer<uint_t>::Iterator it = c.begin();
advance(it, 2);
EXPECT_EQ(3u, *it);
}
TEST(IteratorTest, AdvanceZeroOnBidirectionalContainer)
{
BidirectionalTestContainer<uint_t> c(2);
c[0] = 1;
c[1] = 2;
BidirectionalTestContainer<uint_t>::Iterator it = c.begin();
advance(it, 0);
EXPECT_EQ(1u, *it);
}
TEST(IteratorTest, AdvanceNegativeOnBidirectionalContainer)
{
BidirectionalTestContainer<uint_t> c(4);
c[0] = 1;
c[1] = 2;
c[2] = 3;
c[3] = 4;
BidirectionalTestContainer<uint_t>::Iterator it = c.end();
advance(it, -3);
EXPECT_EQ(2u, *it);
}
}
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