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710.4653 | Simultaneous Reduction of Dynamic and Static Power in Scan Structures | Power dissipation during test is a major challenge in testing integrated
circuits. Dynamic power has been the dominant part of power dissipation in CMOS
circuits, however, in future technologies the static portion of power
dissipation will outreach the dynamic portion. This paper proposes an efficient
technique to reduce both dynamic and static power dissipation in scan
structures. Scan cell outputs which are not on the critical path(s) are
multiplexed to fixed values during scan mode. These constant values and primary
inputs are selected such that the transitions occurred on non-multiplexed scan
cells are suppressed and the leakage current during scan mode is decreased. A
method for finding these vectors is also proposed. Effectiveness of this
technique is proved by experiments performed on ISCAS89 benchmark circuits.
| cs.AR | power dissipation during test is a major challenge in testing integrated circuits dynamic power has been the dominant part of power dissipation in cmos circuits however in future technologies the static portion of power dissipation will outreach the dynamic portion this paper proposes an efficient technique to reduce both dynamic and static power dissipation in scan structures scan cell outputs which are not on the critical paths are multiplexed to fixed values during scan mode these constant values and primary inputs are selected such that the transitions occurred on nonmultiplexed scan cells are suppressed and the leakage current during scan mode is decreased a method for finding these vectors is also proposed effectiveness of this technique is proved by experiments performed on iscas89 benchmark circuits | [['power', 'dissipation', 'during', 'test', 'is', 'a', 'major', 'challenge', 'in', 'testing', 'integrated', 'circuits', 'dynamic', 'power', 'has', 'been', 'the', 'dominant', 'part', 'of', 'power', 'dissipation', 'in', 'cmos', 'circuits', 'however', 'in', 'future', 'technologies', 'the', 'static', 'portion', 'of', 'power', 'dissipation', 'will', 'outreach', 'the', 'dynamic', 'portion', 'this', 'paper', 'proposes', 'an', 'efficient', 'technique', 'to', 'reduce', 'both', 'dynamic', 'and', 'static', 'power', 'dissipation', 'in', 'scan', 'structures', 'scan', 'cell', 'outputs', 'which', 'are', 'not', 'on', 'the', 'critical', 'paths', 'are', 'multiplexed', 'to', 'fixed', 'values', 'during', 'scan', 'mode', 'these', 'constant', 'values', 'and', 'primary', 'inputs', 'are', 'selected', 'such', 'that', 'the', 'transitions', 'occurred', 'on', 'nonmultiplexed', 'scan', 'cells', 'are', 'suppressed', 'and', 'the', 'leakage', 'current', 'during', 'scan', 'mode', 'is', 'decreased', 'a', 'method', 'for', 'finding', 'these', 'vectors', 'is', 'also', 'proposed', 'effectiveness', 'of', 'this', 'technique', 'is', 'proved', 'by', 'experiments', 'performed', 'on', 'iscas89', 'benchmark', 'circuits']] | [-0.14978517260961235, 0.12285713446617592, -0.018722065574489535, 0.004246323272585869, -0.052136890897527335, -0.14088660106481984, 0.036360765592195095, 0.3849218190610409, -0.2465386660695076, -0.3206020864583552, 0.12155310550704598, -0.2691834098994732, -0.12071998003870249, 0.26189577335864306, -0.05408329395577312, 0.09360375031293369, 0.07485749272257089, -0.020100636325776577, 0.007136844273656607, -0.22246299901604652, 0.22761372654984008, 0.12985547064617275, 0.36246296962327323, 0.028398800764232873, 0.06405716641619802, -0.044273135852068664, -0.051309126926586034, 0.02562411991506815, -0.09400609390815953, 0.0648769598864019, 0.28929004434868694, 0.14378859979845585, 0.3041140625849366, -0.44608323404192923, -0.22156933672167362, 0.11042379620298744, 0.13608645360171795, 0.06351758781354874, -0.05979450545366854, -0.19092677175626158, 0.12674132953723893, -0.1438823846128653, -0.03235729352757335, -0.07827512376010418, 0.03059722824394703, 0.00499733282905072, -0.2901134999729693, 0.053601171161746605, 0.014747977007180453, 0.04089131845533848, -0.049227404410019514, -0.10047084622085095, 0.00361565874889493, 0.127182903945446, -0.015658234830014408, 0.029030849328264594, 0.2012222744282335, -0.11951302449032665, -0.14222188996651675, 0.32503007620573043, 0.004167386405169964, -0.16464847514778375, 0.1346429278254509, -0.11278298355266451, -0.10791353955492378, 0.16047925585880876, 0.21605711394548416, 0.08335553075000644, -0.14867396309413017, 0.04843689204240218, 0.06203560464829207, 0.19610597588121892, 0.07182637611217797, 0.012429645795375109, 0.21702810841798784, 0.20805544415861368, 0.05307654930651188, 0.16636245532706379, -0.12649842838011682, -0.09255121300928294, -0.28476330362632873, -0.10578453467041254, -0.174728326653596, -0.004458326959866099, -0.04104298715817276, -0.11290557996556162, 0.42059459640830754, 0.15434498459473253, 0.1429863444045186, 0.026024428638629617, 0.3822501704990864, 0.11708488880097866, 0.1343183392547071, 0.06178353426977992, 0.25444571444392206, 0.054543028371408585, 0.14999995262175797, -0.221390226110816, 0.07011328993737698, 0.0037130843102931976] |
710.4654 | Modeling Interconnect Variability Using Efficient Parametric Model Order
Reduction | Assessing IC manufacturing process fluctuations and their impacts on IC
interconnect performance has become unavoidable for modern DSM designs.
However, the construction of parametric interconnect models is often hampered
by the rapid increase in computational cost and model complexity. In this paper
we present an efficient yet accurate parametric model order reduction algorithm
for addressing the variability of IC interconnect performance. The efficiency
of the approach lies in a novel combination of low-rank matrix approximation
and multi-parameter moment matching. The complexity of the proposed parametric
model order reduction is as low as that of a standard Krylov subspace method
when applied to a nominal system. Under the projection-based framework, our
algorithm also preserves the passivity of the resulting parametric models.
| cs.AR | assessing ic manufacturing process fluctuations and their impacts on ic interconnect performance has become unavoidable for modern dsm designs however the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity in this paper we present an efficient yet accurate parametric model order reduction algorithm for addressing the variability of ic interconnect performance the efficiency of the approach lies in a novel combination of lowrank matrix approximation and multiparameter moment matching the complexity of the proposed parametric model order reduction is as low as that of a standard krylov subspace method when applied to a nominal system under the projectionbased framework our algorithm also preserves the passivity of the resulting parametric models | [['assessing', 'ic', 'manufacturing', 'process', 'fluctuations', 'and', 'their', 'impacts', 'on', 'ic', 'interconnect', 'performance', 'has', 'become', 'unavoidable', 'for', 'modern', 'dsm', 'designs', 'however', 'the', 'construction', 'of', 'parametric', 'interconnect', 'models', 'is', 'often', 'hampered', 'by', 'the', 'rapid', 'increase', 'in', 'computational', 'cost', 'and', 'model', 'complexity', 'in', 'this', 'paper', 'we', 'present', 'an', 'efficient', 'yet', 'accurate', 'parametric', 'model', 'order', 'reduction', 'algorithm', 'for', 'addressing', 'the', 'variability', 'of', 'ic', 'interconnect', 'performance', 'the', 'efficiency', 'of', 'the', 'approach', 'lies', 'in', 'a', 'novel', 'combination', 'of', 'lowrank', 'matrix', 'approximation', 'and', 'multiparameter', 'moment', 'matching', 'the', 'complexity', 'of', 'the', 'proposed', 'parametric', 'model', 'order', 'reduction', 'is', 'as', 'low', 'as', 'that', 'of', 'a', 'standard', 'krylov', 'subspace', 'method', 'when', 'applied', 'to', 'a', 'nominal', 'system', 'under', 'the', 'projectionbased', 'framework', 'our', 'algorithm', 'also', 'preserves', 'the', 'passivity', 'of', 'the', 'resulting', 'parametric', 'models']] | [-0.08971060580467262, -0.008503504837547856, -0.04593636617064476, 0.052283201750424266, -0.06485854827527267, -0.13165737156329366, 0.07071831827973558, 0.3866410549109181, -0.27841590248669185, -0.30239519441189866, 0.1277244360234666, -0.2009519537134717, -0.16791869297157974, 0.2109890098082057, -0.11518291844210277, 0.10945606950748091, 0.06238816642241242, -0.042555164182946706, -0.08016417568578618, -0.2582621891051531, 0.26299720189708753, 0.11490668643576403, 0.37091891878129296, -0.006414650080356902, 0.13843529545192723, -0.028212615474088428, 0.006823935948583919, -0.015423099743687392, -0.04385596720415682, 0.17327942908159458, 0.24590098035484212, 0.15597904898459092, 0.31458972084025544, -0.41632190843811256, -0.224786501852941, 0.12090590123067765, 0.15155573804707576, 0.10451893894157062, -0.04732124065146005, -0.20952688354979424, 0.08645092329631249, -0.2177067201817408, -0.10749638740671799, -0.1037927486252253, -0.04555152300745249, -0.016069245687685908, -0.2871096563215057, 0.07638175355750718, 0.10289565094280988, 0.06614882872017916, -0.017229975142981857, -0.1299604611073543, 0.05024583048458832, 0.05018493986693405, 0.007846951004224442, 0.004686956495667497, 0.09703262686768237, -0.14282699355972, -0.13056582646386233, 0.3828926561846553, -0.015687349078749926, -0.18433889093187947, 0.18039833336758118, -0.047092990862438455, -0.12382376848254353, 0.1530565730916957, 0.22667057610815391, 0.06676799940954273, -0.1486216499456835, 0.11677691762136723, 0.04774530119417856, 0.17184466901235282, -0.003045674634631723, 0.04072984337884312, 0.1165142526035197, 0.2694629941950552, 0.09098495893801252, 0.13864270113408567, -0.09178301552698637, -0.10312676763472457, -0.24739882661184917, -0.12449317441314633, -0.16753331957928216, -0.02066768174408935, -0.1251891777653024, -0.2008003520507676, 0.38420748279895633, 0.19233380535733885, 0.14353875456533086, 0.05791212182181577, 0.39652770922208824, 0.1541780197539386, 0.06617920379115579, 0.07049006177500511, 0.2323624867965312, 0.12182355405723987, 0.05630940068307003, -0.26125040095454705, 0.11949621326833343, 0.056948336850230895] |
710.4655 | A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs | This paper proposes a diagnosis scheme aimed at reducing diagnosis time of
distributed small embedded SRAMs (e-SRAMs). This scheme improves the one
proposed in [A parallel built-in self-diagnostic method for embedded memory
buffers, A parallel built-in self-diagnostic method for embedded memory
arrays]. The improvements are mainly two-fold. On one hand, the diagnosis of
time-consuming Data Retention Faults (DRFs), which is neglected by the
diagnosis architecture in [A parallel built-in self-diagnostic method for
embedded memory buffers, A parallel built-in self-diagnostic method for
embedded memory arrays], is now considered and performed via a DFT technique
referred to as the "No Write Recovery Test Mode (NWRTM)". On the other hand, a
pair comprising a Serial to Parallel Converter (SPC) and a Parallel to Serial
Converter (PSC) is utilized to replace the bi-directional serial interface, to
avoid the problems of serial fault masking and defect rate dependent diagnosis.
Results from our evaluations show that the proposed diagnosis scheme achieves
an increased diagnosis coverage and reduces diagnosis time compared to those
obtained in [A parallel built-in self-diagnostic method for embedded memory
buffers, A parallel built-in self-diagnostic method for embedded memory
arrays], with neglectable extra area cost.
| cs.AR | this paper proposes a diagnosis scheme aimed at reducing diagnosis time of distributed small embedded srams esrams this scheme improves the one proposed in a parallel builtin selfdiagnostic method for embedded memory buffers a parallel builtin selfdiagnostic method for embedded memory arrays the improvements are mainly twofold on one hand the diagnosis of timeconsuming data retention faults drfs which is neglected by the diagnosis architecture in a parallel builtin selfdiagnostic method for embedded memory buffers a parallel builtin selfdiagnostic method for embedded memory arrays is now considered and performed via a dft technique referred to as the no write recovery test mode nwrtm on the other hand a pair comprising a serial to parallel converter spc and a parallel to serial converter psc is utilized to replace the bidirectional serial interface to avoid the problems of serial fault masking and defect rate dependent diagnosis results from our evaluations show that the proposed diagnosis scheme achieves an increased diagnosis coverage and reduces diagnosis time compared to those obtained in a parallel builtin selfdiagnostic method for embedded memory buffers a parallel builtin selfdiagnostic method for embedded memory arrays with neglectable extra area cost | [['this', 'paper', 'proposes', 'a', 'diagnosis', 'scheme', 'aimed', 'at', 'reducing', 'diagnosis', 'time', 'of', 'distributed', 'small', 'embedded', 'srams', 'esrams', 'this', 'scheme', 'improves', 'the', 'one', 'proposed', 'in', 'a', 'parallel', 'builtin', 'selfdiagnostic', 'method', 'for', 'embedded', 'memory', 'buffers', 'a', 'parallel', 'builtin', 'selfdiagnostic', 'method', 'for', 'embedded', 'memory', 'arrays', 'the', 'improvements', 'are', 'mainly', 'twofold', 'on', 'one', 'hand', 'the', 'diagnosis', 'of', 'timeconsuming', 'data', 'retention', 'faults', 'drfs', 'which', 'is', 'neglected', 'by', 'the', 'diagnosis', 'architecture', 'in', 'a', 'parallel', 'builtin', 'selfdiagnostic', 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710.4656 | A Memory Hierarchical Layer Assigning and Prefetching Technique to
Overcome the Memory Performance/Energy Bottleneck | The memory subsystem has always been a bottleneck in performance as well as
significant power contributor in memory intensive applications. Many
researchers have presented multi-layered memory hierarchies as a means to
design energy and performance efficient systems. However, most of the previous
work do not explore trade-offs systematically. We fill this gap by proposing a
formalized technique that takes into consideration data reuse, limited lifetime
of the arrays of an application and application specific prefetching
opportunities, and performs a thorough trade-off exploration for different
memory layer sizes. This technique has been implemented on a prototype tool,
which was tested successfully using nine real-life applications of industrial
relevance. Following this approach we have able to reduce execution time up to
60%, and energy consumption up to 70%.
| cs.AR | the memory subsystem has always been a bottleneck in performance as well as significant power contributor in memory intensive applications many researchers have presented multilayered memory hierarchies as a means to design energy and performance efficient systems however most of the previous work do not explore tradeoffs systematically we fill this gap by proposing a formalized technique that takes into consideration data reuse limited lifetime of the arrays of an application and application specific prefetching opportunities and performs a thorough tradeoff exploration for different memory layer sizes this technique has been implemented on a prototype tool which was tested successfully using nine reallife applications of industrial relevance following this approach we have able to reduce execution time up to 60 and energy consumption up to 70 | [['the', 'memory', 'subsystem', 'has', 'always', 'been', 'a', 'bottleneck', 'in', 'performance', 'as', 'well', 'as', 'significant', 'power', 'contributor', 'in', 'memory', 'intensive', 'applications', 'many', 'researchers', 'have', 'presented', 'multilayered', 'memory', 'hierarchies', 'as', 'a', 'means', 'to', 'design', 'energy', 'and', 'performance', 'efficient', 'systems', 'however', 'most', 'of', 'the', 'previous', 'work', 'do', 'not', 'explore', 'tradeoffs', 'systematically', 'we', 'fill', 'this', 'gap', 'by', 'proposing', 'a', 'formalized', 'technique', 'that', 'takes', 'into', 'consideration', 'data', 'reuse', 'limited', 'lifetime', 'of', 'the', 'arrays', 'of', 'an', 'application', 'and', 'application', 'specific', 'prefetching', 'opportunities', 'and', 'performs', 'a', 'thorough', 'tradeoff', 'exploration', 'for', 'different', 'memory', 'layer', 'sizes', 'this', 'technique', 'has', 'been', 'implemented', 'on', 'a', 'prototype', 'tool', 'which', 'was', 'tested', 'successfully', 'using', 'nine', 'reallife', 'applications', 'of', 'industrial', 'relevance', 'following', 'this', 'approach', 'we', 'have', 'able', 'to', 'reduce', 'execution', 'time', 'up', 'to', '60', 'and', 'energy', 'consumption', 'up', 'to', '70']] | [-0.09565547968945577, 0.03164454217501713, -0.05232714027506373, 0.05740741113781012, -0.1003553116664527, -0.13900232189778416, 0.09612442810589167, 0.43338026257143136, -0.24972510281007826, -0.4125990979521284, 0.13197099484525443, -0.22086583803170398, -0.13066451135830628, 0.24235714090311722, -0.08501671334462506, 0.13218834770091306, 0.08019150701806038, -0.025417567504244665, -0.030603720190507982, -0.28338345972865464, 0.22839813789774088, 0.12566388844113266, 0.353747178667358, 0.08178362980603225, 0.07138369432816814, -0.039818878030581845, -0.019197007275319526, 0.020772680041513274, -0.08152624770717387, 0.10800668444587952, 0.3094422180771029, 0.1501398762643692, 0.360131635496925, -0.45292233965001144, -0.25012308289666496, 0.0719875734787257, 0.17494298943162745, 0.06356727292055324, -0.08719835281815558, -0.22037036708807425, 0.09493250166073382, -0.2563535138994219, -0.06294040608456329, -0.13824125574088642, 0.03314703798276328, -0.01841824077945646, -0.20929658662394754, -0.02571739358383985, 0.059192121742174975, 0.03777154291137343, -0.015766267367224727, -0.13327473175475404, 0.06009531789274502, 0.17518490654534646, 0.02916734493411486, -0.00028473881280256645, 0.1201357736939653, -0.06934484811167099, -0.15413636956105214, 0.37066808351803393, -0.01791178764006685, -0.16773940810549354, 0.20298177717135302, -0.012366845708576933, -0.1452954382125643, 0.12203744563850619, 0.24055311543680358, 0.08279160233510155, -0.22057389176731546, 0.07781796039651251, 0.02586548285381425, 0.20891378107591577, 0.08273560126748172, 0.06837542731423922, 0.1682222087919298, 0.28836695558672387, 0.03584795996374894, 0.18331341190441025, -0.07653272466175998, -0.10168114942516984, -0.18273705866701517, -0.17811889732108702, -0.18292747702383036, 0.026974745678816116, -0.03138529512863089, -0.08713109255398786, 0.406363967857841, 0.1947576628596243, 0.16377400434649889, 0.043540778051551786, 0.3548448912592398, 0.06384916396327464, 0.17386808533901496, 0.0856728012939649, 0.1869443465423371, 0.033504186853182516, 0.19135730682192223, -0.18358544942124613, 0.07698907274457198, -0.04290121657744286] |
710.4657 | New Schemes for Self-Testing RAM | This paper gives an overview of a new technique, named pseudo-ring testing
(PRT). PRT can be applied for testing wide type of random access memories
(RAM): bit- or word-oriented and single- or dual-port RAM's. An essential
particularity of the proposed methodology is the emulation of a linear
automaton over Galois field by memory own components.
| cs.AR | this paper gives an overview of a new technique named pseudoring testing prt prt can be applied for testing wide type of random access memories ram bit or wordoriented and single or dualport rams an essential particularity of the proposed methodology is the emulation of a linear automaton over galois field by memory own components | [['this', 'paper', 'gives', 'an', 'overview', 'of', 'a', 'new', 'technique', 'named', 'pseudoring', 'testing', 'prt', 'prt', 'can', 'be', 'applied', 'for', 'testing', 'wide', 'type', 'of', 'random', 'access', 'memories', 'ram', 'bit', 'or', 'wordoriented', 'and', 'single', 'or', 'dualport', 'rams', 'an', 'essential', 'particularity', 'of', 'the', 'proposed', 'methodology', 'is', 'the', 'emulation', 'of', 'a', 'linear', 'automaton', 'over', 'galois', 'field', 'by', 'memory', 'own', 'components']] | [-0.1548154658770231, 0.07077299792118455, -0.09665675875201651, 0.0021490938622843138, -0.12082428270104256, -0.22215232286940922, 0.040663273888640106, 0.3362565961751071, -0.3018425130708651, -0.272167778421532, 0.1179445176131346, -0.15061074078760364, -0.1345476714767177, 0.23632838814942675, -0.13526489673690362, 0.05850048044865781, 0.015597265399992465, 0.06585119031369686, -0.0017538502304391428, -0.29163065623830664, 0.24575657851316712, 0.07282623183405534, 0.3014998227865858, -0.019511572958435863, 0.12478332026776942, 0.055958086590875276, -0.044822025468403644, -0.005924514308571815, -0.05312210287560116, 0.08884364499033175, 0.24095075853507628, 0.18070089888166296, 0.3285881586203521, -0.4406890820034526, -0.19952695421578193, 0.05863115136321126, 0.14485597718845714, 0.09348540121520107, -0.0959806979041208, -0.275342139296911, 0.11181413424624638, -0.24433518621054562, -0.06508600763468579, -0.07722952182997357, 0.02910246736666357, 0.012874932256950574, -0.3148213222961534, -0.05268130003559318, 0.11046703020957384, 0.12098783794790506, -0.03529932127249512, -0.094202336398038, 0.13849696452644739, 0.09791652651673013, -0.06036028131757948, 0.08254148280883039, 0.11495702419938011, -0.09594905900938266, -0.18990186625583605, 0.36522291759875686, -0.0523667926307429, -0.15828508248722012, 0.16552449730648236, -0.0024964751696891405, -0.11354370855048976, 0.10451377106153152, 0.18396108380772852, 0.05893663350831379, -0.18431889308108526, 0.09527287665458227, -0.0451470125508918, 0.2086358701471578, 0.04617154484784061, 0.014460046767172488, 0.20311614375519144, 0.20802026919343256, 0.03370525106583955, 0.16255770523566754, -0.09029741255058484, -0.06313848338005218, -0.25776546718552706, -0.21402620089409705, -0.19233904043212532, 0.04762337819080461, -0.06278895874565933, -0.1888146372511983, 0.4223578975959258, 0.1435611196454953, 0.1046599712243981, 0.09460815526545048, 0.3347633430226283, 0.054974738229066136, 0.11523204588077285, 0.09472386304458434, 0.07704631313681602, 0.1386569903020493, 0.08634987028781324, -0.14915023704313418, 0.10870357107963752, 0.04903009558435191] |
710.4658 | Compositional Memory Systems for Multimedia Communicating Tasks | Conventional cache models are not suited for real-time parallel processing
because tasks may flush each other's data out of the cache in an unpredictable
manner. In this way the system is not compositional so the overall performance
is difficult to predict and the integration of new tasks expensive. This paper
proposes a new method that imposes compositionality to the system?s performance
and makes different memory hierarchy optimizations possible for multimedia
communicating tasks when running on embedded multiprocessor architectures. The
method is based on a cache allocation strategy that assigns sets of the unified
cache exclusively to tasks and to the communication buffers. We also
analytically formulate the problem and describe a method to compute the cache
partitioning ratio for optimizing the throughput and the consumed power. When
applied to a multiprocessor with memory hierarchy our technique delivers also
performance gain. Compared to the shared cache case, for an application
consisting of two jpeg decoders and one edge detection algorithm 5 times less
misses are experienced and for an mpeg2 decoder 6.5 times less misses are
experienced.
| cs.AR cs.MM | conventional cache models are not suited for realtime parallel processing because tasks may flush each others data out of the cache in an unpredictable manner in this way the system is not compositional so the overall performance is difficult to predict and the integration of new tasks expensive this paper proposes a new method that imposes compositionality to the systems performance and makes different memory hierarchy optimizations possible for multimedia communicating tasks when running on embedded multiprocessor architectures the method is based on a cache allocation strategy that assigns sets of the unified cache exclusively to tasks and to the communication buffers we also analytically formulate the problem and describe a method to compute the cache partitioning ratio for optimizing the throughput and the consumed power when applied to a multiprocessor with memory hierarchy our technique delivers also performance gain compared to the shared cache case for an application consisting of two jpeg decoders and one edge detection algorithm 5 times less misses are experienced and for an mpeg2 decoder 65 times less misses are experienced | [['conventional', 'cache', 'models', 'are', 'not', 'suited', 'for', 'realtime', 'parallel', 'processing', 'because', 'tasks', 'may', 'flush', 'each', 'others', 'data', 'out', 'of', 'the', 'cache', 'in', 'an', 'unpredictable', 'manner', 'in', 'this', 'way', 'the', 'system', 'is', 'not', 'compositional', 'so', 'the', 'overall', 'performance', 'is', 'difficult', 'to', 'predict', 'and', 'the', 'integration', 'of', 'new', 'tasks', 'expensive', 'this', 'paper', 'proposes', 'a', 'new', 'method', 'that', 'imposes', 'compositionality', 'to', 'the', 'systems', 'performance', 'and', 'makes', 'different', 'memory', 'hierarchy', 'optimizations', 'possible', 'for', 'multimedia', 'communicating', 'tasks', 'when', 'running', 'on', 'embedded', 'multiprocessor', 'architectures', 'the', 'method', 'is', 'based', 'on', 'a', 'cache', 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710.4659 | Synchronization Processor Synthesis for Latency Insensitive Systems | In this paper we present our contribution in terms of synchronization
processor for a SoC design methodology based on the theory of the latency
insensitive systems (LIS) of Carloni et al. Our contribution consists in IP
encapsulation into a new wrapper model which speed and area are optimized and
synthetizability guarantied. The main benefit of our approach is to preserve
the local IP performances when encapsulating them and reduce SoC silicon area.
| cs.AR | in this paper we present our contribution in terms of synchronization processor for a soc design methodology based on the theory of the latency insensitive systems lis of carloni et al our contribution consists in ip encapsulation into a new wrapper model which speed and area are optimized and synthetizability guarantied the main benefit of our approach is to preserve the local ip performances when encapsulating them and reduce soc silicon area | [['in', 'this', 'paper', 'we', 'present', 'our', 'contribution', 'in', 'terms', 'of', 'synchronization', 'processor', 'for', 'a', 'soc', 'design', 'methodology', 'based', 'on', 'the', 'theory', 'of', 'the', 'latency', 'insensitive', 'systems', 'lis', 'of', 'carloni', 'et', 'al', 'our', 'contribution', 'consists', 'in', 'ip', 'encapsulation', 'into', 'a', 'new', 'wrapper', 'model', 'which', 'speed', 'and', 'area', 'are', 'optimized', 'and', 'synthetizability', 'guarantied', 'the', 'main', 'benefit', 'of', 'our', 'approach', 'is', 'to', 'preserve', 'the', 'local', 'ip', 'performances', 'when', 'encapsulating', 'them', 'and', 'reduce', 'soc', 'silicon', 'area']] | [-0.1273760802578181, -0.009391802988414253, -0.02730134223986949, -0.039735189219936726, -0.02729042579552957, -0.13821798279615385, 0.10306194698371525, 0.34139615906668563, -0.2653539554748152, -0.35696983890874046, 0.06272570878832734, -0.23804811390915087, -0.18128005327390773, 0.21109468808863313, -0.1302926150716043, 0.03721054133826068, 0.03140044642080154, -0.0686780229876084, -0.031115730173353638, -0.2949776772958493, 0.27127712124825587, 0.10424667387934668, 0.3369951761327684, 0.06949504486152104, 0.05895700241838183, 0.017043786429400954, -0.008247045321123941, 0.015627966821193696, -0.06173193769396416, 0.19787011560983955, 0.23321197740733624, 0.11512732266315392, 0.2559056764734643, -0.42456198944044965, -0.17646643542684615, -0.00723191919470472, 0.10465628347093506, 0.0973412175845754, -0.049105093260628306, -0.2592209970378982, 0.11508767737873964, -0.20451822427234478, -0.08150590585012521, -0.05589960395757641, 0.019791340069579225, 0.03893403569569013, -0.2439405440485903, 0.02400062440761498, 0.08881812788812178, 0.03548902152106166, -0.03262417851282018, -0.12629854170206403, 0.029571346403099597, 0.10389890193016202, -0.023302172002981285, 0.04006852020642587, 0.13914581273815463, -0.05942487065746848, -0.09380992740126592, 0.36141560673713685, -0.015611199954790728, -0.1617503022010039, 0.16310590267780103, 0.012505749173994576, -0.14838293003849684, 0.10004140597635082, 0.24137425374771868, 0.07998101228981146, -0.1590901543862336, 0.09561248287708232, 0.01575391335146768, 0.2076768565390791, 0.006427929074769574, 0.04991660313680768, 0.16867395462468265, 0.24519112829584627, 0.07751114186165588, 0.1536007371198918, -0.10205699402015722, -0.09867368815549915, -0.2887044108273195, -0.20461534529126116, -0.17428237503128394, -0.016862196515181234, -0.05428806343053501, -0.1399191185033747, 0.45217176188847846, 0.21686183823538677, 0.1362109127354675, 0.06184042956114614, 0.3390152909926006, 0.07608019151791398, 0.09991619241024767, 0.13174483488712993, 0.25914394514901296, 0.07994779920471566, 0.13997882501488285, -0.22963625084209655, 0.057111185589539155, 0.04982800353983683] |
710.466 | Thermal-Aware Task Allocation and Scheduling for Embedded Systems | Temperature affects not only the reliability but also the performance, power,
and cost of the embedded system. This paper proposes a thermal-aware task
allocation and scheduling algorithm for embedded systems. The algorithm is used
as a sub-routine for hardware/software co-synthesis to reduce the peak
temperature and achieve a thermally even distribution while meeting real time
constraints. The paper investigates both power-aware and thermal-aware
approaches to task allocation and scheduling. The experimental results show
that the thermal-aware approach outperforms the power-aware schemes in terms of
maximal and average temperature reductions. To the best of our knowledge, this
is the first task allocation and scheduling algorithm that takes temperature
into consideration.
| cs.AR | temperature affects not only the reliability but also the performance power and cost of the embedded system this paper proposes a thermalaware task allocation and scheduling algorithm for embedded systems the algorithm is used as a subroutine for hardwaresoftware cosynthesis to reduce the peak temperature and achieve a thermally even distribution while meeting real time constraints the paper investigates both poweraware and thermalaware approaches to task allocation and scheduling the experimental results show that the thermalaware approach outperforms the poweraware schemes in terms of maximal and average temperature reductions to the best of our knowledge this is the first task allocation and scheduling algorithm that takes temperature into consideration | [['temperature', 'affects', 'not', 'only', 'the', 'reliability', 'but', 'also', 'the', 'performance', 'power', 'and', 'cost', 'of', 'the', 'embedded', 'system', 'this', 'paper', 'proposes', 'a', 'thermalaware', 'task', 'allocation', 'and', 'scheduling', 'algorithm', 'for', 'embedded', 'systems', 'the', 'algorithm', 'is', 'used', 'as', 'a', 'subroutine', 'for', 'hardwaresoftware', 'cosynthesis', 'to', 'reduce', 'the', 'peak', 'temperature', 'and', 'achieve', 'a', 'thermally', 'even', 'distribution', 'while', 'meeting', 'real', 'time', 'constraints', 'the', 'paper', 'investigates', 'both', 'poweraware', 'and', 'thermalaware', 'approaches', 'to', 'task', 'allocation', 'and', 'scheduling', 'the', 'experimental', 'results', 'show', 'that', 'the', 'thermalaware', 'approach', 'outperforms', 'the', 'poweraware', 'schemes', 'in', 'terms', 'of', 'maximal', 'and', 'average', 'temperature', 'reductions', 'to', 'the', 'best', 'of', 'our', 'knowledge', 'this', 'is', 'the', 'first', 'task', 'allocation', 'and', 'scheduling', 'algorithm', 'that', 'takes', 'temperature', 'into', 'consideration']] | [-0.16848604757244776, -0.014013830636982558, -0.0732999246123187, -0.007863149444205225, -0.08542976311382351, -0.16580910658583456, 0.1219226302250092, 0.4074729115386075, -0.23985129391449853, -0.35614622372347826, 0.11476081702751406, -0.21408779458372443, -0.15260003619494106, 0.22018932466130328, -0.12215953943994615, 0.08426847691656253, 0.07640789855066515, 0.028815419996293997, -0.024875765389211716, -0.30331970018189436, 0.25958510745560254, 0.11133043199709249, 0.3837344609884494, 0.10554004409307734, 0.10756556708963776, -0.007091221867402623, 0.01224838204600703, 0.011602358360680829, -0.07565486416236152, 0.09051777669783989, 0.28995574892865955, 0.1885090736381778, 0.2978904823550459, -0.3794278344566669, -0.20460817367457912, 0.12082693137980383, 0.15721985720815734, 0.043834138847460305, -0.0073189144642220455, -0.19925912255164954, 0.10480725431575551, -0.18168915184471038, -0.0020707916092435152, -0.06476845258394034, -0.04098470668829636, -0.00044617324655260376, -0.32318590060645425, 0.035444820750186457, 0.06768528652300529, -0.021931296299903764, -0.11831843022069116, -0.13738965585191282, 0.04571066197614536, 0.14039267418871915, 0.02119787238589531, 0.03269204013733142, 0.13345025278149394, -0.11571687240785825, -0.16411920576228187, 0.42742279882824746, -0.014676332164026045, -0.17578712090157791, 0.1291242146847445, -0.02059441555393945, -0.1584305609533683, 0.11637149419242498, 0.24189869815979256, 0.11771227236529556, -0.14579004817001454, 0.04405088538203576, 0.003852705343053975, 0.19800649009166507, 0.03936557103495259, 0.03811059714670917, 0.11882515268084175, 0.2481737990923431, 0.11617976380512118, 0.1625665230655171, -0.06400519320228641, -0.10896963250680203, -0.21453247606378356, -0.16608439722534166, -0.1832102211961232, -0.05322617176829927, -0.07450511420282872, -0.10265425306321933, 0.4060044298375692, 0.19544678353149136, 0.14846741228680546, 0.1558659351110424, 0.4271531068386698, 0.12253299924126322, 0.029605299994827958, 0.19083972822782932, 0.13127721195886716, 0.015406058722073127, 0.16284042414397412, -0.2891715654479596, 0.0849067543381227, 0.005400077986676212] |
710.4661 | Bright-Field AAPSM Conflict Detection and Correction | As feature sizes shrink, it will be necessary to use AAPSM
(Alternating-Aperture Phase Shift Masking) to image critical features,
especially on the polysilicon layer. This imposes additional constraints on the
layouts beyond traditional design rules. Of particular note is the requirement
that all critical features be flanked by opposite-phase shifters, while the
shifters obey minimum width and spacing requirements. A layout is called
phase-assignable if it satisfies this requirement. If a layout is not
phase-assignable, the phase conflicts have to removed to enable the use of
AAPSM for the layout. Previous work has sought to detect a suitable set of
phase Conflicts to be removed, as well as correct them. The contribution of
this paper are the following: (1) a new approach to detect a minimal set of
phase conflicts (also referred to as AAPSM conflicts), which when corrected
will produce a phase-assignable layout; (2) a novel layout modification scheme
for correcting these AAPSM conflicts. The proposed approach for conflict
detection shows significant improvements in the quality of results and runtime
for real industrial circuits, when compared to previous methods. To the best of
our knowledge, this is the first time layout modification results are presented
for bright-field AAPSM. Our experiments show that the percentage area increase
for making a layout phase-assignable ranges from 0.7-11.8%.
| cs.AR | as feature sizes shrink it will be necessary to use aapsm alternatingaperture phase shift masking to image critical features especially on the polysilicon layer this imposes additional constraints on the layouts beyond traditional design rules of particular note is the requirement that all critical features be flanked by oppositephase shifters while the shifters obey minimum width and spacing requirements a layout is called phaseassignable if it satisfies this requirement if a layout is not phaseassignable the phase conflicts have to removed to enable the use of aapsm for the layout previous work has sought to detect a suitable set of phase conflicts to be removed as well as correct them the contribution of this paper are the following 1 a new approach to detect a minimal set of phase conflicts also referred to as aapsm conflicts which when corrected will produce a phaseassignable layout 2 a novel layout modification scheme for correcting these aapsm conflicts the proposed approach for conflict detection shows significant improvements in the quality of results and runtime for real industrial circuits when compared to previous methods to the best of our knowledge this is the first time layout modification results are presented for brightfield aapsm our experiments show that the percentage area increase for making a layout phaseassignable ranges from 07118 | [['as', 'feature', 'sizes', 'shrink', 'it', 'will', 'be', 'necessary', 'to', 'use', 'aapsm', 'alternatingaperture', 'phase', 'shift', 'masking', 'to', 'image', 'critical', 'features', 'especially', 'on', 'the', 'polysilicon', 'layer', 'this', 'imposes', 'additional', 'constraints', 'on', 'the', 'layouts', 'beyond', 'traditional', 'design', 'rules', 'of', 'particular', 'note', 'is', 'the', 'requirement', 'that', 'all', 'critical', 'features', 'be', 'flanked', 'by', 'oppositephase', 'shifters', 'while', 'the', 'shifters', 'obey', 'minimum', 'width', 'and', 'spacing', 'requirements', 'a', 'layout', 'is', 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710.4662 | Bounding the number of rational places using Weierstrass semigroups | Let Lambda be a numerical semigroup. Assume there exists an algebraic
function field over GF(q) in one variable which possesses a rational place that
has Lambda as its Weierstrass semigroup. We ask the question as to how many
rational places such a function field can possibly have and we derive an upper
bound in terms of the generators of Lambda and q. Our bound is an improvement
to a bound by Lewittes which takes into account only the multiplicity of Lambda
and q. From the new bound we derive significant improvements to Serre's upper
bound in the cases q=2, 3 and 4. We finally show that Lewittes' bound has
important implications to the theory of towers of function fields.
| math.AG math.NT | let lambda be a numerical semigroup assume there exists an algebraic function field over gfq in one variable which possesses a rational place that has lambda as its weierstrass semigroup we ask the question as to how many rational places such a function field can possibly have and we derive an upper bound in terms of the generators of lambda and q our bound is an improvement to a bound by lewittes which takes into account only the multiplicity of lambda and q from the new bound we derive significant improvements to serres upper bound in the cases q2 3 and 4 we finally show that lewittes bound has important implications to the theory of towers of function fields | [['let', 'lambda', 'be', 'a', 'numerical', 'semigroup', 'assume', 'there', 'exists', 'an', 'algebraic', 'function', 'field', 'over', 'gfq', 'in', 'one', 'variable', 'which', 'possesses', 'a', 'rational', 'place', 'that', 'has', 'lambda', 'as', 'its', 'weierstrass', 'semigroup', 'we', 'ask', 'the', 'question', 'as', 'to', 'how', 'many', 'rational', 'places', 'such', 'a', 'function', 'field', 'can', 'possibly', 'have', 'and', 'we', 'derive', 'an', 'upper', 'bound', 'in', 'terms', 'of', 'the', 'generators', 'of', 'lambda', 'and', 'q', 'our', 'bound', 'is', 'an', 'improvement', 'to', 'a', 'bound', 'by', 'lewittes', 'which', 'takes', 'into', 'account', 'only', 'the', 'multiplicity', 'of', 'lambda', 'and', 'q', 'from', 'the', 'new', 'bound', 'we', 'derive', 'significant', 'improvements', 'to', 'serres', 'upper', 'bound', 'in', 'the', 'cases', 'q2', '3', 'and', '4', 'we', 'finally', 'show', 'that', 'lewittes', 'bound', 'has', 'important', 'implications', 'to', 'the', 'theory', 'of', 'towers', 'of', 'function', 'fields']] | [-0.1511150517661375, 0.09664707263760922, -0.13869400068867108, 0.07918699153507237, -0.06677813885123038, -0.1292619389137488, 0.053241651805563825, 0.29755824531952874, -0.2653119399392304, -0.30158680696196916, 0.07950575953885569, -0.2539339091847925, -0.13102145716469704, 0.2381918915692216, -0.048523589434540444, -0.015857995402150077, 0.0013600313300345123, 0.1358509320577904, -0.05163148621942441, -0.28490662084845436, 0.33706283647207025, 0.010660760562491267, 0.17800057609076417, 0.12459910944292024, 0.11486209061450693, -0.005382951472283286, 0.04897372033290502, -0.029291931206073457, -0.21001766445254613, 0.09312483669696923, 0.25727417057051377, 0.15720236060373924, 0.2625303706858589, -0.3803208601610156, -0.1711726752383744, 0.19471441775936038, 0.1936195342011061, 0.052242598408332265, -0.03844173556240667, -0.20550066890868068, 0.11984824858695864, -0.17826707070857725, -0.1289050374649653, -0.07219042033426651, 0.0980673072245285, 0.0029248757945264086, -0.3232194062698038, -0.004278618173219827, 0.12695071412770845, 0.06364145696098611, -0.04977786316469844, -0.17943315911243723, -0.013909388018552871, 0.10745703525246442, 0.05087202316846605, 0.08898800444797057, 0.05382605858671503, -0.14760237702896364, -0.11191672147760372, 0.3300027382098326, -0.11205534664610745, -0.20752161050982335, 0.11822405545346189, -0.16734357494782626, -0.11704480160857324, 0.11344535974394374, 0.16395357172904895, 0.10626574029349682, -0.05092390598494466, 0.19900946862831273, -0.13368896444664657, 0.17774005049150907, 0.07493611918997113, 0.04995955821878018, 0.13899406468292244, 0.09776756101671387, 0.09530341481064063, 0.15265214953771128, -0.027108885199144606, -0.0362875082015506, -0.3399171684907765, -0.1613277070265373, -0.13946235634605675, 0.10596550841807943, -0.12318635386358086, -0.15416892971686957, 0.34237244729140476, 0.11917475710951668, 0.2189819378105282, 0.06228183119600842, 0.23088683220342646, 0.1962723035606, 0.05054455960732924, 0.09569571992898938, 0.18490928090216607, 0.14758714697785488, -0.0294490244069348, -0.14079405019693703, 0.022445315099908273, 0.09623954399340168] |
710.4663 | Statistical Modeling of Pipeline Delay and Design of Pipeline under
Process Variation to Enhance Yield in sub-100nm Technologies | Operating frequency of a pipelined circuit is determined by the delay of the
slowest pipeline stage. However, under statistical delay variation in sub-100nm
technology regime, the slowest stage is not readily identifiable and the
estimation of the pipeline yield with respect to a target delay is a
challenging problem. We have proposed analytical models to estimate yield for a
pipelined design based on delay distributions of individual pipe stages. Using
the proposed models, we have shown that change in logic depth and imbalance
between the stage delays can improve the yield of a pipeline. A statistical
methodology has been developed to optimally design a pipeline circuit for
enhancing yield. Optimization results show that, proper imbalance among the
stage delays in a pipeline improves design yield by 9% for the same area and
performance (and area reduction by about 8.4% under a yield constraint) over a
balanced design.
| cs.AR | operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage however under statistical delay variation in sub100nm technology regime the slowest stage is not readily identifiable and the estimation of the pipeline yield with respect to a target delay is a challenging problem we have proposed analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages using the proposed models we have shown that change in logic depth and imbalance between the stage delays can improve the yield of a pipeline a statistical methodology has been developed to optimally design a pipeline circuit for enhancing yield optimization results show that proper imbalance among the stage delays in a pipeline improves design yield by 9 for the same area and performance and area reduction by about 84 under a yield constraint over a balanced design | [['operating', 'frequency', 'of', 'a', 'pipelined', 'circuit', 'is', 'determined', 'by', 'the', 'delay', 'of', 'the', 'slowest', 'pipeline', 'stage', 'however', 'under', 'statistical', 'delay', 'variation', 'in', 'sub100nm', 'technology', 'regime', 'the', 'slowest', 'stage', 'is', 'not', 'readily', 'identifiable', 'and', 'the', 'estimation', 'of', 'the', 'pipeline', 'yield', 'with', 'respect', 'to', 'a', 'target', 'delay', 'is', 'a', 'challenging', 'problem', 'we', 'have', 'proposed', 'analytical', 'models', 'to', 'estimate', 'yield', 'for', 'a', 'pipelined', 'design', 'based', 'on', 'delay', 'distributions', 'of', 'individual', 'pipe', 'stages', 'using', 'the', 'proposed', 'models', 'we', 'have', 'shown', 'that', 'change', 'in', 'logic', 'depth', 'and', 'imbalance', 'between', 'the', 'stage', 'delays', 'can', 'improve', 'the', 'yield', 'of', 'a', 'pipeline', 'a', 'statistical', 'methodology', 'has', 'been', 'developed', 'to', 'optimally', 'design', 'a', 'pipeline', 'circuit', 'for', 'enhancing', 'yield', 'optimization', 'results', 'show', 'that', 'proper', 'imbalance', 'among', 'the', 'stage', 'delays', 'in', 'a', 'pipeline', 'improves', 'design', 'yield', 'by', '9', 'for', 'the', 'same', 'area', 'and', 'performance', 'and', 'area', 'reduction', 'by', 'about', '84', 'under', 'a', 'yield', 'constraint', 'over', 'a', 'balanced', 'design']] | [-0.11354613856517007, 0.035423998823896255, -0.11152369437143714, -0.006714800260264148, -0.047420820715476056, -0.1696466108226553, 0.06310871525407852, 0.4165914605568055, -0.24093733954743868, -0.3574802887766166, 0.11687030892923703, -0.19398660703125048, -0.12892586386130592, 0.26655059852352253, -0.11139467989924509, 0.10491535043483283, 0.1395958910955965, 0.020291570938338024, -0.062165968778993, -0.2600690605701739, 0.23940171102429328, 0.09396315429385016, 0.3405644277389459, 0.004228557366907492, 0.15111025638853004, -0.024708464052718208, -0.03427603701446332, 0.043165389803193864, -0.09471682447286364, 0.10722255793504645, 0.26360301369688116, 0.17940391348136372, 0.27245429888380324, -0.3960804524039533, -0.23274773889740763, 0.08656608212785162, 0.11214266692566983, 0.09547087036985524, -0.04611736782398835, -0.22456055242238807, 0.10427183029558636, -0.1701296684062932, -0.04576087609997818, -0.031663350653232766, 0.014710094424940291, 0.031047354682766815, -0.28247211961911955, 0.05146948429344057, 0.05966276646952848, 0.03315492229279587, -0.04444571061782083, -0.12354428801989677, 0.02969417465711329, 0.12494669296639357, -0.022427205857979197, 0.022629210224919986, 0.13143240157190114, -0.10772355087735012, -0.10730908325790954, 0.3423804038261272, -0.07476741983713646, -0.19037560288391242, 0.12527687947874014, -0.063220422965202, -0.12925640917003003, 0.18826595530528448, 0.2201568654732031, 0.0713225131962119, -0.19055253636253502, 0.015489319176254731, 0.059137276234422005, 0.22190135994888083, 0.06581242065750012, 0.015996206745023833, 0.1713108839878977, 0.26511704487738763, 0.09995082004049628, 0.16737078193758875, -0.1177632161622018, -0.07661342382633766, -0.24675171822943046, -0.13169452831225129, -0.12809563252669412, -0.02407932290195592, -0.06431999463915863, -0.09361452324261262, 0.4013525529504836, 0.1491403698043733, 0.18313399124510435, 0.10594519955853672, 0.3294283825473315, 0.12535185227487364, 0.10693152228848048, 0.07351888755501128, 0.2649225119919497, 0.07701324722032715, 0.11708285548600691, -0.25616341171236584, 0.13040575917436406, 0.011360513892176807] |
710.4664 | Confronting the trans-Planckian question of inflationary cosmology with
dissipative effects | We provide a class of QFTs which exhibit dissipation above a threshold
energy, thereby breaking Lorentz invariance. Unitarity is preserved by coupling
the fields to additional degrees of freedom (heavy fields) which introduce the
rest frame. Using the Equivalence Principle, we define these theories in
arbitrary curved spacetime. We then confront the trans-Planckian question of
inflationary cosmology. When dissipation increases with the energy, the quantum
field describing adiabatic perturbations is completely damped at the onset of
inflation. However it still exists as a composite operator made with the
additional fields. And when these are in their ground state, the standard power
spectrum obtains if the threshold energy is much larger that the Hubble
parameter. In fact, as the energy redshifts below the threshold, the composite
operator behaves as if it were a free field endowed with standard vacuum
fluctuations. The relationship between our models and the Brane World scenarios
studied by Libanov and Rubakov displaying similar effects is discussed. The
signatures of dissipation will be studied in a forthcoming paper.
| hep-th | we provide a class of qfts which exhibit dissipation above a threshold energy thereby breaking lorentz invariance unitarity is preserved by coupling the fields to additional degrees of freedom heavy fields which introduce the rest frame using the equivalence principle we define these theories in arbitrary curved spacetime we then confront the transplanckian question of inflationary cosmology when dissipation increases with the energy the quantum field describing adiabatic perturbations is completely damped at the onset of inflation however it still exists as a composite operator made with the additional fields and when these are in their ground state the standard power spectrum obtains if the threshold energy is much larger that the hubble parameter in fact as the energy redshifts below the threshold the composite operator behaves as if it were a free field endowed with standard vacuum fluctuations the relationship between our models and the brane world scenarios studied by libanov and rubakov displaying similar effects is discussed the signatures of dissipation will be studied in a forthcoming paper | [['we', 'provide', 'a', 'class', 'of', 'qfts', 'which', 'exhibit', 'dissipation', 'above', 'a', 'threshold', 'energy', 'thereby', 'breaking', 'lorentz', 'invariance', 'unitarity', 'is', 'preserved', 'by', 'coupling', 'the', 'fields', 'to', 'additional', 'degrees', 'of', 'freedom', 'heavy', 'fields', 'which', 'introduce', 'the', 'rest', 'frame', 'using', 'the', 'equivalence', 'principle', 'we', 'define', 'these', 'theories', 'in', 'arbitrary', 'curved', 'spacetime', 'we', 'then', 'confront', 'the', 'transplanckian', 'question', 'of', 'inflationary', 'cosmology', 'when', 'dissipation', 'increases', 'with', 'the', 'energy', 'the', 'quantum', 'field', 'describing', 'adiabatic', 'perturbations', 'is', 'completely', 'damped', 'at', 'the', 'onset', 'of', 'inflation', 'however', 'it', 'still', 'exists', 'as', 'a', 'composite', 'operator', 'made', 'with', 'the', 'additional', 'fields', 'and', 'when', 'these', 'are', 'in', 'their', 'ground', 'state', 'the', 'standard', 'power', 'spectrum', 'obtains', 'if', 'the', 'threshold', 'energy', 'is', 'much', 'larger', 'that', 'the', 'hubble', 'parameter', 'in', 'fact', 'as', 'the', 'energy', 'redshifts', 'below', 'the', 'threshold', 'the', 'composite', 'operator', 'behaves', 'as', 'if', 'it', 'were', 'a', 'free', 'field', 'endowed', 'with', 'standard', 'vacuum', 'fluctuations', 'the', 'relationship', 'between', 'our', 'models', 'and', 'the', 'brane', 'world', 'scenarios', 'studied', 'by', 'libanov', 'and', 'rubakov', 'displaying', 'similar', 'effects', 'is', 'discussed', 'the', 'signatures', 'of', 'dissipation', 'will', 'be', 'studied', 'in', 'a', 'forthcoming', 'paper']] | [-0.15349970878647454, 0.24763147138781053, -0.07223591289569806, 0.11907083561820303, -0.06821778530431305, -0.15362282237038016, -0.01942644106188359, 0.3202379989608593, -0.25546031601771096, -0.3082679421007192, 0.08527434446515526, -0.2430127109042727, -0.09384987562944418, 0.15685199903594274, -0.011491858681454461, 0.01344229716576151, 0.0217937444179655, 0.06063851101489975, -0.057481644496723966, -0.21419794008565637, 0.35997505365876403, 0.10980527250567373, 0.2616937469922491, 0.041545744392932696, 0.095408611848245, -0.024275991715733292, 0.03894950565262064, 0.041633924195879086, -0.14700396601876178, 0.05727993462616357, 0.20352181112902193, 0.08429491298394443, 0.23900413526133937, -0.3865815880791058, -0.24563231086496198, 0.13682352907173115, 0.1104892425420942, 0.12808435775350624, -0.03919179277227965, -0.27240055205421687, 0.05250872123281102, -0.1438273631460612, -0.16775625710067002, -0.059175162204161025, -0.004370986303512955, -0.036206479551485524, -0.24166717976001065, 0.11287296641226748, 0.04151582997223396, 0.04523392662749703, -0.057070465802529155, -0.05166763184762962, -0.04833938677095362, 0.060108887802150936, 0.10132666266683114, 0.03421733065469731, 0.14811481343934962, -0.1806531486448628, -0.07715039021892131, 0.39325180497659734, -0.08908847012397277, -0.18025039928860564, 0.15641354014490835, -0.14464359969650148, -0.0989298141933771, 0.10080081330937438, 0.10436107678967114, 0.0782455088317218, -0.11747688199300457, 0.16771647352181077, 0.0023917278189476603, 0.15068781623043692, 0.07478819111053496, 0.08741978766429706, 0.23567480576560784, 0.11094174450869568, 0.045082832918056016, 0.1344507196387717, -0.041557109272713666, -0.11001046682493044, -0.3795545392410731, -0.11835295211292318, -0.14504736751736796, 0.09041682177859761, -0.08987263379146321, -0.1449893660975631, 0.38420459215898484, 0.14768675318850238, 0.19667135864033325, 0.04428956520980632, 0.271853537230543, 0.14619350839494424, 0.0772380908254049, 0.08045121445389432, 0.32719902107602306, 0.1250719715050317, 0.10496923639356384, -0.20233855579191676, -0.02429963219580213, 0.042628017382299495] |
710.4665 | New Perspectives and Opportunities From the Wild West of Microelectronic
Biochips | Application of Microelectronic to bioanalysis is an emerging field which
holds great promise. From the standpoint of electronic and system design,
biochips imply a radical change of perspective, since new, completely different
constraints emerge while other usual constraints can be relaxed. While
electronic parts of the system can rely on the usual established design-flow,
fluidic and packaging design, calls for a new approach which relies
significantly on experiments. We hereby make some general considerations based
on our experience in the development of biochips for cell analysis.
| cs.AR | application of microelectronic to bioanalysis is an emerging field which holds great promise from the standpoint of electronic and system design biochips imply a radical change of perspective since new completely different constraints emerge while other usual constraints can be relaxed while electronic parts of the system can rely on the usual established designflow fluidic and packaging design calls for a new approach which relies significantly on experiments we hereby make some general considerations based on our experience in the development of biochips for cell analysis | [['application', 'of', 'microelectronic', 'to', 'bioanalysis', 'is', 'an', 'emerging', 'field', 'which', 'holds', 'great', 'promise', 'from', 'the', 'standpoint', 'of', 'electronic', 'and', 'system', 'design', 'biochips', 'imply', 'a', 'radical', 'change', 'of', 'perspective', 'since', 'new', 'completely', 'different', 'constraints', 'emerge', 'while', 'other', 'usual', 'constraints', 'can', 'be', 'relaxed', 'while', 'electronic', 'parts', 'of', 'the', 'system', 'can', 'rely', 'on', 'the', 'usual', 'established', 'designflow', 'fluidic', 'and', 'packaging', 'design', 'calls', 'for', 'a', 'new', 'approach', 'which', 'relies', 'significantly', 'on', 'experiments', 'we', 'hereby', 'make', 'some', 'general', 'considerations', 'based', 'on', 'our', 'experience', 'in', 'the', 'development', 'of', 'biochips', 'for', 'cell', 'analysis']] | [-0.10633777900160674, 0.07763065915599274, -0.10220925643601839, -0.013693664068191806, -0.12057618726702297, -0.17005396219079985, 0.058456374343265505, 0.31368418083909677, -0.25317077642197117, -0.2985974943594021, 0.1391045507755788, -0.21080607030102436, -0.19209524686722196, 0.2985730915604269, -0.07995954080320457, 0.023160212415763562, 0.07604816792779329, -0.018580280989408494, -0.08278658294721561, -0.20163759120246944, 0.32029878124868605, 0.050401642398141766, 0.36117476711378377, 0.11661837464746307, 0.08128977933460299, 0.035321009263177126, 0.00090560333474594, 0.03752606062985518, -0.09451981438871693, 0.1904581289170036, 0.2225504583953058, 0.16347856121137738, 0.27123919260852475, -0.5137737689868492, -0.214857496956692, 0.04071638864629409, 0.13161964383633698, 0.11473042272195658, -0.09277486416155144, -0.26547458362491694, 0.07114341963520822, -0.15442147526670905, -0.10890286909964154, -0.11065327201915139, -0.04262249211862902, 0.03626802069381537, -0.2518233565147966, 0.0060836883508326375, 0.07414193798185272, 0.04466123378232998, -0.07441149806768141, -0.14845509558696957, 0.01804355186793734, 0.13812259249115252, 0.021127970390679204, -0.008357428077279645, 0.1974819180336507, -0.11846704806255944, -0.1203166146598318, 0.4198338972623734, 0.004011471739367527, -0.16064212785705048, 0.21725195026956498, -0.07564871405415675, -0.1686986240120057, 0.08597632508355994, 0.17250202758347286, 0.07381559210445951, -0.16289428207365905, 0.08249017212622087, 0.004822890159180936, 0.1581767789033406, 0.0064861930653398086, 0.09534925511449246, 0.20866387027644498, 0.20817361917784985, 0.09502904857782757, 0.10443728700869113, -0.012240301256122835, -0.11778345824910931, -0.2341768924092107, -0.195975489344667, -0.14748222818324233, 0.05908978827544214, -0.0478580319264438, -0.15055913529495762, 0.37331639933673777, 0.16790170736254795, 0.12536968413521263, 0.020665598334744573, 0.30422986978117156, 0.08598986094516209, 0.11306857706650215, 0.000636781838393825, 0.2561856307106449, 0.057093211351072086, 0.10984213102389784, -0.16394872583229753, 0.08172189949956887, 0.007424444634029094] |
710.4666 | Verification of Embedded Memory Systems using Efficient Memory Modeling | We describe verification techniques for embedded memory systems using
efficient memory modeling (EMM), without explicitly modeling each memory bit.
We extend our previously proposed approach of EMM in Bounded Model Checking
(BMC) for a single read/write port single memory system, to more commonly
occurring systems with multiple memories, having multiple read and write ports.
More importantly, we augment such EMM to providing correctness proofs, in
addition to finding real bugs as before. The novelties of our verification
approach are in a) combining EMM with proof-based abstraction that preserves
the correctness of a property up to a certain analysis depth of SAT-based BMC,
and b) modeling arbitrary initial memory state precisely and thereby, providing
inductive proofs using SAT-based BMC for embedded memory systems. Similar to
the previous approach, we construct a verification model by eliminating memory
arrays, but retaining the memory interface signals with their control logic and
adding constraints on those signals at every analysis depth to preserve the
data forwarding semantics. The size of these EMM constraints depends
quadratically on the number of memory accesses and the number of read and write
ports; and linearly on the address and data widths and the number of memories.
We show the effectiveness of our approach on several industry designs and
software programs.
| cs.LO | we describe verification techniques for embedded memory systems using efficient memory modeling emm without explicitly modeling each memory bit we extend our previously proposed approach of emm in bounded model checking bmc for a single readwrite port single memory system to more commonly occurring systems with multiple memories having multiple read and write ports more importantly we augment such emm to providing correctness proofs in addition to finding real bugs as before the novelties of our verification approach are in a combining emm with proofbased abstraction that preserves the correctness of a property up to a certain analysis depth of satbased bmc and b modeling arbitrary initial memory state precisely and thereby providing inductive proofs using satbased bmc for embedded memory systems similar to the previous approach we construct a verification model by eliminating memory arrays but retaining the memory interface signals with their control logic and adding constraints on those signals at every analysis depth to preserve the data forwarding semantics the size of these emm constraints depends quadratically on the number of memory accesses and the number of read and write ports and linearly on the address and data widths and the number of memories we show the effectiveness of our approach on several industry designs and software programs | [['we', 'describe', 'verification', 'techniques', 'for', 'embedded', 'memory', 'systems', 'using', 'efficient', 'memory', 'modeling', 'emm', 'without', 'explicitly', 'modeling', 'each', 'memory', 'bit', 'we', 'extend', 'our', 'previously', 'proposed', 'approach', 'of', 'emm', 'in', 'bounded', 'model', 'checking', 'bmc', 'for', 'a', 'single', 'readwrite', 'port', 'single', 'memory', 'system', 'to', 'more', 'commonly', 'occurring', 'systems', 'with', 'multiple', 'memories', 'having', 'multiple', 'read', 'and', 'write', 'ports', 'more', 'importantly', 'we', 'augment', 'such', 'emm', 'to', 'providing', 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710.4667 | Integration, Verification and Layout of a Complex Multimedia SOC | We present our experience of designing a single-chip controller for advanced
digital still camera from specification all the way to mass production. The
process involves collaboration with camera system designer, IP vendors, EDA
vendors, silicon wafer foundry, package and testing houses, and camera maker.
We also co-work with academic research groups to develop a JPEG codec IP and
memory BIST and SOC testing methodology. In this presentation, we cover the
problems encountered, our solutions, and lessons learned.
| cs.AR cs.MM | we present our experience of designing a singlechip controller for advanced digital still camera from specification all the way to mass production the process involves collaboration with camera system designer ip vendors eda vendors silicon wafer foundry package and testing houses and camera maker we also cowork with academic research groups to develop a jpeg codec ip and memory bist and soc testing methodology in this presentation we cover the problems encountered our solutions and lessons learned | [['we', 'present', 'our', 'experience', 'of', 'designing', 'a', 'singlechip', 'controller', 'for', 'advanced', 'digital', 'still', 'camera', 'from', 'specification', 'all', 'the', 'way', 'to', 'mass', 'production', 'the', 'process', 'involves', 'collaboration', 'with', 'camera', 'system', 'designer', 'ip', 'vendors', 'eda', 'vendors', 'silicon', 'wafer', 'foundry', 'package', 'and', 'testing', 'houses', 'and', 'camera', 'maker', 'we', 'also', 'cowork', 'with', 'academic', 'research', 'groups', 'to', 'develop', 'a', 'jpeg', 'codec', 'ip', 'and', 'memory', 'bist', 'and', 'soc', 'testing', 'methodology', 'in', 'this', 'presentation', 'we', 'cover', 'the', 'problems', 'encountered', 'our', 'solutions', 'and', 'lessons', 'learned']] | [-0.09131636274181992, 3.103871437671938e-05, -0.07971966086494688, -0.018107334241353544, -0.14800300667871183, -0.2602394323820542, 0.06361474937109865, 0.4550561906377736, -0.2455772635723023, -0.3844617264296271, 0.13291631752815047, -0.27018727074793886, -0.14577288935144775, 0.2140592544976818, -0.14962195381552815, 0.08648952105891351, 0.09313214870512877, -0.10998221001845147, -0.009885155687745856, -0.29814999018287236, 0.2623377543089813, 0.0758330500807221, 0.31243628155023445, -0.0006016148866987542, 0.11258385386808138, 0.032537113473824174, -0.02689665354601426, -0.0589203748876523, -0.10382202811735242, 0.11208610493141398, 0.3635776479924588, 0.22667302318701618, 0.2885600253449459, -0.4161320193425605, -0.10612970046502979, 0.017645992792064424, 0.06281515725545193, 0.048706167101811026, -0.13156311597834391, -0.3584433534721795, 0.08512661941839676, -0.2557076033952303, -0.06258882430235022, -0.0056694261392725535, -0.03830963133001014, -0.013442639261484146, -0.26812474151436044, -0.11600268767314877, 0.012420814790713944, 0.09026409007032941, -0.05404089575351559, -0.12363096844178233, 0.051469122408889234, 0.15664669212051913, 0.0034564646189928203, 0.03615376787370463, 0.2241839848054377, -0.1437350522916715, -0.13891159892572383, 0.3479317884990259, 0.031852496270163864, -0.11999837712899439, 0.15922970531621677, -0.033698769310783395, -0.15246089799697266, 0.0536838266875987, 0.2340687082185851, 0.033347896416671574, -0.217881961664381, 0.0676063799052683, 0.05095114881834505, 0.2281964868031393, 0.05596883109032397, -0.009707436112588957, 0.18485777523049987, 0.27440758277417016, 0.04295205458459493, 0.13363728011762233, -0.055671612759684456, -0.060594111959768555, -0.2518090342759694, -0.19279890429032476, -0.11993380540546864, -0.012233404592782455, -0.05715662323908825, -0.14783470271657662, 0.38013839746188177, 0.2543434727979873, 0.004284440686828212, 0.07924742393783833, 0.39492899199065407, -0.014757421489584407, 0.16669621982758767, 0.11515861814596544, 0.15449434285983443, -0.007124676862363948, 0.23255718036211634, -0.10564043585327454, 0.048922979700268786, -0.0006217535701580346] |
710.4668 | A generalization of Tverberg's Theorem | The well know theorem of Tverberg states that if n > (d+1)(r-1) then one can
partition any set of n points in R^d to r disjoint subsets whose convex hulls
have a common point. The numbers T(d,r) = (d + 1)(r - 1) + 1 are known as
Tverberg numbers. Reay asks the following question: if we add an additional
parameter k (1 < k < r+1) what is the minimal number of points we need in order
to guarantee that there exists an r partition of them such that any k of the r
convex hulls intersect. This minimal number is denoted by T(d,r,k). Reay
conjectured that T(d,r,k) = T(d,r) for all d,r and k. In this article we prove
that this is true for the following cases: when k > [ (d+3)/2 ]-1 or when d <
rk/(r-k)-1 and for the specific values d = 3; r = 4; k = 2 and d = 5; r = 3; k
= 2.
| math.CO | the well know theorem of tverberg states that if n d1r1 then one can partition any set of n points in rd to r disjoint subsets whose convex hulls have a common point the numbers tdr d 1r 1 1 are known as tverberg numbers reay asks the following question if we add an additional parameter k 1 k r1 what is the minimal number of points we need in order to guarantee that there exists an r partition of them such that any k of the r convex hulls intersect this minimal number is denoted by tdrk reay conjectured that tdrk tdr for all dr and k in this article we prove that this is true for the following cases when k d32 1 or when d rkrk1 and for the specific values d 3 r 4 k 2 and d 5 r 3 k 2 | [['the', 'well', 'know', 'theorem', 'of', 'tverberg', 'states', 'that', 'if', 'n', 'd1r1', 'then', 'one', 'can', 'partition', 'any', 'set', 'of', 'n', 'points', 'in', 'rd', 'to', 'r', 'disjoint', 'subsets', 'whose', 'convex', 'hulls', 'have', 'a', 'common', 'point', 'the', 'numbers', 'tdr', 'd', '1r', '1', '1', 'are', 'known', 'as', 'tverberg', 'numbers', 'reay', 'asks', 'the', 'following', 'question', 'if', 'we', 'add', 'an', 'additional', 'parameter', 'k', '1', 'k', 'r1', 'what', 'is', 'the', 'minimal', 'number', 'of', 'points', 'we', 'need', 'in', 'order', 'to', 'guarantee', 'that', 'there', 'exists', 'an', 'r', 'partition', 'of', 'them', 'such', 'that', 'any', 'k', 'of', 'the', 'r', 'convex', 'hulls', 'intersect', 'this', 'minimal', 'number', 'is', 'denoted', 'by', 'tdrk', 'reay', 'conjectured', 'that', 'tdrk', 'tdr', 'for', 'all', 'dr', 'and', 'k', 'in', 'this', 'article', 'we', 'prove', 'that', 'this', 'is', 'true', 'for', 'the', 'following', 'cases', 'when', 'k', 'd32', '1', 'or', 'when', 'd', 'rkrk1', 'and', 'for', 'the', 'specific', 'values', 'd', '3', 'r', '4', 'k', '2', 'and', 'd', '5', 'r', '3', 'k', '2']] | [-0.18772859554216786, 0.14698452040592982, -0.022894990449719183, 0.027540238795580565, -0.008724386969880833, -0.2256486313059353, 0.06458262600724331, 0.30357421676048657, -0.28332825032733644, -0.2770190387052464, 0.08930674741139075, -0.3267253528550997, -0.11112271893567607, 0.11687892591385367, -0.05238455360416661, 0.013158862784417783, -0.00924370049985803, 0.11175778416356633, -0.00618708965212263, -0.33187340214275396, 0.3022942051187262, -0.09925436365607006, 0.11767266538902674, 0.07060237214216715, 0.033366720726179494, 0.015340980796885865, 0.03418893203907809, 0.06020734988534739, -0.20718295331292344, 0.06391919307676111, 0.28385137485249057, 0.20661336800142133, 0.2838512257887767, -0.3506957457264091, -0.13597666314079335, 0.21450932423984698, 0.15009263589965194, -0.01192406060213184, 0.052264315396925054, -0.14162387958747316, 0.21038206097249829, -0.0950963548612553, -0.1439973814933971, -0.019504427714468715, 0.19032967261240616, -0.017364738535109933, -0.3227370190466722, -0.031408457450203965, 0.1557257219317037, 0.08899127360648261, 0.007968639560903493, -0.2174931948131823, -0.010969147261987616, 0.08550876658124901, 0.007546713883448001, 0.13897495966574008, 0.034397331501155363, -0.07797405506822873, -0.08567451345376097, 0.3524648252666205, -0.01523731334682007, -0.18616838064174968, 0.16317401635965292, -0.19328107486303547, -0.13903005264448717, 0.12949698202155688, 0.06757516895381772, 0.14457051928799886, -0.05720295239068157, 0.1841294370071435, -0.13633747305721045, 0.15309993979473063, 0.13175441991371734, -0.015907184403207337, 0.126305351105447, 0.04984582239644719, 0.12858436918749078, 0.09113579920258608, -0.054202811335176036, 0.05552731556296869, -0.37872000824712165, -0.15686647532755263, -0.22822610363347937, 0.13096330203506704, -0.13521975059344327, -0.10888309062334832, 0.298970774211758, 0.10708426173552106, 0.23607501455654317, 0.09395565006269754, 0.227712060275188, 0.04609468909661478, 0.004330545012559091, 0.1686918881096571, 0.11770888922696972, 0.07855566682691288, -0.02580321920788163, -0.12924685544119432, -0.011790844520645124, 0.10897641323532883] |
710.4669 | SOC Testing Methodology and Practice | On a commercial digital still camera (DSC) controller chip we practice a
novel SOC test integration platform, solving real problems in test scheduling,
test IO reduction, timing of functional test, scan IO sharing, embedded memory
built-in self-test (BIST), etc. The chip has been fabricated and tested
successfully by our approach. Test results justify that short test integration
cost, short test time, and small area overhead can be achieved. To support SOC
testing, a memory BIST compiler and an SOC testing integration system have been
developed.
| cs.AR | on a commercial digital still camera dsc controller chip we practice a novel soc test integration platform solving real problems in test scheduling test io reduction timing of functional test scan io sharing embedded memory builtin selftest bist etc the chip has been fabricated and tested successfully by our approach test results justify that short test integration cost short test time and small area overhead can be achieved to support soc testing a memory bist compiler and an soc testing integration system have been developed | [['on', 'a', 'commercial', 'digital', 'still', 'camera', 'dsc', 'controller', 'chip', 'we', 'practice', 'a', 'novel', 'soc', 'test', 'integration', 'platform', 'solving', 'real', 'problems', 'in', 'test', 'scheduling', 'test', 'io', 'reduction', 'timing', 'of', 'functional', 'test', 'scan', 'io', 'sharing', 'embedded', 'memory', 'builtin', 'selftest', 'bist', 'etc', 'the', 'chip', 'has', 'been', 'fabricated', 'and', 'tested', 'successfully', 'by', 'our', 'approach', 'test', 'results', 'justify', 'that', 'short', 'test', 'integration', 'cost', 'short', 'test', 'time', 'and', 'small', 'area', 'overhead', 'can', 'be', 'achieved', 'to', 'support', 'soc', 'testing', 'a', 'memory', 'bist', 'compiler', 'and', 'an', 'soc', 'testing', 'integration', 'system', 'have', 'been', 'developed']] | [-0.1705548318212523, -0.029488048358539614, -0.06965486710507642, 0.02298349056064206, -0.07360670533688629, -0.30965453408768073, 0.07169087112278623, 0.4180480778546018, -0.19619978189687518, -0.40352026300833505, 0.1371925887364127, -0.1705691753393587, -0.09345571794821059, 0.28595419961424984, -0.12600547513404095, 0.1859923299840268, 0.12258410186452025, -0.11367656253552173, -0.02831996364368345, -0.331718222172383, 0.14318166270660346, 0.09428998199017609, 0.38569732571897264, 0.049132834489950365, 0.10957453534664477, -0.04262147592106724, 0.0020378412350135692, 0.02868923708139097, 0.00032009982242016123, 0.08572412249700659, 0.2881255100316861, 0.1620269917499493, 0.34658501624020144, -0.4793397345881471, -0.15782384945846656, 0.004590824969551143, 0.06948897158453131, 0.03875429772169275, -0.09432901012409917, -0.3282652989522937, 0.10254558063495685, -0.2569884624057415, -0.03438330228056978, -0.15250774085631266, 0.027477528297287578, -0.0060363900573814615, -0.2635859727640362, -0.07643778627628789, 0.03055075505912742, 0.13009229157503474, -0.028974644637064024, -0.07105907834929359, 0.07487557472606354, 0.09416267950197353, -0.04235839458072887, 0.025801819656044243, 0.18342427300179706, -0.02844115680850604, -0.20425858120707904, 0.3295862459084567, -0.012792837211643072, -0.1887733192895265, 0.17236155632006772, -0.005228321325472173, -0.11776467062094632, 0.08682673642247477, 0.26658571662709996, 0.04332168772816658, -0.2310155894196428, 0.12374583244227859, 0.019690203617381698, 0.30253431981100753, 0.10768889185479459, 0.002259647410691661, 0.166304495295181, 0.29790910077007376, -0.004336334291078588, 0.1530971430200974, -0.12219821368891964, -0.09366646575714078, -0.23710873359677326, -0.225060633676784, -0.23741308193215552, -0.00795433389789918, -0.06278799004965763, -0.1391453305916751, 0.3441667888203965, 0.18831621056203457, 0.020535403270931805, 0.10485544050221934, 0.3592412363956956, 0.07933305172824903, 0.1921876255532398, 0.08937479508492877, 0.17481843881747303, -0.0007272619288414717, 0.1518129492562045, -0.21241207252640057, 0.059869543243856994, -0.03247807528823614] |
710.467 | Evolutionary Optimization in Code-Based Test Compression | We provide a general formulation for the code-based test compression problem
with fixed-length input blocks and propose a solution approach based on
Evolutionary Algorithms. In contrast to existing code-based methods, we allow
unspecified values in matching vectors, which allows encoding of arbitrary test
sets using a relatively small number of code-words. Experimental results for
both stuck-at and path delay fault test sets for ISCAS circuits demonstrate an
improvement compared to existing techniques.
| cs.AR | we provide a general formulation for the codebased test compression problem with fixedlength input blocks and propose a solution approach based on evolutionary algorithms in contrast to existing codebased methods we allow unspecified values in matching vectors which allows encoding of arbitrary test sets using a relatively small number of codewords experimental results for both stuckat and path delay fault test sets for iscas circuits demonstrate an improvement compared to existing techniques | [['we', 'provide', 'a', 'general', 'formulation', 'for', 'the', 'codebased', 'test', 'compression', 'problem', 'with', 'fixedlength', 'input', 'blocks', 'and', 'propose', 'a', 'solution', 'approach', 'based', 'on', 'evolutionary', 'algorithms', 'in', 'contrast', 'to', 'existing', 'codebased', 'methods', 'we', 'allow', 'unspecified', 'values', 'in', 'matching', 'vectors', 'which', 'allows', 'encoding', 'of', 'arbitrary', 'test', 'sets', 'using', 'a', 'relatively', 'small', 'number', 'of', 'codewords', 'experimental', 'results', 'for', 'both', 'stuckat', 'and', 'path', 'delay', 'fault', 'test', 'sets', 'for', 'iscas', 'circuits', 'demonstrate', 'an', 'improvement', 'compared', 'to', 'existing', 'techniques']] | [-0.12237882639359061, -0.014590040701174681, -0.08252201365151753, 0.0623762085807458, -0.05809410639469408, -0.20607170400277633, 0.09340580332920784, 0.4108827304508951, -0.22396992603575605, -0.3099631253345352, 0.10435909107521486, -0.21142003950747798, -0.15226667408650327, 0.2437569271035803, -0.11975387463139163, 0.17547829392767905, 0.10975832042438721, 0.008591729443044946, -0.08542562403535056, -0.29403047137505683, 0.2596190016095837, 0.03874721992502196, 0.3484420113317255, -0.020790023690400023, 0.12393883975326186, 0.018298773961659107, -0.05173484009638843, 0.034969812423999734, -0.10757442374435616, 0.1726148750021821, 0.28954581552534364, 0.2117259429133911, 0.23609984746306306, -0.4291412149969902, -0.18895420050507206, 0.07599129119060105, 0.1339999080745555, 0.2016672793720823, -0.061760133250370726, -0.2432299564825371, 0.12268254230568548, -0.16676593045445365, -0.011513153000527786, -0.09937935483847266, -0.025658140851495165, 0.008408635673630569, -0.3635718008865499, -0.0009663945076883667, 0.026879824232310057, 0.015122739200402672, -0.07245972819914136, -0.14749822504786103, 0.13480374239750542, 0.09569646685203123, -0.013526530341348715, 0.04835526694336699, 0.07729030350714715, -0.07265220008169611, -0.2189231155983483, 0.3709500602627587, -0.04202065687018654, -0.24136874441238534, 0.18868416461433904, 0.007172124887195726, -0.12406539051638295, 0.1043099718582299, 0.21335644824689048, 0.13065504629371893, -0.10344197753713363, 0.04210619304568455, -0.033277664669892855, 0.20560419316300088, 0.10064072824186748, 0.06036562672832386, 0.15281423620732917, 0.18169786175712943, 0.07329381680271278, 0.17272178963564025, -0.10159785408824165, -0.052401486713077046, -0.269765582246085, -0.12495664949528873, -0.1459677841113363, -0.03410941261487702, -0.14481379919864898, -0.19347958028083667, 0.3657713005086407, 0.2243664320428959, 0.20151872819082606, 0.1722182509013995, 0.3548318701278832, 0.032343221918886736, 0.06653535254817042, 0.12174115310578297, 0.13496991708557793, 0.09724524862637433, 0.0050714635096179945, -0.16338768380066743, 0.08682954860463117, 0.0896139014318275] |
710.4671 | An Application-Specific Design Methodology for STbus Crossbar Generation | As the communication requirements of current and future Multiprocessor
Systems on Chips (MPSoCs) continue to increase, scalable communication
architectures are needed to support the heavy communication demands of the
system. This is reflected in the recent trend that many of the standard bus
products such as STbus, have now introduced the capability of designing a
crossbar with multiple buses operating in parallel. The crossbar configuration
should be designed to closely match the application traffic characteristics and
performance requirements. In this work we address this issue of
application-specific design of optimal crossbar (using STbus crossbar
architecture), satisfying the performance requirements of the application and
optimal binding of cores onto the crossbar resources. We present a simulation
based design approach that is based on analysis of actual traffic trace of the
application, considering local variations in traffic rates, temporal overlap
among traffic streams and criticality of traffic streams. Our methodology is
applied to several MPSoC designs and the resulting crossbar platforms are
validated for performance by cycle-accurate SystemC simulation of the designs.
The experimental case studies show large reduction in packet latencies (up to
7x) and large crossbar component savings (up to 3.5x) compared to traditional
design approaches.
| cs.AR | as the communication requirements of current and future multiprocessor systems on chips mpsocs continue to increase scalable communication architectures are needed to support the heavy communication demands of the system this is reflected in the recent trend that many of the standard bus products such as stbus have now introduced the capability of designing a crossbar with multiple buses operating in parallel the crossbar configuration should be designed to closely match the application traffic characteristics and performance requirements in this work we address this issue of applicationspecific design of optimal crossbar using stbus crossbar architecture satisfying the performance requirements of the application and optimal binding of cores onto the crossbar resources we present a simulation based design approach that is based on analysis of actual traffic trace of the application considering local variations in traffic rates temporal overlap among traffic streams and criticality of traffic streams our methodology is applied to several mpsoc designs and the resulting crossbar platforms are validated for performance by cycleaccurate systemc simulation of the designs the experimental case studies show large reduction in packet latencies up to 7x and large crossbar component savings up to 35x compared to traditional design approaches | [['as', 'the', 'communication', 'requirements', 'of', 'current', 'and', 'future', 'multiprocessor', 'systems', 'on', 'chips', 'mpsocs', 'continue', 'to', 'increase', 'scalable', 'communication', 'architectures', 'are', 'needed', 'to', 'support', 'the', 'heavy', 'communication', 'demands', 'of', 'the', 'system', 'this', 'is', 'reflected', 'in', 'the', 'recent', 'trend', 'that', 'many', 'of', 'the', 'standard', 'bus', 'products', 'such', 'as', 'stbus', 'have', 'now', 'introduced', 'the', 'capability', 'of', 'designing', 'a', 'crossbar', 'with', 'multiple', 'buses', 'operating', 'in', 'parallel', 'the', 'crossbar', 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710.4672 | Yield Enhancement of Digital Microfluidics-Based Biochips Using Space
Redundancy and Local Reconfiguration | As microfluidics-based biochips become more complex, manufacturing yield will
have significant influence on production volume and product cost. We propose an
interstitial redundancy approach to enhance the yield of biochips that are
based on droplet-based microfluidics. In this design method, spare cells are
placed in the interstitial sites within the microfluidic array, and they
replace neighboring faulty cells via local reconfiguration. The proposed design
method is evaluated using a set of concurrent real-life bioassays.
| cs.AR | as microfluidicsbased biochips become more complex manufacturing yield will have significant influence on production volume and product cost we propose an interstitial redundancy approach to enhance the yield of biochips that are based on dropletbased microfluidics in this design method spare cells are placed in the interstitial sites within the microfluidic array and they replace neighboring faulty cells via local reconfiguration the proposed design method is evaluated using a set of concurrent reallife bioassays | [['as', 'microfluidicsbased', 'biochips', 'become', 'more', 'complex', 'manufacturing', 'yield', 'will', 'have', 'significant', 'influence', 'on', 'production', 'volume', 'and', 'product', 'cost', 'we', 'propose', 'an', 'interstitial', 'redundancy', 'approach', 'to', 'enhance', 'the', 'yield', 'of', 'biochips', 'that', 'are', 'based', 'on', 'dropletbased', 'microfluidics', 'in', 'this', 'design', 'method', 'spare', 'cells', 'are', 'placed', 'in', 'the', 'interstitial', 'sites', 'within', 'the', 'microfluidic', 'array', 'and', 'they', 'replace', 'neighboring', 'faulty', 'cells', 'via', 'local', 'reconfiguration', 'the', 'proposed', 'design', 'method', 'is', 'evaluated', 'using', 'a', 'set', 'of', 'concurrent', 'reallife', 'bioassays']] | [-0.09290546540177201, 0.10106050223918361, -0.0003585891508673494, -0.03770460093368751, -0.02380299722977184, -0.15332879236194533, 0.05779602669645101, 0.4243408811555521, -0.22063491274476857, -0.28125396726780405, 0.09099612528823216, -0.2631632032980387, -0.18663035241282872, 0.21073095349443927, -0.11513490499488103, 0.022905493230634445, 0.09570300645144605, -0.00999087285930039, 0.03616219736726929, -0.27272812538855784, 0.20371774938492407, 0.07165441672141487, 0.3517912442141489, 0.07444783762047016, 0.08589287345121438, 0.009646249066635564, -0.022197273014761456, 0.05204641294187388, -0.09073746747801763, 0.17621412639945866, 0.273228939416554, 0.1435030530634764, 0.27779330973312055, -0.5392531046039752, -0.17437780671123718, 0.09595838499356162, 0.1363016080136436, 0.07237906638860099, -0.10094143165612901, -0.244292688027427, 0.09832250732752318, -0.18684224582377923, -0.03398318688787923, -0.10061454739283167, -0.033496454578346095, 0.04286532634491655, -0.2595328916040425, 0.011380760615842568, -0.049576372512288996, 0.044241596255577297, -0.0392315799080943, -0.14330063217218864, 0.0031704944338196437, 0.13052504039621232, -0.05288109454213063, -0.00855570555211523, 0.24804885434364346, -0.04169758688973112, -0.11903393087354866, 0.35830533899668904, 0.04066039865358254, -0.2430999890957783, 0.21178911471538045, -0.04227096556585182, -0.11229866966479332, 0.16932932493855823, 0.27999950844693827, 0.0880542050140935, -0.19244510886838306, 0.014020222778797048, 0.014659143090751526, 0.15356150971461288, 0.1086679724693248, 0.0412298470823648, 0.17181390099781188, 0.2936457404615106, 0.08772334245323027, 0.13530611460068817, -0.11553790515943153, -0.08944392081576626, -0.20949116467523413, -0.20018877215507264, -0.1557905970179048, -0.004883304427101, -0.07767842928650852, -0.1952252482768853, 0.2937817257275251, 0.15410415787797271, 0.12756232572467746, -0.009667050732123489, 0.3075296676126183, 0.013922548963180176, 0.1592733008988403, 0.025703426708492474, 0.20555713241668166, 0.05548504502764223, 0.1300043628702091, -0.20264294472321667, 0.10823890092984043, 0.05210009137973995] |
710.4673 | Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic
Biochips | Microfluidics-based biochips are soon expected to revolutionize clinical
diagnosis, DNA sequencing, and other laboratory procedures involving molecular
biology. Most microfluidic biochips are based on the principle of continuous
fluid flow and they rely on permanently-etched microchannels, micropumps, and
microvalves. We focus here on the automated design of "digital" droplet-based
microfluidic biochips. In contrast to continuous-flow systems, digital
microfluidics offers dynamic reconfigurability; groups of cells in a
microfluidics array can be reconfigured to change their functionality during
the concurrent execution of a set of bioassays. We present a simulated
annealing-based technique for module placement in such biochips. The placement
procedure not only addresses chip area, but it also considers fault tolerance,
which allows a microfluidic module to be relocated elsewhere in the system when
a single cell is detected to be faulty. Simulation results are presented for a
case study involving the polymerase chain reaction.
| cs.AR | microfluidicsbased biochips are soon expected to revolutionize clinical diagnosis dna sequencing and other laboratory procedures involving molecular biology most microfluidic biochips are based on the principle of continuous fluid flow and they rely on permanentlyetched microchannels micropumps and microvalves we focus here on the automated design of digital dropletbased microfluidic biochips in contrast to continuousflow systems digital microfluidics offers dynamic reconfigurability groups of cells in a microfluidics array can be reconfigured to change their functionality during the concurrent execution of a set of bioassays we present a simulated annealingbased technique for module placement in such biochips the placement procedure not only addresses chip area but it also considers fault tolerance which allows a microfluidic module to be relocated elsewhere in the system when a single cell is detected to be faulty simulation results are presented for a case study involving the polymerase chain reaction | [['microfluidicsbased', 'biochips', 'are', 'soon', 'expected', 'to', 'revolutionize', 'clinical', 'diagnosis', 'dna', 'sequencing', 'and', 'other', 'laboratory', 'procedures', 'involving', 'molecular', 'biology', 'most', 'microfluidic', 'biochips', 'are', 'based', 'on', 'the', 'principle', 'of', 'continuous', 'fluid', 'flow', 'and', 'they', 'rely', 'on', 'permanentlyetched', 'microchannels', 'micropumps', 'and', 'microvalves', 'we', 'focus', 'here', 'on', 'the', 'automated', 'design', 'of', 'digital', 'dropletbased', 'microfluidic', 'biochips', 'in', 'contrast', 'to', 'continuousflow', 'systems', 'digital', 'microfluidics', 'offers', 'dynamic', 'reconfigurability', 'groups', 'of', 'cells', 'in', 'a', 'microfluidics', 'array', 'can', 'be', 'reconfigured', 'to', 'change', 'their', 'functionality', 'during', 'the', 'concurrent', 'execution', 'of', 'a', 'set', 'of', 'bioassays', 'we', 'present', 'a', 'simulated', 'annealingbased', 'technique', 'for', 'module', 'placement', 'in', 'such', 'biochips', 'the', 'placement', 'procedure', 'not', 'only', 'addresses', 'chip', 'area', 'but', 'it', 'also', 'considers', 'fault', 'tolerance', 'which', 'allows', 'a', 'microfluidic', 'module', 'to', 'be', 'relocated', 'elsewhere', 'in', 'the', 'system', 'when', 'a', 'single', 'cell', 'is', 'detected', 'to', 'be', 'faulty', 'simulation', 'results', 'are', 'presented', 'for', 'a', 'case', 'study', 'involving', 'the', 'polymerase', 'chain', 'reaction']] | [-0.11889559713120139, 0.09266114764532048, -0.03009364962709812, -0.030425579163318003, -0.07273175349642694, -0.18793514438471953, 0.05385599217103371, 0.41430473991368016, -0.26172016197766346, -0.2745932524289664, 0.14334284041476975, -0.21122818293132323, -0.1628959312129923, 0.2938869096351866, -0.12645813766014302, 0.08197827303116406, 0.09661382985943649, -0.016102151540239196, 0.06369409481929221, -0.216565697845793, 0.17687997085527635, 0.06276407063295933, 0.3214590361663206, 0.053130470861477486, 0.10265103739712544, 0.011840497892887764, -0.03164834257798978, 0.023724018960115566, -0.1263085741838309, 0.1140301333884643, 0.3375243060717123, 0.1582827456787386, 0.26933917028068655, -0.49204515129275306, -0.2063452225198156, 0.08766491127423418, 0.1517803057778994, 0.14877453945416458, -0.0716144885420209, -0.24868363498637952, 0.09837037425252124, -0.17336887935124023, -0.07806248816294255, -0.06047287909887915, -0.03343712445599573, 0.06703377735610841, -0.22895464538858915, 0.014635786677925507, -0.016524272486337945, 0.10080054998528999, -0.02877505042329496, -0.07802509370230837, 0.016933610575916375, 0.13791469551076044, -0.06757331084178, 0.0012566702217798233, 0.2858775639939319, -0.08707921898884463, -0.14243520893366404, 0.3810192147453486, 0.04925113999035577, -0.2193962023987002, 0.21851366475178585, -0.06729534102118456, -0.16325822377472488, 0.1323055538502981, 0.23885264361119815, 0.08856060452641211, -0.20434898461928858, 0.015050455805284798, 0.029703116956868694, 0.17906081011440134, 0.08556323309107618, -0.006021208188850695, 0.19896018622495548, 0.2810125154636564, 0.053724549172944586, 0.1346669842576785, -0.09973059315562353, -0.07589877065940118, -0.2188752162808054, -0.21121800321475667, -0.14420704693454778, 0.022843887539302544, -0.011453127007768325, -0.17906585068304195, 0.3280601278537701, 0.12419807831130245, 0.08131327894581876, 0.022610092895518675, 0.3327691610541824, -0.015479690032010131, 0.13755941364920737, -0.006273599456287395, 0.1807883563517055, 0.07006328148623063, 0.18076627013194835, -0.19275063676366083, 0.08727563219636836, 0.019956595382430185] |
710.4674 | Bars in Disk-Dominated and Bulge-Dominated Galaxies at z~0: New Insights
from ~3600 SDSS Galaxies | We present a study of large-scale bars in the local Universe, based on a
large sample of ~3692 galaxies, with -18.5 <= M_g < -22.0 mag and redshift 0.01
<= z < 0.03, drawn from the Sloan Digitized Sky Survey. Our sample includes
many galaxies that are disk-dominated and of late Hubble types. Both color cuts
and S\'ersic cuts yield a similar sample of ~2000 disk galaxies. We
characterize bars and disks by ellipse-fitting r-band images and applying
quantitative criteria. After excluding highly inclined ($>60^{\circ}$) systems,
we find the following results. (1) The optical r-band fraction (f_opt-r) of
barred galaxies, when averaged over the whole sample, is ~48%-52%. (2) When
galaxies are separated according to half light radius (r_e), or normalized
r_e/R_24, which is a measure of the bulge-to-disk (B/D) ratio, a remarkable
result is seen: f_opt-r rises sharply, from ~40% in galaxies that have small
r_e/R_24 and visually appear to host prominent bulges, to ~70% for galaxies
that have large r_e/R_24 and appear disk-dominated. (3) $f_{\rm opt-r}$ rises
for galaxies with bluer colors (by ~30%) and lower masses (by ~15%-20%). (4)
While hierarchical $\Lambda$CDM models of galaxy evolution models fail to
produce galaxies without classical bulges, our study finds that ~20% of disk
galaxies appear to be ``quasi-bulgeless''. (5) After applying the same cutoffs
in magnitude (M_V<-19.3 mag), bar size (a_bar >= 1.5 kpc), and bar ellipticity
(e_bar >=~0.4) that studies out to z~1 apply to ensure a complete sample,
adequate spatial resolution, and reliable bar identification, we obtain an
optical r-band bar fraction of 34%. This is comparable to the value reported at
z~0.2-1.0, implying that the optical bar fraction does not decline dramatically
by an order of magnitude in bright galaxies out to z~1. (abridged)
| astro-ph | we present a study of largescale bars in the local universe based on a large sample of 3692 galaxies with 185 m_g 220 mag and redshift 001 z 003 drawn from the sloan digitized sky survey our sample includes many galaxies that are diskdominated and of late hubble types both color cuts and sersic cuts yield a similar sample of 2000 disk galaxies we characterize bars and disks by ellipsefitting rband images and applying quantitative criteria after excluding highly inclined 60circ systems we find the following results 1 the optical rband fraction f_optr of barred galaxies when averaged over the whole sample is 4852 2 when galaxies are separated according to half light radius r_e or normalized r_er_24 which is a measure of the bulgetodisk bd ratio a remarkable result is seen f_optr rises sharply from 40 in galaxies that have small r_er_24 and visually appear to host prominent bulges to 70 for galaxies that have large r_er_24 and appear diskdominated 3 f_rm optr rises for galaxies with bluer colors by 30 and lower masses by 1520 4 while hierarchical lambdacdm models of galaxy evolution models fail to produce galaxies without classical bulges our study finds that 20 of disk galaxies appear to be quasibulgeless 5 after applying the same cutoffs in magnitude m_v193 mag bar size a_bar 15 kpc and bar ellipticity e_bar 04 that studies out to z1 apply to ensure a complete sample adequate spatial resolution and reliable bar identification we obtain an optical rband bar fraction of 34 this is comparable to the value reported at z0210 implying that the optical bar fraction does not decline dramatically by an order of magnitude in bright galaxies out to z1 abridged | [['we', 'present', 'a', 'study', 'of', 'largescale', 'bars', 'in', 'the', 'local', 'universe', 'based', 'on', 'a', 'large', 'sample', 'of', '3692', 'galaxies', 'with', '185', 'm_g', '220', 'mag', 'and', 'redshift', '001', 'z', '003', 'drawn', 'from', 'the', 'sloan', 'digitized', 'sky', 'survey', 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710.4675 | A Conversation with Shoutir Kishore Chatterjee | Shoutir Kishore Chatterjee was born in Ranchi, a small hill station in India,
on November 6, 1934. He received his B.Sc. in statistics from the Presidency
College, Calcutta, in 1954, and M.Sc. and Ph.D. degrees in statistics from the
University of Calcutta in 1956 and 1962, respectively. He was appointed a
lecturer in the Department of Statistics, University of Calcutta, in 1960 and
was a member of its faculty until his retirement as a professor in 1997.
Indeed, from the 1970s he steered the teaching and research activities of the
department for the next three decades. Professor Chatterjee was the National
Lecturer in Statistics (1985--1986) of the University Grants Commission, India,
the President of the Section of Statistics of the Indian Science Congress
(1989) and an Emeritus Scientist (1997--2000) of the Council of Scientific and
Industrial Research, India. Professor Chatterjee, affectionately known as SKC
to his students and admirers, is a truly exceptional person who embodies the
spirit of eternal India. He firmly believes that ``fulfillment in man's life
does not come from amassing a lot of money, after the threshold of what is
required for achieving a decent living is crossed. It does not come even from
peer recognition for intellectual achievements. Of course, one has to work and
toil a lot before one realizes these facts.''
| stat.ME | shoutir kishore chatterjee was born in ranchi a small hill station in india on november 6 1934 he received his bsc in statistics from the presidency college calcutta in 1954 and msc and phd degrees in statistics from the university of calcutta in 1956 and 1962 respectively he was appointed a lecturer in the department of statistics university of calcutta in 1960 and was a member of its faculty until his retirement as a professor in 1997 indeed from the 1970s he steered the teaching and research activities of the department for the next three decades professor chatterjee was the national lecturer in statistics 19851986 of the university grants commission india the president of the section of statistics of the indian science congress 1989 and an emeritus scientist 19972000 of the council of scientific and industrial research india professor chatterjee affectionately known as skc to his students and admirers is a truly exceptional person who embodies the spirit of eternal india he firmly believes that fulfillment in mans life does not come from amassing a lot of money after the threshold of what is required for achieving a decent living is crossed it does not come even from peer recognition for intellectual achievements of course one has to work and toil a lot before one realizes these facts | [['shoutir', 'kishore', 'chatterjee', 'was', 'born', 'in', 'ranchi', 'a', 'small', 'hill', 'station', 'in', 'india', 'on', 'november', '6', '1934', 'he', 'received', 'his', 'bsc', 'in', 'statistics', 'from', 'the', 'presidency', 'college', 'calcutta', 'in', '1954', 'and', 'msc', 'and', 'phd', 'degrees', 'in', 'statistics', 'from', 'the', 'university', 'of', 'calcutta', 'in', '1956', 'and', '1962', 'respectively', 'he', 'was', 'appointed', 'a', 'lecturer', 'in', 'the', 'department', 'of', 'statistics', 'university', 'of', 'calcutta', 'in', '1960', 'and', 'was', 'a', 'member', 'of', 'its', 'faculty', 'until', 'his', 'retirement', 'as', 'a', 'professor', 'in', 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710.4676 | Many-body calculations of relativistic energy shifts for single- and
double-valence atoms | Relativistic Hartree-Fock method together with many-body perturbation theory
and configuration interaction techniques are used to calculate relativistic
energy shifts for frequencies of the strong electric dipole transitions of C
III, C IV, Na I, Mg I, Mg II, Al II, Al III, Si IV, Ca II and Zn II. These
transitions are used for search of the variation of the fine structure constant
in quasar absorption spectra. The results are in good agreement with previous
calculations. The analysis of Breit contributions is also presented.
| physics.atom-ph | relativistic hartreefock method together with manybody perturbation theory and configuration interaction techniques are used to calculate relativistic energy shifts for frequencies of the strong electric dipole transitions of c iii c iv na i mg i mg ii al ii al iii si iv ca ii and zn ii these transitions are used for search of the variation of the fine structure constant in quasar absorption spectra the results are in good agreement with previous calculations the analysis of breit contributions is also presented | [['relativistic', 'hartreefock', 'method', 'together', 'with', 'manybody', 'perturbation', 'theory', 'and', 'configuration', 'interaction', 'techniques', 'are', 'used', 'to', 'calculate', 'relativistic', 'energy', 'shifts', 'for', 'frequencies', 'of', 'the', 'strong', 'electric', 'dipole', 'transitions', 'of', 'c', 'iii', 'c', 'iv', 'na', 'i', 'mg', 'i', 'mg', 'ii', 'al', 'ii', 'al', 'iii', 'si', 'iv', 'ca', 'ii', 'and', 'zn', 'ii', 'these', 'transitions', 'are', 'used', 'for', 'search', 'of', 'the', 'variation', 'of', 'the', 'fine', 'structure', 'constant', 'in', 'quasar', 'absorption', 'spectra', 'the', 'results', 'are', 'in', 'good', 'agreement', 'with', 'previous', 'calculations', 'the', 'analysis', 'of', 'breit', 'contributions', 'is', 'also', 'presented']] | [-0.04974923420342661, 0.08283039940787214, 0.05719749814098967, 0.06768356350810445, -0.007120904124652346, -0.22402159846457098, 0.030086964508795756, 0.44444989617026986, -0.17136716363131113, -0.32614622197468723, -0.05688439206763481, -0.31575112137943506, -0.06612411135851982, 0.09498672361951321, 0.05210998539058935, -0.03980899155361667, 0.028110193235555754, -0.05829294587463318, -0.09182322557483401, -0.1763427828652008, 0.29911224123290076, 0.09281843000402053, 0.24540812333690978, 0.03804067246216748, -0.07701115424389995, -0.03339710609621501, -0.06382957823751938, 0.12479219352826476, -0.1345221215326871, 0.1308506439728219, 0.23071589654136915, 0.12433066596055314, 0.1862540334280181, -0.3898459534781675, -0.16821538695755103, -0.020470172466178025, 0.10092761491735776, 0.18547747869576728, -0.061759690618297704, -0.29752005796347347, 0.031781596408802126, -0.1250397252872409, -0.13495971904402332, -0.06430174341602694, 0.09686103177123837, 0.10822120390921122, -0.297674921239377, 0.0636562327268794, 0.03437987019285737, 0.08962290164371163, -0.09682914961151601, -0.17528879764999838, -0.056925539617493214, 0.04134454440680288, -0.027177667475327672, -0.009084507107867726, 0.12256918614730239, -0.044731780365552934, -0.10038243054545351, 0.42690275445403086, -0.15577484166160935, -0.039447847371255715, 0.16882146822865166, -0.14051090847213, -0.1456562392427475, 0.20664277616223053, 0.12374954363552942, 0.11716608984646709, -0.07891690334197067, 0.1618504183619128, 0.07008416697915111, 0.1590797054315252, -0.003100823649826149, 0.04046767590755605, 0.12983686311746992, 0.03447545571197268, -0.044419484334953484, -0.03473705010921029, -0.1717181444234614, -0.05835534693878366, -0.35445166545520934, -0.15405212292846823, -0.1276854410701032, 0.007346363401406312, -0.07294380685302063, -0.16516707350854717, 0.353921560498531, 0.07207523491455331, 0.1840919649694115, -0.048886387542422326, 0.22244641869994147, 0.13276874183100604, 0.004260446743241378, 0.07520512252536025, 0.32080063165769734, 0.2094734151115907, 0.16196052990077683, -0.32473015522867044, 0.03487885120834801, 0.08689984905954805] |
710.4677 | Congruences between modular forms and related modules | We fix $\ell$ a prime and let $M$ be an integer such that $\ell\not|M$; let
$f\in S_2(\Gamma_1(M\ell^2))$ be a newform supercuspidal of fixed type related
to the nebentypus, at $\ell$ and special at a finite set of primes. Let
$\TT^\psi$ be the local quaternionic Hecke algebra associated to $f$. The
algebra $\TT^\psi$ acts on a module $\mathcal M^\psi_f$ coming from the
cohomology of a Shimura curve. Applying the Taylor-Wiles criterion and a recent
Savitt's theorem, $\TT^\psi$ is the universal deformation ring of a global
Galois deformation problem associated to $\orho_f$. Moreover $\mathcal
M^\psi_f$ is free of rank 2 over $\TT^\psi$. If $f$ occurs at minimal level, by
a generalization of a Conrad, Diamond and Taylor's result and by the classical
Ihara's lemma, we prove a theorem of raising the level and a result about
congruence ideals. The extension of this results to the non minimal case is an
open problem.
| math.NT | we fix ell a prime and let m be an integer such that ellnotm let fin s_2gamma_1mell2 be a newform supercuspidal of fixed type related to the nebentypus at ell and special at a finite set of primes let ttpsi be the local quaternionic hecke algebra associated to f the algebra ttpsi acts on a module mathcal mpsi_f coming from the cohomology of a shimura curve applying the taylorwiles criterion and a recent savitts theorem ttpsi is the universal deformation ring of a global galois deformation problem associated to orho_f moreover mathcal mpsi_f is free of rank 2 over ttpsi if f occurs at minimal level by a generalization of a conrad diamond and taylors result and by the classical iharas lemma we prove a theorem of raising the level and a result about congruence ideals the extension of this results to the non minimal case is an open problem | [['we', 'fix', 'ell', 'a', 'prime', 'and', 'let', 'm', 'be', 'an', 'integer', 'such', 'that', 'ellnotm', 'let', 'fin', 's_2gamma_1mell2', 'be', 'a', 'newform', 'supercuspidal', 'of', 'fixed', 'type', 'related', 'to', 'the', 'nebentypus', 'at', 'ell', 'and', 'special', 'at', 'a', 'finite', 'set', 'of', 'primes', 'let', 'ttpsi', 'be', 'the', 'local', 'quaternionic', 'hecke', 'algebra', 'associated', 'to', 'f', 'the', 'algebra', 'ttpsi', 'acts', 'on', 'a', 'module', 'mathcal', 'mpsi_f', 'coming', 'from', 'the', 'cohomology', 'of', 'a', 'shimura', 'curve', 'applying', 'the', 'taylorwiles', 'criterion', 'and', 'a', 'recent', 'savitts', 'theorem', 'ttpsi', 'is', 'the', 'universal', 'deformation', 'ring', 'of', 'a', 'global', 'galois', 'deformation', 'problem', 'associated', 'to', 'orho_f', 'moreover', 'mathcal', 'mpsi_f', 'is', 'free', 'of', 'rank', '2', 'over', 'ttpsi', 'if', 'f', 'occurs', 'at', 'minimal', 'level', 'by', 'a', 'generalization', 'of', 'a', 'conrad', 'diamond', 'and', 'taylors', 'result', 'and', 'by', 'the', 'classical', 'iharas', 'lemma', 'we', 'prove', 'a', 'theorem', 'of', 'raising', 'the', 'level', 'and', 'a', 'result', 'about', 'congruence', 'ideals', 'the', 'extension', 'of', 'this', 'results', 'to', 'the', 'non', 'minimal', 'case', 'is', 'an', 'open', 'problem']] | [-0.19734992844233704, 0.06694519528193471, -0.12700648290208644, 0.032865908457703576, -0.09886282113115562, -0.1706378545463344, 0.01924769205571566, 0.2359609501112977, -0.387454494031974, -0.2014860354635554, 0.10025208024388929, -0.2557399924650478, -0.10826494978553253, 0.22746254748037448, -0.15386843076137463, -0.03202926074138506, 0.044043390106202826, 0.14523825269295937, -0.07500667132262606, -0.2640910801969262, 0.3702054330238348, 0.0037212535894973874, 0.18114989776707566, 0.0642856272105645, 0.09902181522915675, 0.03892701481365495, 0.03901506906388224, -0.04174328710036611, -0.15139077135755644, 0.12151091148714638, 0.3142844136325746, 0.07027481501993155, 0.2801219130827424, -0.3505177451491666, -0.1027815872835668, 0.2524450990539562, 0.1068299159524031, -0.01553080329257581, 0.016981297618056286, -0.23722069385015251, 0.1804164755352152, -0.17735922489535166, -0.19890508775845067, -0.03283599162952871, 0.06704937134135333, -0.037254418537486345, -0.3259222893716974, 0.01779248286927921, 0.1426833377077451, 0.1796880723370325, -0.06282035354201475, -0.10001788545115334, -0.047321795044505656, 0.01465153776613685, -0.03490070652818152, 0.11458384422399427, 0.10017684448070617, -0.09206505662910382, -0.11820044649842505, 0.349448104802933, -0.06152122147452448, -0.1968647660445034, 0.09745745192695823, -0.16828445358098382, -0.1543602771352097, 0.09198839809283123, 0.07256550068753616, 0.1259789869236556, 0.00921374049762057, 0.22649837186084673, -0.15201196956008467, 0.09263228080089903, 0.12408921028125203, -0.05237817631374734, 0.1537883259718203, 0.060283217378633305, 0.0895027983765936, 0.12712276580067636, 0.009580666188412579, 0.05451877211453393, -0.38634223161756787, -0.1782242732264826, -0.14031638543625982, 0.17746150376074687, -0.09763618357444809, -0.14289755122606745, 0.40652129958228517, 0.047997834260766266, 0.17516623475886364, 0.12800222465496822, 0.18719150059850007, 0.11791406681095395, 0.08520967846400002, 0.06074165031895973, 0.05187732195999059, 0.2339630312506213, -0.05571562544355402, -0.15504008221452953, -0.03406725162171319, 0.20534133479102618] |
710.4678 | CMOS-Based Biosensor Arrays | CMOS-based sensor array chips provide new and attractive features as compared
to today's standard tools for medical, diagnostic, and biotechnical
applications. Examples for molecule- and cell-based approaches and related
circuit design issues are discussed.
| cs.AR | cmosbased sensor array chips provide new and attractive features as compared to todays standard tools for medical diagnostic and biotechnical applications examples for molecule and cellbased approaches and related circuit design issues are discussed | [['cmosbased', 'sensor', 'array', 'chips', 'provide', 'new', 'and', 'attractive', 'features', 'as', 'compared', 'to', 'todays', 'standard', 'tools', 'for', 'medical', 'diagnostic', 'and', 'biotechnical', 'applications', 'examples', 'for', 'molecule', 'and', 'cellbased', 'approaches', 'and', 'related', 'circuit', 'design', 'issues', 'are', 'discussed']] | [0.006738024380277185, -0.016814699067788964, 0.06839311859734795, 0.09506384584614459, -0.05874330569606494, -0.3327530429643743, -0.025276577428859824, 0.4142460542566636, -0.22370084216270378, -0.32705178385710015, 0.19136395891580513, -0.3327912366949022, -0.19790962864370906, 0.3620361757519491, -0.1037744084811386, 0.1440658677533707, 0.09305703100364875, -0.0600896205758224, 0.028551051598590088, -0.18665470537619994, 0.1970171809525174, 0.07620148084071629, 0.3417923066436368, 0.0907888055422946, 0.0904566423748346, -0.0780315525994143, -0.04344893803285873, 0.0073385564747321256, -0.11973699515082818, 0.17162923635367086, 0.38638093815568614, 0.17635588323259177, 0.24322254114839084, -0.5189687045374953, -0.20589992598466136, 0.03201929370270056, 0.15477729242240243, 0.06940338105949409, -0.12736161580430824, -0.27368205150260644, 0.06684772862011895, -0.16855209298870144, -0.11985770119901966, -0.1737404839026139, 0.017084539813153884, 0.10025421705316095, -0.27114404325702174, -0.05284559854087146, -0.041414452826275545, 0.08594341940410874, 0.011730560005697258, -0.2320985829402857, 0.1283648562453249, 0.1256632314008825, -0.052622824195115006, -0.0016335960724117124, 0.2455901404404465, -0.17551750571960034, -0.19763502664864063, 0.38175890561850634, 0.0561558445367743, -0.16801990572746625, 0.2648559920489788, 0.09345544522682972, -0.13114179757094996, 0.014001091503921677, 0.17426215271081993, 0.020780588774120107, -0.1909929466817309, 0.026261980063281953, 0.15310114890556126, 0.1481324588496457, 0.04234550877556424, 0.13126844392322443, 0.20751073693527894, 0.2474497096503482, 0.029851302915417096, 0.15638901337104685, -0.08240756384261391, -0.08133740651914302, -0.24698927869801135, -0.18757180099868598, -0.12784560469855719, -0.055649833719465226, -0.054718711274771896, -0.17965940205270753, 0.36641518059460554, 0.19767303123851032, 0.07174512097502456, -0.029721827301032403, 0.38183408120975776, 0.012489346756517668, 0.1379709086031653, -0.023389492813936052, 0.14126352963092573, 0.12619115565629566, 0.1606527654803358, -0.11574777222909581, 0.02681945436223246, -0.027217879610629204] |
710.4679 | DVS for On-Chip Bus Designs Based on Timing Error Correction | On-chip buses are typically designed to meet performance constraints at
worst-case conditions, including process corner, temperature, IR-drop, and
neighboring net switching pattern. This can result in significant performance
slack at more typical operating conditions. In this paper, we propose a dynamic
voltage scaling (DVS) technique for buses, based on a double sampling latch
which can detect and correct for delay errors without the need for
retransmission. The proposed approach recovers the available slack at
non-worst-case operating points through more aggressive voltage scaling and
tracks changing conditions by monitoring the error recovery rate. Voltage
margins needed in traditional designs to accommodate worst-case performance
conditions are therefore eliminated, resulting in a significant improvement in
energy efficiency. The approach was implemented for a 6mm memory read bus
operating at 1.5GHz (0.13 $\mu$m technology node) and was simulated for a
number of benchmark programs. Even at the worst-case process and environment
conditions, energy gains of up to 17% are achieved, with error recovery rates
under 2.3%. At more typical process and environment conditions, energy gains
range from 35% to 45%, with a performance degradation under 2%. An analysis of
optimum interconnect architectures for maximizing energy gains with this
approach shows that the proposed approach performs well with technology
scaling.
| cs.AR | onchip buses are typically designed to meet performance constraints at worstcase conditions including process corner temperature irdrop and neighboring net switching pattern this can result in significant performance slack at more typical operating conditions in this paper we propose a dynamic voltage scaling dvs technique for buses based on a double sampling latch which can detect and correct for delay errors without the need for retransmission the proposed approach recovers the available slack at nonworstcase operating points through more aggressive voltage scaling and tracks changing conditions by monitoring the error recovery rate voltage margins needed in traditional designs to accommodate worstcase performance conditions are therefore eliminated resulting in a significant improvement in energy efficiency the approach was implemented for a 6mm memory read bus operating at 15ghz 013 mum technology node and was simulated for a number of benchmark programs even at the worstcase process and environment conditions energy gains of up to 17 are achieved with error recovery rates under 23 at more typical process and environment conditions energy gains range from 35 to 45 with a performance degradation under 2 an analysis of optimum interconnect architectures for maximizing energy gains with this approach shows that the proposed approach performs well with technology scaling | [['onchip', 'buses', 'are', 'typically', 'designed', 'to', 'meet', 'performance', 'constraints', 'at', 'worstcase', 'conditions', 'including', 'process', 'corner', 'temperature', 'irdrop', 'and', 'neighboring', 'net', 'switching', 'pattern', 'this', 'can', 'result', 'in', 'significant', 'performance', 'slack', 'at', 'more', 'typical', 'operating', 'conditions', 'in', 'this', 'paper', 'we', 'propose', 'a', 'dynamic', 'voltage', 'scaling', 'dvs', 'technique', 'for', 'buses', 'based', 'on', 'a', 'double', 'sampling', 'latch', 'which', 'can', 'detect', 'and', 'correct', 'for', 'delay', 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710.468 | Energy Bounds for Fault-Tolerant Nanoscale Designs | The problem of determining lower bounds for the energy cost of a given
nanoscale design is addressed via a complexity theory-based approach. This
paper provides a theoretical framework that is able to assess the trade-offs
existing in nanoscale designs between the amount of redundancy needed for a
given level of resilience to errors and the associated energy cost. Circuit
size, logic depth and error resilience are analyzed and brought together in a
theoretical framework that can be seamlessly integrated with automated
synthesis tools and can guide the design process of nanoscale systems comprised
of failure prone devices. The impact of redundancy addition on the switching
energy and its relationship with leakage energy is modeled in detail. Results
show that 99% error resilience is possible for fault-tolerant designs, but at
the expense of at least 40% more energy if individual gates fail independently
with probability of 1%.
| cs.CC cs.IT math.IT | the problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theorybased approach this paper provides a theoretical framework that is able to assess the tradeoffs existing in nanoscale designs between the amount of redundancy needed for a given level of resilience to errors and the associated energy cost circuit size logic depth and error resilience are analyzed and brought together in a theoretical framework that can be seamlessly integrated with automated synthesis tools and can guide the design process of nanoscale systems comprised of failure prone devices the impact of redundancy addition on the switching energy and its relationship with leakage energy is modeled in detail results show that 99 error resilience is possible for faulttolerant designs but at the expense of at least 40 more energy if individual gates fail independently with probability of 1 | [['the', 'problem', 'of', 'determining', 'lower', 'bounds', 'for', 'the', 'energy', 'cost', 'of', 'a', 'given', 'nanoscale', 'design', 'is', 'addressed', 'via', 'a', 'complexity', 'theorybased', 'approach', 'this', 'paper', 'provides', 'a', 'theoretical', 'framework', 'that', 'is', 'able', 'to', 'assess', 'the', 'tradeoffs', 'existing', 'in', 'nanoscale', 'designs', 'between', 'the', 'amount', 'of', 'redundancy', 'needed', 'for', 'a', 'given', 'level', 'of', 'resilience', 'to', 'errors', 'and', 'the', 'associated', 'energy', 'cost', 'circuit', 'size', 'logic', 'depth', 'and', 'error', 'resilience', 'are', 'analyzed', 'and', 'brought', 'together', 'in', 'a', 'theoretical', 'framework', 'that', 'can', 'be', 'seamlessly', 'integrated', 'with', 'automated', 'synthesis', 'tools', 'and', 'can', 'guide', 'the', 'design', 'process', 'of', 'nanoscale', 'systems', 'comprised', 'of', 'failure', 'prone', 'devices', 'the', 'impact', 'of', 'redundancy', 'addition', 'on', 'the', 'switching', 'energy', 'and', 'its', 'relationship', 'with', 'leakage', 'energy', 'is', 'modeled', 'in', 'detail', 'results', 'show', 'that', '99', 'error', 'resilience', 'is', 'possible', 'for', 'faulttolerant', 'designs', 'but', 'at', 'the', 'expense', 'of', 'at', 'least', '40', 'more', 'energy', 'if', 'individual', 'gates', 'fail', 'independently', 'with', 'probability', 'of', '1']] | [-0.12716639797244705, 0.07167212387757402, -0.04014183965205432, 0.0619732631440419, -0.021139951199548295, -0.16030372773402382, 0.10935282984777188, 0.37778204478872046, -0.2553629534548684, -0.3659337647960917, 0.09593971774112815, -0.24550836458036754, -0.1436124603161971, 0.21288839775163118, -0.12628455587012105, 0.11160211927338809, 0.0598341664189482, 0.011530503471165078, -0.038796736764297374, -0.24868671785344765, 0.2529857570675444, 0.1341636781584733, 0.3106471743731287, 0.08623055259662055, 0.08140354429703359, -0.03446741867969961, 0.0006208172935533197, 0.051043973802684564, -0.11417162180825396, 0.18600414594083592, 0.3028301595365756, 0.15358789815975685, 0.3270374105012121, -0.4685207186521937, -0.18701919893357802, 0.07839787258161192, 0.10046105901710689, 0.09175577302214574, -0.055075304880630616, -0.2195746085195075, 0.1223542995141717, -0.1613816167483081, -0.10567258510007826, -0.05817311114597406, -0.00983975563606579, 0.024789613410065026, -0.2632800914883001, 0.028151982093918813, 0.05420512889275863, 0.043207277518327106, -0.021031030656371987, -0.1099954191435843, -0.021243851520248675, 0.13203676559719935, -0.03574837193595507, 0.01347741331248895, 0.14821354787133328, -0.10357292038898865, -0.14797468394781016, 0.35430489956363015, 0.017632684357821532, -0.2078683979503096, 0.16146982480669778, -0.058935205050272076, -0.10048692407443711, 0.15127452307584863, 0.20277550345133633, 0.022338048452894166, -0.16413619235390797, 0.0648347123391282, 0.09471721805581083, 0.2288582706568788, 0.03628536550430198, 0.10760907021555284, 0.1827276831122804, 0.2422454007837462, 0.09109860259006182, 0.14836274687605847, -0.09006506976335028, -0.06373348674610933, -0.2963845411982158, -0.14202268969559442, -0.16878425992374652, 0.010132988304065617, -0.08189689194931479, -0.10447544534291996, 0.3941328493265869, 0.19176924736430384, 0.1587138729718552, 0.10630089785642156, 0.35151976423197717, 0.10896049593320142, 0.058671363546474745, 0.09464211368053028, 0.22010487852911528, 0.10138433270972885, 0.05686075806821862, -0.22217365117880758, 0.12244386883924575, -0.016055378959233528] |
710.4681 | A Quality-of-Service Mechanism for Interconnection Networks in
System-on-Chips | As Moore's Law continues to fuel the ability to build ever increasingly
complex system-on-chips (SoCs), achieving performance goals is rising as a
critical challenge to completing designs. In particular, the system
interconnect must efficiently service a diverse set of data flows with widely
ranging quality-of-service (QoS) requirements. However, the known solutions for
off-chip interconnects such as large-scale networks are not necessarily
applicable to the on-chip environment. Latency and memory constraints for
on-chip interconnects are quite different from larger-scale interconnects. This
paper introduces a novel on-chip interconnect arbitration scheme. We show how
this scheme can be distributed across a chip for high-speed implementation. We
compare the performance of the arbitration scheme with other known interconnect
arbitration schemes. Existing schemes typically focus heavily on either low
latency of service for some initiators, or alternatively on guaranteed
bandwidth delivery for other initiators. Our scheme allows service latency on
some initiators to be traded off smoothly against jitter bounds on other
initiators, while still delivering bandwidth guarantees. This scheme is a
subset of the QoS controls that are available in the SonicsMX? (SMX) product.
| cs.AR | as moores law continues to fuel the ability to build ever increasingly complex systemonchips socs achieving performance goals is rising as a critical challenge to completing designs in particular the system interconnect must efficiently service a diverse set of data flows with widely ranging qualityofservice qos requirements however the known solutions for offchip interconnects such as largescale networks are not necessarily applicable to the onchip environment latency and memory constraints for onchip interconnects are quite different from largerscale interconnects this paper introduces a novel onchip interconnect arbitration scheme we show how this scheme can be distributed across a chip for highspeed implementation we compare the performance of the arbitration scheme with other known interconnect arbitration schemes existing schemes typically focus heavily on either low latency of service for some initiators or alternatively on guaranteed bandwidth delivery for other initiators our scheme allows service latency on some initiators to be traded off smoothly against jitter bounds on other initiators while still delivering bandwidth guarantees this scheme is a subset of the qos controls that are available in the sonicsmx smx product | [['as', 'moores', 'law', 'continues', 'to', 'fuel', 'the', 'ability', 'to', 'build', 'ever', 'increasingly', 'complex', 'systemonchips', 'socs', 'achieving', 'performance', 'goals', 'is', 'rising', 'as', 'a', 'critical', 'challenge', 'to', 'completing', 'designs', 'in', 'particular', 'the', 'system', 'interconnect', 'must', 'efficiently', 'service', 'a', 'diverse', 'set', 'of', 'data', 'flows', 'with', 'widely', 'ranging', 'qualityofservice', 'qos', 'requirements', 'however', 'the', 'known', 'solutions', 'for', 'offchip', 'interconnects', 'such', 'as', 'largescale', 'networks', 'are', 'not', 'necessarily', 'applicable', 'to', 'the', 'onchip', 'environment', 'latency', 'and', 'memory', 'constraints', 'for', 'onchip', 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710.4682 | Applying UML and MDA to Real Systems Design | Traditionally system design has been made from a black box/functionality only
perspective which forces the developer to concentrate on how the functionality
can be decomposed and recomposed into so called components. While this
technique is well established and well known it does suffer fromsome drawbacks;
namely that the systems produced can often be forced into certain, incompatible
architectures, difficult to maintain or reuse and the code itself difficult to
debug. Now that ideas such as the OMG's Model Based Architecture (MDA) or Model
Based Engineering (MBE) and the ubiquitous modelling language UML are being
used (allegedly) and desired we face a number of challenges to existing
techniques.
| cs.SE | traditionally system design has been made from a black boxfunctionality only perspective which forces the developer to concentrate on how the functionality can be decomposed and recomposed into so called components while this technique is well established and well known it does suffer fromsome drawbacks namely that the systems produced can often be forced into certain incompatible architectures difficult to maintain or reuse and the code itself difficult to debug now that ideas such as the omgs model based architecture mda or model based engineering mbe and the ubiquitous modelling language uml are being used allegedly and desired we face a number of challenges to existing techniques | [['traditionally', 'system', 'design', 'has', 'been', 'made', 'from', 'a', 'black', 'boxfunctionality', 'only', 'perspective', 'which', 'forces', 'the', 'developer', 'to', 'concentrate', 'on', 'how', 'the', 'functionality', 'can', 'be', 'decomposed', 'and', 'recomposed', 'into', 'so', 'called', 'components', 'while', 'this', 'technique', 'is', 'well', 'established', 'and', 'well', 'known', 'it', 'does', 'suffer', 'fromsome', 'drawbacks', 'namely', 'that', 'the', 'systems', 'produced', 'can', 'often', 'be', 'forced', 'into', 'certain', 'incompatible', 'architectures', 'difficult', 'to', 'maintain', 'or', 'reuse', 'and', 'the', 'code', 'itself', 'difficult', 'to', 'debug', 'now', 'that', 'ideas', 'such', 'as', 'the', 'omgs', 'model', 'based', 'architecture', 'mda', 'or', 'model', 'based', 'engineering', 'mbe', 'and', 'the', 'ubiquitous', 'modelling', 'language', 'uml', 'are', 'being', 'used', 'allegedly', 'and', 'desired', 'we', 'face', 'a', 'number', 'of', 'challenges', 'to', 'existing', 'techniques']] | [-0.051372233815934684, 0.053979025745675674, -0.09113519882694596, 0.08473636177146719, -0.15020902881487494, -0.22494493531772777, 0.013156445376946414, 0.3894668833308277, -0.3172474806862218, -0.3418319676780984, 0.15134107092439775, -0.2262470314877906, -0.18084295894950628, 0.2080732272760499, -0.0985962634861824, 0.09429767400558506, 0.05536792754594769, -0.007606731231013934, -0.024829334120399185, -0.2201441217657356, 0.2842483462322326, 0.06349902606480533, 0.3102068633018505, 0.04250843070358747, 0.09989801943087341, -0.03919565319707285, -0.005074854869772458, 0.04675929217288891, -0.053241116554237945, 0.12250415426457212, 0.281410494939025, 0.2342078823973203, 0.27723504562440904, -0.4770580893238297, -0.21594865444515432, 0.07894473386861917, 0.1863484292867638, 0.09994897075285691, -0.013024823315485956, -0.27019930936928305, 0.08756107624531502, -0.20699131194768208, -0.08260159121737594, -0.10604194898513102, -0.04758881094111573, 0.013608128993794145, -0.2291762282262512, -0.03244628317299343, 0.10306428646103345, 0.01675751266191669, 0.008626368063934414, -0.12853502284713267, -0.03844613199055727, 0.17410993774731953, 0.05420385177380272, 0.044179804772803824, 0.159390860006568, -0.0998244761954993, -0.11423934681252354, 0.4262314308700817, 0.012993235189822459, -0.2230100803077221, 0.26295607072035115, -0.02481641031446911, -0.14906710699378026, 0.08224783866621908, 0.18191834920573802, 0.07314944620288553, -0.1856506808705273, 0.04963586198199274, 0.04815374525884787, 0.23417354760625, 0.03739341504295312, 0.024354396033145133, 0.24704491287203773, 0.17175969873954142, -0.0013752488980008778, 0.11557992337149613, -0.013810550175341113, -0.08180292629237686, -0.18679698546904894, -0.11632388500230653, -0.16496148505469874, 0.014460736842426871, 0.042824179672641634, -0.18820424869301774, 0.3451751922789429, 0.18860624681803442, 0.1583284020157797, 0.005306368260200889, 0.38443460436981347, 0.07863534690390918, 0.18134247395126815, 0.075145650424418, 0.21605987904393778, 0.04729771994143015, 0.10537419686138275, -0.12292581194058239, 0.12045397303466286, 0.023720882025857766] |
710.4683 | The Challenges of Hardware Synthesis from C-Like Languages | MANY TECHNIQUES for synthesizing digital hardware from C-like languages have
been proposed, but none have emerged as successful as Verilog or VHDL for
register-transfer-level design. This paper looks at two of the fundamental
challenges: concurrency and timing control.
| cs.PL | many techniques for synthesizing digital hardware from clike languages have been proposed but none have emerged as successful as verilog or vhdl for registertransferlevel design this paper looks at two of the fundamental challenges concurrency and timing control | [['many', 'techniques', 'for', 'synthesizing', 'digital', 'hardware', 'from', 'clike', 'languages', 'have', 'been', 'proposed', 'but', 'none', 'have', 'emerged', 'as', 'successful', 'as', 'verilog', 'or', 'vhdl', 'for', 'registertransferlevel', 'design', 'this', 'paper', 'looks', 'at', 'two', 'of', 'the', 'fundamental', 'challenges', 'concurrency', 'and', 'timing', 'control']] | [-0.08176759039555248, -0.01857522876643752, -0.05208471410505071, 0.04729428996860578, -0.11949208794111335, -0.26658068682897734, -0.016141587814844743, 0.42320288939250483, -0.25789029423046755, -0.3957294193096459, 0.17532769119920763, -0.21758183828127142, -0.16748736947900741, 0.31583660548376674, -0.13274933844553055, 0.17187610882762316, 0.011678708025027771, -0.025964478694584466, -0.04937821221412034, -0.2285952491283014, 0.2232322774991091, 0.007651945972513105, 0.3033749009356708, 0.006960810627788305, 0.12538412130261595, -0.03552474996477768, 0.0056334470927312565, -0.00947031650591541, -0.007800749037414789, 0.11974413934591654, 0.39206542890216856, 0.27027902074435073, 0.33693656665147154, -0.47597389688362945, -0.2224380074673005, 0.04665596610740633, 0.16641213032542854, 0.12718646934356642, -0.15699613771426515, -0.21651603596133961, 0.15027444639771775, -0.24887176019114418, -0.039387805639086546, -0.11334696948226239, 0.031146261668008927, 0.0197451305953232, -0.14997605727733793, -0.13383250952874487, 0.06520759563490346, 0.1457129411298681, 0.04508767948435569, -0.1968940622299104, 0.030387097050914087, 0.18924441432102104, 0.01226884061218919, 0.01646509229180378, 0.10709158003934331, -0.08552178981512584, -0.2513150054256658, 0.39824350077558207, 0.05744579975568765, -0.13049288360855063, 0.2652126525503558, 0.008863851478373682, -0.27730186846157584, 0.07871047943528439, 0.17419491813996354, 0.021605330267669382, -0.23700906620738474, 0.10704426230655077, 0.03996571858186979, 0.21701141728742704, 0.149889794876799, 0.10327852860948927, 0.2738782844027957, 0.26748911880359455, 0.022183364519937517, 0.09937844776573616, -0.04890910374957162, -0.06544809944524958, -0.1979670916256067, -0.1374110749897522, -0.10880915641885351, -0.04149740911718156, 0.03744924510239208, -0.17727174068725593, 0.38212117482278796, 0.16116214139588378, 0.05051368746805836, 0.08116157190572168, 0.42786195753393946, 0.04433200069753503, 0.13885940772456093, 0.07855993388472376, 0.19786324342272268, 0.0008767193082619358, 0.2044073563270472, -0.12761954729432692, 0.1455909627414233, 0.013042519020067679] |
710.4684 | Reliability-Centric High-Level Synthesis | Importance of addressing soft errors in both safety critical applications and
commercial consumer products is increasing, mainly due to ever shrinking
geometries, higher-density circuits, and employment of power-saving techniques
such as voltage scaling and component shut-down. As a result, it is becoming
necessary to treat reliability as a first-class citizen in system design. In
particular, reliability decisions taken early in system design can have
significant benefits in terms of design quality. Motivated by this observation,
this paper presents a reliability-centric high-level synthesis approach that
addresses the soft error problem. The proposed approach tries to maximize
reliability of the design while observing the bounds on area and performance,
and makes use of our reliability characterization of hardware components such
as adders and multipliers. We implemented the proposed approach, performed
experiments with several designs, and compared the results with those obtained
by a prior proposal.
| cs.AR | importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing mainly due to ever shrinking geometries higherdensity circuits and employment of powersaving techniques such as voltage scaling and component shutdown as a result it is becoming necessary to treat reliability as a firstclass citizen in system design in particular reliability decisions taken early in system design can have significant benefits in terms of design quality motivated by this observation this paper presents a reliabilitycentric highlevel synthesis approach that addresses the soft error problem the proposed approach tries to maximize reliability of the design while observing the bounds on area and performance and makes use of our reliability characterization of hardware components such as adders and multipliers we implemented the proposed approach performed experiments with several designs and compared the results with those obtained by a prior proposal | [['importance', 'of', 'addressing', 'soft', 'errors', 'in', 'both', 'safety', 'critical', 'applications', 'and', 'commercial', 'consumer', 'products', 'is', 'increasing', 'mainly', 'due', 'to', 'ever', 'shrinking', 'geometries', 'higherdensity', 'circuits', 'and', 'employment', 'of', 'powersaving', 'techniques', 'such', 'as', 'voltage', 'scaling', 'and', 'component', 'shutdown', 'as', 'a', 'result', 'it', 'is', 'becoming', 'necessary', 'to', 'treat', 'reliability', 'as', 'a', 'firstclass', 'citizen', 'in', 'system', 'design', 'in', 'particular', 'reliability', 'decisions', 'taken', 'early', 'in', 'system', 'design', 'can', 'have', 'significant', 'benefits', 'in', 'terms', 'of', 'design', 'quality', 'motivated', 'by', 'this', 'observation', 'this', 'paper', 'presents', 'a', 'reliabilitycentric', 'highlevel', 'synthesis', 'approach', 'that', 'addresses', 'the', 'soft', 'error', 'problem', 'the', 'proposed', 'approach', 'tries', 'to', 'maximize', 'reliability', 'of', 'the', 'design', 'while', 'observing', 'the', 'bounds', 'on', 'area', 'and', 'performance', 'and', 'makes', 'use', 'of', 'our', 'reliability', 'characterization', 'of', 'hardware', 'components', 'such', 'as', 'adders', 'and', 'multipliers', 'we', 'implemented', 'the', 'proposed', 'approach', 'performed', 'experiments', 'with', 'several', 'designs', 'and', 'compared', 'the', 'results', 'with', 'those', 'obtained', 'by', 'a', 'prior', 'proposal']] | [-0.12201872620154434, 0.009509023387168705, -0.03149469978090796, 0.00796938631650795, -0.07286333549000375, -0.13149610132923428, 0.07091984541309525, 0.39485100303894616, -0.20629811696183514, -0.3730778896420355, 0.16673164938914287, -0.24856364591257044, -0.1728822705860604, 0.25180093172780227, -0.14097050843025807, 0.13609913324373185, 0.07813988323159464, -0.0218952795667705, -0.05737378213388196, -0.2679215651628574, 0.2626647264901614, 0.10450220800785374, 0.3460888310899617, 0.06416945419812077, 0.0570784870381008, 0.023735306845505684, -0.039251622212657204, 0.01755214319564402, -0.07565046388609376, 0.13810102638877061, 0.30795657661543424, 0.1830843236505605, 0.3338568241132135, -0.4193158873724161, -0.19640710445540682, 0.061222964664921165, 0.14082927718548707, 0.034039492671325486, -0.07302446707732267, -0.2586046659164655, 0.07561310483339492, -0.22768419075914673, -0.10520150283561416, -0.10353848903950691, -0.031246565731609582, 0.028027250417131066, -0.25316434355885525, -0.014383241585062318, 0.05885613039070347, 0.033822178512706726, -0.04894372943828119, -0.1347576831729794, 0.020875944058299328, 0.15779888893589936, 0.05570104915950395, 0.006056037272366, 0.14925971066802216, -0.13592902076443736, -0.1545038842727286, 0.380505595389019, -0.004543102592308546, -0.17321261482946182, 0.18888416439688333, -0.040716150206182494, -0.14340760840863828, 0.09912448377318969, 0.21356581398089167, 0.058946469857711604, -0.1619814071266479, 0.038742301553163126, 0.07603155845664704, 0.17337770575106565, 0.04532836122982676, 0.0613702956413273, 0.17919507209690366, 0.23770741313781169, 0.07302033761798028, 0.17128623668272475, -0.05254054308744331, -0.0642094028110183, -0.257269682134764, -0.14424987153263277, -0.16198016973343535, -0.004781529466411702, -0.05179676280406543, -0.1148405596802444, 0.38086042252802094, 0.2053650820096561, 0.1379092989594374, 0.0713014961220324, 0.38775145649437753, 0.07738945795437091, 0.1039218024717985, 0.05041548059958125, 0.21865542414417805, 0.08034979812694307, 0.14546254906363942, -0.19179309057448926, 0.09792849063729002, 0.015336214983671851] |
710.4685 | Reliable System Specification for Self-Checking Data-Paths | The design of reliable circuits has received a lot of attention in the past,
leading to the definition of several design techniques introducing fault
detection and fault tolerance properties in systems for critical
applications/environments. Such design methodologies tackled the problem at
different abstraction levels, from switch-level to logic, RT level, and more
recently to system level. Aim of this paper is to introduce a novel
system-level technique based on the redefinition of the operators functionality
in the system specification. This technique provides reliability properties to
the system data path, transparently with respect to the designer. Feasibility,
fault coverage, performance degradation and overheads are investigated on a FIR
circuit.
| cs.AR | the design of reliable circuits has received a lot of attention in the past leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applicationsenvironments such design methodologies tackled the problem at different abstraction levels from switchlevel to logic rt level and more recently to system level aim of this paper is to introduce a novel systemlevel technique based on the redefinition of the operators functionality in the system specification this technique provides reliability properties to the system data path transparently with respect to the designer feasibility fault coverage performance degradation and overheads are investigated on a fir circuit | [['the', 'design', 'of', 'reliable', 'circuits', 'has', 'received', 'a', 'lot', 'of', 'attention', 'in', 'the', 'past', 'leading', 'to', 'the', 'definition', 'of', 'several', 'design', 'techniques', 'introducing', 'fault', 'detection', 'and', 'fault', 'tolerance', 'properties', 'in', 'systems', 'for', 'critical', 'applicationsenvironments', 'such', 'design', 'methodologies', 'tackled', 'the', 'problem', 'at', 'different', 'abstraction', 'levels', 'from', 'switchlevel', 'to', 'logic', 'rt', 'level', 'and', 'more', 'recently', 'to', 'system', 'level', 'aim', 'of', 'this', 'paper', 'is', 'to', 'introduce', 'a', 'novel', 'systemlevel', 'technique', 'based', 'on', 'the', 'redefinition', 'of', 'the', 'operators', 'functionality', 'in', 'the', 'system', 'specification', 'this', 'technique', 'provides', 'reliability', 'properties', 'to', 'the', 'system', 'data', 'path', 'transparently', 'with', 'respect', 'to', 'the', 'designer', 'feasibility', 'fault', 'coverage', 'performance', 'degradation', 'and', 'overheads', 'are', 'investigated', 'on', 'a', 'fir', 'circuit']] | [-0.16264367863021897, -0.03380005683679626, -0.04789437816197158, -0.005421241878241933, -0.07759472399835808, -0.14900467652423344, 0.09085885984952154, 0.3979433005464808, -0.25935282749299593, -0.33504415324390513, 0.10059546516826025, -0.23462004341044515, -0.16639359421448185, 0.2080077336538794, -0.1355048210518259, 0.16191377716121386, 0.0318979728481796, 0.008617762447651124, -0.06263184747087576, -0.23373625696118358, 0.29553385120201503, 0.14043936461104817, 0.3371530179426355, 0.06355126176626896, 0.07590139195221951, -0.014858537650104822, 0.018144831742283027, 0.009908145550585721, -0.10124312362080123, 0.15674687778238944, 0.2918481713793469, 0.20873299389550426, 0.3277874932501395, -0.43227450386181754, -0.2340307368958404, 0.036806850193314394, 0.08652069420061724, 0.09235869029774067, -0.029475615171628854, -0.26376396119770296, 0.13418325138682463, -0.20537129943786225, -0.07186786560034204, -0.07067339852417134, -0.01958950549223513, -0.02642390877008438, -0.22309190631439946, -0.04980908049147506, 0.0508720405215292, 0.09125356247894606, -0.019489836400234193, -0.08786001481348649, 0.013281004252966563, 0.13435640821578246, -0.01800564647968507, -0.000490054674336757, 0.15254491715217536, -0.11578867327254969, -0.16119951788634765, 0.3684388694687272, 0.019348828910568834, -0.20980834902070886, 0.19053167568844795, -0.05241633623065251, -0.1847313792392049, 0.14556254013353642, 0.2300626625063091, 0.05903940819113797, -0.22014287018375295, 0.052380061069753826, 0.11589711986236134, 0.19876137275231193, 0.036297441080195024, 0.08957197330892086, 0.19260662084178756, 0.2529648648539804, 0.09848818910431187, 0.1818576435830866, -0.055032449480111024, -0.06344957572610099, -0.2441950158198487, -0.14942894577277158, -0.12612448947697455, -0.005746203041986896, -0.0336578318357461, -0.1677542507499105, 0.42836737896333327, 0.24183671792775815, 0.1262195583527363, 0.08872792373174133, 0.3776407476233424, 0.11940323322449091, 0.10436532797537884, 0.027813563944842173, 0.18752861258086204, 0.08133539082131015, 0.1336494115409705, -0.21140318200793085, 0.10750487663361402, 0.041210283447311806] |
710.4686 | Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores | Many SOCs today contain both digital and analog embedded cores. Even though
the test cost for such mixed-signal SOCs is significantly higher than that for
digital SOCs, most prior research in this area has focused exclusively on
digital cores. We propose a low-cost test development methodology for
mixed-signal SOCs that allows the analog and digital cores to be tested in a
unified manner, thereby minimizing the overall test cost. The analog cores in
the SOC are wrapped such that they can be accessed using a digital test access
mechanism (TAM). We evaluate the impact of the use of analog test wrappers on
area overhead and test time. To reduce area overhead, we present an analog test
wrapper optimization technique, which is then combined with TAM optimization in
a cost-oriented heuristic approach for test scheduling. We also demonstrate the
feasibility of using analog wrappers by presenting transistor-level simulations
for an analog wrapper and a representative core. We present experimental
results on test scheduling for an ITC'02 benchmark SOC that has been augmented
with five analog cores.
| cs.AR | many socs today contain both digital and analog embedded cores even though the test cost for such mixedsignal socs is significantly higher than that for digital socs most prior research in this area has focused exclusively on digital cores we propose a lowcost test development methodology for mixedsignal socs that allows the analog and digital cores to be tested in a unified manner thereby minimizing the overall test cost the analog cores in the soc are wrapped such that they can be accessed using a digital test access mechanism tam we evaluate the impact of the use of analog test wrappers on area overhead and test time to reduce area overhead we present an analog test wrapper optimization technique which is then combined with tam optimization in a costoriented heuristic approach for test scheduling we also demonstrate the feasibility of using analog wrappers by presenting transistorlevel simulations for an analog wrapper and a representative core we present experimental results on test scheduling for an itc02 benchmark soc that has been augmented with five analog cores | [['many', 'socs', 'today', 'contain', 'both', 'digital', 'and', 'analog', 'embedded', 'cores', 'even', 'though', 'the', 'test', 'cost', 'for', 'such', 'mixedsignal', 'socs', 'is', 'significantly', 'higher', 'than', 'that', 'for', 'digital', 'socs', 'most', 'prior', 'research', 'in', 'this', 'area', 'has', 'focused', 'exclusively', 'on', 'digital', 'cores', 'we', 'propose', 'a', 'lowcost', 'test', 'development', 'methodology', 'for', 'mixedsignal', 'socs', 'that', 'allows', 'the', 'analog', 'and', 'digital', 'cores', 'to', 'be', 'tested', 'in', 'a', 'unified', 'manner', 'thereby', 'minimizing', 'the', 'overall', 'test', 'cost', 'the', 'analog', 'cores', 'in', 'the', 'soc', 'are', 'wrapped', 'such', 'that', 'they', 'can', 'be', 'accessed', 'using', 'a', 'digital', 'test', 'access', 'mechanism', 'tam', 'we', 'evaluate', 'the', 'impact', 'of', 'the', 'use', 'of', 'analog', 'test', 'wrappers', 'on', 'area', 'overhead', 'and', 'test', 'time', 'to', 'reduce', 'area', 'overhead', 'we', 'present', 'an', 'analog', 'test', 'wrapper', 'optimization', 'technique', 'which', 'is', 'then', 'combined', 'with', 'tam', 'optimization', 'in', 'a', 'costoriented', 'heuristic', 'approach', 'for', 'test', 'scheduling', 'we', 'also', 'demonstrate', 'the', 'feasibility', 'of', 'using', 'analog', 'wrappers', 'by', 'presenting', 'transistorlevel', 'simulations', 'for', 'an', 'analog', 'wrapper', 'and', 'a', 'representative', 'core', 'we', 'present', 'experimental', 'results', 'on', 'test', 'scheduling', 'for', 'an', 'itc02', 'benchmark', 'soc', 'that', 'has', 'been', 'augmented', 'with', 'five', 'analog', 'cores']] | [-0.11673855149054102, -0.019020544006239756, -0.056444280734285715, 0.051336979494164034, -0.09354178421199322, -0.14704705413697022, 0.06865485496336728, 0.38943860067852903, -0.17751709409124616, -0.35276505177042317, 0.15410193078752074, -0.2103969129215693, -0.15685862343758344, 0.28030170876532795, -0.0849607415563826, 0.06991072795819492, 0.06914877190121582, -0.05746235686487385, -0.04048246279225818, -0.2724187223826136, 0.24240040592450116, 0.08722430400284273, 0.34087826751704725, 0.004563655726212476, 0.08751006835872041, -0.024208900263266903, -0.027183643994087885, 0.01415755889245442, -0.048520668425231374, 0.11190661653344121, 0.24604720761999488, 0.19272838198978987, 0.2786404361056962, -0.4646825799558844, -0.16224987868751797, 0.08908697799646428, 0.14309108848683535, 0.08954981464826103, -0.12066210660484752, -0.24500942418085678, 0.14980797180639846, -0.22569126137399248, -0.05671630057639309, -0.10382735820487142, -0.001601239251238959, 0.006647202574781009, -0.2616580864467791, -0.012411381973652168, 0.016612062102981977, 0.07083806350295033, -0.03018638119267832, -0.1317529451181846, 0.05274182015231677, 0.0947601714497432, -0.05782276730385742, 0.030955359733530453, 0.16121978072249996, -0.08469929944420333, -0.15849835083154695, 0.3705729720621769, -0.0374836712214996, -0.21633318578026126, 0.19500942049281939, -0.020821040917986207, -0.14780268070154956, 0.08920368036521333, 0.25785276401788, 0.06464109286665916, -0.16519542242799487, 0.06976848062526966, -0.009305329924183233, 0.22241431362527822, 0.05899145275088293, 0.01668668048190219, 0.21006533756319964, 0.25022376846522093, 0.045618549011581175, 0.1905031167715788, -0.1244399041882051, -0.09821174757355558, -0.23042918689948108, -0.21417320670560003, -0.19872304933411736, 0.006301497657384191, -0.03579952230909839, -0.12380036575985806, 0.34791494614311624, 0.18464981055951543, 0.11309390166242207, 0.07992262025031129, 0.3755340757540294, 0.0675230808689126, 0.17338056155081305, 0.10386221562113081, 0.20567198131233455, 0.03064993995774005, 0.11975702501567347, -0.17697070086907063, 0.02419993915462068, 0.012389130423377668] |
710.4687 | On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of
System Chips | Multi-site testing is a popular and effective way to increase test throughput
and reduce test costs. We present a test throughput model, in which we focus on
wafer testing, and consider parameters like test time, index time,
abort-on-fail, and contact yield. Conventional multi-site testing requires
sufficient ATE resources, such as ATE channels, to allow to test multiple SOCs
in parallel. In this paper, we design and optimize on-chip DfT, in order to
maximize the test throughput for a given SOC and ATE. The on-chip DfT consists
of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We
present experimental results for a Philips SOC and several ITC'02 SOC Test
Benchmarks.
| cs.AR | multisite testing is a popular and effective way to increase test throughput and reduce test costs we present a test throughput model in which we focus on wafer testing and consider parameters like test time index time abortonfail and contact yield conventional multisite testing requires sufficient ate resources such as ate channels to allow to test multiple socs in parallel in this paper we design and optimize onchip dft in order to maximize the test throughput for a given soc and ate the onchip dft consists of an erpct wrapper and for modular socs module wrappers and tams we present experimental results for a philips soc and several itc02 soc test benchmarks | [['multisite', 'testing', 'is', 'a', 'popular', 'and', 'effective', 'way', 'to', 'increase', 'test', 'throughput', 'and', 'reduce', 'test', 'costs', 'we', 'present', 'a', 'test', 'throughput', 'model', 'in', 'which', 'we', 'focus', 'on', 'wafer', 'testing', 'and', 'consider', 'parameters', 'like', 'test', 'time', 'index', 'time', 'abortonfail', 'and', 'contact', 'yield', 'conventional', 'multisite', 'testing', 'requires', 'sufficient', 'ate', 'resources', 'such', 'as', 'ate', 'channels', 'to', 'allow', 'to', 'test', 'multiple', 'socs', 'in', 'parallel', 'in', 'this', 'paper', 'we', 'design', 'and', 'optimize', 'onchip', 'dft', 'in', 'order', 'to', 'maximize', 'the', 'test', 'throughput', 'for', 'a', 'given', 'soc', 'and', 'ate', 'the', 'onchip', 'dft', 'consists', 'of', 'an', 'erpct', 'wrapper', 'and', 'for', 'modular', 'socs', 'module', 'wrappers', 'and', 'tams', 'we', 'present', 'experimental', 'results', 'for', 'a', 'philips', 'soc', 'and', 'several', 'itc02', 'soc', 'test', 'benchmarks']] | [-0.12898950378241186, -0.007235112992533356, -0.03369796332818541, 0.04426173262975432, -0.052459028346294706, -0.23375595306808297, 0.0954523640276007, 0.4073958780616522, -0.1842304537496106, -0.3590588313866068, 0.07353525359014218, -0.21487239331261002, -0.12131128213791685, 0.23077138248746368, -0.0890859249799343, 0.12601732057519258, 0.10087491193447601, -0.039979922456074166, -0.03483699049207974, -0.3000394566693682, 0.2243003293448551, 0.11979711205613884, 0.3352792072448541, 0.06958712906661359, 0.07193313678726554, 0.03317336228422143, -0.01873170661697672, -0.012833364731208845, -0.09559508580291136, 0.10018852356059307, 0.28987545655532315, 0.12418213680555874, 0.28857451011850077, -0.4600837356156924, -0.12946064361286433, 0.05378789679062637, 0.053756367622620684, 0.06878401303812015, -0.023323526421815833, -0.24358259301039983, 0.08484288341662084, -0.20996196998113936, -0.032883160673505205, -0.13462712734260343, -0.0030537396531806075, 0.013235700435259125, -0.3698468273420903, 0.016188006880640222, 0.019547465845773167, 0.09567506431855939, -0.04116171885874461, -0.1037844102491032, 0.08256010558794845, 0.11776180670025166, 0.0028405827131461015, 0.012626502823761918, 0.1200039911380207, -0.09424344801597974, -0.1478950741192834, 0.3864679823883555, -0.07049871629040519, -0.192454702174291, 0.2118393877013163, -0.011267414792779495, -0.14050513420423325, 0.024631297969343987, 0.27263234310190787, 0.07062306080902503, -0.1736998203125867, 0.05704003106326457, 0.04277947169135917, 0.22173453960144385, 0.052942747870375485, 0.03403682105073875, 0.15330322296781973, 0.23390909611162813, 0.057162269158288835, 0.18207441749770872, -0.16407413150988182, -0.05197441239248623, -0.2528689193629279, -0.26642345005477014, -0.16752928560176356, -0.00510319333777509, -0.07462811137388185, -0.15740845783359625, 0.3968479742042043, 0.20364126324314963, 0.0939740424959878, 0.1231963221502321, 0.2984275455332615, 0.05342571678708985, 0.12304007052020594, 0.09829204029572958, 0.19593503152612934, 0.031124283190795476, 0.07407299383035437, -0.20946575368077242, 0.027710519828410312, -0.03120389587976123] |
710.4688 | On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based
FPGAs | Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for
SRAM-based FPGA. However, one of the main challenges in achieving 100%
robustness in designs protected by TMR running on programmable platforms is to
prevent upsets in the routing from provoking undesirable connections between
signals from distinct redundant logic parts, which can generate an error in the
output. This paper investigates the optimal design of the TMR logic (e.g., by
cleverly inserting voters) to ensure robustness. Four different versions of a
TMR digital filter were analyzed by fault injection. Faults were randomly
inserted straight into the bitstream of the FPGA. The experimental results
presented in this paper demonstrate that the number and placement of voters in
the TMR design can directly affect the fault tolerance, ranging from 4.03% to
0.98% the number of upsets in the routing able to cause an error in the TMR
circuit.
| cs.AR | triple modular redundancy tmr is a suitable fault tolerant technique for srambased fpga however one of the main challenges in achieving 100 robustness in designs protected by tmr running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts which can generate an error in the output this paper investigates the optimal design of the tmr logic eg by cleverly inserting voters to ensure robustness four different versions of a tmr digital filter were analyzed by fault injection faults were randomly inserted straight into the bitstream of the fpga the experimental results presented in this paper demonstrate that the number and placement of voters in the tmr design can directly affect the fault tolerance ranging from 403 to 098 the number of upsets in the routing able to cause an error in the tmr circuit | [['triple', 'modular', 'redundancy', 'tmr', 'is', 'a', 'suitable', 'fault', 'tolerant', 'technique', 'for', 'srambased', 'fpga', 'however', 'one', 'of', 'the', 'main', 'challenges', 'in', 'achieving', '100', 'robustness', 'in', 'designs', 'protected', 'by', 'tmr', 'running', 'on', 'programmable', 'platforms', 'is', 'to', 'prevent', 'upsets', 'in', 'the', 'routing', 'from', 'provoking', 'undesirable', 'connections', 'between', 'signals', 'from', 'distinct', 'redundant', 'logic', 'parts', 'which', 'can', 'generate', 'an', 'error', 'in', 'the', 'output', 'this', 'paper', 'investigates', 'the', 'optimal', 'design', 'of', 'the', 'tmr', 'logic', 'eg', 'by', 'cleverly', 'inserting', 'voters', 'to', 'ensure', 'robustness', 'four', 'different', 'versions', 'of', 'a', 'tmr', 'digital', 'filter', 'were', 'analyzed', 'by', 'fault', 'injection', 'faults', 'were', 'randomly', 'inserted', 'straight', 'into', 'the', 'bitstream', 'of', 'the', 'fpga', 'the', 'experimental', 'results', 'presented', 'in', 'this', 'paper', 'demonstrate', 'that', 'the', 'number', 'and', 'placement', 'of', 'voters', 'in', 'the', 'tmr', 'design', 'can', 'directly', 'affect', 'the', 'fault', 'tolerance', 'ranging', 'from', '403', 'to', '098', 'the', 'number', 'of', 'upsets', 'in', 'the', 'routing', 'able', 'to', 'cause', 'an', 'error', 'in', 'the', 'tmr', 'circuit']] | [-0.22446900824633464, 0.05158569025412387, 0.005224051677991878, -0.010474709640831163, -0.03844425377770078, -0.2143782468046993, 0.08607216199942903, 0.3821321887136373, -0.2653381873738684, -0.38408724985353343, 0.08408234218990251, -0.23773775943108413, -0.16271638811553177, 0.21359897512393966, -0.17629524056276638, 0.09143296175330162, 0.035366914473966, -0.011062438970540127, -0.017450735823742482, -0.28406532602512263, 0.25414852174764424, 0.07871432312802501, 0.3367391453915569, 0.030184688695580046, 0.06327954512599805, 0.018471338738342873, 0.03529630103052836, 0.019998923980643693, -0.04207333326021772, 0.080530618761159, 0.3144289859226101, 0.11782565692835169, 0.26617361540102386, -0.46964150146072514, -0.10450376109666612, 0.06753586686203537, 0.1261015406438773, 0.107645937078154, -0.026324134185265954, -0.2954082698983855, 0.1657839657974825, -0.190791455751336, -0.020185807107051527, -0.022574936184666935, -0.03390428773127496, 0.03384888553409837, -0.2347432917226361, -0.03945985541213304, 0.03824369530496506, 0.044082370612208974, 0.0033317236516828812, -0.10379963433720835, -0.010232360191541175, 0.11611702909999311, -0.01787424953144095, -0.015834243851713836, 0.18923878400029984, -0.08175021387702046, -0.21385165462940167, 0.31480698222422027, 0.04133152871788161, -0.1783733150590058, 0.08842173280283706, -0.022524169011500804, -0.11496304498653706, 0.1632985558603214, 0.1866571289576488, 0.03792593261858525, -0.17172051091002274, 0.021357213114691284, 0.08751671098544236, 0.23245545942974213, 0.12608737930693753, 0.058036371890123784, 0.19708955590294241, 0.18325697341040798, 0.0845389451436086, 0.20368971763185084, -0.11072415005625386, -0.05060035050750952, -0.258116207931953, -0.14728799981343374, -0.1519122671906849, 0.020712814446895905, -0.1055542659236729, -0.18444038624077883, 0.4272503017014122, 0.2372091724537313, 0.17027178504312895, 0.06171880360797992, 0.38205307577130676, 0.05159430051771031, 0.14430543271288887, 0.05531982729236965, 0.2171458243232935, 0.0466823641048132, 0.1111136517512982, -0.22192774212453514, 0.15543357988066767, -0.028244921270987555] |
710.4689 | Functional Equivalence Checking for Verification of Algebraic
Transformations on Array-Intensive Source Code | Development of energy and performance-efficient embedded software is
increasingly relying on application of complex transformations on the critical
parts of the source code. Designers applying such nontrivial source code
transformations are often faced with the problem of ensuring functional
equivalence of the original and transformed programs. Currently they have to
rely on incomplete and time-consuming simulation. Formal automatic verification
of the transformed program against the original is instead desirable. This
calls for equivalence checking tools similar to the ones available for
comparing digital circuits. We present such a tool to compare array-intensive
programs related through a combination of important global transformations like
expression propagations, loop and algebraic transformations. When the
transformed program fails to pass the equivalence check, the tool provides
specific feedback on the possible locations of errors.
| cs.LO | development of energy and performanceefficient embedded software is increasingly relying on application of complex transformations on the critical parts of the source code designers applying such nontrivial source code transformations are often faced with the problem of ensuring functional equivalence of the original and transformed programs currently they have to rely on incomplete and timeconsuming simulation formal automatic verification of the transformed program against the original is instead desirable this calls for equivalence checking tools similar to the ones available for comparing digital circuits we present such a tool to compare arrayintensive programs related through a combination of important global transformations like expression propagations loop and algebraic transformations when the transformed program fails to pass the equivalence check the tool provides specific feedback on the possible locations of errors | [['development', 'of', 'energy', 'and', 'performanceefficient', 'embedded', 'software', 'is', 'increasingly', 'relying', 'on', 'application', 'of', 'complex', 'transformations', 'on', 'the', 'critical', 'parts', 'of', 'the', 'source', 'code', 'designers', 'applying', 'such', 'nontrivial', 'source', 'code', 'transformations', 'are', 'often', 'faced', 'with', 'the', 'problem', 'of', 'ensuring', 'functional', 'equivalence', 'of', 'the', 'original', 'and', 'transformed', 'programs', 'currently', 'they', 'have', 'to', 'rely', 'on', 'incomplete', 'and', 'timeconsuming', 'simulation', 'formal', 'automatic', 'verification', 'of', 'the', 'transformed', 'program', 'against', 'the', 'original', 'is', 'instead', 'desirable', 'this', 'calls', 'for', 'equivalence', 'checking', 'tools', 'similar', 'to', 'the', 'ones', 'available', 'for', 'comparing', 'digital', 'circuits', 'we', 'present', 'such', 'a', 'tool', 'to', 'compare', 'arrayintensive', 'programs', 'related', 'through', 'a', 'combination', 'of', 'important', 'global', 'transformations', 'like', 'expression', 'propagations', 'loop', 'and', 'algebraic', 'transformations', 'when', 'the', 'transformed', 'program', 'fails', 'to', 'pass', 'the', 'equivalence', 'check', 'the', 'tool', 'provides', 'specific', 'feedback', 'on', 'the', 'possible', 'locations', 'of', 'errors']] | [-0.1117071501775938, -0.013796315792449347, -0.08387894581959356, 0.13836995256041712, -0.12601825948364623, -0.17376640476066413, 0.04788706593552795, 0.36336208444352697, -0.28942592895963765, -0.34304326487426445, 0.1861328980445451, -0.258009486769392, -0.11546129148130811, 0.25654876069165766, -0.05533597663074263, 0.12521580043505495, 0.09499169568582548, 0.008311726147396944, -0.08025736848749936, -0.22292672544277795, 0.3352110344535253, 0.07392614169456944, 0.29904857012406577, -0.020647041063286423, 0.09831929534644358, 0.05462545403059366, -0.0957085516993103, 0.010754878996636748, -0.06086141578248137, 0.13872780352207562, 0.27895404001575064, 0.2281776956047892, 0.2559689464117217, -0.46639691474370837, -0.14002245286934253, 0.06845417277113806, 0.1252525740130768, 0.11333878487935216, -0.05353202903551585, -0.2909037202420666, 0.062441925136885776, -0.12404561819010011, -0.09015186616461578, -0.11721827619613742, -0.01962575041615646, 0.011124583991250967, -0.22862880460837284, -0.02611284188222228, 0.05516183056582616, 0.09111394814589596, -0.025451539132898073, -0.07886743315818213, -0.02599114693488603, 0.1913177059905138, 0.03149683020026313, 0.033040683507537985, 0.1418808773489977, -0.09388700948008813, -0.09761179988565818, 0.40960269459471926, 0.007463092362970172, -0.20688147383135208, 0.2353146985305224, -0.006696739113031644, -0.17856791517953938, 0.10708383214109995, 0.1615037202952415, 0.08514157172114181, -0.14527845207299747, 0.10100463463917492, 0.03584975336942323, 0.19899877688964815, 0.03548210052274695, 0.012635846805619442, 0.20157631844333482, 0.13745627205499894, 0.022876106461099402, 0.18538842009981787, 0.027429407980846695, -0.09483041245844141, -0.3076650731734873, -0.15560503641334106, -0.10825074675280279, 0.018576352571056585, -0.050858105556199726, -0.20343022869705538, 0.37430534068876364, 0.176003202126938, 0.08760817378656718, 0.06611708612877905, 0.3401963133511581, 0.10817039347992564, 0.12123994541255478, 0.06138751137356355, 0.17823407460576085, 0.08981754414656559, 0.07546893047493347, -0.18857380883460204, 0.11646349379961474, 0.06912588427855273] |
710.469 | RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power | This paper presents a novel repeater insertion algorithm for interconnect
power minimization. The novelty of our approach is in the judicious integration
of an analytical solver and a dynamic programming based method. Specifically,
the analytical solver chooses a concise repeater library and a small set of
repeater location candidates such that the dynamic programming algorithm can be
performed fast with little degradation of the solution quality. In comparison
with previously reported repeater insertion schemes, within comparable
runtimes, our approach achieves up to 37% higher power savings. Moreover, for
the same design quality, our scheme attains a speedup of two orders of
magnitude.
| cs.OH | this paper presents a novel repeater insertion algorithm for interconnect power minimization the novelty of our approach is in the judicious integration of an analytical solver and a dynamic programming based method specifically the analytical solver chooses a concise repeater library and a small set of repeater location candidates such that the dynamic programming algorithm can be performed fast with little degradation of the solution quality in comparison with previously reported repeater insertion schemes within comparable runtimes our approach achieves up to 37 higher power savings moreover for the same design quality our scheme attains a speedup of two orders of magnitude | [['this', 'paper', 'presents', 'a', 'novel', 'repeater', 'insertion', 'algorithm', 'for', 'interconnect', 'power', 'minimization', 'the', 'novelty', 'of', 'our', 'approach', 'is', 'in', 'the', 'judicious', 'integration', 'of', 'an', 'analytical', 'solver', 'and', 'a', 'dynamic', 'programming', 'based', 'method', 'specifically', 'the', 'analytical', 'solver', 'chooses', 'a', 'concise', 'repeater', 'library', 'and', 'a', 'small', 'set', 'of', 'repeater', 'location', 'candidates', 'such', 'that', 'the', 'dynamic', 'programming', 'algorithm', 'can', 'be', 'performed', 'fast', 'with', 'little', 'degradation', 'of', 'the', 'solution', 'quality', 'in', 'comparison', 'with', 'previously', 'reported', 'repeater', 'insertion', 'schemes', 'within', 'comparable', 'runtimes', 'our', 'approach', 'achieves', 'up', 'to', '37', 'higher', 'power', 'savings', 'moreover', 'for', 'the', 'same', 'design', 'quality', 'our', 'scheme', 'attains', 'a', 'speedup', 'of', 'two', 'orders', 'of', 'magnitude']] | [-0.1525641077166131, -0.035364355388475245, -0.09458809133673854, -0.008985893727809774, -0.08528422146086015, -0.1761097627116696, 0.1319073070418181, 0.4168871243246922, -0.24119079556297876, -0.4029609802379912, 0.0647357860511607, -0.22548276081900387, -0.1355428728183695, 0.26946445055963364, -0.07891384276844488, 0.10240884394129264, 0.10308372116574616, -0.007091903492954432, -0.08913070354930253, -0.25391817001589373, 0.18397193769787384, 0.1124694019592568, 0.32196866658826667, 0.039908064686802816, 0.12423543869882968, -0.04043150564607726, 0.007542782125300637, -0.00800030977994788, -0.04365214519466641, 0.17633661697846928, 0.23668370734644578, 0.1361414528287509, 0.324153824965013, -0.40243148940670137, -0.1728503360577366, 0.015445775589814373, 0.13069347609017118, 0.10366746270116053, -0.07774930209487531, -0.22022647284628713, 0.11534688221724412, -0.2559621966005686, -0.07722551342300779, -0.07766083176430388, -0.042398066200571606, 0.0033147837784068255, -0.3148038741452254, 0.018918363964664477, 0.004293004799561173, 0.0032512605254191394, -0.034436290422865355, -0.1315359753994819, 0.10255114239293571, 0.07438548319224342, -0.027145302791705392, 0.07412998134489446, 0.10335209357378748, -0.06517618992959387, -0.22581365349013174, 0.37622744411083997, -0.05062602280511284, -0.17538679082873368, 0.1572632809904605, -0.03937540627906427, -0.14430616561588192, 0.18502766068102608, 0.18524250530583017, 0.15634118800288907, -0.14481016671211988, 0.03140492439064581, 0.012131432591773132, 0.21494688550192936, 0.05409096998582576, 0.06604608355144806, 0.09707619592675246, 0.27237161945588156, 0.09095990534543115, 0.17591206942954302, -0.07795682286058425, -0.11385047747114417, -0.27447764034949096, -0.16046789257476726, -0.20098958201204226, -0.01116039105188832, -0.18373921777403632, -0.14935539489812857, 0.3968851999917188, 0.18509082349619882, 0.1192978214810365, 0.130292369755825, 0.41072194833381503, 0.10511373933281991, 0.10280997674300463, 0.16056639124073235, 0.19747325017427406, 0.024165586954183586, 0.07943992431369136, -0.2341689066955701, 0.06795398719316605, 0.060722917656176816] |
710.4691 | An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer
Types | Buffer insertion is a popular technique to reduce the interconnect delay. The
classic buffer insertion algorithm of van Ginneken has time complexity O(n^2),
where n is the number of buffer positions. Lillis, Cheng and Lin extended van
Ginneken's algorithm to allow b buffer types in time O (b^2 n^2). For modern
design libraries that contain hundreds of buffers, it is a serious challenge to
balance the speed and performance of the buffer insertion algorithm. In this
paper, we present a new algorithm that computes the optimal buffer insertion in
O (bn^2) time. The reduction is achieved by the observation that the (Q, C)
pairs of the candidates that generate the new candidates must form a convex
hull. On industrial test cases, the new algorithm is faster than the previous
best buffer insertion algorithms by orders of magnitude.
| cs.AR | buffer insertion is a popular technique to reduce the interconnect delay the classic buffer insertion algorithm of van ginneken has time complexity on2 where n is the number of buffer positions lillis cheng and lin extended van ginnekens algorithm to allow b buffer types in time o b2 n2 for modern design libraries that contain hundreds of buffers it is a serious challenge to balance the speed and performance of the buffer insertion algorithm in this paper we present a new algorithm that computes the optimal buffer insertion in o bn2 time the reduction is achieved by the observation that the q c pairs of the candidates that generate the new candidates must form a convex hull on industrial test cases the new algorithm is faster than the previous best buffer insertion algorithms by orders of magnitude | [['buffer', 'insertion', 'is', 'a', 'popular', 'technique', 'to', 'reduce', 'the', 'interconnect', 'delay', 'the', 'classic', 'buffer', 'insertion', 'algorithm', 'of', 'van', 'ginneken', 'has', 'time', 'complexity', 'on2', 'where', 'n', 'is', 'the', 'number', 'of', 'buffer', 'positions', 'lillis', 'cheng', 'and', 'lin', 'extended', 'van', 'ginnekens', 'algorithm', 'to', 'allow', 'b', 'buffer', 'types', 'in', 'time', 'o', 'b2', 'n2', 'for', 'modern', 'design', 'libraries', 'that', 'contain', 'hundreds', 'of', 'buffers', 'it', 'is', 'a', 'serious', 'challenge', 'to', 'balance', 'the', 'speed', 'and', 'performance', 'of', 'the', 'buffer', 'insertion', 'algorithm', 'in', 'this', 'paper', 'we', 'present', 'a', 'new', 'algorithm', 'that', 'computes', 'the', 'optimal', 'buffer', 'insertion', 'in', 'o', 'bn2', 'time', 'the', 'reduction', 'is', 'achieved', 'by', 'the', 'observation', 'that', 'the', 'q', 'c', 'pairs', 'of', 'the', 'candidates', 'that', 'generate', 'the', 'new', 'candidates', 'must', 'form', 'a', 'convex', 'hull', 'on', 'industrial', 'test', 'cases', 'the', 'new', 'algorithm', 'is', 'faster', 'than', 'the', 'previous', 'best', 'buffer', 'insertion', 'algorithms', 'by', 'orders', 'of', 'magnitude']] | [-0.14240652190368455, 0.05953103841157324, -0.006336669187381196, -0.011691521187729911, -0.041133679279279134, -0.2002525436900445, 0.14755807209103158, 0.38201203892257674, -0.25123682302951034, -0.37831292896350815, 0.07441344757567842, -0.2659494025465935, -0.09922303322097982, 0.1690378224115763, -0.10507056165708979, 0.07595554305198811, 0.0646903583651353, 0.0025868748311203586, -0.026988573243785927, -0.3357320423932996, 0.20646369119727317, 0.07270579148125626, 0.2690064687552904, 0.02117532493421502, 0.04819598295591222, -0.014730621970244754, 0.005230354699445193, -0.014399771991181174, -0.10116569992565766, 0.09290542160751604, 0.2162206375332021, 0.15695018783375037, 0.2889987975358963, -0.4377613116347634, -0.15841470535066146, 0.05438759956342071, 0.12637510082559356, 0.09036658159387645, -0.07227749637686022, -0.17927783011778523, 0.11169586279394744, -0.1444836466698282, -0.07893822355015176, -0.01131757628172636, 0.06767242284554209, 0.011002720169872462, -0.2807110636286549, -0.002547495866388972, 0.06681028021405687, -0.028466861670725603, -0.01628416320726053, -0.15695383647150957, 0.031415622604927466, 0.0791076911272787, -0.019444817067262952, 0.058883486211355494, 0.11972399523009115, -0.06946325769826922, -0.13944869142359317, 0.3742142223836437, -0.0489555446700577, -0.13958550422320337, 0.17510344718110316, -0.03962197540842219, -0.11145994418870601, 0.19154060366493997, 0.16844385150653213, 0.13093637400515265, -0.12432709911059756, 0.1252417983800006, -0.047191048263391454, 0.1967679349924507, 0.16070532142497432, 0.011403404641896486, 0.09559469863358858, 0.1799989305019601, 0.10489019117259017, 0.1620217401867927, -0.0933160734147445, -0.0751785503512721, -0.2625245331671895, -0.21840739785476393, -0.18103533309585512, -0.003945717890399383, -0.10620792606587473, -0.1526105609631649, 0.31786418350851303, 0.14336220476838912, 0.19339461336190353, 0.04943623338172685, 0.3460592190359733, 0.09444703790011691, 0.10596793532022275, 0.11665408765035334, 0.14643515422140985, 0.03506702318641621, 0.11064580611453684, -0.262786680966296, 0.1023089470230599, 0.12086895465287867] |
710.4692 | Cantilever-Based Biosensors in CMOS Technology | Single-chip CMOS-based biosensors that feature microcantilevers as transducer
elements are presented. The cantilevers are functionalized for the capturing of
specific analytes, e.g., proteins or DNA. The binding of the analyte changes
the mechanical properties of the cantilevers such as surface stress and
resonant frequency, which can be detected by an integrated Wheatstone bridge.
The monolithic integrated readout allows for a high signal-to-noise ratio,
lowers the sensitivity to external interference and enables autonomous device
operation.
| cs.AR | singlechip cmosbased biosensors that feature microcantilevers as transducer elements are presented the cantilevers are functionalized for the capturing of specific analytes eg proteins or dna the binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency which can be detected by an integrated wheatstone bridge the monolithic integrated readout allows for a high signaltonoise ratio lowers the sensitivity to external interference and enables autonomous device operation | [['singlechip', 'cmosbased', 'biosensors', 'that', 'feature', 'microcantilevers', 'as', 'transducer', 'elements', 'are', 'presented', 'the', 'cantilevers', 'are', 'functionalized', 'for', 'the', 'capturing', 'of', 'specific', 'analytes', 'eg', 'proteins', 'or', 'dna', 'the', 'binding', 'of', 'the', 'analyte', 'changes', 'the', 'mechanical', 'properties', 'of', 'the', 'cantilevers', 'such', 'as', 'surface', 'stress', 'and', 'resonant', 'frequency', 'which', 'can', 'be', 'detected', 'by', 'an', 'integrated', 'wheatstone', 'bridge', 'the', 'monolithic', 'integrated', 'readout', 'allows', 'for', 'a', 'high', 'signaltonoise', 'ratio', 'lowers', 'the', 'sensitivity', 'to', 'external', 'interference', 'and', 'enables', 'autonomous', 'device', 'operation']] | [-0.13774793096692176, 0.15049301180536262, 0.008742328682864035, -0.0388316366494306, -0.043945683655643684, -0.19714479955743897, 0.0195322630807405, 0.4388861985927498, -0.25621918439739255, -0.3556082233962779, 0.04379287336927813, -0.2851525320125999, -0.13203038287355337, 0.240835563984473, -0.058717088040744735, 0.09460838302667882, 0.047768340918008946, -0.02726297962756173, 0.015840642572682653, -0.08213562067799471, 0.17934853797526779, 0.11723663581132486, 0.33192728551708767, 0.05326551465141411, 0.1518907417713136, -0.025927541299244843, 0.04610354720765876, -0.01873331025205049, -0.05909023960988191, 0.15467160577031178, 0.30997761968221216, 0.029505951235674927, 0.20505786211406057, -0.4618610831329951, -0.18680232049695947, 0.053697132066559246, 0.14043228071544012, 0.08814562564696865, -0.023523181632815582, -0.2751819045106704, 0.07152714015840478, -0.13079819723812713, -0.09801774190713626, -0.07280068940206154, -0.0035888542219795084, 0.10431518584389139, -0.23496185504906886, 0.04376628003838296, 0.027092239133560576, 0.06775971716018142, -0.05689817109551105, -0.10826993317066415, -0.04200475250144262, 0.15902643142003767, -0.07955272783953193, -0.047640733600191366, 0.35651269613614156, -0.12800038754436616, -0.08633524385545202, 0.34712420311611697, -0.04366776678157416, -0.169839876118695, 0.2083061121064364, -0.05280266123874163, -0.025300235613375098, 0.1524867581493045, 0.16447340237052255, 0.06780763215234352, -0.20638661089548338, -0.012232991176141376, 0.11633837861134796, 0.24288527102436167, 0.157823704107589, 0.09798306127305369, 0.22705752759341252, 0.2508920202333782, 0.06771399908875292, 0.16725674840288135, -0.15721106008198615, 0.04587800951196334, -0.22333963939013915, -0.22421167096173442, -0.17334791199096503, 0.028658546129795345, -0.08368506454949179, -0.19341368323846445, 0.35323432714023906, 0.06961301065107486, 0.1321670009779769, 0.009559042338042747, 0.3246324121813617, 0.09086424577666598, 0.1636500999117522, -0.08334056908466123, 0.2764975670976816, 0.13317122564940537, 0.10445061239816651, -0.28076337447006106, 0.058199814055114985, -0.051363851291810265] |
710.4693 | Memory Testing Under Different Stress Conditions: An Industrial
Evaluation | This paper presents the effectiveness of various stress conditions (mainly
voltage and frequency) on detecting the resistive shorts and open defects in
deep sub-micron embedded memories in an industrial environment. Simulation
studies on very-low voltage, high voltage and at-speed testing show the need of
the stress conditions for high quality products; i.e., low defect-per-million
(DPM) level, which is driving the semiconductor market today. The above test
conditions have been validated to screen out bad devices on real silicon (a
test-chip) built on CMOS 0.18 um technology. IFA (inductive fault analysis)
based simulation technique leads to an efficient fault coverage and DPM
estimator, which helps the customers upfront to make decisions on test
algorithm implementations under different stress conditions in order to reduce
the number of test escapes.
| cs.AR | this paper presents the effectiveness of various stress conditions mainly voltage and frequency on detecting the resistive shorts and open defects in deep submicron embedded memories in an industrial environment simulation studies on verylow voltage high voltage and atspeed testing show the need of the stress conditions for high quality products ie low defectpermillion dpm level which is driving the semiconductor market today the above test conditions have been validated to screen out bad devices on real silicon a testchip built on cmos 018 um technology ifa inductive fault analysis based simulation technique leads to an efficient fault coverage and dpm estimator which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes | [['this', 'paper', 'presents', 'the', 'effectiveness', 'of', 'various', 'stress', 'conditions', 'mainly', 'voltage', 'and', 'frequency', 'on', 'detecting', 'the', 'resistive', 'shorts', 'and', 'open', 'defects', 'in', 'deep', 'submicron', 'embedded', 'memories', 'in', 'an', 'industrial', 'environment', 'simulation', 'studies', 'on', 'verylow', 'voltage', 'high', 'voltage', 'and', 'atspeed', 'testing', 'show', 'the', 'need', 'of', 'the', 'stress', 'conditions', 'for', 'high', 'quality', 'products', 'ie', 'low', 'defectpermillion', 'dpm', 'level', 'which', 'is', 'driving', 'the', 'semiconductor', 'market', 'today', 'the', 'above', 'test', 'conditions', 'have', 'been', 'validated', 'to', 'screen', 'out', 'bad', 'devices', 'on', 'real', 'silicon', 'a', 'testchip', 'built', 'on', 'cmos', '018', 'um', 'technology', 'ifa', 'inductive', 'fault', 'analysis', 'based', 'simulation', 'technique', 'leads', 'to', 'an', 'efficient', 'fault', 'coverage', 'and', 'dpm', 'estimator', 'which', 'helps', 'the', 'customers', 'upfront', 'to', 'make', 'decisions', 'on', 'test', 'algorithm', 'implementations', 'under', 'different', 'stress', 'conditions', 'in', 'order', 'to', 'reduce', 'the', 'number', 'of', 'test', 'escapes']] | [-0.125724295139431, 0.055011911576637804, -0.04364756475311763, 0.006236423722593971, -0.04001751857521456, -0.16899909592410994, 0.05897359286678866, 0.4257738556535471, -0.19002506012717882, -0.3434863641695489, 0.14313774453272807, -0.23237262719074295, -0.08617071972952949, 0.2427631905052944, -0.11516529278707735, 0.09996060386580961, 0.06294140622314502, -0.0384013102323349, -0.012826107519065282, -0.25521083340226186, 0.22060423226110518, 0.11661987665773643, 0.4388264448175, 0.08568232459254518, 0.09301979514947604, -0.04809452463468049, -0.012469215769438989, -0.013364008513264476, -0.10524209251346452, 0.05870659678568325, 0.2722769875582012, 0.07210734062495508, 0.30112085598779637, -0.4831349103755894, -0.15920165382392173, 0.06747371021525136, 0.06884515551584107, 0.030758594212654446, -0.05403777397152716, -0.27323758844581864, 0.1382111570805252, -0.1674786452203989, -0.0703516710818226, -0.06988637189802137, -0.01934242912287277, 0.0025088712018692776, -0.2798562043546034, 0.002333101312008997, 0.011045436946756488, 0.07762470357637438, -0.06327418052179772, -0.11242045711962477, 0.005362516600779066, 0.10142361063816001, 0.012656255741603673, -0.019780061650043722, 0.2558592366172917, -0.12965262173268471, -0.10240837317403584, 0.31749250262325246, -0.007524734933025366, -0.1706319564947903, 0.23487188480886823, -0.09025349108491182, -0.10285315582794803, 0.13496358520055693, 0.23665433376288367, 0.058490694182673615, -0.20315983774055477, 0.048935774307455944, 0.062329420857759756, 0.1909256147836069, 0.09756973431453049, -0.006230557285663154, 0.21421585545416863, 0.24986461353384787, 0.06323888763371441, 0.14766396661215123, -0.11214853364730343, -0.03467443510742178, -0.2561773883219483, -0.1713830372447976, -0.14688419334087816, 0.03707577878819956, -0.1008904919740633, -0.21858685664529542, 0.3455054885486052, 0.2309985748189132, 0.11129351237434007, 0.03182638499013606, 0.3727333511979807, 0.07433509217604758, 0.08756037700980429, 0.044733929608824725, 0.19330722445045553, 0.07824479677670058, 0.14149619266760374, -0.20856408047164599, 0.101975409216706, -0.035055603577001465] |
710.4694 | Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum
Gates Using Multiple-Valued Logic and Group Theory | We propose an approach to optimally synthesize quantum circuits from
non-permutative quantum gates such as Controlled-Square-Root-of-Not (i.e.
Controlled-V). Our approach reduces the synthesis problem to multiple-valued
optimization and uses group theory. We devise a novel technique that transforms
the quantum logic synthesis problem from a multi-valued constrained
optimization problem to a group permutation problem. The transformation enables
us to utilize group theory to exploit the properties of the synthesis problem.
Assuming a cost of one for each two-qubit gate, we found all reversible
circuits with quantum costs of 4, 5, 6, etc, and give another algorithm to
realize these reversible circuits with quantum gates.
| cs.LO | we propose an approach to optimally synthesize quantum circuits from nonpermutative quantum gates such as controlledsquarerootofnot ie controlledv our approach reduces the synthesis problem to multiplevalued optimization and uses group theory we devise a novel technique that transforms the quantum logic synthesis problem from a multivalued constrained optimization problem to a group permutation problem the transformation enables us to utilize group theory to exploit the properties of the synthesis problem assuming a cost of one for each twoqubit gate we found all reversible circuits with quantum costs of 4 5 6 etc and give another algorithm to realize these reversible circuits with quantum gates | [['we', 'propose', 'an', 'approach', 'to', 'optimally', 'synthesize', 'quantum', 'circuits', 'from', 'nonpermutative', 'quantum', 'gates', 'such', 'as', 'controlledsquarerootofnot', 'ie', 'controlledv', 'our', 'approach', 'reduces', 'the', 'synthesis', 'problem', 'to', 'multiplevalued', 'optimization', 'and', 'uses', 'group', 'theory', 'we', 'devise', 'a', 'novel', 'technique', 'that', 'transforms', 'the', 'quantum', 'logic', 'synthesis', 'problem', 'from', 'a', 'multivalued', 'constrained', 'optimization', 'problem', 'to', 'a', 'group', 'permutation', 'problem', 'the', 'transformation', 'enables', 'us', 'to', 'utilize', 'group', 'theory', 'to', 'exploit', 'the', 'properties', 'of', 'the', 'synthesis', 'problem', 'assuming', 'a', 'cost', 'of', 'one', 'for', 'each', 'twoqubit', 'gate', 'we', 'found', 'all', 'reversible', 'circuits', 'with', 'quantum', 'costs', 'of', '4', '5', '6', 'etc', 'and', 'give', 'another', 'algorithm', 'to', 'realize', 'these', 'reversible', 'circuits', 'with', 'quantum', 'gates']] | [-0.09174699612947948, 0.06710515910084473, -0.07556130763773314, 0.014465861908141888, -0.07702025487635504, -0.22903295603635557, 0.11997348001208522, 0.40427274669648383, -0.3574952268516462, -0.33853126905274156, 0.062098034554818535, -0.229555287384702, -0.21444655319803632, 0.23612977062151128, -0.1070248688623656, 0.15501589802842514, -0.010815146753527955, -0.017405975664801458, -0.1204630918829364, -0.24734203671744348, 0.23415238314933673, -0.026315900991332953, 0.26748200593968197, -0.03394914170106252, 0.1494205156980338, 0.030704641500122698, 0.05808911058029123, -0.016492130435711027, -0.08121230432288047, 0.1757805533284851, 0.29994390012842476, 0.18100610435666406, 0.26506389631414967, -0.4688179758833904, -0.17523758647981666, 0.0980417100877008, 0.07116788132207505, 0.2053561503907629, -0.06292573244803969, -0.23640345434165178, 0.09133344734037369, -0.1620224698848438, -0.04838873453748723, -0.08318173017480648, -0.03171589714589109, -0.0744575437765532, -0.2606824544605379, -0.02191807318915523, 0.0605130233692334, 0.0049834055186924985, -0.00542520749492242, -0.06565436297415883, 0.08418701717620898, 0.12748440199842057, -0.11775878484488703, 0.019477690213962513, 0.15887867155491703, -0.0552033950647741, -0.23574382390977597, 0.3690188927530293, 0.014053606291246764, -0.2036521841004929, 0.12047977663585734, -0.013765715920895922, -0.18225421971075384, 0.08490139864015338, 0.1709252871326445, 0.1384817738469471, -0.1387918257866712, 0.12123998548429203, 0.0048875925039836, 0.24005202220424132, 0.005485060652170111, 0.04413042933789685, 0.14281474150187684, 0.14380371032794023, 0.1604096934555427, 0.23079378082069987, -0.009420947518710997, -0.09310312264635429, -0.2698998547286964, -0.18472255518039069, -0.14467289229494282, 0.09577409554199845, -0.03764890873200927, -0.19021994768477538, 0.3948561181679514, 0.17443648605223963, 0.14861819898200623, 0.1260054020174578, 0.2760334072598055, 0.1326097290524665, 0.10030830813590072, 0.06663282676691226, 0.119368002147359, 0.20145599533091574, 0.04400839200060742, -0.2580628634416772, 0.022315688664093614, 0.0823626912349616] |
710.4695 | SAT-Based Complete Don't-Care Computation for Network Optimization | This paper describes an improved approach to Boolean network optimization
using internal don't-cares. The improvements concern the type of don't-cares
computed, their scope, and the computation method. Instead of the traditionally
used compatible observability don't-cares (CODCs), we introduce and justify the
use of complete don't-cares (CDC). To ensure the robustness of the don't-care
computation for very large industrial networks, a optional windowing scheme is
implemented that computes substantial subsets of the CDCs in reasonable time.
Finally, we give a SAT-based don't-care computation algorithm that is more
efficient than BDD-based algorithms. Experimental results confirm that these
improvements work well in practice. Complete don't-cares allow for a reduction
in the number of literals compared to the CODCs. Windowing guarantees
robustness, even for very large benchmarks on which previous methods could not
be applied. SAT reduces the runtime and enhances robustness, making don't-cares
affordable for a variety of other Boolean methods applied to the network.
| cs.LO | this paper describes an improved approach to boolean network optimization using internal dontcares the improvements concern the type of dontcares computed their scope and the computation method instead of the traditionally used compatible observability dontcares codcs we introduce and justify the use of complete dontcares cdc to ensure the robustness of the dontcare computation for very large industrial networks a optional windowing scheme is implemented that computes substantial subsets of the cdcs in reasonable time finally we give a satbased dontcare computation algorithm that is more efficient than bddbased algorithms experimental results confirm that these improvements work well in practice complete dontcares allow for a reduction in the number of literals compared to the codcs windowing guarantees robustness even for very large benchmarks on which previous methods could not be applied sat reduces the runtime and enhances robustness making dontcares affordable for a variety of other boolean methods applied to the network | [['this', 'paper', 'describes', 'an', 'improved', 'approach', 'to', 'boolean', 'network', 'optimization', 'using', 'internal', 'dontcares', 'the', 'improvements', 'concern', 'the', 'type', 'of', 'dontcares', 'computed', 'their', 'scope', 'and', 'the', 'computation', 'method', 'instead', 'of', 'the', 'traditionally', 'used', 'compatible', 'observability', 'dontcares', 'codcs', 'we', 'introduce', 'and', 'justify', 'the', 'use', 'of', 'complete', 'dontcares', 'cdc', 'to', 'ensure', 'the', 'robustness', 'of', 'the', 'dontcare', 'computation', 'for', 'very', 'large', 'industrial', 'networks', 'a', 'optional', 'windowing', 'scheme', 'is', 'implemented', 'that', 'computes', 'substantial', 'subsets', 'of', 'the', 'cdcs', 'in', 'reasonable', 'time', 'finally', 'we', 'give', 'a', 'satbased', 'dontcare', 'computation', 'algorithm', 'that', 'is', 'more', 'efficient', 'than', 'bddbased', 'algorithms', 'experimental', 'results', 'confirm', 'that', 'these', 'improvements', 'work', 'well', 'in', 'practice', 'complete', 'dontcares', 'allow', 'for', 'a', 'reduction', 'in', 'the', 'number', 'of', 'literals', 'compared', 'to', 'the', 'codcs', 'windowing', 'guarantees', 'robustness', 'even', 'for', 'very', 'large', 'benchmarks', 'on', 'which', 'previous', 'methods', 'could', 'not', 'be', 'applied', 'sat', 'reduces', 'the', 'runtime', 'and', 'enhances', 'robustness', 'making', 'dontcares', 'affordable', 'for', 'a', 'variety', 'of', 'other', 'boolean', 'methods', 'applied', 'to', 'the', 'network']] | [-0.08034100610374784, -0.035585663237046296, -0.06367230826988816, 0.09412829264144723, -0.0921086234288911, -0.1417699588773151, 0.08627473948601012, 0.4039855903138717, -0.22843825920019298, -0.3171758579959472, 0.13186763965912784, -0.17575051095957558, -0.1406966273742728, 0.25918340203662715, -0.1343743239508088, 0.12482682629177967, 0.1272961112127329, -0.007570363176055253, -0.07458339170494582, -0.31681230147369205, 0.23776716185112795, 0.05717929881686966, 0.30897632919251916, 0.06533019230390588, 0.07193079319942626, -0.002931197916623205, -0.06600857527926564, 0.06998860116271922, -0.06459697615117573, 0.1598399281067153, 0.27722742771574604, 0.20868311424739658, 0.29900864952243866, -0.44994793869554994, -0.16623463632849356, 0.12512187037927408, 0.136928161031877, 0.13329514498900003, -0.016780383482594818, -0.25583289563655853, 0.1338355576992035, -0.2028066410931448, -0.08385290650495639, -0.1720107529560725, -0.010133182931070527, 0.003083262482153562, -0.30070583530701694, -0.008787556954969963, 0.058774400546681135, 0.04278262121602893, -0.016193630549435813, -0.13431517722085118, 0.036796946986578406, 0.10427508813949923, -0.00698644421606635, 0.0340342314230899, 0.1092156280639271, -0.10977432425289105, -0.16536220253134767, 0.36639388840645554, -0.048179638407600575, -0.21131325203925372, 0.18758727582792442, -0.028786962494874994, -0.17012478789314628, 0.12523846911266445, 0.18212529524229468, 0.11941243605688215, -0.11327990394706527, 0.07585932488436811, -0.015458632931113244, 0.18660049011620383, 0.044102653420219816, 0.03911779314900438, 0.08079660085495562, 0.20887178077052038, 0.09280428022146225, 0.14949918699567205, -0.04234885753287623, -0.09912595097286006, -0.2541784244325633, -0.14950797573042413, -0.16183578056283296, -0.03061622141074622, -0.12286993224144681, -0.16120637152033548, 0.3785258166298687, 0.22423053103809557, 0.14998975423475105, 0.13661667574895545, 0.3445427906140685, 0.07229197101046642, 0.10376659288847198, 0.0796914677383999, 0.1973921613721177, 0.09056067100415627, 0.11116876500037809, -0.20657399703438084, 0.11159914535470307, 0.040229141333450874] |
710.4696 | Avoiding closed timelike curves with a collapsing rotating null dust
shell | We present an idealised model of gravitational collapse, describing a
collapsing rotating cylindrical shell of null dust in flat space, with the
metric of a spinning cosmic string as the exterior. We find that the shell
bounces before closed timelike curves can be formed. Our results also suggest
slightly different definitions for the mass and angular momentum of the string.
| gr-qc | we present an idealised model of gravitational collapse describing a collapsing rotating cylindrical shell of null dust in flat space with the metric of a spinning cosmic string as the exterior we find that the shell bounces before closed timelike curves can be formed our results also suggest slightly different definitions for the mass and angular momentum of the string | [['we', 'present', 'an', 'idealised', 'model', 'of', 'gravitational', 'collapse', 'describing', 'a', 'collapsing', 'rotating', 'cylindrical', 'shell', 'of', 'null', 'dust', 'in', 'flat', 'space', 'with', 'the', 'metric', 'of', 'a', 'spinning', 'cosmic', 'string', 'as', 'the', 'exterior', 'we', 'find', 'that', 'the', 'shell', 'bounces', 'before', 'closed', 'timelike', 'curves', 'can', 'be', 'formed', 'our', 'results', 'also', 'suggest', 'slightly', 'different', 'definitions', 'for', 'the', 'mass', 'and', 'angular', 'momentum', 'of', 'the', 'string']] | [-0.14907755348831414, 0.16382341946615878, -0.11109768206564088, 0.11964755998924374, -0.08086346810062726, -0.06610392511356622, -0.039514724149679145, 0.3508349143899977, -0.16929990630596875, -0.25834983289823865, 0.03109061893968222, -0.21336401851537326, -0.04887598399848988, 0.16309368007738764, -0.022235325227181118, -0.011323517995576064, 0.055928053023914494, 0.018060622977403303, -0.14195906145420548, -0.2069487924532344, 0.42256294096199176, 0.09342968611357112, 0.20376034417034436, 0.0003980063134804368, 0.08927071036596317, -0.05316558889268587, -0.009591344185173512, 0.06396541245388411, -0.1901683844205157, 0.05611673848470673, 0.13812535751300553, 0.1540008907051136, 0.12847617169997344, -0.4933059118688107, -0.2510372030393531, 0.06785186150421699, 0.2034909594648828, 0.1661504805708925, -0.07115461100668957, -0.2761719207589825, 0.02401898221093385, -0.20198809408272306, -0.2449489385355264, -0.0014643379487097262, 0.07180323142868777, 0.007008211004237334, -0.17647770117036998, 0.08380288471962558, 0.0903196090211471, -0.029230478548076158, -0.157267953044114, -0.03507468787332376, -0.08506407609287028, 0.03409226713702083, 0.11718808143438461, 0.06776005423162132, 0.17490162471464524, -0.07737234911570946, -0.04721127727534622, 0.38390178124730784, -0.09998902642788986, -0.22271602982655167, 0.11372810027872522, -0.20777954946582516, -0.07776976563036442, 0.1459165031866481, 0.12232970134355128, 0.15314322290165971, -0.11058978644820551, 0.0884041231503943, -0.05727929730977242, 0.11180674072044591, 0.18776134761671226, -0.025854478178856274, 0.38797519424794397, 0.15356665734822553, -0.03463719063438475, 0.17078124589364355, -0.1496573702742656, -0.11370832089645168, -0.3879597056657076, -0.15808023945428432, -0.10432283218639592, 0.09427164156610766, -0.20000171966360844, -0.24625658633497854, 0.2862720209406689, 0.03187556238165901, 0.2111368232096235, 0.06516268282818298, 0.2801838495458166, 0.020595988920346524, 0.03520213801724215, 0.17813243699880937, 0.3032985851013412, 0.11572325358477732, 0.0956622786509494, -0.2199848236826559, -0.07080931269253293, 0.04277821545644353] |
710.4697 | Statistical Timing Based Optimization using Gate Sizing | The increased dominance of intra-die process variations has motivated the
field of Statistical Static Timing Analysis (SSTA) and has raised the need for
SSTA-based circuit optimization. In this paper, we propose a new sensitivity
based, statistical gate sizing method. Since brute-force computation of the
change in circuit delay distribution to gate size change is computationally
expensive, we propose an efficient and exact pruning algorithm. The pruning
algorithm is based on a novel theory of perturbation bounds which are shown to
decrease as they propagate through the circuit. This allows pruning of gate
sensitivities without complete propagation of their perturbations. We apply our
proposed optimization algorithm to ISCAS benchmark circuits and demonstrate the
accuracy and efficiency of the proposed method. Our results show an improvement
of up to 10.5% in the 99-percentile circuit delay for the same circuit area,
using the proposed statistical optimizer and a run time improvement of up to
56x compared to the brute-force approach.
| cs.AR | the increased dominance of intradie process variations has motivated the field of statistical static timing analysis ssta and has raised the need for sstabased circuit optimization in this paper we propose a new sensitivity based statistical gate sizing method since bruteforce computation of the change in circuit delay distribution to gate size change is computationally expensive we propose an efficient and exact pruning algorithm the pruning algorithm is based on a novel theory of perturbation bounds which are shown to decrease as they propagate through the circuit this allows pruning of gate sensitivities without complete propagation of their perturbations we apply our proposed optimization algorithm to iscas benchmark circuits and demonstrate the accuracy and efficiency of the proposed method our results show an improvement of up to 105 in the 99percentile circuit delay for the same circuit area using the proposed statistical optimizer and a run time improvement of up to 56x compared to the bruteforce approach | [['the', 'increased', 'dominance', 'of', 'intradie', 'process', 'variations', 'has', 'motivated', 'the', 'field', 'of', 'statistical', 'static', 'timing', 'analysis', 'ssta', 'and', 'has', 'raised', 'the', 'need', 'for', 'sstabased', 'circuit', 'optimization', 'in', 'this', 'paper', 'we', 'propose', 'a', 'new', 'sensitivity', 'based', 'statistical', 'gate', 'sizing', 'method', 'since', 'bruteforce', 'computation', 'of', 'the', 'change', 'in', 'circuit', 'delay', 'distribution', 'to', 'gate', 'size', 'change', 'is', 'computationally', 'expensive', 'we', 'propose', 'an', 'efficient', 'and', 'exact', 'pruning', 'algorithm', 'the', 'pruning', 'algorithm', 'is', 'based', 'on', 'a', 'novel', 'theory', 'of', 'perturbation', 'bounds', 'which', 'are', 'shown', 'to', 'decrease', 'as', 'they', 'propagate', 'through', 'the', 'circuit', 'this', 'allows', 'pruning', 'of', 'gate', 'sensitivities', 'without', 'complete', 'propagation', 'of', 'their', 'perturbations', 'we', 'apply', 'our', 'proposed', 'optimization', 'algorithm', 'to', 'iscas', 'benchmark', 'circuits', 'and', 'demonstrate', 'the', 'accuracy', 'and', 'efficiency', 'of', 'the', 'proposed', 'method', 'our', 'results', 'show', 'an', 'improvement', 'of', 'up', 'to', '105', 'in', 'the', '99percentile', 'circuit', 'delay', 'for', 'the', 'same', 'circuit', 'area', 'using', 'the', 'proposed', 'statistical', 'optimizer', 'and', 'a', 'run', 'time', 'improvement', 'of', 'up', 'to', '56x', 'compared', 'to', 'the', 'bruteforce', 'approach']] | [-0.10620828970961345, 0.0006254740294096265, -0.07972329589024235, 0.017841036821995327, -0.054199056276543575, -0.14327387423738353, 0.12829317493884304, 0.41170617882404237, -0.24069253980581248, -0.3874004603599428, 0.08834956020688299, -0.20708990833193272, -0.17568512284196913, 0.2385386866275463, -0.09921403196863315, 0.1425769094365661, 0.06817162461131328, -0.01158669503865304, -0.0894636254003211, -0.30316577018571217, 0.20623571446993957, 0.10577584772564277, 0.31175918012325254, 0.052762615533739135, 0.11834370161031747, -0.03362829380142563, -0.026955867267830613, 0.013795652871274135, -0.0765426669015803, 0.13983140922719975, 0.2089371339832062, 0.1761500680238589, 0.2781152262249599, -0.43742483549497346, -0.18468453924401435, 0.09431110064245084, 0.1491925402260204, 0.137532748707552, -0.042167015655673795, -0.2673819149956228, 0.11497867682513285, -0.17466734311930449, -0.05148818446383751, -0.1220434164997287, 0.004239839487316014, -0.008561472886229878, -0.2859250350383582, 0.03690581623609964, 0.04087621052205175, 0.013961455186030694, 0.014480138123080787, -0.10598142973038477, 0.07627567638002046, 0.09761252376710536, 0.013975042616003555, 0.03997927153174608, 0.1619896388419166, -0.09008715857219483, -0.18619934829290619, 0.32954438158323046, -0.06918317485334617, -0.18319913913350697, 0.12614917688528318, -0.04053046022199379, -0.10890896416075721, 0.16563353933055291, 0.21118661682665735, 0.12007361400249571, -0.1357827323531224, 0.06528678623310823, 0.03774004704137514, 0.2144534828930537, 0.050338786031881515, 0.00297195174090274, 0.09714927762299293, 0.25123645795370125, 0.12018016069014738, 0.18077523916409435, -0.094054371299972, -0.08613393085936157, -0.26983493828976696, -0.1438536243747569, -0.1761987796166682, 0.009809084596451034, -0.09781004244553503, -0.1711428589125197, 0.4268649549997569, 0.23854925129078813, 0.14617447406295445, 0.12729980745851727, 0.3367695530465284, 0.14064481892613936, 0.0718336639088252, 0.09577955303006117, 0.23023229228429398, 0.10259161059224567, 0.08795766146587473, -0.26974813127587854, 0.06796341052871537, 0.024143730108807614] |
710.4698 | Automated Synthesis of Assertion Monitors using Visual Specifications | Automated synthesis of monitors from high-level properties plays a
significant role in assertion-based verification. We present here a methodology
to synthesize assertion monitors from visual specifications given in CESC
(Clocked Event Sequence Chart). CESC is a visual language designed for
specifying system level interactions involving single and multiple clock
domains. It has well-defined graphical and textual syntax and formal semantics
based on synchronous language paradigm enabling formal analysis of
specifications. In this paper we provide an overview of CESC language with few
illustrative examples. The algorithm for automated synthesis of assertion
monitors from CESC specifications is described. A few examples from standard
bus protocols (OCP-IP and AMBA) are presented to demonstrate the application of
monitor synthesis algorithm.
| cs.LO | automated synthesis of monitors from highlevel properties plays a significant role in assertionbased verification we present here a methodology to synthesize assertion monitors from visual specifications given in cesc clocked event sequence chart cesc is a visual language designed for specifying system level interactions involving single and multiple clock domains it has welldefined graphical and textual syntax and formal semantics based on synchronous language paradigm enabling formal analysis of specifications in this paper we provide an overview of cesc language with few illustrative examples the algorithm for automated synthesis of assertion monitors from cesc specifications is described a few examples from standard bus protocols ocpip and amba are presented to demonstrate the application of monitor synthesis algorithm | [['automated', 'synthesis', 'of', 'monitors', 'from', 'highlevel', 'properties', 'plays', 'a', 'significant', 'role', 'in', 'assertionbased', 'verification', 'we', 'present', 'here', 'a', 'methodology', 'to', 'synthesize', 'assertion', 'monitors', 'from', 'visual', 'specifications', 'given', 'in', 'cesc', 'clocked', 'event', 'sequence', 'chart', 'cesc', 'is', 'a', 'visual', 'language', 'designed', 'for', 'specifying', 'system', 'level', 'interactions', 'involving', 'single', 'and', 'multiple', 'clock', 'domains', 'it', 'has', 'welldefined', 'graphical', 'and', 'textual', 'syntax', 'and', 'formal', 'semantics', 'based', 'on', 'synchronous', 'language', 'paradigm', 'enabling', 'formal', 'analysis', 'of', 'specifications', 'in', 'this', 'paper', 'we', 'provide', 'an', 'overview', 'of', 'cesc', 'language', 'with', 'few', 'illustrative', 'examples', 'the', 'algorithm', 'for', 'automated', 'synthesis', 'of', 'assertion', 'monitors', 'from', 'cesc', 'specifications', 'is', 'described', 'a', 'few', 'examples', 'from', 'standard', 'bus', 'protocols', 'ocpip', 'and', 'amba', 'are', 'presented', 'to', 'demonstrate', 'the', 'application', 'of', 'monitor', 'synthesis', 'algorithm']] | [-0.10765776277624135, -0.027349768221405422, -0.07318267791285099, 0.06460396883354907, -0.13617534370057222, -0.1818863567615185, 0.06455701188955071, 0.4402046204897864, -0.25433432410374796, -0.377032725959374, 0.09063925117290386, -0.23845520801842213, -0.13995100028716542, 0.25983277440135333, -0.12544817888932625, 0.09288698214543822, 0.09234754008377485, 0.029959039883296696, -0.03428241386929334, -0.1443110934894227, 0.25604006678572505, 0.016635573615625114, 0.2713219730368141, -0.026582797142227405, 0.12289088107806084, 0.0335493039054764, -0.04451306726269681, -0.05398220507877654, -0.06892102179599219, 0.13620745250955224, 0.3682937243118368, 0.3054869643629304, 0.2777276620357137, -0.4285699447681164, -0.1334274303226266, -0.00025411147588125336, 0.10370171548405277, 0.12221868208419845, -0.10165128220727764, -0.3282474595732216, 0.07767091457057616, -0.23375345978801587, -0.045801020171172144, -0.11026016694236675, 0.006608405624163048, 0.04042330261014787, -0.23332547991042796, -0.07226612907031486, 0.12410602998791327, 0.19875729174738557, -0.041343594399473535, -0.047327345009323146, 0.00274165521239348, 0.15823307319881458, -0.05738689301631831, 0.012553031288603208, 0.16602541614677116, -0.05912684458348065, -0.17165500277267962, 0.3433427709508045, -0.039155043414713625, -0.16080041289136843, 0.18494786741914518, -0.0014405947395375576, -0.2350172544548545, 0.08216593455089706, 0.1737867606530801, 0.10770419015547116, -0.2073637431423212, 0.08115688437835067, 0.02935683832439626, 0.2815222770481467, 0.05076908962479953, 0.020402142135747547, 0.23585261656212267, 0.2936079660269978, -0.012704886965240865, 0.16772313178356352, -0.010364414519903347, -0.08977674586088236, -0.3140721540212639, -0.12914792063910963, -0.084053114466048, -0.03078105629136754, -0.01213559902078424, -0.17382812688372035, 0.41504049192760784, 0.21256364564860947, 0.08348878606318913, 0.0963369692140861, 0.34464549579143783, 0.05710184176709374, 0.06220032646449219, 0.02469285994222195, 0.12103657541266674, 0.037385049115481045, 0.15276904008752698, -0.12334156603901647, 0.12479492868216516, 0.05800158380338087] |
710.4699 | Characterization of quantum angular-momentum fluctuations via principal
components | We elaborate an approach to quantum fluctuations of angular momentum based on
the diagonalization of the covariance matrix in two versions: real symmetric
and complex Hermitian. At difference with previous approaches this is SU(2)
invariant and avoids any difficulty caused by nontrivial commutators.
Meaningful uncertainty relations are derived which are nontrivial even for
vanishing mean angular momentum. We apply this approach to some relevant
states.
| quant-ph | we elaborate an approach to quantum fluctuations of angular momentum based on the diagonalization of the covariance matrix in two versions real symmetric and complex hermitian at difference with previous approaches this is su2 invariant and avoids any difficulty caused by nontrivial commutators meaningful uncertainty relations are derived which are nontrivial even for vanishing mean angular momentum we apply this approach to some relevant states | [['we', 'elaborate', 'an', 'approach', 'to', 'quantum', 'fluctuations', 'of', 'angular', 'momentum', 'based', 'on', 'the', 'diagonalization', 'of', 'the', 'covariance', 'matrix', 'in', 'two', 'versions', 'real', 'symmetric', 'and', 'complex', 'hermitian', 'at', 'difference', 'with', 'previous', 'approaches', 'this', 'is', 'su2', 'invariant', 'and', 'avoids', 'any', 'difficulty', 'caused', 'by', 'nontrivial', 'commutators', 'meaningful', 'uncertainty', 'relations', 'are', 'derived', 'which', 'are', 'nontrivial', 'even', 'for', 'vanishing', 'mean', 'angular', 'momentum', 'we', 'apply', 'this', 'approach', 'to', 'some', 'relevant', 'states']] | [-0.15395789074783142, 0.1555251536122971, -0.07618893647136596, 0.12863670900428237, -0.1045385107684594, -0.10794035187707497, -0.013952612536601149, 0.3827944498222608, -0.2283184743557985, -0.27775596827985005, 0.07402494332502381, -0.2793555513740732, -0.15440777832498917, 0.1652988209747351, -0.06839385622969041, 0.09484831424286733, 0.053887599516803254, 0.029608026641206098, -0.1821454291536401, -0.21666555903278864, 0.41713751462789683, -0.0025652874923812654, 0.2626788526630172, 0.05338952185836836, 0.12749899425185643, 0.03512941416926109, -0.07285545363019293, 0.006118875383757628, -0.09816238539150128, 0.13946270385237697, 0.23375539547548843, 0.03909077127822316, 0.21715469463513448, -0.3868044345997847, -0.15877415742725134, 0.14076996250794485, 0.12080045288983876, 0.14591900024813814, -0.012523711825577686, -0.31240937205461355, 0.06650595541756887, -0.17235039809288888, -0.13031856286554383, -0.1587684646141357, 0.013807854801416396, -0.05266329324446045, -0.2717497818243618, 0.15028132741482786, 0.0724688639291204, 0.05698831491888716, -0.033861032028037766, -0.1588198163904823, 0.011052005544591409, 0.10046030866125455, 0.05222324222111358, -0.01478772178435555, 0.10173514931677625, -0.06046124380081892, -0.11489313353354541, 0.3388264434376302, -0.009056193438860086, -0.3086489396026501, 0.1347231375769927, -0.13098271565350633, -0.1440148647946234, 0.10183036185156268, 0.12032947508761516, 0.11297952441068795, -0.11175519377709581, 0.11527802929676209, -0.027906204151132933, 0.130284525688666, 0.0410230123069106, 0.07768708766939549, 0.1885813971838126, 0.03169930206181911, 0.0718614697169799, 0.08613479272820629, -0.04214669143279585, -0.18272898419258687, -0.2998501617318163, -0.12603612386603624, -0.23246539214339393, 0.10192420282759346, -0.11514261339817984, -0.13651975396160895, 0.3782552441725364, 0.15984024803798932, 0.22795797794197614, 0.0716568807229543, 0.3195562340319157, 0.1498166985451602, 0.06058366856036278, 0.08196798950577011, 0.19645060284573657, 0.17398341728302721, 0.05044415404733557, -0.2435450904429532, -0.013434673920990183, 0.09514196403324604] |
710.47 | A Decompilation Approach to Partitioning Software for
Microprocessor/FPGA Platforms | In this paper, we present a software compilation approach for
microprocessor/FPGA platforms that partitions a software binary onto custom
hardware implemented in the FPGA. Our approach imposes less restrictions on
software tool flow than previous compiler approaches, allowing software
designers to use any software language and compiler. Our approach uses a
back-end partitioning tool that utilizes decompilation techniques to recover
important high-level information, resulting in performance comparable to
high-level compiler-based approaches.
| cs.SE | in this paper we present a software compilation approach for microprocessorfpga platforms that partitions a software binary onto custom hardware implemented in the fpga our approach imposes less restrictions on software tool flow than previous compiler approaches allowing software designers to use any software language and compiler our approach uses a backend partitioning tool that utilizes decompilation techniques to recover important highlevel information resulting in performance comparable to highlevel compilerbased approaches | [['in', 'this', 'paper', 'we', 'present', 'a', 'software', 'compilation', 'approach', 'for', 'microprocessorfpga', 'platforms', 'that', 'partitions', 'a', 'software', 'binary', 'onto', 'custom', 'hardware', 'implemented', 'in', 'the', 'fpga', 'our', 'approach', 'imposes', 'less', 'restrictions', 'on', 'software', 'tool', 'flow', 'than', 'previous', 'compiler', 'approaches', 'allowing', 'software', 'designers', 'to', 'use', 'any', 'software', 'language', 'and', 'compiler', 'our', 'approach', 'uses', 'a', 'backend', 'partitioning', 'tool', 'that', 'utilizes', 'decompilation', 'techniques', 'to', 'recover', 'important', 'highlevel', 'information', 'resulting', 'in', 'performance', 'comparable', 'to', 'highlevel', 'compilerbased', 'approaches']] | [-0.07126034393108317, -0.0942051101475954, -0.14826477788987436, 0.031615811970550564, -0.19822337604793056, -0.238988891995645, 0.02773794865601563, 0.44930956682988576, -0.22571359639987348, -0.3819404595132385, 0.05918034315940791, -0.19034421048127115, -0.15193857630448682, 0.3257043269063745, -0.1098037962003478, 0.13336684411790753, 0.1752877043027963, -0.05723247110311474, -0.0862181400002945, -0.23244752770156732, 0.23221593840446855, 0.07441388391224402, 0.3245528797619045, 0.017128122531409773, 0.0668097562821848, 0.0010604757216892073, -0.03539783953955131, -0.07578905276688082, -0.08682043152366532, 0.20952300220461828, 0.37835948978816825, 0.32269696462234215, 0.32411068896097794, -0.46367770082184245, -0.13577598345998143, -0.022172125109604427, 0.13567744667109635, 0.08914802987128496, -0.021703118772711603, -0.2737770801493233, 0.09637762670006071, -0.27708715037442744, -0.02980379895972354, -0.13525388951280287, -0.07575286529692156, -0.049280925391108864, -0.2244995846529491, -0.11778255747631192, 0.0923965593633641, 0.07564291503014309, 0.024286951271018813, -0.11821239407706474, 0.027553273983565826, 0.1395005424107824, -0.04268954311098371, 0.11284707093312006, 0.21166056826311563, -0.03428825623954513, -0.16921860322555793, 0.3583852718717286, -0.012486402132656492, -0.23264355968151773, 0.2388255450741521, 0.09111191248521208, -0.26100346303677985, 0.09376098327338696, 0.24457385214045643, 0.06302796860358545, -0.21122964841446706, 0.11040316607187768, 0.08609015479949968, 0.30944113345716945, 0.02328813531785272, -0.007781234004401735, 0.17269605297395693, 0.25096514004482223, 0.041127833684108085, 0.1958664542463209, 0.004920418138083603, -0.05219212606815355, -0.21586635373532773, -0.14884011233225464, -0.13714394480921327, -0.04703567628083485, -0.072311153640164, -0.19163889874305043, 0.36780388791646274, 0.2820910132589883, 0.013362526128600751, 0.11099997738243214, 0.5031113767198154, -0.022169126866252293, 0.19509273203355926, 0.1784496249165386, 0.059819899467817905, 0.0006478486316544669, 0.18224216098897159, -0.14096006927180238, 0.09494090530622218, 0.05649106181060363] |
710.4701 | A Prediction Packetizing Scheme for Reducing Channel Traffic in
Transaction-Level Hardware/Software Co-Emulation | This paper presents a scheme for efficient channel usage between simulator
and accelerator where the accelerator models some RTL sub-blocks in the
accelerator-based hardware/software co-simulation while the simulator runs
transaction-level model of the remaining part of the whole chip being verified.
With conventional simulation accelerator, evaluations of simulator and
accelerator alternate at every valid simulation time, which results in poor
simulation performance due to startup overhead of simulator-accelerator channel
access. The startup overhead can be reduced by merging multiple transactions on
the channel into a single burst traffic. We propose a predictive packetizing
scheme for reducing channel traffic by merging as many transactions into a
burst traffic as possible based on 'prediction and rollback.' Under ideal
condition with 100% prediction accuracy, the proposed method shows a
performance gain of 1500% compared to the conventional one.
| cs.PF | this paper presents a scheme for efficient channel usage between simulator and accelerator where the accelerator models some rtl subblocks in the acceleratorbased hardwaresoftware cosimulation while the simulator runs transactionlevel model of the remaining part of the whole chip being verified with conventional simulation accelerator evaluations of simulator and accelerator alternate at every valid simulation time which results in poor simulation performance due to startup overhead of simulatoraccelerator channel access the startup overhead can be reduced by merging multiple transactions on the channel into a single burst traffic we propose a predictive packetizing scheme for reducing channel traffic by merging as many transactions into a burst traffic as possible based on prediction and rollback under ideal condition with 100 prediction accuracy the proposed method shows a performance gain of 1500 compared to the conventional one | [['this', 'paper', 'presents', 'a', 'scheme', 'for', 'efficient', 'channel', 'usage', 'between', 'simulator', 'and', 'accelerator', 'where', 'the', 'accelerator', 'models', 'some', 'rtl', 'subblocks', 'in', 'the', 'acceleratorbased', 'hardwaresoftware', 'cosimulation', 'while', 'the', 'simulator', 'runs', 'transactionlevel', 'model', 'of', 'the', 'remaining', 'part', 'of', 'the', 'whole', 'chip', 'being', 'verified', 'with', 'conventional', 'simulation', 'accelerator', 'evaluations', 'of', 'simulator', 'and', 'accelerator', 'alternate', 'at', 'every', 'valid', 'simulation', 'time', 'which', 'results', 'in', 'poor', 'simulation', 'performance', 'due', 'to', 'startup', 'overhead', 'of', 'simulatoraccelerator', 'channel', 'access', 'the', 'startup', 'overhead', 'can', 'be', 'reduced', 'by', 'merging', 'multiple', 'transactions', 'on', 'the', 'channel', 'into', 'a', 'single', 'burst', 'traffic', 'we', 'propose', 'a', 'predictive', 'packetizing', 'scheme', 'for', 'reducing', 'channel', 'traffic', 'by', 'merging', 'as', 'many', 'transactions', 'into', 'a', 'burst', 'traffic', 'as', 'possible', 'based', 'on', 'prediction', 'and', 'rollback', 'under', 'ideal', 'condition', 'with', '100', 'prediction', 'accuracy', 'the', 'proposed', 'method', 'shows', 'a', 'performance', 'gain', 'of', '1500', 'compared', 'to', 'the', 'conventional', 'one']] | [-0.15212744535332112, 0.04535093509655138, -0.06831583653968808, 0.003520876788044054, -0.026301995609515814, -0.22182407071533844, 0.10412093687231856, 0.37564467512687344, -0.22866592029305666, -0.3495421814627217, 0.11943959209009308, -0.2281633157815252, -0.07680269647424662, 0.2696773302338709, -0.06125705344497429, 0.1222628663518095, 0.15771462687088134, -0.0007343955646107968, -0.04035405831847382, -0.27733832904088657, 0.2102820888742286, 0.1485386913098724, 0.3599427743688842, 0.041238656165550946, 0.12799289653469859, -0.00011483561667732727, -0.029173509613873393, -0.05231952938372427, -0.024945092404347013, 0.05107360873966569, 0.28048921009662753, 0.15523821026562973, 0.2937932390075429, -0.4784565000797891, -0.22091797668542854, 0.04408774792419789, 0.12885629387110248, 0.043054911364885255, -0.06881958234502017, -0.27985098458742513, 0.10236232034525924, -0.2723156144156268, -0.041240865508220474, -0.012050249893918522, -0.06684092540097863, 0.004645814783468535, -0.31351345944869563, 0.028270056592020438, -0.008825957396984996, 0.03696036837378839, 7.063096137087148e-05, -0.08203470768911161, 0.030470546863665033, 0.11486859247788675, 0.005493551337762379, 0.02683080591723547, 0.14619927860654652, -0.10432632451463855, -0.144822067759679, 0.3958892706305461, -0.02278626136502769, -0.17831573372311132, 0.17062157162122035, -0.0569562171340773, -0.07914664072187659, 0.14849448934962442, 0.23563060728453197, 0.009534155813402924, -0.1621719857229662, 0.007393368928171554, 0.007045726263825607, 0.18894115575375667, 0.038319413963341174, 0.020487700974134573, 0.15151336722258002, 0.30173812716275006, 0.05384753511726674, 0.14006434704607731, -0.09543138691154134, -0.09909755268346, -0.28150854766398625, -0.14884550594444618, -0.14466794952837736, -0.01805719927205403, -0.052434299898852905, -0.0961903015333683, 0.41750157292409495, 0.18089658849350967, 0.13950708177276797, 0.10163038955122597, 0.43503701503395587, 0.03244845628129192, 0.10407390334832489, 0.14612688183000214, 0.14259772516084185, 0.018029856912203525, 0.14025368764331297, -0.2173058599394683, 0.10269932157388027, 0.004639683958297049] |
710.4702 | A Register Allocation Algorithm in the Presence of Scalar Replacement
for Fine-Grain Configurable Architectures | The aggressive application of scalar replacement to array references
substantially reduces the number of memory operations at the expense of a
possibly very large number of registers. In this paper we describe a register
allocation algorithm that assigns registers to scalar replaced array references
along the critical paths of a computation, in many cases exploiting the
opportunity for concurrent memory accesses. Experimental results, for a set of
image/signal processing code kernels, reveal that the proposed algorithm leads
to a substantial reduction of the number of execution cycles for the
corresponding hardware implementation on a contemporary
Field-Programmable-Gate-Array (FPGA) when compared to other greedy allocation
algorithms, in some cases, using even fewer number of registers.
| cs.PL | the aggressive application of scalar replacement to array references substantially reduces the number of memory operations at the expense of a possibly very large number of registers in this paper we describe a register allocation algorithm that assigns registers to scalar replaced array references along the critical paths of a computation in many cases exploiting the opportunity for concurrent memory accesses experimental results for a set of imagesignal processing code kernels reveal that the proposed algorithm leads to a substantial reduction of the number of execution cycles for the corresponding hardware implementation on a contemporary fieldprogrammablegatearray fpga when compared to other greedy allocation algorithms in some cases using even fewer number of registers | [['the', 'aggressive', 'application', 'of', 'scalar', 'replacement', 'to', 'array', 'references', 'substantially', 'reduces', 'the', 'number', 'of', 'memory', 'operations', 'at', 'the', 'expense', 'of', 'a', 'possibly', 'very', 'large', 'number', 'of', 'registers', 'in', 'this', 'paper', 'we', 'describe', 'a', 'register', 'allocation', 'algorithm', 'that', 'assigns', 'registers', 'to', 'scalar', 'replaced', 'array', 'references', 'along', 'the', 'critical', 'paths', 'of', 'a', 'computation', 'in', 'many', 'cases', 'exploiting', 'the', 'opportunity', 'for', 'concurrent', 'memory', 'accesses', 'experimental', 'results', 'for', 'a', 'set', 'of', 'imagesignal', 'processing', 'code', 'kernels', 'reveal', 'that', 'the', 'proposed', 'algorithm', 'leads', 'to', 'a', 'substantial', 'reduction', 'of', 'the', 'number', 'of', 'execution', 'cycles', 'for', 'the', 'corresponding', 'hardware', 'implementation', 'on', 'a', 'contemporary', 'fieldprogrammablegatearray', 'fpga', 'when', 'compared', 'to', 'other', 'greedy', 'allocation', 'algorithms', 'in', 'some', 'cases', 'using', 'even', 'fewer', 'number', 'of', 'registers']] | [-0.19251917602377944, 0.05995318358951148, -0.01815715389134961, 0.021776116036302744, -0.07809329483175784, -0.1909376753527405, 0.1254928790897663, 0.3728337704669684, -0.24290956797111513, -0.3832092219797362, 0.10975259487687643, -0.24136983108889712, -0.10388672358489462, 0.25585460143962074, -0.09699132690496169, 0.049943473065338494, 0.14047887736316106, 0.047532813438530344, -0.032512354948266875, -0.29079089875572856, 0.21043917499426762, 0.09154263219846014, 0.2591034931829199, -0.02976367114544181, 0.07893829959877101, 0.005867546632154179, -0.047407386365063885, 0.01907014995461915, -0.0019997777174337117, 0.13136337406883417, 0.27781644435890485, 0.17875743098141225, 0.310377648233303, -0.4744966844362872, -0.1358862017514184, 0.11429315970079708, 0.1296797726317891, 0.15450915060189022, -0.04329225292375278, -0.20417517088312057, 0.0980229819667459, -0.1877907368304607, -0.05237597496514874, -0.08593724013712745, 0.014786831045057625, 0.02272132661892101, -0.2794745417465622, -0.0470932277135684, 0.03095164270052919, 0.04202077462936619, -0.010793143434316985, -0.15291709859073827, 0.05664590861007517, 0.0866166288066909, 0.0038447880651801825, 0.0359684930174678, 0.12256201902761989, -0.13998580280167516, -0.16130763435545045, 0.3546980670154361, 0.0033000796143564264, -0.18939651663614704, 0.1734084604956609, -0.0661449463493357, -0.17352999531431124, 0.1670573566308511, 0.18877065733457649, 0.0513771927050714, -0.09057290115600024, 0.08171043589702874, -0.012073104643994676, 0.2086667158042214, 0.11868248009081331, 0.09275219154993206, 0.1257243911324102, 0.17963363194264406, 0.1170957174425504, 0.2149267327471794, -0.0507604146176683, -0.10385378467279745, -0.2800957886252685, -0.1774988866948531, -0.19175226820724284, 0.004573981098863962, -0.12484678140442286, -0.15806888044712, 0.3894214045223115, 0.19218964348380854, 0.15521658850567682, 0.1201559336072283, 0.3510870187393656, 0.036623741457593235, 0.1463745402371777, 0.13899170599013036, 0.07439841067623222, 0.07848558927902818, 0.14885087260128266, -0.2463287517644598, 0.05737930824813832, 0.028118448694710554] |
710.4703 | A Way Memoization Technique for Reducing Power Consumption of Caches in
Application Specific Integrated Processors | This paper presents a technique for eliminating redundant cache-tag and
cache-way accesses to reduce power consumption. The basic idea is to keep a
small number of Most Recently Used (MRU) addresses in a Memory Address Buffer
(MAB) and to omit redundant tag and way accesses when there is a MAB-hit. Since
the approach keeps only tag and set-index values in the MAB, the energy and
area overheads are relatively small even for a MAB with a large number of
entries. Furthermore, the approach does not sacrifice the performance. In other
words, neither the cycle time nor the number of executed cycles increases. The
proposed technique has been applied to Fujitsu VLIW processor (FR-V) and its
power saving has been estimated using NanoSim. Experiments for 32kB 2-way set
associative caches show the power consumption of I-cache and D-cache can be
reduced by 40% and 50%, respectively.
| cs.AR | this paper presents a technique for eliminating redundant cachetag and cacheway accesses to reduce power consumption the basic idea is to keep a small number of most recently used mru addresses in a memory address buffer mab and to omit redundant tag and way accesses when there is a mabhit since the approach keeps only tag and setindex values in the mab the energy and area overheads are relatively small even for a mab with a large number of entries furthermore the approach does not sacrifice the performance in other words neither the cycle time nor the number of executed cycles increases the proposed technique has been applied to fujitsu vliw processor frv and its power saving has been estimated using nanosim experiments for 32kb 2way set associative caches show the power consumption of icache and dcache can be reduced by 40 and 50 respectively | [['this', 'paper', 'presents', 'a', 'technique', 'for', 'eliminating', 'redundant', 'cachetag', 'and', 'cacheway', 'accesses', 'to', 'reduce', 'power', 'consumption', 'the', 'basic', 'idea', 'is', 'to', 'keep', 'a', 'small', 'number', 'of', 'most', 'recently', 'used', 'mru', 'addresses', 'in', 'a', 'memory', 'address', 'buffer', 'mab', 'and', 'to', 'omit', 'redundant', 'tag', 'and', 'way', 'accesses', 'when', 'there', 'is', 'a', 'mabhit', 'since', 'the', 'approach', 'keeps', 'only', 'tag', 'and', 'setindex', 'values', 'in', 'the', 'mab', 'the', 'energy', 'and', 'area', 'overheads', 'are', 'relatively', 'small', 'even', 'for', 'a', 'mab', 'with', 'a', 'large', 'number', 'of', 'entries', 'furthermore', 'the', 'approach', 'does', 'not', 'sacrifice', 'the', 'performance', 'in', 'other', 'words', 'neither', 'the', 'cycle', 'time', 'nor', 'the', 'number', 'of', 'executed', 'cycles', 'increases', 'the', 'proposed', 'technique', 'has', 'been', 'applied', 'to', 'fujitsu', 'vliw', 'processor', 'frv', 'and', 'its', 'power', 'saving', 'has', 'been', 'estimated', 'using', 'nanosim', 'experiments', 'for', '32kb', '2way', 'set', 'associative', 'caches', 'show', 'the', 'power', 'consumption', 'of', 'icache', 'and', 'dcache', 'can', 'be', 'reduced', 'by', '40', 'and', '50', 'respectively']] | [-0.15888450246817176, 0.08714740240500997, -0.01386253005636019, 0.02372579121088231, -0.0934770178940633, -0.17421768696901077, 0.1341596224650646, 0.3703440275529157, -0.28526854577923083, -0.3801963127899807, 0.11603377089056227, -0.26249180636976077, -0.08008635048484565, 0.19741898750847517, -0.158589457033499, 0.06980022394566111, 0.07165048448065214, 0.07944287775772745, -0.0036905722480024333, -0.2877795351601705, 0.22671375503389002, 0.09708144340961092, 0.273060751938855, 0.03840780695495398, 0.09726089638011678, -0.01795412356918003, -0.05028345590740766, 0.044889692139923165, -0.010232839939197984, 0.0876738234706547, 0.2712130129414921, 0.16697861914576936, 0.32759662901145825, -0.4530750672076491, -0.1825299053452909, 0.13176968447405144, 0.12625862870270899, 0.07740743308681557, -0.04482648343495701, -0.1859768147283382, 0.18346304934222143, -0.22917707379151514, -0.034524999368274446, -0.09717599580408601, 0.024204609692906557, 0.014714208910700636, -0.2717022297421362, 0.009093897105059654, 0.0418451402194636, 0.01999100562239039, 0.00015969430788190684, -0.11819791298931585, 0.03891381698802276, 0.13258937510018123, 0.04114531827213216, 0.025946619294489316, 0.13698306967220877, -0.11101062011574328, -0.10402223329140764, 0.3721050021873004, -0.01452017763454089, -0.20715446929713927, 0.15778665251665466, -0.07562848926645002, -0.1375637311276227, 0.1456476324170396, 0.1645072990677495, 0.08580246079119219, -0.14440549013385823, 0.10210623869974422, 0.0032865843850363426, 0.24522729180213335, 0.10197974870528054, 0.053931719262449856, 0.12241272843760047, 0.19850622255024433, 0.07950094294315879, 0.14024946103134003, -0.10439961083044393, -0.07270904513501117, -0.18826496301799256, -0.15515691571045612, -0.18693098455053364, -0.0069833546594304935, -0.05451497245630362, -0.10138702723265126, 0.3748630565748064, 0.14567213744073565, 0.19486352031969506, 0.11026492628498354, 0.355994915748285, 0.09269017050900256, 0.16534611900029975, 0.16125998934528427, 0.15437461546473746, 0.05630780012259071, 0.13155557609338692, -0.2088434262626359, 0.09942249558947008, 0.008760209083962052] |
710.4704 | Resource Sharing and Pipelining in Coarse-Grained Reconfigurable
Architecture for Domain-Specific Optimization | Coarse-grained reconfigurable architectures aim to achieve both goals of high
performance and flexibility. However, existing reconfigurable array
architectures require many resources without considering the specific
application domain. Functional resources that take long latency and/or large
area can be pipelined and/or shared among the processing elements. Therefore
the hardware cost and the delay can be effectively reduced without any
performance degradation for some application domains. We suggest such
reconfigurable array architecture template and design space exploration flow
for domain-specific optimization. Experimental results show that our approach
is much more efficient both in performance and area compared to existing
reconfigurable architectures.
| cs.AR | coarsegrained reconfigurable architectures aim to achieve both goals of high performance and flexibility however existing reconfigurable array architectures require many resources without considering the specific application domain functional resources that take long latency andor large area can be pipelined andor shared among the processing elements therefore the hardware cost and the delay can be effectively reduced without any performance degradation for some application domains we suggest such reconfigurable array architecture template and design space exploration flow for domainspecific optimization experimental results show that our approach is much more efficient both in performance and area compared to existing reconfigurable architectures | [['coarsegrained', 'reconfigurable', 'architectures', 'aim', 'to', 'achieve', 'both', 'goals', 'of', 'high', 'performance', 'and', 'flexibility', 'however', 'existing', 'reconfigurable', 'array', 'architectures', 'require', 'many', 'resources', 'without', 'considering', 'the', 'specific', 'application', 'domain', 'functional', 'resources', 'that', 'take', 'long', 'latency', 'andor', 'large', 'area', 'can', 'be', 'pipelined', 'andor', 'shared', 'among', 'the', 'processing', 'elements', 'therefore', 'the', 'hardware', 'cost', 'and', 'the', 'delay', 'can', 'be', 'effectively', 'reduced', 'without', 'any', 'performance', 'degradation', 'for', 'some', 'application', 'domains', 'we', 'suggest', 'such', 'reconfigurable', 'array', 'architecture', 'template', 'and', 'design', 'space', 'exploration', 'flow', 'for', 'domainspecific', 'optimization', 'experimental', 'results', 'show', 'that', 'our', 'approach', 'is', 'much', 'more', 'efficient', 'both', 'in', 'performance', 'and', 'area', 'compared', 'to', 'existing', 'reconfigurable', 'architectures']] | [-0.16827600263882278, 0.009977793513863074, -0.009328416122989071, 0.02021941516402582, -0.1471914461439927, -0.20210255616617323, 0.028971784541176424, 0.5170034018505101, -0.28579336002168026, -0.3961239917241413, 0.13219773916014932, -0.17236140150002985, -0.1803040354526743, 0.25797276955681164, -0.12618566879701584, 0.11393327330888221, 0.15454489271147082, -0.06569203565066511, -0.06448108781742948, -0.26012928890196063, 0.19172782241719577, 0.08349796250989341, 0.3793245540329754, 0.04939370210555316, 0.061519619477254275, -0.04836735774697078, 0.017653689686811032, 0.015516647986416244, -0.02873253827456578, 0.18859178974114435, 0.35633782980342704, 0.1949198530008546, 0.2835370267581458, -0.5013988873535635, -0.26020200990817766, 0.07771744020753588, 0.14492645973546636, 0.0743655877939256, -0.06440333810807182, -0.2540940095193101, 0.08961888406169366, -0.2182391071692109, -0.04971166945655237, -0.1614738558724786, -0.053194610058621625, 0.046409131652167576, -0.26069027458251726, -0.058616877214823185, 0.02940639131937665, 0.02290544153727365, -0.01944295743555583, -0.15986014051701536, 0.04097171191530622, 0.15231133917007933, -0.06691765374823878, 0.035738004912443534, 0.18403429907248026, -0.14351905300517123, -0.14193002186301681, 0.35317365343522544, 0.002157089761411301, -0.25998680394453305, 0.22742589193424492, -0.025318658292161848, -0.15048194979552668, 0.13315099759986906, 0.2438750055834952, 0.040431884136239084, -0.1697446026020881, 0.056000992975602244, 0.10768916770919329, 0.24792085269070935, 0.06563700020614296, 0.13868081482183753, 0.20265991208755008, 0.28182327626931547, 0.1093611611503722, 0.16907128926855747, -0.04613136790335329, -0.09897747822811431, -0.1964699043798251, -0.16828960252718794, -0.19915552502686176, -0.043098962799918775, -0.11839825943091208, -0.07091800575003479, 0.3390020385074119, 0.18194338788217843, 0.13325297976420683, 0.1436809219250625, 0.4103418878006815, -0.005133432593676403, 0.19095846831403446, 0.11796156890370478, 0.14062642937466135, -0.033629735842384774, 0.15298744195112676, -0.22126218853894658, 0.07259168209169399, -0.07435381785975863] |
710.4705 | A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores
using Dynamic Hardware/Software Partitioning | Field programmable gate arrays (FPGAs) provide designers with the ability to
quickly create hardware circuits. Increases in FPGA configurable logic capacity
and decreasing FPGA costs have enabled designers to more readily incorporate
FPGAs in their designs. FPGA vendors have begun providing configurable soft
processor cores that can be synthesized onto their FPGA products. While FPGAs
with soft processor cores provide designers with increased flexibility, such
processors typically have degraded performance and energy consumption compared
to hard-core processors. Previously, we proposed warp processing, a technique
capable of optimizing a software application by dynamically and transparently
re-implementing critical software kernels as custom circuits in on-chip
configurable logic. In this paper, we study the potential of a MicroBlaze
soft-core based warp processing system to eliminate the performance and energy
overhead of a soft-core processor compared to a hard-core processor. We
demonstrate that the soft-core based warp processor achieves average speedups
of 5.8 and energy reductions of 57% compared to the soft core alone. Our data
shows that a soft-core based warp processor yields performance and energy
consumption competitive with existing hard-core processors, thus expanding the
usefulness of soft processor cores on FPGAs to a broader range of applications.
| cs.AR | field programmable gate arrays fpgas provide designers with the ability to quickly create hardware circuits increases in fpga configurable logic capacity and decreasing fpga costs have enabled designers to more readily incorporate fpgas in their designs fpga vendors have begun providing configurable soft processor cores that can be synthesized onto their fpga products while fpgas with soft processor cores provide designers with increased flexibility such processors typically have degraded performance and energy consumption compared to hardcore processors previously we proposed warp processing a technique capable of optimizing a software application by dynamically and transparently reimplementing critical software kernels as custom circuits in onchip configurable logic in this paper we study the potential of a microblaze softcore based warp processing system to eliminate the performance and energy overhead of a softcore processor compared to a hardcore processor we demonstrate that the softcore based warp processor achieves average speedups of 58 and energy reductions of 57 compared to the soft core alone our data shows that a softcore based warp processor yields performance and energy consumption competitive with existing hardcore processors thus expanding the usefulness of soft processor cores on fpgas to a broader range of applications | [['field', 'programmable', 'gate', 'arrays', 'fpgas', 'provide', 'designers', 'with', 'the', 'ability', 'to', 'quickly', 'create', 'hardware', 'circuits', 'increases', 'in', 'fpga', 'configurable', 'logic', 'capacity', 'and', 'decreasing', 'fpga', 'costs', 'have', 'enabled', 'designers', 'to', 'more', 'readily', 'incorporate', 'fpgas', 'in', 'their', 'designs', 'fpga', 'vendors', 'have', 'begun', 'providing', 'configurable', 'soft', 'processor', 'cores', 'that', 'can', 'be', 'synthesized', 'onto', 'their', 'fpga', 'products', 'while', 'fpgas', 'with', 'soft', 'processor', 'cores', 'provide', 'designers', 'with', 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710.4706 | An Infrastructure to Functionally Test Designs Generated by Compilers
Targeting FPGAs | This paper presents an infrastructure to test the functionality of the
specific architectures output by a high-level compiler targeting dynamically
reconfigurable hardware. It results in a suitable scheme to verify the
architectures generated by the compiler, each time new optimization techniques
are included or changes in the compiler are performed. We believe this kind of
infrastructure is important to verify, by functional simulation, further
research techniques, as far as compilation to Field-Programmable Gate Array
(FPGA) platforms is concerned.
| cs.AR | this paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware it results in a suitable scheme to verify the architectures generated by the compiler each time new optimization techniques are included or changes in the compiler are performed we believe this kind of infrastructure is important to verify by functional simulation further research techniques as far as compilation to fieldprogrammable gate array fpga platforms is concerned | [['this', 'paper', 'presents', 'an', 'infrastructure', 'to', 'test', 'the', 'functionality', 'of', 'the', 'specific', 'architectures', 'output', 'by', 'a', 'highlevel', 'compiler', 'targeting', 'dynamically', 'reconfigurable', 'hardware', 'it', 'results', 'in', 'a', 'suitable', 'scheme', 'to', 'verify', 'the', 'architectures', 'generated', 'by', 'the', 'compiler', 'each', 'time', 'new', 'optimization', 'techniques', 'are', 'included', 'or', 'changes', 'in', 'the', 'compiler', 'are', 'performed', 'we', 'believe', 'this', 'kind', 'of', 'infrastructure', 'is', 'important', 'to', 'verify', 'by', 'functional', 'simulation', 'further', 'research', 'techniques', 'as', 'far', 'as', 'compilation', 'to', 'fieldprogrammable', 'gate', 'array', 'fpga', 'platforms', 'is', 'concerned']] | [-0.17552288031826416, 0.005470956187846008, -0.03979007209627292, 0.015193655633200437, -0.108506652001196, -0.21887883874707115, 0.046746229159441266, 0.4557658991752527, -0.2801707773111187, -0.35983228927048355, 0.11101666532564335, -0.167210109018458, -0.17783856017288202, 0.2902720320510129, -0.08347645034201634, 0.13330031729613742, 0.10492458205538778, -0.05406741640315606, -0.048951938008077636, -0.2660049861058211, 0.2513588998102559, 0.12688379663114363, 0.3136056347224766, 0.03643975258231736, 0.045053275099071935, -0.07489051723566192, -0.018937100381709825, -0.05585186321956989, -0.06145931999437893, 0.13259779787497394, 0.3451651220615858, 0.24130110095183438, 0.3474626399528904, -0.4804664189234758, -0.14346408129980168, -0.013110774658763638, 0.10269568286215265, 0.09453378030313896, -0.05971196813819309, -0.3099583912258729, 0.12803489775008833, -0.21540798806848052, -0.10182880932011475, -0.12458299470540041, -0.047827940446157485, 0.03814553815680437, -0.22888077395514417, -0.10925030002060036, 0.028343754975746076, 0.07345647411420941, 0.016686181836307813, -0.09641148324291675, 0.03376870105663935, 0.11845166727196044, -0.019731500000955585, 0.06637558491843848, 0.21041472316480792, -0.07432909765376304, -0.18394474998916474, 0.33688865649776584, 0.01121633934477965, -0.19922973710345104, 0.1694706394456518, 0.02317392882795479, -0.19560708079893047, 0.07475946829296075, 0.21725623110213724, 0.0752774816698944, -0.22898438849892372, 0.09183320443695173, 0.0474768238954055, 0.25041896286301124, 0.007685648647542947, 0.007187084748576849, 0.1872907954877099, 0.24317518511834818, 0.04687812857520886, 0.24013877406011885, -0.007094409143274578, -0.04909353655351039, -0.29739245146704024, -0.16230469901496783, -0.18183402102201796, -0.039039895517560534, -0.006592820577609997, -0.14275140394098484, 0.3887118650467388, 0.1967563656942683, 0.07990110762274036, 0.05319318718232889, 0.43716555977096927, 0.04215110804682645, 0.1956464840630547, 0.0871408540301789, 0.13939154667791742, 0.034492443491800286, 0.17818608020360654, -0.17762522510169312, 0.07122484567457249, -0.0011432790973534186] |
710.4707 | Energy- and Performance-Driven NoC Communication Architecture Synthesis
Using a Decomposition Approach | In this paper, we present a methodology for customized communication
architecture synthesis that matches the communication requirements of the
target application. This is an important problem, particularly for
network-based implementations of complex applications. Our approach is based on
using frequently encountered generic communication primitives as an alphabet
capable of characterizing any given communication pattern. The proposed
algorithm searches through the entire design space for a solution that
minimizes the system total energy consumption, while satisfying the other
design constraints. Compared to the standard mesh architecture, the customized
architecture generated by the newly proposed approach shows about 36%
throughput increase and 51% reduction in the energy required to encrypt 128
bits of data with a standard encryption algorithm.
| cs.AR | in this paper we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application this is an important problem particularly for networkbased implementations of complex applications our approach is based on using frequently encountered generic communication primitives as an alphabet capable of characterizing any given communication pattern the proposed algorithm searches through the entire design space for a solution that minimizes the system total energy consumption while satisfying the other design constraints compared to the standard mesh architecture the customized architecture generated by the newly proposed approach shows about 36 throughput increase and 51 reduction in the energy required to encrypt 128 bits of data with a standard encryption algorithm | [['in', 'this', 'paper', 'we', 'present', 'a', 'methodology', 'for', 'customized', 'communication', 'architecture', 'synthesis', 'that', 'matches', 'the', 'communication', 'requirements', 'of', 'the', 'target', 'application', 'this', 'is', 'an', 'important', 'problem', 'particularly', 'for', 'networkbased', 'implementations', 'of', 'complex', 'applications', 'our', 'approach', 'is', 'based', 'on', 'using', 'frequently', 'encountered', 'generic', 'communication', 'primitives', 'as', 'an', 'alphabet', 'capable', 'of', 'characterizing', 'any', 'given', 'communication', 'pattern', 'the', 'proposed', 'algorithm', 'searches', 'through', 'the', 'entire', 'design', 'space', 'for', 'a', 'solution', 'that', 'minimizes', 'the', 'system', 'total', 'energy', 'consumption', 'while', 'satisfying', 'the', 'other', 'design', 'constraints', 'compared', 'to', 'the', 'standard', 'mesh', 'architecture', 'the', 'customized', 'architecture', 'generated', 'by', 'the', 'newly', 'proposed', 'approach', 'shows', 'about', '36', 'throughput', 'increase', 'and', '51', 'reduction', 'in', 'the', 'energy', 'required', 'to', 'encrypt', '128', 'bits', 'of', 'data', 'with', 'a', 'standard', 'encryption', 'algorithm']] | [-0.14464212556441242, -0.009205027982646313, -0.042686772252170324, 0.026020481337247908, -0.05841145030835755, -0.17549455785152748, 0.0757385429669506, 0.35841756941288966, -0.26717063453462386, -0.3784111632814265, 0.1066408945256486, -0.219244081992656, -0.18676186639529008, 0.2354022950077286, -0.10972801895223112, 0.12157402896027789, 0.09440999129452766, 0.0243308671300387, -0.04632604750008601, -0.2621103529499955, 0.26694108136560424, 0.09889945420874362, 0.3492142917492833, 0.0018063653300269546, 0.10438328633248074, 0.031146076841192305, -0.031431296951750405, -0.05553824642029368, -0.0810205838191532, 0.16640057979036185, 0.26062497172433025, 0.23016519060867846, 0.27892916633261955, -0.4049084051551982, -0.21376470330322528, 0.08230085571447754, 0.14613842533933175, 0.07468940674040753, -0.09655942709750345, -0.25502595281562745, 0.125787743466755, -0.1905507939035853, -0.07263630335657005, -0.04044438947119519, -0.011829188348263757, 0.023003437468268644, -0.30393590128574616, -0.02867828206055694, 0.019369306445766527, 0.032269103261522755, -0.06158502531659781, -0.09360607565703014, 0.026750248428991336, 0.10701098909171727, -0.04505718925283251, 0.058823630231647536, 0.1378247042019398, -0.10242741279160747, -0.15385028624182773, 0.40514295211491674, -0.03521139303453139, -0.2061996676473536, 0.14315771525845122, 0.007382187383392682, -0.1461586974039833, 0.15732176827951375, 0.2144123856853853, 0.07985527535629833, -0.1788301571773795, 0.0723542135510331, 0.003472905844832078, 0.23994289099987054, 0.03754237877268694, 0.06902637934853506, 0.13214299191211343, 0.2613949991332797, 0.09566793308601293, 0.1512665813952947, -0.09551477997213538, -0.09841141582299502, -0.2728736319889625, -0.1717795583829443, -0.20278603423776853, -0.040041614510914966, -0.09680063488809133, -0.10077714959844056, 0.37913060987081665, 0.20110118022968626, 0.15122415569539255, 0.11421879879636769, 0.395921130799967, 0.06369851296369591, 0.12791714168543744, 0.13506993303736115, 0.15554479401335758, 0.03068226967484523, 0.13698252185614, -0.201261107949142, 0.07988373275734803, 0.016669521209759973] |
710.4708 | Discovery potential of the LHC for extended gauge symmetries | Many models of physics beyond the Standard Model are based on extended gauge
symmetries and predict the existence of new heavy particles, often at the TeV
scale. Such particles include heavy W and Z bosons, doubly charged higgses,
heavy majorana neutrinos, leptoquarks and heavy fermions. The discovery
potential of the LHC, which will start in 2008, for various particles predicted
in extended gauge theories will be described in this paper.
| hep-ex | many models of physics beyond the standard model are based on extended gauge symmetries and predict the existence of new heavy particles often at the tev scale such particles include heavy w and z bosons doubly charged higgses heavy majorana neutrinos leptoquarks and heavy fermions the discovery potential of the lhc which will start in 2008 for various particles predicted in extended gauge theories will be described in this paper | [['many', 'models', 'of', 'physics', 'beyond', 'the', 'standard', 'model', 'are', 'based', 'on', 'extended', 'gauge', 'symmetries', 'and', 'predict', 'the', 'existence', 'of', 'new', 'heavy', 'particles', 'often', 'at', 'the', 'tev', 'scale', 'such', 'particles', 'include', 'heavy', 'w', 'and', 'z', 'bosons', 'doubly', 'charged', 'higgses', 'heavy', 'majorana', 'neutrinos', 'leptoquarks', 'and', 'heavy', 'fermions', 'the', 'discovery', 'potential', 'of', 'the', 'lhc', 'which', 'will', 'start', 'in', '2008', 'for', 'various', 'particles', 'predicted', 'in', 'extended', 'gauge', 'theories', 'will', 'be', 'described', 'in', 'this', 'paper']] | [-0.05319480491203389, 0.3797621210438332, -0.039157402029793176, 0.19850745429118563, -0.03578354279909815, -0.22790658269410155, -0.009221667462095086, 0.27524512859859634, -0.20828780942995634, -0.3257143236430628, 0.007212780005232032, -0.3093834591231176, -0.0011853563665811505, 0.07486944348617856, 0.05331856547854841, 0.060261559366647684, 0.06493912444316915, 0.003023663562323366, -0.03837338076638324, -0.28456084217344013, 0.27068014186806977, 0.05368928603295769, 0.17507909962109158, 0.08803205905881312, 0.02682343251737101, 0.02986353209375271, -0.04653219689082887, -0.0950634244297232, -0.05850655350035855, 0.08092510331688182, 0.1605450508341164, 0.014019708674667137, 0.13034663200378419, -0.4159486891435725, -0.19260579303705266, 0.1661330277898482, 0.21046183054401937, 0.12004228113718064, -0.15108671491200637, -0.38244575082457494, 0.077951278497598, -0.22438891028453198, -0.1898531686947016, -0.04395452632036592, -0.06096678466669151, -0.057648811170033044, -0.28340142478368113, 0.06537470038913723, -0.03240967847939048, 0.023027929331042935, 0.0062405327002384835, -0.17654717443677198, -0.04617538304633594, -0.041446738430698, 0.16686862235240238, -0.050898394899974976, 0.14907892746185616, -0.21779114410746842, -0.20930696141107807, 0.4417142564089902, -0.09819842572989208, -0.17391824887267182, 0.2752061959389331, -0.12776571587393326, -0.2092340962495655, 0.09817411418605064, 0.29009901722893117, 0.09316538634177829, -0.2091890058214111, 0.21663114172832657, -0.06891277016007474, 0.11157727612049452, 0.031000739901459642, 0.08220233528741769, 0.33134040401450227, 0.18223694836986917, -0.008690418623154983, -0.009027980761935136, -0.054943640270669544, -0.07257363834817494, -0.4228135514339166, -0.17689081880796168, -0.09781458183590855, 0.019194253144918808, -0.03631951132992981, -0.10318395572581461, 0.4163903394447906, 0.16365258741259042, 0.19754395365182842, -0.019185920869598964, 0.15983895364749645, 0.0513771931906896, 0.08021474571100302, 0.04762987668759056, 0.3168738707367863, 0.11370318462806088, 0.13395055368143532, -0.15733373050710986, -0.07346520592857685, 0.11143203993061823] |
710.4709 | Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? | This special session adresses the problems that designers face when
implementing analog and digital circuits in nanometer technologies. An
introductory embedded tutorial will give an overview of the design problems at
hand : the leakage power and process variability and their implications for
digital circuits and memories, and the reducing supply voltages, the design
productivity and signal integrity problems for embedded analog blocks. Next, a
panel of experts from both industrial semiconductor houses and design
companies, EDA vendors and research institutes will present and discuss with
the audience their opinions on whether the design road ends at marker "65nm" or
not.
| cs.AR | this special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies an introductory embedded tutorial will give an overview of the design problems at hand the leakage power and process variability and their implications for digital circuits and memories and the reducing supply voltages the design productivity and signal integrity problems for embedded analog blocks next a panel of experts from both industrial semiconductor houses and design companies eda vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker 65nm or not | [['this', 'special', 'session', 'adresses', 'the', 'problems', 'that', 'designers', 'face', 'when', 'implementing', 'analog', 'and', 'digital', 'circuits', 'in', 'nanometer', 'technologies', 'an', 'introductory', 'embedded', 'tutorial', 'will', 'give', 'an', 'overview', 'of', 'the', 'design', 'problems', 'at', 'hand', 'the', 'leakage', 'power', 'and', 'process', 'variability', 'and', 'their', 'implications', 'for', 'digital', 'circuits', 'and', 'memories', 'and', 'the', 'reducing', 'supply', 'voltages', 'the', 'design', 'productivity', 'and', 'signal', 'integrity', 'problems', 'for', 'embedded', 'analog', 'blocks', 'next', 'a', 'panel', 'of', 'experts', 'from', 'both', 'industrial', 'semiconductor', 'houses', 'and', 'design', 'companies', 'eda', 'vendors', 'and', 'research', 'institutes', 'will', 'present', 'and', 'discuss', 'with', 'the', 'audience', 'their', 'opinions', 'on', 'whether', 'the', 'design', 'road', 'ends', 'at', 'marker', '65nm', 'or', 'not']] | [-0.09683134540915489, 0.0553345347152208, -0.0009691943088546395, 0.01963658518574448, -0.12027383871376514, -0.21059786196332425, 0.05081560532096773, 0.40719287275802346, -0.2422109719645232, -0.3238820652291179, 0.2222476051293779, -0.30068959689931946, -0.15406407857546583, 0.26033745568012817, -0.13969614676199854, 0.03784733823034912, 0.045962511759717016, -0.03042390357935801, -0.013175603926647454, -0.2780491029471159, 0.24063106924295424, 0.09711625418625772, 0.35781526943668723, 0.07355180988553911, 0.08262547896243631, -0.01720239807968028, -0.02773615508340299, -0.04883342201821506, -0.09890945797124004, 0.15211807276587933, 0.39590557157993317, 0.1856528074434027, 0.3554172066273168, -0.5057456165552139, -0.12349752606358379, 0.07618019503875985, 0.09313787543680518, 0.0634081835951656, -0.11163255133549682, -0.2885187345556915, 0.04684752237983048, -0.1725109676271677, -0.08949291680939496, 0.009179748077876866, 0.007093678936362266, 0.026802130956202746, -0.20367462845984846, -0.09722652086056768, 0.05294820431619882, 0.12128599409013986, -0.00701623123139143, -0.14843115364201367, 0.039501891820691526, 0.20235978753917153, -0.03390241746121319, -0.04250426492188126, 0.2208182137273252, -0.17389158342033625, -0.1939433315768838, 0.35001403918489815, 0.06630555706564337, -0.13176706355880013, 0.153369114844827, -0.04339753438718617, -0.10814093253575266, 0.03211345502058975, 0.2774515682645142, -0.002061768784187734, -0.19359915051449206, 0.052035437891609033, 0.10233070206828415, 0.22166878536110743, 0.07956312238704413, 0.04360263483133167, 0.282950379177928, 0.23050988936563954, 0.06434755730908365, 0.14206009423127397, -0.009883921263972298, -0.05373535662889481, -0.2715244119684212, -0.17074199873022736, -0.11600919103249907, 0.028647948671277845, -0.04204353978726431, -0.167056285913568, 0.39299966448917983, 0.16918894078815355, 0.06643124737776816, 0.048105879854410886, 0.3834901721589267, 0.017785834446549416, 0.08125908734742553, 0.061339204269315814, 0.14598413359373807, 0.06983118222095072, 0.22416160945314914, -0.14644670778652652, 0.0835416347393766, -0.03789506792556494] |
710.471 | HEBS: Histogram Equalization for Backlight Scaling | In this paper, a method is proposed for finding a pixel transformation
function that maximizes backlight dimming while maintaining a pre-specified
image distortion level for a liquid crystal display. This is achieved by
finding a pixel transformation function, which maps the original image
histogram to a new histogram with lower dynamic range. Next the contrast of the
transformed image is enhanced so as to compensate for brightness loss that
would arise from backlight dimming. The proposed approach relies on an accurate
definition of the image distortion which takes into account both the pixel
value differences and a model of the human visual system and is amenable to
highly efficient hardware realization. Experimental results show that the
histogram equalization for backlight scaling method results in about 45% power
saving with an effective distortion rate of 5% and 65% power saving for a 20%
distortion rate. This is significantly higher power savings compared to
previously reported backlight dimming approaches.
| cs.OH | in this paper a method is proposed for finding a pixel transformation function that maximizes backlight dimming while maintaining a prespecified image distortion level for a liquid crystal display this is achieved by finding a pixel transformation function which maps the original image histogram to a new histogram with lower dynamic range next the contrast of the transformed image is enhanced so as to compensate for brightness loss that would arise from backlight dimming the proposed approach relies on an accurate definition of the image distortion which takes into account both the pixel value differences and a model of the human visual system and is amenable to highly efficient hardware realization experimental results show that the histogram equalization for backlight scaling method results in about 45 power saving with an effective distortion rate of 5 and 65 power saving for a 20 distortion rate this is significantly higher power savings compared to previously reported backlight dimming approaches | [['in', 'this', 'paper', 'a', 'method', 'is', 'proposed', 'for', 'finding', 'a', 'pixel', 'transformation', 'function', 'that', 'maximizes', 'backlight', 'dimming', 'while', 'maintaining', 'a', 'prespecified', 'image', 'distortion', 'level', 'for', 'a', 'liquid', 'crystal', 'display', 'this', 'is', 'achieved', 'by', 'finding', 'a', 'pixel', 'transformation', 'function', 'which', 'maps', 'the', 'original', 'image', 'histogram', 'to', 'a', 'new', 'histogram', 'with', 'lower', 'dynamic', 'range', 'next', 'the', 'contrast', 'of', 'the', 'transformed', 'image', 'is', 'enhanced', 'so', 'as', 'to', 'compensate', 'for', 'brightness', 'loss', 'that', 'would', 'arise', 'from', 'backlight', 'dimming', 'the', 'proposed', 'approach', 'relies', 'on', 'an', 'accurate', 'definition', 'of', 'the', 'image', 'distortion', 'which', 'takes', 'into', 'account', 'both', 'the', 'pixel', 'value', 'differences', 'and', 'a', 'model', 'of', 'the', 'human', 'visual', 'system', 'and', 'is', 'amenable', 'to', 'highly', 'efficient', 'hardware', 'realization', 'experimental', 'results', 'show', 'that', 'the', 'histogram', 'equalization', 'for', 'backlight', 'scaling', 'method', 'results', 'in', 'about', '45', 'power', 'saving', 'with', 'an', 'effective', 'distortion', 'rate', 'of', '5', 'and', '65', 'power', 'saving', 'for', 'a', '20', 'distortion', 'rate', 'this', 'is', 'significantly', 'higher', 'power', 'savings', 'compared', 'to', 'previously', 'reported', 'backlight', 'dimming', 'approaches']] | [-0.06933569441591005, 0.03267997097995898, -0.08793148313423584, 0.04331509177098466, -0.06104208219345588, -0.13427643975017556, 0.061372556878627534, 0.4107515316480284, -0.24546873618761125, -0.3540077955598474, 0.08229127762524803, -0.273645195585029, -0.15292514117054973, 0.22094866179543768, -0.1319424820995102, 0.07449926991181768, 0.056136553240999296, 0.008371122190313544, -0.09850927431782956, -0.24721160879622622, 0.22107131128454474, 0.12448595850698792, 0.3440090341101976, 0.02179479547687302, 0.14762504771277665, -0.017851393107787532, -0.02912134127869348, 0.017155561857162768, -0.0788586443300032, 0.1264803291440817, 0.23964536278048873, 0.12487143863906051, 0.26855422765206377, -0.3340948661196099, -0.24808819820825603, 0.053549557170907786, 0.1338715945566251, 0.08602618903313188, -0.09978149952974977, -0.2452196657040696, 0.12022351486471951, -0.15949673863101133, -0.03273258181763398, -0.03842465662705908, 0.008111514340920053, -0.0402860092953853, -0.32869390349769906, 0.09110452593996592, 0.08132958015320217, 0.048907363971185155, -0.08542084722975447, -0.10706352110089035, 0.010937397169530582, 0.11570025093046724, -0.004562648859284343, 0.12440178232289002, 0.15770509750522957, -0.1458051598966003, -0.07808433267937463, 0.3943850073227837, -0.053878027576490475, -0.1650117307465381, 0.11142927062828212, -0.11109677881038019, -0.0853227835792194, 0.2249960197835781, 0.16631141980586478, 0.04573835413991978, -0.14008261696405852, -0.014489241016681668, 0.01840252847748862, 0.23221174702285582, 0.07463835951557775, 0.037658118183137315, 0.18620475460211658, 0.1879233763946938, 0.1136769737431388, 0.16256745775366666, -0.15801407213939744, -0.04384663112010736, -0.242774108261653, -0.13939455810963594, -0.17249647864202855, -0.02398232382182388, -0.13894888054207635, -0.13927076235235591, 0.3973227689979942, 0.16076259256880374, 0.23102173225799943, 0.11117102171792678, 0.3505623661023179, 0.14265406648346643, 0.13393435668560622, 0.03943826074142507, 0.22005399805345352, 0.03662170365802754, 0.0994604095967878, -0.1960132440187298, 0.05931945119400147, 0.049093832586636875] |
710.4711 | FPGA Architecture for Multi-Style Asynchronous Logic | This paper presents a novel FPGA architecture for implementing various styles
of asynchronous logic. The main objective is to break the dependency between
the FPGA architecture dedicated to asynchronous logic and the logic style. The
innovative aspects of the architecture are described. Moreover the structure is
well suited to be rebuilt and adapted to fit with further asynchronous logic
evolutions thanks to the architecture genericity. A full-adder was implemented
in different styles of logic to show the architecture flexibility.
| cs.AR | this paper presents a novel fpga architecture for implementing various styles of asynchronous logic the main objective is to break the dependency between the fpga architecture dedicated to asynchronous logic and the logic style the innovative aspects of the architecture are described moreover the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions thanks to the architecture genericity a fulladder was implemented in different styles of logic to show the architecture flexibility | [['this', 'paper', 'presents', 'a', 'novel', 'fpga', 'architecture', 'for', 'implementing', 'various', 'styles', 'of', 'asynchronous', 'logic', 'the', 'main', 'objective', 'is', 'to', 'break', 'the', 'dependency', 'between', 'the', 'fpga', 'architecture', 'dedicated', 'to', 'asynchronous', 'logic', 'and', 'the', 'logic', 'style', 'the', 'innovative', 'aspects', 'of', 'the', 'architecture', 'are', 'described', 'moreover', 'the', 'structure', 'is', 'well', 'suited', 'to', 'be', 'rebuilt', 'and', 'adapted', 'to', 'fit', 'with', 'further', 'asynchronous', 'logic', 'evolutions', 'thanks', 'to', 'the', 'architecture', 'genericity', 'a', 'fulladder', 'was', 'implemented', 'in', 'different', 'styles', 'of', 'logic', 'to', 'show', 'the', 'architecture', 'flexibility']] | [-0.13367330432645505, -0.026547740741125956, -0.09141278798585828, 0.07175574296808365, -0.15727551628045644, -0.21619488761017594, -0.008027116625121783, 0.4601894265300111, -0.3095249853839603, -0.36231659211312667, 0.051246922231821604, -0.12231062381245385, -0.16855725301783295, 0.1837946652682333, -0.16009563334946392, 0.08297356566461393, 0.025100909833666644, -0.01881835917069848, -0.06773730820005087, -0.23945536758880354, 0.2462343994433744, 0.0660856796452139, 0.3247478706408528, 0.004870005052159482, 0.1206711778237449, -0.019616392379202232, 0.031376105131982246, -0.031118686947547183, -0.003968629154930764, 0.1700155812056287, 0.33342690651800155, 0.22576217956935304, 0.27577077984350107, -0.46900741109931016, -0.11308014779528484, 0.00225419695548053, 0.09364291938033568, 0.07999744141309321, 0.0009978091509281835, -0.3140145491667186, 0.10839231479677218, -0.22947994056098822, -0.061473321004570286, -0.10987700584427088, -0.0039842767122236986, 0.07050051973967612, -0.2495206507560915, -0.08945745553915636, 0.1545227144541266, 0.05033831069646757, -0.01104959798976779, -0.07551022982696377, 0.03652438627632594, 0.1103162631934768, -0.06262242809362427, 0.05090929632652787, 0.13928477342323034, -0.022558124735951424, -0.19669430721786957, 0.3037265075924747, -0.00694339341613688, -0.19420633840380544, 0.1650718542028077, -0.021101623136974588, -0.18329153047827415, 0.03816718496735903, 0.16597882474336442, 0.05010240830008023, -0.20711430065596145, 0.08317746670743159, 0.06508828100712993, 0.25103519479758873, 0.04899167909015772, 0.061003476499190815, 0.2050944353583493, 0.3160608306621449, -0.008993888966432667, 0.22804923686699918, -0.015882426724014687, -0.12732798552517838, -0.25731727575199514, -0.140226651442862, -0.10731049160225482, -0.0804369520275158, -0.02111961212137396, -0.1398190659930623, 0.45874877804536607, 0.20351154084871464, 0.12366781183341637, 0.14630030425666254, 0.40639444942810116, 0.0491938836507122, 0.16779001009992406, 0.07603854186762171, 0.15524208673004863, 0.10048165546221396, 0.2200444072154881, -0.19977591239811876, 0.1120087682340247, 0.0273044934832267] |
710.4712 | An Accurate SER Estimation Method Based on Propagation Probability | In this paper, we present an accurate but very fast soft error rate (SER)
estimation technique for digital circuits based on error propagation
probability (EPP) computation. Experiments results and comparison of the
results with the random simulation technique show that our proposed method is
on average within 6% of the random simulation method and four to five orders of
magnitude faster.
| cs.AR | in this paper we present an accurate but very fast soft error rate ser estimation technique for digital circuits based on error propagation probability epp computation experiments results and comparison of the results with the random simulation technique show that our proposed method is on average within 6 of the random simulation method and four to five orders of magnitude faster | [['in', 'this', 'paper', 'we', 'present', 'an', 'accurate', 'but', 'very', 'fast', 'soft', 'error', 'rate', 'ser', 'estimation', 'technique', 'for', 'digital', 'circuits', 'based', 'on', 'error', 'propagation', 'probability', 'epp', 'computation', 'experiments', 'results', 'and', 'comparison', 'of', 'the', 'results', 'with', 'the', 'random', 'simulation', 'technique', 'show', 'that', 'our', 'proposed', 'method', 'is', 'on', 'average', 'within', '6', 'of', 'the', 'random', 'simulation', 'method', 'and', 'four', 'to', 'five', 'orders', 'of', 'magnitude', 'faster']] | [-0.08457902291804918, 0.012166191192322838, -0.06859293589979167, 0.013578613874594086, 0.030858014282755187, -0.09926140146543745, 0.09555333154848547, 0.4355498529115661, -0.1691107840628409, -0.3470689646258462, 0.13396695253752233, -0.2465679267818322, -0.211128547543385, 0.3291422877094296, -0.05110943403245774, 0.10330059745761215, 0.10800163411214704, 0.020647242970642497, -0.09231367522133056, -0.32285846162159915, 0.20897042516191475, 0.08756703787223725, 0.3485478568196175, 0.005820507030995166, 0.1135123512768721, 0.01342939813411413, -0.08850171204778504, 0.012689090471287242, -0.11148567063045463, 0.15210712907194604, 0.17541840122859986, 0.12218380856831543, 0.2715175177474491, -0.40627414403391665, -0.18073170606169056, 0.044735939012932, 0.16327519073593813, 0.1416854782518549, -0.08956521749878149, -0.25898785650974415, 0.13092970244823116, -0.1912991857064552, -0.05953986997731396, -0.09143264422223704, -0.011287582633619914, 0.024166625115226527, -0.31472706590153154, 0.11405208890925574, 0.04058545271362193, 0.03247801768669828, 0.0036715848302682403, -0.14784918366702365, 0.10470324697079839, 0.08366913872114459, 0.01854490917405022, 0.05510759375775691, 0.1047372813489227, -0.07726439279809472, -0.17953134534239282, 0.30885765417937006, -0.08991295003072648, -0.187456750875858, 0.19201673628747096, -0.11405036571105469, -0.10544217324464536, 0.1873970384419453, 0.21635861774204207, 0.14787906553351976, -0.13381918457138245, -0.023240158389719417, 0.01502490935266995, 0.22473139804406245, 0.004691416748845187, 0.03806256412024625, 0.07334539361420225, 0.21710774053621, 0.06888602499956967, 0.10818137371240825, -0.1627654089271778, -0.09849311906050463, -0.27815202799182936, -0.1239749199773288, -0.1959845508586188, -0.01568831369799913, -0.1377408209931464, -0.1376094238252425, 0.38992055458948016, 0.2323024813391146, 0.13260710633314046, 0.14765143186831084, 0.3729393627555644, 0.09124946819625979, 0.012071499631541674, 0.11001507481025746, 0.2269924040578428, 0.10310850730623866, 0.05529341805482008, -0.21212149894658905, 0.05515636958670421, 0.08611222001204848] |
710.4713 | Improving the Process-Variation Tolerance of Digital Circuits Using Gate
Sizing and Statistical Techniques | A new approach for enhancing the process-variation tolerance of digital
circuits is described. We extend recent advances in statistical timing analysis
into an optimization framework. Our objective is to reduce the performance
variance of a technology-mapped circuit where delays across elements are
represented by random variables which capture the manufacturing variations. We
introduce the notion of statistical critical paths, which account for both
means and variances of performance variation. An optimization engine is used to
size gates with a goal of reducing the timing variance along the statistical
critical paths. We apply a pair of nested statistical analysis methods
deploying a slower more accurate approach for tracking statistical critical
paths and a fast engine for evaluation of gate size assignments. We derive a
new approximation for the max operation on random variables which is deployed
for the faster inner engine. Circuit optimization is carried out using a
gain-based algorithm that terminates when constraints are satisfied or no
further improvements can be made. We show optimization results that demonstrate
an average of 72% reduction in performance variation at the expense of average
20% increase in design area.
| cs.AR | a new approach for enhancing the processvariation tolerance of digital circuits is described we extend recent advances in statistical timing analysis into an optimization framework our objective is to reduce the performance variance of a technologymapped circuit where delays across elements are represented by random variables which capture the manufacturing variations we introduce the notion of statistical critical paths which account for both means and variances of performance variation an optimization engine is used to size gates with a goal of reducing the timing variance along the statistical critical paths we apply a pair of nested statistical analysis methods deploying a slower more accurate approach for tracking statistical critical paths and a fast engine for evaluation of gate size assignments we derive a new approximation for the max operation on random variables which is deployed for the faster inner engine circuit optimization is carried out using a gainbased algorithm that terminates when constraints are satisfied or no further improvements can be made we show optimization results that demonstrate an average of 72 reduction in performance variation at the expense of average 20 increase in design area | [['a', 'new', 'approach', 'for', 'enhancing', 'the', 'processvariation', 'tolerance', 'of', 'digital', 'circuits', 'is', 'described', 'we', 'extend', 'recent', 'advances', 'in', 'statistical', 'timing', 'analysis', 'into', 'an', 'optimization', 'framework', 'our', 'objective', 'is', 'to', 'reduce', 'the', 'performance', 'variance', 'of', 'a', 'technologymapped', 'circuit', 'where', 'delays', 'across', 'elements', 'are', 'represented', 'by', 'random', 'variables', 'which', 'capture', 'the', 'manufacturing', 'variations', 'we', 'introduce', 'the', 'notion', 'of', 'statistical', 'critical', 'paths', 'which', 'account', 'for', 'both', 'means', 'and', 'variances', 'of', 'performance', 'variation', 'an', 'optimization', 'engine', 'is', 'used', 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710.4714 | Assertion-Based Design Exploration of DVS in Network Processor
Architectures | With the scaling of technology and higher requirements on performance and
functionality, power dissipation is becoming one of the major design
considerations in the development of network processors. In this paper, we use
an assertion-based methodology for system-level power/performance analysis to
study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and
execution-based DVS, in a network processor model. Using the automatically
generated distribution analyzers, we analyze the power and performance
distributions and study their trade-offs for the two DVS policies with
different parameter settings such as threshold values and window sizes. We
discuss the optimal configurations of the two DVS policies under different
design requirements. By a set of experiments, we show that the assertion-based
trace analysis methodology is an efficient tool that can help a designer easily
compare and study optimal architectural configurations in a large design space.
| cs.AR | with the scaling of technology and higher requirements on performance and functionality power dissipation is becoming one of the major design considerations in the development of network processors in this paper we use an assertionbased methodology for systemlevel powerperformance analysis to study two dynamic voltage scaling dvs techniques trafficbased dvs and executionbased dvs in a network processor model using the automatically generated distribution analyzers we analyze the power and performance distributions and study their tradeoffs for the two dvs policies with different parameter settings such as threshold values and window sizes we discuss the optimal configurations of the two dvs policies under different design requirements by a set of experiments we show that the assertionbased trace analysis methodology is an efficient tool that can help a designer easily compare and study optimal architectural configurations in a large design space | [['with', 'the', 'scaling', 'of', 'technology', 'and', 'higher', 'requirements', 'on', 'performance', 'and', 'functionality', 'power', 'dissipation', 'is', 'becoming', 'one', 'of', 'the', 'major', 'design', 'considerations', 'in', 'the', 'development', 'of', 'network', 'processors', 'in', 'this', 'paper', 'we', 'use', 'an', 'assertionbased', 'methodology', 'for', 'systemlevel', 'powerperformance', 'analysis', 'to', 'study', 'two', 'dynamic', 'voltage', 'scaling', 'dvs', 'techniques', 'trafficbased', 'dvs', 'and', 'executionbased', 'dvs', 'in', 'a', 'network', 'processor', 'model', 'using', 'the', 'automatically', 'generated', 'distribution', 'analyzers', 'we', 'analyze', 'the', 'power', 'and', 'performance', 'distributions', 'and', 'study', 'their', 'tradeoffs', 'for', 'the', 'two', 'dvs', 'policies', 'with', 'different', 'parameter', 'settings', 'such', 'as', 'threshold', 'values', 'and', 'window', 'sizes', 'we', 'discuss', 'the', 'optimal', 'configurations', 'of', 'the', 'two', 'dvs', 'policies', 'under', 'different', 'design', 'requirements', 'by', 'a', 'set', 'of', 'experiments', 'we', 'show', 'that', 'the', 'assertionbased', 'trace', 'analysis', 'methodology', 'is', 'an', 'efficient', 'tool', 'that', 'can', 'help', 'a', 'designer', 'easily', 'compare', 'and', 'study', 'optimal', 'architectural', 'configurations', 'in', 'a', 'large', 'design', 'space']] | [-0.13852835902877206, 0.026698788735394118, -0.07465836694866097, 0.04281511956829202, -0.05666060863638953, -0.15965012669657097, 0.05762548782230814, 0.41909043190719414, -0.24960506071584473, -0.35215406682637096, 0.1257881345160359, -0.2243539959815391, -0.17903711402239345, 0.2380439407249122, -0.0773292202870998, 0.12068296008395356, 0.04819437038327614, -0.03855064226542231, -0.06354220247016751, -0.19627502306679384, 0.29261225809698266, 0.07618741409035681, 0.39372533226131107, 0.04120222420269195, 0.07098597376573858, -0.017764955482666763, -0.0032883662882884092, 0.03636154179689943, -0.1364676948816209, 0.11773279702907308, 0.2664660708643764, 0.20117355884126514, 0.3078253620786579, -0.4149479334034937, -0.161721780654981, 0.07020838341253588, 0.09305076922202925, 0.044165730925290275, -0.04259722634208583, -0.22882224527596357, 0.12710593421038963, -0.2193009799359728, -0.07101150923710076, -0.12047692116604541, -0.026927378410540468, 0.03251667667294202, -0.3003288620727793, -0.047484122171475414, 0.011975188304087241, 0.051512198289856315, -0.05830173513168643, -0.09159847199179821, 0.04062231592733494, 0.16674478545725485, 0.01797103452271775, -0.032846902324583566, 0.17486420982155493, -0.13863957953210518, -0.17047395224167075, 0.35106091608675266, -0.008806475806686517, -0.2197780401894836, 0.1741328066509726, -0.07522133057401013, -0.1482220569009082, 0.05474564356045972, 0.23901699405672738, 0.07361451469415384, -0.1962637116616632, 0.0367239316721889, 0.03312600635012223, 0.19169621761861466, 0.029200890918912217, 0.04488922542349683, 0.16447231086413208, 0.24391865930620502, 0.07460352323828734, 0.18779211114127214, -0.07023156518552104, -0.09008406331802872, -0.2695782534550313, -0.1388444166107894, -0.131355390917483, -0.023116484990430553, -0.1383180737240188, -0.11525929207317263, 0.4102532167034559, 0.2056195453268295, 0.17936861118688682, 0.08794680880985671, 0.36395744558611365, 0.07474487848932061, 0.0945944641867532, 0.08732617663206171, 0.15874496251495435, 0.008295190944369856, 0.14460133234869768, -0.22804334312727634, 0.04592979108753929, -0.01647328884883536] |
710.4715 | Circuit-Level Modeling for Concurrent Testing of Operational Defects due
to Gate Oxide Breakdown | As device sizes shrink and current densities increase, the probability of
device failures due to gate oxide breakdown (OBD) also increases. To provide
designs that are tolerant to such failures, we must investigate and understand
the manifestations of this physical phenomenon at the circuit and system level.
In this paper, we develop a model for operational OBD defects, and we explore
how to test for faults due to OBD. For a NAND gate, we derive the necessary
input conditions that excite and detect errors due to OBD defects at the gate
level. We show that traditional pattern generators fail to exercise all of
these defects. Finally, we show that these test patterns can be propagated and
justified for a combinational circuit in a manner similar to traditional ATPG.
| cs.AR | as device sizes shrink and current densities increase the probability of device failures due to gate oxide breakdown obd also increases to provide designs that are tolerant to such failures we must investigate and understand the manifestations of this physical phenomenon at the circuit and system level in this paper we develop a model for operational obd defects and we explore how to test for faults due to obd for a nand gate we derive the necessary input conditions that excite and detect errors due to obd defects at the gate level we show that traditional pattern generators fail to exercise all of these defects finally we show that these test patterns can be propagated and justified for a combinational circuit in a manner similar to traditional atpg | [['as', 'device', 'sizes', 'shrink', 'and', 'current', 'densities', 'increase', 'the', 'probability', 'of', 'device', 'failures', 'due', 'to', 'gate', 'oxide', 'breakdown', 'obd', 'also', 'increases', 'to', 'provide', 'designs', 'that', 'are', 'tolerant', 'to', 'such', 'failures', 'we', 'must', 'investigate', 'and', 'understand', 'the', 'manifestations', 'of', 'this', 'physical', 'phenomenon', 'at', 'the', 'circuit', 'and', 'system', 'level', 'in', 'this', 'paper', 'we', 'develop', 'a', 'model', 'for', 'operational', 'obd', 'defects', 'and', 'we', 'explore', 'how', 'to', 'test', 'for', 'faults', 'due', 'to', 'obd', 'for', 'a', 'nand', 'gate', 'we', 'derive', 'the', 'necessary', 'input', 'conditions', 'that', 'excite', 'and', 'detect', 'errors', 'due', 'to', 'obd', 'defects', 'at', 'the', 'gate', 'level', 'we', 'show', 'that', 'traditional', 'pattern', 'generators', 'fail', 'to', 'exercise', 'all', 'of', 'these', 'defects', 'finally', 'we', 'show', 'that', 'these', 'test', 'patterns', 'can', 'be', 'propagated', 'and', 'justified', 'for', 'a', 'combinational', 'circuit', 'in', 'a', 'manner', 'similar', 'to', 'traditional', 'atpg']] | [-0.11187261707368634, 0.09726589530328056, -0.032301757812092546, 0.08575966244643496, -0.016840890539242537, -0.17642970766610233, 0.1228703798906281, 0.41841071378439665, -0.25751640103226237, -0.3397945109391003, 0.0986261916859803, -0.23115309568129305, -0.19241110527218552, 0.18295691706225625, -0.15767611640876567, 0.05570183353847824, 0.022125087820313638, -0.028538765563780544, -0.06368461668898817, -0.23036182946088957, 0.24599221992320963, 0.08202661309701398, 0.3000749978382373, 0.07986555735988077, 0.06117818287020782, -0.047887160390018835, 0.05602592363607073, 0.040749772888375446, -0.10499285595983565, 0.06776383209216874, 0.2819957711180905, 0.11412359222413215, 0.22644536040024832, -0.5188830939587206, -0.17796861762690241, 0.07851596023829188, 0.10718671133145108, 0.17250810766927316, -0.028315674412624503, -0.23984946132986806, 0.1658057585118513, -0.17381427472719224, -0.1296491069442709, -0.10771678336254809, 0.011496329942019656, 0.0159528202675574, -0.2736155963903002, 0.0004966322064774431, 0.0730279867129866, 0.0287714622245403, 0.002060865041130455, -0.03868650935601181, 0.023129921548388666, 0.14122887632765924, -0.002218878683379444, -0.0042609400275068765, 0.20184382872685092, -0.09535248404790764, -0.14610959805577295, 0.35137086728354916, 0.0008349791128239303, -0.17363109599716608, 0.20484889223007485, -0.11907419532417407, -0.11368902084836918, 0.0753050631624319, 0.22272186200643773, 0.02891257577630313, -0.13876445101050194, -0.0044908692780154524, 0.06857125534588704, 0.19527755386661738, 0.08898681895880145, 0.06473401845960325, 0.20550455842749216, 0.15356208598677767, 0.09048457637254614, 0.18712964150381595, -0.10331010047593736, -0.02186730386893032, -0.3166794559947448, -0.1608743087053881, -0.12327939746955963, 0.03634399601651239, -0.019281019221352835, -0.18894007663766388, 0.4126423576963134, 0.2763765427916951, 0.17871322235805565, 0.061299681234231684, 0.29922071313194465, 0.1357747757783727, 0.10153254457691219, 0.054421449181973, 0.1893384840368526, 0.07469169716387114, 0.06422978288901504, -0.2380452061916003, 0.10681051299980027, -0.021456448375829495] |
710.4716 | Optimized Generation of Data-Path from C Codes for FPGAs | FPGAs, as computing devices, offer significant speedup over microprocessors.
Furthermore, their configurability offers an advantage over traditional ASICs.
However, they do not yet enjoy high-level language programmability, as
microprocessors do. This has become the main obstacle for their wider
acceptance by application designers. ROCCC is a compiler designed to generate
circuits from C source code to execute on FPGAs, more specifically on CSoCs. It
generates RTL level HDLs from frequently executing kernels in an application.
In this paper, we describe ROCCC's system overview and focus on its data path
generation. We compare the performance of ROCCC-generated VHDL code with that
of Xilinx IPs. The synthesis result shows that ROCCC-generated circuit takes
around 2x ~ 3x area and runs at comparable clock rate.
| cs.AR | fpgas as computing devices offer significant speedup over microprocessors furthermore their configurability offers an advantage over traditional asics however they do not yet enjoy highlevel language programmability as microprocessors do this has become the main obstacle for their wider acceptance by application designers roccc is a compiler designed to generate circuits from c source code to execute on fpgas more specifically on csocs it generates rtl level hdls from frequently executing kernels in an application in this paper we describe rocccs system overview and focus on its data path generation we compare the performance of rocccgenerated vhdl code with that of xilinx ips the synthesis result shows that rocccgenerated circuit takes around 2x 3x area and runs at comparable clock rate | [['fpgas', 'as', 'computing', 'devices', 'offer', 'significant', 'speedup', 'over', 'microprocessors', 'furthermore', 'their', 'configurability', 'offers', 'an', 'advantage', 'over', 'traditional', 'asics', 'however', 'they', 'do', 'not', 'yet', 'enjoy', 'highlevel', 'language', 'programmability', 'as', 'microprocessors', 'do', 'this', 'has', 'become', 'the', 'main', 'obstacle', 'for', 'their', 'wider', 'acceptance', 'by', 'application', 'designers', 'roccc', 'is', 'a', 'compiler', 'designed', 'to', 'generate', 'circuits', 'from', 'c', 'source', 'code', 'to', 'execute', 'on', 'fpgas', 'more', 'specifically', 'on', 'csocs', 'it', 'generates', 'rtl', 'level', 'hdls', 'from', 'frequently', 'executing', 'kernels', 'in', 'an', 'application', 'in', 'this', 'paper', 'we', 'describe', 'rocccs', 'system', 'overview', 'and', 'focus', 'on', 'its', 'data', 'path', 'generation', 'we', 'compare', 'the', 'performance', 'of', 'rocccgenerated', 'vhdl', 'code', 'with', 'that', 'of', 'xilinx', 'ips', 'the', 'synthesis', 'result', 'shows', 'that', 'rocccgenerated', 'circuit', 'takes', 'around', '2x', '3x', 'area', 'and', 'runs', 'at', 'comparable', 'clock', 'rate']] | [-0.11857774052060331, -0.010410096364490607, -0.051079225930911694, 0.026715698464439535, -0.08792251096633466, -0.19703996057581644, 0.04110026922907033, 0.4878452192182126, -0.22378931192924148, -0.3627789444492563, 0.10287394030120872, -0.23844597217343425, -0.1025303387488036, 0.34818878365154177, -0.11774961261848069, 0.07756244247404696, 0.10896793273682504, 0.0019866860248958285, -0.060516833263935275, -0.27734125677000165, 0.20830200013259184, 0.12329161244889965, 0.29285177669649864, 0.040635969738840406, 0.09291106105437907, -0.03905186603129234, 0.024489904049298038, -0.06778470366059439, -0.02365496722315742, 0.1198786921961152, 0.29007769785821436, 0.22906655094626804, 0.29126542705799574, -0.4919164403139249, -0.14472706022915308, 0.04077523047023493, 0.1488557472906035, 0.08157072301306155, -0.07362479706175888, -0.2273174843993848, 0.1420430892633031, -0.25492691823443314, -0.019332822025424558, -0.11411140258221522, 0.010818405076861382, 0.017053814259175536, -0.1887753669668556, -0.11932468893735305, 0.09472803237807492, 0.10444584694569525, 0.020151484853198308, -0.13586063677262838, 0.038410927462594016, 0.1348727696656209, -0.05408778836262291, 0.08779193231274131, 0.18426571900541286, -0.10160509882160745, -0.16866654735159778, 0.3906366102883349, -0.03520080560372899, -0.1676578505774555, 0.2080735099815723, -0.04029843807220459, -0.1285506590552952, 0.12304217544100855, 0.2440762376088811, 0.03304057546040934, -0.14061523416160565, 0.11707758536542077, 0.05012183847391735, 0.24992294245571628, 0.06043527109103034, 0.07821111666119616, 0.19776034656407201, 0.23062190971863658, 0.07583130911124222, 0.1567063825002507, -0.04649241600874002, -0.0919627721907328, -0.22172778736314047, -0.17923880883937945, -0.15196272178917475, 0.024494426531600767, -0.040041831643674926, -0.17313573554806086, 0.39138070147322573, 0.24283681740660382, 0.09721040808717193, 0.14009643001076968, 0.3768398813012501, 0.07838480772814997, 0.21817169398089628, 0.1450965376327867, 0.13341749520648433, -0.0017369520364572172, 0.16968568366871256, -0.15438847104492395, 0.08738916894501966, -0.03865759970377321] |
710.4717 | Multi-Placement Structures for Fast and Optimized Placement in Analog
Circuit Synthesis | This paper presents the novel idea of multi-placement structures, for a fast
and optimized placement instantiation in analog circuit synthesis. These
structures need to be generated only once for a specific circuit topology. When
used in synthesis, these pre-generated structures instantiate various layout
floorplans for various sizes and parameters of a circuit. Unlike procedural
layout generators, they enable fast placement of circuits while keeping the
quality of the placements at a high level during a synthesis process. The fast
placement is a result of high speed instantiation resulting from the efficiency
of the multi-placement structure. The good quality of placements derive from
the extensive and intelligent search process that is used to build the
multi-placement structure. The target benchmarks of these structures are analog
circuits in the vicinity of 25 modules. An algorithm for the generation of such
multi-placement structures is presented. Experimental results show placement
execution times with an average of a few milliseconds making them usable during
layout-aware synthesis for optimized placements.
| cs.AR | this paper presents the novel idea of multiplacement structures for a fast and optimized placement instantiation in analog circuit synthesis these structures need to be generated only once for a specific circuit topology when used in synthesis these pregenerated structures instantiate various layout floorplans for various sizes and parameters of a circuit unlike procedural layout generators they enable fast placement of circuits while keeping the quality of the placements at a high level during a synthesis process the fast placement is a result of high speed instantiation resulting from the efficiency of the multiplacement structure the good quality of placements derive from the extensive and intelligent search process that is used to build the multiplacement structure the target benchmarks of these structures are analog circuits in the vicinity of 25 modules an algorithm for the generation of such multiplacement structures is presented experimental results show placement execution times with an average of a few milliseconds making them usable during layoutaware synthesis for optimized placements | [['this', 'paper', 'presents', 'the', 'novel', 'idea', 'of', 'multiplacement', 'structures', 'for', 'a', 'fast', 'and', 'optimized', 'placement', 'instantiation', 'in', 'analog', 'circuit', 'synthesis', 'these', 'structures', 'need', 'to', 'be', 'generated', 'only', 'once', 'for', 'a', 'specific', 'circuit', 'topology', 'when', 'used', 'in', 'synthesis', 'these', 'pregenerated', 'structures', 'instantiate', 'various', 'layout', 'floorplans', 'for', 'various', 'sizes', 'and', 'parameters', 'of', 'a', 'circuit', 'unlike', 'procedural', 'layout', 'generators', 'they', 'enable', 'fast', 'placement', 'of', 'circuits', 'while', 'keeping', 'the', 'quality', 'of', 'the', 'placements', 'at', 'a', 'high', 'level', 'during', 'a', 'synthesis', 'process', 'the', 'fast', 'placement', 'is', 'a', 'result', 'of', 'high', 'speed', 'instantiation', 'resulting', 'from', 'the', 'efficiency', 'of', 'the', 'multiplacement', 'structure', 'the', 'good', 'quality', 'of', 'placements', 'derive', 'from', 'the', 'extensive', 'and', 'intelligent', 'search', 'process', 'that', 'is', 'used', 'to', 'build', 'the', 'multiplacement', 'structure', 'the', 'target', 'benchmarks', 'of', 'these', 'structures', 'are', 'analog', 'circuits', 'in', 'the', 'vicinity', 'of', '25', 'modules', 'an', 'algorithm', 'for', 'the', 'generation', 'of', 'such', 'multiplacement', 'structures', 'is', 'presented', 'experimental', 'results', 'show', 'placement', 'execution', 'times', 'with', 'an', 'average', 'of', 'a', 'few', 'milliseconds', 'making', 'them', 'usable', 'during', 'layoutaware', 'synthesis', 'for', 'optimized', 'placements']] | [-0.11560898816934219, 0.04963598003850188, -0.024709326239223253, 0.026767278129272, -0.06274647804022562, -0.11908171498273476, 0.0798189737557195, 0.4440445246646272, -0.2718732875939345, -0.3838793836397732, 0.1293888434422736, -0.18625180182478776, -0.1408732856322852, 0.23931287024624465, -0.07189810389607418, 0.0901543728257643, 0.0920493368275191, -0.003448877179080893, -0.06594711674374483, -0.21106526447266977, 0.2301980056856736, 0.10664142886312997, 0.3440113707513707, -0.028849355955948917, 0.09546636696053078, -0.01744903230233254, 0.007518567704232182, -0.015227826715378864, -0.06128350394181148, 0.16447641957755677, 0.27204082698402243, 0.18831895236295035, 0.22216387021798278, -0.4596841413777594, -0.1458721664299757, 0.04491078753660365, 0.10195206902586151, 0.12030299232630967, -0.10725205371485705, -0.23491728776588855, 0.13099907440269684, -0.1583815396382905, -0.08505568845288419, -0.05969360279396358, 0.0011006159673831084, 0.0508521257572461, -0.2795409376700352, -0.060614286158120305, 0.03310068731590901, 0.033642175678368205, -0.03731701427377851, -0.11660617410784542, 0.007505930112618044, 0.18157021319667566, -0.08216751355389644, -0.012889365508560399, 0.15256918081978232, -0.1429220938773985, -0.15837394320633172, 0.3726449680582779, 0.015763943549245596, -0.17989562794199873, 0.17002714864367324, -0.04816768635575455, -0.1555299694612963, 0.1543172085600928, 0.18486560036700855, 0.10996248180943928, -0.14377994779981856, 0.038030351817724295, 0.010356137915883532, 0.2184210957663997, 0.07701008909143417, 0.029452667148533937, 0.199362665392095, 0.251493748564205, 0.06543651942402215, 0.17200050959093838, -0.06487702441819881, -0.05154902654949848, -0.27713430658119115, -0.15946280472150937, -0.13814886482205332, 0.006059294955509647, -0.09905950752878065, -0.18460273600421936, 0.40378370233697863, 0.17445775339028177, 0.1964575030880685, 0.07486328879575722, 0.3359428067441757, 0.065319929604146, 0.10965834831444138, 0.0774810620549521, 0.15311737152145857, 0.052105053447232375, 0.0998049263158109, -0.196006206697614, 0.10524140965909039, 0.045732328588733585] |
710.4718 | Noise Figure Evaluation Using Low Cost BIST | A technique for evaluating noise figure suitable for BIST implementation is
described. It is based on a low cost single-bit digitizer, which allows the
simultaneous evaluation of noise figure in several test points of the analog
circuit. The method is also able to benefit from SoC resources, like memory and
processing power. Theoretical background and experimental results are presented
in order to demonstrate the feasibility of the approach.
| cs.OH | a technique for evaluating noise figure suitable for bist implementation is described it is based on a low cost singlebit digitizer which allows the simultaneous evaluation of noise figure in several test points of the analog circuit the method is also able to benefit from soc resources like memory and processing power theoretical background and experimental results are presented in order to demonstrate the feasibility of the approach | [['a', 'technique', 'for', 'evaluating', 'noise', 'figure', 'suitable', 'for', 'bist', 'implementation', 'is', 'described', 'it', 'is', 'based', 'on', 'a', 'low', 'cost', 'singlebit', 'digitizer', 'which', 'allows', 'the', 'simultaneous', 'evaluation', 'of', 'noise', 'figure', 'in', 'several', 'test', 'points', 'of', 'the', 'analog', 'circuit', 'the', 'method', 'is', 'also', 'able', 'to', 'benefit', 'from', 'soc', 'resources', 'like', 'memory', 'and', 'processing', 'power', 'theoretical', 'background', 'and', 'experimental', 'results', 'are', 'presented', 'in', 'order', 'to', 'demonstrate', 'the', 'feasibility', 'of', 'the', 'approach']] | [-0.10979279562803533, -0.00384851815589868, -0.06780797806020607, 0.016313886343542597, -0.06223656958557994, -0.17010628737454467, 0.08039653306717381, 0.3740630311966764, -0.22068246184190846, -0.3532945480581154, 0.11460857718895354, -0.2501675517005959, -0.17127214802209945, 0.3240807306377546, -0.09191247239633572, 0.11589180202880765, 0.06640524753225584, 0.00915419651359758, -0.02885734679276699, -0.2573573306641158, 0.23110169529236907, 0.13390874898280292, 0.3528522739241667, 0.048046249232035786, 0.11537525813807459, -0.030223754809840638, -0.04231737774577649, 0.007449579260805074, -0.032820816514739656, 0.125507492085864, 0.24862959890571587, 0.14108326623681933, 0.2570054955670939, -0.39117103889036703, -0.1546092198559028, 0.04087036501561456, 0.05290172900319757, 0.10568721249857095, -0.05416309931966038, -0.2607663915328243, 0.11841384914484532, -0.18973111335242934, -0.054920167895033956, -0.16666028933490024, -0.02779920243055505, 0.009681751513305832, -0.3193333654061836, 0.0208364974545582, 0.06200352934940705, 0.028685993473867282, -0.006961437504608458, -0.13513088051695377, 0.07141054822268951, 0.11417510388555992, -0.042294845118543464, 0.0024926452520851266, 0.14756832308108536, -0.10789668694248095, -0.13736351041178055, 0.3867545533541809, -0.057740934119518736, -0.21017533259959342, 0.15593098842552588, -0.07404242170056985, -0.10747830128050684, 0.13384736582691617, 0.1772269154624904, 0.048860758062373326, -0.17159321294713983, 0.07637550155446018, 0.06116251916597214, 0.20441147909664056, 0.03715631553410169, 0.06836977523669381, 0.14955972570597248, 0.23176538475843914, 0.05590271767612327, 0.18999522979549296, -0.12269749422472052, -0.07625988549005021, -0.29446788149310604, -0.17852631516699843, -0.2447853962863412, -0.0005170463940457386, -0.06852625703108703, -0.09953086893074214, 0.41227315145763843, 0.23291005900896647, 0.133519451791311, 0.05658585055190248, 0.3875819549841039, 0.11252163625185323, 0.06387799682424349, 0.05006596071453875, 0.18802382498431733, 0.08354920185828472, 0.11210785986280397, -0.24137796653667465, 0.0202371942851802, 0.018572609269005412] |
710.4719 | Specification Test Compaction for Analog Circuits and MEMS | Testing a non-digital integrated system against all of its specifications can
be quite expensive due to the elaborate test application and measurement setup
required. We propose to eliminate redundant tests by employing e-SVM based
statistical learning. Application of the proposed methodology to an operational
amplifier and a MEMS accelerometer reveal that redundant tests can be
statistically identified from a complete set of specification-based tests with
negligible error. Specifically, after eliminating five of eleven
specification-based tests for an operational amplifier, the defect escape and
yield loss is small at 0.6% and 0.9%, respectively. For the accelerometer,
defect escape of 0.2% and yield loss of 0.1% occurs when the hot and colt tests
are eliminated. For the accelerometer, this level of Compaction would reduce
test cost by more than half.
| cs.AR | testing a nondigital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required we propose to eliminate redundant tests by employing esvm based statistical learning application of the proposed methodology to an operational amplifier and a mems accelerometer reveal that redundant tests can be statistically identified from a complete set of specificationbased tests with negligible error specifically after eliminating five of eleven specificationbased tests for an operational amplifier the defect escape and yield loss is small at 06 and 09 respectively for the accelerometer defect escape of 02 and yield loss of 01 occurs when the hot and colt tests are eliminated for the accelerometer this level of compaction would reduce test cost by more than half | [['testing', 'a', 'nondigital', 'integrated', 'system', 'against', 'all', 'of', 'its', 'specifications', 'can', 'be', 'quite', 'expensive', 'due', 'to', 'the', 'elaborate', 'test', 'application', 'and', 'measurement', 'setup', 'required', 'we', 'propose', 'to', 'eliminate', 'redundant', 'tests', 'by', 'employing', 'esvm', 'based', 'statistical', 'learning', 'application', 'of', 'the', 'proposed', 'methodology', 'to', 'an', 'operational', 'amplifier', 'and', 'a', 'mems', 'accelerometer', 'reveal', 'that', 'redundant', 'tests', 'can', 'be', 'statistically', 'identified', 'from', 'a', 'complete', 'set', 'of', 'specificationbased', 'tests', 'with', 'negligible', 'error', 'specifically', 'after', 'eliminating', 'five', 'of', 'eleven', 'specificationbased', 'tests', 'for', 'an', 'operational', 'amplifier', 'the', 'defect', 'escape', 'and', 'yield', 'loss', 'is', 'small', 'at', '06', 'and', '09', 'respectively', 'for', 'the', 'accelerometer', 'defect', 'escape', 'of', '02', 'and', 'yield', 'loss', 'of', '01', 'occurs', 'when', 'the', 'hot', 'and', 'colt', 'tests', 'are', 'eliminated', 'for', 'the', 'accelerometer', 'this', 'level', 'of', 'compaction', 'would', 'reduce', 'test', 'cost', 'by', 'more', 'than', 'half']] | [-0.07327719732264687, 0.09170472200095514, -0.07449898195973649, 0.044926137135430116, -0.02129937605345695, -0.20178773034525316, 0.08841972269015166, 0.3635368484446383, -0.1948307050487364, -0.37198508883217773, 0.14414932184914991, -0.27461104096448796, -0.07819078790067922, 0.2568433656481894, -0.10863486764673877, 0.08271726822860055, 0.09351053388099971, -0.01691790550441195, -0.06884024472491024, -0.2525149318143816, 0.2322403237445456, 0.11350329185462021, 0.274077418892769, 0.002727125020602381, 0.12994504966369763, -0.010637731477434886, -0.04997689504997702, 0.03926144075427777, -0.07594780858147085, 0.10786004015427875, 0.23530049422594507, 0.17664605422737442, 0.3064042364254477, -0.4210658749037488, -0.15558566155066111, 0.07629231498466701, 0.09651766515586262, 0.09734015533421922, -0.032680935228787046, -0.27049408166661976, 0.11220568071273486, -0.18826093967255997, -0.1077612436992505, -0.09645345252865237, -0.022300931394070855, -0.021267925785106466, -0.3010394496368391, 0.0714668423876049, 0.025550836088561166, 0.10671241760371238, -0.02144655880268927, -0.10372105711891397, 0.0028954408237871925, 0.09902316375244152, 0.005901686152384624, -0.006094882876830411, 0.20270631128306113, -0.06734937711574841, -0.09963693228590588, 0.38149906276893897, -0.03904763216578574, -0.18866960339864172, 0.1832369471823166, -0.08246545999184413, -0.10106990352918313, 0.16596257783780535, 0.17801917916760546, 0.03662899565538318, -0.18554669695479636, -0.025440341341089252, 0.07191995394188823, 0.21802189123384128, 0.10727732693795394, 0.03744808572718478, 0.17974106276657167, 0.18927259399467625, 0.05690465989251306, 0.1425816497241154, -0.1329544114946263, -0.004997779433725504, -0.3172916437785222, -0.13645947413101028, -0.1394163496420154, 0.03596197016625188, -0.09847170770040889, -0.12354466577581182, 0.3292400379789861, 0.19931461852718527, 0.14292195662636104, 0.06506877448996455, 0.3241860438908238, 0.1038401092827278, 0.09172880487868518, 0.051765600253457084, 0.2670149817837285, 0.07027510158702965, 0.04376803617924452, -0.20022639856622446, 0.0652594880244922, -0.028296220055817972] |
710.472 | Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits | Nanometer circuits are becoming increasingly susceptible to soft-errors due
to alpha-particle and atmospheric neutron strikes as device scaling reduces
node capacitances and supply/threshold voltage scaling reduces noise margins.
It is becoming crucial to add soft-error tolerance estimation and optimization
to the design flow to handle the increasing susceptibility. The first part of
this paper presents a tool for accurate soft-error tolerance analysis of
nanometer circuits (ASERTA) that can be used to estimate the soft-error
tolerance of nanometer circuits consisting of millions of gates. The tolerance
estimates generated by the tool match SPICE generated estimates closely while
taking orders of magnitude less computation time. The second part of the paper
presents a tool for soft-error tolerance optimization of nanometer circuits
(SERTOPT) using the tolerance estimates generated by ASERTA. The tool finds
optimal sizes, channel lengths, supply voltages and threshold voltages to be
assigned to gates in a combinational circuit such that the soft-error tolerance
is increased while meeting the timing constraint. Experiments on ISCAS'85
benchmark circuits showed that soft-error rate of the optimized circuit
decreased by as much as 47% with marginal increase in circuit delay.
| cs.AR | nanometer circuits are becoming increasingly susceptible to softerrors due to alphaparticle and atmospheric neutron strikes as device scaling reduces node capacitances and supplythreshold voltage scaling reduces noise margins it is becoming crucial to add softerror tolerance estimation and optimization to the design flow to handle the increasing susceptibility the first part of this paper presents a tool for accurate softerror tolerance analysis of nanometer circuits aserta that can be used to estimate the softerror tolerance of nanometer circuits consisting of millions of gates the tolerance estimates generated by the tool match spice generated estimates closely while taking orders of magnitude less computation time the second part of the paper presents a tool for softerror tolerance optimization of nanometer circuits sertopt using the tolerance estimates generated by aserta the tool finds optimal sizes channel lengths supply voltages and threshold voltages to be assigned to gates in a combinational circuit such that the softerror tolerance is increased while meeting the timing constraint experiments on iscas85 benchmark circuits showed that softerror rate of the optimized circuit decreased by as much as 47 with marginal increase in circuit delay | [['nanometer', 'circuits', 'are', 'becoming', 'increasingly', 'susceptible', 'to', 'softerrors', 'due', 'to', 'alphaparticle', 'and', 'atmospheric', 'neutron', 'strikes', 'as', 'device', 'scaling', 'reduces', 'node', 'capacitances', 'and', 'supplythreshold', 'voltage', 'scaling', 'reduces', 'noise', 'margins', 'it', 'is', 'becoming', 'crucial', 'to', 'add', 'softerror', 'tolerance', 'estimation', 'and', 'optimization', 'to', 'the', 'design', 'flow', 'to', 'handle', 'the', 'increasing', 'susceptibility', 'the', 'first', 'part', 'of', 'this', 'paper', 'presents', 'a', 'tool', 'for', 'accurate', 'softerror', 'tolerance', 'analysis', 'of', 'nanometer', 'circuits', 'aserta', 'that', 'can', 'be', 'used', 'to', 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710.4721 | IEEE 1149.4 Compatible ABMs for Basic RF Measurements | An analogue testing standard IEEE 1149.4 is mainly targeted for low-frequency
testing. The problem studied in this paper is extending the standard also for
radio frequency testing. IEEE 1149.4 compatible measurement structures (ABMs)
developed in this study extract the information one is measuring from the radio
frequency signal and represent the result as a DC voltage level. The ABMs
presented in this paper are targeted for power and frequency measurements
operating in frequencies from 1 GHz to 2 GHz. The power measurement error
caused by temperature, supply voltage and process variations is roughly 2 dB
and the frequency measurement error is 0.1 GHz, respectively.
| cs.AR | an analogue testing standard ieee 11494 is mainly targeted for lowfrequency testing the problem studied in this paper is extending the standard also for radio frequency testing ieee 11494 compatible measurement structures abms developed in this study extract the information one is measuring from the radio frequency signal and represent the result as a dc voltage level the abms presented in this paper are targeted for power and frequency measurements operating in frequencies from 1 ghz to 2 ghz the power measurement error caused by temperature supply voltage and process variations is roughly 2 db and the frequency measurement error is 01 ghz respectively | [['an', 'analogue', 'testing', 'standard', 'ieee', '11494', 'is', 'mainly', 'targeted', 'for', 'lowfrequency', 'testing', 'the', 'problem', 'studied', 'in', 'this', 'paper', 'is', 'extending', 'the', 'standard', 'also', 'for', 'radio', 'frequency', 'testing', 'ieee', '11494', 'compatible', 'measurement', 'structures', 'abms', 'developed', 'in', 'this', 'study', 'extract', 'the', 'information', 'one', 'is', 'measuring', 'from', 'the', 'radio', 'frequency', 'signal', 'and', 'represent', 'the', 'result', 'as', 'a', 'dc', 'voltage', 'level', 'the', 'abms', 'presented', 'in', 'this', 'paper', 'are', 'targeted', 'for', 'power', 'and', 'frequency', 'measurements', 'operating', 'in', 'frequencies', 'from', '1', 'ghz', 'to', '2', 'ghz', 'the', 'power', 'measurement', 'error', 'caused', 'by', 'temperature', 'supply', 'voltage', 'and', 'process', 'variations', 'is', 'roughly', '2', 'db', 'and', 'the', 'frequency', 'measurement', 'error', 'is', '01', 'ghz', 'respectively']] | [-0.14104837696784392, 0.09039457758808567, 0.016979222185909748, 0.0062430725157320505, -0.03440569345660221, -0.16006529710452574, 0.09113051325682765, 0.3687722110010397, -0.24021978095138016, -0.3121988356758196, 0.1621178996686537, -0.21897841085536549, -0.08707056197678097, 0.2600290254653933, -0.06619903455094363, 0.03752487865858711, 0.008794501712635303, -0.024919041340651277, -3.078119614376472e-05, -0.12639872092180526, 0.22862396038209015, 0.14450885434276783, 0.33502980581341457, 0.0073695772667773645, 0.04921165168679391, -0.04294235989129028, -0.08297943049826874, -0.015774041665001556, -0.08275490944372275, 0.052265960795921274, 0.32029298891743213, 0.113007528505897, 0.25308745551424533, -0.317472285268685, -0.1910357874204727, 0.094765552037503, 0.041811127632032506, 0.06544542983129549, -0.016299436289745454, -0.26812884697350314, 0.1250854707054364, -0.18289435353989786, -0.08570540256243056, 0.06024072287031091, 0.009808929941545311, 0.021742923147170447, -0.30505220458592075, 0.1294096441144155, 0.05441875953469067, 0.12546398130675349, -0.04517701934897699, -0.11072713249954037, 0.0636301617621659, 0.11693451707217789, -0.018885234650952043, 0.050312523047558406, 0.17020518490328237, -0.07616045591734852, -0.16568478843412146, 0.3515472421019625, -0.06228199729006379, -0.13310001166358304, 0.14950899763677555, -0.1522785750387881, -0.1294831992709078, 0.08439345274550411, 0.18739129018677675, 0.01703455934609967, -0.19154184823408008, 0.05931584487105003, 0.050368075769466274, 0.26584436156106395, 0.14197595237055793, 0.03861962332246968, 0.1724778632275187, 0.1926404885150707, 0.061833165666589945, 0.119826495136994, -0.16701310683185092, -0.009647224505897611, -0.268166239051005, -0.09080198909997797, -0.19239283910988328, 0.07912040372432855, -0.04624850876448013, -0.08575102539571862, 0.4488463607043601, 0.1717757527009011, 0.1267764695087233, 0.08711793985164079, 0.38464860786468935, 0.17444719691859342, 0.049389481101220906, 0.0880317250221896, 0.27941348173100355, 0.15278110352497046, 0.13666440713076064, -0.16343618257759282, 0.01038310353536732, -0.060687514707052075] |
710.4722 | Designer-Driven Topology Optimization for Pipelined Analog to Digital
Converters | This paper suggests a practical "hybrid" synthesis methodology which
integrates designer-derived analytical models for system-level description with
simulation-based models at the circuit level. We show how to optimize
stage-resolution to minimize the power in a pipelined ADC. Exploration (via
detailed synthesis) of several ADC configurations is used to show that a
4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS
converter in a 0.25 $\mu$m CMOS process.
| cs.AR | this paper suggests a practical hybrid synthesis methodology which integrates designerderived analytical models for systemlevel description with simulationbased models at the circuit level we show how to optimize stageresolution to minimize the power in a pipelined adc exploration via detailed synthesis of several adc configurations is used to show that a 432 resolution distribution uses the least power for a 13bit 40 msps converter in a 025 mum cmos process | [['this', 'paper', 'suggests', 'a', 'practical', 'hybrid', 'synthesis', 'methodology', 'which', 'integrates', 'designerderived', 'analytical', 'models', 'for', 'systemlevel', 'description', 'with', 'simulationbased', 'models', 'at', 'the', 'circuit', 'level', 'we', 'show', 'how', 'to', 'optimize', 'stageresolution', 'to', 'minimize', 'the', 'power', 'in', 'a', 'pipelined', 'adc', 'exploration', 'via', 'detailed', 'synthesis', 'of', 'several', 'adc', 'configurations', 'is', 'used', 'to', 'show', 'that', 'a', '432', 'resolution', 'distribution', 'uses', 'the', 'least', 'power', 'for', 'a', '13bit', '40', 'msps', 'converter', 'in', 'a', '025', 'mum', 'cmos', 'process']] | [-0.062205003456337685, 0.0018903102287883633, -0.07812995049727163, 0.03757426241007586, -0.060750374994449206, -0.16033409454046624, 0.08358984091840406, 0.4243857883361738, -0.2416287022920798, -0.3555964664347581, 0.05907641093024233, -0.23747865258674347, -0.13358355142565362, 0.24629088279916278, -0.1090089823188844, 0.07985614111591409, 0.061535154434560396, -0.07683644304747012, -0.04584842983723632, -0.16535032704583744, 0.180557399557264, 0.1379327602239687, 0.30791601533098006, -0.032850772024257416, 0.17005640048700482, -0.06400952829437247, 0.01847539550221678, -0.0548297368240223, -0.13615461291952508, 0.11028445569047732, 0.30655813223211903, 0.1504436054670099, 0.26540332669809236, -0.42195015742596403, -0.22970945731069503, 0.03717951626697583, 0.13984220969810415, 0.06374169351122995, -0.08343088688023055, -0.13535707557935323, 0.1682972241637867, -0.24086314915165083, -0.06273421399128526, -0.037480528522004834, -0.05587945436474992, 0.018163178991804373, -0.3128503130456961, -0.035327734297085835, 0.0630904960710166, 0.06597893151677033, -0.036906642331950255, -0.1553075243093407, 0.022312929443737018, 0.05841489174444951, -0.092096098945841, -0.0021659512009381304, 0.13923525614246948, -0.07486692084513827, -0.1283908539674064, 0.33447418689950187, -0.03920363850279975, -0.19231646658102078, 0.1370881411677866, -0.07479128821878069, -0.1678061936773471, 0.15157131975822485, 0.21178781961215964, 0.06498255969873115, -0.20641029009824868, 0.04122953620085965, 0.057787599959480226, 0.3036010705713016, 0.016444155501563158, 2.018130148079858e-05, 0.23145361558478603, 0.28697628439612577, 0.058209425130330804, 0.18496625212632786, -0.14267401222083995, -0.07184907191419113, -0.27011636319333937, -0.14690531926479802, -0.12423606343400567, 0.053930061323735026, -0.06182798954533107, -0.1194164698210253, 0.41697868173802966, 0.21400542794935293, 0.1679821066391557, 0.13303809201713207, 0.4083086560174489, 0.13901051200592696, 0.07141986683900677, 0.0709344805287781, 0.185401763023336, 0.10137632888925971, 0.11930554764651095, -0.20943599342326844, 0.004427694583506282, -0.02246256743960861] |
710.4723 | Simulation Methodology for Analysis of Substrate Noise Impact on Analog
/ RF Circuits Including Interconnect Resistance | This paper reports a novel simulation methodology for analysis and prediction
of substrate noise impact on analog / RF circuits taking into account the role
of the parasitic resistance of the on-chip interconnect in the impact
mechanism. This methodology allows investigation of the role of the separate
devices (also parasitic devices) in the analog / RF circuit in the overall
impact. This way is revealed which devices have to be taken care of (shielding,
topology change) to protect the circuit against substrate noise. The developed
methodology is used to analyze impact of substrate noise on a 3 GHz LC-tank
Voltage Controlled Oscillator (VCO) designed in a high-ohmic 0.18 $\mu$m 1PM6
CMOS technology. For this VCO (in the investigated frequency range from DC to
15 MHz) impact is mainly caused by resistive coupling of noise from the
substrate to the non-ideal on-chip ground interconnect, resulting in analog
ground bounce and frequency modulation. Hence, the presented test-case reveals
the important role of the on-chip interconnect in the phenomenon of substrate
noise impact.
| cs.PF | this paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog rf circuits taking into account the role of the parasitic resistance of the onchip interconnect in the impact mechanism this methodology allows investigation of the role of the separate devices also parasitic devices in the analog rf circuit in the overall impact this way is revealed which devices have to be taken care of shielding topology change to protect the circuit against substrate noise the developed methodology is used to analyze impact of substrate noise on a 3 ghz lctank voltage controlled oscillator vco designed in a highohmic 018 mum 1pm6 cmos technology for this vco in the investigated frequency range from dc to 15 mhz impact is mainly caused by resistive coupling of noise from the substrate to the nonideal onchip ground interconnect resulting in analog ground bounce and frequency modulation hence the presented testcase reveals the important role of the onchip interconnect in the phenomenon of substrate noise impact | [['this', 'paper', 'reports', 'a', 'novel', 'simulation', 'methodology', 'for', 'analysis', 'and', 'prediction', 'of', 'substrate', 'noise', 'impact', 'on', 'analog', 'rf', 'circuits', 'taking', 'into', 'account', 'the', 'role', 'of', 'the', 'parasitic', 'resistance', 'of', 'the', 'onchip', 'interconnect', 'in', 'the', 'impact', 'mechanism', 'this', 'methodology', 'allows', 'investigation', 'of', 'the', 'role', 'of', 'the', 'separate', 'devices', 'also', 'parasitic', 'devices', 'in', 'the', 'analog', 'rf', 'circuit', 'in', 'the', 'overall', 'impact', 'this', 'way', 'is', 'revealed', 'which', 'devices', 'have', 'to', 'be', 'taken', 'care', 'of', 'shielding', 'topology', 'change', 'to', 'protect', 'the', 'circuit', 'against', 'substrate', 'noise', 'the', 'developed', 'methodology', 'is', 'used', 'to', 'analyze', 'impact', 'of', 'substrate', 'noise', 'on', 'a', '3', 'ghz', 'lctank', 'voltage', 'controlled', 'oscillator', 'vco', 'designed', 'in', 'a', 'highohmic', '018', 'mum', '1pm6', 'cmos', 'technology', 'for', 'this', 'vco', 'in', 'the', 'investigated', 'frequency', 'range', 'from', 'dc', 'to', '15', 'mhz', 'impact', 'is', 'mainly', 'caused', 'by', 'resistive', 'coupling', 'of', 'noise', 'from', 'the', 'substrate', 'to', 'the', 'nonideal', 'onchip', 'ground', 'interconnect', 'resulting', 'in', 'analog', 'ground', 'bounce', 'and', 'frequency', 'modulation', 'hence', 'the', 'presented', 'testcase', 'reveals', 'the', 'important', 'role', 'of', 'the', 'onchip', 'interconnect', 'in', 'the', 'phenomenon', 'of', 'substrate', 'noise', 'impact']] | [-0.1735272679059957, 0.07887074046386743, -0.02573016344665, -0.02393858026255887, -0.029492537317101854, -0.1726160160103162, 0.10315861456244847, 0.396683904820638, -0.22599773639700857, -0.3300314638539251, 0.07343658534964233, -0.2285618517304671, -0.1676515064409833, 0.25876423326623904, -0.06468845667676573, 0.04477503020681037, 0.004919390980973391, -0.07803376549181629, 0.019499314533047242, -0.1593678769184254, 0.24635791007979177, 0.13009820496666957, 0.39364221970921, 0.07469211979376444, 0.083766571282555, -0.056881689486172365, -0.027804503408092332, -0.02481790702700256, -0.08206241515869028, 0.07105830410517842, 0.2625835125211133, -0.00515105970433902, 0.27874949044850933, -0.49063992145168317, -0.22016521726723715, 0.06664217376509254, 0.0980646750659693, 0.11046496466158452, -0.0655097159548629, -0.2781639627618603, 0.0851723371376564, -0.18857445008491716, -0.08278759185609433, 0.0009134400591074702, -0.00843552515999111, -0.00027003121865262466, -0.21979269888588643, 0.016811868547376367, 0.0647423283676673, 0.06808013867598071, -0.041336205762271705, -0.12455051945499986, 0.006787214473069432, 0.13302851561193932, -0.03963560678956522, -0.005628944294673043, 0.24075213110730814, -0.07891088770842741, -0.08071479221233671, 0.325621693869155, -0.039097610856855224, -0.1605110135877397, 0.10349881182935268, -0.12147605133871267, -0.05225974385604173, 0.14541496844760265, 0.2245760935089405, -0.021280769030114704, -0.16246485609297517, 0.04296783289902967, 0.13513925368897617, 0.21775108186741282, 0.06194102319086486, 0.10058413068932223, 0.20549702370561748, 0.2610066018911662, 0.029667524440306608, 0.21215623721455124, -0.1457146099766475, -0.02606729143130851, -0.2585864612406277, -0.13172168172447077, -0.16321348913114922, 0.08089380727096247, -0.04887496874263056, -0.15564044533544277, 0.40282867006194517, 0.20993053216728416, 0.11208085469194655, -0.057338745265228516, 0.3907731161508934, 0.08919794528874153, 0.11538283174565758, -0.004244442009479256, 0.2685906246349395, 0.1693629905632669, 0.16959096894722925, -0.28603909591757076, 0.07357058728563741, -0.05136229559296675] |
710.4724 | Systematic Figure of Merit Computation for the Design of Pipeline ADC | The emerging concept of SoC-AMS leads to research new top-down methodologies
to aid systems designers in sizing analog and mixed devices. This work applies
this idea to the high-level optimization of pipeline ADC. Considering a given
technology, it consists in comparing different configurations according to
their imperfections and their architectures without FFT computation or
time-consuming simulations. The final selection is based on a figure of merit.
| cs.AR | the emerging concept of socams leads to research new topdown methodologies to aid systems designers in sizing analog and mixed devices this work applies this idea to the highlevel optimization of pipeline adc considering a given technology it consists in comparing different configurations according to their imperfections and their architectures without fft computation or timeconsuming simulations the final selection is based on a figure of merit | [['the', 'emerging', 'concept', 'of', 'socams', 'leads', 'to', 'research', 'new', 'topdown', 'methodologies', 'to', 'aid', 'systems', 'designers', 'in', 'sizing', 'analog', 'and', 'mixed', 'devices', 'this', 'work', 'applies', 'this', 'idea', 'to', 'the', 'highlevel', 'optimization', 'of', 'pipeline', 'adc', 'considering', 'a', 'given', 'technology', 'it', 'consists', 'in', 'comparing', 'different', 'configurations', 'according', 'to', 'their', 'imperfections', 'and', 'their', 'architectures', 'without', 'fft', 'computation', 'or', 'timeconsuming', 'simulations', 'the', 'final', 'selection', 'is', 'based', 'on', 'a', 'figure', 'of', 'merit']] | [-0.11814657418200603, 0.01691199864547413, -0.08283172121916253, 0.012788658866730447, -0.1299251636633506, -0.17752458474670466, 0.06454630918765011, 0.387944193639291, -0.25244402729977783, -0.3632918626643144, 0.09173004330279162, -0.20216020887287764, -0.16740630196335798, 0.2582274373298368, -0.1542313019597294, 0.10325483295779962, 0.08584034220458796, -0.06624488432246906, -0.09636630827847581, -0.24176865638627743, 0.2765996030961665, 0.11838692392294224, 0.3793217588789188, -0.025616730190813543, 0.07403753804974259, 0.010003036174636621, -0.068705236302832, -0.030996298121149617, -0.09694892731137, 0.19142024166738758, 0.28416431345618687, 0.1676870529898084, 0.3280602661462931, -0.4438611879658241, -0.1720663896546914, 0.04706372688166224, 0.12436385777993844, 0.10737039239074175, -0.04568255993071944, -0.2543363062252935, 0.10558259314499223, -0.19535990666213016, -0.08079266977617339, -0.07777228857068201, -0.03864634188536841, -0.007320685885273493, -0.24037615339486645, -0.040677308670889874, 0.040687687465777764, 0.033467768841924574, -0.041910542213904244, -0.1481448626289001, 0.03961949803364965, 0.15109222577705692, -0.031182596879079937, 0.0005240565541988381, 0.19146231167878097, -0.11826671892418884, -0.16219221367858924, 0.3961914511540761, 0.050389254752259985, -0.24257114281824146, 0.19545533035237056, 0.020337380483173406, -0.13747903890907764, 0.10298815504289591, 0.2117802557320549, 0.08623735101965184, -0.16534023178168214, 0.03958584676819066, 0.10474987974247107, 0.16792847947575726, 0.04408230805912843, 0.026937761390581728, 0.25025294942136567, 0.25537026888475967, 0.046887376968963786, 0.19683112423293866, -0.054260276597387226, -0.10549626599710721, -0.23127593429615864, -0.15780159640484132, -0.19138936613901303, 0.00814751282047767, -0.03858757043355861, -0.14809991443673007, 0.37979633279431324, 0.22129796187465006, 0.12317174101391663, 0.01261311247586631, 0.40874445638977563, 0.07712429961046348, 0.1165043263624494, 0.01952246936181417, 0.16557384475779074, 0.07849366960044091, 0.17541991541735255, -0.1985574750444637, 0.04774290573281737, 0.014679571033383791] |
710.4725 | Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits | This issue discusses the fault-trajectory approach suitability for fault
diagnosis on analog networks. Recent works have shown promising results
concerning a method based on this concept for ATPG for diagnosing faults on
analog networks. Such method relies on evolutionary techniques, where a generic
algorithm (GA) is coded to generate a set of optimum frequencies capable to
disclose faults.
| cs.NE | this issue discusses the faulttrajectory approach suitability for fault diagnosis on analog networks recent works have shown promising results concerning a method based on this concept for atpg for diagnosing faults on analog networks such method relies on evolutionary techniques where a generic algorithm ga is coded to generate a set of optimum frequencies capable to disclose faults | [['this', 'issue', 'discusses', 'the', 'faulttrajectory', 'approach', 'suitability', 'for', 'fault', 'diagnosis', 'on', 'analog', 'networks', 'recent', 'works', 'have', 'shown', 'promising', 'results', 'concerning', 'a', 'method', 'based', 'on', 'this', 'concept', 'for', 'atpg', 'for', 'diagnosing', 'faults', 'on', 'analog', 'networks', 'such', 'method', 'relies', 'on', 'evolutionary', 'techniques', 'where', 'a', 'generic', 'algorithm', 'ga', 'is', 'coded', 'to', 'generate', 'a', 'set', 'of', 'optimum', 'frequencies', 'capable', 'to', 'disclose', 'faults']] | [-0.11549443774243914, -0.05909269158483336, -0.052539250012813954, 0.06022061956658339, -0.06550608045143778, -0.1751450937192299, 0.08399139424753294, 0.37169411615877035, -0.16616449150534576, -0.29652541715717107, 0.12713742493896893, -0.18806818121096544, -0.2879207528670106, 0.3040854587758842, -0.12940668173363074, 0.12825440370330685, 0.10354874004265743, 0.02407049766758032, -0.006353448018464341, -0.237243737228901, 0.29485779104492904, 0.08857411616726925, 0.39558901360029713, 0.038633470815655435, 0.11041369514637872, 0.04191419620295627, -0.028821038237462442, 0.0036716266420849584, -0.09020428315393235, 0.14607332903368955, 0.3012488688293256, 0.19372978901261823, 0.31445792549404133, -0.4201964029159985, -0.27311737969386995, 0.07694184324262958, 0.10376522562613613, 0.16120139757792154, -0.09696188644228275, -0.28049759001454766, 0.1911743200923267, -0.13198455029346964, -0.0931300419186683, -0.11236727878394161, 0.005581463760647334, 0.011446609871519174, -0.28697074988954946, -0.012203112979860683, 0.03498971535775222, 0.05366313102932876, -0.04149644749990681, -0.11938560116023086, 0.12785275072561936, 0.056631214851350115, -0.03694644542982835, 0.0373138771392405, 0.14017834310142094, -0.02339038492503102, -0.20981708394461557, 0.3420870875318845, 0.012937428919892562, -0.20516922785655448, 0.21487518211646953, 0.05925063339568544, -0.22496983436704204, 0.10048365275980088, 0.2336164931684994, 0.12961470430488126, -0.15087318961230808, 0.030202953226602915, 0.026784362369462064, 0.1704483839046014, 0.044377098039707595, 0.016825297651322263, 0.20607501013702795, 0.2833842642670661, 0.0830367320429599, 0.1434611280963413, -0.09460964741536596, -0.05761469181692391, -0.1793372558772956, -0.13457500552268406, -0.20475993570953346, 0.019957078302181082, -0.048690522342854946, -0.19288844316370637, 0.41628992531383247, 0.2537983685176362, 0.14108941329054928, 0.04482348153792452, 0.3669894522938289, 0.02187959751621779, 0.08805426651317823, 0.0602558591533779, 0.19076904503571426, 0.10018083616568331, 0.1221237545016042, -0.18738552044644102, 0.14402756700496466, 0.13620421274058653] |
710.4726 | A New Independent Limit on the Cosmological Constant/Dark Energy from
the Relativistic Bending of Light by Galaxies and Clusters of Galaxies | We derive new limits on the value of the cosmological constant, $\Lambda$,
based on the Einstein bending of light by systems where the lens is a distant
galaxy or a cluster of galaxies. We use an amended lens equation in which the
contribution of $\Lambda$ to the Einstein deflection angle is taken into
account and use observations of Einstein radii around several lens systems. We
use in our calculations a Schwarzschild-de Sitter vacuole exactly matched into
a Friedmann-Robertson-Walker background and show that a $\Lambda$-contribution
term appears in the deflection angle within the lens equation. We find that the
contribution of the $\Lambda$-term to the bending angle is larger than the
second-order term for many lens systems. Using these observations of bending
angles, we derive new limits on the value of $\Lambda$. These limits constitute
the best observational upper bound on $\Lambda$ after cosmological constraints
and are only two orders of magnitude away from the value determined by those
cosmological constraints.
| astro-ph gr-qc hep-th | we derive new limits on the value of the cosmological constant lambda based on the einstein bending of light by systems where the lens is a distant galaxy or a cluster of galaxies we use an amended lens equation in which the contribution of lambda to the einstein deflection angle is taken into account and use observations of einstein radii around several lens systems we use in our calculations a schwarzschildde sitter vacuole exactly matched into a friedmannrobertsonwalker background and show that a lambdacontribution term appears in the deflection angle within the lens equation we find that the contribution of the lambdaterm to the bending angle is larger than the secondorder term for many lens systems using these observations of bending angles we derive new limits on the value of lambda these limits constitute the best observational upper bound on lambda after cosmological constraints and are only two orders of magnitude away from the value determined by those cosmological constraints | [['we', 'derive', 'new', 'limits', 'on', 'the', 'value', 'of', 'the', 'cosmological', 'constant', 'lambda', 'based', 'on', 'the', 'einstein', 'bending', 'of', 'light', 'by', 'systems', 'where', 'the', 'lens', 'is', 'a', 'distant', 'galaxy', 'or', 'a', 'cluster', 'of', 'galaxies', 'we', 'use', 'an', 'amended', 'lens', 'equation', 'in', 'which', 'the', 'contribution', 'of', 'lambda', 'to', 'the', 'einstein', 'deflection', 'angle', 'is', 'taken', 'into', 'account', 'and', 'use', 'observations', 'of', 'einstein', 'radii', 'around', 'several', 'lens', 'systems', 'we', 'use', 'in', 'our', 'calculations', 'a', 'schwarzschildde', 'sitter', 'vacuole', 'exactly', 'matched', 'into', 'a', 'friedmannrobertsonwalker', 'background', 'and', 'show', 'that', 'a', 'lambdacontribution', 'term', 'appears', 'in', 'the', 'deflection', 'angle', 'within', 'the', 'lens', 'equation', 'we', 'find', 'that', 'the', 'contribution', 'of', 'the', 'lambdaterm', 'to', 'the', 'bending', 'angle', 'is', 'larger', 'than', 'the', 'secondorder', 'term', 'for', 'many', 'lens', 'systems', 'using', 'these', 'observations', 'of', 'bending', 'angles', 'we', 'derive', 'new', 'limits', 'on', 'the', 'value', 'of', 'lambda', 'these', 'limits', 'constitute', 'the', 'best', 'observational', 'upper', 'bound', 'on', 'lambda', 'after', 'cosmological', 'constraints', 'and', 'are', 'only', 'two', 'orders', 'of', 'magnitude', 'away', 'from', 'the', 'value', 'determined', 'by', 'those', 'cosmological', 'constraints']] | [-0.15506135825794073, 0.07314534727039193, -0.0915119968729574, 0.06416256499620236, -0.12571489392434182, -0.10111584794764705, 0.002221543037291593, 0.33220556540613844, -0.1998690274667065, -0.3155651569085301, 0.07285380020588285, -0.29476652152648886, -0.074424895447673, 0.22527031011809157, 0.013118467432792363, 0.003526846397925848, 0.028782798762216507, 0.01368041822991375, -0.07448058441550758, -0.2350287759477425, 0.36742067030695436, 0.052933078587242645, 0.17069729902296849, 0.003411397463847069, 0.12654583897359623, -0.01020939396577155, -0.02437401928136465, 0.06884188475614449, -0.22745567053285906, 0.0797674070367203, 0.15400382030005538, 0.09327787816020772, 0.20039728016785854, -0.366272854507438, -0.19833304629362417, 0.06358311403800482, 0.11941533191012418, 0.14114974877495412, -0.012081419622947304, -0.3141165202690007, 0.04136728733608136, -0.14182550337388175, -0.15879896668564975, 0.03222212604707936, 0.016015570212460164, 0.0010837569668795328, -0.21967110692731356, 0.0910723698589037, 0.014823706721031817, -0.023302750571774767, -0.1076335800290342, -0.13006626337813507, 0.001397176330862274, 0.09184725887622426, 0.08354817303454024, 0.02101279157887465, 0.1363339306180418, -0.1471558169479359, -0.035336001541863823, 0.43909300350636804, -0.13098662673928058, -0.1914947879397817, 0.09439386630506963, -0.16494279262264194, -0.117531385322529, 0.11697972564132146, 0.15983073320239782, 0.11764293343982653, -0.14329352136994214, 0.10592985780998983, -0.0035965343741055744, 0.22166045119476346, 0.10244000883942833, 0.018383401049298833, 0.293723968343821, 0.10584449086853731, 0.07545781386803847, 0.09855719830301947, -0.11261663123168661, -0.0735082849999304, -0.3370618155729846, -0.10580018115758533, -0.1546147374711556, 0.09691519945649044, -0.17625273901754301, -0.1312626938058928, 0.3092919494956732, 0.13034893108426399, 0.20428625642140424, 0.0909241150688298, 0.30214491065989874, 0.0983425603576192, 0.07460217609117101, 0.043766775720536055, 0.3914167426743269, 0.12535791576740407, 0.05916759505891388, -0.20627652771724095, -0.006640638769516405, 0.06134254581868977] |
710.4727 | Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated
Oscillator Clock-Recovery Circuit | We present a complete top-down design of a low-power multi-channel clock
recovery circuit based on gated current-controlled oscillators. The flow
includes several tools and methods used to specify block constraints, to design
and verify the topology down to the transistor level, as well as to achieve a
power consumption as low as 5mW/Gbit/s. Statistical simulation is used to
estimate the achievable bit error rate in presence of phase and frequency
errors and to prove the feasibility of the concept. VHDL modeling provides
extensive verification of the topology. Thermal noise modeling based on
well-known concepts delivers design parameters for the device sizing and
biasing. We present two practical examples of possible design improvements
analyzed and implemented with this methodology.
| cs.AR | we present a complete topdown design of a lowpower multichannel clock recovery circuit based on gated currentcontrolled oscillators the flow includes several tools and methods used to specify block constraints to design and verify the topology down to the transistor level as well as to achieve a power consumption as low as 5mwgbits statistical simulation is used to estimate the achievable bit error rate in presence of phase and frequency errors and to prove the feasibility of the concept vhdl modeling provides extensive verification of the topology thermal noise modeling based on wellknown concepts delivers design parameters for the device sizing and biasing we present two practical examples of possible design improvements analyzed and implemented with this methodology | [['we', 'present', 'a', 'complete', 'topdown', 'design', 'of', 'a', 'lowpower', 'multichannel', 'clock', 'recovery', 'circuit', 'based', 'on', 'gated', 'currentcontrolled', 'oscillators', 'the', 'flow', 'includes', 'several', 'tools', 'and', 'methods', 'used', 'to', 'specify', 'block', 'constraints', 'to', 'design', 'and', 'verify', 'the', 'topology', 'down', 'to', 'the', 'transistor', 'level', 'as', 'well', 'as', 'to', 'achieve', 'a', 'power', 'consumption', 'as', 'low', 'as', '5mwgbits', 'statistical', 'simulation', 'is', 'used', 'to', 'estimate', 'the', 'achievable', 'bit', 'error', 'rate', 'in', 'presence', 'of', 'phase', 'and', 'frequency', 'errors', 'and', 'to', 'prove', 'the', 'feasibility', 'of', 'the', 'concept', 'vhdl', 'modeling', 'provides', 'extensive', 'verification', 'of', 'the', 'topology', 'thermal', 'noise', 'modeling', 'based', 'on', 'wellknown', 'concepts', 'delivers', 'design', 'parameters', 'for', 'the', 'device', 'sizing', 'and', 'biasing', 'we', 'present', 'two', 'practical', 'examples', 'of', 'possible', 'design', 'improvements', 'analyzed', 'and', 'implemented', 'with', 'this', 'methodology']] | [-0.135797946425314, -0.01585997924861363, -0.045169695029751614, 0.02231865253749216, -0.06795417464489484, -0.18612924481256524, 0.10485479175550942, 0.39200984310900044, -0.24822782061229914, -0.33970405510029733, 0.1339833073787646, -0.19797666643897438, -0.15744064909726396, 0.2757032068732839, -0.11301678866466396, 0.11925710143887588, 0.03310016945251224, -0.010808404052478826, -0.06923866549354549, -0.19807253087448895, 0.21433362171340448, 0.13681019998641095, 0.3477756411123734, 0.03161427744417491, 0.14203847282860652, -0.010893330766031375, -0.01933688634576706, -0.001142476725145283, -0.12819497849847963, 0.12281535282874337, 0.27165748162640846, 0.1436772658390144, 0.2596513988115849, -0.45122988653393126, -0.22719587510427794, 0.03168066013226301, 0.0922703452519754, 0.10346328277682137, -0.07435763463712274, -0.2458582559489032, 0.10433234144639, -0.18765568104970595, -0.07284101113103904, -0.11442026331260577, -0.04900545913439531, 0.041306316526208676, -0.295433053563739, 0.0017762827949646192, 0.043403913801273286, 0.03735031319670697, -0.0012270141886467608, -0.1264903008048303, 0.026821431988436315, 0.16969203978824693, -0.029307908535751905, -0.02235694675339171, 0.19140168754622722, -0.06892554114700064, -0.17219938326459855, 0.3698387774997033, -0.0541625125025216, -0.20764534540760976, 0.17004156647086877, -0.041232595088867806, -0.11027045373239705, 0.07872126056836584, 0.231640797904414, 0.051895723536881246, -0.16597690434855783, 0.025745708087676115, 0.0774046065699723, 0.21622266978399557, 0.025392883067202363, 0.08734052865487388, 0.16237284410267305, 0.2790963747180425, 0.0687989248918035, 0.20482951825341353, -0.12649021990016165, -0.07299172594938348, -0.29660082053946346, -0.11129457000881815, -0.16350558537464494, 0.02003489457604149, -0.05569574026252605, -0.15725062268539372, 0.4161820965301659, 0.2140375846145181, 0.1379023289037311, 0.0779239166703107, 0.3989512942349299, 0.09684407850727439, 0.039542734750315674, 0.055421444123738214, 0.20905723170035034, 0.14325396547046226, 0.10455732291930506, -0.23055626836040208, 0.036287521014117405, 0.017507837981813483] |
710.4728 | Energy-Aware Routing for E-Textile Applications | As the scale of electronic devices shrinks, "electronic textiles"
(e-textiles) will make possible a wide variety of novel applications which are
currently unfeasible. Due to the wearability concerns, low-power techniques are
critical for e-textile applications. In this paper, we address the issue of the
energy-aware routing for e-textile platforms and propose an efficient algorithm
to solve it. The platform we consider consists of dedicated components for
e-textiles, including computational modules, dedicated transmission lines and
thin-film batteries on fiber substrates. Furthermore, we derive an analytical
upper bound for the achievable number of jobs completed over all possible
routing strategies. From a practical standpoint, for the Advanced Encryption
Standard (AES) cipher, the routing technique we propose achieves about fifty
percent of this analytical upper bound. Moreover, compared to the
non-energy-aware counterpart, our routing technique increases the number of
encryption jobs completed by one order of magnitude.
| cs.AR | as the scale of electronic devices shrinks electronic textiles etextiles will make possible a wide variety of novel applications which are currently unfeasible due to the wearability concerns lowpower techniques are critical for etextile applications in this paper we address the issue of the energyaware routing for etextile platforms and propose an efficient algorithm to solve it the platform we consider consists of dedicated components for etextiles including computational modules dedicated transmission lines and thinfilm batteries on fiber substrates furthermore we derive an analytical upper bound for the achievable number of jobs completed over all possible routing strategies from a practical standpoint for the advanced encryption standard aes cipher the routing technique we propose achieves about fifty percent of this analytical upper bound moreover compared to the nonenergyaware counterpart our routing technique increases the number of encryption jobs completed by one order of magnitude | [['as', 'the', 'scale', 'of', 'electronic', 'devices', 'shrinks', 'electronic', 'textiles', 'etextiles', 'will', 'make', 'possible', 'a', 'wide', 'variety', 'of', 'novel', 'applications', 'which', 'are', 'currently', 'unfeasible', 'due', 'to', 'the', 'wearability', 'concerns', 'lowpower', 'techniques', 'are', 'critical', 'for', 'etextile', 'applications', 'in', 'this', 'paper', 'we', 'address', 'the', 'issue', 'of', 'the', 'energyaware', 'routing', 'for', 'etextile', 'platforms', 'and', 'propose', 'an', 'efficient', 'algorithm', 'to', 'solve', 'it', 'the', 'platform', 'we', 'consider', 'consists', 'of', 'dedicated', 'components', 'for', 'etextiles', 'including', 'computational', 'modules', 'dedicated', 'transmission', 'lines', 'and', 'thinfilm', 'batteries', 'on', 'fiber', 'substrates', 'furthermore', 'we', 'derive', 'an', 'analytical', 'upper', 'bound', 'for', 'the', 'achievable', 'number', 'of', 'jobs', 'completed', 'over', 'all', 'possible', 'routing', 'strategies', 'from', 'a', 'practical', 'standpoint', 'for', 'the', 'advanced', 'encryption', 'standard', 'aes', 'cipher', 'the', 'routing', 'technique', 'we', 'propose', 'achieves', 'about', 'fifty', 'percent', 'of', 'this', 'analytical', 'upper', 'bound', 'moreover', 'compared', 'to', 'the', 'nonenergyaware', 'counterpart', 'our', 'routing', 'technique', 'increases', 'the', 'number', 'of', 'encryption', 'jobs', 'completed', 'by', 'one', 'order', 'of', 'magnitude']] | [-0.1982298354529082, 0.025219076853253752, -0.025233966933731783, 0.02298591598861765, -0.0744130510328245, -0.1946857265669007, 0.11417487962254, 0.3876661027497645, -0.2568974222786434, -0.3353170818312371, 0.13496879706446557, -0.2570400056660387, -0.1357522490079323, 0.2678976693332644, -0.10153341288711373, 0.1132563464409599, 0.043140303909923905, -0.008214716376829231, -0.029143573875631476, -0.2811295116412724, 0.26706514227474837, 0.07277775547922925, 0.33920881578183554, 0.07212135917341984, 0.07827733259595243, 0.009546596190317514, -0.021830511170419606, -0.05236982652943925, -0.1601232644236574, 0.15835120216844248, 0.29697562990617665, 0.14870028480134428, 0.2882924834200254, -0.45464750891881633, -0.18520448252670996, 0.08643039389090705, 0.16051526761329765, 0.1110057809632866, -0.07040113339890851, -0.22023121199194104, 0.12187823309919778, -0.23092696177013589, -0.10810929361938462, -0.07226374372179416, -0.008037417217204017, 0.0026418602437520704, -0.2308803332427926, -0.01971569461814055, -0.02652299109555728, 0.024121146972360525, -0.03291033388824278, -0.12634059807932968, 0.08570204107982522, 0.10987824560902643, -0.003934543960437126, -0.029184378823100304, 0.14183504292774443, -0.12378225273432884, -0.16092841254864285, 0.3901675859770031, 0.00186873968040029, -0.11089170815304239, 0.1407258054258051, 0.003849548495751112, -0.1288997794987373, 0.13234957703133796, 0.2198740287505566, 0.12021059038923353, -0.15496665214647454, 0.05923615385949982, 0.00340194110461372, 0.17651061395989032, 0.06852121552756281, 0.08857647632909212, 0.14169292184293059, 0.2466953222553992, 0.14241428270143192, 0.1607619193238074, -0.08894028277004283, -0.06745500437641212, -0.222540189142187, -0.19707869108624307, -0.1660104568904028, 0.03786732519626723, -0.06737918563906255, -0.14228343085265316, 0.3747460336642379, 0.20870530946140595, 0.11602796305710754, 0.062013872186587264, 0.3906364099565127, 0.05820312858592217, 0.08650039811329652, 0.11233809634593996, 0.20246058491517704, 0.07578814265857771, 0.12309365472153609, -0.1510588988960648, 0.07249555847085748, 0.02462388697271863] |
710.4729 | Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled
Bulk-CMOS Logic Circuits | In nanometer scaled CMOS devices significant increase in the subthreshold,
the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage,
results in the large increase of total leakage power in a logic circuit.
Leakage components interact with each other in device level (through device
geometry, doping profile) and also in the circuit level (through node
voltages). Due to the circuit level interaction of the different leakage
components, the leakage of a logic gate strongly depends on the circuit
topology i.e. number and nature of the other logic gates connected to its input
and output. In this paper, for the first time, we have analyzed loading effect
on leakage and proposed a method to accurately estimate the total leakage in a
logic circuit, from its logic level description considering the impact of
loading and transistor stacking.
| cs.AR | in nanometer scaled cmos devices significant increase in the subthreshold the gate and the reverse biased junction bandtobandtunneling btbt leakage results in the large increase of total leakage power in a logic circuit leakage components interact with each other in device level through device geometry doping profile and also in the circuit level through node voltages due to the circuit level interaction of the different leakage components the leakage of a logic gate strongly depends on the circuit topology ie number and nature of the other logic gates connected to its input and output in this paper for the first time we have analyzed loading effect on leakage and proposed a method to accurately estimate the total leakage in a logic circuit from its logic level description considering the impact of loading and transistor stacking | [['in', 'nanometer', 'scaled', 'cmos', 'devices', 'significant', 'increase', 'in', 'the', 'subthreshold', 'the', 'gate', 'and', 'the', 'reverse', 'biased', 'junction', 'bandtobandtunneling', 'btbt', 'leakage', 'results', 'in', 'the', 'large', 'increase', 'of', 'total', 'leakage', 'power', 'in', 'a', 'logic', 'circuit', 'leakage', 'components', 'interact', 'with', 'each', 'other', 'in', 'device', 'level', 'through', 'device', 'geometry', 'doping', 'profile', 'and', 'also', 'in', 'the', 'circuit', 'level', 'through', 'node', 'voltages', 'due', 'to', 'the', 'circuit', 'level', 'interaction', 'of', 'the', 'different', 'leakage', 'components', 'the', 'leakage', 'of', 'a', 'logic', 'gate', 'strongly', 'depends', 'on', 'the', 'circuit', 'topology', 'ie', 'number', 'and', 'nature', 'of', 'the', 'other', 'logic', 'gates', 'connected', 'to', 'its', 'input', 'and', 'output', 'in', 'this', 'paper', 'for', 'the', 'first', 'time', 'we', 'have', 'analyzed', 'loading', 'effect', 'on', 'leakage', 'and', 'proposed', 'a', 'method', 'to', 'accurately', 'estimate', 'the', 'total', 'leakage', 'in', 'a', 'logic', 'circuit', 'from', 'its', 'logic', 'level', 'description', 'considering', 'the', 'impact', 'of', 'loading', 'and', 'transistor', 'stacking']] | [-0.17242390866071652, 0.06719483693178965, 0.004521753722384794, 0.002100529714744649, -0.0037012526265053605, -0.19616725257556164, 0.1361417283083368, 0.36614964813438816, -0.2832341640527402, -0.36145080584309885, 0.03841265107838632, -0.29219097938777794, -0.10079264534948353, 0.225598955940483, -0.08800427907462746, 0.038556009418949655, -0.010681517978212726, -0.0025600990864323146, -0.024322380004242174, -0.20819533211457084, 0.23224554209511228, 0.06654609915619689, 0.34632165008919563, 0.08403570910762828, 0.09749053270250226, -0.026186332808557287, 0.0481133290441401, 0.05007593167090872, -0.03891546542603356, 0.0928205204554208, 0.24379276427998095, 0.08818225282654445, 0.22656857069414943, -0.5240834978089404, -0.15946294960162755, 0.026608107715789506, 0.08739781099347287, 0.12630231918266682, -0.0245885895599903, -0.25244977689389864, 0.08512450614596592, -0.20574142686925384, -0.01674169067581403, 0.014369750669948868, 0.03730183681334132, 0.05432765806483021, -0.1878945278872583, 0.00593334402165327, 0.08009929053221287, 0.02970821518145168, 0.0029638716815267134, -0.07861769842913499, -0.03497684783121543, 0.12838635362733378, -0.06271081977548189, -0.00210120546919947, 0.255214235317935, -0.15265759361261474, -0.1286950244554388, 0.25899431267544737, -0.04423416797210699, -0.19251885081540598, 0.09392778757341039, -0.16322413907358563, -0.06510809410377336, 0.1167642454887782, 0.1919896148228601, 0.024495821957017726, -0.13890622798075428, 0.08014673173493608, 0.09693601560334104, 0.2578675314512993, 0.0800006111889188, 0.09101080110491212, 0.18683044607542568, 0.21042767688701514, 0.0767768462953712, 0.18361270042925157, -0.09915293646614075, -0.04204244361130465, -0.31537004178667916, -0.1289901074730972, -0.15585765409380642, 0.06211512536157979, -0.06513314429299608, -0.17469453521649728, 0.46735260217214253, 0.20126599825070754, 0.16758923749647922, 0.03148758308544977, 0.40868693929332406, 0.18295055954133285, 0.13374082764624548, 0.026720822284779157, 0.203054991237986, 0.1709389082823338, 0.08962810400581515, -0.2911613808750217, 0.11753225720960146, -0.05535839149144603] |
710.473 | Strange hadron yields and ratios in heavy ion collisions at RHIC energy | Recent experimental data support the presence of quark coalescence in heavy
ion collisions at RHIC energies. Hadronization of quark matter and hadron
formation in heavy ion collisions can be described by the coalescence process,
and measured data are reproduced successfully. On the other hand, the
theoretical coalescence calculations are based on a non-relativistic
description. Here we investigate the robustness of the coalescence description,
using different wave-function overlap during hadron formation.
| nucl-th | recent experimental data support the presence of quark coalescence in heavy ion collisions at rhic energies hadronization of quark matter and hadron formation in heavy ion collisions can be described by the coalescence process and measured data are reproduced successfully on the other hand the theoretical coalescence calculations are based on a nonrelativistic description here we investigate the robustness of the coalescence description using different wavefunction overlap during hadron formation | [['recent', 'experimental', 'data', 'support', 'the', 'presence', 'of', 'quark', 'coalescence', 'in', 'heavy', 'ion', 'collisions', 'at', 'rhic', 'energies', 'hadronization', 'of', 'quark', 'matter', 'and', 'hadron', 'formation', 'in', 'heavy', 'ion', 'collisions', 'can', 'be', 'described', 'by', 'the', 'coalescence', 'process', 'and', 'measured', 'data', 'are', 'reproduced', 'successfully', 'on', 'the', 'other', 'hand', 'the', 'theoretical', 'coalescence', 'calculations', 'are', 'based', 'on', 'a', 'nonrelativistic', 'description', 'here', 'we', 'investigate', 'the', 'robustness', 'of', 'the', 'coalescence', 'description', 'using', 'different', 'wavefunction', 'overlap', 'during', 'hadron', 'formation']] | [-0.027061333447428688, 0.26462136409910664, -0.1708951554460717, 0.13215722584461348, 0.004929008148610592, -0.07854442801991744, -0.036894512149904454, 0.3376598374652011, -0.1545913726557046, -0.2806463706174067, -0.016526087636261115, -0.31713582849396127, 0.08615605280002846, 0.1280703008540773, 0.08974413381490325, 0.09173878394067288, 0.18775600721793514, -0.001199605276009866, -0.06859497277598296, -0.2106124569528869, 0.3136039624888716, 0.10304576455216323, 0.24820258552873772, 0.20242143291980028, 0.004372019962673741, 0.041511923181159156, -0.026409965607204607, -0.0194941154481577, -0.12599210601433047, 0.04492450251460208, 0.2271721695832509, 0.06356620811192053, 0.13615551021482264, -0.4845951854650463, -0.21802498275355903, 0.03056263229144471, 0.14578325328017985, 0.1842044677053179, -0.14341706491541117, -0.2752986922061869, 0.07234275917123471, -0.24784869855003697, -0.14458342982855227, -0.08990312412913357, -0.031997028957786305, 0.043587863691417233, -0.26755148168387155, 0.11404565878744637, -0.0367305113135704, 0.019053557317965895, -0.035817667901782056, -0.15579982631440673, -0.10089837182978434, -0.03229281875704016, 0.057701776921333346, 0.06965378343925945, 0.23571842309486654, -0.12660678207674728, -0.18173729870135763, 0.4146187477878162, -0.013115082770985153, -0.11082778466599329, 0.2549567738847275, -0.2170733842533082, -0.18329414022820337, 0.12559739678565945, 0.27867646625797665, 0.07951991354514445, -0.19816184796925101, 0.020493334337308104, 0.012101491547322698, 0.12354056272275298, 0.14390902565792202, 0.043111308138551456, 0.27442907943789446, 0.3010378110605026, -0.16490849307073013, 0.04796375025388053, -0.09760360951269312, -0.14534942632141923, -0.3725059985050133, -0.04061153837413128, -0.19367078671764051, 0.0027128640562295915, -0.06726451713683283, -0.06116520262190274, 0.3679858065875513, 0.10831814067039107, 0.28608501850228224, -0.06629447652625718, 0.3113636822040592, 0.06174829812454326, 0.009342967426138264, 0.07622354319984359, 0.28613939540726796, 0.14677784177142061, 0.13245092273822853, -0.31440954277557986, 0.10448201449887295, 0.08836247914337686] |
710.4731 | Leakage-Aware Interconnect for On-Chip Network | On-chip networks have been proposed as the interconnect fabric for future
systems-on-chip and multi-processors on chip. Power is one of the main
constraints of these systems and interconnect consumes a significant portion of
the power budget. In this paper, we propose four leakage-aware interconnect
schemes. Our schemes achieve 10.13%~63.57% active leakage savings and
12.35%~95.96% standby leakage savings across schemes while the delay penalty
ranges from 0% to 4.69%.
| cs.AR | onchip networks have been proposed as the interconnect fabric for future systemsonchip and multiprocessors on chip power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget in this paper we propose four leakageaware interconnect schemes our schemes achieve 10136357 active leakage savings and 12359596 standby leakage savings across schemes while the delay penalty ranges from 0 to 469 | [['onchip', 'networks', 'have', 'been', 'proposed', 'as', 'the', 'interconnect', 'fabric', 'for', 'future', 'systemsonchip', 'and', 'multiprocessors', 'on', 'chip', 'power', 'is', 'one', 'of', 'the', 'main', 'constraints', 'of', 'these', 'systems', 'and', 'interconnect', 'consumes', 'a', 'significant', 'portion', 'of', 'the', 'power', 'budget', 'in', 'this', 'paper', 'we', 'propose', 'four', 'leakageaware', 'interconnect', 'schemes', 'our', 'schemes', 'achieve', '10136357', 'active', 'leakage', 'savings', 'and', '12359596', 'standby', 'leakage', 'savings', 'across', 'schemes', 'while', 'the', 'delay', 'penalty', 'ranges', 'from', '0', 'to', '469']] | [-0.21203538743922343, -0.02570978509118924, 0.009480460690191159, -0.04837698088242458, -0.02605967104721528, -0.19986102197749112, 0.11206320434844551, 0.4290624608214085, -0.22365989060356067, -0.35939773416433196, 0.10706612081087839, -0.28614888761479124, -0.07247078668039579, 0.26431047363350024, -0.11244190586014435, 0.0844483970449521, 0.013533560157968447, -0.05784383608171573, -0.021839799767789932, -0.2866389274382247, 0.23733142396578422, 0.09722479994480426, 0.3854203317887508, 0.08140111712138885, 0.1378427866147831, -0.1411606479364519, -0.006149750331846567, -0.04318155744113028, -0.036909238275480816, 0.16700410720390768, 0.2939116152433249, 0.11775639262408591, 0.35069479724535574, -0.4866492163389921, -0.25090403916994825, 0.11648889175401284, 0.13947033271766626, 0.05327743771485984, -0.04013415563744135, -0.1700174307450652, 0.12348047297430009, -0.27987830322235824, 0.00947117883210572, -0.04684382891998841, 0.008764002185601454, 0.06895459997736347, -0.23413213270788008, 0.023723026938163316, -0.0014295921732599918, -0.014337049424648285, -0.01914569095063668, -0.15646143057562698, 0.017853943398222327, 0.1533283134850745, -0.03107980933541862, -0.03185252293657798, 0.1616038213054148, -0.09862596817099704, -0.14918956515880732, 0.37620559019538075, 0.013608885957644536, -0.1563519285669407, 0.11028895621689466, -0.014227351560615576, -0.09966701686812135, 0.12415894807244722, 0.26811801031805, 0.04509857692397558, -0.10467363701990018, 0.039917852526279884, 0.07057057423338008, 0.23329810677812649, 0.0534519512206316, 0.1359231349080801, 0.16352775268829786, 0.22113063417088527, 0.1443579692286081, 0.14569346518882623, -0.12777676310461875, -0.07644090744881676, -0.2778847990700832, -0.1473200378509668, -0.12557652670030411, 0.015701279072807384, -0.0899864054779755, -0.05304447292851714, 0.3746007904696923, 0.1583651232891358, 0.11044140991110069, 0.09950457625046301, 0.4590475087555555, 0.08554692045570567, 0.1867435473232315, 0.1310371118454406, 0.232593119975466, 0.03632469109904308, 0.19499753281975596, -0.2308429240499838, 0.03576678274772488, -0.07049061783517782] |
710.4732 | Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless
Microsensor Networks: Modeling and Improvement Perspectives | Wireless microsensor networks, which have been the topic of intensive
research in recent years, are now emerging in industrial applications. An
important milestone in this transition has been the release of the IEEE
802.15.4 standard that specifies interoperable wireless physical and medium
access control layers targeted to sensor node radios. In this paper, we
evaluate the potential of an 802.15.4 radio for use in an ultra low power
sensor node operating in a dense network. Starting from measurements carried
out on the off-the-shelf radio, effective radio activation and link adaptation
policies are derived. It is shown that, in a typical sensor network scenario,
the average power per node can be reduced down to 211m mm mW. Next, the energy
consumption breakdown between the different phases of a packet transmission is
presented, indicating which part of the transceiver architecture can most
effectively be optimized in order to further reduce the radio power, enabling
self-powered wireless microsensor networks.
| cs.NI | wireless microsensor networks which have been the topic of intensive research in recent years are now emerging in industrial applications an important milestone in this transition has been the release of the ieee 802154 standard that specifies interoperable wireless physical and medium access control layers targeted to sensor node radios in this paper we evaluate the potential of an 802154 radio for use in an ultra low power sensor node operating in a dense network starting from measurements carried out on the offtheshelf radio effective radio activation and link adaptation policies are derived it is shown that in a typical sensor network scenario the average power per node can be reduced down to 211m mm mw next the energy consumption breakdown between the different phases of a packet transmission is presented indicating which part of the transceiver architecture can most effectively be optimized in order to further reduce the radio power enabling selfpowered wireless microsensor networks | [['wireless', 'microsensor', 'networks', 'which', 'have', 'been', 'the', 'topic', 'of', 'intensive', 'research', 'in', 'recent', 'years', 'are', 'now', 'emerging', 'in', 'industrial', 'applications', 'an', 'important', 'milestone', 'in', 'this', 'transition', 'has', 'been', 'the', 'release', 'of', 'the', 'ieee', '802154', 'standard', 'that', 'specifies', 'interoperable', 'wireless', 'physical', 'and', 'medium', 'access', 'control', 'layers', 'targeted', 'to', 'sensor', 'node', 'radios', 'in', 'this', 'paper', 'we', 'evaluate', 'the', 'potential', 'of', 'an', '802154', 'radio', 'for', 'use', 'in', 'an', 'ultra', 'low', 'power', 'sensor', 'node', 'operating', 'in', 'a', 'dense', 'network', 'starting', 'from', 'measurements', 'carried', 'out', 'on', 'the', 'offtheshelf', 'radio', 'effective', 'radio', 'activation', 'and', 'link', 'adaptation', 'policies', 'are', 'derived', 'it', 'is', 'shown', 'that', 'in', 'a', 'typical', 'sensor', 'network', 'scenario', 'the', 'average', 'power', 'per', 'node', 'can', 'be', 'reduced', 'down', 'to', '211m', 'mm', 'mw', 'next', 'the', 'energy', 'consumption', 'breakdown', 'between', 'the', 'different', 'phases', 'of', 'a', 'packet', 'transmission', 'is', 'presented', 'indicating', 'which', 'part', 'of', 'the', 'transceiver', 'architecture', 'can', 'most', 'effectively', 'be', 'optimized', 'in', 'order', 'to', 'further', 'reduce', 'the', 'radio', 'power', 'enabling', 'selfpowered', 'wireless', 'microsensor', 'networks']] | [-0.19048216962931497, 0.03736135962582569, -0.0091759437214463, -0.03906732941827466, -0.06705002613035181, -0.1905427205015815, 0.07180916325474579, 0.4305660211931794, -0.25902244159726484, -0.3164771750208832, 0.10204642033204436, -0.253895985169877, -0.17056329357287575, 0.18903676830607677, -0.07523669423835892, 0.08415169361152595, 0.03215229234417841, 0.019340310930725066, 0.014527262672181091, -0.22205395486295945, 0.22746923718180867, 0.16817951660843627, 0.3790926861817077, 0.05755734030577925, 0.07290216730607132, -0.050308391122868466, -0.04010572751323062, -0.04621024421536394, -0.04229442441973069, 0.1184116477567342, 0.3506804891531506, 0.13109070682717908, 0.28236775216796706, -0.4852144749714963, -0.30689630901380893, 0.09566555181067557, 0.160618951153611, 0.03440788221064835, -0.036765314377994546, -0.26062759305200267, 0.1495340076455426, -0.28742870084580874, -0.057522277155470466, 0.02742553815703779, -0.005079460354341614, 0.05589550917126959, -0.2651943338133635, -0.012831768347138178, -0.05460949235806061, 0.050402448206178604, -0.05063613389258183, -0.05662836086065058, 0.01255226224781044, 0.17163716447689842, -0.018082841927365912, 0.03959203963919032, 0.172571694595559, -0.1327842620737952, -0.11711752729099845, 0.37383147783937953, 0.017584667179823644, -0.1144821816304278, 0.1533522481279027, -0.03871595006175114, -0.16161415767405302, 0.10926291986158299, 0.24721521655878714, 0.03981067806241974, -0.21526500479949098, 0.029705817633376066, 0.02036054980220093, 0.16559384257172144, 0.0718994045930524, 0.07303236104029741, 0.2076448708171806, 0.2526472575121349, 0.12386269275729934, 0.12313081914288623, -0.14736159240015811, -0.07800817511705381, -0.2181441070421809, -0.1092314652768114, -0.22337223230410488, 0.06646649457754628, -0.07787320918775344, -0.06803106954377595, 0.415568900859404, 0.16522081836442193, 0.12697166829640347, 0.030470852502771924, 0.3841874158941209, 0.0977689343046457, 0.14141121710680665, 0.12674752481642268, 0.26243642445413334, 0.07660754705148358, 0.21387392073689449, -0.13649068894615818, 0.0516436485941672, -0.05029731747363844] |
710.4733 | Smart Temperature Sensor for Thermal Testing of Cell-Based ICs | In this paper we present a simple and efficient built-in temperature sensor
for thermal monitoring of standard-cell based VLSI circuits. The proposed smart
temperature sensor uses a ring-oscillator composed of complex gates instead of
inverters to optimize their linearity. Simulation results from a 0.18$\mu$m
CMOS technology show that the non-linearity error of the sensor can be reduced
when an adequate set of standard logic gates is selected.
| cs.AR | in this paper we present a simple and efficient builtin temperature sensor for thermal monitoring of standardcell based vlsi circuits the proposed smart temperature sensor uses a ringoscillator composed of complex gates instead of inverters to optimize their linearity simulation results from a 018mum cmos technology show that the nonlinearity error of the sensor can be reduced when an adequate set of standard logic gates is selected | [['in', 'this', 'paper', 'we', 'present', 'a', 'simple', 'and', 'efficient', 'builtin', 'temperature', 'sensor', 'for', 'thermal', 'monitoring', 'of', 'standardcell', 'based', 'vlsi', 'circuits', 'the', 'proposed', 'smart', 'temperature', 'sensor', 'uses', 'a', 'ringoscillator', 'composed', 'of', 'complex', 'gates', 'instead', 'of', 'inverters', 'to', 'optimize', 'their', 'linearity', 'simulation', 'results', 'from', 'a', '018mum', 'cmos', 'technology', 'show', 'that', 'the', 'nonlinearity', 'error', 'of', 'the', 'sensor', 'can', 'be', 'reduced', 'when', 'an', 'adequate', 'set', 'of', 'standard', 'logic', 'gates', 'is', 'selected']] | [-0.11981493455470738, 0.06238414945321644, -0.025696074745307367, -0.054426195255170264, -0.05787830349678794, -0.1922437911923749, 0.06171464361074014, 0.4105604688890956, -0.25468390799042856, -0.30894075257872994, 0.09849802168107337, -0.23644319027803387, -0.16059452935234841, 0.2725352048732792, -0.15489511864937164, 0.11290102564927304, 0.03232523408774851, -0.002247932536358183, -0.03810136543170577, -0.22176833114248107, 0.20282631435177542, 0.09211509209126234, 0.32926276084882294, 0.0020810415135752974, 0.14958313910403487, -0.02190496241250499, 0.023841118087258303, 0.027375130321491848, -0.045004253011663393, 0.1392586336464085, 0.2957226406415981, 0.1083150474834397, 0.25826394023147947, -0.4862422569598438, -0.17656622050245377, 0.0764934508496839, 0.07151978662207539, 0.07898640061135996, -0.08475282284515825, -0.2597552253159158, 0.1371451625230045, -0.19770218923363383, -0.07504501280191382, -0.06878792256060423, -0.0010068927411780212, 0.05222092201989709, -0.30560089053699013, -0.01669641694223339, 0.05268354090212873, 0.0670530187657498, 0.008365081397421432, -0.09322959286245433, 0.007324906845689949, 0.0917116270853016, -0.14706575594292107, -0.028766165580953275, 0.24423708829492558, -0.07409641580924278, -0.15261196415645606, 0.31011967637195165, -0.006690676272917313, -0.15754833803371046, 0.11362170957903744, -0.016658835550487944, -0.08494831872821758, 0.09397982032687376, 0.19055577050047842, 0.0826856411612508, -0.21262595124977507, 0.07396882499310639, 0.04877586400305683, 0.2649516564843273, 0.020379648967222733, 0.05690118580859042, 0.17912166837997961, 0.2722172065264066, 0.08465446401951891, 0.1702816681389584, -0.08971847462905289, -0.038468828103787295, -0.3014882128036609, -0.16034185214701926, -0.23179990283538107, 0.05344917043817766, -0.09132187468132928, -0.18396601182493297, 0.40737884994031803, 0.22438451481954844, 0.12301880941077163, 0.07812755014465163, 0.39507546388741693, 0.12454010589797028, 0.14442302136696084, 0.03767756189953423, 0.21058468325910243, 0.10668196639215405, 0.1440155359662392, -0.20118030839754888, 0.04561558535505989, -0.02153789020270448] |
710.4734 | Computational Intelligence Characterization Method of Semiconductor
Device | Characterization of semiconductor devices is used to gather as much data
about the device as possible to determine weaknesses in design or trends in the
manufacturing process. In this paper, we propose a novel multiple trip point
characterization concept to overcome the constraint of single trip point
concept in device characterization phase. In addition, we use computational
intelligence techniques (e.g. neural network, fuzzy and genetic algorithm) to
further manipulate these sets of multiple trip point values and tests based on
semiconductor test equipments, Our experimental results demonstrate an
excellent design parameter variation analysis in device characterization phase,
as well as detection of a set of worst case tests that can provoke the worst
case variation, while traditional approach was not capable of detecting them.
| cs.AI cs.NE | characterization of semiconductor devices is used to gather as much data about the device as possible to determine weaknesses in design or trends in the manufacturing process in this paper we propose a novel multiple trip point characterization concept to overcome the constraint of single trip point concept in device characterization phase in addition we use computational intelligence techniques eg neural network fuzzy and genetic algorithm to further manipulate these sets of multiple trip point values and tests based on semiconductor test equipments our experimental results demonstrate an excellent design parameter variation analysis in device characterization phase as well as detection of a set of worst case tests that can provoke the worst case variation while traditional approach was not capable of detecting them | [['characterization', 'of', 'semiconductor', 'devices', 'is', 'used', 'to', 'gather', 'as', 'much', 'data', 'about', 'the', 'device', 'as', 'possible', 'to', 'determine', 'weaknesses', 'in', 'design', 'or', 'trends', 'in', 'the', 'manufacturing', 'process', 'in', 'this', 'paper', 'we', 'propose', 'a', 'novel', 'multiple', 'trip', 'point', 'characterization', 'concept', 'to', 'overcome', 'the', 'constraint', 'of', 'single', 'trip', 'point', 'concept', 'in', 'device', 'characterization', 'phase', 'in', 'addition', 'we', 'use', 'computational', 'intelligence', 'techniques', 'eg', 'neural', 'network', 'fuzzy', 'and', 'genetic', 'algorithm', 'to', 'further', 'manipulate', 'these', 'sets', 'of', 'multiple', 'trip', 'point', 'values', 'and', 'tests', 'based', 'on', 'semiconductor', 'test', 'equipments', 'our', 'experimental', 'results', 'demonstrate', 'an', 'excellent', 'design', 'parameter', 'variation', 'analysis', 'in', 'device', 'characterization', 'phase', 'as', 'well', 'as', 'detection', 'of', 'a', 'set', 'of', 'worst', 'case', 'tests', 'that', 'can', 'provoke', 'the', 'worst', 'case', 'variation', 'while', 'traditional', 'approach', 'was', 'not', 'capable', 'of', 'detecting', 'them']] | [-0.09639220983503506, 0.016683011125297204, -0.060896843521585385, 0.0415900805275757, -0.1029449354842185, -0.17965326279461866, 0.1219597703386699, 0.40687504317611456, -0.26544940753674673, -0.3591183992515829, 0.09799177228705958, -0.26500828795495535, -0.214752004864896, 0.2466680874030346, -0.1296740435777352, 0.09839668421127792, 0.05814673024560175, -0.007291174238367427, -0.046386479143327435, -0.22485581992734824, 0.2630798819084321, 0.07804669992202112, 0.34939036143553115, 0.03250169659206163, 0.06166691851385328, 0.017548640164726924, -0.015458437260906888, 0.006747593693885832, -0.10511023043088039, 0.10442770258223097, 0.29406816235578226, 0.17165632556838495, 0.31050715063728634, -0.44372733855139346, -0.20222901082747885, 0.10998656878796136, 0.12669984126806677, 0.08598369260829303, -0.06113653518203195, -0.26050836971074703, 0.09563291441619155, -0.1559631485649715, -0.12027484891105784, -0.10122233848725896, -0.03932748885539871, 0.005211670927594476, -0.2530530096771526, -0.04164901334461906, 0.04291617047819009, 0.06839513566885744, -0.04470531149889857, -0.09231375942697688, 0.0534630311303772, 0.147988869078202, 0.010024775782620699, 0.0021180135550938786, 0.1661753618654104, -0.092646392706346, -0.19352642814215693, 0.3745979558255884, -0.029873060668075095, -0.17772077652813506, 0.17424223871691333, -0.08640447521822588, -0.12418475789919255, 0.08149454478857919, 0.22687056446222648, 0.0952970115073596, -0.19378334211726342, -0.010956737897246174, 0.014397233484252807, 0.17671762851809505, 0.07630893961721731, 0.06635594186598374, 0.1932955097872764, 0.2550839680517393, 0.09296822391690747, 0.16084055192655913, -0.12144148102308991, -0.07798977285640449, -0.26647771705756895, -0.18638457753132248, -0.1963897273244877, 0.0038353623288370025, -0.0762464665212094, -0.18162258993834257, 0.37766518006702104, 0.2116049832867218, 0.17745054392482065, 0.03213823384665433, 0.3484515864402056, 0.039293809891645534, 0.06732225202910241, -0.005012446687737059, 0.1891595312335994, 0.055040615674618994, 0.11330771933106946, -0.1748465358743429, 0.10320413858449508, 0.0002174666827364314] |
710.4735 | Worst-Case and Average-Case Analysis of n-Detection Test Sets | Test sets that detect each target fault n times (n-detection test sets) are
typically generated for restricted values of n due to the increase in test set
size with n. We perform both a worst-case analysis and an average-case analysis
to check the effect of restricting n on the unmodeled fault coverage of an
(arbitrary) n-detection test set. Our analysis is independent of any particular
test set or test generation approach. It is based on a specific set of target
faults and a specific set of untargeted faults. It shows that, depending on the
circuit, very large values of n may be needed to guarantee the detection of all
the untargeted faults. We discuss the implications of these results.
| cs.AR | test sets that detect each target fault n times ndetection test sets are typically generated for restricted values of n due to the increase in test set size with n we perform both a worstcase analysis and an averagecase analysis to check the effect of restricting n on the unmodeled fault coverage of an arbitrary ndetection test set our analysis is independent of any particular test set or test generation approach it is based on a specific set of target faults and a specific set of untargeted faults it shows that depending on the circuit very large values of n may be needed to guarantee the detection of all the untargeted faults we discuss the implications of these results | [['test', 'sets', 'that', 'detect', 'each', 'target', 'fault', 'n', 'times', 'ndetection', 'test', 'sets', 'are', 'typically', 'generated', 'for', 'restricted', 'values', 'of', 'n', 'due', 'to', 'the', 'increase', 'in', 'test', 'set', 'size', 'with', 'n', 'we', 'perform', 'both', 'a', 'worstcase', 'analysis', 'and', 'an', 'averagecase', 'analysis', 'to', 'check', 'the', 'effect', 'of', 'restricting', 'n', 'on', 'the', 'unmodeled', 'fault', 'coverage', 'of', 'an', 'arbitrary', 'ndetection', 'test', 'set', 'our', 'analysis', 'is', 'independent', 'of', 'any', 'particular', 'test', 'set', 'or', 'test', 'generation', 'approach', 'it', 'is', 'based', 'on', 'a', 'specific', 'set', 'of', 'target', 'faults', 'and', 'a', 'specific', 'set', 'of', 'untargeted', 'faults', 'it', 'shows', 'that', 'depending', 'on', 'the', 'circuit', 'very', 'large', 'values', 'of', 'n', 'may', 'be', 'needed', 'to', 'guarantee', 'the', 'detection', 'of', 'all', 'the', 'untargeted', 'faults', 'we', 'discuss', 'the', 'implications', 'of', 'these', 'results']] | [-0.1371050832743864, 0.0440316313430448, -0.013899516155067673, 0.04007412139604935, -0.04844966389907476, -0.13177664006033388, 0.10400629524364431, 0.3260680829357897, -0.18065820267806068, -0.36216513674833584, 0.14078157637009603, -0.27207919638842726, -0.09025373588451463, 0.22947837954235828, -0.04126497629918476, 0.08615524228090125, 0.08744578822252229, 0.062325202254976474, -0.023501367622620273, -0.31629604724848753, 0.2797598657695752, 0.054096666029375844, 0.29218750827523887, 0.021904381163195413, 0.050991071177184835, 4.8831672383806646e-05, -0.05199467524106049, 0.05855655014608453, -0.06707113684947566, 0.07629842454424271, 0.2248926880554511, 0.19588677933220464, 0.2657586965455204, -0.4162160560934462, -0.14586171351818958, 0.16344854567582026, 0.08081834190166913, 0.11209620823526484, 0.01090815824130152, -0.26506712193139154, 0.1689968535469638, -0.13780816526820835, -0.0974910950455337, -0.07537230976228403, 0.055828984858643294, 0.04910749111037988, -0.3152549321500537, -0.027100735391752843, 0.0712990216138717, 0.060158788095204495, -0.047529724235527024, -0.09764056357865532, 0.02288711975272904, 0.1340574920595361, 0.03535012018460876, 0.012918127708646476, 0.14796780943462592, -0.07989866681333281, -0.12142237077833304, 0.37508996824423474, -0.014102348540392187, -0.22249321645905829, 0.21455833884592876, -0.1306149929833527, -0.17289335543337542, 0.10662190213552716, 0.22603204675241667, 0.13429522974171346, -0.11627638083783129, 0.06685352666028894, -0.052447096802867375, 0.24224917167144963, 0.08299960603969347, 0.007439927293513066, 0.17202517778152981, 0.19856377904956093, 0.08387528889629449, 0.17036580405114457, -0.13054322991241565, -0.0023830228915008213, -0.3577898882297624, -0.12837529682323465, -0.20397499141892275, 0.04873098931613609, -0.13608196037637396, -0.20915943095221734, 0.37499286788396347, 0.20604908932522775, 0.21869482953523278, 0.08273958888414323, 0.2624526297689503, 0.08344729192235058, 0.042552618755616695, 0.07112778888012354, 0.17847557271170056, 0.03612847445118758, -0.03879373671455134, -0.21686354170863828, 0.11943790891295315, -0.014021767599858407] |
710.4736 | A New Embedded Measurement Structure for eDRAM Capacitor | The embedded DRAM (eDRAM) is more and more used in System On Chip (SOC). The
integration of the DRAM capacitor process into a logic process is challenging
to get satisfactory yields. The specific process of DRAM capacitor and the low
capacitance value (~30F) of this device induce problems of process monitoring
and failure analysis. We propose a new test structure to measure the
capacitance value of each DRAM cell capacitor in a DRAM array. This concept has
been validated by simulation on a 0.18$\mu$m eDRAM technology.
| cs.AR | the embedded dram edram is more and more used in system on chip soc the integration of the dram capacitor process into a logic process is challenging to get satisfactory yields the specific process of dram capacitor and the low capacitance value 30f of this device induce problems of process monitoring and failure analysis we propose a new test structure to measure the capacitance value of each dram cell capacitor in a dram array this concept has been validated by simulation on a 018mum edram technology | [['the', 'embedded', 'dram', 'edram', 'is', 'more', 'and', 'more', 'used', 'in', 'system', 'on', 'chip', 'soc', 'the', 'integration', 'of', 'the', 'dram', 'capacitor', 'process', 'into', 'a', 'logic', 'process', 'is', 'challenging', 'to', 'get', 'satisfactory', 'yields', 'the', 'specific', 'process', 'of', 'dram', 'capacitor', 'and', 'the', 'low', 'capacitance', 'value', '30f', 'of', 'this', 'device', 'induce', 'problems', 'of', 'process', 'monitoring', 'and', 'failure', 'analysis', 'we', 'propose', 'a', 'new', 'test', 'structure', 'to', 'measure', 'the', 'capacitance', 'value', 'of', 'each', 'dram', 'cell', 'capacitor', 'in', 'a', 'dram', 'array', 'this', 'concept', 'has', 'been', 'validated', 'by', 'simulation', 'on', 'a', '018mum', 'edram', 'technology']] | [-0.17648760187439622, 0.011183754603981095, -0.04798220640034689, -0.03912780717355952, -0.0420614805757342, -0.23113006292020574, 0.11422348945018124, 0.38727471723276025, -0.23105827600640408, -0.3185297999311896, 0.10230940296862494, -0.21643471414880716, -0.11346284006448352, 0.22817076562410768, -0.14671956394552527, 0.07502803714836345, 0.07309855209006107, -0.04719610604019288, 0.015565897031303714, -0.19742856692687116, 0.2263735231012106, 0.09805274084210396, 0.3374703243484392, 0.052304089781554305, 0.14637513171662303, -0.07743872975766221, 0.04043067128342741, -0.0009437727796680787, -0.07649168163428412, 0.12577367189668995, 0.23851764414678603, 0.08630933478638968, 0.31750211019397656, -0.4929084322470076, -0.1618365455610568, 0.024475144644213073, 0.05834808792501195, 0.058672823669279325, -0.04229217868414707, -0.23829041679992397, 0.1237194304847542, -0.24722581595620688, -0.022854277447742575, -0.05414177798529101, 0.001667859240928117, -0.02183847455855678, -0.2382541036431897, 0.0041691053165670705, 0.04575363984879326, 0.021665099947987234, -0.023989266003755963, -0.11045200672849793, 0.04233554997207487, 0.11155907723176128, -0.04102290032349308, 0.01224106257671819, 0.26403675090850276, -0.03484747152885093, -0.11819368254612474, 0.3180686653947786, 0.023525536950568065, -0.17892815385232955, 0.11058820418136961, -0.12630612424520007, -0.0789761948180111, 0.1236501070068163, 0.19648505851955098, 0.01475016474723816, -0.21438102326698272, 0.07196103399174343, 0.03017772106481168, 0.25161241297336184, 0.08242975093205185, 0.006442229559316354, 0.19405161872067872, 0.3283567241666948, 0.07280249802724403, 0.20234428975073732, -0.1060842132771059, -0.05771672206876032, -0.24785644088816994, -0.221928807884893, -0.20728382095968462, 0.05008856842468958, -0.07121907654714853, -0.20698903459398185, 0.4225314631291172, 0.17803742023037664, 0.13198869475985275, 0.02165591446134974, 0.3589207978809581, 0.12533590902629144, 0.20873385421411297, 0.027964520837892505, 0.1472370226155309, 0.09969299166353748, 0.23537582454874234, -0.1999157282469027, 0.10051612426691195, -0.00895236596081625] |
710.4737 | Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling | This paper presents new fast exact feasibility tests for uniprocessor
real-time systems using preemptive EDF scheduling. Task sets which are accepted
by previously described sufficient tests will be evaluated in nearly the same
time as with the old tests by the new algorithms. Many task sets are not
accepted by the earlier tests despite them beeing feasible. These task sets
will be evaluated by the new algorithms a lot faster than with known exact
feasibility tests. Therefore it is possible to use them for many applications
for which only sufficient test are suitable. Additionally this paper shows that
the best previous known sufficient test, the best known feasibility bound and
the best known approximation algorithm can be derived from these new tests. In
result this leads to an integrated schedulability theory for EDF.
| cs.OH | this paper presents new fast exact feasibility tests for uniprocessor realtime systems using preemptive edf scheduling task sets which are accepted by previously described sufficient tests will be evaluated in nearly the same time as with the old tests by the new algorithms many task sets are not accepted by the earlier tests despite them beeing feasible these task sets will be evaluated by the new algorithms a lot faster than with known exact feasibility tests therefore it is possible to use them for many applications for which only sufficient test are suitable additionally this paper shows that the best previous known sufficient test the best known feasibility bound and the best known approximation algorithm can be derived from these new tests in result this leads to an integrated schedulability theory for edf | [['this', 'paper', 'presents', 'new', 'fast', 'exact', 'feasibility', 'tests', 'for', 'uniprocessor', 'realtime', 'systems', 'using', 'preemptive', 'edf', 'scheduling', 'task', 'sets', 'which', 'are', 'accepted', 'by', 'previously', 'described', 'sufficient', 'tests', 'will', 'be', 'evaluated', 'in', 'nearly', 'the', 'same', 'time', 'as', 'with', 'the', 'old', 'tests', 'by', 'the', 'new', 'algorithms', 'many', 'task', 'sets', 'are', 'not', 'accepted', 'by', 'the', 'earlier', 'tests', 'despite', 'them', 'beeing', 'feasible', 'these', 'task', 'sets', 'will', 'be', 'evaluated', 'by', 'the', 'new', 'algorithms', 'a', 'lot', 'faster', 'than', 'with', 'known', 'exact', 'feasibility', 'tests', 'therefore', 'it', 'is', 'possible', 'to', 'use', 'them', 'for', 'many', 'applications', 'for', 'which', 'only', 'sufficient', 'test', 'are', 'suitable', 'additionally', 'this', 'paper', 'shows', 'that', 'the', 'best', 'previous', 'known', 'sufficient', 'test', 'the', 'best', 'known', 'feasibility', 'bound', 'and', 'the', 'best', 'known', 'approximation', 'algorithm', 'can', 'be', 'derived', 'from', 'these', 'new', 'tests', 'in', 'result', 'this', 'leads', 'to', 'an', 'integrated', 'schedulability', 'theory', 'for', 'edf']] | [-0.09323362910531853, 0.028793449223998242, -0.06417497204042467, 0.1115219763679696, -0.07559561828865592, -0.18547695968650224, 0.06904289676261631, 0.3847800897280301, -0.20817989673941656, -0.3718867780801777, 0.149266450622126, -0.17499282741236424, -0.14291669410229765, 0.30088647667850765, -0.08791687044392067, 0.15741550462684573, 0.10276383869314945, 0.013472053264372778, -0.04203962559393376, -0.3301324523789318, 0.2426699622065053, 0.0949312074011878, 0.3018683670018625, 0.016554498152205145, 0.029274402557403073, -0.040580550383748415, -0.029309287490463236, 0.04067880343435738, -0.10587960151681734, 0.09336505853395938, 0.2791553255979364, 0.22105050991688455, 0.2836563125658864, -0.4162985890459521, -0.1614632567432814, 0.10588126137320485, 0.1476928101733495, 0.10364573646539864, -0.04931867899394181, -0.2767672485608916, 0.12643836678488923, -0.15246060073263662, -0.10636803447934133, -0.15290843885868116, -0.003705303954954882, 0.027973292679070755, -0.2752957775159494, 0.04140505470384501, 0.03036813960319623, 0.012154323223950271, -0.04252592727885043, -0.14490949961573893, 0.10866072832753784, 0.11325490140685238, 0.05035707221324451, 0.03443340827357304, 0.07293288874320854, -0.061950583313766835, -0.1811352940766435, 0.4011392610329658, -0.011672389847283336, -0.17491911679831915, 0.23524322436205147, -0.06689357884312258, -0.17357365466318184, 0.10430109130281646, 0.14005624282320864, 0.15719597895727738, -0.2439925660050117, 0.03883919486023452, -0.07761194590563164, 0.16964529179512783, 0.06317216372712606, -0.00853146928803701, 0.15574381283407374, 0.17968810181294506, 0.08166039302591514, 0.12812532266493382, 0.0013641275923271994, -0.06847533443286188, -0.31550402410986617, -0.11461014871282461, -0.1935683858871488, -0.022445866903635897, -0.04474284100384343, -0.1175182589952995, 0.35180323000969294, 0.19320598452639087, 0.11477497787936065, 0.09854105585149693, 0.3413473822288495, 0.09409555121757356, 0.07899026793980957, 0.11317253888180283, 0.25260669426873056, 0.04175891148808755, 0.06063583144862065, -0.1564013897808955, 0.10430935189772145, 0.033589661016332026] |
710.4738 | Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique | Complex applications implemented as Systems on Chip (SoCs) demand extensive
use of system level modeling and validation. Their implementation gathers a
large number of complex IP cores and advanced interconnection schemes, such as
hierarchical bus architectures or networks on chip (NoCs). Modeling
applications involves capturing its computation and communication
characteristics. Previously proposed communication weighted models (CWM)
consider only the application communication aspects. This work proposes a
communication dependence and computation model (CDCM) that can simultaneously
consider both aspects of an application. It presents a solution to the problem
of mapping applications on regular NoCs while considering execution time and
energy consumption. The use of CDCM is shown to provide estimated average
reductions of 40% in execution time, and 20% in energy consumption, for current
technologies.
| cs.AR | complex applications implemented as systems on chip socs demand extensive use of system level modeling and validation their implementation gathers a large number of complex ip cores and advanced interconnection schemes such as hierarchical bus architectures or networks on chip nocs modeling applications involves capturing its computation and communication characteristics previously proposed communication weighted models cwm consider only the application communication aspects this work proposes a communication dependence and computation model cdcm that can simultaneously consider both aspects of an application it presents a solution to the problem of mapping applications on regular nocs while considering execution time and energy consumption the use of cdcm is shown to provide estimated average reductions of 40 in execution time and 20 in energy consumption for current technologies | [['complex', 'applications', 'implemented', 'as', 'systems', 'on', 'chip', 'socs', 'demand', 'extensive', 'use', 'of', 'system', 'level', 'modeling', 'and', 'validation', 'their', 'implementation', 'gathers', 'a', 'large', 'number', 'of', 'complex', 'ip', 'cores', 'and', 'advanced', 'interconnection', 'schemes', 'such', 'as', 'hierarchical', 'bus', 'architectures', 'or', 'networks', 'on', 'chip', 'nocs', 'modeling', 'applications', 'involves', 'capturing', 'its', 'computation', 'and', 'communication', 'characteristics', 'previously', 'proposed', 'communication', 'weighted', 'models', 'cwm', 'consider', 'only', 'the', 'application', 'communication', 'aspects', 'this', 'work', 'proposes', 'a', 'communication', 'dependence', 'and', 'computation', 'model', 'cdcm', 'that', 'can', 'simultaneously', 'consider', 'both', 'aspects', 'of', 'an', 'application', 'it', 'presents', 'a', 'solution', 'to', 'the', 'problem', 'of', 'mapping', 'applications', 'on', 'regular', 'nocs', 'while', 'considering', 'execution', 'time', 'and', 'energy', 'consumption', 'the', 'use', 'of', 'cdcm', 'is', 'shown', 'to', 'provide', 'estimated', 'average', 'reductions', 'of', '40', 'in', 'execution', 'time', 'and', '20', 'in', 'energy', 'consumption', 'for', 'current', 'technologies']] | [-0.20030740820291656, -0.009494159312808045, 0.004600954279909289, 0.02930531323682971, -0.04327206941306349, -0.18238596767054613, 0.06663578588972072, 0.3932228893102185, -0.26812396773583885, -0.3895603776795835, 0.14560793480093825, -0.23241720375854794, -0.16561925524989582, 0.24279780417483876, -0.07689570732995853, 0.09925842456987158, 0.1008037390401284, -0.0019784808786854724, -0.035999128353882325, -0.2509933375011433, 0.24353096301750682, 0.07786715665938167, 0.3517770639571505, 0.06230422909697139, 0.12416279525306773, 0.025632560845631047, -0.04036355224188145, -0.03494686816584289, -0.05917118286281659, 0.15879217895718928, 0.2831154228845004, 0.19206718352767146, 0.29960704049686104, -0.47653821293961224, -0.2623888644696463, 0.08161607189709699, 0.1300159954679827, 0.04008098957090964, -0.04249543213849599, -0.23689613635916779, 0.05031743474168385, -0.23540142226994523, -0.06770043591239937, -0.08897561032696044, 0.03239342192191691, 0.04871461164855542, -0.2318105060773773, -0.010518171309637345, 0.0073651865794800405, 0.06554136001239948, -0.03382755487464459, -0.08033122727552777, 0.022189715468302007, 0.1363754431789029, -0.0446884304491379, -0.038946733767179983, 0.17345339980551866, -0.1317149023241477, -0.1765584248502368, 0.395800750187742, -0.002885972715656811, -0.18316055459776756, 0.21221484910181868, 0.009368340636232519, -0.14229981489933846, 0.06932901622863805, 0.2653808256353789, 0.06779892792607226, -0.15265192740362107, 0.08259891848197222, 0.06909393403315689, 0.20145917433404886, 0.04397648273649194, 0.0804598477926499, 0.1609741233448248, 0.2717034322686675, 0.08790464113973748, 0.13136336124455747, -0.07008456158058006, -0.13637776867906767, -0.2195461572004043, -0.1695376001146993, -0.17023966240325594, 0.0058523853635036845, -0.06475853977457059, -0.12974071629961567, 0.39674826110221023, 0.1712737029145767, 0.13390192847577778, 0.11583023250852598, 0.40642322720656915, 0.09469018974417169, 0.12013999209360682, 0.12375932091059602, 0.12414616873540832, 0.06282989860406311, 0.18728423919490864, -0.17032274920815163, 0.08001911090838353, -0.003311447829492693] |
710.4739 | Q-DPM: An Efficient Model-Free Dynamic Power Management Technique | When applying Dynamic Power Management (DPM) technique to pervasively
deployed embedded systems, the technique needs to be very efficient so that it
is feasible to implement the technique on low end processor and tight-budget
memory. Furthermore, it should have the capability to track time varying
behavior rapidly because the time varying is an inherent characteristic of real
world system. Existing methods, which are usually model-based, may not satisfy
the aforementioned requirements. In this paper, we propose a model-free DPM
technique based on Q-Learning. Q-DPM is much more efficient because it removes
the overhead of parameter estimator and mode-switch controller. Furthermore,
its policy optimization is performed via consecutive online trialing, which
also leads to very rapid response to time varying behavior.
| cs.OH | when applying dynamic power management dpm technique to pervasively deployed embedded systems the technique needs to be very efficient so that it is feasible to implement the technique on low end processor and tightbudget memory furthermore it should have the capability to track time varying behavior rapidly because the time varying is an inherent characteristic of real world system existing methods which are usually modelbased may not satisfy the aforementioned requirements in this paper we propose a modelfree dpm technique based on qlearning qdpm is much more efficient because it removes the overhead of parameter estimator and modeswitch controller furthermore its policy optimization is performed via consecutive online trialing which also leads to very rapid response to time varying behavior | [['when', 'applying', 'dynamic', 'power', 'management', 'dpm', 'technique', 'to', 'pervasively', 'deployed', 'embedded', 'systems', 'the', 'technique', 'needs', 'to', 'be', 'very', 'efficient', 'so', 'that', 'it', 'is', 'feasible', 'to', 'implement', 'the', 'technique', 'on', 'low', 'end', 'processor', 'and', 'tightbudget', 'memory', 'furthermore', 'it', 'should', 'have', 'the', 'capability', 'to', 'track', 'time', 'varying', 'behavior', 'rapidly', 'because', 'the', 'time', 'varying', 'is', 'an', 'inherent', 'characteristic', 'of', 'real', 'world', 'system', 'existing', 'methods', 'which', 'are', 'usually', 'modelbased', 'may', 'not', 'satisfy', 'the', 'aforementioned', 'requirements', 'in', 'this', 'paper', 'we', 'propose', 'a', 'modelfree', 'dpm', 'technique', 'based', 'on', 'qlearning', 'qdpm', 'is', 'much', 'more', 'efficient', 'because', 'it', 'removes', 'the', 'overhead', 'of', 'parameter', 'estimator', 'and', 'modeswitch', 'controller', 'furthermore', 'its', 'policy', 'optimization', 'is', 'performed', 'via', 'consecutive', 'online', 'trialing', 'which', 'also', 'leads', 'to', 'very', 'rapid', 'response', 'to', 'time', 'varying', 'behavior']] | [-0.1010069314770512, 0.0741725070055019, -0.1314429859093462, 0.042593710083697535, -0.1432974396022753, -0.21493881413092217, 0.060299911406925984, 0.45068168442728174, -0.2845387677781475, -0.337534151191258, 0.14898841581247652, -0.189774202190849, -0.16759213248594132, 0.21905781828965515, -0.12353133444443472, 0.10651144766573134, 0.06260684875146541, 0.014233846764645388, -0.035292931681132726, -0.2637342889435016, 0.24838018296565065, 0.11127580685588793, 0.3387937129526917, 0.019459833130320042, 0.10434784391958617, -0.021897654632170103, 0.0027079079429515535, 0.021163195212427367, -0.03984407204807523, 0.10123494577904542, 0.2927582818401866, 0.16455417938339403, 0.31135327669366014, -0.448909091994039, -0.17864126189110371, 0.12977867948018715, 0.16493131551079643, 0.06997743272222579, -0.01388232990699864, -0.23050487567431843, 0.1299093253751341, -0.19509089163416982, -0.07544138678150554, -0.14207878839582777, 0.006572938283395945, -0.025297434315976933, -0.2974338035465369, 0.018934281560558524, 0.0240587741892753, -0.009460285668157868, -0.0010236994906639059, -0.060849637154322594, 0.0522910264842053, 0.11973757792635359, 0.059636040097182125, 0.04444894727327439, 0.16671738506127626, -0.07063458258142838, -0.08093520285736801, 0.34512815754223836, -0.0030073692612190787, -0.21472935900728926, 0.2191377302361095, -0.04811476125047566, -0.13059120426654944, 0.15533640812117305, 0.22672198594420448, 0.13543350068438384, -0.19352755252469397, 0.052516504508516804, 0.04437292608408592, 0.22375724484554976, 0.006102245444288621, 0.030058690403990097, 0.12500393413938582, 0.218245959138243, 0.113923532428602, 0.13908712108098129, -0.07735694104280227, -0.12666076610688692, -0.18652383546130016, -0.11964709046654977, -0.17705048595427766, -0.023101954408359125, -0.06270597754897048, -0.15591029561737663, 0.3501987845485664, 0.21649454083218056, 0.17043782495216936, 0.08346719953478274, 0.39913604780235606, 0.13373703747573826, 0.11623236832893494, 0.09030547015305258, 0.18622461715951943, 0.019593788418345727, 0.1835855176497219, -0.22879558339969724, 0.12649358817750317, -0.0032502938906212426] |
710.474 | A New Approach to Component Testing | Carefully tested electric/electronic components are a requirement for
effective hardware-in-the-loop tests and vehicle tests in automotive industry.
A new method for definition and execution of component tests is described. The
most important advantage of this method is independance from the test stand. It
therefore offers the oppportunity to build up knowledge over a long period of
time and the ability to share this knowledge with different partners.
| cs.OH | carefully tested electricelectronic components are a requirement for effective hardwareintheloop tests and vehicle tests in automotive industry a new method for definition and execution of component tests is described the most important advantage of this method is independance from the test stand it therefore offers the oppportunity to build up knowledge over a long period of time and the ability to share this knowledge with different partners | [['carefully', 'tested', 'electricelectronic', 'components', 'are', 'a', 'requirement', 'for', 'effective', 'hardwareintheloop', 'tests', 'and', 'vehicle', 'tests', 'in', 'automotive', 'industry', 'a', 'new', 'method', 'for', 'definition', 'and', 'execution', 'of', 'component', 'tests', 'is', 'described', 'the', 'most', 'important', 'advantage', 'of', 'this', 'method', 'is', 'independance', 'from', 'the', 'test', 'stand', 'it', 'therefore', 'offers', 'the', 'oppportunity', 'to', 'build', 'up', 'knowledge', 'over', 'a', 'long', 'period', 'of', 'time', 'and', 'the', 'ability', 'to', 'share', 'this', 'knowledge', 'with', 'different', 'partners']] | [-0.07119257101932397, 0.0326296327313265, -0.12431703866101228, 0.025961290543469098, -0.10134646734939172, -0.16303979624779177, 0.04172878387885598, 0.3741593210743024, -0.2034843713277951, -0.364971432949488, 0.12772187726536335, -0.22522144026051347, -0.08298704318988781, 0.26000394248045405, -0.05298820924586975, 0.08180117229751956, 0.08600115654273675, 0.01829137263389734, -0.01453443836558458, -0.25687199166187874, 0.23701635794714093, 0.05625724580425483, 0.31152307919871347, 0.04443117191728491, 0.12063277939764352, -0.02913222204750547, -0.07171623653490454, -0.01772036561026023, -0.039494588218915924, 0.14091032459042394, 0.2782420419299832, 0.1990917129155535, 0.32395443459256335, -0.3961375736273252, -0.1802153038720672, 0.08938223195907015, 0.06818775874920763, 0.07226391926837655, -0.014432127444216838, -0.2752796276257588, 0.11493418785528495, -0.21414685573142309, -0.16460566314367148, -0.105056971956331, 0.028947814768896653, 0.00032699569486654723, -0.29611235060370883, -0.02335653094834505, 0.046915518497833264, 0.07442985466466501, -0.027129036779157244, -0.0880584363753979, 0.058136078987557155, 0.1944112728206584, 0.09738712307209006, 0.009256021520839288, 0.12876092228465355, -0.09921100600264393, -0.12069996818900108, 0.42686628762346046, -0.06118964393032142, -0.19878664429371173, 0.1951753529934929, -0.06450575793054528, -0.1399326726821108, 0.07681390580792839, 0.19354229717013927, 0.09340208788187458, -0.18854031349317385, 0.04251148436820726, 0.02510240413248539, 0.1723241989715741, 0.050572341875746274, -0.004371962037224036, 0.221302946886191, 0.2559670158876823, 0.038978448079321354, 0.09573800507037399, -0.06649240719584318, -0.11098009477047106, -0.27877306684385983, -0.1948845071144975, -0.17720401100814342, -0.0031242113273877363, -0.05117163688342911, -0.10423070130010063, 0.4299523927271366, 0.2028964348280659, 0.12652732311533046, 0.04640659383283212, 0.3628363358215071, 0.024069659719960047, 0.13075041072375965, 0.0773587251511904, 0.21249890759264908, 0.06719362858969431, 0.10661513921983827, -0.1617001764010638, 0.09256595203366418, -0.005952520052400919] |
710.4741 | Measurement of the spatio-temporal distribution of harmonic and
transient eddy currents in a liquid metal | Harmonic and transient eddy currents in a liquid metal positioned above an
excitation coil are determined by measuring the voltage drop in a simple
potential probe. The resulting spatio-temporal eddy current field is compared
with the corresponding analytical expressions for a conducting half-space.
Further, a deformation of the eddy current distribution due to a non-conducting
torus immersed into the liquid metal is measured and compared with numerical
results. The method can be generalized to arbitrary geometries, and might help
to validate numerical models for non-destructive testing and magnetic
inductance tomography.
| physics.flu-dyn physics.class-ph | harmonic and transient eddy currents in a liquid metal positioned above an excitation coil are determined by measuring the voltage drop in a simple potential probe the resulting spatiotemporal eddy current field is compared with the corresponding analytical expressions for a conducting halfspace further a deformation of the eddy current distribution due to a nonconducting torus immersed into the liquid metal is measured and compared with numerical results the method can be generalized to arbitrary geometries and might help to validate numerical models for nondestructive testing and magnetic inductance tomography | [['harmonic', 'and', 'transient', 'eddy', 'currents', 'in', 'a', 'liquid', 'metal', 'positioned', 'above', 'an', 'excitation', 'coil', 'are', 'determined', 'by', 'measuring', 'the', 'voltage', 'drop', 'in', 'a', 'simple', 'potential', 'probe', 'the', 'resulting', 'spatiotemporal', 'eddy', 'current', 'field', 'is', 'compared', 'with', 'the', 'corresponding', 'analytical', 'expressions', 'for', 'a', 'conducting', 'halfspace', 'further', 'a', 'deformation', 'of', 'the', 'eddy', 'current', 'distribution', 'due', 'to', 'a', 'nonconducting', 'torus', 'immersed', 'into', 'the', 'liquid', 'metal', 'is', 'measured', 'and', 'compared', 'with', 'numerical', 'results', 'the', 'method', 'can', 'be', 'generalized', 'to', 'arbitrary', 'geometries', 'and', 'might', 'help', 'to', 'validate', 'numerical', 'models', 'for', 'nondestructive', 'testing', 'and', 'magnetic', 'inductance', 'tomography']] | [-0.09763730599855383, 0.14901011498764596, -0.04328725201129499, 0.01978550910587526, -0.038354096535800235, -0.14952165368013084, -0.0007119789590231246, 0.36436022797392476, -0.22243202299707465, -0.30156156913532567, 0.09830239151035332, -0.25817126986156735, -0.08031948631008466, 0.2658326544980001, -0.014137094522205492, 0.0489496454079118, 0.028463666054368432, -0.05195519659771687, -0.0760318783732752, -0.11084650382916961, 0.23528150658433636, 0.06043389215936056, 0.3287807477845086, 0.09055131378376649, 0.08998353459303164, -0.07923504059823851, -0.00509917578763432, 0.11236306718136702, -0.1384497480156521, 0.07466327068913314, 0.25287822717982633, -0.043760634216273, 0.18982953623765045, -0.5000829128548503, -0.21126962438639668, 0.051770430332463646, 0.13886520970716246, 0.13649048174007072, -0.05461133706072966, -0.2994767513540056, 0.05396965827999844, -0.16679497567367638, -0.16614285704886747, -0.10600493140518666, -0.004392097001740088, 0.06242766507526135, -0.3214533152783083, 0.06620384688592619, 0.015429549845349458, 0.061396251577470036, -0.09008752368907962, -0.08207273119801863, -0.010277759589047895, 0.07683036240212257, 0.01567641110288807, 0.07127573553524498, 0.22555458658478325, -0.16387850657726327, -0.06516493968148199, 0.3176765974611044, -0.08020720605014099, -0.2577660886425292, 0.17338946919060416, -0.15432677613571286, 0.0382300154137839, 0.18840415448778206, 0.14804801516648797, 0.07630474780065317, -0.16629166197575007, 0.014892841070993907, -0.022246660975118477, 0.1459795276931901, 0.062051370558846325, -0.09019705582565317, 0.2667152295923895, 0.2179239965056897, 0.027052939822897314, 0.17687054611742498, -0.1485610347448124, -0.033775606813530125, -0.27154661861455276, -0.1882492919659449, -0.19051338335913087, 0.05790287525418939, -0.08234763497732477, -0.19445490818470718, 0.3967923533688817, 0.12294622992113646, 0.14881803623090187, 0.014974101086651596, 0.35087464592523043, 0.13924938620119873, 0.043482344618274105, 0.048426509006983705, 0.23501541655924585, 0.21148381223126003, 0.08836545389559534, -0.2712161518892066, 0.05571869619501134, 0.03731720523080892] |
710.4742 | Hardware Accelerated Power Estimation | In this paper, we present power emulation, a novel design paradigm that
utilizes hardware acceleration for the purpose of fast power estimation. Power
emulation is based on the observation that the functions necessary for power
estimation (power model evaluation, aggregation, etc.) can be implemented as
hardware circuits. Therefore, we can enhance any given design with "power
estimation hardware", map it to a prototyping platform, and exercise it with
any given test stimuli to obtain power consumption estimates. Our empirical
studies with industrial designs reveal that power emulation can achieve
significant speedups (10X to 500X) over state-of-the-art commercial
register-transfer level (RTL) power estimation tools.
| cs.AR | in this paper we present power emulation a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation power emulation is based on the observation that the functions necessary for power estimation power model evaluation aggregation etc can be implemented as hardware circuits therefore we can enhance any given design with power estimation hardware map it to a prototyping platform and exercise it with any given test stimuli to obtain power consumption estimates our empirical studies with industrial designs reveal that power emulation can achieve significant speedups 10x to 500x over stateoftheart commercial registertransfer level rtl power estimation tools | [['in', 'this', 'paper', 'we', 'present', 'power', 'emulation', 'a', 'novel', 'design', 'paradigm', 'that', 'utilizes', 'hardware', 'acceleration', 'for', 'the', 'purpose', 'of', 'fast', 'power', 'estimation', 'power', 'emulation', 'is', 'based', 'on', 'the', 'observation', 'that', 'the', 'functions', 'necessary', 'for', 'power', 'estimation', 'power', 'model', 'evaluation', 'aggregation', 'etc', 'can', 'be', 'implemented', 'as', 'hardware', 'circuits', 'therefore', 'we', 'can', 'enhance', 'any', 'given', 'design', 'with', 'power', 'estimation', 'hardware', 'map', 'it', 'to', 'a', 'prototyping', 'platform', 'and', 'exercise', 'it', 'with', 'any', 'given', 'test', 'stimuli', 'to', 'obtain', 'power', 'consumption', 'estimates', 'our', 'empirical', 'studies', 'with', 'industrial', 'designs', 'reveal', 'that', 'power', 'emulation', 'can', 'achieve', 'significant', 'speedups', '10x', 'to', '500x', 'over', 'stateoftheart', 'commercial', 'registertransfer', 'level', 'rtl', 'power', 'estimation', 'tools']] | [-0.12370470362417038, -0.012406705381366814, -0.0828244065418297, -0.021996679471679104, -0.09672607385578284, -0.22309159205376522, 0.02520402239802863, 0.4107327121264726, -0.2270458158630046, -0.35874205269823667, 0.12123470276976185, -0.19979206357124144, -0.17846063989241726, 0.32783534149729726, -0.11949945086143116, 0.11070647441501756, 0.0774997754329906, -0.029202811553332847, -0.06154528281168822, -0.23914385334670812, 0.17472262528286434, 0.16896819592751924, 0.3690981865019619, 0.04007266745653944, 0.09291329011954005, -0.05103736333729862, -0.00024002498847622316, -0.02527775052139192, -0.08113149550026542, 0.14721515739915295, 0.3171957844090693, 0.23243566937360333, 0.3143839432668049, -0.4287150362416089, -0.2242310717408048, 0.13454991552608034, 0.10929431847649292, 0.02812542713437121, -0.09852102493473952, -0.2031865348062903, 0.12283531767180533, -0.26120357678805306, -0.049525418662402815, -0.17468753492982958, -0.04558658360467446, 0.04478071716803949, -0.34433758204567777, -0.020367219171586258, 0.02821899681053694, 0.06209109445075387, -0.00981743958353707, -0.09834544555944147, 0.08106182833220267, 0.13114504160323334, -0.04155534462781749, 0.005872594790806705, 0.21343892153569508, -0.10484654175850011, -0.1773039824171082, 0.35852800362101456, -0.023904055635019846, -0.22241278204307394, 0.13124947228414702, -0.04829632784285157, -0.1329736964487769, 0.08951885853803636, 0.2673217996150183, -0.0045200515932909855, -0.14986343395181942, 0.023688523432814055, 0.05341760921789315, 0.2736952624541427, 0.007376190858160697, 0.0013764397494350244, 0.1802421556152765, 0.24446698087403207, 0.08926222792564376, 0.15729555568897427, -0.07823535806083491, -0.04546573501333449, -0.2456703143696147, -0.13436064406499285, -0.175004335748737, 0.0479786827057166, -0.09363823194829272, -0.13051998576384435, 0.41188593306443066, 0.22818571608965693, 0.08128781746892096, 0.1624171781236107, 0.47933506159093775, 0.13802305242336058, 0.10013019392104114, 0.13066761971912483, 0.16325276178868434, 0.009925773683754564, 0.12183938914055494, -0.18820741232846258, 0.07801464332032551, -0.02833117058645319] |
710.4743 | Efficient Solution of Language Equations Using Partitioned
Representations | A class of discrete event synthesis problems can be reduced to solving
language equations f . X ⊆ S, where F is the fixed component and S the
specification. Sequential synthesis deals with FSMs when the automata for F and
S are prefix closed, and are naturally represented by multi-level networks with
latches. For this special case, we present an efficient computation, using
partitioned representations, of the most general prefix-closed solution of the
above class of language equations. The transition and the output relations of
the FSMs for F and S in their partitioned form are represented by the sets of
output and next state functions of the corresponding networks. Experimentally,
we show that using partitioned representations is much faster than using
monolithic representations, as well as applicable to larger problem instances.
| cs.LO | a class of discrete event synthesis problems can be reduced to solving language equations f x sube s where f is the fixed component and s the specification sequential synthesis deals with fsms when the automata for f and s are prefix closed and are naturally represented by multilevel networks with latches for this special case we present an efficient computation using partitioned representations of the most general prefixclosed solution of the above class of language equations the transition and the output relations of the fsms for f and s in their partitioned form are represented by the sets of output and next state functions of the corresponding networks experimentally we show that using partitioned representations is much faster than using monolithic representations as well as applicable to larger problem instances | [['a', 'class', 'of', 'discrete', 'event', 'synthesis', 'problems', 'can', 'be', 'reduced', 'to', 'solving', 'language', 'equations', 'f', 'x', 'sube', 's', 'where', 'f', 'is', 'the', 'fixed', 'component', 'and', 's', 'the', 'specification', 'sequential', 'synthesis', 'deals', 'with', 'fsms', 'when', 'the', 'automata', 'for', 'f', 'and', 's', 'are', 'prefix', 'closed', 'and', 'are', 'naturally', 'represented', 'by', 'multilevel', 'networks', 'with', 'latches', 'for', 'this', 'special', 'case', 'we', 'present', 'an', 'efficient', 'computation', 'using', 'partitioned', 'representations', 'of', 'the', 'most', 'general', 'prefixclosed', 'solution', 'of', 'the', 'above', 'class', 'of', 'language', 'equations', 'the', 'transition', 'and', 'the', 'output', 'relations', 'of', 'the', 'fsms', 'for', 'f', 'and', 's', 'in', 'their', 'partitioned', 'form', 'are', 'represented', 'by', 'the', 'sets', 'of', 'output', 'and', 'next', 'state', 'functions', 'of', 'the', 'corresponding', 'networks', 'experimentally', 'we', 'show', 'that', 'using', 'partitioned', 'representations', 'is', 'much', 'faster', 'than', 'using', 'monolithic', 'representations', 'as', 'well', 'as', 'applicable', 'to', 'larger', 'problem', 'instances']] | [-0.11367994886464798, 0.10359568137221056, 0.008147367561021104, 0.06285858598913854, -0.05490819425859417, -0.15655055434729617, 0.02568717705479895, 0.3742880750895263, -0.3282170187511768, -0.28569118701136453, 0.11015480029163882, -0.2562889404182967, -0.10599636162380473, 0.22032462288804638, -0.04035485260381112, 0.06869549797579216, 0.07309816509950906, 0.05437037072216089, -0.0867565193410533, -0.21804226310565494, 0.3248439923645212, -0.03726658946118103, 0.24720718044644366, -0.05681950688505402, 0.1044801998955126, -0.012257495035345737, 0.014574209880083799, 0.052052174046492344, -0.055351842893567385, 0.14884994711923916, 0.3259038135301895, 0.1954684298306417, 0.24889842165240014, -0.4254933600815443, -0.19681186290242925, 0.14250370819085778, 0.13483574983234015, 0.05978488421264606, 0.011853668208305652, -0.28221180477501967, 0.13967981005374056, -0.15917526284376016, -0.042212461250332685, -0.06947450189349744, 0.06617698187832362, 0.03696866841413654, -0.302736715411839, 0.014488825681977548, 0.0930508952256507, 0.04139237248410399, -0.03398678448015394, -0.14112219176380536, -0.035759970175030714, 0.09370007016270672, -0.04001506390050054, 0.04114536932275559, 0.07225292510567949, -0.09841364328212177, -0.12411033613607288, 0.3892108224547253, -0.0769924857892105, -0.25149191082097017, 0.16234018685511098, -0.06555547821693695, -0.13950697214056093, 0.10578676848761881, 0.16275477785473833, 0.17961035485092838, -0.11845928600937791, 0.11174346635816619, -0.06377695362585095, 0.17122088194412824, 0.05484685167097128, 0.008548115346527014, 0.1535661137376267, 0.18530257521018098, 0.05119620931979555, 0.18761112404037983, 0.0029353054432878986, -0.07926123467847132, -0.29818214828578327, -0.14131102902958026, -0.16218870190294601, 0.023831654701811762, -0.07169931062089745, -0.16742872875900222, 0.381684487977495, 0.10117157391415765, 0.1830538433797371, 0.12512664125086023, 0.2412730797014844, 0.17244391777875046, 0.07211283484581285, 0.11744441479229584, 0.08735584613795463, 0.11648061376673957, 0.03762199682398484, -0.16551587748197982, 0.08987177587830676, 0.10968676775765533] |
710.4744 | Magnetohydrodynamics In The Context Of Nelson's Stochastic Mechanics | A simple generalization of the MHD model accounting for the fluctuations of
the configurations due to kinetic effects in plasmas in short times small
scales is considered. The velocity of conductive fluid and the magnetic field
are considerd as the stochastic fields (or random trial trajectories) for which
the classical MHD equations play the role of the mean field equations in the
spirit of stochastic mechanics of E. Nelson.
| physics.plasm-ph physics.class-ph | a simple generalization of the mhd model accounting for the fluctuations of the configurations due to kinetic effects in plasmas in short times small scales is considered the velocity of conductive fluid and the magnetic field are considerd as the stochastic fields or random trial trajectories for which the classical mhd equations play the role of the mean field equations in the spirit of stochastic mechanics of e nelson | [['a', 'simple', 'generalization', 'of', 'the', 'mhd', 'model', 'accounting', 'for', 'the', 'fluctuations', 'of', 'the', 'configurations', 'due', 'to', 'kinetic', 'effects', 'in', 'plasmas', 'in', 'short', 'times', 'small', 'scales', 'is', 'considered', 'the', 'velocity', 'of', 'conductive', 'fluid', 'and', 'the', 'magnetic', 'field', 'are', 'considerd', 'as', 'the', 'stochastic', 'fields', 'or', 'random', 'trial', 'trajectories', 'for', 'which', 'the', 'classical', 'mhd', 'equations', 'play', 'the', 'role', 'of', 'the', 'mean', 'field', 'equations', 'in', 'the', 'spirit', 'of', 'stochastic', 'mechanics', 'of', 'e', 'nelson']] | [-0.15305207739921584, 0.19573018462329672, -0.05817030795067009, 0.09934820907791078, -0.0027811759947866635, -0.05656243337021358, -0.0714991823365183, 0.24032348791218322, -0.25746892398034316, -0.3060119272736104, 0.04228001790782572, -0.210675952753619, -0.09797093650137169, 0.19397435546515213, -0.001204525876412357, 0.0430092192457422, 0.02407209557629582, 0.00323629778796348, -0.012587111154773636, -0.1950231877128607, 0.2861864739840013, 0.09678690004553916, 0.23638104424690423, -0.01796786203150354, 0.12572366449361047, 0.0010077683929947839, -0.02234260252325971, 0.08146725810956264, -0.11493063602677506, 0.0266184878292615, 0.18438322605916124, 0.010621360192696253, 0.3055826809959135, -0.5060881189192119, -0.26262542369195085, 0.059016967462240784, 0.10695785772902351, 0.15108444939023288, 0.005454304263643597, -0.24551175847865533, 0.013333239612857933, -0.12020753813313617, -0.16286551859229803, -0.022813080641292574, 0.05230573658912402, 0.08135404432381409, -0.2988640659124307, 0.15867542167720589, 0.10319510504664124, 0.0693055476086042, -0.09786238167873597, -0.09736459503841141, -0.022237218862426453, 0.08020513162921196, 0.09656425400981275, 0.04932570258371424, 0.14958891505375504, -0.20662266560627715, -0.10852165200302134, 0.43488225305749884, -0.07329423986105384, -0.24522805370498393, 0.16984565245608488, -0.14036004076563363, -0.07654235947310277, 0.1451481360996115, 0.19141479638283668, 0.13478470642956486, -0.1308209413757035, 0.12686081870334168, -0.03758705815298658, 0.060721228000424475, 0.0315171404255797, 0.017937584503459326, 0.2009832648884343, 0.1353383318291626, 0.008451678041044785, 0.08321281270785393, -0.10932908487924631, -0.18530093746232815, -0.33141716259179055, -0.15940240743583528, -0.13835855775877184, 0.09541576937477077, -0.1017666259994376, -0.2339169973797718, 0.37246499224093516, 0.17690529904000973, 0.13179328978277635, 0.013013477661592913, 0.2587192376562651, 0.1540560159896352, 0.01669456742271997, 0.10590574875527965, 0.2531940552500495, 0.23739288404475953, 0.1515996268801931, -0.24534834121468652, 0.018138171065652717, 0.10973086051534915] |
710.4745 | Embedded Automotive System Development Process | Model based design enables the automatic generation of final-build software
from models for high-volume automotive embedded systems. This paper presents a
framework of processes, methods and tools for the design of automotive embedded
systems. A steer-by-wire system serves as an example.
| cs.OH | model based design enables the automatic generation of finalbuild software from models for highvolume automotive embedded systems this paper presents a framework of processes methods and tools for the design of automotive embedded systems a steerbywire system serves as an example | [['model', 'based', 'design', 'enables', 'the', 'automatic', 'generation', 'of', 'finalbuild', 'software', 'from', 'models', 'for', 'highvolume', 'automotive', 'embedded', 'systems', 'this', 'paper', 'presents', 'a', 'framework', 'of', 'processes', 'methods', 'and', 'tools', 'for', 'the', 'design', 'of', 'automotive', 'embedded', 'systems', 'a', 'steerbywire', 'system', 'serves', 'as', 'an', 'example']] | [-0.14322878317907453, -0.05872609443867986, -0.060720119159668684, -0.007832074785255827, -0.018386206589639187, -0.15925779619719832, -0.005663638465921395, 0.3514691762626171, -0.19865668462589384, -0.3177878925111145, 0.17012677562888712, -0.22099287087330594, -0.23341821572976187, 0.3302866003185045, -0.09348004257772118, 0.1347920876694843, 0.08364573931321502, -0.04718047760543413, 0.0012501363293267787, -0.1091094322502613, 0.2996173332212493, 0.03633661654312163, 0.3146865101531148, 0.013395018869778142, 0.10584577800473198, 0.025607863190816715, -0.002251730940770358, -0.06578476261347532, -0.06479090806096792, 0.23984195676166564, 0.3028418767306903, 0.22121505783870815, 0.3281156976823695, -0.4257194028934464, -0.2507753866666462, 0.05975049145054072, 0.16595853278413414, 0.0894428692292422, -0.10701731964945793, -0.275459005124867, 0.04191574045980815, -0.2826178798917681, -0.1574953270610422, -0.07263392247259617, -0.04411181784234941, 0.021864250674843787, -0.3209934186190367, -0.054382880800403655, 0.10081017408519984, 0.08820773067418486, -0.06844024890160653, -0.05727411346451845, 0.044853210853761996, 0.203068591329793, -0.05457016588479746, -0.01433746695984155, 0.173564856381563, -0.1201476642221678, -0.20438720360398294, 0.47218008190393446, -0.01825488044996746, -0.18915771305037196, 0.2319475026859436, 0.0885157398879528, -0.18041362940566613, 0.05095620136708021, 0.3353776606847532, 0.12844905788078903, -0.24975797154475005, 0.10029669885843759, 0.07634717690525576, 0.21832014587707818, -0.11349026224343106, 0.004269867320545018, 0.24132111481158064, 0.3676138360984623, 0.03018239822704345, 0.20222742361947893, -0.04169784244149923, -0.07739372008945793, -0.289086990384385, -0.2115560168400407, -0.06458854940719902, -0.03359351293183863, -0.00997228587475547, -0.22023701695725323, 0.35696300173876805, 0.21061471309512853, 0.08998795286752284, 0.020788383798208087, 0.4167697038501501, 0.05873589651600923, 0.08361928830854595, 0.04631476341746747, 0.10387599088717252, 0.058404394914396106, 0.19946724828332663, -0.08812710695201531, 0.07149189281044528, 0.041278680227696894] |
710.4746 | RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in
SystemC | This paper presents the methodology and the modeling constructs we have
developed to capture the real time aspects of RTOS simulation models in a
System Level Design Language (SLDL) like SystemC. We describe these constructs
and show how they are used to build a simulation model of an RTOS kernel
targeting the $\mu$-ITRON OS specification standard.
| cs.OS | this paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of rtos simulation models in a system level design language sldl like systemc we describe these constructs and show how they are used to build a simulation model of an rtos kernel targeting the muitron os specification standard | [['this', 'paper', 'presents', 'the', 'methodology', 'and', 'the', 'modeling', 'constructs', 'we', 'have', 'developed', 'to', 'capture', 'the', 'real', 'time', 'aspects', 'of', 'rtos', 'simulation', 'models', 'in', 'a', 'system', 'level', 'design', 'language', 'sldl', 'like', 'systemc', 'we', 'describe', 'these', 'constructs', 'and', 'show', 'how', 'they', 'are', 'used', 'to', 'build', 'a', 'simulation', 'model', 'of', 'an', 'rtos', 'kernel', 'targeting', 'the', 'muitron', 'os', 'specification', 'standard']] | [-0.08654991761539821, -0.026619516112313484, -0.10715790498242886, 0.0730837000150199, -0.061766813060751664, -0.15269671501246868, -0.0035763229609949996, 0.4038820149445975, -0.27472632709476685, -0.33759044893775825, 0.09367092756373394, -0.24255357737894412, -0.20023271824336714, 0.20212926535815415, -0.08603407604688848, 0.08309445380992084, 0.09295890220285703, -0.005263063871232724, -0.021536089042287872, -0.23129167168021755, 0.28002111862103146, 0.08147025918932976, 0.2692100758905764, 0.004452185550083716, 0.1025913665243597, -0.005839953142977147, -0.05203353767110794, -0.03332710561032096, -0.11524146986711356, 0.14984556275454383, 0.2982445217147432, 0.24467743460640864, 0.2912665618652547, -0.4839773186379009, -0.19541153433749936, 0.06300852286060238, 0.09144033335528716, 0.09221115851498864, -0.023598628360088223, -0.2640927075753333, 0.09831702576398298, -0.21754674707470392, -0.09399034746025724, -0.14323727903818642, -0.06575627861268542, 0.009410671294770308, -0.23432655575366138, -0.07511693961849367, 0.07428547144539792, 0.06135917905097207, -0.01966318804598241, -0.07779978254283951, 0.04412683557408551, 0.15813574462232213, -0.01725991364542602, -0.025451138457692986, 0.1424798257821412, -0.06115659744978917, -0.165617808751348, 0.38530621360297557, -0.04288154362304205, -0.2355395398960725, 0.2441611763227869, -0.041435037877548625, -0.17563515326387627, 0.013460845617508446, 0.27232459075403986, 0.08556506796136361, -0.18118226481601596, 0.11010806589965122, -0.0034357332387352705, 0.22870865540096053, -0.027484483033832576, -0.04997222467015187, 0.15868360963132647, 0.26116208394092544, -0.04432470697685386, 0.14774049341644127, -0.05548476338972924, -0.11353190587316123, -0.27154128196545774, -0.1883293457105066, -0.08711706320496483, -0.039063965901732445, -0.01115030641786116, -0.2061942079001003, 0.4334639546081976, 0.2816886159988051, 0.15494449860933754, 0.11743819849841573, 0.3337793587362049, 0.12455402370714755, 0.0693008132899801, 0.09186233936257109, 0.12550217676390377, 0.005410625047429844, 0.15864787262829919, -0.16696151728845304, 0.09629696456680971, 0.03818923972236613] |
710.4747 | An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories | Memory cores are usually the densest portion with the smallest feature size
in system-on-chip (SOC) designs. The reliability of memory cores thus has heavy
impact on the reliability of SOCs. Transparent test is one of useful technique
for improving the reliability of memories during life time. This paper presents
a systematic algorithm used for transforming a bit-oriented march test into a
transparent word-oriented march test. The transformed transparent march test
has shorter test complexity compared with that proposed in the previous works
[Theory of transparent BIST for RAMs, A transparent online memory test for
simultaneous detection of functional faults and soft errors in memories]. For
example, if a memory with 32-bit words is tested with March C-, time complexity
of the transparent word-oriented test transformed by the proposed scheme is
only about 56% or 19% time complexity of the transparent word-oriented test
converted by the scheme reported in [Theory of transparent BIST for RAMs] or [A
transparent online memory test for simultaneous detection of functional faults
and soft errors in memories], respectively.
| cs.AR | memory cores are usually the densest portion with the smallest feature size in systemonchip soc designs the reliability of memory cores thus has heavy impact on the reliability of socs transparent test is one of useful technique for improving the reliability of memories during life time this paper presents a systematic algorithm used for transforming a bitoriented march test into a transparent wordoriented march test the transformed transparent march test has shorter test complexity compared with that proposed in the previous works theory of transparent bist for rams a transparent online memory test for simultaneous detection of functional faults and soft errors in memories for example if a memory with 32bit words is tested with march c time complexity of the transparent wordoriented test transformed by the proposed scheme is only about 56 or 19 time complexity of the transparent wordoriented test converted by the scheme reported in theory of transparent bist for rams or a transparent online memory test for simultaneous detection of functional faults and soft errors in memories respectively | [['memory', 'cores', 'are', 'usually', 'the', 'densest', 'portion', 'with', 'the', 'smallest', 'feature', 'size', 'in', 'systemonchip', 'soc', 'designs', 'the', 'reliability', 'of', 'memory', 'cores', 'thus', 'has', 'heavy', 'impact', 'on', 'the', 'reliability', 'of', 'socs', 'transparent', 'test', 'is', 'one', 'of', 'useful', 'technique', 'for', 'improving', 'the', 'reliability', 'of', 'memories', 'during', 'life', 'time', 'this', 'paper', 'presents', 'a', 'systematic', 'algorithm', 'used', 'for', 'transforming', 'a', 'bitoriented', 'march', 'test', 'into', 'a', 'transparent', 'wordoriented', 'march', 'test', 'the', 'transformed', 'transparent', 'march', 'test', 'has', 'shorter', 'test', 'complexity', 'compared', 'with', 'that', 'proposed', 'in', 'the', 'previous', 'works', 'theory', 'of', 'transparent', 'bist', 'for', 'rams', 'a', 'transparent', 'online', 'memory', 'test', 'for', 'simultaneous', 'detection', 'of', 'functional', 'faults', 'and', 'soft', 'errors', 'in', 'memories', 'for', 'example', 'if', 'a', 'memory', 'with', '32bit', 'words', 'is', 'tested', 'with', 'march', 'c', 'time', 'complexity', 'of', 'the', 'transparent', 'wordoriented', 'test', 'transformed', 'by', 'the', 'proposed', 'scheme', 'is', 'only', 'about', '56', 'or', '19', 'time', 'complexity', 'of', 'the', 'transparent', 'wordoriented', 'test', 'converted', 'by', 'the', 'scheme', 'reported', 'in', 'theory', 'of', 'transparent', 'bist', 'for', 'rams', 'or', 'a', 'transparent', 'online', 'memory', 'test', 'for', 'simultaneous', 'detection', 'of', 'functional', 'faults', 'and', 'soft', 'errors', 'in', 'memories', 'respectively']] | [-0.1107081207284314, 0.08084079922111921, -0.05620549735613167, 0.030388126143005265, -0.07198511396513083, -0.19098685750044708, 0.10570384388949267, 0.38741579102785434, -0.16847655336849046, -0.36023838892524934, 0.13451136180624734, -0.22008156990849, -0.08310093569601777, 0.2221902815200697, -0.089622867768116, 0.10088740467083056, 0.07981556848566004, 3.345334444866451e-05, -0.034384720946586324, -0.2950774338637847, 0.19259294645378885, 0.1088899896902487, 0.3147105864292487, -0.004128326718738779, 0.06885828626028068, 0.01637094559115466, -0.048347324650019924, -0.01719290579447176, -0.018053979508866093, 0.08834687227381226, 0.25757594174857057, 0.12334898362196116, 0.3023800359887266, -0.4978499878089615, -0.18164300883654505, 0.009759732412423418, 0.06559391974452558, 0.03943712277836058, -0.07107086689279112, -0.2923511251181819, 0.0907231197140158, -0.17418472490376294, -0.06990707679489237, -0.04926842938804712, 0.08153833838472099, -0.02723574378462725, -0.25465107300023676, 0.058112799874940065, 0.06091961999042068, 0.04077270936740692, -0.026250514553773197, -0.09798214001429462, 0.059918429935351014, 0.10974817247898859, -0.018945512246762858, 0.012566983319418289, 0.10166135031004371, -0.09263712555023863, -0.14180567294229254, 0.3714332521113372, -0.011608157702180188, -0.14077465549357734, 0.1837109927965198, -0.044784452420995075, -0.1461897894694757, 0.14955103521906707, 0.20162705231327996, 0.106514964241881, -0.16119176215427214, 0.07737230881811716, 0.001458387928514005, 0.24639955441586586, 0.09589990630994963, 0.047370578154250116, 0.16108436705165563, 0.24385954089852613, -0.010031845685917624, 0.19318943186987972, -0.09809254302756948, -0.04685682154918458, -0.2599624813754967, -0.21476774361677642, -0.18247799067433143, 0.004338776113378794, -0.09127902282726122, -0.15464818562640872, 0.3789113502677305, 0.16814005394942713, 0.11402675997043504, 0.08944489265965341, 0.3411927058599716, 0.06549447415353254, 0.12374007076276791, 0.11370627925363044, 0.21725661082323208, 0.07120652971410214, 0.132515195841078, -0.14604093693467507, 0.114778854044934, 0.024163650354197205] |
710.4748 | Systematic Transaction Level Modeling of Embedded Systems with SystemC | This paper gives an overview of a transaction level modeling (TLM) design
flow for straightforward embedded system design with SystemC. The goal is to
systematically develop both application-specific HW and SW components of an
embedded system using the TLM approach, thus allowing for fast communication
architecture exploration, rapid prototyping and early embedded SW development.
To this end, we specify the lightweight transaction-based communication
protocol SHIP and present a methodology for automatic mapping of the
communication part of a system to a given architecture, including HW/SW
interfaces.
| cs.AR | this paper gives an overview of a transaction level modeling tlm design flow for straightforward embedded system design with systemc the goal is to systematically develop both applicationspecific hw and sw components of an embedded system using the tlm approach thus allowing for fast communication architecture exploration rapid prototyping and early embedded sw development to this end we specify the lightweight transactionbased communication protocol ship and present a methodology for automatic mapping of the communication part of a system to a given architecture including hwsw interfaces | [['this', 'paper', 'gives', 'an', 'overview', 'of', 'a', 'transaction', 'level', 'modeling', 'tlm', 'design', 'flow', 'for', 'straightforward', 'embedded', 'system', 'design', 'with', 'systemc', 'the', 'goal', 'is', 'to', 'systematically', 'develop', 'both', 'applicationspecific', 'hw', 'and', 'sw', 'components', 'of', 'an', 'embedded', 'system', 'using', 'the', 'tlm', 'approach', 'thus', 'allowing', 'for', 'fast', 'communication', 'architecture', 'exploration', 'rapid', 'prototyping', 'and', 'early', 'embedded', 'sw', 'development', 'to', 'this', 'end', 'we', 'specify', 'the', 'lightweight', 'transactionbased', 'communication', 'protocol', 'ship', 'and', 'present', 'a', 'methodology', 'for', 'automatic', 'mapping', 'of', 'the', 'communication', 'part', 'of', 'a', 'system', 'to', 'a', 'given', 'architecture', 'including', 'hwsw', 'interfaces']] | [-0.20628322386940898, -0.0067510442766983625, -0.07842539614716242, -0.031088224074770805, -0.07985987481769434, -0.20827404583999237, 0.03736720031511775, 0.3967677777373167, -0.260073235810756, -0.32509172556185445, 0.13422243727566024, -0.1620101369051046, -0.17918942118236839, 0.19714365189700106, -0.08525579657167369, 0.0769292556160931, 0.10095637239147584, -0.04335009132858452, -0.016970741938526178, -0.16866449104164466, 0.25020640954202, 0.08441062413459254, 0.29378961125756936, 0.0324330952243208, 0.09966563280173686, 0.04659651792987228, -0.040588520770502644, -0.04459133644068484, -0.09790559376719905, 0.22738433530727445, 0.2877465653433573, 0.20356400384632653, 0.28351278361312093, -0.4480136827197532, -0.1702358467520626, 0.002903665459259998, 0.1557963141659816, 0.07407416924455225, -0.08476077924417548, -0.2754148138080572, 0.08501571176985148, -0.2710898864424116, -0.13144045191015616, -0.05708953462064613, 0.023885331327788705, -0.02678676384912674, -0.27376320901824985, -0.08242064833554417, 0.04147337575789627, 0.0698432493792457, -0.05207065846987589, -0.0154168090071031, 0.04866566033736088, 0.1523113210203646, -0.08387930462472575, 0.06591159599152296, 0.155475020885121, -0.09886060487397752, -0.10828818523779858, 0.37361520966298356, -0.009719194370581833, -0.17106937450291806, 0.22852402900313135, 0.013553398398704133, -0.1407386946686825, 0.1019559512293876, 0.26973169111798323, 0.05905612031279435, -0.22411704514998682, 0.04725774935092019, 0.0928245501979904, 0.22371321985887926, -0.03356056377226704, 0.007040932095003163, 0.20715938920025215, 0.3130043674541941, 0.07714827962111083, 0.18622246539480117, -0.06472933641634881, -0.08314345543391916, -0.28305533874866573, -0.24375524842938365, -0.09598628038995315, -0.022830935704067003, -0.03365280905276196, -0.18383437566199276, 0.4079795782779192, 0.17146368930116296, 0.1221379861019032, 0.10080858221450864, 0.38347088435101645, 0.07179142706919202, 0.07196525482157635, 0.1174589604610404, 0.14233563181424383, 0.04231962256220191, 0.18206081510153274, -0.18492643731689556, 0.07577445414891942, 0.031123004658797453] |
710.4749 | Electroweak and QCD corrections to Higgs production via vector-boson
fusion at the LHC | The radiative corrections of the strong and electroweak interactions are
calculated at next-to-leading order for Higgs-boson production in the
weak-boson-fusion channel at hadron colliders. Specifically, the calculation
includes all weak-boson fusion and quark--antiquark annihilation diagrams to
Higgs-boson production in association with two hard jets, including all
corresponding interferences. The results on the QCD corrections confirm that
previously made approximations of neglecting s-channel diagrams and
interferences are well suited for predictions of Higgs production with
dedicated vector-boson fusion cuts at the LHC. The electroweak corrections,
which also include real corrections from incoming photons and leading
heavy-Higgs-boson effects at two-loop order, are of the same size as the QCD
corrections, viz. typically at the level of 5-10% for a Higgs-boson mass up to
\sim 700 GeV. In general, both types of corrections do not simply rescale
differential distributions, but induce distortions at the level of 10%. The
discussed corrections have been implemented in a flexible Monte Carlo event
generator.
| hep-ph | the radiative corrections of the strong and electroweak interactions are calculated at nexttoleading order for higgsboson production in the weakbosonfusion channel at hadron colliders specifically the calculation includes all weakboson fusion and quarkantiquark annihilation diagrams to higgsboson production in association with two hard jets including all corresponding interferences the results on the qcd corrections confirm that previously made approximations of neglecting schannel diagrams and interferences are well suited for predictions of higgs production with dedicated vectorboson fusion cuts at the lhc the electroweak corrections which also include real corrections from incoming photons and leading heavyhiggsboson effects at twoloop order are of the same size as the qcd corrections viz typically at the level of 510 for a higgsboson mass up to sim 700 gev in general both types of corrections do not simply rescale differential distributions but induce distortions at the level of 10 the discussed corrections have been implemented in a flexible monte carlo event generator | [['the', 'radiative', 'corrections', 'of', 'the', 'strong', 'and', 'electroweak', 'interactions', 'are', 'calculated', 'at', 'nexttoleading', 'order', 'for', 'higgsboson', 'production', 'in', 'the', 'weakbosonfusion', 'channel', 'at', 'hadron', 'colliders', 'specifically', 'the', 'calculation', 'includes', 'all', 'weakboson', 'fusion', 'and', 'quarkantiquark', 'annihilation', 'diagrams', 'to', 'higgsboson', 'production', 'in', 'association', 'with', 'two', 'hard', 'jets', 'including', 'all', 'corresponding', 'interferences', 'the', 'results', 'on', 'the', 'qcd', 'corrections', 'confirm', 'that', 'previously', 'made', 'approximations', 'of', 'neglecting', 'schannel', 'diagrams', 'and', 'interferences', 'are', 'well', 'suited', 'for', 'predictions', 'of', 'higgs', 'production', 'with', 'dedicated', 'vectorboson', 'fusion', 'cuts', 'at', 'the', 'lhc', 'the', 'electroweak', 'corrections', 'which', 'also', 'include', 'real', 'corrections', 'from', 'incoming', 'photons', 'and', 'leading', 'heavyhiggsboson', 'effects', 'at', 'twoloop', 'order', 'are', 'of', 'the', 'same', 'size', 'as', 'the', 'qcd', 'corrections', 'viz', 'typically', 'at', 'the', 'level', 'of', '510', 'for', 'a', 'higgsboson', 'mass', 'up', 'to', 'sim', '700', 'gev', 'in', 'general', 'both', 'types', 'of', 'corrections', 'do', 'not', 'simply', 'rescale', 'differential', 'distributions', 'but', 'induce', 'distortions', 'at', 'the', 'level', 'of', '10', 'the', 'discussed', 'corrections', 'have', 'been', 'implemented', 'in', 'a', 'flexible', 'monte', 'carlo', 'event', 'generator']] | [-0.04555941974761997, 0.21032815015723538, -0.055438471649206914, 0.2032751422138161, -0.022449963909995024, -0.11063148038592308, 0.010335681082052031, 0.35440086575735147, -0.17778165624506628, -0.29716483522562465, 0.012467659197178236, -0.3694640021403409, 0.04380256484802456, 0.1605606831344746, 0.1073728665401032, 0.09517499982159894, 0.09811751243575316, 0.0072516217133754, -0.05169274332539392, -0.26107526166886563, 0.3128860573904221, 0.08511385358395471, 0.17969960158644097, 0.1733974245952288, 0.061750301807988316, 0.03776236842119485, -0.09755576258135223, -0.07178324015194158, -0.10008943321170903, 0.024961120644762257, 0.2230651552268381, -0.02748052194821322, 0.11509539747555446, -0.336974514179691, -0.12515991534385237, 0.09075828790583108, 0.17194933820053176, 0.14252371135576344, -0.031245052266515982, -0.2636874928836159, 0.11315957897870689, -0.2621982212053837, -0.07326629749872977, -0.0802826688263067, -0.04716220169601025, -0.048103875676347954, -0.3557538244280828, 0.04684369275060921, -0.07197228500806388, 0.012290075182570678, 0.044843260189192075, -0.184966900207215, -0.09419161970667826, 0.0743950261084873, 0.07352417984244763, 0.027883090180045315, 0.18087950511983816, -0.2118492319729108, -0.23149116018232385, 0.4370802078799457, -0.03740167393123695, -0.1516872167210599, 0.16367165794763655, -0.21080267811372022, -0.17964047110479348, 0.23450610734326588, 0.24275643655668447, 0.0869087813015001, -0.18546151302926905, 0.14078206051538467, 0.1204383211910345, 0.1070709341579372, 0.10038512003768212, 0.08910482069573834, 0.20612105212595527, 0.14245936782306926, -0.06245856344474444, 0.07246842234770642, -0.09756075784676727, -0.11454694339068262, -0.4660663983078709, -0.05887477884104677, -0.030234552239168697, -0.004353493507684558, -0.08901411432818848, -0.1361403431992527, 0.3272604167307164, 0.14378875426823498, 0.22594504021397335, 0.05132723198150682, 0.35982865136217584, 0.11817019056620752, 0.14061448729009765, 0.059591408729980325, 0.3309008748223115, 0.147876436106709, 0.10255193476013508, -0.2378922715875065, 0.026961585935197808, 0.07243545148610642] |
710.475 | On the Analysis of Reed Solomon Coding for Resilience to
Transient/Permanent Faults in Highly Reliable Memories | Single Event Upsets (SEU) as well as permanent faults can significantly
affect the correct on-line operation of digital systems, such as memories and
microprocessors; a memory can be made resilient to permanent and transient
faults by using modular redundancy and coding. In this paper, different memory
systems are compared: these systems utilize simplex and duplex arrangements
with a combination of Reed Solomon coding and scrubbing. The memory systems and
their operations are analyzed by novel Markov chains to characterize
performance for dynamic reconfiguration as well as error detection and
correction under the occurrence of permanent and transient faults. For a
specific Reed Solomon code, the duplex arrangement allows to efficiently cope
with the occurrence of permanent faults, while the use of scrubbing allows to
cope with transient faults.
| cs.IT math.IT | single event upsets seu as well as permanent faults can significantly affect the correct online operation of digital systems such as memories and microprocessors a memory can be made resilient to permanent and transient faults by using modular redundancy and coding in this paper different memory systems are compared these systems utilize simplex and duplex arrangements with a combination of reed solomon coding and scrubbing the memory systems and their operations are analyzed by novel markov chains to characterize performance for dynamic reconfiguration as well as error detection and correction under the occurrence of permanent and transient faults for a specific reed solomon code the duplex arrangement allows to efficiently cope with the occurrence of permanent faults while the use of scrubbing allows to cope with transient faults | [['single', 'event', 'upsets', 'seu', 'as', 'well', 'as', 'permanent', 'faults', 'can', 'significantly', 'affect', 'the', 'correct', 'online', 'operation', 'of', 'digital', 'systems', 'such', 'as', 'memories', 'and', 'microprocessors', 'a', 'memory', 'can', 'be', 'made', 'resilient', 'to', 'permanent', 'and', 'transient', 'faults', 'by', 'using', 'modular', 'redundancy', 'and', 'coding', 'in', 'this', 'paper', 'different', 'memory', 'systems', 'are', 'compared', 'these', 'systems', 'utilize', 'simplex', 'and', 'duplex', 'arrangements', 'with', 'a', 'combination', 'of', 'reed', 'solomon', 'coding', 'and', 'scrubbing', 'the', 'memory', 'systems', 'and', 'their', 'operations', 'are', 'analyzed', 'by', 'novel', 'markov', 'chains', 'to', 'characterize', 'performance', 'for', 'dynamic', 'reconfiguration', 'as', 'well', 'as', 'error', 'detection', 'and', 'correction', 'under', 'the', 'occurrence', 'of', 'permanent', 'and', 'transient', 'faults', 'for', 'a', 'specific', 'reed', 'solomon', 'code', 'the', 'duplex', 'arrangement', 'allows', 'to', 'efficiently', 'cope', 'with', 'the', 'occurrence', 'of', 'permanent', 'faults', 'while', 'the', 'use', 'of', 'scrubbing', 'allows', 'to', 'cope', 'with', 'transient', 'faults']] | [-0.20353885049962628, 0.08122610112695838, 0.04522080712922616, 0.04228353837515897, -0.04441723954369081, -0.20700197221231065, 0.0959479302591717, 0.3768493782263249, -0.2781808140243811, -0.3363325913724111, 0.21026139746072658, -0.2245271720260007, -0.1925192560738651, 0.18122135988960508, -0.15788525250536622, 0.12009381299139932, 0.054884477009181865, 0.005996204119583126, -0.02340614711283706, -0.256261016606004, 0.22832102257962106, 0.15797775242026546, 0.2799379812204279, -0.01167113305427847, 0.047833825567067834, 0.08075189045484876, 0.004377828237920767, 0.02859312781583867, -0.028939665757206967, 0.07517705022110022, 0.27928710694504844, 0.1404844489588868, 0.206636954768328, -0.47854855321202194, -0.20595649127062643, 0.06298525707188674, 0.1213672677622526, 0.1497592900784639, -0.007680394704948412, -0.27145211391325574, 0.1256072773685446, -0.24910378407366807, -0.05684084032691317, -0.11972379972576164, 0.002266831128508784, 0.12120894231657076, -0.25870028086501407, 0.0029406843495962676, 0.08280729269063158, 0.05344832534319721, -0.01953491608310287, -0.05530682011885801, 0.02900640988809755, 0.14500187842349987, -0.03368033235801704, 0.0035675897561304737, 0.1512983178254217, -0.07754886469956546, -0.22094077477231622, 0.3683899965399178, 0.017092819292884087, -0.13770942555493093, 0.20733078670309624, -0.039511834424047265, -0.12891031161416322, 0.15803209631121717, 0.22987940170423826, 0.0506703952269163, -0.17008075748890406, 0.004354571379735717, 0.07891561997530516, 0.20081925872364081, 0.1324855599705188, 0.07811069690069417, 0.17158918480163265, 0.1730391420351225, 0.04723665070923744, 0.22729553308363393, -0.11141360997862648, -0.059341022482840344, -0.2017035335957189, -0.17218763238088286, -0.16818649121978524, 0.01577767175331246, -0.07189928992647765, -0.19952732927777106, 0.3637014556006761, 0.1281168475817367, 0.11902956909943896, 0.08744648562424118, 0.31664234279014636, 0.02831364071880671, 0.1489322982433805, 0.09491396494559012, 0.15014317833993118, 0.0872103804940707, 0.1304613777774648, -0.22818661072233226, 0.18378734528596397, 0.005231216611718992] |
710.4751 | Influence of Memory Hierarchies on Predictability for Time Constrained
Embedded Software | Safety-critical embedded systems having to meet real-time constraints are
expected to be highly predictable in order to guarantee at design time that
certain timing deadlines will always be met. This requirement usually prevents
designers from utilizing caches due to their highly dynamic, thus hardly
predictable behavior. The integration of scratchpad memories represents an
alternative approach which allows the system to benefit from a performance gain
comparable to that of caches while at the same time maintaining predictability.
In this work, we compare the impact of scratchpad memories and caches on worst
case execution time (WCET) analysis results. We show that caches, despite
requiring complex techniques, can have a negative impact on the predicted WCET,
while the estimated WCET for scratchpad memories scales with the achieved
Performance gain at no extra analysis cost.
| cs.AR | safetycritical embedded systems having to meet realtime constraints are expected to be highly predictable in order to guarantee at design time that certain timing deadlines will always be met this requirement usually prevents designers from utilizing caches due to their highly dynamic thus hardly predictable behavior the integration of scratchpad memories represents an alternative approach which allows the system to benefit from a performance gain comparable to that of caches while at the same time maintaining predictability in this work we compare the impact of scratchpad memories and caches on worst case execution time wcet analysis results we show that caches despite requiring complex techniques can have a negative impact on the predicted wcet while the estimated wcet for scratchpad memories scales with the achieved performance gain at no extra analysis cost | [['safetycritical', 'embedded', 'systems', 'having', 'to', 'meet', 'realtime', 'constraints', 'are', 'expected', 'to', 'be', 'highly', 'predictable', 'in', 'order', 'to', 'guarantee', 'at', 'design', 'time', 'that', 'certain', 'timing', 'deadlines', 'will', 'always', 'be', 'met', 'this', 'requirement', 'usually', 'prevents', 'designers', 'from', 'utilizing', 'caches', 'due', 'to', 'their', 'highly', 'dynamic', 'thus', 'hardly', 'predictable', 'behavior', 'the', 'integration', 'of', 'scratchpad', 'memories', 'represents', 'an', 'alternative', 'approach', 'which', 'allows', 'the', 'system', 'to', 'benefit', 'from', 'a', 'performance', 'gain', 'comparable', 'to', 'that', 'of', 'caches', 'while', 'at', 'the', 'same', 'time', 'maintaining', 'predictability', 'in', 'this', 'work', 'we', 'compare', 'the', 'impact', 'of', 'scratchpad', 'memories', 'and', 'caches', 'on', 'worst', 'case', 'execution', 'time', 'wcet', 'analysis', 'results', 'we', 'show', 'that', 'caches', 'despite', 'requiring', 'complex', 'techniques', 'can', 'have', 'a', 'negative', 'impact', 'on', 'the', 'predicted', 'wcet', 'while', 'the', 'estimated', 'wcet', 'for', 'scratchpad', 'memories', 'scales', 'with', 'the', 'achieved', 'performance', 'gain', 'at', 'no', 'extra', 'analysis', 'cost']] | [-0.18174332518229316, 0.05529355602155909, -0.06342126719413721, 0.04393769554250563, -0.08718290721828287, -0.1778368094872514, 0.12217865605260048, 0.42512847141673166, -0.2603896536236403, -0.3598963544478245, 0.14319559450042574, -0.2534793341501702, -0.0906733437017961, 0.2163899181671723, -0.12886762889948758, 0.07190210332610701, 0.104311896159109, 0.036001479752347666, -0.0644633689631574, -0.3004279305389377, 0.2225972558892064, 0.13816069577693602, 0.3154492698694495, 0.05948994164954814, 0.0484407147547851, -0.04197374457197094, 0.0022153076654031984, -0.001683498066444317, -0.019880294048562064, 0.10106872522385058, 0.30792120368586795, 0.13873598591255193, 0.30639186510145944, -0.5180828412994742, -0.1876119376163732, 0.11818527331519307, 0.1419445893967129, 0.06446914556065829, -0.02622873779601474, -0.24582646426455484, 0.13841686753739574, -0.18774276178781735, -0.06139911330220374, -0.10644423379739182, -0.04114634937352755, -0.010388799123712957, -0.2680901916006185, -0.02977186090058901, 0.03695389701346302, 0.010999582912490674, -0.025542496400620705, -0.0710508630577489, 0.0024757105610192275, 0.15496264271805008, 0.041730537731906006, -0.009043814157573224, 0.14850144878657762, -0.1303531775695526, -0.1412003808407903, 0.3959857049313458, -0.02096552752702723, -0.19829144438898022, 0.20476086247380768, -0.10513320029448633, -0.1441224944234515, 0.1543376497680914, 0.22886393572711808, 0.04998975636254093, -0.14987617611151302, 0.03219827383740763, 0.08178537317629282, 0.25840128823112923, 0.08597623449520941, 0.15338598716929977, 0.17665223382893158, 0.22128763934597373, 0.09765834197804163, 0.1205283896997571, -0.021953414476504833, -0.12240459978982637, -0.2168590803066212, -0.1310543601509628, -0.1783963981521965, 0.020667367030083286, -0.11483076108682629, -0.10546960922974077, 0.33494049547748134, 0.2002103381515057, 0.15200703965048445, 0.1716780120755588, 0.3839918985207932, 0.11203483425461772, 0.13414586341594148, 0.14040438521822746, 0.19484237233039245, -0.04663759118270581, 0.19009259684455834, -0.20532957824550316, 0.1665602014629368, -0.04409213046627966] |
710.4752 | An Iterative Algorithm for Battery-Aware Task Scheduling on Portable
Computing Platforms | In this work we consider battery powered portable systems which either have
Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable
processors as their main processing element. An application is modeled in the
form of a precedence task graph at a coarse level of granularity. We assume
that for each task in the task graph several unique design-points are available
which correspond to different hardware implementations for FPGAs and different
voltage-frequency combinations for processors. It is assumed that performance
and total power consumption estimates for each design-point are available for
any given portable platfrom, including the peripheral components such as memory
and display power usage. We present an iterative heuristic algorithm which
finds a sequence of tasks along with an appropriate design-point for each task,
such that a deadline is met and the amount of battery energy used is as small
as possible. A detailed illustrative example along with a case study of a
real-world application of a robotic arm controller which demonstrates the
usefulness of our algorithm is also presented.
| cs.OH | in this work we consider battery powered portable systems which either have field programmable gate arrays fpga or voltage and frequency scalable processors as their main processing element an application is modeled in the form of a precedence task graph at a coarse level of granularity we assume that for each task in the task graph several unique designpoints are available which correspond to different hardware implementations for fpgas and different voltagefrequency combinations for processors it is assumed that performance and total power consumption estimates for each designpoint are available for any given portable platfrom including the peripheral components such as memory and display power usage we present an iterative heuristic algorithm which finds a sequence of tasks along with an appropriate designpoint for each task such that a deadline is met and the amount of battery energy used is as small as possible a detailed illustrative example along with a case study of a realworld application of a robotic arm controller which demonstrates the usefulness of our algorithm is also presented | [['in', 'this', 'work', 'we', 'consider', 'battery', 'powered', 'portable', 'systems', 'which', 'either', 'have', 'field', 'programmable', 'gate', 'arrays', 'fpga', 'or', 'voltage', 'and', 'frequency', 'scalable', 'processors', 'as', 'their', 'main', 'processing', 'element', 'an', 'application', 'is', 'modeled', 'in', 'the', 'form', 'of', 'a', 'precedence', 'task', 'graph', 'at', 'a', 'coarse', 'level', 'of', 'granularity', 'we', 'assume', 'that', 'for', 'each', 'task', 'in', 'the', 'task', 'graph', 'several', 'unique', 'designpoints', 'are', 'available', 'which', 'correspond', 'to', 'different', 'hardware', 'implementations', 'for', 'fpgas', 'and', 'different', 'voltagefrequency', 'combinations', 'for', 'processors', 'it', 'is', 'assumed', 'that', 'performance', 'and', 'total', 'power', 'consumption', 'estimates', 'for', 'each', 'designpoint', 'are', 'available', 'for', 'any', 'given', 'portable', 'platfrom', 'including', 'the', 'peripheral', 'components', 'such', 'as', 'memory', 'and', 'display', 'power', 'usage', 'we', 'present', 'an', 'iterative', 'heuristic', 'algorithm', 'which', 'finds', 'a', 'sequence', 'of', 'tasks', 'along', 'with', 'an', 'appropriate', 'designpoint', 'for', 'each', 'task', 'such', 'that', 'a', 'deadline', 'is', 'met', 'and', 'the', 'amount', 'of', 'battery', 'energy', 'used', 'is', 'as', 'small', 'as', 'possible', 'a', 'detailed', 'illustrative', 'example', 'along', 'with', 'a', 'case', 'study', 'of', 'a', 'realworld', 'application', 'of', 'a', 'robotic', 'arm', 'controller', 'which', 'demonstrates', 'the', 'usefulness', 'of', 'our', 'algorithm', 'is', 'also', 'presented']] | [-0.1633143602022236, 0.035429897313016614, -0.028838333921850704, -0.004457321225865079, -0.0908413801918782, -0.19480950171904018, 0.029906664001395085, 0.4580660488101698, -0.249094997025774, -0.3546740269354944, 0.12879164284961353, -0.22665569836196178, -0.12672596638072892, 0.26448963175755036, -0.0870596811022378, 0.06680315623643332, 0.10545671220790523, 0.08386518808436536, -0.018720199838017357, -0.22601125066527553, 0.24421784430575957, 0.057997092454960306, 0.26695171111939653, 0.029966858620311888, 0.1312233023982983, -0.031161962932119855, 0.01669010458759398, 0.009179810562359524, -0.04150943755697275, 0.10865431708849169, 0.3073275671686999, 0.16819280164227599, 0.2951562513508612, -0.44712471273461624, -0.16709958426404878, 0.09521809439840061, 0.11555434129245225, 0.06343532844524209, -0.08265958568691054, -0.22154690944894573, 0.12593780483404685, -0.21594619191282186, -0.044229689004298835, -0.0711371720383232, 0.03660268060255995, 0.06215152640444493, -0.2870726946344976, -0.012198847583065452, 0.027868484895970186, 0.06256665568244421, -0.036831175991600115, -0.12139862623804393, 0.02354253310615951, 0.162196067756581, -0.007070460705324963, 0.023192284797308577, 0.1690171115915291, -0.10346471913674447, -0.1490510864712719, 0.3890087376459546, 0.01249616721733695, -0.21015954003364423, 0.18085494519410922, -0.010488265489194808, -0.1781286158698744, 0.07463120717910074, 0.2090904784161553, 0.09332192295862894, -0.16094532199522724, 0.0549777613442053, 0.005622842787055387, 0.20845294501244402, 0.052654915871763866, 0.039814768079113924, 0.1888475823673486, 0.248635458216692, 0.10374502967893239, 0.17866689772511432, -0.053568634520550926, -0.049321599110997, -0.3031454214914924, -0.1716632516625049, -0.22507670733778337, 0.00564646540719661, -0.08435575092179144, -0.16160718146628433, 0.3883084963141907, 0.15119465091265738, 0.1741734858175429, 0.07960535854882826, 0.39007277641489746, 0.1047527530858393, 0.10491876805982818, 0.1264062707071259, 0.1069066122456986, 0.03420878582844688, 0.13837201534659557, -0.19510178676795303, 0.05671231236885346, -0.012258509889111988] |
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