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710.4753
Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation
Static program analysis by abstract interpretation is an efficient method to determine properties of embedded software. One example is value analysis, which determines the values stored in the processor registers. Its results are used as input to more advanced analyses, which ultimately yield information about the stack usage and the timing behavior of embedded software.
cs.LO
static program analysis by abstract interpretation is an efficient method to determine properties of embedded software one example is value analysis which determines the values stored in the processor registers its results are used as input to more advanced analyses which ultimately yield information about the stack usage and the timing behavior of embedded software
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710.4754
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer
Research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based architectures but have not focused on compatibility communication standards. This paper describes a number of issues faced when designing a VC-neutral NoC, i.e. compatible with standards such as AHB 2.0, AXI, VCI, OCP, and various other proprietary protocols, and how a layered approach to communication helps solve these issues.
cs.AR
research studies have demonstrated the feasibility and advantages of networkonchip noc over traditional busbased architectures but have not focused on compatibility communication standards this paper describes a number of issues faced when designing a vcneutral noc ie compatible with standards such as ahb 20 axi vci ocp and various other proprietary protocols and how a layered approach to communication helps solve these issues
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710.4755
Model Reuse through Hardware Design Patterns
Increasing reuse opportunities is a well-known problem for software designers as well as for hardware designers. Nonetheless, current software and hardware engineering practices have embraced different approaches to this problem. Software designs are usually modelled after a set of proven solutions to recurrent problems called design patterns. This approach differs from the component-based reuse usually found in hardware designs: design patterns do not specify unnecessary implementation details. Several authors have already proposed translating structural design patterns concepts to hardware design. In this paper we extend the discussion to behavioural design patterns. Specifically, we describe how the hardware version of the Iterator can be used to enhance model reuse.
cs.SE
increasing reuse opportunities is a wellknown problem for software designers as well as for hardware designers nonetheless current software and hardware engineering practices have embraced different approaches to this problem software designs are usually modelled after a set of proven solutions to recurrent problems called design patterns this approach differs from the componentbased reuse usually found in hardware designs design patterns do not specify unnecessary implementation details several authors have already proposed translating structural design patterns concepts to hardware design in this paper we extend the discussion to behavioural design patterns specifically we describe how the hardware version of the iterator can be used to enhance model reuse
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710.4756
Design Method for Constant Power Consumption of Differential Logic Circuits
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To address this issue, logic gates that have a constant power dissipation independent of the input signals, are used in security ICs. This paper presents a design methodology to create fully connected differential pull down networks. Fully connected differential pull down networks are transistor networks that for any complementary input combination connect all the internal nodes of the network to one of the external nodes of the network. They are memoryless and for that reason have a constant load capacitance and power consumption. This type of networks is used in specialized logic gates to guarantee a constant contribution of the internal nodes into the total power consumption of the logic gate.
cs.CR
side channel attacks are a major security concern for smart cards and other embedded devices they analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security ic to address this issue logic gates that have a constant power dissipation independent of the input signals are used in security ics this paper presents a design methodology to create fully connected differential pull down networks fully connected differential pull down networks are transistor networks that for any complementary input combination connect all the internal nodes of the network to one of the external nodes of the network they are memoryless and for that reason have a constant load capacitance and power consumption this type of networks is used in specialized logic gates to guarantee a constant contribution of the internal nodes into the total power consumption of the logic gate
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710.4757
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation
Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Hardened circuits are currently required in many applications where Fault Tolerance (FT) was not a requirement in the very near past. The use of platform FPGAs for the emulation of single-event upset effects (SEU) is gaining attention in order to speed up the FT evaluation. In this work, a new emulation system for FT evaluation with respect to SEU effects is proposed, providing shorter evaluation times by performing all the evaluation process in the FPGA and avoiding emulator-host communication bottlenecks.
cs.AR
very deep submicron and nanometer technologies have increased notably integrated circuit ic sensitiveness to radiation soft errors are currently appearing into ics working at earth surface hardened circuits are currently required in many applications where fault tolerance ft was not a requirement in the very near past the use of platform fpgas for the emulation of singleevent upset effects seu is gaining attention in order to speed up the ft evaluation in this work a new emulation system for ft evaluation with respect to seu effects is proposed providing shorter evaluation times by performing all the evaluation process in the fpga and avoiding emulatorhost communication bottlenecks
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710.4758
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling
A novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems. The idea is to construct a fully-preemptive schedule that leads to minimum energy consumption when the tasks take on approximately the average execution cycles yet still guarantees no deadline violation during the worst-case scenario. End-time for each sub-instance of the tasks obtained from the schedule is used for the on-line dynamic voltage scaling (DVS) of the tasks. For the tasks that normally require a small number of cycles but occasionally a large number of cycles to complete, such a schedule provides more opportunities for slack utilization and hence results in larger energy saving. The concept is realized by formulating the problem as a Non-Linear Programming (NLP) optimization problem. Experimental results show that, by using the proposed scheme, the total energy consumption at runtime is reduced by as high as 60% for randomly generated task sets when comparing with the static scheduling approach only using worst case workload.
cs.OH
a novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems the idea is to construct a fullypreemptive schedule that leads to minimum energy consumption when the tasks take on approximately the average execution cycles yet still guarantees no deadline violation during the worstcase scenario endtime for each subinstance of the tasks obtained from the schedule is used for the online dynamic voltage scaling dvs of the tasks for the tasks that normally require a small number of cycles but occasionally a large number of cycles to complete such a schedule provides more opportunities for slack utilization and hence results in larger energy saving the concept is realized by formulating the problem as a nonlinear programming nlp optimization problem experimental results show that by using the proposed scheme the total energy consumption at runtime is reduced by as high as 60 for randomly generated task sets when comparing with the static scheduling approach only using worst case workload
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710.4759
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12mm technology showing excellent results.
cs.AR
as technology scales down the static power is expected to become a significant fraction of the total power the exponential dependence of static power with the operating temperature makes the thermal profile estimation of highperformance ics a key issue to compute the total power dissipated in nextgenerations in this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of cmos gates the models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization the models developed are compared to measurements and spice simulations for a 012mm technology showing excellent results
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710.476
Low Power Oriented CMOS Circuit Optimization Protocol
Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a closed form model of delay in CMOS structures to define metrics for a deterministic selection of the optimization alternative. The target is delay constraint satisfaction with minimum area cost. We validate the design space exploration method, defining maximum and minimum delay bounds on logical paths. Then we adapt this method to a "constant sensitivity method" allowing to size a circuit at minimum area under a delay constraint. An optimisation protocol is finally defined to manage the trade-off performance constraint - circuit structure. These methods are implemented in an optimization tool (POPS) and validated by comparing on a 0.25$\mu$m process, the optimization efficiency obtained on various benchmarks (ISCAS?85) to that resulting from an industrial tool.
cs.AR
low power oriented circuit optimization consists in selecting the best alternative between gate sizing buffer insertion and logic structure transformation for satisfying a delay constraint at minimum area cost in this paper we used a closed form model of delay in cmos structures to define metrics for a deterministic selection of the optimization alternative the target is delay constraint satisfaction with minimum area cost we validate the design space exploration method defining maximum and minimum delay bounds on logical paths then we adapt this method to a constant sensitivity method allowing to size a circuit at minimum area under a delay constraint an optimisation protocol is finally defined to manage the tradeoff performance constraint circuit structure these methods are implemented in an optimization tool pops and validated by comparing on a 025mum process the optimization efficiency obtained on various benchmarks iscas85 to that resulting from an industrial tool
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710.4761
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about $\pm$25ps timing accuracy.
cs.AR
this paper describes two research projects that develop new lowcost techniques for testing devices with multiple highspeed 2 to 5 gbps signals each project uses commercially available components to keep costs low yet achieves performance characteristics comparable to and in some ways exceeding more expensive ate a common cmos fpgabased logic core provides flexibility adaptability and communication with controlling computers while customized positive emittercoupled logic pecl achieves multigigahertz data rates with about pm25ps timing accuracy
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710.4762
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Transfer Level) to final layout with optimizing switch transistor structure.
cs.AR
this paper presents a design flow for an improved selective multithresholdselectivemt circuit the selectivemt circuit is improved so that plural mtcells can share one switch transistor we propose the design methodology from rtlregister transfer level to final layout with optimizing switch transistor structure
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710.4763
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.
cs.AR
this paper addresses delay test for soc devices with high frequency clock domains a logic design for onchip highspeed clock generation implemented to avoid expensive test equipment is described in detail techniques for onchip clock generation meant to reduce test vector count and to increase test quality are discussed atpg results for the proposed techniques are given
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710.4764
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip
Many existing thermal management techniques focus on reducing the overall power consumption of the chip, and do not address location-specific temperature problems referred to as hotspots. We propose the use of dynamic runtime reconfiguration to shift the hotspot-inducing computation periodically and make the thermal profile more uniform. Our analysis shows that dynamic reconfiguration is an effective technique in reducing hotspots for NoCs.
cs.AR
many existing thermal management techniques focus on reducing the overall power consumption of the chip and do not address locationspecific temperature problems referred to as hotspots we propose the use of dynamic runtime reconfiguration to shift the hotspotinducing computation periodically and make the thermal profile more uniform our analysis shows that dynamic reconfiguration is an effective technique in reducing hotspots for nocs
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710.4765
Robust control of uncertain multi-inventory systems via Linear Matrix Inequality
We consider a continuous time linear multi inventory system with unknown demands bounded within ellipsoids and controls bounded within ellipsoids or polytopes. We address the problem of "-stabilizing the inventory since this implies some reduction of the inventory costs. The main results are certain conditions under which "-stabilizability is possible through a saturated linear state feedback control. All the results are based on a Linear Matrix Inequalities (LMIs) approach and on some recent techniques for the modeling and analysis of polytopic systems with saturations.
math.OC math.DS
we consider a continuous time linear multi inventory system with unknown demands bounded within ellipsoids and controls bounded within ellipsoids or polytopes we address the problem of stabilizing the inventory since this implies some reduction of the inventory costs the main results are certain conditions under which stabilizability is possible through a saturated linear state feedback control all the results are based on a linear matrix inequalities lmis approach and on some recent techniques for the modeling and analysis of polytopic systems with saturations
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710.4766
Gravitational Anomaly and Hawking Radiation of Brane World Black Holes
We apply Wilczek and his collaborators' anomaly cancellation approach to the 3-dimensional Schwarzschild- and BTZ-like brane world black holes induced by the generalized C metrics in the Randall-Sundrum scenario. Based on the fact that the horizon of brane world black hole will extend into the bulk spacetime, we do the calculation from the bulk generalized C metrics side and show that this approach also reproduces the correct Hawking radiation for these brane world black holes. Besides, since this approach does not involve the dynamical equation, it also shows that the Hawking radiation is only a kinematic effect.
hep-th
we apply wilczek and his collaborators anomaly cancellation approach to the 3dimensional schwarzschild and btzlike brane world black holes induced by the generalized c metrics in the randallsundrum scenario based on the fact that the horizon of brane world black hole will extend into the bulk spacetime we do the calculation from the bulk generalized c metrics side and show that this approach also reproduces the correct hawking radiation for these brane world black holes besides since this approach does not involve the dynamical equation it also shows that the hawking radiation is only a kinematic effect
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710.4767
Relativistic hydrodynamics with strangeness production
The relativistic hydrodynamic approach is used to describe production of strangeness and/or heavy quarks in ultrarelativistic heavy ion reactions. Production processes are important ingredients of dissipative effects in the hadronic liquid. Beyond viscosity also chemo- and thermo-diffusion processes are considered. This also allows to specify chemical and thermal freeze-out conditions.
hep-ph
the relativistic hydrodynamic approach is used to describe production of strangeness andor heavy quarks in ultrarelativistic heavy ion reactions production processes are important ingredients of dissipative effects in the hadronic liquid beyond viscosity also chemo and thermodiffusion processes are considered this also allows to specify chemical and thermal freezeout conditions
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710.4768
A Conversation with Dorothy Gilford
In 1946, Public Law 588 of the 79th Congress established the Office of Naval Research (ONR). Its mission was to plan, foster and encourage scientific research in support of Naval problems. The establishment of ONR predates the National Science Foundation and initiated the refocusing of scientific infrastructure in the United States following World War II. At the time, ONR was the only source for federal support of basic research in the United States. Dorothy Gilford was one of the first Heads of the Probability and Statistics program at the Office of Naval Research (1955 to 1962), and she went on to serve as Director of the Mathematical Sciences Division (1962 to 1968). During her time at ONR, Dorothy influenced many areas of statistics and mathematics and was ahead of her time in promoting interdisciplinary projects. Dorothy continued her career at the National Center for Education Statistics (1969 to 1974). She was active in starting international comparisons of education outcomes in different countries, which has influenced educational policy in the United States. Dorothy went on to serve in many capacities at the National Academy of Sciences, including Director of Human Resources Studies (1975 to 1978), Senior Statistician on the Committee on National Statistics (1978 to 1988) and Director of the Board on International Comparative Studies in Education (1988 to 1994). The following is a conversation we had with Dorothy Gilford in March of 2004. We found her to be an interesting person and a remarkable statistician. We hope you agree.
stat.ME
in 1946 public law 588 of the 79th congress established the office of naval research onr its mission was to plan foster and encourage scientific research in support of naval problems the establishment of onr predates the national science foundation and initiated the refocusing of scientific infrastructure in the united states following world war ii at the time onr was the only source for federal support of basic research in the united states dorothy gilford was one of the first heads of the probability and statistics program at the office of naval research 1955 to 1962 and she went on to serve as director of the mathematical sciences division 1962 to 1968 during her time at onr dorothy influenced many areas of statistics and mathematics and was ahead of her time in promoting interdisciplinary projects dorothy continued her career at the national center for education statistics 1969 to 1974 she was active in starting international comparisons of education outcomes in different countries which has influenced educational policy in the united states dorothy went on to serve in many capacities at the national academy of sciences including director of human resources studies 1975 to 1978 senior statistician on the committee on national statistics 1978 to 1988 and director of the board on international comparative studies in education 1988 to 1994 the following is a conversation we had with dorothy gilford in march of 2004 we found her to be an interesting person and a remarkable statistician we hope you agree
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710.4769
Chiral behavior of pseudo-Goldstone boson masses and decay constants in 2+1 flavor QCD
We present preliminary results for the chiral behavior of charged pseudo-Goldstone-boson masses and decay constants. These are obtained in simulations with N_f=2+1 flavors of tree-level, O(a)-improved Wilson sea quarks. In these simulations, mesons are composed of either valence quarks discretized in the same way as the sea quarks (unitary simulations) or of overlap valence quarks (mixed-action simulations). We find that the chiral behavior of the pseudoscalar meson masses in the mixed-action calculations cannot be explained with continuum, partially-quenched chiral perturbation theory. We show that the inclusion of O(a^2) unitarity violations in the chiral expansion resolves this discrepancy and that the size of the unitarity violations required are consistent with those which we observe in the zero-momentum, scalar-isotriplet-meson propagator.
hep-lat hep-ph
we present preliminary results for the chiral behavior of charged pseudogoldstoneboson masses and decay constants these are obtained in simulations with n_f21 flavors of treelevel oaimproved wilson sea quarks in these simulations mesons are composed of either valence quarks discretized in the same way as the sea quarks unitary simulations or of overlap valence quarks mixedaction simulations we find that the chiral behavior of the pseudoscalar meson masses in the mixedaction calculations cannot be explained with continuum partiallyquenched chiral perturbation theory we show that the inclusion of oa2 unitarity violations in the chiral expansion resolves this discrepancy and that the size of the unitarity violations required are consistent with those which we observe in the zeromomentum scalarisotripletmeson propagator
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710.477
Constructing Spin Interference Devices from Nanometric Rings
The study of nanospintronic devices utilizing coherent transport through molecular scale multiply-connected geometries in the presence of moderate magnetic fields is presented. It is shown how two types of simple devices, spin filters and spin splitters (or Stern-Gerlach devices) may be constructed from molecular nanometric rings utilizing the Aharonov-Bohm effect. The current is calculated within a single electron approximation and within a many-body master equation approach where charging effects are accounted for in the Coulomb Blockade regime. We provide rules and tools to develop and analyze efficient spintronic devices based on nanometric interferometers.
cond-mat.str-el cond-mat.mtrl-sci
the study of nanospintronic devices utilizing coherent transport through molecular scale multiplyconnected geometries in the presence of moderate magnetic fields is presented it is shown how two types of simple devices spin filters and spin splitters or sterngerlach devices may be constructed from molecular nanometric rings utilizing the aharonovbohm effect the current is calculated within a single electron approximation and within a manybody master equation approach where charging effects are accounted for in the coulomb blockade regime we provide rules and tools to develop and analyze efficient spintronic devices based on nanometric interferometers
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710.4771
Non-equilibrium nanothermodynamics
Entropy production for a system not in the thermodynamic limit is formulated using Hill's nanothermodynamics, in which a macroscopic ensemble of such systems is considered. External influence of the environment on the average nanosystem is connected to irreversible work with an explicit formula based on Jarzynsky equality. Entropy production retains its usual form as a sum of products of fluxes and forces and Onsager's symmetry principle is proven to hold for the average nanosystem if it is valid for the macroscopic ensemble, by two methods. The first one provides expressions that relate the coefficients of the two systems. The second gives a general condition for a system under a external force to preserve Onsager's symmetry.
cond-mat.stat-mech
entropy production for a system not in the thermodynamic limit is formulated using hills nanothermodynamics in which a macroscopic ensemble of such systems is considered external influence of the environment on the average nanosystem is connected to irreversible work with an explicit formula based on jarzynsky equality entropy production retains its usual form as a sum of products of fluxes and forces and onsagers symmetry principle is proven to hold for the average nanosystem if it is valid for the macroscopic ensemble by two methods the first one provides expressions that relate the coefficients of the two systems the second gives a general condition for a system under a external force to preserve onsagers symmetry
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710.4772
One-dimensional Model of a Gamma Klystron
A new scheme for amplification of coherent gamma rays is proposed. The key elements are crystalline undulators - single crystals with periodically bent crystallographic planes exposed to a high energy beam of charged particles undergoing channeling inside the crystals. The scheme consists of two such crystals separated by a vacuum gap. The beam passes the crystals successively. The particles perform undulator motion inside the crystals following the periodic shape of the crystallographic planes. Gamma rays passing the crystals parallel to the beam get amplified due to interaction with the particles inside the crystals. The term `gamma klystron' is proposed for the scheme because its operational principles are similar to those of the optical klystron. A more simple one-crystal scheme is considered as well for the sake of comparison. It is shown that the gamma ray amplification in the klystron scheme can be reached at considerably lower particle densities than in the one-crystal scheme, provided that the gap between the crystals is sufficiently large.
physics.acc-ph physics.optics
a new scheme for amplification of coherent gamma rays is proposed the key elements are crystalline undulators single crystals with periodically bent crystallographic planes exposed to a high energy beam of charged particles undergoing channeling inside the crystals the scheme consists of two such crystals separated by a vacuum gap the beam passes the crystals successively the particles perform undulator motion inside the crystals following the periodic shape of the crystallographic planes gamma rays passing the crystals parallel to the beam get amplified due to interaction with the particles inside the crystals the term gamma klystron is proposed for the scheme because its operational principles are similar to those of the optical klystron a more simple onecrystal scheme is considered as well for the sake of comparison it is shown that the gamma ray amplification in the klystron scheme can be reached at considerably lower particle densities than in the onecrystal scheme provided that the gap between the crystals is sufficiently large
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710.4773
The ground state phases of orbitally degenerate spinel oxides
I review the microscopic spin-orbital Hamiltonian and ground state properties of spin one-half spinel oxides with threefold $t_{2g}$ orbital degeneracy. It is shown that for any orbital configuration a ground state of corresponding spin only Hamiltonian is infinitely degenerate in the classical limit. The extensive classical degeneracy is lifted by the quantum nature of the spins, an effect similar to order-out-of-disorder phenomenon by quantum fluctuations. This drives the system to a non-magnetic spin-singlet dimer manifold with a residual degeneracy due to relative orientation of dimers. The magneto-elastic mechanism of lifting the ``orientational'' degeneracy is also briefly reviewed.
cond-mat.str-el cond-mat.mtrl-sci
i review the microscopic spinorbital hamiltonian and ground state properties of spin onehalf spinel oxides with threefold t_2g orbital degeneracy it is shown that for any orbital configuration a ground state of corresponding spin only hamiltonian is infinitely degenerate in the classical limit the extensive classical degeneracy is lifted by the quantum nature of the spins an effect similar to orderoutofdisorder phenomenon by quantum fluctuations this drives the system to a nonmagnetic spinsinglet dimer manifold with a residual degeneracy due to relative orientation of dimers the magnetoelastic mechanism of lifting the orientational degeneracy is also briefly reviewed
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710.4774
On the integrability of holomorphic vector fields
We determine topological and algebraic conditions for a germ of holomorphic foliation $\mathcal F(X)$ induced by a generic vector field $X$ on $(\mathbb{C}^{3},0)$ to have a holomorphic first integral, i.e., a germ of holomorphic map $F \colon(\mathbb{C}^{3},0)\longrightarrow(\mathbb{C}^{2},0)$ such that the leaves of $\mathcal F(X)$ are contained in the level curves of $F$.
math.CV
we determine topological and algebraic conditions for a germ of holomorphic foliation mathcal fx induced by a generic vector field x on mathbbc30 to have a holomorphic first integral ie a germ of holomorphic map f colonmathbbc30longrightarrowmathbbc20 such that the leaves of mathcal fx are contained in the level curves of f
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710.4775
Two-Loop Heavy-Flavor Contribution to Bhabha Scattering
We evaluate the two-loop QED corrections to the Bhabha scattering cross section which involve the vacuum polarization by heavy fermions of arbitrary mass m_f >> m_e. The results are valid for generic values of the Mandelstam invariants s,t,u >> m_e^2.
hep-ph
we evaluate the twoloop qed corrections to the bhabha scattering cross section which involve the vacuum polarization by heavy fermions of arbitrary mass m_f m_e the results are valid for generic values of the mandelstam invariants stu m_e2
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710.4776
Small-scale structure and dynamics of the lower solar atmosphere
The chromosphere of the quiet Sun is a highly intermittent and dynamic phenomenon. Three-dimensional radiation (magneto-)hydrodynamic simulations exhibit a mesh-like pattern of hot shock fronts and cool expanding post-shock regions in the sub-canopy part of the inter-network. This domain might be called "fluctosphere". The pattern is produced by propagating shock waves, which are excited at the top of the convection zone and in the photospheric overshoot layer. New high-resolution observations reveal a ubiquitous small-scale pattern of bright structures and dark regions in-between. Although it qualitatively resembles the picture seen in models, more observations - e.g. with the future ALMA - are needed for thorough comparisons with present and future models. Quantitative comparisons demand for synthetic intensity maps and spectra for the three-dimensional (magneto-)hydrodynamic simulations. The necessary radiative transfer calculations, which have to take into account deviations from local thermodynamic equilibrium, are computationally very involved so that no reliable results have been produced so far. Until this task becomes feasible, we have to rely on careful qualitative comparisons of simulations and observations. Here we discuss what effects have to be considered for such a comparison. Nevertheless we are now on the verge of assembling a comprehensive picture of the solar chromosphere in inter-network regions as dynamic interplay of shock waves and structuring and guiding magnetic fields.
astro-ph
the chromosphere of the quiet sun is a highly intermittent and dynamic phenomenon threedimensional radiation magnetohydrodynamic simulations exhibit a meshlike pattern of hot shock fronts and cool expanding postshock regions in the subcanopy part of the internetwork this domain might be called fluctosphere the pattern is produced by propagating shock waves which are excited at the top of the convection zone and in the photospheric overshoot layer new highresolution observations reveal a ubiquitous smallscale pattern of bright structures and dark regions inbetween although it qualitatively resembles the picture seen in models more observations eg with the future alma are needed for thorough comparisons with present and future models quantitative comparisons demand for synthetic intensity maps and spectra for the threedimensional magnetohydrodynamic simulations the necessary radiative transfer calculations which have to take into account deviations from local thermodynamic equilibrium are computationally very involved so that no reliable results have been produced so far until this task becomes feasible we have to rely on careful qualitative comparisons of simulations and observations here we discuss what effects have to be considered for such a comparison nevertheless we are now on the verge of assembling a comprehensive picture of the solar chromosphere in internetwork regions as dynamic interplay of shock waves and structuring and guiding magnetic fields
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710.4777
Periodicity-dependence of the ferroelectric properties in BiFeO3/SrTiO3 multiferroic superlattices
Artificial superlattices of (BiFeO3)m(SrTiO3)m (m= 1 to 10 unit cells) consisting of multiferroic BiFeO3 and insulating SrTiO3 layers were fabricated on (100)-oriented SrTiO3 substrates by pulsed laser ablation. The remnant polarization and leakage current behavior were studied varying the periodicity (8-80A) of the superlattice. The leakage current was reduced by few orders of magnitude on increase of periodicity compared to single layer BiFeO3 thin films. Reduced leakage and intrinsic polarization hysteresis was observed and was confirmed by PUND analysis for periodicities in the range 20-60A. The leakage current was observed to be dominated by space charge limited conduction
cond-mat.mtrl-sci cond-mat.str-el
artificial superlattices of bifeo3msrtio3m m 1 to 10 unit cells consisting of multiferroic bifeo3 and insulating srtio3 layers were fabricated on 100oriented srtio3 substrates by pulsed laser ablation the remnant polarization and leakage current behavior were studied varying the periodicity 880a of the superlattice the leakage current was reduced by few orders of magnitude on increase of periodicity compared to single layer bifeo3 thin films reduced leakage and intrinsic polarization hysteresis was observed and was confirmed by pund analysis for periodicities in the range 2060a the leakage current was observed to be dominated by space charge limited conduction
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710.4778
The Hasse principle for pairs of diagonal cubic forms
By means of the Hardy-Littlewood method, we apply a new mean value theorem for exponential sums to confirm the truth, over the rational numbers, of the Hasse principle for pairs of diagonal cubic forms in thirteen or more variables.
math.NT
by means of the hardylittlewood method we apply a new mean value theorem for exponential sums to confirm the truth over the rational numbers of the hasse principle for pairs of diagonal cubic forms in thirteen or more variables
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710.4779
Leading Pollicott-Ruelle Resonances for Chaotic Area-Preserving Maps
Recent investigations in nonlinear sciences show that not only hyperbolic but also mixed dynamical systems may exhibit exponential relaxation in the chaotic regime. The relaxation rates, which lead the decay of probability distributions and correlation functions, are related to the classical evolution resolvent (Perron-Frobenius operator) pole logarithm, the so called Pollicott-Ruelle resonances. In this Brief Report, the leading Pollicott-Ruelle resonances are calculated analytically for a general class of area-preserving maps. Besides the leading resonances related to the diffusive modes of momentum dynamics (slow rate), we also calculate the leading faster rate, related to the angular correlations. The analytical results are compared to the existing results in the literature.
nlin.CD
recent investigations in nonlinear sciences show that not only hyperbolic but also mixed dynamical systems may exhibit exponential relaxation in the chaotic regime the relaxation rates which lead the decay of probability distributions and correlation functions are related to the classical evolution resolvent perronfrobenius operator pole logarithm the so called pollicottruelle resonances in this brief report the leading pollicottruelle resonances are calculated analytically for a general class of areapreserving maps besides the leading resonances related to the diffusive modes of momentum dynamics slow rate we also calculate the leading faster rate related to the angular correlations the analytical results are compared to the existing results in the literature
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710.478
Querying XML Documents in Logic Programming
Extensible Markup Language (XML) is a simple, very flexible text format derived from SGML. Originally designed to meet the challenges of large-scale electronic publishing, XML is also playing an increasingly important role in the exchange of a wide variety of data on the Web and elsewhere. XPath language is the result of an effort to provide address parts of an XML document. In support of this primary purpose, it becomes in a query language against an XML document. In this paper we present a proposal for the implementation of the XPath language in logic programming. With this aim we will describe the representation of XML documents by means of a logic program. Rules and facts can be used for representing the document schema and the XML document itself. In particular, we will present how to index XML documents in logic programs: rules are supposed to be stored in main memory, however facts are stored in secondary memory by using two kind of indexes: one for each XML tag, and other for each group of terminal items. In addition, we will study how to query by means of the XPath language against a logic program representing an XML document. It evolves the specialization of the logic program with regard to the XPath expression. Finally, we will also explain how to combine the indexing and the top-down evaluation of the logic program. To appear in Theory and Practice of Logic Programming (TPLP)"
cs.PL cs.DB
extensible markup language xml is a simple very flexible text format derived from sgml originally designed to meet the challenges of largescale electronic publishing xml is also playing an increasingly important role in the exchange of a wide variety of data on the web and elsewhere xpath language is the result of an effort to provide address parts of an xml document in support of this primary purpose it becomes in a query language against an xml document in this paper we present a proposal for the implementation of the xpath language in logic programming with this aim we will describe the representation of xml documents by means of a logic program rules and facts can be used for representing the document schema and the xml document itself in particular we will present how to index xml documents in logic programs rules are supposed to be stored in main memory however facts are stored in secondary memory by using two kind of indexes one for each xml tag and other for each group of terminal items in addition we will study how to query by means of the xpath language against a logic program representing an xml document it evolves the specialization of the logic program with regard to the xpath expression finally we will also explain how to combine the indexing and the topdown evaluation of the logic program to appear in theory and practice of logic programming tplp
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710.4781
Distributions for Higgs + jet at hadron colliders: MSSM vs SM
We present pseudorapidity and transverse momentum distributions for the cross section for the production of the lightest neutral Higgs boson in association with a high-p_T hadronic jet, calculated in the framework of the minimal supersymmetric standard model. We discuss the theoretical predictions for the differential cross sections at the Large Hadron Collider and the Tevatron. In particular, we present the differences in the distributions compared to the Standard Model.
hep-ph hep-ex
we present pseudorapidity and transverse momentum distributions for the cross section for the production of the lightest neutral higgs boson in association with a highp_t hadronic jet calculated in the framework of the minimal supersymmetric standard model we discuss the theoretical predictions for the differential cross sections at the large hadron collider and the tevatron in particular we present the differences in the distributions compared to the standard model
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710.4782
q-Dependence of the giant bond-stretching phonon anomaly in the stripe compound La1.48Nd0.4Sr0.12CuO4 measured by IXS
Inelastic x-ray scattering (IXS) was used to study the Cu-O bond-stretching vibrations in the static stripe phase compound La1.48Nd0.4Sr0.12CuO4. It was found that the intrinsic width in Q-space of the previously reported huge anomalous phonon softening and broadening is approximately 0.08r.l.u HWHM. A detailed comparison was also made to inelastic neutron scattering (INS) studies, which indicate a two-peak lineshape (with superimposed broad and narrow peaks) in the vicinity of the anomaly. The high resolution IXS data show that the narrow peak is mostly an artifact of the poor transverse Q-resolution of INS. Otherwise the agreement between the INS and IXS was excellent.
cond-mat.supr-con
inelastic xray scattering ixs was used to study the cuo bondstretching vibrations in the static stripe phase compound la148nd04sr012cuo4 it was found that the intrinsic width in qspace of the previously reported huge anomalous phonon softening and broadening is approximately 008rlu hwhm a detailed comparison was also made to inelastic neutron scattering ins studies which indicate a twopeak lineshape with superimposed broad and narrow peaks in the vicinity of the anomaly the high resolution ixs data show that the narrow peak is mostly an artifact of the poor transverse qresolution of ins otherwise the agreement between the ins and ixs was excellent
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710.4783
The ANTARES Detector: Electronics and Readout
In this paper, we illustrate the main features of the electronics and data acquisition systems of the ANTARES apparatus, a large volume, deep-sea neutrino telescope under construction in the Mediterranean Sea off the coast of Toulon, France. The apparatus consists of an array of 900 large-area photomultipliers arranged on 12 detection lines, 5 of which are in data acquisition since January 2007. The schedule is to complete the apparatus construction in early 2008.
astro-ph
in this paper we illustrate the main features of the electronics and data acquisition systems of the antares apparatus a large volume deepsea neutrino telescope under construction in the mediterranean sea off the coast of toulon france the apparatus consists of an array of 900 largearea photomultipliers arranged on 12 detection lines 5 of which are in data acquisition since january 2007 the schedule is to complete the apparatus construction in early 2008
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710.4784
Linearization of fourth-order ordinary differential equations by point transformations
We present here the solution of the problem on linearization of fourth-order equations by means of point transformations. We show that all fourth-order equations that are linearizable by point transformations are contained in the class of equations which is linear in the third-order derivative. We provide the linearization test and describe the procedure for obtaining the linearizing transformations as well as the linearized equation.
math.CA
we present here the solution of the problem on linearization of fourthorder equations by means of point transformations we show that all fourthorder equations that are linearizable by point transformations are contained in the class of equations which is linear in the thirdorder derivative we provide the linearization test and describe the procedure for obtaining the linearizing transformations as well as the linearized equation
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710.4785
Influence of surface diffusion on catalytic reactivity of spatially inhomogeneous surfaces mean field modeling
Kinetics of model catalytic processes proceeding on inhomogeneous surfaces is studied. We employ an extended mean-field model that takes into account surface inhomogeneities. The influence of surface diffusion of adsorbent on the kinetics of the catalytic process is investigated. It is shown that diffusion is responsible for differences in the reaction rate of systems with different arrangements of active sites. The presence of cooperative effects between inactive and active sites is demonstrated and the conditions when these effects are important are discussed. We show that basic catalytic phenomena on nonuniform surfaces can be studied with mean-field modeling methods.
cond-mat.mtrl-sci
kinetics of model catalytic processes proceeding on inhomogeneous surfaces is studied we employ an extended meanfield model that takes into account surface inhomogeneities the influence of surface diffusion of adsorbent on the kinetics of the catalytic process is investigated it is shown that diffusion is responsible for differences in the reaction rate of systems with different arrangements of active sites the presence of cooperative effects between inactive and active sites is demonstrated and the conditions when these effects are important are discussed we show that basic catalytic phenomena on nonuniform surfaces can be studied with meanfield modeling methods
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710.4786
Proper motions of field L and T dwarfs
The proper motion measurements for 143 previously known L and T dwarfs are presented. From this sample we identify and discuss 8 high velocity L dwarfs. We also find 4 new wide common proper motion binaries/multiple systems. Using the moving cluster methods we have also identified a number of L dwarfs that may be members of the Ursa Major (age ~400 Myr), the Hyades (age ~625 Myr) and the Pleiades (age ~125 Myr) moving groups.
astro-ph
the proper motion measurements for 143 previously known l and t dwarfs are presented from this sample we identify and discuss 8 high velocity l dwarfs we also find 4 new wide common proper motion binariesmultiple systems using the moving cluster methods we have also identified a number of l dwarfs that may be members of the ursa major age 400 myr the hyades age 625 myr and the pleiades age 125 myr moving groups
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710.4787
SUSY sensitivity in final states with leptons, jets, and missing transverse energy
Final states with leptons, jets and missing transverse energy are a promising way to detect Supersymmetry at the Large Hadron Collider. Results of simulation studies performed by the CMS and ATLAS collaborations are presented. The discovery of new physics is shown to be possible within the first fb^-1 of collected integrated luminosity.
hep-ph
final states with leptons jets and missing transverse energy are a promising way to detect supersymmetry at the large hadron collider results of simulation studies performed by the cms and atlas collaborations are presented the discovery of new physics is shown to be possible within the first fb1 of collected integrated luminosity
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710.4788
A Bayesian Hierarchical Model for the Analysis of a Longitudinal Dynamic Contrast-Enhanced MRI Cancer Study
Imaging in clinical oncology trials provides a wealth of information that contributes to the drug development process, especially in early phase studies. This paper focuses on kinetic modeling in DCE-MRI, inspired by mixed-effects models that are frequently used in the analysis of clinical trials. Instead of summarizing each scanning session as a single kinetic parameter -- such as median $\ktrans$ across all voxels in the tumor ROI -- we propose to analyze all voxel time courses from all scans and across all subjects simultaneously in a single model. The kinetic parameters from the usual non-linear regression model are decomposed into unique components associated with factors from the longitudinal study; e.g., treatment, patient and voxel effects. A Bayesian hierarchical model provides the framework in order to construct a data model, a parameter model, as well as prior distributions. The posterior distribution of the kinetic parameters is estimated using Markov chain Monte Carlo (MCMC) methods. Hypothesis testing at the study level for an overall treatment effect is straightforward and the patient- and voxel-level parameters capture random effects that provide additional information at various levels of resolution to allow a thorough evaluation of the clinical trial. The proposed method is validated with a breast cancer study, where the subjects were imaged before and after two cycles of chemotherapy, demonstrating the clinical potential of this method to longitudinal oncology studies.
stat.AP physics.med-ph
imaging in clinical oncology trials provides a wealth of information that contributes to the drug development process especially in early phase studies this paper focuses on kinetic modeling in dcemri inspired by mixedeffects models that are frequently used in the analysis of clinical trials instead of summarizing each scanning session as a single kinetic parameter such as median ktrans across all voxels in the tumor roi we propose to analyze all voxel time courses from all scans and across all subjects simultaneously in a single model the kinetic parameters from the usual nonlinear regression model are decomposed into unique components associated with factors from the longitudinal study eg treatment patient and voxel effects a bayesian hierarchical model provides the framework in order to construct a data model a parameter model as well as prior distributions the posterior distribution of the kinetic parameters is estimated using markov chain monte carlo mcmc methods hypothesis testing at the study level for an overall treatment effect is straightforward and the patient and voxellevel parameters capture random effects that provide additional information at various levels of resolution to allow a thorough evaluation of the clinical trial the proposed method is validated with a breast cancer study where the subjects were imaged before and after two cycles of chemotherapy demonstrating the clinical potential of this method to longitudinal oncology studies
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710.4789
Sinh-Gordon Boundary TBA and Boundary Liouville Reflection Amplitude
The ground state energy of the sinh-Gordon model defined on the strip is studied using the boundary thermodynamic Bethe ansatz equation. Its ultraviolet (small width of the strip) behavior is compared with the one obtained from the boundary Liouville reflection amplitude. The results are in perfect agreement in the allowable range of the parameters and provide convincing support for both approaches. We also describe how the ultraviolet limit of the effective central charge can exceed one in the parameter range when the Liouville zero mode forms a bound state.
hep-th
the ground state energy of the sinhgordon model defined on the strip is studied using the boundary thermodynamic bethe ansatz equation its ultraviolet small width of the strip behavior is compared with the one obtained from the boundary liouville reflection amplitude the results are in perfect agreement in the allowable range of the parameters and provide convincing support for both approaches we also describe how the ultraviolet limit of the effective central charge can exceed one in the parameter range when the liouville zero mode forms a bound state
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710.479
Variational principle for Hamiltonians with degenerate bottom
We consider perturbations of Hamiltonians whose Fourier symbol attains its minimum along a hypersurface. Such operators arise in several domains, like spintronics, theory of supercondictivity, or theory of superfluidity. Variational estimates for the number of eigenvalues below the essential spectrum in terms of the perturbation potential are provided. In particular, we provide an elementary proof that negative potentials lead to an infinite discrete spectrum.
math-ph math.MP
we consider perturbations of hamiltonians whose fourier symbol attains its minimum along a hypersurface such operators arise in several domains like spintronics theory of supercondictivity or theory of superfluidity variational estimates for the number of eigenvalues below the essential spectrum in terms of the perturbation potential are provided in particular we provide an elementary proof that negative potentials lead to an infinite discrete spectrum
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710.4791
Test vectors for trilinear forms, when two representations are unramified
Let F be a finite extension of Qp and G be GL(2,F). When V is the tensor product of three infinite dimensional, irreducible, admissible representations of G, the space of G-invariant linear forms has dimension 0 or 1. When a non-zero linear form exists, one wants to find an element of V which is not in its kernel : this is a test vector. Gross and Prasad found explicit test vectors when the three representations are unramified principal series, and when the three representations are unramified twists of the Steinberg representation. In this paper, we find an explicit test vector when two of the representations are unramified principal series and the third one has ramification at least 1.
math.NT
let f be a finite extension of qp and g be gl2f when v is the tensor product of three infinite dimensional irreducible admissible representations of g the space of ginvariant linear forms has dimension 0 or 1 when a nonzero linear form exists one wants to find an element of v which is not in its kernel this is a test vector gross and prasad found explicit test vectors when the three representations are unramified principal series and when the three representations are unramified twists of the steinberg representation in this paper we find an explicit test vector when two of the representations are unramified principal series and the third one has ramification at least 1
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710.4792
Sur une conjecture de Dehornoy
Let M_n be the n! * n! matrix indexed by permutations of S_n, defined by M_n(sigma,tau)=1 if every descent of tau^{-1} is also a descent of sigma, and M_n(sigma,tau)=0 otherwise. We prove the following result, conjectured by P. Dehornoy: the characteristic polynomial P_n(x)=|xI-M_n| of M_n divides P_{n+1}(x) in Z[x].
math.CO math.GR
let m_n be the n n matrix indexed by permutations of s_n defined by m_nsigmatau1 if every descent of tau1 is also a descent of sigma and m_nsigmatau0 otherwise we prove the following result conjectured by p dehornoy the characteristic polynomial p_nxxim_n of m_n divides p_n1x in zx
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710.4793
Unified Modeling of Complex Real-Time Control Systems
Complex real-time control system is a software dense and algorithms dense system, which needs modern software engineering techniques to design. UML is an object-oriented industrial standard modeling language, used more and more in real-time domain. This paper first analyses the advantages and problems of using UML for real-time control systems design. Then, it proposes an extension of UML-RT to support time-continuous subsystems modeling. So we can unify modeling of complex real-time control systems on UML-RT platform, from requirement analysis, model design, simulation, until generation code.
cs.SE
complex realtime control system is a software dense and algorithms dense system which needs modern software engineering techniques to design uml is an objectoriented industrial standard modeling language used more and more in realtime domain this paper first analyses the advantages and problems of using uml for realtime control systems design then it proposes an extension of umlrt to support timecontinuous subsystems modeling so we can unify modeling of complex realtime control systems on umlrt platform from requirement analysis model design simulation until generation code
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710.4794
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and then extend this to two level cache systems. In addition to leakage, our studies also account for the dynamic power expanded as a result of cache misses. Our results show that one can often reduce overall power by increasing the size of the L2 cache if we only allow one pair of Vth/T_{ox} in L2. However, if we allow the memory cells and the peripherals to have their own Vth's and T_{ox}'s, we show that a two-level cache system with smaller L2's will yield less total leakage. We further show that two Vth's and two T_{ox}'s are sufficient to get close to an optimal solution, and that Vth is generally a better design knob than T_{ox} for leakage optimization, thus it is better to restrict the number of T_{ox}'s rather than Vth's if cost is a concern.
cs.AR
in this paper we investigate the impact of t_ox and vth on power performance tradeoffs for onchip caches we start by examining the optimization of the various components of a single level cache and then extend this to two level cache systems in addition to leakage our studies also account for the dynamic power expanded as a result of cache misses our results show that one can often reduce overall power by increasing the size of the l2 cache if we only allow one pair of vtht_ox in l2 however if we allow the memory cells and the peripherals to have their own vths and t_oxs we show that a twolevel cache system with smaller l2s will yield less total leakage we further show that two vths and two t_oxs are sufficient to get close to an optimal solution and that vth is generally a better design knob than t_ox for leakage optimization thus it is better to restrict the number of t_oxs rather than vths if cost is a concern
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710.4795
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the test access mechanism. Experimental results are based on ITC'02 benchmarks and on two open core processors compliant with MIPS and SPARC instruction set. The results show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time without additional cost in area and pins.
cs.AR
the increasing complexity and the short life cycles of embedded systems are pushing the current systemonchip designs towards a rapid increasing on the number of programmable processing units while decreasing the gate count for custom logic considering this trend this work proposes a test planning method capable of reusing available processors as test sources and sinks and the onchip network as the test access mechanism experimental results are based on itc02 benchmarks and on two open core processors compliant with mips and sparc instruction set the results show that the cooperative use of both the onchip network and the embedded processors can increase the test parallelism and reduce the test time without additional cost in area and pins
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710.4796
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware
Due to the emergence of highly dynamic multimedia applications there is a need for flexible platforms and run-time scheduling support for embedded systems. Dynamic Reconfigurable Hardware (DRHW) is a promising candidate to provide this flexibility but, currently, not sufficient run-time scheduling support to deal with the run-time reconfigurations exists. Moreover, executing at run-time a complex scheduling heuristic to provide this support may generate an excessive run-time penalty. Hence, we have developed a hybrid design/run-time prefetch heuristic that schedules the reconfigurations at run-time, but carries out the scheduling computations at design-time by carefully identifying a set of near-optimal schedules that can be selected at run-time. This approach provides run-time flexibility with a negligible penalty.
cs.AR
due to the emergence of highly dynamic multimedia applications there is a need for flexible platforms and runtime scheduling support for embedded systems dynamic reconfigurable hardware drhw is a promising candidate to provide this flexibility but currently not sufficient runtime scheduling support to deal with the runtime reconfigurations exists moreover executing at runtime a complex scheduling heuristic to provide this support may generate an excessive runtime penalty hence we have developed a hybrid designruntime prefetch heuristic that schedules the reconfigurations at runtime but carries out the scheduling computations at designtime by carefully identifying a set of nearoptimal schedules that can be selected at runtime this approach provides runtime flexibility with a negligible penalty
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710.4797
Rapid Generation of Thermal-Safe Test Schedules
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.
cs.OH
overheating has been acknowledged as a major issue in testing complex socs several power constrained systemlevel dft solutions power constrained test scheduling have recently been proposed to tackle this problem however as it will be shown in this paper imposing a chiplevel maximum power constraint doesnt necessarily avoid local overheating due to the nonuniform distribution of power across the chip this paper proposes a new approach for dealing with overheating during test by embedding thermal awareness into test scheduling the proposed approach facilitates rapid generation of thermalsafer test schedules without requiring timeconsuming thermal simulations this is achieved by employing a lowcomplexity test session thermal model used to guide the test schedule generation algorithm this approach reduces the chances of a design respin due to potential overheating during test
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710.4798
System Synthesis for Networks of Programmable Blocks
The advent of sensor networks presents untapped opportunities for synthesis. We examine the problem of synthesis of behavioral specifications into networks of programmable sensor blocks. The particular behavioral specification we consider is an intuitive user-created network diagram of sensor blocks, each block having a pre-defined combinational or sequential behavior. We synthesize this specification to a new network that utilizes a minimum number of programmable blocks in place of the pre-defined blocks, thus reducing network size and hence network cost and power. We focus on the main task of this synthesis problem, namely partitioning pre-defined blocks onto a minimum number of programmable blocks, introducing the efficient but effective PareDown decomposition algorithm for the task. We describe the synthesis and simulation tools we developed. We provide results showing excellent network size reductions through such synthesis, and significant speedups of our algorithm over exhaustive search while obtaining near-optimal results for 15 real network designs as well as nearly 10,000 randomly generated designs.
cs.OH
the advent of sensor networks presents untapped opportunities for synthesis we examine the problem of synthesis of behavioral specifications into networks of programmable sensor blocks the particular behavioral specification we consider is an intuitive usercreated network diagram of sensor blocks each block having a predefined combinational or sequential behavior we synthesize this specification to a new network that utilizes a minimum number of programmable blocks in place of the predefined blocks thus reducing network size and hence network cost and power we focus on the main task of this synthesis problem namely partitioning predefined blocks onto a minimum number of programmable blocks introducing the efficient but effective paredown decomposition algorithm for the task we describe the synthesis and simulation tools we developed we provide results showing excellent network size reductions through such synthesis and significant speedups of our algorithm over exhaustive search while obtaining nearoptimal results for 15 real network designs as well as nearly 10000 randomly generated designs
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710.4799
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space requirements, power, real-time predictability, and reliability. In particular, many modern embedded systems operate under tight memory space constraints. One way of satisfying these constraints is to compress executable code and data as much as possible. While research on code compression have studied efficient hardware and software based code strategies, many of these techniques do not take application behavior into account, that is, the same compression/decompression strategy is used irrespective of the application being optimized. This paper presents a code compression strategy based on control flow graph (CFG) representation of the embedded program. The idea is to start with a memory image wherein all basic blocks are compressed, and decompress only the blocks that are predicted to be needed in the near future. When the current access to a basic block is over, our approach also decides the point at which the block could be compressed. We propose several compression and decompression strategies that try to reduce memory requirements without excessively increasing the original instruction cycle counts.
cs.OH
as compared to a large spectrum of performance optimizations relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space requirements power realtime predictability and reliability in particular many modern embedded systems operate under tight memory space constraints one way of satisfying these constraints is to compress executable code and data as much as possible while research on code compression have studied efficient hardware and software based code strategies many of these techniques do not take application behavior into account that is the same compressiondecompression strategy is used irrespective of the application being optimized this paper presents a code compression strategy based on control flow graph cfg representation of the embedded program the idea is to start with a memory image wherein all basic blocks are compressed and decompress only the blocks that are predicted to be needed in the near future when the current access to a basic block is over our approach also decides the point at which the block could be compressed we propose several compression and decompression strategies that try to reduce memory requirements without excessively increasing the original instruction cycle counts
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710.48
An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security
The hybrid hiding encryption algorithm, as its name implies, embraces concepts from both steganography and cryptography. In this exertion, an improved micro-architecture Field Programmable Gate Array (FPGA) implementation of this algorithm is presented. This design overcomes the observed limitations of a previously-designed micro-architecture. These observed limitations are: no exploitation of the possibility of parallel bit replacement, and the fact that the input plaintext was encrypted serially, which caused a dependency between the throughput and the nature of the used secret key. This dependency can be viewed by some as vulnerability in the security of the implemented micro-architecture. The proposed modified micro-architecture is constructed using five basic modules. These modules are; the message cache, the message alignment module, the key cache, the comparator, and at last the encryption module. In this work, we provide comprehensive simulation and implementation results. These are: the timing diagrams, the post-implementation timing and routing reports, and finally the floor plan. Moreover, a detailed comparison with other FPGA implementations is made available and discussed.
cs.CR
the hybrid hiding encryption algorithm as its name implies embraces concepts from both steganography and cryptography in this exertion an improved microarchitecture field programmable gate array fpga implementation of this algorithm is presented this design overcomes the observed limitations of a previouslydesigned microarchitecture these observed limitations are no exploitation of the possibility of parallel bit replacement and the fact that the input plaintext was encrypted serially which caused a dependency between the throughput and the nature of the used secret key this dependency can be viewed by some as vulnerability in the security of the implemented microarchitecture the proposed modified microarchitecture is constructed using five basic modules these modules are the message cache the message alignment module the key cache the comparator and at last the encryption module in this work we provide comprehensive simulation and implementation results these are the timing diagrams the postimplementation timing and routing reports and finally the floor plan moreover a detailed comparison with other fpga implementations is made available and discussed
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710.4801
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the slowest operation. This resulted in large slack times wasted in those cycles executing faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. While these techniques have produced successful designs, its effectiveness is often limited due to the area increment that may derive from chaining, and the extra latencies that may derive from multicycling. In this paper we present an optimization method that solves the time-constrained scheduling problem by transforming behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance. Our proposal breaks up some of the specification operations, allowing their execution during several possibly unconsecutive cycles, and also the calculation of several data-dependent operation fragments in the same cycle. To do so, it takes into account the circuit latency and the execution time of every specification operation. The experimental results carried out show that circuits obtained from the optimized specification are on average 60% faster than those synthesized from the original specification, with only slight increments in the circuit area.
cs.AR
early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the slowest operation this resulted in large slack times wasted in those cycles executing faster operations to reduce the wasted times multicycle and chaining techniques have been employed while these techniques have produced successful designs its effectiveness is often limited due to the area increment that may derive from chaining and the extra latencies that may derive from multicycling in this paper we present an optimization method that solves the timeconstrained scheduling problem by transforming behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance our proposal breaks up some of the specification operations allowing their execution during several possibly unconsecutive cycles and also the calculation of several datadependent operation fragments in the same cycle to do so it takes into account the circuit latency and the execution time of every specification operation the experimental results carried out show that circuits obtained from the optimized specification are on average 60 faster than those synthesized from the original specification with only slight increments in the circuit area
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710.4802
Mutation Sampling Technique for the Generation of Structural Test Data
Our goal is to produce validation data that can be used as an efficient (pre) test set for structural stuck-at faults. In this paper, we detail an original test-oriented mutation sampling technique used for generating such data and we present a first evaluation on these validation data with regard to a structural test.
cs.OH
our goal is to produce validation data that can be used as an efficient pre test set for structural stuckat faults in this paper we detail an original testoriented mutation sampling technique used for generating such data and we present a first evaluation on these validation data with regard to a structural test
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710.4803
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
The widening spectrum of applications and services provided by portable and embedded devices bring a new dimension of concerns in security. Most of those embedded systems (pay-TV, PDAs, mobile phones, etc...) make use of external memory. As a result, the main problem is that data and instructions are constantly exchanged between memory (RAM) and CPU in clear form on the bus. This memory may contain confidential data like commercial software or private contents, which either the end-user or the content provider is willing to protect. The goal of this paper is to clearly describe the problem of processor-memory bus communications in this regard and the existing techniques applied to secure the communication channel through encryption - Performance overheads implied by those solutions will be extensively discussed in this paper.
cs.CR
the widening spectrum of applications and services provided by portable and embedded devices bring a new dimension of concerns in security most of those embedded systems paytv pdas mobile phones etc make use of external memory as a result the main problem is that data and instructions are constantly exchanged between memory ram and cpu in clear form on the bus this memory may contain confidential data like commercial software or private contents which either the enduser or the content provider is willing to protect the goal of this paper is to clearly describe the problem of processormemory bus communications in this regard and the existing techniques applied to secure the communication channel through encryption performance overheads implied by those solutions will be extensively discussed in this paper
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710.4804
Singular polarimetry: Evolution of polarization singularities in electromagnetic waves propagating through a weakly anisotropic medium
We describe the evolution of a paraxial electromagnetic wave characterizing by a non-uniform polarization distribution with singularities and propagating in a weakly anisotropic medium. Our approach is based on the Stokes vector evolution equation applied to a non-uniform initial polarization field. In the case of a homogeneous medium, this equation is integrated analytically. This yields a 3-dimensional distribution of the polarization parameters containing singularities, i.e. C-lines of circular polarization and L-surfaces of linear polarization. The general theory is applied to specific examples of the unfolding of a vectorial vortex in birefringent and dichroic media.
physics.optics
we describe the evolution of a paraxial electromagnetic wave characterizing by a nonuniform polarization distribution with singularities and propagating in a weakly anisotropic medium our approach is based on the stokes vector evolution equation applied to a nonuniform initial polarization field in the case of a homogeneous medium this equation is integrated analytically this yields a 3dimensional distribution of the polarization parameters containing singularities ie clines of circular polarization and lsurfaces of linear polarization the general theory is applied to specific examples of the unfolding of a vectorial vortex in birefringent and dichroic media
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710.4805
Modeling of a Reconfigurable OFDM IP Block Family For an RF System Simulator
The idea of design domain specific Mother Model of IP block family as a base of modeling of system integration is presented here. A common reconfigurable Mother Model for ten different standardized digital OFDM transmitters has been developed. By means of a set of parameters, the mother model can be reconfigured to any of the ten selected standards. So far the applicability of the proposed reconfiguration and analog-digital co-modeling methods have been proved by modeling the function of the digital parts of three, 802.11a, ADSL and DRM, transmitters in an RF system simulator. The model is intended to be used as signal source template in RF system simulations. The concept is not restricted to signal sources, it can be applied to any IP block development. The idea of the Mother Model will be applied in other design domains to prove that in certain application areas, OFDM transceivers in this case, the design process can progress simultaneously in different design domains - mixed signal, system and RTL-architectural - without the need of high-level synthesis. Only the Mother Models of three design domains are needed to be formally proved to function as specified.
cs.AR
the idea of design domain specific mother model of ip block family as a base of modeling of system integration is presented here a common reconfigurable mother model for ten different standardized digital ofdm transmitters has been developed by means of a set of parameters the mother model can be reconfigured to any of the ten selected standards so far the applicability of the proposed reconfiguration and analogdigital comodeling methods have been proved by modeling the function of the digital parts of three 80211a adsl and drm transmitters in an rf system simulator the model is intended to be used as signal source template in rf system simulations the concept is not restricted to signal sources it can be applied to any ip block development the idea of the mother model will be applied in other design domains to prove that in certain application areas ofdm transceivers in this case the design process can progress simultaneously in different design domains mixed signal system and rtlarchitectural without the need of highlevel synthesis only the mother models of three design domains are needed to be formally proved to function as specified
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710.4806
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.
cs.AR
this paper presents a digital vlsi design flow to create secure sidechannel attack sca resistant integrated circuits the design flow starts from a normal design in a hardware description language such as vhdl or verilog and provides a direct path to a sca resistant layout instead of a full custom layout or an iterative design process with extensive simulations a few key modifications are incorporated in a regular synchronous cmos standard cell design flow we discuss the basis for sidechannel attack resistance and adjust the library databases and constraints files of the synthesis and place route procedures accordingly experimental results show that a dpa attack on a regular single ended cmos standard cell implementation of a module of the des algorithm discloses the secret key after 200 measurements the same attack on a secure version still does not disclose the secret key after more than 2000 measurements
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710.4807
A Constraint Network Based Approach to Memory Layout Optimization
While loop restructuring based code optimization for array intensive applications has been successful in the past, it has several problems such as the requirement of checking dependences (legality issues) and transformation of all of the array references within the loop body indiscriminately (while some of the references can benefit from the transformation, others may not). As a result, data transformations, i.e., transformations that modify memory layout of array data instead of loop structure have been proposed. One of the problems associated with data transformations is the difficulty of selecting a memory layout for an array that is acceptable to the entire program (not just to a single loop). In this paper, we formulate the problem of determining the memory layouts of arrays as a constraint network, and explore several methods of solution in a systematic way. Our experiments provide strong support in favor of employing constraint processing, and point out future research directions.
cs.PL
while loop restructuring based code optimization for array intensive applications has been successful in the past it has several problems such as the requirement of checking dependences legality issues and transformation of all of the array references within the loop body indiscriminately while some of the references can benefit from the transformation others may not as a result data transformations ie transformations that modify memory layout of array data instead of loop structure have been proposed one of the problems associated with data transformations is the difficulty of selecting a memory layout for an array that is acceptable to the entire program not just to a single loop in this paper we formulate the problem of determining the memory layouts of arrays as a constraint network and explore several methods of solution in a systematic way our experiments provide strong support in favor of employing constraint processing and point out future research directions
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710.4808
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model shows 353 times faster than pin-accurate RTL model while maintaining 97% of accuracy on average. We also present the development procedure of TLM of a bus architecture.
cs.AR
transaction level modeling tlm approach is used to meet the simulation speed as well as cycle accuracy for large scale soc performance analysis we implemented a transactionlevel model of a proprietary bus called ahb which supports an extended amba20 protocol the ahb transactionlevel model shows 353 times faster than pinaccurate rtl model while maintaining 97 of accuracy on average we also present the development procedure of tlm of a bus architecture
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710.4809
C Based Hardware Design for Wireless Applications
The algorithms used in wireless applications are increasingly more sophisticated and consequently more challenging to implement in hardware. Traditional design flows require developing the micro architecture, coding the RTL, and verifying the generated RTL against the original functional C or MATLAB specification. This paper describes a C-based design flow that is well suited for the hardware implementation of DSP algorithms commonly found in wireless applications. The C design flow relies on guided synthesis to generate the RTL directly from the untimed C algorithm. The specifics of the C-based design flow are described using a simple DSP filtering algorithm consisting of a forward adaptive equalizer, a 64-QAM slicer and an adaptive decision feedback equalizer. The example illustrates some of the capabilities and advantages offered by this flow.
cs.AR
the algorithms used in wireless applications are increasingly more sophisticated and consequently more challenging to implement in hardware traditional design flows require developing the micro architecture coding the rtl and verifying the generated rtl against the original functional c or matlab specification this paper describes a cbased design flow that is well suited for the hardware implementation of dsp algorithms commonly found in wireless applications the c design flow relies on guided synthesis to generate the rtl directly from the untimed c algorithm the specifics of the cbased design flow are described using a simple dsp filtering algorithm consisting of a forward adaptive equalizer a 64qam slicer and an adaptive decision feedback equalizer the example illustrates some of the capabilities and advantages offered by this flow
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710.481
Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method
Securing communication channels is especially needed in wireless environments. But applying cipher mechanisms in software is limited by the calculation and energy resources of the mobile devices. If hardware is applied to realize cryptographic operations cost becomes an issue. In this paper we describe an approach which tackles all these three points. We implemented a hardware accelerator for polynomial multiplication in extended Galois fields (GF) applying Karatsuba's method iteratively. With this approach the area consumption is reduced to 2.1 mm^2 in comparison to. 6.2 mm^2 for the standard application of Karatsuba's method i.e. for recursive application. Our approach also reduces the energy consumption to 60 per cent of the original approach. The price we have to pay for these achievement is the increased execution time. In our implementation a polynomial multiplication takes 3 clock cycles whereas the recurisve Karatsuba approach needs only one clock cycle. But considering area, energy and calculation speed we are convinced that the benefits of our approach outweigh its drawback.
cs.CR
securing communication channels is especially needed in wireless environments but applying cipher mechanisms in software is limited by the calculation and energy resources of the mobile devices if hardware is applied to realize cryptographic operations cost becomes an issue in this paper we describe an approach which tackles all these three points we implemented a hardware accelerator for polynomial multiplication in extended galois fields gf applying karatsubas method iteratively with this approach the area consumption is reduced to 21 mm2 in comparison to 62 mm2 for the standard application of karatsubas method ie for recursive application our approach also reduces the energy consumption to 60 per cent of the original approach the price we have to pay for these achievement is the increased execution time in our implementation a polynomial multiplication takes 3 clock cycles whereas the recurisve karatsuba approach needs only one clock cycle but considering area energy and calculation speed we are convinced that the benefits of our approach outweigh its drawback
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710.4811
System Level Analysis of the Bluetooth Standard
The SystemC modules of the Link Manager Layer and Baseband Layer have been designed in this work at behavioral level to analyze the performances of the Bluetooth standard. In particular the probability of the creation of a piconet in presence of noise in the channel and the power reduction using the sniff and hold mode have been investigated.
cs.OH
the systemc modules of the link manager layer and baseband layer have been designed in this work at behavioral level to analyze the performances of the bluetooth standard in particular the probability of the creation of a piconet in presence of noise in the channel and the power reduction using the sniff and hold mode have been investigated
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710.4812
Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures
The JPEG2000 standard defines the discrete wavelet transform (DWT) as a linear space-to-frequency transform of the image domain in an irreversible compression. This irreversible discrete wavelet transform is implemented by FIR filter using 9/7 Daubechies coefficients or a lifting scheme of factorizated coefficients from 9/7 Daubechies coefficients. This work investigates the tradeoffs between area, power and data throughput (or operating frequency) of several implementations of the Discrete Wavelet Transform using the lifting scheme in various pipeline designs. This paper shows the results of five different architectures synthesized and simulated in FPGAs. It concludes that the descriptions with pipelined operators provide the best area-power-operating frequency trade-off over non-pipelined operators descriptions. Those descriptions require around 40% more hardware to increase the maximum operating frequency up to 100% and reduce power consumption to less than 50%. Starting from behavioral HDL descriptions provide the best area-power-operating frequency trade-off, improving hardware cost and maximum operating frequency around 30% in comparison to structural descriptions for the same power requirement.
cs.AR
the jpeg2000 standard defines the discrete wavelet transform dwt as a linear spacetofrequency transform of the image domain in an irreversible compression this irreversible discrete wavelet transform is implemented by fir filter using 97 daubechies coefficients or a lifting scheme of factorizated coefficients from 97 daubechies coefficients this work investigates the tradeoffs between area power and data throughput or operating frequency of several implementations of the discrete wavelet transform using the lifting scheme in various pipeline designs this paper shows the results of five different architectures synthesized and simulated in fpgas it concludes that the descriptions with pipelined operators provide the best areapoweroperating frequency tradeoff over nonpipelined operators descriptions those descriptions require around 40 more hardware to increase the maximum operating frequency up to 100 and reduce power consumption to less than 50 starting from behavioral hdl descriptions provide the best areapoweroperating frequency tradeoff improving hardware cost and maximum operating frequency around 30 in comparison to structural descriptions for the same power requirement
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710.4813
Queue Management in Network Processors
One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we analyze the performance bottlenecks of various data memory managers integrated in typical Network Processing Units (NPUs). We expose the performance limitations of software implementations utilizing the RISC processing cores typically found in most NPU architectures and we identify the requirements for hardware assisted memory management in order to achieve wire-speed operation at gigabit per second rates. Furthermore, we describe the architecture and performance of a hardware memory manager that fulfills those requirements. This memory manager, although it is implemented in a reconfigurable technology, it can provide up to 6.2Gbps of aggregate throughput, while handling 32K independent queues.
cs.AR
one of the main bottlenecks when designing a network processing system is very often its memory subsystem this is mainly due to the stateoftheart network links operating at very high speeds and to the fact that in order to support advanced quality of service qos a large number of independent queues is desirable in this paper we analyze the performance bottlenecks of various data memory managers integrated in typical network processing units npus we expose the performance limitations of software implementations utilizing the risc processing cores typically found in most npu architectures and we identify the requirements for hardware assisted memory management in order to achieve wirespeed operation at gigabit per second rates furthermore we describe the architecture and performance of a hardware memory manager that fulfills those requirements this memory manager although it is implemented in a reconfigurable technology it can provide up to 62gbps of aggregate throughput while handling 32k independent queues
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710.4814
picoArray Technology: The Tool's Story
This paper briefly describes the picoArray? architecture, and in particular the deterministic internal communication fabric. The methods that have been developed for debugging and verifying systems using devices from the picoArray family are explained. In order to maximize the computational ability of these devices, hardware debugging support has been kept to a minimum and the methods and tools developed to take this into account.
cs.AR
this paper briefly describes the picoarray architecture and in particular the deterministic internal communication fabric the methods that have been developed for debugging and verifying systems using devices from the picoarray family are explained in order to maximize the computational ability of these devices hardware debugging support has been kept to a minimum and the methods and tools developed to take this into account
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710.4815
Direct Conversion Pulsed UWB Transceiver Architecture
Ultra-wideband (UWB) communication is an emerging wireless technology that promises high data rates over short distances and precise locationing. The large available bandwidth and the constraint of a maximum power spectral density drives a unique set of system challenges. This paper addresses these challenges using two UWB transceivers and a discrete prototype platform.
cs.NI
ultrawideband uwb communication is an emerging wireless technology that promises high data rates over short distances and precise locationing the large available bandwidth and the constraint of a maximum power spectral density drives a unique set of system challenges this paper addresses these challenges using two uwb transceivers and a discrete prototype platform
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710.4816
Power Saving Techniques for Wireless LANs
Fast wireless access has rapidly become commonplace. Wireless access points and Hotspot servers are sprouting everywhere. Battery lifetime continues to be a critical issue in mobile computing. This paper first gives an overview of WLAN energy saving strategies, followed by an illustration of a system-level methodology for saving power in heterogeneous wireless environments.
cs.NI
fast wireless access has rapidly become commonplace wireless access points and hotspot servers are sprouting everywhere battery lifetime continues to be a critical issue in mobile computing this paper first gives an overview of wlan energy saving strategies followed by an illustration of a systemlevel methodology for saving power in heterogeneous wireless environments
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710.4817
Performance Considerations for an Embedded Implementation of OMA DRM 2
As digital content services gain importance in the mobile world, Digital Rights Management (DRM) applications will become a key component of mobile terminals. This paper examines the effect dedicated hardware macros for specific cryptographic functions have on the performance of a mobile terminal that supports version 2 of the open standard for Digital Rights Management defined by the Open Mobile Alliance (OMA). Following a general description of the standard, the paper contains a detailed analysis of the cryptographic operations that have to be carried out before protected content can be accessed. The combination of this analysis with data on execution times for specific algorithms realized in hardware and software has made it possible to build a model which has allowed us to assert that hardware acceleration for specific cryptographic algorithms can significantly reduce the impact DRM has on a mobile terminal's processing performance and battery life.
cs.CR
as digital content services gain importance in the mobile world digital rights management drm applications will become a key component of mobile terminals this paper examines the effect dedicated hardware macros for specific cryptographic functions have on the performance of a mobile terminal that supports version 2 of the open standard for digital rights management defined by the open mobile alliance oma following a general description of the standard the paper contains a detailed analysis of the cryptographic operations that have to be carried out before protected content can be accessed the combination of this analysis with data on execution times for specific algorithms realized in hardware and software has made it possible to build a model which has allowed us to assert that hardware acceleration for specific cryptographic algorithms can significantly reduce the impact drm has on a mobile terminals processing performance and battery life
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710.4818
Wireless LAN: Past, Present, and Future
This paper retraces the historical development of wireless LAN technology in the context of the pursuit of ever higher data rate, describes the significant technical breakthroughs that are now occurring, and speculates on future directions that the technology may take over the remainder of the decade. The challenges that these developments have created for low power operation are considered, as well as some of the opportunities that are presented to mitigate them. The importance of MIMO as an emerging technology for 802.11 is specifically highlighted, both in terms of the significant increase in data rate and range that it enables as well as the considerable challenge that it presents for the development of low power wireless LAN products.
cs.NI
this paper retraces the historical development of wireless lan technology in the context of the pursuit of ever higher data rate describes the significant technical breakthroughs that are now occurring and speculates on future directions that the technology may take over the remainder of the decade the challenges that these developments have created for low power operation are considered as well as some of the opportunities that are presented to mitigate them the importance of mimo as an emerging technology for 80211 is specifically highlighted both in terms of the significant increase in data rate and range that it enables as well as the considerable challenge that it presents for the development of low power wireless lan products
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710.4819
A High Quality/Low Computational Cost Technique for Block Matching Motion Estimation
Motion estimation is the most critical process in video coding systems. First of all, it has a definitive impact on the rate-distortion performance given by the video encoder. Secondly, it is the most computationally intensive process within the encoding loop. For these reasons, the design of high-performance low-cost motion estimators is a crucial task in the video compression field. An adaptive cost block matching (ACBM) motion estimation technique is presented in this paper, featuring an excellent tradeoff between the quality of the reconstructed video sequences and the computational effort. Simulation results demonstrate that the ACBM algorithm achieves a slight better rate-distortion performance than the one given by the well-known full search algorithm block matching algorithm with reductions of up to 95% in the computational load.
cs.MM
motion estimation is the most critical process in video coding systems first of all it has a definitive impact on the ratedistortion performance given by the video encoder secondly it is the most computationally intensive process within the encoding loop for these reasons the design of highperformance lowcost motion estimators is a crucial task in the video compression field an adaptive cost block matching acbm motion estimation technique is presented in this paper featuring an excellent tradeoff between the quality of the reconstructed video sequences and the computational effort simulation results demonstrate that the acbm algorithm achieves a slight better ratedistortion performance than the one given by the wellknown full search algorithm block matching algorithm with reductions of up to 95 in the computational load
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710.482
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic. Experimental results on a number of MediaBench, EEMBC and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20x faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application (AES) by effectively exploiting its regular structure.
cs.AR
customization of processor architectures through instruction set extensions ises is an effective way to meet the growing performance demands of embedded applications a highquality ise generation approach needs to obtain results close to those achieved by experienced designers particularly for complex applications that exhibit regularity expert designers are able to exploit manually such regularity in the data flow graphs to generate highquality ises in this paper we present isegen an approach that identifies highquality ises by iterative improvement following the basic principles of the wellknown kernighanlin kl mincut heuristic experimental results on a number of mediabench eembc and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search we also show that our isegen technique is on average 20x faster than a genetic formulation that generates equivalent solutions furthermore the ises identified by our technique exhibit 35 more speedup than the genetic solution on a large cryptographic application aes by effectively exploiting its regular structure
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710.4821
Multimedia Applications of Multiprocessor Systems-on-Chips
This paper surveys the characteristics of multimedia systems. Multimedia applications today are dominated by compression and decompression, but multimedia devices must also implement many other functions such as security and file management. We introduce some basic concepts of multimedia algorithms and the larger set of functions that multimedia systems-on-chips must implement.
cs.MM
this paper surveys the characteristics of multimedia systems multimedia applications today are dominated by compression and decompression but multimedia devices must also implement many other functions such as security and file management we introduce some basic concepts of multimedia algorithms and the larger set of functions that multimedia systemsonchips must implement
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710.4822
Testing Bell inequalities with photon-subtracted Gaussian states
Recently, photon subtracted Gaussian states (PSGSs) were generated by several experimental groups. Those states were called "Schr\"odinger kittens" due to their similarities to superpositions of coherent states (SCSs) with small amplitudes. We compare the ideal SCSs and the PSGSs for experimental tests of certain types of Bell inequalities. In particular, we analyze the effects of the key experimental components used to generate PSGSs: mixedness of the Gaussian states, limited transmittivity of the beam splitter and the avalanche photodetector which cannot resolve photon numbers. As a result of this analysis, the degrees of mixedness and the beam splitter transmittivity that can be allowed for successful tests of Bell inequalities are revealed.
quant-ph
recently photon subtracted gaussian states psgss were generated by several experimental groups those states were called schrodinger kittens due to their similarities to superpositions of coherent states scss with small amplitudes we compare the ideal scss and the psgss for experimental tests of certain types of bell inequalities in particular we analyze the effects of the key experimental components used to generate psgss mixedness of the gaussian states limited transmittivity of the beam splitter and the avalanche photodetector which cannot resolve photon numbers as a result of this analysis the degrees of mixedness and the beam splitter transmittivity that can be allowed for successful tests of bell inequalities are revealed
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710.4823
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of microprocessors is not sufficient and power consumption is too high. Instruction profiling on a typical test algorithm has shown that pixel address calculations are the dominant operations to be optimized. Therefore AddressLib, a structured scheme for pixel addressing was developed, that can be accelerated by AddressEngine, a coprocessor for visual information processing. In this paper, the architectural design of AddressEngine is described, which in the first step supports a subset of the AddressLib. Dataflow and memory organization are optimized during architectural design. AddressEngine was implemented in a FPGA and was tested with MPEG-7 Global Motion Estimation algorithm. Results on processing speed and circuit complexity are given and compared to a pure software implementation. The next step will be the support for the full AddressLib, including segment addressing. An outlook on further investigations on dynamic reconfiguration capabilities is given.
cs.MM
visual information processing will play an increasingly important role in future electronics systems in many applications eg video surveillance cameras data throughput of microprocessors is not sufficient and power consumption is too high instruction profiling on a typical test algorithm has shown that pixel address calculations are the dominant operations to be optimized therefore addresslib a structured scheme for pixel addressing was developed that can be accelerated by addressengine a coprocessor for visual information processing in this paper the architectural design of addressengine is described which in the first step supports a subset of the addresslib dataflow and memory organization are optimized during architectural design addressengine was implemented in a fpga and was tested with mpeg7 global motion estimation algorithm results on processing speed and circuit complexity are given and compared to a pure software implementation the next step will be the support for the full addresslib including segment addressing an outlook on further investigations on dynamic reconfiguration capabilities is given
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710.4824
FPGA based Agile Algorithm-On-Demand Co-Processor
With growing computational needs of many real-world applications, frequently changing specifications of standards, and the high design and NRE costs of ASICs, an algorithm-agile FPGA based co-processor has become a viable alternative. In this article, we report about the general design of an algorith-agile co-processor and the proof-of-concept implementation.
cs.AR
with growing computational needs of many realworld applications frequently changing specifications of standards and the high design and nre costs of asics an algorithmagile fpga based coprocessor has become a viable alternative in this article we report about the general design of an algorithagile coprocessor and the proofofconcept implementation
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710.4825
Meeting the Embedded Design Needs of Automotive Applications
The importance of embedded systems in driving innovation in automotive applications continues to grow. Understanding the specific needs of developers targeting this market is also helping to drive innovation in RISC core design. This paper describes how a RISC instruction set architecture has evolved to better meet those needs, and the key implementation features in two very different RISC cores are used to demonstrate the challenges of designing for real-time automotive systems.
cs.AR
the importance of embedded systems in driving innovation in automotive applications continues to grow understanding the specific needs of developers targeting this market is also helping to drive innovation in risc core design this paper describes how a risc instruction set architecture has evolved to better meet those needs and the key implementation features in two very different risc cores are used to demonstrate the challenges of designing for realtime automotive systems
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710.4826
The Integration of On-Line Monitoring and Reconfiguration Functions using EDAA - European design and Automation Association1149.4 Into a Safety Critical Automotive Electronic Control Unit
This paper presents an innovative application of EDAA - European design and Automation Association 1149.4 and the Integrated Diagnostic Reconfiguration (IDR) as tools for the implementation of an embedded test solution for an Automotive Electronic Control Unit implemented as a fully integrated mixed signal system. The paper described how the test architecture can be used for fault avoidance with results from a hardware prototype presented. The paper concludes that fault avoidance can be integrated into mixed signal electronic systems to handle key failure modes.
cs.AR
this paper presents an innovative application of edaa european design and automation association 11494 and the integrated diagnostic reconfiguration idr as tools for the implementation of an embedded test solution for an automotive electronic control unit implemented as a fully integrated mixed signal system the paper described how the test architecture can be used for fault avoidance with results from a hardware prototype presented the paper concludes that fault avoidance can be integrated into mixed signal electronic systems to handle key failure modes
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710.4827
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
The introduction of complex SoCs with multiple processor cores presents new development challenges, such that development support is now a decisive factor when choosing a System-on-Chip (SoC). The presented developments support strategy addresses the challenges using both architecture and technology approaches. The Multi-Core Debug Support (MCDS) architecture provides flexible triggering using cross triggers and a multiple core break and suspend switch. Temporal trace ordering is guaranteed down to cycle level by on-chip time stamping. The Package Sized-ICE (PSI) approach is a novel method of including trace buffers, overlay memories, processing resources and communication interfaces without changing device behavior. PSI requires no external emulation box, as the debug host interfaces directly with the SoC using a standard interface.
cs.AR
the introduction of complex socs with multiple processor cores presents new development challenges such that development support is now a decisive factor when choosing a systemonchip soc the presented developments support strategy addresses the challenges using both architecture and technology approaches the multicore debug support mcds architecture provides flexible triggering using cross triggers and a multiple core break and suspend switch temporal trace ordering is guaranteed down to cycle level by onchip time stamping the package sizedice psi approach is a novel method of including trace buffers overlay memories processing resources and communication interfaces without changing device behavior psi requires no external emulation box as the debug host interfaces directly with the soc using a standard interface
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710.4828
Bounds for Visual Cryptography Schemes
In this paper, we investigate the best pixel expansion of the various models of visual cryptography schemes. In this regard, we consider visual cryptography schemes introduced by Tzeng and Hu [13]. In such a model, only minimal qualified sets can recover the secret image and that the recovered secret image can be darker or lighter than the background. Blundo et al. [4] introduced a lower bound for the best pixel expansion of this scheme in terms of minimal qualified sets. We present another lower bound for the best pixel expansion of the scheme. As a corollary, we introduce a lower bound, based on an induced matching of hypergraph of qualified sets, for the best pixel expansion of the aforementioned model and the traditional model of visual cryptography realized by basis matrices. Finally, we study access structures based on graphs and we present an upper bound for the smallest pixel expansion in terms of strong chromatic index.
cs.CR
in this paper we investigate the best pixel expansion of the various models of visual cryptography schemes in this regard we consider visual cryptography schemes introduced by tzeng and hu 13 in such a model only minimal qualified sets can recover the secret image and that the recovered secret image can be darker or lighter than the background blundo et al 4 introduced a lower bound for the best pixel expansion of this scheme in terms of minimal qualified sets we present another lower bound for the best pixel expansion of the scheme as a corollary we introduce a lower bound based on an induced matching of hypergraph of qualified sets for the best pixel expansion of the aforementioned model and the traditional model of visual cryptography realized by basis matrices finally we study access structures based on graphs and we present an upper bound for the smallest pixel expansion in terms of strong chromatic index
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710.4829
AutoMoDe - Model-Based Development of Automotive Software
This paper describes first results from the AutoMoDe (Automotive Model-Based Development) project. The overall goal of the project is to develop an integrated methodology for model-based development of automotive control software, based on problem-specific design notations with an explicit formal foundation. Based on the existing AutoFOCUS framework, a tool prototype is being developed in order to illustrate and validate the key elements of our approach.
cs.SE
this paper describes first results from the automode automotive modelbased development project the overall goal of the project is to develop an integrated methodology for modelbased development of automotive control software based on problemspecific design notations with an explicit formal foundation based on the existing autofocus framework a tool prototype is being developed in order to illustrate and validate the key elements of our approach
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710.483
Violation of Generalized Bose-Einstein symmetry and quantum entanglement of pi(-)pi(+) isospin states in pion pair production piN->pi(-)pi(+)N
Generalized Bose-Einstein symmetry requires that J+I=even for two-pion angular states of spin J and total isospin I. We show that the symmetry predicts three linearly independent constraints on partial wave intensities with even spin for pi(-)p->pi(-)pi(+)n, pi(-)p->pi(0)pi(0)n and pi(+)p->pi(+)pi(+)n. Available data violate all three constraints for S, D^0, D^U and D^N partial waves. The violations of the symmetry imply a presence of the symmetry violating contributions to transversity amplitudes in pi(-)p->pi(-)pi(+)n and predict quantum entanglement of pi(-)pi(+) isospin states which is excluded by the symmetry. We derive approximate lower and upper bounds on entanglement amplitudes |a_S| and |a_A|. The bounds provide a clear evidence for entanglement of pi(-)pi(+) isospin states below 840 MeV and suggest the entanglement at higher dipion masses. The small values of |a_S| \sim 0.10-0.20 below 840 MeV explain the puzzling differences between the S-wave intensities in pi(-)p->pi(-)pi(+)n and pi(-)p->pi(0)pi(0)n and reveal a suppression of isospin I=0,2 contribution in the S-wave amplitudes in pi(-)p->pi(-)pi(+)n. The large isospin I=1 contribution of rho^0(770) to both S- and P-wave amplitudes is due to large entanglement amplitude |a_A| \sim 0.98-0.99. These findings confirm the predictions of a model of non-unitary dynamics of the pion creation processes arising from a CPT violating interaction of these processes with a quantum environment.
hep-ph hep-th
generalized boseeinstein symmetry requires that jieven for twopion angular states of spin j and total isospin i we show that the symmetry predicts three linearly independent constraints on partial wave intensities with even spin for pippipin pippi0pi0n and pippipin available data violate all three constraints for s d0 du and dn partial waves the violations of the symmetry imply a presence of the symmetry violating contributions to transversity amplitudes in pippipin and predict quantum entanglement of pipi isospin states which is excluded by the symmetry we derive approximate lower and upper bounds on entanglement amplitudes a_s and a_a the bounds provide a clear evidence for entanglement of pipi isospin states below 840 mev and suggest the entanglement at higher dipion masses the small values of a_s sim 010020 below 840 mev explain the puzzling differences between the swave intensities in pippipin and pippi0pi0n and reveal a suppression of isospin i02 contribution in the swave amplitudes in pippipin the large isospin i1 contribution of rho0770 to both s and pwave amplitudes is due to large entanglement amplitude a_a sim 098099 these findings confirm the predictions of a model of nonunitary dynamics of the pion creation processes arising from a cpt violating interaction of these processes with a quantum environment
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710.4831
LC Oscillator Driver for Safety Critical Applications
A CMOS harmonic signal LC oscillator driver for automotive applications working in a harsh environment with high safety critical requirements is described. The driver can be used with a wide range of external components parameters (LC resonance network of a sensor). Quality factor of the external LC network can vary two decades. Amplitude regulation of the driver is digitally controlled and the DAC is constructed as exponential with piece-wise-linear (PWL) approximation. Low current consumption for high quality resonance networks is achieved. Realized oscillator is robust, used in safety critical application and has low EMC emissions.
cs.OH
a cmos harmonic signal lc oscillator driver for automotive applications working in a harsh environment with high safety critical requirements is described the driver can be used with a wide range of external components parameters lc resonance network of a sensor quality factor of the external lc network can vary two decades amplitude regulation of the driver is digitally controlled and the dac is constructed as exponential with piecewiselinear pwl approximation low current consumption for high quality resonance networks is achieved realized oscillator is robust used in safety critical application and has low emc emissions
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710.4832
SystemC Analysis of a New Dynamic Power Management Architecture
This paper presents a new dynamic power management architecture of a System on Chip. The Power State Machine describing the status of the core follows the recommendations of the ACPI standard. The algorithm controls the power states of each block on the basis of battery status, chip temperature and a user defined task priority.
cs.AR
this paper presents a new dynamic power management architecture of a system on chip the power state machine describing the status of the core follows the recommendations of the acpi standard the algorithm controls the power states of each block on the basis of battery status chip temperature and a user defined task priority
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710.4833
Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety Systems
We present a system for the boresighting of sensors using inertial measurement devices as the basis for developing a range of dynamic real-time sensor fusion applications. The proof of concept utilizes a COTS FPGA platform for sensor fusion and real-time correction of a misaligned video sensor. We exploit a custom-designed 32-bit soft processor core and C-based design & synthesis for rapid, platform-neutral development. Kalman filter and sensor fusion techniques established in advanced aviation systems are applied to automotive vehicles with results exceeding typical industry requirements for sensor alignment. Results of the static and the dynamic tests demonstrate that using inexpensive accelerometers mounted on (or during assembly of) a sensor and an Inertial Measurement Unit (IMU) fixed to a vehicle can be used to compute the misalignment of the sensor to the IMU and thus vehicle. In some cases the model predications and test results exceeded the requirements by an order of magnitude with a 3-sigma or 99% confidence.
cs.AR
we present a system for the boresighting of sensors using inertial measurement devices as the basis for developing a range of dynamic realtime sensor fusion applications the proof of concept utilizes a cots fpga platform for sensor fusion and realtime correction of a misaligned video sensor we exploit a customdesigned 32bit soft processor core and cbased design synthesis for rapid platformneutral development kalman filter and sensor fusion techniques established in advanced aviation systems are applied to automotive vehicles with results exceeding typical industry requirements for sensor alignment results of the static and the dynamic tests demonstrate that using inexpensive accelerometers mounted on or during assembly of a sensor and an inertial measurement unit imu fixed to a vehicle can be used to compute the misalignment of the sensor to the imu and thus vehicle in some cases the model predications and test results exceeded the requirements by an order of magnitude with a 3sigma or 99 confidence
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710.4834
Platform Based Design for Automotive Sensor Conditioning
In this paper a general architecture suitable to interface several kinds of sensors for automotive applications is presented. A platform based design approach is pursued to improve system performance while minimizing time-to-market.. The platform is composed by an analog front-end and a digital section. The latter is based on a microcontroller core (8051 IP by Oregano) plus a set of dedicated hardware dedicated to the complex signal processing required for sensor conditioning. The microcontroller handles also the communication with external devices (as a PC) for data output and fast prototyping. A case study is presented concerning the conditioning of a Gyro yaw rate sensor for automotive applications. Measured performance results outperform current state-of-the-art commercial devices.
cs.AR
in this paper a general architecture suitable to interface several kinds of sensors for automotive applications is presented a platform based design approach is pursued to improve system performance while minimizing timetomarket the platform is composed by an analog frontend and a digital section the latter is based on a microcontroller core 8051 ip by oregano plus a set of dedicated hardware dedicated to the complex signal processing required for sensor conditioning the microcontroller handles also the communication with external devices as a pc for data output and fast prototyping a case study is presented concerning the conditioning of a gyro yaw rate sensor for automotive applications measured performance results outperform current stateoftheart commercial devices
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710.4835
A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring
A monolithic integrated tactile sensor array is presented, which is used to perform non-invasive blood pressure monitoring of a patient. The advantage of this device compared to a hand cuff based approach is the capability of recording continuous blood pressure data. The capacitive, membrane-based sensor device is fabricated in an industrial CMOS-technology combined with post-CMOS micromachining. The capacitance change is detected by a S?-modulator. The modulator is operated at a sampling rate of 128kS/s and achieves a resolution of 12bit with an external decimation filter and an OSR of 128.
cs.OH
a monolithic integrated tactile sensor array is presented which is used to perform noninvasive blood pressure monitoring of a patient the advantage of this device compared to a hand cuff based approach is the capability of recording continuous blood pressure data the capacitive membranebased sensor device is fabricated in an industrial cmostechnology combined with postcmos micromachining the capacitance change is detected by a smodulator the modulator is operated at a sampling rate of 128kss and achieves a resolution of 12bit with an external decimation filter and an osr of 128
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710.4836
A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems
Presented are a methodology and a DFII-based tool for AC-stability analysis of a wide variety of closed-loop continuous-time (operational amplifiers and other linear circuits). The methodology used allows for easy identification and diagnostics of ac-stability problems including not only main-loop effects but also local-instability loops in current mirrors, bias circuits and emitter or source followers without breaking the loop. The results of the analysis are easy to interpret. Estimated phase margin is readily available. Instability nodes and loops along with their respective oscillation frequencies are immediately identified and mapped to the existing circuit nodes thus offering significant advantages compared to traditional "black-box" methods of stability analysis (Transient Overshoot, Bode and Phase margin plots etc.). The tool for AC-Stability analysis is written in SKILL? and is fully integrated in DFII? environment. Its "push-button" graphical user interface (GUI) is easy to use and understand. The tool can be invoked directly from Composer? schematic and does not require active Analog Artist? session. The tool is not dependent on the use of a specific fabrication technology or Process Design Kit customization. It requires OCEAN?, Spectre? and Waveform calculator capabilities to run.
cs.OH
presented are a methodology and a dfiibased tool for acstability analysis of a wide variety of closedloop continuoustime operational amplifiers and other linear circuits the methodology used allows for easy identification and diagnostics of acstability problems including not only mainloop effects but also localinstability loops in current mirrors bias circuits and emitter or source followers without breaking the loop the results of the analysis are easy to interpret estimated phase margin is readily available instability nodes and loops along with their respective oscillation frequencies are immediately identified and mapped to the existing circuit nodes thus offering significant advantages compared to traditional blackbox methods of stability analysis transient overshoot bode and phase margin plots etc the tool for acstability analysis is written in skill and is fully integrated in dfii environment its pushbutton graphical user interface gui is easy to use and understand the tool can be invoked directly from composer schematic and does not require active analog artist session the tool is not dependent on the use of a specific fabrication technology or process design kit customization it requires ocean spectre and waveform calculator capabilities to run
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710.4837
Color transparency and short-range correlations in exclusive pion photo- and electroproduction from nuclei
A relativistic and quantum mechanical framework to compute nuclear transparencies for pion photo- and electroproduction reactions is presented. Final-state interactions for the ejected pions and nucleons are implemented in a relativistic eikonal approach. At sufficiently large ejectile energies, a relativistic Glauber model can be adopted. At lower energies, the framework possesses the flexibility to use relativistic optical potentials. The proposed model can account for the color-transparency (CT) phenomenon and short-range correlations (SRC) in the nucleus. Results are presented for kinematics corresponding to completed and planned experiments at Jefferson Lab. The influence of CT and SRC on the nuclear transparency is studied. Both the SRC and CT mechanisms increase the nuclear transparency. The two mechanisms can be clearly separated, though, as they exhibit a completely different dependence on the hard scale parameter. The nucleon and pion transparencies as computed in the relativistic Glauber approach are compared with optical-potential and semi-classical calculations. The similarities in the trends and magnitudes of the nuclear transparencies indicate that they are not subject to strong model dependencies.
nucl-th
a relativistic and quantum mechanical framework to compute nuclear transparencies for pion photo and electroproduction reactions is presented finalstate interactions for the ejected pions and nucleons are implemented in a relativistic eikonal approach at sufficiently large ejectile energies a relativistic glauber model can be adopted at lower energies the framework possesses the flexibility to use relativistic optical potentials the proposed model can account for the colortransparency ct phenomenon and shortrange correlations src in the nucleus results are presented for kinematics corresponding to completed and planned experiments at jefferson lab the influence of ct and src on the nuclear transparency is studied both the src and ct mechanisms increase the nuclear transparency the two mechanisms can be clearly separated though as they exhibit a completely different dependence on the hard scale parameter the nucleon and pion transparencies as computed in the relativistic glauber approach are compared with opticalpotential and semiclassical calculations the similarities in the trends and magnitudes of the nuclear transparencies indicate that they are not subject to strong model dependencies
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710.4838
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13$\mu$m Digital CMOS
A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realized in a standard digital 0.13 $\mu$m CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400fF, which leads to an easily drivable analog converter interface. Operating at 1.2GSps the ADC achieves an effective resolution bandwidth (ERBW) of 700MHz, while consuming 160mW of power. At 600MSps we achieve an ERBW of 600MHz with only 90mW power consumption, both from a 1.5V supply. This corresponds to outstanding Figure-of-Merit numbers (FoM) of 2.2 and 1.5pJ/convstep, respectively. The module area is 0.12mm^2.
cs.AR
a 6bit flashadc with 12gsps wide analog bandwidth and low power realized in a standard digital 013 mum cmos copper technology is presented employing capacitive interpolation gives various advantages when designing for low power no need for a reference resistor ladder implicit sampleandhold operation no edge effects in the interpolation network as compared to resistive interpolation and a very low input capacitance of only 400ff which leads to an easily drivable analog converter interface operating at 12gsps the adc achieves an effective resolution bandwidth erbw of 700mhz while consuming 160mw of power at 600msps we achieve an erbw of 600mhz with only 90mw power consumption both from a 15v supply this corresponds to outstanding figureofmerit numbers fom of 22 and 15pjconvstep respectively the module area is 012mm2
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710.4839
A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18$\mu$m Digital CMOS
A 12 bit Pipeline ADC fabricated in a 0.18 $\mu$m pure digital CMOS technology is presented. Its nominal conversion rate is 110MS/s and the nominal supply voltage is 1.8V. The effective number of bits is 10.4 when a 10MHz input signal with 2V_{P-P} signal swing is applied. The occupied silicon area is 0.86mm^2 and the power consumption equals 97mW. A switched capacitor bias current circuit scale the bias current automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140MS/s.
cs.AR
a 12 bit pipeline adc fabricated in a 018 mum pure digital cmos technology is presented its nominal conversion rate is 110mss and the nominal supply voltage is 18v the effective number of bits is 104 when a 10mhz input signal with 2v_pp signal swing is applied the occupied silicon area is 086mm2 and the power consumption equals 97mw a switched capacitor bias current circuit scale the bias current automatically with the conversion rate which gives scaleable power consumption and full performance of the adc from 20 to 140mss
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710.484
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-a-chip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test time, and the good diagnostic capabilities. The paper reports figures about the achieved fault coverage, the required area overhead, and the performance slowdown, and compares the figures with those for alternative approaches, such as those based on full scan and sequential ATPG.
cs.AR
in this paper we describe how we applied a bistbased approach to the test of a logic core to be included in systemonachip soc environments the approach advantages are the ability to protect the core ip the simple test interface thanks also to the adoption of the p1500 standard the possibility to run the test atspeed the reduced test time and the good diagnostic capabilities the paper reports figures about the achieved fault coverage the required area overhead and the performance slowdown and compares the figures with those for alternative approaches such as those based on full scan and sequential atpg
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710.4841
Electronic structure of the c(4 x 2) reconstructed Ge(001) surface
We investigate the electronic structure of the c(4 x 2) reconstructed Ge(001) surface using band structure calculations based on density functional theory and the generalized gradient approximation. In particular, we take into account the details of surface reconstruction by means of well relaxed crystal structures. The surface electronic states are identified and the local density of states is compared to recent data from scanning tunneling spectroscopy. We obtain almost perfect agreement between theory and experiment for both the occupied and unoccupied states, which allows us to clarify the interpretation of the experimental data.
cond-mat.mtrl-sci
we investigate the electronic structure of the c4 x 2 reconstructed ge001 surface using band structure calculations based on density functional theory and the generalized gradient approximation in particular we take into account the details of surface reconstruction by means of well relaxed crystal structures the surface electronic states are identified and the local density of states is compared to recent data from scanning tunneling spectroscopy we obtain almost perfect agreement between theory and experiment for both the occupied and unoccupied states which allows us to clarify the interpretation of the experimental data
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710.4842
Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm
At 130 nm and 90 nm, power consumption (both dynamic and static) has become a barrier in the roadmap for SoC designs targeting battery powered, mobile applications. This paper presents the results of dynamic and static power reduction achieved implementing Tensilica's 32-bit Xtensa microprocessor core, using Virtual Silicon's Power Management IP. Independent voltage islands are created using Virtual Silicon's VIP PowerSaver standard cells by using voltage level shifting cells and voltage isolation cells to implement power islands. The VIP PowerSaver standard cells are characterized at 1.2V, 1.0V and 0.8V, to accommodate voltage scaling. Power islands can also be turned off completely. Designers can significantly lower both the dynamic power and the quiescent or leakage power of their SoC designs, with very little impact on speed or area using Virtual Silicon's VIP Gate Bias standard cells.
cs.AR
at 130 nm and 90 nm power consumption both dynamic and static has become a barrier in the roadmap for soc designs targeting battery powered mobile applications this paper presents the results of dynamic and static power reduction achieved implementing tensilicas 32bit xtensa microprocessor core using virtual silicons power management ip independent voltage islands are created using virtual silicons vip powersaver standard cells by using voltage level shifting cells and voltage isolation cells to implement power islands the vip powersaver standard cells are characterized at 12v 10v and 08v to accommodate voltage scaling power islands can also be turned off completely designers can significantly lower both the dynamic power and the quiescent or leakage power of their soc designs with very little impact on speed or area using virtual silicons vip gate bias standard cells
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710.4843
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable on-chip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.
cs.AR
the multinoc system implements a programmable onchip multiprocessing platform built on top of an efficient low area overhead intrachip interconnection scheme the employed interconnection structure is a network on chip or noc nocs are emerging as a viable alternative to increasing demands on interconnection architectures due to the following characteristics i energy efficiency and reliability ii scalability of bandwidth when compared to traditional bus architectures iii reusability iv distributed routing decisions an external host computer feeds multinoc with application instructions and data after this initialization procedure multinoc executes some algorithm after finishing execution of the algorithm output data can be read back by the host sequential or parallel algorithms conveniently adapted to the multinoc structure can be executed the main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in socs leading to the concept of sea of processors systems
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710.4844
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hybrid reconfigurable architecture is considered so as the methodology can be applicable to a large number of heterogeneous reconfigurable platforms. The methodology mainly consists of two stages, the analysis and the mapping of the application onto fine and coarse-grain hardware resources. A prototype framework consisting of analysis, partitioning and mapping tools has been also developed. For the coarse-grain reconfigurable hardware, we use our previous-developed high-performance coarse-grain data-path. In this work, the methodology is validated using two real-world applications, an OFDM transmitter and a JPEG encoder. In the case of the OFDM transmitter, a maximum clock cycles decrease of 82% relative to the ones in an all fine-grain mapping solution is achieved. The corresponding performance improvement for the JPEG is 43%.
cs.AR
in this paper we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity a generic hybrid reconfigurable architecture is considered so as the methodology can be applicable to a large number of heterogeneous reconfigurable platforms the methodology mainly consists of two stages the analysis and the mapping of the application onto fine and coarsegrain hardware resources a prototype framework consisting of analysis partitioning and mapping tools has been also developed for the coarsegrain reconfigurable hardware we use our previousdeveloped highperformance coarsegrain datapath in this work the methodology is validated using two realworld applications an ofdm transmitter and a jpeg encoder in the case of the ofdm transmitter a maximum clock cycles decrease of 82 relative to the ones in an all finegrain mapping solution is achieved the corresponding performance improvement for the jpeg is 43
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710.4845
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems
This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares Register Transfer Level (RTL) Hardware Description Language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained.
cs.AR
this paper evaluates the use of pin and cycle accurate systemc models for embedded system design exploration and early software development the target system is microblaze vanillanet platform running microblaze uclinux operating system the paper compares register transfer level rtl hardware description language hdl simulation speed to the simulation speed of several different systemc models it is shown that simulation speed of pin and cycle accurate models can go up to 150 khz compared to 100 hz range of hdl simulation furthermore utilising techniques that temporarily compromise cycle accuracy effective simulation speed of up to 500 khz can be obtained
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710.4846
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Recently a lot of multimedia applications are emerging on portable appliances. They require both the flexibility of upgradeable devices (traditionally software based) and a powerful computing engine (typically hardware). In this context, programmable HW and dynamic reconfiguration allow novel approaches to the migration of algorithms from SW to HW. Thus, in the frame of the Symbad project, we propose an industrial design flow for reconfigurable SoC's. The goal of Symbad consists of developing a system level design platform for hardware and software SoC systems including formal and semi-formal verification techniques.
cs.MM cs.LO
recently a lot of multimedia applications are emerging on portable appliances they require both the flexibility of upgradeable devices traditionally software based and a powerful computing engine typically hardware in this context programmable hw and dynamic reconfiguration allow novel approaches to the migration of algorithms from sw to hw thus in the frame of the symbad project we propose an industrial design flow for reconfigurable socs the goal of symbad consists of developing a system level design platform for hardware and software soc systems including formal and semiformal verification techniques
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710.4847
Bayesian sequential change diagnosis
Sequential change diagnosis is the joint problem of detection and identification of a sudden and unobservable change in the distribution of a random sequence. In this problem, the common probability law of a sequence of i.i.d. random variables suddenly changes at some disorder time to one of finitely many alternatives. This disorder time marks the start of a new regime, whose fingerprint is the new law of observations. Both the disorder time and the identity of the new regime are unknown and unobservable. The objective is to detect the regime-change as soon as possible, and, at the same time, to determine its identity as accurately as possible. Prompt and correct diagnosis is crucial for quick execution of the most appropriate measures in response to the new regime, as in fault detection and isolation in industrial processes, and target detection and identification in national defense. The problem is formulated in a Bayesian framework. An optimal sequential decision strategy is found, and an accurate numerical scheme is described for its implementation. Geometrical properties of the optimal strategy are illustrated via numerical examples. The traditional problems of Bayesian change-detection and Bayesian sequential multi-hypothesis testing are solved as special cases. In addition, a solution is obtained for the problem of detection and identification of component failure(s) in a system with suspended animation.
math.PR cs.IT math.IT math.ST stat.TH
sequential change diagnosis is the joint problem of detection and identification of a sudden and unobservable change in the distribution of a random sequence in this problem the common probability law of a sequence of iid random variables suddenly changes at some disorder time to one of finitely many alternatives this disorder time marks the start of a new regime whose fingerprint is the new law of observations both the disorder time and the identity of the new regime are unknown and unobservable the objective is to detect the regimechange as soon as possible and at the same time to determine its identity as accurately as possible prompt and correct diagnosis is crucial for quick execution of the most appropriate measures in response to the new regime as in fault detection and isolation in industrial processes and target detection and identification in national defense the problem is formulated in a bayesian framework an optimal sequential decision strategy is found and an accurate numerical scheme is described for its implementation geometrical properties of the optimal strategy are illustrated via numerical examples the traditional problems of bayesian changedetection and bayesian sequential multihypothesis testing are solved as special cases in addition a solution is obtained for the problem of detection and identification of component failures in a system with suspended animation
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710.4848
A Formal Verification Methodology for Checking Data Integrity
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verification is to define good verification scopes; we should define clearly what to be verified formally upon designs under tests. We considered the following three practical requirements when we defined the scope of formal verification. They are (a) hard to verify (b) small to handle, and (c) easy to understand. Our novel approach is to break down generic properties for system into stereotype properties in block level and to define requirements for Verifiable RTL. Consequently, each designer instead of verification experts can describe properties of the design easily, and formal model checking can be applied systematically and thoroughly to all the leaf modules. During the development of a component chip for server platforms, we focused on RAS (Reliability, Availability, and Serviceability) features and described more than 2000 properties in PSL. As a result of the formal verification, we found several critical logic bugs in a short time with limited resources, and successfully verified all of them. This paper presents a study of the functional verification methodology.
cs.LO
formal verification techniques have been playing an important role in presilicon validation processes one of the most important points considered in performing formal verification is to define good verification scopes we should define clearly what to be verified formally upon designs under tests we considered the following three practical requirements when we defined the scope of formal verification they are a hard to verify b small to handle and c easy to understand our novel approach is to break down generic properties for system into stereotype properties in block level and to define requirements for verifiable rtl consequently each designer instead of verification experts can describe properties of the design easily and formal model checking can be applied systematically and thoroughly to all the leaf modules during the development of a component chip for server platforms we focused on ras reliability availability and serviceability features and described more than 2000 properties in psl as a result of the formal verification we found several critical logic bugs in a short time with limited resources and successfully verified all of them this paper presents a study of the functional verification methodology
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710.4849
Laser-to-proton energy transfer efficiency in laser-plasma interactions
It is shown that the energy of protons accelerated in laser-matter interaction experiments may be significantly increased through the process of splitting the incoming laser pulse into multiple interaction stages of equal intensity. From a thermodynamic point of view, the splitting procedure can be viewed as an effective way of increasing the efficiency of energy transfer from the laser light to protons, which peaks for processes having the least amount of entropy gain. It is predicted that it should be possible to achieve $\apprge 100%$ increase in the energy efficiency in a six-stage laser proton accelerator compared to a single laser-target interaction scheme.
physics.plasm-ph physics.acc-ph
it is shown that the energy of protons accelerated in lasermatter interaction experiments may be significantly increased through the process of splitting the incoming laser pulse into multiple interaction stages of equal intensity from a thermodynamic point of view the splitting procedure can be viewed as an effective way of increasing the efficiency of energy transfer from the laser light to protons which peaks for processes having the least amount of entropy gain it is predicted that it should be possible to achieve apprge 100 increase in the energy efficiency in a sixstage laser proton accelerator compared to a single lasertarget interaction scheme
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710.485
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems
This contribution presents a new approach for allocating suitable function-implementation variants depending on given quality-of-service function-requirements for run-time reconfigurable multi-device systems. Our approach adapts methodologies from the domain of knowledge-based systems which can be used for doing run-time hardware/software resource usage optimizations.
cs.AR
this contribution presents a new approach for allocating suitable functionimplementation variants depending on given qualityofservice functionrequirements for runtime reconfigurable multidevice systems our approach adapts methodologies from the domain of knowledgebased systems which can be used for doing runtime hardwaresoftware resource usage optimizations
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710.4851
Common Reusable Verification Environment for BCA and RTL Models
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different people and to reuse the same environment for the two design views. Applying this methodology the verification task starts as soon as the functional specification is signed off and it runs in parallel to the models and design development. The verification environment is modeled with the aid of dedicated verification languages and it is applied to both the models. The test suite is exactly the same and thus it's possible to verify the alignment between the two models. In fact the final step is to check the cycle-by-cycle match of the interface behavior. A regression tool and a bus analyzer have been developed to help the verification and the alignment process. The former is used to automate the testbench generation and to run the two test suites. The latter is used to verify the alignment between the two models comparing the waveforms obtained in each run. The quality metrics used to validate the flow are full functional coverage and full alignment at each IP port.
cs.LO
this paper deals with a common verification methodology and environment for systemc bca and rtl models the aim is to save effort by avoiding the same work done twice by different people and to reuse the same environment for the two design views applying this methodology the verification task starts as soon as the functional specification is signed off and it runs in parallel to the models and design development the verification environment is modeled with the aid of dedicated verification languages and it is applied to both the models the test suite is exactly the same and thus its possible to verify the alignment between the two models in fact the final step is to check the cyclebycycle match of the interface behavior a regression tool and a bus analyzer have been developed to help the verification and the alignment process the former is used to automate the testbench generation and to run the two test suites the latter is used to verify the alignment between the two models comparing the waveforms obtained in each run the quality metrics used to validate the flow are full functional coverage and full alignment at each ip port
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710.4852
An Assembler Driven Verification Methodology (ADVM)
This paper presents an overview of an assembler driven verification methodology (ADVM) that was created and implemented for a chip card project at Infineon Technologies AG. The primary advantage of this methodology is that it enables rapid porting of directed tests to new targets and derivatives, with only a minimum amount of code refactoring. As a consequence, considerable verification development time and effort was saved.
cs.OH
this paper presents an overview of an assembler driven verification methodology advm that was created and implemented for a chip card project at infineon technologies ag the primary advantage of this methodology is that it enables rapid porting of directed tests to new targets and derivatives with only a minimum amount of code refactoring as a consequence considerable verification development time and effort was saved
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