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<title>Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</title>
<title>CMSIS-Core (Cortex-M): Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</title>
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<a href="#func-members">Functions</a> </div>
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<div class="title">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</div> </div>
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<p>Access to dedicated SIMD instructions.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gac20aa0f741d0a1494d58c531e38d5785"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac20aa0f741d0a1494d58c531e38d5785">__SADD8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gac20aa0f741d0a1494d58c531e38d5785"><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit signed addition. <a href="#gac20aa0f741d0a1494d58c531e38d5785">More...</a><br/></td></tr>
<tr class="separator:gac20aa0f741d0a1494d58c531e38d5785"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf2f5a9132dcfc6d01d34cd971c425713"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713">__QADD8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gaf2f5a9132dcfc6d01d34cd971c425713"><td class="mdescLeft"> </td><td class="mdescRight">Q setting quad 8-bit saturating addition. <a href="#gaf2f5a9132dcfc6d01d34cd971c425713">More...</a><br/></td></tr>
<tr class="separator:gaf2f5a9132dcfc6d01d34cd971c425713"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga524575b442ea01aec10c762bf4d85fea"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga524575b442ea01aec10c762bf4d85fea">__SHADD8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga524575b442ea01aec10c762bf4d85fea"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit signed addition with halved results. <a href="#ga524575b442ea01aec10c762bf4d85fea">More...</a><br/></td></tr>
<tr class="separator:ga524575b442ea01aec10c762bf4d85fea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab3d7fd00d113b20fb3741a17394da762"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gab3d7fd00d113b20fb3741a17394da762">__UADD8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gab3d7fd00d113b20fb3741a17394da762"><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit unsigned addition. <a href="#gab3d7fd00d113b20fb3741a17394da762">More...</a><br/></td></tr>
<tr class="separator:gab3d7fd00d113b20fb3741a17394da762"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafa9af218db3934a692fb06fa728d8031"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gafa9af218db3934a692fb06fa728d8031">__UQADD8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gafa9af218db3934a692fb06fa728d8031"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned saturating addition. <a href="#gafa9af218db3934a692fb06fa728d8031">More...</a><br/></td></tr>
<tr class="separator:gafa9af218db3934a692fb06fa728d8031"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3a14e5485e59bf0f23595b7c2a94eb0b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga3a14e5485e59bf0f23595b7c2a94eb0b">__UHADD8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga3a14e5485e59bf0f23595b7c2a94eb0b"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned addition with halved results. <a href="#ga3a14e5485e59bf0f23595b7c2a94eb0b">More...</a><br/></td></tr>
<tr class="separator:ga3a14e5485e59bf0f23595b7c2a94eb0b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba63bb52e1e93fb527e26f3d474da12e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaba63bb52e1e93fb527e26f3d474da12e">__SSUB8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gaba63bb52e1e93fb527e26f3d474da12e"><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit signed subtraction. <a href="#gaba63bb52e1e93fb527e26f3d474da12e">More...</a><br/></td></tr>
<tr class="separator:gaba63bb52e1e93fb527e26f3d474da12e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga753493a65493880c28baa82c151a0d61"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga753493a65493880c28baa82c151a0d61">__QSUB8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga753493a65493880c28baa82c151a0d61"><td class="mdescLeft"> </td><td class="mdescRight">Q setting quad 8-bit saturating subtract. <a href="#ga753493a65493880c28baa82c151a0d61">More...</a><br/></td></tr>
<tr class="separator:ga753493a65493880c28baa82c151a0d61"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac3ec7215b354d925a239f3b31df2b77b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac3ec7215b354d925a239f3b31df2b77b">__SHSUB8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gac3ec7215b354d925a239f3b31df2b77b"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit signed subtraction with halved results. <a href="#gac3ec7215b354d925a239f3b31df2b77b">More...</a><br/></td></tr>
<tr class="separator:gac3ec7215b354d925a239f3b31df2b77b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacb7257dc3b8e9acbd0ef0e31ff87d4b8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">__USUB8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gacb7257dc3b8e9acbd0ef0e31ff87d4b8"><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit unsigned subtract. <a href="#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">More...</a><br/></td></tr>
<tr class="separator:gacb7257dc3b8e9acbd0ef0e31ff87d4b8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9736fe816aec74fe886e7fb949734eab"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9736fe816aec74fe886e7fb949734eab">__UQSUB8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga9736fe816aec74fe886e7fb949734eab"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned saturating subtraction. <a href="#ga9736fe816aec74fe886e7fb949734eab">More...</a><br/></td></tr>
<tr class="separator:ga9736fe816aec74fe886e7fb949734eab"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga48a55df1c3e73923b73819d7c19b392d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga48a55df1c3e73923b73819d7c19b392d">__UHSUB8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga48a55df1c3e73923b73819d7c19b392d"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned subtraction with halved results. <a href="#ga48a55df1c3e73923b73819d7c19b392d">More...</a><br/></td></tr>
<tr class="separator:ga48a55df1c3e73923b73819d7c19b392d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad0bf46373a1c05aabf64517e84be5984"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad0bf46373a1c05aabf64517e84be5984">__SADD16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gad0bf46373a1c05aabf64517e84be5984"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed addition. <a href="#gad0bf46373a1c05aabf64517e84be5984">More...</a><br/></td></tr>
<tr class="separator:gad0bf46373a1c05aabf64517e84be5984"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae83a53ec04b496304bed6d9fe8f7461b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gae83a53ec04b496304bed6d9fe8f7461b">__QADD16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gae83a53ec04b496304bed6d9fe8f7461b"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturating addition. <a href="#gae83a53ec04b496304bed6d9fe8f7461b">More...</a><br/></td></tr>
<tr class="separator:gae83a53ec04b496304bed6d9fe8f7461b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga15d8899a173effb8ad8c7268da32b60e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga15d8899a173effb8ad8c7268da32b60e"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed addition with halved results. <a href="#ga15d8899a173effb8ad8c7268da32b60e">More...</a><br/></td></tr>
<tr class="separator:ga15d8899a173effb8ad8c7268da32b60e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa1160f0cf76d6aa292fbad54a1aa6b74"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74">__UADD16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gaa1160f0cf76d6aa292fbad54a1aa6b74"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned addition. <a href="#gaa1160f0cf76d6aa292fbad54a1aa6b74">More...</a><br/></td></tr>
<tr class="separator:gaa1160f0cf76d6aa292fbad54a1aa6b74"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9e2cc5117e79578a08b25f1e89022966"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9e2cc5117e79578a08b25f1e89022966">__UQADD16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga9e2cc5117e79578a08b25f1e89022966"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating addition. <a href="#ga9e2cc5117e79578a08b25f1e89022966">More...</a><br/></td></tr>
<tr class="separator:ga9e2cc5117e79578a08b25f1e89022966"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabd0b0e2da2e6364e176d051687702b86"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gabd0b0e2da2e6364e176d051687702b86">__UHADD16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gabd0b0e2da2e6364e176d051687702b86"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned addition with halved results. <a href="#gabd0b0e2da2e6364e176d051687702b86">More...</a><br/></td></tr>
<tr class="separator:gabd0b0e2da2e6364e176d051687702b86"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4262f73be75efbac6b46ab7c71aa6cbc"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">__SSUB16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga4262f73be75efbac6b46ab7c71aa6cbc"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed subtraction. <a href="#ga4262f73be75efbac6b46ab7c71aa6cbc">More...</a><br/></td></tr>
<tr class="separator:ga4262f73be75efbac6b46ab7c71aa6cbc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad089605c16df9823a2c8aaa37777aae5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad089605c16df9823a2c8aaa37777aae5">__QSUB16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gad089605c16df9823a2c8aaa37777aae5"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturating subtract. <a href="#gad089605c16df9823a2c8aaa37777aae5">More...</a><br/></td></tr>
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<tr class="memitem:ga31328467f0f91b8ff9ae9a01682ad3bf"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf">__SHSUB16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga31328467f0f91b8ff9ae9a01682ad3bf"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed subtraction with halved results. <a href="#ga31328467f0f91b8ff9ae9a01682ad3bf">More...</a><br/></td></tr>
<tr class="separator:ga31328467f0f91b8ff9ae9a01682ad3bf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9f2b77e11fc4a77b26c36c423ed45b4e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e">__USUB16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga9f2b77e11fc4a77b26c36c423ed45b4e"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned subtract. <a href="#ga9f2b77e11fc4a77b26c36c423ed45b4e">More...</a><br/></td></tr>
<tr class="separator:ga9f2b77e11fc4a77b26c36c423ed45b4e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5ec4e2e231d15e5c692233feb3806187"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5ec4e2e231d15e5c692233feb3806187">__UQSUB16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga5ec4e2e231d15e5c692233feb3806187"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating subtraction. <a href="#ga5ec4e2e231d15e5c692233feb3806187">More...</a><br/></td></tr>
<tr class="separator:ga5ec4e2e231d15e5c692233feb3806187"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1f7545b8dc33bb97982731cb9d427a69"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga1f7545b8dc33bb97982731cb9d427a69">__UHSUB16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga1f7545b8dc33bb97982731cb9d427a69"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned subtraction with halved results. <a href="#ga1f7545b8dc33bb97982731cb9d427a69">More...</a><br/></td></tr>
<tr class="separator:ga1f7545b8dc33bb97982731cb9d427a69"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5845084fd99c872e98cf5553d554de2a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5845084fd99c872e98cf5553d554de2a">__SASX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga5845084fd99c872e98cf5553d554de2a"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit addition and subtraction with exchange. <a href="#ga5845084fd99c872e98cf5553d554de2a">More...</a><br/></td></tr>
<tr class="separator:ga5845084fd99c872e98cf5553d554de2a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga87618799672e1511e33964bc71467eb3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga87618799672e1511e33964bc71467eb3"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit add and subtract with exchange. <a href="#ga87618799672e1511e33964bc71467eb3">More...</a><br/></td></tr>
<tr class="separator:ga87618799672e1511e33964bc71467eb3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae0a649035f67627464fd80e7218c89d5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gae0a649035f67627464fd80e7218c89d5"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed addition and subtraction with halved results. <a href="#gae0a649035f67627464fd80e7218c89d5">More...</a><br/></td></tr>
<tr class="separator:gae0a649035f67627464fd80e7218c89d5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga980353d2c72ebb879282e49f592fddc0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga980353d2c72ebb879282e49f592fddc0">__UASX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga980353d2c72ebb879282e49f592fddc0"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned addition and subtraction with exchange. <a href="#ga980353d2c72ebb879282e49f592fddc0">More...</a><br/></td></tr>
<tr class="separator:ga980353d2c72ebb879282e49f592fddc0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5eff3ae5eabcd73f3049996ca391becb"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5eff3ae5eabcd73f3049996ca391becb">__UQASX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga5eff3ae5eabcd73f3049996ca391becb"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating addition and subtraction with exchange. <a href="#ga5eff3ae5eabcd73f3049996ca391becb">More...</a><br/></td></tr>
<tr class="separator:ga5eff3ae5eabcd73f3049996ca391becb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga028f0732b961fb6e5209326fb3855261"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga028f0732b961fb6e5209326fb3855261">__UHASX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga028f0732b961fb6e5209326fb3855261"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned addition and subtraction with halved results and exchange. <a href="#ga028f0732b961fb6e5209326fb3855261">More...</a><br/></td></tr>
<tr class="separator:ga028f0732b961fb6e5209326fb3855261"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9d3bc5c539f9bd50f7d59ffa37ac6a65"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">__SSAX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga9d3bc5c539f9bd50f7d59ffa37ac6a65"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed subtraction and addition with exchange. <a href="#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">More...</a><br/></td></tr>
<tr class="separator:ga9d3bc5c539f9bd50f7d59ffa37ac6a65"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab41eb2b17512ab01d476fc9d5bd19520"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gab41eb2b17512ab01d476fc9d5bd19520"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit subtract and add with exchange. <a href="#gab41eb2b17512ab01d476fc9d5bd19520">More...</a><br/></td></tr>
<tr class="separator:gab41eb2b17512ab01d476fc9d5bd19520"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafadbd89c36b5addcf1ca10dd392db3e9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gafadbd89c36b5addcf1ca10dd392db3e9"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed subtraction and addition with halved results. <a href="#gafadbd89c36b5addcf1ca10dd392db3e9">More...</a><br/></td></tr>
<tr class="separator:gafadbd89c36b5addcf1ca10dd392db3e9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga578a082747436772c482c96d7a58e45e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga578a082747436772c482c96d7a58e45e">__USAX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga578a082747436772c482c96d7a58e45e"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned subtract and add with exchange. <a href="#ga578a082747436772c482c96d7a58e45e">More...</a><br/></td></tr>
<tr class="separator:ga578a082747436772c482c96d7a58e45e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadecfdfabc328d8939d49d996f2fd4482"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gadecfdfabc328d8939d49d996f2fd4482">__UQSAX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gadecfdfabc328d8939d49d996f2fd4482"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating subtraction and addition with exchange. <a href="#gadecfdfabc328d8939d49d996f2fd4482">More...</a><br/></td></tr>
<tr class="separator:gadecfdfabc328d8939d49d996f2fd4482"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga09e129e6613329aab87c89f1108b7ed7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga09e129e6613329aab87c89f1108b7ed7">__UHSAX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga09e129e6613329aab87c89f1108b7ed7"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned subtraction and addition with halved results and exchange. <a href="#ga09e129e6613329aab87c89f1108b7ed7">More...</a><br/></td></tr>
<tr class="separator:ga09e129e6613329aab87c89f1108b7ed7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac8855c07044239ea775c8128013204f0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac8855c07044239ea775c8128013204f0">__USAD8</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gac8855c07044239ea775c8128013204f0"><td class="mdescLeft"> </td><td class="mdescRight">Unsigned sum of quad 8-bit unsigned absolute difference. <a href="#gac8855c07044239ea775c8128013204f0">More...</a><br/></td></tr>
<tr class="separator:gac8855c07044239ea775c8128013204f0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad032bd21f013c5d29f5fcb6b0f02bc3f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad032bd21f013c5d29f5fcb6b0f02bc3f">__USADA8</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr>
<tr class="memdesc:gad032bd21f013c5d29f5fcb6b0f02bc3f"><td class="mdescLeft"> </td><td class="mdescRight">Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. <a href="#gad032bd21f013c5d29f5fcb6b0f02bc3f">More...</a><br/></td></tr>
<tr class="separator:gad032bd21f013c5d29f5fcb6b0f02bc3f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga95e666b82216066bf6064d1244e6883c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga95e666b82216066bf6064d1244e6883c">__SSAT16</a> (uint32_t val1, const uint32_t val2)</td></tr>
<tr class="memdesc:ga95e666b82216066bf6064d1244e6883c"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturate. <a href="#ga95e666b82216066bf6064d1244e6883c">More...</a><br/></td></tr>
<tr class="separator:ga95e666b82216066bf6064d1244e6883c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga967f516afff5900cf30f1a81907cdd89"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga967f516afff5900cf30f1a81907cdd89">__USAT16</a> (uint32_t val1, const uint32_t val2)</td></tr>
<tr class="memdesc:ga967f516afff5900cf30f1a81907cdd89"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit unsigned saturate. <a href="#ga967f516afff5900cf30f1a81907cdd89">More...</a><br/></td></tr>
<tr class="separator:ga967f516afff5900cf30f1a81907cdd89"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab41d713653b16f8d9fef44d14e397228"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gab41d713653b16f8d9fef44d14e397228">__UXTB16</a> (uint32_t val)</td></tr>
<tr class="memdesc:gab41d713653b16f8d9fef44d14e397228"><td class="mdescLeft"> </td><td class="mdescRight">Dual extract 8-bits and zero-extend to 16-bits. <a href="#gab41d713653b16f8d9fef44d14e397228">More...</a><br/></td></tr>
<tr class="separator:gab41d713653b16f8d9fef44d14e397228"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad25ce96db0f17096bbd815f4817faf09"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad25ce96db0f17096bbd815f4817faf09">__UXTAB16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gad25ce96db0f17096bbd815f4817faf09"><td class="mdescLeft"> </td><td class="mdescRight">Extracted 16-bit to 32-bit unsigned addition. <a href="#gad25ce96db0f17096bbd815f4817faf09">More...</a><br/></td></tr>
<tr class="separator:gad25ce96db0f17096bbd815f4817faf09"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">__SXTB16</a> (uint32_t val)</td></tr>
<tr class="memdesc:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="mdescLeft"> </td><td class="mdescRight">Dual extract 8-bits and sign extend each to 16-bits. <a href="#ga38dce3dd13ba212e80ec3cff4abeb11a">More...</a><br/></td></tr>
<tr class="separator:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac540b4fc41d30778ba102d2a65db5589"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac540b4fc41d30778ba102d2a65db5589">__SXTAB16</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gac540b4fc41d30778ba102d2a65db5589"><td class="mdescLeft"> </td><td class="mdescRight">Dual extracted 8-bit to 16-bit signed addition. <a href="#gac540b4fc41d30778ba102d2a65db5589">More...</a><br/></td></tr>
<tr class="separator:gac540b4fc41d30778ba102d2a65db5589"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae326e368a1624d2dfb4b97c626939257"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gae326e368a1624d2dfb4b97c626939257">__SMUAD</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gae326e368a1624d2dfb4b97c626939257"><td class="mdescLeft"> </td><td class="mdescRight">Q setting sum of dual 16-bit signed multiply. <a href="#gae326e368a1624d2dfb4b97c626939257">More...</a><br/></td></tr>
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<tr class="memitem:gaee6390f86965cb662500f690b0012092"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaee6390f86965cb662500f690b0012092">__SMUADX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gaee6390f86965cb662500f690b0012092"><td class="mdescLeft"> </td><td class="mdescRight">Q setting sum of dual 16-bit signed multiply with exchange. <a href="#gaee6390f86965cb662500f690b0012092">More...</a><br/></td></tr>
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<tr class="memitem:gaea60757232f740ec6b09980eebb614ff"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> (int32_t val1, int32_t val2, int32_t val3)</td></tr>
<tr class="memdesc:gaea60757232f740ec6b09980eebb614ff"><td class="mdescLeft"> </td><td class="mdescRight">32-bit signed multiply with 32-bit truncated accumulator. <a href="#gaea60757232f740ec6b09980eebb614ff">More...</a><br/></td></tr>
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<tr class="memitem:gae0c86f3298532183f3a29f5bb454d354"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gae0c86f3298532183f3a29f5bb454d354">__SMLAD</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr>
<tr class="memdesc:gae0c86f3298532183f3a29f5bb454d354"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with single 32-bit accumulator. <a href="#gae0c86f3298532183f3a29f5bb454d354">More...</a><br/></td></tr>
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<tr class="memitem:ga9c286d330f4fb29b256335add91eec9f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9c286d330f4fb29b256335add91eec9f">__SMLADX</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr>
<tr class="memdesc:ga9c286d330f4fb29b256335add91eec9f"><td class="mdescLeft"> </td><td class="mdescRight">Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. <a href="#ga9c286d330f4fb29b256335add91eec9f">More...</a><br/></td></tr>
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<tr class="memitem:gad80e9b20c1736fd798f897362273a146"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad80e9b20c1736fd798f897362273a146">__SMLALD</a> (uint32_t val1, uint32_t val2, uint64_t val3)</td></tr>
<tr class="memdesc:gad80e9b20c1736fd798f897362273a146"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with single 64-bit accumulator. <a href="#gad80e9b20c1736fd798f897362273a146">More...</a><br/></td></tr>
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<tr class="memitem:gad1adad1b3f2667328cc0db6c6b4f41cf"><td class="memItemLeft" align="right" valign="top">unsigned long long </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf">__SMLALDX</a> (uint32_t val1, uint32_t val2, unsigned long long val3)</td></tr>
<tr class="memdesc:gad1adad1b3f2667328cc0db6c6b4f41cf"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with exchange with single 64-bit accumulator. <a href="#gad1adad1b3f2667328cc0db6c6b4f41cf">More...</a><br/></td></tr>
<tr class="separator:gad1adad1b3f2667328cc0db6c6b4f41cf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga039142a5368840683cf329cb55b73f84"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga039142a5368840683cf329cb55b73f84">__SMUSD</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga039142a5368840683cf329cb55b73f84"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply returning difference. <a href="#ga039142a5368840683cf329cb55b73f84">More...</a><br/></td></tr>
<tr class="separator:ga039142a5368840683cf329cb55b73f84"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabb5bcba694bf17b141c32e6a8474f60e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gabb5bcba694bf17b141c32e6a8474f60e">__SMUSDX</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gabb5bcba694bf17b141c32e6a8474f60e"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with exchange returning difference. <a href="#gabb5bcba694bf17b141c32e6a8474f60e">More...</a><br/></td></tr>
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<tr class="memitem:gaf4350af7f2030c36f43b2c104a9d16cd"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd">__SMLSD</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr>
<tr class="memdesc:gaf4350af7f2030c36f43b2c104a9d16cd"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply subtract with 32-bit accumulate. <a href="#gaf4350af7f2030c36f43b2c104a9d16cd">More...</a><br/></td></tr>
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<tr class="memitem:ga5290ce5564770ad124910d2583dc0a9e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5290ce5564770ad124910d2583dc0a9e">__SMLSDX</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr>
<tr class="memdesc:ga5290ce5564770ad124910d2583dc0a9e"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. <a href="#ga5290ce5564770ad124910d2583dc0a9e">More...</a><br/></td></tr>
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<tr class="memitem:ga5611f7314e0c8f53da377918dfbf42ee"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5611f7314e0c8f53da377918dfbf42ee">__SMLSLD</a> (uint32_t val1, uint32_t val2, uint64_t val3)</td></tr>
<tr class="memdesc:ga5611f7314e0c8f53da377918dfbf42ee"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply subtract with 64-bit accumulate. <a href="#ga5611f7314e0c8f53da377918dfbf42ee">More...</a><br/></td></tr>
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<tr class="memitem:ga83e69ef81057d3cbd06863d729385187"><td class="memItemLeft" align="right" valign="top">unsigned long long </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga83e69ef81057d3cbd06863d729385187">__SMLSLDX</a> (uint32_t val1, uint32_t val2, unsigned long long val3)</td></tr>
<tr class="memdesc:ga83e69ef81057d3cbd06863d729385187"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. <a href="#ga83e69ef81057d3cbd06863d729385187">More...</a><br/></td></tr>
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<tr class="memitem:gaf5448e591fe49161b6759b48aecb08fe"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaf5448e591fe49161b6759b48aecb08fe">__SEL</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:gaf5448e591fe49161b6759b48aecb08fe"><td class="mdescLeft"> </td><td class="mdescRight">Select bytes based on GE bits. <a href="#gaf5448e591fe49161b6759b48aecb08fe">More...</a><br/></td></tr>
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<tr class="memitem:ga17b873f246c9f5e9355760ffef3dad4a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga17b873f246c9f5e9355760ffef3dad4a">__QADD</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga17b873f246c9f5e9355760ffef3dad4a"><td class="mdescLeft"> </td><td class="mdescRight">Q setting saturating add. <a href="#ga17b873f246c9f5e9355760ffef3dad4a">More...</a><br/></td></tr>
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<tr class="memitem:ga3ba259f8f05a36f7b88b469a71ffc096"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096">__QSUB</a> (uint32_t val1, uint32_t val2)</td></tr>
<tr class="memdesc:ga3ba259f8f05a36f7b88b469a71ffc096"><td class="mdescLeft"> </td><td class="mdescRight">Q setting saturating subtract. <a href="#ga3ba259f8f05a36f7b88b469a71ffc096">More...</a><br/></td></tr>
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<tr class="memitem:gaefb8ebf3a54e197464da1ff69a44f4b5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5">__PKHBT</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr>
<tr class="memdesc:gaefb8ebf3a54e197464da1ff69a44f4b5"><td class="mdescLeft"> </td><td class="mdescRight">Halfword packing instruction. Combines bits[15:0] of <em>val1</em> with bits[31:16] of <em>val2</em> levitated with the <em>val3</em>. <a href="#gaefb8ebf3a54e197464da1ff69a44f4b5">More...</a><br/></td></tr>
<tr class="separator:gaefb8ebf3a54e197464da1ff69a44f4b5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafd8fe4a6d87e947caa81a69ec36c1666"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">__PKHTB</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr>
<tr class="memdesc:gafd8fe4a6d87e947caa81a69ec36c1666"><td class="mdescLeft"> </td><td class="mdescRight">Halfword packing instruction. Combines bits[31:16] of <em>val1</em> with bits[15:0] of <em>val2</em> right-shifted with the <em>val3</em>. <a href="#gafd8fe4a6d87e947caa81a69ec36c1666">More...</a><br/></td></tr>
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</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p><b>Single Instruction Multiple Data (SIMD)</b> extensions are provided <b>only for Cortex-M4 and Cortex-M7 cores</b> to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.</p>
<p><b>SIMD Features:</b></p>
<ul>
<li>Simultaneous computation of 2x16-bit or 4x8-bit operands</li>
<li>Fractional arithmetic</li>
<li>User definable saturation modes (arbitrary word-width)</li>
<li>Dual 16x16 multiply-add/subtract 32x32 fractional MAC</li>
<li>Simultaneous 8/16-bit select operations</li>
<li>Performance up to 3.2 GOPS at 800MHz</li>
<li>Performance is achieved with a "near zero" increase in power consumption on a typical implementation</li>
</ul>
<p><b>Examples:</b> </p>
<p><b>Addition:</b> Add two values using SIMD function</p>
<div class="fragment"><div class="line">uint32_t add_halfwords(uint32_t val1, uint32_t val2)</div>
<div class="line">{</div>
<div class="line"> <span class="keywordflow">return</span> <a class="code" href="group__intrinsic__SIMD__gr.html#gad0bf46373a1c05aabf64517e84be5984">__SADD16</a>(val1, val2);</div>
<div class="line">}</div>
</div><!-- fragment --><p><b>Subtraction:</b> Subtract two values using SIMD function</p>
<div class="fragment"><div class="line">uint32_t sub_halfwords(uint32_t val1, uint32_t val2)</div>
<div class="line">{</div>
<div class="line"> <span class="keywordflow">return</span> <a class="code" href="group__intrinsic__SIMD__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">__SSUB16</a>(val1, val2);</div>
<div class="line">}</div>
</div><!-- fragment --><p><b>Multiplication:</b> Performing a multiplication using SIMD function</p>
<div class="fragment"><div class="line">uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)</div>
<div class="line">{</div>
<div class="line"> <span class="keywordflow">return</span> <a class="code" href="group__intrinsic__SIMD__gr.html#gae326e368a1624d2dfb4b97c626939257">__SMUAD</a>(val1, val2);</div>
<div class="line">}</div>
</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="gaefb8ebf3a54e197464da1ff69a44f4b5"></a>
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<td class="memname">uint32_t __PKHBT </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
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<td>)</td>
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<p>Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands </td></tr>
<tr><td class="paramname">val3</td><td>value for left-shifting <em>val2</em>. Value range [0..31].</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the combination of halfwords.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0]</div>
<div class="line">res[31:16] = val2[31:16]<<val3 </div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __PKHTB </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val3</em> </td>
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<p>Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>second 16-bit operands </td></tr>
<tr><td class="paramname">val2</td><td>first 16-bit operands </td></tr>
<tr><td class="paramname">val3</td><td>value for right-shifting <em>val2</em>. Value range [1..32].</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the combination of halfwords.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val2[15:0]>>val3</div>
<div class="line">res[31:16] = val1[31:16] </div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
<a class="anchor" id="ga17b873f246c9f5e9355760ffef3dad4a"></a>
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<td class="memname">uint32_t __QADD </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
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<p>This function enables you to obtain the saturating add of two integers.<br/>
The Q bit is set if the operation saturates.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first summand of the saturating add operation. </td></tr>
<tr><td class="paramname">val2</td><td>second summand of the saturating add operation.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the saturating addition of val1 and val2.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[31:0] = SAT(val1 + SAT(val2))</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __QADD16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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<p>This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the saturated addition of the low halfwords, in the low halfword of the return value. </li>
<li>the saturated addition of the high halfwords, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0]</div>
<div class="line">res[31:16] = val1[31:16] + val2[31:16]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __QADD8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the saturated addition of the first byte of each operand in the first byte of the return value. </li>
<li>the saturated addition of the second byte of each operand in the second byte of the return value. </li>
<li>the saturated addition of the third byte of each operand in the third byte of the return value. </li>
<li>the saturated addition of the fourth byte of each operand in the fourth byte of the return value. </li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] </div>
<div class="line">res[15:8] = val1[15:8] + val2[15:8] </div>
<div class="line">res[23:16] = val1[23:16] + val2[23:16] </div>
<div class="line">res[31:24] = val1[31:24] + val2[31:24] </div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __QASX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[31:16] </div>
<div class="line">res[31:16] = val1[31:16] + val2[15:0] </div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __QSAX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value. </li>
<li>the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value. </li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[31:16]</div>
<div class="line">res[31:16] = val1[31:16] - val2[15:0] </div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __QSUB </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to obtain the saturating subtraction of two integers.<br/>
The Q bit is set if the operation saturates.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>minuend of the saturating subtraction operation. </td></tr>
<tr><td class="paramname">val2</td><td>subtrahend of the saturating subtraction operation.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the saturating subtraction of val1 and val2.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[31:0] = SAT(val1 - SAT(val2))</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __QSUB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. </li>
<li>the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0]</div>
<div class="line">res[31:16] = val1[31:16] - val2[31:16]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __QSUB8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li>
<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li>
<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li>
<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The returned results are saturated to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0] </div>
<div class="line">res[15:8] = val1[15:8] - val2[15:8]</div>
<div class="line">res[23:16] = val1[23:16] - val2[23:16]</div>
<div class="line">res[31:24] = val1[31:24] - val2[31:24]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SADD16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit signed integer additions.<br/>
The GE bits in the APSR are set according to the results of the additions.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the addition of the low halfwords in the low halfword of the return value. </li>
<li>the addition of the high halfwords in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li>
<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0]</div>
<div class="line">res[31:16] = val1[31:16] + val2[31:16]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SADD8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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<p>This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the addition of the first bytes from each operand, in the first byte of the return value. </li>
<li>the addition of the second bytes of each operand, in the second byte of the return value. </li>
<li>the addition of the third bytes of each operand, in the third byte of the return value. </li>
<li>the addition of the fourth bytes of each operand, in the fourth byte of the return value. </li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[7:0] >= 0 then APSR.GE[0] = 1 else 0 </li>
<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li>
<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li>
<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] </div>
<div class="line">res[15:8] = val1[15:8] + val2[15:8] </div>
<div class="line">res[23:16] = val1[23:16] + val2[23:16] </div>
<div class="line">res[31:24] = val1[31:24] + val2[31:24] </div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SASX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.<br/>
The GE bits in the APRS are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li>
<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[31:16] </div>
<div class="line">res[31:16] = val1[31:16] + val2[15:0] </div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SEL </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>four selectable 8-bit values. </td></tr>
<tr><td class="paramname">val2</td><td>four selectable 8-bit values.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria: <ul>
<li>if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0] </li>
<li>if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8] </li>
<li>if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16] </li>
<li>if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24] </li>
</ul>
</dd></dl>
</div>
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<td class="memname">uint32_t __SHADD16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two signed 16-bit integer additions, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved addition of the low halfwords, in the low halfword of the return value. </li>
<li>the halved addition of the high halfwords, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0] >> 1</div>
<div class="line">res[31:16] = val1[31:16] + val2[31:16] >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SHADD8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four signed 8-bit integer additions, halving the results. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved addition of the first bytes from each operand, in the first byte of the return value. </li>
<li>the halved addition of the second bytes from each operand, in the second byte of the return value. </li>
<li>the halved addition of the third bytes from each operand, in the third byte of the return value. </li>
<li>the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] >> 1</div>
<div class="line">res[15:8] = val1[15:8] + val2[15:8] >> 1</div>
<div class="line">res[23:16] = val1[23:16] + val2[23:16] >> 1</div>
<div class="line">res[31:24] = val1[31:24] + val2[31:24] >> 1 </div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SHASX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = (val1[15:0] - val2[31:16]) >> 1 </div>
<div class="line">res[31:16] = (val1[31:16] - val2[15:0] ) >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SHSAX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li>
<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = (val1[15:0] + val2[31:16]) >> 1</div>
<div class="line">res[31:16] = (val1[31:16] - val2[15:0] ) >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SHSUB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two signed 16-bit integer subtractions, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. </li>
<li>the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0] >> 1</div>
<div class="line">res[31:16] = val1[31:16] - val2[31:16] >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SHSUB8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four signed 8-bit integer subtractions, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li>
<li>the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li>
<li>the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li>
<li>the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0] >> 1</div>
<div class="line">res[15:8] = val1[15:8] - val2[15:8] >> 1</div>
<div class="line">res[23:16] = val1[23:16] - val2[23:16] >> 1</div>
<div class="line">res[31:24] = val1[31:24] - val2[31:24] >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SMLAD </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.<br/>
The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the product of each multiplication added to the accumulate value, as a 32-bit integer.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div>
<div class="line">p2 = val1[31:16] * val2[31:16]</div>
<div class="line">res[31:0] = p1 + p2 + val3[31:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SMLADX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.<br/>
The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div>
<div class="line">p2 = val1[31:16] * val2[15:0]</div>
<div class="line">res[31:0] = p1 + p2 + val3[31:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint64_t __SMLALD </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint64_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the product of each multiplication added to the accumulate value.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div>
<div class="line">p2 = val1[31:16] * val2[31:16]</div>
<div class="line">sum = p1 + p2 + val3[63:32][31:0]</div>
<div class="line">res[63:32] = sum[63:32]</div>
<div class="line">res[31:0] = sum[31:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">unsigned long long __SMLALDX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">unsigned long long </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the product of each multiplication added to the accumulate value.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div>
<div class="line">p2 = val1[31:16] * val2[15:0]</div>
<div class="line">sum = p1 + p2 + val3[63:32][31:0]</div>
<div class="line">res[63:32] = sum[63:32]</div>
<div class="line">res[31:0] = sum[31:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SMLSD </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.<br/>
The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div>
<div class="line">p2 = val1[31:16] * val2[31:16]</div>
<div class="line">res[31:0] = p1 - p2 + val3[31:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __SMLSDX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.<br/>
The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div>
<div class="line">p2 = val1[31:16] * val2[15:0]</div>
<div class="line">res[31:0] = p1 - p2 + val3[31:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint64_t __SMLSLD </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint64_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo2<sup>64</sup>.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div>
<div class="line">p2 = val1[31:16] * val2[31:16]</div>
<div class="line">res[63:0] = p1 - p2 + val3[63:0]</div>
</div><!-- fragment --> </dd></dl>
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<td class="memname">unsigned long long __SMLSLDX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">unsigned long long </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo2<sup>64</sup>.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div>
<div class="line">p2 = val1[31:16] * val2[15:0]</div>
<div class="line">res[63:0] = p1 - p2 + val3[63:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SMMLA </td>
<td>(</td>
<td class="paramtype">int32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">int32_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform a signed 32-bit multiplications, adding the most significant 32 bits of the 64-bit result to a 32-bit accumulate operand.<br/>
</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for multiplication. </td></tr>
<tr><td class="paramname">val3</td><td>accumulate value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p = val1 * val2</div>
<div class="line">res[31:0] = p[61:32] + val3[31:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SMUAD </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit signed multiplications, adding the products together.<br/>
The Q bit is set if the addition overflows.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the sum of the products of the two 16-bit signed multiplications.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div>
<div class="line">p2 = val1[31:16] * val2[31:16]</div>
<div class="line">res[31:0] = p1 + p2</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SMUADX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.<br/>
The Q bit is set if the addition overflows.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div>
<div class="line">p2 = val1[31:16] * val2[15:0]</div>
<div class="line">res[31:0] = p1 + p2</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SMUSD </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the difference of the products of the two 16-bit signed multiplications.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div>
<div class="line">p2 = val1[31:16] * val2[31:16]</div>
<div class="line">res[31:0] = p1 - p2</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SMUSDX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the difference of the products of the two 16-bit signed multiplications.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div>
<div class="line">p2 = val1[31:16] * val2[15:0]</div>
<div class="line">res[31:0] = p1 - p2</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SSAT16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">const uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to saturate two signed 16-bit values to a selected signed range.<br/>
The Q bit is set if either operation saturates.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>two signed 16-bit values to be saturated. </td></tr>
<tr><td class="paramname">val2</td><td>bit position for saturation, an integral constant expression in the range 1 to 16.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the sum of the absolute differences of the following bytes, added to the accumulation value: <ul>
<li>the signed saturation of the low halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the low halfword of the return value. </li>
<li>the signed saturation of the high halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">Saturate halfwords in val1 to the <span class="keywordtype">signed</span> range specified by the bit position in val2</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SSAX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.<br/>
The GE bits in the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li>
<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li>
<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[31:16]</div>
<div class="line">res[31:16] = val1[31:16] - val2[15:0] </div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SSUB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit signed integer subtractions.<br/>
The GE bits in the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit operands of each subtraction. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit operands of each subtraction.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl>
<dl class="section user"><dt></dt><dd>If <ul>
<li>res is the return value, then: </li>
<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li>
<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0]</div>
<div class="line">res[31:16] = val1[31:16] - val2[31:16]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SSUB8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four 8-bit signed integer subtractions.<br/>
The GE bits in the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit operands of each subtraction. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit operands of each subtraction.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li>
<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li>
<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li>
<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on </dt><dd>the results of the operation.</dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 </li>
<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li>
<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li>
<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0] </div>
<div class="line">res[15:8] = val1[15:8] - val2[15:8]</div>
<div class="line">res[23:16] = val1[23:16] - val2[23:16]</div>
<div class="line">res[31:24] = val1[31:24] - val2[31:24]</div>
</div><!-- fragment --> </dd></dl>
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<td class="memname">uint32_t __SXTAB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>values added to the zero-extended to 16-bit values. </td></tr>
<tr><td class="paramname">val2</td><td>two 8-bit values to be extracted and zero-extended.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the addition of <em>val1</em> and <em>val2</em>, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + SignExtended(val2[7:0])</div>
<div class="line">res[31:16] = val1[31:16] + SignExtended(val2[23:16])</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __SXTB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val</td><td>two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the 8-bit values sign-extended to 16-bit values. <ul>
<li>sign-extended value of val[7:0] in the low halfword of the return value. </li>
<li>sign-extended value of val[23:16] in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = SignExtended(val[7:0]</div>
<div class="line">res[31:16] = SignExtended(val[23:16]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __UADD16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit unsigned integer additions.<br/>
The GE bits in the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit summands for each addition. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit summands for each addition.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the addition of the low halfwords in each operand, in the low halfword of the return value. </li>
<li>the addition of the high halfwords in each operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00 </li>
<li>if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0] </div>
<div class="line">res[31:16] = val1[31:16] + val2[31:16]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UADD8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit summands for each addition. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit summands for each addition.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved addition of the first bytes from each operand, in the first byte of the return value. </li>
<li>the halved addition of the second bytes from each operand, in the second byte of the return value. </li>
<li>the halved addition of the third bytes from each operand, in the third byte of the return value. </li>
<li>the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0 </li>
<li>if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0 </li>
<li>if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0 </li>
<li>if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] </div>
<div class="line">res[15:8] = val1[15:8] + val2[15:8]</div>
<div class="line">res[23:16] = val1[23:16] + val2[23:16]</div>
<div class="line">res[31:24] = val1[31:24] + val2[31:24]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UASX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.<br/>
The GE bits in the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl>
<dl class="section user"><dt>If <em>res</em> is the return value, then:</dt><dd><ul>
<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li>
<li>if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[31:16]</div>
<div class="line">res[31:16] = val1[31:16] + val2[15:0] </div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UHADD16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two unsigned 16-bit integer additions, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved addition of the low halfwords in each operand, in the low halfword of the return value. </li>
<li>the halved addition of the high halfwords in each operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0] >> 1</div>
<div class="line">res[31:16] = val1[31:16] + val2[31:16] >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UHADD8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four unsigned 8-bit integer additions, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved addition of the first bytes in each operand, in the first byte of the return value. </li>
<li>the halved addition of the second bytes in each operand, in the second byte of the return value. </li>
<li>the halved addition of the third bytes in each operand, in the third byte of the return value. </li>
<li>the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] >> 1</div>
<div class="line">res[15:8] = val1[15:8] + val2[15:8] >> 1</div>
<div class="line">res[23:16] = val1[23:16] + val2[23:16] >> 1</div>
<div class="line">res[31:24] = val1[31:24] + val2[31:24] >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UHASX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved subtraction of the high halfword in the second operand from the low halfword in the first operand. </li>
<li>the halved addition of the high halfword in the first operand and the low halfword in the second operand.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = (val1[15:0] - val2[31:16]) >> 1</div>
<div class="line">res[31:16] = (val1[31:16] + val2[15:0] ) >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UHSAX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = (val1[15:0] + val2[31:16]) >> 1</div>
<div class="line">res[31:16] = (val1[31:16] - val2[15:0] ) >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UHSUB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0] >> 1</div>
<div class="line">res[31:16] = val1[31:16] - val2[31:16] >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UHSUB8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li>
<li>the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li>
<li>the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li>
<li>the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0] >> 1</div>
<div class="line">res[15:8] = val1[15:8] - val2[15:8] >> 1</div>
<div class="line">res[23:16] = val1[23:16] - val2[23:16] >> 1</div>
<div class="line">res[31:24] = val1[31:24] - val2[31:24] >> 1</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UQADD16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value. </li>
<li>the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0] </div>
<div class="line">res[31:16] = val1[31:16] + val2[31:16]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UQADD8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the halved addition of the first bytes in each operand, in the first byte of the return value. </li>
<li>the halved addition of the second bytes in each operand, in the second byte of the return value. </li>
<li>the halved addition of the third bytes in each operand, in the third byte of the return value. </li>
<li>the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The results are saturated to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] </div>
<div class="line">res[15:8] = val1[15:8] + val2[15:8]</div>
<div class="line">res[23:16] = val1[23:16] + val2[23:16]</div>
<div class="line">res[31:24] = val1[31:24] + val2[31:24]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
<a class="anchor" id="ga5eff3ae5eabcd73f3049996ca391becb"></a>
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<td class="memname">uint32_t __UQASX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[31:16]</div>
<div class="line">res[31:16] = val1[31:16] + val2[15:0] </div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __UQSAX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li>
<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[31:16]</div>
<div class="line">res[31:16] = val1[31:16] - val2[15:0] </div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UQSUB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit operands for each subtraction. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit operands for each subtraction.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0] </div>
<div class="line">res[31:16] = val1[31:16] - val2[31:16] </div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UQSUB8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li>
<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li>
<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li>
<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The results are saturated to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0]</div>
<div class="line">res[15:8] = val1[15:8] - val2[15:8]</div>
<div class="line">res[23:16] = val1[23:16] - val2[23:16]</div>
<div class="line">res[31:24] = val1[31:24] - val2[31:24]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __USAD8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit operands for the subtractions. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit operands for the subtractions.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the first byte in the second operand from the first byte in the first operand. </li>
<li>the subtraction of the second byte in the second operand from the second byte in the first operand. </li>
<li>the subtraction of the third byte in the second operand from the third byte in the first operand. </li>
<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand. </li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>The sum is returned as a single unsigned integer.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">absdiff1 = val1[7:0] - val2[7:0]</div>
<div class="line">absdiff2 = val1[15:8] - val2[15:8]</div>
<div class="line">absdiff3 = val1[23:16] - val2[23:16]</div>
<div class="line">absdiff4 = val1[31:24] - val2[31:24]</div>
<div class="line">res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __USADA8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val3</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit operands for the subtractions. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit operands for the subtractions. </td></tr>
<tr><td class="paramname">val3</td><td>accumulation value.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the sum of the absolute differences of the following bytes, added to the accumulation value: <ul>
<li>the subtraction of the first byte in the second operand from the first byte in the first operand. </li>
<li>the subtraction of the second byte in the second operand from the second byte in the first operand. </li>
<li>the subtraction of the third byte in the second operand from the third byte in the first operand. </li>
<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">absdiff1 = val1[7:0] - val2[7:0]</div>
<div class="line">absdiff2 = val1[15:8] - val2[15:8]</div>
<div class="line">absdiff3 = val1[23:16] - val2[23:16]</div>
<div class="line">absdiff4 = val1[31:24] - val2[31:24]</div>
<div class="line">sum = absdiff1 + absdiff2 + absdiff3 + absdiff4</div>
<div class="line">res[31:0] = sum[31:0] + val3[31:0]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __USAT16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">const uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to saturate two signed 16-bit values to a selected unsigned range.<br/>
The Q bit is set if either operation saturates.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>two 16-bit values that are to be saturated. </td></tr>
<tr><td class="paramname">val2</td><td>bit position for saturation, and must be an integral constant expression in the range 0 to 15.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the saturation of the two signed 16-bit values, as non-negative values. <ul>
<li>the saturation of the low halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the low halfword of the return value. </li>
<li>the saturation of the high halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">Saturate halfwords in val1 to the <span class="keywordtype">unsigned</span> range specified by the bit position in val2</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __USAX </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.<br/>
The GE bits in the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr>
<tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li>
<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00 </li>
<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[31:16]</div>
<div class="line">res[31:16] = val1[31:16] - val2[15:0] </div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __USUB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform two 16-bit unsigned integer subtractions.<br/>
The GE bits in the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li>
<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li>
<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0] </div>
<div class="line">res[31:16] = val1[31:16] - val2[31:16] </div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __USUB8 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr>
<tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li>
<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li>
<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li>
<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl>
<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul>
<li>if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 </li>
<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li>
<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li>
<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0]</div>
<div class="line">res[15:8] = val1[15:8] - val2[15:8]</div>
<div class="line">res[23:16] = val1[23:16] - val2[23:16]</div>
<div class="line">res[31:24] = val1[31:24] - val2[31:24]</div>
</div><!-- fragment --> </dd></dl>
</div>
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<td class="memname">uint32_t __UXTAB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val2</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val1</td><td>value added to the zero-extended to 16-bit values. </td></tr>
<tr><td class="paramname">val2</td><td>two 8-bit values to be extracted and zero-extended.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the 8-bit values in <em>val2</em>, zero-extended to 16-bit values and added to <em>val1</em>.</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0]</div>
<div class="line">res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]</div>
</div><!-- fragment --> </dd></dl>
</div>
</div>
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<td class="memname">uint32_t __UXTB16 </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>val</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">val</td><td>two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the 8-bit values zero-extended to 16-bit values. <ul>
<li>zero-extended value of val[7:0] in the low halfword of the return value. </li>
<li>zero-extended value of val[23:16] in the high halfword of the return value.</li>
</ul>
</dd></dl>
<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = ZeroExtended(val[7:0] )</div>
<div class="line">res[31:16] = ZeroExtended(val[23:16])</div>
</div><!-- fragment --> </dd></dl>
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<p>Functions that relate to the Memory Protection Unit.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Setup information of a single MPU Region. <a href="structARM__MPU__Region__t.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gab4bfac6284dc050dc6fa6aeb8e954c2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gab4bfac6284dc050dc6fa6aeb8e954c2c">ARM_MPU_ATTR_DEVICE</a>   ( 0U )</td></tr>
<tr class="memdesc:gab4bfac6284dc050dc6fa6aeb8e954c2c"><td class="mdescLeft"> </td><td class="mdescRight">Attribute for device memory (outer only) <a href="#gab4bfac6284dc050dc6fa6aeb8e954c2c">More...</a><br/></td></tr>
<tr class="separator:gab4bfac6284dc050dc6fa6aeb8e954c2c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga03266f9660485693eb1baec6ba255ab2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga03266f9660485693eb1baec6ba255ab2">ARM_MPU_ATTR_NON_CACHEABLE</a>   ( 4U )</td></tr>
<tr class="memdesc:ga03266f9660485693eb1baec6ba255ab2"><td class="mdescLeft"> </td><td class="mdescRight">Attribute for non-cacheable, normal memory. <a href="#ga03266f9660485693eb1baec6ba255ab2">More...</a><br/></td></tr>
<tr class="separator:ga03266f9660485693eb1baec6ba255ab2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac2f1c567950e3785d75773362b525390"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">ARM_MPU_ATTR_MEMORY_</a>(NT, WB, RA, WA)</td></tr>
<tr class="memdesc:gac2f1c567950e3785d75773362b525390"><td class="mdescLeft"> </td><td class="mdescRight">Attribute for normal memory (outer and inner) <a href="#gac2f1c567950e3785d75773362b525390">More...</a><br/></td></tr>
<tr class="separator:gac2f1c567950e3785d75773362b525390"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabfa9ae279357044cf5b74e77af22a686"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gabfa9ae279357044cf5b74e77af22a686">ARM_MPU_ATTR_DEVICE_nGnRnE</a></td></tr>
<tr class="memdesc:gabfa9ae279357044cf5b74e77af22a686"><td class="mdescLeft"> </td><td class="mdescRight">Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement. <a href="#gabfa9ae279357044cf5b74e77af22a686">More...</a><br/></td></tr>
<tr class="separator:gabfa9ae279357044cf5b74e77af22a686"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6e08ae44fab85e03fea96ae6a5fcdfb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga6e08ae44fab85e03fea96ae6a5fcdfb0">ARM_MPU_ATTR_DEVICE_nGnRE</a></td></tr>
<tr class="memdesc:ga6e08ae44fab85e03fea96ae6a5fcdfb0"><td class="mdescLeft"> </td><td class="mdescRight">Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement. <a href="#ga6e08ae44fab85e03fea96ae6a5fcdfb0">More...</a><br/></td></tr>
<tr class="separator:ga6e08ae44fab85e03fea96ae6a5fcdfb0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadcc9977aabb4dc7177d30cbbac1b53d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gadcc9977aabb4dc7177d30cbbac1b53d1">ARM_MPU_ATTR_DEVICE_nGRE</a></td></tr>
<tr class="memdesc:gadcc9977aabb4dc7177d30cbbac1b53d1"><td class="mdescLeft"> </td><td class="mdescRight">Device memory type non Gathering, Re-ordering, Early Write Acknowledgement. <a href="#gadcc9977aabb4dc7177d30cbbac1b53d1">More...</a><br/></td></tr>
<tr class="separator:gadcc9977aabb4dc7177d30cbbac1b53d1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga496bcd6a2bbd038d8935049fec9d0fda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga496bcd6a2bbd038d8935049fec9d0fda">ARM_MPU_ATTR_DEVICE_GRE</a></td></tr>
<tr class="memdesc:ga496bcd6a2bbd038d8935049fec9d0fda"><td class="mdescLeft"> </td><td class="mdescRight">Device memory type Gathering, Re-ordering, Early Write Acknowledgement. <a href="#ga496bcd6a2bbd038d8935049fec9d0fda">More...</a><br/></td></tr>
<tr class="separator:ga496bcd6a2bbd038d8935049fec9d0fda"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2c465cc9429b8233bcb9cd7cbef0e54c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga2c465cc9429b8233bcb9cd7cbef0e54c">ARM_MPU_ATTR</a>(O, I)</td></tr>
<tr class="memdesc:ga2c465cc9429b8233bcb9cd7cbef0e54c"><td class="mdescLeft"> </td><td class="mdescRight">Memory Attribute. <a href="#ga2c465cc9429b8233bcb9cd7cbef0e54c">More...</a><br/></td></tr>
<tr class="separator:ga2c465cc9429b8233bcb9cd7cbef0e54c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3d0f688198289f72264f73cf72a742e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a></td></tr>
<tr class="memdesc:ga3d0f688198289f72264f73cf72a742e8"><td class="mdescLeft"> </td><td class="mdescRight">Normal memory non-shareable. <a href="#ga3d0f688198289f72264f73cf72a742e8">More...</a><br/></td></tr>
<tr class="separator:ga3d0f688198289f72264f73cf72a742e8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac4fddbdb9e1350bce6906de33c1fd500"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gac4fddbdb9e1350bce6906de33c1fd500">ARM_MPU_SH_OUTER</a></td></tr>
<tr class="memdesc:gac4fddbdb9e1350bce6906de33c1fd500"><td class="mdescLeft"> </td><td class="mdescRight">Normal memory outer shareable. <a href="#gac4fddbdb9e1350bce6906de33c1fd500">More...</a><br/></td></tr>
<tr class="separator:gac4fddbdb9e1350bce6906de33c1fd500"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga73c70127f24f34781ad463cbe51d8f6b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga73c70127f24f34781ad463cbe51d8f6b">ARM_MPU_SH_INNER</a></td></tr>
<tr class="memdesc:ga73c70127f24f34781ad463cbe51d8f6b"><td class="mdescLeft"> </td><td class="mdescRight">Normal memory inner shareable. <a href="#ga73c70127f24f34781ad463cbe51d8f6b">More...</a><br/></td></tr>
<tr class="separator:ga73c70127f24f34781ad463cbe51d8f6b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga81b2aa3fb55cdd5feadff02da10d391b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga81b2aa3fb55cdd5feadff02da10d391b">ARM_MPU_AP_</a>(RO, NP)</td></tr>
<tr class="memdesc:ga81b2aa3fb55cdd5feadff02da10d391b"><td class="mdescLeft"> </td><td class="mdescRight">Memory access permissions. <a href="#ga81b2aa3fb55cdd5feadff02da10d391b">More...</a><br/></td></tr>
<tr class="separator:ga81b2aa3fb55cdd5feadff02da10d391b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafe39c2f98058bcac7e7e0501e64e7a9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gafe39c2f98058bcac7e7e0501e64e7a9d">ARM_MPU_RBAR</a>(BASE, SH, RO, NP, XN)</td></tr>
<tr class="memdesc:gafe39c2f98058bcac7e7e0501e64e7a9d"><td class="mdescLeft"> </td><td class="mdescRight">Region Base Address Register value. <a href="#gafe39c2f98058bcac7e7e0501e64e7a9d">More...</a><br/></td></tr>
<tr class="separator:gafe39c2f98058bcac7e7e0501e64e7a9d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaeaaa071276ba7956944e6c3dc05d677e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(LIMIT, IDX)</td></tr>
<tr class="memdesc:gaeaaa071276ba7956944e6c3dc05d677e"><td class="mdescLeft"> </td><td class="mdescRight">Region Limit Address Register value. <a href="#gaeaaa071276ba7956944e6c3dc05d677e">More...</a><br/></td></tr>
<tr class="separator:gaeaaa071276ba7956944e6c3dc05d677e"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga5a3f40314553baccdeea551f86d9a997"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga5a3f40314553baccdeea551f86d9a997">ARM_MPU_Enable</a> (uint32_t MPU_Control)</td></tr>
<tr class="separator:ga5a3f40314553baccdeea551f86d9a997"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga61814eba4652a0fdfb76bbe222086327"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga61814eba4652a0fdfb76bbe222086327">ARM_MPU_Disable</a> (void)</td></tr>
<tr class="separator:ga61814eba4652a0fdfb76bbe222086327"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5866c75d6deb9148a1e9af6337eec50a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga5866c75d6deb9148a1e9af6337eec50a">ARM_MPU_Enable_NS</a> (uint32_t MPU_Control)</td></tr>
<tr class="separator:ga5866c75d6deb9148a1e9af6337eec50a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga389f9b6049d176bc83f9964d3259b712"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga389f9b6049d176bc83f9964d3259b712">ARM_MPU_Disable_NS</a> (void)</td></tr>
<tr class="separator:ga389f9b6049d176bc83f9964d3259b712"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1799413f08a157d636a1491371c15ce2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga1799413f08a157d636a1491371c15ce2">ARM_MPU_SetMemAttrEx</a> (<a class="el" href="structMPU__Type.html">MPU_Type</a> *mpu, uint8_t idx, uint8_t attr)</td></tr>
<tr class="separator:ga1799413f08a157d636a1491371c15ce2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab5b3c0a53d19c09a5550f1d9071ae65c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gab5b3c0a53d19c09a5550f1d9071ae65c">ARM_MPU_SetMemAttr</a> (uint8_t idx, uint8_t attr)</td></tr>
<tr class="separator:gab5b3c0a53d19c09a5550f1d9071ae65c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5100a150a755902af2455a455a329ef9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga5100a150a755902af2455a455a329ef9">ARM_MPU_SetMemAttr_NS</a> (uint8_t idx, uint8_t attr)</td></tr>
<tr class="separator:ga5100a150a755902af2455a455a329ef9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga01fa1151c9ec0ba5de76f908c0999316"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga01fa1151c9ec0ba5de76f908c0999316">ARM_MPU_ClrRegionEx</a> (<a class="el" href="structMPU__Type.html">MPU_Type</a> *mpu, uint32_t rnr)</td></tr>
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<tr class="memitem:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c">ARM_MPU_ClrRegion</a> (uint32_t rnr)</td></tr>
<tr class="separator:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac526bc5bfcf048ce57a44c0c0cdadbe4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gac526bc5bfcf048ce57a44c0c0cdadbe4">ARM_MPU_ClrRegion_NS</a> (uint32_t rnr)</td></tr>
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<tr class="memitem:ga3d50ba8546252bea959e45c8fdf16993"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga3d50ba8546252bea959e45c8fdf16993">ARM_MPU_SetRegionEx</a> (<a class="el" href="structMPU__Type.html">MPU_Type</a> *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)</td></tr>
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<tr class="memitem:ga6d7f220015c070c0e469948c1775ee3d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga6d7f220015c070c0e469948c1775ee3d">ARM_MPU_SetRegion</a> (uint32_t rnr, uint32_t rbar, uint32_t rlar)</td></tr>
<tr class="separator:ga6d7f220015c070c0e469948c1775ee3d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7566931ca9bb9f22d213a67ec5f8c745"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga7566931ca9bb9f22d213a67ec5f8c745">ARM_MPU_SetRegion_NS</a> (uint32_t rnr, uint32_t rbar, uint32_t rlar)</td></tr>
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<tr class="memitem:gac1a949403bf84eecaf407003fb553ae7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gac1a949403bf84eecaf407003fb553ae7">ARM_MPU_OrderedMemcpy</a> (volatile uint32_t *dst, const uint32_t *<a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a> src, uint32_t len)</td></tr>
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<tr class="memitem:gab6094419f2abd678f1f3b121cd115049"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gab6094419f2abd678f1f3b121cd115049">ARM_MPU_LoadEx</a> (<a class="el" href="structMPU__Type.html">MPU_Type</a> *mpu, uint32_t rnr, <a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const *table, uint32_t cnt)</td></tr>
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<tr class="memitem:gaca76614e3091c7324aa9d60e634621bf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#gaca76614e3091c7324aa9d60e634621bf">ARM_MPU_Load</a> (uint32_t rnr, <a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const *table, uint32_t cnt)</td></tr>
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<tr class="memitem:ga7f8c6e09be98067d613e4df1832c543d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu8__functions.html#ga7f8c6e09be98067d613e4df1832c543d">ARM_MPU_Load_NS</a> (uint32_t rnr, <a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const *table, uint32_t cnt)</td></tr>
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</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.</p>
<p>The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><span class="keywordtype">void</span> main() </div>
<div class="line">{</div>
<div class="line"> <span class="comment">// Set Region 0 using Attr 0</span></div>
<div class="line"> <a class="code" href="group__mpu8__functions.html#gab5b3c0a53d19c09a5550f1d9071ae65c">ARM_MPU_SetMemAttr</a>(0UL, <a class="code" href="group__mpu8__functions.html#ga2c465cc9429b8233bcb9cd7cbef0e54c">ARM_MPU_ATTR</a>( <span class="comment">/* Normal memory */</span></div>
<div class="line"> <a class="code" href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">ARM_MPU_ATTR_MEMORY_</a>(0UL, 1UL, 1UL, 1UL), <span class="comment">/* Outer Write-Back transient with read and write allocate */</span></div>
<div class="line"> <a class="code" href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">ARM_MPU_ATTR_MEMORY_</a>(0UL, 0UL, 1UL, 1UL) <span class="comment">/* Inner Write-Through transient with read and write allocate */</span></div>
<div class="line"> ));</div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>(0UL,</div>
<div class="line"> <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x08000000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 1UL), <span class="comment">/* Non-shareable, read/write, non-privileged, execute-never */</span></div>
<div class="line"> <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x080FFFFFUL, 0UL) <span class="comment">/* 1MB memory block using Attr 0 */</span></div>
<div class="line"> );</div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a>(0);</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Execute application code that is access protected by the MPU</span></div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a>();</div>
<div class="line">}</div>
</div><!-- fragment --> <h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga81b2aa3fb55cdd5feadff02da10d391b"></a>
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<td class="memname">#define ARM_MPU_AP_</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">RO, </td>
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<td class="paramkey"></td>
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<td class="paramtype"> </td>
<td class="paramname">NP </td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">RO</td><td>Read-Only: Set to 1 for read-only memory. </td></tr>
<tr><td class="paramname">NP</td><td>Non-Privileged: Set to 1 for non-privileged memory. </td></tr>
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<td class="memname">#define ARM_MPU_ATTR</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">O, </td>
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<td></td>
<td class="paramtype"> </td>
<td class="paramname">I </td>
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<td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">O</td><td>Outer memory attributes </td></tr>
<tr><td class="paramname">I</td><td>O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes </td></tr>
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<td class="memname">#define ARM_MPU_ATTR_DEVICE   ( 0U )</td>
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<td class="memname">#define ARM_MPU_ATTR_DEVICE_GRE</td>
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<td class="memname">#define ARM_MPU_ATTR_DEVICE_nGnRE</td>
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<td class="memname">#define ARM_MPU_ATTR_DEVICE_nGnRnE</td>
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<td class="memname">#define ARM_MPU_ATTR_DEVICE_nGRE</td>
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<td class="memname">#define ARM_MPU_ATTR_MEMORY_</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">NT, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">WB, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">RA, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">WA </td>
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<td></td>
<td>)</td>
<td></td><td></td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">NT</td><td>Non-Transient: Set to 1 for non-transient data. </td></tr>
<tr><td class="paramname">WB</td><td>Write-Back: Set to 1 to use write-back update policy. </td></tr>
<tr><td class="paramname">RA</td><td>Read Allocation: Set to 1 to use cache allocation on read miss. </td></tr>
<tr><td class="paramname">WA</td><td>Write Allocation: Set to 1 to use cache allocation on write miss. </td></tr>
</table>
</dd>
</dl>
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<td class="memname">#define ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )</td>
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<td class="memname">#define ARM_MPU_RBAR</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">BASE, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">SH, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">RO, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">NP, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">XN </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">BASE</td><td>The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. </td></tr>
<tr><td class="paramname">SH</td><td>Defines the Shareability domain for this memory region. </td></tr>
<tr><td class="paramname">RO</td><td>Read-Only: Set to 1 for a read-only memory region. </td></tr>
<tr><td class="paramname">NP</td><td>Non-Privileged: Set to 1 for a non-privileged memory region. </td></tr>
<tr><td class="paramname">XN</td><td>eXecute Never: Set to 1 for a non-executable memory region. </td></tr>
</table>
</dd>
</dl>
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<td class="memname">#define ARM_MPU_RLAR</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">LIMIT, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">IDX </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">LIMIT</td><td>The limit address bits [31:5] for this memory region. The value is one extended. </td></tr>
<tr><td class="paramname">IDX</td><td>The attribute index to be associated with this memory region. </td></tr>
</table>
</dd>
</dl>
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<td class="memname">#define ARM_MPU_SH_INNER</td>
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<td class="memname">#define ARM_MPU_SH_NON</td>
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<td class="memname">#define ARM_MPU_SH_OUTER</td>
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<h2 class="groupheader">Function Documentation</h2>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegion </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Clear and disable the given MPU region. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr>
</table>
</dd>
</dl>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegion_NS </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Clear and disable the given Non-secure MPU region. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr>
</table>
</dd>
</dl>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegionEx </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structMPU__Type.html">MPU_Type</a> * </td>
<td class="paramname"><em>mpu</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
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<p>Clear and disable the given MPU region of the given MPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">mpu</td><td>Pointer to MPU to be used. </td></tr>
<tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr>
</table>
</dd>
</dl>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Disable </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
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<p>Disable the MPU. </p>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Disable_NS </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
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<p>Disable the Non-secure MPU. </p>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Enable </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>MPU_Control</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Enable the MPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">MPU_Control</td><td>Default access permissions for unconfigured regions. </td></tr>
</table>
</dd>
</dl>
</div>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> ARM_MPU_Enable_NS </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>MPU_Control</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Enable the Non-secure MPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">MPU_Control</td><td>Default access permissions for unconfigured regions. </td></tr>
</table>
</dd>
</dl>
</div>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Load </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const * </td>
<td class="paramname"><em>table</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>cnt</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Load the given number of MPU regions from a table. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rnr</td><td>First region number to be configured. </td></tr>
<tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr>
<tr><td class="paramname">cnt</td><td>Amount of regions to be configured.</td></tr>
</table>
</dd>
</dl>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><span class="keyword">const</span> <a class="code" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> mpuTable[1][4] = {</div>
<div class="line"> {</div>
<div class="line"> <span class="comment">// BASE SH RO NP XN LIMIT ATTR </span></div>
<div class="line"> { .<a class="code" href="structARM__MPU__Region__t.html#afe7a7721aa08988d915670efa432cdd2">RBAR</a> = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x08000000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 0UL), .RLAR = <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x080FFFFFUL, 0UL) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x20000000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 1UL), .RLAR = <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x20007FFFUL, 0UL) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x40020000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 1UL), .RLAR = <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x40021FFFUL, 1UL) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0x40022000UL, <a class="code" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">ARM_MPU_SH_NON</a>, 0UL, 1UL, 1UL), .RLAR = <a class="code" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">ARM_MPU_RLAR</a>(0x40022FFFUL, 1UL) }</div>
<div class="line"> }</div>
<div class="line">};</div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> UpdateMpu(uint32_t idx)</div>
<div class="line">{</div>
<div class="line"> <a class="code" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a>(0, mpuTable[idx], 4);</div>
<div class="line">}</div>
</div><!-- fragment -->
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Load_NS </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const * </td>
<td class="paramname"><em>table</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>cnt</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Load the given number of MPU regions from a table to the Non-secure MPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rnr</td><td>First region number to be configured. </td></tr>
<tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr>
<tr><td class="paramname">cnt</td><td>Amount of regions to be configured. </td></tr>
</table>
</dd>
</dl>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_LoadEx </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structMPU__Type.html">MPU_Type</a> * </td>
<td class="paramname"><em>mpu</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> const * </td>
<td class="paramname"><em>table</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>cnt</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Load the given number of MPU regions from a table to the given MPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">mpu</td><td>Pointer to the MPU registers to be used. </td></tr>
<tr><td class="paramname">rnr</td><td>First region number to be configured. </td></tr>
<tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr>
<tr><td class="paramname">cnt</td><td>Amount of regions to be configured. </td></tr>
</table>
</dd>
</dl>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_OrderedMemcpy </td>
<td>(</td>
<td class="paramtype">volatile uint32_t * </td>
<td class="paramname"><em>dst</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">const uint32_t *<a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a> </td>
<td class="paramname"><em>src</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>len</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Memcopy with strictly ordered memory access, e.g. for register targets. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">dst</td><td>Destination data is copied to. </td></tr>
<tr><td class="paramname">src</td><td>Source data is copied from. </td></tr>
<tr><td class="paramname">len</td><td>Amount of data words to be copied. </td></tr>
</table>
</dd>
</dl>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetMemAttr </td>
<td>(</td>
<td class="paramtype">uint8_t </td>
<td class="paramname"><em>idx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint8_t </td>
<td class="paramname"><em>attr</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Set the memory attribute encoding. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">idx</td><td>The attribute index to be set [0-7] </td></tr>
<tr><td class="paramname">attr</td><td>The attribute value to be set. </td></tr>
</table>
</dd>
</dl>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetMemAttr_NS </td>
<td>(</td>
<td class="paramtype">uint8_t </td>
<td class="paramname"><em>idx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint8_t </td>
<td class="paramname"><em>attr</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Set the memory attribute encoding to the Non-secure MPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">idx</td><td>The attribute index to be set [0-7] </td></tr>
<tr><td class="paramname">attr</td><td>The attribute value to be set. </td></tr>
</table>
</dd>
</dl>
</div>
</div>
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<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetMemAttrEx </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structMPU__Type.html">MPU_Type</a> * </td>
<td class="paramname"><em>mpu</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint8_t </td>
<td class="paramname"><em>idx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint8_t </td>
<td class="paramname"><em>attr</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Set the memory attribute encoding to the given MPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">mpu</td><td>Pointer to the MPU to be configured. </td></tr>
<tr><td class="paramname">idx</td><td>The attribute index to be set [0-7] </td></tr>
<tr><td class="paramname">attr</td><td>The attribute value to be set. </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="ga6d7f220015c070c0e469948c1775ee3d"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegion </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rbar</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rlar</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Configure the given MPU region. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr>
<tr><td class="paramname">rbar</td><td>Value for RBAR register. </td></tr>
<tr><td class="paramname">rlar</td><td>Value for RLAR register. </td></tr>
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</dl>
</div>
</div>
<a class="anchor" id="ga7566931ca9bb9f22d213a67ec5f8c745"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegion_NS </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rbar</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rlar</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Configure the given Non-secure MPU region. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr>
<tr><td class="paramname">rbar</td><td>Value for RBAR register. </td></tr>
<tr><td class="paramname">rlar</td><td>Value for RLAR register. </td></tr>
</table>
</dd>
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</div>
<a class="anchor" id="ga3d50ba8546252bea959e45c8fdf16993"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegionEx </td>
<td>(</td>
<td class="paramtype"><a class="el" href="structMPU__Type.html">MPU_Type</a> * </td>
<td class="paramname"><em>mpu</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rbar</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rlar</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Configure the given MPU region of the given MPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">mpu</td><td>Pointer to MPU to be used. </td></tr>
<tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr>
<tr><td class="paramname">rbar</td><td>Value for RBAR register. </td></tr>
<tr><td class="paramname">rlar</td><td>Value for RLAR register. </td></tr>
</table>
</dd>
</dl>
</div>
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<a href="#define-members">Macros</a> </div>
<div class="headertitle">
<div class="title">Define values<div class="ingroups"><a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a></div></div> </div>
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<p>Define values for MPU region setup.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gadb0a92c0928c113120567e85ff1ba05c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a></td></tr>
<tr class="memdesc:gadb0a92c0928c113120567e85ff1ba05c"><td class="mdescLeft"> </td><td class="mdescRight">Size values of a MPU region (in RASR field) <a href="#gadb0a92c0928c113120567e85ff1ba05c">More...</a><br/></td></tr>
<tr class="separator:gadb0a92c0928c113120567e85ff1ba05c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc4788126d7798469cb862a08d3050cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a></td></tr>
<tr class="memdesc:gabc4788126d7798469cb862a08d3050cc"><td class="mdescLeft"> </td><td class="mdescRight">Values for MPU region access permissions (in RASR field) <a href="#gabc4788126d7798469cb862a08d3050cc">More...</a><br/></td></tr>
<tr class="separator:gabc4788126d7798469cb862a08d3050cc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga71d41084e984be70a23cb640fd89d1e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a></td></tr>
<tr class="memdesc:ga71d41084e984be70a23cb640fd89d1e2"><td class="mdescLeft"> </td><td class="mdescRight">Values for MPU region access attributes (in RASR field) <a href="#ga71d41084e984be70a23cb640fd89d1e2">More...</a><br/></td></tr>
<tr class="separator:ga71d41084e984be70a23cb640fd89d1e2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab23596306119e7831847bd9683de3934"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a></td></tr>
<tr class="memdesc:gab23596306119e7831847bd9683de3934"><td class="mdescLeft"> </td><td class="mdescRight">Cache policy values for MPU region access attributes (in RASR field) <a href="#gab23596306119e7831847bd9683de3934">More...</a><br/></td></tr>
<tr class="separator:gab23596306119e7831847bd9683de3934"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The following define values are used with <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> to setup the <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value field in the MPU region.</p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structARM__MPU__Region__t.html" title="Setup information of a single MPU Region. ">ARM_MPU_Region_t</a>, <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>, <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>. </dd></dl>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga71d41084e984be70a23cb640fd89d1e2"></a>
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<td class="memname">#define ARM_MPU_ACCESS_xxx</td>
</tr>
</table>
</div><div class="memdoc">
<p>The following define values are used to compose the access attributes for an MPU region: </p>
<table class="doxtable">
<tr>
<th align="left">#define </th><th align="left">TEX </th><th align="left">Shareable </th><th align="left">Cacheable </th><th align="left">Bufferable </th><th align="left">Description </th></tr>
<tr>
<td align="left">ARM_MPU_ACCESS_ORDERED </td><td align="left">000b </td><td align="left">1 </td><td align="left">0 </td><td align="left">0 </td><td align="left">Strongly ordered memory </td></tr>
<tr>
<td align="left">ARM_MPU_ACCESS_DEVICE(S) </td><td align="left">0s0b </td><td align="left">S </td><td align="left">0 </td><td align="left">S </td><td align="left">Memory mapped peripheral device, shared (S=1) or non-shared (S=0) </td></tr>
<tr>
<td align="left">ARM_MPU_ACCESS_NORMAL(O,I,S) </td><td align="left">1BBb </td><td align="left">S </td><td align="left">A </td><td align="left">A </td><td align="left">Normal memory, with outer/inner cache policy (O/I=<a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a>, shared (S=1) or non-share (S=0) </td></tr>
</table>
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</div>
<a class="anchor" id="gabc4788126d7798469cb862a08d3050cc"></a>
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<tr>
<td class="memname">#define ARM_MPU_AP_xxx</td>
</tr>
</table>
</div><div class="memdoc">
<p>The following define values are used to compose the access permission for an MPU region: </p>
<table class="doxtable">
<tr>
<th align="left">#define </th><th align="left">Value </th><th align="left">Access permissions </th></tr>
<tr>
<td align="left">ARM_MPU_AP_NONE </td><td align="left">0x0U </td><td align="left">None: any access generates a permission fault. </td></tr>
<tr>
<td align="left">ARM_MPU_AP_PRIV </td><td align="left">0x1U </td><td align="left">Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault. </td></tr>
<tr>
<td align="left">ARM_MPU_AP_URO </td><td align="left">0x2U </td><td align="left">Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault. </td></tr>
<tr>
<td align="left">ARM_MPU_AP_FULL </td><td align="left">0x3U </td><td align="left">Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated. </td></tr>
<tr>
<td align="left">ARM_MPU_AP_PRO </td><td align="left">0x5U </td><td align="left">Privileged Read-only: any unprivileged access or privileged write generates a permission fault. </td></tr>
<tr>
<td align="left">ARM_MPU_AP_RO </td><td align="left">0x6U </td><td align="left">Privileged and Unprivileged Read-only: any write generates a permission fault. </td></tr>
</table>
</div>
</div>
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<td class="memname">#define ARM_MPU_CACHEP_xxx</td>
</tr>
</table>
</div><div class="memdoc">
<p>The following define values are used to compose the cacheability flags within the access attributes for an MPU region: </p>
<table class="doxtable">
<tr>
<th align="left">#define </th><th align="left">Value </th><th align="left">Cacheability policy </th></tr>
<tr>
<td align="left">ARM_MPU_CACHEP_NOCACHE </td><td align="left">00b </td><td align="left">Non-cacheable </td></tr>
<tr>
<td align="left">ARM_MPU_CACHEP_WB_WRA </td><td align="left">01b </td><td align="left">Write-back, write and read allocate </td></tr>
<tr>
<td align="left">ARM_MPU_CACHEP_WT_NWA </td><td align="left">10b </td><td align="left">Write-through, no write allocate </td></tr>
<tr>
<td align="left">ARM_MPU_CACHEP_WB_NWA </td><td align="left">11b </td><td align="left">Write-back, no write allocate </td></tr>
</table>
</div>
</div>
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<td class="memname">#define ARM_MPU_REGION_SIZE_xxx</td>
</tr>
</table>
</div><div class="memdoc">
<p>The following define values are used to compose the size information for an MPU region:</p>
<table class="doxtable">
<tr>
<th align="left">#define </th><th align="left">Value </th><th align="left">Description </th></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_32B </td><td align="left">0x04U </td><td align="left">Region size 32 Bytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_64B </td><td align="left">0x05U </td><td align="left">Region size 64 Bytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_128B </td><td align="left">0x06U </td><td align="left">Region size 128 Bytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_256B </td><td align="left">0x07U </td><td align="left">Region size 256 Bytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_512B </td><td align="left">0x08U </td><td align="left">Region size 512 Bytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_1KB </td><td align="left">0x09U </td><td align="left">Region size 1 KByte </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_2KB </td><td align="left">0x0AU </td><td align="left">Region size 2 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_4KB </td><td align="left">0x0BU </td><td align="left">Region size 4 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_8KB </td><td align="left">0x0CU </td><td align="left">Region size 8 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_16KB </td><td align="left">0x0DU </td><td align="left">Region size 16 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_32KB </td><td align="left">0x0EU </td><td align="left">Region size 32 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_64KB </td><td align="left">0x0FU </td><td align="left">Region size 64 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_128KB </td><td align="left">0x10U </td><td align="left">Region size 128 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_256KB </td><td align="left">0x11U </td><td align="left">Region size 256 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_512KB </td><td align="left">0x12U </td><td align="left">Region size 512 KBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_1MB </td><td align="left">0x13U </td><td align="left">Region size 1 MByte </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_2MB </td><td align="left">0x14U </td><td align="left">Region size 2 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_4MB </td><td align="left">0x15U </td><td align="left">Region size 4 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_8MB </td><td align="left">0x16U </td><td align="left">Region size 8 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_16MB </td><td align="left">0x17U </td><td align="left">Region size 16 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_32MB </td><td align="left">0x18U </td><td align="left">Region size 32 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_64MB </td><td align="left">0x19U </td><td align="left">Region size 64 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_128MB </td><td align="left">0x1AU </td><td align="left">Region size 128 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_256MB </td><td align="left">0x1BU </td><td align="left">Region size 256 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_512MB </td><td align="left">0x1CU </td><td align="left">Region size 512 MBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_1GB </td><td align="left">0x1DU </td><td align="left">Region size 1 GByte </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_2GB </td><td align="left">0x1EU </td><td align="left">Region size 2 GBytes </td></tr>
<tr>
<td align="left">ARM_MPU_REGION_SIZE_4GB </td><td align="left">0x1FU </td><td align="left">Region size 4 GBytes </td></tr>
</table>
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<div class="title">MPU Functions for Armv6-M/v7-M</div> </div>
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<p>Functions that relate to the Memory Protection Unit.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
Content</h2></td></tr>
<tr class="memitem:group__mpu__defines"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html">Define values</a></td></tr>
<tr class="memdesc:group__mpu__defines"><td class="mdescLeft"> </td><td class="mdescRight">Define values for MPU region setup. <br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html">MPU_Type</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure type to access the Memory Protection Unit (MPU). <a href="structMPU__Type.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Setup information of a single MPU Region. <a href="structARM__MPU__Region__t.html#details">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga3fead12dc24a6d00ad53f55a042486ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(Region, BaseAddress)</td></tr>
<tr class="memdesc:ga3fead12dc24a6d00ad53f55a042486ca"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Base Address Register Value. <a href="#ga3fead12dc24a6d00ad53f55a042486ca">More...</a><br/></td></tr>
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<tr class="memitem:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)</td></tr>
<tr class="memdesc:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Attribute and Size Register Value. <a href="#ga96b93785c92e2dbcb3a2356c25bf2adc">More...</a><br/></td></tr>
<tr class="separator:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga332ed5f8969dd4df6b61c6ae32ec36dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc">ARM_MPU_RASR_EX</a>(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)</td></tr>
<tr class="memdesc:ga332ed5f8969dd4df6b61c6ae32ec36dc"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Attribute and Size Register Value. <a href="#ga332ed5f8969dd4df6b61c6ae32ec36dc">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a> (uint32_t MPU_CTRL)</td></tr>
<tr class="memdesc:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="mdescLeft"> </td><td class="mdescRight">Enable the memory protection unit (MPU) and. <a href="#ga31406efd492ec9a091a70ffa2d8a42fb">More...</a><br/></td></tr>
<tr class="separator:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7cbc0a4a066ed90e85c8176228235d57"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a> ()</td></tr>
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<tr class="memitem:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c">ARM_MPU_ClrRegion</a> (uint32_t rnr)</td></tr>
<tr class="separator:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga16931f9ad84d7289e8218e169ae6db5d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a> (uint32_t rbar, uint32_t rasr)</td></tr>
<tr class="separator:ga16931f9ad84d7289e8218e169ae6db5d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga042ba1a6a1a58795231459ac0410b809"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a> (uint32_t rnr, uint32_t rbar, uint32_t rasr)</td></tr>
<tr class="separator:ga042ba1a6a1a58795231459ac0410b809"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac1a949403bf84eecaf407003fb553ae7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#gac1a949403bf84eecaf407003fb553ae7">ARM_MPU_OrderedMemcpy</a> (volatile uint32_t *dst, const uint32_t *<a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a> src, uint32_t len)</td></tr>
<tr class="separator:gac1a949403bf84eecaf407003fb553ae7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafa27b26d5847fa8e465584e376b6078a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a> (MPU_Region_t const *table, uint32_t cnt)</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.</p>
<p>The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><span class="keywordtype">void</span> main() </div>
<div class="line">{</div>
<div class="line"> <span class="comment">// Set Region 0</span></div>
<div class="line"> <a class="code" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>(0UL, 0x08000000UL, MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB));</div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a>(0);</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Execute application code that is access protected by the MPU</span></div>
<div class="line"> </div>
<div class="line"> <a class="code" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a>();</div>
<div class="line">}</div>
</div><!-- fragment --> <h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define ARM_MPU_RASR</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">DisableExec, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">AccessPermission, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">TypeExtField, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">IsShareable, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">IsCacheable, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">IsBufferable, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">SubRegionDisable, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">Size </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
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<p>This macro is used to construct a valid <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value. The ENABLE bit of the RASR value is implicitly set to 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">DisableExec</td><td>Instruction access disable bit. 1 = disable instruction fetches. </td></tr>
<tr><td class="paramname">AccessPermission</td><td>Data access permission configures read/write access for User and Privileged mode. Possible values see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr>
<tr><td class="paramname">TypeExtField</td><td>Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. </td></tr>
<tr><td class="paramname">IsShareable</td><td>1 = region is shareable between multiple bus masters. </td></tr>
<tr><td class="paramname">IsCacheable</td><td>1 = region is cacheable (values may be kept in cache). </td></tr>
<tr><td class="paramname">IsBufferable</td><td>1 = region is bufferable (when using write-back caching). Cacheable but non-bufferable regions use write-through policy. </td></tr>
<tr><td class="paramname">SubRegionDisable</td><td>Sub-region disable field (8 bits). </td></tr>
<tr><td class="paramname">Size</td><td>Region size with values defined under <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a>. </td></tr>
</table>
</dd>
</dl>
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<td class="memname">#define ARM_MPU_RASR_EX</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">DisableExec, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">AccessPermission, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">AccessAttributes, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">SubRegionDisable, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">Size </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td>
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</div><div class="memdoc">
<p>This macro is used to construct a valid <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value. The ENABLE bit of the RASR value is implicitly set to 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">DisableExec</td><td>Instruction access disable bit, 1= disable instruction fetches. </td></tr>
<tr><td class="paramname">AccessPermission</td><td>Data access permission configures read/write access for User and Privileged mode. Possible values see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr>
<tr><td class="paramname">AccessAttributes</td><td>Memory access attribution, see <a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a>. </td></tr>
<tr><td class="paramname">SubRegionDisable</td><td>Sub-region disable field (8 bits). </td></tr>
<tr><td class="paramname">Size</td><td>Region size with values defined under <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a>. </td></tr>
</table>
</dd>
</dl>
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<td class="memname">#define ARM_MPU_RBAR</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">Region, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">BaseAddress </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td>
</tr>
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<p>This preprocessor function can be used to construct a valid <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> value. The VALID bit is implicitly set to 1.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">Region</td><td>The region to be configured, number 0 to 15. </td></tr>
<tr><td class="paramname">BaseAddress</td><td>The base address for the region. </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegion </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em></td><td>)</td>
<td></td>
</tr>
</table>
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<p>Clear and disable the given MPU region. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr>
</table>
</dd>
</dl>
</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Disable </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
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<p>Disable the MPU. </p>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Enable </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>MPU_CTRL</em></td><td>)</td>
<td></td>
</tr>
</table>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">MPU_CTRL</td><td>Additional control settings that configure MPU behaviour</td></tr>
</table>
</dd>
</dl>
<p>The function <a class="el" href="group__mpu8__functions.html#ga5a3f40314553baccdeea551f86d9a997">ARM_MPU_Enable</a> writes to the register <a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">MPU->CTRL</a> and sets bit ENABLE. The parameter <em>MPU_CTRL</em> provides additional bit values (see table below) that configure the MPU behaviour. For processors that implement an <b>MPU Fault Handler</b> the <a class="el" href="group__NVIC__gr.html">MemoryManagement_IRQn</a> exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.</p>
<p>The following table contains possible values for the parameter <em>MPU_CTRL</em> that set specific bits in register MPU->CTRL. </p>
<table class="doxtable">
<tr>
<th align="left">Bit </th><th align="left">MPU_CTRL value </th><th align="left">When applied </th><th align="left">When not applied </th></tr>
<tr>
<td align="left">1 </td><td align="left">MPU_CTRL_HFNMIENA_Msk </td><td align="left">Enable MPU during hard fault, NMI, and FAULTMASK handlers execution </td><td align="left">Disable MPU during hard fault, NMI, and FAULTMASK handler execution </td></tr>
<tr>
<td align="left">2 </td><td align="left">MPU_CTRL_PRIVDEFENA_Msk </td><td align="left">Enable default memory map as a background region for privileged access </td><td align="left">Use only MPU region settings </td></tr>
</table>
<p><b>Example:</b></p>
<div class="fragment"><div class="line"><span class="comment">// enable MPU with all region definitions. Exceptions are not protected by MPU.</span></div>
<div class="line"> MPU_Enable (0);</div>
<div class="line"> </div>
<div class="line"><span class="comment">// enable MPU with all region definitions and background regions for privileged access. Exceptions are protected by MPU.</span></div>
<div class="line"> MPU_Enable (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Load </td>
<td>(</td>
<td class="paramtype">MPU_Region_t const * </td>
<td class="paramname"><em>table</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>cnt</em> </td>
</tr>
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<td></td>
<td>)</td>
<td></td><td></td>
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<p>Load the given number of MPU regions from a table. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr>
<tr><td class="paramname">cnt</td><td>Number of regions to be configured.</td></tr>
</table>
</dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>only up to 16 regions can be handled as the function <a class="el" href="group__mpu8__functions.html#gaca76614e3091c7324aa9d60e634621bf">ARM_MPU_Load</a> uses the REGION field in <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU->RBAR</a>.</dd></dl>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><span class="keyword">const</span> <a class="code" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> mpuTable[3][4] = {</div>
<div class="line"> {</div>
<div class="line"> { .<a class="code" href="structARM__MPU__Region__t.html#afe7a7721aa08988d915670efa432cdd2">RBAR</a> = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0UL, 0x08000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(1UL, 0x20000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(2UL, 0x40020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(3UL, 0x40022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div>
<div class="line"> },</div>
<div class="line"> {</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(4UL, 0x08000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(5UL, 0x20000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(6UL, 0x40020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(7UL, 0x40022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div>
<div class="line"> },</div>
<div class="line"> {</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(4UL, 0x18000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(5UL, 0x30000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(6UL, 0x50020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div>
<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(7UL, 0x50022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div>
<div class="line"> }</div>
<div class="line">};</div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> UpdateMpu(uint32_t idx)</div>
<div class="line">{</div>
<div class="line"> <a class="code" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a>(mpuTable[idx], 4);</div>
<div class="line">}</div>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_OrderedMemcpy </td>
<td>(</td>
<td class="paramtype">volatile uint32_t * </td>
<td class="paramname"><em>dst</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">const uint32_t *<a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a> </td>
<td class="paramname"><em>src</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>len</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
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<p>Memcopy with strictly ordered memory access, e.g. for register targets. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">dst</td><td>Destination data is copied to. </td></tr>
<tr><td class="paramname">src</td><td>Source data is copied from. </td></tr>
<tr><td class="paramname">len</td><td>Amount of data words to be copied. </td></tr>
</table>
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<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegion </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rbar</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rasr</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Configure an MPU region.</p>
<p>The region number should be contained in the rbar value.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rbar</td><td>Value for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> register. </td></tr>
<tr><td class="paramname">rasr</td><td>Value for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> register. </td></tr>
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<a class="anchor" id="ga042ba1a6a1a58795231459ac0410b809"></a>
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<div class="memproto">
<table class="memname">
<tr>
<td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegionEx </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rnr</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rbar</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>rasr</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Configure the given MPU region. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr>
<tr><td class="paramname">rbar</td><td>Value for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> register. </td></tr>
<tr><td class="paramname">rasr</td><td>Value for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> register. </td></tr>
</table>
</dd>
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<a href="#func-members">Functions</a> </div>
<div class="headertitle">
<div class="title">NVIC Functions<div class="ingroups"><a class="el" href="group__trustzone__functions.html">TrustZone for Armv8-M/v8.1-M</a></div></div> </div>
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<div class="contents">
<p>Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga0d3b5db0685bd95cc8bd2f7ad0891d39"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga0d3b5db0685bd95cc8bd2f7ad0891d39">TZ_NVIC_SetPriorityGrouping_NS</a> (uint32_t PriorityGroup)</td></tr>
<tr class="memdesc:ga0d3b5db0685bd95cc8bd2f7ad0891d39"><td class="mdescLeft"> </td><td class="mdescRight">Set Priority Grouping (non-secure) <a href="#ga0d3b5db0685bd95cc8bd2f7ad0891d39">More...</a><br/></td></tr>
<tr class="separator:ga0d3b5db0685bd95cc8bd2f7ad0891d39"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf5f578628bc8b7154b29577f6f6a87fd"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gaf5f578628bc8b7154b29577f6f6a87fd">TZ_NVIC_GetPriorityGrouping_NS</a> (void)</td></tr>
<tr class="memdesc:gaf5f578628bc8b7154b29577f6f6a87fd"><td class="mdescLeft"> </td><td class="mdescRight">Get Priority Grouping (non-secure) <a href="#gaf5f578628bc8b7154b29577f6f6a87fd">More...</a><br/></td></tr>
<tr class="separator:gaf5f578628bc8b7154b29577f6f6a87fd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaedea4c16dd4a0b792c7e9d1da4c49295"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gaedea4c16dd4a0b792c7e9d1da4c49295">TZ_NVIC_EnableIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gaedea4c16dd4a0b792c7e9d1da4c49295"><td class="mdescLeft"> </td><td class="mdescRight">Enable External Interrupt (non-secure) <a href="#gaedea4c16dd4a0b792c7e9d1da4c49295">More...</a><br/></td></tr>
<tr class="separator:gaedea4c16dd4a0b792c7e9d1da4c49295"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga57d2a6736704c4a39421ed1a2e7b689b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga57d2a6736704c4a39421ed1a2e7b689b">TZ_NVIC_GetEnableIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga57d2a6736704c4a39421ed1a2e7b689b"><td class="mdescLeft"> </td><td class="mdescRight">Get Interrupt Enable status (non-secure) <a href="#ga57d2a6736704c4a39421ed1a2e7b689b">More...</a><br/></td></tr>
<tr class="separator:ga57d2a6736704c4a39421ed1a2e7b689b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc58593dea7803c1f1e1ed3b098f497c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gabc58593dea7803c1f1e1ed3b098f497c">TZ_NVIC_DisableIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gabc58593dea7803c1f1e1ed3b098f497c"><td class="mdescLeft"> </td><td class="mdescRight">Disable External Interrupt (non-secure) <a href="#gabc58593dea7803c1f1e1ed3b098f497c">More...</a><br/></td></tr>
<tr class="separator:gabc58593dea7803c1f1e1ed3b098f497c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab85bd0d55d746caf0e414be5284afe24"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gab85bd0d55d746caf0e414be5284afe24">TZ_NVIC_GetPendingIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gab85bd0d55d746caf0e414be5284afe24"><td class="mdescLeft"> </td><td class="mdescRight">Get Pending Interrupt (non-secure) <a href="#gab85bd0d55d746caf0e414be5284afe24">More...</a><br/></td></tr>
<tr class="separator:gab85bd0d55d746caf0e414be5284afe24"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaccbc9aa0eacf4d4c3d3046edb9e02edd"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gaccbc9aa0eacf4d4c3d3046edb9e02edd">TZ_NVIC_SetPendingIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gaccbc9aa0eacf4d4c3d3046edb9e02edd"><td class="mdescLeft"> </td><td class="mdescRight">Set Pending Interrupt (non-secure) <a href="#gaccbc9aa0eacf4d4c3d3046edb9e02edd">More...</a><br/></td></tr>
<tr class="separator:gaccbc9aa0eacf4d4c3d3046edb9e02edd"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3b30f8b602b593a806617b671a50731a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga3b30f8b602b593a806617b671a50731a">TZ_NVIC_ClearPendingIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga3b30f8b602b593a806617b671a50731a"><td class="mdescLeft"> </td><td class="mdescRight">Clear Pending Interrupt (non-secure) <a href="#ga3b30f8b602b593a806617b671a50731a">More...</a><br/></td></tr>
<tr class="separator:ga3b30f8b602b593a806617b671a50731a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1bffd79bd6365d83281883b6c4b0f218"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga1bffd79bd6365d83281883b6c4b0f218">TZ_NVIC_GetActive_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga1bffd79bd6365d83281883b6c4b0f218"><td class="mdescLeft"> </td><td class="mdescRight">Get Active Interrupt (non-secure) <a href="#ga1bffd79bd6365d83281883b6c4b0f218">More...</a><br/></td></tr>
<tr class="separator:ga1bffd79bd6365d83281883b6c4b0f218"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2caf0df3603378c436c838138e42059a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga2caf0df3603378c436c838138e42059a">TZ_NVIC_SetPriority_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr>
<tr class="memdesc:ga2caf0df3603378c436c838138e42059a"><td class="mdescLeft"> </td><td class="mdescRight">Set Interrupt Priority (non-secure) <a href="#ga2caf0df3603378c436c838138e42059a">More...</a><br/></td></tr>
<tr class="separator:ga2caf0df3603378c436c838138e42059a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gade6a8784339946fdd50575d7e65a3268"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gade6a8784339946fdd50575d7e65a3268">TZ_NVIC_GetPriority_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gade6a8784339946fdd50575d7e65a3268"><td class="mdescLeft"> </td><td class="mdescRight">Get Interrupt Priority (non-secure) <a href="#gade6a8784339946fdd50575d7e65a3268">More...</a><br/></td></tr>
<tr class="separator:gade6a8784339946fdd50575d7e65a3268"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="ga3b30f8b602b593a806617b671a50731a"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">void TZ_NVIC_ClearPendingIRQ_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Clears the pending bit of an non-secure external interrupt when in secure state. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr>
</table>
</dd>
</dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">NVIC_ClearPendingIRQ</a> </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="gabc58593dea7803c1f1e1ed3b098f497c"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">void TZ_NVIC_DisableIRQ_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Disables a device-specific interrupt in the non-secure NVIC when in secure state. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr>
</table>
</dd>
</dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a> </li>
</ul>
</dd></dl>
</div>
</div>
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<div class="memitem">
<div class="memproto">
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<td class="memname">void TZ_NVIC_EnableIRQ_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Enables a device-specific interrupt in the non-secure NVIC when in secure state. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr>
</table>
</dd>
</dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a> </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="ga1bffd79bd6365d83281883b6c4b0f218"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">uint32_t TZ_NVIC_GetActive_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Reads the active register in non-secure NVIC when in secure state and returns the active bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Interrupt status is not active. </dd>
<dd>
1 Interrupt status is active. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">NVIC_GetActive</a> </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="ga57d2a6736704c4a39421ed1a2e7b689b"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">uint32_t TZ_NVIC_GetEnableIRQ_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Interrupt is not enabled. </dd>
<dd>
1 Interrupt is enabled. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c" title="Disable a device specific interrupt. ">NVIC_DisableIRQ</a>; </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="gab85bd0d55d746caf0e414be5284afe24"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">uint32_t TZ_NVIC_GetPendingIRQ_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Reads the pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Interrupt status is not pending. </dd>
<dd>
1 Interrupt status is pending. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a> </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="gade6a8784339946fdd50575d7e65a3268"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">uint32_t TZ_NVIC_GetPriority_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Reads the priority of an non-secure interrupt when in secure state. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="gaf5f578628bc8b7154b29577f6f6a87fd"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">uint32_t TZ_NVIC_GetPriorityGrouping_NS </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Reads the priority grouping field from the non-secure NVIC when in secure state. </p>
<dl class="section return"><dt>Returns</dt><dd>Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Mainline. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a> </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="gaccbc9aa0eacf4d4c3d3046edb9e02edd"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">void TZ_NVIC_SetPendingIRQ_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Sets the pending bit of an non-secure external interrupt when in secure state. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. Value cannot be negative. </td></tr>
</table>
</dd>
</dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a> </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="ga2caf0df3603378c436c838138e42059a"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">void TZ_NVIC_SetPriority_NS </td>
<td>(</td>
<td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
<td class="paramname"><em>IRQn</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>priority</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Sets the priority of an non-secure interrupt when in secure state. </p>
<dl class="section note"><dt>Note</dt><dd>The priority cannot be set for every core interrupt. </dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>Priority to set. </td></tr>
</table>
</dd>
</dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a> </li>
</ul>
</dd></dl>
</div>
</div>
<a class="anchor" id="ga0d3b5db0685bd95cc8bd2f7ad0891d39"></a>
<div class="memitem">
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<table class="memname">
<tr>
<td class="memname">void TZ_NVIC_SetPriorityGrouping_NS </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>PriorityGroup</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority grouping field. </td></tr>
</table>
</dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Mainline. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a> </li>
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<div class="title">Peripheral Access</div> </div>
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<p>Naming conventions and optional features for accessing peripherals.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field, value)</td></tr>
<tr class="memdesc:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft"> </td><td class="mdescRight">Mask and shift a bit field value for assigning the result to a peripheral register. <a href="#ga286e3b913dbd236c7f48ea70c8821f4e">More...</a><br/></td></tr>
<tr class="separator:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field, value)</td></tr>
<tr class="memdesc:ga139b6e261c981f014f386927ca4a8444"><td class="mdescLeft"> </td><td class="mdescRight">Extract from a peripheral register value the a bit field value. <a href="#ga139b6e261c981f014f386927ca4a8444">More...</a><br/></td></tr>
<tr class="separator:ga139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains typically these definition and also includes the core specific header files.</p>
<p>The definitions for <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals. Refer to <a href="../../SVD/html/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information.</p>
<p>Each peripheral provides a data type definition with a name that is composed of:</p>
<ul>
<li>an optional prefix <b><<em>device abbreviation></em>_</b></li>
<li><b><<em>peripheral name</em>></b></li>
<li>postfix <b>_Type</b> or <b>_TypeDef</b> to identify a type definition.</li>
</ul>
<p>Examples:</p>
<ul>
<li><b>UART_TypeDef</b> for the peripheral <b>UART</b>.</li>
<li><b>LPC_UART_TypeDef</b> for the device family <b>LPC</b> and the peripheral <b>UART</b>.</li>
</ul>
<p>The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.</p>
<ul>
<li>IO Type Qualifiers are used to specify the access to peripheral variables. <table class="doxtable">
<tr>
<th align="left">IO Type Qualifier </th><th align="left">Type </th><th align="left">Description </th></tr>
<tr>
<td align="left"><b>__IM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read only' permissions </td></tr>
<tr>
<td align="left"><b>__OM</b> </td><td align="left">Struct member </td><td align="left">Defines 'write only' permissions </td></tr>
<tr>
<td align="left"><b>__IOM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read / write' permissions </td></tr>
<tr>
<td align="left"><b>__I</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read only' permissions </td></tr>
<tr>
<td align="left"><b>__O</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'write only' permissions </td></tr>
<tr>
<td align="left"><b>__IO</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read / write' permissions </td></tr>
</table>
<dl class="section note"><dt>Note</dt><dd><b>__IM</b>, <b>__OM</b>, <b>__IOM</b> are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used <b>__I</b>, <b>__O</b>, <b>__IO</b> also for struct member definitions.</dd></dl>
The typedef <b><<em>device abbreviation</em>>_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.</li>
</ul>
<div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line">{</div>
<div class="line"> <span class="keyword">union </span>{</div>
<div class="line"> __IM uint8_t RBR; <span class="comment">/* Offset: 0x000 (R/ ) Receiver Buffer Register */</span></div>
<div class="line"> __OM uint8_t THR; <span class="comment">/* Offset: 0x000 ( /W) Transmit Holding Register */</span></div>
<div class="line"> __IOM uint8_t DLL; <span class="comment">/* Offset: 0x000 (R/W) Divisor Latch LSB */</span></div>
<div class="line"> uint32_t RESERVED0;</div>
<div class="line"> };</div>
<div class="line"> <span class="keyword">union </span>{</div>
<div class="line"> __IOM uint8_t DLM; <span class="comment">/* Offset: 0x004 (R/W) Divisor Latch MSB */</span></div>
<div class="line"> __IOM uint32_t IER; <span class="comment">/* Offset: 0x004 (R/W) Interrupt Enable Register */</span></div>
<div class="line"> };</div>
<div class="line"> <span class="keyword">union </span>{</div>
<div class="line"> __IM uint32_t IIR; <span class="comment">/* Offset: 0x008 (R/ ) Interrupt ID Register */</span></div>
<div class="line"> __OM uint8_t FCR; <span class="comment">/* Offset: 0x008 ( /W) FIFO Control Register */</span></div>
<div class="line"> };</div>
<div class="line"> __IOM uint8_t LCR; <span class="comment">/* Offset: 0x00C (R/W) Line Control Register */</span></div>
<div class="line"> uint8_t RESERVED1[7];</div>
<div class="line"> __IM uint8_t LSR; <span class="comment">/* Offset: 0x014 (R/ ) Line Status Register */</span></div>
<div class="line"> uint8_t RESERVED2[7];</div>
<div class="line"> __IOM uint8_t SCR; <span class="comment">/* Offset: 0x01C (R/W) Scratch Pad Register */</span></div>
<div class="line"> uint8_t RESERVED3[3];</div>
<div class="line"> __IOM uint32_t ACR; <span class="comment">/* Offset: 0x020 (R/W) Autobaud Control Register */</span></div>
<div class="line"> __IOM uint8_t ICR; <span class="comment">/* Offset: 0x024 (R/W) IrDA Control Register */</span></div>
<div class="line"> uint8_t RESERVED4[3];</div>
<div class="line"> __IOM uint8_t FDR; <span class="comment">/* Offset: 0x028 (R/W) Fractional Divider Register */</span></div>
<div class="line"> uint8_t RESERVED5[7];</div>
<div class="line"> __IOM uint8_t TER; <span class="comment">/* Offset: 0x030 (R/W) Transmit Enable Register */</span></div>
<div class="line"> uint8_t RESERVED6[39];</div>
<div class="line"> __IM uint8_t FIFOLVL; <span class="comment">/* Offset: 0x058 (R/ ) FIFO Level Register */</span></div>
<div class="line">} LPC_UART_TypeDef;</div>
</div><!-- fragment --><p>To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.</p>
<p><b>Example:</b> In this example <b>LPC_UART2</b> and <b>LPC_UART3</b> are two pointers to UARTs defined with above register structure. <br/>
</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )</span></div>
<div class="line"><span class="preprocessor">#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</span></div>
</div><!-- fragment --><dl class="section note"><dt>Note</dt><dd><ul>
<li>The prefix <b>LPC</b> is optional.</li>
</ul>
</dd></dl>
<p>The registers in the various UARTs can now be referred in the user code as shown below:<br/>
</p>
<div class="fragment"><div class="line">val = LPC_UART2->DR <span class="comment">// is the data register of UART1.</span></div>
</div><!-- fragment --><hr/>
<h1><a class="anchor" id="core_cmsis_pal_min_reqs"></a>
Minimal Requirements</h1>
<p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b>core_cm<em>#</em>.h</b> define as a minimum: <br/>
<br/>
</p>
<ul>
<li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br/>
<br/>
<b>Example:</b> <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line">{</div>
<div class="line"> __IOM uint32_t CTRL; <span class="comment">/* Offset: 0x000 (R/W) SysTick Control and Status Register */</span></div>
<div class="line"> __IOM uint32_t LOAD; <span class="comment">/* Offset: 0x004 (R/W) SysTick Reload Value Register */</span></div>
<div class="line"> __IOM uint32_t VAL; <span class="comment">/* Offset: 0x008 (R/W) SysTick Current Value Register */</span></div>
<div class="line"> __IM uint32_t CALIB; <span class="comment">/* Offset: 0x00C (R/ ) SysTick Calibration Register */</span></div>
<div class="line">} <a class="code" href="structSysTick__Type.html">SysTick_Type</a>;</div>
</div><!-- fragment --></li>
<li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br/>
<br/>
<b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010) </span><span class="comment">/* SysTick Base Address */</span><span class="preprocessor"></span></div>
</div><!-- fragment --></li>
<li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2). <br/>
<br/>
<b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick ((SysTick_Type *) Systick_BASE) </span><span class="comment">/* SysTick access definition */</span><span class="preprocessor"></span></div>
</div><!-- fragment --></li>
</ul>
<p>These definitions allow accessing peripheral registers with simple assignments.</p>
<ul>
<li><b>Example:</b> <br/>
<div class="fragment"><div class="line">SysTick->CTRL = 0;</div>
</div><!-- fragment --></li>
</ul>
<hr/>
<h1><a class="anchor" id="core_cmsis_pal_opts"></a>
Optional Features</h1>
<p>Optionally, the file <b><em>device</em>.h</b> may define:</p>
<ul>
<li><a class="el" href="group__peripheral__gr.html#core_cmsis_pal_bitfields">Register Bit Fields</a> and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <b><<em>device abbreviation</em>>_</b> and <b><<em>peripheral name</em>>_</b>. It is recommended to use CAPITAL letters for #define constants.</li>
<li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b><<em>device abbreviation</em>>_</b> and <b><<em>peripheral name</em>>_</b>.</li>
</ul>
<hr/>
<h1><a class="anchor" id="core_cmsis_pal_bitfields"></a>
Register Bit Fields</h1>
<p>For Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also for other peripheral registers.</p>
<p><b>Example:</b></p>
<p>Bit field definitions for register CPUID in SCB (System Control Block).</p>
<div class="fragment"><div class="line"><span class="comment">/* SCB CPUID Register Definitions */</span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos 24U </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Pos 20U </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos 16U </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Pos 4U </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Pos 0U </span></div>
<div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Msk (0xFUL </span><span class="comment">/*<< SCB_CPUID_REVISION_Pos*/</span><span class="preprocessor">) </span></div>
</div><!-- fragment --><p>The macros <b><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning the result to a peripheral register. ">_VAL2FLD(field, value)</a></b> and <b><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444" title="Extract from a peripheral register value the a bit field value. ">_FLD2VAL(field, value)</a></b> enable access to bit fields. </p>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga139b6e261c981f014f386927ca4a8444"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define _FLD2VAL</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">field, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">value </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">field</td><td>name of bit field. </td></tr>
<tr><td class="paramname">value</td><td>value of the register. This parameter is interpreted as an uint32_t type.</td></tr>
</table>
</dd>
</dl>
<p>The macro <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to extract the value of a bit field from a register.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><span class="keywordtype">id</span> = <a class="code" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(SCB_CPUID_REVISION, SCB->CPUID);</div>
</div><!-- fragment -->
</div>
</div>
<a class="anchor" id="ga286e3b913dbd236c7f48ea70c8821f4e"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define _VAL2FLD</td>
<td>(</td>
<td class="paramtype"> </td>
<td class="paramname">field, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype"> </td>
<td class="paramname">value </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">field</td><td>name of bit field. </td></tr>
<tr><td class="paramname">value</td><td>value for the bit field. This parameter is interpreted as an uint32_t type.</td></tr>
</table>
</dd>
</dl>
<p>The macro <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to shift bit-field values for assigning to a register.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line">SCB->CPUID = <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(SCB_CPUID_REVISION, 0x3) | <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(SCB_CPUID_VARIANT, 0x3);</div>
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<a href="#func-members">Functions</a> </div>
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<div class="title">SAU Functions<div class="ingroups"><a class="el" href="group__trustzone__functions.html">TrustZone for Armv8-M/v8.1-M</a></div></div> </div>
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<p>Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga6093bc5939ea8924fbcfdffb8f0553f1"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> (void)</td></tr>
<tr class="memdesc:ga6093bc5939ea8924fbcfdffb8f0553f1"><td class="mdescLeft"> </td><td class="mdescRight">Setup Secure Attribute Unit (SAU) and non-secure interrupts. <a href="#ga6093bc5939ea8924fbcfdffb8f0553f1">More...</a><br/></td></tr>
<tr class="separator:ga6093bc5939ea8924fbcfdffb8f0553f1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga187377409289e34838225ce801fb102c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sau__trustzone__functions.html#ga187377409289e34838225ce801fb102c">TZ_SAU_Enable</a> (void)</td></tr>
<tr class="memdesc:ga187377409289e34838225ce801fb102c"><td class="mdescLeft"> </td><td class="mdescRight">Enable Security Attribution Unit (SAU) <a href="#ga187377409289e34838225ce801fb102c">More...</a><br/></td></tr>
<tr class="separator:ga187377409289e34838225ce801fb102c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga42e201cea0a4b09f588a28b751f726fb"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sau__trustzone__functions.html#ga42e201cea0a4b09f588a28b751f726fb">TZ_SAU_Disable</a> (void)</td></tr>
<tr class="memdesc:ga42e201cea0a4b09f588a28b751f726fb"><td class="mdescLeft"> </td><td class="mdescRight">Disable Security Attribution Unit (SAU) <a href="#ga42e201cea0a4b09f588a28b751f726fb">More...</a><br/></td></tr>
<tr class="separator:ga42e201cea0a4b09f588a28b751f726fb"><td class="memSeparator" colspan="2"> </td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The Secure Attribution Unit (SAU) functions SAU</p>
<dl class="section note"><dt>Note</dt><dd>A SAU is always present if the security extension is available. The functionality differs if the SAU contains SAU regions. If SAU regions are available is configured with the macro __SAUREGION_PRESENT (see <a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a>). </dd></dl>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="ga42e201cea0a4b09f588a28b751f726fb"></a>
<div class="memitem">
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<td class="memname">void TZ_SAU_Disable </td>
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<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
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<p>Disables the Security Attribution Unit (SAU). </p>
</div>
</div>
<a class="anchor" id="ga187377409289e34838225ce801fb102c"></a>
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<td class="memname">void TZ_SAU_Enable </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
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<p>Enables the Security Attribution Unit (SAU). </p>
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<td class="memname">void TZ_SAU_Setup </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>The function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> uses the settings in the <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts. It is called from the function <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>. </p>
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<div class="title">System and Clock Configuration</div> </div>
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<p>Functions for system and clock setup available in system_<em>device</em>.c.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> (void)</td></tr>
<tr class="memdesc:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="mdescLeft"> </td><td class="mdescRight">Function to Initialize the system. <a href="#ga93f514700ccf00d08dbdcff7f1224eb2">More...</a><br/></td></tr>
<tr class="separator:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> (void)</td></tr>
<tr class="memdesc:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="mdescLeft"> </td><td class="mdescRight">Function to update the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>. <a href="#gae0c36a9591fe6e9c45ecb21a794f0f0f">More...</a><br/></td></tr>
<tr class="separator:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="memSeparator" colspan="2"> </td></tr>
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Variables</h2></td></tr>
<tr class="memitem:gaa3cd3e43291e81e795d642b79b6088e6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a></td></tr>
<tr class="memdesc:gaa3cd3e43291e81e795d642b79b6088e6"><td class="mdescLeft"> </td><td class="mdescRight">Variable to hold the system core clock value. <a href="#gaa3cd3e43291e81e795d642b79b6088e6">More...</a><br/></td></tr>
<tr class="separator:gaa3cd3e43291e81e795d642b79b6088e6"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>Arm provides a template file <b>system_<em>device</em>.c</b> that must be adapted by the silicon vendor to match their actual device. As a <b>minimum requirement</b>, this file must provide:</p>
<ul>
<li>A device-specific system configuration function, <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit()</a>.</li>
<li>A global variable that contains the system frequency, <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>.</li>
</ul>
<p>The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.</p>
<dl class="section note"><dt>Note</dt><dd>Please pay special attention to the static variable <code>SystemCoreClock</code>. This variable might be used throughout the whole system initialization and runtime to calculate frequency/time related values. Thus one must assure that the variable always reflects the actual system clock speed. Be aware that a value stored to <code>SystemCoreClock</code> during low level initializaton (i.e. <code><a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a></code>) might get overwritten by C libray startup code and/or .bss section initialization. Thus its highly recommended to call <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> at the beginning of the user <code>main()</code> routine.</dd></dl>
<h1><a class="anchor" id="system_init_code_ex_sec"></a>
Code Example</h1>
<p>The code below shows the usage of the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> and the functions <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> and <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Function to update the variable SystemCoreClock. ">SystemCoreClockUpdate()</a> with an LPC1700.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#include "LPC17xx.h"</span></div>
<div class="line"></div>
<div class="line">uint32_t coreClock_1 = 0; <span class="comment">/* Variables to store core clock values */</span></div>
<div class="line">uint32_t coreClock_2 = 0;</div>
<div class="line"></div>
<div class="line"></div>
<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div>
<div class="line"></div>
<div class="line"> coreClock_1 = <a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>; <span class="comment">/* Store value of predefined SystemCoreClock */</span></div>
<div class="line"></div>
<div class="line"> <a class="code" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a>(); <span class="comment">/* Update SystemCoreClock according to register settings */</span></div>
<div class="line"></div>
<div class="line"> coreClock_2 = <a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>; <span class="comment">/* Store value of calculated SystemCoreClock */</span></div>
<div class="line"></div>
<div class="line"> <span class="keywordflow">if</span> (coreClock_2 != coreClock_1) { <span class="comment">/* Without changing the clock setting both core clock values should be the same */</span> </div>
<div class="line"> <span class="comment">// Error Handling</span></div>
<div class="line"> }</div>
<div class="line"></div>
<div class="line"> <span class="keywordflow">while</span>(1);</div>
<div class="line">}</div>
</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="gae0c36a9591fe6e9c45ecb21a794f0f0f"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">void SystemCoreClockUpdate </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
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<p>Updates the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock. </p>
</div>
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<td class="memname">void SystemInit </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>. SystemInit is called from the file <b>startup<em>_device</em></b>. </p>
</div>
</div>
<h2 class="groupheader">Variable Documentation</h2>
<a class="anchor" id="gaa3cd3e43291e81e795d642b79b6088e6"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">uint32_t SystemCoreClock</td>
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<p>Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.</p>
<dl class="section attention"><dt>Attention</dt><dd>Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger. </dd></dl>
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<div class="title">SysTick Functions<div class="ingroups"><a class="el" href="group__trustzone__functions.html">TrustZone for Armv8-M/v8.1-M</a></div></div> </div>
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<p>SysTick functions related to TrustZone for Armv8-M.
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Functions</h2></td></tr>
<tr class="memitem:gad18a1b1a6796c652f2b35e728f2e2670"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__systick__trustzone__functions.html#gad18a1b1a6796c652f2b35e728f2e2670">TZ_SysTick_Config_NS</a> (uint32_t ticks)</td></tr>
<tr class="memdesc:gad18a1b1a6796c652f2b35e728f2e2670"><td class="mdescLeft"> </td><td class="mdescRight">System Tick Configuration (non-secure) <a href="#gad18a1b1a6796c652f2b35e728f2e2670">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<h2 class="groupheader">Function Documentation</h2>
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<td class="memname">uint32_t TZ_SysTick_Config_NS </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>ticks</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ticks</td><td>Number of ticks between two interrupts. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded. </dd>
<dd>
1 Function failed. </dd></dl>
<dl class="section note"><dt>Note</dt><dd>When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><em>device</em>.h</b> must contain a vendor-specific implementation of this function. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><ul>
<li><a class="el" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a> </li>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/group__systick__trustzone__functions.html | HTML | apache-2.0 | 8,603 |
var group__systick__trustzone__functions =
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]; | YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/group__systick__trustzone__functions.js | JavaScript | apache-2.0 | 164 |
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<div class="title">TrustZone for Armv8-M/v8.1-M</div> </div>
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<p>Functions that related to optional Armv8-M and Armv8.1-M security extension.
<a href="#details">More...</a></p>
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<tr class="memitem:group__coreregister__trustzone__functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html">Core Register Access Functions</a></td></tr>
<tr class="memdesc:group__coreregister__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">Core register Access functions related to TrustZone for Armv8-M. <br/></td></tr>
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<tr class="memdesc:group__nvic__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M. <br/></td></tr>
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<tr class="memdesc:group__systick__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">SysTick functions related to TrustZone for Armv8-M. <br/></td></tr>
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<tr class="memitem:group__sau__trustzone__functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sau__trustzone__functions.html">SAU Functions</a></td></tr>
<tr class="memdesc:group__sau__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M. <br/></td></tr>
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<tr class="memitem:group__context__trustzone__functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__context__trustzone__functions.html">RTOS Context Management</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The Armv8-M architecture has optional Armv8-M security extension based on Arm TrustZone technology. To access Arm TrustZone extensions for Armv8-M additional CMSIS functions are provided:</p>
<ul>
<li><a class="el" href="group__coreregister__trustzone__functions.html">Core Register Access Functions</a></li>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/group__trustzone__functions.html | HTML | apache-2.0 | 9,725 |
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<tr class="memitem:ga85987c5fcc1e012d7ac01369ee6ca2b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5">__CM_CMSIS_VERSION_MAIN</a></td></tr>
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<tr class="memitem:ga22083cbe7f0606cfd538ec12b2e41608"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608">__CM_CMSIS_VERSION_SUB</a></td></tr>
<tr class="memdesc:ga22083cbe7f0606cfd538ec12b2e41608"><td class="mdescLeft"> </td><td class="mdescRight">Contains the CMSIS minor version. <a href="#ga22083cbe7f0606cfd538ec12b2e41608">More...</a><br/></td></tr>
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<tr class="memitem:ga39f3d64ff95fb58feccc7639e537ff89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#ga39f3d64ff95fb58feccc7639e537ff89">__CM_CMSIS_VERSION</a></td></tr>
<tr class="memdesc:ga39f3d64ff95fb58feccc7639e537ff89"><td class="mdescLeft"> </td><td class="mdescRight">Contains the CMSIS version. <a href="#ga39f3d64ff95fb58feccc7639e537ff89">More...</a><br/></td></tr>
<tr class="separator:ga39f3d64ff95fb58feccc7639e537ff89"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga63ea62503c88acab19fcf3d5743009e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#ga63ea62503c88acab19fcf3d5743009e3">__CORTEX_M</a></td></tr>
<tr class="memdesc:ga63ea62503c88acab19fcf3d5743009e3"><td class="mdescLeft"> </td><td class="mdescRight">Contains the core version for a Cortex-M class controller. <a href="#ga63ea62503c88acab19fcf3d5743009e3">More...</a><br/></td></tr>
<tr class="separator:ga63ea62503c88acab19fcf3d5743009e3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaeaaf66c86e5ae02a0e1fe542cb7f4d8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c">__CORTEX_SC</a></td></tr>
<tr class="memdesc:gaeaaf66c86e5ae02a0e1fe542cb7f4d8c"><td class="mdescLeft"> </td><td class="mdescRight">Contains the core version for a Cortex Secure Core controller. <a href="#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c">More...</a><br/></td></tr>
<tr class="separator:gaeaaf66c86e5ae02a0e1fe542cb7f4d8c"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The header file <b>cmsis_version.h</b> is included by each core header so that these definitions are available.</p>
<p><b>Code Example:</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#if defined(__CM_CMSIS_VERSION) && \</span></div>
<div class="line"><span class="preprocessor"> (__CM_CMSIS_VERSION >= 0x00050001)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error Yes, we have CMSIS 5.1 or later</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#else</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error We need CMSIS 5.1 or later!</span></div>
<div class="line"><span class="preprocessor">#endif</span></div>
</div><!-- fragment --><p><b>Deprecated</b></p>
<p>The following macros are deprecated:</p>
<ul>
<li><b>__XXX_CMSIS_VERSION_MAIN</b> which is replaced by <a class="el" href="group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5">__CM_CMSIS_VERSION_MAIN</a>.</li>
<li><b>__XXX_CMSIS_VERSION_SUB</b> which is replaced by <a class="el" href="group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608">__CM_CMSIS_VERSION_SUB</a>.</li>
<li><b>__XXX_CMSIS_VERSION</b> which is replaced by <a class="el" href="group__version__control__gr.html#ga39f3d64ff95fb58feccc7639e537ff89">__CM_CMSIS_VERSION</a>. </li>
</ul>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga39f3d64ff95fb58feccc7639e537ff89"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">#define __CM_CMSIS_VERSION</td>
</tr>
</table>
</div><div class="memdoc">
<p>The CMSIS version is a combination of the <a class="el" href="group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5">__CM_CMSIS_VERSION_MAIN</a> (bits 31..15) and <a class="el" href="group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608">__CM_CMSIS_VERSION_SUB</a> (bits 14..0). </p>
</div>
</div>
<a class="anchor" id="ga85987c5fcc1e012d7ac01369ee6ca2b5"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="memname">#define __CM_CMSIS_VERSION_MAIN</td>
</tr>
</table>
</div><div class="memdoc">
<p>The CMSIS major version can be used to differentiate between CMSIS major releases. </p>
</div>
</div>
<a class="anchor" id="ga22083cbe7f0606cfd538ec12b2e41608"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define __CM_CMSIS_VERSION_SUB</td>
</tr>
</table>
</div><div class="memdoc">
<p>The CMSIS minor version can be used to query a CMSIS release update level. </p>
</div>
</div>
<a class="anchor" id="ga63ea62503c88acab19fcf3d5743009e3"></a>
<div class="memitem">
<div class="memproto">
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<td class="memname">#define __CORTEX_M</td>
</tr>
</table>
</div><div class="memdoc">
<p>This define can be used to differentiate between the various available Cortex-M controllers. Possible values are:</p>
<ul>
<li>0 for a Cortex-M0 or Cortex-M0+</li>
<li>1 for a Cortex-M1</li>
<li>3 for a Cortex-M3</li>
<li>4 for a Cortex-M4</li>
<li>7 for a Cortex-M7</li>
<li>23 for a Cortex-M23</li>
<li>33 for a Cortex-M33</li>
<li>35 for a Cortex-M35P</li>
</ul>
<p>This define is only available for Cortex-M class controllers. <b>Code Example:</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#if defined(__CORTEX_M) && (__CORTEX_M == 4)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error Yes, we have an Cortex-M4 controller.</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#else</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error We need a Cortex-M4 controller!</span></div>
<div class="line"><span class="preprocessor">#endif</span></div>
</div><!-- fragment -->
</div>
</div>
<a class="anchor" id="gaeaaf66c86e5ae02a0e1fe542cb7f4d8c"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">#define __CORTEX_SC</td>
</tr>
</table>
</div><div class="memdoc">
<p>This define can be used to differentiate between the various available Cortex Secure Core controllers. Possible values are:</p>
<ul>
<li>000 for a Cortex-SC000</li>
<li>300 for a Cortex-SC300</li>
</ul>
<p>This define is only available for Cortex Secure Core controllers. <b>Code Example:</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#if defined(__CORTEX_SC) && (__CORTEX_SC == 300U)</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error Yes, we have an Cortex SC300 controller.</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#else</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error We need a Cortex SC300 controller!</span></div>
<div class="line"><span class="preprocessor">#endif</span></div>
</div><!-- fragment -->
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<li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/group__version__control__gr.html | HTML | apache-2.0 | 14,828 |
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<div id="projectname">CMSIS-Core (Cortex-M)
 <span id="projectnumber">Version 5.3.0</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
<ul>
<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
</ul>
<p>The following sections provide details about the CMSIS-Core (Cortex-M):</p>
<ul>
<li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
<li><a class="el" href="using_TrustZone_pg.html">Using TrustZone® for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture.</li>
<li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
<li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
</ul>
<hr/>
<h2>CMSIS-Core (Cortex-M) in ARM::CMSIS Pack </h2>
<p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p>
<table class="doxtable">
<tr>
<th>File/Folder </th><th>Content </th></tr>
<tr>
<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
<tr>
<td><b>CMSIS\Core\Include</b> </td><td>CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
<tr>
<td><b>Device</b> </td><td><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices </td></tr>
<tr>
<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors </td></tr>
</table>
<hr/>
<h1><a class="anchor" id="ref_v6-v8M"></a>
Processor Support</h1>
<p>CMSIS supports the complete range of <a href="https://developer.arm.com/products/processors/cortex-m" target="_blank"><b>Cortex-M processors</b></a> and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M/v8.1-M architecture</b></a> including security extensions.</p>
<h2><a class="anchor" id="ref_man_sec"></a>
Cortex-M Reference Manuals</h2>
<p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p>
<ul>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
</ul>
<p>The <b>Cortex-M23</b> and <b>Cortex-M33</b> are described with Technical Reference Manuals that are available here:</p>
<ul>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)</li>
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)</li>
</ul>
<p>CMSIS also supports the following Cortex-M processor variants:</p>
<ul>
<li><a href="https://developer.arm.com/products/processors/cortex-m/cortex-m1" target="_blank"><b>Cortex-M1</b></a> is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).</li>
<li><a href="https://developer.arm.com/products/processors/cortex-m/sc000-processor" target="_blank"><b>SecurCore SC000</b></a> is designed specifically for smartcard and security applications (Armv6-M architecture).</li>
<li><a href="https://developer.arm.com/products/processors/cortex-m/sc300-processor" target="_blank"><b>SecurCore SC300</b></a> is designed specifically for smartcard and security applications (Armv7-M architecture).</li>
<li><a href="https://developer.arm.com/products/processors/cortex-m/sc300-processor" target="_blank"><b>Cortex-M35P</b></a> is a temper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.</li>
</ul>
<h2><a class="anchor" id="ARMv8M"></a>
Armv8-M and Armv8.1-M Architecture</h2>
<p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles and Armv8.1M are supported by CMSIS.</p>
<p>The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p>
<p>The Armv8.1-M Architecture further extends Armv8-M with Helium, an Microcontroller Vector Extension (MVE) and further instruction set and debug extensions. More information about Armv8.1-M Architecture is available under <a href="https://developer.arm.com/technologies/helium" target="_blank"><b>Arm Helium technology</b></a>.</p>
<hr/>
<h1><a class="anchor" id="tested_tools_sec"></a>
Tested and Verified Toolchains</h1>
<p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p>
<ul>
<li>Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23/33/35P, Armv8-M, Armv8.1-M)</li>
<li>Arm: Arm Compiler 6.12</li>
<li>Arm: Arm Compiler 6.6.2 (not for Cortex-M0/23/33/35P, Armv8-M, Armv8.1-M)</li>
<li>GNU: GNU Tools for Arm Embedded 8.2.1 2018q4</li>
<li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183</li>
</ul>
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<div id="projectname">CMSIS-Core (Cortex-M)
 <span id="projectnumber">Version 5.3.0</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="contents">
<div class="textblock">Here is a list of all modules:</div><div class="directory">
<div class="levels">[detail level <span onclick="javascript:toggleLevel(1);">1</span><span onclick="javascript:toggleLevel(2);">2</span>]</div><table class="directory">
<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__version__control__gr.html" target="_self">Version Control</a></td><td class="desc">Version #define symbols for CMSIS release specific C/C++ source code </td></tr>
<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__compiler__conntrol__gr.html" target="_self">Compiler Control</a></td><td class="desc">Compiler agnostic #define symbols for generic C/C++ source code </td></tr>
<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__peripheral__gr.html" target="_self">Peripheral Access</a></td><td class="desc">Naming conventions and optional features for accessing peripherals </td></tr>
<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__system__init__gr.html" target="_self">System and Clock Configuration</a></td><td class="desc">Functions for system and clock setup available in system_<em>device</em>.c </td></tr>
<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__NVIC__gr.html" target="_self">Interrupts and Exceptions (NVIC)</a></td><td class="desc">Functions to access the Nested Vector Interrupt Controller (NVIC) </td></tr>
<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__Core__Register__gr.html" target="_self">Core Register Access</a></td><td class="desc">Functions to access the Cortex-M core registers </td></tr>
<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic__CPU__gr.html" target="_self">Intrinsic Functions for CPU Instructions</a></td><td class="desc">Functions that generate specific Cortex-M CPU Instructions </td></tr>
<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic__SIMD__gr.html" target="_self">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a></td><td class="desc">Access to dedicated SIMD instructions </td></tr>
<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__fpu__functions.html" target="_self">FPU Functions</a></td><td class="desc">Functions that relate to the Floating-Point Arithmetic Unit </td></tr>
<tr id="row_9_"><td class="entry"><img id="arr_9_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('9_')"/><a class="el" href="group__mpu__functions.html" target="_self">MPU Functions for Armv6-M/v7-M</a></td><td class="desc">Functions that relate to the Memory Protection Unit </td></tr>
<tr id="row_9_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__mpu__defines.html" target="_self">Define values</a></td><td class="desc">Define values for MPU region setup </td></tr>
<tr id="row_10_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__mpu8__functions.html" target="_self">MPU Functions for Armv8-M</a></td><td class="desc">Functions that relate to the Memory Protection Unit </td></tr>
<tr id="row_11_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__SysTick__gr.html" target="_self">Systick Timer (SYSTICK)</a></td><td class="desc">Initialize and start the SysTick timer </td></tr>
<tr id="row_12_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__ITM__Debug__gr.html" target="_self">Debug Access</a></td><td class="desc">Debug Access to the Instrumented Trace Macrocell (ITM) </td></tr>
<tr id="row_13_" class="even"><td class="entry"><img id="arr_13_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('13_')"/><a class="el" href="group__trustzone__functions.html" target="_self">TrustZone for Armv8-M/v8.1-M</a></td><td class="desc">Functions that related to optional Armv8-M and Armv8.1-M security extension </td></tr>
<tr id="row_13_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__coreregister__trustzone__functions.html" target="_self">Core Register Access Functions</a></td><td class="desc">Core register Access functions related to TrustZone for Armv8-M </td></tr>
<tr id="row_13_1_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__nvic__trustzone__functions.html" target="_self">NVIC Functions</a></td><td class="desc">Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M </td></tr>
<tr id="row_13_2_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__systick__trustzone__functions.html" target="_self">SysTick Functions</a></td><td class="desc">SysTick functions related to TrustZone for Armv8-M </td></tr>
<tr id="row_13_3_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__sau__trustzone__functions.html" target="_self">SAU Functions</a></td><td class="desc">Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M </td></tr>
<tr id="row_13_4_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__context__trustzone__functions.html" target="_self">RTOS Context Management</a></td><td class="desc">RTOS Thread Context Management for Armv8-M TrustZone </td></tr>
<tr id="row_14_" class="even"><td class="entry"><img id="arr_14_" src="ftv2mlastnode.png" alt="\" width="16" height="22" onclick="toggleFolder('14_')"/><a class="el" href="group__cache__functions__m7.html" target="_self">Cache Functions (only Cortex-M7)</a></td><td class="desc">Functions for Instruction and Data Cache </td></tr>
<tr id="row_14_0_"><td class="entry"><img src="ftv2blank.png" alt=" " width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__Icache__functions__m7.html" target="_self">I-Cache Functions</a></td><td class="desc">Functions for the instruction cache </td></tr>
<tr id="row_14_1_" class="even"><td class="entry"><img src="ftv2blank.png" alt=" " width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__Dcache__functions__m7.html" target="_self">D-Cache Functions</a></td><td class="desc">Functions for the data cache </td></tr>
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$('.item').removeClass('selected');
$('.item').removeAttr('id');
$(a).parent().parent().addClass('selected');
$(a).parent().parent().attr('id','selected');
}
var anchor = $(aname);
gotoAnchor(anchor,aname,true);
};
} else {
a.href = url;
a.onclick = function() { storeLink(link); }
}
} else {
if (childrenData != null)
{
a.className = "nolink";
a.href = "javascript:void(0)";
a.onclick = node.expandToggle.onclick;
}
}
node.childrenUL = null;
node.getChildrenUL = function() {
if (!node.childrenUL) {
node.childrenUL = document.createElement("ul");
node.childrenUL.className = "children_ul";
node.childrenUL.style.display = "none";
node.li.appendChild(node.childrenUL);
}
return node.childrenUL;
};
return node;
}
function showRoot()
{
var headerHeight = $("#top").height();
var footerHeight = $("#nav-path").height();
var windowHeight = $(window).height() - headerHeight - footerHeight;
(function (){ // retry until we can scroll to the selected item
try {
var navtree=$('#nav-tree');
navtree.scrollTo('#selected',0,{offset:-windowHeight/2});
} catch (err) {
setTimeout(arguments.callee, 0);
}
})();
}
function expandNode(o, node, imm, showRoot)
{
if (node.childrenData && !node.expanded) {
if (typeof(node.childrenData)==='string') {
var varName = node.childrenData;
getScript(node.relpath+varName,function(){
node.childrenData = getData(varName);
expandNode(o, node, imm, showRoot);
}, showRoot);
} else {
if (!node.childrenVisited) {
getNode(o, node);
} if (imm || ($.browser.msie && $.browser.version>8)) {
// somehow slideDown jumps to the start of tree for IE9 :-(
$(node.getChildrenUL()).show();
} else {
$(node.getChildrenUL()).slideDown("fast");
}
if (node.isLast) {
node.plus_img.src = node.relpath+"ftv2mlastnode.png";
} else {
node.plus_img.src = node.relpath+"ftv2mnode.png";
}
node.expanded = true;
}
}
}
function glowEffect(n,duration)
{
n.addClass('glow').delay(duration).queue(function(next){
$(this).removeClass('glow');next();
});
}
function highlightAnchor()
{
var aname = $(location).attr('hash');
var anchor = $(aname);
if (anchor.parent().attr('class')=='memItemLeft'){
var rows = $('.memberdecls tr[class$="'+
window.location.hash.substring(1)+'"]');
glowEffect(rows.children(),300); // member without details
} else if (anchor.parents().slice(2).prop('tagName')=='TR') {
glowEffect(anchor.parents('div.memitem'),1000); // enum value
} else if (anchor.parent().attr('class')=='fieldtype'){
glowEffect(anchor.parent().parent(),1000); // struct field
} else if (anchor.parent().is(":header")) {
glowEffect(anchor.parent(),1000); // section header
} else {
glowEffect(anchor.next(),1000); // normal member
}
gotoAnchor(anchor,aname,false);
}
function selectAndHighlight(hash,n)
{
var a;
if (hash) {
var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1);
a=$('.item a[class$="'+link+'"]');
}
if (a && a.length) {
a.parent().parent().addClass('selected');
a.parent().parent().attr('id','selected');
highlightAnchor();
} else if (n) {
$(n.itemDiv).addClass('selected');
$(n.itemDiv).attr('id','selected');
}
if ($('#nav-tree-contents .item:first').hasClass('selected')) {
$('#nav-sync').css('top','30px');
} else {
$('#nav-sync').css('top','5px');
}
showRoot();
}
function showNode(o, node, index, hash)
{
if (node && node.childrenData) {
if (typeof(node.childrenData)==='string') {
var varName = node.childrenData;
getScript(node.relpath+varName,function(){
node.childrenData = getData(varName);
showNode(o,node,index,hash);
},true);
} else {
if (!node.childrenVisited) {
getNode(o, node);
}
$(node.getChildrenUL()).css({'display':'block'});
if (node.isLast) {
node.plus_img.src = node.relpath+"ftv2mlastnode.png";
} else {
node.plus_img.src = node.relpath+"ftv2mnode.png";
}
node.expanded = true;
var n = node.children[o.breadcrumbs[index]];
if (index+1<o.breadcrumbs.length) {
showNode(o,n,index+1,hash);
} else {
if (typeof(n.childrenData)==='string') {
var varName = n.childrenData;
getScript(n.relpath+varName,function(){
n.childrenData = getData(varName);
node.expanded=false;
showNode(o,node,index,hash); // retry with child node expanded
},true);
} else {
var rootBase = stripPath(o.toroot.replace(/\..+$/, ''));
if (rootBase=="index" || rootBase=="pages" || rootBase=="search") {
expandNode(o, n, true, true);
}
selectAndHighlight(hash,n);
}
}
}
} else {
selectAndHighlight(hash);
}
}
function removeToInsertLater(element) {
var parentNode = element.parentNode;
var nextSibling = element.nextSibling;
parentNode.removeChild(element);
return function() {
if (nextSibling) {
parentNode.insertBefore(element, nextSibling);
} else {
parentNode.appendChild(element);
}
};
}
function getNode(o, po)
{
var insertFunction = removeToInsertLater(po.li);
po.childrenVisited = true;
var l = po.childrenData.length-1;
for (var i in po.childrenData) {
var nodeData = po.childrenData[i];
po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],
i==l);
}
insertFunction();
}
function gotoNode(o,subIndex,root,hash,relpath)
{
var nti = navTreeSubIndices[subIndex][root+hash];
o.breadcrumbs = $.extend(true, [], nti ? nti : navTreeSubIndices[subIndex][root]);
if (!o.breadcrumbs && root!=NAVTREE[0][1]) { // fallback: show index
navTo(o,NAVTREE[0][1],"",relpath);
$('.item').removeClass('selected');
$('.item').removeAttr('id');
}
if (o.breadcrumbs) {
o.breadcrumbs.unshift(0); // add 0 for root node
showNode(o, o.node, 0, hash);
}
}
function navTo(o,root,hash,relpath)
{
var link = cachedLink();
if (link) {
var parts = link.split('#');
root = parts[0];
if (parts.length>1) hash = '#'+parts[1];
else hash='';
}
if (hash.match(/^#l\d+$/)) {
var anchor=$('a[name='+hash.substring(1)+']');
glowEffect(anchor.parent(),1000); // line number
hash=''; // strip line number anchors
//root=root.replace(/_source\./,'.'); // source link to doc link
}
var url=root+hash;
var i=-1;
while (NAVTREEINDEX[i+1]<=url) i++;
if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index
if (navTreeSubIndices[i]) {
gotoNode(o,i,root,hash,relpath)
} else {
getScript(relpath+'navtreeindex'+i,function(){
navTreeSubIndices[i] = eval('NAVTREEINDEX'+i);
if (navTreeSubIndices[i]) {
gotoNode(o,i,root,hash,relpath);
}
},true);
}
}
function showSyncOff(n,relpath)
{
n.html('<img src="'+relpath+'sync_off.png" title="'+SYNCOFFMSG+'"/>');
}
function showSyncOn(n,relpath)
{
n.html('<img src="'+relpath+'sync_on.png" title="'+SYNCONMSG+'"/>');
}
function toggleSyncButton(relpath)
{
var navSync = $('#nav-sync');
if (navSync.hasClass('sync')) {
navSync.removeClass('sync');
showSyncOff(navSync,relpath);
storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash'));
} else {
navSync.addClass('sync');
showSyncOn(navSync,relpath);
deleteLink();
}
}
function initNavTree(toroot,relpath)
{
var o = new Object();
o.toroot = toroot;
o.node = new Object();
o.node.li = document.getElementById("nav-tree-contents");
o.node.childrenData = NAVTREE;
o.node.children = new Array();
o.node.childrenUL = document.createElement("ul");
o.node.getChildrenUL = function() { return o.node.childrenUL; };
o.node.li.appendChild(o.node.childrenUL);
o.node.depth = 0;
o.node.relpath = relpath;
o.node.expanded = false;
o.node.isLast = true;
o.node.plus_img = document.createElement("img");
o.node.plus_img.src = relpath+"ftv2pnode.png";
o.node.plus_img.width = 16;
o.node.plus_img.height = 22;
if (localStorageSupported()) {
var navSync = $('#nav-sync');
if (cachedLink()) {
showSyncOff(navSync,relpath);
navSync.removeClass('sync');
} else {
showSyncOn(navSync,relpath);
}
navSync.click(function(){ toggleSyncButton(relpath); });
}
$(window).load(function(){
navTo(o,toroot,window.location.hash,relpath);
showRoot();
});
$(window).bind('hashchange', function(){
if (window.location.hash && window.location.hash.length>1){
var a;
if ($(location).attr('hash')){
var clslink=stripPath($(location).attr('pathname'))+':'+
$(location).attr('hash').substring(1);
a=$('.item a[class$="'+clslink+'"]');
}
if (a==null || !$(a).parent().parent().hasClass('selected')){
$('.item').removeClass('selected');
$('.item').removeAttr('id');
}
var link=stripPath2($(location).attr('pathname'));
navTo(o,link,$(location).attr('hash'),relpath);
} else if (!animationInProgress) {
$('#doc-content').scrollTop(0);
$('.item').removeClass('selected');
$('.item').removeAttr('id');
navTo(o,toroot,window.location.hash,relpath);
}
})
}
| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/navtree.js | JavaScript | apache-2.0 | 16,662 |
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<div class="textblock"><p>The <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> contains the initial setup of the TrustZone hardware in an Armv8-M system. The function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> is call from <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> and uses the settings in this file to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS). The following initializations are performed:</p>
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<li><a class="el" href="partition_h_pg.html#sau_ctrlregister_sec">SAU CTRL register settings</a> provides settings for the SAU CTRL register.</li>
<li><a class="el" href="partition_h_pg.html#sau_regions_sect">Configuration of the SAU Address Regions</a> provides configuration of the SAU Address Regions.</li>
<li><a class="el" href="partition_h_pg.html#sau_sleepexception_sec">Configuration of Sleep and Exception behaviour</a> provides device-specific deepsleep and exception settings.</li>
<li><a class="el" href="partition_h_pg.html#sau_interrupttarget_sec">Configuration of Interrupt Target settings</a> provides device-specific interrupt target settings.</li>
</ul>
<h1><a class="anchor" id="sau_ctrlregister_sec"></a>
SAU CTRL register settings</h1>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>SAU_INIT_CTRL </td><td>0 .. 1 </td><td>0 </td><td>Initialize SAU CTRL register or not<ul>
<li>0: do not initialize SAU CTRL register</li>
<li>1: initialize SAU CTRL register </li>
</ul>
</td></tr>
<tr>
<td>SAU_INIT_CTRL_ENABLE </td><td>0 .. 1 </td><td>0 </td><td>enable/disable the SAU<ul>
<li>0: disable SAU</li>
<li>1: enable SAU </li>
</ul>
</td></tr>
<tr>
<td>SAU_INIT_CTRL_ALLNS </td><td>0 .. 1 </td><td>0 </td><td>value for SAU_CTRL register bit ALLNS<ul>
<li>0: all Memory is Secure</li>
<li>1: all Memory is Non-Secure </li>
</ul>
</td></tr>
</table>
<h1><a class="anchor" id="sau_regions_sect"></a>
Configuration of the SAU Address Regions</h1>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>SAU_REGIONS_MAX </td><td>0 .. tbd </td><td>8 </td><td>maximum number of SAU regions </td></tr>
<tr>
<td>SAU_INIT_REGION<number> </td><td>0 .. 1 </td><td>0 </td><td>initialize SAU region or not<ul>
<li>0: do not initialize SAU region</li>
<li>1: initialize SAU region </li>
</ul>
</td></tr>
<tr>
<td>SAU_INIT_START<number> </td><td>0x00000000 .. 0xFFFFFFE0<br/>
[in steps of 32] </td><td>0x00000000 </td><td>region start address </td></tr>
<tr>
<td>SAU_INIT_END<number> </td><td>0x00000000 .. 0xFFFFFFE0<br/>
[in steps of 32] </td><td>0x00000000 </td><td>region start address </td></tr>
<tr>
<td>SAU_INIT_NSC<number> </td><td>0 .. 1 </td><td>0 </td><td>SAU region attribute<ul>
<li>0: Non-Secure</li>
<li>1: Secure, Non-Secure callable </li>
</ul>
</td></tr>
</table>
<p>The range of <number> is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each <number>.</p>
<p>The following example shows a set of SAU region macros.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define SAU_REGIONS_MAX 8 </span><span class="comment">/* Max. number of SAU regions */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION0 1</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START0 0x00000000 </span><span class="comment">/* start address of SAU region 0 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END0 0x001FFFE0 </span><span class="comment">/* end address of SAU region 0 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC0 1</span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION1 1</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START1 0x00200000 </span><span class="comment">/* start address of SAU region 1 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END1 0x003FFFE0 </span><span class="comment">/* end address of SAU region 1 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC1 0</span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION2 1</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START2 0x20200000 </span><span class="comment">/* start address of SAU region 2 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END2 0x203FFFE0 </span><span class="comment">/* end address of SAU region 2 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC2 0</span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION3 1</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START3 0x40000000 </span><span class="comment">/* start address of SAU region 3 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END3 0x40040000 </span><span class="comment">/* end address of SAU region 3 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC3 0</span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION4 0</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START4 0x00000000 </span><span class="comment">/* start address of SAU region 4 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END4 0x00000000 </span><span class="comment">/* end address of SAU region 4 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC4 0</span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION5 0</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START5 0x00000000 </span><span class="comment">/* start address of SAU region 5 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END5 0x00000000 </span><span class="comment">/* end address of SAU region 5 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC5 0</span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION6 0</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START6 0x00000000 </span><span class="comment">/* start address of SAU region 6 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END6 0x00000000 </span><span class="comment">/* end address of SAU region 6 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC6 0</span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION7 0</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START7 0x00000000 </span><span class="comment">/* start address of SAU region 7 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END7 0x00000000 </span><span class="comment">/* end address of SAU region 7 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_NSC7 0</span></div>
</div><!-- fragment --><h1><a class="anchor" id="sau_sleepexception_sec"></a>
Configuration of Sleep and Exception behaviour</h1>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>CSR_INIT_DEEPSLEEPS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_CSR register bit DEEPSLEEPS<ul>
<li>0: Deep Sleep can be enabled by Secure and Non-Secure state</li>
<li>1: Deep Sleep can be enabled by Secure state only </li>
</ul>
</td></tr>
<tr>
<td>AIRCR_INIT_SYSRESETREQS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit SYSRESETREQS<ul>
<li>0: System reset request accessible from Secure and Non-Secure state</li>
<li>1: System reset request accessible from Secure state only </li>
</ul>
</td></tr>
<tr>
<td>AIRCR_INIT_PRIS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit PRIS<ul>
<li>0: Priority of Non-Secure exceptions is Not altered</li>
<li>1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF </li>
</ul>
</td></tr>
<tr>
<td>AIRCR_INIT_BFHFNMINS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit BFHFNMINS<ul>
<li>0: BusFault, HardFault, and NMI target are Secure state</li>
<li>1: BusFault, HardFault, and NMI target are Non-Secure state </li>
</ul>
</td></tr>
</table>
<h1><a class="anchor" id="sau_interrupttarget_sec"></a>
Configuration of Interrupt Target settings</h1>
<p>Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to <a class="el" href="using_TrustZone_pg.html#Model_TrustZone">Programmers Model with TrustZone</a> for more information.</p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>NVIC_INIT_ITNS<number> </td><td>0x00000000 .. 0xFFFFFFFF<br/>
[each bit represents an interrupt] </td><td>0x00000000 </td><td>Interrupt vector target<ul>
<li>0: Secure state</li>
<li>1: Non-Secure state </li>
</ul>
</td></tr>
</table>
<p>The range of <number> is 0 .. (<number of external interrupts> + 31) / 32.</p>
<p>The following example shows the configuration for a maximum of 64 external interrupts.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS0 0x0000122B</span></div>
<div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS1 0x0000003A</span></div>
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<div class="textblock"><p>The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.</p>
<table class="cmtable" summary="Register Mapping">
<tr>
<th>CMSIS Register Name </th><th>Cortex-M3, Cortex-M4, and Cortex-M7 </th><th>Cortex-M0 and Cortex-M0+ </th><th>Register Name </th></tr>
<tr>
<th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access </th></tr>
<tr>
<td>NVIC->ISER[] </td><td>NVIC_ISER0..7 </td><td>ISER </td><td>Interrupt Set-Enable Registers </td></tr>
<tr>
<td>NVIC->ICER[] </td><td>NVIC_ICER0..7 </td><td>ICER </td><td>Interrupt Clear-Enable Registers </td></tr>
<tr>
<td>NVIC->ISPR[] </td><td>NVIC_ISPR0..7 </td><td>ISPR </td><td>Interrupt Set-Pending Registers </td></tr>
<tr>
<td>NVIC->ICPR[] </td><td>NVIC_ICPR0..7 </td><td>ICPR </td><td>Interrupt Clear-Pending Registers </td></tr>
<tr>
<td>NVIC->IABR[] </td><td>NVIC_IABR0..7 </td><td>- </td><td>Interrupt Active Bit Register </td></tr>
<tr>
<td>NVIC->IP[] </td><td>NVIC_IPR0..59 </td><td>IPR0..7 </td><td>Interrupt Priority Register </td></tr>
<tr>
<td>NVIC->STIR </td><td>STIR </td><td>- </td><td>Software Triggered Interrupt Register </td></tr>
<tr>
<th colspan="4">System Control Block (SCB) Register Access </th></tr>
<tr>
<td>SCB->CPUID </td><td>CPUID </td><td>CPUID </td><td>CPUID Base Register </td></tr>
<tr>
<td>SCB->ICSR </td><td>ICSR </td><td>ICSR </td><td>Interrupt Control and State Register </td></tr>
<tr>
<td>SCB->VTOR </td><td>VTOR </td><td>- </td><td>Vector Table Offset Register </td></tr>
<tr>
<td>SCB->AIRCR </td><td>AIRCR </td><td>AIRCR </td><td>Application Interrupt and Reset Control Register </td></tr>
<tr>
<td>SCB->SCR </td><td>SCR </td><td>SCR </td><td>System Control Register </td></tr>
<tr>
<td>SCB->CCR </td><td>CCR </td><td>CCR </td><td>Configuration and Control Register </td></tr>
<tr>
<td>SCB->SHP[] </td><td>SHPR1..3 </td><td>SHPR2..3 </td><td>System Handler Priority Registers </td></tr>
<tr>
<td>SCB->SHCSR </td><td>SHCSR </td><td>SHCSR </td><td>System Handler Control and State Register </td></tr>
<tr>
<td>SCB->CFSR </td><td>CFSR </td><td>- </td><td>Configurable Fault Status Registers </td></tr>
<tr>
<td>SCB->HFSR </td><td>HFSR </td><td>- </td><td>HardFault Status Register </td></tr>
<tr>
<td>SCB->DFSR </td><td>DFSR </td><td>- </td><td>Debug Fault Status Register </td></tr>
<tr>
<td>SCB->MMFAR </td><td>MMFAR </td><td>- </td><td>MemManage Fault Address Register </td></tr>
<tr>
<td>SCB->BFAR </td><td>BFAR </td><td>- </td><td>BusFault Address Register </td></tr>
<tr>
<td>SCB->AFSR </td><td>AFSR </td><td>- </td><td>Auxiliary Fault Status Register </td></tr>
<tr>
<td>SCB->PFR[] </td><td>ID_PFR0..1 </td><td>- </td><td>Processor Feature Registers </td></tr>
<tr>
<td>SCB->DFR </td><td>ID_DFR0 </td><td>- </td><td>Debug Feature Register </td></tr>
<tr>
<td>SCB->ADR </td><td>ID_AFR0 </td><td>- </td><td>Auxiliary Feature Register </td></tr>
<tr>
<td>SCB->MMFR[] </td><td>ID_MMFR0..3 </td><td>- </td><td>Memory Model Feature Registers </td></tr>
<tr>
<td>SCB->ISAR[] </td><td>ID_ISAR0..4 </td><td>- </td><td>Instruction Set Attributes Registers </td></tr>
<tr>
<td>SCB->CPACR </td><td>CPACR </td><td>- </td><td>Coprocessor Access Control Register </td></tr>
<tr>
<th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access </th></tr>
<tr>
<td>SCnSCB->ICTR </td><td>ICTR </td><td>- </td><td>Interrupt Controller Type Register </td></tr>
<tr>
<td>SCnSCB->ACTLR </td><td>ACTLR </td><td>- </td><td>Auxiliary Control Register </td></tr>
<tr>
<th colspan="4">System Timer (SysTick) Control and Status Register Access </th></tr>
<tr>
<td>SysTick->CTRL </td><td>STCSR </td><td>SYST_CSR </td><td>SysTick Control and Status Register </td></tr>
<tr>
<td>SysTick->LOAD </td><td>STRVR </td><td>SYST_RVR </td><td>SysTick Reload Value Register </td></tr>
<tr>
<td>SysTick->VAL </td><td>STCVR </td><td>SYST_CVR </td><td>SysTick Current Value Register </td></tr>
<tr>
<td>SysTick->CALIB </td><td>STCR </td><td>SYST_CALIB </td><td>SysTick Calibaration Value Register </td></tr>
<tr>
<th colspan="4">Data Watchpoint and Trace (DWT) Register Access </th></tr>
<tr>
<td>DWT->CTRL </td><td>DWT_CTRL </td><td>- </td><td>Control Register </td></tr>
<tr>
<td>DWT->CYCCNT </td><td>DWT_CYCCNT </td><td>- </td><td>Cycle Count Register </td></tr>
<tr>
<td>DWT->CPICNT </td><td>DWT_CPICNT </td><td>- </td><td>CPI Count Register </td></tr>
<tr>
<td>DWT->EXCCNT </td><td>DWT_EXCCNT </td><td>- </td><td>Exception Overhead Count Register </td></tr>
<tr>
<td>DWT->SLEEPCNT </td><td>DWT_SLEEPCNT </td><td>- </td><td>Sleep Count Register </td></tr>
<tr>
<td>DWT->LSUCNT </td><td>DWT_LSUCNT </td><td>- </td><td>LSU Count Register </td></tr>
<tr>
<td>DWT->FOLDCNT </td><td>DWT_FOLDCNT </td><td>- </td><td>Folded-instruction Count Register </td></tr>
<tr>
<td>DWT->PCSR </td><td>DWT_PCSR </td><td>- </td><td>Program Counter Sample Register </td></tr>
<tr>
<td>DWT->COMP0..3 </td><td>DWT_COMP0..3 </td><td>- </td><td>Comparator Register 0..3 </td></tr>
<tr>
<td>DWT->MASK0..3 </td><td>DWT_MASK0..3 </td><td>- </td><td>Mask Register 0..3 </td></tr>
<tr>
<td>DWT->FUNCTION0..3 </td><td>DWT_FUNCTION0..3 </td><td>- </td><td>Function Register 0..3 </td></tr>
<tr>
<th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access </th></tr>
<tr>
<td>ITM->PORT[] </td><td>ITM_STIM0..31 </td><td>- </td><td>Stimulus Port Registers </td></tr>
<tr>
<td>ITM->TER </td><td>ITM_TER </td><td>- </td><td>Trace Enable Register </td></tr>
<tr>
<td>ITM->TPR </td><td>ITM_TPR </td><td>- </td><td>ITM Trace Privilege Register </td></tr>
<tr>
<td>ITM->TCR </td><td>ITM_TCR </td><td>- </td><td>Trace Control Register </td></tr>
<tr>
<th colspan="4">Trace Port Interface (TPIU) Register Access </th></tr>
<tr>
<td>TPI->SSPSR </td><td>TPIU_SSPR </td><td>- </td><td>Supported Parallel Port Size Register </td></tr>
<tr>
<td>TPI->CSPSR </td><td>TPIU_CSPSR </td><td>- </td><td>Current Parallel Port Size Register </td></tr>
<tr>
<td>TPI->ACPR </td><td>TPIU_ACPR </td><td>- </td><td>Asynchronous Clock Prescaler Register </td></tr>
<tr>
<td>TPI->SPPR </td><td>TPIU_SPPR </td><td>- </td><td>Selected Pin Protocol Register </td></tr>
<tr>
<td>TPI->FFSR </td><td>TPIU_FFSR </td><td>- </td><td>Formatter and Flush Status Register </td></tr>
<tr>
<td>TPI->FFCR </td><td>TPIU_FFCR </td><td>- </td><td>Formatter and Flush Control Register </td></tr>
<tr>
<td>TPI->FSCR </td><td>TPIU_FSCR </td><td>- </td><td>Formatter Synchronization Counter Register </td></tr>
<tr>
<td>TPI->TRIGGER </td><td>TRIGGER </td><td>- </td><td>TRIGGER </td></tr>
<tr>
<td>TPI->FIFO0 </td><td>FIFO data 0 </td><td>- </td><td>Integration ETM Data </td></tr>
<tr>
<td>TPI->ITATBCTR2 </td><td>ITATBCTR2 </td><td>- </td><td>ITATBCTR2 </td></tr>
<tr>
<td>TPI->ITATBCTR0 </td><td>ITATBCTR0 </td><td>- </td><td>ITATBCTR0 </td></tr>
<tr>
<td>TPI->FIFO1 </td><td>FIFO data 1 </td><td>- </td><td>Integration ITM Data </td></tr>
<tr>
<td>TPI->ITCTRL </td><td>TPIU_ITCTRL </td><td>- </td><td>Integration Mode Control </td></tr>
<tr>
<td>TPI->CLAIMSET </td><td>CLAIMSET </td><td>- </td><td>Claim tag set </td></tr>
<tr>
<td>TPI->CLAIMCLR </td><td>CLAIMCLR </td><td>- </td><td>Claim tag clear </td></tr>
<tr>
<td>TPI->DEVID </td><td>TPIU_DEVID </td><td>- </td><td>TPIU_DEVID </td></tr>
<tr>
<td>TPI->DEVTYPE </td><td>TPIU_DEVTYPE </td><td>- </td><td>TPIU_DEVTYPE </td></tr>
<tr>
<th colspan="4">Memory Protection Unit (MPU) Register Access </th></tr>
<tr>
<td>MPU->TYPE </td><td>MPU_TYPE </td><td>- </td><td>MPU Type Register </td></tr>
<tr>
<td>MPU->CTRL </td><td>MPU_CTRL </td><td>- </td><td>MPU Control Register </td></tr>
<tr>
<td>MPU->RNR </td><td>MPU_RNR </td><td>- </td><td>MPU Region Number Register </td></tr>
<tr>
<td>MPU->RBAR </td><td>MPU_RBAR </td><td>- </td><td>MPU Region Base Address Register </td></tr>
<tr>
<td>MPU->RASR </td><td>MPU_RASR </td><td>- </td><td>MPU Region Attribute and Size Register </td></tr>
<tr>
<td>MPU->RBAR_A1..3 </td><td>MPU_RBAR_A1..3 </td><td>- </td><td>MPU alias Register </td></tr>
<tr>
<td>MPU->RSAR_A1..3 </td><td>MPU_RSAR_A1..3 </td><td>- </td><td>MPU alias Register </td></tr>
<tr>
<th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU] </th></tr>
<tr>
<td>FPU->FPCCR </td><td>FPCCR </td><td>- </td><td>FP Context Control Register </td></tr>
<tr>
<td>FPU->FPCAR </td><td>FPCAR </td><td>- </td><td>FP Context Address Register </td></tr>
<tr>
<td>FPU->FPDSCR </td><td>FPDSCR </td><td>- </td><td>FP Default Status Control Register </td></tr>
<tr>
<td>FPU->MVFR0..1 </td><td>MVFR0..1 </td><td>- </td><td>Media and VFP Feature Registers </td></tr>
</table>
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/search/classes_7.html | HTML | apache-2.0 | 1,015 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/search/classes_8.html | HTML | apache-2.0 | 1,015 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/search/classes_9.html | HTML | apache-2.0 | 1,015 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/search/enums_0.html | HTML | apache-2.0 | 1,013 |
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| YifuLiu/AliOS-Things | components/cmsis/docs/Core/html/search/enumvalues_0.html | HTML | apache-2.0 | 1,018 |